University of Southern California Dissertations and Theses

RF and mm-wave blocker-tolerant reconfigurable receiver front-ends

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RF and mm-wave blocker-tolerant reconfigurable receiver front-ends

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Content RF and mm-Wave Blocker-Tolerant Recongurable Receiver Front-Ends by Pingyue Song A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulllment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (Electrical Engineering) December 2020 Copyright 2020 Pingyue Song Dedication To my wife Yating, and our parents. ii Acknowledgements A single man can work as hard as he would like, but will achieve little without help and support from the people around. I always say that if I were to be able to graduate as a Doctor one day, I would have to owe the most credit to my wife and my soul mate, Yating Zhu. Over these many years in US, Yating has been always on my side. She could be my biggest admirer when I only got a slight research advancement, and she could me my exclusive cheer leader to cheer me up when I feel down and blue. I am the luckiest man in the world to meet you half-way across the globe here at USC, and marry you as my wife. I Love you Yating, and this work is dedicated to you! Research can be very unpredictable, and you would never know how, or whether the results can come through. However, I must say I do deeply regret and even feel guilty that I cannot nish this chapter of my life sooner, so I can tend to my dear parents, my mum Guiping Ma and my dad Lianjun Song. One could not ask for better parents. They nurture me, but more importantly they guide me to be a really man, and to be kind and genuine to people, and be passionate and serious for career and professions. Hopefully this work can make you feel proud of your iii son, and if so, that should make all these years' sleepless nights worthy. Love you mum and dad! Same love and gratefulness also go to my parents-in-law, Wenhua Huang and Li Zhu, for their invaluable patience and support over the years. I would like to thank my PhD advisor, Prof. Hossein Hashemi. As unbelievable as it might sound like, I knew almost nothing about circuit design when I met Prof. Hashemi years ago, and yet he still took me under the wings and admitted me to his fantastic research group. He was really brave, and I would be forever grateful. At work, his focus on details and tireless commitment in pursuit for perfection is what I admire the most. Needless to say, Prof. Hashemi is and will remain my greatest professional in uence. I am very grateful for the advice of my qualifying examination and defense com- mittee members: Prof. Mike Shuo-Wei Chen, Prof. Aluizio Prata, Prof. Jayakanth Ravichandran, Prof. Constantine Sideris, and Prof. Eun Sok Kim. I would espe- cially like to thank Prof. Prata for his mentoring throughout the course of my PhD. He always believe in me right from the beginning of my USC career, and he shows me it is really possible make your hobby your job and enjoy every moment of life. I would like to give special shout outs to the forever helpful and caring EE stas, Diane Demetras, Kim Reid, Jenny Lin, Elizabeth Castaneda, and Sunny Bhalla. You guys are the best! Last but certainly not the least, my lab mates. Over my long USC years, I have this privilege to meet this group of beautiful souls, and they are the very reason iv why I could endure those unspeakable dark times and eventually came out as a survivor. Samer Idres, Dr. Sushil Subramanian, Aria Samiei, Masashi Yamagata, Dr. Sungwon Chung, Vinay Chenna, Vishal Choudhari, Dr. Run Chen, Dr. Kunal Datta, Dr. Alireza Imani, Chenliang Du, Dr. Fatemeh Rezaeifar, Dr. Zahra Safarian, Makoto Nakai, Dr. Keisuke Kondo, Dr. Hooman Abediasl, Dr. Ankush Goel, Dr. Hongrui Wang, and Dr. Marcelo Segura, and also friends from Prof. Mike Chen's group, Shiyu Su, Aoyang Zhang, Cheng-Ru Ho, Qiaochu Zhang, Juzheng Lv, Jaewon Nam, Tzu-Fan Wu, Mohsen Hassanpourghadi, and Mostafa Abouelkassem: I will forever treasure the invaluable guidance and vision placed upon me, and the memorable tears and laughters, banters and swearing we shared. It is you guys that made my USC experience unique. v Table of Contents Dedication ii Acknowledgements iii List Of Figures viii Abstract xvii Chapter 1: Introduction 1 1.1 Blocker Tolerance in Wireless Receivers . . . . . . . . . . . . . . . . 1 1.2 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 2: Architectural and Circuit Tradeos for RF and mm-wave beamforming and MIMO receiving arrays 8 2.1 Performance trade-o for mm-wave Receiver Building Blocks . . . . 9 2.1.1 Passive Circuit Building Blocks . . . . . . . . . . . . . . . . 9 2.1.2 Active Circuit Building Blocks . . . . . . . . . . . . . . . . . 21 2.2 Power Consumption Analysis for mm-wave Receivers Array Archi- tectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 Conclusions and Recommendations for Future Work . . . . . . . . . 69 Chapter 3: RF Filter Synthesis based on Passively-Coupled N-Path Resonators 71 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.2 synthesizing lters with transmission zeros based on passively-coupled LC resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.3 synthesizing lters with transmission zeros based on passively-coupled N-Path resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.4 CMOS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.4.1 Insertion Loss and Noise Performance . . . . . . . . . . . . . 97 3.4.2 Large-Signal Performance . . . . . . . . . . . . . . . . . . . 99 3.5 Measurement Result and Comparison . . . . . . . . . . . . . . . . . 101 3.5.1 S-Parameters (S 21 ; S 11 , and S 22 ) . . . . . . . . . . . . . . . . 102 vi 3.5.2 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.5.3 ICP 1dB ; B 1dB ; IIP2, and IIP3 . . . . . . . . . . . . . . . . 105 3.5.4 Performance Comparison . . . . . . . . . . . . . . . . . . . . 108 3.6 Conclusion and Recommendations for Future Work . . . . . . . . . 109 Chapter 4: mm-Wave Mixer-First Receiver with Selective Passive Wideband Low-Pass Filtering 112 4.1 Introduction: Passive-mixer-rst receivers in mm-Wave frequency . 112 4.2 mm-Wave switched-complex-impedance based mixer-rst receiver . 115 4.3 mm-Wave Mixer-First Receiver System Level Design and Trade-Os 124 4.4 CMOS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.5 Measurement Result and Comparison . . . . . . . . . . . . . . . . . 142 4.6 Conclusion and Recommendations for Future Work . . . . . . . . . 150 Chapter 5: Wideband mm-Wave Phase Shifters Based on Constant- Impedance Tunable Transmission Lines 152 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.2 Constant-Impedance Tunable T-Lines . . . . . . . . . . . . . . . . . 157 5.3 Implementation and Measurement Results . . . . . . . . . . . . . . 165 5.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Chapter 6: Conclusion and Recommendations for Future Work 172 6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . 174 Reference List 176 Appendix A Interconnect Parasitic De-Embedding . . . . . . . . . . . . . . . . . . . . 190 Appendix B Eect of Buering Inductor on N-Path Filters . . . . . . . . . . . . . . . 195 vii List Of Figures 1.1 Array of bulk-acoustic (BAW) lters in a multi-band receiver. . . . 2 1.2 Basic receivers with blockers. . . . . . . . . . . . . . . . . . . . . . 3 1.3 Blocker-tolerance recongurable receivers. . . . . . . . . . . . . . . 5 2.1 Performance summary of representative reported 20 - 94 GHz mm- wave passive BPFs versus the fractional bandwidth. . . . . . . . . . 13 2.2 Representative schematic of various phase-shifter design. . . . . . . 15 2.3 Insertion loss of a passive re ection-type phase-shifter with varactors of dierent quality factor. . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Performance summary of representative reported mm-wave passive phase shifter designs. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 Performance characterization of quadrature passive mixers on out- of-band IIP3, minimal achievable NF, and power consumption for (a)-(c) dierent relative switch resistance , and (d)-(f) dierent switching frequency f LO . All results are generated based on Eqn. 2.12 to Eqn. 2.14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6 Performance summary of representative reported 20 - 80 GHz mm- wave silicon CS LNAs versus extrapolated FOM LNA lines. . . . . . . 24 2.7 Circuit schematic of a representative double-balanced Gilbert-cell active mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 Performance summary of representative reported 10 - 70 GHz mm- wave Gilbert-cell active mixers versus extrapolated FOM Mixer lines. 26 viii 2.9 Performance summary of representative reported 10 - 100 GHz mm- wave RF active VMs versus extrapolated FOM RFActiveVM lines. . 28 2.10 Performance summary of representative reported active LPF+VGA designs versus extrapolated FOM LPF+VGA lines. . . . . . . . . . . . 30 2.11 Summary of power performance characterization of various receiver building blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.12 Analog phased-array systems (a) with RF-path phase-shifting (RF Array), (b) with RF-path phase-shifting and late-LNA (RF Array, Late-LNA), and (c) with RF-path VM-based phase-shifting (RF Ar- ray, VM). Phase shifters in scheme (a) and (b) are all passive. . . . 34 2.13 Analog phased-array systems (a) with baseband phase-shifting (BB Array), (b) with mixer-rst baseband phase-shifting (BB Array, Mixer- First), (c) with LO-path phase-shifting (LO Array), and (d) with mixer-rst LO-path phase-shifting (LO Array, Mixer-First). . . . . . 35 2.14 Blocking test prole for mm-wave receivers. . . . . . . . . . . . . . 37 2.15 Representative signal levels at the input of each RF Array stage. . . 38 2.16 Representative signal levels at the input of each LO Array stage. . . 39 2.17 Representative signal levels at the input of each BB Array stage. . . 40 2.18 Power consumption of RF-, BB-, and LO-arrays with dierent out- of-band blocker levels. . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.19 Power consumption of RF-, BB-, and LO-arrays with dierent in- band blocker-1 (IB-BLK1) levels. . . . . . . . . . . . . . . . . . . . 43 2.20 Power consumption of RF-, BB-, and LO-arrays with dierent signal channel bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.21 Power consumption of RF-, BB-, and LO-arrays with dierent num- ber of receiving antenna. . . . . . . . . . . . . . . . . . . . . . . . . 44 ix 2.22 Hybrid array systems (a) with RF-path phase-shifting (RF Hybrid), (b) with RF-path phase-shifting and late-LNA (RF Hybrid, Late- LNA), and (c) with RF-path VM-based phase-shifting (RF Hybrid, VM). Phase shifters in scheme (a) and (b) are all passive. . . . . . . 48 2.23 Hybrid array systems (a) with baseband phase-shifting (BB Hybrid), and (b) with mixer-rst baseband phase-shifting (BB Hybrid, Mixer- First). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.24 Hybrid array systems (a) with LO-path phase-shifting (LO Hybrid), and (b) with mixer-rst LO-path phase-shifting (LO Hybrid, Mixer- First). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.25 Power consumption of RF, BB, and LO hybrids with dierent out- of-band blocker levels. . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.26 Power consumption of RF, BB, and LO hybrids with dierent in- band blocker-1 (IB-BLK1) levels. . . . . . . . . . . . . . . . . . . . 52 2.27 Power consumption of RF, BB, and LO hybrids with dierent signal channel bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.28 Power consumption of RF, BB, and LO hybrids with dierent num- ber of receiving antenna. . . . . . . . . . . . . . . . . . . . . . . . . 53 2.29 Power consumption of RF, BB, and LO hybrids with 32 antennas and dierent number of supported user streams. . . . . . . . . . . . 54 2.30 Power consumption of RF, BB, and LO hybrids with 4096 antennas and dierent number of supported user streams. . . . . . . . . . . . 54 2.31 Digital array systems (a) with LNAs (Digital Array), and (b) without LNAs (Digital Array, Mixer-First). . . . . . . . . . . . . . . . . . . 56 2.32 Representative signal levels at the input of each Digital Array stage. 57 2.33 Power consumption of digital arrays with dierent out-of-band blocker levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.34 Power consumption of digital arrays with dierent in-band blocker-1 (IB-BLK1) levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 x 2.35 Power consumption of digital arrays with dierent signal channel bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.36 Power consumption of digital arrays with dierent number of receiv- ing antenna. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.37 Power consumption of digital arrays with 32 antennas and dierent number of supported user streams. . . . . . . . . . . . . . . . . . . 60 2.38 Power consumption of digital arrays with 4096 antennas and dierent number of supported user streams. . . . . . . . . . . . . . . . . . . 60 2.39 Power consumption of arrays with dierent out-of-band blocker levels. 62 2.40 Power consumption of arrays with dierent in-band blocker-1 (IB- BLK1) levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.41 Power consumption of arrays with dierent signal channel bandwidth. 64 2.42 Power consumption of arrays with dierent number of receiving an- tenna. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.43 Power consumption of arrays with 32 antennas and dierent number of supported user streams. . . . . . . . . . . . . . . . . . . . . . . . 66 2.44 Power consumption of arrays with 4096 antennas and dierent num- ber of supported user streams. . . . . . . . . . . . . . . . . . . . . . 67 2.45 Power consumption of arrays with (a) 32 elements and (b) 4096 el- ements, of which digital processors are implemented by digital tech- nologies with dierent normalized power eciency. . . . . . . . . . . 68 3.1 Frequency responses of an ideal all-pole lter, and all-pole lters with nite-Q components and increasing lter order N. . . . . . . . . . . 72 3.2 Frequency response of an all-pole BPF, and a same order BPF with transmission zeros. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.3 Simulated input impedance of an N-Path resonator and its LC equiv- alence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.4 BPF synthesis with N-Path resonators, capacitors and inductors. . . 77 xi 3.5 Reactance frequency response of (a) N-branch, (b) C-branch, and (C) L-branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.6 (a) Capacitor-coupled high-Q LC resonator as a BPF, (b) Low-Q- inductor-coupled high-Q LC resonator as a BPF, (c) Serial-inductor- and-capacitor-coupled high-Q LC resonator as a BPF, (d) Simulated frequency responses from BPFs shown in (a){(c), with same trans- mission zeros locations, and (e) serial-coupling inductor for various transmission zero locations, as required in (b) and (c). . . . . . . . 79 3.7 Representative synthesized BPFs and corresponding simulated fre- quency responses (loss-less components) with (a) 3-coupled LC res- onators, (b) 4-coupled LC resonators, and (c) 5-coupled LC resonators. 81 3.8 Representative optimized 3-resonator-coupled LC lter components values for various BW and OOB rejection lter requirements. . . . . 82 3.9 Simulated frequency response comparison between a coupled LC res- onator and a directly-transformed N-Path resonator based lter. . . 83 3.10 Simulated frequency response comparison between a coupled LC res- onator and the directly-transformed N-Path resonator based lters, with additional buering inductors. . . . . . . . . . . . . . . . . . . 85 3.11 Eects of nite-Q inductors on simulated lter frequency response. . 86 3.12 Eect of nite switch resistance R SW on simulated input impedance frequency response of a single N-Path resonator. . . . . . . . . . . . 87 3.13 Eect of parasitic capacitance C PAR on simulated input impedance frequency response of a single N-Path resonator. . . . . . . . . . . . 88 3.14 Eective in-band quality factor and out-of-band to in-band rejection for an N-Path resonator as a function of 65nm NMOS switch size for dierent switched capacitor C values. All NMOS transistors have minimum length, and both port impedance equal to 50 . . . . . . . 90 3.15 Simulated frequency response of proposed coupled N-Path-resonator based lters, with dierent equivalent switch sizes. . . . . . . . . . . 91 xii 3.16 Comparing on-chip LC resonator versus on-chip N-Path resonator approaches towards constructing integrated recongurable RF BPFs. Schematic and simulation results for (a) LC prototype featuring in- ductors with Q = 10, with and without Q-boost (ideal bias tees not shown), and (b) N-Path prototype featuring inductors with Q = 10, 65nm CMOS transistors as switches, with and without Q-boost. . . 92 3.17 Simulated linearity performance of a single N-Path-resonator-based lter, with and without cross-coupled pairs as negative resistance. . 94 3.18 Schematic of the dierential N-path-based recongurable BPF pro- totype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.19 Clock generation for N-Path resonators. . . . . . . . . . . . . . . . . 97 3.20 Simplied model for insertion loss and noise analysis around lter center frequency ! LO . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.21 Simplied equivalent lter schematic at lter center frequency ! LO , and the lower-frequency transmission zero ! TZ . . . . . . . . . . . . 100 3.22 Chip micro-photograph of the lter prototype. . . . . . . . . . . . . 101 3.23 Representative measured lter response with a 40 MHz bandwidth centered on f LO = 875 MHz. . . . . . . . . . . . . . . . . . . . . . . 102 3.24 Representative measured lter shapes with bandwidth of 30, 40, and 50 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.25 Representative measured small signal S-parameters and group de- lay of lters with similar frequency response centered on dierent frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.26 Representative measured NF of lters with similar frequency re- sponse centered on dierent frequencies. Filter congurations are the same as indicated in Fig. 3.25. . . . . . . . . . . . . . . . . . . 106 3.27 Measured blocker NF (blocker frequency oset f = 30 MHz) for a lter response with a 40 MHz bandwidth centered on f LO = 875 MHz.106 xiii 3.28 (a) ICP 1dB and IIP3 measurements for a lter response with a 40 MHz bandwidth centered on f LO = 875 MHz, (b) B 1dB and IIP3 measurements for a lter response with a 40 MHz bandwidth cen- tered onf LO = 875 MHz, with dierent frequency oset f, and (c) IIP2 measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.1 Eective quality factor of an N-Path resonator at dierent frequen- cies for dierent equivalent switch sizes. . . . . . . . . . . . . . . . . 113 4.2 Regular paasive mixer-rst receiver front-end. . . . . . . . . . . . . 114 4.3 Base-band poly-phase network schematic and voltage gain transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.4 Analytical model for poly-phase mixer scheme. . . . . . . . . . . . . 117 4.5 Representative analytical and simulated in-band input impedance of a poly-phase mixer for dierent R L . . . . . . . . . . . . . . . . . . . 118 4.6 Representative analytical and simulated in-band voltage gain of a poly-phase mixer for dierent R L . . . . . . . . . . . . . . . . . . . . 120 4.7 Representative analytical and simulated in-band NF of a poly-phase mixer for dierent R L . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.8 Simulated comparison between characteristic performance of poly- phase and regular mixer. . . . . . . . . . . . . . . . . . . . . . . . . 123 4.9 Poly-phase mixer with dierential input switching scheme, where cascaded RC stages are added to generate double-sided transmission zeros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.10 Poly-phase mixer with input matching network and double-sided transmission zeros centered at dierent frequencies. . . . . . . . . . 126 4.11 Schematic and frequency response of a passive 3 rd -order elliptic LPF with dierent inductor quality factor Q L . . . . . . . . . . . . . . . . 127 4.12 Schematic and RF-to-BB frequency response of the proposed mixer- rst receiver with a 3 rd -order elliptic low-pass lter with ideal switches and dierent values for inductor Q L . . . . . . . . . . . . . . . . . . 130 xiv 4.13 1 and 2 of a representative quadrature sinusoid LO waveforms. . . 131 4.14 (a) Representative schematic of a RC-loaded quadrature mixer with sinusoidally-switched CMOS transistors and input matching net- work, and (b) LTI model equivalent to (a). . . . . . . . . . . . . . . 132 4.15 Simulated and analytical performance of the quadrature passive mixer in Fig. 4.14: (a) mixer input impedanceZ mixer , (b) conversion gain, (c) NF, (d) out-of-band IIP3, and (e) estimated LO circuitory power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.16 Simulated and analytical performance of the sinusoidally-driven quadra- ture passive mixer in Fig. 4.14 at dierent LO frequency for NMOS width = 30m andR L = 80 : (a) conversion gain, (c) NF, (d) out- of-band IIP3, and (d) estimated LO circuitory power consumption. 138 4.17 Schematic of the implemented mm-wave receiver. . . . . . . . . . . 140 4.18 Mixer-driver schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.19 Layout and lumped equivalent model of the implemented elliptic low-pass lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.20 (a) Baseband amplier Schematic, and (b) simulated low-pass fre- quency response of the elliptic LPF and the baseband amplier. . . 143 4.21 Photos of (a) the silicon chip, and (b) test PCB. . . . . . . . . . . 144 4.22 Representative measured and simulated receiver (a) RF-to-BB fre- quency response, and (b) double-side band (DSB) NF at f LO =27 GHz with baseband amplier turned ON. . . . . . . . . . . . . . . . 145 4.23 Representative measured receiver RF-to-BB frequency response and DSB NF with (a) baseband amplier turned ON, and (b) baseband amplier turned OFF. . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.24 ICP 1dB and B 1dB measurements for a RX response centered on f LO =29.0 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.1 Various phase shifter architectures. . . . . . . . . . . . . . . . . . . 153 5.2 Hybrid MIMO architecture suitable for large-scale mm-wave arrays. 154 xv 5.3 3D view of a conventional tunable t-line featuring signal owing in top metal layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.4 Cross section of a conventional tunable t-line featuring signal owing in top metal layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.5 Conventional and inverted t-line in a typical metal layers cross- section of a modern commercial CMOS technology. . . . . . . . . . 161 5.6 Proposed inverted t-line featuring signal owing in a lower metal layer.162 5.7 Cross section of the proposed inverted t-line featuring signal owing in a lower metal layer. . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.8 Chip microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.9 Measured characteristic impedance. . . . . . . . . . . . . . . . . . . 166 5.10 Measured attenuation coecient . . . . . . . . . . . . . . . . . . . 166 5.11 Measured wavenumber . . . . . . . . . . . . . . . . . . . . . . . . 167 5.12 Measured equivalent group delay. . . . . . . . . . . . . . . . . . . . 167 5.13 Measured equivalent transmission line inductance and capacitance. . 168 5.14 Measured large signal performance at 45 GHz. . . . . . . . . . . . . 168 5.15 Performance comparison of passive mm-wave phase shifters. . . . . 170 A.1 A two-port IO network. . . . . . . . . . . . . . . . . . . . . . . . . . 190 A.2 A IO complete network. . . . . . . . . . . . . . . . . . . . . . . . . 191 A.3 IO network Back-to-Back. . . . . . . . . . . . . . . . . . . . . . . . 191 A.4 IO network Reversed. . . . . . . . . . . . . . . . . . . . . . . . . . . 191 A.5 IO network ZL Load. . . . . . . . . . . . . . . . . . . . . . . . . . . 193 B.1 Eect of buering inductor L Buer on coupled-N-Path-resonator based lters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 xvi Abstract A selective receiver front-end whose frequency response can be tuned is highly de- sirable to substantially attenuate the interference before it reaches more vulnerable circuit blocks. However, compact, low-loss, linear, selective, and recongurable de- signs have been dicult to implement specically in a CMOS platform, where the passive components have low-quality factors. This thesis presents innovative inte- grated solutions, from both system level and circuit level, to the implementation of such recongurable interference-tolerant receivers at RF and mm-wave frequencies. Given characteristic of the available receiver building blocks, receivers and receiver-array architectures can be compared to each other with their major per- formance parameters optimized under the same system-level requirement. The ultimate architecture with optimal resource eciency depends on signal and in- terference conditions, communication applications, the system scale as well as IC technology parameters, and a detailed analysis is presented in this thesis. At RF frequencies, it is shown that N-path resonators, emulating a second-order resonator close to the clock frequency, can be coupled using passive components to xvii synthesize tunable selective RF lter transfer functions. A general lter synthesizing methodology as well as CMOS design trade-os are discussed. At millimeter-wave frequencies when the N-path resonators' quality factor is lim- ited by CMOS switch quality, a receiver front-end with selective transfer functions across a wide frequency range can be implemented based on mixer-rst schemes. Higher-order passive low-pass lter networks can be placed at the mixer output to signicantly enhance the attenuation to the out-of-band inference, with an accept- able design-area-associated cost at mm-wave frequencies. Finally, compact RF phase shifters with high linearity and wide bandwidth are highly desired, and inverted tunable transmission-lines can be implemented as wideband phase shifters for large-scale mm-wave monolithic beam-forming schemes. xviii Chapter 1 Introduction 1.1 Blocker Tolerance in Wireless Receivers Modern wireless receivers are required to exhibit unprecedented exibility by being able to cover several standards with a wide frequency range. Along with the desired signals, unwanted content can be introduced to the receivers input as well, and the sources of this interferences can be other radios with similar applications co- existing in the same neighborhood, or intentional jammers to purposely detriment the proper operation of other users' radios. For the purpose of this thesis, any channel or band of signals that is undesired by a communication system by protocol is considered interference, or a blocker. In most applications, the unwanted blockers are apart from the desired signal in frequency domain, and when they are both captured by the receiver antennas, analog lter are typically placed immediately afterward to attenuate the blockers' level while not disturbing the desired signal. These lters are required to have 1 Figure 1.1: Array of bulk-acoustic (BAW) lters in a multi-band receiver. low insertion loss and process high-order ltering transfer functions to eciently condition close-by blockers. In general, the in-band insertion loss of a bandpass lter (BPF) with components of homogenous quality factor Q is approximately given by [1] Insertion Loss(dB) 8:68 K N Q ! 0 ! 3dB ; (1.1) where N is the lter order, Q is components quality factors, ! 0 and ! 3dB are the center frequency and 3 dB-bandwidth of the lter, and K is a constant that depends on the lter type (e.g., Butterworth, Chebychev). In an all-pole lter, higher selectivity (higher transition-band roll-o) can be obtained with higher lter order (larger N) at the expense of an increased in-band insertion loss (Fig. 3.1). This fundamental trade-o makes it necessary to use technologies that oer high-Q passive components. 2 Figure 1.2: Basic receivers with blockers. In conventional radiofrequency receivers, these front-end analog lters are im- plemented as discrete modules using surface-acoustic or bulk-acoustic technologies to facilitate resonators with quality factors over a thousand (Fig. 1.1). However, acoustic lters are not tunable, and they are designed to have xed center frequen- cies and transfer functions. Therefore, multiple acoustic lters with each designed for a specic frequency band, are needed for a multi-band modern receiver caus- ing a foot-print and cost overhead. Apart from the issue of scaling up with the number of bands of interest, the frequency scaling-up also hinders the broad use of such acoustic lters in recongurable receivers operating in mm-Wave frequencies, where high-Q acoustic resonators cannot be realized. 3 Undesirable as they are, removing or replacing these superior acoustic lters while being able to cover a wide frequency range are non-trivial. Removing front- end lters completely will force the rest of the receiver to operate with a wide instan- taneous bandwidth and a high input dynamic range. A representative receiver of such conguration, with only a down-conversion mixer as front-end, would require a high-speed high-dynamic range analog-to-digital converter (ADC) as baseband processor, and its power consumption as revealed in Fig. 1.2(a) can be overwhelm- ingly high. On the other hand, directly replacing the high-Q acoustic lters with on-chip integrated tunable lters can reduce the blocker level and thus ease the burden of the rest of the receiver from a linearity point of view. Unfortunately, electromagnetic resonators realized using integrated inductors or transmission lines structures often have orders-of-magnitude lower quality factor than the acoustic counterparts, and the supplementation of tunable element such as CMOS transis- tors and varactors would further degrade the Q to around 10. As shown in Fig. 1.2(b), the excessive noise as a by-product of such lters with low-Q resonators is not workable for any receiver design. A core program of this thesis is the proposal of novel CMOS-friendly architec- tures and building blocks for receiver front-ends, that provide tunable frequency- domain selectivity with high-dynamic range. More specically, as shown in Fig.1.3, at radiofrequency, recongurable bandpass lters with highly-selective transfer func- tions can be used as front-end lters. While at much higher frequencies such as 4 Figure 1.3: Blocker-tolerance recongurable receivers. mm-Wave frequencies when such techniques might not be optimal, receiver archi- tectures with recongurablility, high selectivity and dynamic range are proposed featuring novel designs of lters together with down-conversion mixers. 1.2 Dissertation Outline The dissertation examines design of blocker-tolerant receivers and the building blocks in three applications, and discuss how optimal receiver design can be achieved involving the new building blocks and concepts. Chapter 2 of this dissertation comprehensively compare a variety of dierent receiver architectures in respect of their power consumption under the same re- ceiving blocking prole. Conventional and proposed receivers building blocks are rstly introduced, and their individual power consumption are summarized as a function of critical receiver design parameters such as bandwidth, noise, linearity, gain, etc. Next, these building blocks are interconnected to form various receiver architectures, and total power consumption of each architecture is minimized and 5 compared to each other when used to receive the same desired signal in presence of several xed nearby blockers in frequency domain. Specically, in mm-Wave frequency, this comparison is conducted in the context of receiver array to align with the realistic application of mm-Wave radios. Motivated by Chapter 2 of the necessity of a recongurable RF BPF, Chapter 3 discusses a synthesizing methodology of RF BPFs that uses multiple passively- coupled N-Path resonators to realize a more selective transfer function with trans- mission zeros. It is further shown that the low quality factor of coupling passives (e.g., low-Q inductors) does not signicantly deteriorate the lter characteristics. The transfer function of these BPFs is tunable by a combination of clock frequency and capacitor values. The increase of insertion loss due to CMOS switch parasitics may be mitigated by introducing negative resistances at the expense of increased power consumption and noise. This work is another step towards possible replace- ment or augmentation of acoustic lters in recongurable RF transceivers. Design details and measurement results of a proof-of-concept lter prototype with a 0.8 to 1.1 GHz tunable bandpass frequency realized in a 65nm CMOS technology are presented. Chapter 4 shifts the research application to digital array system at mm-Wave frequencies. It is shown that high-order passive lters, instead of passive or active RC lters, may be used as the load of passive mixers in mm-Wave digital arrays enabling more selective transfer functions across a wide frequency range without 6 compromising linearity. A proof-of-concept 65nm CMOS prototype, covering 21 GHz to 29 GHz frequency range, using a 3rd-order elliptic passive lter as the load of passive mixer, is designed, fabricated, and measured. This design approach may be suitable for fully digital mm-wave arrays. Chapter 5 discusses design of a major building block of blocker-tolerance ana- log RF phased-array system : phase shifters. It introduces an integrated inverted stripline-like tunable transmission line structure where the propagation velocity can be modied as the characteristic impedance remains constant. Such constant- impedance tunable t-lines technique enables realization of wide-band phase shifters for large-scale mm-wave monolithic beam-forming schemes. Available metal lay- ers of commercial silicon processes along with high-ft FET switches can be used judiciously to change the eective capacitance and inductance of on-chip t-lines to vary the propagation velocity without aecting the characteristic impedance. Proof-of-concept prototypes realized in a commercial CMOS SOI process verify the eectiveness of the proposed inverted strip-line-based tunable transmission-line in comparison with previously-reported tunable t-lines. Chapter 6 concludes the dissertation with remarks and suggestions for future work. 7 Chapter 2 Architectural and Circuit Tradeos for RF and mm-wave beamforming and MIMO receiving arrays From a signal processing perspective, a wireless receiver can be thought of as a system divided into the following subsystems: antenna, analog front-end, analog baseband, data conversion, frequency generation, and digital baseband [2]. The analog front-end is comprised of bandpass lters, ampliers, and mixers. The analog baseband is also comprised of low-pass lters and gain stages. In most receiver designs, the channel selectivity and interference mitigation are predominantly set by the analog low-pass lters. The analog baseband is followed by the data conversion and digital baseband subsystems, where data is converted from analog to digital domain, ltered and passed on to further digital signal processing units. 8 A key factor dictating the choice of receiver architecture is the power consump- tion, particularly in handheld and mobile devices. The optimal receiver architecture with minimal power cost may vary based on communication application, signal and interference condition, and available IC technology. This chapter attempts to give an initial estimation of the overall power consumption of various receiver array choices. This system-level power calculation is based on receiver building blocks analysis where design trade-os are studied in details. 2.1 Performance trade-o for mm-wave Receiver Building Blocks In this section, we model the power consumption of recongurable receiver building blocks as functions of major design parameters. 2.1.1 Passive Circuit Building Blocks Passive Lowpass Filters (LPF): The transfer function of a generic lossless LPF with N poles and M zeros (N > M) may be expressed as H LPF (s) = N(s) D(s) = 1 + P M i=1 a i s i 1 + P N i=1 b i s i : (2.1) 9 The poles and (transmission) zeros of the LPF are roots of the nominator and denominator, respectively. Group delay, dened as the minus derivative of the phase response with frequency, at zero frequency is given by T D (0) = T D (!)j !=0 = d\H LPF (j!) d! j !=0 =b 1 a 1 : (2.2) Within a decade of the pole frequency, ! , each pole aects the phase response with -45 degree per decade as \H LPF (j!)j !2(!=10;10! ) 4 log 10 ! ! : (2.3) Therefore, each pole introduces group delay that is equal to T D (!)j !2(!=10;10! ) = d\H LPF (j!) d! 4 log 10 (e) 1 ! 0:34 ! : (2.4) In an N-pole lter with purely real poles and purely imaginary zeros, the largest possible group delay is then given by T D;LPF;max (!) 0:34 N ! : (2.5) In most lters, the maximum group delay occurs at the edge of passband. Therefore, T D;LPF;max (!) 0:34 N BW ; (2.6) 10 where BW is the single-sideband bandwidth of the LPF. Now, let us consider the lter loss that is due to the loss of passive components such as inductors and capacitors. Let's assume that the loss of inductor (L) may be modeled with a series resistance (R), and the loss of capacitor (C) may be modeled with a parallel conductance (G). Under fairly generic assumptions, the passband insertion loss (IL) of an LPF may be related to its passband group delay, T D (!), and the loss of lter components as [3] IL LPF (!)[dB] 8:68 T D (!)k Q ; (2.7) wherek Q ,R=L =G=C is assumed to be constant for all inductors and capacitors in the lter. From Eqn. 2.6 and 2.7, the maximum passband insertion loss of an N-pole LPF with purely-real poles may be expressed as IL LPF (!)[dB] 8:68 0:34 N ! k Q 3 N ! k Q : (2.8) Passive Bandpass Filters (BPF): A band-select bandpass lter can be placed right after the receiving antenna to suppress out-of-band blockers. In a classical lter design approach, a BPF centered at frequency ! 0 is synthesized by applying the following transformation to a low-pass lter (LPF) transfer function s7!Q s ! 0 + ! 0 s ; (2.9) 11 where s is the Laplace transform variable. With this transformation, the transfer function of the LPF is essentially shifted to be centered around! 0 . In RF and mm- wave frequencies, the loss of components is often characterized by the component quality factor (Q). The quality factor is proportional to the ratio of stored to lost electromagnetic energy in one RF cycle. The quality factor of an inductor and a capacitor are given by Q L = !L R and Q C =!CG, respectively. In a lossless passive component, the quality factor is innity. Assuming identical quality factor for all the passive components in a BPF (Q C =Q C =Q), the passband insertion loss of a BPF may be expressed as [3] IL BPF (!)[dB] 8:68 T D (!)! 0 Q : (2.10) Similarly, the maximum passband insertion loss of an N-pole BPF having double- sideband bandwidth (BW) centered around! 0 with purely imaginary transmission zeros may be expressed as IL BPF;max (!)[dB] 8:68K N BW ! 0 Q ; (2.11) where K accounts for the eect of complex poles on the group delay, and it depends on lter type. For example, for Butterworth LPF, is about 1.3. For Chebychev lter with 0.5 dB passband ripple, the factor is about 1.8 [1]. The number of poles in the lter depends on the transition band and stopband specications. In 12 Figure 2.1: Performance summary of representative reported 20 - 94 GHz mm-wave passive BPFs versus the fractional bandwidth. general, a more selective lter requires a steeper transition band and larger number of poles, which may cause more insertion loss, and this performance trade-o is limited fundamentally by the quality factor Q. Figure 2.1 compares some representative reported 20 - 94 GHz mm-wave dis- crete ([4]-[12]) as well as integrated ([13]-[22]) passive BPFs' performance with the extrapolated Q eff based on Eqn. 2.11 assuming a unity lter-type constant K = 1. Discrete BPFs can be made tunable while maintaining relatively high quality 13 factors due to the low-loss lter tuning mechanisms such as MEMS-based varac- tors [4] and manually-recongured structures [5]. Compared to dielectric waveg- uide/cavity based tunable BPFs withQ eff around 20000, the conduction-loss along the electromagnetic-based wave-guiding structures is more signicant if the BPFs are implemented on a integrated platform, where the metal and dielectric material qualities are relatively poor. Integrated mm-wave lters with xed lter transfer functions fail register an eective Q over 40 as shown in Fig. 2.1, and it would drop even further for tunable channel-select monolithic BPFs consisting of integrated varators with typical Q around 10 [23] at mm-wave frequencies. Relatively high- insertion loss together with the non-negligible foot-print prevent a popular use of front-end BPFs in mm-wave radio designs, especially for large-scale array systems. Passive Phase-Shifter: Passive variable phase shifters (Fig.2.2) are pre- ferred over their active counterparts due to higher linearity and lower power con- sumption, with the insertion loss being one of the design challenges especially for high-resolution implementations. Similar to the passive BPFs, the insertion loss of passive shifters operating at mm-wave frequencies is mostly limited by the tuning mechanism. For example, Fig. 2.3 shows the analytical insertion loss of a passive re ection-type phase-shifter [24], which consists of a loss-less quadrature hybrid, and varactors with dierent Q at the re ection load. The expected analytical in- sertion loss is around 10 dB for a 360-degree re etion-type phase shifter loaded with a Q=10 varactor. 14 Figure 2.2: Representative schematic of various phase-shifter design. 15 Figure 2.3: Insertion loss of a passive re ection-type phase-shifter with varactors of dierent quality factor. 16 Figure 2.4: Performance summary of representative reported mm-wave passive phase shifter designs. 17 Figure 2.4 summarizes performances of some reported mm-wave passive phase- shifters, which are implemented based with various phase-shifter topologies includ- ing re ection-type ([23][25]-[28]), switched-LC ([29]-[36]), and tunable transmission- line-based ([37]-[41]). For a state-of-the-art mm-wave passive-shifter with high- resolution, the insertion loss is expected to be around 10 dB for a 360-degree of phase shift range. Transistors with gates terminated to a control voltage through a large resistor serve as linear and robust tunable mechanisms for phase shifters with IIP3 higher than 30 dBm [37]. Since the phase shifters are located at the very front-end of the array prior to any array power combination, they rarely have to withstand a signal level of more than 25 dBm. In this work, the non-linearity of the phase shifters is ignored. Passive Quadrature Down-conversion Mixer: Switching transistors used as mixers are often treated as passive components since they do not directly draw any power. Nonetheless, the mixer drivers do consume non-negligible power especially when used to drive transistors with small ON-resistance switching at mm-wave frequencies. A recent trend have witnessed a popular use of passive mixers for mm-wave frequency converters due to the supe- rior linearity and power eciency [110]. The performance trade-o among linear- ity, noise factor and power consumption of a 4 -phase quadrature passive mixers' 18 (Fig.2.5), dictated by the ratio between ON-resistance of the switching transis- tors R SW and source resistance R S ( =R SW =R S ), can be expressed based on the analysis in [42] as IIP3 OOB = r 8 3 (1+) 4 3 [V OD 2 +V SAT 2 (1+)] (2.12) F MIN = (1 +) h 1 + 1+ +16! LO =! SW 4:28(1++16! LO =! SW ) + TR ! LO 12 i (2.13) Power = 4V DD 2 2R S ! LO ! SW 1 + 6 TR ! SW ; (2.14) where IIP3 OOB is the calculated out-of-band IIP3, F MIN is the minimal achiev- able noise factor. ! LO is the LO switching frequency, with TR being the rise-fall time of the LO clocking waveforms. V OD and V SAT are the over-driving voltage and velocity-saturation voltages of a given technology, respectively. The other technology-dependent parameter is ! SW [129], and it is dened as inverse of prod- uct ofR SW and individual switch parasitic capacitanceC SW [! SW = (R SW C CW ) 1 ]. Quadrature passive mixers base on Eqn. 2.12-2.14 for dierent CMOS technol- ogy parameters are compared for their linearity, noise and power consumption, with results shown in Fig. 2.5. With IIP3-OOB and NF MIN mostly dictated by and RF , the superiority of 28nm CMOS as a more advanced technology over 45nm and 65nm CMOS shows up fully at the power consumption comparison in Fig. 2.5(c) and (f), by which more ecient charging and discharging of the mixer gates are granted. 19 Figure 2.5: Performance characterization of quadrature passive mixers on out-of- band IIP3, minimal achievable NF, and power consumption for (a)-(c) dierent relative switch resistance , and (d)-(f) dierent switching frequency f LO . All results are generated based on Eqn. 2.12 to Eqn. 2.14. 20 2.1.2 Active Circuit Building Blocks General Limits on Power Consumption of Active Circuit Components:. For any active block with source resistance R S , assume that the maximum linear voltage swing at the RF input is V in;max limited by the -1dB compression point (ICP 1dB ) as ICP 1dB = V 2 in;max 2R S : (2.15) The maximum linear voltage swing at the output V out;max of this active circuit having voltage gain A V is given by V out;max =A V V in;max =A V p 2R S ICP 1dB : (2.16) The maximum output voltage swing of a linear block (up to the -1dB compression point) is limited by V DD for an inductive connection to the supply voltage, and by the product of DC current (I DC ) and the eective resistance at the output (R D ). In other words, for inductive connections to the supply voltage V out;max <minfV DD ;I DC R D g: (2.17) 21 Hence, the lowest value for the supply voltage, DC current, and DC power con- sumption, in the case of inductive connection to the supply voltage can be found to be, respectively as, V DD > A V p 2R S ICP 1dB ; (2.18) I DC > 1 R D A V p 2R S ICP 1dB ; (2.19) P DC = V DD I DC > 2 R S R D A 2 V ICP 1dB : (2.20) Low Noise Amplier: Consider a LNA implemented as an inductively- degenerated common-source amplier with tuned load as in Fig. 2.6, and the real-part impedance looking into the amplier is assumed to be matched to a source resistance of R S . In other words, RefZ IN g = R IN g m L S C GS =R S : (2.21) The voltage gainA V and noise factorF , under input impedance matching condition, are given by A V = R D 2!L S (2.22) and F 1 + g m R S ! g m =C GS 2 ; (2.23) 22 where R D is the eective resistance of the load resonator at resonance, and its contribution to the noise factor is ignored. Eqn. 2.21 to Eqn. 2.23, together with Eqn. 2.18 can now be combined to nd a lower-bound on noise factor F 1 + g m 1 4R S R D A V 2 > 1 + g m 1 4R S p 2R S ICP 1dB I DC 2 = 1 + g m I DC ICP 1dB I DC : (2.24) From Eqn. 2.24 and Eqn. 2.18, a lower-bound on the DC power consumption as a function of linearity and noise factor requirements can be found as P DC > g m I DC ICP 1dB 3=2 F 1 A V p 2R S : (2.25) In MOSFETs, assuming the transistor is biased in velocity saturation (which is reasonable given the desire to have a linear current-voltage characteristic), g m =I DC is also independent of bias conditions and only a function of technology. Equation 2.25 validates a performance metric, the Figure Of Merit (FOM) for a low-noise amplier given by FOM LNA = G (IIP3) 3=2 P DC;LNA (F 1) ; (2.26) 23 Figure 2.6: Performance summary of representative reported 20 - 80 GHz mm-wave silicon CS LNAs versus extrapolated FOM LNA lines. where G is voltage gain, and F is the noise factor. IIP3 is the input-referred 3rd-order interception point, and it is assumed to be 10-dB lower than the -1dB compression point. Figure 2.6 compares the performances of some reported mm-wave LNA designs [44]-[61] along with the FOM LNA lines dened in Eqn. 2.26, with all LNAs imple- mented as common-source(CS) ampliers or close variations operating in 20 - 80 GHz frequency range. The state-of-the-art FOM LNA is around 1 mW 1=2 . Active Down-conversion Mixer: Consider a double-balanced current-commuting Gilbert-cell active mixer (Fig.2.7), and the expressions for voltage conversion gain and noise factor are given by CG = 2 g m R D (2.27) 24 and F 1 + 2 2 1 g m R S = 1 + 2 R D R S 1 CG ; (2.28) where R D is the eective resistance at the output, and the noise contribution of the g m transconductance transistors is dominant over all the other noise sources. Equation 2.29 can be combined with Eqn. 2.16 to provide a lower-bound on noise factor as F> 1 + 2 V out;max R S I DC 1 CG = 1 + 2 p 2R S ICP 1dB R S I DC : (2.29) Equation 2.29 combined with Eqn. 2.16 lead to a lower bound on power consump- tion as a function of specied linearity, noise factor, and conversion gain require- ments P DC > CGICP 1dB F 1 : (2.30) Equation 2.30 validates a performance metric, the Figure Of Merit for the active downconversion mixers given by FOM Mixer = CG IIP3 P DC;Mixer (F 1) ; (2.31) where CG is conversion voltage gain, and F is the noise factor. IIP3 is the input- referred 3rd-order interception point, and it is assumed to be 10-dB lower than the -1dB compression point. 25 Figure 2.7: Circuit schematic of a representative double-balanced Gilbert-cell active mixer. Figure 2.8: Performance summary of representative reported 10 - 70 GHz mm-wave Gilbert-cell active mixers versus extrapolated FOM Mixer lines. 26 Figure 2.8 compares the performances of some recently-reported mm-wave active mixer designs [62]-[76] along with the FOM Mixer lines dened in Eqn. 2.31, with all mixers implemented as Gilbert cells or close variation operating in 10 - 70 GHz frequency range. The state-of-the-art FOM Mixer is around 0.1. RF active vector-modulator (VM): RF active vector-modulators can be used active phase shifters, where variable gain is placed upon quadrature signals before combining network to achieve desired phase shift. Since the variable gain units in the VM implemented as in [77] have similar circuit design topologies as Gilbert-cell active mixers, in this work we assume the Rf active VMs follow similar performance trade-os of active mixers which can be expressed as FOM RFActiveVM = G IIP3 P DC;RFActiveVM (F 1) : (2.32) Figure 2.9 compares the performances of some recently-reported mm-wave active mixer designs [27],[77]-[83] along with the FOM RFActiveVM lines dened in Eqn. 2.32, with all reported VMs operating in 10 - 70 GHz frequency range. The state- of-the-art FOM RFActiveVM is around 0.05. Baseband analog LPF and Variable-Gain Amplier (VGA): Due to similar circuit topologies, baseband LPFs and VGAs as baseband core processing 27 Figure 2.9: Performance summary of representative reported 10 - 100 GHz mm- wave RF active VMs versus extrapolated FOM RFActiveVM lines. 28 units can be co-characterized as a bundled module. Consider a OTA-based RC lter, and its performance can be predicted by a FOM LPF+VGA dened in P LPF+VGA = SFDRN G BW Ch FOM LPF+VGA ; (2.33) , with derivations covered in [84] and [85]. Here N is the lter order, G is the module voltage gain,BW Ch is the channel bandwidth in Hz. SFNR is the spurious- free dynamic range, and the relationship between the SFDR, IIP3 and RMS noise (P noise ) is given by [87] SFDR dB = 2 3 (IIP 3 dBV P noise;dBV ): (2.34) Figure 2.10 summarizes performances of some reported active LPF and VGA designs [87]-[101] along with the FOM LPF+VGA lines, and it shows that the state- of-the-art FOM LPF+VGA is around 20 10 15 J 1 . Analog-to-digital converter (ADC): It is well known that high-performance ADCs are not currently power ecient, and this trade-o can be characterized as [102] P ADC = FOM 2 f Sample 2 ENOB ; (2.35) wheref Sample is the sampling speed of ADC in Hz, ENOB is the ADC eective bit, and we assume FOM ADC = 50 fJ/conv for a modern ADC. 29 Figure 2.10: Performance summary of representative reported active LPF+VGA designs versus extrapolated FOM LPF+VGA lines. 30 Frequency Synthesizer and Digital Signal Processor:Phase-locked loops (PLLs) are commonly used as frequency synthesizers in almost every electronic system to provided a clock or reference frequency. The timing jitter or phase noise of the PLL output is generally used as the main quality criterion, which in principle dictates the power drawn by the PLL as [103] P PLL;mW = 10 FOM 2;dB =10 2 T ; (2.36) where FOM 2;dB is assumed to be -240 dB for modern PLLs, T is the RMS jitter in second, and we use parameter T = 110fs which is sucient to facilitate a complete 5G radio link with EVM below -30 dBc [104]. Digital lters are required to extract signal samples from converted data streams. Power consumption of each FIR-based digital lters is [105] P DigiFilter = FOM DigiFilter f Sample N; (2.37) where N is the order of the digital lter and we consider N=100 for this chapter, and FOM DigiFilter is the energy per real multiply-and-accumulate operation in a FIR lter, and it is about 100 fJ at mm-wave frequency for a 28-nm CMOS technology [105]. 31 Figure 2.11: Summary of power performance characterization of various receiver building blocks. The digital arrays require digital beamformers multiplying the inputs from each antenna branch, and the power consumption for each of the beamformer is [105] P DigiBeamformer = FOM DigiBeamformer BW Ch ; (2.38) where BW Ch is the channel bandwidth, and FOM DigiBeamformer is the energy per complex multiply-and-accumulate operation, which is estimated to be 1 pJ at mm- wave frequency for a modern CMOS technology [105]. For an M-element digital array supporting N concurrent user beams, at least MN digital beamformers of such are required. Figure 2.11 summarizes the power performance characterization of various re- ceiver building blocks covered in this section. While satisfying the system-level as 32 well as block-level requirements set by the communication applications, the overall power consumption of a complete receiver consisting of aforementioned building blocks can be minimized by distributing power resource optimally to each block. Details of this system-level analysis and architectural optimization will be covered in the following section. 2.2 Power Consumption Analysis for mm-wave Receivers Array Architectures Wireless receivers at millimeter-wave frequencies are commonly employed in an array systems to improve the overall channel capacity and system robustness. A challenge for these systems is power consumption, particularly when large number of receivers with wide bandwidth are involved in presence of interferences. Nonethe- less, receivers with dierent architectural variation may have dierent power trend, and here more quantitative comparison will be demonstrated based on block-level characterization shown previously in Section 2.1. Phased arrays emulate a high-gain antenna by providing array gain, while also allow for the directional beam to be steered using on-chip phase shifting mechanism. Depending on the domain where the signals from dierent path are added up and the specic phase shifting mechanism, analog phased-array systems can be generally categorized as RF-path, baseband, and LO-path phase-shifting arrays. 33 Figure 2.12: Analog phased-array systems (a) with RF-path phase-shifting (RF Array), (b) with RF-path phase-shifting and late-LNA (RF Array, Late-LNA), and (c) with RF-path VM-based phase-shifting (RF Array, VM). Phase shifters in scheme (a) and (b) are all passive. 34 Figure 2.13: Analog phased-array systems (a) with baseband phase-shifting (BB Array), (b) with mixer-rst baseband phase-shifting (BB Array, Mixer-First), (c) with LO-path phase-shifting (LO Array), and (d) with mixer-rst LO-path phase- shifting (LO Array, Mixer-First). 35 Conventional analog RF phased-array systems, as summarized in Fig. 2.12(a), utilize RF-path passive phase-shifters to align the signals coming from the desired spatial direction and thus form a beam [64][106]. Low power consumption and relative compact area motivate the use of passive RF phase shifters, whose supe- rior tolerance against out-of-band blockers could be further exploited when placed directly after the receiving antenna as shown in Fig. 2.12(b). A late-LNA can be inserted after the combining network to help suppress the aect of noise due to the passive and lossy phase-shifters on the overall system noise gure. However, RF passive phase-shifters with high resolution and low insertion loss are challenging to achieve, while they could be replaced with active RF-VM based alternatives [107] in Fig. 2.12(c) for boosted gain. The phase shifting mechanism of an array can be achieved in baseband domain after the down-conversion mixers. In baseband arrays [108] as in Fig. 2.13(a), active vector modulators apply tunable complex weights to the information from each antenna path, which is added up in baseband domain and further digitized by the ADC. The baseband array variation re ecting on the recent trend of replacing the front-end LNA is displayed in Fig. 2.13(b) leaving the passive-mixers leading the receiving front-ends. Relocating the phase-shifters from RF-path to LO-path mitigates the insertion loss eect on the main signal path, while the same equivalent phase shift can be 36 Figure 2.14: Blocking test prole for mm-wave receivers. applied with phase-staggered mixers [109], and this architecture is displayed in Fig. 2.13(c) and the mixer-rst variation in Fig. 2.13(d). In conventional receiver designs, the down-conversion mixers and baseband low- pass lters are implemented using active circuitory for their gain and compactness. Recent works [110] have replaced the active LPFs by passive structures to benet power consumption and dynamic range. In this work, the insertion loss of the high-order passive LPF is assumed to follow Eqn. 2.8. Figure 2.14 illustrates the blocking prole assumed to test and compare various mm-wave receiver architectures. Two blockers IB-BLK1 and IB-BLK2 are placed in-band next to the desired signal, and in this work the level of IB-BLK2 is always assumed to be -20 dBm. An out-of-band blocker OOB-BLK is placed to the edge of 37 Figure 2.15: Representative signal levels at the input of each RF Array stage. 38 Figure 2.16: Representative signal levels at the input of each LO Array stage. 39 Figure 2.17: Representative signal levels at the input of each BB Array stage. 40 the in-band with a buering zone existing in between. With the IB-BLK1 and OOB- BLK at the array input are set to be -30 dBm and 5 dBm respectively, all signal levels which include the desired signal, noise, in-band as well as out-of-band blockers as they pass through the 32-element RF, LO and BB receiver arrays are shown in Fig. 2.15 to 2.17, respectively. Mixers and LPFs are all active implementations. All signal level data are taken at each input of corresponding receiver array stages, and if there are multiple equivalent receiving circuit blocks (e.g. LNAs and passive phase-shifters in the RF array) in parallel, the data only indicate the level of one of them at the input. The loss-less power combiners witness a 30.10 dB increase, which is given by 10log10(32 2 ) for a 32-element array, on the level of the desired signal due to constructive addition of voltage, and also a halved increase in dB for the noise due to direct addition of power. With the benet of the phase shifting mechanisms that are introduced in dierent ways across, both in-band blockers IB- BLK1 and IB-BLK2 have a relative rejection of -15 dB to the desired signals after the power combiner through possible array nulling [111] or other equivalent array techniques. It is important to note that this array nulling cannot introduce relative rejections to the out-of-band blocker OOB-BLK due to the bandwidth limitation on the phase-shift tuning mechanisms. In this work it is assumed that the OOB- BLK from input branches of power combiner add up in power following a gain of 15.05 dB given as 10log10(32) for a 32-element array, and the OOB-BLKs have to be attenuated to at least -13 dB below noise level to avoid any signicant aliasing. 41 Figure 2.18: Power consumption of RF-, BB-, and LO-arrays with dierent out-of- band blocker levels. Due to the lack of sucient front-end bandpass ltering, LNAs leading the receiver would be dynamic-range limited designs. The power consumptions of the LNAs and baseband LPFs, with the latter being the only channel-select components to lower the dynamic range of the band-select ADC input, occupy a signicant portion of the analog and mixed-signal receiver front-end power budget. Figure 2.15 to 2.17 give early implications and justications to eorts of replacing or removing the LNAs and active baseband components to reduce the overall receiver power consumption. Figure 2.18 summarizes the minimum power consumption of various analog phased-arrays with 32 antenna, -75 dBm sensitivity and 0.5 GHz of channel band- width in presence of a -30 dBm IB-BLK1. In this work the required minimum SNR is 10 dB. Note that power consumption gures in this chapter include power 42 Figure 2.19: Power consumption of RF-, BB-, and LO-arrays with dierent in-band blocker-1 (IB-BLK1) levels. Figure 2.20: Power consumption of RF-, BB-, and LO-arrays with dierent signal channel bandwidth. 43 Figure 2.21: Power consumption of RF-, BB-, and LO-arrays with dierent number of receiving antenna. invested to receiver front-end, ADC, digital lters, digital beam-formers (if apply), and frequency synthesizers (PLL). With the same dynamic range requirement, pas- sive implementation of mixers and LPFs require less power investment than their active counter-parts. Therefore, arrays with active mixers and active LPFs all consume more power than the arrays with passive mixers and LPFs as shown in Fig. 2.18. This dynamic-range-limited power consumption of active circuit blocks also predict an overall trend of the increase of array power consumption for higher OOB-BLK level. The only exceptions to this trend are the mixer-rst BB and LO arrays, where the OOB-BLK are well tolerated by the passive mixers, and subse- quently ltered by the passive LPFs before it places dynamic-range pressure on other baseband active circuitory. Due to the lack of ecient ltering, the front-end 44 active ampliers are required to operate under a high-dynamic range environment in case of high-level OOB-BLK demanding a signicant power budget. In partic- ular, among the arrays with passive mixers and LPFs, the RF arrays with VM have the highest expected power consumption, and this is because they have two front-end ampliers in cascade: one LNA and one VM. The total number of front- end ampliers can be reduced to one late-LNA in the common receiver path of a RF array, and predominately relaxes the power overhead on the arrays with same mixers and LPFs options. Ultimately, the front-end ampliers can be removed al- together leaving the passive mixers leading the receiver front-end, and as shown in Fig. 2.18, the resulting mixer-rst BB and LO receiver arrays have the highest power eciency among all array architectures regardless of the OOB-BLK level. In-band blockers when buried underneath the more signicant OOB-BLK would not aect the dynamic-range-limited analog front-end power consumption. How- ever, as indicated Fig. 2.19, when the in-band blockers becomes comparable to the OOB-BLKs, their post-LPF residue start to dictate the ADC input dynamic range demanding a higher power consumption. Once rise beyond the OOB-BLK level (5 dBm in Fig. 2.19), the in-band blockers would dominate the dynamic-range of the entire analog and mixed-signal receiving front-end, and therefore drive up the total array power consumption. Most of active circuit blocks of the receivers have a near linear dependence of power consumption on bandwidth, so across the table in Fig. 2.20 we observe 45 that the arrays' power consumption rise with channel bandwidth. Note that as the bandwidth increases, the phase shifters and vector modulators have to increase their bandwidth as well, and ultimately they would have to insert nearly true-time-delay between antenna path to steer the broadband signal properly in spatial domain, which fundamentally limits the throughput of high-speed arrays [112]. Arrays of larger scales are preferred in applications when complicated array patterns are required for excessive signal processing in spatial domain, or to com- pensate the link propagation loss by increasing the eective antenna aperture size [113]. Figure 2.21 quantitatively compares power consumption of the various ar- rays from with 2 antenna to with 512 antenna. For array architectures including RF arrays with late-LNA, BB and LO mixer-rst arrays, they have lossy and thus noisy components such as passive phase-shifters or passive mixers lead the entire receiver, and they fail to satisfy the required NF for arrays with antennas fewer than 8. Having low-noise gain at the front-end (e.g. LNA) provides necessary for arrays with low-number of antennas, where the system is primarily limited by SNR and not SNIR. As the array scale grows, active mixers and active LPFs in the RF and LO arrays consume most of the power due to the linearity requirement set by the combined blocker power from all antenna branches. Though the combined blocker power would have to increase with the number of antenna branches, each individual active mixers and LPFs can aord to have more noise due to the benet of extra 46 array gain, and overall active mixers and LPFs have similar dynamic range require- ments regardless of the array size. One major dierence of larger-scale arrays from small-scale arrays though, is that for the same sensitivity requirement, the active circuitories can provide less active gain with the help of increased array gain, and thus with the same dynamic range requirement, the active mixers and active LPFs do consume overall less power as correctly suggested by Fig. 2.21. Nontheless, in- creasing number of active mixers do eventually at the benet of larger array gain when the antenna number increases for LO arrays with active mixers and LPFs, and it inevitably drives up the power requirement for BB arrays with more active LPFs. Arrays with passive mixers and LPFs are more robust under the increased linearity stress on blocks after the combining network as shown also in Fig. 2.18, therefore they are more power ecient with antenna number fewer than about 100 and gradually loses their advantage towards arrays with larger scale. Analog arrays summarized in Fig. 2.12 and Fig. 2.13 can be expanded to support more than one data stream, and one of the common congurations this expansion is called hybrid arrays [114] as shown in Fig. 2.22 -2.24, where several analog arrays are 'merged' in a hybrid way to share a few front-end blocks before reaching to separate data processing chains. Specically, hybrid arrays are popu- lar candidates for implementation of multi-input multi-output (MIMO) schemes, because they can steer independent data streams to dierent spatial directions by 47 Figure 2.22: Hybrid array systems (a) with RF-path phase-shifting (RF Hybrid), (b) with RF-path phase-shifting and late-LNA (RF Hybrid, Late-LNA), and (c) with RF-path VM-based phase-shifting (RF Hybrid, VM). Phase shifters in scheme (a) and (b) are all passive. 48 Figure 2.23: Hybrid array systems (a) with baseband phase-shifting (BB Hybrid), and (b) with mixer-rst baseband phase-shifting (BB Hybrid, Mixer-First). 49 Figure 2.24: Hybrid array systems (a) with LO-path phase-shifting (LO Hybrid), and (b) with mixer-rst LO-path phase-shifting (LO Hybrid, Mixer-First). 50 Figure 2.25: Power consumption of RF, BB, and LO hybrids with dierent out-of- band blocker levels. enforcing dierent equivalent analog phase-shifting weights on dierent user chan- nels. Figure 2.25 to Fig. 2.28 summarizes the minimum power consumption of various hybrid arrays with 2 streams and -75 dBm of sensitivity requirement. It is apparent that similar trends shown in analog arrays' comparison gures can be observed here as well, in that arrays with active mixers and LPFs consume increasing amount of extra power compared with the ones with passive counterparts in almost all circumstances except when the scale of the array grows beyond a certain level. Nontheless, when used as the rst circuit blocks instead of LNAs, the resulting passive-mixers-rst hybrid array scheme would always consume less power than the same arrays with LNAs as shown in Fig. 2.28 regardless of the application. Hybrid 51 Figure 2.26: Power consumption of RF, BB, and LO hybrids with dierent in-band blocker-1 (IB-BLK1) levels. Figure 2.27: Power consumption of RF, BB, and LO hybrids with dierent signal channel bandwidth. 52 Figure 2.28: Power consumption of RF, BB, and LO hybrids with dierent number of receiving antenna. arrays with lossy components leading the receiver front-end, including RF Hybrid with late-LNA, LO-, and BB-mixer-rst Hybrids, cannot satisfy the minimum NF requirement with only 2 antennas available. The capacity expansion of hybrid array to support more user streams calls for hardware up-scaling, and since each user stream requires independent signal pro- cessing, the power consumption scales almost linearly to the supported capacity as shown in Fig. 2.29. BB hybrid arrays with active mixers and LPFs have scales up its power consumption more mildly than other active hybrid arrays due to the simplicity of their phase shifting mechanism and post-combing baseband signal processing chain. Arrays deployed at the side of base stations are required to sup- port more user steams than user equipement, and they demand more number of 53 Figure 2.29: Power consumption of RF, BB, and LO hybrids with 32 antennas and dierent number of supported user streams. Figure 2.30: Power consumption of RF, BB, and LO hybrids with 4096 antennas and dierent number of supported user streams. 54 elements/antennas. Figure 2.30 gives expected base station array power consump- tion, and it rises with growing supported capacity similar to Fig. 2.29 for a much smaller arrays. Nontheless, an interesting observation nds the RF arrays with VM and passive mixers consume more power than the ones with active mixers. When the array scale grows large, the combined power showing up at the input of the RF array mixers are signicant. While the active mixers designs with high linearity but also high NF are not necessarily power-hungry, the passive mixers unfortunately demands signicant power for larger transistors with high linearity regardless of the noise performance. Digital arrays, where each antenna is followed by a dedicated receiver and data converter, are gaining more interest thanks to the superior exibility and function- ality of digital array architectures over their analog and hybrid counterparts [116]. Though the concept of digital beamforming is developed sometime ago [115], the continued improvement in the energy eciency of data converters and digital pro- cessors have enabled rst waves of digital arrays implementation towards real-life applications[116]. Figure 2.31(a) is a representative schematic of such digital array, and similar to the hybrid arrays, the front-end LNAs can be removed leading to passive-mixer-rst digital arrays as shown in Fig. 2.31(b). The signal levels as they pass through a representative digital array is presented in Fig. 2.32. Figure 2.33 to Fig. 2.36 summarizes the minimum power consumption of digital arrays with -75 dBm of sensitivity requirement. Similar to the corresponding analog 55 Figure 2.31: Digital array systems (a) with LNAs (Digital Array), and (b) without LNAs (Digital Array, Mixer-First). 56 Figure 2.32: Representative signal levels at the input of each Digital Array stage. 57 Figure 2.33: Power consumption of digital arrays with dierent out-of-band blocker levels. Figure 2.34: Power consumption of digital arrays with dierent in-band blocker-1 (IB-BLK1) levels. 58 Figure 2.35: Power consumption of digital arrays with dierent signal channel bandwidth. Figure 2.36: Power consumption of digital arrays with dierent number of receiving antenna. 59 Figure 2.37: Power consumption of digital arrays with 32 antennas and dierent number of supported user streams. Figure 2.38: Power consumption of digital arrays with 4096 antennas and dierent number of supported user streams. 60 and hybrid architectures, mixer-rst digital arrays with only 2 antennas available cannot satisfy the minimum NF requirement. Apart from the similar trends shown up also in analog and hybrid arrays, one unique nding about digital array is demonstrated in Fig. 2.36 where all three arrays' total power increase with antenna number, and this is because the majority of the power is consumed in mixed-signal and digital circuits. When each antenna path requires a separate ADC and a separate high-order digital lter, and overall system power would have to increase accordingly to accommodate the booming capacity. The communication capacity, in particular the number of concurrent user streams supported for a digital array given a xed scale can be expanded in digital domain processors. Figure 2.37 indicates that the additional power due to this digital-domain capacity upscaling is almost negligible for a small-scale user equipment, but can be signicant for a large array supporting hundreds of user streams as shown in Fig. 2.38 when additional digital beamformer units dominate the power consumption overhead. Power comparison among all aforementioned array architectures are shown in Fig. 2.39 to Fig. 2.42. Passive mixers and LPFs with their superior linearity im- mune the array system from extra blockers while the active counterparts contribute the most to the increase of power consumption with higher OOB blocker levels indi- cated in Fig. 2.39 and 2.40. Digital arrays when equipped with passive mixers and LPFs have approximately the same power eciency as arrays with active mixers 61 Figure 2.39: Power consumption of arrays with dierent out-of-band blocker levels. 62 Figure 2.40: Power consumption of arrays with dierent in-band blocker-1 (IB- BLK1) levels. 63 Figure 2.41: Power consumption of arrays with dierent signal channel bandwidth. 64 Figure 2.42: Power consumption of arrays with dierent number of receiving an- tenna. 65 Figure 2.43: Power consumption of arrays with 32 antennas and dierent number of supported user streams. 66 Figure 2.44: Power consumption of arrays with 4096 antennas and dierent number of supported user streams. 67 Figure 2.45: Power consumption of arrays with (a) 32 elements and (b) 4096 el- ements, of which digital processors are implemented by digital technologies with dierent normalized power eciency. and LPFs in presence of high-level blockers. Unlike the channel bandwidth expan- sion not aecting the relative trend of power consumption among various arrays as shown in Fig. 2.41, the scale of the array system or in other words the number of receiving antennas plays a critical role of setting up the optimal architecture at least in terms of power consumption. RF analog array with passive mixers and LPFs always serves as the most ecient array architecture regardless of the array scale. If more than one user stream is demanded, then at lower end of antenna number axis of Fig. 2.42 the hybrid and digital arrays and with passive components carry less power consumption, while they gradually lose their advantage and eventually prevails to hybrid arrays with active counterparts. Since use of passive front-end units signicantly mitigate the analog front-end cost, for most applications digital arrays are more power-hungry compared to the 68 analog and hybrid arrays due to the independent mixed-signal and digital hard- ware implementation. This power consumption gap may be reduced if more power- ecient digital technology is employed for the implementation of digital processors as shown in Fig. 2.45. Nontheless, the new levels of performance and multifunc- tionality such as MIMO applications supporting large numbers of users streams, might eventually put digital implementation to its advantage, and other array de- sign constrains besides the power consumption such as area-cost and signal-routing complexity [114] may further justify the migration to digital arrays for 5G and beyond applications. 2.3 Conclusions and Recommendations for Future Work This chapter summarized major performance trade-os of building blocks for large- scale mm-wave receiver arrays, with an emphasis on power consumption. In princi- ple, under the same system-level requirement including linearity and sensitivity, DC power as a resource to any receiver architecture can be optimally distributed to the corresponding receiver building blocks in an eort to achieve minimal overall power consumption. Optimal power consumption of various receiver and receiver-array architectures consisting of aforementioned building blocks are compared. The ulti- mate architecture with optimal power eciency depends on signal and interference 69 conditions, communication applications, the system scale as well as IC technology parameters. The analytical results highlighted in this chapter focus on performance down- conversion receivers, and the similar system-level calculation can be readily ex- panded to heterodyne receivers and its variations. Phase shifters and vector mod- ulators that can insert nearly true-time-delay between antenna path are vital for high-speed large-scale arrays, while their designs remains as challenging topics. Though the eect of power combining as well as LO distribution network is ignored in this chapter, wide-band low-loss and compact signal network, especially for a large-scale receiver array at mm-wave frequency can be challenging. Ultimately, the drive towards high-speed and low-power data converters and digital processors are vital to fully open up the exibility and functionality of digital array architec- tures. 70 Chapter 3 RF Filter Synthesis based on Passively-Coupled N-Path Resonators 3.1 Introduction Wireless communication receivers incorporate a number of radiofrequency (RF) lters, each tuned at one of the desired frequency bands, at the front end so that the undesired signals are substantially attenuated before reaching the active blocks. In principle, all these lters can be replaced with a single recongurable RF lter whose frequency response can be tuned. However, compact, low-loss, linear, se- lective, and recongurable RF lters have been dicult to implement specically in a CMOS platform where the passive components have low quality factors. In general, the in-band insertion loss of a bandpass lter (BPF) with components of homogenous quality factor Q is approximately given by (1.1). In an all-pole lter, This chapter is adopted from [129]. 71 Figure 3.1: Frequency responses of an ideal all-pole lter, and all-pole lters with nite-Q components and increasing lter order N. higher selectivity (higher transition-band roll-o) can be obtained with higher lter order (larger N) at the expense of an increased in-band insertion loss (Fig. 3.1). This fundamental trade-o makes it necessary to use technologies that oer high-Q passive components. An N-Path structure, consisting of an array of switched capacitors driven with non-overlapping phases of a clock, emulates the frequency response of a high-Q second-order RLC resonator whose resonant frequency is set by the clock frequency [117]. In the past, a passively-coupled network of N-path resonators has been used to synthesize high-order all-pole tunable lter transfer functions [118]-[121], albeit with limited selectivity due to the absence of transmission zeros. On the other hand, active networks have also been used to couple N-path resonators in pursuit 72 of more selective lters [122]-[124] at the expense of higher noise, nonlinearity, and power consumption. The objective of this paper is to realize passively-coupled N-path-resonator-based recongurable BPFs with high selectivity and a wide pass- band bandwidth. Transmission zeros can be added into the lter transfer function to improve the transition-band roll-o without signicantly changing the in-band response. Figure 3.2 shows that a BPF with transmission zeros has less pass- band insertion loss compared with an all-pole BPF with the same lter order, same component quality factor Q, and same pass-band bandwidth. In this paper, we demonstrate a synthesis approach that enables the realization of CMOS BPFs that utilize N-path resonators and passive coupling networks. The incorporation of transmission zeros in the transfer function results in wide pass-band bandwidth, sharp transition-band roll-o, and decent stop-band attenuation. The linearity and power consumption of the lter are acceptable thanks to using a passive coupling network. The paper is organized as follows. Section II demonstrates an intuitive approach to synthesize a BPF with transmission zeros. The lter consists of second-order LC-resonators, all tuned to the same frequency, and passive coupling networks. Section III shows how the second-order LC-resonators can be replaced with N-path resonators to realize a clock-tunable selective BPF with transmission zeros. Im- plementation details of a CMOS prototype recongurable BPF and corresponding 73 Figure 3.2: Frequency response of an all-pole BPF, and a same order BPF with transmission zeros. measurement results are covered in Sections IV and V, respectively. Section VI presents the concluding remarks. 74 3.2 synthesizing lters with transmission zeros based on passively-coupled LC resonators Close to the lter center frequency (given by clock frequency), N-Path resonators have been shown [122] to resemble LC second-order resonators with the same res- onator frequency and a scaled capacitor (Fig. 3.3). More specically, the equivalent RLC values of an N-Path resonator can be expressed as R P = sin 2 (=N) (=N) 2 sin 2 (=N) R S ; (3.1) C P = 2 2Nsin 2 (=N) C; (3.2) L P = 1 ! 2 CLK C P ; (3.3) leading to a quality factor given by Q P = R P C P ! CLK = 2 2N (=N) 2 sin 2 (=N) ! CLK R S C: (3.4) For example, a 4-phase N-Path resonator with 50 source resistance, and 30 pF switched capacitors, can have a quality factor around 100 at 1.0 GHz, which is signicantly larger than an on-chip LC resonator. The high quality factor of an N-path resonator may be exploited to realize a selective low-loss BPF. Such a lter should consist of high-Q N-path resonators, 75 Figure 3.3: Simulated input impedance of an N-Path resonator and its LC equiva- lence. all clocked with the same frequency, and passive coupling networks. Therefore, the rst step of our proposed synthesis method is the realization of a resonator-based BPF where all resonators have the same resonant frequency. Ideally, the resonators in such a lter can be replaced with their N-path equivalences to realize an N- path-resonator-based BPF (Fig. 3.4). This synthesizing methodology implies that basic building units available for passive-coupled LC resonator based lter synthesis are high-Q LC resonators of the same resonant frequency, capacitors, and on-chip inductors. Figure 3.5 shows three representative shunt topologies constructed with the available building units, as well as their corresponding reactance frequency re- sponses. All three shunt topologies have the same parallel resonant frequency at 76 Figure 3.4: BPF synthesis with N-Path resonators, capacitors and inductors. 77 Figure 3.5: Reactance frequency response of (a) N-branch, (b) C-branch, and (C) L-branch. ! 0 . The parallel LC resonator (N-branch) of Fig. 3.5(a) behaves inductively and capacitively at frequencies below and above the resonant frequency! 0 , respectively. Adding a capacitor in series with the parallel LC resonator, together making a so- called C-coupled shunt branch (C-branch), adds a transmission zero at a frequency ! LTZ (Fig. 3.5(b)) into the reactance frequency response, and this frequency ! LTZ is always below ! 0 . Likewise, a series inductor added to the parallel LC resonator (L-branch) adds an above-! 0 transmission zero at ! RTZ (Fig. 3.5(c)) in the reactance frequency response. It is worth noting that if a circuit schematic contains a C-coupled (L-coupled) shunt branch, then the overall frequency response must have a transmission zero at ! LTZ (! RTZ ). At all other frequencies, these circuits emulate an inductor or a capacitor as shown in the plots. 78 Figure 3.6: (a) Capacitor-coupled high-Q LC resonator as a BPF, (b) Low-Q- inductor-coupled high-Q LC resonator as a BPF, (c) Serial-inductor-and-capacitor- coupled high-Q LC resonator as a BPF, (d) Simulated frequency responses from BPFs shown in (a){(c), with same transmission zeros locations, and (e) serial- coupling inductor for various transmission zero locations, as required in (b) and (c). 79 Synthesized lters in this work only use these three congurations (N-, C-, and L-branch) in Fig. 3.5 as shunt connections. The loss of parallel LC resonators bring about extra in-band insertion loss. On the other hand, the loss of coupling capacitor and inductor in Fig. 3.5(b)-(c) reduces the rejections at corresponding transmission zeros. Given that the quality factor of an inductor is typically less than that of a capacitor, the transmission zero created by coupling inductors will be aected more (Fig. 3.6). This observation makes the use of shunt branches like in Fig. 3.6(c) even less desirable because the reduced rejected caused by series resistance from the low-Q inductor is present at both! RTZ and! LTZ . To create close-by transmission zeros on both sides of! 0 , values of coupling inductors L SERLC needed for L-and-C-coupled branch would be much larger compared with L SERL in L-branch as shown in Fig. 3.6(e). Another interesting observation on Fig. 3.6 is that even though a low-Q series inductor is used in an L-branch, there is hardly any insertion loss degradation around ! 0 compared with that of a C-branch. Here, insertion loss around ! 0 is dictated by the parallel resistance of the parallel resonator, not the series resistance of the coupling inductor. We will use high-Q N-Path resonators to emulate the parallel LC resonators to maintain low in-band insertion loss. Coupling inductors may be realized as spirals because their losses will not degrade the in-band insertion loss as much. 80 Figure 3.7: Representative synthesized BPFs and corresponding simulated fre- quency responses (loss-less components) with (a) 3-coupled LC resonators, (b) 4- coupled LC resonators, and (c) 5-coupled LC resonators. 81 Figure 3.8: Representative optimized 3-resonator-coupled LC lter components values for various BW and OOB rejection lter requirements. Figure 3.7(a) shows a basic coupled-resonators-based lter conguration with the three aforementioned shunt branches coupled by a series capacitor and a series inductor. This lter is designed to have a center frequency f 0 at 1.0 GHz, pass- band bandwidth 50 MHz, transition-band roll-o slope of 130 dB/100 MHz, and stop-band rejection of 22 dB. The frequency response of this lter consisting of only loss-less components is shown, with two transmission zeros f LTZ and f RTZ at 960 MHz and 1.04 GHz, respectively. Computer-aided parameter optimization is used to determine optimal values of each passive component based on specic lter response requirements. Figure 3.8 summarizes optimized components values for representative lter requirements with center frequency at 1.0 GHz. Components values of LC lters in Fig. 3.8 can be used either directly for lter syntheses at 82 Figure 3.9: Simulated frequency response comparison between a coupled LC res- onator and a directly-transformed N-Path resonator based lter. dierent center frequencies with proper scaling, or as initial conditions input to the optimization process targeting variant ltering requirements. More stringent lter response requirements can be satised by coupling more shunt branches to achieve higher order of ltering. More specically, shunt C-branches coupled with series capacitors and shunt L-branches coupled with series inductor can be added to the left and right of the main schematic to further enhance the lter selectivity (Fig. 3.7(b) and (c)). 83 3.3 synthesizing lters with transmission zeros based on passively-coupled N-Path resonators In theory, any coupled-LC-resonator-based lter synthesized as those in Section II can be readily transformed into a coupled-N-Path-resonator-based lter, by replac- ing the parallel LC resonators with N-Path resonators. However, in practice, direct replacement of LC resonators with N-Path resonators does not lead to a satisfactory frequency response. For example, the direct replacement of parallel LC resonators with N-Path resonators in the lter design of Fig. 3.9 leads to the disappearance of the lower-frequency transmission zero and deformation of the corresponding pass- band edge. The unwanted response can be traced back to instantaneous charge sharing between capacitors from dierent capacitively-coupled N-Path resonators. This undesired phenomenon can be prevented by introducing inductive coupling between N-Path resonators [125] because inductors prohibit the instant change of current. The higher-frequency transmission zero and corresponding passband edge, both formed by the inductively coupled L-branch, remain intact in the LC-to-N- Path transformation. In this work, we choose to eliminate direct capacitive coupling between the N- Path resonators by introducing extra buering inductors in the series path. The minimum buering inductor values required to stop the instant charge sharing depends on source resistance, loaded capacitors, and resonators operating frequency. 84 Figure 3.10: Simulated frequency response comparison between a coupled LC res- onator and the directly-transformed N-Path resonator based lters, with additional buering inductors. Meanwhile, the upper bonds of buering inductor values are ultimately set by the desired frequency response. More details of sizing buering inductors are discussed in the Appendix A. Figure 3.10 suggests that the N-Path resonator based lter now has an identical response to its LC-alternative in the presence of the properly sized series buering inductors. As discussed in the last section, lter performance, for the most part, is dictated by the Q of the parallel resonators and not by the Q of the series- or shunt-coupling inductors. As shown in the simulation results in Fig. 3.11, using coupling inductors with Q of 10 slightly degrades the lter response. However, reducing the Q of parallel resonators to the same value of 10 fundamentally changes the lter response making it practically useless. This further proves the necessity of N-Path resonators to the lter synthesizing method proposed in this paper. 85 Figure 3.11: Eects of nite-Q inductors on simulated lter frequency response. 3.4 CMOS Implementation Previously, all switches used for N-Path resonator based synthesis are assumed to be perfect \ON-OFF" state switches. In reality, however, CMOS transistor used as switches in N-Path circuits always carry nite switch resistance and nite parasitic capacitance. Switch resistance as extra resistance in shunt paths would increase the equivalent impedance at both in-band and out-of-band frequencies [122] [126] [42]. This increased impedance, however, aects the in-band and out-of- band lter responses of an N-Path lter dierently as shown in Fig. 3.12. In band, without the presence of parasitic capacitance, R SW can be merged in series with source resistance R S following Thevenin{Norton equivalence transformation. This additional resistance would slightly increase resonator Q as indicated in (3.5), where R S from (3.4) is now replaced with R S + R SW . However, at out-of-band frequencies 86 Figure 3.12: Eect of nite switch resistance R SW on simulated input impedance frequency response of a single N-Path resonator. where smaller input impedance is preferred to achieve larger rejection, increasing R SW is detrimental. Q PR SW = 2 2N (=N) 2 sin 2 (=N) ! CLK (R S + R SW )C: (3.5) The parasitic capacitance of CMOS transistors used as switches leads to un- wanted charge sharing among the branches of switched capacitors. This deteriorates the lter in-band response by eectively reducing the resonator quality factor (Fig. 3.13). If this N-Path resonator is used in a two-port system as a BPF, theoretical 87 Figure 3.13: Eect of parasitic capacitance C PAR on simulated input impedance frequency response of a single N-Path resonator. 88 analysis in [127] shows that C PAR then would reduce in-band gain approximately to G = (1)= (1 (1)) (3.6) for small , where = C PAR =(C + C PAR ), = e =R S (C+C PAR ) , and = T CLK =N. Hence, the resonator quality factor Q PC PAR in the presence of C PAR can be ex- pressed as Q PC PAR = G! CLK C P R S Q P ! CLK C P R S + Q P (1G) ; (3.7) where C P and Q P are dened in (3) and (3.4), respectively. The product of R SW and individual switch parasitic capacitance C SW (= C PAR =N) is nearly a constant across various CMOS switch sizes, and only a function of tech- nology. For instance, this product is approximately 400 fs in the 65nm CMOS process. Smaller switch size (larger R SW , smaller C SW ) results in lower in-band in- sertion loss at expense of reduced out-of-band rejection. On the other hand, larger switch size (smaller R SW , larger C SW ) results in larger in-band insertion loss while maintaining decent out-of-band rejection. Figure 3.14 shows the eective in-band quality factor and out-of-band to in-band rejection for an N-Path resonator when N=4, and impedance of both input and output port equal to 50 as a function of 65nm NMOS switch size for dierent switched capacitor C values. Therefore, switch sizes are often times a design choice and can vary based on applications and N-Path lter schematics. Simulation results in Fig. 3.15 display frequency 89 Figure 3.14: Eective in-band quality factor and out-of-band to in-band rejection for an N-Path resonator as a function of 65nm NMOS switch size for dierent switched capacitor C values. All NMOS transistors have minimum length, and both port impedance equal to 50 . response of the proposed coupled 4-phase N-Path-resonator-based lter, with three dierent combination of R SW and C PAR assuming R SW C SW = R SW C PAR 4 = 400 fs. These curves may suggest that a switch size corresponding to R SW = 5 and C PAR = 320 fF yields the most reasonable trade-o between in-band insertion loss and out-of-band rejection. Furthermore, scaled CMOS technology with reduced R SW C SW product would improve the performance of such switched-capacitor-based synthesized lters. 90 Figure 3.15: Simulated frequency response of proposed coupled N-Path-resonator based lters, with dierent equivalent switch sizes. In theory, negative resistances may be added in parallel to each N-Path resonator to compensate loss and bring the lter response closer to the original case (loss-less resonators) with much less in-band insertion loss and better selectivity. Here, the required negative resistance is far less compared with what would be needed if low- Q on-chip LC resonators were used instead of N-Path resonators. In other words, if negative resistors, implemented as cross-coupled transistor pairs, are added into both LC- and N-Path resonator based lters, then the N-Path lter would consume much less DC current while generating less noise compared with LC alternative (Fig. 3.16). Furthermore, CMOS technology scaling would facilitate synthesized lters with reduce power consumption and noise penalty for such negative resistance. 91 Figure 3.16: Comparing on-chip LC resonator versus on-chip N-Path resonator approaches towards constructing inte- grated recongurable RF BPFs. Schematic and simulation results for (a) LC prototype featuring inductors with Q = 10, with and without Q-boost (ideal bias tees not shown), and (b) N-Path prototype featuring inductors with Q = 10, 65nm CMOS transistors as switches, with and without Q-boost. 92 To fully utilize the capability of a CMOS transistor in terms of linearity, boot- strapping circuitry at gate terminals is used to guarantee the transistor is turned on by the CLK signals regardless of the source/drain voltage. The linearity of the N-Path schematic, however, in general, is limited by the OFF-level of CLK signals, which are often set to ground level (same level as bulk terminal). A large input signal can reduce the drain/source voltage well below the gate voltage and turn the transistor switch back on although it is not meant to be in the OFF state. Therefore, assuming the transistors' source/drain are DC biased at V DD =2 with the thresh- old voltage being V TH , the largest swing allowed at the drain of a CMOS switch is around V DD =2 + V TH . This is correctly predicted by 1-dB power compression point in Fig. 3.17, where a single N-Path resonator is put under the linearity test. The presence of the cross-coupled pair as negative resistance, though implemented using I/O 2.5V devices to allow a larger swing, slightly degrades the linearity of N-Path resonators, as shown also in Fig. 3.17. It is well worth noting that, some linearity-related gure-of-merit (FOM), such as out-of-band and in-band intermod- ulation test, are extrapolated from small-signal measurements and may not be able to predict sudden ON-OFF switching events. In fact, N-Path-resonator-based lter systems may have an input-referred 3rd-order interception point (IIP3) arrive later than what would be predicted as 10 dB away from an 1-dB power compression point for a typical 3rd-order nonlinear system. Such results have been reported previously [118][120]. 93 Figure 3.17: Simulated linearity performance of a single N-Path-resonator-based lter, with and without cross-coupled pairs as negative resistance. 94 To demonstrate the proposed lter synthesizing approach, a three-coupled N- Path-resonator-based dierential lter [128] has been fabricated in the TSMC 65nm CMOS technology (Fig. 3.18). The lter is fully dierential. Inductors are realized as spirals, and all capacitors are realized as a bank of switched-MIM-caps to enable lter tunability. To maintain the desired DC bias voltage of 0.5V across each N- Path lter and suppress the gain at even harmonics, complementary cross-coupled dierential pairs are used. 2.5V NMOS and PMOS I/O transistors are used for the cross-coupled pairs to allow larger voltage swings and, hence, to enhance system linearity. Binary-weighted arrays of complementary cross-coupled dierential pairs are employed to control the value of Q-boosting negative resistances to realize dierent lter responses. As mentioned before, the N-Path resonators are decoupled from each other and the rest of the circuitry by using inductors to avoid unwanted charge sharing. This isolation enables the use of capacitance-heavy ESD protection circuitry at the input and output of lters. Another advantage of the isolation is that it also removes the requirement for coherent operation of the multiple N-Path resonators. In other words, the relative phases between the clock signals fed to dierent N- Path resonators do not aect the lter response. To reduce the power consumption and layout challenges associated with routing multiple phases of a high frequency clock, the multiphase clock signals for each N-Path resonator are generated locally from master{slave clock dividers and are further expanded to larger swing by the 95 Figure 3.18: Schematic of the dierential N-path-based recongurable BPF prototype. 96 Figure 3.19: Clock generation for N-Path resonators. Figure 3.20: Simplied model for insertion loss and noise analysis around lter center frequency ! LO . bootstrapping circuitry similar to [130]. Figure 3.19 highlights the clock generation scheme and exemplary clock waveforms for N-Path resonators. 3.4.1 Insertion Loss and Noise Performance The noise gure of a passive lter is equal to its insertion loss. However, the noise gure of an N-path-resonator-based lter, irrespective of whether or not it includes a Q-boosting circuitry, is not necessarily equal to its insertion loss. Figure 3.20 shows a simplied noise equivalent schematic of the lter prototype around its 97 center frequency. To simplify the analysis, we assume all capacitor are ideal, and the eective parallel resistance of N-path resonators are completely cancelled by the Q-boosting circuitries. In other words, around the center frequency, all shunt paths are considered open circuit. Among all noise sources, the noise currents of Q-boosting circuitries (cross-coupled dierential pairs), represented asI n;Q A ,I n;Q B , andI n;Q C , dominate the noise generated by the loss of spiral inductors, represented asV n;R 1 , V n;R 2 , andV n;R 3 , and the noise of large CMOS switches. The eect of LO phase noise is also ignored [135]. The input impedance matching condition may be satised by choosing R L = R S , and (L 1 + L 2 + L 3 ) C 2 = 1=! 2 LO . Based on this simplied model, lter in-band insertion loss S 21 (! LO ) can be calculated as S 21 (! LO ) = 20log 10 2R S 2R S + R 1 + R 2 + R 3 : (3.8) The lter noise factor can then be expressed as F = 2 + R 1 + R 2 + R 3 R S + I n;Q A (R S + R 1 ) 2 + (! LO L 1 ) 2 4kT R S + I n;Q B (R S + R 1 + R 2 ) 2 + (! LO L 3 ) 2 4kT R S + I n;Q C (R S + R 1 + R 2 + R 3 ) 2 4kT R S : (3.9) 98 For example, for a lter centered at 1.0 GHz with R S = 50 , R 1 = R 2 = R 3 = 4 , L 1 = 5:0 nH, L 2 = 10:0 nH, and I n;Q A = I n;Q B = I n;Q C = 1:0 10 22 A=Hz 2 , the S 21 (! LO ) and NF is calculated to be {1.0 dB and 6.1 dB, respectively. Note that in (3.9), the rst term captures the noise contribution of load resistance that is assumed to be equal to source resistance in this implementation. The noise con- tribution of the source resistance can be dierent, and potentially smaller, if the source resistance is realized as an active circuitry. Overall, the output noise is dominated by the contribution of noise current of Q-boosting circuitries, which is inversely proportional to equivalent quality factor of N-Path resonators. As para- sitic capacitance due to CMOS transistors is the main cause of the deterioration of the lter resonator quality factor, CMOS technology scaling would facilitate synthesized lters with lower NF. 3.4.2 Large-Signal Performance The linearity of the lter is limited by the linearity of the CMOS switches which in turn is dictated by the voltage swing across each switch. The voltage swing across dierent resonators depend on the input frequency. Figure 3.21 shows the equivalent schematic and estimated relative voltage swings across the parallel resonators in two cases, namely, when the input signal frequency is equal to the clock frequency, ! LO , and when the input frequency is equal to one of the transmission zeros, ! TZ . To simplify the analysis, lossless coupling networks and perfect input and output 99 Figure 3.21: Simplied equivalent lter schematic at lter center frequency ! LO , and the lower-frequency transmission zero ! TZ . impedance matching conditions are assumed. For a lter with L 1 < L 2 in Fig. 3.21, input voltage with frequency at! LO enforces the largest voltage swing V BLO onto the resonator in the middle among others, while input voltage at frequency ! TZ only induces voltage swing V ATZ across the left-most resonator (in C-branch). The voltage swing ratio between V BLO and V ATZ can be expressed as V BLO V ATZ = j(j! LO L 2 + R S )(j! TZ L 1 + R S )! TZ Cj 2R S : (3.10) For example, for a lter with! LO = 875 MHz 2,! TZ = 835 MHz 2, R S = 50 , L 1 = 5:1 nH, L 2 = 10:1 nH, and C = 3:2 pF, the voltage swing ratio dened in (3.10) is around 0.71. One may prematurely conclude this less-than-unity ratio points to the ability of the lter to handle larger in-band than out-of-band input voltage swings. However, it is important to note that when the input frequency is ! LO , 100 Figure 3.22: Chip micro-photograph of the lter prototype. large voltage swings appear across all three parallel resonators. This is in contrast to the case where the input frequency is ! TZ , which primarily results in a large voltage swing across one of the resonators. Overall, the synthesized lter has a similar capacity to handle large input voltage from both in- and out-of-band. 3.5 Measurement Result and Comparison The prototype chip (Fig. 3.22) is packaged into a 24-pin 5mm-by-5mm QFN pack- age through wire-bonds. To facilitate single-ended measurements, two o-chip baluns are used at the input and output. The insertion loss due to the baluns, and PCB parasitics are de-embedded with the test PCB board measurement data based on the algorithm discussed in Appendix A. Measurement results in this paper are referred to the chip input and output. 101 Figure 3.23: Representative measured lter response with a 40 MHz bandwidth centered on f LO = 875 MHz. 3.5.1 S-Parameters (S 21 ; S 11 , and S 22 ) Figure 3.23 shows a representative measured lter frequency response with f LO = 875 MHz, passband bandwidth of 40 MHz, and transition band roll-o slope of 100 dB/100 MHz, with specic components values used. In this specic conguration, transmission zeros are placed at around 835 MHz and 910 MHz resulting in>17 dB and >19 dB blocker rejection at these two close-in frequencies, respectively. It is seen that the gain at the second harmonic is signicantly suppressed thanks to the dierential clocking scheme. Even higher second harmonic suppression, as indicated by the simulation results in Fig. 3.23 , could have been achieved if the symmetry were better maintained for the chip layout design. Measured in-band insertion loss S 21 (! LO ) deviates from (3.8) due to the N-Path resonators' nite quality factors despite the presence of negative resistance, as well as imperfect input impedance matching. 102 Figure 3.24: Representative measured lter shapes with bandwidth of 30, 40, and 50 MHz. To accommodate dierent ltering requirement, lter bandwidth and locations of transmission zeros can be tuned by changing discrete capacitor values and equiv- alent negative resistances. As shown in Fig. 3.24, tunable bandwidth from 30 to 50 MHz is achieved while maintaining roll-o slope >100 dB/100 MHz and in-band input/output return loss larger than 7 dB. Figure 3.25 demonstrates that the lter response with a bandwidth of 40 MHz, the roll-o slope of 100 dB/100 MHz, and return loss larger than 7 dB can be replicated across a wide spectrum from 800 MHz to 1.1 GHz. It is important to mention that maintaining a similar lter response at dierent center frequencies requires adjusting the values of tunable capacitors, as well as the value of Q-boosting negative resistances as the LO frequency changes. 103 Figure 3.25: Representative measured small signal S-parameters and group delay of lters with similar frequency response centered on dierent frequencies. 104 3.5.2 Noise Figure Figure 3.26 shows NF of the prototype lter as it is tuned from 800 MHz to 1.1 GHz with identical lter congurations indicated in Fig. 3.25. Measurements at frequencies extremely close tof LO are dicult to due to LO leakage. Atf LO = 875 MHz, {45 dBm LO leakage is observed in measurement, which can be mitigated by a more symmetric chip layout design. Large unwanted out-of-band signals, aka blockers, degrade the NF due to de- sensitization or reciprocal mixing with LO phase noise. Figure 3.27 shows the measured NF as a function of blocker power for 875 MHz LO-frequency while the blocker oset was 30 MHz. To ensure that the phase noise of the RF signal gener- ator that is used to create the blocker signal does not aect the measurements, a selective narrow-band SAW lter is placed at the blocker signal generator output. The measured NF degradation is only 0.3 dB for a 0-dBm blocker. Overall, the presence of strong blockers degrades NF mostly due to gain compression, other than LO phase noise, as the measured B 1dB = +6 dBm is close to where NF degrades by about 1 dB. 3.5.3 ICP 1dB ; B 1dB ; IIP2, and IIP3 Figure 3.28 shows the large-signal measurement results. For in-band linearity mea- surements, rst, a single tone at 864 MHz close to the middle of lter pass-band is used. The measured in-band 1-dB compression point is 7 dBm. Second, two 105 Figure 3.26: Representative measured NF of lters with similar frequency response centered on dierent frequencies. Filter congurations are the same as indicated in Fig. 3.25. Figure 3.27: Measured blocker NF (blocker frequency oset f = 30 MHz) for a lter response with a 40 MHz bandwidth centered on f LO = 875 MHz. 106 Figure 3.28: (a) ICP 1dB and IIP3 measurements for a lter response with a 40 MHz bandwidth centered on f LO = 875 MHz, (b) B 1dB and IIP3 measurements for a lter response with a 40 MHz bandwidth centered on f LO = 875 MHz, with dierent frequency oset f, and (c) IIP2 measurements. 107 in-band tones with 1 MHz frequency oset are used as inputs to the lter. The measured in-band IIP3 is 25 dBm. For out-of-band nonlinearity measurements, a blocker signal with varying frequency osets relative to the in-band tone is added. Note that the oset frequency of 30 MHz corresponds to the blocker frequency of 834 MHz, which is equal to the frequency of one of the transmission zeros in the lter transfer function. The blocker-induced 1-dB compression point is 9 dBm when the blocker signal is only 40 MHz away from the signal. In a two-tone test, when two out-of-band tones separated by 40 MHz are input to the lter, the measured out-of-band IIP3 is 24 dBm. Second-order non-linearity may cause in-band desensi- tization due to in-band or out-of-band interferences. IIP2 merely due to out-of-band interference is measured to be 37 dBm, as shown in Fig. 3.28(c). External narrow- band SAW lters are placed to the output of the signal generators to suppress the intrinsic second-order harmonics. In-band- and out-of-band-interference-induced second-order non-linearity has also been characterized as shown in Fig. 3.28(c), and the linearly-extrapolated second-order inter-modulation curve intercepts the in-band (f 1 =860 MHz) and out-of-band (f 2 =1724 MHz) curves when input power P IN is equal to 40 and 61 dBm, respectively. 3.5.4 Performance Comparison The performance summary and comparison with the state-of-the-art CMOS re- congurable RF ltering systems is shown in Table I. Compared with prior-art, 108 this work achieves simultaneous wide pass-band bandwidth and sharp roll-o slope across a wide spectrum while maintaining comparable NF, system linearity, and power consumption. 3.6 Conclusion and Recommendations for Future Work It is shown that N-Path resonators, emulating a second-order resonator close to the clock frequency, can be coupled using passive components to realize selective lter transfer functions with transmission zeros. It is further shown that the low quality factor of coupling passives (e.g., low-Q inductors) does not signicantly deteriorate the lter characteristics. The transfer function of these BPFs is tunable by a combination of clock frequency and capacitor values. The increase of insertion loss due to CMOS switch parasitics may be mitigated by introducing negative resistances at the expense of increased power consumption and noise. This work is another step towards possible replacement or augmentation of acoustic lters in recongurable RF transceivers. Discrete inductors are necessary for the wide passband bandwidth and close-by transimission zeros, however they limit the recongurability and tuning range of the lter. Replacement of such inductors would greatly improve the design agility and reduce the area cost. One possible approach is to introduce another frequency into 109 110 the system that denes the passband bandwidth, yet without aliasing out-of-band interference to in-band and pollute the signal. 111 Chapter 4 mm-Wave Mixer-First Receiver with Selective Passive Wideband Low-Pass Filtering 4.1 Introduction: Passive-mixer-rst receivers in mm-Wave frequency In principle, the lter synthesis methodology discussed in chapter 3 can applied on implementation of recongurable channel-select front-end lter at any given fre- quency. Since high-Q acoustic resonators are not available at mm-Wave frequencies, coupled-N-Path-resonator based tunable lters are likely to provide promising al- ternatives at the very front-end of mm-Wave receivers. However, as discussed in section 3.4, unwanted charge sharing among the branches of switched capacitors deteriorates the lter in-band response by eectively reducing the resonator quality factor. Furthermore, eqn. (3.7) reveals that the level of degradation of N-Path resonator's quality factor also depends on the clock frequency ! CLK . In fact, as 112 Figure 4.1: Eective quality factor of an N-Path resonator at dierent frequencies for dierent equivalent switch sizes. lter center frequency increases with clock frequency ! CLK , the unwanted charge sharing between C and C PAR further deteriorates the resonator quality factor. N- Path resonator may have Q less than 20 around 20 GHz, as shown in g. 4.1 if large switch sizes are chosen with large parasitic capacitance. On the other hand, smaller switches with large switch resistance reduce the out-of-band rejection. This trade-o between in-band and out-of-band lter characteristics puts a limit on N- Path-resonator based lter synthesis at mm-Wave frequencies [136]. To break the trade-o between in-band insertion loss and out-of-band rejec- tion associated with coupled-N-Path-resonator-based lters, alternative ltering schemes have to be considered. Re-visiting on the general principles of N-Path ltering while treating the array of switches as passive mixers reveals that the volt- age information stored on each capacitor contains the phase-interleaved frequency- down-converted input signal. Immediate placement of these passive mixers right after the receiving antennas characterizes this scheme as a \passive mixer rst" 113 Figure 4.2: Regular paasive mixer-rst receiver front-end. receiver front-end [42]. Mixer-rst receivers have had a signicant impact in the sub-6GHz frequency range, enabling exible reception and interference resilience. Attempts to push operating frequency into the millimeter-wave and 5G range for massive MIMO applications have been justied via the power eciency of passive mixers, which has been discussed with details in Chapter 2. Compared to the aforementioned N-Path lters, in a conventional mixer-rst scheme as shown in g. 4.2, additional resistors R L are loaded in parallel with capacitors to provide necessary input matching to the antenna. More importantly, unlike N-Path-resonator-based lters, the trade-o between in-band and out-of- band characteristics is no longer limited by technology parameters like f T . Specif- ically, at in-band close-to-clock frequency, the switch resistance R SW is in series with another resistor R L , and RF-to-base band(BB) gain increases with larger R L to R SW ratio. On the other hand, at out-of-band far-away-from-clock frequency, 114 the shunt capacitor C L with small impedance would bypass R L , so that the out- of-band gain(attenuation) can be further reduced by choosing large C L . Note that the dierence between in-band and out-of-band gain can be further increased by placing C L and R L into shunt path of an amplier. Higher-order all-pole RF-to-BB ltering through mixer-rst scheme can be achieved by synthesizing a higher order shunt impedance loaded to the amplier, and this impedance synthesis can be done either passively [120], or actively [137]. Trans- mission zeros can be added to the overall transfer function [133] by canceling the gain through shunt feedback and amplication path, though the actual location of transmission zeros are mathematically dicult to predict when parasitics of the amplication path is considered. 4.2 mm-Wave switched-complex-impedance based mixer-rst receiver To further extend the overall lter selectivity beyond amplier shunt-impedance synthesis, complex-impedance can be loaded to the output of the switching tran- sistors as mixers. An example of such complex impedance is a poly-phase RC structure put in front of a pair of parallel RC as shown in g. 4.3, whose ABCD characteristic matrix can be expressed as 115 Figure 4.3: Base-band poly-phase network schematic and voltage gain transfer function. 2 6 6 4 V IN I IN 3 7 7 5 = 1 1 +jsRC 2 6 6 4 1 +sCR R 2sC 1 +sCR 3 7 7 5 2 6 6 4 V OUT I OUT 3 7 7 5 : (4.1) Note that this ABCD matrix of eqn. (4.1) is only true when the quadrature input phase is guaranteed. Instead of separate impedance loaded to each mixer phase, a poly-phase mixer has a complex impedance loaded simultaneously to the quadrature-phase passive mixer. Under the quadrature condition, the output volt- age V OUT versus input current I IN gain G BB can be expressed as G BB (s) = V OUT I IN (s) = (1 +jsRC)R L s 2 R L C L RC +s(R L C L +RC + 2R L C) + 1 : (4.2) A signature feature of this network is that it contains an transmission-zero at fre- quency ! TZ = + 1 RC as shown in g. 4.3. This transmission zero can be ipped to 116 Figure 4.4: Analytical model for poly-phase mixer scheme. negative frequencies by exchanging R with C. Another useful parameter of this net- work is the equivalent complex input impedance Z BB dened as the ratio between V IN and I IN , and it can be calculated as Z BB (s) = V IN I IN (s) = R +R L +sRR L (C +C L ) s 2 R L C L RC +s(R L C L +RC + 2R L C) + 1 : (4.3) When a network as shown in g. 4.3 is loaded simultaneously to the quadrature- phase poly-phase mixer, such system is equivalent to a system where each mixer phase is loaded by a separate impedance Z BB (s) as shown in g. 4.4. Treating base-band impedance as separated Z BB (s), RF input impedance can be analyzed similarly to [117] whereZ BB (s) at dierent LO harmonics is folded to RF with cor- responding Fourier coecient. However, analysis in [117] ignores the sample-and- hold-region-induced parallel resistance (equal to R P of eqn. (3.1) at 1st-harmonic of clock frequency), and this resistance from various clocks harmonics are constants, and they can be derived using time-domain analysis. With this sample-and-hold 117 Figure 4.5: Representative analytical and simulated in-band input impedance of a poly-phase mixer for dierent R L . eect taken into account, poly-phase mixer input impedance at LO frequency can be calculated as Z IN (! LO ) 2 2 Z BB (0)jjR NP : (4.4) Here, R NP = 214 , and it is assumed that BB impedance Z BB (s) have negligible value at LO frequency, and this approximation is validated by comparing analytical predictions to spectre simulation shown in g. 4.5. Seen as the result of current division between source resistance R S and mixer input impedance, current owing to the mixer can also be calculated as well as 118 the BB voltage seen at the nal output. Hence, the gain from input voltage to base-band output voltage can be calculated as G(!) = 1 R NP (R NP +R S )Z MIX +R S R NP V BB (!! LO ) I BB (!! LO ) ; (4.5) where 1 = 0:225e j=4 , Z MIX is the harmonic-folding components of the mixer input impedance ignoring the sample-and-hold parameter R NP , and the BB gain V BB (!! LO ) I BB (!! LO ) has been given in eqn. (4.2). Eqn. (4.5) also reveals the fact that overall RF-to-BB tranfer function would have a transmission zero at ! LO +! TZ . When input frequency RF is very close to LO frequency, in-band gain can be expressed as G(! LO ) 1 R L R NP (R NP +R S )Z MIX (! LO ) +R S R NP ; (4.6) where Z MIX = 2 2 Z BB (0), and this equation is validated by Fig. 4.6. If C L = C, R L >>R, and 6R S >>R, 3-dB bandwidth of such system can also be calculated as BW 3dB 1 R S C (0:17 + 0:67R S R L ): (4.7) When the input RF frequency is extremely far away from LO frequency, the BB impedance is negligible, hence the gain from RF to BB can be extremely small. 119 Figure 4.6: Representative analytical and simulated in-band voltage gain of a poly- phase mixer for dierent R L . Particularly, when input frequency is a bit further away from the transmission zero, around ! LO + 2! TZ , the RF-to-BB gain is approximately equal to G(! LO + 2! TZ ) 1 R 2R S (3 + 2j) (4.8) when C L =C, and R L >>R. In a word, the major advantage of such system arises from the capability of rejecting high-level blocker close to transmission-zero frequency, however, this ad- vantage comes at a price of extra noise caused by introduction of R. Total noise at 120 the output are contributed by three noise sources: source resistance R S , transmis- sion zero resistance R, and load resistanceR L . The output noise power due to each of them is N OUT;R S = 4kT R S X n=0;1;2 j R S ==R NP (n! LO )R L n R S ==R NP (n! LO ) +Z MIX (n! LO ) j 2 ; (4.9) N OUT;R = 4kTRj R L R L +MR S +R j 2 ; (4.10) N OUT;R L = 4kT R L jR L ==(MR S +R)j 2 : (4.11) Input noise power due to R S is N OUT;R S = 4kT R S jZ MIX (! LO )==R S ==R NP j 2 ; (4.12) hence the noise factor of such system can be expressed as F = 4 1 (R L +R) R L 2 N OUT;R S +N OUT;R +N OUT;R L N IN;R S ; (4.13) and it is validated through g. (4.7). Eqn.(4.21) indicates that noise factor ratio between a poly-phase mixer and a regular RC-loaded mixer (R=0) is approximately F PolyPhase F RegularMixer (1 + R R L ) 2 , hence it is reasonable to choose smaller R over R L ratio to reduce additional noise beyond regular mixers. Fig. 4.8 shows representative characteristic response from a poly-phase mixer with ideal components, and they are put into comparison with a regular mixer with 121 Figure 4.7: Representative analytical and simulated in-band NF of a poly-phase mixer for dierent R L . R Poly =C Poly = 0. Note that all transfer functions shown in this gure are down- converted RF-to-BB tranfer function. Thanks to the transmission zero embedded in the single-ended transfer function S21 and the dierential transfer function S31, the poly-phase mixer has much more signicant blocker-tolerant/rejection capability. Due to the relatively small R Poly , within 300 MHz of BW 3dB , NF only degrades around 1.5 dB compared to the regular mixer counter part. Double-sided transmission zeros can be added to the transfer functions by cas- cading two RC stages with interchanged R and C. Dierential input switching scheme can also be employed to further suppress blocker content at the output due to DC of LO signals. Since the noise gure is dominated by the RC structure in front of the gm-cell, extra poly-phase RC structure can be placed at the output of the gm-cell, and this can further increase the overall blocker rejection capability at the output without much sacricing the NF. Fig. 4.9 demonstrates simulated 122 Figure 4.8: Simulated comparison between characteristic performance of poly-phase and regular mixer. 123 performance from a representative poly-phase mixer where practical gm-cells are assembled using 65nm CMOS technology are included to test the linearity of such system. When a blocker is placed at 32 GHz (1 GHz away from the transmission zero), the 1-dB compression point (B 1dB ) is 25.5 dBm, and this is a signicant improvement from a regular mixer from same technology with around 0 dBmB 1dB . The ltering transfer function can be shifted to dierent center frequencies by tun- ing the clock frequency, while a S11<-10 dB can be well maintained with the help of integrated matching network as shown in Fig. 4.10. 4.3 mm-Wave Mixer-First Receiver System Level Design and Trade-Os Mm-Wave mixer-rst receivers based on switched-complex-impedance discussed in section 4.2 provide a highly-desired attenuation to nearby blockers, but at the cost of narrow passband bandwidth due to the close-in transmission zeros. Modern lters or equivalent ltering mechanisms require exibility on both the passband bandwidth and attenuation level of nearby blockers for dierent applications, there- fore a more general type of lter transfer function synthesis is desired. Consider the cases where the load of a passive mixer is a generalized passive network. Transmission zeros in the mixer's passive load improve the selectivity and out-of-band rejection of the passive mixer-based receiver without sacricing This section is adopted from [110] 124 Figure 4.9: Poly-phase mixer with dierential input switching scheme, where cascaded RC stages are added to generate double-sided transmission zeros. 125 Figure 4.10: Poly-phase mixer with input matching network and double-sided transmission zeros centered at dierent frequencies. 126 Figure 4.11: Schematic and frequency response of a passive 3 rd -order elliptic LPF with dierent inductor quality factor Q L . linearity. As a special case, the mixer's passive load may be a third-order network realized as a doubly-terminatedCLCC -conguration with an elliptic transfer function. Representative simulated transfer functions of such a third-order elliptic lter for dierent values of inductor quality factor are shown in Fig. 4.11. Figure 4.11 indicates that such elliptic low-pass lter maintains its a high selectivity even 127 for modest inductor quality factor values of Q5. The lumped component values for this lter are derived from [138] C 1 = g 1 Z 0 BW ; (4.14) C 2 = g 2P Z 0 BW ; (4.15) L = g 2 Z 0 BW ; (4.16) where Z 0 is the termination impedance value, BW is the lter's pass-band band- width, and g 1 , g 2 , and g 2P are constants that depend on in-band ripple and out- of-band attenuation requirements. Given the large bandwidth of mm-wave sys- tems, the values of these components will be reasonable for on-chip implementation [139]. For instance, a third-order elliptic lter with an 800-MHz bandwidth requires L = 40:5nH, C 1 = 942:1fF , and C 2 = 120:0fF when terminated to Z 0 = 200 . It is well known that the low pass impedance of the passive mixer's load R L is frequency translated by the LO frequency at the RF port. The in-band input impedance of a quadrature mixer can be approximated as 2 2 R L [129][42]. The RF-to-baseband(BB) transfer function of the loaded passive mixer will have a high selectivity with the load's transmission zero appearing around the LO frequency referenced to the RF port (Fig. 4.12). The improved selectivity compared to the conventional passive mixers with single-pole RC lter load is clear, and an even 128 more advanced selectivity can be achieved by choosing higher order LPFs at the expense of extra insertion loss and design areas. Non-overlapping quatrature LO waveforms with 25-percent duty-cycle as indi- cated in Fig. 4.12 are highly desirable to maintain low insertion loss and NF [42], however at mm-wave frequencies they are dicult to generate due to the large bandwidth required at the gate of switching transistors [140]. Tunable-resonator- based LO circuitry [141][142] is typically used to reduce the power consumption per mixer at high frequencies, yet the narrow-band nature of these resonant cir- cuits means that the LO drive waveforms will be sinusoidal and mixers of adjacent phases might be on at the same time. Figure 4.13 shows adjacent phases of repre- sentative quadrature sinusoid waveforms V 1 and V 2 : V 1 = V 0 +V 0 cos (! LO t); (4.17) V 2 = V 0 +V 0 sin (! LO t); (4.18) whereV 0 is the sine-wave amplitude and! LO is the clock frequency. If the switches are assumed to be fully on when clocking waveforms rise beyond V turnON , then the overlapping time between adjacent clock phases 1 and 2 can be expressed as OL = 2 2cos 1 V turnON V 0 1 : (4.19) 129 Figure 4.12: Schematic and RF-to-BB frequency response of the proposed mixer- rst receiver with a 3 rd -order elliptic low-pass lter with ideal switches and dierent values for inductor Q L . 130 Figure 4.13: 1 and 2 of a representative quadrature sinusoid LO waveforms. For example, at 25 GHz, OL is about 6.6 ps for V 0 =0.75 V and V turnON =0.95 V. Note that in practiceV turnON is set by the bias voltage and threshold voltage of the switching transistors. Replacing the single-pole RC load with high-order elliptic lter as passive mixer load signicantly improves the attenuation to nearby out-of-band interferences as shown in Fig. 4.11. Nonetheless, at frequencies that are close to or far away from the LO frequency, the high-order passive elliptic lter provides a low-impedance path either directly through the inductor connecting the mixer output to the load resis- tanceR L , or through the capacitor in shunt withR L to the ground. Since both the in-band and far out-of-band characteristics of the elliptic-lter load mixer-rst re- ceiver is similar to a single-pole RC-loaded design, it is adequate and simpler in com- putation to study the system-level performance such as in-band input impedance, conversion gain, noise and linearity just based on the RC-loaded designs. A rep- resentative schematic of a RC-loaded quadrature mixer with sinusoidally-switched 131 Figure 4.14: (a) Representative schematic of a RC-loaded quadrature mixer with sinusoidally-switched CMOS transistors and input matching network, and (b) LTI model equivalent to (a). 132 CMOS transistors and its equivalent LTI model is given in Fig. 4.14. Here R SW and C SW are equivalent switch ON-resistance and capacitance, respectively. The shunt resistance R SH = K N R SW , with kernal K N modeling the power lost to harmonic re-radiation approximately equal to [42] K N = 4:3 1 + 1 R SW =R S + 16! LO R SW C SW : (4.20) R OL models the clock-phases overlapping eect, and it can be expressed as R OL = 12 R SW ! LO OL with OL being the equivalent overlapping time between adjacent clock phases given by Eqn. 4.19 for sinusoid clocking waveforms. Figure 4.15(a) compares the simulated input impedance of the quadrature pas- sive mixer shown in Fig. 4.14(a) with the analytical results based on the LTI equivalent model for dierent NMOS switch sizes and load resistance R L . Simu- lation and analytical results in Figure 4.15 are computed with the in-band input frequencyf RF =f LO =25 GHz, OL =6.6 ps,R L C L =1 ns, and all transistors based on 65nm CMOS technology. NMOS switches with larger width have smaller R SW and largerC SW , and as shown in Fig. 4.15(a), sizing of these switches NMOS tran- sistors aect the mixer input impedance to a slightly greater extent than the R L does when the latter is eectively in parallel with other shunt resistance including R SH and R OL . A L-section matching network with a series AC-coupling capacitor C MAT and a parallel inductor L MAT can be used to boost the real-part of the mixer input 133 Figure 4.15: Simulated and analytical performance of the quadrature passive mixer in Fig. 4.14: (a) mixer input impedanceZ mixer , (b) conversion gain, (c) NF, (d) out-of-band IIP3, and (e) estimated LO circuitory power consumption. 134 impedanceZ Mixer to match the desired 50- source resistance. Considering the ef- fect of input matching network, the simulated conversion gain for dierent switched transistor sizes and load resistance R L is summarized in Fig. 4.15(b), with ana- lytical results computed based on Fig. 4.14(b). Large R L and transistor with smaller C SW are preferred to maintain a relatively high shunt impedance and thus an acceptable conversion gain. The noise performance of the quadrature mixer with noise-less load can also be estimated based on the LTI model in Fig. 4.14(b). In other words, the quadra- ture mixer noise factor while ignoring the noise contribution from the load can be expressed approximately as [42] F = 1 + R SW R S 1 + R SW +R S R SW 1 K N + OL ! LO 12 : (4.21) Figure 4.15(c) shows that at the frequency of interest (25 GHz), the noise factor F is around 9 dB, and it is not a sensitive function of theR L or transistor size if the load noise is ignored. However, as suggested by Fig. 4.15(b), this mixer stage might have a conversion gain less than unity. When the noise-less loadR L is replaced by a noisy baseband circuitory with the same input impedance, its noise contribution would be \amplied" by the quadrature mixer stage and shows up in the overall noise gure. Figure 4.15(c) demonstrates the overall F with a noisy baseband circuitory with NF=3dB (measured with respect to a 50- source impedance) at the mixer load, and it can be observed that the design conguration with close-to-unity conversion 135 gain in Fig. 4.15(b) would bring less extra noise when the baseband circuitory noise is taken into account. Passive mixers are attractive candidates for mm-wave frequency converters mostly due to the superior linearity and power eciency. The out-of-band IIP3 of a quadrature mixer can be estimated as [42] IIP3 OOB = s 8 3 (1 +) 4 3 V OD 2 +V SAT 2 (1 +) ; (4.22) where =R SW =R S , and V OD and V SAT are the over-driving voltage and velocity- saturation voltages 65nm CMOS technology, respectively. Figure 4.15(d) shows that >20dBm of an out-of-band IIP3 can be obtained if transistors with 30m width are used as mixers. The quadrature passive mixers can be made more linear at the cost of an increased power consumption invested to the LO circuitory when large transistors with small ON-resistance R SW have to be switched on and o periodically, and this pair of design parameter trade-o is demonstrated in Fig. 4.15(d) and (e). For a resonator-based mixer driver as LO circuitory, the power consumption is approximately given as P LO =V DD V 0 (C SW +C Par )! LO Q RES ; (4.23) where V 0 is the amplitude of the LO waveform, and C Par is the capacitance ac- counting for the capacitive parasitic at the output node. C Par together in parallel 136 with theC SW form the eective capacitive load of the LO circuitory resonator with a quality factor Q RES . Taking into account the fact that the inductance L required in the elliptic base- band lter dened in Eqn. 4.16 is proportional to the Z 0 which is equal to the load resistance R L , these curves in Fig. 4.15 may suggest that a 30m switched transistor with R L around 100-Ohm yields the most reasonable trade-o between in-band conversion gain, noise, linearity, LO circuitory power and design area. Figure 4.16 summarizes the performance of a sinusoidally-driven quadrature mixers at dierent LO frequencies for NMOS width = 30 m and R L = 80 . The shunt capacitors C SW in Fig. 4.14(b) slightly degrades the conversion gain and noise performance at higher LO frequencies while the out-of-band IIP3 in Fig. 4.14(c) stays approximately unchanged when it is dictated mostly by the transistor properties. The LO circuitory power consumption, on the other hand, would rise with the LO frequency as sugguested in Eqn. 4.23 and displayed in Fig. 4.14(d). 4.4 CMOS Implementation A mm-wave receiver prototype [110], following the aforementioned scheme, is de- signed with the system-level schematic shown in Fig. 4.17. On the RF input side, an L-network formed by an on-chip spiral inductor and an on-chip capacitor pro- vides input impedance matching, AC coupling, and moderate electrostatic discharge 137 Figure 4.16: Simulated and analytical performance of the sinusoidally-driven quadrature passive mixer in Fig. 4.14 at dierent LO frequency for NMOS width = 30m andR L = 80 : (a) conversion gain, (c) NF, (d) out-of-band IIP3, and (d) estimated LO circuitory power consumption. 138 (ESD) protection. Based on trade-o between linearity, noise and power consump- tion covered in section 4.3, the CMOS transistor used as mixers are implemented as triple-well devices with 30m width each with the equivalent load resistanceR L of the LPF chosen as 87 . Baseband ampliers, with a bypass mode to facilitate large input signals, follow the receiver frontend to boost the gain when the signals are small. Baseband buers are included to enable measurements. Dierential LO signals are input to an on-chip wideband dierential quadrature hybrid to gener- ate 4-phase quadrature LO signals which are subsequently buered before feeding the gates of switching transistors (Fig. 4.18). The gate-to-source voltage of the mixer can be increased to reduce the equivalent switch resistance at the expense of degraded mixer linearity [132]. The 3 rd -order elliptic low-pass lter along with the input routing network is shown in Fig. 4.19. Each inductor is realized as a 3-metal-layer-stacked spiral [143]. Note that the two inductors are driven in a dierential manner by design, so that the total net magnetic eld is almost zero and so does the induced Eddie current in the surrounding ground. This dierential design enables compact foot- print without sacricing the quality factor. Equivalent shunt capacitance towards the mixer side are formed by discrete MIM capacitors and parasitic metal-to-metal fringing capacitance between inductor traces and nearby ground. The entire ellip- tic low-pass lter along with the routing network are co-designed and simulated in Ansys HFSS, with equivalent model shown in Fig. 4.19. The baseband low-noise 139 Figure 4.17: Schematic of the implemented mm-wave receiver. 140 Figure 4.18: Mixer-driver schematic. amplier with resistive feedback and cross-coupled neutralization capacitors (Fig. 4.20(a)) provides both resistive and capacitive load to the elliptic lter. Funda- mentally, the instantaneous bandwidth of the RF-to-BB conversion gain frequency response is limited by the passive low-pass lter design. As indicated in Fig. 4.19, the passive EM structure intentionally provides very little capacitance to the out- put load towards the baseband amplier side, such that more capacity are left to accommodate the equivalent input capacitance of baseband amplier which are large due to the high-g m transistors for suppressing the overall noise contribution. The equivalent input capacitance of the turned-ON baseband amplier, which is only partially neutralized by the cross-coupled capacitor pair due to stability con- cerns, is slightly larger than the capacitance when the amplier is OFF as shown in Fig. 4.20(b). Reducing the input capacitance by going for smaller transistors may reduce the limitation of the baseband amplier on the instantaneous bandwidth, 141 Figure 4.19: Layout and lumped equivalent model of the implemented elliptic low- pass lter. however it may come at the expense of increased noise gure given same DC power consumption. 4.5 Measurement Result and Comparison A proof-of-concept prototype chip has been fabricated in the TSMC 65nm CMOS technology (Fig. 4.21(a)), and is directly mounted on a printed circuit board (PCB) with conductive epoxy. The RF input, LO, and baseband pads are wire-bonded to 142 Figure 4.20: (a) Baseband amplier Schematic, and (b) simulated low-pass fre- quency response of the elliptic LPF and the baseband amplier. the PCB (Fig. 4.21(b)), routed using appropriate traces, and fed to edge connectors (Southwest, 1092-04A-6) for measurements. To facilitate single-ended measure- ments, surface-mount bias-tees (Marki, BT-0014SMG-2) and baluns (Marki,BAL- 0009SMG) are used at the baseband I/Q outputs. The wirebond inductances (500 pH) and the PCB traces are included in the impedance matching circuitries for the RF input and LO paths. Measurement results in this paper are referred to the PCB input and output, with the insertion loss due to the bias-tees, baluns, and PCB parasitics de-embedded based on the test PCB board measurement data. Figure 4.22 shows a representative measured receiver RF-to-BB frequency re- sponse as well as NF withf LO = 27 GHz. Set by the third-order passive elliptic lter, 143 Figure 4.21: Photos of (a) the silicon chip, and (b) test PCB. 144 Figure 4.22: Representative measured and simulated receiver (a) RF-to-BB fre- quency response, and (b) double-side band (DSB) NF at f LO =27 GHz with base- band amplier turned ON. 145 the response has an instantaneous baseband bandwidth around 0.5 GHz with a 49- dB stopband-to-passband rejection. Measured frequency response deviates from the simulation results due to to designer's misinterpretation of transistor model provided by the fabrication foundry. The deep N-wells of the triple-well NMOS transistors are wrongly connected to a low impedance ground, thus extra parasitic capacitance are introduced to source of switching transistors through bulk node. Since this extra parasitic capacitance is in parallel with the switch parasitic capac- itanceC SW in Fig. 4.14(b), it would reduce the kernal K N in Eqn. 4.20 and hence decrease the conversion gain and increase overall noise gure in a similar way to C SW . Figure 4.23 shows representative measured receiver conversion gain responses at dierent LO frequencies when the baseband amplier is turned ON or OFF (bypassed). The frequency range of the receiver front-end (-3 dB bandwidth), limited by the input impedance matching network at RF and LO path and the LO-path tuned mixer-drivers, is around 21.0 GHz to 29.0 GHz. When LO is far away from 25.0 GHz, the extra parasitic capacitance wrongly introduced by the bulk node cannot be fully resonated out by shunt inductance in the input matching network and it could dominate the mixer load, and hence limit the S11 to track LO frequency. Figure 4.24 shows the large-signal measurement results of the receiver withf LO = 29.0 GHz. For in-band linearity measurements, a single tone at 29.2 GHz close to 146 Figure 4.23: Representative measured receiver RF-to-BB frequency response and DSB NF with (a) baseband amplier turned ON, and (b) baseband amplier turned OFF. 147 Figure 4.24: ICP 1dB and B 1dB measurements for a RX response centered on f LO =29.0 GHz. the middle of receiver pass-band is placed. When the baseband amplier is turned on, the measured in-band 1-dB compression point ICP 1dB is -6 dBm, which is limited by the baseband amplier. Bypassing the amplier improves the ICP 1dB to 3 dB, and it is only limited by the DC-bias and voltage swing at the gate of switching transistors. In out-of band linearity measurements, a blocker signal with varying frequency osets relative to the in-band tone is added. With the baseband amplier turned ON or OFF, the receiver demonstrates similar tolerance to out- of-band blocker and this is because the passive elliptic LPF largely suppresses the blocker level before it reaches the baseband amplier stage. The blocker-induced 1-dB compression point B 1dB is about 3.4 dBm when the blocker signal is only 1 GHz away from the signal. At an increased oset frequency, the elliptic LPF 148 149 eectively short-circuits the source of the CMOS passive mixer, therefore the far- away blocker enforces a much relieved stress to the mixer compared to a close-in blocker. The receivers achieves higher than 6.5 dBm B 1dB when the blocker is 6 GHz away from the in-band signal. The performance summary and comparison with the state-of-the-art integrated mm-wave receivers is shown in Table I. Compared with prior-art, this work achieves simultaneous sharp roll-o slope across a wide spectrum, large out-of-band rejec- tion, and high dynamic-range while maintaining comparable NF, and power con- sumption. 4.6 Conclusion and Recommendations for Future Work This chapter demonstrates that single-input-single-output high-order passive l- ters or complex-impedance-based passive lters, instead of passive or active real- impedanceRC lters, may be used as the load of mm-wave passive mixers enabling more selective transfer functions across a wide frequency range without compro- mising linearity. This design approach may be suitable for fully digital mm-wave arrays. 150 Synthesis of arbitrary ltering transfer function using switched-complex-impedance- based mixer remains an open problem. Multiple switched transistors with system- atically staggered LO phase shifts, together with some active compensation network might help extend the transmission-zero limited passband bandwidth. When high- order passive lters are used as mixer load, low-loss and compact lter designs are vital but yet challenging for large-scale array systems. 151 Chapter 5 Wideband mm-Wave Phase Shifters Based on Constant-Impedance Tunable Transmission Lines 5.1 Introduction The upcoming 5G wireless communication standard is expected to exploit beam- forming at mm-wave frequencies to increase the overall wireless capacity [149][150]. Variable phase shifters and variable amplitude adjusters are the two main compo- nents of beam-formers. Passive variable phase shifters [29] are preferred over their active counterparts due to higher linearity, lower power consumption, and bidirec- tional response enabling their usage in both transmit and receive beam-forming paths. Millimeter-wave phase shifters should be wideband to support the channel This chapter is adopted from [37]. 152 Figure 5.1: Various phase shifter architectures. bandwidths that are required to support the high data rates of future wireless stan- dards. Finally, phase shifters should be compact to enable monolithic realization of large-scale mm-wave beam-forming transceivers. Figure 5.1 summarizes various common variable phase shifter architectures. Switched-type phase shifters in Fig. 5.1(a) contain multiple transmission-lines, which also be implemented as lumped LC units, and switching between each t- line can produce dierent true-time delay. This passive-only design consumes zero static power, and can be very wide-band. However, designs including multiple transmission-lines are very area-demanding. By tuning the impedance loaded to a quadrature hybrid in Fig. 5.1(b), various phase shift can be generated from input to output. Switch-capacitor bank is a good candidate for the tunable impedance unit, being both passive and compact. Unfortunately, quadrature hybrid itself may consume a lot of chip area. Vector modulators in Fig. 5.1(c) are widely used in 153 Figure 5.2: Hybrid MIMO architecture suitable for large-scale mm-wave arrays. CMOS phased array systems. Compact designs normally require active variable gain units and quadrature mixers, but they are not as linear as their passive alter- natives. Transmission lines with tunable eective inductance L and capacitance C, essentially absorb the phased array tunability into the routing network itself. This \dual-functioning" passive design can eectively save chip area. In large-scale monolithic mm-wave antenna arrays, especially those supporting multi-input multi-output (MIMO) schemes, the interconnect network connecting N antennas toB transceivers is a complexNB matrix constructed from on-chip transmission lines (Fig. 5.2). The beam-forming building blocks can be embedded within the same interconnect network. Specically, variable phase shifters may be constructed from the interconnect transmission lines (t-lines). The phase of a 154 propagating electromagnetic signal on a t-line may be modied by changing the propagation velocity which is a function of unit-length inductance and capacitance of the t-line. T-lines with adjustable unit-length capacitance have been used in impedance matching networks [151] or as phase shifters [152]. In [39], eective inductance and capacitance of a t-line are adjusted simultaneously to maintain a constant characteristic impedance while modifying the propagation velocity to realize a mm-wave phase shifter. This work presents a novel tunable t-line design, mimicking an inverted strip- line structure. Signal is routed in a lower metal layer sandwiched between oating structures. These oating structures are conditionally connected to global ground through switches to control the eective inductance and capacitance. Bringing down signal path from top to a lower metal layer enlarges the tuning range of both inductance and capacitance. Section 5.2 covers the operating principles and design guidelines of constant-impedance tunable t-lines. Section 5.3 summarizes the implementation and measurement results of prototype phase shifters based on constant-impedance tunable t-lines. To have an objective comparison, the perfor- mance of the proposed t-line is compared with that of a t-line based on [39] that is fabricated in the same process. Section 5.4 concludes the paper. 155 Figure 5.3: 3D view of a conventional tunable t-line featuring signal owing in top metal layer. 156 5.2 Constant-Impedance Tunable T-Lines Figure 5.3 demonstrates a conventional implementation of constant-impedance tun- able transmission lines [39]. According to their design methodology, signal is routed in top metal layer of a given technology, while locations of capacitive and inductive ground are determined by FET switches controlled by complementary voltages VB1 and VB2. When VB1 is OFF and VB2 is ON, the dark green meander metallic structure is connected to the global ground on two sides, and serves as the capaci- tive ground in this mode. Return currents, on the other hand, have no alternative routes but to ow back from sides. If we now turn o VB2 and switch on VB1, return currents see a closer path to ow back and they will take it. Now both capacitive and inductive ground lie in the light green rod shown at the bottom. Overall, compared to the mode described below, top mode has signal path closer to the capacitive ground while further to inductive ground. Therefore, qualitatively, we are safe to dene the top mode as \High-Beta Mode" with larger L and C. With careful design, characteristic impedance can be maintained, and dierence between beta generates the desired phase shift. Figure 5.4 illustrates cross-sections of a traditional constant-impedance tunable t-line, such as that in [39], under two congurations (low- and high-). Signal line is on a top metal layer, while the locations of capacitive ground (where electric eld ends) and inductive ground (where return current ows) are determined by FET switches controlled by complementary voltages VB1 and VB2. When VB1 is 157 Figure 5.4: Cross section of a conventional tunable t-line featuring signal owing in top metal layer. 158 OFF and VB2 is ON, the meander structure (denoted as \Patterned" in the gure) is connected to the global ground through VB2 as the capacitive ground, and thus the eective t-line capacitance is C ATR . Due to the fact that the \Patterned" structure is mostly orthogonal to signal route, return currents are forced to ow through global ground on two sides. Therefore, in this case, the inductive ground is the same as the global ground. On the other hand, when VB1 is ON and VB2 is OFF, capacitive ground is moved down to the \Float" structure, which reduces the eective t-line capacitance to C ATR C BTR = (C ATR +C BTR ). At the same time, this \Float" structure is now the inductive ground since it directs the return current. Intuitively speaking, since this "Float" structure is much closer to the signal line than to the global ground on the two sides, when VB1 is ON (and VB2 OFF), the eective t-line inductance is smaller than the other scenario when VB1 is OFF (and VB2 ON). Quantitatively, if we model the signal and return currents as currents bounded by two parallel wires, then the classic Neumann formula [153] allows to compare the eective t-line inductance of the two modes as L OFFTR L ONTR ln d R ln d 0 R ln (5+35)m 2:3m=2 ln 7:8m 2:3m=2 = 1:85; (5.1) where L ONTR and L OFFTR are eective inductances of this tunable t-line when VB1 value is set to ON and OFF, respectively,d andd 0 are distances between signal and return current paths in the two modes, and R is the estimated wire radius. 159 Here, we assume R is approximately equal to the signal line thickness. The eective t-line capacitance can be modeled as a parallel-plate capacitance so that C OFFTR C ONTR C ATR C ATR C BTR C ATR +C BTR 1=2 1:5m 1 (1:5+5:1)m = 2:20; (5.2) whereC ON;TR andC OFF;TR are the eective capacitances of this tunable t-line when VB1 value is set to ON and OFF, respectively. Note that eective overlapping area between the signal line and the \Patterned" structure is about half of the total area of the signal line. Given the ratios from equations (5.1) and (5.2) are close, it is safe to say that the characteristic impedance given by q L C remains nearly constant in the two modes as the propagation velocity given by 1 p LC changes. Furthermore, phase shift tuning range TR obtained from certain length,l, of this tunable t-line can be calculated as TR = ( OFFTR ONTR )l 0:50 OFFTR l = 0:50 OFFTR : (5.3) In our designs presented in this paper, the t-line structure width of 100 m is assumed. To fully exploit the ner lithographical resolutions of lower metal layers in stan- dard silicon processes and also vertically adjacent metal layers (Fig.5.5), we propose 160 Figure 5.5: Conventional and inverted t-line in a typical metal layers cross-section of a modern commercial CMOS technology. an alternative constant-impedance tunable t-line featuring an inverted strip-line structure as showin in Fig. 5.6. Two oating structures, which are conditionally connected to global ground through complementary switches, are placed above and underneath the signal route. Compared to the previous tunable t-line, (1) both oating structures are closer to the signal line, and (2) width of signal line is re- duced. Overall, the eective t-line capacitance and inductance are both increased compared to the previous case leading to a slower propagation velocity. In order to maintain a constant characteristic impedance, a \Z-Float" structure is designed to further increase the eective t-line inductance. Cross-section of the proposed t-line is shown in Fig. 5.7. 161 Figure 5.6: Proposed inverted t-line featuring signal owing in a lower metal layer. 162 Figure 5.7: Cross section of the proposed inverted t-line featuring signal owing in a lower metal layer. 163 The ratio of t-line eective capacitance in the two designs, when the VB1 is set to OFF mode, can be expressed as C OFFIV C OFFTR C AIV C ATR 6:5m=2 0:8m 10m=2 1:5m = 1:21: (5.4) The ratios of inverted tunable t-line inductance and capacitance between the two modes are L OFFIV L ONIV ln d 0 R ln d R ln 2 p 40 2 +4:2 2 m 0:6m ln 4:2m 0:6m = 2:52; (5.5) and C OFFIV C ONIV C AIV C BIV 1=2 0:8m 1=4 4:2m = 2:63; (5.6) respectively. Now, the phase shift tuning range of the proposed inverted strip-line tunable t-line IV can be calculated as IV = ( OFFIV ONIV )l = 0:61 OFFIV 0:61 OFFTR C OFFIV =C OFFTR = 0:74 OFFTR = 1:48 OFFTR : (5.7) 164 Figure 5.8: Chip microphotograph. The aforementioned rst-order analyses shows that proposed inverted strip-line tunable t-line has larger phase shift tuning range given the same design constraints such as a constant characteristic impedance, t-line width, and fabrication process compared with the prior such tunable t-lines. 5.3 Implementation and Measurement Results The two aforementioned constant-impedance tunable-transmission-line-based phase shifters are implemented in a 45nm CMOS SOI process (Fig. 5.8). T-line param- eters are extracted from the measured S-parameters and to get stand-alone per- formance of the t-line, HFSS simulated S-parameters of the pads are de-embedded from the measured S-parameters. 165 Figure 5.9: Measured characteristic impedance. Figure 5.10: Measured attenuation coecient . 166 Figure 5.11: Measured wavenumber . Figure 5.12: Measured equivalent group delay. 167 Figure 5.13: Measured equivalent transmission line inductance and capacitance. Figure 5.14: Measured large signal performance at 45 GHz. 168 Figure 5.9 conrms that the characteristic impedance of both tunable t-lines in both modes remain constant across a wide frequency range. Employment of thinner lower metal layer for the signal in the inverted strip-line-based design inevitably increases its attenuation per unit length as shown in Fig. 5.10. However, enhanced phase shift tuning range reduces the t-line length required to achieve the same phase shift target; hence, the overall transmission loss for the same total phase shift is lower in the proposed structure. Simulation and measurement results in Fig. 5.11 demonstrate that at 45 GHz, phase shifter that is based on the proposed tunable t- line has about 40% larger phase shift tuning range than the one based on previously- reported t-lines, and this number matches the analysis given by Eqn. (5.7). At 45 GHz, both phase shifters have similar phase shift tuning range; nevertheless, the proposed design takes up to only 65% area of the previously-reported design with about 1.0 dB lower insertion loss. Figure 5.12 demontrates the measured equivalent group delay. Fig. 5.13 highlights eective transmission line inductance and capacitance in both structures closely following the aforementioned rst-order analysis. As sugguest by the large-signal measurement results in Fig. 5.14 the phase shifters are quite linear, and should not come at a surprise when the entire design only consist of electromagnetic structures and transistors used as passive switches. Figure 5.15 summarizes measurement results from both phase shifters along with selected reported passive mm-wave phase shifters. Compared to the on-chip 169 Figure 5.15: Performance comparison of passive mm-wave phase shifters. reference phase shifter, this work is 35% more compact while maintaining other crucial performance parameters. 5.4 Conclusions Constant-impedance tunable t-lines enable realization of wide-band phase shifters for large-scale mm-wave monolithic beam-forming schemes. Available metal lay- ers of commercial silicon processes along with high-f t FET switches can be used judiciously to change the eective capacitance and inductance of on-chip t-lines to vary the propagation velocity without aecting the characteristic impedance. Proof-of-concept prototypes realized in a commercial CMOS SOI process verify the 170 eectiveness of the proposed inverted strip-line-based tunable transmission-line in comparison with previously-reported tunable t-lines. 171 Chapter 6 Conclusion and Recommendations for Future Work 6.1 Summary This thesis provides a study of RF and mm-Wave blocker-tolerant recongurable receiver systems. The contributions of this work include the development of original concepts and theoretical ndings, which are supported by several proof-of-concept integrated CMOS chips. Major performance trade-os of building blocks for large-scale mm-wave receiver arrays are summarized, with an emphasis on power consumption. In principle, un- der the same system-level requirement including linearity and sensitivity, DC power as a resource to any receiver architecture can be optimally distributed to the cor- responding receiver building blocks in an eort to achieve minimal overall power consumption. Optimal power consumption of various receiver and receiver-array 172 architectures consisting of aforementioned building blocks are compared. The ulti- mate architecture with optimal power eciency depends on signal and interference conditions, communication applications, the system scale as well as IC technology parameters. When not limited by the CMOS switch quality, recongurable and selective front-end bandpass lters can be critical to software-dened radios at RF frequen- cies. It is shown that N-Path resonators, emulating a second-order resonator close to the clock frequency, can be coupled using passive components to realize selective lter transfer functions with transmission zeros. It is further shown that the low quality factor of coupling passives (e.g., low-Q inductors) does not signicantly de- teriorate the lter characteristics. The transfer function of these BPFs is tunable by a combination of clock frequency and capacitor values. The increase of inser- tion loss due to CMOS switch parasitics may be mitigated by introducing negative resistances at the expense of increased power consumption and noise. This design approach is another step towards possible replacement or augmentation of acoustic lters in recongurable RF transceivers. Passive mixer-rst receivers are favored for their superiority in linearity and power eciency. It is demonstrated that single-input-single-output high-order pas- sive lters or complex-impedance-based passive lters, instead of passive or active real-impedance RC lters, may be used as the load of mm-wave passive mixers enabling more selective transfer functions across a wide frequency range without 173 compromising linearity. This design approach may be suitable for fully digital mm-wave arrays. Constant-impedance tunable t-lines enable realization of wide-band phase shifters for large-scale mm-wave monolithic beam-forming schemes. Available metal lay- ers of commercial silicon processes along with high-f t FET switches can be used judiciously to change the eective capacitance and inductance of on-chip t-lines to vary the propagation velocity without aecting the characteristic impedance. Proof-of-concept prototypes realized in a commercial CMOS SOI process verify the eectiveness of the proposed inverted strip-line-based tunable transmission-line in comparison with previously-reported tunable t-lines. 6.2 Recommendations for Future Work The analytical results highlighted in this Chapter 2 focus on performance down- conversion receivers, and the similar system-level calculation can be readily ex- panded to heterodyne receivers and its variations. Phase shifters and vector mod- ulators that can insert nearly true-time-delay between antenna path are vital for high-speed large-scale arrays, while their designs remains as challenging topics. Though the eect of power combining as well as LO distribution network is ignored in this chapter, wide-band low-loss and compact signal network, especially for a large-scale receiver array at mm-wave frequency can be challenging. Ultimately, the drive towards high-speed and low-power data converters and digital processors 174 are vital to fully open up the exibility and functionality of digital array architec- tures. Discrete inductors are necessary to the wide passband bandwidth and close-by transimission zeros of the lters discussed in Chapter 3, however they limit the recongurability and tuning range of the lter. Replacement of such inductors would greatly improve the design agility and reduce the area cost. One possible ap- proach is to introduce another frequency into the system that denes the passband bandwidth, yet without aliasing out-of-band interference to in-band and pollute the signal. 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Na- tional Bureau of Standards, pp. 301-344, 1908. 189 Appendix A Interconnect Parasitic De-Embedding The input and output voltage and current of a two-port network as shown in Fig. A.1 are linked by its corresponding ABCD matrix 2 6 6 4 V 1 I 1 3 7 7 5 = 2 6 6 4 A B C D 3 7 7 5 2 6 6 4 V 2 I 2 3 7 7 5 : (A.1) The ABCD matrix of any two-port network is unique and not a function of the properties of the testing source. Figure A.1: A two-port IO network. 190 Figure A.2: A IO complete network. Figure A.3: IO network Back-to-Back. Figure A.4: IO network Reversed. 191 Oftentimes in real lab measures, the DUT is only accessible to the external testing environment through some transitional IO networks such as on-chip pads and some necessary routing structures as in Fig.A.2. If the property such as the ABCD matrix of the IO networks is known, then their eects on the overall mea- sured results can be readily de-embedded to reveal the desired stand-alone DUT property. However, this rarely is the case, especially for custom designed on-chip IO networks for high-frequency transitions. One of the common method is to place test structures consisting of the duplicated transitional structure along with the main DUT on the same die, so that measurement on just the IO networks can be conducted. However, it is not straight forward to directly measure the IO network, since the side of the transitional network that directly connects the DUT is not accessible to the external environment. One of the indirect measurements of the IO network is based on measurements on a back-to-back IO conguration as shown in Fig. A.3, which consists of the reserved duplication of the IO network (Fig. A.4) connected directly to the original IO network. If the IO network is fully passive, thenADBC = 1, and the ABCD matrix of its reversed alternative can be expressed as 2 6 6 4 V 1 I 1 3 7 7 5 = 2 6 6 4 D B C A 3 7 7 5 2 6 6 4 V 2 I 2 3 7 7 5 : (A.2) The input and output of the back-to-back IO network are linked as 192 Figure A.5: IO network ZL Load. 2 6 6 4 V 1 I 1 3 7 7 5 = 2 6 6 4 A B C D 3 7 7 5 2 6 6 4 D B C A 3 7 7 5 2 6 6 4 V 2 I 2 3 7 7 5 = 2 6 6 4 AD +BC 2AB 2CD AD +BC 3 7 7 5 2 6 6 4 V 2 I 2 3 7 7 5 , 2 6 6 4 A TH B TH C TH D TH 3 7 7 5 2 6 6 4 V 2 I 2 3 7 7 5 ; (A.3) where A TH ;B TH ;C TH , and D TH are directly measurable quantities. Solving the eq. (A.3) reveals that AD = A TH + 1 2 ; (A.4) BC = A TH 1 2 ; (A.5) CD = C TH 2 ; (A.6) AB = B TH 2 : (A.7) 193 One more equation besides eq. (A.4) to eq. (A.7) is required to solve for A, B, C, and D, and it can be established based on measurements when a known xed impedance is loaded at the output of the IO network as shown in Fig. A.5. The measurable re ected scattering parameter S 11LD is S 11LD = A + B=Z L CZ L D A + B=Z L + CZ L + D : (A.8) Eq. (A.4) to eq. (A.7) and eq. (A.8) together uniquely determine the characteristic ABCD matrix of the IO network. Specically, A 2 = 1 2Z L (S 11LD + 1)(A TH + 1) 2 Z L (1 S 11LD )(A TH + 1)B TH (1 S 11LD )(A TH + 1) (S 11LD + 1)C TH Z L ; (A.9) B = B TH 2A ; (A.10) C = A C TH A TH + 1 ; (A.11) D = A TH + 1 2A : (A.12) In principle two possibleA P andA N exist as solutions, however it does not matter which one we choose because they would both lead to same DUT property after de- embedding the IO networks from same measured overall results. Note that though the load impedance Z L can be any known impedance, it can not be left as open or short circuit. For example, if Z L =1, eq. (A.8) becomes S11 L D =1 and it cannot generate another unique equation beyond eq. (A.4) to eq. (A.7). 194 Appendix B Eect of Buering Inductor on N-Path Filters As explained in Section.3.4, to reduce the unwanted charge sharing between passively- coupled N-path resonators, buering inductors L Buer may be used. The L Buer value should be large enough to suppress the unwanted charge sharing, but not too large to modify the desired frequency response. Figure B.1 shows the simulated frequency responses of coupled-resonator-based BPFs that include a transmission zero at the left-side of the pass-band. Results corresponding to LC- and N-path resonators-based lters, with dierent L Buer values, are shown. In this example, the simulated plots suggest that L Buer 5 nH is appropriate. In the implemented lter prototype, an initial value of L Buer = 5 nH is assumed; computer optimization is then used to nalize the value of each L Buer (Fig. 3.18). 195 Figure B.1: Eect of buering inductor L Buer on coupled-N-Path-resonator based lters. 196

Abstract (if available)

Abstract A selective receiver front-end whose frequency response can be tuned is highly desirable to substantially attenuate the interference before it reaches more vulnerable circuit blocks. However, compact, low-loss, linear, selective, and reconfigurable designs have been difficult to implement especially in a CMOS platform, where the passive components have low-quality factors. This thesis presents innovative integrated solutions, from both system level and circuit level, to the implementation of such reconfigurable interference-tolerant receivers at RF and mm-wave frequencies. ❧ Given characteristic of the available receiver building blocks, receivers and receiver-array architectures can be compared to each other with their major performance parameters optimized under the same system-level requirement. The ultimate architecture with optimal resource efficiency depends on signal and interference conditions, communication applications, the system scale as well as IC technology parameters, and a detailed analysis is presented in this thesis. ❧ At RF frequencies, it is shown that N-path resonators, emulating a second-order resonator close to the clock frequency, can be coupled using passive components to synthesize tunable selective RF filter transfer functions. A general filter synthesizing methodology as well as CMOS design trade-offs are discussed. ❧ At millimeter-wave frequencies when the N-path resonators' quality factor is limited by CMOS switch quality, a receiver front-end with selective transfer functions across a wide frequency range can be implemented based on mixer-first schemes. Higher-order passive low-pass filter networks can be placed at the mixer output to significantly enhance the attenuation to the out-of-band inference, with an acceptable design-area-associated cost at mm-wave frequencies. ❧ Finally, compact RF phase shifters with high linearity and wide bandwidth are highly desired, and inverted tunable transmission-lines can be implemented as wideband phase shifters for large-scale mm-wave monolithic beam-forming schemes.

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Asset Metadata

Creator Song, Pingyue (author)

Core Title RF and mm-wave blocker-tolerant reconfigurable receiver front-ends

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 11/01/2020

Defense Date 10/06/2020

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag block-tolerant circuit,CMOS,integrated circuit,millimeter-wave,OAI-PMH Harvest,radiofrequency,reconfigurable circuit,wireless receiver

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Hashemi, Hossein (committee chair), Chen, Mike Shuo-wei (committee member), Prata, Aluizio (committee member), Ravichandran, Jayakanth (committee member)

Creator Email davidsongusc@gmail.com,pingyues@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c89-388115

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