Close
About
FAQ
Home
Collections
Login
USC Login
Register
0
Selected
Invert selection
Deselect all
Deselect all
Click here to refresh results
Click here to refresh results
USC
/
Digital Library
/
University of Southern California Dissertations and Theses
/
Low-power, dual sampling-rate, shared-architecture ADC for implantable biomedical systems
(USC Thesis Other)
Low-power, dual sampling-rate, shared-architecture ADC for implantable biomedical systems
PDF
Download
Share
Open document
Flip pages
Contact Us
Contact Us
Copy asset link
Request this asset
Transcript (if available)
Content
Copyright 2019 Kiran K. Gururaj
LOW-POWER, DUAL SAMPLING-RATE, SHARED-
ARCHITECTURE ADC FOR IMPLANTABLE BIOMEDICAL
SYSTEMS
by
Kiran K. Gururaj
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
May 2019
ii
The dissertation of Kiran K. Gururaj is approved:
12/10/2018
Prof. Bindu Madhavan (Chair) Date
12/10/2018
Prof. Aluizio Prata (Co-Chair) Date
12/10/2018
Prof. Shuo-Wei (Mike) Chen Date
12/10/2018
Prof. James Moore Date
University of Southern California, Los Angeles
Committee members’ signatures are on file.
Contact the USC library for more information.
iii
Dedication
To my parents and the almighty
iv
Acknowledgements
First and foremost, I express my deepest gratitude to the late Prof. Choma,
who had been instrumental in shaping up my PhD program. Right from the beginning of my long
journey in pursuit of a doctoral degree, he had been a true inspiration and an invaluable source of
knowledge. I certainly miss him and his guidance. It is a great loss, and I am deeply indebted to
him for all the help and advice.
I thank Prof. Edward Lee, who was my first co-advisor at USC, along with the
late Prof. Choma. Prof. Lee’s guidance helped me navigate my course work, and my screening
exam.
I thank my qualifying and defense committee: Prof. Aluizio Prata, Prof. James Moore,
Prof. Mike Chen, and Prof. Vasilis Marmarelis, for their support, time, and advice.
My colleagues at Boston Scientific: Mr. Tim White, Mr. Goran Marnfeldt,
Mr. David Wagenbach, Dr. Pujitha Weerakoon, Mr. Emanuel Feldman, Ms. May Cheng,
Ms. Sara Bilow, and Dr. Vahagn Hokhikyan - I thank them for their encouragement, and help.
Words are not enough to thank my advisor Prof. Bindu Madhavan, who has been a
Godsend mentor. I can say with utmost certainty that I would have discontinued my pursuit had I
not found Prof. Madhavan. He has been a great teacher and a terrific guide. His teachings will
always be remembered and applied to advance my career, and life in general. I also admire and
appreciate the fact that he always kept his responsibility towards my graduation, no matter how
much life has changed around him. I greatly appreciate his teaching, insight, guidance, supervision,
and assistance over the course of my dissertation research.
Finally, my family and I dedicate this doctoral dissertation to them. They have given me the
strength, support, and motivation to see this through.
v
Table of Contents
Dedication …...………..……………………………………………………………… iii
Acknowledgements ….……………………………………………………………… iv
List of Figures ….…………………………………………………………………….. ix
List of Tables ………………………………………………………………..………. xii
Abstract ………………………………………………………………………....…… xiv
Dissertation Organization …………………………………………………...…… xvi
1 Introduction ................................................................................................... 1
The Spinal Cord Stimulator implantable biomedical system .............................................. 4
The Deep Brain Stimulator implantable biomedical system ............................................... 5
Reported closed-loop solutions for implantable systems ................................................... 6
ADC requirements for multi-channel closed-loop SCS and DBS implantable systems ..... 8
1.4.1 ADC specifications to sense Local Field Potentials ................................................... 9
1.4.2 ADC specifications to sense Extra-Cellular Neural Action-Potentials ..................... 11
1.4.3 ADC specifications to sense Evoked Compound Action-Potentials ........................ 12
1.4.4 ADC resolution determination based on the effects of the ETI ............................... 13
1.4.5 ADC Sampling-Rate Needed for Multi-Channel Neural-Sensing and Spike-Sorting15
Analog to Digital converter choices .................................................................................. 19
Dissertation Research Question ....................................................................................... 21
Hypothesis ........................................................................................................................ 22
2 Literature Survey on ADCs ........................................................................ 25
Contributions to the ADC Architecture ............................................................................. 26
Contributions to the ADC Specifications .......................................................................... 27
Contributions to the ADC design that are circuit specific ................................................. 29
Contributions of this Research Work ................................................................................ 29
3 The SAR-A ADC Architecture .................................................................... 30
SAR-A ADC architecture highlights .................................................................................. 32
Combining the two ADC architectures ............................................................................. 32
Re-using the analog circuit-blocks to save implementation-area ..................................... 32
vi
4 The SAR-A ADC circuit design .................................................................. 33
SAR ADC mode of the SAR-A ADC ................................................................................. 33
Algorithmic ADC mode of the SAR-A ADC ...................................................................... 36
Design challenges implementing the SAR-A ADC architecture ....................................... 38
4.3.1 Sub-threshold drain-to-source leakage current of the SAR ADC’s internal C-DAC
affecting the quantization error of the SAR ADC mode ........................................... 38
4.3.2 Comparator design challenges affecting the SAR and the Algorithmic ADC modes’
performance ............................................................................................................. 40
4.3.3 Charge-sharing between the multiply-by-2 and the comparator block in the
Algorithmic ADC affecting the quantization error of the Algorithmic ADC mode ..... 43
4.3.4 The effects of input-referred DC-offset, mismatch and 1/f noise contribution on the
SAR and the Algorithmic ADC modes ..................................................................... 43
5 Measurement Results ................................................................................. 46
Physical design of the SAR-A ADC in CMOS XFAB XH018 process .............................. 46
Testing the SAR-A ADC ................................................................................................... 50
Measurement Setup to Characterize the SAR-A ADC ..................................................... 54
Organization of the test result sections ............................................................................ 55
Testing the SAR-A ADC for Static Errors ......................................................................... 56
Static Error Measurement Results of the SAR ADC mode ................................................... 57
Static Error Measurement Results of the Algorithmic ADC mode .................................... 59
Potential causes for the gap in measured results versus the target specifications for the
Algorithmic ADC ............................................................................................................... 63
5.8.1 Effects of Clock Jitter on the Algorithmic DC performance ...................................... 63
5.8.2 Effects of Substrate noise injection onto the Algorithmic ADC front-end ................ 64
5.8.3 Effects of improper Reference Current Calibration .................................................. 65
5.8.4 Mismatch in the current mirror that sets the bias-current for the Algorithmic ADC . 67
Lack of the effect of the current mirror mismatch on the SAR ADC performance ........... 69
Testing the SAR-A ADC for Dynamic Errors ..................................................................... 70
5.10.1 Single-Tone transient testing using Sinewave fitting and FFT spectral analysis..... 70
5.10.2 Transient test setup and measurement results of the SAR ADC mode ....................... 71
5.10.3 Transient test setup and measurement results of the Algorithmic ADC mode ............. 73
Two-tone testing to compute intermodulation distortion (IMD) of the SAR-A ADC ........................ 75
5.11.1 Procedure for the two tone IMD testing ....................................................................... 75
5.11.2 Test setup and IMD measurement results of the two-tone testing for the SAR ADC mode
................................................................................................................................. 75
5.11.3 Test setup and IMD measurement results of the two-tone testing for the Algorithmic ADC
mode ........................................................................................................................ 77
Measured performance summary of the SAR-A ADC ...................................................... 80
vii
6 Architecture feasibility and Technology Scaling ..................................... 82
Implementing a standalone, dual sampling-rate SAR ADC in 180 nm CMOS process to
achieve all target specifications ........................................................................................ 82
Implementing a standalone, dual sampling-rate Algorithmic ADC in 180 nm CMOS process
to achieve all target specifications .................................................................................... 83
Technology scaling of the proposed shared-architecture, dual sampling-rate SAR-A ADC
and comparison with the standalone SAR ADC (optimized for the higher sampling-speed
of 5 MSa/s) to achieve all target specifications ................................................................ 85
6.3.1 SARA-A ADC scaling in terms of the power-dissipation .......................................... 86
6.3.2 SAR-A ADC scaling in implementation-area ........................................................... 88
6.3.3 Power-dissipation comparison between the scaled SAR-A ADC and a standalone
SAR ADC designed to achieve target specifications for CMOS process-technology
nodes with minimum feature-size less than 130 nm ................................................ 90
6.3.3.1 Compare the power-dissipation of the scaled, shared-architecture SAR-A ADC
operating in low-speed mode (100 kSa/s) with that of a standalone 5 MSa/s single
SAR ADC that has been designed for optimal operation at 5 MSa/s, operating at
100 kSa/s ............................................................................................................. 90
6.3.3.2 Compare the power-dissipation of the scaled SAR-A ADC in high-speed mode
(5 MSa/s) with that of a 5 MSa/s standalone single SAR ADC at 5 MSa/s ......... 92
6.3.4 Implementation-area scaling comparison between the scaled SAR-A ADC and a
standalone SAR ADC designed to achieve target specifications up to 5 MSa/s for
CMOS process-technology nodes with minimum feature-size less than 130 nm ... 93
Technology scaling of the proposed shared-architecture, dual sampling-rate SAR-A ADC
to achieve all target specifications .................................................................................... 94
Future work: Scaling the proposed shared-architecture, dual sampling-rate SAR-A ADC to
sub-40 nm CMOS process-technology............................................................................. 98
7 Dissertation Summary ................................................................................ 99
8 References................................................................................................. 101
9 Appendix A – Internal Digital-to-Analog Converter (C-DAC) design for the
SAR ADC .................................................................................................... 110
Analysis to compute unit capacitance of the C-DAC based on the input-referred kBT/C
noise, capacitor-mismatch and settling-time requirements ............................................ 114
9.1.1 Input-referred kBT/C noise requirements ............................................................... 114
9.1.2 Capacitor-mismatch requirements ......................................................................... 114
9.1.3 C-DAC Settling-time requirements ........................................................................ 115
Sub-Threshold drain-to-source leakage current in the C-DAC ...................................... 118
10 Appendix B – Shared Comparator design for the SAR-A ADC ............. 123
Architecture of the comparator ................................................................................... 123
10.1.1 Comparator Design Methodology .......................................................................... 127
10.1.2 Small Signal Analysis of the Comparator .............................................................. 129
10.1.3 DC Simulations of the comparator ......................................................................... 135
viii
10.1.4 Impedance calculation looking up from the drain of the tail current source transistor
in the comparator ................................................................................................... 137
11 Appendix C – Effects of mismatch, input-referred DC-offset and 1/f noise
contributions ............................................................................................. 142
Offset Cancellation Techniques ................................................................................. 145
11.1.1 Overview of the techniques for offset cancellation ................................................ 145
11.1.2 Auto Zero (AZ) offset cancellation technique ........................................................ 145
11.1.3 Correlated Double Sampling (CDS) offset cancellation technique ........................ 146
11.1.4 Chopper Stabilization (CHS) offset cancellation technique ................................... 146
11.1.5 Comparison of the three techniques discussed above .......................................... 147
Analytical determination of the input-referred offset-voltage and validation via HSpice
Monte-Carlo simulations............................................................................................. 148
11.2.1 Input-referred offset-voltage expression for differential amplifier with Resistive load .
............................................................................................................................... 148
11.2.1.1 Hand calculations and Hspice simulation setup to validate the derivations and
hand calculations .......................................................................................... 151
11.2.2 Input-referred offset voltage expression for differential amplifier with PMOS current
mirror load .............................................................................................................. 152
11.2.2.1 Hand calculations and Hspice simulation setup to validate the derivations and
hand calculations .......................................................................................... 155
11.2.3 Input-referred offset voltage expression for NMOS-PMOS cross-coupled pair
transistors .............................................................................................................. 157
11.2.3.1 Input-referred offset voltage expression for NMOS-PMOS cross-coupled pair
transistors with common-source input transistors ......................................... 159
11.2.4 Input-referred offset-voltage expression for clocked-comparator .......................... 163
11.2.4.1 Hand calculations and Hspice simulation setup to validate the derivations and
hand calculations .......................................................................................... 167
1/f noise contribution reduction techniques ............................................................... 169
11.3.1 CDS technique for reducing the 1/f noise contribution .......................................... 170
11.3.2 Chopper Stabilization (CHS) technique for reducing the 1/f noise contribution .... 171
Choice of the technique to compensate for the comparator mismatch, input-referred DC-
offset and 1/f noise contributions ............................................................................... 172
12 Reference Appendix .................................................................................. 173
ix
List of Figures
Figure 1-1: Block diagram of a typical biomedical system (sensing chain) ..................................... 3
Figure 1-2: Spinal Cord Stimulator Implantable Pulse Generator intercepting the pain signals. ..... 4
Figure 1-3: Implanted Deep Brain Stimulator. .................................................................................. 5
Figure 1-4: A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way
wireless telemetry for the treatment of neurological disorders [70]. ....................... 7
Figure 1-5: Architectural block diagram of a Medtronic Corporation’s Deep Brain Stimulator (DBS)
Implantable Pulse Generator (IPG) [23]. ................................................................. 8
Figure 1-6: Frequency band of interest for the LFPs. .................................................................... 10
Figure 1-7: Extra-Cellular Neural Action-Potentials [9] .................................................................. 11
Figure 1-8: Experimental setup to understand the effects of the ETI on the sensed-signals. ....... 14
Figure 1-9: Measured signal quality of the differential response through the ETI. ........................ 14
Figure 1-10: ADC sampling-rate requirements based on the neural-signal bandwidth and the AAF
requirements. ........................................................................................................ 17
Figure 1-11: 10-12-bit SAR ADC implementations in literature. .................................................... 20
Figure 1-12: 10-12-bit Algorithmic ADC implementations in literature. .......................................... 21
Figure 3-1: High-level block diagram of the SAR-A ADC showing the input and output signals. .. 30
Figure 3-2: Architectural block diagram of the SAR-A ADC........................................................... 30
Figure 4-1: Architectural block diagram of the SAR ADC mode of the SAR-A ADC. .................... 33
Figure 4-2: Block diagram of the Successive Approximation Register Analog to Digital Converter.
.............................................................................................................................. 34
Figure 4-3: Detailed schematics of the C-DAC and the comparator sub-blocks in the SAR ADC. 34
Figure 4-4: Architectural block diagram of the Algorithmic ADC mode of the SAR-A ADC. .......... 37
Figure 4-5: Schematic representation of the Algorithmic ADC with the designed shared comparator.
.............................................................................................................................. 38
Figure 4-6: Chopper-Stabilization technique on the designed shared comparator. ...................... 45
Figure 5-1: Die Micrograph of the SAR-A ADC chip showing various core modules. ................... 46
Figure 5-2: (a) Example layout of a stacked and inter-digitated MOM capacitor formed by Metal-1
through Metal-5 layers, with terminals T1 and T2. (b) Example of abutting two
copies of the MOM capacitor-cell layout in (a) to realize a capacitor-cell with twice
the capacitance of that in (a). ................................................................................ 48
Figure 5-3: SAR ADC’s internal C-DAC array floorplan. ................................................................ 49
Figure 5-4: Ideal transfer characteristic of an Analog to Digital Converter. ................................... 51
Figure 5-5: Transfer characteristic of the measured ADC showing the offset, gain and full-scale
errors when compared with the transfer function of the ideal ADC [98]. .............. 51
Figure 5-6: Power spectrum of the ADC output [93]. ..................................................................... 52
Figure 5-7: Second and Third order IMD products for a two-tone input signal to the ADC [99]. ... 54
Figure 5-8: Characterization test setup for the SAR-A ADC. ......................................................... 55
x
Figure 5-9: SAR ADC mode static errors test setup. ..................................................................... 57
Figure 5-10: Measured DNL/INL plots of the SAR ADC mode of the SARA ADC at 100 kSa/s at
37 °C, with AVDD = 1.8 V, DVDD = 1.8 V and bias-current = 1 µA...................... 58
Figure 5-11: Measured DNL of the SAR ADC mode across all the available five chips. ............... 59
Figure 5-12: SAR ADC mode’s measured maximum DNL variation measured across five chips. 59
Figure 5-13: Algorithmic ADC mode static errors test setup. ......................................................... 60
Figure 5-14: Measured INL/DNL plots of the Algorithmic ADC mode of the SARA ADC at 5 MSa/s
with AVDD = 1.8 V, DVDD = 1.8 V and bias-current = 40 µA. .............................. 61
Figure 5-15: Measured DNL of the Algorithmic ADC mode across the three chips. ..................... 62
Figure 5-16: Algorithmic DC mode’s measured maximum DNL variation measured across three
chips. ..................................................................................................................... 62
Figure 5-17: SAR ADC mode dynamic errors test setup. .............................................................. 71
Figure 5-18: FFT of the measured SAR ADC output at 100 kSa/s with 9.985 kHz sine input tone.
.............................................................................................................................. 72
Figure 5-19: Measured dynamic performance of the 100 kSa/s SAR ADC for a single-tone input.
.............................................................................................................................. 72
Figure 5-20: Algorithmic ADC mode dynamic errors test setup. .................................................... 73
Figure 5-21: FFT of the measured Algorithmic ADC output at 5 MSa/s with 499.25 kHz sine input
tone. ...................................................................................................................... 74
Figure 5-22: Measured dynamic performance of the 5 MSa/s Algorithmic ADC for a single-tone
input. ...................................................................................................................... 74
Figure 5-23: Measurement setup for the two-tone IMD testing of the SAR-A ADC. ...................... 75
Figure 5-24: FFT of the measured SAR ADC output at 100 kSa/s for a two-tone input. ............... 76
Figure 5-25: FFT of the measured Algorithmic ADC output at 5 MSa/s for a two-tone input. ....... 78
Figure 5-26: Two-Tone IMD Mean Dynamic Range vs Input-Power level for the SAR ADC mode,
measured on three chips. ...................................................................................... 79
Figure 5-27: Two-Tone IMD Mean Dynamic Range vs Input-Power level for the Algorithmic ADC
mode, measured on three chips. .......................................................................... 80
Figure 6-1: FFT of the measured Algorithmic ADC output sampling at 100 kSa/s with a 9.985 kHz
input tone............................................................................................................... 84
Figure 9-1: Functional schematic of a 12-Bit Digital-to-Analog Converter using the capacitor divider
approach. ............................................................................................................ 112
Figure 9-2: Equivalent Circuit of Figure 9-1. ............................................................................... 113
Figure 9-3: Functional schematic of an NMOS transistor switch for SDSL current estimation.... 119
Figure 9-4: SDSL current for varying Vdrain shown in Figure 9-3 at junction temperature = 80ºC.
............................................................................................................................ 120
Figure 10-1: Ideal transfer characteristic of a comparator. .......................................................... 123
Figure 10-2: Transfer characteristic of a comparator with finite gain. .......................................... 123
Figure 10-3: Block diagram of the comparator. ............................................................................ 125
Figure 10-4: Full schematic circuit diagram of a clocked-comparator. ........................................ 126
xi
Figure 10-5: Cross-Couple inverter pair (a) Transistor-level representation (b) Transistor small-
signal equivalent representation. ........................................................................ 130
Figure 10-6: Cross-Coupled inverter pair with input transistors (a) Transistor-level representation
(b) Transistor small-signal half-circuit equivalent representation........................ 131
Figure 10-7: Latch-based clocked-comparator (a) Transistor-level (b) small-signal half-circuit
equivalent representation. ................................................................................... 134
Figure 10-8: DC transfer characteristics of the latch-based clocked-comparator circuit shown in
Figure 10-4. ........................................................................................................ 136
Figure 10-9: DC Gain of the latch-based clocked-comparator circuit shown in Figure 10-4. ..... 136
Figure 10-10: Computation of small-signal gain shown in Equation (80). .................................. 137
Figure 10-11: Comparator half-circuit representation for impedance calculation. ....................... 140
Figure 10-12: Circuit to small-signal representation for deriving an expression for Zin. ............... 140
Figure 10-13: Circuit to small-signal representation for deriving an expression for the impedance
looking up from node “a” shown in Figure 10-4. ................................................ 141
Figure 10-14: Impedance looking up from node “a” of the comparator shown in Figure 10-4. ... 141
Figure 11-1: Transient simulations of the comparator output without mismatch effects for tm,
ws and wp corners at Tj= 80 °C. ......................................................................... 143
Figure 11-2: Transient simulations of the comparator output with mismatch effects (modeled as
input-referred offset-voltage = 1 mV) for tm, ws and wp corners at junction
temperature Tj = 80°C. ........................................................................................ 144
Figure 11-3: Functional block diagram of an Auto-zeroing offset cancellation technique. .......... 145
Figure 11-4: Functional block diagram of a CHS offset cancellation technique [122]. ................ 146
Figure 11-5: Functional Circuit schematic of a differential amplifier with resistive load for deriving
the expression for standard deviation of input-referred offset voltage Vos .......... 148
Figure 11-6: Microsoft-Excel spreadsheet plot capturing the HSpice simulation results for each
iteration run of Monte-Carlo simulations for the differential amplifier with resistive
load shown in Figure 11-5. ................................................................................. 152
Figure 11-7: Functional circuit schematic of a differential amplifier with PMOS current mirror load
for deriving the expression for standard deviation of input-referred offset voltage Vos
............................................................................................................................ 153
Figure 11-8: Microsoft-Excel spreadsheet plot capturing the HSpice simulation results for each
iteration run of Monte-Carlo simulations for the differential amplifier circuit shown in
Figure 11-7. ........................................................................................................ 157
Figure 11-9: Cross-Coupled inverter pair (a) Transistor-level representation (b) Transistor small-
signal equivalent representation ......................................................................... 158
Figure 11-10: Cross-Coupled inverter pair with input transistors (a) Transistor-level representation
(b) Transistor small-signal half-circuit equivalent representation........................ 160
Figure 11-11: Full schematic circuit diagram of a clocked-comparator deriving the expression for
standard deviation of input-referred offset voltage Vos. ....................................... 164
Figure 11-12: Microsoft-Excel spreadsheet plot capturing the HSpice simulation results for each
iteration run of Monte-Carlo simulations for the clocked-comparator circuit shown in
Figure 11-11. ...................................................................................................... 168
Figure 11-13: Microsoft-Excel spreadsheet plotting the 1/f noise corner-frequency across
temperatures from Table 11.9 for three XFAB technologies mentioned above. . 170
xii
List of Tables
Table 1.1: Sampling-rate determination for Neural LFP and AP sensing. ..................................... 19
Table 1.2: Best available ADC architectures in the sampling-speed range of interest. ................. 24
Table 1.3: Target specifications of the SAR-A ADC. ...................................................................... 24
Table 2.1: List of novel ADC architectures published in the literature. ........................................... 27
Table 2.2: List of novel ADC design specifications published in the literature. .............................. 28
Table 2.3: ADC specifications in the sampling-speed range of 50-100 kSa/s and 3-5 MSa/s. ...... 28
Table 2.4: ADC designs that introduce novel circuit design techniques. ....................................... 29
Table 2.5: Contributions of this dissertation. .................................................................................. 29
Table 3.1: Different modes of the SAR-A ADC based on the switch positions. ............................. 31
Table 3.2: Relationship of clock-signals in the SAR-A ADC........................................................... 31
Table 3.3: Target specifications of the SAR-A ADC. ...................................................................... 32
Table 5.1: SAR ADC mode’s sampling-speed characterization. .................................................... 58
Table 5.2: Algorithmic ADC mode’s measured sampling-speed characterization. ........................ 61
Table 5.3: Effects of clock jitter on the Algorithmic ADC’s sampling-speed. .................................. 64
Table 5.4: Effects of substrate-isolation on the Algorithmic ADC’s sampling-speed. .................... 65
Table 5.5: Effects of supply variation on the Algorithmic ADC’s sampling-speed. ......................... 65
Table 5.6: Bandgap reference current calibration using the source meter and resistor methods.. 66
Table 5.7: Effects of incorrect reference current calibration on the Algorithmic ADC performance.
.............................................................................................................................. 67
Table 5.8: 3-sigma ∆ID/ID current mirror mismatch error in the Algorithmic ADC, across corners.
.............................................................................................................................. 68
Table 5.9: Effect of bias-current increase in the Algorithmic ADC sampling-speed. ...................... 69
Table 5.10: Test Setup and instrumentation for SAR ADC’s sinewave fitting and FFT analysis. .. 71
Table 5.11: Test Setup and instrumentation for the Algo ADC’s sinewave fitting and FFT analysis.
.............................................................................................................................. 73
Table 5.12: Test Setup and instrumentation for the SAR ADC’s two-tone testing. ........................ 76
Table 5.13: Two tone IM3 results of the SAR ADC mode. ............................................................. 77
Table 5.14: Test Setup and instrumentation for the Algo ADC’s two-tone testing. ........................ 78
Table 5.15: Two-tone IM3 results of the Algorithmic ADC mode. .................................................. 79
Table 5.16: Measurement results summary of the SAR-A ADC. ................................................... 80
Table 5.17: SAR-A ADC Power-dissipation measured across five chips. ...................................... 81
Table 5.18: SAR-A ADC performance comparison with the best available standalone ADCs suitable
for implantable neuro-stimulators. ......................................................................... 81
Table 6.1: Power-dissipation of the SAR-A ADC modes sampling at 100 kSa/s. .......................... 84
Table 6.2: SAR-A ADC scaling in terms of power-dissipation. ....................................................... 87
Table 6.3: Implementation-area scaling of the scaled SAR-A ADC. .............................................. 89
xiii
Table 6.4: Power-dissipation comparison between 100 kSa/s SAR-A ADC mode and a 5 MSa/s
standalone SAR ADC operating at 100 kSa/s. ..................................................... 91
Table 6.5: Power-dissipation comparison between 5 MSa/s SAR-A ADC mode and a 5 MSa/s
standalone SAR ADC operating at 5 MSa/s. ........................................................ 92
Table 6.6: Implementation-area scaling comparison between the scaled SAR-A ADC and a
standalone SAR ADC designed to achieve target specifications up to 5 MSa/s. . 93
Table 6.7: Performance comparison table with the scaled SAR-A ADC. ....................................... 96
Table 9.1: Summary of the C-DAC Unit-Capacitor value determination. ..................................... 118
Table 9.2: Sub-threshold drain to source leakage current for the setup shown in Figure 9-3..... 120
Table 9.3: Error on the C-DAC output for Least Significant Bit transitions. .................................. 121
Table 9.4: Voltage Error on the C-DAC output for Most Significant Bit transitions. ..................... 121
Table 11.1: Design parameters for the circuit shown in Figure 11-5. .......................................... 151
Table 11.2: 3-sigma standard deviation in the input-referred offset recorded for various Monte-Carlo
iterations for the circuit shown in Figure 11-5. ................................................... 152
Table 11.3: Design parameters for the circuit shown in Figure 11-7. .......................................... 155
Table 11.4: 3-sigma standard deviation in the input-referred offset recorded for various Monte-Carlo
iterations for differential amplifier with PMOS load circuit shown in Figure 11-7.
............................................................................................................................ 156
Table 11.5: Transistors and their region of operation in the clocked-comparator circuit shown in
Figure 11-11. ...................................................................................................... 164
Table 11.6: Design parameters for the clocked-comparator shown in Figure 11-11. ................. 167
Table 11.7: 3-sigma standard deviation in the input-referred offset recorded for various Monte-Carlo
iterations for differential amplifier with PMOS load. ............................................ 168
Table 11.8: 3-sigma standard deviation of the input-referred DC-offset. ..................................... 169
Table 11.9: 1/f noise corner-frequency simulations for three XFAB technologies. ...................... 169
xiv
Abstract
Neural-sensing, defined as the real-time, continuous monitoring of neural-signals, has many
important uses. It is required for the accurate detection of precursors of neural disorders such as
epilepsy. Neural-sensing enables the detection of posture variations, enhancing the quality of life
of patients suffering from neuro-muscular disorders such as Parkinson’s disease, Dystonia, and
Essential tremor. Unlike open-ended neural-stimulation in which stimulation is either active with the
help of patient feedback or continuously active - positive, long-term stimulation therapy outcomes
require timely and reliable stimulation therapy, which requires autonomous closed-loop stimulation
solutions. Autonomous closed-loop stimulation solution requires multi-channel neural-sensing
integrated with the neural-stimulation system to close the loop in implantable biomedical systems.
The key for any implantable biomedical system that aims at sensing neural-signals is an Analog to
Digital Converter (ADC). The ADC converts the incoming, amplified, analog neural-signal to its
digital representation for further processing, and evaluation. To close the loop, multi-channel
implantable systems require high-performance ADCs that switch between sampling-speeds less
than 1 MSamples/s (MSa/s) for sensing neural local field potentials, and 1-10 MSa/s for sensing
evoked or spontaneous neural action-potentials, as well as neural spike sorting. Multi-channel
(30-100 channels) implantable biomedical systems can either have multiple (30-100) ADCs
implemented on the same die [6 - 8] or can have a single ADC sampling at a very high rate of at
least two-to-three times greater than the neural signal bandwidth multiplied by the number of
sensing channels, multiplexing all the channels (30-100), for neural-sensing and/or
neural spike-sorting. The available ADC implementation choices magnify the impact of power-
dissipation and silicon-area per ADC in multi-channel implantable systems, that strive for battery
life of 7 – 10 days on a rechargeable battery and/or small implantable device size less than twenty
(20) cubic-centimeters.
This dissertation proposes and validates an original shared-architecture Successive Approximation
Register / Algorithmic (SAR-A) ADC for closed-loop implantable biomedical systems, to achieve
significantly lower area at similar power and specifications as individual ADCs that achieve desired
xv
specifications in each sampling range. The proposed SAR-A ADC combines the Successive
Approximation Register (SAR) ADC architecture for sampling-speeds less than 1 MSa/s for
multi-channel sensing of neural local field potentials, and the Algorithmic ADC architecture for
sampling-speeds between 1-10 MSa/s for multi-channel sensing of evoked or spontaneous neural
action-potentials, providing 12-bits of resolution in each sampling-speed range with reduced
implementation-area and power-dissipation over alternate solutions.
The SAR-A ADC architecture was first designed, implemented and simulated in the 0.35 µm CMOS
XFAB XH035 process, where the worst-case, post-layout, pad-to-pad, extracted simulation
power-dissipation of the 12-bit SAR-A ADC is 95.5 µW for the SAR ADC mode sampling at
100 kSa/s, and 4.87 mW for the Algorithmic ADC mode sampling at 5 MSa/s. The core
implementation-area of the 12-bit SAR- A ADC in the 0.35 µm CMOS process is 0.55 mm
2
. The
0.35 μm CMOS process from XFAB foundry was chosen as the process-technology vehicle to
verify the SAR-A ADC architecture. This was mainly due to the availability of high-voltage Metal
Oxide Semiconductor (MOS) transistor process-modules in this process (along with the 0.6 μm,
and the 0.8 μm CMOS process) that are typically used for the delivery of the neural-stimulation
therapy. With the CMOS technology scaling rapidly, and with the availability of the high-voltage
MOS transistor process-modules in deep sub-micron process like the 0.18 μm CMOS, it is now
viable to utilize the 0.18 μm (or 180 nm) CMOS process as a test vehicle to realize the SAR-A ADC.
The 12-bit SAR-A ADC architecture is fabricated in 180 nm CMOS Six-metal one-polysilicon
gate (6M1P) XFAB XH018 process with a supply-voltage of 1.8 V, occupying a core
implementation-area of 0.31 mm
2
. In the SAR and the Algorithmic ADC modes, the measured
power-dissipation (including the analog, digital, and reference) is 36.9 μW and 3.99 mW
respectively, operating from a 1.8 V power supply. In the 100 kSa/s SAR ADC mode, the ADC
achieves a measured SFDR of 66.3 dB, a measured SINAD (SNDR) of 65.081 dB, and a measured
ENOB of 10.518 bits. The SAR ADC mode’s measured DNL and INL are 0.54 LSB and 0.66 LSB,
respectively. In the Algorithmic ADC mode, at 5 MSa/s, the ADC achieves a measured SFDR of
63.87 dB, a measured SINAD (SNDR) of 62.77 dB, and a measured ENOB of 10.134 bits. The
Algorithmic ADC mode’s measured DNL and INL are 1.08 LSB and 1.17 LSB, respectively.
xvi
Dissertation Organization
Chapter 1 introduces the available open-ended implantable neuro-stimulators, and motivates the
need for closed-loop solutions, followed by determining the ADC specifications for neural-sensing,
to close the loop. Chapter 1 further discusses the available ADC choices, and ends with the
dissertation research question, and the hypothesis.
Chapter 2 is a literature survey of relevant ADCs with categorization of the published literature
based on novelty of ADC architecture, specifications or circuit design, ending with the summary of
the contributions of this research work.
Chapter 3 documents the proposed shared-architecture hybrid SAR-A ADC. As a supplement to
Chapter 3, Appendix C evaluates the three well-understood techniques for compensating the
mismatch, the input-referred DC-offset, and the 1/f noise contributions. Appendix C also articulates
the rationale for choosing the chopper-stabilization technique from among the three techniques that
can be implemented in the proposed shared-architecture ADC.
Chapter 4 discusses the design of the SAR-A ADC at a high-level, and the challenges implementing
the hybrid ADC architecture. As an extension to Chapter 4, the system level analysis and design
of the sub-blocks in the SAR-A ADC are detailed in Appendices A and B. Appendix A discusses
the analysis and the design of the internal C-DAC of the SAR ADC. Appendix B details the
system-level analysis and the circuit-design of implementation of the key block of the shared
comparator in the SAR-A ADC.
Chapter 5 presents the measured results of the SAR-A ADC fabricated in the XFAB 6M1P 180 nm
CMOS process-technology, outlining the various procedures and the analysis to evaluate the static
and the dynamic performance of the SAR-A ADC. Potential causes for the deviation in performance
results are also discussed here. Chapter 5 concludes by documenting the performance summary
based on the measured results, and the comparison with the standalone state-of-the-art ADCs.
xvii
Chapter 6 then answers the four main questions to determine the feasibility of the SAR-A ADC
architecture, and how the proposed shared-architecture SAR-A ADC would scale with the CMOS
technology feature-size. Comparisons of the SAR-A ADC performance at 65 nm and 40 nm CMOS
process (based on calculations and extrapolation) are made with the recently published deep
sub-micron (65 nm, 40 nm, etc.) technology implementations of the SAR ADC.
Finally, Chapter 7 presents the dissertation summary.
Chapter 9, Appendix A documents the analysis and the design of the SAR ADC’s internal C-DAC.
Appendix A also discusses the effects of the sub-threshold drain to source leakage current on the
performance of the SAR ADC’s internal C-DAC. Appendix A serves as an extension to
Section 4.3.1 of Chapter 4.
Chapter 10, Appendix B details the analysis and design of the shared-comparator by dwelling into
small-signal (AC), DC, and the transient analysis. The analysis of the small-signal impedance of
the comparator looking up from the drain of the tail current transistor is also documented in this
chapter. Appendix B serves an extension to Section 4.3.2 of Chapter 4.
Chapter 11, Appendix C first introduces the effects of mismatch, input-referred DC-offset and
1/f noise contributions on the ADC performance. Then the three well-understood offset
compensation techniques are presented and evaluated. This is then followed by the analytical
determination of the input-referred offset of the shared-comparator, using Monte-Carlo simulations.
Finally, the rationale to pick the Chopper-stabilization technique as the compensation technique is
outlined. Appendix C serves as an extension to Section 4.3.4 of Chapter 4, as well Chapter 3.
1
1 Introduction
Signals in the real world are analog: light, sound, neural-signals, etc. Real world analog signals
must be converted into their digital form before they can be processed by digital systems. Analog
to Digital Converters (ADCs), which convert incoming, amplified, analog signal to their digital
representation for further processing and evaluation, have a wide range of applications in electronic
systems. In implantable biomedical systems, the ADC plays a key role by providing an interface
between the analog front-end and the subsequent digital circuit-blocks. The analog front-end needs
to amplify small (few μV-mV of signal amplitude) biological analog neural-signals from multiple
channels (8-100), into larger ones (hundreds of mV of signal amplitude). The neural-signal of
interest is then digitized by the ADC, prior to subsequent signal processing in the digital domain.
The utility of this signal processing is to characterize the neural-signal for pre-cursor (event-onset)
detection, channel identification, and configuration of stimulation parameters for timely and reliable
delivery of neural-stimulation therapy.
Recent success in treating neurological disorders involves the usage of Active Implantable Medical
Devices (AIMD) that interface with the central nervous system. These AIMDs typically consists of an
Implantable Pulse Generator (IPG) and leads (also called as electrodes) that deliver neural-stimulation
therapy. Current clinically approved implantable neuro-stimulators for Spinal Cord Stimulation (SCS)
require patient intervention (manually adjusting amplitude, frequency, and stimulation patterns) to deliver
neural-stimulation therapy for chronic pain treatment. Deep Brain Stimulation (DBS) therapies use Brain
Machine Interface (BMI) or AIMDs to treat neurological conditions, such as paralysis, prosthetic limb
control, essential tremor, Parkinson’s disease, and dystonia. DBS therapy entails using the Implantable
Pulse Generator (IPG) in an open-loop (no-feedback from the patient) configuration and is sometimes
paired with an external processing module to deliver neural-stimulation to close the loop [1, 2]. Current
AIMD designs focus on optimizing either the neural-stimulation delivery or neural-recording
capability, but not both. Continuous and real-time monitoring of the neural-signals is required for
2
accurate precursor detection. This is the key for ensuring that stimulation therapy is delivered reliably
and only when needed in closed-loop implantable biomedical systems.
Autonomous Implantable Biomedical Systems (IBS) typically run on battery
1
power. If we consider
a rechargeable battery with a capacity of 200 milli-Ampere-hour (mAh), operating at a nominal
voltage of 3.6 V, having dimensions of 17 mm x 35 mm [81], then a biomedical system that
continuously consumes 1 mA of battery current will completely drain the 200 mAh battery in
200 hours. Typically, these systems are “duty-cycled” to prevent continuous current draw from the
battery. In sleep, inactive, or power-down modes
2
, an IBS will consume current in the order of 10 μA
from the battery which is enough to power-up the essential circuits, such as voltage references and
voltage regulators. In active-mode, an IBS will consume current in the order of 10 mA from the
battery, for the delivery of neural-stimulation therapy or telemetry. Figure 1-1 shows the typical
block diagram of a microelectronic, implantable biomedical sensing system, where the
neural-signal from the tissue is amplified and digitized prior to subsequent processing. Essential
circuit-blocks, such as telemetry (receiver / transmitter), neural-stimulation, and battery
management, are not shown here. A bandpass filter is used to eliminate the Electrode-Tissue
Interface (ETI) induced DC-offset (< 10 mV) and prevent aliasing (high-frequency components of
the signal that could fold back into the frequency band of interest). The pass-band of the bandpass
filter is typically from 100 Hz – 10 kHz for sensing neural action-potentials or local field-potentials.
The Variable Gain Amplifier (VGA) is typically positioned after the filter and before the ADC to
provide appropriate gain settings depending on the required amplification of the incoming signal.
The ADC circuit, which is the interface between the analog front-end and the subsequent digital
circuit-blocks, becomes operational during the sensing mode. Less than 1 mA total current drain
can be partitioned to the front-end sensing circuitry. This is based on a typical recharge time-gap
1
Typical capacity of AA cell battery is 700 mAh; AAA cell battery is 340 mAh; D cell battery is 3000 mAh; Li-ion battery is
700 mAh.
2
The sleep mode or the inactive mode or the power-down mode of an IBS is the mode in which neural-stimulation or the
telemetry related circuits are not functioning.
3
of 7-8 days using a 200 mAh rechargeable battery. Prosthetic implantable biomedical devices, like
Deep Brain Stimulator (DBS), Spinal Cord Stimulator (SCS), and Retinal Stimulator, need to cater
to varying stimulus requirements of patients for different regions of the human body.
Single sensing Channel shown
Biological
Tissue
Electrode
Array
ADC
Low Noise
Amplifier
Filter
Variable Gain
Amplifier
Processor
Bit
Stream
Figure 1-1: Block diagram of a typical biomedical system (sensing chain)
ADCs are useful in achieving the desired resolution in neural-sensing. For example, an ADC with
12-bits of resolution and with a full-scale detection range of 0 V to 1 V will have a resolution of
1/2
12
= 245 μV. In this context, resolution is defined as the smallest analog-input signal an ADC can
digitize. The analysis and processing of the digital signals are dependent on the specific demands
enforced by the precise delivery of the neural-stimulation therapy. Therefore, power-dissipation is
a very important consideration of the front-end sensing chain, which include the ADCs. Longer
battery life and new features are expected in every new generation of implantable devices.
Advanced power management and system-on-chip integration are needed to limit high-power
off-chip communications and are the means to increase battery life in an IBS [25]. Most implantable
biomedical systems today require patient intervention for delivery of neural-stimulation therapy.
There is a need for closed-loop implantable systems that operate without any feedback from the
patient and run autonomously for precise delivery of neural-stimulation therapy. They operate
continuously, monitoring relevant neural-signals (either neural action-potentials or neural
local field potentials) for accurate precursor detection before delivering the appropriately configured
neural-stimulation therapy.
4
The Spinal Cord Stimulator implantable biomedical system
The Spinal Cord Stimulator (SCS) is an Implantable Pulse Generator (IPG) system. SCS IPG is
used for neural-stimulation therapy to inhibit the pain signals that are carried by the nerve fibers
from different parts of the body to the brain through the spinal cord. Neuropathic pain is treatable
with Spinal Cord Stimulation. The neural-stimulation therapy is targeted towards patients with acute
chronic pain. Pain is typically a perceived sensation resulting from signals transmitted from the pain
site to the brain, via the spinal cord. By applying electrical stimulation to the nerve bundle present
in the dorsal column of the spinal cord, the pain sensation can be replaced with a sensation called
paresthesia, which is a tingling sensation (as shown in Figure 1-2 in blue color). Therefore, during
pain suppression, a patient undergoing spinal neural-stimulation therapy will not feel the chronic
pain but will feel this tingling sensation as a side-effect in the same body part where the
neural-stimulation therapy is targeted. The system utilizes a multi-contact wire (referred to as the
“Lead”), where one end of the Lead is epidurally placed along the dorsal column of the spinal cord.
The other end of the Lead is attached to a programmable, implantable, pulse-generating device.
Figure 1-2: Spinal Cord Stimulator Implantable Pulse Generator intercepting the pain
signals.
In a 16-channel implantable device, two Leads with 8 electrodes each are typically connected to
the IPG. The distal ends (away from the IPG) of the leads have 8 platinum electrodes each that are
placed in the dorsal columns of the spinal cord for stimulation of the nerves in the spinal cord.
The impedance of the tissue-fibers varies between 300-5000 Ω. Following Ohms law, the SCS IPG
generates constant-current bi-phasic pulses to the nerves as therapy, by varying the output voltage
depending on the measured impedance.
5
The Deep Brain Stimulator implantable biomedical system
Deep brain stimulation (DBS) is a therapy used to treat a variety of disabling neurological
symptoms. The most common symptoms of one such disease, Parkinson’s disease (PD), are
rigidity, stiffness, slowed movement, and walking problems. The therapy is also used to treat
essential tremor, a common neurological movement disorder. At present, the therapy is used only
for PD patients whose symptoms cannot be adequately controlled with medications. DBS uses a
surgically implanted, battery-operated, medical device called a Neurostimulator with an
approximate volume of 40 cubic-centimeters.
(A) (B)
Figure 1-3: Implanted Deep Brain Stimulator.
(A) Leads implanted in the human brain. (B) Medtronic DBS implant. The battery and
circuitry form the IPG, which is implanted in the chest. The electrodes are placed into a
specific neural circuit within the brain. Connections are made between the IPG and
electrodes via a lead system placed in the neck.
The neurostimulator delivers electrical stimulation to targeted areas in the brain (see Figure 1-3)
that control movement, blocking the abnormal nerve signals that cause tremor and PD symptoms.
Before the procedure, a neurosurgeon uses Magnetic Resonance Imaging (MRI) or Computed
Tomography (CT) scanning to identify and locate the precise target area within the brain where
6
electrical nerve signals generate the above symptoms. Generally, these targets are the thalamus,
sub-thalamic nucleus, and Globus-pallidus regions of the brain.
The DBS system consists of three components: The Lead, the extension, and the neurostimulator.
a. The lead (also referred as an electrode), is a thin insulated wire that is inserted through a
small opening in the skull and implanted in the brain. The tip of the electrode is positioned
at the targeted brain area.
b. The extension is an insulated wire that is passed under the skin of the head, neck, and
shoulder, connecting the lead to the neurostimulator.
c. The neurostimulator (also referred to as the ‘battery pack’), is the third component and is
usually implanted under the skin near the collarbone.
In some cases, it may be implanted lower in the chest or under the skin over the abdomen. Once
the system is in place, electrical impulses are sent from the neurostimulator up along the extension
wire, the lead, and into the brain. These impulses interfere and block the electrical signals that
cause the abnormal neurological symptoms described earlier in this section.
Reported closed-loop solutions for implantable systems
Figure 1-4 shows the University of Michigan’s implementation of a closed-loop DBS stimulator for the
treatment of Parkinson’s disease [70]. This is an 8-channel system with power-dissipation of 486 μW
using a 3.3 V battery. The system relies on an off-the-shelf Micro-Processor. A logarithmic (log)-domain
signal processing chain is introduced, that incorporates a log-ADC, digital log-filters, and a log-DSP. This
system has one 8-bit resolution Logarithmic ADC, multiplexing 8-channels, implemented in the 0.18 μm
CMOS process in the year 2012. Reliable precursor detection via adaptive neural-sensing that can
enable precise delivery of neural-stimulation therapy is missing in the stimulator system solution.
Figure 1-5 shows the system block diagram of a Medtronic DBS IPG. The sensing and control
extensions are interconnected with the neurostimulator circuits and electrodes. The sensing and control
module has three key circuit-blocks: The Neural-spectral Processing Integrated Circuit (NPIC) that
connects to the electrodes and senses neural-signals; a micro-processor or micro-controller for
7
performing algorithms on the neural-signal based on the feature extraction; and a memory unit for
recording events and general data-logging.
Figure 1-4: A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-
way wireless telemetry for the treatment of neurological disorders [70].
The NPIC chip that is implemented in 0.8 μm CMOS is integrated with the stimulator to extract the
neural-signals. This system uses an ADC with a resolution of 10 bits and is part of the off-the-shelf
microcontroller. This is because of the availability of the ADC functional block in the micro-controller
chip. The 8-Channel System has a power-dissipation of 575 μW from a 3.2 V, 6.3 Ah primary-cell
battery. The US Food and Drug Administration (FDA) approved Medtronic’s DBS as a treatment
for essential tremor in 1997, for Parkinson's disease in 2002 and dystonia in 2003. DBS is also
routinely used to treat chronic pain, and various affective disorders, including major depression.
8
Figure 1-5: Architectural block diagram of a Medtronic Corporation’s Deep Brain Stimulator
(DBS) Implantable Pulse Generator (IPG) [23].
ADC requirements for multi-channel closed-loop SCS and DBS
implantable systems
Closed-loop (without any feedback from the patient) implantable biomedical systems need to
continuously monitor neural-signals. For example, an implantable device used for DBS for detecting
epileptic seizure onset must monitor neural-signal activity in the brain for event detection of seizure
onset and deliver neural-stimulation based therapy to counteract the seizure. Such implantable
devices need to have an analog to digital conversion capable of decoding the neural-signal activity
by continuously monitoring the neural-signals from different channels in real time. Another possible
example is a closed-loop Spinal Cord Stimulator (SCS) used for controlling chronic pain. A
closed-loop SCS system needs to monitor the neural-signal activity in the spinal cord and deliver
therapy by identifying and masking the pain signals going to the brain. [3, 4, 5] aims at closing the
loop by integrating the neural-recording and the neural-stimulation based on the signal processing
of the neural-recording. These closed-loop implementations have one [4] or two [5] Successive
Approximation Register (SAR) ADCs implemented in a System on a Chip (SoC), that are operating
at the same sampling-speed, and are limited to 4 - 16 channels in the front-end sensing capabilities,
mainly due to the complexity of the analog front-end, ADC sampling-rate and power-dissipation
9
requirements. On the other hand, research on multi-channel (up to 100 channels) implantable
systems for neural-sensing or neural-spike-sorting applications have multiple ADCs implemented
on the same die. [6] proposed a 96 channel neural-interface system with 96 SAR ADCs sampling
at 100 kSa/s fabricated in 0.13 µm CMOS, while [7] proposed a 100 channel implantable
neural-recording system fabricated in 0.18 µm CMOS with 10 SAR ADCs on a die, and each
SAR ADC multiplexing 10 channels, sampling at 245 kSa/s. [8] proposed a 100 channel
neural-recording IC, again with 10 SAR ADCs, with each ADC multiplexing 10 channels at a
sampling-rate of 200 kSa/s in 0.18 µm CMOS. Having multiple ADCs on a single die leads to a
significant increase in area and power-dissipation, which battery powered AIMDs cannot afford. Let
us determine the ADC requirements (Resolution, Sampling-Rate) needed to decode the
neural-signals of interest for the SCS and the DBS.
1.4.1 ADC specifications to sense Local Field Potentials
Since epilepsy causes repeated and sudden seizures, people with this condition would benefit
greatly from a therapy that can detect seizures as they are starting or predict them before they
begin and prevent them from occurring. Implantable closed-loop devices are considered a new
frontier in epilepsy treatment, where sensing and analyzing Local Field Potentials (LFPs) in the
brain is becoming necessary for epileptic treatment. The LFP neural-signal has an amplitude range
of 10 µV – 1.5 mV [62, 74]. Therefore, the minimum ADC resolution needed is
log2 (1.5 mV/10 µV) = 8 bits. A feature extraction processor is typically used, following the ADC, to
characterize the sensed neural-signal for seizure onset [74, 77]. The critical metrics for seizure
onset detection are the sensitivity (% of test-seizures identified), the specificity (false-alarms/hour)
and the latency (delay in the extraction processor’s declaration of the seizure activity) [75, 78, 79].
These metrics are affected by the number of divisions (bins) of the frequency band of interest and
the ADC resolution. Going from two-bins to eight-bins, improves the sensitivity (from 45% to 90%),
and the specificity (from 1.5 to 1 false-alarms/hour), and reduces the latency (from 18 to 6 seconds)
[74, 76]. Based on the experimental results, it is determined that onset detection improves as the
10
resolution of the ADC is increased to at least 10-bits [74]. Therefore, implementing an ADC with
resolution of 12-bits will guarantee the Effective Number of Bits (ENOB) of at least 10 bits.
Figure 1-6 shows the frequency band of interest for the Local Field Potentials for epileptic seizure
detection and analysis. Fast Ripples and High-Frequency Epileptiform Oscillations (HFEO) have
the strongest association with epileptic seizure onset [71]. HFEOs are also called Slow Ripples.
HFEOs are found in neocortical epilepsy patients. Neocortical epilepsy is a type of seizure disorder
that can be either partial (focal) or generalized, in which the seizures originate in the neocortex part
of the external surface layer of the brain. This is not a good indicator of seizure location but has a
strong association with seizure onset [72]. The Ripples band (100-250 Hz) does not show a clear
differentiation between seizure onset and non-onset areas. Rate of occurrence of Fast Ripples (FR)
are much higher within the seizure onset zone than outside the zone [63]. FRs occurs before
ipsilateral temporal lobe seizures [62]. Localized in hippocampus (focal seizure onset -- seizures
take 20 seconds or more to spread out of the focus region), the frequency band of the FR is
250Hz - 600Hz.
Figure 1-6: Frequency band of interest for the LFPs.
The FR and HFEO seizure onsets are referred to as electrical onsets - a subtle but characteristic
change, which can be noticed in an EEG or an LFP recording. The clinical onset (characterized by
muscle reflexes followed by the actual seizure) occurs 7-10 seconds after the electrical onset [6].
Multiple electrical onsets occur before the actual clinical onset [80]. For LFP, maximum signal
bandwidth is 600 Hz. Therefore, we need to sample the 600 Hz bandwidth LFP signal with an
anti-aliasing six-pole filter at 3 kSa/s. To integrate the LFP sensing with a 32-channel
neuro-stimulator, the ADC must be capable of sampling at least at 96 kSa/s for 12-bit operation (at
least 10 ENOB).
11
1.4.2 ADC specifications to sense Extra-Cellular Neural Action-Potentials
The amplitude of the Extra-Cellular Neural Action-Potential (ENAP) varies depending on the location
of the probing (sensing) in the brain w.r.t to the cell-soma (see Figure 1-7) with maximum
peak-to-peak amplitude of 200 µV [9, 11, 13]. To enable spike-sorting using a template-matching
(TM) technique, a minimum voltage resolution of 0.6 µV is needed [9], based on 80% true-positive
detection. This translates to a minimum of log2 (200/0.6) = 8.38 bits of resolution. In [10], both True
and False positive detection were used to quantify the spike-detection and spike-sorting
performance for varying number of target unit cells (1, 2, and 4 – each microelectrode recording
1, 2 or 4 neurons), and standard deviation of the background noise (σN = 0.01 to 0.3) w.r.t the ENAP
peak amplitude of 200 µV. Spike-detection algorithms such as absolute-value threshold detection
(ABS), Nonlinear Energy Operator detection (NEO), Stationary Wavelet Transform Product detection
(SWTP), Matched-filter based detection (MF), and spike-sorting algorithms such as Principal
Component Analysis (PCA), Discrete Wavelet Transform (DWT), Discrete Derivatives (DD), and
Fuzzy C-means (FCM) were evaluated, to determine the sampling resolution needed for accurate
(above 95% true positive and below 5% false positive) spike-detection and spike-sorting. The
sampling resolution needed was found to be 9.3 bits = 10 Effective Number of Bits (ENOB) [11, 13].
Figure 1-7: Extra-Cellular Neural Action-Potentials [9]
ENAP sensing and spike-sorting can be performed using micro-wires (there can be 16-25
micro-wires/lead for a total of 4 leads for 32-contact stimulation / ENAP sensing) facilitating 64-100-
channel ENAP-Spike sorting. For ENAP, the maximum signal bandwidth is 10 kHz. Therefore, we need
12
to sample the 10 kHz bandwidth ENAP signal with an anti-aliasing six-pole filter at 50 kSa/s per channel.
For 64 - 100 channel ENAP sensing, the ADC sampling-speed must be 3 - 5 MSa/s at 12-bits.
1.4.3 ADC specifications to sense Evoked Compound Action-Potentials
Spinal Cord Stimulation (SCS) is currently an approved therapeutic technique to treat lower limb
and back chronic pain in patients with Failed Back Surgery Syndrome (FBSS) and Chronic
Regional Pain Syndrome (CRPS). The therapy is delivered with leads placed in the epidural space
of the Spinal Cord. The leads are connected to an implantable pulse generator, which is implanted
subcutaneously. Currently, the stimulation therapeutic technique is open-loop (the device does not
receive feedback directly from the patient’s nervous system) and the patient feedback such as
location of paresthesia and pain level are used to re-program the device and evaluate therapeutic
outcomes on a continual basis in a clinical setting. It is desired to be able to directly assess the
evoked response from stimulation and close the loop (in which the device would receive feedback
from the patient’s nervous system and be able to adjust stimulation parameters based on that
feedback). One method is to use the remaining non-stimulation electrodes of the implanted
multi-electrode array to record the evoked activity from the spinal cord and use this as objective
information to adjust the stimulation parameters. This Evoked Compound Action-Potentials (ECAP)
in Spinal Cord Stimulation applications can be studied for posture detection, lead migration, and
nerve damage (nerve conduction study). This is accomplished by stimulating at least one electrode
pair and measuring the response on adjacent electrode(s) or distant electrodes along the neural
path to the brain. Since ECAP amplitude reflects the neural response to stimulation directly, sensing
ECAPs enable control of stimulation pulse-width and amplitude to account for posture variations or
lead migration. A raw ECAP signal ranges from 100s of µV to 10s of mV resulting is 8-10 bits of
dynamic range. Since ECAP is an evoked response to stimulation, the induced artifacts (typically
in 100s of mV) due to stimulation in adjacent electrodes, needs to be accounted for in the Dynamic
Range (DR) requirements of the analog front-end, necessitating the ADC resolution to be at least
12-bits (see Section 1.4.4). There are two ECAP modes of operation: Amplitude measurement
and conduction-velocity measurement.
13
• Amplitude measurement, where the signal bandwidth of interest is up to 7 kHz. Sampling at
150 kSa/s per channel (accounting for anti-aliasing filter 4-pole), the ADC sampling-speed
needs to be at least 2.4 MSa/s for 16 channels or 4.8 MSa/s for 32 channels.
• Conduction-Velocity (CV) measurement range of 70 m/s to 120 m/s. Conduction-velocity
measurement should be within +/- 10%. Based on this information, for a worst-case scenario
of 4 mm electrode spacing, and for CV of 120 m/s, we have 4 mm = dt * 120 m/s. Therefore,
dt = 33.3 µs; and 10% of CV => dt/10 = 3.33 µs; This implies that the sampling-rate
Fs = 1/3.33 µs = 303 kSa/s per channel.
Therefore, for sensing ECAPs an ADC should have sampling-rate of at least 303 kSa/s per
channel. To facilitate sensing on at least 16 of the 32 channels (typically half the number of
channels, for posture detection and correction), the ADC sampling-rate needs to be at least
16*303 kSa/s = 4.85 MSa/s featuring resolution of at least 12-bits.
1.4.4 ADC resolution determination based on the effects of the ETI
LFPs represent the ensemble activity of millions of neurons, therefore requiring a larger surface contact
area (~ 1 mm
2
) to sense this ensemble activity. The APs on the other hand represent a single neuronal
activity, needing smaller surface contact area (< 0.1 mm
2
) to sense them. In [72], the neural-signals in
the human brain are sensed using the macro and micro contacts. The surface contact area of the
electrode that interfaces with the tissue determines the type of the neural-signal that is sensed by that
electrode. LFPs are sensed with macro contacts due to their larger surface area (compared to the
micro-contacts) and the APs are sensed with the micro-contacts. Therefore, the Electrode to Tissue
Interface (ETI) plays a vital role in sensing the neural-signals. As discussed in the previous section, ECAP
is an evoked response to stimulation. Therefore, induced stimulation artifacts (typically in 100s of mV)
due to the stimulation in adjacent electrodes, needs to be accounted in the Dynamic Range (DR)
requirements of the analog front-end. The ETI is a non-linear circuit element where the electron-to-ionic
charge transduction occurs. Therefore, it is important to understand how the noise and distortion
introduced by the ETI affects the quality of the recorded signals, especially the stimulation artifacts.
A series of experiments were carried out (thanks to Dr. Hokhikyan for helping with the experimental setup
14
(see Figure 1-8) and measurements (see Figure 1-9)), where differential stimuli is applied to the
worst-case configuration of two stimulus electrodes with differential response measured at electrodes
adjacent to the stimulating electrodes through the ETI.
Figure 1-8: Experimental setup to understand the effects of the ETI on the sensed-signals.
Figure 1-9: Measured signal quality of the differential response through the ETI.
The experimental measurement setup is shown in Figure 1-8, where the differential stimuli is applied
between the two electrodes, while the differential response via the ETI is sensed from the two electrodes
adjacent to the differential stimuli. This arrangement of sensing adjacent to the stimulus presents the
15
worst-case capture of the Stimulation artifact because the stimulation artifact attenuates as it progresses
farther away from the stimulation site. ETI responses are recorded through 0.2 S/m Phosphate Buffered
Saline (PBS), which is an experimental proxy for sheep brain due to similar bulk conductivity. Figure 1-9
shows the measurement results of the signal quality of the response through the ETI. This response
includes the overall setup plus the electrode configuration plus the ETI response. We can see that in the
LFP band of interest (10 Hz – 600 Hz), the maximum measured signal quality is 11.1 Effective Number
of Bits (ENOB), where as in the AP band of interest (10 Hz – 10 kHz), the maximum measured signal
quality is 11.6 ENOB. This means that we need a very high-quality, low-noise ADC with at least 12-bits
of resolution to sense LFPs and APs.
1.4.5 ADC Sampling-Rate Needed for Multi-Channel Neural-Sensing and Spike-Sorting
Multi-channel implantable systems for neural-sensing and neural spike-sorting can either have multiple
ADCs implemented on the same die:
• A 96-channel neural-interface system with 96 ADCs sampling at 100 kSa/s in 0.13 µm CMOS
in the year 2012 [6]
• A 100-channel implantable neural-recording system with 10 ADCs, with each ADC multiplexing
10 channels and sampling at 245 kSa/s in 0.18 µm CMOS in the year 2013 [7]
• A 100-channel neural-recording IC with 10 ADCs with each ADC multiplexing 10 channels and
sampling at 200 kSa/s in 0.18 µm CMOS in the year 2013 [8].
Or the implantable system can have one ADC sampling at a significantly higher rate (in < 10 MSa/s
range) to ensure that all the channels (30-100 channels) are multiplexed for neural-sensing and
neural-spike-sorting. One implementation approach is to have 100 ADCs for 100-channels for LFP
and AP sensing with each ADC sampling at 50 kHz all the time [6-8]. This results in significant
implementation-area penalty and power consumption, due to 100 ADCs on the same die. The
second approach, as described in [4], is to implement a dedicated ADC for sensing LFPs and
another dedicated ADC for sensing APs on the same die. This increases the implementation-area
and power-dissipation, compared to a single ADC implementation. Furthermore, the input-referred
DC-offset calibration for each ADC must be managed and accounted for, during signal-processing.
16
The third approach is to have one ADC that can multiplex multiple channels, switching from one
mode for sensing LFP to a second mode for sensing AP based on the neural-signal precursor
identification. This approach significantly reduces the implementation-area and power-dissipation
compared to multiple ADCs on a single die approach. Furthermore, the input-referred DC-offset is
constant because both modes of the ADC share the same critical analog circuit-blocks for
neural-sensing of the LFPs and the APs.
Commercially available AIMDs that are used for DBS and SCS therapies have evolved from
8-channel to 32-channel [19] neural-stimulation systems. A regulatory-body – Food and Drug
Administration (FDA) approved and commercially available 32-channel AIMD is an open-ended
neural-stimulator (neural-stimulation without sensing and closed-loop capabilities). To close the
loop, a 32-channel neural-stimulator should be integrated with a 32-channel front-end
neural-sensing circuitry and interface (using a combination of macro and micro electrodes), and
then process (ADC followed by a Digital Signal Processing unit (DSP)) the sensed neural LFP and
the neural AP. The utility of this signal processing unit is to characterize the neural-signal for
event-onset detection and channel identification [74, 77]. Once an event-onset detection and
channel identification are made, then the stimulator can be programmed with the necessary
amplitude, pulse-width and period for the precise delivery (on the identified channel) of
neural-stimulation therapy.
To accurately decode the analog neural-signals, any induced artifacts either due to stimulation or
the ETI needs to be accounted for in the Dynamic Range (DR) and Signal to Noise (SNR)
requirements of the analog neural-sensing front-end, which includes the ADC. Anti-aliasing filter
roll-off must satisfy the SNR requirements of the ADC. The ADC sampling-rate for neural-sensing
can be chosen to ease the design requirements of the Anti-Aliasing Filter (AAF). Neural LFP signal
information is present in the bandwidth of 1 Hz – 600 Hz. For single channel LFP sensing, the ADC
must be sampled at the rate of 3 – 9 kSa/s (5 – 15 times) to satisfy the SNR requirements of 74 dB
to achieve the resolution of 12-bits. The goal is to arrive at the minimum sampling-rate
specifications based on the LFP signal bandwidth to satisfy the SNR requirements of 12-bits.
Furthermore, the sampling-rate determination is made to prevent aliasing of undesired signals such
17
that the aliased images of the input signal should not corrupt the input SNR of 74 dB (12-bits).
As shown in Figure 1-10, for neural LFP sensing, increasing the ADC sampling frequency (FS) to
3 kSa/s, 4.8 kSa/s or 6 kSa/s due to the challenge presented by the SNR requirements of 12-bits,
also relaxes the requirement on the transition band (pass band to stop band) roll-off by facilitating
a 6- pole, 5-pole, or 4-pole AAF design, respectively. Similarly, for neural Action-Potentials (AP),
the signal information is present in the bandwidth of 100 Hz – 10 kHz. Therefore, for single channel
AP sensing, the ADC must be sampled at the rate of 50 – 150 kSa/s (5 – 15 times), to satisfy the
SNR requirements of 74 dB to achieve the resolution of 12-bits.
To illustrate this, let us choose the AP sensing scenario (see Figure 1-10), where we choose the
FS = 30 kHz (FSNyq + FAP) as the ADC sampling frequency, and the bandpass filter’s low-pass
cut-off frequency as 10 kHz (FAP). Then, the roll-off from pass-band corner frequency of 10 kHz
(FAP) to the start of the stop-band 20 kHz (FS – FAP) must be at LEAST 74 dB to satisfy the input
SNR requirements of 12-bit ADC (SNR = 6.02 N + 1.76, for an N-bit ADC). This means that the
filter roll-off must be 74 dB/octave (from 10 kHz to 20 kHz).
Figure 1-10: ADC sampling-rate requirements based on the neural-signal bandwidth and the
AAF requirements.
Neural Local
Field
Potentials
10 600
10
-5
10
-4
10
-3
10
-6
Frequency (Hz)
Voltage (V)
1.2k
F snyq
1.8k
F s (ADC)
Band-Pass Filter (Low-Pass)
Cut-off Freq F LFP = 600 Hz
Choice
0.2µV
(74 db/Octave)
=> 13-pole
filter
Neural Local
Field
Potentials
10 600
10
-5
10
-4
10
-3
10
-6
Frequency (Hz)
Voltage (V)
1.2k
F snyq
1.8k
F s (ADC)
Band-Pass Filter (Low-Pass)
Cut-off Freq F LFP = 600 Hz
Choice
0.2µV
6-pole filter
3k 2.4k 3.6k 4.2k 4.8k 5.4k 6k
5-pole filter
F s (ADC)
Choice
F s (ADC)
Choice
74 dB SNR
4-pole filter
74 dB SNR
F S - F LFP
(F S – F LFP ) (F S – F LFP ) (F S – F LFP )
Neural
Action
Potentials
100 10k
10
-5
10
-4
10
-3
10
-6
Frequency (Hz)
Voltage (V)
20k
F snyq
30k
F s (ADC)
Band-Pass Filter (Low-Pass)
Cut-off Freq F AP = 10 kHz
Choice
0.2µV
(74 db/Octave)
=> 13-pole
filter
Neural
Action
Potentials
100 10k
10
-5
10
-4
10
-3
10
-6
Frequency (Hz)
Voltage (V)
20k
F snyq
30k
F s (ADC)
Band-Pass Filter (Low-Pass)
Cut-off Freq F AP = 10 kHz
Choice
0.2µV
6-pole filter
50k 40k 60k 70k 80k 140k 150k
5-pole filter
F s (ADC)
Choice
F s (ADC)
Choice
74 dB SNR
4-pole filter
74 dB SNR
F S - F AP
(F S – F AP ) (F S – F AP ) (F S – F AP )
18
With a single-pole filter yielding a roll-off of 6 dB/octave (or 20 dB/decade), a 13-pole
3
filter is needed to
satisfy the SNR requirements of 12-bits. To achieve an integrated filter solution, a biquadratic filter
(Operational Transconductance Amplifier (OTA) – Capacitor) based implementation is possible.
However, the biquadratic filter’s quality factor (Q) and the center frequency (f0) variations are the principle
cause of the high order (8
th
order and above) filters’ overall frequency-response degradation [18].
Furthermore, as the filter order increases, the number of biquadratic filter sections for the filter increase;
thus, increasing the power consumption and the implementation-area. Therefore, for Neural AP sensing,
also shown in Figure 1-10, increasing the ADC sampling frequency (FS) to 50 kHz, 80 kHz, or 150 kHz
relaxes the requirement (to achieve the 74 dB SNR (12-bits)) on the band pass filter’s transition band
(pass-band to stop-band) roll-off, by facilitating a 6-pole, 5-pole, or 4-pole filter design, respectively.
In the LFP sensing mode to facilitate the pre-cursor detection, the sensing front-end must be
continuously active. Therefore, the power-dissipation of the ADC, and the sensing front-end in general
needs to be minimized. In the LFP band of interest, cross-frequency-band correlation between α, β, γ,
HFEO, Ripples (see Figure 1-6) has been shown to be useful in predicting temporal epileptic seizures
[82, 83, 84]. To facilitate cross-frequency-band correlation, the neural-sensing front-end specifically the
AAF must exhibit a linear phase response or a constant group delay in the LFP pass band. This is to
ensure that neural-signal in an LFP sub-band (for e.g.: β band) is not phase shifted with respect to the
neural-signal in other LFP sub-bands (for e.g.: HFEO). Bessel filters are typically used in the analog
domain as AAF to obtain a linear phase response in the pass band (LFP band 10 – 600 Hz) of interest.
It is also known that the higher the order of the Bessel filter leads to a more linear phase response.
Therefore, we choose 6-pole (instead of a 5-pole or 4-pole) AAF, thus leading to an ADC sampling-rate
of 3 kSa/s per channel (shown in Figure 1-10), based on the SNR requirements (74 dB) of 12-bits.
Furthermore, implementing a slightly-complex 6-pole AAF for a 3 kSa/s per channel ADC is still better
than a 4-pole AAF with the ADC sampling at 6 kSa/s (twice that of 3 kSa/s) in the overall system
power-dissipation because, at 6 kSa/s sampling-rate, the other system level aspects like the clocking
power, the micro-processor timing sequence to parse and analyze the sensed data, bias-currents for the
3
[74 / (20*log (2)) = 13-pole filter for 30 kSa/s sampling-rate, 74 / (20*log (4)) = 6-pole filter for 50 kSa/s sampling-rate,
(74 / (20*log (7)) = 5-pole filter for 80 kSa/s sampling-rate or 74/ (20*log (14)) = 4-pole filter for 150 kSa/s sampling-rate].
19
ADC to sample at higher rate, will all increase. On the other hand, the neural-AP sensing is a duty-cycled
event (not active all the time), and cross-frequency-band correlation in the AP band (100 Hz – 10 kHz)
has not yet been proven useful. Therefore, if we consider the overall system power budget, we can relax
the order of the anti-aliasing filter to 4-pole (lower–power-dissipation and reduced design complexity
compared to 6-pole filter) resulting in an ADC sampling-rate of 150 kSa/s per channel to sense
neural-APs. Table 1.1 summarizes the minimum ADC sampling-rate requirements to achieve the desired
SNR of 12-bits, for a 32-channel neural-sensing closed-loop SCS and DBS applications.
Table 1.1: Sampling-rate determination for Neural LFP and AP sensing.
* 6-pole anti-aliasing filter.
+
4-pole anti-aliasing filter
Analog to Digital converter choices
Based on the analysis in Section 1.4, the ADC metrics needed to decode neural-signals of interest and
facilitate precise delivery of neural-stimulation therapy are:
◼ Minimum ADC resolution of 12-bits
◼ ADC Sampling-Rate of 50 - 100 kSa/s, 3 - 5 MSa/s
◼ Implementation process-technology such as 0.18 µm CMOS and above (0.18 µm,
0.25 µm, 0.35 µm, etc.), to enable integration with the Neural-Stimulation circuitry.
Based on the available, well-understood ADC architectures, the following ADCs satisfy the needs listed
above:
The SAR ADC is used for digitizing analog signals in applications that require sampling-speeds
Fs < 1 MSa/s, require 10-12 bits of resolution, have low power-dissipation of < 0.3 mW, have
implementation-area < 0.5 mm
2
(see Figure 1-11 for published 10-12-bit SAR ADC implementations with
a sampling-rate < 250 kSa/s). SAR ADC consists of a Capacitive Digital-to-Analog Converter (C-DAC),
Number
of
Channels
Neural-
Signal
type
Minimum ADC
Sampling-Rate
/ channel
Time Division
Multiplexed (TDM)
ADC Sampling-Rate
32 LFP
3 kSa/s
*
32 * 3 kSa/s
= 92 kSa/s
32 AP
150 kSa/s
+
32 * 150 kSa/s
= 4.8 MSa/s
20
comparator, and Successive Approximation Register (SAR) sub-blocks. SAR ADCs are suited for
applications that have non-periodic inputs, since conversions can be started at will. This feature makes
the SAR architecture ideal for converting a series of time-independent signals such as
neural-signals. SAR ADCs need minimum amount of analog circuitry (one comparator), hence energy
efficient as the rest of the sub-blocks are digital circuit-blocks. However, SAR ADC’s sampling-speed is
limited by the settling-time of the C-DAC array, which must settle to within the resolution of N-bits for
an N-bit converter. SAR ADC implementation-area increases with the resolution of the ADC, mainly due
to the increase in area of the C-DAC.
Figure 1-11: 10-12-bit SAR ADC implementations in literature.
The Algorithmic ADC is used for digitizing analog signals in applications that require
sampling-speeds (Fs) < 1-10 MSa/s, providing 10-12 bits of resolution, tolerate moderate power
consumption of < 15 mW, and have implementation-area < 0.2 mm
2
(see Figure 1-12 for published
10-12 bit Algorithmic ADC implementations with a sampling-rate < 15 MSa/s). Algorithmic ADC consists
of a sample-and-hold, multiply-by-2, comparator, shift-registers, and subtractor sub-blocks. Like the SAR
ADCs, the Algorithmic ADCs are suited for applications that have non-periodic inputs, since conversions
can be started at any point of time. This feature makes the Algorithmic ADC architecture ideal for
converting a series of time-independent signals like neural-signals. Algorithmic ADCs also need
minimum amount of analog circuitry (one comparator and switched capacitor circuits for S/H,
0
50
100
150
200
250
0
50
100
150
200
250
300
350
100 180 260 340 420 500 580 660
Sampling Rate (kSa/s)
Power Dissipation (µW)
Process Technology (nm)
Published 10-to-12 bit SAR ADC Implementations
(Sampling Rate under 250 kSa/s)
Power in µW
Fs in kSa/s
21
multiply-by-2 and subtractor) facilitating an energy efficient design, as the rest of the sub-blocks are digital
(shift-registers) circuit-blocks. The transistor Transition Frequency (FT) for a given process-technology,
the comparator’s bias-current, and its intrinsic gain dictates the comparator’s output settling-time, and in
turn the sampling-speed of the Algorithmic ADC. Furthermore, the sample and hold action followed by
multiply-by-2 action up-front in the Algorithmic ADC allows for a smaller sampling capacitor compared to
the SAR ADC. This alleviates the settling-time requirements on the sample and hold block, thereby
facilitating higher sampling-speeds compared to the SAR ADCs.
Figure 1-12: 10-12-bit Algorithmic ADC implementations in literature.
Dissertation Research Question
The goal of neural-stimulation therapy is to develop a closed-loop implantable system that
can reliably detect the precursors of neural-disorders, validate the precursors, and then
tranquilize the neural-disorder through neural-stimulation before it spreads.
Accurate precursor detection in closed-loop implantable biomedical systems is the key to ensuring
that the stimulation therapy is delivered reliably and ONLY when needed. Such implantable
devices require high-performance ADCs for continuous, real-time monitoring of relevant
neural-signals. The neural-sensing front-end architectures must
• continuously monitor biological signals
• consume low-power until the first precursor detection, and then
0
2
4
6
8
10
12
0
2
4
6
8
10
12
100 140 180 220 260
Sampling Rate (MSa/s)
Power Dissipation (mW)
Process Technology (nm)
Published 10-to-12 bit Algorithmic ADC implementations
(sampling rate under 15 MSa/s)
Power in mW
Fs in MSa/s
22
• switch to a higher sampling-rate monitoring mode to ensure the subsequent
precursors are sampled at a faster rate, and that the signature of the event-onset is
validated before delivering the appropriate neural-stimulation based therapy.
This doctoral dissertation proposes a shared-architecture Successive Approximation
Register / Algorithmic (SAR-A) ADC (shown in Figure 3-2) that combines
❑ the Successive Approximation Register (SAR) ADC architecture operating at
sampling-speeds < 1 MSa/s for sensing neural local field potentials and
❑ the Algorithmic ADC architecture operating at sampling-speeds between 1-10 MSa/s for
sensing neural action-potentials and neural spike-sorting,
providing 12-bits of resolution in each sampling-speed range, targeting lower area than alternate
implementation of two standalone ADCs, and lower power-dissipation in each mode of the shared
ADC than that of each of the standalone ADCs.
The dissertation question:
Can the proposed shared architecture SAR-A ADC be superior to the best available, two
standalone (the SAR only [27] and the Algorithmic only [37]) ADC architectures in
implementation-area and power-dissipation and still achieve similar resolution in each
sampling-speed range for the desired closed-loop implantable biomedical systems?
Hypothesis
The SAR-A ADC architecture is superior to the best available standalone ADC (SAR / Algorithmic)
architectures in implementation-area and power-dissipation and achieves similar resolution in
each sampling-speed range for the desired closed-loop implantable biomedical systems.
To test this hypothesis, we design and verify the SAR-Algorithmic (SAR-A) ADC architecture in the
0.35 μm CMOS XFAB XH035 process-technology using the 3.3 V thin-oxide transistors. The
0.35 μm CMOS process from XFAB foundry was chosen as the process-technology vehicle to
23
verify the SAR-A ADC architecture. This was mainly due to the availability of high-voltage Metal
Oxide Semiconductor (MOS) transistor process-modules in this process (along with 0.6 μm, and
0.8 μm CMOS process) that are typically used for neural-stimulation therapy delivery. With CMOS
technology scaling rapidly and with the availability of the high-voltage MOS transistor
process-modules in deep submicron process, like the 0.18 μm CMOS since early 2012, it is now
viable to utilize the 0.18 μm process as a test vehicle to realize the SAR-A ADC. Based on the best
available 12-bit ADC designs in the literature, we compare the following:
1. Best available standalone SAR ADC operating in the sampling-speed range of
50-to-100 kSa/S.
2. Best available standalone Algorithmic ADC operating in the sampling-speed range of
3-to-5 MSa/s.
3. Dual Architecture: Best available SAR and Algorithmic ADCs implemented independently
on the same die, each turned ON based on the analog signal bandwidth.
4. SAR-A Architecture: The proposed shared architecture SAR-Algorithmic (SAR-A) ADC.
We can see that:
[27] Implements a SAR ADC with 12-bits of resolution, sampling at 100 kSa/s, and with a power-
dissipation of 82.5 μW in the 0.18 μm CMOS process and [37] Implements an 11-bit, 3.3 MSa/s, 5.5 mW
Algorithmic ADC in the 0.25 μm CMOS process. It can be argued that [27] and [37] can be used as
standalone and implemented on the same die for a total of two separate ADCs and still achieve the
desired sampling-rates (100 kSamples/s and 3.3 MSamples/s) with resolution of 11-12 bits. The penalty
for this approach is the increase in implementation-area, as the referenced standalone ADCs together
would occupy a total of 0.78 mm
2
. In implantable biomedical systems where power-dissipation and area
reduction are of paramount interest, the approach of having two separate standalone ADCs does not
achieve the minimum ADC implementation-area and power-dissipation. Table 1.2 summarizes the best
available ADC architectures in the sampling-speed range of interest and compares them to the proposed
single-ended implementation of the SAR-A ADC architecture.
24
Table 1.2: Best available ADC architectures in the sampling-speed range of interest.
Architecture Resolution Speed
Power-dissipation
(normalized to 3.3V
Supply)
Core
Implementation-
Area
SAR ADC [27]
Standalone
12-bits 100 kSa/s 82.5 μW 0.63 mm
2
Algorithmic ADC
[37] Standalone
12-bits 3.3 MSa/s 5.5 mW 0.15 mm
2
Dual ADC --
Best available SAR
and Algorithmic [27]
[37] combined
12-bits
100 kSa/s
or
3.3 MSa/s
82.5 μW for
SAR ADC and
5.5 mW for
Algorithmic ADC
0.78 mm
2
The proposed
shared-architecture
SAR-A (SAR-
Algorithmic) ADC
Target
resolution
of 12-bits
100 kSa/s
or 5 MSa/s
Target power
consumption of
< 100 μW for SAR
ADC and
< 5 mW for the
Algorithmic ADC
Target area
< 0.45 mm
2
(considering a
single-ended
implementation of
the
SAR-A ADC
The measured results obtained from the realization of the SAR-A ADC to match the target
specifications (see the Table 1.3) will establish the truth or the falsehood of the hypothesis: that
“the SAR-A ADC architecture is better than the best available standalone ADC (SAR / Algorithmic)
architectures in implementation-area and power-dissipation and achieves a similar resolution
performance in terms of resolution in each sampling-speed range”. Table 1.3 lists the target
specifications for the SAR-A ADC based on the Section 1.4.
Table 1.3: Target specifications of the SAR-A ADC.
Mode SAR ADC Algorithmic ADC
Resolution 12-bits 12-bits
Speed 100 kSa/s 5 MSa/s
Power Consumption < 100 μW < 5 mW
Implementation-area < 0.3 mm
2
< 0.15 mm
2
25
2 Literature Survey on ADCs
Different types of ADC architectures have been published in the literature. Important aspects of the
design of an ADC are sampling peed, resolution, power consumption, linearity, INL, DNL, SNDR,
ENOB. Some ADCs provide a resolution-scalable capability [51,56], while other ADCs provide a
speed-scalable capability [53,58]. The two main types of data converters are:
1. Nyquist-Rate Converters: These types of converters generate a series of output values in
which each value has a one-to-one correspondence with a single input value. In most cases,
Nyquist rate converters operate at 1.5 to 10 times the Nyquist rate (i.e., 3 to 20 times the input
signal’s bandwidth). Examples of Nyquist-rate converters are:
➢ Successive approximation ADC
➢ Algorithmic ADC
➢ Integrating ADC
➢ Pipeline ADC
➢ Flash ADC
2. Oversampling Converters: These types of converters operate much faster than the input
signal’s Nyquist rate (typically 20 to 512 times faster) and increase the output’s signal-to-noise
ratio (SNR) by filtering out quantization noise that is not in the signal’s bandwidth. Examples
of oversampling converters are:
➢ Sigma-Delta ADC
➢ Time interleaved ADC
26
The published research literature was surveyed to tabulate ADCs that have resolution of at least 8 bits
along the three important vectors of ADC architecture, specifications and circuit techniques. They are:
• Architecture – To check the uniqueness of the proposed SAR-A ADC architecture (see
Figure 3-2).
• Specifications – To check if an implementation to achieve 12-bit resolution at 100 kSa/s
sampling-speed and 12-bit resolution at 5 MSamples/s sampling-speed; at optimal power
consumption at these sampling-speed ranges.
• Circuits – To tabulate the novel circuit design techniques in the ADC design found in literature.
The following journals and conferences were surveyed to validate the claims above, in the three
categories using the IEEExplore website. They are:
IEEE Journal of Solid-State Circuits (IEEE JSSC)
IEEE Transactions on circuits and systems – I and II (IEEE TCAS)
IEEE Transactions on biomedical engineering
IEEE Transactions on biomedical circuits and systems
IEEE International Solid States Circuits Conference (IEEE ISSCC)
IEEE Custom Integrated Circuit Conference (IEEE CICC)
IEEE International Symposium on Circuits and Systems Conference (IEEE ISCAS)
IEEE Very Large-Scale Integration Integrated Circuits Conference (IEEE VLSI)
Journal of low power electronics
Analog Integrated Circuits and Signal Processing
Contributions to the ADC Architecture
Table 2.1 lists various ADC architecture designs that are published in the literature. These contributions
bring out novelty in the architectural design of the ADC. As we can see from the table, the proposed
SAR-A ADC architecture has not been published in the literature up to year 2018.
27
Table 2.1: List of novel ADC architectures published in the literature.
Contributions to the ADC Specifications
Table 2.2 lists various ADC designs that are documented in the literature, which contribute to the
enhancements in the specifications (sampling-rate, power consumption, physical area, supply-voltage,
and process-technology of implementation) of the ADC.
ADC
Architecture
Novelty in Architecture
Sampling
Rate
(Sa/s)
Power
Consumption
(W)
Physical
Area
(mm
2
)
Power
Supply
(V)
Process
Technology
12-bit SAR-
Dual Slope
[24]
First 6 MSB bits
decided by SAR ADC
and 6 LSB bits decided
by Dual-Slope ADC
50 k 60 μ 0.8 1.8
0.18 μm
CMOS
10-bit SAR
[25]
Resistor-Capacitor
Hybrid DAC
architecture to achieve
10-bit resolution
250 k 1410 μ 1 1.8
0.18 μm
CMOS
8-bit SAR
[26]
Passive charge-sharing
DAC
50 M 0.7 m 1.32 1
90 nm
CMOS
12-bit
Algorithmic
[47]
Capacitance ratio-
independent ADC
40 k 68.4 μ 0.041 1.8
0.13 μm
CMOS
13.5-bit
Sigma Delta
[43]
Single-bit 2-2 cascaded
architecture
360 k 5 m 0.4 1.8
0.4 μm
BiCMOS
16-bit Sigma
Delta [38]
Cascaded modulator
with switched-capacitor
integrator architecture
50 k 2.5 m 1.5 1.8
0.8 μm
CMOS
10-bit SAR
[52]
Self-timed timing
control SAR ADC
architecture
70 k 300 μ 1.1 1.8
0.18 μm
CMOS
8-bit SAR
[53]
Asynchronous SAR
controller-based SAR
ADC architecture
4 M 28.4 μ 0.019 1
0.18 μm
CMOS
5-10-bit SAR
[56]
1-6-bit scalable DAC
architecture to achieve
5-10-bit resolution
20 k 0.2 μ 0.212 0.55
65 nm
CMOS
8-bit SAR
[57]
2b-per-cycle
conversion with
interpolated sampling
400 M 4 m 0.024 1
65 nm
CMOS
8-bit SAR
[58]
Differential switched
capacitor network
10 M 69 μ 0.07 1
90 nm
CMOS
10-bit SAR
[59]
Variable window
function
10 M 98 μ 0.086 1
0.18 μm
CMOS
8-bit
logarithmic
[46]
Local feedback
calibration
300 3 μ 4.84 3
1.5 μm
CMOS
10-bit SAR
[54]
Binary-scaled error
compensation DAC
100 M 1.13 m 0.026 1.2
65 nm
CMOS
28
Table 2.2: List of novel ADC design specifications published in the literature.
From Table 2.2, we can summarize the enhancements in the specifications for the ADC in the
sampling-speed range (50-to-100 kSa/S and 3-to-5 MSa/S) of interest as shown in Table 2.3.
Table 2.3: ADC specifications in the sampling-speed range of 50-100 kSa/s and 3-5 MSa/s.
ADC
Architecture
Enhancements in
Specifications
Sampling
Rate (Sa/s)
Power
Consumption
(W)
Physical
Area
(mm
2
)
Power
Supply
(V)
Process
Technology
8 and12 bit
SAR [27]
12-bit, 100 kSa/s,
25 μW
100 k 25 μ 0.2 1
0.18 μm
CMOS
8-bit SAR
[60]
8-bit, 100 kSa/s,
3.1 μW
100 k 3.1 μ 0.32 1
0.25 μm
CMOS
8-bit SAR
[51]
8-bit
(1 V, 150 kSa/s,
30 μW) or
(0.5 V, 4.1 kSa/s,
0.85 μW)
4.1 k 850 n 0.25 0.5
0.18 μm
CMOS
12-bit SAR
[44]
12-bit, 1 kSa/s,
100 nW
1 k 100 n 0.3 0.9
0.18 μm
CMOS
12-bit
Algorithmic
[31]
12-bit, 41.67 kSa/s,
32 μW
41.67 k 32 μ 0.055 1.8
0.13 μm
CMOS
12-bit Sigma
Delta [39]
12-bit, 25 kSa/s,
135 μW
25 k 135 μ 1 1.5
0.5 μm
CMOS
8-bit SAR
[48]
8-bit, 11.25 kSa/s,
166 nW
11.25 k 166 n NA 1.2
0.18 μm
CMOS
10-bit SAR
[50]
10-bit, 40 kSa/s,
32.6 μW
40 k 32.6 μ 0.35 1
0.18 μm
CMOS
11-bit
Algorithmic
[33]
11-bit, 10 MSa/s,
10.5 mW
10 M 10.5 m 0.19 3
0.13 μm
CMOS
12-bit
Algorithmic
[37]
12-bit, 3.3 MSa/s,
5.5 mW
3.3 M 5.5 m 0.15 2.5
0.25 μm
CMOS
10-bit SAR
[36]
10-bit, 50 MSa/s,
820 μW
50 M 820 μ 0.039 1
65 nm
CMOS
5-10-bit SAR
[56]
10-bit, 20 kSa/s,
200 nW
20 k 200 n 0.212 0.55
65 nm
CMOS
10-bit SAR
[59]
10-bit, 10 MSa/s,
98 μW
10 M 98 μ 0.086 1
0.18 μm
CMOS
ADC
Architecture
Resolution
Sampling
Rate
(Samples/s)
Power
Consumption
(W)
Physical
Area
(mm2)
Power
Supply
(V)
Process
Technology
SAR [27] 12-bit 100 k 25 μ 0.2 1 0.18 μm CMOS
Algorithmic [37] 12-bit 3.3 M 5.5 m 0.15 2.5 0.25 μm CMOS
29
Contributions to the ADC design that are circuit specific
Table 2.4 lists various ADC designs that are documented in the literature. These contributions bring out
the novel circuit design techniques in the ADC design. As we can see from the table, the proposed
chopper-stabilization technique on a clocked-comparator has not been published in the literature.
Table 2.4: ADC designs that introduce novel circuit design techniques.
Contributions of this Research Work
It is evident from the above research literature survey that the SAR-A ADC architecture has not
been implemented. Table 2.5 summarizes the contributions of this dissertation.
Table 2.5: Contributions of this dissertation.
Area of
Research in
ADCs
Dissertation contributions
Architecture
Shared-Architecture SAR / Algorithmic (SAR-A) ADC that shares two ADC architectures
implemented and optimized for the relevant sampling-speed ranges targeting lower area
than alternate implementation of two standalone ADCs and lower power-dissipation in
each mode of the shared ADC than that of each of the standalone ADCs.
Specifications
12-bit, 100 kSamples/s, < 100 μW SAR ADC, in 0.18 μm CMOS process.
12-bit, 5 MSamples/s, < 5 mW Algorithmic ADC, in 0.18 μm CMOS process.
Circuits
Chopper-stabilization technique on the clocked-comparator, to cancel the effects of
mismatch, input-referred DC-offset, and the 1/f noise contributions.
ADC
Architecture
Circuit Novelty
Sampling
Rate
(Sa/s)
Power
Consumption
(W)
Physica
l Area
(mm2)
Power
Supply
(V)
Process
Technology
10-bit
Algorithmic
[30]
Switched Opamp based
integrated ADC
2.9 k 17.8 μ 0.0348 2.8
0.8 μm
BiCMOS
10-bit SAR
[29]
P/ N-type Comparator 15 k 13.4 μ 0.4 1.5
0.18 μm
CMOS
11-bit
Algorithmic
[33]
Capacitor scaling and
sharing technique
10 M 10.5 m 0.19 3
0.13 μm
CMOS
8-bit
logarithmic
[46]
Temperature and local
feedback offset
compensation
300 3 μ 4.84 3
1.5 μm
CMOS
12-bit
Algorithmic
[28]
Two-cycle residual
amplifier
800 k 1.9 m 2.13 3.3
2 μm
CMOS
12-bit SAR
[32]
Error correction circuit to
introduce redundancy
200 k 6.6 m 2 3.3
0.13 μm
CMOS
12-bit SAR
[42]
Self-timed comparator 1 M 15 m 0.5 3.5
0.6 μm
CMOS
30
3 The SAR-A ADC Architecture
The shared-architecture Successive Approximation Register / Algorithmic (SAR-A) ADC block
diagram and architecture are shown in Figure 3-1 and Figure 3-2, respectively. The “S” switch in
Figure 3-2 activates the SAR ADC mode of operation, and the “A” switch in Figure 3-2 activates
the Algorithmic mode of operation.
Figure 3-1: High-level block diagram of the SAR-A ADC showing the input and output signals.
Clock Generator
Shift
Registers
ClkA
Digital to Analog
Converter (DAC)
using Binary
Weighted
Capacitive Array
Successive Approximation
Register (SAR) Control Block
ClkS
Multiply-
by-2
ClkA
Analog
Input
(V in)
S
A
A
S
S Switch for SAR ADC operation
A Switch for Algorithmic ADC operation
Reusable blocks between the two modes of operation
Sample
and Hold
Circuit
A
Reset
Start
D<12:1>
12-bit SAR
ADC Output
Serial
12-bit
Algorithmic
ADC
Output
V ref
ClkS
SAR-A ADC
Main Clock
ClkS ClkA Reset Start
Latch_Clk
Chopping technique employed to compensate for the mismatch,
the input-referred DC offset, and the 1/f noise contributions
S
A
SAR
EOC
Algo
EOC
Chopper Stabilized
Comparator
Amp Latch
f
ch
LPF
f
ch
f
ch
Latch_Clk
Figure 3-2: Architectural block diagram of the SAR-A ADC.
Analog
Input
(Vin)
Parallel, 12-bit
SAR ADC
Output
12-bit, 100 kSa/s
SAR ADC
12-bit, 5 MSa/s
Algorithmic ADC
SAR-A ADC
S
A
Shared Circuit
Blocks
Serial, 12-bit
Algorithmic
ADC Output
Reference
Voltage
(Vref)
SAR-A
Main Clk Power
SAR EOC
Algo EOC
EOC – End of Conversion
Sensing Neural LFP
Sensing Neural AP
12
31
Figure 3-2 shows the architectural block diagram of the SAR-A ADC, where Vref is the reference
voltage, Vin is the analog-input to the ADC, Digital bits D<12:1> is the 12-bit SAR ADC output, and
Dout is the serial output of the Algorithmic ADC. ClkA is the sampling clock-signal of the Algorithmic
ADC, while ClkS is the sampling clock-signal of the SAR ADC. Switches “S” and “A” are mutually
exclusive (i.e. when “S” is open, “A” is closed and vice-versa) and are energized by a control block
outside the SAR-A ADC. The design of the control block is outside the scope of this research work.
Table 3.1: Different modes of the SAR-A ADC based on the switch positions.
Switch S Switch A Mode of Operation
Open Open No ADC operation
Open Closed Algorithmic ADC
Closed Open SAR ADC
Closed Closed Not Valid
Table 3.1 summarizes the different modes of operation of the SAR-A ADC. The shaded area in the
proposed SAR-A ADC architecture shown in Figure 3-1 and Figure 3-2 corresponds to the
reusable circuit-blocks (the shared comparator with the mismatch, input-referred DC-offset and
1/f noise-compensation circuitry) between the two modes of operation (i.e., the SAR and the
Algorithmic). Table 3.2 shows the relationship of clock-signals in the SAR-A ADC shown in
Figure 3-2.
Table 3.2: Relationship of clock-signals in the SAR-A ADC.
Clock-signal
SAR-A ADC Modes
SAR ADC Algorithmic ADC
SAR-A ADC Main Clock-
signal (External Clock)
200 MHz (50% duty cycle) 200 MHz (50% duty cycle)
ClkS
+
100 kHz (50 % duty cycle) Not Active
ClkA
+
Not Active 5 MHz (50% duty cycle)
fch
+
5 MHz (50% duty cycle) 200 MHz (50% duty cycle)
Latch_Clk
+
60% - 40% duty cycle of
Sar_Int_Clk
#
ɸ2*
# Sar_Int_Clk is the 2 MHz internal clock-signal for the SAR ADC.
* Algorithmic ADC uses ɸ1, ɸ2, ɸ3 clock-signals, internally generated from the main clock-signal.
+
Derived internally from the SAR-A ADC Main Clock-signal.
32
SAR-A ADC architecture highlights
This section details the proposed architecture shown in Figure 3-2. The highlights of the proposed
shared-architecture are in
1. Combining the two ADC architectures: The SAR ADC operating at sampling-speed < 1 MSa/s
and the Algorithmic ADC operating at sampling-speeds between 1-10 MSa/s.
2. Re-using analog circuit-blocks between the SAR and Algorithmic ADC to reduce the
implementation-area.
Combining the two ADC architectures
The proposed SAR-A ADC architecture shown in Figure 3-2 combines the SAR ADC operating at
sampling-speeds < 1 MSa/s and the Algorithmic ADC operating at sampling-speeds between
1-10 MSa/s providing 12-bits of resolution for each sampling-speed range. Table 3.3 lists the target
specifications for the SAR-A ADC based on the results of the Section 1.4.
Table 3.3: Target specifications of the SAR-A ADC.
Mode SAR ADC Algorithmic ADC
Resolution 12-bits 12-bits
Speed 100 kSa/s 5 MSa/s
Power Consumption < 100 μW < 5 mW
Implementation-area < 0.3 mm
2
< 0.15 mm
2
Re-using the analog circuit-blocks to save implementation-area
In the proposed SAR-A ADC architecture shown in Figure 3-2, we can see that there are shaded
areas in the SAR-A ADC block diagram. The reduction in the implementation-area of the
SAR-A ADC is achieved by sharing the circuit-blocks between the two modes of operation (i.e., the
SAR or the Algorithmic mode). These reusable circuit-blocks are the clock-signal-generation
circuitry, the comparator, and the chopper stabilization circuit employed to compensate for effects
of the mismatch, input-referred DC-offset, and the 1/f noise contributions.
33
4 The SAR-A ADC circuit design
SAR ADC mode of the SAR-A ADC
Figure 4-1 shows the architecture of the Successive Approximation Register (SAR) Analog to
Digital Converter (ADC) mode of the SAR-A ADC. The SAR ADC circuit consists of four blocks:
a. A sample and hold circuit (S/H) to sample the analog-input voltage (Vin).
b. An internal Capacitive Digital-to-Analog Converter (C-DAC) that supplies
the comparator with an analog voltage equivalent of the digital code output for comparison
with the reference voltage (Vref).
Shift
Registers
ClkA
Digital to Analog
Converter (DAC)
using Binary
Weighted
Capacitive Array
Successive Approximation
Register (SAR) Control Block
ClkS
Multiply-
by-2
ClkA
Analog
Input
(V in )
S
A
A
S
S Switch for SAR ADC operation
A Switch for Algorithmic ADC operation
Active Blocks during the SAR ADC mode of operation
Sample
and Hold
Circuit
A
Reset
Start
D<12:1>
12-bit SAR
ADC Output
Serial
12-bit
Algorithmic
ADC
Output
V ref
ClkS
Clock Generator
SAR-A ADC
Main Clock
ClkS ClkA Reset Start
Latch_Clk
Chopping technique employed to compensate for the mismatch,
the input-referred DC offset, and the 1/f noise contributions
S
A
SAR
EOC
Algo
EOC
Chopper Stabilized
Comparator
Amp Latch
f
ch
LPF
f
ch
f
ch
Latch_Clk
Figure 4-1: Architectural block diagram of the SAR ADC mode of the SAR-A ADC.
c. A successive approximation register (SAR) digital block designed to supply an approximate
digital code to the internal C-DAC.
d. A comparator circuit that compares the reference voltage (Vref) to the sampled input, and
provides the result of the comparison to the successive approximation register (SAR)
control block.
34
Digital to Analog Converter (DAC)
using Split-Capacitor Binary-Weighted
Capacitive Array
Chopper-Stablized Dynamic
Latched Comparator
ClkS
Analog
Input
(V in)
Sample and Hold
Circuit (S/H)
Reset
Start
D<12:1>
12-bit SAR ADC
Output
V ref
Sampling
Clock
Latch_Clk
Latch
f ch
f ch
Successive
Approximation
Register (SAR)
Control Block
V a
LPF Amp
SAR EOC
(Signal to indicate
the data is ready)
f ch
Figure 4-2: Block diagram of the Successive Approximation Register Analog to Digital
Converter.
C 12 C 11
C A
C 1 C 2
12-bit
Binary-Weighted
Split-Capacitor
Array
GND VREF VIN
MSB DAC LSB DAC
VREF
GND
VREF
GND
Vlatch_Clk
Vlatch_Clk Vlatch_Clk
V a
I1
Vdd
Vout1 Vout2
f ch
f ch_bar
VREF
Xin1 Xin2
X3 X4
X1 X2
f ch
f ch_bar
f ch_bar
f ch
f ch_bar
f ch
Xtail
Digital to Analog Converter (DAC)
using Split-Capacitor Binary-Weighted
Capacitive Array
Chopper-Stablized
Dynamic Latched
Comparator
ClkS
Analog
Input
(V in )
Sample and
Hold
Circuit (S/H)
Reset
Start
D<12:1>
V ref
Sampling
Clock
Latch_Clk
Latch
f ch
f ch
Successive
Approximation
Register (SAR)
Control Block
V a
LPF Amp
f ch
Figure 4-3: Detailed schematics of the C-DAC and the comparator sub-blocks in the SAR ADC.
35
Figure 4-2, shows a block diagram of the SAR ADC, where Vref is the reference voltage, Vin is the
analog-input to the ADC, digital bits D<12:1> is the 12-bit SAR ADC output. The choice of Vref
should equal or exceed the dynamic range of the analog-input voltage Vin (0 V to 0.9 V). Choosing
Vref equal to the maximum value of analog-input voltage of 0.9 V yields resolution of 220 µV/bit for
the 12-bit SAR-A ADC. The analog-input signal Vin is sampled at the beginning of each conversion
cycle. Conversion starts with the comparator comparing the input signal Vin to the reference
voltage (Vref), which determines the Most Significant Bit (MSB) of Vin. Based on the result, the
search region for the second MSB is evaluated. Each comparison between Vin and the updated
reference voltage generates one bit of Vin, so the N-bit SAR ADC will need N comparisons. The
two principal factors that determine the sampling-speed of the SAR ADC are: the ability of the
comparator to resolve within +/- ½ LSB of the reference voltage, within each conversion cycle and
TAcquisition, the internal C-DAC’s acquisition-time. TAcquisition is defined as the time required by the
C-DAC array to reach the final-value within +/- ½ LSB of the analog-input for the desired 12-bit
resolution. The acquisition time (TAcquisition) includes the sampling-switch delay-time, the
slewing-time, and the settling-time (Ts) to attain the desired precision in sampling the analog-input.
Figure 4-3 shows detailed schematics of the SAR ADC’s internal C-DAC, and the Comparator
block in the SAR ADC. To reduce the SAR ADC’s internal C-DAC implementation-area, a split-
capacitor binary-weighted capacitor array is implemented. The sample-and-hold circuit and the
internal C-DAC circuit are combined and implemented as a split-capacitor binary-weighted
capacitor-array, wherein an N-bit C-DAC is divided into an M-bit MSB sub-C-DAC and a K-bit LSB
sub-C-DAC with an attenuation capacitor in between the sub-C-DACs. Appendix A discusses the
analysis and the design of the internal C-DAC of the SAR ADC using the split-capacitor
binary-weighted array. The output of the binary-weighted capacitor array C-DAC (Va) is provided
as an input to the chopper-stabilized, dynamic latched-Comparator, where Va is compared with the
reference voltage (Vref) for each bit determination. Different capacitor layout topologies and metal
layer combinations were investigated, and their capacitance values were extracted to determine
the best capacitor layout topology that yields a capacitor unit cell with the highest capacitance
per-unit-area in the selected CMOS process with minimized parasitic capacitance to substrate. The
36
following layout techniques were used to minimize edge effects and layout related constraints (such
as guarding the sensitive nodes from substrate noise, shielding the sensitive signals to avoid
cross-talk). They are:
a. the addition of dummies devices (transistors, resistors, capacitors) around devices that
needed to be matched (to minimize the difference in the device parameters).
b. the addition of double guard bands (P-substrate and N-well strips) [95, 96] around
devices that interfaced with the sensitive nodes,
c. the addition of shielded traces for the reference voltage, the reference current, and the
analog-input all the way from the pad.
Please refer to Section 5.1 for a more detailed discussion of the layout of the chip. This dissertation
proposes and implements a chopper-stabilization technique on the clocked-comparator, to cancel
the effects of mismatch, input-referred DC-offset, and the 1/f noise contributions. Appendix B
details the system-level analysis and the circuit-design of implementation of the key block of the
shared comparator in the SAR-A ADC.
Algorithmic ADC mode of the SAR-A ADC
The Algorithmic analog to digital converter is also known as the cyclic converter. The block diagram of
the Algorithmic ADC mode of the SAR-A ADC is shown in Figure 4-4 . The algorithmic ADC consists of
a sample-and-hold circuit, a multiply-by-2 circuit, a comparator, and a reference-subtraction circuit. The
operation of the Algorithmic ADC (shown in Figure 4-5) involves sampling the input signal using the
multiply-by-2 circuit. Selecting the input signal, instead of the loop signal using the select switch
(Loop_Clk), does this operation (see Figure 4-5). The sampled input signal is then amplified by the
C+C capacitive addition) multiply-by-2 circuit. To extract the digital information from the input signal, the
resultant voltage at node “a”, denoted by Va, is compared to the reference voltage (Vref) by the
comparator. If Va is larger than the reference voltage, the corresponding bit is set to “logic 1” and the
reference is then subtracted from Va; otherwise, the corresponding bit is set to “logic 0” and the node
voltage Va is kept unchanged. The resultant voltage at node “z” denoted by Vz is then transferred, by
means of the switch controlled by the Loop_Clk, back into the analog loop for further successive bit
37
determinations. This process continues until the desired numbers of bits have been obtained, whereupon
a new sampled value of the input signal is processed. Thus, the digital-output (Dout) is available in a
serial manner, with the Most Significant Bit (MSB) available first.
Clock Generator
Shift
Registers
ClkA
Digital to Analog
Converter (DAC)
using Binary
Weighted
Capacitive Array
Successive Approximation
Register (SAR) Control Block
ClkS
Multiply-
by-2
ClkA
Analog
Input
(Vin)
S
A
A
S
S Switch for SAR ADC operation
A Switch for Algorithmic ADC operation
Active Blocks during the Algorithmic ADC mode of operation
Sample
and Hold
Circuit
A
Reset
Start
D<12:1>
12-bit SAR
ADC Output
Serial
12-bit
Algorithmic
ADC
Output
Vref
ClkS
SAR-A ADC Main Clock
ClkS ClkA Reset Start
Latch_Clk
Chopping technique employed to compensate for the mismatch,
the input-referred DC offset, and the 1/f noise contributions
S
A
SAR
EOC
Algo
EOC
Chopper Stabilized
Comparator
Amp Latch
f
ch
LPF
f
ch
f
ch
Latch_Clk
Figure 4-4: Architectural block diagram of the Algorithmic ADC mode of the SAR-A ADC.
Both the sample-and-hold and the multiply-by-two circuit-blocks are usually realized using matched-
capacitors and MOS operational amplifiers. The reference-subtraction circuit is incorporated into the
multiply-by-two amplifier by attaching the capacitor to the input-summing node of the operational
amplifier. The gain values are defined by the ratio of capacitors. They can be only as accurate as the
matching of the capacitors. Thus, the signal in the traversing loop, suffers from loop-gain error, which is
the sum of the gain errors of the sample-and-hold and the multiply-by-two amplifiers. Similarly, the input-
referred DC-offset voltage of the operational amplifiers which are in the order of 5 - 10 mV along with the
thermal and the flicker noise contributions of the input-pair of the operational amplifiers contribute to the
loop-offset error. Loop-gain errors and the loop-offset errors lead to missing codes in the digital-output of
the Algorithmic ADC. This dissertation implements a 5 MSa/s, 12-bit Algorithmic ADC. Both the
multiply-by-2 and the subtractor circuit blocks are implemented as MOS transistor switches and
38
capacitors without the need for operational amplifiers. The difficulty with operational amplifiers is that
they must be designed to have very low input-referred noise performance typically (determine the fraction
of LSB), low leakage-current, low gain-error, low offset-voltage and very low power-dissipation. In return,
they offer very good current drive and isolation between nodes. Switched-capacitor circuits, on the other
hand, must be designed to have low thermal and 1/f noise contributions from the switches and minimal
charge-sharing between the internal nodes. This dissertation implements the switched-capacitor based
circuit design for the multiply-by-2 and the subtractor circuit-blocks (Figure 4-5) as opposed to an
Opamp-based design that can also achieve the required characteristics with the associated mismatch,
input-referred DC-offset and the 1/f noise-compensation circuitry.
a
Loop_Clk
1
1
1
2
3
3
C1
C1
C2
C2
x
Vin
Vref
3
3
3
Amp
fch
fch
fch
2
Latch LPF
fch
C1
C1
1
2
2
2
2
2
3
x1
x2
x3
z
z1
z2
z3
y
a1
Clock signal1
Clock signal2
Clock signal3
3
1
2
3
3
Data Out
Serial
(Dout)
Figure 4-5: Schematic representation of the Algorithmic ADC with the designed shared
comparator.
Design challenges implementing the SAR-A ADC architecture
4.3.1 Sub-threshold drain-to-source leakage current of the SAR ADC’s internal C-DAC
affecting the quantization error of the SAR ADC mode
Due to the finite resolution of the C-DAC in the SAR ADC, there will always be deviation from the
quantized C-DAC output to the input voltage to the C-DAC. This deviation is termed as quantization
39
error. The maximum quantization error for an ideal ADC is +/- 0.5 LSB. Therefore, the goal is to
keep the quantization error less than +/- 0.5 LSB. During the sample and hold phase, the N-Channel
MOSFET (NMOS) transistor switch’s Sub-Threshold Drain-to-Source Leakage (SDSL) current in
the branch of the Most Significant Bit (MSB) capacitor, in the binary-weighted C-DAC array
(Figure 4-3) in the SAR ADC is the main cause of the ADC quantization error. This is because
SDSL current removes the charge during the hold phase, that represents the sampled signal
voltage resulting in quantization error. Analytical considerations for target quantization-error
(please refer to Appendix A, Section 9.1, for the derivations and determination of the analytical
considerations for the quantization-error) less than or equal to +/- 0.2 LSB (constituting for the
design target of 40% of the +/- 0.5 LSB quantization error for an ideal ADC) indicate that the
maximum SDSL current in the switches (switches associated with the C12 capacitor in the 12-bit
binary-weighted split-capacitor C- DAC array, see Figure 4-3) is 0.1 nA. The sizing of
NMOS-transistor switches needs to comprehend the impact of the SDSL current on the output of
the C-DAC. Comparing the simulated quantization error at the output of the C-DAC for two distinct
cases – with and without ideal switches, verified that the 16 µA SDSL current of the non-ideal
switches resulted in the three LSB quantization error at the output of the C-DAC. The SDSL current
of 16 µA in the non-ideal switches in the C-DAC exceeded the maximum allowable SDSL current
by a factor of 16x10
4
. The SDSL current was reduced from 16 µA to 80 pA by increasing the gate
length of the NMOS-transistor switch to 2 µm from 0.35 µm. (Please refer to Appendix A,
Section 9.2, for detailed analysis of SDSL current in the C-DAC). The tradeoff in this exercise is
the increased drain-to-source ON resistance of the switch due to the increase in gate length. This
NMOS-transistor switch (Vin switch associated with the C12 capacitor in the 12-bit binary-weighted
split-capacitor array, see Figure 4-3) is ON in the sampling phase of the ADC operation. Increasing
the gate length could increase the drain-source voltage drop across the switch. This results in the
inability of the capacitor connected to the drain of the NMOS-switch to charge up to the sampled
value of Vin in the sampling phase, resulting in quantization error at the output of the C-DAC. These
considerations force a tradeoff between choosing the right gate-length of the switch transistor to
minimize SDSL current and ensuring that the ON resistance during sampling operation does not
40
contribute to increased quantization error (less than the ideal ADC’s quantization error of
+/- 0.5 LSB) in the sampling phase. Detailed simulations across Process, Voltage and Temperature
(PVT) corners indicate that the quantization error at the output of the C-DAC is reduced to 52 µV
(corresponding to quantization error of 0.25 LSB) for switch transistor (in branch of the MSB
capacitor) gate-length of 2 µm. The circuit was simulated at an initial condition of 0.9 V
(corresponding to the maximum analog-input voltage at the input of the C-DAC) at the output of the
C-DAC
4.3.2 Comparator design challenges affecting the SAR and the Algorithmic ADC modes’
performance
The two principal factors that determine the deviation from the inherent quantization error
(+/- 0.5 LSB for the ideal ADC) of the SAR-A ADC are: the internal C-DAC’s finite resolution, and
the inability of the comparator to resolve within +/- 0.5 LSB of the reference voltage, within each
conversion cycle. Ideally, a comparator has infinite gain resulting in zero decision errors. This is
because the comparator output yields a logic-high when the comparator’s input voltage is greater
than the reference voltage and yields a logic-low when the comparator’s input voltage is smaller
than the reference voltage. Practically, a comparator has finite gain resulting in decision errors
when the comparator’s input-voltage is on the either side of the reference voltage. A latch-based
clocked-comparator provides higher gain than a traditional analog comparator by using a
clock-signal to leverage positive feedback. Furthermore, to facilitate correct bit decisions in each
comparison phase, the input to the comparator must have sufficient amplitude (greater +/- 1 LSB
from the reference voltage) to overcome deterministic errors such as offset, hysteresis, and random
errors due to device flicker and thermal noise in the clocked-comparator’s decision [100]. The use
of clock-signal in the clocked-comparator exposes the performance of the comparator to the
additional factors of clock-signal’s timing-jitter, finite rise and fall times of the clock-signal edge,
variation in the desired clock-signal duty-cycle that potentially affect or limit its performance in the
decision making process [101]. These errors in decision making contribute to the deviation from
the inherent quantization error in the ADC result.
41
The main causes for the deviation from the inherent quantization error originating from the
clocked-comparator circuit (see Figure 4-3) are:
a. The inability of the clocked-comparator design to resolve input level within +/- 0.5 LSB
(constituting for the inherent quantization error of an ideal ADC) of Vref (0.9 V) input.
b. Low large-signal output-impedance of the tail-current-source transistor (see Figure 4-3) in
comparison to the ideal current source during the non-linear transient operation of the
clocked-comparator.
The comparator design approach and analysis to overcome the above causes of the quantization
error is detailed in Appendix B, from page 123. To identify the specific design parameters to
achieve the target specifications, the following steps were followed in the design approach of the
comparator.
Step 1: Transistor DC and small-signal (AC) analysis
The transistor small-signal analysis equations were derived for:
a. The cross-coupled inverter pair
b. The cross-coupled inverter pair with input transistors
c. The latch-based comparator circuit used in this work
This step was to understand how a transistor’s transconductance (gm) and
On-Resistance (ro) influence the small-signal voltage gain (Av) of the comparator. Circuits
corresponding to items “a” and “b” were first analyzed to obtain an understanding of the
small-signal characteristics. Sizing the transistors in the comparator circuit was based on
the small-signal voltage gain (Av) expression for the latch-based comparator circuit
corresponding to item “c”, to maximize the small-signal voltage gain. The analysis for the
small-signal voltage gain (Av) of the comparator is shown in Appendix B, Section 10.1.2,
page 129, where the small-signal voltage gain (Av) is
min1 mx3 ox3 mx1 ox1 ox1 ox3 mx3 mx3 mx1
v
mx3 mx1 mx3 ox3 mx1 ox1
g [g r g r - (r r g ) (g - g )]
A
(g - g ) (g r - g r )
+
= Equation (1)
42
Step 2: Impedance calculation looking upward from the drain of the tail current source transistor
shown in Figure 4-3 for the comparator
The tail current source transistor should be able to provide a constant current of 6 µA
(based on the slew-rate specification of 0.18 V/ns). Using small-signal analysis, the
impedance of the circuit looking up from the drain of the tail current transistor was derived.
Through DC simulations, the value of this impedance was calculated to be 570 kΩ. This
impedance was 30 times larger than the small-signal drain-to-source resistance (18 kΩ) of
the tail current source transistor. With this high-impedance looking up from the drain of the
tail current transistor, the node voltage is forced to ground (0 V). For the transistor to
function as a tail current-source, its small-signal drain-to-source impedance must be much
higher (by a factor of 10) than the impedance looking into the circuit connected to its drain.
Sizing the transistors for minimizing the impedance looking up from drain of the tail current
source transistor, increase the small-signal drain-to-source resistance to 210 kΩ, ensuring
the tail current source transistor is in saturation (Vds > Vgs – Vth) and provide a constant
current of 6 µA to the comparator circuit to satisfy the slew-rate requirement of 0.18 V/ns.
The impedance (Z) looking up from the drain of the tail current source transistor is given
by the following equation (derivation shown in Appendix B, Section 10.1.4).
Z =
y
ox3 oln1
y mln1 oln1 mx1 ox1 oin1
V
(r r )
I [(g r ) (1 - g (r - r ))]
+
=
Equation (2)
Step 3: DC simulations
DC simulations were performed to determine the transfer characteristics of the comparator
circuit shown in Figure 4-3 across Process, Voltage, and Temperature (PVT). The first
derivative of this plot is the voltage gain of the circuit. For the Worst-Case power (Wp)
process corner at junction temperature of 80 ºC, DC simulations verified that the
worst-case DC gain of the comparator is within 10 % (DC gain of 182) of the analytical DC
gain value of 201 from the small-signal voltage gain (Av) equation derived in Step 1 for the
latch-based comparator (using values of gm and ro for each transistor).
43
Step 4: Transient simulations
Transient simulations of the comparator were performed to validate the comparator design
to resolve the input level within +/-0.5 LSB of the Voltage Reference (Vref) of 0.9 V. The
transient simulations were also performed to check if the rise times and fall times of the
comparator output met the slew-rate requirement of 0.18 V/ns. For Vref of 0.9 V, transient
simulations showed that the design could resolve the input level within +/- 200 µV of Vref,
thus enabling the comparator to resolve input level within +/- 0.5 LSB of Vref.
4.3.3 Charge-sharing between the multiply-by-2 and the comparator block in the
Algorithmic ADC affecting the quantization error of the Algorithmic ADC
mode
The comparator's input is tied to the output of the multiply-by-2 circuit (see Figure 4-5), loading the
output of the multiply-by-2 circuit. Due to the conservation of charge between the capacitor (C1) of
the multiply-by-2 and the gate capacitance (Cgg) of the comparator's input transistor, the node
voltage Vx1 (output of the multiply-by-2,) is lowered (C1*Vx1/ (C1+Cgg)). This results in maximum
error of 2 mV (9 LSB) at the output of the multiply-by-2 for Vin=0.9 V. To overcome this problem,
the input to the comparator is gated from the output of the multiply-by-2. Therefore, the algorithmic
ADC loop sees the comparator input capacitance only after the multiply-by-2 operation has
completed. The comparator must be compensated for mismatch, input-referred DC-offset and the
1/f noise contributions, by way of implementing the chopper-stabilization circuit in the comparator.
This means that a chopper circuit block is introduced before the input of the comparator. This
chopper block (shown in Figure 4-5) will isolate the loop node (output of the multiply-by-2) from the
comparator input, eliminating charge sharing error at the comparator input.
4.3.4 The effects of input-referred DC-offset, mismatch and 1/f noise contribution on the
SAR and the Algorithmic ADC modes
From Figure 3-2, we see that the single-ended analog-input signal is first sampled by the sample
and hold circuit. The issue of mismatch in the sample and hold circuit stage does not arise because
of the single-ended signal processing in the sample and hold circuit stage. The comparator block
is the second stage in the signal flow after the sample and hold stage, where the sampled input is
44
compared with the reference voltage (Vref). Any mismatch inherent to the comparator block makes
a decisive impact in creating an error in comparison at the output of the comparator. This error will
directly add to the quantization error of the SAR and the Algorithmic ADC, limiting the accuracy of
the analog to digital conversion. Thus, the comparator is the dominant part of the SAR-A ADC
architecture that provides the largest offset contribution. The input-referred DC-offset voltage
compensation for the comparator is essential to reduce the overall offset contribution of the
SAR-A ADC. On the other hand, one can choose to avoid on-chip input-referred DC-offset
compensation and resort to calibration to remove the offset during wafer level testing or periodically
during operation. The consequences of this approach are that we need additional calibration
circuitry on-chip which will increase the overall ADC implementation-area and power-dissipation.
This will also increase the wafer-level testing time to perform the calibration of each die on wafer
[85, 87, 88]. There is also a potential yield hit due to this approach because the offset of the
comparator will limit the dynamic range of the comparator. Furthermore, the 1/f noise contribution
near or below the 1/f noise corner-frequency (for a MOSFET at a Process Voltage and Temperature
(PVT)) is many times the thermal-noise contribution for the same MOSFET. This means that any
circuit that employs a sampling clock frequency close to 1 MHz will have to cancel the 1/f noise
contribution affecting the ADC performance. The variance (σ
2
) expression (Equation (3)) of the
input-referred DC-offset for the shared comparator is derived in Appendix C, Section 11.2.4, from
page 163.
The suitability of the Auto Zeroing (AZ) / correlated Double Sampling (CDS) and chopper
Stabilization (CHS) techniques [16] were analyzed (Appendix C, Section 11.1.5, page 147) to
compensate for the mismatch, input-referred DC-offset and 1/f noise contributions of the
comparator on the overall performance of the SAR-A ADC.
( 1) ( 3) ( 1)
( 3) ( 1) ( 1)
( 3) ( 1) ( 1)
22
( 1) ( 1) 2 2 2 2
( ) ( ) ( ) ( )
( 3) ( 1)
2
2 2 2
( ) ( ) ( )
( 1)
os thn Xin thp X thn X
p X n X n Xin
p X n X n Xin
mn Xin mn Xin
V V V V
mp X mn X
K K K
m Xin
K K K
gg
gg
I
g
= + +
+ + −
Equation (3)
45
Figure 4-6: Chopper-Stabilization technique on the designed shared comparator.
With the comparisons made on the three techniques, it is apparent that a CHS can eliminate the effects
of mismatch; input-referred DC-offset and cancels the 1/f noise contribution. Modulating the signal to a
higher frequency by m1(t) (shown in Figure 11-4) (frequency where 1/f noise contribution is insignificant)
and then demodulate back (m2(t) also shown in Figure 11-4) to the baseband after comparison
eliminates the 1/f noise contribution effect on the shared-comparator. Based on the evaluation, the
chopper stabilization compensation technique (shown in Figure 4-6) is employed with an on-chip
low-pass filter, to cancel the effects of mismatch, input-referred DC-offset, and 1/f noise contributions on
the shared clocked-comparator. The transfer function of the implemented 3
rd
order Low Pass Filter (LPF)
to provide 60 dB attenuation at the 3
rd
harmonic of the chopping frequency is shown Equation (4).
Equation (4)
Where the coefficients of the filter for maximally flat pass-band response are k=1, a1=2, a2=2, a3=1.
Wc = 2*π*fc is the cut-off frequency of the LPF. fc = 1.5 MHz is the cut-off frequency of the LPF for
the SAR ADC mode providing 60 dB attenuation for the 3
rd
harmonic of the chopping frequency
(fch) of 5 MHz fc = 65 MHz is the cut-off frequency of the LPF for the Algorithmic ADC mode providing
60 dB attenuation for the 3
rd
harmonic of the chopping frequency (fch) of 200 MHz
.
23
1 2 3
()
1 ( ) ( ) ( )
c c c
k
Hs
s s s
a a a
w w w
=
+ + +
46
5 Measurement Results
Physical design of the SAR-A ADC in CMOS XFAB XH018 process
Figure 5-1: Die Micrograph of the SAR-A ADC chip showing various core modules.
The die microphotograph of the SAR-A ADC is shown in Figure 5-1 . The analog-input is located
on the left-corner of the die. All the clock-signals, clock power and clock ground are brought in from
the bottom side of the die to provide maximum isolation and to avoid any crosstalk with the
analog- input. To minimize the substrate-noise injection the sensitive analog front-end input stages
have their dedicated power and ground pins at the IC level supplied from the top side of the die.
These power and ground pins are dedicated pins even at the package level. The digital I/O pads
have their own separate power (VDDIO) and ground (VSSIO) pads. The analog-input is protected
from crosstalk by two ground pads on the either side. The overall die size of the SAR-A ADC with
pads is 2.8 mm x 2.4 mm. The SAR-A ADC core area without pads is
800 μm x 380 μm = 0.31 mm
2
. Each of the modules of the SAR-A ADC along with the other circuit-
blocks are highlighted in the die microphotograph (see Figure 5-1). The SAR-A ADC is fabricated
47
in 0.18 μm CMOS XFAB XH018 process-technology. The following layout techniques were used
to minimize edge effects and layout related constraints (such as guarding the sensitive nodes from
substrate noise, shielding the sensitive signals to avoid cross-talk). They are the addition of
dummies devices (transistors, resistors, capacitors), double guard bands (P-substrate and N-well
strips) around devices interfacing with the sensitive nodes, shielded traces for the reference
voltage, reference current, and analog-input all the way from the pad. The following critical design
aspects were resolved in the physical design to achieve 12-bit operation.
a. Evaluating the layout topology for the capacitors used in the SAR-A ADC;
b. Minimizing the SAR ADC mode’s internal C-DAC capacitor-array mismatch, and
parasitics to achieve 12-bit ENOB;
c. Effects of the substrate noise injected by the Input / output (I/O) drivers on the
SAR-A ADC front-end analog circuitry.
The following three paragraphs discuss the above aspects.
Different capacitor layout topologies and metal layer combinations were investigated, and their
capacitance values were extracted to come up with better capacitor topology to be used in the
SAR-A ADC layout. Since polysilicon (poly 1 – poly 2) parallel plate caps are not standard in the CMOS
XFAB 0.35 µm or the 0.18 µm process, other combinations of metal and poly were laid out. This was to
check for their extracted capacitance, and their parasitic capacitances to the substrate, with a goal to
identify a layout topology(s) that would yield a capacitor unit cell with the highest capacitance
per-unit-area in the selected CMOS process with minimized parasitic capacitance to substrate.
Metal-Oxide-Metal (MOM) capacitors were evaluated as they exploit the effects of inter-layer capacitive
coupling between the plates formed by standard metallization. Inter-layer capacitive coupling provides
superior matching-characteristics than vertical coupling due to tighter process control of lateral
dimensions than that of metal and dielectric layer thicknesses. Fringe capacitance dominates parallel
plate capacitance in fine feature-size CMOS as wires become taller as they become narrower (to limit
the increase in on-chip sheet-resistance). Hence, MOM caps are more area-efficient than parallel plate
caps unless the dielectric is very thin (MIM caps), which have cost and reliability issues. Figure 5-2 (a)
48
shows an example layout of a stacked and inter-digitated MOM capacitor-cell formed by Metal-1 through
Metal-5 layers, where T1 and T2 are the terminals of the MOM capacitor. An example of abutting two
copies of the MOM capacitor-cell layout in Figure 5-2 (a) to realize a capacitor-cell with twice the
capacitance of that in Figure 5-2 (a) is shown in Figure 5-2 (b).
T1
T2
(a)
T1
T2
(b)
T1
T2
Figure 5-2: (a) Example layout of a stacked and inter-digitated MOM capacitor formed by Metal-1
through Metal-5 layers, with terminals T1 and T2. (b) Example of abutting two copies of the MOM
capacitor-cell layout in (a) to realize a capacitor-cell with twice the capacitance of that in (a).
The total capacitance in the C-DAC-array increases with the resolution of the charge-redistribution
(CR) ADC. Incorporating the Sample and Hold (S/H) as a part of the C-DAC takes the inherent
advantage of using the C-DAC array for S/H. Hence the input is sampled onto the biggest capacitor
in the C-DAC alleviating the limitation of the kBT/C noise. Also, the Charge-Redistribution C-DAC
performs the S/H operation eliminating the need for a separate Sample and Hold amplifier.
Techniques such as bridged charge-redistribution SAR ADC are implemented in the SAR-A ADC
to reduce the Ctotal of the CR-SAR, as opposed to the traditional 2
N
binary-weighted C-DAC, thereby
reducing the dynamic power consumption of the SAR ADC. To minimize the SAR ADC’s internal
C-DAC’s capacitance-array mismatch, and to minimize the parasitic capacitance in the
binary-weighted array, an iterative approach of extracting the C-DAC capacitor array was taken.
Based on the post-layout extracted simulation results, the placements of the Most Significant Bit
(MSB) and the Least Significant Bit (LSB) capacitor elements were adjusted. Figure 5-3 shows the
floorplan of the C-DAC array, where the numbers 1 through 12 correspond to Figure 4-3’s LSB and
MSB C-DACs.
49
Figure 5-3: SAR ADC’s internal C-DAC array floorplan.
The nine squares in the center labeled as “A” correspond to the attenuation capacitor CA (see
Figure 4-3). This layout is common-centroid and meets the 4-axis symmetry (X, Y, 45 degrees, and
135 degrees) to minimize the effects of first and second order process gradients [89]. This floorplan also
takes edge effects into account by adding sufficient dummy capacitors (D) all around the C-DAC-array
and achieves a better symmetry, as well as minimizes the routing while connecting the capacitors.
The Input/output (I/O) drivers for the pads on the bottom and the left-hand side of the die floorplan (see
Figure 5-1) have long wires from the pads in the I/O pad ring in the chip to the ADC circuitry in the core
of the chip. This is to be handled by having the main output pad drivers located near the I/O pads (which
drive a lot off of-chip capacitance and therefore sink a lot of current and inject noise into the substrate).
To get to the core area from the pads, we have small buffers for driving the on-chip wiring. Since the
substrate is common to both the I/O pad circuitry and the ADC front-end, and that substrate is typically
shorted to ground locally at circuits to avoid latch up, noise injected into the ground/substrate node will
be transmitted via the substrate to the sensitive ADC front-end. The substrate node can be modeled as
an RC mesh, which gets excited as follows: I = C * dV/dt; where dV is the voltage change in time dt at
the package pin load. This current “I” returns to the Printed Circuit Board (PCB) ground through a bond-
wire inductance, which results in voltage noise = L * dI/dt. Therefore, voltage noise excitation at the
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
D D 12 12 D D D 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 D D D 12 12 D D
D D 12 11 12 D D 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 D D 12 11 12 D D
D D D 12 11 12 D 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 D 12 11 12 D D D
D D D D 12 11 12 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 12 11 12 D D D D
D D D D D 12 11 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 11 12 D D D D D
D D 12 12 12 12 12 10 10 10 11 10 10 10 10 10 10 10 11 10 10 10 12 12 12 12 12 D D
D D 12 12 12 12 12 10 9 10 11 10 9 9 9 9 9 10 11 10 9 10 12 12 12 12 12 D D
D D 12 12 12 12 12 10 10 8 11 11 9 8 8 8 9 11 11 8 10 10 12 12 12 12 12 D D
D D 12 12 12 12 12 11 11 11 6 4 4 6 6 6 4 4 6 11 11 11 12 12 12 12 12 D D
D D 12 12 12 12 12 10 10 11 3 5 5 6 5 6 5 5 1 11 10 10 12 12 12 12 12 D D
D D 12 11 11 11 11 10 9 9 3 5 7 6 7 6 7 5 2 9 9 10 11 11 11 11 12 D D
D D 12 11 11 11 11 10 9 8 6 6 6 A A A 6 6 6 8 9 10 11 11 11 11 12 D D
D D 12 11 11 11 11 10 9 8 6 5 7 A A A 7 5 6 8 9 10 11 11 11 11 12 D D
D D 12 11 11 11 11 10 9 8 6 6 6 A A A 6 6 6 8 9 10 11 11 11 11 12 D D
D D 12 11 11 11 11 10 9 9 3 5 7 6 7 6 7 5 2 9 9 10 11 11 11 11 12 D D
D D 12 12 12 12 12 10 10 11 3 5 5 6 5 6 5 5 1 11 10 10 12 12 12 12 12 D D
D D 12 12 12 12 12 11 11 11 6 4 4 6 6 6 4 4 6 11 11 11 12 12 12 12 12 D D
D D 12 12 12 12 12 10 10 8 11 11 9 8 8 8 9 11 11 8 10 10 12 12 12 12 12 D D
D D 12 12 12 12 12 10 9 10 11 10 9 9 9 9 9 10 11 10 9 10 12 12 12 12 12 D D
D D 12 12 12 12 12 10 10 10 11 10 10 10 10 10 10 10 11 10 10 10 12 12 12 12 12 D D
D D D D D 12 11 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 11 12 D D D D D
D D D D 12 11 12 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 12 11 12 D D D D
D D D 12 11 12 D 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 D 12 11 12 D D D
D D 12 11 12 D D 12 12 12 12 12 11 11 11 11 11 12 12 12 12 12 D D 12 11 12 D D
D D 12 12 D D D 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 D D D 12 12 D D
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
50
I/O driver substrate node location close to it = L * C * (dV/dt) * (dV/dt). If we can provide a very
low-impedance return path to a very low-impedance, quiet, ground (closest to noise source), and a very
quiet supply, then we can shunt the substrate noise injected by the I/O drivers away from the SAR-A ADC
front-end analog circuitry. This level of substrate-noise isolation will require dedicated pads to shunt the
noise to ground instead of the sensitive ADC front-end. Substrate-isolation ground is accomplished by
putting down many substrate-contact strips (20 µm wide, continuous, with lots of vias to metal) 5 µm from
the I/O pads at the periphery, between the core and the peripheral I/O pads. The substrate-contact strip
is connected to its own pads (four dedicated pads used in the SAR-A ADC layout) and it is bonded to
package cavity ground which is connected to ground at the PCB. For the substrate-isolation power, we
need an N-well strip with continuous vias and metal between the substrate-isolation ground strip and the
core. This N-well strip contact needs to be connected to at least one pad (four dedicated pads used in
the SARA ADC layout) for connecting to very clean and quiet, low-impedance dedicated supply at the
package level. The same approach is repeated (with dedicated pads) to isolate the core and the buffers
near it for driving the on-chip wiring.
Testing the SAR-A ADC
This section records the measurement results of the Successive Approximation
Register / Algorithmic (SAR-A) ADC fabricated in 0.18 μm CMOS XFAB XH018
process-technology node. XFAB’s Multi-Project Wafer (MPW) shuttle run was used, where only
five (5) ICs per customer were delivered. The design and implementation of the shared-architecture
SAR-A ADC is targeted towards neural-sensing in closed-loop implantable systems. The objective
of the realization and subsequent measurements of the SAR-A ADC is to provide insight into the
advantages and limitations of combining the two (the SAR and the Algorithmic) ADC architectures.
The measured results obtained from the characterization of the SAR-A ADC to match the target
specifications will establish the truth or the falsehood of the hypothesis outlined in
Chapter 1 – Section 1.3. The actual Static and Dynamic error characteristics of the SAR-A ADC
are compared with the target Static and Dynamic specifications of the SAR-A ADC.
51
Static Error Tests:
The ideal transfer characteristic of the ADC is shown in Figure 5-4. One Least Significant Bit (LSB)
is defined as the smallest analog value an ADC can resolve. Figure 5-5 shows the offset, gain, and
full-scale errors of the measured ADC when compared with the transfer function of the ideal ADC.
The ADC accuracy is determined by the Differential Non-Linearity and the Integral Non-Linearity.
Figure 5-4: Ideal transfer characteristic of an Analog to Digital Converter.
Figure 5-5: Transfer characteristic of the measured ADC showing the offset, gain and
full-scale errors when compared with the transfer function of the ideal ADC [98].
o Differential Non-Linearity (DNL): DNL error is defined as the difference between a measured
step width and the ideal step value of 1 LSB. For an ideal ADC, in which the DNL = 0 LSB,
each analog step equals 1 LSB (1 LSB = VFSR/2
N
, where VFSR is the full-scale range, and
N is the resolution of the ADC). A DNL error of ≤ 1LSB guarantees a monotonic transfer
function without any missing codes. The DNL is defined as follows [97]:
52
DNL = |
(V
𝐷 +1
− V
𝐷 )
V
𝐿𝑆𝐵 −𝐼𝐷𝐸𝐴𝐿 − 1
|, where 0 < D < 2
N
- 2. Equation (5)
Where VD is the analog value corresponding to the digital-output code D, N is the ADC
resolution, and VLSB-IDEAL is the ideal spacing for two adjacent digital codes.
o Integral Non-Linearity (INL): INL error is defined as the deviation in LSB of a measured
transfer function from an ideal linear transfer function. The INL is defined as follows [97]:
INL = |
𝑉 𝐷 – 𝑉 𝑍𝐸𝑅𝑂 V
LSB−IDEAL
- D |, where 0 < D < 2
N
-1. Equation (6)
VD is the analog value corresponding to the digital-output code D, N is the resolution of the
ADC, VZERO is the minimum analog-input corresponding to an all-zero output code, and
VLSB-IDEAL is the ideal voltage spacing for two adjacent digital codes. INL error also provides
the offset and the gain error information of the ADC (see Figure 5-5).
Dynamic Error Tests:
Dynamic error tests are executed to check the AC performance of the ADC. A sine-wave fitting and a
Fast Fourier Transform (FFT) computation needs to be performed to compute the dynamic errors in the
ADC [93]. The power spectrum of the ADC output for a single tone input to the ADC is shown in
Figure 5-6.
F
signal
Fs/2
Frequency
dBFS
RMS Fundamental signal
SFDR
Noise Floor
Largest
Spur
SFDR – Spurious Free
Dynamic Range
Figure 5-6: Power spectrum of the ADC output [93].
Fsignal is the input tone to the ADC. This is generated by using the sine-wave waveform generator and is
applied to the input of the ADC as shown in Figure 5-8.
53
o Spurious-free dynamic range (SFDR) and Total Harmonic Distortion (THD): SFDR refers to
dynamic range between the RMS fundamental signal and the largest spur (harmonic) present
in the power spectrum of the ADC output (see Figure 5-6). The dynamic range of the ADC is
affected by the harmonics (mainly 2
nd
to 6
th
) of the fundamental tone of the input, if they are not
suppressed appropriately. THD computes the power in the harmonics with respect to the
fundamental tone, by taking the ratio of the RMS value of the fundamental tone to the RMS of
its harmonics [92, 93].
Equation (7)
o Signal-to-Noise ratio (SNR): SNR is calculated from the FFT output of the ADC by taking the
ratio of the RMS value of the fundamental tone to the noise power of the FFT output [92, 93, 94].
SNR computation excludes the power in the harmonics (the first 6 harmonics), which is
considered by THD calculation.
Equation (8)
o Signal to noise-plus-distortion ratio (SINAD or SNDR): SINAD is also calculated from the FFT
output of the ADC by taking the ratio of the RMS value of the fundamental tone to the sum of
the powers of the harmonics and the noise. SINAD is defined by the following equation [93, 94].
SINAD in dB provides the effective dynamic range of the ADC accounting for the total noise and
the harmonic distortion.
Equation (9)
o Effective Number of Bits (ENOB): ENOB value (given by Equation (10)) is derived from the
SINAD, which accounts for the total noise and the harmonic distortion present at the ADC output
[93, 94]. Therefore, ENOB in bits present the actual resolution of the ADC for a given input
frequency and the ADC sampling-rate.
Equation (10)
P
Signal
THD =10 log
10
P
Harmonic-Distortion
=
P
Signal
SNR 10 log
10
P
Noise
= = +
SNR THD
--
10 10
SNDR SINAD -10 log [10 10 ]
10
max
SNDR [dB] - 1.76
ENOB =
6.02
54
o Intermodulation Distortion (IMD): The power spectrum output of the ADC for a two-tone input to
the ADC is shown in Figure 5-7. Two tone intermodulation distortions are measured by applying
two sinewaves (at frequencies f1 and f2) at the input of the ADC [92, 99]. The amplitude of each
of the tone is set slightly more than 6 dB below the full-scale range of the ADC. This is to ensure
the ADC input does not saturate when the two tones are added in phase. The locations of the
second and third order intermodulation products are shown in Figure 5-7. The third order
intermodulation products (IM3) are computed as 2 f2 - f1 and 2 f1- f2. The higher the IMD (which is
the ratio between the power of the fundamental tones and the power of the IM3 products) the
better the linearity of the ADC.
f
1
f
2
2f
1
-f
2
2f
2
-f
1
Fs/2
f
1
-f
2
Frequency
dBFS
IM3 IM3 IM2
f 1, f 2 – Two input tones
IM2 – Second Order IMD products
IM3 – Third Order IMD products
Fs – Sampling Frequency
Figure 5-7: Second and Third order IMD products for a two-tone input signal to the ADC [99].
Measurement Setup to Characterize the SAR-A ADC
A Printed Circuit Board (PCB) was fabricated to characterize the SAR-A ADC. Figure 5-8 shows
the characterization test setup of the SAR-A ADC to measure the static and the dynamic errors.
A four-layer board with separate ground and power planes has been fabricated to ensure good
signal integrity. Bypass capacitors to ground were used to filter the high and low-frequency noise
on the power-supply voltages and reference voltage. The SAR-A ADC Integrated Circuit (IC) is
packaged in a 64-pin Quad-Flat No-lead (QFN) package. Compared to the alternatives, a QFN
packaged IC has shorter bond-wires inside the package connecting the IC to the package pins,
55
reducing power, ground and substrate noise that is induced due to the single-ended digital-output
transitions of the ADC. Please refer to Section 5.1 that describes the layout strategy for noise
reduction, and the selection of SAR-A ADC’s power, ground and I/O pad-distribution on the die.
The packaged QFN SAR-A ADC IC is placed in a QFN socket on the PCB. The QFN socket
facilitates in switching out the packaged SAR-A ADC IC without disturbing the measurement/test
setup. The split analog and digital grounds are joined at a single point on the PCB, so that the noisy
digital return currents will not cause any ground noise or ground-bounce on the analog ground
supply. The high-speed digital signal traces are routed away from sensitive analog traces to avoid
cross-talk.
Figure 5-8: Characterization test setup for the SAR-A ADC.
Organization of the test result sections
The 12-bit SAR-A ADC architecture is fabricated in CMOS 6M1P XFAB XH018 process with a
supply-voltage of 1.8 V, occupying a core implementation-area of 0.31 mm
2
. Section 5.5 describes the
procedure to characterize the SAR-A ADC for static errors. Section 5.6 talks about the measurement
setup and records the DNL and the INL measurement results of the SAR ADC mode on the available
five chips, including the sampling-speed characterization. Similarly, Section 5.7 talks about the
measurement setup and records the DNL and the INL measurement results of the Algorithmic ADC
mode on three of the five chips, including the sampling-speed characterization. Section 5.8 and 5.9
discusses the potential causes for the gap in measured results versus the target specifications of the
56
SAR-A ADC modes, focusing on the effects of the clock-signal edge’s timing jitter, substrate noise
injection onto the analog front-end of the ADC, improper calibration of the reference current, and
mismatch in the current mirror that sets the bias-currents. Section 5.10 talks about the measurement
setup and records the dynamic measurement results of the SAR and the Algorithmic ADC modes of the
SAR-A ADC using single-tone transient testing method. Section 5.11 details the two-tone transient
testing and records the Intermodulation Distortion (IMD) measurement results of the SAR-A ADC.
Finally, Section 5.12 summarizes the measurement results of the SAR-A ADC and draws comparisons
with the best available standalone ADCs suitable for implantable neuro-stimulators.
Testing the SAR-A ADC for Static Errors
For an ideal ADC that has no INL or DNL errors, all codes have equal chances of occurrence, and there
should be the same number of counts in each code. In reality, because of the quantization error, the
measured INL and DNL values are non-zero. Static error-testing of the ADC is accomplished by applying
a histogram-based approach. This involves collecting many digitized sample outputs of the ADC over a
period, for a well-defined input signal. A linear triangular waveform which exceeds (by 1 mV) both ends
of the full-scale range of the ADC is applied to the input of the ADC. Many samples are collected for the
triangular waveform input, and the number of occurrences of each code is calculated. The frequency of
the waveform should be low enough, such that the ADC does not have transient related errors, and the
frequency must not be related to the sampling frequency. The procedure to compute the DNL and the
INL of the ADC, using the histogram-based testing with linear triangular ramp input is detailed below.
Step 1: A triangular waveform input with it peak-peak slightly exceeding the full-scale range
(0 – Vref) of the ADC is applied as the input to the ADC. The frequency of the triangular ramp
input should be low enough, so that the ADC samples all the 4096 (N=12-bits) samples linearly.
Step 2: At least 20*4096 = 81,920 (MT) samples are collected for the triangular waveform input.
Step 3: Count the number of occurrences of each code h(n)Actual. For full-scale triangular input,
the theoretical number of hits is h(n)Theoretical = MT / (2
N
-2).
Step 4: Calculate DNL of each code for n = 1 to 2
N
-2: DNL = (h(n)Actual / h(n)Theoretical) – 1
Step 5: Calculate INL by INLn = ∑ (i =0 to n) DNLi.
57
As we can see from the above procedure, the histogram testing can be implemented by running the ADC
at the desired sampling-speed. This will enable us to evaluate if the ADC is able to achieve the
sampling-speed performance for the desired ENOB simultaneously. With this approach, all the four-
performance metrics, namely, the DNL, the INL, sampling-speed, and the ENOB of the ADC can be
evaluated. Since the SAR-A ADC architecture combines the SAR and the Algorithmic ADC, we need to
characterize each ADC mode individually to understand their advantages / limitations. This will also
provide insights into the robustness of this architecture.
Static Error Measurement Results of the SAR ADC mode
For histogram-based testing, as noted in the procedure above, the frequency of the triangular ramp
input should be low enough, such that the SAR ADC samples all the 4096 (N=12-bits) samples
linearly. If an average of 20 samples for each code is desired, then for a 100 kSa/s ADC, which
equates to sampling every 10 µs, the frequency of the input signal (triangular ramp) to the ADC,
should be less than 1/ (10 µs * 20 *4096) = 1.25 Hz. Figure 5-9 shows the static error test setup
for the SAR ADC mode.
PCB inside the Temperature Chamber
ADC
UUT
Linear Triangular
Waveform Generator
Amp : 0-0.9V
Frequency : 1.25Hz
Pulse Generator for Clock
Generator
Frequency : 200 MHz
Power / Ground / References
National
Instruments PXI
SPI/USB Interface
Computer
ADC out
12-bits
Figure 5-9: SAR ADC mode static errors test setup.
Following the histogram-based procedure outlined above, the SAR ADC performance is evaluated.
The target performance of the SAR ADC mode is to achieve 100 kSa/s sampling-speed at 12-bits
(ENOB). All fabricated chips (total of five) were measured to evaluate the static performance of the
SAR ADC. Table 5.1 summarizes the results for the SAR ADC mode of the SARA ADC, where we
can see the sampling-speed of the SAR ADC exceeds the target sampling-speed of 100 kSa/s at
58
12-bits, for all FIVE fabricated chips. This performance was achieved with no changes to the analog
and the digital voltage supplies or the bias-currents.
Table 5.1: SAR ADC mode’s sampling-speed characterization.
Index Analog Supply
AVDD (V)
Digital Supply
DVDD (V)
Bias-current
Increase (%)
SAR Sampling-speed
(kSa/s) at 12-bits
Chip 1 1.8 1.8 0 142.5
Chip 2 1.8 1.8 0 145
Chip 3 1.8 1.8 0 144
Chip 4 1.8 1.8 0 141
Chip 5 1.8 1.8 0 142
Figure 5-10: Measured DNL/INL plots of the SAR ADC mode of the SARA ADC at 100 kSa/s at
37 °C, with AVDD = 1.8 V, DVDD = 1.8 V and bias-current = 1 µA.
Above plot (Figure 5-10) shows the DNL/INL plots of the SAR ADC at a sampling-rate of 100 kSa/s,
and no changes to AVDD (1.8 V) or DVDD (1.8 V) or the bias-current (1µA). The measured
maximum DNL is 0.54 LSB and INL is 0.66 LSB. We measured the DNL/INL of the SAR ADC mode
across all the five fabricated chips as they all met the sampling-rate specifications of the SAR ADC
mode, without any changes to the supply-voltage or the bias-current. We can see from Figure
5-11 that the measured maximum DNL across the five chips is < 0.6 LSB, indicating that there are
no missing codes in the 12-bit 100 kSa/s SAR ADC mode of operation.
59
Figure 5-11: Measured DNL of the SAR ADC mode across all the available five chips.
Figure 5-12 shows the measured maximum DNL variation of the SAR ADC mode at 100 kSa/s across
the available five chips. We can see that all five fabricated chips have similar variations in DNL
(< 0.6 LSB). This verifies the robustness of the design and the measurement setup of the measured
result.
Figure 5-12: SAR ADC mode’s measured maximum DNL variation measured across five chips.
Static Error Measurement Results of the Algorithmic ADC mode
The frequency of the triangular ramp input should be low enough for the histogram-based testing,
such that the Algorithmic ADC samples all the 4096 (N=12-bits) samples linearly. If an average of
20 samples for each code is desired, then the frequency of the input signal (triangular ramp) to the
60
ADC, should be less than 1 / (200 ns * 20 *4096) = 61 Hz for 5 MSa/s (sampling every 200 ns)
Algorithmic ADC operation.
PCB inside the Temperature Chamber
ADC
UUT
Linear Triangular
Waveform Generator
Amp : 0-0.9V
Frequency : 61 Hz
Pulse Generator for Clock
Generator
Frequency : 200 MHz
Power / Ground / References
National
Instruments PXI
SPI/USB Interface
Computer
ADC Out
12-bits
Figure 5-13: Algorithmic ADC mode static errors test setup.
Figure 5-13 shows the static-error test setup for the Algorithmic ADC mode. Following the
histogram-based procedure outline above, the Algorithmic ADC performance is evaluated. The
target performance of the Algorithmic ADC mode was to achieve a sampling-speed of 5 MSa/s at
12-bits (ENOB). FIVE chips were measured to evaluate the static performance of the Algorithmic
ADC. Table 5.2 summarizes the measurement results for the Algorithmic ADC mode, where we
can see the sampling-speed of 5 MSa/s is achieved (rows in bold and italicized) for three of the five
chips with a slight increase (up to 2.5%) in bias-currents. Chip 5 meets the sampling-speed
specification of 5 MSa/s at 12-bits, without any changes to the nominal values of the supply and
bias-currents. Even though the Table 5.2 points to a better Algorithmic ADC performance by
increasing the bias-current alone, it should be noted that the supply variation (lowering the Digital
supply or increasing the Analog supply) also led to improved ADC performance. To understand this
further, we need to evaluate the potential error-sources that affect the ADC performance.
Section 5.8 discusses the potential error sources that could cause the performance gap in the
Algorithmic ADC. Figure 5-14 shows the INL/DNL plots of the Algorithmic ADC for Chip 5, with a
measured sampling-rate of 5 MSa/s with nominal supply and bias-currents. The max DNL is
+1.08 LSB and max INL is +1.12 LSB.
61
Table 5.2: Algorithmic ADC mode’s measured sampling-speed characterization.
.
Index Analog
Supply (V)
Digital Supply
(V)
Bias-current
Increase (%)
Algorithmic ADC
(MSa/s)
Chip 1 1.8 1.8 0 4.992
Chip 1 1.8 1.8 1.25 5.083
Chip 2 1.8 1.8 0 4.891
Chip 2 1.8 1.8 1.25 4.975
Chip 2 1.8 1.8 2.50 5.056
Chip 3 1.8 1.8 0 4.983
Chip 3 1.8 1.8 1.25 5.070
Chip 4 1.8 1.8 0 4.545
Chip 4 1.8 1.8 1.25 4.619
Chip 4 1.8 1.8 2.50 4.692
Chip 4 1.8 1.8 3.75 4.771
Chip 4 1.8 1.8 5 4.846
Chip 5 1.8 1.8 -2.50 4.933
Chip 5 1.8 1.8 -1.25 5.016
Chip 5 1.8 1.8 0 5.104
Figure 5-14: Measured INL/DNL plots of the Algorithmic ADC mode of the SARA ADC at
5 MSa/s with AVDD = 1.8 V, DVDD = 1.8 V and bias-current = 40 µA.
62
Figure 5-15: Measured DNL of the Algorithmic ADC mode across the three chips.
Three of the available five chips met the sampling-rate specifications of the Algorithmic ADC mode,
without any changes to the supply-voltage or the bias-current. Therefore, we measured the DNL/INL of
the SAR ADC mode across these three chips. We can see from Figure 5-15 that the maximum DNL
across the three chips is < 1.06 LSB. This also indicates that there are no missing codes in the 12-bit
5 MSa/s Algorithmic ADC mode of operation. Figure 5-16 shows the measured maximum DNL variation
of the Algorithmic ADC mode at 5 MSa/s across the available three chips. We can see that all three
fabricated chips have similar variations in DNL (< 1.06 LSB). This verifies the robustness of the design
and the measurement setup of the measured result.
Figure 5-16: Algorithmic DC mode’s measured maximum DNL variation measured across three
chips.
63
Potential causes for the gap in measured results versus the target
specifications for the Algorithmic ADC
We have seen the SAR ADC mode performance meets the target specifications without any
changes to the supply or bias-currents for all the FIVE chips tested. For the Algorithmic ADC mode,
we had to vary the bias-current to meet the target specification on FOUR of the FIVE chips. For a
high-speed high-performance ADC implementation, such as the Algorithmic ADC mode of the
SARA ADC, various factors affect the ADC performance. We have identified the following potential
error sources that could cause the performance gap in the Algorithmic ADC.
• Effects of the Clock Jitter on the ADC performance
• Effects of Substrate noise injection onto the analog front-end of the ADC
• Effects of improper calibration of the reference current
• Mismatch in the current mirror that sets the bias-currents.
5.8.1 Effects of Clock Jitter on the Algorithmic DC performance
Careful selection of a clock source is needed to ensure the sampling performance of the Analog to
Digital Converter (ADC) is not compromised. When the sample and hold switch of the Algorithmic
ADC is closed, the input of the ADC is connected to the sampling capacitor. At the instant the switch
is opened one-half clock period later, the voltage on the capacitor is sampled and held. Variation
in the time (known as aperture uncertainty or jitter) at which the switch is opened, will result in an
error voltage that is proportional to the magnitude of the jitter and the input signal. In other words,
the greater the sampling-rate and amplitude of the signal, the more susceptible the ADC
performance is to the jitter on the clock source. The theoretical limit on the SNR, resulting from the
clock jitter (σ) is given by [90]
SNR = - 20 log (2 π Fnyq σRMS) Equation (11)
The theoretical value of the jitter on the clock source is σRMS < 4.4 ps or the σpk-pk < 12.7 ps, for
5 MSa/s operation of the SAR-A ADC in Algorithmic ADC mode, achieving an ENOB of 12-bits
(74 dB SNR). Hence, a clock source with peak-to-peak jitter less than 10 ps is required to minimize
64
the effects of the clock jitter on the ADC performance. Three clock sources with peak-peak jitter
specification of 350 ps, 4 ps and 1.25 ps were used to characterize the SAR-A ADC in Algorithmic
ADC mode. Table 5.3 shows the effects of the clock jitter on the Algorithmic ADC performance
measured using three clock sources. The Algorithmic ADC’s sampling-speed performance
improved drastically by using a 1.25 ps jitter clock source. Only the two best performing chips
(Chip 1 and Chip 5) with 350 ps jitter clock source were used to test the 4 ps jitter clock source.
The results in Table 5.3 show lower than targeted sampling-speed results (using 1.25 ps jitter clock
source). This is because the other sources of error (such as substrate-isolation, reference-current
mismatch) were not corrected during these measurements.
Table 5.3: Effects of clock jitter on the Algorithmic ADC’s sampling-speed.
peak-peak
clock jitter
(ps)
Measured Algorithmic ADC Sampling-speed (MSa/s) at 12-bits
Chip 1 Chip 2 Chip 3 Chip 4 Chip 5
350 3.300 2.95 3.1 2.716 3.450
4 4.125 not measured not measured not measured 4.250
1.25 4.350 4.125 4.225 3.9 4.475
5.8.2 Effects of Substrate noise injection onto the Algorithmic ADC front-end
The Input/output (I/O) drivers for the pads on the bottom and the left-hand side of the die floorplan
(see Figure 5-1) have long wires from the pads in the I/O pad ring in the chip to the ADC circuitry
in the core of the chip. This is handled by having the main drivers located near the I/O pads (which
drive a lot off of-chip capacitance and; therefore, sink a lot of current and inject noise into the
substrate). To get from the core to the pads, we have small buffers for driving the on-chip wiring.
Since the substrate is common to both I/O pad circuitry and the ADC front-end and that substrate
is typically shorted to ground locally at circuits to avoid latch up, noise injected into the
ground/substrate node will be transmitted via the substrate to the sensitive ADC front-end.
The substrate node can be modeled as an RC mesh, which gets excited as follows: I = C * dV/dt;
where dV is the voltage change in time dt at the package pin load. This current “I” returns to PCB
65
ground through a bond-wire inductance, which results in voltage noise = L * dI/dt. Therefore, voltage
noise excitation at the I/O driver substrate node location close to it = L*C*(dV/dt) *(dV/dt). If we can
provide a very low-impedance return path to a very low-impedance, quiet, ground (closest to noise
source), and a very quiet supply, then we can shunt the substrate noise injected by the I/O drivers
away from the SAR-A ADC front-end analog circuitry. This level of substrate-noise isolation will
require dedicated pads to shunt the noise to ground instead of the sensitive ADC front-end.
Table 5.4 records the measured results with and without substrate-isolation.
Table 5.4: Effects of substrate-isolation on the Algorithmic ADC’s sampling-speed.
Lowering the digital supply (DVDD), reduces the influence of substrate noise injection from the
digital circuitry's (including clock buffers and I/O) transitions into the analog circuit due to longer
rise and fall times as DVD drops. Table 5.5 shows the influence of lowering the DVDD on the ADC
performance.
Table 5.5: Effects of supply variation on the Algorithmic ADC’s sampling-speed.
DVDD(V)
Measured Algorithmic ADC Sampling-speed (MSa/s) at 12-bits
Chip 1 Chip 2 Chip 3 Chip 4 Chip 5
1.8 4.830 4.850 4.800 4.458 4.780
1.75 4.916 4.933 4.875 4.530 4.890
1.70 4.966 4.979 4.908 4.591 4.920
5.8.3 Effects of improper Reference Current Calibration
The reference current Iref (100 nA) out of the bandgap is mirrored 1:1, and that (mirrored current)
is multiplied (100x) to get 10 µA reference calibration current. This reference calibration current is
Substrate-Isolation
Measured Algorithmic ADC Sampling-speed (MSa/s) at 12-bits
Chip 1 Chip 2 Chip 3 Chip 4 Chip 5
Tied to DVDD 4.64 4.625 4.59 4.125 4.55
Tied to a dedicated
supply other than
DVDD
4.83 4.850 4.80 4.458 4.78
66
sent out of the chip and through a 100 kΩ resistor to ground on the PCB. Therefore, the voltage
across the resistor is adjusted to 1 V (10 µA x 100 kΩ) using the Iref calibration bits. This in turn
sets reference current Iref to 100 nA. Measuring the 10 µA calibration current through the
source-meter using the calibration bits that were set by the resistor method came out to be 9.15 µA,
which is 10.93% less than the target 10 µA. This meant that the Iref is calibrated to 91.5 nA instead
of 100 nA. This lowered the bias-current (that is set by multiplying the Iref of 91.5 nA instead of
100 nA) supplied to the comparator in the Algorithmic ADC mode resulting in reduced sampling-
speed. If the resistor (100 kΩ) on the PCB is not measured independently, then the reference
current calibration could be offset depending on the tolerance of the resistor. With resistor tolerance
as high as 7%, the Iref calibration circuit was sinking < 10 µA to provide a voltage drop of 1 V across
the 100 kΩ resistor. The correct way to calibrate the reference current was to measure current
directly using a source meter instead of using a resistor-based approach. For each chip, the
calibration bits were set using the resistor-based approach, then the calibration current is measured
using the source meter approach. The measured calibration current for each chip is tabulated in
Table 5.6.
Table 5.6: Bandgap reference current calibration using the source meter and resistor methods.
Index
Calibration Current recorded
using Source Meter approach
Variation in Calibration
Current w.r.t to Resistor
method
Chip 1 9.15 µA 10.93 %
Chip 2 9.18 µA 10.89 %
Chip 3 9.11 µA 10.97 %
Chip 4 9.09 µA 11.01 %
Chip 5 9.16 µA 10.91 %
With the source meter calibration approach, the reference current Iref is calibrated to 10 µA (in turn
100 nA at the output of the bandgap). Table 5.7 shows the measured results of Algorithmic ADC
after correcting for the Iref calibration.
67
Table 5.7: Effects of incorrect reference current calibration on the Algorithmic ADC performance.
Reference
Calibration
Measured Algorithmic ADC Sampling-speed (MSa/s)
at 12-bits
Chip 1 Chip 2 Chip 3 Chip 4 Chip 5
Resistor (+7% error) based
with a bias-current increase of
+10%
4.916 4.933 4.875 4.530 4.920
Source meter based, with 0%
bias-current increase.
4.992 4.891 4.983 4.545 5.104
5.8.4 Mismatch in the current mirror that sets the bias-current for the Algorithmic
ADC
The 100 nA current out of the bandgap is mirrored 1:1, and the mirrored current is multiplied (100x)
to get 10 µA reference current for calibration. The bandgap current mirror and the 10 µA reference
current for calibration are laid out using common-centroid layout topology to maximize matching of
the transistors constituting the current mirror. Edge effects that affect matching are minimized by
surrounding the layout with dummy devices of the same width and length as the transistors in the
current mirror. The mirrored current is multiplied (400x) to get the 40 µA Algorithmic ADC
bias-current. These are laid out together in common centroid layout topology and surrounded by
dummy devices, separately from the calibration circuit. The possible explanation for the difference
in the bias-current variation to achieve the desired sampling-speeds on three chips, could be due
to the transistor layout matching of current mirrors that generate the 100 nA and the 40 µA. Since
this is a different path from the calibration current multiplier, the only visible metric to this mirror
path is the ADC performance. Small changes in the nano-Amperes current scale (1.25 nA - 2.5 nA)
when multiplied to get 40 µA results in a variation of 500 nA – 1 µA.
Considering the MOSFET related random-mismatch parameters, for the threshold voltage
mismatch, it has been shown that the difference in threshold voltages between two identically sized
MOSFETs [14] behave as
=
t
Vt
V
A
W L
Equation (12)
68
AVt in Equation 12 is a parametric value that can be obtained from the process and device
specifications document, for a given technology from a given CMOS foundry. W and L are the width
and length of the identically sized transistors whose mismatch is to be determined. For a current
factor β (defined by µCoxW/L) mismatch [14], we have
( )
=
A
W L
Equation (13)
Here, the parametric value of Aβ (Pelgrom’s co-efficient) can also be obtained from the process
specifications document, for a given technology from a given CMOS foundry. Calculating the drain
current mismatch for the current mirror that sets the bias-current for the Algorithmic ADC for tm,
ws, wp corners. The 3-sigma ∆β/β or ∆ID/ID mismatch is shown in Table 5.8 (at Tj= 37
o
C).
Table 5.8: 3-sigma ∆ID/ID current mirror mismatch error in the Algorithmic ADC, across corners.
XH018 Process Corner 3-Sigma (∆ID/ID) Error (%)
Worst-Case Power 2.8589 %
Typical Mean 2.9708 %
Worst-Case Speed 3.1626 %
This shows that it is possible to have the bias-current variations of 1.25 - 2.5 % that is seen in
measurement results of the Algorithmic ADC. Table 5.9 documents the measurement results
(of 4 chips) where the bias-current needed to increase up to 2.5% to meet the specifications of 5
MSa/s at 12-bits for the Algorithmic ADC. One possible way to minimize the mismatch effect in the
current mirror that produces the Algorithmic ADC bias-current is to reduce the mirror ratio (1:400)
from the bandgap generated reference to the Algorithmic ADC bias-current reference. In the current
design, the bandgap is designed to generate 100 nA of reference current (this is useful at system
level where other circuit-blocks might need bias-currents in 100’s nA to µA range).
69
Table 5.9: Effect of bias-current increase in the Algorithmic ADC sampling-speed.
Index
(Chip #)
Bias-current
Increase
(%)
Sampling-speed (MSa/s)
at 12-bits
1 1.25 5.083
2 2.50 5.056
3 1.25 5.070
5 0 5.104
To minimize the ratio of 400 times, we can design a bandgap that produces 1 µA of reference
current. This will reduce the mirror ratio to 40 times, which then reduces the mismatch effect due
to a compact layout of 1:40 current mirrors.
Lack of the effect of the current mirror mismatch on the SAR ADC
performance
The 100 nA current out of the bandgap is mirrored 1:1, and that (mirrored current) is multiplied
(1:10) to get 1 µA bias-current for the SAR ADC mode. The mirrored current from the bandgap
along with the 1 µA (1000 nA) bias-current are laid out using common-centroid layout topology to
maximize matching of the transistors constituting the current mirror. Edge effects that affect
matching are minimized by surrounding the layout with dummy devices of the same width and
length as the transistors in the current mirror. Allowing for +/- 3.16 % 3-sigma mismatch error
(see Table 5-8), the bias-current for the SAR ADC mode might have a variation from 970 nA to
1030 nA. The bias-current variation, if present, influences only the comparator settling-time
because the reference bias-current is applied only to the comparator block. For the SAR ADC mode
of the SAR-A ADC architecture, the C-DAC array’s settling-time determines the maximum
sampling-rate that can be achieved because of the charge re-distribution effect imposed on the
C-DAC array. The maximum settling-time of a C-DAC is determined by the settling-time of the most
significant bit. This is because the largest change in the C-DAC’s output occurs due to the most
significant bit. Since the SAR ADC's sampling-speed is limited by the settling-time of the C-DAC,
70
which must settle to within the resolution (+/- 0.5 LSB) of the overall converter, the effect of the
reference current mirror mismatch does not influence the sampling-speed determination.
The measurement results show the SAR ADC achieving a minimum sampling-speed of 141 kSa/s
(across all 5 chips) exceeding the target sampling-speed of 100 kSa/s at 12-bits.
Testing the SAR-A ADC for Dynamic Errors
5.10.1 Single-Tone transient testing using Sinewave fitting and FFT spectral analysis
While the static error testing helps determine if the ADC meets the INL and DNL requirements for
DC input signals, it does not guarantee that the ADC will meet the transient requirements for the
AC input signals. The power spectrum of the ADC output for a single-tone input (Fsignal) to the ADC
is shown in Figure 5-6. An FFT analysis is used to measure the AC distortion of the signal [91, 93].
From that, three important parameters are defined, including Signal to Noise and Distortion ratio
(SINAD or SNDR), Spurious-Free Dynamic Range (SFDR), and Effective Number of Bits (ENOB).
The procedure for this transient testing is outlined below.
• A sinewave input with frequency (Fin) that is not a sub-harmonic of the sampling frequency
(Fs) is applied as the input to the ADC.
• N samples are collected which consists of M complete cycles of the input sinewave
governed by the equation M =N* Fin / Fs.
• A best-fit sinewave is then computed from the sampled data points. The actual RMS error
from the best-fit sinewave QA is then calculated. The theoretical K-bit RMS quantization
error QT is calculated which equals q/√ (12), where q is the weight of the LSB. The Effective
Number of Bits ENOB is then computed by K – log2 [QA / QT].
FFT spectral analysis is computed based on the data points and the SFDR, SINAD metrics are
calculated as per the equations shown in Pages 52 - 54. This is accomplished by implementing an
FFT on the sampled data in National Instruments (NI) LabVIEW environment. The procedure
outline above is automated in the NI LabVIEW environment [91]. The following sections report the
transient measurement results of the SAR and the Algorithmic ADC modes for a single-tone and
two-tone input signals. Chip5 is used as the DUT for transient measurements.
71
5.10.2 Transient test setup and measurement results of the SAR ADC mode
Referring to the Figure 5-13 , Table 5.10 is built up to describe the test setup and instrumentation
details for the sinewave fitting and FFT spectral analysis procedure outlined above. The
measurement data for this experiment should facilitate the FFT computation, like the one shown in
Figure 5-6, where Fsignal = 9.975 kHz with the SAR ADC sampling-speed of 100 kSa/s. Based on
the 4096-point FFT computation, the performance metrics, namely SFDR, SINAD and ENOB are
computed as per the equations shown in Pages 52 - 54. Figure 5-18 plots the FFT computation of
the SAR ADC output with an input tone of 9.975 kHz which achieves an SFDR of 66.298 dB, an
SNDR of 65.081 dB, translating to an ENOB of 10.518 bits.
Table 5.10: Test Setup and instrumentation for SAR ADC’s sinewave fitting and FFT analysis.
Components in
Figure 5-17
Test Equipment Input Conditions
Sinusoidal waveform
generator
Key-sight 33622A waveform generator
0-0.9V; 9.975 kHz Sine
waveform
Pulse generator for
clock generation
Key-sight 33622A waveform generator
200 MHz; 50% duty
cycle clock
Temperature Chamber Test Equity 105 Temp. Half Cube 37 °C
PCB inside the Temperature Chamber
ADC
UUT
Sinusoidal Waveform
Generator
Pulse Generator for
Clock Generation
Power / Ground / References
National
Instruments PXI
SPI/USB Interface
Computer
SAR ADC
Out
12-bits
Figure 5-17: SAR ADC mode dynamic errors test setup.
72
Figure 5-18: FFT of the measured SAR ADC output at 100 kSa/s with 9.985 kHz sine input tone.
Figure 5-19 shows the dynamic performance of the 100 kSa/S SAR ADC, where the input
frequency is varied from DC up to the Nyquist rate (50 kHz). The computed ENOB in the LFP band
of interest (1- 600 Hz) is 10.57 bits.
Figure 5-19: Measured dynamic performance of the 100 kSa/s SAR ADC for a single-tone input.
73
5.10.3 Transient test setup and measurement results of the Algorithmic ADC mode
Referring to Figure 5-20, Table 5.11 is built up to describe the test setup and instrumentation details
for the sinewave fitting and FFT spectral analysis procedure outlined above.
Table 5.11: Test Setup and instrumentation for the Algo ADC’s sinewave fitting and FFT analysis.
Components in Figure 5-20 Test Equipment Input Conditions
Sinewave waveform
generator
Key-sight 33622A
waveform generator
0-0.9V; 498.98 kHz Sine waveform
Pulse generator for clock
generation
Key-sight 33622A
waveform generator
200 MHz; 50% duty cycle clock
Temperature Chamber
Test Equity 105 Temp.
Half Cube Chamber
37 °C
PCB inside the Temperature Chamber
ADC
UUT
Sinusoidal Waveform
Generator
Pulse Generator for
Clock Generation
Power / Ground / References
National
Instruments PXI
SPI/USB Interface
Computer
Algorithmic
ADC Out
12-bits
Figure 5-20: Algorithmic ADC mode dynamic errors test setup.
The measurement data for this experiment should facilitate the FFT computation like the one shown
in Figure 5-6, where Fsignal = 498.98 kHz with the Algorithmic ADC sampling-speed of 5 MSa/s.
Based on the 4096-point FFT computation, the performance metrics, namely, SFDR, SINAD, and
ENOB are computed as per the equations on Pages 52 - 54. Figure 5-21 plots the FFT computation
of the Algorithmic ADC output with an input tone of 498.98 kHz which achieves an ENOB of
10.134 bits.
74
Figure 5-21: FFT of the measured Algorithmic ADC output at 5 MSa/s with 499.25 kHz sine input
tone.
Figure 5-14 shows the dynamic performance of the 5 MSa/S Algorithmic ADC. Where the input
frequency is varied from DC up to the Nyquist rate (2.5 MHz). The computed ENOB in the
ECAP/ENAP band of interest (0.1- 10 kHz) is 10.24 bits.
Figure 5-22: Measured dynamic performance of the 5 MSa/s Algorithmic ADC for a single-tone
input.
75
Two-tone testing to compute intermodulation distortion (IMD) of the SAR-A ADC
5.11.1 Procedure for the two tone IMD testing
Figure 5-23 shows the measurement setup to perform the two-tone intermodulation distortion testing of
the ADC. The procedure for the two-tone intermodulation testing is outlined below.
• Two-tone intermodulation distortions are measured by applying two sinewaves to the input of the
ADC at frequencies f1 and f2. Frequency f2 is picked to be 1.1 f1.
• The amplitude of each of the tone is set slightly more than 6 dB below the full-scale range of the
ADC. This to ensure the ADC input does not go beyond the full-scale range, when the two tones
are added in phase.
• With the matched amplitude on both the signal generators, measure the 3
rd
order
intermodulation products 2f2 - f1 and 2f1- f2 and ratio them to the amplitude of the signals at
frequencies f1 and f2.
Figure 5-23: Measurement setup for the two-tone IMD testing of the SAR-A ADC.
5.11.2 Test setup and IMD measurement results of the two-tone testing for the SAR
ADC mode
Referring to Figure 5-23, Table 5.12 is built up to describe the test setup and instrumentation details
for the 3
rd
order IMD (IM3) procedure outlined in Section 5.11.1. The measurement data for this
experiment should facilitate the FFT computation that shows the two input tones and their 3
rd
order
intermodulation distortion tones 2f2 - f1 and 2f1- f2.
76
Table 5.12: Test Setup and instrumentation for the SAR ADC’s two-tone testing.
Components in
Figure 5-23
Test Equipment Input Conditions
Sinewave waveform
generator 1
Key-sight 33622A waveform
generator (Channel 1)
Varying input power levels (-10 to
+2 dBm) 48.4 kHz Sine waveform
(SAR ADC mode)
Sinewave waveform
generator 2
Key-sight 33622A waveform
generator (Channel 2)
Varying Input power levels (-10 to
+2 dBm) 48.9 kHz Sine waveform
(SAR ADC mode)
Power Combiner Pasternack PE2082 DC - 6 GHz rated at 2 Watts
Temperature
Chamber
Test Equity 105 Temperature
Half Cube Chamber
37 °C
The dynamic range is computed based on the 4096-point FFT computation. Figure 5-24 plots the
FFT of the two-tone IMD of the SAR ADC output which demonstrates a dynamic range of
68.873 dB. The input power levels are varied from -10 to +2 dBm to measure the dynamic range
due to two-tone IMD. The measurements are repeated three times at each input power level to
verify the robustness of the measurement setup and the repeatability of the measured result.
Figure 5-24: FFT of the measured SAR ADC output at 100 kSa/s for a two-tone input.
77
Table 5.13 lists the two-tone IMD DR for varying input-power levels. The mean DR variation for
three successive measurements on one chip is 0.56 dB for input-power from -10 to +2 dBm.
Table 5.13: Two tone IM3 results of the SAR ADC mode.
Two-Tone IM3 -- SAR ADC mode
Tone1
(Hz)
Tone2
(Hz)
Power
(dBm)
IM3
(dB)
IM3 Mean
(dB)
IM3 Std.
Deviation
48.4k 48.9k 0 68.873
48.4k 48.9k 0 68.842
48.4k 48.9k 0 68.845 68.853 0.0171
48.4k 48.9k 2 68.705
48.4k 48.9k 2 68.682
48.4k 48.9k 2 68.752 68.713 0.0357
48.4k 48.9k -2 69.106
48.4k 48.9k -2 69.128
48.4k 48.9k -2 69.141 69.125 0.0177
48.4k 48.9k -4 69.252
48.4k 48.9k -4 69.263
48.4k 48.9k -4 69.259 69.258 0.0056
48.4k 48.9k -6 69.254
48.4k 48.9k -6 69.26
48.4k 48.9k -6 69.268 69.261 0.0070
48.4k 48.9k -10 69.276
48.4k 48.9k -10 69.269
48.4k 48.9k -10 69.271 69.272 0.0036
5.11.3 Test setup and IMD measurement results of the two-tone testing for the
Algorithmic ADC mode
Referring to Figure 5-23, Table 5.14 is built up to describe the test setup and instrumentation details
for the 3
rd
order IMD (IM3) procedure outlined in Section 5.11.1. The measurement data for this
experiment should facilitate the FFT computation that shows the two input tones and their 3
rd
order
intermodulation distortion tones 2f2 - f1 and 2f1- f2. The dynamic range (DR) is computed based on
the 4096-point FFT computation. Figure 5-25 plots the FFT of the two-tone IMD of the Algorithmic
ADC output which achieves a SFDR of 67.241 dB. The input power levels are varied from
-10 to +2 dBm to measure the dynamic range due to two-tone IMD. The measurements are
repeated three times at each input power level to verify the robustness of the measurement setup
and the repeatability of the measured result.
78
Table 5.14: Test Setup and instrumentation for the Algo ADC’s two-tone testing.
Components in Figure
5-23
Test Equipment Input Conditions
Sinewave waveform
generator 1
Key-sight 33622A waveform
generator (Channel 1)
Varying input power levels
(-10 to +2 dBm)
2.425 MHz Sine waveform
(Algo ADC mode)
Sinewave waveform
generator 2
Key-sight 33622A waveform
generator (Channel 2)
Varying Input power levels
(-10 to +2 dBm)
2.45 MHz Sine waveform
(Algo ADC mode)
Power Combiner Pasternack PE2082 DC - 6 GHz rated at 2 Watts
Temperature Chamber
Test Equity 105 Temperature
Half Cube Chamber
37 °C
Figure 5-25: FFT of the measured Algorithmic ADC output at 5 MSa/s for a two-tone input.
Table 5.15 lists the two-tone IMD DR for varying input-power levels. The mean DR variation for
three successive measurements on one chip is 1.03 dB for input-power from -10 to +2 dBm. The
input power levels are varied from -10 to +2 dBm to measure the dynamic range due to two-tone
IMD. The measured plot of two-tone IMD – IM3 of the SAR ADC mode versus input-power levels
across three chips is shown in the Figure 5-26. The input power levels are varied from
-10 to +2 dBm to measure the dynamic range due to two-tone IMD.
79
Table 5.15: Two-tone IM3 results of the Algorithmic ADC mode.
Two-Tone IM3 – Algorithmic ADC mode
Tone1
(Hz)
Tone2
(Hz)
Power
(dBm)
IM3
(dB)
IM3 Mean
(dB)
IM3 Std.
Deviation
2.425M 2.45M 0 67.185
2.425M 2.45M 0 67.241
2.425M 2.45M 0 66.993 67.140 0.130
2.425M 2.45M 2 66.642
2.425M 2.45M 2 66.864
2.425M 2.45M 2 66.487 66.664 0.189
2.425M 2.45M -2 67.662
2.425M 2.45M -2 67.435 67.536 0.116
2.425M 2.45M -4 67.658
2.425M 2.45M -4 67.676
2.425M 2.45M -4 67.682 67.672 0.012
2.425M 2.45M -6 67.698
2.425M 2.45M -6 67.684
2.425M 2.45M -6 67.680 67.687 0.009
2.425M 2.45M -10 67.710
2.425M 2.45M -10 67.693
2.425M 2.45M -10 67.702 67.702 0.009
Figure 5-26: Two-Tone IMD Mean Dynamic Range vs Input-Power level for the SAR ADC mode,
measured on three chips.
The measured plot of two-tone IMD – IM3 of the Algorithmic ADC mode versus input-power levels
across three chips is shown in the Figure 5-27. The IM3 variation is 2.5 dB for input-power from
-10 to +2 dBm.
80
Figure 5-27: Two-Tone IMD Mean Dynamic Range vs Input-Power level for the Algorithmic ADC
mode, measured on three chips.
Measured performance summary of the SAR-A ADC
Table 5.16 summarizes the measurement results of the SAR-A ADC fabricated in XFAB XH018
180 nm CMOS process. These measurement results are recorded at human-body temperature of
37
o
C, with Analog and Digital power supply at 1.8 V. Table 5.17 shows the power-dissipation
measurement results of the SAR and the Algorithmic ADC modes of the SAR-A ADC.
Table 5.16: Measurement results summary of the SAR-A ADC.
The performance comparison table (Table 5.18) compares the best available standalone ADC
architectures in the relevant sampling-speed ranges suitable for implantable neuro-stimulators. The
SAR ADC Mode
(No. of chips measured = 5)
Algorithmic ADC Mode
(No. of chips measured = 3)
Measured Min Max Min Max
DNL (LSB) -0.14 0.54 -0.08 1.08
INL (LSB) -0.66 0.3 -0.17 1.17
Sampling-speed 100 kSa/s 145 kSa/s 4.983 MSa/s 5.1 MSa/s
SFDR (dB) 65.20 66.30 62.60 63.87
SINAD (dB) 64.10 65.08 61.30 62.77
ENOB (bits) 10.35 10.518 9.89 10.134
Two-Tone IMD SFDR (dB) 68.88 69.27 66.13 67.70
Power-dissipation 36.9 μW 37.8 μW 3.99 mW 4.07 mW
81
process-technology choice (180 nm CMOS and higher) was also the criteria to pick these
implementations to make a fair comparison. This is due to the availability of high-voltage (up to
20 V) Metal Oxide Semiconductor (MOS) transistors process-modules in these processes,
typically, used for the delivery of the neural-stimulation therapy. The normalized core
implementation-area is calculated by dividing the core implementation-area by the square of the
process-technology feature-size.
Table 5.17: SAR-A ADC Power-dissipation measured across five chips.
SAR-A ADC
Power-dissipation of the SAR ADC
mode sampling at 100 kSa/s
Power-dissipation of the Algorithmic
ADC mode sampling at 5 MSa/s
Chip 1 37.27 μW 4.07 mW
Chip 2 37.17 μW 4.14 mW*
Chip 3 37.80 μW 4.05 mW
Chip 4 37.21 μW 3.69 mW**
Chip 5 36.90 μW 3.99 mW
* Power-dissipation of Chip 2 in the Algorithmic ADC mode was measured with a bias-current increase of 2.5%.
** Power-dissipation for Chip 4 in the Algorithmic ADC mode was measured at 4.85 MSa/s sampling-rate.
Table 5.18: SAR-A ADC performance comparison with the best available standalone ADCs
suitable for implantable neuro-stimulators.
[27] [37]
This Work –
SAR-A ADC
CMOS Technology (L) 0.18 μm 0.25 μm 0.18 μm
Core
Implementation-area (A)
0.63 mm
2
0.15 mm
2
0.31 mm
2
Normalized Core
Implementation-area (A/L
2
)
(lower is better)
19.44e6 2.4e6 9.57e6
ADC Architecture SAR Algorithmic SAR Algorithmic
Target Resolution
8-bits or
12-bits
12-bits 12-bits 12-bits
ENOB (bits) 10.55 10.43 10.518 10.134
Sampling-Rate (Fs) [kSa/s] 100 3300 100 5000
Power-dissipation (P) --
normalized to 1.8 V supply
(lower is better)
45 μW 3.96 mW 36.9 μW 3.99 mW
Energy = P/ Fs [pJ] 450 1200 369 798
Walden FOM [92]
= P/ (2
ENOB
*Fs)
[ fJ/conv-step]
300 926 252 710
82
6 Architecture feasibility and Technology Scaling
The proposed architecture combines the SAR and the Algorithmic ADCs, to accomplish the
dual-sampling-rate feature needed for neural-sensing of LFPs and APs. This section addresses
four main questions that determine the feasibility and scaling of the proposed dual-sampling-rate
reconfigurable ADC architecture. They are:
1. Can we implement a standalone SAR ADC in a 180 nm CMOS process to achieve the
target dual-sampling-rate?
2. Can we implement a standalone Algorithmic ADC in a 180 nm CMOS process to achieve
the target dual-sampling-rate?
3. How does the shared-architecture SAR-A ADC scale (in terms of implementation-area and
power-dissipation), and compare with the standalone SAR ADC implementation?
4. As technology scales, how does the proposed shared-architecture SAR-A ADC scale?
The selection of fine feature-size CMOS process technologies for implantable
biomedical-applications is limited by the increasing IC design and fabrication costs in advanced
CMOS process technologies, the high unit (IC) cost due to the low product-volumes in implantable
biomedical-applications compared to the high product-volumes in consumer electronics, the
availability of high-voltage MOS transistor process-modules in the target CMOS
process-technology and the long product-development cycle times due to the stringent regulatory
approval process for the therapeutic use of implantable biomedical devices. In this chapter, we
ignore the above considerations and consider the impact of technology scaling on the SAR-A ADC
architecture for the sake of completeness.
Implementing a standalone, dual sampling-rate SAR ADC in 180 nm
CMOS process to achieve all target specifications
Measurement results in the previous section confirm that the SAR ADC mode can sample at
100 kSa/s. Therefore, the question is to determine the SAR ADC’s capability of sampling at
5 MSa/s. To implement a 5 MSa/s 12-bit SAR ADC in 180 nm CMOS process, the SAR clocking
must accommodate at least 14 clock (one purge, one sample and 12 conversions) cycles. This
83
means for a 5 MSa/s input sampling (sample every 200 ns), the sample cycle, as well as each
conversion cycle, is 14 ns. The two principal factors that determine the sampling-speed of the
SAR ADC are: the internal C-DAC’s acquisition (TAcquisition) and settling-time (Ts) within +/- ½ LSB
of the desired 12-bit resolution, and the ability of the comparator to resolve within +/- ½ LSB of the
reference voltage, within each conversion cycle. We can infer from the Algorithmic ADC mode’s
measurement results that the comparator can resolve to within +/- ½ LSB of the reference voltage
within 14 ns, by consuming more power. This means that the internal C-DAC’s settling-time is the
key factor for the operation of the SAR ADC at 5 MSa/s. Ideally, based on the SNR (74 dB) and
kBT/C requirements for 12-bit operation, the minimum (lumped) sampling capacitance of each
split-capacitor C-DAC is 2pF.
T
s
C
s
2
2 ( ln ( ) ) R
E
s
Equation (14)
The largest available fixed (in width and length) MOM (Metal-1 through Metal-5) capacitor-cell
layout with silicon-correlated model (that forms the basis of the capacitor-mismatch criteria) in
180 nm XFAB XH018 CMOS process is 52.8 fF. This means the minimum value (lumped) of the
sampling capacitor is 3.38 pF (= 2
6
* 52.8 fF based on the split 6-bit main-C-DAC and the 6-bit
sub-C-DAC), satisfying the constraints on the choice of the C-DAC’s unit-capacitor value shown in
Table 9.1, page 118. Assuming 10 ns (70% of 14 ns for 5 MSa/s operation) C-DAC output
settling-time, then the sampling capacitor (lumped for each split-capacitor sub-C-DAC) must be
less than 210 fF (Equation (14)), where R is the ON-resistance of the sampling switch and Es is the
sampling error. This means the smallest capacitor in the split-capacitor C-DAC must be 3.3 fF,
which is an order of magnitude smaller than the largest available MOM unit-capacitor (52.8 fF)
cell-layout. Therefore, 12-bit, 5 MSa/s SAR ADC operation is not feasible in 180 nm CMOS
process.
Implementing a standalone, dual sampling-rate Algorithmic ADC in
180 nm CMOS process to achieve all target specifications
The measurement results in Section 5.7, Section 5.10.3, and Section 5.11.3 confirm that the
Algorithmic ADC mode of the SAR-A ADC achieves all target specifications at 5 MSa/s. Therefore,
84
the second question reduces to the determination of how the Algorithmic ADC mode's performance
compares with that of the of the SAR-ADC mode at 100 kSa/s. To verify this, the transient
measurements of the Algorithmic ADC at 100 kSa/s were recorded. Figure 6-1 plots the computed
FFT of the measured transient output of the Algorithmic ADC mode of the SAR-A ADC for an input
tone of 9.985 kHz. The measured ENOB is 10.41 bits, which is inline with the measured ENOB
between 10.35 and 10.57 (across five chips) for the SAR ADC mode of the SAR-A ADC at
100 kSa/s (Table 5.16, page 80).
Figure 6-1: FFT of the measured Algorithmic ADC output sampling at 100 kSa/s with a
9.985 kHz input tone.
Table 6.1: Power-dissipation of the SAR-A ADC modes sampling at 100 kSa/s.
SAR-A
ADC
Power-
dissipation
Measured
Power-dissipation
of the SAR ADC
mode sampling at
100 kSa/s
Supply at 1.8 V
Measured
Power-dissipation
of the Algorithmic
ADC mode
sampling at
100 kSa/s
Supply at 1.8 V
Measured excess
power-dissipation
of the Algorithmic
ADC mode over
the SAR ADC
mode at 100 kSa/s
Factor by which
the Algorithmic
ADC mode
consumes more
power than the
SAR ADC mode
at 100 kSa/s
Chip 1 37.27 μW 59.6 μW 22.33 μW 1.599
Chip 2 37.17 μW 60.8 μW 23.63 μW 1.635
Chip 3 37.80 μW 58.7 μW 20.90 μW 1.552
Chip 4 37.21 μW 59.2 μW 21.99 μW 1.591
Chip 5 36.90 μW 60.3 μW 23.40 μW 1.634
Table 6.1 shows that, across five chips, the measured Algorithmic ADC mode of the SAR-A ADC
consumes approximately 1.6 more power than the SAR ADC mode of the SAR-A ADC at
85
100 kSa/s. While both the Algorithmic and the SAR modes of the SAR-A ADC achieve essentially
the same ENOB performance, the power-dissipation of Algorithmic ADC mode of the SAR-A ADC
at 100 kSa/s is higher than that of the SAR ADC mode of the SAR-A mode at 100 kSa/s by
approximately 1.6 due to the higher bias-currents (required to facilitate the operation of the ADC
at 5 MSa/s) of the comparator and the management of the active devices in the C+C (capacitive
addition) stages (see Section 4.2) used for the multiply-by-2, and the summation functions in the
Algorithmic ADC.
Technology scaling of the proposed shared-architecture, dual
sampling-rate SAR-A ADC and comparison with the standalone
SAR ADC (optimized for the higher sampling-speed of 5 MSa/s) to
achieve all target specifications
The first part of the question is: How does the SAR-A ADC scale (in terms of the power-dissipation
and the implementation-area), as CMOS technology feature-size scales?
The analysis that follows in this section for the scaling of power-dissipation assumes constant-field
scaling [117, 121] for CMOS process-technology nodes with minimum feature-size greater than or
equal to 130 nm, and general-scaling [20, 117, 121] for CMOS process-technology nodes with
minimum feature-size less than 130 nm. Constant-field scaling [117, 121] is assumed for CMOS
process-technology nodes with minimum feature-size greater than or equal to 130 nm because the
device dimensions (MOS transistor gate length (L) and the width (W)), the supply-voltage (and
in-turn, the ADC reference voltage (Vref)), and the minimum-width/spacing of the interconnect scale
by
1
𝑠 , where s is defined as the ratio of the minimum feature-size in the current CMOS
process-technology node to the minimum feature-size in the target CMOS process-technology
node [117, 121]. General scaling [20, 117, 121] is assumed for CMOS process-technology nodes
with minimum feature-size less than 130 nm (90 nm, 65 nm, 40 nm, 28 nm, etc.) because the
supply-voltage (Vsupply), and the threshold-voltage (Vt) have not scaled by
1
𝑠 . In general-scaling,
Vsupply, and Vt scale by
𝛼 𝑠 [121]. α is defined as the ratio
𝑉 ′
𝑉 , where V’ is the nominal supply-voltage
86
of the target CMOS process-technology node, and V is the nominal supply-voltage in the current
CMOS process-technology node.
The analysis in this section for the scaling of implementation-area assumes constant-field/general-
scaling for all CMOS process-technology nodes because the device dimensions (MOS transistor
gate length (L) and the width (W)), and the minimum-width/spacing of the interconnect scale
identically by
1
𝑠 for both constant-field and general-scaling methods [117, 121].
6.3.1 SARA-A ADC scaling in terms of the power-dissipation
The internal C-DAC power-dissipation of the SAR-A ADC in the SAR ADC mode at 100 kSa/s is
given by:
PC-DAC = ½ Fs 2
(N/2+2)
Cu Vref
2
Equation (15)
where Cu is the unit capacitance of the binary-weighted capacitor array, and Vref is the reference
voltage. Therefore,
PC-DAC ∝ Fs Cu Vref
2
Equation (16)
For CMOS process-technology nodes with minimum feature-size greater than or equal to 130 nm,
constant-field scaling implies that
PC-DAC ∝ 𝑠 ∗
1
𝑠 ∗
1
𝑠 2
Equation (17)
PC-DAC ∝
1
𝑠 2
Equation (18)
where s is defined as the ratio of the minimum feature-size in the current CMOS
process-technology node to the minimum feature-size in the target CMOS process-technology
node [117, 121].
The power-dissipation (average) of the shared-comparator is given by:
PShared-Comparator = Ibias * Vsupply Equation (19)
For CMOS process-technology nodes with minimum feature-size greater than or equal to 130 nm,
the drain-saturation-current
Ibias ∝ Cox
𝑊 𝐿 (VGS – Vt)
2
Equation (20)
The scaling of this bias-current (Ibias) is then given by,
87
Ibias∝(S*Cox)*
W
S
⁄
L
S
⁄
* (
(V
GS
-V
t
)
S
)
2
Equation (21)
This means that the shared-comparator’s power-dissipation for CMOS process-technology nodes
with minimum feature-size greater than or equal to 130 nm scales as
PShared-Comparator ∝
1
𝑠 2
Equation (22)
For CMOS process-technology nodes with minimum feature-size less than 130 nm, the drain
saturation-current of minimum gate-length devices deviates from Equation (20) and varies linearly
with respect to the gate-source voltage (VGS) of the MOSFET, due to velocity-saturation [117, 121].
Table 6.2: SAR-A ADC scaling in terms of power-dissipation.
SAR-A ADC
Circuit-Blocks
Power
Equation
Power-Scaling
Proportionality
(CMOS process-technology
nodes with minimum
feature-size greater than or
equal to 130 nm)
Power-Scaling
Proportionality
(CMOS process-technology
nodes with minimum
feature-size less than
130 nm)
Internal C-DAC
CV
2
f
∝
1
𝑠 2
∝
𝛼 2
𝑠 2
Shared-
Comparator
I
bias
V
supply
∝
1
𝑠 2
∝
𝛼 2
𝑠 2
Multiply-by-2
and
Summation
CV
2
f
∝
1
𝑠 2
∝
𝛼 2
𝑠 2
Digital
CV
2
f
∝
1
𝑠 2
∝
𝛼 2
𝑠 2
Based on the general-scaling approach, the drain-saturation-current of a MOSFET scales by
𝛼 𝑠
[121]. Therefore, the power-dissipation of the shared-comparator (Equation (19)) for CMOS
process-technology nodes with minimum feature-size less than 130 nm scales by
𝛼 2
𝑠 2
.
The power-dissipation of the remaining sub-blocks in the SAR-A ADC, namely, the internal-DAC,
the multiply-by-2 function, the summation circuits, and the digital circuit-blocks scales by
𝛼 2
𝑠 2
(based
on Equation (16)). The power-dissipation of the various sub-blocks of the scaled SAR-A ADC is
summarized in Table 6.2, where we can see that the power-dissipation of each of the sub-blocks
88
in the SAR-A ADC scales by
1
𝑠 2
for CMOS process-technology nodes with minimum feature-size
greater than or equal to 130 nm, and by
𝛼 2
𝑠 2
for CMOS process-technology nodes with minimum
feature-size less than 130 nm, where s is defined as the ratio of the minimum feature-size in the
current CMOS process-technology node to the minimum feature-size in the target CMOS process-
technology node [117, 121], and α is defined as the ratio
𝑉 ′
𝑉 , where V’ is the nominal supply-voltage
of the target CMOS process-technology node, and V is the nominal supply-voltage in the current
CMOS process-technology node [121]. For example, scaling the 180 nm CMOS SAR-A ADC in
this dissertation to 130 nm CMOS using constant-field scaling results in a scaled power-dissipation
of 19.24 μW and 2081.2 μW (by scaling the power-dissipation of the SAR-A ADC modes from
Table 5.18, page 81) for the SAR and the Algorithmic ADC modes respectively, operating from a
1.2 V supply. Similarly, scaling the 180 nm CMOS SAR-A ADC in this dissertation to 90 nm CMOS
using general-scaling results in a scaled power-dissipation of 2.84 μW and 307.87 μW (by scaling
the power-dissipation of the SAR-A ADC modes from Table 5.18, page 81) for the SAR and the
Algorithmic ADC modes respectively, operating from a 1 V supply.
6.3.2 SAR-A ADC scaling in implementation-area
The implementation-area of the SAR ADC is dominated by the binary-weighted capacitor array of
the internal C-DAC area
AC-DAC ∝ 2
(N/2+2)
Cu Equation (23)
where the area of the unit-capacitor (Cu) in the binary-weighted C-DAC scales as
𝑊𝐿
𝑠 2
.
Therefore,
AC-DAC ∝
1
𝑠 2
(keeping N constant) Equation (24)
The shared-comparator, and the Algorithmic ADC sub-blocks scale by the way of device
dimensions (
1
𝑠 for MOS transistor length, and
1
𝑠 for MOS transistor width).
Therefore, the implementation-area for the shared-comparator and Algorithmic ADC sub-blocks
scales as
AShared-Comparator ∝
1
𝑠 2
Equation (25)
89
AAlgo-sub-blocks ∝
1
𝑠 2
Equation (26)
Table 6.3 summarizes the scaling of the implementation-area of the SAR-A ADC, where we see
that the implementation-area of each of the sub-blocks in the SAR-A ADC scales by
1
𝑠 2
, where s is
defined as the ratio of the minimum feature-size in the current CMOS process-technology node to
the minimum feature-size in the target CMOS process-technology node [117, 121]. As noted earlier,
the scaling of implementation-area assumes constant-field/general-scaling for all CMOS
process-technology nodes because the device dimensions (MOS transistor gate length (L) and the
width (W)), and the minimum-width/spacing of the interconnect scales identically by
1
𝑠 for both
constant-field and general-scaling methods [117, 121].
Table 6.3: Implementation-area scaling of the scaled SAR-A ADC.
SAR-A ADC Circuit-Blocks Equation
Implementation-Area
Scaling
Proportionality
Internal C-DAC 2
(N/2+2)
C
u
∝
1
𝑠 2
Shared-Comparator WL ∝
1
𝑠 2
Multiply-by-2 and Summation WL ∝
1
𝑠 2
Digital WL ∝
1
𝑠 2
For example, scaling the 180 nm CMOS SAR-A ADC in this dissertation to 130 nm CMOS results
in a scaled implementation-area of 0.162 mm
2
(by scaling the implementation-area of the
SAR-A ADC from Table 5.18, page 81). Similarly, scaling the 180 nm CMOS SAR-A ADC in this
dissertation to 90 nm CMOS results in a scaled implementation-area of 0.0775 mm
2
(by scaling the
implementation-area of the SAR-A ADC from Table 5.18, page 81).
90
6.3.3 Power-dissipation comparison between the scaled SAR-A ADC and a standalone SAR ADC
designed to achieve target specifications for CMOS process-technology nodes with minimum
feature-size less than 130 nm
This sub-section answers the second part of the question in this section, namely: How does the
shared-architecture SAR-A ADC compare (in terms of the power-dissipation and the
implementation-area) to a standalone single SAR ADC (optimized for the higher sampling-speed
of 5 MSa/s), as the minimum CMOS feature-size scales?
To answer the question being addressed in this sub-section, let us break it up into two parts, based
on the modes of operation of the SAR-A ADC (SAR ADC mode at 100 kSa/s and Algorithmic ADC
mode at 5 MSa/s). General-scaling [20, 117, 121] is applied for CMOS process-technology nodes
with minimum feature-size less than 130 nm.
6.3.3.1 Compare the power-dissipation of the scaled, shared-architecture SAR-A ADC
operating in low-speed mode (100 kSa/s) with that of a standalone 5 MSa/s single
SAR ADC that has been designed for optimal operation at 5 MSa/s, operating at
100 kSa/s
The power-dissipation of the SAR ADC mode’s internal C-DAC of the SAR-A ADC scales
by
𝛼 2
𝑠 2
as per Table 6.2. Since we are operating the standalone SAR ADC at 100 kSa/s, the
power-dissipation of the internal C-DAC (which follows CV
2
Fs, per Equation (16)) also
scales by the sampling-speed (Fs) reduction from 5 MSa/s to 100 kSa/s. This reduction
factor X is given by (
5𝑒 6
100𝑒 3
). Therefore,
PStandalone-SAR-ADC-internal-C-DAC-100k ∝
𝛼 2
𝑋 𝑠 2
Equation (27)
To make a fair comparison, the power-dissipation of the internal C-DAC in the 100 kSa/s
SAR ADC mode of the SAR-A ADC is assumed to scale by
𝛼 2
𝑋 𝑠 2
as CMOS
process-technology scales. This is because the hypothetical standalone SAR ADC is
assumed to have a similar internal C-DAC architecture as the scaled SAR-A ADC’s internal
C-DAC. The bias-current and in turn, the power-dissipation of the comparator in the SAR
ADC designed for operation at 5 MSa/s does not scale with sampling rate, resulting in
roughly the same power-dissipation of the comparator at 5 MSa/s and 100 kSa/s. On the
91
other hand, the scaled SAR-A ADC’s comparator implementation would be optimized for
power-dissipation, and performance at 100 kSa/s operation. Therefore, the bias-current of
the shared-comparator in the scaled SAR-A ADC scales by
𝛼 2
𝑌 𝑠 2
, where Y is ratio of the
bias-currents (given by
I
bias (
5MSa
s
)
I
bias(
100kSa
s
)
) supplied to the shared-comparator for the two
sampling-speeds.
Therefore,
PSAR-ADC-Standalone-100k ∝
𝛼 2
𝑋 𝑠 2
+
𝛼 2
𝑠 2
Equation (28)
whereas,
PSAR-A-ADC-100k ∝
𝛼 2
𝑋 𝑠 2
+
𝛼 2
𝑌 𝑠 2
Equation (29)
Table 6.4 summarizes the power-scaling proportionality of the various sub-blocks of the
SAR ADC mode of the scaled SAR-A ADC operating at 100 kSa/s and the same
sub-blocks of the scaled, 5 MSa/s standalone SAR ADC operating at 100 kSa/s. We see
from Equations (28) and (29) that the total power-dissipation of the 100 kSa/s scaled
SAR-A ADC’s power-dissipation is lower than that of the 5 MSa/s standalone SAR ADC
operating at 100 kSa/s by (1 -
1
𝑌 )
𝛼 2
𝑠 2
, where Y is the ratio of bias-currents supplied to the
shared-comparator of the SAR-A ADC to that of the comparator of the 5 MSa/s standalone
SAR ADC operating at 100 kSa/s.
Table 6.4: Power-dissipation comparison between 100 kSa/s SAR-A ADC mode and a
5 MSa/s standalone SAR ADC operating at 100 kSa/s.
Standalone SAR
and SAR-A ADC
Circuit-Blocks
operational at
100 kSa/s
5 MSa/s Standalone
SAR ADC
Power-Scaling
Proportionality
100 kSa/s
SAR-A ADC
Power-Scaling
Proportionality
Notes
Internal C-DAC ∝
𝛼 2
𝑋 𝑠 2
∝
𝛼 2
𝑋 𝑠 2
X =
5𝑒 6
100𝑒 3
Comparator ∝
𝛼 2
𝑠 2
∝
𝛼 2
𝑌 𝑠 2
Y =
𝐼 𝑏𝑖𝑎𝑠 (
5𝑀𝑆𝑎 𝑠 )
𝐼 𝑏𝑖𝑎𝑠 (
100𝑘𝑆𝑎 𝑠 )
Digital ∝
𝛼 2
𝑠 2
∝
𝛼 2
𝑠 2
CV
2
f
92
6.3.3.2 Compare the power-dissipation of the scaled SAR-A ADC in high-speed mode
(5 MSa/s) with that of a 5 MSa/s standalone single SAR ADC at 5 MSa/s
Following the same approach as above and using general-scaling for the scaling of the
power-dissipation of a standalone, 5 MSa/s SAR ADC operating at 5 MSa/s, we get
PSAR-ADC-Standalone-5M ∝
𝛼 2
𝑠 2
(Internal C-DAC) +
𝛼 2
𝑠 2
(Comparator) +
𝛼 2
𝑠 2
(Digital)
Table 6.5: Power-dissipation comparison between 5 MSa/s SAR-A ADC mode and a
5 MSa/s standalone SAR ADC operating at 5 MSa/s.
Standalone SAR and
SAR-A ADC
circuit-blocks
operational at 5 MSa/s
Standalone SAR ADC
Power-Scaling
Proportionality
SAR-A ADC
Power-Scaling
Proportionality
Internal C-DAC ∝
𝛼 2
𝑠 2
--
Muitiply-by-2 and
Summation
-- ∝
𝛼 2
𝑠 2
Comparator ∝
𝛼 2
𝑠 2
∝
𝛼 2
𝑠 2
Digital ∝
𝛼 2
𝑠 2
∝
𝛼 2
𝑠 2
Therefore,
PSAR-ADC-Standalone-5M ∝
𝛼 2
𝑠 2
. Equation (30)
For the 5 MSa/s scaled SAR-A ADC, the power-dissipation will be
PSAR-A-ADC-5M ∝
𝛼 2
𝑠 2
(multiply-by- 2) +
𝛼 2
𝑠 2
(summation) +
𝛼 2
𝑠 2
(shared-comparator),
which means
PSAR-A-ADC-5M ∝
𝛼 2
𝑠 2
. Equation (31)
Table 6.5 summarizes the power-scaling proportionality of each of the sub-blocks in the
5 MSa/s Algorithmic ADC mode of the SAR-A ADC and that of the same sub-blocks in the
5 MSa/s standalone SAR ADC operating at 5 MSa/s. From Equations (30) and (31), we
see that the scaled shared-architecture SAR-A ADC operating at 5 MSa/s would have the
same power-dissipation as the 5 MSa/s standalone SAR ADC operating at 5 MSa/s.
93
6.3.4 Implementation-area scaling comparison between the scaled SAR-A ADC and a standalone
SAR ADC designed to achieve target specifications up to 5 MSa/s for CMOS process-
technology nodes with minimum feature-size less than 130 nm
The scaling of implementation-area assumes constant-field/general-scaling for all CMOS
process-technology nodes because the device dimensions (MOS transistor gate length (L) and the
width (W)), and the minimum-width/spacing of the interconnect scales identically by
1
𝑠 for both
constant-field and general-scaling methods [117, 121]. Following the discussion that answers the
first part of the technology scaling question, the SAR-A ADC’s implementation-area scales as
follows (see Table 6.3):
ASAR-A-ADC ∝
1
𝑠 2
(AC-DAC) +
1
𝑠 2
(Ashared-comparator) +
1
𝑠 2
(AAlgo-sub-blocks) +
1
𝑠 2
(ADigital) Equation (32)
Therefore,
ASAR-A-ADC-implementation-area ∝
1
𝑠 2
Equation (33)
Similarly, for the standalone single SAR-ADC, the implementation-area will scale as
ASAR--ADC-standalone ∝
1
𝑠 2
(AC-DAC) +
1
𝑠 2
(AComparator) +
1
𝑠 2
(ADigital) Equation (34)
Therefore,
ASAR--ADC-standalone-implementation-area ∝
1
𝑠 2
. Equation (35)
Table 6.6: Implementation-area scaling comparison between the scaled SAR-A ADC and a
standalone SAR ADC designed to achieve target specifications up to 5 MSa/s.
Standalone SAR and
SAR-A ADC Circuit-Blocks
Standalone SAR ADC
Implementation-Area
Scaling Proportionality
SAR-A ADC
Implementation-Area
Scaling Proportionality
Internal C-DAC ∝
1
𝑠 2
∝
1
𝑠 2
Shared Comparator ∝
1
𝑠 2
∝
1
𝑠 2
Multiply-by-2 and Summation -- ∝
1
𝑠 2
Digital ∝
1
𝑠 2
∝
1
𝑠 2
Table 6.6 summarizes the implementation-area proportionality of each of the sub-blocks in the
scaled SAR-A ADC and that of the same sub-blocks in the scaled, 5 MSa/s standalone SAR ADC.
From Equations (32) and (34) and Table 6.6, we see that the scaled SAR-A ADC’s
94
implementation-area is larger than that of the scaled, standalone SAR-ADC designed to achieve
target specifications up to 5 MSa/s by
1
𝑠 2
, which corresponds to the implementation-area of the
multiply-by-2 and summation sub-blocks in the SAR-A ADC (that occupy 26% of the
implementation-area of the SAR-A ADC in 180 nm CMOS process-technology). Here, s is defined
as the ratio of the minimum feature-size in the current CMOS process-technology node to the
minimum feature-size in the target CMOS process-technology node [117, 121].
Technology scaling of the proposed shared-architecture, dual
sampling-rate SAR-A ADC to achieve all target specifications
The availability of high-voltage MOS transistor process-modules in CMOS process-technology
nodes with minimum feature-size less than 100 nm, will enable the integration and implementation
of the neuro-stimulators and the neural-sensing front-end on the same die in those CMOS
process-technology nodes. With relevance to the targeted sampling-speeds (100 kSa/s and
5 MSa/s) and ADC resolution (12-bits), technology scaling is considered to the 40 nm CMOS
process-technology node for the purpose of comparing the extrapolated performance of the
hypothetical scaled shared-architecture SAR-A ADC with the best performing, published SAR ADC
implementations in the finest feature-size (found to be 40 nm at the time of writing this dissertation)
CMOS process-technology [113, 114, 115], having specifications closest to the target
specifications of the shared-architecture SAR-A ADC in this dissertation. Table 6.7 shows the
extrapolated performance of the scaled SAR-A ADC architecture if it were to be implemented in
the selected CMOS process-technology nodes of 65 nm and 40 nm.
The extrapolated implementation-area and power-dissipation numbers of the hypothetical scaled
SAR-A ADC in Table 6.7 are based on the results from [116], which points out that the
general-scaling method [20, 117] is becoming increasingly less accurate for predicting performance
metrics as well as comparing designs across deep-submicron process-technology nodes.
For the implementation-area scaling between CMOS process-technology nodes, [116] calculates
the geometric-mean of the scaling-factors related to the minimum feature-size, Metal-1 half-pitch
and the logic gate-size, all of which are obtained from the International Technology Roadmap for
95
Semiconductors (ITRS) reports [118,119]. Table 6.7 shows the implementation-area scaling of the
SAR-A ADC based on the area-scaling factors (Table 4 of [116]). For power-dissipation, delay and
energy scaling, [116] updates the general-scaling method by implementing a curve-fit technique
based on the HSPICE simulations to model the CMOS circuit performance from different
process-technology nodes using the Predictive Technology Model (PTM) [120] and the ITRS
reports. The analysis and results in [116] focusses only on the scaling of digital circuits for different
process-technology nodes. The scaling of analog circuits is not addressed in [116]. We therefore,
use the results of general-scaling to address the scaling of power-dissipation, delay and energy of
the analog circuits in CMOS process-technology nodes with minimum feature-size less than
130 nm. All sub-blocks in the SAR-A ADC except for the shared-comparator are digital
circuit-blocks. The shared-comparator is an analog circuit-block. This is reflected in the
power-scaling proportionality equations for the sub-blocks in the SAR-A ADC (Table 6.2, page 87)
which have been derived using the general-scaling approach (see Section 6.3, page 85) for CMOS
process-technology nodes with minimum feature-size less than 130 nm. Therefore, the scaling
equations in [116] can be applied to the digital circuit-blocks in the SAR-A ADC. We need to
determine the fraction of the total power-dissipation that the shared-comparator (the analog circuit-
block in the SAR-A ADC) consumes for each of the SAR-A ADC modes and scale that using
general-scaling equations. The power-dissipation of the rest of the SAR-A ADC (digital circuit-
blocks) will be scaled using the equations in [116].
The average power-consumption of the shared-comparator of the SAR-A ADC implemented in
180 nm CMOS process-technology node for one conversion-cycle (corresponding to twenty (20)
clock-cycles for 12-bit operation) is determined to be 1.935 μW and 382 μW in the SAR and the
Algorithmic ADC modes of the SAR-A ADC respectively, from transient simulations of the
post-layout parasitic-extracted netlist of the 180 nm CMOS SAR-A ADC. This translates to 5.24 %
and 9.57 % of the total power-dissipation of the SAR-A ADC implemented in 180 nm CMOS
process-technology node (see Table 5.18, page 81) for the SAR and the Algorithmic ADC modes
respectively, from a 1.8 V supply.
96
The power-dissipation of the scaled shared-comparator in a target CMOS process-technology node
is calculated by applying the general-scaling equation (Table 6.2, page 86), with the allocation of
5.24 % and 9.57 % of the total power-dissipation for the SAR and the Algorithmic ADC modes
respectively.
The power-dissipation of the scaled digital circuit-blocks of the SAR-A ADC is obtained by using
equation 6, equation 9, and the coefficient values from Table 5 of [116] to scale the remaining
94.76 % and 90.43 % of the total power-dissipation of the SAR and the Algorithmic ADC modes of
the SAR-A ADC respectively, for the same target CMOS process-technology node.
The scaled, total power-dissipation value for the SAR-A ADC in a target CMOS process-technology
node (shown in Table 6.7 for 65 nm and 40 nm CMOS process-technology nodes) is the sum of
the power-dissipation values of the scaled shared-comparator and the scaled digital circuit-blocks
in that target CMOS process-technology node.
The sampling-rate (100 kSa/s for the SAR ADC and 5 MSa/s for the Algorithmic ADC) as well as
the measured ENOB, are assumed to be constant (un-changed) as process-technology scales for
the calculation of the Walden Figure-of-Merit (FOM).
Table 6.7: Performance comparison table with the scaled SAR-A ADC.
[122] [113] [114] [115]
Extrapolated performance of the scaled
SAR-A ADC**
CMOS Technology 65 nm 65 nm 40 nm 40 nm 65 nm 40 nm
Core Area (mm
2
) 0.076 0.07 0.014 0.0675 0.0258 0.0105
Supply [V] 0.6 1.1 0.7 1.0 1.0 0.7
Architecture SAR SAR SAR SAR SAR Algorithmic SAR Algorithmic
Resolution [bits] 12 10 12 13 12 12 12 12
ENOB [bits] 10.1 9.11 11.19 10.36 10.51 10.13 10.51 10.13
Sampling-speed
(Fs) [Sa/s]
40k 30M 200k 6.4M 100k 5M 100k 5M
Power-dissipation
(P) [μW]
0.097 850 0.51 46 1.844 197.607 0.486 51.520
Walden FOM [92]
= P/(2^ENOB*Fs)
[fJ/conv-step]
2.2 51 1.1 5.5 12.645 35.270 3.333 9.195
97
Comparing the 65 nm CMOS SAR ADC implementations [113, 122] to the extrapolated
performance of the scaled 65 nm CMOS SAR-A ADC in Table 6.7, we see that the scaled
shared-architecture SAR-A ADC results in an extrapolated implementation that is 2.71 smaller in
on-chip implementation-area, and features a Walden FOM that is higher by 10.445 fJ/conv-step
when compared with the 65 nm CMOS 40 kSa/s asynchronous SAR ADC operating from a 0.6 V
supply [122], and lower by 15.73 fJ/conv-step when compared with the 65 nm CMOS 30 MSa/s
SAR ADC operating from a 1.1 V supply [113]. [122] has a Walden FOM that is lower by
10.445 fJ/conv-step and a power-dissipation that is lower by 1.747 μW than the extrapolated
Walden FOM and the extrapolated power-dissipation of the scaled 65 nm CMOS, 100 kSa/s
SAR ADC mode of the SAR-A ADC due to the following reasons:
a. Reduced power supply-voltage (0.6V) of operation compared to the nominal supply
voltage of 1.0 V for core transistors in 65 nm CMOS, possibly due to leveraging the low
sampling-rate of 40 kSa/s for moderate-inversion/sub-threshold biasing of core transistors
in the analog comparator
b. Choice of asynchronous clock-signals for the SAR ADC operation
c. Choice of 250 aF unit-capacitor cell for realizing the internal C-DAC of the SAR ADC
which reduces the power dissipated for driving the C-DAC to its final value in the time
constraint determined by the 40 kSa/s sampling rate.
It should be noted that using a 250 aF unit-capacitor cell will result in poor DNL and INL for
SAR ADC resolution of 12 bits (see Table 5.16, page 80) and reduced ENOB (see Table 5.18,
page 81), which is evident from the measured results presented in [122]. These deficiencies can
be traced to the input-referred kBT/C noise (see Section 9.1.1, page 114) and yield consequences
(see Section 9.1.2, page 115) of the design choice of 250 aF for the unit-capacitor cell for the
internal C-DAC for a 40 kSa/s SAR ADC with resolution of 12-bits.
We see from Table 6.7 (highlighted columns), that the shared-architecture SAR-A ADC scales
favorably in comparison with traditional SAR ADCs in a CMOS process-technology node with
minimum feature-size of 40 nm, and results in an extrapolated implementation that is 6.43 smaller
in on-chip implementation-area, and features a Walden FOM that is higher by 2.233 fJ/conv-step
98
and 3.695 fJ/conv-step for the sampling-speeds of 100 kSa/s and 5 MSa/s respectively, when
compared with the best performing, published SAR ADC implementations in the finest feature-size
(found to be 40 nm at the time of writing this dissertation) CMOS process-technology node [114,
115], having specifications closest to the target specifications of the shared-architecture
SAR-A ADC in this dissertation.
Therefore, we conclude that the shared-architecture SAR-A ADC scales favorably in comparison
with traditional SAR ADCs in CMOS process-technology nodes with minimum feature-size less
than 130 nm.
Future work: Scaling the proposed shared-architecture,
dual sampling-rate SAR-A ADC to sub-40 nm CMOS process-
technology
The technology-scaling analysis in this chapter relies only on the small-signal transistor parameters that
are expected to scale with CMOS process-technology. It is expected that circuit design considerations
will have to reckon with reduced supply-voltage and limited transistor-width palette in FinFET on Bulk
[106, 107] and FinFET on FD-SOI [106, 107] transistors as CMOS process-technology scales below
40 nm. Double-patterning for sub-40 nm CMOS process-technology nodes [108, 109, 112] and triple-
patterning for sub-12 nm CMOS process-technology nodes [110, 111] are prevalent in the absence of
Extreme Ultra-Violet (UV) lithography [111] for low-level interconnect layers (Poly-1, Metal-1, Metal-2,
Metal-3, etc.) as the feature-pitch is below the resolution limit of the optical projection-system used in
photo-lithography in the CMOS manufacturing process. The additional multiple-patterning layout and
pattern-density requirements for each metal-layer in sub-40 nm CMOS process-technology nodes place
additional constraints on the determination of the required design values and layout realization of the
unit-capacitor cells for the DACs in the ADCs [see Section 9.1, page 114]. These considerations may
dictate the choice of MIM capacitor unit-cells (if available in the CMOS process-technology node) instead
of MOM capacitor unit-cells. The refinement of the SAR-A ADC architecture technology-scaling analysis,
which takes the above considerations into account for sub-40 nm CMOS process-technology nodes, is
left for future work. Within the constraints of the above considerations, the proposed SAR-A ADC
architecture is not anticipated to have any limitations due to CMOS process-technology scaling.
99
7 Dissertation Summary
This research work has proposed, implemented, measured and validated an original shared-architecture
ADC for implantable biomedical systems which enables simultaneous 32-channel neural LFP and
AP sensing, to achieve significantly lower area at similar power and specifications as standalone ADCs
that achieve desired specifications in each sampling range, by combining the two ADC architectures:
the SAR ADC operating at sampling-speed of 100 kSa/s and the Algorithmic ADC operating at
sampling-speed of 5 MSa/s, providing 12-bits of resolution in each sampling-speed range. It has
validated the area and power advantages of the shared-architecture SAR-A ADC over that of two
standalone ADCs for the desired application with the same target ADC specifications. The SAR-A ADC
architecture was first designed, implemented and simulated in the 0.35 µm CMOS XFAB XH035
process, where the core implementation-area of the 12-bit SAR-A ADC in the 0.35 µm CMOS XFAB
XH035 process was 0.55 mm
2
. The worst-case post-layout simulation power consumption of the 12-bit
SAR-A ADC was 95.5 µW for the SAR ADC mode sampling at 100 kSa/s and 4.87 mW for the
Algorithmic ADC mode sampling at 5 MSa/s. With CMOS technology scaling rapidly, and with the
availability of the high-voltage MOS transistor process-modules in deep sub-micron CMOS process such
as 180 nm CMOS, the SAR-A ADC was designed, implemented, fabricated and its performance
measured utilizing the XFAB XH018 180 nm CMOS fabrication process as a test vehicle.
The 12-bit SAR-A ADC architecture is fabricated in CMOS 6M1P XFAB XH018 process with a
supply-voltage of 1.8 V, occupying a core implementation-area of 0.31 mm
2
. In the 100 kSa/s SAR ADC
mode, the ADC achieves a measured SFDR of 66.3 dB, a measured SINAD of 65.081 dB, and a
measured ENOB of 10.518 bits. The measured DNL and INL of the SAR ADC mode are 0.54 LSB and
0.66 LSB, respectively. In the Algorithmic ADC mode, at 5 MSa/s, the ADC achieves a measured SFDR
of 63.87 dB, a measured SINAD of 62.77 dB and a measured ENOB of 10.134 bits. The measured DNL
and INL of the Algorithmic ADC mode are 1.08 LSB and 1.17 LSB, respectively. The measured
power-dissipation (including the analog, digital, and reference) is 36.9 μW and 3.99 mW for the SAR and
the Algorithmic ADC modes of the SAR-A ADC respectively, from a 1.8 V supply. Analog circuit-blocks,
such as the chopper-stabilized comparator and the input switches, have been re-used in the SAR-A ADC
100
architecture, between the SAR and the Algorithmic ADC implementations, to reduce the
implementation-area and normalize the mismatch, input-referred DC-offset and 1/f noise contributions
across the two modes. A two-tone test to compute IMD for both the modes reveals the SAR-A ADC’s
linearity and its capability of identifying two tones with a measured dynamic range of 68.87 dB
(SAR ADC mode) and 67.24 dB (Algorithmic mode) close to their respective Nyquist frequencies.
The SAR and Algorithmic ADC modes achieve a Walden FOM [92] of 252 and 710 fJ/conv-step
respectively, operating from a 1.8 V supply.
This research work demonstrates the truth of the dissertation research hypothesis that the proposed
shared-architecture SAR-A ADC, when compared with the best performing implementations for
standalone ADC (SAR / Algorithmic) architectures [27, 37] with comparable specifications to the
SAR-A ADC in this dissertation, results in an implementation that is 2.52 smaller in on-chip
implementation-area, and features a Walden FOM that is lower by 48 fJ/conv-step and 216 fJ/conv-step
for the targeted sampling-speeds of 100 kSa/s and 5 MSa/s respectively (see Table 5.18, page 81), for
the targeted ADC resolution (12-bits) and the choice of CMOS process-technology node for the desired
closed-loop implantable biomedical systems, usually integrated with neural-stimulation circuitry. The
choice of CMOS process-technology node corresponds to those CMOS process-technology nodes with
high-voltage MOS transistor process-modules, which at the time of writing this dissertation, have
minimum feature-size greater than or equal to 180 nm.
The shared-architecture SAR-A ADC scales favorably in comparison with traditional SAR ADCs in
CMOS process-technology nodes with minimum feature-size less than 130 nm. The scaling analysis in
Table 6.7 (page 96) shows that an extrapolated implementation of the SAR-A ADC in CMOS
process-technology node with minimum feature-size of 40 nm is 6.43 smaller in on-chip
implementation-area, and features a Walden FOM that is higher by 2.233 fJ/conv-step and
3.695 fJ/conv-step for the sampling-speeds of 100 kSa/s and 5 MSa/s respectively, when compared with
the best performing, published SAR ADC implementations in the finest feature-size (found to be 40 nm
at the time of writing this dissertation) CMOS process-technology nodes [114, 115], having specifications
closest to the target specifications of the shared-architecture SAR-A ADC in this dissertation.
101
8 References
1. J. L. Collinger et al., “High-performance neuroprosthetic control by an individual with tetraplegia,”
Lancet, Vol. 381, no. 9866, pp. 557–564, 2013.
2. L. R. Hochberg et al., “Reach and grasp by people with tetraplegia using a neurally controlled
robotic arm,” Nature, Vol. 485, no. 7398, pp. 372–375, 2012.
3. Sun FT, Morrell MJ, “The RNS System: responsive cortical stimulation for the treatment of refractory
partial epilepsy”, Expert Rev Med Devices, 11: 563-572, 2014.
4. Xilin Liu et al., “Design of a Closed-Loop, Bidirectional Brain Machine Interface System with
Energy Efficient Neural Feature Extraction and PID Control”. IEEE TBioCAS, Aug. 2017.
5. H. Rhew et al., “A fully self-contained logarithmic closed-loop deep brain stimulation SoC with
wireless telemetry and wireless power management,” IEEE JSSC, Oct. 2014.
6. Gao et al., “A 96-ch full data rate direct neural interface in 0.13 μm CMOS”, IEEE JSSC, April 2012.
7. Zou et al., “A 100-channel 1-mW implantable neural recording IC, IEEE TCAS-1, Oct. 2013.
8. Han et al., “A 0.45V 100-Channel Neural-Recording IC with Sub-μW/Channel Consumption in
0.18μm CMOS”, IEEE ISSCC, 2013.
9. Cohen et al., “Contributions of intrinsic and synaptic activities to the generation of neuronal
discharges in in-vitro hippocampus”. Journal of Physiology, pp 485-502, 2000.
10. Thorbergsson et al., “Minimizing data transfer with sustained performance in wireless brain-
machine interfaces”, Journal of Neural Engineering, 2012.
11. Y. Ghanbari et al., "Robustness of neural spike sorting to sampling rate and quantization bit
depth", 16th International Conference on DSP, July 2009.
12. http://www.maxim-ic.com/app-notes/index.mvp/id/748 “Figure 5 in Application note on
“Understanding how ADC errors affect system performance”.
13. Fee et al., "Automatic sorting of multiple unit neuronal signals in the presence of anisotropic
and non-Gaussian variability", Journal of neuroscience methods, Vol. 69, Nov.1996.
14. M.J.M. Pelgrom et al., “Matching properties of MOS transistors,” IEEE JSSC, Vol. 24, pp. 1433-
1439, Oct. 1989.
102
15. Ali-Hajimiri et al., “Design issues in cross-coupled inverter sense amplifier”, ISCAS, 1998.
16. C. C. Enz and G. C. Temes, "Circuit Techniques for Reducing the Effects of Op-Amp
Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilization," IEEE,
JSSC, Nov. 1996.
17. Argus III Retinal Prosthesis system, 2-sight medical products, Sylmar, California.
18. Sumesaglam et al., “A digital automatic tuning technique for higher-order continuous time
filters”, IEEE TCAS-1, Oct 2004.
19. Papathanasiou et al., “An implantable CMOS signal conditioning system for recording nerve
signals with cuff electrodes”, IEEE ISCAS, 2000.
20. Mark Bohr, “A 30 Year retrospective on Dennard’s MOSFET scaling paper”, IEEE Solid-State
Circuits Society Newsletter, Vol. 12, Issue:1, Winter 2007.
21. Li, P.W.; Chin, M.J.; Gray, P.R.; Castello, R., “A ratio-independent algorithmic analog-to-digital
conversion technique” IEEE JSSC, Dec. 1984.
22. Suarez, R.E., Gray, P.R., Hodges, D.A, “All-MOS charge-redistribution analog-to-digital
conversion techniques. II” IEEE JSSC, Dec. 1975.
23. Avestruz et al., “A 5 μW/Channel Spectral Analysis IC for Chronic Bidirectional Brain–Machine
Interfaces”, IEEE JSSC, Dec. 2008.
24. Xiang Fang et al., “A CMOS 12 bit 50 kSa/S micro-power SAR and Dual-slope Hybrid ADC”,
IEEE MWSCAS, 2009.
25. H. Yu et al., “Low power interface circuits for bio-implantable Microsystems”, ISSCC, 2003.
26. Cranicixx, J et al., “A 65fJ/Conversion-Step 0-50 MSa/s 0 to 0.7 mW, 9bit charge sharing SAR
ADC”, IEEE ISSCC, 2007.
27. Verma, N.; Chandrakasan, A.P., “An Ultra-Low Energy 12-bit Rate-Resolution Scalable SAR
ADC for Wireless Sensor Nodes”, IEEE JSSC, June 2007.
28. Jin-Sheng Wang, Chin-Long Wey, “A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic
A/D converter”, IEEE TCAS II, May 1999.
29. Hoonki Kim, et al., “A Low Power Consumption 10-bit Rail-to-Rail SAR ADC Using a C-2C
Capacitor Array”, IEEE EDSSC, Dec. 2008.
103
30. Bonfini, G et al., “An ultra-low-power switched Opamp-based 10-B integrated ADC for
Implantable Biomedical Application”, IEEE TCAS I, Jan. 2004.
31. Jarvin, A, et al., “A 12-Bit, 41.67 kSa/s, 32 μW Ratio-Independent Algorithmic ADC”, IEEE VLSI
Circuits Conference, 2006.
32. Shrivastava A, “12-bit non-calibrating noise-immune redundant SAR ADC for system-on-a-chip
IEEE ISCAS, May 2006.
33. Min Gyu Kim, et al., “A 10MS/s 11-b 0.19mm2 Algorithmic ADC with Improved Clocking”, IEEE
VLSI Circuits Conference, 2006.
34. Yotsuyanagi, M et al., “A 12 bit 5 μsec CMOS recursive ADC with 25 mW power consumption”,
IEEE CICC, May 1989.
35. Doyle, J et al., “A low power 12-bit ADC for systems applications”, IEE Colloquium on Systems
on a Chip, Sept. 1998.
36. M. Yoshioka et al., “A 10b 50MS/s 820μW SAR ADC with On-Chip Digital Calibration”, IEEE
ISSCC, 2010.
37. Patrick Quinn et al., “Capacitor Matching Insensitive 12-bit 3.3 MS/s Algorithmic ADC in 0.25μm
CMOS”, IEEE CICC, 2003.
38. Rabii S et al., “A 1.8-V digital-audio ∑∆ modulator in 0.8-μm CMOS”, IEEE JSSC, June 1997.
39. Gerfers et al., “A 1.5-V 12-bit power-efficient continuous-time third-order ∑∆”, IEEE JSSC,
Aug. 2003.
40. Scott et al., “An ultra–low power ADC for distributed sensor networks”, IEEE ESSIRC, 2002.
41. Hwi-Cheol Kim et al., “A partially switched-Opamp technique for high-speed low-power
pipelined analog-to-digital converters”, IEEE TCAS I, April 2006.
42. Promitzer, G et al., “12-bit low-power fully differential switched capacitor noncalibrating
successive approximation ADC with 1 MS/s”, IEEE JSSC, July 2001.
43. Oliaei, O et al., “A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE”,
IEEE JSSSC, Jan. 2002.
44. Roy, Tan Kuo Hwi et al., “A 0.9V 100nW Rail-to-Rail SAR ADC for Biomedical Applications”,
IEEE International Symposium on Integrated Circuits, Sept. 2007.
104
45. Van der Zwan, E.J et al., “A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system for AM/FM
radio receivers”, IEEE JSSC, Dec. 2000.
46. Ji-Jon Sit et al., “A micropower logarithmic A/D with offset and temperature compensation”
IEEE JSSC, Feb. 2004.
47. Jarvinen, J.A.M et al., “A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor
Interface”, IEEE ISCAS, May 2007.
48. Kianpour, I et al., “An 8-bit 166nw 11.25 kS/s 0.18um two-Step-SAR ADC for RFID applications
using novel DAC architecture” NORCHIP, 2010.
49. Pietri, S et al., "A fully integrated touch screen controller based on 12b 825kS/s SAR ADC"
Micro-Nanoelectronics, Technology and Applications, 2009.
50. Hwang-Cherng Chow et al., “1V 10-bit successive approximation ADC for low power
biomedical applications,” European Conference on Circuit Theory and Design, Aug. 2007.
51. J. Sauerbrey, D et al.,” A 0.5V 1-uW Successive Approximation ADCIEEE JSSC July 2003.
52. H. C. Chow et al., “A 1.8V, 0.3mW, 10-bit SA-ADC with New Self-Timed Timing Control for
Biomedical Applications”, IEEE ISCAS, May 2005.
53. Chen, Yen-Ju et al., “A 1-V 8-bit 100kS/s-to-4MS/s asynchronous SAR ADC with 46fJ/conv.-
step”, VLSI Design, Automation and Test (VLSI-DAT), 2011.
54. C. Liu et al., “A 10b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation”, IEEE
ISSCC, 2010.
55. C. Liu et al., “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure”,
IEEE JSSC, April 2010.
56. Marcus Yip, Anantha Chandrakasan, “A resolution-reconfigurable 5-to-10b, 0.4-to-1V power
scalable SAR ADC”, IEEE ISSCC, Feb. 2011.
57. Hegong Wei et al., “A 0.024mm2 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in
65 nm CMOS”, IEEE ISSCC 2011.
58. Pieter Harpe et al., “A 30fJ/Conversion-Step 8b 0-to-10MS/s Asynchronous SAR ADC in
90 nm CMOS”, IEEE ISSCC 2010.
105
59. Chun-Cheng Liu et al., “A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in
0.18μm CMOS” IEEE VLSI Conference, 2010.
60. Michael D. Scott et al., “An Ultralow-Energy ADC for Smart Dust”, IEEE JSSC July 2003.
61. Reid Harrison et al., “A custom multielectrode array with integrated low-noise amplifiers”, IEEE
Engineering in Medicine and Biology Conference, 2003.
62. Urrestarazu, et al., “Interictal high-frequency oscillations (100-500 Hz) in the intracerebral EEG
of epileptic patients”, Brain, 2007.
63. Staba et al., “Quantitative analysis of high-frequency oscillations (80-500 Hz) recorded in
human epileptic hippocampus and entorhinal cortex”, Journal of Neurophysiology, 2002.
64. Jin-Sheng Wang, Chin-Long Wey, “A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic
A/D converter”, IEEE TCAS II, May 1999.
65. Chun-Jen et al., “A low-voltage CMOS rail-to-rail operational amplifier”, IEEE ISCAS 2004.
66. Jarvin et al., “A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC”, IEEE VLSI Circuits
Conference, 2006.
67. Min Gyu Kim et al., “A 10MS/s 11-b 0.19mm2 Algorithmic ADC with Improved Clocking”, IEEE
VLSI Circuits Conference, 2006.
68. Yotsuyanagi, M et al., “A 12 bit 5 μsec CMOS recursive ADC with 25 mW power consumption”,
IEEE CICC, May 1989.
69. Patrick Quinn et al., “Capacitor Matching Insensitive 12-bit 3.3 MS/s Algorithmic ADC in 0.25μm
CMOS”, IEEE CICC, 2003.
70. Rhew et al., Wirelessly powered log-based closed-loop deep brain stimulation SoC with two-
way wireless telemetry for treatment of neurological disorders”, IEEE VLSI, 2012.
71. Firpi et al., “High-frequency oscillations detected in epileptic networks using swarmed neural-
network features”, Annals of Biomedical engineering, Vol. 35, No 9, 2007
72. Worrell et al., “High-frequency oscillations in human temporal lobe: simultaneous microwire
and clinical macroelectrode recordings”, Pg. 928-937, Brain Journal of Neurology, 2008
73. http://www.hopkinsmedicine.org/healthlibrary/conditions/nervous_system_disorders/refractory
epilepsy_135,5/
106
74. Verma, N et al., “EEG acquisition SoC with integrated feature extraction processor for a chronic
seizure detection system”, IEEE JSSC, Vol. 45, No 4, 2010.
75. Ali Shoeb et al., “Impact of patient-specificity on seizure onset detection performance”, IEEE
EMBS Conference, France, Aug 2007.
76. Verma, N et al., “Data-driven approaches for computation in biomedical devices: A case study
of EEG monitoring for chronic seizure detection”, Journal of Low-Power electronics, April 2011.
77. Chen et al., “The implementation of a Low-Power biomedical signal processor for real-time
epileptic seizure detection on absence animal models”, IEEE Journal on Emerging and
selected topics in circuits and systems, Vol. 1, No.4, Dec 2011
78. de Chazal et al., “Automatic classification of heartbeats using ECG morphology and heartbeat
interval features”, IEEE Trans. Biomed. Eng., Vol. 51, 2004.
79. Shoeb, Guttag,” Application of machine learning to epileptic seizure detection”, 27
th
International conf. on Machine Learning, Israel, 2010.
80. Bertram, “The relevance of kindling for human epilepsy”, Epilepsia 48 (Supplement 2), 2007.
81. “Quallion medical batteries”,
http://www.enersys.com/WorkArea/DownloadAsset.aspx?id=25769803876.
82. Adhikari, A et al., “Cross-correlation of instantaneous amplitudes of field potential oscillations:
A straightforward method to estimate the directionality and lag between brain areas”, Journal
of Neuroscience Methods, Volume 191, Issue 2, 2010.
83. Haddad, T et al., “Temporal Epilepsy Seizures monitoring and prediction using Cross-
Correlation and Chaos Theory”, Healthcare Technology Letters. Vol. 1. 45-50, 2014.
84. Quintero-Rincon, Antonio et al., “Spike-and-Wave detection in epileptic signals using cross-
correlation and decision trees” Revista Argentina de Bioingeniería. 22. 3-6, 2018.
85. “Texas Instruments - Introduction to Filters”, http://www.ti.com/lit/an/snoa224a/snoa224a.pdf
86. Y. Chen et al., “Split capacitor DAC mismatch calibration in successive approximation ADC,”
in Proc. IEEE Custom Integrated Circuits Conf., Sep. 13–16, 2009, pp. 279–282.
87. M. Yoshioka et al., “A 10 b 50 MS/s 820 SAR ADC with on-chip digital calibration,” IEEE Trans.
Biomed. Circuits Syst., Vol. 4, no. 6, pp. 410–416, Dec. 2010.
107
88. J. A. McNeill et al., “All-digital background calibration of a successive approximation ADC using
the “Split ADC” architecture,” IEEE TCAS. I, Vol. 58, no. 10, pp. 2355–2365, Oct. 2011.
89. Colin C. McAndrew, “Layout symmetries: Quantification and Application to Cancel Nonlinear
Process Gradients”, IEEE Trans. on CAD of ICs and Systems, Vol. 36, No.1, Jan. 2017.
90. M. Shinagawa et al., “Jitter analysis of high-speed sampling systems”, IEEE JSSC, Vol. 25, pp
220-224, Feb. 1990.
91. “National Instruments - Using Fast Fourier Transforms and Power Spectra in LabVIEW”,
http://www.ni.com/white-paper/4541/en/
92. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia
of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
93. “Analog Devices - Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR”,
https://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf
94. “Maxim Integrated - Data Conversion Calculator”, https://www.maximintegrated.com/en/
design/tools/calculators/product-design/data-conversion.cfm
95. E. Charbon et al., “Substrate Noise Analysis and Optimization for IC Design, IEEE Circuits and
Devices Magazine. Vol. 18, Issue 2, March 2002.
96. S. Ardalan et al., “An overview of substrate noise reduction techniques”, IEEE ISSCS, March 2004.
97. “Maxim Integrated – INL/DNL measurements for High-Speed ADCs”,
https://www.maximintegrated.com/en/app-notes/index.mvp/id/283
98. “Maxim Integrated – Understanding how ADC errors affects system performance”,
https://www.maximintegrated.com/en/app-notes/index.mvp/id/748
99. “Analog Devices – IMD considerations for ADCs”, https://www.analog.com/media/en/training-
seminars/tutorials/MT-012.pdf
100. Sepke, T. et al., “Noise Analysis for Comparator-Based Circuits.” IEEE Transactions on Circuits
and Systems -1, Regular Papers, pg 541-553, 2009.
101. Kim, J. et al., “Simulation and Analysis of Random Decision Errors in Clocked Comparators”,
IEEE Transactions on Circuits and Systems -1, Regular Papers, Vol.56, No.8, Aug. 2009.
108
102. Jarvin, A et al., “A 12-Bit, 41.67 kSa/s, 32 µW Ratio-Independent Algorithmic ADC”, IEEE
VLSI Circuits Conference, 2006.
103. Wei-Hsin Tseng et al., “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted
Wireless Transmitters”, IEEE JSSC, Vol. 51, No. 10, Oct. 2016.
104. G. Regis et al., “A 3,3V 12bits rail-to-rail ADC SAR for neuronal implant”, IEEE International
NEWCAS Conference, June 2010.
105. Xicai Yue, “Determining the reliable minimum unit capacitance for the DAC capacitor array
of SAR ADCs”, Microelectronics Journal, pg 473-478, June 2013.
106. Mendez, Horacio et al "Comparing SOI and bulk FinFETs: Performance, manufacturing
variability, and cost", Solid State Technology, Vol. 52, No. 10, Nov. 2009.
107. Baedi, Javad et al., "Comparing the Performance of FinFET SoI and FinFET Bulk”, Scinzer
Journal of Eng, Vol. 2, Issue 3, 2016.
108. “GlobalFoundaries enhances 28nm design flow; prepares for double patterning",
https://www.electronicsweekly.com/news/business/finance/globalfoundries-enhances-28nm-
design-flow-prepares-for-double-patterning-2012-06/, 2012.
109. “Seeing double: TSMC adopts new lithography technique to push Moore’s law to 20nm",
https://www.extremetech.com/computing/160509-seeing-double-tsmc-adopts-new-
lithography-technique-to-push-moores-law-to-20nm, 2013.
110. “Samsung Starts Industry’s First Mass Production of System-on-Chip with 10-Nanometer
FinFET Technology”, https://news.samsung.com/global/samsung-starts-industrys-first-mass-
production-of-system-on-chip-with-10-nanometer-finfet-technology, 2016.
111. “TSMC - Scope and Limit of Lithography to the End of Moore’s Law”,
http://www.ispd.cc/slides/2012/ISPD12_Keynote.pdf, 2012.
112. Iessi, Umberto et al., "Double patterning overlay and CD budget for 32 nm technology
node", Proceedings of SPIE - The International Society for Optical Engineering, 2009.
113. Young-Kyun Cho et al., “A 10-bit 30-MS/s successive approximation register analog-to-
digital converter for low-power sub-sampling applications”, Microelectronics Journal, Vol.42,
Issue 12, Dec. 2011.
109
114. Yao-Sheng Hu et al., “A 510 nW 12-bit 200kS/s SAR-Assisted SAR ADC Using a Re-
Switching Technique”, IEEE Symposium on VLSI Circuits 2017.
115. Ming Ding et al., “A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC Utilizing a Redundancy-
Facilitated Background Error-Detection-and-Correction Scheme”, IEEE ISSCC 2015.
116. Aaron Stillmaker et al., "Scaling equations for the accurate prediction of CMOS device
performance from 180 nm to 7 nm", Integration the VLSI journal, Vol.58, 2017.
117. J.M. Rabaey et al., "Digital Integrated Circuits: A Design Perspective", 2nd edition, Pearson
Education, Upper Saddle River, NJ, 2003.
118. “International technology roadmap for semiconductors”, http://www.itrs2.net/, 2015.
119. “International technology roadmap for semiconductors”, http://www.itrs2.net/, 2014.
120. “Predictive Technology Model”, http://ptm.asu.edu/, 2019.
121. Yuan Taur et al., “Fundamentals of modern VLSI devices”, Cambridge Univ. Press, 1998.
122. Pieter Harpe et al., “A 2.2/2.7 fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven
Noise Reduction”, IEEE ISSCC 2013.
110
9 Appendix A – Internal Digital-to-Analog Converter
(C-DAC) design for the SAR ADC
The capacitive Digital-to-Analog (DAC) converter fundamentally converts binary digits or digital bits
into its analog equivalent based on the reference voltage / current. Normally the output voltage is
a linear function of the input number. The specifications define the accuracy of the converter, its
static and dynamic performance. Essentially, a C-DAC will have the reference voltage / current as
the input and an analog voltage equivalent to the digital word as the output. The basic C-DAC will
have voltage / current reference generation block, binary switches, scaling network and an output
amplifier. The scaling network and the binary switches operate on the externally supplied reference
voltage to create the digital word as either a voltage or charge signal and the output amplifier
converts this signal to a voltage signal that can be sampled without affecting the value of the
conversion.
To achieve smaller core implementation-area, an N-bit resolution C-DAC can be divided into
K smaller sub-C-DACs with each sub-C-DAC having a resolution of N/K. Therefore, more resolution
can be achieved because of reduced largest-to-smallest component spread. To achieve this, we
can have the following architectures.
1. Combination of similarly scaled sub-C-DACs
a) Divider approach (scale the analog output of the sub-C-DACs)
b) Sub-ranging approach (scale the reference voltage / charge of the sub-C-DACs)
2. Combination of differently scaled sub-C-DACs.
If an N-bit C-DAC is divided into an M-bit MSB sub-C-DAC and a K-bit LSB sub-C-DAC to form an
M+K=N bit C-DAC, a divider approach would be to divide (or scale) the K-bit LSB C-DAC by 2
M
,
and then add the output of an M-bit sub-C-DAC to the output of the K-bit LSB sub-C-DAC after the
scaling, we get an M+K bit C-DAC. Achieving perfect scaling to the K bit sub-C-DAC is difficult, so
the accuracy of the LSB C-DAC is not as accurate as the MSB C-DAC. In a similar way, the
111
reference voltage scaling is achieved in the sub-ranging approach architecture for the C-DAC only
this time, instead of the output of the LSB C-DAC being scaled by 2
M
; the reference voltage going
into the K-bit LSB sub-C-DAC is scaled by the same value resulting in an N-bit C-DAC. Here, the
accuracy considerations are like that of the divider approach mentioned above.
The charge-scaling C-DAC approach operates by binary division of the total charge applied to the
capacitor array. A two-phase non-overlapping clock is used for this converter. The accuracy of the
capacitor and the physical area required are both factors limiting the number of bits used. The
accuracy is dependent on the capacitor ratios. Also, this approach has the capacitor ratio between
MSB and LSB capacitors to be 2
N
:1, in extreme case, which is undesirable in terms of physical
area occupied.
The total amount of capacitance required for a given size converter can be reduced by using a
capacitor divider approach (split-capacitor C-DAC) as shown in Figure 9-1. In this configuration,
the portion of the array that lies to the left of the attenuating capacitor is called the LSB array, and
the portion to the right is the MSB array. The smallest bit of the MSB array would give a 1/64 scaling
of the reference. The next smaller bit would be the highest bit of the LSB array, which would be
½ of the reference attenuated by 1/64 to give a scaling of 1/128 and so on. It is calculated that the
CA, the attenuating capacitor, will have a value equal to 2*C/63, where C is the capacitance
corresponding to the MSB bit of the array.
The internal C-DAC in the SAR ADC (see Figure 9-1) converts binary inputs (Vlow=0V,
Vhigh=1.8V) from the SAR control block (these binary inputs are also the output of the ADC) into
its analog equivalent based on the reference voltage (Vref). The C-DAC has binary inputs (b1-b12,
b1_bar-b12_bar), Vref, and sample (S2), hold (S1b), conversion (S1) clocks as the inputs to the
block and an analog voltage equivalent to the binary conversion as the output. The comparator
compares the output value of the C-DAC to the reference voltage (see Figure 4-2), generating
logic “0” or logic “1” state depending on whether the output value of C-DAC is higher or lower than
Vref. The SAR control block generates the relevant clocks S1, S1b, S2, and Latch Clock, for ADC
operation. It also contains the successive approximation digital logic for the operation of the ADC.
S2, S1b, S1 are the sample, hold and conversion clocks respectively in the C-DAC. They are
112
generated in the SAR control block. They are derived from the ADC clock, Reset and Start signal.
The Start signal in the ADC goes high initiating the ADC operation. Clock S2 starts transitioning
from logic-low to logic-high at the following positive edge of the ADC clock, to initiate the sample
phase.
GND VREF
C 12 C 11
C A
C 1 C 2
12-bit
Binary-Weighted
Split-Capacitor
Array
VIN
VREF
GND
VREF
GND
V a
S2 S1 S1b S2 S1b S1
LSB DAC MSB DAC
Figure 9-1: Functional schematic of a 12-Bit Digital-to-Analog Converter using the capacitor
divider approach.
This causes the C-DAC output node to have the sampled value of the Vin. One ADC clock cycle
later, S2 transitions to logic-low and S1 transitions to logic-high, starting the conversion phase.
S1 stays high for the succeeding 12 ADC clock cycles during the conversion process. Depending
on the value of bit / bit_bar (logic “high” / logic “low”), the bottom plate of the capacitor is pulled to
Vref (0.9 V) or ground (0 V). The value at the output of the C-DAC is Vin + (Vref or 0V). For the
SAR operation, Output of the C-DAC is {Vin + (a fraction of Vref (either of Vref /2, Vref /4, Vref /8, etc.))}.
The design of such a C-DAC involves in calculating the value of CA, such that the whole array
performs as 12-bit digital-to-analog conversion. For this, the series combination of CA and the
effective capacitance of LSB array must terminate the MSB array equivalent to C/32. Therefore,
1/CA + 1/Cb = 1/(C/32), where Cb=CLSB is the equivalent capacitance of the LSB C-DAC array.
Hence, C/32 = 1/ (1/CA +1/2C), solving this will yield CA = 2C/63. This CA, as we can see, does not
translate to an integer multiple of the unit capacitance. Therefore, 1/CA + 1/Cb = 1/ C/32, where
113
Cb=CLSB is the equivalent capacitance of the LSB C-DAC array. Cb is chosen such that CA as well
as the LSB capacitor array, yield an integer multiple of the unit capacitance.
C
A
C
LSB
C
MSB
V
2
V
1
2C 63C/32
2C/63
Figure 9-2: Equivalent Circuit of Figure 9-1.
The best possible combination was calculated to be CA = C/28 and Cb = C/4, still satisfying the
1/CA + 1/Cb = 1/(C/32). The LSB capacitor array of the C-DAC is calculated based on Cb =C/4
which yields the smallest capacitor (unit-capacitor) in the C-DAC to be Cb/(2
N/2
) = C/256 for 12-bit
implementation, if the C-DAC is split into two (= N/2 = 6) sub-C-DACs. The C-DAC array is designed
such that CA = C/28 and CLSB = C/4. Then V1 and V2 can be expressed as
11
1 1 1 ref 2 ref 3 ref
1 1 1
4 ref 5 ref 6 ref
aa
V a b V ( ) b V ( ) b V
24
a a a
( ) b V ( ) b V ( ) b V
8 16 32
= + + +
++
Equation
(36)
2 7 ref 8 ref 9 ref
10 ref 11 ref 12 ref
1 1 1
V ( ) b V ( ) b V ( ) b V
2 4 8
1 1 1
( ) b V ( ) b V ( ) b V
16 32 64
= + + +
++
Equation
(37)
Where a1 = 32/63;
Therefore,
1 2 3 4 5 6
1 ref
64 b b b b b b
V ( ) [ ] V
63 2 4 8 16 32 64
= + + + + +
Equation (38)
7 8 9 10 11 12
2 ref
b b b b b b
V [ ] V
2 4 8 16 32 64
= + + + + +
Equation (39)
Using superposition on V1 and V2 in Figure 9-2, we have
a 1 2
63 1
V ( ) V ( ) V ;
64 64
=+ Equation (40)
114
Substituting Equation (38) and Equation (39) in Equation (40), we get
3 5 6 7 1 2 4
a ref
8 9 10 11 12
bb b b bbb
2 4 8 16 32 64 128
V V
b b b bb
256 512 1024 2048 4096
+ + + + + +
=
+ + + + +
Equation (41)
Analysis to compute unit capacitance of the C-DAC based on the
input-referred kBT/C noise, capacitor-mismatch and settling-time
requirements
9.1.1 Input-referred k BT/C noise requirements
An important consideration that drives the ENOB metric of the ADC is the total intrinsic
input-referred noise, of which the input-referred kBT/C noise of the C-DAC is a significant
component, where C is the total capacitance of the C-DAC seen at the sampling switch at the input
of the ADC. This consideration places a floor on how low the unit-capacitor value can be and hence
its implementation-area and therefore, the total C-DAC implementation-area. The input-referred
kBT/C noise is given by Equation (42) [105].
1
V
2*2
ref
B
N
kT
C
+
Equation (42)
Where kB is the Boltzmann constant (1.38064852E-23 m
2
kg s
-2
K
-1
), T is absolute temperature
in Kelvin (
o
K), Vref is the reference voltage (0.9 V), and N is the resolution (12-bits) of the ADC.
Solving Equation (42) for C yields a minimum total C-DAC capacitance of 0.35 pF, which translates
to minimum unit-capacitor value of 22.16 fF based on the LSB of the C-DAC-array (divide by 64)
sampling in the binary-weighted split-capacitor C-DAC-array (see pages 102-104 starting with 2
nd
paragraph on page 102).
9.1.2 Capacitor-mismatch requirements
The implementation-area, power-dissipation and settling-time of the C-DAC decrease with the
reduction in the capacitance of the unit-capacitor cell used to implement the C-DAC. These benefits
tradeoff with the resulting increased capacitance-mismatch due to the fundamental dependence of
115
the capacitor-mismatch on the area of the unit-capacitor cell used to implement the C-DAC. The
standard-deviation of the capacitor-mismatch is given by Equation (43), found in the process
specifications manual for the XFAB XH018 180 nm CMOS process, where Ac is the process-related
capacitor-matching parameter with units of %-µm. The value of the process-specific
area-capacitance parameter is specific to the particular capacitor structure (MIM, MOM-types,
etc.,). One determines the capacitor area for a desired capacitor-mismatch, which then determines
the capacitor value.
A
WL
C
C
C
=
Equation (43)
The unit-capacitor value calculated by Equation (43) satisfies both the DNL and the INL
requirements of the C-DAC capacitor array [105]. Based on the process specifications manual for
the XFAB XH018 180 nm CMOS process, the 1-σ standard deviation
C
C
is < 0.1 % for the
Metal-1 through Metal-5 Metal-Oxide-Metal (MOM) capacitors. To achieve 99.7% confidence on
the DNL and the INL of 1 LSB at 12-bits (N), 3-σ standard deviation (= 3*0.1%) for the
capacitor-mismatch is chosen. Therefore, from [104, 105] we have
1
2 *3*0.1%
WL > 6.14 m
2
N
−
=
Equation (44)
Referring to the XFAB XH018 180 nm CMOS process specification manual, the area-capacitance
for the MOM (Metal-1 through Metal-5) capacitor is 1.09 fF/µm
2
, which results in a minimum
unit-capacitor value of 41.13 fF (= (6.14 µm)
2
*1.09 fF/µm
2
) to achieve 12-bit resolution and satisfy
the 3-σ DNL and INL of 1 LSB.
9.1.3 C-DAC Settling-time requirements
The analog-to-digital conversion cycle of a 12-bit resolution 100 kSa/s SAR ADC needs to occur
within 1/100 kHz = 10 µs. This means that the following essential phases for each conversion cycle
need to be completed in 10 µs. They are
a. the purge phase (to zero-out the voltage on the sampling-capacitor in the C-DAC),
116
b. the sample and hold phase (to sample and hold the analog-input on to the C-DAC),
c. 12-bit conversion phase (to evaluate each of the 12-bit determinations), and
d. the End-of-Conversion (EOC) phase (binary data ready).
With twelve (12) clock-cycles for each of the 12-bit determinations, and two (2) clock-cycles each
for the purge, sample, hold and EOC phases, we need at least twenty (20) clock-cycles of the
SAR ADC mode’s 2 MHz internal clock-signal (see Table 3.2) for a conversion cycle of
10 μs (= 100 kSa/s). This translates to a sample-phase duration of 1 μs (= 10 μs*2/20). Therefore,
during the sampling-phase, the sampled-voltage on the C-DAC array must settle within 12-bits
(220 μV of settling-accuracy – see page 35) of the analog-input within a fraction of 1 μs, so that the
settled value of the signal voltage is ready for conversion. Let us now look at the unit-capacitor
sizing of the C-DAC to satisfy the minimum settling-time (< 1 μs) requirements to achieve
12-bit resolution at 100 kSa/s. For the first order transfer function,
ps
ps
C C
a
a(s) where R ( )
(1 S) C C
==
++
Equation (45)
Cp is the parasitic capacitance on node V(b), and Cs is the sampling capacitance. Then, the output
voltage is given by
out i
V (s) = a(s)V (s) Equation (46)
out
ps
i
s
V (s) 1
C C
V (s)
1
(a(s) C )
=
+
+
Equation (47)
The time constant is given by
s
s
ps
C
1 a ( )
C C
=
+
+
Equation (48)
If minimum DC gain is chosen for the N –bit accuracy, then the settling-time
ss
T N(ln 2) =
Therefore,
s
s
ps
T N (ln2)
C
1 a ( )
C C
=
+
+
Equation (49)
Where, )
) C (C
C
* (Cp R
s p
s
+
= here R is the on-resistance of the switch, then
117
s
p
ps
s
s
ps
C
R C
(C C )
T N (ln2)
C
1 a ( )
C C
+
=
+
+
Equation (50)
ps
s
sp
R C C
T N (ln2)
(1 a) C C
=
++
Equation (51)
The sampling capacitance, Cs, should be as larger as possible for the smallest settling-time while
it should be as small as possible to minimize the signal acquisition time. Hence, Cs should be
chosen, such that Ts / TAcquisition < 1. Let us calculate the R of the input-switch, which is modeled as
a transmission gate. The sampling-error Es can be approximated as
s
in in
-T
2 R C
s
E 2 e = Equation (52)
With < 1 µs of settling-time for a 100 kSa/s sampling-rate, yields Es = 10
-7
.
then
s
s
s
1
R C
2
2 F (ln ( ))
E
Equation (53)
With Es = 10
-7
, Fs = 100 kHz, R can be written as
) g g (
1
dsn dsp
+
p ox gsp tp n ox gsn tn
1
R
WW
(( C ( ) (|V | - |V |)) ( C ( ) (V - V ) ))
LL
=
+
Equation (54)
With W/L of NMOS = 10 μm / 0.35 μm,
We get
s
s
s
1
C
2
2 F (ln ( )) R
E
Equation (55)
With R value of 10 KΩ we get Cs < 34.4 pF to reduce the implementation-area of the C-DAC and
facilitate the settling-time < 1 μs. This means that the smallest capacitance (unit-capacitor value)
in the C-DAC need to be less than 34.4 pF/256 < 134.37 fF (see page 113) to satisfy the
settling-time requirements of the C-DAC.
118
The constraints on the C-DAC unit-capacitor value based on the requirements of input-referred
kBT/C noise, capacitor mismatch (based on the capacitor area for a desired capacitor-mismatch)
and settling-time requirements (to achieve 12-bit resolution at 100 kSa/s) are summarized in
Table 9.1. We can see that the upper-bound of the unit-capacitor cell value is set by the
C-DAC-array’s settling-time requirement and the lower-bound is set by the capacitor-mismatch
requirement. The largest available fixed (in width and length) MOM (Metal-1 through Metal-5)
capacitor-cell layout with silicon-correlated model (that forms the basis of the capacitor-mismatch
criteria) in 180 nm XFAB XH018 CMOS process is 52.8 fF. Two of these capacitor-cell layouts are
abutted to create the C-DAC’s unit-capacitor cell value of 105.6 fF (= 2*52.8 fF) as shown in
Figure 5-2 (b), page 48. This choice of the C-DAC unit-capacitor value favors the
capacitor-mismatch constraint and satisfies both the C-DAC settling-time constraint and the kBT/C
noise constraint shown in Table 9.1.
Table 9.1: Summary of the C-DAC Unit-Capacitor value determination.
Requirements
Constraints on the choice of the C-DAC
unit-capacitor value
kBT/C noise > 22.16 fF (minimum)
Capacitor-mismatch > 41.13 fF (minimum)
C-DAC-array settling-time < 134.37 fF (maximum)
Sub-Threshold drain-to-source leakage current in the C-DAC
Due to the finite resolution of the C-DAC in the SAR ADC, there will always be deviation from the
quantized C-DAC output to the input voltage to the C-DAC. This deviation is termed as quantization
error. The maximum quantization error for an ideal ADC is +/- 0.5 LSB. Therefore, the goal is to
keep the quantization error less than +/- 0.5 LSB. During the sample and hold phase, the N-Channel
MOSFET (NMOS) transistor switch’s Sub-Threshold Drain-to-Source Leakage (SDSL) current in
the branch of the Most Significant Bit (MSB) capacitor, in the binary-weighted capacitive array
C-DAC (Figure 4-3) in the SAR ADC is the main cause of the ADC quantization error. This is
because SDSL current removes the charge during the hold phase, that represents the sampled
119
signal voltage resulting in quantization error. Analytical considerations for target quantization-error
(please refer to Appendix A, Section 9.1.1, for the derivations and determination of the analytical
considerations for the quantization-error) less than or equal to +/- 0.2 LSB (constituting for the
design target of 40% of the +/- 0.5 LSB quantization error for an ideal ADC) indicate that the
maximum SDSL current in the switches (switches associated with the C12 capacitor in the 12-bit
binary-weighted split-capacitor array, (see Figure 4-3) is 0.1 nA. The sizing of NMOS-transistor
switches needs to comprehend the impact of the SDSL current on the output of the C-DAC.
Comparing the simulated quantization error at the output of the C-DAC for two distinct cases – with
and without ideal switches, verified that the 16 µA SDSL current of the non-ideal switches resulted
in the three LSB quantization error at the output of the C-DAC. The SDSL current of 16 µA in the
non-ideal switches in the C-DAC exceeded the maximum allowable SDSL current by a factor of
16x10
4
. The SDSL current was reduced from 16 µA to 80 pA by increasing the gate length of the
NMOS-transistor switch to 2 µm from 0.35 µm. The circuit is simplified as shown in Figure 9-3, to
simulate the switch in OFF condition (gate, source and substrate of the NMOS transistor are
connected to circuit ground (0 V)). The drain terminal of the transistor in Figure 9-3 is swept with a
DC voltage source from 0 V to 1.7 V, and the corresponding value of SDSL current was recorded.
Vdrain
Figure 9-3: Functional schematic of an NMOS transistor switch for SDSL current estimation.
Table 9.2 shows the sub-threshold drain to source leakage current through an NMOS transistor by
sweeping the drain voltage (Vdrain) in Figure 9-3. After determining the SDSL current through the
NMOS transistor as shown in Figure 9-3, the whole C-DAC was simulated to compute the SDSL
120
current. Results showed that the worst-case sub-threshold drain-source leakage current in one
C-DAC branch, across Process, Voltage and Temperature (PVT) corners was found to be
0.3146 nA for Wp corner at junction temperature of 80 ºC.
Table 9.2: Sub-threshold drain to source leakage current for the setup shown in Figure 9-3.
Figure 9-4 shows the SDSL current for Tm, Ws and Wp process corners for varying Vdrain shown
in Figure 9-3. Changing the gate-length from 0.35 m to 2 m reduced the SDSL current to 30 pA
for Wp corner at junction temperature of 80 ºC.
Figure 9-4: SDSL current for varying Vdrain shown in Figure 9-3 at junction temperature = 80ºC.
Process
Corner
Drain
Voltage
→
SDSL current (pA) for varying drain voltage (Vdrain) (see Figure 9-3)
0.2 V 0.4 V 0.6 V 0.8 V 1 V 1.2 V 1.4 V 1.6 V
Tm @ 80ºC 2.924 3.73 4.55 5.416 6.32 7.28 8.32 9.41
Ws @ 80ºC 0.706 1.12 1.53 1.948 2.36 2.77 3.197 3.61
Wos @ 80ºC 116.88 145.89 177.8 214.83 257.7 308.24 367.39 436.23
Wp @ 80ºC 90.22 111.5 134.56 161.01 191.305 226.58 267.49 314.6
Wof @ 80ºC 116.88 145.89 177.8 214.83 257.74 308.24 367.3 436.2
Wzf @ 80ºC 0.696 1.10 1.51 1.93 2.34 2.75 3.17 3.58
121
Table 9.3: Error on the C-DAC output for Least Significant Bit transitions.
Bit12 ON
(LSB) (V)
Bit11
ON (V)
Bit10
ON (V)
Bit9
ON (V)
Bit8 ON
(V)
Bit7
ON (V)
Bit6 ON
(V)
Bit5 ON
(V)
Tm @ 80ºC 1.000385 1.00077 1.00154 1.00308 1.006163 1.01232 1.024952 1.049912
Ws @ 80ºC 1.000385 1.00077 1.00154 1.00308 1.006163 1.01232 1.024958 1.04992
Wos @ 80ºC 1.000386 1.00077 1.00154 1.00308 1.006164 1.01232 1.024954 1.04991
Wp @ 80ºC 1.000385 1.00077 1.00154 1.00308 1.006164 1.01232 1.024952 1.049906
Wof @ 80ºC 1.000386 1.00077 1.00154 1.00308 1.006164 1.01232 1.024954 1.04991
Wzf @ 80ºC 1.000385 1.00077 1.00154 1.00308 1.006163 1.01232 1.024954 1.049915
Wzs @ 80ºC 1.000385 1.00077 1.00154 1.00308 1.006163 1.01232 1.024954 1.049915
Difference in
V(a) to Initial
Condition 0.0003852 0.00077 0.00154 0.00308 0.006163 0.01232 0.024952 0.049906
Difference in
microvolts 385.2 770.3 1540.8 3081.7 6163.5 12327.6 24952.4 49905.8
Error to the
actual value 5.425E-06 1.1E-05 2.2E-05 4.3E-05 8.65E-05 0.00017 4.76E-05 9.42E-05
Error in
microvolts 5.425 10.95 21.7 43.3 86.5 172.4 47.6 94.2
The complete C-DAC configuration, as shown in Figure 9-1, was simulated to estimate the
sub-threshold drain-source leakage current. During the sample mode in transient analysis, the
maximum sub-threshold leakage current across PVT yielded 16 µA with minimum length (0.35 µm)
for Wp corner at 80ºC. This sub-threshold leakage current was through the transistor to the ground
in the branch of biggest capacitor (MSB) in the C-DAC. This along with SDSL currents in other
branches are tabulated in Tables 9.3 and 9.4 for different process corners (shown in the tables).
The tradeoff in this exercise is the increased drain-to-source ON resistance of the switch due to the
increase in gate length.
Table 9.4: Voltage Error on the C-DAC output for Most Significant Bit transitions.
Bit6 ON
(V)
Bit5 ON
(V)
Bit4 ON
(V)
Bit3 ON
(V)
Bit2 ON
(V)
Bit1 ON
(V) (MSB)
Tm @ 80ºC 1.024952 1.049912 1.099834 1.199698 1.399472 1.7990518
Ws @ 80ºC 1.024958 1.04992 1.099859 1.199711 1.399561 1.7992379
Wos @ 80ºC 1.024954 1.04991 1.099828 1.199681 1.399429 1.7989592
Wp @ 80ºC 1.024952 1.049906 1.099821 1.199665 1.399394 1.7988791
Wof @ 80ºC 1.024954 1.04991 1.099828 1.199681 1.399429 1.7989592
Wzf @ 80ºC 1.024954 1.049915 1.099842 1.199706 1.39951 1.7997307
Wzs @ 80ºC 1.024954 1.049915 1.099842 1.199706 1.39951 1.7991307
Difference in V(a) to
Initial Condition of 1V 0.024952 0.049906 0.099821 0.199665 0.399394 0.7988791
Difference in
microvolts 24952.4 49905.8 99821.2 199665.2 399394.1 798879.1
Error in the actual
value 4.76E-05 9.42E-05 0.000179 0.000335 0.000606 0.0011209
Error in microvolts 47.6 94.2 178.8 334.8 605.9 1120.9
122
This NMOS transistor switch is ON in the sampling phase of the ADC operation. Increasing the
gate length could result in a drain-source voltage drop across the switch. This results in the inability
of the capacitor (connected to the drain of the NMOS switch; to charge up to the sampled value of
Vin (due to a series ON resistance of the switch to the ground) in the sampling phase resulting in a
quantization error. It is a tradeoff in choosing the right gate length of the transistor to minimize
SDSL current and ensuring that the ON resistance (during sampling operation) does not contribute
to increased quantization error (less than +/- 0.5 LSB) in the sampling phase. For L= 2 m across
PVT, the error in the output of the C-DAC reduced to 52 V for an initial condition of 0.9 V on the
output of the C-DAC, corresponding to 0.25 LSB in the quantization error.
123
10 Appendix B – Shared Comparator design for the
SAR-A ADC
Architecture of the comparator
A comparator is a circuit that has a binary output (Logic Vlow (0 V) or Vhigh (1.8 V). Figure 10-1
shows the ideal transfer characteristic of the comparator. The output of comparator is high
(Vhigh = 1.8 V) when Vin+ - Vin- > 0 and low (Vlow = 0 V) when Vin+ - Vin-< 0. This means that the gain
Av= (Vout+ -Vout-) / (Vin+ - Vin-) is infinite as output transitions from Vlow to Vhigh for (Vin+ - Vin-) = 0.
Figure 10-2 shows the transfer characteristic of comparator with a finite gain. Higher the gain of
the comparator, smaller the value of (Vin+ - Vin-) required for the output to transition from Vlow to
Vhigh.
V
in+
- V
in-
V
out+
- V
out-
V
High
V
Low
Figure 10-1: Ideal transfer characteristic of a comparator.
V
in+
- V
in-
V
out+
- V
out-
V
High
V
Low
Figure 10-2: Transfer characteristic of a comparator with finite gain.
124
There are different types of comparators, such as an open-loop Operational Amplifier (Opamp),
multi-stage op-amp as a comparator, positive-feedback using track and latch comparators,
including the differential comparators. The choice of a comparator architecture is dependent on the
speed of the application. Principles, like charge-injection and input-referred offset voltage
cancellation, must be considered in design of comparators. The simplest approach for realizing a
comparator is to use an Opamp in an open loop configuration. The main drawback of this approach
is the slow response time and larger settling-time. This kind of Opamp has a resolution limited to
the input-offset voltage of the Opamp. One way of eliminating the input offset voltage is having a
capacitor in series with the input, such that the offset can be stored in the capacitor during the reset
phase and can be cancelled during the comparison phase. The primary limitation of this approach
is that the op-amps require compensation during the reset phase because of the non-ideality of
nature of a realizable op-amp to ensure stability.
The major limitation on the resolution of the comparator is due to the charge injection errors also
called a clock feed-through. This error is due to the unwanted charge being injected into the circuit
when the transistors turn off due to switching. NMOS/PMOS transistors or transmission gates are
used to realize the switches. When MOS switches are on, they operate in the triode region and
have zero volts between their drain and source. When MOS switches turn off, charge errors occur
by two mechanisms. The first is due to the channel charge, which must flow out from the channel
region of the transistor to the drain and source junctions. The second charge is due to the overlap
capacitance between the gate and the junctions. The simplest way to reduce these errors is to use
large capacitors, but large capacitors greater than 5 pF require a large amount of silicon area.
Furthermore, integrated capacitors have parasitic capacitance between the bottom plate and the
substrate that might be of the order comparable to the original capacitance. An alternative approach
to minimizing the charge injection errors is to use fully differential design. A third approach that can
be used along with differential design is to realize multi-stage comparators, where the clock feed-
through of the first stage is stored on the coupling capacitor between the first and second stage
and so on. This approach can be used to realize high-resolution comparators; however, this
125
approach does have the limitation that requires multiple-phase clock waveforms that slow down
the circuits and, also, the need for the signal to propagate through all the stages.
High-speed comparators typically have one or more gain stages also called pre-amplifiers followed
by a track and latch stage. Figure 10-3 shows the block diagram of the comparator implemented.
It consists of a pre-amplifier, latch stage and inverters. The rationale behind this architecture is as
follows: the preamplifier is used to obtain higher resolution and to minimize the effects of charge
transfer into or out of the inputs when the track and latch goes from track mode to latch mode. The
output of the preamplifier is still smaller than the voltage levels needed to drive the digital circuitry.
The track and latch circuit amplify this signal further during the track phase and then amplify it again
during the latch phase when positive feedback is enabled. The positive feedback regenerates the
analog signal into a full-scale digital signal. The track and latch stage minimize the total number of
gain stages required, even when a high-resolution is needed; and thus, is faster than the
multi-stage approach.
V
IN1
V
IN2
V
out1
V
out2
Pre-Amplifier Latch Inverters
Figure 10-3: Block diagram of the comparator.
The transistor level circuit of the comparator block in the SAR ADC (see Figure 4-2) is shown in
Figure 10-4. The operation of the comparator is as follows: During the preset phase, Vlatch is low,
ensuring the nodes “out1” and “out2” are forced to Vdd= 1.8 V by PMOS transistors Xlp1 and Xlp2.
NMOS transistors Xln1 and Xln2 are OFF (gate voltage Vlatch is low), isolating the input pair
transistors and the output node in the preset phase. When Vlatch goes high, the comparator enters
the track and latch phase, where a comparison operation is initiated between the inputs “in1” and
“Vref”. If the voltage value of “in1 – Vref” is positive, then the output voltage “out1” is pulled down
126
from Vdd more strongly than the output voltage “out2”. Likewise, if the voltage value of “in1 - Vref”
is negative, then the output voltage “out2” is pulled down from Vdd more strongly than the output
voltage “out1”. When “out1” or “out2” are low enough, such that the PMOS transistor’s (X3 or X4)
source-gate voltage VSG > |Vth| (the threshold voltage of the PMOS transistor), the transistors X3
or X4 starts to conduct, triggering a positive feedback, latching the output of the comparator. The
output inverters (A1 and A2) restore the comparator outputs to digital logic levels (Vlow= 0 V,
Vhigh=1.8 V). The bias-current of this circuit (current flowing through Xtail1) is important parameter
for the design of this comparator. The speed (how fast the output of the comparator transitions from
one logic state to another for a given load at the output) and power consumption of the comparator
are determined by this bias-current. The tradeoff is between choosing a smaller current for lower
power consumption and moderate settling-time; and larger current to minimize the settling-time at
the cost of increase in power consumption.
V latch_Clk
I
1
Vdd
V out1 V out2
V REF
XIN1 XIN2
X3
X4
X1 X2
Xtail1
V IN
V latch_Clk
V latch_Clk
XL3
XL4
XL1 XL2
Xtail0
a
Figure 10-4: Full schematic circuit diagram of a clocked-comparator.
127
10.1.1 Comparator Design Methodology
The two principal factors that determine the deviation from the inherent quantization error
(+/- 0.5 LSB for the ideal ADC) of the SAR-A ADC are: the internal C-DAC’s finite resolution, and
the ability of the comparator to resolve within +/- 0.5 LSB of the reference voltage, within each
conversion cycle. Ideally, a comparator has finite gain resulting in zero decision errors. This is
because the comparator output yields a logic high when the comparator’s input voltage is greater
than the reference voltage and yields a logic low when the comparator’s input voltage is smaller
than the reference voltage. Practically, a comparator has finite gain resulting in decision errors
when the comparator’s input-voltage is on the either side of the reference voltage. Furthermore, to
facilitate correct bit decisions in each comparison phase, the input to the comparator must have
sufficient amplitude (greater +/- 1 LSB from the reference voltage) to overcome deterministic errors
such as offset, hysteresis, as well as random errors due to device flicker and thermal noise, and
timing-jitter in the comparator’s decision [100, 101]. These errors in decision making contribute to
the deviation from the inherent quantization error in the ADC result. The main causes for the
deviation from the inherent quantization error originating from the comparator circuit
(see Figure 4-3) are:
a. The inability of the comparator design to resolve input level within +/- 0.5 LSB (constituting
for the inherent quantization error of an ideal ADC) of Vref (0.9 V) input.
b. The inability of the tail-current-source transistor of the comparator (see Figure 4-3) to
provide a constant current during the non-linear transient operation of the comparator.
The comparator design approach and analysis to overcome the above causes of the quantization
error is detailed in Appendix B, from page 123. To identify the specific design parameters to
achieve the target specifications, the following steps were followed in the design approach of the
comparator.
Step 1: Transistor small-signal analysis
The transistor small-signal analysis equations were derived for:
a. The cross-coupled inverter pair (Figure 10-5),
b. The cross-coupled inverter pair with input transistors (Figure 10-6),
128
c. The latch-based comparator circuit used in this work (Figure 10-7).
This was to understand how a transistor’s transconductance (gm) and On-Resistance (ro)
influence the small-signal voltage gain (Av) of the comparator. Circuits A and B were first
analyzed to obtain an understanding of the small-signal characteristics. Sizing the
transistors in the comparator circuit was based on the small-signal voltage gain
(Equation (80)) for the latch-based comparator circuit in item C, to maximize the
small-signal voltage gain. With reference to comparator circuit in Figure 10-4, Equation
(80) showing that, increasing the gm of the input transistor Xin1 and matching the gm of
transistors X1 and X3 increase the small-signal voltage gain of the circuit Av. Matching
the gm * ro product of transistors X1 and X3 also increases Av. The same conclusions can
be derived from Equation (67). This showed that the positive feedback (transistors X3,
X5 for circuit B; X1, X3 for circuit C) in both the analysis (Equation (67) and Equation
(80)) plays a dominant role in the determining the gain of the circuit.
Step 2: Impedance calculation looking up from the drain of the tail current source transistor (Xtail1
shown in Figure 10-4) in the comparator
The tail current source transistor (Xtail1 shown in Figure 10-4 of the comparator) should
be able to provide a constant current of 6 A (based on the slew-rate specification of 0.18
V/ns). Using small-signal analysis, the impedance of the circuit looking up from the drain
of the tail current transistor (Xtail1) was derived. Through DC simulations, the value of this
impedance was calculated to be 570 kΩ. This impedance was 30 times larger than the
small-signal drain-to-source resistance (18 kΩ) of the tail current source transistor. With
this high-impedance looking up from node “a”, the node voltage at “a” is forced to ground
(0 V). In order for transistor Xtail1 in Figure 10-4 to function as a tail current-source, its
small-signal drain-to-source impedance has to be much higher (by a factor of 10) than the
impedance looking into the circuit connected to its drain. Sizing the transistors based on
Equation (85) for minimizing the impedance looking up from node “a”, reduced the
impedance to 210 kΩ. The voltage at node “a” with this impedance of 210 kΩ was found
to be 0.33 V. This node voltage at “a” is enough to ensure the tail current source transistor
129
is in saturation (Vds > Vgs – Vth =>0.33 V > 0.7 V-0.6 V) and provide a constant current of
6 A to the comparator circuit to satisfy the slew-rate requirement of 0.18 V/ns.
Step 3: DC simulations
DC simulations were performed to determine the transfer characteristics of the comparator
circuit shown in Figure 4-3 across Process, Voltage, and Temperature (PVT). The first
derivative of this plot is the voltage gain of the circuit. For the Worst-Case power (Wp)
process corner at junction temperature of 80ºC, DC simulations verified that the worst-case
DC gain of the comparator is within 10 % (DC gain of 182) of the analytical DC gain value
of 201 from the small-signal voltage gain equation derived in Step 1 for the latch-based
comparator (using values of gm and ro for each transistor in the Equation (80) obtained
from Hspice DC simulations). The voltage gain plots (through DC simulation and Av
computation based on the Equation (80)) are shown in Figure 10-9, Figure 10-10.
Step 4: Transient analysis
Transient simulations of the comparator were performed to validate the comparator
design to resolve the input level within +/-0.5 LSB of the Voltage Reference (Vref) of 0.9 V.
The transient simulations were also performed to check if the rise times and fall times of
the comparator output met the slew-rate requirement of 0.18 V/ns. For Vref of 0.9 V,
transient simulations showed that the design could resolve the input level within
+/- 200 µV of Vref, thus enabling the comparator to resolve input level within +/- 0.5 LSB
of Vref.
10.1.2 Small Signal Analysis of the Comparator
This section details the transistor small-signal analysis derivations for,
A. The cross-coupled inverter pair circuit.
B. The cross-coupled inverter pair circuit with input transistors and
C. Latch-based comparator circuit used in this work.
130
This step-by-step approach was to understand how a transistor’s transconductance (gm) and
small-signal drain-to-source resistance (ro) influence the small-signal voltage gain (Av) of the
comparator circuit (Figure 10-4) discussed in item C.
A. Cross Coupled Inverter Pair
The cross-coupled inverter pair circuit shown in Figure 10-5(a) was analyzed for small-signal
operation. The operation of this circuit is based on the principle of regeneration (positive feedback).
Figure 10-5(b) shows the small-signal equivalent representation for the circuit shown in Figure 10-5 (a).
V
b
R
C
L
g
mx1
*V
a
g
mx3
*V
a
R
C
L
g
mx2
*V
a
g
mx4
*V
a
(b)
V
a
X4 X3
X1 X2
S1
(a)
Figure 10-5: Cross-Couple inverter pair (a) Transistor-level representation (b) Transistor small-
signal equivalent representation.
For the half-circuit on the left in Figure 10-5(b), we have:
a a b mx1 mx3
L ox1 ox3 L
dV V V (g g )
0
dt (C (r r ) C
+
+ + =
+
Equation
(56)
b b a mx1 mx3
L ox1 ox3 L
dV V V (g g )
0
dt (C (r r ) C
+
+ + =
+
Equation
(57)
Where vout1 = Va and vout2 = Vb,
CL is the parasitic capacitance on the nodes a, b
gmx1 is the transconductance of the NMOS transistor X1,
gmx3 is the transconductance of the PMOS transistor X3,
rox1 and rox3 are the ON resistance of the NMOS and PMOS transistors respectively.
131
Subtracting Equation (56) from Equation (57)
a b a b
mx1 mx3
L ox1 ox3
d (V -V ) - (V - V ) 1
- (g g ) 0
dt C (r r )
= + =
+
Equation (58)
if ) g (g
) r (r
1
mx3 mx1
ox3 ox1
+
+
then (Va-Vb) over time will be
L mx1 mx3
ab
(t/ C / (g g ))
(V - V )(t) V(0) e
+
= Equation (59)
Equation (59) shows that the time constant of CL/ (gmx1 + gmx3) determines how fast the outputs
Vout1 and Vout2, can transition to the logic levels of Vlow and Vhigh.
B. Cross Coupled Inverter Pair with Input Transistors
A cross-coupled inverter pair with input transistors and a tail current source transistor
(Figure 10-6 (a)) is analyzed for small-signal operation. The operation of this circuit is also based on the
regeneration (positive feedback) provided by transistors X3, X5 and X4, X6. Depending on the polarity
of the value of (Vin – Vref), the output voltages Vout1 and Vout2 settle to opposite rails (Vdd or Gnd) due to
the regeneration mechanism. Transistors X1 and X2 provide the inputs for comparison in the form of
current. X7 is the tail current source transistor providing a constant current to the circuit. Figure 10-6 (b)
shows the small-signal half-circuit equivalent representation of Figure 10-6 (a). Transistors X1, X3 and
X5 form the half circuit with transistor X1’s source node considered as AC ground.
R ox1
g mx5*V out2
g mx3*V out2
(b)
g mx1*V in R ox5
R ox3
V out1
X4 X3
X1 X2
(a)
V out2
V IN V REF
X5 X6
V b
Figure 10-6: Cross-Coupled inverter pair with input transistors (a) Transistor-level
representation (b) Transistor small-signal half-circuit equivalent representation.
132
Applying Kirchhoff’s current law in Figure 10-6 (b), we have
mx1 in mx5 out2 mx3 out2
g V g V g V 0 + + =
Equation (60)
The node voltage Vout1 is given by
mx3 out2 ox3 out1 mx1 in mx5 out2 ox1 ox5
g V r V (g V g V ) (r || r ) = = +
Equation (61)
mx1 in mx5 out1
ox1 ox5 out1
mx3 ox3
(g V ) (g V )
( ) (r || r ) V
(g r )
+
=
Equation (62)
Let rox1 || rox5 = rp
p mx5
out1 mx1 in p
mx3 ox3
(r g )
V (1 - ) g V r
(g r )
=
Equation (63)
mx1 mx3 ox3 p
out1
in1 mx3 ox3 mx5 p
(g g r r )
V
V (g r - g r )
=
Equation (64)
Also
mx1 ox1 in out2 mx3 ox3 mx5 p
g r V V [(g r ) - (g r )] = Equation (65)
out2 mx1 1
in1 mx3 ox3 mx5 p
V g
V [(g r ) - (g r )]
ox
r
=
Equation (66)
From Equation (64) and Equation (66) we have, A
V
V - V
v
in1
out1 out2
= is given by
mx1 ox1 mx3 ox3 p
v
mx3 ox3 mx5 p
[g (r - g r r )]
A ,
[(g r ) - (g r )]
=
Equation (67)
Where rp = rox1 || rox5
Equation (66) shows that increasing the gm of the input transistor X1 and matching the “gm ro”
product of transistors X3 and X5 increase the small-signal voltage gain of the circuit Av. This means
133
that the positive feedback (transistors X3, X5) plays a dominant role in the determining the gain of
the circuit.
C. Latch-based Comparator small-signal analysis:
The small-signal analysis of the latch-based comparator is described in this section. Figure 10-7
shows the circuit, as well as the transistor small-signal half-circuit equivalent. The transistors X1,
Xin1, Xln1 and X3 comprise the half-circuit. Applying Kirchhoff’s voltage and current law
in Figure 10-7 (b), The voltage on node “out1” is given by:
out1 mx3 ut2 0x3
V g Vo r =
Equation (68)
The branch current through Roin1 is given by:
out1 x
min1 mbin1 in1
oin1
(V - V )
(g g ) V
R
=+ Equation (69)
Also, node
x mx1 ox1 out2
V g r V = Equation (70)
out1 mx1 ox1 out2 min1 in1 oin1
V - g r V g V R = Equation (71)
mx1 ox1 out1
out1 min1 in1 oin1
mx3 ox3
(g r V )
V - g V R
(g r )
= Equation (72)
out1 mx3 ox3 mx1 0x1 min1 in1 oin1 mx3 ox3
V (g r - g r ) g V R g r = Equation (73)
out1 min1 oin1 mx3 ox3
in1 mx3 ox3 mx1 ox1
V g R g r
-
V (g r g r )
= Equation (74)
Also,
mx3 out2 min1 in1 mx1 out2
g V g V g V =+ Equation (75)
out2 mx3 mx1 min1 in1
V (g - g ) g V = Equation (76)
) g - (g
g
V
V
mx1 mx3
min1
in1
out2
= Equation (77)
Therefore, from Equation (74) and Equation (77), we have:
A
V
) V - (V
v
in1
out1 out2
= =
min1 min1 oin1 mx3 ox3
mx3 mx1 mx3 ox3 mx1 ox1
g g R g r
{ } - { }
(g - g ) (g r - g r )
Equation (78)
134
v mx3 mx1 mx3 ox3 mx1 ox1
(Denominator of A ) (g - g ) (g r - g r ) = Equation (79)
V latch_Clk
I
1
Vdd
V out1 V out2
V REF
XIN1 XIN2
X3
X4
X1 X2
Xtail1
V IN1
V latch_Clk
V latch_Clk
XL3
XL4
XL1 XL2
Xtail0
(a)
R ox1
g min1*V in1
(b)
g mx1*V out2
R oin1
V in1
-g min3*V out2 R ox3
Figure 10-7: Latch-based clocked-comparator (a) Transistor-level (b) small-signal half-
circuit equivalent representation.
Av = (Numerator of Av) / (Denominator of Av)
min1 mx3 ox3 mx1 ox1 ox1 ox3 mx3 mx3 mx1
v
mx3 mx1 mx3 ox3 mx1 ox1
g [g r g r - (r r g ) (g -g )]
A
(g - g ) (g r - g r )
+
= Equation (80)
Analyzing Equation (80), we see that by increasing the gm of the input transistor and matching the
gm of transistors X1 and X3, the small signal voltage gain of the circuit Av increases. Also, matching
the gm * ro product for transistors X1 and X3 increases Av. The same conclusions can be derived
v min1 mx3 ox3 mx1 ox1 ox1 ox3 mx3 mx3 mx1
(Numerator of A ) g [g r g r - (r r g ) (g -g )] =+
135
from Equation (67) as well. This shows that the positive feedback in both the analysis (Equation
(67) and Equation (80)) plays a dominant role in the determining the gain of the circuit.
10.1.3 DC Simulations of the comparator
The DC transfer characteristic of the latch-based comparator circuit shown in Figure 10-4 was
simulated across Process Voltage and Temperature (PVT) using XFAB XH035 CMOS models is
shown in Figure 10-8. Each of the panels (1, 2, and 3) in Figure 10-8 plots the differential output
voltage (Vout_diff) as a function of differential input voltage (Vin_diff) for the tm, ws and wp process
corners, respectively, at junction temperature of 80ºC. These three process corners bracket the
worst case (very slow devices (ws), very fast devices (wp, high-power)) variations in NMOS / PMOS
transistor parameters (threshold voltage, mobility, oxide thickness, etc.). For differential input
Vin_diff < 0, the Vout_diff for each for each process corner is logic Vlow (0 V) and for Vin_diff > 0,
the output switches to logic Vhigh (3.3 V). Panel 1 of Figure 10-9 plots the zoomed in version (around
Vin_diff of 0 V) of the DC transfer characteristic for Wp process corner (panel 3 in Figure 10-8).
This (panel 1 of Figure 10-9) shows the plot of differential output voltage (Vout_diff) as a function
of differential input voltage (Vin_diff). The first derivative of Vout_diff versus Vin_diff (panel1) gives
the gain of comparator. This is shown in panel 2 of Figure 10-9. The value of the DC gain in this
plot is 172 for Wp process corner at junction temperature of 80ºC. The value of the gain
(first derivative of Vout_diff versus Vin_diff) for tm and ws corner was found to be 240 and 400,
respectively. Sizing the transistors of comparator circuit based on the knowledge of Equation (80)
maximized the gain of the circuit to meet the analytical estimate of Av =201 (Figure 10-10)
computed from Equation (80). Figure 10-10 plots the computation of small-signal voltage gain,
using values of gm and ro (for Tm corner, Junction Temperature TJ= 80ºC) for each transistor in the
Equation (80), obtained from spice DC simulations. The worst-case variation in small-signal
voltage gain (Av) between DC simulations and analytical estimate is 19 (a difference of 15%).
136
Figure 10-8: DC transfer characteristics of the latch-based clocked-comparator circuit
shown in Figure 10-4.
Figure 10-9: DC Gain of the latch-based clocked-comparator circuit shown in
Figure 10-4.
137
Figure 10-10: Computation of small-signal gain shown in Equation (80).
10.1.4 Impedance calculation looking up from the drain of the tail current source transistor in the
comparator
In the previous design, the tail current source transistor (Xtail1 shown in Figure 10-4 of the
comparator) was unable to provide a constant current of 6 A (based on the slew-rate specification
of 0.18 V/ns). The voltage at node “a” (drain of the tail current source transistor Xtail1) was forced
to ground (0 V) during the comparator operation. Qualitatively, this meant that the impedance
looking upward of node “a” was much higher compared to the impedance from node “a” to ground
(drain-to-source resistance of the tail current source transistor). Using small-signal analysis, the
impedance of the circuit looking up from the drain of the tail current transistor (Xtail1) was derived
( Equation (99)). Using DC simulations, the value of this impedance was calculated to be 570 kΩ.
This impedance looking up from the drain of the tail current source transistor was 30 times larger
than the small-signal drain-to-source resistance (18 kΩ) of the tail current source transistor. In order
for transistor Xtail1 in Figure 10-4 to function as a tail current-source, its small-signal
drain-to-source impedance has to be much higher (by a factor of 10) than the impedance looking
into the circuit connected to its drain. In other words, with this high-ratio of impedance from Vdd to
138
node “a” and node “a” to Gnd, the drain voltage of the tail current source transistor (node “a”) was
not being biased to keep the tail current source transistor in saturation (Vds < Vgs – Vth).
Figure 10-11, Figure 10-12, Figure 10-13 show the details of the small-signal representation of
the half-circuit of the comparator block shown in Figure 10-4. Figure 10-11 shows a step-by-step
breakup of the main comparator into its half circuit representation and the definition of impedance
Zin. Zin is the impedance looking up from node “x” (Figure 10-11). Figure 10-12 shows the graphical
derivation of the small-signal circuit for deriving an expression for Zin (given by Vx / Ix) from the
circuit graphically derived in Figure 10-11.
Expression for Z in using the small-signal representation in Figure 10-12 :
Applying Kirchhoff’s voltage and current law in Figure 10-12, we have:
The node voltage
x ox3 x oln1 x mln1 mbln1 x
V r I r (I - (g g ) V ] = + + Equation (81)
x ox3 oln1
x mln1 mbln1 oln1
V (r r )
I (1 (g g ) r )
+
=
++
Equation (82)
If
mln1 mbln1 oln1
(g g ) r 1 + Equation (83)
Then
x ox3 oln1
x mln1 mbln1 oln1
V (r r )
I ((g g ) r )
+
=
+
Equation (84)
Therefore,
x ox3 oln1
in
x oln1 mln1 mbln1
V (r r )
Z
I (r (g g ))
+
==
+
Equation (85)
Using the value of Zin obtained from Equation (85), the expression for the impedance looking up
from node “a” is derived. Figure 10-13 shows the graphical derivation of the small-signal circuit for
deriving the expression for the small-signal (ac) impedance, looking up from the drain of the tail
current source transistor.
Calculation of impedance looking up from node “a” in Figure 10-13 using Zin obtained:
Applying Kirchhoff’s current and voltage law in Figure 10-13, we have:
The node voltage
x y in
V I Z ; =
139
min1 mbin1 in1 oin1 x xx
(g g ) V r V - V += Equation (86)
mx1 out2 ox1 xx y
g V r V - V = Equation (87)
mx1 out2 ox1 x min1 mbin1 1 oin1 y
-g V r V - (g g ) V r V + + = Equation (88)
Since
out2 y
V - V = ,
y y in mx1 out2 ox1 min1 mbin1 1 oin1
V I Z - g V r - (g g ) V r =+ Equation (89)
y mx1 ox1 y in min1 mbin1 1 oin1
V (1 -g r ) I Z - (g g ) V r =+ Equation (90)
x y mx1 out2 ox1 min1 1 oin1
V - V g V r g V r =+ Equation (91)
y mx1 ox1 y in min1 1 oin1
V (1-g r ) I Z - g V r = Equation (92)
Also
y
m(x1) out2 m(in1) 1 1 m(x1)
m(in1)
V
g V - g V V g
g
= = = Equation (93)
( ) ( )
( ) ( ) ( )
( )
m in1 m x1 o in1
y y in m x1 o x1
m in1
g g r
V (1 - g r ) I Z
g
+= Equation (94)
( )
( ) ( ) ( ) ( ) ( )
in m in1 y
y m in1 m x1 m in1 o x1 o in1
(Z g )
V
I (g - g g (r - r ))
= Equation (95)
Substituting Zin from Equation (85), we have:
Numerator of
( ) ( ) ( )
y
o x3 o ln1 m in1
y
V
(r r ) g
I
=+ Equation (96)
Denominator of
( ) ( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ( )
m ln1 mb ln1 o ln1 m in1 mb in1
y m x1 m in1 mb in1 o x1 o in1
(g g ) r {(g g )
V
- g (g g )(r - r )} I
++
=
+
Equation (97)
( ) ( ) ( )
( ) ( ) ( ) ( ) ( ) ( )
o x3 o ln1 m in1 y
y m ln1 o ln1 m in1 m x1 o x1 o in1
(r r ) g
V
I g r g (1- g (r - r ))
+
= Equation (98)
Z =
( ) ( )
( ) ( ) ( ) ( ) ( )
o x3 o ln1 y
y m ln1 o ln1 m x1 o x1 o in1
(r r )
V
I [(g r ) (1 - g (r - r ))]
+
= Equation (99)
140
V latch_Clk
I 1
Vdd
V out1 V out2
V REF
XIN1 XIN2
X3 X4
X1 X2
Xtail1
V IN1
V latch_Clk
V latch_Clk
XL3 XL4
XL1 XL2
Xtail0
XIN1
X3
V IN1
XL1
V out1
V out2
V latch_Clk
V out2
V b
V b
a
a
XIN1
V out2
V b
a
V IN1
Zin
Vdd
Vdd
Figure 10-11: Comparator half-circuit representation for impedance calculation.
XIN1
V out2
V b
a
V IN1
Zin
Vdd
R oin1 g mbin1*V x g min1*V 1 R ox5
V 1
V x
I x
Zin = V x/I x
Figure 10-12: Circuit to small-signal representation for deriving an expression for Zin.
Computing the value of Vy / Iy obtained in Equation (99) gives the impedance looking up from the
drain of the tail current source transistor. Sizing the transistors in the comparator for minimizing the
impedance looking up from node “a”, reduced the impedance looking up from the drain of the tail
current source transistor to 210 kΩ. Figure 10-14 plots this impedance looking up from the node
“a”, and that of node “a” of the modified design of the comparator. The voltage at node “a” with this
141
impedance of 210 kΩ was found to be 0.33 V. This node voltage at “a” is enough to ensure the tail
current source transistor is in saturation (Vds > Vgs – Vth => 0.33 V > 0.7 V-0.6 V) and provide a
constant current of 6 A to the comparator circuit to satisfy the slew-rate requirement of 0.18 V/ns.
R ox1
g min1*V in1
g mx1*V out2
R oin1
V in1
Zin
V out2
V y
I y
V x/I x = Impedance looking up from node “a”.
Figure 10-13: Circuit to small-signal representation for deriving an expression for the
impedance looking up from node “a” shown in Figure 10-4.
Figure 10-14: Impedance looking up from node “a” of the comparator shown in Figure 10-4.
142
11 Appendix C – Effects of mismatch, input-referred
DC-offset and 1/f noise contributions
Two devices (MOSFETs, resistors, capacitors) of the same size, laid out next to each other, are
not identical after fabrication. The difference between two identical devices is a function of random
offsets during processing. These offsets vary from chip to chip and set a limit on precision attained.
This is typically reflected as data sheet specifications for a given process. Mismatch is classified
into two categories:
A. Systematic mismatch;
B. Random mismatch.
Systematic mismatch is design and layout dependent. Systematic mismatch can be reduced by
employing proper layout techniques, such as common-centroid, inter-digitization, etc. These can
be observed by performing DC operating point simulations in a spice simulator. Random mismatch
in the circuits are due to inevitable manufacturing variations that occur during wafer processing.
Source of random mismatch include: edge effects, implantation, doping, annealing, mobility and
oxide effects. These can be evaluated for a given circuit using Monte-Carlo simulations [6].
The profile of a random mismatch has a Gaussian distribution and can be quantified by statistical
variables of:
– mean
– Standard deviation σ
– Variance: σ
2
Let us consider MOSFET-related random mismatch parameters. Ideally, it has been shown that
the difference in threshold voltages between two identically sized MOSFETs behave as [14]:
WL
A
Vt
V
t
=
Equation (100)
AVt in Equation (100) is a parametric value that can be obtained from the process specifications
document, for a given technology from a given fabrication house. W and L are the width and length
of the identically sized transistors. For a current factor (β) mismatch, we have
143
( )
WL
A
=
Equation (101)
Here, the parametric value of Aβ can also be obtained from the process specifications documents for a
given technology from a given fabrication house. For the calculation of the effect of mismatches on
comparator performance, it is convenient to model a pair of matched devices with random differences in
the variations. The mismatch can be modeled as a voltage source referred to the input of a circuit
(comparator) also termed standard deviation of the input-referred DC-offset voltage accounting for the
variations summarized above. Figure 11-1 shows the transient simulations of the comparator output
without any mismatch effects modeled (input-referred DC-offset voltage = 0 V) for the process corners
Typical Mean (tm) (panel 3), Worst-case Speed (ws) (panel 4) and Worst-case Power (wp) (panel 5)
operating at 80
o
C simulated used in XFAB XH035 CMOS models. Referring to the cursor placement in
time for Figure 11-1, we can see that V(in1) = 1.6995 V and V(in2) = 1.7 V where the input signal level
is greater than 500 μV of the reference voltage, producing an output (logic “0”) for all the three corners
mentioned above.
Figure 11-1: Transient simulations of the comparator output without mismatch effects for
tm, ws and wp corners at Tj= 80 °C.
144
Figure 11-2 shows the transient simulation plots of the comparator output with mismatch effects
modeled (for example an input-referred DC-offset voltage = 1 mV) for the process corners tm (panel
4), ws (panel 5) and wp (panel 6) operating at 80
o
C. The comparator fails to maintain the precision
(refer to the cursor placement in time for Figure 11-2, where the inputs to the comparator
V(in1) = 1.6995 V and V(in2) = 1.7 V) of resolving input signal level > 500 μV of the reference
voltage. The comparator output for all three process corners (tm, ws and wp) yield an incorrect
output (logic “1”) generating an error in the operation of the comparator. Here, input-referred offset
voltage of 1 mV is chosen to account for a 2 LSB variation.
Figure 11-2: Transient simulations of the comparator output with mismatch effects (modeled as
input-referred offset-voltage = 1 mV) for tm, ws and wp corners at junction temperature Tj = 80°C.
From these simulations, we can clearly see that the input-referred DC-offset referred to the input
of the comparator directly impacts the performance of the ADC by degrading the resolution of the
ADC. It is necessary to address the effects of input-referred DC-offset, mismatch and 1/f noise
contribution and compensate for these effects by implementing a compensation technique on the
ADC architecture.
145
Offset Cancellation Techniques
11.1.1 Overview of the techniques for offset cancellation
This section describes various offset-cancellation techniques that can be employed to compensate
the input-referred offset-voltage for the latch-based comparator. The goal is to identify a technique
that consumes low power, cancels offset, minimizes low-frequency and wideband noise, and has
minimal negative effect on the ADC resolution.
The three offset cancellation techniques are:
1. Auto Zero (AZ) mismatch compensation technique
2. Correlated Double Sampling (CDS) mismatch compensation technique
3. Chopper Stabilization (CHS) mismatch compensation technique.
11.1.2 Auto Zero (AZ) offset cancellation technique
The Auto-Zeroing offset-cancellation technique (referred to as Auto-zeroing for short) is a sampling
technique used to sample noise and offset. This sampled offset and noise is stored and subtracted
from the instantaneous value of the signal either at the input or the output of the amplifier. This
technique requires two phases shown in Figure 11-3: a sampling phase during which the offset
voltage Vos and the noise Vn of the amplifier are sampled and stored; and a signal-processing phase
during which the (Vos + Vn) is subtracted from the input signal to achieve an offset free operation.
If noise is constant over time like DC-offset, it will be cancelled by this technique, but if the noise is
varying (in this case low-frequency random noise, such as1/f noise), it will be high-pass filtered.
The cost of this technique is that it increases the noise-floor due to the aliasing of the wideband
noise that is inherent in the process of sampling.
A
2
V
in
Sample &
Hold
S1
A
1
V
os
+ V
N
ϕ
1
V
out
Figure 11-3: Functional block diagram of an Auto-zeroing offset cancellation technique.
146
11.1.3 Correlated Double Sampling (CDS) offset cancellation technique
In Auto-Zeroing technique shown in Figure 11-3, the amplifier is disconnected from the signal path
during the sample phase to Sample and Hold (S/H) the amplifier offset and noise. The Auto-Zeroing
principle is not suitable for continuous time applications where the signal needs to be amplified
continuously. Sampling of the signal must take place within the same clock cycle to facilitate
amplification for continuous time applications. The technique of sampling twice is called Correlated
Double Sampling (CDS) where there are two sampling operations: the first sampling operation is
to sample the amplifier noise and offset (similar to Auto-Zeroing step) followed by a second
operation of sampling the signal and the instantaneous noise of the amplifier. CDS is considered a
special case of Auto-Zeroing and can be described as an Auto-Zeroing operation followed by
sample and hold. The effect of CDS on the amplifier offset and noise is similar to that of the
Auto-Zeroing technique.
11.1.4 Chopper Stabilization (CHS) offset cancellation technique
Auto-Zeroing and CDS are based on sampling technique, while CHS is based on modulation and
demodulation technique. Figure 11-4 shows the principal operation of the CHS technique.
V in V out
V os + V N
m 1(t) m 2(t)
A(f)
V in
fT
1 2 3 4
V out
1 2 3 4
T T
Figure 11-4: Functional block diagram of a CHS offset cancellation technique [123].
Here, the signal is modulated to a higher frequency by m1(t) (shown in Figure 11-4) (frequency
where 1/f noise contribution is insignificant) and then demodulate back (m2(t) also shown in
Figure 11-4) to the baseband after amplification. The input signal is multiplied by a square-wave
signal m1(t) shown in Figure 11-4. This multiplication procedure is called modulation.
After modulation, the signal is amplified by A(f) and then demodulated back (by multiplying the
147
output of amplified signal VA by m2(t)) to the baseband. Ideally, if an amplifier has gain (Av), with
infinite bandwidth, then the signal after modulation and demodulation is a signal AvVin. But the finite
bandwidth of the amplifier introduces frequency components around the modulation frequency,
which must be low-pass filtered to recover the signal. The gain of the amplifier is also sensitive to
the delay. To maintain a maximum DC gain, the phase shift between the input and the output
modulators must match precisely to the phase shift introduced by the amplifier. Since the noise and
offset are modulated only once, they are transposed to the odd harmonics of the output square
wave, leaving the amplifier ideally without any offset and low- frequency noise.
11.1.5 Comparison of the three techniques discussed above
AZ / CDS CHS
Eliminates offset and reduces low-frequency
noise by high-pass filtering
Eliminates both offset and the low-frequency
noise due to modulation- demodulation
Output noise is dominated by the under
sampled wideband noise in AZ. As CDS allows
for an additional sampling, the wideband noise
is already sampled. The fold over component
due to aliasing is less compared to AZ.
The noise spectrum is not folded, and 1/f
remains dominant in the base band before
demodulation. After demodulation the
wideband, noise is folded into the baseband
and replaces the 1/f noise.
Finite bandwidth of the amplifier introduces the
frequency components around the sampling
frequency in both AZ and CDS and must be
low-pass filtered.
Finite bandwidth of the amplifier introduces
frequency components around the chopper
frequency which must be low-pass filtered as
well.
No issue with the phase shift matching as there
is no delay involved.
To maintain a maximum DC gain, the phase
shift between input and output modulators must
match precisely the phase shift introduced by
the amplifier.
There are no gain considerations in these
techniques as there are no subsidiary
amplifiers.
The gain of the chopper amplifier is also
sensitive to the delay introduced by the main
amplifier.
Power consumption is relatively lower
compared to CHS technique
Power consumption is higher as this technique
involves modulation, de-modulation with a
carrier frequency at least 2-3 times higher than
the signal bandwidth.
148
Analytical determination of the input-referred offset-voltage and
validation via HSpice Monte-Carlo simulations
The following sections derive the expression for mismatch in terms of input-referred offset voltages
for the following circuits.
A. A differential amplifier with Resistive load
B. A differential amplifier with PMOS current mirror load
C. A cross-coupled inverter pair
D. A cross-coupled inverter pair with input transistors as common source load
E. A latch-based comparator circuit used in this work
These derivations are followed by numerical calculations for determining the input-referred
offset-voltage. HSpice Monte-Carlo simulations are validated by the input-referred offset calculated
from the analytical derivations of these well-understood circuits.
11.2.1 Input-referred offset-voltage expression for differential amplifier with Resistive load
Vos
Vo1 Vo2
Vdd
R1 R2
M1 M2
2*I
Figure 11-5: Functional Circuit schematic of a differential amplifier with resistive load for deriving
the expression for standard deviation of input-referred offset voltage Vos
The expression for input-referred offset for a differential amplifier with resistive load shown in
Figure 11-5 is derived in this section. Here, the NMOS transistors M1 and M2 are biased to operate
149
in Saturation region with R1 and R2 acting as the load. The small-signal gain of this topology is
V m(M1) 1
A g R ; = Equation (102)
We have the input-referred offset-voltage Vos = Vid (difference in the input voltage), such that
Vo1 – Vo2 = 0;
; V - V V
gs(M2) gs(M1) os
= Equation (103)
The over-drive voltage Vov for a transistor operating in saturation region = Vgs -Vth, then
); V (V V V V
th(M2) ov(M2) th(M1) ov(M1) os
+ + = Equation (104)
= +
d(M1) d(M2)
os thn
n(M1) n(M2)
II
V V - ;
KK
Equation (105)
Where
=
= = =
thn th(M1) th(M2)
d(M1) d(M2) ox (transistor)
ov(M1) ov(M2) n(transistor)
( 1) ( 2) (transistor)
V V - V ;
I I C W
V ; V ; K
L
n
n M n M
KK
Equation (106)
if ΔI is the mismatch in the saturation drain currents between the NMOS transistors M1 and M2,
and if ΔKn is the mismatch in the current factor between the two NMOS transistors, we have
= + = − = + =
nn
d(M1) d(M2) (M1) n (M2) n
KK II
I ; I I ; K K ; K K - ;
2 2 2 2
I
then
+−
= + −
+−
thn
nn
nn
II
I I
22
V
KK
K K
22
os
V
Equation (107)
Simplifying the above equation, we get
= + + − − − +
thn
V 1 1 1 1
4 4 4 4
nn
os
n n n
KK I I I
V
K I K I K
Equation (108)
= + −
thn
2 2
V
44
n
os
nn
K II
V
K I K
Equation (109)
= + −
thn
1
V
2
n
os
nn
K II
V
K I K
Equation (110)
150
Here,
n
K
I
2
1
≡ Gate over-drive voltage
ov
V of the NMOS input transistors;
ΔI/I is due to the mismatch in resistors R1-R2 load, as mismatch of Vtn and Kn are already
accounted for the NMOS input pair transistors.
Let us consider the mismatch in Resistive load of the differential amplifier shown in Figure 11-5.
The output voltage Vo1 = Vo2 = Vdd – (Id R) if R1 = R2 = R; If ΔR is the mismatch between the two
resistors, then Vo1 - Vo2 = Vod = Id ΔR;
Also, if ΔI is the mismatch in the currents of both transistors M1 and M2 then we have:
= + = − = + =
1 2 d(M1) d(M2)
R R ; R R ; I I ; I I - ;
2 2 2 2
R R I I
For Vod = 0, we have
+ + = −
R I R I - ;
2 2 2 2
R I R I
Equation (111)
Simplifying the above expression, we get:
=
IR
IR
Equation (112)
Substituting Equation (112) in Equation (110), we have:
= + −
thn
1
V
2
n
os
nn
K IR
V
K R K
Equation (113)
Also, we have
( 1) ( 1)
( 1)
( 1) ( 1)
2
d M d M
ov M
M m M
II
V
Kg
==
Using the above entity and considering the variance of ΔVthn, ΔR, ΔKn we have the variance of
input-referred offset voltage
os
V as
−
=+
2 2 2 2
( ) ( )
() ()
( 1)
os thn n
n
V V R K
mM
R K
I
g
Equation (114)
151
11.2.1.1 Hand calculations and Hspice simulation setup to validate the derivations and
hand calculations
Table 11.1 shows the design parameters for the circuit shown in Figure 11-5. With these design
parameters, hand calculations of the standard deviation (3-sigma) of the input-referred offset voltage
from Equation (100), Equation (101) and Equation (114) yield 8.35 mV.
Table 11.1: Design parameters for the circuit shown in Figure 11-5.
Transconductance gm(M1) = gm(M2) 125 μS
Saturation over drive voltage Vov(M1) 120 mV
Current I 10 μA
W/L of M1 2 μm /0.18 μm.
R1 =R2 36K
W/L (R1) 3 μm / 30 μm
Avt 7 mV*μm
Aβ 8.98 mV*μm
Ar 7 mV*μm
.
A simulation test bench was setup to capture the input-referred offset voltage using Monte-Carlo
simulations in Hspice. Appendix A shows the netlist and the schematic representation, to simulate
the input-referred offset voltage for the differential amplifier with the resistive load shown
in Figure 11-5. A differential input voltage sweep was setup in series with a DC input common mode
of 1.65 V for this simulation. Monte-Carlo iteration number in the sweep was varied for each run
(10, 100, 500, 1000, 5000, 10,000) to calculate the input-referred offset voltage of the
differential-pair amplifier with the resistive load for each iteration. The result for one-standard
deviation of input-referred offset for 10,000 iteration Monte-Carlo simulations came to be 8.24 mV.
Table 11.2 displays the standard deviation in the input-referred offset recorded for various
Monte-Carlo iterations. Figure 11-6 plots the Table 11.2 using Microsoft-Excel spreadsheet. The
3-sigma input-referred offset-voltage value of 8.24 mV was obtained from 10,000 iteration runs
validating Hspice Monte-Carlo (MC) simulation methodology using 0.35 μm CMOS XFAB-XH035
foundry model decks specific to MC simulations for calculating the input-referred offset voltage.
152
Table 11.2: 3-sigma standard deviation in the input-referred offset recorded for various Monte-
Carlo iterations for the circuit shown in Figure 11-5.
Mode Process Corner Temperature No of Runs
3-sigma standard
deviation of Input-
referred Offset
(mV)
Hand Calculations Typical Mean 27 1 8.350
Monte Carlo Monte Carlo Gaussian 27 5 4.217
Monte Carlo Monte Carlo Gaussian 27 10 4.260
Monte Carlo Monte Carlo Gaussian 27 100 7.920
Monte Carlo Monte Carlo Gaussian 27 500 8.351
Monte Carlo Monte Carlo Gaussian 27 1000 8.320
Monte Carlo Monte Carlo Gaussian 27 5000 8.280
Monte Carlo Monte Carlo Gaussian 27 10000 8.2406
Figure 11-6: Microsoft-Excel spreadsheet plot capturing the HSpice simulation results for each
iteration run of Monte-Carlo simulations for the differential amplifier with resistive load shown in
Figure 11-5.
11.2.2 Input-referred offset voltage expression for differential amplifier with PMOS current mirror
load
Let us derive the expression for input-referred offset Vos for a differential amplifier with PMOS
current mirror load shown in Figure 11-7. Here, the NMOS transistors M1 and M2 are biased to
operate in Saturation region with PMOS transistors M3 and M5 as the load. Both M3 and M5 are
also operating in Saturation region (Vgate = Vdrain). The small-signal gain of this topology
Av = gm(M2) / (gds(M2) + gds(M4)) Equation (115)
153
We have the input-referred offset voltage Vos = Vid (difference in the input voltage), such that
Vo1 – Vo2 = 0;
; V - V V
gs(M2) gs(M1) os
=
Equation (116)
The over-drive voltage Vov for a transistor operating in saturation region = Vgs -Vth, then
Equation (117)
;
I
-
I
V V
) 2 (
d(M2)
) 1 (
d(M1)
thn os
M n M n
K K
+ = Equation (118)
Where,
thn th(M1) th(M2)
d(M1) d(M2) ox (transistor)
ov(M1) ov(M2) n(transistor)
( 1) ( 2) (transistor)
V V - V ;
I I C W
V ; V ; K
L
n
n M n M
KK
=
= = =
Equation (119)
Vos
Vo
Vdd
M1 M2
2*I
M3 M4
Figure 11-7: Functional circuit schematic of a differential amplifier with PMOS current mirror load
for deriving the expression for standard deviation of input-referred offset voltage Vos
;
2
K
- K K ;
2
K
K K ;
2
I
I I ;
2
I
I I
n
n n(M2)
n
n n(M1) d(M2) d(M1)
=
+ =
− =
+ = We have
); V (V V V V
th(M2) ov(M2) th(M1) ov(M1) os
+ + =
154
+−
= + −
+−
thn
nn
II
I I
22
V
KK
K K
22
os
V
Equation (120)
Following the similar derivation method in obtaining Equation (110), we have the input-referred
offset voltage V os for the input transistor pair shown in Figure 11-7 as:
Equation (121)
Here, ΔI/I is due to the PMOS current mirror load mismatch, as mismatch due to Vtn and Kn are
already accounted for the NMOS input pair transistors. Let us consider the mismatch in the PMOS
current mirror load. Since both the PMOS transistors M3 and M4 have the same gate to source
voltage, therefore Vsg3 = Vsg4; The over-drive voltage Vov for a transistor operating in saturation
region = Vgs -Vth, then
V V V V
th(M4) ov(M4) th(M3) ov(M3)
+ = + Equation (122)
;
I
-
I
V
) 4 (
d(M4)
) 3 (
d(M3)
thp
M p M p
K K
= Equation (123)
Where,
thp th(M4) th(M3)
d(M3) d(M4) ox (transistor)
ov(M3) ov(M4) p(transistor)
( 3) ( 3) (transistor)
V V - V ;
I I C W
V ; V ; K
L
p
p M p M
KK
=
= = =
Equation (124)
= + = − = + =
pp
d(M3) d(M4) p(M3) p p(M4) p
KK
II
I ; I I ; K K ; K K - ;
2 2 2 2
I Equation (125)
+−
= −
+−
thp
pp
pp
II
I I
22
V
KK
K K
22
Equation (126)
= + − − − +
thp
V 1 1 1 1
4 4 4 4
pp
p p p
KK
I I I
K I K I K
Equation (127)
Proceeding in a similar fashion for deriving Equation (110), we get
−
+ =
n
n
n
os
K
K
I
I
K
I
V
2
1
V
thn
155
−
=
p
p
p
K
K
I
I
K
I
2
1
V
thp
Equation (128)
Rearranging the above equation, we get
p
p
ovp
K
K
V I
I
+
=
V
2
thp
Equation (129)
Substituting Equation (129) in Equation (121), and using the following identity
2
dd
ov
m
II
V
Kg
== , we get
−
+ + =
n
n
p
p
mn mp
mn
os
K
K
K
K
g
I
g
g
V
thp thn
V V Equation (130)
Considering the variance of ΔVthn, ΔVthp, ΔKp, ΔKn we have the variance of input-referred offset
voltage as
) (
2
) (
2
) 1 (
) (
2
2
) (
2
) (
2
+
+ =
−
n
n
p
p
thp thn os
K
K
K
K
M m
V
mp
mn
V V
g
I
g
g
Equation (131)
11.2.2.1 Hand calculations and Hspice simulation setup to validate the derivations and hand
calculations
Table 11.3: Design parameters for the circuit shown in Figure 11-7.
Transconductance gm(M1) = gm(M2) 125 μS
Drain-source on resistance gds(M1) 3.28 μS
Transconductance gm(M3) = gm(M4) 41 μS
Drain-source on resistance gds(M3) 2.1 μS
Saturation over drive voltage Vov(M1) 121 mV
Current I 10 μA
W/L of (M1) = (M2) 2 μm /0.18 μm
W/L of (M3) = (M4) 0.9 μm / 0.18 μm
Avt-nmos 7 mVμm
Aβ -nmos 8.98 mVμm
Avt-pmos 8.697 mVμm
Aβ -pmos 10.11 mV*μm
Table 11.3 shows the design parameters for the circuit shown in Figure 11-7. With these design
parameters, hand calculations of the standard deviation (3-sigma) of the input-referred offset
os
V
156
voltage from Equation (100), Equation (101) and Equation (131) yield 13.68 mV. A simulation
test bench was setup to capture the input-referred offset voltage using Monte-Carlo simulations in
Hspice. Appendix B shows the netlist and the schematic representation, to simulate the
input-referred offset voltage for the differential amplifier with the PMOS load shown in Figure 11-7.
A differential input voltage sweep was setup in series with a DC input common mode of 1.65 V for
this simulation. Monte-Carlo iteration number in the sweep was varied for each run (10, 100, 500,
1000, 5000, 10,000) to calculate the input-referred offset voltage of the differential-pair amplifier
with the resistive load for each iteration. The result for one-standard deviation of input-referred
offset for 10,000 iteration Monte-Carlo simulations came to be 13.82 mV. Table 11.4 displays the
standard deviation in the input-referred offset recorded for various Monte-Carlo iterations.
Figure 11-8, plots the data in Table 11.4 using Microsoft-Excel spreadsheet. The 3-sigma
input-referred offset-voltage of 13.82 mV was obtained from 10,000 iteration runs validating Hspice
Monte-Carlo (MC) simulation methodology using 0.35 μm CMOS XFAB-XH035 foundry model
decks specific to MC simulations for calculating the input-referred offset voltage.
Table 11.4: 3-sigma standard deviation in the input-referred offset recorded for various Monte-
Carlo iterations for differential amplifier with PMOS load circuit shown in Figure 11-7.
Mode Process Corner Temperature
No of
Runs
3-sigma standard
deviation of Input-
referred Offset
(mV)
Hand Calculations Typical Mean 27 1 13.68
Monte Carlo Monte Carlo Gaussian 27 5 8.98
Monte Carlo Monte Carlo Gaussian 27 10 9.62
Monte Carlo Monte Carlo Gaussian 27 100 14.234
Monte Carlo Monte Carlo Gaussian 27 500 13.873
Monte Carlo Monte Carlo Gaussian 27 1000 13.9423
Monte Carlo Monte Carlo Gaussian 27 5000 13.896
Monte Carlo Monte Carlo Gaussian 27 10000 13.82
157
Figure 11-8: Microsoft-Excel spreadsheet plot capturing the HSpice simulation results for each
iteration run of Monte-Carlo simulations for the differential amplifier circuit shown in Figure 11-7.
The following sections derive the input-referred offset voltage expressions for
a. The cross-coupled inverter pair circuit
b. The cross-coupled inverter pair circuit with input transistors
c. Latch-based comparator circuit used in this work
This step-by-step approach was taken to understand how the cross-coupled pair influences the
derivations for the input-referred offset voltage expression for the latch-based comparator circuit.
11.2.3 Input-referred offset voltage expression for NMOS-PMOS cross-coupled pair transistors
The cross-coupled inverter pair circuit shown in Figure 11-9 was analyzed for small-signal
operation to derive the expression for the input-referred offset voltage. The operation of this circuit
is based on the principle of regeneration (positive feedback). Figure 11-9(b) shows the small-signal
equivalent representation for the circuit shown in Figure 11-9(a). Applying Kirchhoff’s current law
at Vout1, we have
In + Ip + Ix = 0; where In is the current through X1 and Ip is the current through X3 and Ix is the
output current.
( )
p n x
I I I + − = Equation (132)
158
+
− =
p
p
n
n
x
x
I
I
I
I
I
I
Equation (133)
The above equation implies that the input-referred offset is influenced by the ΔI/I of both the NMOS
and PMOS transistors X1-X3 or X2-X4. Hence Vos = Vosn + Vosp.
V
b
R
C
L
g
mx1
*V
a
g
mx3
*V
a
R
C
L
g
mx2
*V
a
g
mx4
*V
a
(b)
V
a
X4 X3
X1 X2
S1
(a)
Figure 11-9: Cross-Coupled inverter pair (a) Transistor-level representation (b) Transistor small-
signal equivalent representation
We have ; V - V V
gs(X2) gs(X1) osn
= Equation (134)
The over-drive voltage Vov for a transistor operating in saturation region = Vgs -Vth, then
); V (V V V V
th(X2) ov(X2) th(X1) ov(X1) osn
+ + = Equation (135)
= +
d(X1) d(X2)
osn thn
( 1) ( 2)
II
V V -
n X n X
KK
Equation (136)
Where,
thn th(X1) th(X2)
d(X1) d(X2) ox (transistor)
ov(X1) ov(M2) n(transistor)
( 1) ( 2) (transistor)
V V - V ;
I I C W
V ; V ; K
L
n
n X n X
KK
=
= = =
Equation (137)
159
= + = − = + =
nn
d(X1) d(X2) n(X1) n (X2) n
KK II
I ; I I ; K K ; K K -
2 2 2 2
I
,
we have
+−
= + −
+−
thn
nn
nn
II
I I
22
V
KK
K K
22
osn
V
Equation (138)
Following the similar derivation method in obtaining Equation (110), we have the input-referred
DC-offset voltage V os for the input transistor pair shown in Figure 11-7 as:
= + −
thn
1
V
2
n
osn
nn
K II
V
K I K
Equation (139)
Similarly, we can derive Vosp as
= + −
thp
1
V
2
p
osp
pp
K
II
V
K I K
Equation (140)
From Equation (139) and Equation (140), we have
()
thn thp
11
V V
22
os Total osn osp
p
n
n n p p
V V V
K
I I K I I
K I K K I K
=+
= + + − + −
Equation (141)
11.2.3.1 Input-referred offset voltage expression for NMOS-PMOS cross-coupled pair
transistors with common-source input transistors
A cross-coupled inverter pair with input transistors and a tail current source transistor
(Figure 11-10 (a)) are analyzed for small-signal operation to derive the expression for the
input-referred DC-offset voltage. The operation of this circuit is also based on the regeneration
(positive feedback) provided by transistors X3, X5 and X4, X6. Depending on the polarity of the
value of (Vin1 – Vref), the output voltages Vout1 and Vout2 settle to opposite rails (Vdd or Gnd) due to
the regeneration mechanism.
160
R
ox1
g
mx5
*V
out2
g
mx3
*V
a
(b)
g
mx1
*V
in R
ox5
R
ox3
V
out1
X4 X3
X1 X2
(a)
V
out2
V
IN
V
REF
X5 X6
V
b
X7
Figure 11-10: Cross-Coupled inverter pair with input transistors (a) Transistor-level
representation (b) Transistor small-signal half-circuit equivalent representation.
Transistors X1 and X2 provide the inputs for comparison, biased to be operating in saturation
region. X7 is the tail current source transistor providing a constant current to the circuit.
Figure 11-10(b) shows the small-signal half-circuit equivalent representation of Figure 11-10(a).
Transistors X1, X3 and X5 form the half circuit with transistor X1’s source node considered as
AC-ground. For input transistors X1 and X2, the input-referred offset voltage is given by
With both the input pair transistors biased to be operating in Saturation region of operation having
equal gate to source voltage (
gs
V ), we have the mismatch in the input transistors manifested as
offset voltage (
os
V ) appearing at the input of the transistors given by:
V - V V
gs(X2) gs(X1) os
= Equation (142)
The over-drive voltage Vov for a transistor operating in saturation region = Vgs -Vth, then
) V (V V V V
th(X2) ov(X2) th(X1) ov(X1) os
+ + = Equation (143)
= +
d(X1) d(X2)
os thn
( 1) ( 2)
II
V V -
n X n X
KK
Equation (144)
161
Where,
;
2
K
- K K ;
2
K
K K ;
2
I
I I ;
2
I
I I
n
n (X2)
n
n n(X1) d(X2) d(X1)
=
+ =
− =
+ = Equation (145)
+−
= + −
+−
thn
nn
nn
II
I I
22
V
KK
K K
22
os
V
Equation (146)
Following the similar derivation method in obtaining Equation (110), we have the input-referred
DC-offset voltage V os for the input transistor pair shown in Figure 11-10 as:
= + −
in
thn
in
I 1
V
2I
in n
os
nn
IK
V
KK
Equation (147)
Here,
in
in
I
I
is due to the mismatch from the load (cross coupled inverter) as the mismatch in the
input pair is already accounted for the NMOS input pair transistors in the form of
thn
V and
n
n
K
K
.
At node Vout1, we have In + Ip + Iin = 0; where In is saturation drain current through transistor X5; Ip
is the saturation drain current through transistor X3 and Iin is the saturation drain current flowing
through the input transistor X1.
=+
p
in n
in n p
I
II
I I I
Equation (148)
Since both the PMOS transistors X3 and X4 have the same gate to source voltage, therefore,
Vsg3 = Vsg4, the over-drive voltage Vov for a transistor operating in saturation region = Vgs -Vth, then
V V V V
th(X4) ov(X4) th(X3) ov(X3)
+ = + Equation (149)
=
d(X3) d(X4)
thp
( 3) ( 4)
II
V - ;
p X p X
KK
Equation (150)
r) (transisto
r) (transisto ox
or) n(transist
) 2 (
d(X2)
ov(M2)
) 1 (
d(X1)
ov(X1) th(X2) th(X1) thn
L
W C
K ;
I
V ;
I
V ; V - V V
n
X n X n
K K
= = = =
162
Where,
thp th(X4) th(X3)
d(X3) d(X4) ox (transistor)
ov(X3) ov(X4) p(transistor)
( 3) ( 3) (transistor)
V V - V ;
I I C W
V ; V ; K
L
p
p X p X
KK
=
= = =
Equation (151)
;
2
K
- K K ;
2
K
K K ;
2
I
I I ;
2
I
I I
p
p p(X4)
p
p p(X3)
p
p d(X4)
p
p d(X3)
=
+ =
− =
+ =
2
K
K
2
I
I
2
K
K
2
I
I
V
p
p
p
p
p
p
p
p
thp(X3)
−
−
−
+
+
= Equation (152)
Proceeding in a similar fashion for deriving Equation (110), we have
−
=
p
p
p
K
K
K
p
p p
thp(X3)
I
I I
2
1
V , Equation (153)
hence, we have
) 3 (
) 3 (
) 3 (
thp(X3)
p
p
V
2
I
I
X p
X p
X ov
K
K
V
+
=
Equation (154)
Also, both the NMOS transistors X5 and X6 have the same gate to source voltage
therefore, Vgs5 = Vgs6; similarly working out the derivation for determining
n
n
I
I
we have,
) 5 (
) 5 (
) 5 (
thn(X5)
n
n
V
2
I
I
X n
X n
X ov
K
K
V
+
=
Equation (155)
Substituting Equation (148), Equation (154) and Equation (155), we get
thn(X5) thp(X3)
( 5) ( 3)
thn
( 1)
( 3) ( 5) ( 1)
( 3) ( 5) ( 1)
V V
22
1
V
2
ov X ov X
in
os
nX
p X n X n X
p X n X n X
VV
I
V
K
K K K
K K K
+
= +
+ + −
Equation (156)
163
Analyzing Equation (141) and Equation (156), we see a similar expression for both cross-coupled
inverter pair and cross-coupled inverter pair with a common-source load. The only difference is that
the (ΔVtp) and (ΔVtn) terms in Equation (156) have a multiplication factor of gmX/gmin. This suggest
that the influence of the cross coupled inverter pair on the input-referred offset voltage
determination, can be reduced by increasing the transconductance of input transistor (gmin) acting
as a common-source load.
11.2.4 Input-referred offset-voltage expression for clocked-comparator
The clocked-comparator circuit shown in Figure 11-11 was analyzed for small-signal operation to
derive the expression for the input-referred offset voltage. Ideal condition is ΔVout(out1-out2) = 0 for
ΔVin(in1-ref) = 0 which is the balanced state (say B1). Due to random mismatch Vout1 ≠ Vout2, hence,
ΔVin is applied to compensate the mismatch, such that ΔVout(out1-out2) = 0. This new balanced state
is same as B1 because mismatches are small disturbances that will not the change the bias
condition of the comparator. To calculate the ΔVin, node voltages in balanced state B1 need to be
found and then treated as the desired state when ΔVin is applied to compensate for mismatch.
Let us choose Vlatch (Latch_Clk) to be high “logic 1” to determine the operating conditions of each
transistor. Also Latch_Clk = “logic 1” is the state when i/p referred offset is maximized by the gain
to reflect at the output.
With Latch_Clk = “logic 1” = Vdd = 1.8 V; PMOS transistors Xlp1 and Xlp2 are OFF as (Vgate = Vdd)
PMOS transistors X3 and X4 have equal Vdrain and Vgate, operating in saturation region. NMOS
transistors Xln1 and Xln2 are in linear region as these transistors act as a switch (Vgate = Latch_Clk
= Vdd and Vdrain = V(out1) = Vdd – Vtp (X3 or X4); also, since |Vtp| > |Vtn|; Vgate –Vtn > Vdrain (V(out1));
Nodes X and Y are pulled close to out1 and out2 respectively and since Vin = Vref, hence Xin1 and
Xin2are operating in saturation region. Gate of X1 andX2 are connected to out1 and out2
respectively. If Vxx > V(out1) – Vtx1 then NMOS transistors X1 and X2 are in saturation. Table 11.5
summarizes the transistors and their region of operation.
164
V latch_Clk
I 1
Vdd
V out1 V out2
V REF
XIN1 XIN2
X3 X4
X1 X2
Xtail1
V IN
V latch_Clk
V latch_Clk
XL3
XL4
XL1 XL2
Xtail0
a
Figure 11-11: Full schematic circuit diagram of a clocked-comparator deriving the
expression for standard deviation of input-referred offset voltage Vos.
Table 11.5: Transistors and their region of operation in the clocked-comparator circuit shown in
Figure 11-11.
Transistors in Figure 11-11 Region of Operation
XL3 /XL4 OFF
X3 /X4 Saturation
XL1 / XL2 Linear
XIN1 / XIN2 Saturation
X1 / X2 Saturation
Let us derive the expression for the input-referred offset due to mismatch in Xin1 & Xin2. With both
the input pair transistors biased to be operating in Saturation region of operation having equal gate
to source voltage ( ) we have the mismatch in the input transistors manifested as offset voltage
( ) appearing at the input of the transistors given by:
V - V V
gs(Xin2) gs(Xin1) os
= Equation (157)
The over-drive voltage Vov for a transistor operating in saturation region = Vgs -Vth, then
) V (V V V V
th(Xin2) ov(Xin2) th(Xin1) ov(Xin1) os
+ + = Equation (158)
gs
V
os
V
165
) 2 (
d(Xin2)
) 1 (
d(Xin1)
thn os
I
-
I
V V
Xin n Xin n
K K
+ = Equation (159)
Where,
thn th(Xin1) th(Xin2)
d(Xin1) d(Xin2) ox (transistor)
ov(Xin1) ov(M2) n(transistor)
( 1) ( 2) (transistor)
V V - V ;
I I C W
V ; V ; K
L
n
n Xin n Xin
KK
=
= = =
Equation (160)
= + = − = + =
nn
d(Xin1) d(Xin2) n(Xin1) n (Xin2) n
KK II
I ; I I ; K K ; K K - ;
2 2 2 2
I
+−
= + −
+−
thn
nn
nn
II
I I
22
V
KK
K K
22
os
V
Equation (161)
Following the similar derivation method in obtaining Equation (110), we have the input-referred
offset voltage V os for the input transistor pair shown in Figure 11-11 as:
= + −
( 1) ( 1)
in
thn
( 1) in ( 1)
I 1
V
2I
Xin n Xin
os
n Xin n Xin
IK
V
KK
Equation (162)
Here, arises from the mismatch between transistors X1-X2 and X3-X4, as the mismatch in
the input pair is already accounted for the NMOS input pair transistors in the form of and
.
Let us consider the mismatch in transistors X3 and X4. Since both the PMOS transistors X3 and
X4 have the same gate to source voltage, therefore, Vsg3 = Vsg4, the over-drive voltage (Vov) for a
transistor operating in saturation region = Vgs -Vth, then
Equation (163)
in
in
I
I
thn
V
n
n
K
K
V V V V
th(X4) ov(X4) th(X3) ov(X3)
+ = +
;
I
-
I
V
) 4 (
d(X4)
) 3 (
d(X3)
thp
X p X p
K K
=
166
Where,
Equation (164)
Proceeding in a similar fashion for deriving Equation (110), we have
, hence, we have Equation (165)
Equation (166)
Also, both the NMOS transistors X1 and X2 have the same gate to source voltage,
Vgs1 = Vgs2; similarly working out the derivation for determining we have,
) 1 (
) 1 (
) 1 (
thn(X1)
n
n
V
2
I
I
X n
X n
X ov
K
K
V
+
=
Equation (167)
Substituting Equation (148), Equation (154) and Equation (155), we get
thn(X1) thp(X3)
( 1) ( 3)
thn(Xin1) ( 1)
( 3) ( 1) ( 1)
( 3) ( 1) ( 1)
V V
22
1
V
2
ov X ov X
os ov Xin
p X n X n Xin
p X n X n Xin
VV
VV
K K K
K K K
+
= +
+ + −
Equation (168)
Considering the standard deviation of ΔVthn, ΔVthp, ΔKn we have the variance of input-referred
DC-offset voltage as
r) (transisto
r) (transisto ox
or) p(transist
) 3 (
d(X4)
ov(X4)
) 3 (
d(X3)
ov(X3) th(X3) th(X4) thp
L
W C
K ;
I
V ;
I
V ; V - V V
p
X p X p
K K
= = = =
;
2
K
- K K ;
2
K
K K ;
2
I
I I ;
2
I
I I
p
p p(X4)
p
p p(X3)
p
p d(X4)
p
p d(X3)
=
+ =
− =
+ =
2
K
K
2
I
I
2
K
K
2
I
I
V
p
p
p
p
p
p
p
p
thp(X3)
−
−
−
+
+
=
−
=
p
p
p
K
K
K
p
p p
thp(X3)
I
I I
2
1
V
) 3 (
) 3 (
) 3 (
thp(X3)
p
p
V
2
I
I
X p
X p
X ov
K
K
V
+
=
n
n
I
I
os
V
167
11.2.4.1 Hand calculations and Hspice simulation setup to validate the derivations and
hand calculations
Table 11.6: Design parameters for the clocked-comparator shown in Figure 11-11.
Transconductance gm(Xin1) = gm(Xin2) 80 μS
Transconductance gm(X1) = gm (X2 74.8 μS
Transconductance gm(X3) = gm(X4) 67.3 μS
Current I(Xin1) = I(Xin2) 3 μA
W/L (Xin1) 20 μm /0.18 μm
W/L (X1) 9 μm / 0.18 μm
W/L (X3) 22 μm / 0.18 μm
Avt-nmos 7 mVμm
Aβ -nmos 8.98 mV*μm
Avt-pmos 8.697 mV*μm
Aβ -pmos 10.11 mV*μm
Table 11.6 shows the design parameters for the circuit shown in Figure 11-11. With these design
parameters, hand calculations of the standard deviation (3-sigma) of the input-referred offset
voltage from Equation (100), Equation (101) and Equation (169) yield 5.02 mV. A simulation test
bench was setup to capture the input-referred offset voltage using Monte-Carlo simulations in
Hspice. Appendix C shows the netlist, to simulate the input-referred offset voltage for the
clocked-comparator. A differential input voltage sweep was setup in series with a DC input common
mode of 0.9 V for this simulation. Monte-Carlo iteration number in the sweep was varied for each
run (10, 100, 300, 500, 700, 1000, 5000) to calculate the input-referred offset voltage of the
differential-pair amplifier with the resistive load for each iteration. The result for one-standard
deviation of input-referred offset for 10,000 iteration Monte-Carlo simulations came to be 5.45 mV.
Table 11.7 displays the standard deviation in the input-referred offset recorded for various
Monte-Carlo iterations. Figure 11-12, plots the data in the Table 11.7 using Microsoft-Excel
spreadsheet. This value of 5.45 mV obtained from 10,000 iteration runs, matches the hand
) (
2
) (
2
) (
2
2
) 1 (
) (
2
2
) 1 (
) 1 (
) (
2
2
) 3 (
) 1 (
) (
2
) (
2
) 1 (
) 1 (
) 1 (
) 1 (
) 3 (
) 3 (
) 1 ( ) 3 ( ) 1 (
−
+
+
+ =
+
Xin n
Xin n
X n
X n
X p
X p
X thn X thp Xin thn os
K
K
K
K
K
K
Xin m
V
X mn
Xin mn
V
X mp
Xin mn
V V
g
I
g
g
g
g
Equation (169)
168
calculation value of 5.02 mV, validating the derivation for calculating the input-referred offset
voltage for the comparator.
Table 11.7: 3-sigma standard deviation in the input-referred offset recorded for various Monte-
Carlo iterations for differential amplifier with PMOS load.
Mode Process Corner Temperature
No of
Monte-
Carlo
Runs
3-sigma
standard
deviation of
Input-referred
Offset (mV)
Hand
Calculations Typical Mean 27 1 5.020
Monte Carlo Monte Carlo Gaussian 27 5 0.113
Monte Carlo Monte Carlo Gaussian 27 100 1.100
Monte Carlo Monte Carlo Gaussian 27 300 2.720
Monte Carlo Monte Carlo Gaussian 27 500 5.450
Monte Carlo Monte Carlo Gaussian 27 750 5.460
Monte Carlo Monte Carlo Gaussian 27 1000 5.224
Monte Carlo Monte Carlo Gaussian 27 5000 5.450
Figure 11-12: Microsoft-Excel spreadsheet plot capturing the HSpice simulation results for
each iteration run of Monte-Carlo simulations for the clocked-comparator circuit shown in
Figure 11-11.
Table 11.8 summarizes the results for the three different circuits analyzed for determining the
standard deviation of the input-referred offset voltage through Monte-Carlo simulations.
169
Table 11.8: 3-sigma standard deviation of the input-referred DC-offset.
Circuit
3-sigma standard
deviation of Input-
Referred Offset Hand
calculations
(mV)
3-sigma standard
deviation of Input-
Referred Offset
(Monte-Carlo
Simulations)
(mV)
No of
Monte-
Carlo
Runs
Differential-Pair Amplifier
with Resistive load
8.350 8.280 5000
Differential-Pair Amplifier
with PMOS current
mirror load
13.68 13.896 5000
Clocked-Comparator 5.020 5.450
5000
1/f noise contribution reduction techniques
Table 11.9 shows the worst-case power corner (wp) 1/f noise corner-frequency across temperature
for the following three process technologies:
A. The 0.6 m minimum gate-length and 0.8 m minimum gate-width NMOS transistor in the
XFAB foundry’s 0.6 m XC06 CMOS process-technology.
B. The 0.35 m minimum gate-length and 0.7 m minimum gate-width NMOS transistor in the
XFAB foundry’s 0.35 m XH035 CMOS process-technology.
C. The 0.18 m minimum gate-length and 0.25 m minimum gate-width NMOS transistor in
the XFAB foundry’s 0.18 m XH018 CMOS process-technology.
Table 11.9: 1/f noise corner-frequency simulations for three XFAB technologies.
Worst case Power (wp) 1/f noise corner-frequency for three XFAB foundry’s process
technologies
Process-
technology 0.6 m CMOS XC06 0.35 m CMOS XH035 0.18 m CMOS XH018
Temperature
(
o
C)
XC06 Noise Corner-
frequency (kHz) for
NMOS transistor with
W/L (0.8 m / 0.6 m)
XH035 Noise Corner-
frequency (kHz) for
NMOS transistor with
W/L (0.7 m / 0.35 m)
XH018 Noise Corner-
frequency (kHz) for
NMOS transistor with
W/L (0.25 m /
0.18 m)
-10 530 940 4350
20 542 966 4410
40 550 975 4470
80 564 985 4520
100 572 1020 4610
125 582 1050 4670
170
Figure 11-13: Microsoft-Excel spreadsheet plotting the 1/f noise corner-frequency across
temperatures from Table 11.9 for three XFAB technologies mentioned above.
As we can see from the Table 11.9 and Figure 11-13, the 1/f noise corner-frequency is 1 MHz for
0.35 m XH035 CMOS process. Therefore, any circuit that employs sampling clock of less than or
close to 1 MHz will have to compensate for the 1/f noise contribution, as it is significantly higher
than the MOSFET thermal-noise contribution below the 1/f noise corner-frequency. Since the
SAR ADC sampling clock is 100 kSamples/s, the problem of 1/f noise contribution affecting the
ADC performance must be cancelled. The auto Zeroing (AZ) / Correlated Double Sampling (CDS),
as well as the chopper Stabilization (CHS) technique, were evaluated to understand the reduction
of the non-ideal effects in the circuits, namely, the 1/f noise, thermal noise, clock feed-through,
channel charge injection. Since CDS technique involves the AZ process, discussing CDS technique
for the non-ideal effects’ reduction will cover the effect of AZ process as well.
11.3.1 CDS technique for reducing the 1/f noise contribution
The CDS can be used not only cancels the amplifier offset, but also reduces the 1/f noise
contribution. Unlike the offset voltage that can be considered constant, the amplifier’s noise is time
varying. The efficiency of the CDS process for the 1/f noise contribution cancellation will strongly
depend on the correlation between the noise sample and the instantaneous noise value from which
the sample is subtracted. The correlation between these two samples of 1/f noise that are
171
separated by a time interval of τ decreases much slower with the increasing τ. The CDS technique
is; thus, efficient for reducing the 1/f noise contribution. The power spectral density (PSD) of the
CDS process can be decomposed into two components: one caused by the 1/f noise contribution
and the other by the fold-over components introduced by sampling of aliased signal. The fold-over
component results from the replicas of the original spectrum shifted by the integer multiples of the
sampling frequency. Equations and plots in [5] show that the magnitude of the transfer function
related to the 1/f noise presents a zero at the origin frequency that cancels out any dc component
present in the noise source. The CDS technique not only cancels the amplifiers DC-offset, but also
strongly reduces the amplifiers 1/f noise due to the double zero introduced by the baseband power
transfer function as shown in [5]. This improvement is obtained at the cost of increased white noise
fold-over component due to the aliasing of the amplifier’s thermal noise.
11.3.2 Chopper Stabilization (CHS) technique for reducing the 1/f noise contribution
The effect of the chopper modulation on the amplifier noise can be analyzed by modulating a noise
source with a carrier signal. The output PSD is derived from the summation of the replicas of the
original spectrum shifted to the odd harmonics of the chopper frequency. Unlike CDS technique,
the chopper modulation does not introduce aliasing of the thermal noise, which for CDS causes the
PSD in the low-frequency to increase proportionally with the ratio of noise bandwidth and the
sampling frequency. The low-frequency PSD resulting from the chopper modulation is nearly
constant [5]. This is because, the noise is not sampled nor held, just periodically inverted without
changing the general properties of the noise in the time domain. Since the noise is modulated only
once, they are transposed to the odd harmonics of the output chopping square wave, leaving the
amplifier ideally without any low- frequency noise. The transfer function for the low-frequency PSD
in the chopper modulation shows that 1/f noise pole is completely removed thus indicating the
1/f noise cancellation.
172
Choice of the technique to compensate for the comparator
mismatch, input-referred DC-offset and 1/f noise contributions
Let us look at the SAR-A ADC architecture to analyze the offset contribution from various circuit-blocks.
We can see from the SAR ADC architecture shown in Figure 4-2, the single-ended analog-input signal
is first sampled by the sample and hold circuit. The sample-and-hold signal processing is single-ended;
therefore, the concept of mismatch does not arise. Comparator block is the second stage in the signal
flow after sample and hold where the sampled input is compared with the reference voltage. Any
mismatch inherent to the comparator block has a decisive impact in creating an error in comparison at
the output of the comparator. This error will directly add to the quantization error of the SAR ADC, limiting
the accuracy of the analog to digital conversion. Thus, the comparator is the dominant part of the
SAR ADC architecture that provides the largest offset contribution. Re-using analog circuit-blocks such
as the shared comparator, between the SAR and Algorithmic ADC reduces the implementation-area,
and normalize the effects of mismatch, input referred DC-offset and 1/f noise contribution, between the
two modes. The input-referred offset-voltage compensation for the comparator is essential in reducing
the overall offset contribution of the SAR-A ADC. The three techniques of Auto-Zeroing, CDS and CHS
have been evaluated for their use in offset cancellation for the comparator block of the SAR-A ADC. With
the comparisons made on the three techniques, it is apparent that a CHS can eliminate the effects of
mismatch; input-referred DC-offset and cancels the 1/f noise contribution. Modulating the signal to a
higher frequency by m1(t) (shown in Figure 11-4) (frequency where 1/f noise contribution is insignificant)
and then demodulate back (m2(t) also shown in Figure 11-4) to the baseband after comparison
eliminates the 1/f noise contribution effect on the shared-comparator.
173
12 Reference Appendix
123. C. C. Enz and G. C. Temes, "Circuit Techniques for Reducing the Effects of Op-Amp
Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilization," IEEE,
JSSC, Nov. 1996.
124. Suarez, R.E., Gray, P.R., Hodges, D.A, “All-MOS charge-redistribution analog-to-digital
conversion techniques. II” IEEE JSSC, Dec. 1975.
125. Shrivastava A, “12-bit non-calibrating noise-immune redundant SAR ADC for system-on-
a-chip IEEE ISCAS, May 2006.
126. Scott, M.D et al., “An ultra–low power ADC for distributed sensor networks”, IEEE ESSIRC,
Sept. 2002.
127. Hwi-Cheol Kim et al., “A partially switched-Opamp technique for high-speed low-power
pipelined analog-to-digital converters”, IEEE TCAS I, April 2006.
128. Michael D. Scott et al., “An Ultralow-Energy ADC for Smart Dust”, IEEE JSSC, July 2003.
129. Li, P.W., Chin, M.J., Gray, P.R., Castello, R., “A ratio-independent algorithmic analog-to-
digital conversion technique”, Solid-State Circuits, IEEE Journal of Volume 19, Issue 6,
Page(s): 828 – 836, Dec. 1984
130. Jin-Sheng Wang, Chin-Long Wey, “A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic
A/D converter”, IEEE TCAS II, May 1999.
131. Chun-Jen et al., “A low-voltage CMOS rail-to-rail operational amplifier”, IEEE ISCAS, 2004.
Abstract (if available)
Abstract
Neural-sensing, defined as the real-time, continuous monitoring of neural-signals, has many important uses. It is required for the accurate detection of precursors of neural disorders such as epilepsy. Neural-sensing enables the detection of posture variations, enhancing the quality of life of patients suffering from neuro-muscular disorders such as Parkinson’s disease, Dystonia, and Essential tremor. Unlike open-ended neural-stimulation in which stimulation is either active with the help of patient feedback or continuously active - positive, long-term stimulation therapy outcomes require timely and reliable stimulation therapy, which requires autonomous closed-loop stimulation solutions. Autonomous closed-loop stimulation solution requires multi-channel neural-sensing integrated with the neural-stimulation system to close the loop in implantable biomedical systems. The key for any implantable biomedical system that aims at sensing neural-signals is an Analog to Digital Converter (ADC). The ADC converts the incoming, amplified, analog neural-signal to its digital representation for further processing, and evaluation. To close the loop, multi-channel implantable systems require high-performance ADCs that switch between sampling-speeds less than 1 MSamples/s (MSa/s) for sensing neural local field potentials, and 1-10 MSa/s for sensing evoked or spontaneous neural action-potentials, as well as neural spike sorting. Multi-channel (30-100 channels) implantable biomedical systems can either have multiple (30-100) ADCs implemented on the same die [6 - 8] or can have a single ADC sampling at a very high rate of at least two-to-three times greater than the neural signal bandwidth multiplied by the number of sensing channels, multiplexing all the channels (30-100), for neural-sensing and/or neural spike-sorting. The available ADC implementation choices magnify the impact of power-dissipation and silicon-area per ADC in multi-channel implantable systems, that strive for battery life of 7 – 10 days on a rechargeable battery and/or small implantable device size less than twenty (20) cubic-centimeters. ❧ This dissertation proposes and validates an original shared-architecture Successive Approximation Register / Algorithmic (SAR-A) ADC for closed-loop implantable biomedical systems, to achieve significantly lower area at similar power and specifications as individual ADCs that achieve desired specifications in each sampling range. The proposed SAR-A ADC combines the Successive Approximation Register (SAR) ADC architecture for sampling-speeds less than 1 MSa/s for multi-channel sensing of neural local field potentials, and the Algorithmic ADC architecture for sampling-speeds between 1-10 MSa/s for multi-channel sensing of evoked or spontaneous neural action-potentials, providing 12-bits of resolution in each sampling-speed range with reduced implementation-area and power-dissipation over alternate solutions. ❧ The SAR-A ADC architecture was first designed, implemented and simulated in the 0.35 µm CMOS XFAB XH035 process, where the worst-case, post-layout, pad-to-pad, extracted simulation power-dissipation of the 12-bit SAR-A ADC is 95.5 µW for the SAR ADC mode sampling at 100 kSa/s, and 4.87 mW for the Algorithmic ADC mode sampling at 5 MSa/s. The core implementation-area of the 12-bit SAR- A ADC in the 0.35 µm CMOS process is 0.55 mm². The 0.35 µm CMOS process from XFAB foundry was chosen as the process-technology vehicle to verify the SAR-A ADC architecture. This was mainly due to the availability of high-voltage Metal Oxide Semiconductor (MOS) transistor process-modules in this process (along with the 0.6 µm, and the 0.8 µm CMOS process) that are typically used for the delivery of the neural-stimulation therapy. With the CMOS technology scaling rapidly, and with the availability of the high-voltage MOS transistor process-modules in deep sub-micron process like the 0.18 µm CMOS, it is now viable to utilize the 0.18 µm (or 180 nm) CMOS process as a test vehicle to realize the SAR-A ADC. The 12-bit SAR-A ADC architecture is fabricated in 180 nm CMOS Six-metal one-polysilicon gate (6M1P) XFAB XH018 process with a supply-voltage of 1.8 V, occupying a core implementation-area of 0.31 mm². In the SAR and the Algorithmic ADC modes, the measured power-dissipation (including the analog, digital, and reference) is 36.9 µW and 3.99 mW respectively, operating from a 1.8 V power supply. In the 100 kSa/s SAR ADC mode, the ADC achieves a measured SFDR of 66.3 dB, a measured SINAD (SNDR) of 65.081 dB, and a measured ENOB of 10.518 bits. The SAR ADC mode’s measured DNL and INL are 0.54 LSB and 0.66 LSB, respectively. In the Algorithmic ADC mode, at 5 MSa/s, the ADC achieves a measured SFDR of 63.87 dB, a measured SINAD (SNDR) of 62.77 dB, and a measured ENOB of 10.134 bits. The Algorithmic ADC mode’s measured DNL and INL are 1.08 LSB and 1.17 LSB, respectively.
Linked assets
University of Southern California Dissertations and Theses
Conceptually similar
PDF
CMOS mixed-signal charge-metering stimulus amplifier for biomimetic microelectronic systems
PDF
A biomimetic approach to non-linear signal processing in ultra low power analog circuits
PDF
Towards high-performance low-cost AMS designs: time-domain conversion and ML-based design automation
PDF
High power, highly efficient millimeter-wave switching power amplifiers for watt-level high-speed silicon transmitters
PDF
Mixed-signal integrated circuits for interference tolerance in wireless receivers and fast frequency hopping
PDF
Bidirectional neural interfaces for neuroprosthetics
PDF
Wideband low phase-noise RF and mm-wave frequency generation
PDF
Improving the speed-power-accuracy trade-off in low-power analog circuits by reverse back-body biasing
PDF
Silicon-based RF/mm-wave power amplifiers and transmitters for future energy efficient communication systems
PDF
Analog and mixed-signal parameter synthesis using machine learning and time-based circuit architectures
PDF
A power adaptive low power low noise band-pass auto-zeroing CMOS amplifier for biomedical implants
PDF
Silicon-based wideband & mm-wave power amplifier architectures and implementations
PDF
Charge-mode analog IC design: a scalable, energy-efficient approach for designing analog circuits in ultra-deep sub-µm all-digital CMOS technologies
Asset Metadata
Creator
Gururaj, Kiran K.
(author)
Core Title
Low-power, dual sampling-rate, shared-architecture ADC for implantable biomedical systems
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
05/09/2021
Defense Date
12/10/2018
Publisher
University of Southern California
(original),
University of Southern California. Libraries
(digital)
Tag
ADC,CMOS integrated circuits,data conversion,dual sampling rate,neural sensing,OAI-PMH Harvest
Format
application/pdf
(imt)
Language
English
Contributor
Electronically uploaded by the author
(provenance)
Advisor
Madhavan, Bindu (
committee chair
), Prata, Aluizio (
committee chair
), Chen, Shuo-Wei (
committee member
), Moore, James (
committee member
)
Creator Email
gururaj@usc.edu,kirangururaj@gmail.com
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-c89-155592
Unique identifier
UC11660350
Identifier
etd-GururajKir-7307.pdf (filename),usctheses-c89-155592 (legacy record id)
Legacy Identifier
etd-GururajKir-7307.pdf
Dmrecord
155592
Document Type
Dissertation
Format
application/pdf (imt)
Rights
Gururaj, Kiran K.
Type
texts
Source
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Access Conditions
The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...
Repository Name
University of Southern California Digital Library
Repository Location
USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA
Tags
ADC
CMOS integrated circuits
data conversion
dual sampling rate
neural sensing