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Flag the faults for reliable quantum computing
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Flag the faults for reliable quantum computing
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FLAG THE FAULTS FOR RELIABLE QUANTUM COMPUTING Copyright 2020 by Rui Chao A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) August 2020 Rui Chao Acknowledgements I feel privileged to have had the opportunity to work with my advisor Ben Reichardt for the past five years. I am sincerely grateful for his invaluable mentorship and unwavering support. He has been a role model for both research and life, and will continue to influence me with his wisdom, meticulosity and integrity. I would also like to thank my qualifying and defense committee- Todd Brun, Daniel Lidar, Stephan Haas, Edmond Jonckheere and Grace Lu- for their helpful suggestions and feedback. I am fortunate to have collaborated with many wonderful researchers in the field. I would like to thank Mario Szegedy for his valuable guidance when I was an intern at Alibaba Quantum Lab and visiting student at Simons Institute; I appreciate the inspiring discussions with Cupjin Huang, David Ding and Andras Gilyen. I would also like to thank Michael Beverland, Nicolas Delfosse and Jeongwan Haah, who have taught me a lot during my internship at Microsoft Quantum. I am also lucky to have received help from many other mentors, colleagues and friends throughout my graduate study. I am particularly grateful to Yaoyun Shi, Jianxin Chen, Ken Brown, Michael Newman and Zhang Jiang for their beneficial advice and insights. Thanks are also due to my office-mate Qian Yu for helping me with math problems. Finally, I would like to thank my parents for their unconditional love and encouragement. ii Table of Contents Acknowledgements List of Tables List of Figures Abstract 1 Introduction 1.1 Motivation and background 1.2 Main results and thesis outline 1.3 Related works and outlook . 2 Preliminaries 2.1 States and gates 2.2 Stabilizer formalism .. 2.3 Fault-tolerance criteria . 3 Flag paradigm-catch the bad faults 3.1 Conventional fault-tolerance constructions ..... . 3.1.1 Transversal implementations of logical gates . 3.1.2 Shor-style error correction ...... . 3.1.3 Steane-style error correction . . . . . . 3.1.4 DiVincenzo-Aliferis decoding method . 3.2 Flag paradigm for quantum fault tolerance 3.2.1 Flag circuits for measuring stabilizers 3.2.2 Flag gadgets for logical computations 4 Flag fault-tolerant error correction 4.1 Flag error correction for common distance-three codes ..... . 4.1.1 Two-qubit error correction for Hamming codes ..... . 4.1.2 Two-qubit error correction for other distance-three codes 4.1.3 Numerical simulations ........... . 4.1.4 Benefits of more flags ........... . 4.2 Flag error correction for arbitrary stabilizer codes . 4.2.1 Notions ................... . 4.2.2 Syndrome-extraction circuits and correction rules . 4.2.3 Computer search for correction rules . . . . . . . . iii ii V vi xi 1 1 4 10 14 14 19 25 31 31 31 34 36 37 38 39 43 46 46 49 51 53 55 58 59 60 68 5 Flag fault-tolerant computation 5.1 Flag gadgets for CZ and CCZ 5.1.1 CZg~g~ ...... . 5.1.2 CCZ gadget ...... . 5.2 Flag computation for [n , n - 2, 2] codes 5.2.1 Permutation symmetries and transversal operations 5.2.2 CZ gate . . . . . . . . . . 5.2.3 Targeted Hadamard gate ......... . 5.2.4 Four-ancilla CCZ gate . . . . . . . . . . . . 5.3 Flag computation for the Hamming [15, 7, 3] code 5.3.1 [15, 7, 3] Hamming code . 5.3.2 Transversal operations ........... . 5.3.3 Permutation symmetries . . . . . . . . . . . 5.3.4 CZ circuits based on permutation symmetries . 5.3.5 Round-robin CZ circuits to complete the Clifford group 5.3.6 Four-qubit fault-tolerant CCZ for universality ..... 6 Other applications of the flag paradigm 6.1 Flag error detection for [n, n - 2, 2] codes ............ . 6.2 Flag state preparation and measurement . . . . . . . . . . ... . 6.2.1 State preparation and measurement for the [5, 1, 3] code . 6.2.2 State preparation for the [15, 7, 3] code ......... . 6.2.3 State preparation and measurement for [n, n - 2, 2] codes 6.3 Flag error correction for fermionic simulations . . . . . 6.3.1 Majorana loop stabilizer codes ........ . 6. 3.2 Fault-tolerant error correction using the MLSC 7 Fault-tolerant error correction with slow qubit reset 7.1 Ancilla-decoding-based scheme for arbitrary distance-three codes Bibliography iv 71 74 75 76 77 78 80 81 82 82 83 83 84 85 89 94 97 97 98 98 100 101 103 105 107 112 ......... . 113 116 List of Tables 4.1 Numbers of ancilla qubits required for different fault-tolerant syndrome-extraction methods. Shor's method, using a verified cat state, requires w + l ancilla qubits, where w is the largest weight of a stabilizer generator. (The [9, 1, 3] Bacon-Shor code is an exception, as it is a subsystem code.) Stephens, Yoder and Kim [Ste 14, YKl 7] have proposed using a cat state on only max{3, iw/21} qubits, combined with a decoding trick from [DA07]; see Section. 7.1. When applicable, our flagged error correction procedure needs only two extra qubits, as observed for the [7, 1, 3] code by [YK17]. Codes marked o are Hamming codes. . . . . . . . . . . . . . . . . . . 48 5.1 Sizes of the k-qubit Clifford group and subgroups. There are ISk I = kl permutations of k qubits. Pfc = A/{± 1, ±i}. CNOT gates generate a group of size IGL(k, 2) 1 = k 1 k · IJj: o (2 - 2 1 ) , adding Hadamard gates generates a larger group, and finally the full Clifford group, up to the I Pfc l = 4k phase-less Paulis, has size 2k 2 rr;=l(4k - 1). The sizes are given as multiples of the previous columns, e.g., I C 2/Pf I = 2 x 3 x 12 x 10 = 720. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.1 Numbers of ancilla qubits for different error-correction schemes. Here, d is the code distance and w is the maximum stabilizer generator weight. In Section. 4.1 and [CB18, TCL20], flag patterns can only detect or reveal partial information about the correlated data errors; adaptive syndrome measurement is further needed for full correction. In [Sho96, Ste97, Kni05b], correlated data errors cannot occur due to ancilla verification. In the other schemes in the table, syndrome-measurement circuits can be scheduled deterministically; (flag) ancilla patterns provide enough information to correct correlated errors. . . . . . . . . . . . . . . . . . . . . . . . . 113 V List of Figures 1.1 Examples of flag-based fault-tolerant schemes. One can fault-tolerantly error-correct one or three logical qubits, respectively using the [5, 1, 3] or [8, 3, 3] code, with no more than ten physical qubits in total. With two extra qubits, one can protect and apply the full Clifford group over the seven logical qubits encoded in the [15, 7, 3] code; four extra qubits are enough for fault-tolerant universal computation. . . . . 5 2.1 A circuit that first prepares a qubit in state IO), then applies gates H , Zand St, and finally measures in the X basis. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 (a) A Clifford circuit that teleports l'lfl) from qubit 1 to qubit 3 in six time steps. Measurements of X 1 and Z 2 yield outcomes a, b E { 1, -1}, respectively. Classical control then applies Z 3 or X 3 , conditioned on a or b, respectively, being nontrivial -1. (b) tracks the stabilizers step by step. Initially, the stabilizer of 11/J) is an unknown reflection but belongs to the algebra generated by X 1 and Z 1 . Therefore, to track l'lfl), it suffices to track X 1 and Z 1 , which we refer to as "logical operators" with abuse of notation. In step 3, the logical X, X 12 , is taken to be the equivalent X 13 , modulo a current stabilizer X 23 . Doing this allows us to avoid collapsing the logical state when measured by Z 2 in step 4, since Z 2 anti-commutes with X 12 . 24 3.1 A canonical choice of stabilizer generators and logical Pauli operators of the Steane code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 Shor-style measurement of a stabilizer X ®w (diagrams show w = 4) using w + l ancillas. (a) Prepare an ancilla qubit in state I+) and apply w CNOTs that control on the ancilla and target on the relevant data qubits. The outcome of the X-basis measurement on the ancilla gives the syndrome bit. An X fault (red) on the ancilla can spread into multiple X errors on the data. (b) Replace the bare ancilla with a w qubit cat state (IO) ® w + ll) ® w)/\1'2 (shaded in blue), and couple it with the relevant data qubits using transversal CNOTs. Apply transversal X-basis measurements on the ancillas, and XOR all the outcomes to get the syndrome bit. A single fault (red) when preparing the cat state can propagate into multiple X errors on the data. ( c) After preparing a cat state, measure the parities of pairs of ancilla qubits (blue) using an extra ancilla that can be recycled. On any odd parity, discard the cat state and re-prepare. Only couple the cat state with the data after verifying that, with high probability, X errors in the cat state did not propagate badly. . . . . . . . . 34 vi 3.3 Steane-style measurements of Z- and X -type stabilizers for a CSS code [n, 1, d] using at least 2n ancilla qubits. All the wires have slashes and represent code blocks of a same stabilizer code. CNOT and measurement symbols are corresponding transversal operations applied over the code blocks. To measure all the Z-type stabilizers, first prepare two code blocks both in the logical I+) state, denoted by "ancilla" and "verifier" respectively. Then perform transversal CNOTs from the verifier to the ancilla code block, followed by transversal X-basis measurements on the verifier. Next perform parity checks on the measured bit string against all the X -type stabilizer generators and the logical X operator. Repeat the preparation and verification until no error is detected. Conditioned on success, apply transversal CNOTs from the data to the ancilla block, followed by transversal Z -basis mea surements on the ancilla. Perform parity checks on the measured bit string agains all the Z-type stabilizers to obtain the syndrome bits. The procedure for X -type stabilizers is similarly constructed. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4 A circuit based on the DiVincenzo-Aliferis decoding method that measures X ® 4 and tolerates a single fault. Prepare the ancillas in a cat state and couple it with the relevant data qubits without verification. Then apply a carefully designed decoding circuit (shaded in blue) followed by qubit-wise measurements. The X basis measurement outcome gives the syndrome bit, and the Z-basis measurement outcomes give the information based on which the potential correlated data errors are corrected. Here, an X correction on the fourth data qubit is applied if and only if the Z-basis measurement outcomes are "101." One can verify that any single fault in the procedure results in at most one data error. . . . . . . . . . . . . . . . 38 3.5 A flag circuit that measures X ® 4 . A syndrome ancilla prepared in I+) is coupled with the four data qubits using CNOTs; a measurement in the X basis gives the syndrome bit when there is no fault. The syndrome ancilla is protected by a flag gadget (blue), which consists of a flag ancilla prepared in IO) and measured in the Z basis, as well as two CNOTs. Correlated errors on the data qubits can result from a single X fault (red) on the syndrome ancilla. But such bad propagation will also trigger the flag measurement outcome to be nontrivial (shaded in red). Provided the flag circuit is carefully designed, possible flagged data errors can be distinguishable, e.g, by their syndromes ( or along with flag pattern if more than one flag ancilla is used). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.6 Flag syndrome extraction for the [7, 1, 3] code. (a) A circuit that extracts the I I IX XX X syndrome, and if a single fault spreads to more than 2 data errors then the Z-basis measurement will return 11), flagging the failure. (b) The nontrivial data errors that can result from a single gate failure in (a) that triggers the flag; these errors are distinguishable by their syndromes and so can be corrected. 40 3.7 CZ gadgets to catch correlated faults. (a) A flag gadget (red) can be used to catch XX, XY, Y X and YY faults after the CZ gate. (b) A similar flag gadget (blue) catches Z Z faults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 Our flagged syndrome-extraction method uses just two ancilla qubits to correct errors fault tolerantly, for a variety of distance-three codes. For example, seven qubits total are enough to correct errors on one encoded qubit, using the [5, 1, 3] code, and 17 qubits are enough to protect seven encoded qubits. . . . . . . . . . . 48 vii 4.2 (a) [15, 7, 3] code parity checks. (b) Flagged circuit to extract the X{s, ... ,15} syndrome fault tolerantly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3 Flagged syndrome extraction for the [5, 1, 3] code. (a) Stabilizers and logical operators. (b) This flag circuit extracts the X Z Z XI syndrome, and if a single fault spreads to a data error of weight 2c: 2 then the X-basis measurement will return I-), flagging the failure. ( c) The nontrivial data errors that can result from a single gate failure in (b) that triggers the flag; these errors are distinguishable by their syndromes and so can be corrected. . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4 (a) Stabilizers for an [8, 3, 3] code. One choice for the logical operators is .X\ = x{4,5,7,s}, Z1 = z{2,5}x{3,s}, X2 = x {3,6}z{4,5} , Z2 = z{l ,5,6,7}, .X3 = z{l,2}X{6,7}, Z 3 = Z{i,2,4,7 }. (b) Stabilizers for a [10, 4, 3] code, based on the [5, 1, 3] code [CRSS97]. One choice for the logical operators is .X1 = X sY10Z1, Z 1 = X 1oY 7Z3, .X2 = X10YsZ2 , Z2 = XsY6Z5, .X3 = X9Y1Z1 , .Z3 = X 4Y3Z1, .X4 = X9Y6Z2, .Z4 = X 4 Y 5 Z 6 . (c) Stabilizers for an [11, 5, 3] code . ..................... 52 4.5 Comparison to previous error-correction schemes. Two-qubit flag error correction ( • ) slightly outperforms Shor-style correction (•) for the [5, 1, 3] code, and both Shor- and Steane-style ( ) error correction for the [7, 1, 3] code. For the [15, 7, 3] code, Steane's method performs best. Logical error rates are plotted divided by p 2 to reveal leading-order coefficients, and p, 3p, 4p and 7p, i.e. , error rates without encoding, are plotted to help judge pseudothresholds [SCCA06]. Two-qubit flag error correction for the [8, 3, 3] ( • ) and [10, 4, 3] ( • ) codes can achieve higher pseudo-thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6 Effect of rest errors on [7, 1, 3] code two-qubit flag ( • ) and Steane-style ( ) error correction. Rest error rates from bottom to top: p/ 100 , p/ 10 and p. 4. 7 Overlapping flags can closely localize Z faults. 4.8 Extracting multiple syndromes with a shared flag. 4.9 (a) Distance-three fault-tolerant measurement of X ® 4 . Each CNOT to the data is protected by two flags. X corrections are applied based on the flag pattern. (b) Schematic showing how the circuit extends to X ®w and arbitrary distance d; control and corrections are omitted. Between each consecutive pair of CNOT gates to the data, d - 1 flags are turned on, and d - 1 turned off, in an alternating fashion: 56 56 57 on, off, on, off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.10 An optimized circuit for measuring X ® 10 . Note that the central data CNOT gates are protected by d - 1 flags, but fewer flags are used toward the ends. With appropriate correction rules, the circuit is fault tolerant to distance d = 5. 61 4.11 A syndrome fault can flip d - 1 or d flags. 62 4.12 Syndrome faults spread to the data and flip intervals of flags. The correction algorithm uses the observed flag pattern, which can be further distorted by flag faults, to infer the syndrome faults' approximate locations. . . . . . . . . . . . . . 62 viii 4.13 Correction rules for the syndrome-extraction circuit in Figure 4.9 to bed-FT. 64 4.14 If d = 7, s ES flips six flags in fe and fc+i• . . . . . . . . . . . . . . . . . . . 65 4.15 Pseudocode for searching for correction rules for a given flag circuit for a specific code to bed-FT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.1 Summary of our flag schemes for logical computation. Using two extra qubits, one can apply fault tolerantly either encoded CNOT and Hadamard gates or the full Clifford group. Four extra qubits are enough for fault-tolerant universal computation. 74 5.2 A CZ gadget. The two gadgets in Figure 3. 7 can be combined to catch all two-qubit correlated faults (Theorem 9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3 Invalid CZ gadget constructions. 5.4 A flag gadget that implements CCZ on the black data qubits. 5.5 (a) If CJ is a permutation automorphism for a self-dual CSS code, then applying CZ gates along its cycles fixes the code space (Claim 11). (b) The logical effect for CZ 76 76 gates following the permutation CJ 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.6 The physical CZ gates in (a) have the logical effect of (b). (c) The circuit can be made fault tolerant by replacing the CZ gates with the gadgets from Figure 3. 7 and Figure 5.2, and simplifying. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.7 Blue gates implement the logical gates as in (5.15). Orange and red gadgets catch X faults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1 (a) Circuit to extract the z @n syndrome. (b) Adding a flag makes it fault tolerant. 98 6.2 Fault-tolerant circuits to (a) prepare encoded I+), and (b) measure logical X, for the [5,1, 3] code. In (a) the measurement outcomes should all be trivial, I+) or IO), for the state to be acceptable. In (b), portions of the circuit may be skipped depending on the measurement results .......................... 100 6.3 CSS fault-tolerant preparation of encoded 10 7 ). 6.4 An example rhombic MLSC. (a) Two tessellations of rhombi on a torus. Opposite sides are identical. We use the first tessellation for simplicity, which consists of an even number of hexagon columns . (b) The generator which can generate the whole directed line graph by translation. ( c) Three types of weight-8 stabilizer generators, up to translation, colored in gray, purple and brown. Red and blue edges represent 101 Pauli Y and Z operators, respectively, supported on the corresponding qubits. 109 ix 6.5 Circuit for simultaneous syndrome extraction of all stabilizer generators of the purple or gray type; the case for the brown type is similar. (a) and (b) illustrate, respectively for measuring the purple and gray types of generators, the layout of the relevant data qubits (black), syndrome ancillas (red) and flag ancillas (green and blue), as well as the connectivity between them (brown lines). (c) and (d) describe the detailed circuit schedules for measuring the purple and gray types of generators, respectively. Both use 10 time steps, including state preparations and measurements. For illustration purposes, gates in different time steps are colored black or gray alternately, and the gates for measuring the stabilizer in the middle of (a) or (b) are enclosed by a purple curve. . . . . . . . . . . . . . . . . . . . . . . . 111 7.1 Stephens-Yoder-Kim syndrome extraction, for a distance-three code. Up to two data qubits are coupled to each ancilla. . ....................... 115 X Abstract Quantum computers will need protection from noise. A delicately designed circuit can correct errors in software-even tolerating faults within itself. However, while there have been experimental tests of quantum error-correcting codes, testing fault-tolerance remains a major challenge. A main difficulty is the substantial overhead; many physical "qubits" ( quantum bits) are needed for each encoded, logical qubit. Although noise rates in quantum computing experiments have dropped dramatically, reliable qubits remain precious. This means that on small- and medium-scale systems in the near future, it will be difficult to test fault-tolerance theory, and to explore the efficacy of different fault-tolerance schemes. It is important to reduce the overhead for fault tolerance. We propose a qubit-efficient paradigm for fault-tolerance circuit design, which we term the "flag method." Traditional approaches achieve fault-tolerance by preventing errors from spreading badly. In our work, instead , we add "flags" to catch the faults that can lead to correlated errors on the data. Provided the flag gadgets are carefully designed, the potential correlated errors can be diagnosed by their syndromes, and accordingly be remedied. For various small quantum codes, we provide flag schemes that are especially promising for testing fault tolerance on near-term devices. For example, in a system with 19 qubits total, we can protect and compute universally on seven encoded qubits in a fault-tolerant manner. We also construct flag schemes for asymptotically large quantum codes, showing that the flag paradigm could be of general theoretical interest as well as practical importance. xi Chapter 1 Introduction 1. 1 Motivation and background Quantum computing holds promise for efficiently solving certain computational tasks which are deemed intractable for known classical counterparts, such as factorizing a large RSA integer [Sho97] and simulating a quantum many-body system [Fey82, Llo96]. Quantum computing is also expected to be capable of plumbing fundamental physics, including gravity [Llo05], field theory [Pre18b], entanglement [RUV13, CRSVl 7, CRSV18, CR20] and general probabilistic theories [CRl 7]. These exciting potentials-upheld by the recent evidence, e.g., "quantum supremacy" [AAB+19J or "Bell inequality violation" [HBD+15]- however, still remain theoretical. In essence, the difficulty of engineering a quantum computer lies in its intrinsic vulnerability to unwanted interactions with the environment and inevitable imperfections within the control system. To combat the ubiquitous noises, one has to protect the logical information, embodied by "qubits" (quantum bits), by spreading it onto a highly entangled system, i.e. , a quantum code. A prominent family of codes that has been extensively studied is the stabilizer code [ Got97]. In a stabilizer code, the logical qubits are encoded into a subspace of a larger block of physical qubits, which is a common eigenspace of a set of stabilizer operators. Errors that plague only a few physical qubits will alter the eigenvalues of the logical state with respect to the stabilizers, and 1 therefore can be detected and preferably be further corrected. The effective errors for the logical information are thereby less likely compared with the otherwise unencoded information. However, error detection or correction alone is not sufficient for reliable quantum computation. For one thing, the elementary computational operations can propagate a single-qubit error over to multiple qubits. For another, the procedure of diagnosing the existing errors is faulty itself and may introduce more errors than it removes. In order to faithfully execute the logical computations, both the manipulation and the preservation of the logical information should constantly quarantine the physical errors and remedy them before becoming uncorrectable. This is the rationale why quantum fault tolerance [Sho96] is required. A milestone result in the fault-tolerance theory states that quantum algorithms can be im plemented to arbitrary accuracy provided the noise rates of elementary operations are below a certain constant threshold [ ABOS, Kit97b]. There are largely two main approaches to achieving fault tolerance. The first approach is code concatenation [KL96a], which is the key idea behind the first threshold existence proofs. Namely, one can take a quantum code and encode each of its physical qubits into another code, leading to a larger quantum code and thus stronger protection. Such procedure can be repeated until a desired level of accuracy is achieved. The second approach is topological codes [Kit03, Kit97a], especially the surface codes, which exhibit numerically high thresholds [DKLP02, RH07, FSG09]. In topological codes, physical qubits are arranged on a lattice, and logical qubits are encoded in homological degrees of freedom that are robust to geometrically local errors. When the physical error rates are below the threshold, the logical error rate is suppressed, for either approach, exponentially with the number of physical qubits. As a consequence, the resource overhead required by fault tolerance, in terms of time and qubits, grows only polylogarithmically with the computation size. While large-scale fault-tolerant quantum computation, blessed with the threshold theorem , is in principle possible, there remains a long steep road towards realizing it practically [CTVl 7]. Analytic lower bounds for accuracy thresholds are in general conservative, although they have 2 been gradually boosted from below 10- 6 to above 10- 3 with improved proof techniques and fault-tolerance constructions. Numeric estimates for accuracy thresholds are typically promising. For example, certain optimized error-correction schemes tailored for the surface codes permit thresholds as high as several percent [WL12, TBFB19], which seem to be within the reach of infidelities on state-of-the-art quantum chips [WBD+19, IBM]. However, the optimistic threshold values can be delusive. Most numerical simulations are limited to ideal or oversimplified error models for the sake of efficiency. It is therefore difficult to evaluate the efficacy of fault-tolerance schemes in the presence of realistic noises. As with any scientific theory, fault tolerance has to be empirically tested and validated, even before a quantum computer can ever be built. P erhaps surprisingly, quantum fault tolerance, advocated for more than two decades, has hardly been demonstrated in experiments. A major hurdle is the substantial overhead: standard fault-tolerance schemes use seven or more physical qubits to encode each logical qubit, with still more qubits devoted to fault-tolerant error correction or computation. Even worse, the overheads will multiply when codes are concatenated for higher reliability. Besides concatenated codes, one may also resort to the surface codes, which require only nearest-neighbor qubit interactions on a planar square lattice and are more amenable to near-term hardware. However, when it comes to running a practical algorithm- whether it be factorizing 2048-bit RSA integers [GE19] or simulating jellium with 1024 spin orbitals [BGB+1s]- using a device with physical error rates of one part in a thousand, thousands of physical qubits may need to be consumed to encode each logical qubit. Given the difficulty of manufactoring a large amount of qubits with high quality, it seems a reasonable goal for the near future to test fault tolerance on small quantum devices, e.g., with tens of physical qubits. There have been, actually, implementations of error correction or detection using small stabilizer codes, e.g., the three-qubit repetition code [CPM+9s, RPH+15], the four-qubit surface code [CMS+15J and the seven-qubit Steane's code [NMM+ 14]. However, these protocols are not fault tolerant in the sense that a single gate failure can propagate badly and result in 3 multiple data errors. Recently, Gottesman [Got16] has discussed comprehensively the criteria for demonstrating fault tolerance in small experiments, and suggested that the [4, 2, 2] code, which encodes two logical qubits in four physical qubits, can be implemented fault-tolerantly with an extra, fifth qubit. Limited fault tolerance based on the [4, 2, 2] code has been subsequently demonstrated in error detection [LGL +17, Vui18], logical state preparation [TCC+17] and computation [HF19] schemes using superconducting or trapped-ion qubits. Testing fault tolerance is a daunting task, not only because reliable qubits are hard to engineer, but also because the criteria for fault tolerance is quite stringent and tricky to verify. However, such task should be beneficial or even necessary. Fault-tolerance experiments on small- and medium-scale quantum devices will enable the designers to assess and validate their schemes, and to adapt to realistic noises. The fault-tolerance theory- so far largely based on simplifying speculations-needs good tests to stand on firmer ground. It is therefore compelling to develop systematic methods for general qubit-efficient fault tolerance and, more importantly, for optimizing schemes tailored for small codes. In this thesis, we will address the central problem of reducing the fault-tolerance overhead required for near-term tests, and supply extensible solutions. 1.2 Main results and thesis outline Our key result is a qubit-efficient paradigm for fault-tolerance circuit design, which we term the "flag" method. We apply the flag paradigm to various small quantum codes and devise fault-tolerance schemes that can be experimented with fewer than twenty qubits, thereby raising the possibility of testing fault tolerance on near-future devices. (See Figure 1.1 for some examples.) We meantime construct flag schemes for asymptotically large quantum codes, showcasing that the flag paradigm could be of general theoretical interests as well as practical importance. 4 Logical qubits Code qubits Ancilla qubits 0 ------+ Y)Y)O +00 o 0 o ------+ 0000 +00 0000 00000 Clifford gates ~ o 0 o 080 ------+ 00000+00()() 00000 ~ Universal gate 8et Figure 1.1: Examples of flag-based fault-tolerant schemes. One can fault-tolerantly error-correct one or three logical qubits, respectively using the [5, 1, 3] or [8, 3, 3] code, with no more than ten physical qubits in total. With two extra qubits, one can protect and apply the full Clifford group over the seven logical qubits encoded in the [15, 7, 3] code; four extra qubits are enough for fault-tolerant universal computation. F lag paradigm for quantum fault tolerance The main problem with fault-tolerant quantum computing is that single faults can spread badly through the circuit. Transversality- the conventional approach to fault tolerance-prevents such spread by isolating qubits into certain small groups so that qubit interactions restricted within individual groups maintain the protection from the quantum code. By contrast, bad spread is allowed in our flag paradigm- the point is that it can be detected and timely corrected. Specifically, given a non-fault-tolerant circuit, we add flag gadgets- which contain extra flag qubits- to those circuit locations where malignant faults could happen. When no fault occurs, the measurement outcomes of the flag qubits are trivial, and the flag gadgets do not alter the effect of the original circuit. When a malignant fault does occur, it will be caught by some flag gadgets and trigger the alert- the outcomes of the flag measurements will be nontrivial. Although errors may have spread to multiple data qubits that are beyond the code's remedy, provided that the flag gadgets were carefully designed, we should be able to deduce the existing data errors from the observed flag pattern or possibly subsequent syndrome-extraction procedure. As long as these errors are 5 corrected before further propagating badly, the flag circuit will remain fault-tolerant. In a nutshell, the flag method uses flag gadgets to catch bad errors. We develop two general types of flag gadgets. The first type is for measuring Pauli operators supported on data qubits. This process typically involves coupling the relevant data qubits to certain ancilla qubits, on which the measurement outcomes reveal the eigenvalues of the P aulis. The Paulis measured can be either stabilizers or logical Pauli operators, as in circumstances of error correction and detection, or logical state preparation and measurement. In these cases, flag gadgets detect those faults on the ancillas that can propagate to the data. The second type is for protecting multi-qubit gates that act on the data. Such gates constitute many useful circuits that implement logical computations without using ancillas. In this case, flag gadgets detect those faults that are supported on multiple data qubits and can propagate within individual code blocks. Fault-tolerant error correction with two extra qubits Limited fault-tolerance schemes have been tested on 5-qubit systems, using the [4, 2, 2] code. Since the code has distance two, it can only detect an error, not correct it. Until recently, the smallest known scheme that can correct an error used the [9, 1, 3] Bacon-Shor code, plus a tenth extra qubit. Although smaller, more efficient error-correcting codes are known, such as the [5, 1, 3] perfect code (the smallest distance-three code), fault-tolerance schemes using these codes have still required at least ten qubits. For example, Shor-style syndrome extraction [Sho96, DA07] requires w + 1 or w ancilla qubits, where w is the largest weight of a stabilizer generator. Steane-style error correction [Ste97, Ste02] for Calderbank-Shor-Steane codes [Ste97, Ste02] uses at least a full code block of extra qubits. Knill's scheme [Kni05b] uses an encoded EPR state and thus at least two extra code blocks. Stephens [Ste14] has proposed that for codes with at most weight-eight stabilizer generators, four extra qubits are enough to fault-tolerantly extract the syndrome. Yoder and Kim [YKl 7] have given fault-tolerance schemes using the [5, 1, 3] code with eight qubits total, and the [7, 1, 3] 6 Steane code with nine qubits total. Extending the latter construction, we develop fault-tolerant error-correction procedures for various common dist ance-three codes that use only two extra qubits, based on the flag paradigm explained above. In particular, with the [5, 1, 3] code our scheme uses only seven qubits total, or ten qubits with the [8, 3, 3] code. A particularly promising application is to the [15, 7, 3] Hamming code: 17 physical qubits suffice to protect seven encoded qubits. Fault-tolerant computation with two or four extra qubits Codes storing multiple qubits have higher rates [CS96], but too large codes tend to tolerate less noise since initializing codewords gets difficult [Ste03]. A key obstacle for using any code with multiple qubits per code block is that it is complicated and inefficient to address the individual encoded qubits to compute on them [Got98b, S105]. For example, to apply CNOT or T gates on logical qubits in a code block, the optimized methods, respectively in [Got98b] and [BZH+ 15], require a full ancillary code block, with no stored data, into which the target logical qubit is transferred temporarily. We apply the low-overhead flag method to compute fault tolerantly on multiple data qubits in codes of distance two or three. 1. For even n, the [n, n - 2, 2] code encodes n - 2 logical qubits into n physical qubits, protected to distance two. We show that with two more qubits, encoded CNOT and Hadamard gates can be applied fault tolerantly. For n ?: 6, four extra qubits suffice to fault-tolerantly apply an encoded CCZ gate, for universality. 2. For better, distance-three protection, we encode seven qubits into 15, and give fault-tolerant circuits for the encoded Clifford group using two more qubits, and for a universal gate set with four extra qubits (19 total). 7 Combined with the two-qubit flag fault-tolerant error-correction schemes, this means that substantial quantum calculations can be implemented fault tolerantly in a quantum device with fewer than 20 physical qubits. In order to compute on data encoded within a single code block, we need to apply two- or three-qubit gates. The particular circuits use symmetries of the codes or a more general round-robin construction from [YTC16]. To render these circuits fault-tolerant, we replace each gate with a flag gadget involving two to four extra qubits. Faults that are supported on multiple qubits can be detected by the flags, and can be corrected for later. The flag gadgets cannot prevent the gates from spreading single-qubit faults into problematic multi-qubit errors. To avoid this problem, we design the circuits carefully, and in some cases intersperse partial error correction procedures between gadgets, an idea from [KLZ96] recently applied and extended by [HFWH13, YTC16]. Sometimes error correction even needs to overlap the gadgets. Fault-tolerant error correction for arbitrary stabilizer codes Chamberland and Beverland [CB18] have formalized the flag idea for error correction and extended it to arbitrary-distance codes. For a general code, they have proposed sufficient conditions on flag syndrome-extraction circuits which can be used to construct a fault-tolerant error-correction protocol. They provide example circuits that satisfy the conditions for several families of codes with asymptotically large distance. However, given syndrome-extraction circuits for a general code, it can be tedious to verify these conditions. It is a priori unknown if a flag-based scheme exists. We provide a flag error-correction scheme that applies to any stabilizer code, unconditionally. Our scheme does not necessarily satisfy the conditions in [CB18]. In particular, our circuit construction relies only on the code's distance and stabilizer generator weights. The key idea is that harmful faults can be approximately located from the observed flag pattern and then corrected right away, before they propagate to correlated data errors. For a distance-d code with stabilizer 8 generators of maximum weight w, the scheme consumes min{d + 1, 2w + 2} extra qubits, provided that qubits can be reset rapidly, in time comparable to a gate operation. Thesis outline Chapter 2 briefly introduces some basic notions that will be used throughout this thesis. Crucial to understanding technical details are the stabilizer formalism and the fault-tolerance criteria, of which we recommend [Got98b, GotlO] for rigorous and complete expositions. Chapter 3 formally presents a comparative study between the fault-tolerance paradigms of transversality and flag. We illustrate these paradigms by elaborating several fault-tolerance constructions for error correction and logical computation. Chapter 4 is focused on flag error-correction schemes that are applicable to certain distance-three codes and arbitrary codes. Material has been presented in [CR18b] and [CR19]. Chapter 5 is focused on flag computation schemes for [n, n - 2, 2] codes and the [15, 7, 3] code. Material has been presented in [CR18a]. Chapter 6 augments the utility of the flag paradigm with schemes for error detection, logical state preparation and measurement for various common codes; these schemes have been presented in [CR18b]. We also provide a flag error-correction scheme for a specific instantiation of the Majorana loop stabilizer codes, which have recently been proposed for efficient simulations of geometrically local fermionic systems [JMBN19]. Chapter 7 gives a fault-tolerant error-correction protocol that applies to arbitrary distance-three codes and measures each ancilla qubit only once at the end of individual syndrome-extraction circuits. This scheme is particularly advantageous for certain realistic scenario where the time for qubit preparations and measurements is much longer than the time for gates. This is in contrast with typical flag schemes which require frequent resets of the flag ancillas. Our scheme extends the DiVincenzo-Aliferis decoding method [DA07] and has been presented in [CR18b]. 9 1.3 Related works and outlook The first explicit use of the flag idea, as far as we know, is by Yoder and Kirn [YKl 7]. Specifically, they measure certain weight-four stabilizer generators of the triangle code each using two ancillas-one revealing the syndrome bit, the other signaling the "hook" error-in a way analogous to our flag gadget depicted in Figure 3.5. Effectively, this can be regarded as generalizing the DiVincenzo-Aliferis decoding method [DA07] by encoding and decoding two-qubit cat states. (Similar idea can also be found in [Ste14] with four-qubit cat states.) Yoder and Kim also provide syndrome-extraction circuits for the [5, 1, 3] and [7, 1, 3] codes using respectively 3 and 2 ancilla qubits. They show that repeated ancilla measurements using these circuits extract sufficient information for fault-tolerant decodings. Extending the constructions in [YKl 7], we systematically introduce the flag method in [CR18b] and [CR18a]. Specifically, we give flag-based schemes for [n, n - 2, 2] codes and several distance three codes, including Hamming codes [2r - 1, 2r - 1 - 2r, 3]. The schemes include those for error detection, logical state preparation and measurement, error correction and computation. All these schemes use only two ancilla qubits, except for those for universal computation requiring four ancillas. In particular, our computation schemes leverage the round-robin construction from [YTC16] and pieceable fault tolerance applied in [KLZ96, HFWH13, YTC16]. Chamberland and Beverland [CB18] further extend the flag idea and provide fault-tolerance criteria for flag-based error-correction protocols for arbitrary-distance codes. In particular, they construct flag circuits using at most four ancillas for code families with arbitrary distance, including rotated surface codes, Reed-Muller codes and hexagonal color codes. Tansuwannont et al. [TCL20] provide flag circuits using four ancillas for measuring logical Pauli operators (including stabilizers) for CSS codes constructed from classical cyclic codes, which can be used for error correction and implementation of logical Clifford operations. 10 One of the drawbacks of typical flag error-correction schemes is the large circuit depth, i.e. , extracting only one syndrome bit at a time. In [Rei18], Reichardt shows that stabilizer generators of Steane's code can be measured in parallel, e.g., three at a time, with three syndrome ancillas used simultaneously as flag ancillas. Furthermore, he shows that two blocks of Steane's code, among other codes, can be error-corrected with no extra qubits. All these schemes conform to planar geometry constraints, i.e., nearest-neighbor interactions. Extending [YKl 7, CR18b, Rei18], Lao and Almudever develop an efficient flag-bridge technique for mapping small flag error-correction circuits onto processors with designated qubit connectivities. Using an error-correction procedure in [Rei18] as subroutines, Chamberland and Cross [CC19] propose two protocols for fault-tolerantly preparing a logical magic state in Steane's code using at most three flag ancillas. In these protocols, when a single fault results in more than one data error, either the protocol is rejected and starts anew ( error detection), or the syndrome is measured to diagnose the correlated errors (error correction). Shi et al. [SCC19] develop a flag-based phase estimation protocol that can be used for preparing Gottesman-Kitaev-Preskill states. An important avenue of applications of the flag idea is for topological codes. Baireuther et al. [BCC+ 19] consider color codes with small distance, and allocate to each plaquette a syndrome ancilla along with a flag ancilla. They show numerically that flag measurement outcomes can be incorporated into a neural network decoder to achieve the full code distance. Chamberland et al. [CZY+20] introduce the topological subsystem heavy-hexagon and subspace heavy-square codes. They construct efficient and scalable decoders for these codes by renormalizing the edge weights of the decoding graph based on the flag measurements. Using a similar idea, Chamberland et al. [CKYZ20] embed the triangular color code along with syndrome and flag ancillas into trivalent connectivity graphs, and maintain the effective code distance using a flag-based decoder. Chamberland and Noh [CN20] further give a fault-tolerant scheme for preparing logical magic state using the triangular color code. They introduce the technique of redundant ancilla encoding, which, 11 combined with flag ancillas, enables measurements of both the stabilizers and logical operators with a same qubit connectivity. Experimentally, a flag scheme for logical state preparation using the [4, 2, 2] error-detecting code has been realized on a superconducting qubit system [Vui18]. Extensive numerical simulations have been performed under realistic error models of trapped-ion qubits for flag schemes for lattice surgery-based logical CNOT implementation [GMB19] and error correction and logical state preparation [BXG+19], all using Steane's code. In the above mentioned references, most flag schemes, especially those for error correction, greatly rely on the underlying codes. Namely, one needs to design the flag circuits carefully such that possible flagged errors are distinguishable by their syndromes. Thus for a general code, it is a priori unknown if a flag scheme even exists for a specific task. In [CR19], we construct a flag error-correction scheme for an arbitrary distance-d code using min { d + l , 2w + 2} ancillas where w is the maximum weight of a stabilizer generator. In this sense, the flag paradigm applies to arbitrary codes at least in term of error correction. Despite the plethora of applications as mentioned above, we believe there remains much to be explored about the flag paradigm. First, it is desirable to develop systematic methods for constructing flag schemes subject to various constraints- including number of ancillas, circuit depth, qubit connectivity, time and error rates of individual operations and etc.- and to examine the trade-offs between them. Second, apart from CZ and CCZ gates that compose the round-robin circuits used in [CR18a], it would be interesting to design flag gadgets for other physical gates that are useful for logical computation. More generally, it might be possible to incorporate the flag paradigm to other known approaches to logical gate synthesis, e.g., the Logical Clifford Synthesis algorithm that applies to arbitrary stabilizer codes [RCPK18]. Third, in the realm of error correction, it might be useful to develop a general formalism that unifies the roles of syndrome and flag ancillas. An example is [Rei18] where syndrome and flag 12 ancillas are utilized interchangeably. An appropriate formalism could be conducive for developing novel flag circuits for parallel syndrome extractions using high-distance codes, e.g., topological codes or general CSS codes. In the main body of the thesis, we will explain in more details the results in [CR18b, CR18a, CR19] and some ongoing works. Individual chapters or sections, when relevant, are concluded with discussions about more specific open problems. 13 Chapter 2 Preliminaries This chapter briefly summarizes some basic notions that are used throughout the thesis. We refer the reader to the textbook [ NCOO] for a comprehensive overview of the field of quantum computing. To facilitate understanding later technical details, we elaborate the stabilizer formalism and specific fault-tolerance criteria. We recommend [Got98b, GotlO] for rigorous and complete expositions. 2.1 States and gates A bit is a classical system with two perfectly distinguishable states {O, 1}. In probability theory, the state of a bit is a vector (a,m =a (l, 0) +;3 (0, 1) a, ;3 E [O , 1] a+ ;3 = 1 , (2.1) namely, being O with probability a and being 1 otherwise. 14 A qubit is a quantum system with two perfectly distinguishable states {I O), 1 1)}. In quantum mechanics, a pure state of a qubit is a unit vector in Hilbert space C 2 , represented in a ket I·) symbol, l'P) ~ ( : ) ~"IO ) HI! ) a,(3 E (C lal2 + 1/312 = 1 ' (2.2) by the Born rule, being I O ) with probability lal 2 and being 1 1) otherwise. Likewise, an n-qubit pure state is a unit vector in the n-fold tensor product ( C 2 ) ®n . For example, when n = 2 17P) = (a , (3,,y, st= alO) ®IO )+ /310) ® 11) + 111) ®IO )+ oil) ® 1 1) (2.3) Normally the tensor product notation can be omitted in appropriate context, e.g., writing I O )® I O ) as I OO). A state 17P) is a product state if one can write 17P) = l1P1)l1P2) for some l1P1) and l1P2); otherwise 17P) is a entangled state. One can expand an n-qubit pure state over an orthonormal basis other than { Ix), x E {0, 1 }n }, for example j = 0, ... , 2n - 1 . (2.4) By convention, { lx),x E {0, l}n} is referred to as the computational basis, and (2.4) is referred to as the Fourier basis. Incorporating classical uncertainty, an n-qubit state can generally be a mixed state (2.5) 15 that is, a probabilistic mixture of an ensemble of countably many n-qubit pure states. Here ('IJ'!I stands for the conjugate transpose of l'IJ'!), and ('IJ'!l'IJ'!) is short for ('IJ'!ll'IJ'!) . We call p a density matrix- a positive semi-definite matrix p = pt , with trace one Tr[p] = 1. One can perform a measurement on a state p with respect to an orthonormal basis { l'IJ'!i) } in the same Hilbert space, and obtain an outcome i with probability determined by (2.6) A reversible transformation, or gate U, on n qubits is a 2n x 2n unitary matrix uut = I Some common single-qubit gates are H = ✓ 'i (l 1 ) (Hadamard gate) 1 - 1 Z = (l O ) (phase-flip) 0 - 1 S ~ (: : ) (ph= gate) X ~ (: : ) (bit-flip) ( 0 -i) Y = iXZ = i O ( 1 0 ) T= . 0 e 2;i In particular, X, Z , Y along with the 2 x 2 identity gate I are called Pauli matrices. Note that z = IO )(O I - 1 1)(11 X = 1+)(+1-1-)(-1 H = l+)(O I + 1-)(11 I+) := (IO)+ ll ))/ v2 1-) := (IO ) - ll ))/ v2 . 16 (2.7) (2.8) (2.9) Figure 2.1: A circuit that first prepares a qubit in state I 0), then applies gates H, Zand st, and finally measures in the X basis. The computational basis {I 0), 1 1)} is also referred to as the Z basis, and the Fourier basis {I+), 1-)} as the Hadamard or X basis. One can depict a circuit that consists of state preparations, gates and measurements in a diagram that proceeds from left to right. See Figure 2.1 for an example. In particular, ket symbols before qubit wires stand for state preparations, and+/- or 0/ 1 symbols after qubit wires stand for qubit measurements in the X and Z bases, respectively. Some common two-qubit gates, along with their circuit symbols, are 1 0 0 0 =t==¼ 0 1 0 0 c N0Ti1 = I 0)(0 li ® 1 1 + 1 1)(lli ® x 1 = ( controlled-X) 0 0 0 1 0 0 1 0 1 0 0 0 X=¼ 0 1 0 0 czi1 = I 0)(0 I; ® 1 1 + 1 1)(l li ® z 1 = ( controlled-Z) 0 0 1 0 0 0 0 - 1 (2.10) In words, a CNOTij gate applies X (NOT) to the target qubit j if the control qubit i is in state I 0), and applies nothing if the control is in 1 1). One can similarly interpret CZ gate and define controlled-Y or CY gate. Note that CZ gate is symmetric- the roles of the control and target qubits do not matter. A general controlled unitary is also a gate, and can be depicted by dot symbols on the controlled wires joined to the unitary on the target wires. 17 Some common three-qubit gates, along with their circuit symbols, are Toffoli = (I -1 11)( 111 ) ® I + 1 11)( 111 ® X (controlled-controlled-X) CCZ = (I - 1 11)( 111 ) ® I + 1 11)( 111 ® Z (cont rolled-controlled-Z) . (2.11) Note t hat CCZ is symmetric over all the three qubits. A finite set of gates on a Hilbert space 1{, which is closed under inversion, is called universal if for any unitary U on 1{ and E > 0, there exist s a finite gate sequence V = Vi V 2 • • • VN from the set , such that IIU- VII :c:;e , (2.12) where II · II is the spectral norm. For any universal gate set, the Solovay-Kitaev theorem [DN06] permits that N = O(logc c 1 ) for some const ant c. 1 Namely, any unitary can be approximated efficiently. Examples of universal gate set s are {Hi , Ti, CNOTi 1 } [Kit97b] {Hi, CCZijk} [Shi03, Aha03] (2.13) A general, potentially nonreversible transformation£ of a quantum state p can be written in the Krauss representation K E(p) = LEkpEk (2.14) k= l 1 The approximation complexity N in general scales polynomially with dim H. However, for most practical cases dim H can be viewed as a const a nt. 18 We also call £ a quantum channel, which is a completely positive, trace-preserving linear map [Cho75]. Note that the density matrices E(p) and p may have different dimensions. 2.2 Stabilizer formalism Any error, a physical evolution itself, can be modeled as a quantum channel. Throughout the thesis we only consider error channels that map a system to itself. Suppose an error channel £ with Krauss operators {Ek} acts on the Hilbert space 1-l. A code C is a subspace of 1-l, and C is a good code for E if there exists a recovery channel R such that R O £( 1'1f;)('1f;I) ex 1'1f;)('1f;I Vl'1f;) E C . (2.15) Let P be the projector on C. The Knill-Laflamme condition [KL96b] says that C is a good code for £ if and only if Vi, j , (2.16) where a is a density matrix. Let D be an error channel with Krauss operators { Di} such that Di E Span{Ek}, where Span is taken over C. One can verify that if C is a good code for£, then C is also a good code for D and the same recovery channel works for both error channels. Suppose£ acts on n qubits, i.e. , 1-l = (C)® n_ Define the n-qubit Pauli group Pn as n Pn = { ia Qs) Pj I a E {O, 1, 2, 3}, Pj E {I, X, Y, Z}} , j=l (2.17) where Pj is a P auli matrix acting on the j-th qubit. Whenever n is clear from the context, we refer to elements in Pn with a = 0 as Pauli operators or simply Paulis. The support of a Pauli operator is the subset of qubits on which it acts nontrivially, and the weight of a Pauli is the size of its support. 19 A channel with all Krauss operators being Paulis is called a Pauli channel. A popular Pauli channel is the n-qubit depolarizing channel Ep(p) = (1 - p) I + _P_ ~ E pE , 4n - 1 L...., EEP,,/ {±1,±i} (2.18) Ef-I which is parametrized by p. For a general error channel £ with Krauss operators {Ek}, define Qc = { j I Ek acts nontrivially on qubit j for some k} ~ [n] (2.19) Pc = {P E Pn / {±1, ±i} I support(P) ~ Qc} . Consider a Pauli channel £' with Krauss operators being exactly (proportional to) Pc. Since every Ek E Span Pc, any good code for£' is also good for£. In practice, it is typically infeasible to assume perfect knowledge of the error channel at hand. Even if { Ek} are always perfectly known, it seems that one has to devise a tailor-made good code for every given error channel. Luckily, the above argument provides a workaround. A code that corrects finite discrete Pauli errors can correct infinitely many continuous error operators. The stabilizer formalism is a powerful framework for constructing good codes for Pauli errors the stabilizer codes. For a given n-qubit system 1i = (C 2 )®n, a stabilizer code C is defined by a subgroup S :s; Pn c = { 11/i) I S11/J) = 11/i) E 1i, vs E S} . (2.20) Note that a nontrivial C entails S to be Abelian and contain only Paulis with phase ± 1. Stabilizers in S can be generated by a set of (independent) stabilizer generators (2.21) 20 Since stabilizers have eigenvalues ±1, the projector onto C is given by n-k IT I ~ Si = 2k-n L S i=l SES (2.22) One can verify that dimC = 2k . (2.23) Namely, a stabilizer code C on n physical qubits with n - k stabilizer generators encodes k logical qubits. We may denote C by [n, k]. In particular, when k = 0, the only state in C is called a stabilizer state. A code with stabilizers generated only by X-type Paulis (i.e., tensor products of I and X) and Z-type Paulis is called a Calderbank-Shor-Steane (CSS) code [CS96, Ste96a, Ste96b]. In particular, a CSS code can be defined by two classical binary linear codes C 1 and C 2 , whose parity check matrices represent respectively the Z- and X-type stabilizer generators, and which satisfy Cr ~ C2. A CSS code is self-dual if C 1 = C2. Denote by N(S) the set of members in Pn with phase ±1 that commute with every stabilizer, namely, the normalizer of Sin Pn up to phases. One can find a set of operators X 1 , Z 1 ,j = 1, 2, ... , k, such that j =/- l, P, Q E {X, Z} . (2.24) One can further verify that k N(S) = { IT Pj Ip E {I, X, Y, Z}}. s ) (2.25) j=l where Yj = iXjzj and Jj is simply the identity operator. We also call N(S) the set of logical Pauli operators. Indeed, operators in N(S) satisfy the same commutation and anti-commutation 21 relations as their corresponding k-qubit Paulis. In addition, operators in a same coset s · S have identical effect when restricted to C. For any x E {O, 1 }k, there exists a unique state Ix) such that i=l,2, ... ,k. (2.26) One can verify that {Ix), x E { 0, 1 }k} constitutes an orthonormal logical basis of C. In fact, this specific basis is the computational basis of the k logical qubits with respect to { .Zi}~=l · One may write, for example, .X2 I001) = IO+ 1), where .X2 serves as the Pauli X operator on logical qubit 2. For any k-qubit unitary U, there exists a unique decomposition U= L Tr[PU]P /2k PE?''k/{±1,±i} The logical gates which have effect U on C are therefore given by U = L Tr[PU]P /2k PEA/ {±1,±i} j5 E PS (2.27) (2.28) Note that U commutes with S. Furthermore, any EE S acts trivially on the encoded qubits, and any EE N(S) \ S incurs a nontrivial Pauli error to the encoded qubits . Let a set of stabilizer generators be fixed: S = (S1 , ... , Sn-k)- The syndromes E {O, 1 }n-k of a Pauli error E is defined by Si = {O if SiE = ESi 1 if SiE = -ESi (2.29) The syndrome bits; is nontrivial if and only if E anti-commutes with S;. Hence any E rf. N(S) has nontrivial syndrome and can be detected. 22 The distance d of a stabilizer code C is defined as d = min weight(E) . E EN(S )\S (2.30) We may denote C by [n, k, d] . One can verify that the set of Paulis with weights at most t = l(d - 1)/ 2J satisfies the Knill-Laflamme condition (2.16) , and thus can be corrected. Indeed, any pair of nontrivial Pauli errors with weights no more than t have distinct nontrivial syndromes. Codes with d = 2 can only detect weight one errors, and are called error-detecting codes. Codes with d :::,: 3 can correct any errors with weight at most t, and are called error-correcting codes. The Schri:idinger picture of a quantum evolution is to keep track of the quantum state. The philosophy of the stabilizer algebra is to take the Heisenberg picture and keep track of the operators. For example, a stabilizer state 17P) is fully characterized by its st abilizers (2.31) Applying a gate U to 17P) results in the state Ul1P) which is stabilized by operators (2.32) We will focus on those gates U such that Ul 1P) is still a stabilizer state, in which case (2.32) remain Paulis with phase ± 1. The n-qubit Clifford group Cn is defined as (2.33) It can be shown that (2.34) 23 1 2 3 4 5 6 11P) ~ +/-~a l+)~!ED~ 0/1 b IO) ED X z (a) Time step 1 2 3 4 5 6 Logical X1 X1 X12 ~ X13 X13 ~ aX3 aX3 X 3 operators Z1 Z1 Z1 ~ Z23 Z23 ~ bZ3 Z3 Z3 Stabilizers X2 , Z3 X23 , Z23 X23, Z123 aX1 , bZ2 aX1 , bZ2 aX1 , bZ2 (b) Figure 2.2: (a) A Clifford circuit that teleports 17P) from qubit 1 to qubit 3 in six time steps. Measurements of X 1 and Z2 yield outcomes a, b E {1 , - 1 }, respectively. Classical control then applies Z3 or X 3 , conditioned on a orb, respectively, being nontrivial - 1. (b) tracks the stabilizers step by step. Initially, the stabilizer of 17P) is an unknown reflection but belongs to the algebra generated by X 1 and Z1. Therefore, to track 17P), it suffices to track X 1 and Z1, which we refer to as "logical operators" with abuse of notation. In step 3, the logical X, X 12 , is taken to be the equivalent X 13 , modulo a current st abilizer X 23. Doing this allows us to avoid collapsing the logical state when measured by Z2 in step 4, since Z2 anti-commutes with X 12 . and a Clifford gate conjugates a stabilizer to a (possibly new) stabilizer. A circuit is called Clifford circuit if it consists solely of 1) state I O ) preparations, 2) Clifford gates and 3) Z-basis measurements. The Gottesman-Knill theorem [Got98a] states that a Clifford circuit can be simulated classically in polynomial time, and the computational model of Clifford circuits is strictly weaker than quantum universality [AG04]. However, adding any non-Clifford gate, example being CCZ or T gate, will achieve universality [NRS , NRSOl]. Simulating a Clifford circuit amounts to "pulling" the stabilizers, initially specified by the Pauli basis preparations, through Clifford gates and finally Pauli basis measurements. Figure 2.2 demonstrates the teleportation of a qubit state 17P), which uses a Clifford circuit and can be described in term of stabilizer algebra. In this thesis, we will extensively use the stabilizer formalism to analyze fault-tolerance properties. That is, we will track how Pauli circuit errors propagate through an error-correction or logical computation circuit by pulling them through Clifford or even non-Clifford gates. We will 24 also use the stabilizer formalism to determine the logical effect of a sequence of physical gates, Clifford or non-Clifford, upon the encoded qubits of a stabilizer code. This amounts to checking how the physical operations conjugate the logical Pauli operators. 2.3 Fault-tolerance criteria Quantum error correction is an elegant theory that dictates how to protect logical qubits from general errors, and how to perform logical operations. However, it is insufficient for reliable quantum computation. The error correction procedure itself is faulty; one has to make sure that it does not incur more errors than it fixes. Logical operations can spread errors badly; for example, a constituent CNOT gate propagates an X error on the control into X errors on both the control and target, beyond what a distance-three stabilizer code can correct. In a broad sense, a protocol using a quantum code is fault-tolerant if it retains the code's protection throughout the process. A viable model for realizing fault-tolerance is encoded simulation. Recall that a circuit consists of elementary operations, including state preparations, gates and qubit measurements. This physical circuit can be simulated by an encoded circuit, for example, by encoding physical qubits into the logical qubits of a quantum error-correcting code, replacing physical operations with gadgets that perform the same operations on the encoded qubits, and intersperse error-correction gadgets between gadgets of operations. The gadgets consist of physical operations, which can be faulty, and in some cases classical controls and computations, which are faultless. In most scenarios, including this thesis, the time required for classical computations is ignored. The goal of fault tolerance is that the noisy encoded circuit faithfully simulates the behavior of the ideal physical circuit where operations are perfect. The exact criteria for fault tolerance depend, inevitably, on the physical error model of the simulation circuit, which largely falls into a dichotomy of being coherent or stochastic. Coherent errors are characterized by unitaries; they are more realistic, but difficult to simulate classically. 25 Stochastic errors are irreversible and have multiple Krauss operators; they sometimes approximate well, and are more tractable to analyze. Fault tolerance has been explored for both regimes. One of the most general models considered allows operations to correlate spatially and temporally, and to coherently interact with a non-Markovian environment [TB05, AKP06, Pre13]. A less general model relaxes the correlations to occur stochastically and to decay exponentially with the number of faulty operations [KLZ98, ABOS, AGP06]. However, uncorrelated error models are de facto adopted by most fault-tolerance arguments, i.e., each operation undergoes an error channel independently. In particular, independent Pauli channels make possible large-scale simulations of fault-tolerance schemes, owing mainly to the stabilizer formalism. Increasing efforts have recently been made towards combating practical coherent errors in various specific scenarios [DPl 7, BEKP18, HDF19, DLNB18]. Other physical considerations include qubit leakage and loss [AT07], geometric connectivity constraints [GotO0], biased noise [AP08], to name a few. In this thesis, we assume the uncorrelated stochastic Pauli error model [Kni05a] with all-to-all qubit connectivity. Specifically, the circuit is sliced into time steps, each of which contains non overlapping operations. Each state preparation, gate, and idle qubit in a time step, is followed by a random Pauli operator supported on the qubit(s) that the operation acts on. Each qubit measurement has its outcome flipped with certain probability. We denote by physical error rate the maximum probability of an individual operation being faulty, and by logical error rate the failure probability of the logical simulation under such error model. Given a fixed physical error model, the exact criteria for fault tolerance further depend on the scope of the physical circuit that one wants to simulate. In one scenario, one may want to be able to perform large-scale universal computations to arbitrary accuracy; a desirable guarantee is that he can do this so long as the physical error rate of his quantum hardware is below a certain constant threshold, regardless of the simulated circuit. In another, one may only care about some small circuit or family of circuits for a restricted usage; a pseudothreshold [SCCA06] of the physical error rate would suffice, below which he can obtain a comparatively lower logical error rate. 26 A conceptually simple criterion for a threshold result is the extended rectangle ( exRec) formalism by Aliferis, Gottesman and Preskill (AGP) [AGP06], which we briefly outline as follows assuming the stochastic Pauli error model. Let a stabilizer code [n, 1, d] be fixed and t = l d 2 1 J 2: 1. A location is an operation (state preparation, gate, qubit measurement) or a resting qubit in a time step. An error is an unwanted nontrivial Pauli on a physical qubit, and a fault is the nontrivial Pauli error( s) affiicting a faulty location. A gadget for an operation is a circuit that, when faultless, performs the corresponding operation to the logical state; a gadget for an idle qubit in a time step is trivially identity gate. An error-correction gadget extracts the syndrome by measuring the stabilizer generators and then performs Pauli corrections; when faultless, it removes up tot errors. Definition 1 (fault-tolerance criteria for threshold [AGP06]). Given the notions defined above, a gadget is fault-tolerant if • A preparation gadget with s faults prepares the correct logical state and leaves with at most s output errors, when s :c; t. • A measurement gadget with r input errors and s faults generates the correct probability distribution of classical outcomes, when r + s :c; t. • A gate gadget with r input errors and s faults performs the correct logical gate and leaves with at most r + s output errors, when r + s :c; t. • An error-correction gadget with r input errors ands faults 1. leaves with at most t output errors, when r + s :c; t, and 2. leaves with a state at most s output errors away from the code space, when s :c; t. A rectangle for a location is a circuit consisting of the gadget of the location followed by a trailing error-correction gadget (which is absent for a measurement). An exRec for a location is a rectangle for that location preceded by a leading error-correction gadget ( which is absent for a preparation). An exRec is good if it contains no more than t faults. An ideal decoder is a faultless 27 circuit that first performs error correction on a code block and then maps the logical state to the corresponding physical qubit state. An exRec for an operation, when followed by an ideal decoder, is correct, if it is equivalent to the leading error-correction gadget (if any) followed by an ideal decoder and subsequently the ideal operation, regardless of the input to the exRec. Fact 2. A good exRec consisting of fault-tolerant gadgets is correct. That the leading error-correction gadget satisfies the condition 2 of Definition 1 is crucial to the independence of the input in the definition of a correct exRec. Roughly, condition 2 of error-correction gadget allows one to pull an ideal decoder through the rectangle of a good exRec, no matter how many errors enter the exRec. Consider a faultless circuit C. Let C' be the circuit constructed by replacing each location in C with the corresponding rectangle. Suppose C' is subject to uncorrelated stochastic Pauli errors with physical error rate p. Then for any subset S of locations in C', the probability that all locations in S are faulty is upper bounded by pl 3 1 . Consider the following transformation of C'. First, place an ideal decoder after each rightmost exRec. If a rightmost exRec is good, then replace the rectangle with the ideal decoder followed by the corresponding operation. If a rightmost exRec is not good, then replace the exRec with a faultless error-correction gadget followed by an ideal decoder and a faulty operation. 2 Continue this procedure by examining the goodness and correctness of the rightmost exRecs, and pull the ideal decoders from right all the way to the left. The resulting circuit C" coincides with C except for those faulty locations. One can verify that for any subset S of locations in C", the probability that all locations in S are faulty is upper bounded by p 1 1 3 1, where p' = pt+ 1 • (t: 1 ) and A is the maximum number of locations of an exRec in C'. That is, C" is subject to (possibly correlated) stochastic Pauli error model with ( A )-1/t physical error rate p'. Therefore, as long as p is smaller than the threshold value t+ l , one can simulate C to arbitrary accuracy by recursively replacing the locations with corresponding 2 We refer the reader to the rigorous proof of threshold in [AGP06], which instead works with the " *-decoder" and "truncated exRec." We abuse t he notions here just to give a high-level sketch. 28 rectangles for sufficiently many levels. Remarkably, the qubit and operation overhead of such multi-level recursive simulation only scales polylogarithmically with the accuracy and the size ofC. Definition 1 can be extended to stabilizer codes encoding k > 1 qubits, although the proof of threshold will be more complicated due to the correlated logical qubits within code blocks. In a typical error-correction procedure for a CSS code, the X- and Z - components of the errors are diagnosed separately by Z- and X -type stabilizer generators, respectively. Therefore, when designing a fault-tolerant gadget for a CSS code, one can apply the criteria to the X and Z error components separately. For a general stabilizer code, one can also apply the criteria to a linear combination (e.g., superposition) of error configurations, where each configuration is analyzed separately. In fault-tolerance experiments on small quantum devices with limited qubits, the simulation is normally restricted only to one level. Suppose an error-correcting code [n, k, d] with t = l d 2 1 J 2: 1 is used for the encoding. Fully exploiting the capability of the code requires that the logical error rate scales as O(pt+ 1 ) with the physical error rate p, which ensures the existence of a pseudothreshold. 3 In this case, one only worries about at most t faults spread among the whole circuit. In particular, every exRec is good. Notice that the condition 2 for an error-correction gadget in Definition 1 is only enforced to guarantee that a good exRec behaves correctly even preceded by an exRec which is not good. Thus condition 2 is not necessary for a pseudothreshold. Definition 3 (fault-tolerance criteria for pseudothreshold). A gadget is fault-tolerant if it satis fies Definition 1, except with an error-correction gadget • An error-correction gadget with r input errors ands faults leaves with at most r + s output errors, when r + s ::; t. 3 A pseudothreshold exists as long as t he logical error rate scales quadratically with p , which might qualify as fault-tolerant in a weak sense. 29 Compared with Definition 1, in Definition 3 the condition 2 for error correction is removed, whereas condition 1 is strengthened from :s; t output errors to :s; r + s. This finer control of error propagation guarantees that the level-one circuit always simulates perfectly provided there are at most t faults within it. The difference between Definition 1 and Definition 3, however, is not essential. In practice, it is generally more convenient to design error-correction gadgets according to Definition 3. The criteria in Definition 1 are either automatically fulfilled, or in many cases can be enforced by modifying the gadget to be independent of the input state [CDT09], e.g., by repeating the error correction for a fixed but sufficient number of rounds. We will illustrate these criteria through various examples in following chapters. Fault-tolerance criteria can also be defined for an error-detecting code, i.e., with d = 2. In this case, one only has to make sure that a single fault does not eventually result in an undetected logical error or incorrect measurement outcome distribution. Definition 4 (fault-tolerance criteria for error-detecting codes) . A gadget is fault-tolerant if • A preparation gadget with s fa ult prepares the correct logical state and leaves with at most s undetected output error, when s :s; 1. • A measurement gadget with r input error and s fault does not generate an undetected incorrect probability distribution of classical outcomes, when r + s :s; 1. • A gate gadget with r input error and s fault performs the correct logical gate and leaves with at most r + s undetected output error, when r + s :s; 1. • An error-detection gadget with r input error and s fault leaves with at most r + s undetected output error, when r + s :s; 1. The rest of this thesis is devoted to constructing qubit-efficient gadgets satisfying Definitions 1, 3 or 4 using the flag paradigm. 30 Chapter 3 Flag paradigm-catch the bad faults This chapter aims to provide a general high-level idea of the flag paradigm. Equipped with the stabilizer formalism and fault-tolerance criteria, we are now able to analyze the fault-tolerance prop erties of various gadgets. We describe several instructive conventional fault-tolerance constructions before elaborating flag-based schemes for both error correction and logical computation. 3.1 Conventional fault-tolerance constructions Perhaps the most popular fault-tolerance paradigm is transversality. A circuit is transversal if there exists a partition LJi Qi of all the qubits such that each operation is supported within some Qi that contains at most one qubit from each code block. A transversal circuit is automatically fault-tolerant because a single fault can never propagate into multiple errors within individual code blocks. In this section, we give examples of fault-tolerant gadgets, for both logical gates and error correction, which consist of transversal operations. 3 .1.1 Transversal implementations of logical gates Logical Pauli operators of any stabilizer code are simply tensor products of single-qubit Paulis, and thus can be implemented transversally. More useful transversal circuits exist for structured stabilizer codes. 31 I I I X X X X I X X I I X X X I X I X I X I I I z z z z I z z I I z z z I z I z I z X = X X X X X X X Z= z z z z z z z Figure 3.1: A canonical choice of stabilizer generators and logical Pauli operators of the Steane code. Consider the seven-qubit 8teane code [7, 1, 3] [Ste96a]. Figure 3.1 shows a choice of stabilizer generators and logical Pauli operators. One can verify that transversal circuits H ® 7 , 3t@ 7 on single code blocks and CNOT® 7 between two code blocks all preserve the stabilizer group under conjugation, and therefore are valid logical operators. Recall that Y = iXZ. We have H ® 7 X H ® 7 = Z 3t0 1 y 3 0 1 = - X CNOT® 7 X 1 CNOT® 7 = X1 0 X2 H ® 7 ZH® 7 = X 3t@ 7 X 3 @ 7 = - Y (3.1) where CNOT® 7 control on all the qubits in the first code block and target on all the corresponding qubits in the second code block. Observe that H ® 7 , 3t@ 7 and CNOT® 7 conjugate logical Pauli operators in the same way that H, 8 and CNOT conjugate corresponding physical Pauli operators. Hence they effectly serve as logical operators H, Sand CNOT for the Steane code; in particular, they can be combined to transversally implement any logical Clifford gate. Generally, transversal CNOT is a valid logical gate for any CSS code; if the logical X and Z operators are selected as X- and Z-type Paulis, then it implements logical transversal CNOT. Furthermore, transversal H is a valid logical gate for any self-dual CSS code, and performs, as is often the case, logical transversal Hadamard. One reason that CSS codes are highly preferable for fault-tolerance schemes is that they usually permit transversal implementations of logical 32 Clifford gates. Prominent families of CSS codes include surface codes [Kit97a, Kit03] and color codes [BMD06, Bom15], which have macroscopic distances but geometrically local st abilizer generators. In particular, the latter family, when restricted to two-dimensional lattices, possess transversal implementations of {H, S, CNOT} , with the Steane code being its smallest member. However, a no-go theorem by [EK09] states that transversal gates that preserve the code space of any error-correcting code generate a finite group, and thus cannot be universal. Many approaches have been developed to complementing transversal logical gates to achieve universality. Bravyi and Kitaev [BK05] propose to implement logical non-Clifford gates using special resource states called magic states that are prepared though the overhead-costly procedure of distillation. Another approach encodes the logical qubits into a subsystem code [Pou05, Bac06] that allows transversal universal logical gate sets provided that the gauge qubits are fixed to a designated state through, e.g., fault-tolerant error correction [PR13, Bom15, Bro19]. Transversal universality can also be accomplished via two codes with complementary transversal gate sets. For example, one can either concatenate these two codes [JOL14], or switch from one code to the other through a series of local deformations [ADCP14]. Recently, Yoder et al. have developed a novel approach to universality which they term pieceable fault tolerance [YTC16], in some sense extending the idea of code switching from [KLZ96, HFWH13]. They construct non-fault-tolerant circuits that preserve the code space and consist of nontransversal gates, based on the so-called round-robin design. They then make these circuits fault-tolerant by dividing them into a sequence of pieces, and appending to each piece a partial error-correction procedure that timely removes the genuine malignant errors and lets pass the other errors in a controllable way. In Chapter 5, we will apply the round-robin design to certain CSS codes for nontransversal logical gate constructions. Analogous to pieceable fault tolerance, we replace each physical gate with a corresponding flag gadget that can catch bad faults, and intersperse partial error-correction procedures between these gadgets when necessary. In particular , the rules of these correction 33 ------1:-tt---t--X -------<~-x (a) w-qubit cat state - .l ...., V I+) 0) 0) 0) V - data q ubits (b) +/ +/ +/ +/- X X verify cat state IO)~ tAe-0/ 1 l+)-----------..-- 0)-ttr+-+--+--- 0)--f+¼-+----- 0)---+H,,-~-- (c) Figure 3.2: Shor-style measurement of a stabilizer X ®w (diagrams show w = 4) using w + 1 ancillas. (a) Prepare an ancilla qubit in state I+) and apply w CNOTs that control on the ancilla and target on the relevant data qubits. The outcome of the X-basis measurement on the ancilla gives the syndrome bit. An X fault (red) on the ancilla can spread into multiple X errors on the data. (b) Replace the bare ancilla with a w-qubit cat state (I O) ® w + ll) ® w)/v'2 (shaded in blue), and couple it with the relevant data qubits using transversal CNOTs. Apply transversal X-basis measurements on the ancillas, and XOR all the outcomes to get the syndrome bit. A single fault (red) when preparing the cat state can propagate into multiple X errors on the data. ( c) After preparing a cat state, measure the parities of pairs of ancilla qubits (blue) using an extra ancilla that can be recycled. On any odd parity, discard the cat state and re-prepare. Only couple the cat state with the data after verifying that, with high probability, X errors in the cat state did not propagate badly. procedures will depend on observed flag pattern. We will briefly introduce examples of these flag gadgets for logical computation in Section. 3.2.2. 3.1.2 Shor-style error correction In the paper where fault-tolerance was first introduced to quantum computing, Shor [Sho96] has provided a fault-tolerant error-correction scheme that applies to arbitrary stabilizer codes. Figure 3.2 gives a brief illustration. A naive method for measuring a stabilizer is to first prepare a bare ancilla in state I+), and then apply a sequence of two-qubit control gates that apply the measured Paulis on the corresponding data qubits conditioned on the ancilla being in state 1 1). Finally measure the ancilla in the X 34 basis to get the syndrome bit. However, this is not fault-tolerant because a single X fault on the ancilla can propagate through control gates into multiple errors on the data. See Figure 3.2(a) . To fix this issue, one can replace the I+) ancilla state with a w-qubit cat state (IO ) ® w +1 1) ® w)/ v'2, where w is the weight of the measured stabilizer. Thew control gates are made transversal by controlling on distinct ancilla qubits and the syndrome bit is calculated as the XOR of the outcomes of transversal X-basis measurements on the cat state. Recalling the criteria in Definition 1, one can verify that s errors present in the cat state before the control gates can incur at most s errors to the data. However, a single fault when preparing the cat state can result in multiple X errors that will spread to the data; see Figure 3.2(b) . To fix this issue, one can verify that the prepared cat state has no correlated X errors before coupling it with the data. One way to do this is measure the parities of pairs of ancilla qubits using an extra ancilla qubit; see Figure 3.2(c) . If any parity is odd, discard the cat state and re-prepare. Provided that the preparation and verification circuits are designed carefully, passing the verification guarantees that s faults therein result in at most s errors in the cat state, which is fault tolerant. The above machinery controls the propagation of bad faults. However, the syndrome bits obtained are not reliable. A single error in the qubit measurement on the cat state flips the syndrome bit; errors occurring on the data and between the syndrome measurement circuits render the syndrome bits obsolete. Pauli corrections based on a spurious syndrome may lead to an nontrivial logical error. A simple solution to this issue is to repeatedly extract the syndrome for sufficiently many rounds and take a majority vote. In the worst case, O(d 2 ) rounds of syndrome extractions are required to fulfill the criteria in Definition l. Note that Shor's scheme requires at least w + l ancillas, where w is the maximum weight of a stabilizer generator. 35 data ancilla verifier +/- l 0/1 1 a)-----~ ----r-T--+ 1- 1 o) ---,j.,---++-EBt-- o / 1 Figure 3.3: Steane-style measurements of Z- and X-type stabilizers for a CSS code [n, 1, d] using at least 2n ancilla qubits. All the wires have slashes and represent code blocks of a same stabilizer code. CNOT and measurement symbols are corresponding transversal operations applied over the code blocks. To measure all the Z-type stabilizers, first prepare two code blocks both in the logical I+) state, denoted by "ancilla" and "verifier" respectively. Then perform transversal CN OTs from the verifier to the ancilla code block, followed by transversal X-basis measurements on the verifier. Next perform parity checks on the measured bit string against all the X-type stabilizer generators and the logical X operator. Repeat the preparation and verification until no error is detected. Conditioned on success, apply transversal CNOTs from the data to the ancilla block, followed by transversal Z-basis measurements on the ancilla. Perform parity checks on the measured bit string agains all the Z-type stabilizers to obtain the syndrome bits. The procedure for X-type stabilizers is similarly constructed. 3.1.3 Steane-style error correction Steane has proposed an error-correction scheme [Ste97] that applies to CSS codes and is more efficient than Shor's scheme. Although recently extended to arbitrary stabilizer codes [ Yod18], Steane's method is most conveniently explained in terms of CSS codes encoding single logical qubit. Instead of measuring one stabilizer at a time, Steane's method measures all X- or Z-type stabilizer generators collectively by applying transversal control gates between every data qubit and the corresponding qubit in an ancilla code block prepared in a certain encoded state. Similar to Shor's method, one should verify that the ancilla code block does not contain correlated errors before coupling it with the data. See Figure 3.3. Given an ancilla code block, X error components can be copied from the data to the ancilla using transversal CNOTs, which serves as a logical CNOT. The syndrome extraction is thus valid if the ancilla is prepared in logical state I+). Provided that all operations are perfect, transversal Z-basis measurements on the ancilla give a bit string, from which one obtains the syndrome bits by taking parity checks against the corresponding Z-type stabilizers. Similar to cat states, the ancilla block in I+) can be verified by another verifier block prepared in the same state, where one makes sure that both the stabilizers and the logical operator have correct parities. Upon 36 successful verification, one is guaranteed that s faults during the preparation result in at most s errors present in the ancilla block. Although a single fault on a data CNOT can affect both a data qubit and an ancilla measurement, the resulting spurious measurement outcome can lead to at most one error on the same corrupted data qubit. The same argument also holds for the measurements of X -type st abilizers. One can verify that any single fault within the whole gadget incurs at most one data error after the Pauli corrections, thus the criterion in Definition 3 is satisfied. Remarkably, there is no need to repeat t he syndrome extraction, in contrast to Shor's method. However, Steane's method requires at least 2n ancilla qubits, where n is the size of a code block. In Section. 4.1, we will numerically compare the performances of Shor's and Steane's schemes on small codes with those of flag-based schemes via Monte Carlo simulations. 3.1.4 DiVincenzo-Aliferis decoding method Many constructions of fault-tolerant error-correction gadgets, including Shor, Steane, and Knill [Kni05a], involve extensive preparations and verifications of ancilla states, and thus would rely on the ability of fast and reliable qubit measurements. In certain qubit systems, however, the time and error rate of qubit measurements can be orders of magnitude higher than those of physical gate operations, hindering large-scale fault-tolerance thereon. It is therefore reassuring that fault tolerance is barely deteriorated in terms of threshold or scalability if measurements are postponed to the end of the circuits [DA07] or even mostly eliminated [PSBTl0]. Below we briefly explain the decoding method introduced by DiVincenzo and Aliferis [DA07] that deals with the issue of slow measurements. The purpose of ancilla verification is to prevent correlated errors in the prepared ancilla from propagating to the data. The DiVincenzo-Aliferis method follows Shor's method to prepare a cat state, but removes this verification and instead appends a decoding procedure on the ancillas immediately after the transversal control gates. Then the ancilla qubits are measured transversally, 37 decoding circuit I+) 0/1 cat I0)--+1+-'"-'--........... --....... ,.____+/- state IO) 0/1 IO) 0/1 data qubits --.....u-:i~------~----- Figure 3.4: A circuit based on the DiVincenzo-Aliferis decoding method that measures X ® 4 and tolerates a single fault. Prepare the ancillas in a cat state and couple it with the relevant data qubits without verification. Then apply a carefully designed decoding circuit (shaded in blue) followed by qubit-wise measurements. The X-basis measurement outcome gives the syndrome bit, and the Z-basis measurement outcomes give the information based on which the potential correlated data errors are corrected. Here, an X correction on the fourth data qubit is applied if and only if the Z-basis measurement outcomes are "101." One can verify that any single fault in the procedure results in at most one data error. and the outcomes reveal the syndrome bit as long as the information about the potential correlated errors incurred to the data. The key is that the circuit that prepares or decodes the ancilla state should be carefully designed to ensure that the ancilla measurement outcomes are sufficient to correct the correlated data errors. This method, when applicable, requires w ancilla qubits where w is the maximum weight of a stabilizer generator. The paper by DiVincenzo and Aliferis [DA07] gives an example circuit that measures X ® 4 and tolerates a single fault. In Figure 3.4 we give an alternative example, and in Chapter 7 we extend this decoding method to construct fault-tolerant error-correction gadgets applicable to arbitrary stabilizer codes with distance three. 3.2 Flag paradigm for quantum fault tolerance In this section, we introduce an alternative fault-tolerance paradigm to transversality-the flag method. As we have discussed in Section. 1.2, the key idea of the flag method is to use flag gadgets 38 flag ancilla ::::;, I0)-+++--------1-.0/ l ¢:: flags possible correlated errors syndrome ancilla ::::;, I+) X + / - ¢= syndrome bit data } flagged errors must qubits ----------1-++--1 be distinguishable Figure 3.5: A flag circuit that measures X ® 4 . A syndrome ancilla prepared in I+) is coupled with the four data qubits using CNOTs; a measurement in the X basis gives the syndrome bit when there is no fault. The syndrome ancilla is protected by a flag gadget (blue) , which consists of a flag ancilla prepared in IO ) and measured in the Z basis, as well as two CNOTs. Correlated errors on the data qubits can result from a single X fault (red) on the syndrome ancilla. But such bad propagation will also trigger the flag measurement outcome to be nontrivial (shaded in red). Provided the flag circuit is carefully designed, possible flagged data errors can be distinguishable, e.g, by their syndromes ( or along with flag pattern if more than one flag ancilla is used). to catch those circuit faults that can propagate badly. For illustration purposes, below we will (1) give a complete error-correction protocol for the [7, 1, 3] Steane code that satisfies the criteria in Definition 3 and consists of flag-based syndrome-extraction circuits, and (2) show examples of flag gadgets for physical CZ and CCZ gates that can be combined to perform fault-tolerant logical gates for several codes. 3.2.1 Flag circuits for measuring stabilizers Normally, measurements of stabilizers involve coupling the data qubits with ancillas. A crucial ingredient of conventional fault-tolerance schemes, as we have explained in Section. 3.1 , is to make such coupling transversal. That is, prepare the ancillas in a special state, e.g., a cat state or logical code block. Thus, a single error in the ancillas cannot propagate into multiple errors in the data. In flag error-correction schemes, however, such bad propagations are allowed to occur. The key is that a flag gadget can be added to protect the ancillas, in such a way that correlated errors resulting from faulty ancillas can be signaled by a nontrivial flag measurement outcome. See Figure 3.5 for a schematic. 39 0 I ) I+) a "" r - b C (a) "" 0 1 r - d I +/- @ failure XI xx XY xz ' ,/ Data errors @ failure Data errors IIIIIXX XI IIIIIIX IIIIXXX xx IIIIIXX IIIIYXX XY IIIIIYX IIIIZXX xz IIIIIZX (b) Figure 3.6: Flag syndrome extraction for the [7, 1, 3] code. (a) A circuit that extracts the IIIXXXX syndrome, and if a single fault spreads to more than 2 data errors then the Z-basis measurement will return I 1), flagging the failure. (b) The nontrivial data errors that can result from a single gate failure in (a) that triggers the flag; these errors are distinguishable by their syndromes and so can be corrected. For example, to measure a stabilizer generator, one couples the relevant data qubits through control gates with a single syndrome ancilla. The syndrome ancilla is protected by a flag gadget that consists of a flag ancilla and two control gates. When such flag circuit has no fault, the measurement outcome on the syndrome ancilla gives the correct syndrome bit, and the measurement outcome on the flag ancilla is trivial. A single fault on the syndrome ancilla can still propagate into multiple errors on the data. Any such bad propagation, however, can be caught by a nontrivial flag measurement outcome. Provided the flag circuit is carefully designed , all possible flagged errors can be distinguished by their syndromes ( or along with flag pattern if more than one flag ancilla is used) , and thus can be corrected. Consider the [7, 1, 3] Steane code, whose stabilizer generators are given in Figure 3.1. Fig ure 3.6( a) gives a flag circuit that measures the first stabilizer II IX XX X. With no faults, the X-basis measurement outcome gives the syndrome bit, and the Z-basis measurement will always give IO ). The purpose of the flag ancilla, prepared in IO ), is to detect gate faults that can propagate to correlated errors, weight two or higher, on the data. Failures after gates a and d cannot create correlated errors. The failures after gates b and c that can create correlated errors are listed 40 in Figure 3.6(b) . (Y failures on the syndrome ancilla have the same effect on the data as X failures.) These failures will all be detected, causing a I 1) measurement outcome. Moreover , observe that the seven distinct data errors have distinct , nontrivial syndromes. Similar to Shor's scheme, flag-based error correction measures one syndrome bit at a time, using a circuit analogous to Figure 3.6(a) . A complete flag error-correction procedure is given by the following. Error-correction procedure l. Use the circuit of Figure 3.6(a) to extract the IIIXXXX syndrome. (a) If the flag ancilla is measured as 1 1), then use the unflagged circuits with bare ancillas to extract all six syndrome bits. Finish by applying the corresponding correction from among IIIIIII , IIIIIXX, IIIIXXX , IIIIYXX, IIIIZXX , IIIIIIX, IIIIIYX, IIIIIZX. (b) Otherwise, if the syndrome is - 1, i.e., the syndrome ancilla is measured as I-), then use unflagged circuits to extract all six syndrome bits. Finish by applying the corresponding correction of weight :s; 1. 2. (If the flag was not raised and the syndrome was trivial, then) Similarly extract the IX XI IX X syndrome. If the flag is raised, then use unflagged circuits to extract the six syndrome bits, and finish by applying the correction from among IIIIIII , IIIIIXX , IIXIIXX , IIYIIXX, IIZIIXX, IIIIIIX, IIIIIY X, IIIIIZX. If the syndrome is nontrivial, then use unflagged circuits to extract the six syndrome bits, and finish by applying the correction of weight :s; 1. 3. Similarly extract the XIX IX IX syndrome, and correct if the flag is raised or the syndrome is nontrivial. 4. Similarly extract the I I I Z Z Z Z syndrome, and correct if the flag is raised or the syndrome is nontrivial. 41 5. Similarly extract the IZZIIZZ syndrome, and correct if the flag is raised or the syndrome is nontrivial. 6. Similarly extract the ZIZIZIZ syndrome, and correct if the flag is raised or the syndrome is nontrivial. We now argue that this non-deterministic procedure satisfies the fault-tolerance criteria in Definition 1 with t = L d 2 1 J = l. • If there are no fault s, then the procedure appropriately corrects the data to the code space. • If the data lies in the code space and there is at most one faulty gate in the error-correction procedure, then: - If all syndromes and flags are trivial, then the data can have at most one error. (No correction is applied.) - If a flag is raised or a syndrome is nontrivial, then the subsequent unflagged syndrome extractions are perfect , and suffice to correct either possibly correlated errors (if the flag is raised) or at most one error (if no flag is raised but the syndrome is nontrivial). • The parity check matrix for the X- or Z-type stabilizer generators is that of the classical Hamming code, which is perfect, i.e., any vector is at most one bit away from the code space. Hence the output state has at most one X or Z error component, regardless input errors or circuit faults. Let us point out that when a syndrome bit extracted by a flagged circuit is nontrivial, then even if the flag is not raised we still extract all six syndrome bits ( using unflagged circuits) before applying a correction. This is because a fault on the data could have been introduced in the middle of syndrome extraction. For example, if we extract the first syndrome as + 1, but a Z 7 error is then added to the data, the remaining syndromes will be - 1, - 1, + 1, + 1, + l. The correction for 42 ( +, -, -, +, +, +) is Z 3 , but were we to apply this correction the data would end up with error I I Z II I Z. The moral is that nontrivial syndromes cannot be trusted unless they are repeated. 3.2.2 Flag gadgets for logical computations Apart from stabilizer measurements, flag gadgets can also be added to those circuits that perform logical operations. Especially in a circuit that consists of either nontransversal operations or non-Clifford gates, flag gadgets can detect bad propagations of faults affiicting multi-qubit gates. In Chapter 5, we will provide flag schemes for logical computation over several CSS codes. The constituent physical gates that we will use in particular, besides Paulis, are CZs and CCZs. There are several reasons for this choice. First, for CSS codes, it is relatively easy to represent the logical basis states in terms of physical computational basis. Since CZ and CCZ are diagonal matrices under the computational basis and only change the phases, it is convenient to analyze their logical effects on the code space. Second, CZ and CCZ have more favorable properties for error propagations than, say, CNOT. For example, they are symmetric in terms of their two or three qubit wires, commute with Z error components, and anti-commute or spread only X error components: (3.2) (3.3) Observe that CZ copies an X (or Y) error on one wire into a Z error on the other, and CCZ copies an X error on one wire into a CZ= ½(II+ IZ + ZI - ZZ) error on the other two wires, 43 i.e., into a linear combination of II, IZ, ZI, ZZ errors. In contrast to CNOT circuits, CZ or CCZ circuits spread X errors only once, for example: (3.4) Based on the above circuit identities, we design flag gadgets as in Figure 3. 7. In particular, consider the circuit of Figure 3.7(a) , using one flag ancilla that at the end is measured in the Z basis. If the gates are perfect, then the measurement returns O and this circuit has the effect of a single CZ gate. If the CZ gate fails with an X or Y fault on the first data qubit, however, then the measurement will return l. Thus certain kinds of faults can be detected. If at most one location fails and the measurement returns 0, then the output cannot have an XX, XY, Y X or YY error. A similar circuit can catch Z faults. If all gates in Figure 3.7(b) are perfect, then the X-basis measurement will return + and the effect will be of a single CZ. If there is at most one fault and the measurement returns +, then the output cannot have a XY or Z Z error. (This fact can be verified by, for example, propagating I Z Z and X Z Z backward through the circuit, and observing that no single gate failure can create either.) (a) I+ ) -i~1----i + / I - (b) Figure 3.7: CZ gadgets to catch correlated faults. (a) A flag gadget (red) can be used to catch XX, XY, YX and YY faults after the CZ gate. (b) A similar flag gadget (blue) catches ZZ faults. As we will see in Chapter 5, the gadgets to catch X and Z faults in Figure 3.7 can be combined into a gadget as in Figure 5.2 that uses two flag ancillas. All single faults in such gadget are caught except those equivalent to a single-qubit fault on the CZ output or input qubits (namely, IX , IY , IZ, XI, YI, ZI and XZ, YZ, ZX, ZY). No CZ gadget can catch more errors than 44 this. Similarly we design a flag gadget for CCZ as in Figure 5.4 that uses four flag ancillas. It satisfies that provided there is at most one failed gate and the measurement outcomes are trivial, 0 and+, then the error(s) on the output is a linear combination of Paulis that could result from a one-qubit fault before or after a perfect CCZ gate. We will explain in more details in Chapter 5. In particular, we will show how to supplement these CZ and CCZ gadgets with intermediate partial error-correction procedures to fault-tolerantly perform logical gates. 45 Chapter 4 Flag fault-tolerant error correction In Section. 3.2.1 we have provided a detailed analysis of a flag error-correction scheme for the [7, 1, 3] Steane code that uses only two extra qubits. In this chapter we will give more examples. Specifically, in Section. 4.1, we give flag error-correction schemes using only two extra qubits for various common distance-three codes, including both small codes and asymptotically large codes. We believe that the schemes tailored for small codes are amenable for near-term fault-tolerance experiments. For example, one sophisticated scheme allows fault-tolerant error correction over seven logical qubits with only 17 physical qubits using the [15, 7, 3] Hamming code. Material in this section is drawn from [CR18b]. In Section. 4.2, we extend the flag error correction to general stabilizer codes with arbitrary distance. For a general distance-d code with stabilizer generators of maximum weight w, we provide a flag scheme that consumes min{d + 1, 2w + 2} ancillas with fast qubit measurement and reset. Material in this section is drawn from [CR19]. 4.1 Flag error correction for common distance-three codes While there have been experimental tests of quantum codes [CPM+98, LGz+os, NMM+ 14, BHMT+14, KBF+15, RPH+ 15, CMS+ 15], testing fault-tolerant error correction remains a major challenge. A main difficulty is the substantial overhead; many physical qubits are needed for each 46 encoded, logical qubit. Limited fault-tolerance schemes have been tested on 5-qubit systems [Got16, LGL +17, Vui18, Tcc+ 17, RRM+1s, HF19], using the [4, 2, 2] code. This code encodes two qubits into four , and the fifth qubit is used for error detection. 1 Since the code has distance two, it can only detect an error, not correct it. Until recently, the smallest known schemes that can correct an error used at least ten qubits. Indeed, to achieve fault tolerance, one would need a tenth extra qubit for the [9, 1, 3] Bacon-Shor code, or five extra qubits for the [5, 1, 3] perfect code. For example, as we have seen in Section. 3.1 , Shor-style syndrome extraction requires w + l [Sho96] ancilla qubits ( or w using the decoding method [DA07]), where w is the largest weight of a stabilizer generator. Steane-style error correction uses at least a full code block of extra qubits, whereas Knill's scheme [Kni05b] uses an encoded EPR state and thus at least two extra code blocks. Yoder and Kim [YKl 7] have given fault-tolerance schemes using the [5, 1, 3] code with eight qubits total, and the [7, 1, 3] Steane code with nine qubits total. Extending the latter construction, we develop fault-tolerance procedures that use only two extra qubits, based on the flag paradigm introduced in Chapter 3. Figure 4.1 highlights some examples, and Table 4.1 summarizes some suitable, distance-three codes and compares the qubit overhead of our schemes to other methods. (In particular, in Section. 7.1 , we generalize a method of Stephens, Yoder and Kim [Ste14, YKl 7]: the "decoded half cat state" method uses a cat state with max{3, iw/21} extra qubits.) In particular, with the [5, 1, 3] code our scheme uses only seven qubits total, or ten qubits with the [8, 3, 3] code. A particularly promising application is to the [15, 7, 3] Hamming code: 17 physical qubits suffice to protect seven encoded qubits. In Section. 5.3, we give fault-tolerant procedures for applying arbitrary Clifford operations on these encoded qubits, also using only two extra qubits, and fault-tolerant universal operations with four extra qubits, 19 total. Substantial fault-tolerance tests can therefore be run on a quantum computer with fewer than 20 qubits. 1 In some of t he referenced experiments, only one of the two encoded qubits was fault-tolerantly protected. T hus, these tests essentially used the [4, 1, 2] Bacon-Shor subsystem code. 47 Logical qubits Code qubits Ancilla qubits 0 ------+ °o°oo +00 o 0 o ------+ 0000 +00 0000 iio-+ °o_9:56°o 000 +00 o 0 o 00000 080 ------+ 00000 +00 00000 Figure 4.1: Our flagged syndrome-extraction method uses just two ancilla qubits to correct errors fault tolerantly, for a variety of distance-three codes. For example, seven qubits total are enough to correct errors on one encoded qubit, using the [5, 1, 3] code, and 17 qubits are enough to protect seven encoded qubits. Ancilla qubits required for Shor Decoded Code cat state half cat Flagged [5,1,3] 5 3 2 o [7,1,3] 5 3 2 [YK17] [9, 1, 3] 1 [8,3,3] 7 3 2 [10,4,3] 9 4 2 [11, 5, 3] 9 4 2 o [15, 7, 3] 9 4 2 o [31, 21, 3] 17 8 2 � [2r - 1, 2r - 1 - 2r, 3] 2r-l + 1 2r-2 2 Table 4.1: Numbers of ancilla qubits required for different fault-tolerant syndrome-extraction methods. Shor's method, using a verified cat state, requires w + l ancilla qubits, where w is the largest weight of a stabilizer generator. (The [9, 1, 3] Bacon-Shor code is an exception, as it is a subsystem code.) Stephens, Yoder and Kim [Ste14, YKl 7] have proposed using a cat state on only max{3, iw/21} qubits, combined with a decoding trick from [DA07]; see Section. 7.1. When applicable, our flagged error-correction procedure needs only two extra qubits, as observed for the [7, 1, 3] code by [YKl 7]. Codes marked o are Hamming codes. 48 4 .1.1 Two-qubit error correction for Hamming codes The Hamming codes are a family of [2,.. - 1, 2r - 1 - 2r, 3] quantum error-correcting codes, for r 2". 3 [CS96, Ste96c]. They are self-dual perfect CSS codes. The smallest member of the Hamming codes is the [7, 1, 3] Steane's code, whose stabilizers and logical Pauli operators have been given in Figure 3.1. In Section. 3.2.1 , we have given a complete procedure for error-correcting Steane's code using only two ancilla qubits. Here we show how to generalize that scheme to an arbitrary Hamming code. 4.1.1.1 [15, 7, 3] Hamming code Consider the r = 4, [15, 7, 3] code, which has four X and four Z stabilizers each given by the parity checks of Figure 4.2(a) . Observe that the columns form the numbers 1 through 2r - 1, written in binary; this holds for each Hamming code. For a subset S, let X s = ITj ES X 1 . The circuit of Figure 4.2(b) works to fault-tolerantly extract the first X syndrome, for X{s, ... ,lS}· Similar to Figure 3.6(a) , any single gate fault that leads to a data error of weight2". 2 will also make the Z-basis measurement output 1 1). Moreover, if the flag is triggered by a single fault , then the possible error X components are 1, X s, X{s,9}, X{s,9 ,10}, X{s,9 ,10,12}, X{s ,9,10,11, 12}, X{s ,9,10,11,12, 14} , X{s,9 ,10,11 ,12,13,14} One can verify that these errors are distinguishable by their Z syndromes. Observe that the order of the CNOT gates is important. Similar circuits work for the other stabilizers, thus giving a two-qubit fault-tolerant error correction procedure for the [15, 7, 3] code. The detailed procedure and the proof for fault tolerance are similar to those for [7, 1, 3] given in Section. 3.2.1. In particular, the procedure satisfies t he criteria in Definition 1 because Hamming codes are self-dual perfect CSS codes. 49 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 (a) 8 9 10 1 1 1 1 1 11 0 1 1 1 1 12 1 0 0 1 1 13 1 0 1 0 1 14 15 0 ,.,. _ T 1- ...., ,. ' ,. ,.,. 0 i' - (b) / 1 +/ - Figure 4.2: (a) [15, 7, 3] code parity checks. (b) Flagged circuit to extract the X{s, .. ,15 } syndrome fault tolerantly. Section. 6.2.2 gives a single-ancilla fault-tolerant circuit to prepare encoded 1 0 7 ) . 4.1.1.2 General Hamming codes C laim 5. Syndromes for the [2r - 1, 2r - 1 - 2r, 3] Hamming code can be fault-tolerantly extracted with two qubits. Proof. Consider the stabilizer X{2r- 1, ... ,2r_ 1}. As in Figure 3.6(a) and Figure 4.2(b) , we give a permutation of the last 2r-l qubits so that , when the flag is triggered , the possible X errors have distinct syndromes. Let p(x) be a degree-(r - 1) primitive polynomial over GF(2). 2 For j = 0, ... , 2r- l - 2, let q 1 ( x) = x 1 mod p; these are distinct polynomials of degree ::; r - 2. Furthermore, the remainders of their cumulative sums, L i=o xi, are also distinct. (Otherwise, if O = xH 1 + ... + xk = xH 1 (x k-j + 1)/ (x + 1), then considering the lowest-order terms give x k-j + 1 = 0, contradicting that p is primitive.) identify both qubit indices and syndromes with polynomial coefficients, and then combine the above two properties. � 2 We thank Qian Yu for suggesting this construction. 50 @ failure Data error ZI IIZXI zx IXZXI I+) +/- ZY IYZXI zz IZZXI I O) 0/1 a b C d X z z X I @ failure Data error I X z z X ZI IIIXI X I X z z zx IIXXI z X I X z ZY IIYXI X= X X X X X zz IIZXI Z= z z z z z (a) (b) (c) Figure 4.3: Flagged syndrome extraction for the [5, 1, 3] code. (a) Stabilizers and logical operators. (b) This flag circuit extracts the X Z Z XI syndrome, and if a single fault spreads to a data error of weight 2: 2 then the X -basis measurement will return I-), flagging the failure. ( c) The nontrivial data errors that can result from a single gate failure in (b) that triggers the flag; these errors are distinguishable by their syndromes and so can be corrected. 4 .1.2 Two-qubit error correction for other distance-three codes The perfect [5, 1, 3] code [LMPZ96] has the stabilizer generators, and logical X and Z operators of Figure 4.3(a) . The syndrome for the first stabilizer, XZZXI, can be extracted by the flag circuit in Fig ure 4.3(b) . Failures after gates a and d cannot create correlated errors. The failures after gates b and c that can create correlated errors are listed in Figure 4.3(c) . (Y failures on the first qubit have the same effect on the data as Z failures.) These failures cause nontrivial flag measurement outcomes. Moreover, observe that the seven distinct data errors have distinct, nontrivial syndromes. The complete error-correction procedure and the proof for fault tolerance are similar to those for the Hamming codes. In particular, the procedure satisfies the criteria in Definition 1 as the [5, 1, 3] code is perfect. We give two-ancilla-qubit fault-tolerant state preparation and measurement circuits in Sec- tion. 6.2.l. 51 X X X X X X X X X X I I I z z y y X X X X X X X X X X X X z z z z z z z z z z I I I X X z z y y y y z z z z z z z z X z z X I z y y z I I X X z z I I y y y y I I z y X z y X I X z z X I z y y z I z z z z z z z z z z I z X I X y z y X I X z z z I z y y z X I I z z X I y X z I X I z z X y y z X I X z y z I z y y I z I y z y y z X I (a) (b) (c) Figure 4.4: (a) Stabilizers for an [8, 3, 3] code. One choice for the logical operators is .X1 x{4,5 ,7,s}, Z1 = z{2,5}x{3,s}, X2 = x{3 ,6}z{4,5}, Z2 = z{l ,5 ,6, 7} , .X3 = z{l ,2}X{6,1}, Z 3 z{l ,2 ,4 ,7}· (b) Stabilizers for a [10,4, 3] code, based on the [5, 1, 3] code [CRSS97]. One choice for the logical operators is .X1 = X 8Y 10 Z 1 , Z 1 = X 10 Y 7 Z 3 , .X2 = X 10 Y 8 Z 2 , Z 2 = X 8Y 6 Z 5 , .X3 = X 9Y1Z1, Z 3 = X4Y3Z1 , .X4 = X 9Y6Z2 , Z4 = X4Y5Z6. (c) Stabilizers for an [11 , 5, 3] code. Figure 4.4 presents [8, 3, 3] , [10, 4, 3] and [11, 5, 3] codes [Ste96c, CRSS97, Got96]. Many other distance-three codes are given in the code t ables at [Gra07]. The general property required for our flagged procedure to fulfill the criterion in Definition 3 for measuring an operator is: for an operator Z 1Z2Z3 . . . Z w (up to qubit permutations and local Clifford unitaries), t he different errors PjZj+l .. . Z w, for P E {I, X, Y, Z} and j E {2, . .. , w - 1}, should have distinct and nontrivial syndromes. (For a CSS code, for which X and Z errors can be corrected separately, it is enough that the syndromes for different errors be different for P E {J, Z}.) We have verified this property indeed holds for some qubit permutation of each of the st abilizer generators for the [11 , 5, 3] code, For the [10, 4, 3] code, there are permutat ions that work for st abilizers X ® 10 and Z ® 10 , which can detect any single-qubit error. For example, the order 1, 2, 3, 4, 6, 7, 5, 8, 9, 10 works for both. (With 1, 2, .. . , 10, the errors Z 9 X 10 and Y 6 X{ 7 , 8 , 9 , 10 } have the same syndrome.) If an error is detected or the flag is triggered, t he st abilizers can all be measured without flags to diagnose the problem. For the [8, 3, 3] code, there are no valid permutations for X ® 8 and Z ® 8 . Instead, to detect single-qubit errors we can measure with flags XXYZIYZI , ZZIXYIXY and IIZYXZYX. T herefore, for all of these codes, two ancilla qubits are enough to fault-tolerantly extract the syndromes and apply error correction. 52 For the [10, 4, 3] and [8, 3, 3] codes, we measure a subset of stabilizers to detect an error, before optionally measuring the remaining stabilizers. Some two-qubit errors, such as XX I • • • I , will not be detected and therefore will not be corrected. The error-correction procedures thus fail the fault-tolerant error correction criteria in Definition l. This is fine for fault-tolerant computation with one level of encoding, but is not enough for analyzing two or more code concatenation levels. 4.1.3 Numerical simulations In order to get a sense for the practicality of the two-qubit flag error-correction schemes, we simulate error correction using a standard depolarizing noise error model on the one- and two-qubit operations [Kni05a]. 3 The error model is specified as follows. • Gate is faulty with probability p, in which case the gate is followed by a Pauli chosen uniformly at random from the set of all possible nontrivial Paulis supported on the qubit(s) that the gate acts on. • Preparation of IO ) or 1 1) is affiicted with X or Z with probability 4p/15, respectively. • Qubit measurement outcome in the Z or X basis is flipped with probability 4p/15. • Idle qubit in a time step is faulty with probability p,p/10,p/100 or 0, as will be specified. When faulty, the qubit is affiicted with a uniformly chosen nontrivial Pauli. Figure 4.5 shows the results from simulating at least 10 6 consecutive error-correction rounds for each value of the CNOT failure rate p. Observe that for the [15, 7, 3] code, Steane-style error correction, which extracts all stabilizer syndromes at once, performs better than either the Shor- style or two-qubit flag procedures. For the [5, 1, 3] and [7, 1, 3] codes, the different error-correction methods are all very close. By carefully using their stabilizer generators in the flagged schemes, multi-qubit block codes like the [8, 3, 3] and [10, 4, 3] codes give higher pseudo-thresholds. 3 T he source code is at https: //github. com/chaor11/twoqubi tee . 53 1000 [7, 1, 3] 500 iii t ' i ! : , t , • I , t 1 [5, 1, 3] 200 4 10- Figure 4.5: Comparison to previous error-correction schemes. Two-qubit flag error correction ( • ) slightly outperforms Shor-style correction(•) for the [5, 1, 3] code, and both Shor- and Steane-style () error correction for the [7, 1, 3] code. For the [15, 7, 3] code, Steane's method performs best. Logical error rates are plotted divided by p 2 to reveal leading-order coefficients, and p, 3p, 4p and 7p, i.e., error rates without encoding, are plotted to help judge pseudothresholds [SCCA06]. Two-qubit flag error correction for the [8, 3, 3] ( • ) and [10, 4, 3] ( • ) codes can achieve higher pseudo-thresholds. 54 For simulations using the Shor's method, we prepare cat states using circuits similar to that in Figure 3.2(c). Since we are considering distance three, it suffices to use one verifier ancilla and measure the parity of one pair of cat ancillas for one time. For simulations using the Steane's method, we prepare and verify the encoded ancilla states using circuits similar to that in Figure 6.3 using one verifier ancilla, which we will explain later in Section. 6.2.2. For both Shor's and Steane's simulations, the logical error rates are estimated conditioned on the success of ancilla verifications. Note that the Pauli corrections performed in the simulations are never realized in the error correction in practice. Such corrections can be processed classically by updating the Pauli frame [Kni05a, AGP06]. We emphasize that the simulations performed in Figure 4.5 do not introduce memory errors on resting qubits, nor add errors for moving qubits into position to apply the gates. This is a better assumption for some experimental platforms than others. For comparison, we simulate the two-qubit flag and Steane-style error-correction schemes on the [7, 1, 3] code with rest error rates of p/100, p/10 and p; see Figure 4.6. As one may expect, the advantage of the two-qubit flag schemes over Steane's scheme could reverse when the memory error increases. At the highest rest error rate, the Steane-style scheme outperforms the two-qubit flag scheme. 4 .1.4 Benefits of more flags We have focused on extracting syndromes using two extra qubits in order to minimize the qubit overhead. With just one more qubit, however, fault-tolerant syndrome extraction becomes considerably simpler. Consider for example the circuit in Figure 4. 7 for extracting a Z Z Z Z syndrome. Every CNOT gate into the syndrome ancilla has its own flag, to catch Z faults that can lead to correlated Z errors on the data. The flags allow for closely localizing any fault, thereby easing error recovery. For example, if there is a single fault and only the second flag above is triggered, 55 ',,,,, , , • • • •.tt • • • • • • • • • • • • Flag ,,, ... ~~-··············· 200 5 10- ',, ...... . ' .. . ',,,, Steane • : 1 ,,p • ----------- I ,·······~~······· ',, .... • ti : , ••. I,•~--, •••• , .•..... ,.~···· =•·· ',, .... ,,, 10-2 p Figure 4.6: Effect of rest errors on [7, 1, 3] code two-qubit flag ( • ) and Steane-style ( ) error correction. Rest error rates from bottom to top: p/100, p/10 and p. l+)- IO) -++++lf++++-<F-l+++l......+H-++++lf+----fif++++-<E-l+---<f-l+- O /1 Figure 4.7: Overlapping flags can closely localize Z faults. 56 I+) I ~ - ~ T ,.I._ , "" ' "' r " - I-' (a) - - T ,l ,.1._- "" +/- 0/1 0/1 I+) 0 0 0 l "' 't' l - " I-' - 't' "' - (b) Figure 4.8: Extracting multiple syndromes with a shared flag. - - + I ,l o ,l"" 0 "" 0 / /1 /1 /1 then the Z error on the data can be I I I I, I Z Z Z or I I Z Z. The regions covered by the flags overlap so that no Z fault is missed. This technique is most effective if qubit initialization and measurement is fast. In Section. 4.2, we provide schemes based on such technique that applies to arbitrary codes unconditionally. Less extreme versions of the technique, in which some gates share flags, can also be used. In Chapter 5 we use variants of this technique to apply operations fault tolerantly to data in a block code, with little qubit overhead. For a large code with many stabilizers, and especially with rest errors, it can be inefficient to extract the syndromes one at a time. The circuit in Figure 4.S(a) extracts two of the [7, 1, 3] code's syndromes at once, using a shared flag. Figure 4.S(b) uses a shared flag to extract all three Z syndromes. A single fault can lead to at most a weight-one X error and, if the flag is not triggered, a weight-one Z error. If the flag is triggered, the gates are arranged so that the different Z errors are distinguishable. The circuit uses four qubits and 15 CNOT gates, versus seven qubits and 25 CNOT gates for Steane-style extraction with the decoding trick [DA07]; however the syndrome 100 can occur with errors 1, Z 1 , Z 3 or Z 5 and so, unlike in Steane's scheme, must be verified before applying a correction. 57 The design space for fault-tolerant error correction thus expands considerably with more allowed qubits. A natural problem is to extend the flag technique to medium-size codes of higher distance, which we will address in Section. 4.2. 4.2 Flag error correction for arbitrary stabilizer codes Chamberland and Beverland [CB18] have formalized the flag idea for error correction and extended it to arbitrary-distance codes. For a distance-d code, they provide sufficient conditions for syndrome-extraction circuits that can be used to construct a fault-tolerant error-correction protocol satisfying the criteria in Definition 1. We roughly paraphrase their sufficient conditions- namely, the t-fiag circuit and the flag t-FTEC condition with t = l d 2 1 J- as "detectability" and "distinguishability", respectively, as follows. Detectability: each stabilizer generator is measured with a flag circuit that signals whenever s :c; l d 2 1 J faults result in more than s data errors. Distinguishability: any two data error patterns, each arising from at most l d 2 1 j faults spread among the stabilizer generators' flag circuits and resulting in same flag pattern, either have distinct syndromes or differ by a stabilizer. They give several flag circuits using very few ancillas that they show satisfy the above conditions for families of codes including the rotated surface codes, Reed-Muller codes and hexagonal color codes. However , for a general code and given specific syndrome-extraction circuits, it could be tedious to verify these conditions. Thus in this case, it is a priori unknown if flag error-correction scheme exists. Below, we provide a flag error-correction scheme that applies to any stabilizer code, uncon ditionally. Our scheme does not necessarily satisfy the conditions in [CB18]. In particular, our 58 circuit construction is similar to that in Figure 4.7, and relies only on the code's distance and stabilizer generator weights. The key idea is that harmful faults can be approximately located from the observed flag pattern and then corrected right away, before they propagate to correlated data errors. For a distance-d code with stabilizer generators of maximum weight w, the scheme requires one syndrome ancilla and min{ d, 2w + 1} flag ancillas. No further qubits are needed, provided that the ancillas can be reset rapidly, in time comparable to a gate operation. Unlike Shor's, Steane's and Knill's schemes, our procedure does not verify the ancillas; no postselection is needed. Unlike previous flag schemes (e.g., in Section. 4.1 ), ours is non-adaptive, in the sense that the flag measurement outcomes alone provide enough information to correct correlated errors; no extra syndrome measurement is required. 4.2.1 Notions We restrict to codes with odd distance d = 2t + l. We assume the uncorrelated stochastic Pauli error model. Namely, faults can occur in elementary operations: single-qubit preparations and measurements, single- and two-qubit gates, and idle positions. Our protocol measures one stabilizer generator at a time, like Shor's method. The flag circuit uses one syndrome ancilla and one or more flag ancillas. If there are no faults, measuring the syndrome ancilla gives the syndrome, and the flag ancilla measurement outcomes will be trivial. Definition 6. A flag syndrome-measurement circuit is d-FT if any k s; t faults result in at most k data errors, after corrections based on the flag pattern. For example, the circuit in Figure 3.4 is 3-FT for a weight-four stabilizer. An important observation is that one can construct a fault-tolerant error-correction protocol satisfying Definition 1 by measuring one stabilizer generator at a time, each using a d-FT flag circuit. Indeed, d-FT circuits automatically guarantee condition 1 of the criteria for error correction. One way to achieve 59 condition 2 is to keep measuring the syndromes until the same syndrome repeats consecutively a certain number of times without flags being triggered [Sho96]. Notice that Definition 6 is stronger than that of the t-flag circuit introduced by Chamberland and Beverland [CB18], which guarantees a nontrivial flag pattern whenever s :c; t faults result in more than s errors. In particular, they give a scheme for constructing a 2-flag circuit that requires five ancilla qubits; and give a conjectured scheme for constructing a general t-flag circuit that requires w ancilla qubits. In the remainder of the thesis, denote by Ii i the Hamming weight, and by f EB g the bitwise XOR, of binary strings f and g. Single-qubit measurements in diagrams without specifications are all in the Z basis (IO ), 1 1)). 4.2.2 Syndrome-extraction circuits and correction rules In this section, we present a flag circuit that measures a stabilizer of an arbitrary distance-d code. Without loss of generality, we may take the stabilizer to be X ®w . Figure 4. 9 illustrates the construction. A syndrome ancilla, initialized in I+), is coupled to the w data qubits with CNOT gates. Each of these CNOT gates is protected by a different set of d - l flags. Between CNOT gates to the data, the flags are carefully transitioned- with flag j for the next CNOT turned on just before flag j for the previous CNOT is turned off, for j E [d - 1]-so that there are always either d - l or d active flags, except at the very beginning and end. Observe that with fast qubit reset, this construction requires at most d flag ancillas, so d + l ancilla qubits total. Conjecture 7. With appropriate correction rules based on the flag pattern, the procedure of Fig ure 4- 9 is d-FT. A stronger statement might also hold. Based on computer analyses of circuits for d E {3, 5, 7} (see Section. 4.2.3), it appears that the data CNOTs toward the beginning or end require fewer flags: 60 data I I I I I (a) I I I I (b) I I I I Figure 4.9: (a) Distance-three fault-tolerant measurement of X ® 4 . Each CNOT to the data is protected by two flags. X corrections are applied based on the flag pattern. (b) Schematic showing how the circuit extends to X ®w and arbitrary distance d; control and corrections are omitted. Between each consecutive pair of CNOT gates to the data, d - 1 flags are turned on, and d - 1 turned off, in an alternating fashion: on, off, on, off. Figure 4.10: An optimized circuit for measuring X ® 10 . Note that the central data CNOT gates are protected by d - 1 flags, but fewer flags are used toward the ends. With appropriate correction rules, the circuit is fault tolerant to distance d = 5. 61 Figure 4.11: A syndrome fault can flip d - l or d flags. q l-q q l-q Figure 4.12: Syndrome faults spread to the data and flip intervals of flags. The correction algorithm uses the observed flag pattern, which can be further distorted by flag faults, to infer the syndrome faults' approximate locations. 0, 1, 2, ... ,d - 2,d - l,d- l , ... ,d - l,d - 2, ... , 2, 1,0 flags instead of always d - l flags. The first and last data CNOTs require no flag protection because a syndrome-ancilla fault immediately before or after these gates can propagate to an error of weight only O or 1. Moving toward the middle, the number of flags needed then steadily increases up to a maximum of d - l. Figure 4.10 shows an example, with w = 10 and d = 5. However, we will not attempt to prove Conjecture 7. Instead, in order to simplify the correction rules' boundary conditions, modify the scheme of Figure 4.9 by prepending r = (d + 1) 2 /4 rounds of d - l flags. That is, follow Figure 4.9 for a weight r + w stabilizer, except do not use data CNOTs in the first r rounds. We will show: Lemma 8. The modified procedure, with (d + 1) 2 /4 initial flag rounds and appropriate correction rules, is d-FT. 62 Let us first give some intuition. Distinguish possible circuit faults into syndrome faults and flag faults. Syndrome faults cause X faults on the syndrome ancilla; they can spread to correlated data errors. Flag faults are measurement faults on flag ancillas; they do not spread to the data. A syndrome fault can trigger d - 1 or d flags, as in Figure 4.11 , or < d - 1 flags on the left and right boundaries, as in Figure 4.9(a) . The motivation for the initial flag rounds is so that our correction algorithm, which works from left to right, does not need to account for left boundary conditions. Assume for the moment that every syndrome fault flips exactly d - 1 flags. Imagine laying the flags along the real line, so that successive flags cover consecutive intervals of length 1/(d - 1); then each syndrome fault flips an interval of length one. The up to t flag faults can further flip intervals with total length up to d~l = 1/2. As shown in Figure 4.12, the pattern of triggered flags depends on how the flipped intervals overlap. The correction algorithm needs to use the observed flags to deduce the approximate locations of the syndrome faults. It does not need to determine the exact locations because all that matters is how the faults propagate to data-qubit errors, via the upward data CNOTs located at integers on the line. Also, an even number of syndrome faults with overlapping intervals, as on the left side of Figure 4.12, does not require any data correction for fault tolerance. Proof of Lemma 8. We will give an explicit correction algorithm and then analyze it inductively. Since a syndrome fault can trigger flags in up to two consecutive flag rounds, with at least t(t-1+2)+t = t(t+ 2) initial flag rounds, there must be at least one sequence of at least t consecutive flag rounds in which no flags are triggered. Call this sequence the "start" rounds. Furthermore, the correction algorithm can identify start rounds without knowing the fault locations. (Although faults can cancel out, they cannot over such a long stretch. As on the right side of Figure 4.12, three syndrome faults cancel out over a length-one interval, more generally t faults can cancel out an interval of length at most t/2.) Having identified the start rounds, the algorithm discards all 63 flags to their left. (Faults on the syndrome ancilla before it interacts with the data do not cause any data errors.) For fault tolerance, it suffices to consider only syndrome and flag faults; any other fault either can be ignored or is equivalent to a syndrome or flag fault. Divide the faults after the start rounds into three sets: set F of flag faults , set Sd of syndrome faults flipping exactly d flags, and set Sd - I of syndrome faults either flipping d - 1 flags or on the last round. They satisfy IFI + ISdl + I Sd-11 :c; t. For instance, a YY fault on a data CNOT is in Sd-l· Now we specify our correction algorithm, and then prove that syndrome measurement is d-fault tolerant. The algorithm will work through the flags from the start rounds on, from left to right, interpreting one round of d - 1 flags at a time. Denote by Ji, h, ... E { 0, 1} 2 t the rounds of flags after the start rounds, Jc being the flags around data (or dummy) CNOT £, as in Figure 4.14. Let n be the rightmost nontrivial round, and define c E {O, 1 } 2 t, lei = 1 as the rightmost nontrivial flag of fn- mo+- 02t for i = 1, 2, ... , n do mi +- mi -1 EB Ji if lmil > t or (i = n, lmi l = t , lmi EB s l > t) then mi +- mi EB 1 2t corner-case fix Apply X to data CNOT targets from i onwards Figure 4.13: Correction rules for the syndrome-extraction circuit in Figure 4.9 to bed-FT. The algorithm deals with each round in the same way except round n. When i = n and lm;I = t, the corner-case fix effectively flips the rightmost nontrivial flag c. 64 f eEB f e =001111 f e+1 EB f e+1 = 110000 I I I I I I I I s £+1 £+2 Figure 4.14: If d = 7, s ES flips six flags in!£ and !£+ 1 . The proof proceeds by incorporating faults one at a time but with n and c fixed. We compare the algorithm's behavior before and after each fault is incorporated. For fault tolerance, we argue that the residual data errors after the corrections never outnumber the current faults. Split each fault in Sd into a d - l bit syndrome fault, plus one extra flag fault at the end. That is, define F to be the union of F and the rightmost bits from Sd, and let S be the union of Sd-l For the base case, we consider all the faults in F with no data errors. Define r 1 , ... , r 0 E {O, 1 } 2 t as the flag patterns flipped by faults in F. In subsequent inductive steps, we add faults in S, from left to right, one at a time. Suppose the added fault s occurs between data CNOTs £ and £ + 1, causing data errors PeXe+iXc+ 2 • • • for some PE { I, X, Y , Z}. We will prove, by induction in s, that for all i 2c: £ + 1, the value of mi when the algorithm finishes satisfies mi= E9}= 1 r 1 . (For the base case, set £ = 0.) Consider the base case of faults in F. Then Ji= ri. We claim that mi= E9}= 1 r 1 . This is clear since I E9}= 1 r 1 1 :c:; IFI :c::; t and so corrections are never triggered except possibly at round n. If lmo_ 1 EB ro I = t, then necessarily Sd-l = 0 and the flag c is attributed to the rightmost fault in F. In particular, Imo EB cl = t - l. Therefore, lmil or Imo EB cl never exceeds t, and the algorithm applies no corrections, as desired. 65 Now consider adding a syndrome fault s E S, between data CNOTs £ and £ + l. Define Ji and mi as the parameters of the algorithm (when finished) in the previous induction step, withouts. (See Figure 4.14 for an example.) Withs added, the algorithm's behavior does not change until i = £. (Recall that D and c are fixed.) Beyond £, the following observation will essentially finish the proof. Observation. In exactly one of the two rounds i =£and£+ 1 the algorithm changes its behavior: either applying the correction when it did not before, or vice versa. The algorithm's behavior remains unchanged for i 2c: £ + 2. Since s flips 2t flags, we have (le EB fe) EB (le+1 EB fe+i) = l 2t . ( 4.1) Note that me EB me-i EB fe E {1 2 t, 0 2 t}, depending on whether in round £, X data corrections are applied or not. To show the observation, we consider all possible scenarios. l. me EB me-i EB le-/=- me EB me-i EB fe, i.e., the correction behavior changes at round£. Since me-1 = me-1, we have me EB le EB me EB fe = 1 2 t. Adding (4.1) , me EB fe+1 = me EB le+1, and the algorithm's behavior does not change from round £+ 1 on. In particular, for i 2c: £ + 1, still mi = mi = EB;=l r 1 . The change of corrections XeXe+i · · · leaves at most one data error PeXe, as desired. 2. me EB me-1 EB le = me EB me-1 EB fe, i.e., the correction behavior does not change at round £. Adding me-1 = me-1 and (4.1) gives (me EB le+1) EB (me EB fe+1) = 1 2 t. We claim the correction behavior changes at round £ + 1, and so the change of corrections Xg+ 1Xg+ 2 · · · leaves at most one data error Pe, as desired. (a) lme EB le+il -/=- t. Then one of the terms me EB le+1 and me EB fe+i has weight > t and the other < t. The correction behavior changes in round£+ l. Thus, we have 66 me+i EB m e+i = (me EB !c+1) EB (me EB h+1) EB 1 2 t = 0 2 t and so m i = mi = EB;= l rj for i2:£+1. (b) lme EB !c+1I = t. Then lme+il = t. Then since m e+1 = EBi~i rj and I EBi~i rjl :c; IFI, we have Sd-l = 0. Therefore,£+ 1 = 0 and the corner-case fix is triggered in round £ + 1, both with and withouts. Since (me EB !c+1 ) EB (me EB h+1) = 1 2 t and lel = 1, { le EB me EB h+1I, le EB me EB !c+1I} = {t - 1, t + l}. As one of the terms has weight> t, the correction behavior changes in round £ + 1. When s occurs after the last data CNOT, it can flip fewer than 2t flags- but since it causes no data errors, it can be ignored. � Note that when the algorithm finishes I mo I is a lower bound of the number of faults that have occurred in the syndrome-measurement circuit. This information, combined with the measured syndrome, can be used to reduce the number of repetitions of syndrome measurements in ad-FT error-correction protocol [Sho96, Zal97, CB18]. We emphasize that for a weight-w stabilizer, it can incur at most w data errors. Hence it suffices to protect each data CNOT with 2t' flags, and to append t'(t' + 2) initial flag rounds to the circuit in Figure 4.9, where t' = min { t, w}. Namely, the total number of ancillas required by our protocol, given the ability of rapid qubit reset, is min{d + 1, 2w + 2}. Intuitively, it seems that our protocol might be optimal in the required number of ancilla qubits when w » d. Namely, in order to have an optimality argument that is rigorous to a least extent, we restrict the scope of protocols to those that are applicable to families of codes with asymptotically large stabilizer weights with respect to the distances. In particular, the number of required ancillas should reasonably be a constant with respect to w. In this case, there exists an ancilla a coupled via CNOTs with a subset of » d relevant data qubits. A fault on a can result in disastrous correlated errors. Hence the flags triggered by such a fault, corrupted by up to t - 1 flag faults, should be distinguishable from a flag pattern with t flag faults. Thus a should be 67 protected by at least (t - 1) + t + 1 = d - 1 flags. The number of flags protecting o: changes by one at a time, so in order to keep at least d - 1 flags on it, at some time it is protected by d flags. In total, counting o:, at least d + 1 ancillas are needed for the flag circuit to be d-FT. We remark that it seems that the only case, if any, that our error-correction scheme could be practical is when w » d. Indeed, when for example 2w + 2 :S: d + 1, our scheme requires roughly as many rounds of syndrome extractions as Shor's scheme, whereas using roughly twice as many ancillas. Furthermore, our scheme consumes a substantial amount of CNOT gates; denoting t' = min{t,w}, each syndrome-extraction circuit has t'(t' + 2) + w flag rounds and each round opens/closes 2t' flags. In particular, we do not expect our protocol to be applicable to quantum low density parity check (LDPC) codes or topological codes. An open problem is to reduce or even remove the initial flag rounds in our scheme while remaining d-FT, as in Conjecture 7. This might require drastically different correction rules. It would also be interesting to optimize our circuit construction and correction rules for specific code families, and qubit geometry and connectivity constraints. Compared with the flag schemes in Section. 4.1, our scheme in Figure 4.9 requires substantially more flag ancillas and qubit resets. This can be seen as a sacrifice of overhead for generality. In Chapter 7, we will address the scenario of slow qubit resets, i.e., the time for qubit preparation and measurement is much longer than that for gate. In particular, we will give error-correction schemes with reduced number of ancillas which are measured only once at the end of circuits. 4.2.3 Computer search for correction rules Given an arbitrary flag circuit that measures a stabilizer generator of a specific code, it is generally difficult to tell whether there exist correction rules to achieve fault tolerance. The pseudocode in Figure 4.15 runs a brute-force search for d-FT correction rules, given a flag circuit C as input. Again, the stabilizer is taken to be X ® w, without loss of generality. 68 In the pseudocode, flag and error denote the flag pattern and data error pattern resulting from a set of circuit faults, respectively. Recall that C consists of only one syndrome ancilla, possibly multiple flag ancillas, and only CNOT gates. Any relevant fault in C is equivalent to some element of F, except for two-qubit faults on data CNOTs, with X on the control and PE {I, X, Y, Z} on the target- we account for them with the subset F *. V is a dictionary whose keys are possible flag patterns generated by combinations of at most t faults. The value of each key contains all the fault combinations that generate the corresponding flag pattern. There exist d-FT correction rules if and only if for each key-value pair (k, v) E V there exist consistent corrections for fault combinations in v. Specifically, for each F E v, SF contains all the valid X data corrections for F , in form of binary strings. Indeed, Q = [w] \ Q contains all the data qubits whose errors are unknown Paulis, thus corrections on Q can be arbitrary. However, corrections on Q should remove sufficient errors so that the residual data error EQ has weight no greater than IF\ F * I- Conditioned on success, the code returns a set R of valid correction rules indexed by the observed flag pattern. 69 Input: t, C Let: F = set of faults in C consisting of • X faults just before every data or flag CNOT control • X faults on every flag measurement Let: F* CF be the faults before the data CNOT controls D +- { (k, v) Iv= {F CF I flag(F) = k, IFI < t}} R+-0 for (k, v) in 'D for F in v Q +- { data qubits not targeted by CNOTs in F n F*} Sp+- {error(F) EB E IEE {O, l}w, IEQI <IF\ F*I} R[k] +-nFEvSF if R[k] = 0 return Fail Figure 4.15: P seudocode for searching for correction rules for a given flag circuit for a specific code to be d-FT. 70 Chapter 5 Flag fault-tolerant computation In Section. 1.2 and Section. 3.2.2, we have given cursory descriptions of how to construct flag gadgets for CZ and CCZ gates and combine them with error correction to fault-tolerantly compute. In this chapter we expand all the details, which are entirely drawn from [CR18a]. In fault-tolerant schemes for computation, multiple physical qubits are needed for each logical qubit. For example, one qubit encodes into seven physical qubits using the Steane code [Ste96a], or into nine physical qubits using the Bacon-Shor and smallest surface codes [Bac06, BMD07, HFDVM12]. These schemes do not take advantage of the most efficient, high-rate quantum error-correcting codes. More efficient codes are excellent choices for storing quantum memory or communicating quantum information over a noisy channel. However , for a fault-tolerance scheme, we need to be able to compute on the encoded data without giving up the code's protection. Implementing certain joint operations can be easy; for example, for any CSS code, transversal physical CNOT gates between two code blocks, i.e., for all j a CNOT from qubit j of the first block to qubit j of the second block, implement transversal logical CNOT gates. It is difficult, though, to address separately the logical qubits encoded in a code block, e.g., to implement a logical CNOT from logical qubit j of the first block to logical qubit j' of the second block. 71 Gottesman [Got98b] has proposed a method for isolating a single logical qubit by teleporting it into a fresh code block in which the other logical qubit positions are unused, computing on it there, and teleporting it back. This gives up the efficiency of the code, but if only a few operations are scheduled in the quantum computer at a time, then it may be acceptable to devote a few full code blocks to single logical qubits. If many operations are scheduled in parallel, however, then this scheme generates a significant space overhead. The amount of parallelism depends on the quantum algorithm being run. Steane and Ibinson [S105] have studied this scheme further , and combined it with computation by teleportation [GC99] to reduce the time overhead of Gottesman's scheme. The effect of their extensions on the space overhead, which is more critical, depends on the logical operation. For a logical CNOT gate between two logical qubits stored in the same code block, they reduce the overhead from two to one extra code blocks, and for a logical CNOT gate between logical qubits stored in different code blocks, they do not reduce the space overhead. The balance of logical CNOT gates between versus within code blocks depends on the compilation of the quantum algorithm, and how the logical qubits are arranged in the code blocks. Brun et al. [BzH+ 15] propose a scheme for universal computation using CSS block codes that encode multiple logical qubits into individual code blocks. Specifically, they store logical qubits into large CSS block codes and perform Steane's error correction const antly. The logical Clifford gates are realized by sequences of direct measurements of logical Pauli operators. The logical non-Clifford T gate is implemented by first teleporting the target logical qubit into a fresh ancilla block of code that encodes a single logical qubit and supports transversal logical T gate, e.g. , the [15, 1, 3] Reed-Muller code. The logical qubit is then teleported back after the transversal gates. They reduce the qubit overhead to tens of physical qubits per logical one for implementations of certain practically interesting quantum algorithms. Due to the substantial measurements of stabilizers and logical operators, as well as teleportations, their scheme requires extensive fault-tolerant preparations of ancilla blocks of logical states, which can be implemented in a scalable and efficient way, e.g. , using the techniques in [ZLB18]. 72 Gottesman [Got14] gives a scheme for universal quantum computation that permits constant accuracy threshold. His scheme applies to LDPC codes with certain good properties and incurs only a constant qubit overhead when the code size goes asymptotically large. In this chapter, we introduce lower-overhead flag schemes for computing fault-tolerantly on multiple logical qubits in single blocks of codes of distance two or three. 1. For even n, the [n, n - 2, 2] code encodes n - 2 logical qubits into n physical qubits, protected to distance two. In Section. 5.2, we show that with two more qubits, encoded CNOT and Hadamard gates can be applied fault tolerantly. For n :::,: 6, four extra qubits suffice to fault-tolerantly apply an encoded CCZ gate, for universality. Our scheme is fault-tolerant by the criterion in Definition 4. 2. For better, distance-three protection, in Section. 5.3 we encode seven qubits into 15, and give fault-tolerant circuits for the encoded Clifford group using two more qubits, and for a universal gate set with four extra qubits (19 total). Our scheme is fault-tolerant by the criterion in Definition 3. Combined with the two-qubit flag fault-tolerant error-detection and error-correction methods in Section. 6.1 and Section. 4.1, this means that substantial quantum calculations can be imple mented fault tolerantly in a quantum device with fewer than 20 physical qubits. Figure Figure 5.1 summarizes our results. Our constructions consist of two stages- first devise physical circuits that have desired logical effects and then render them fault-tolerant. The particular physical circuits that we use are composed of Paulis, CZ and CCZ gates, which have certain favorable properties as discussed in Section. 3.2.2. To analyze their logical effects, we leverage symmetries of the codes or a more general round-robin design from [YTC16]. These circuits are not fault tolerant, because a single gate failure can cause a correlated error of weight two or worse, which a distance-three code cannot correct. To fix this, we replace each multi-qubit gate with a gadget involving two to four more 73 00 d=2 ----+ 00 d= 2 00 ----+ ------------------ o0aod=3 o 0 o _, Logical qubits 00000 00000 + 00000 Code qubits Ancilla qubits Figure 5.1: Summary of our flag schemes for logical computation. Using two extra qubits, one can apply fault tolerantly either encoded CNOT and Hadamard gates or the full Clifford group. Four extra qubits are enough for fault-tolerant universal computation. qubits. With no gate faults, the gadgets are equivalent to the ideal gates they replace. The gadgets' purpose is to detect correlated errors, so that they can be corrected for later. The gadgets cannot prevent the gates from spreading single-qubit faults into problematic multi-qubit errors. To remedy error propagation, we intersperse partial error correction procedures between gadgets, an idea from [KLZ96] recently applied and extended by [HFWH13, YTC16]. Sometimes error correction even needs to overlap the gadgets. 5.1 Flag gadgets for CZ and CCZ A main trick we use is to replace CZ and CCZ gates with small gadgets that can catch correlated faults. The gadgets are reminiscent of one-ancilla-qubit fault-tolerant SWAP gate gadgets [ GotO0]. 74 Figure 5.2: A CZ gadget. The two gadgets in Figure 3.7 can be combined to catch all two-qubit correlated faults (Theorem 9). 5.1.1 CZ gadget Recall that in Section. 3.2.2, we have introduced two gadgets in Figure 3.7 that respectively catch X and Z error components arising from a single fault on a CZ gate. These two gadgets can be combined: Theorem 9. With no faults, the circuit of Figure 5.2 implements a CZ gate, with the measurements outputting + and 0. If there is at most one fault and the measurements return + and 0, then neither XX , XY, Y X, YY nor Z Z errors can occur on the output. Thus all single faults are caught except those equivalent to a fault on the CZ output or input qubits (namely, IX,IY,IZ,XI ,YI ,ZI and XZ,YZ,ZX,ZY). No CZ gadget can catch more errors than this. The order of the gates matters. Although the last two gates in Figure 3. 7(b) formally commute, switching them changes the faulty circuit so that an undetected Z Z error can occur due to a single gate fault. Similarly, in Figure 5.2 it is important that the gadget for catching Z faults go inside that for X faults. With the other order, a single fault can lead to an undetected XX error. See Figure 5.3. In practice, not every CZ gate need always be replaced with the full CZ gate gadget of Figure 5.2. Multiple gates can sometimes be combined under single flags. We will see examples below. 75 I+) l cl:I ;,c+/ I : (a) (b) Figure 5.3: Invalid CZ gadget constructions. IO) 0 / 1 I+)---------- + / - IO) 0 / 1 I+) +/- Figure 5.4: A flag gadget that implements CCZ on the black data qubits. 5.1.2 CCZ gadget Recall that in Section. 3.2.2 we have mentioned that CCZ commutes with Z errors, and copies an X error on the input into a CZ = ½(II + IZ + ZI - ZZ) error on the output, i.e., into a linear combination of II, IZ, ZI and ZZ errors. The gadget in Figure 5.4, using four ancilla qubits, implements a CCZ on the black data qubits. Furthermore, it satisfies that provided there is at most one failed gate and the mea- surement results are trivial, 0 and +, then the error on the output is a linear combination of P aulis that could result from a one-qubit fault before or after a perfect CCZ gate, i.e., III,IIZ,IIX,IIY,IZX,IZY,ZZX,ZZY and qubit permutations thereof. That without faults the black and blue gates realize a CCZ is a special case of the following claim [YTC16], with r = 3, Sf = {2, 3}, Sf = {5, 6}, Sf = {7}. Claim 10. Consider an n-qubit CSS code with k encoded qubits given by X\ = X 5 x , Z 1 = Z 5 z J .1 for Sf, Sf ~ [n]. Let U be the product of c(r- l) Z = 1 - 2jF )(lr l gates applied to every tuple of 76 qubits in Sf x Sf x · · · x S; . (If the Sf sets are not disjoint, then some of the applied gates will be c (s- i ) Z for some s < r.) Then U is a valid logical operation. It implements logical c (r -l) Z on the first r encoded qubits. Proof. For the case that the sets Sf are disjoint, the claim is immediate in the case of singleton sets and follows in general by induction on t he set size using the identity (5.1) for any gate G, on one or more qubits, with G 2 = 1. (Figure 3.7(b) provides one example.) More generally, the claim follows by writing out computational basis codewords as superpositions of computational basis st ates, and computing the effect of U. For ( x, y) E { 0, 1 Y x { 0, 1 }k-r, the codeword lxy) is a uniform superposition of computational basis states: r k lxy) ex IT X ? IT j = l i=r+ l XY i - r ' stabilizers X s (5.2) The relationships Xizj = (- l)"'j zjxi imply that I Sf n s f I is odd for i = j and even otherwise; and for any stabilizer Xs , [X s , Z 1 ] = 0 so IS n Sf I is even. If x -/- F , say x 1 = 0, then for every term lz) in the above sum, z has an even number of l s in Sf , implying that Ulz) = lz) . Hence Ulxy) = lxy). If x = lr , then for any term lz) in lxy), z has an odd number of ls in each Sf and therefore Ulz) = -lz) . Hence Ulxy) = -lxy). � 5.2 Flag computation for [n, n - 2, 2] codes For even n , the [n, n - 2, 2] error-detecting code has stabilizers X ®n and z @n, and logical operators X 1 = X1Xj+1, Z 1 = Z j+1Zn for j = 1, ... ,n - 2. This code, its symmetries, and 77 methods of computing fault tolerantly on the encoded qubits were studied by Gottesman [Got98b]. However, his techniques require at least 2n extra qubits. For example, to apply a CNOT gate between two logical qubits in the same code block, he teleports them each into separate code blocks, applies transversal CNOT gates between the blocks, and then teleports them back. We will give a fault-tolerant implementation of encoded CNOT and Hadamard gates on arbitrary logical qubits, using only two extra qubits. Two-qubit fault-tolerant procedures for state preparation, error detection and projective measurement are given in Chapter 6. For n 2". 6 (so there are at least three encoded qubits), we will give a four-qubit fault-tolerant implementation of the encoded CCZ gate, thereby completing a universal gate set. 5.2.1 Permutation symmetries and transversal operations Fault tolerance for a distance-two code means that any single fault within an operation should either have no effect or lead to a detectable error. For example, of course the 4n- 2 logical Pauli operators can all be applied fault tolerantly, since the operations do not couple any qubits. All qubit permutations preserve the two stabilizers and therefore preserve the code space. They are also fault tolerant if implemented either by relabeling the qubits or by moving them past each other (and not by using two-qubit SWAP gates [ GotO0]). For i,j E [n - 2], i-=/- j , the qubit swap (i + 1,j + 1) swaps the logical qubits i and j. The qubit swap (1, 2) implements logical CNOTs from qubits 2 through n - 2 into 1, and the qubit swap (2, n) implements logical CNOTs in the opposite direction: and (5.3) Transversal Hadamard, H ®n, followed by the qubit swap (1, n) , implements logical H ®(n- 2 ). 78 k Sk GL(k, 2) (CNOT,H) Ck/P£ 1 1 xl x2 x 3 2 2 x 3 x12 xlO 3 6 x28 x240 x36 4 24 x840 xl 7280 x136 5 120 x 83328 x 4700160 x 528 6 720 x27998208 X 4963368960 x2080 7 5040 x 3.2 • 10 10 x2.1 • 10 13 x 8256 8 40320 X 1.3 · 10 14 x3.4 • 10 17 x32896 Table 5.1: Sizes of the k-qubit Clifford group and subgroups. There are I Sk l = kl permutations of k qubits. P£ = Pk/{±l, ±i}. CNOT gates generate a group of size IGL(k, 2) 1 = rr;: ~(2k - 2 1 ) , adding Hadamard gates generates a larg;er group, and finally the full Clifford group, up to the IP£ 1 = 4k phase-less Paulis, has size 2k IT]= 1 (4k - 1). The sizes are given as multiples of the previous columns, e.g., I C 2/ P~ I = 2 x 3 x 12 x 10 = 720. The Clifford reflection G = ,12(X + Y) conjugates X +-+ Y and Z-+ - Z. Transversal G is a valid logical operation (up to Zn to correct the X ®n syndrome if n = 2 mod 4). It implements logical CZ gates between all encoded qubits: (5.4) The operations given so far generate a group much smaller than the full (n - 2)-qubit Clifford group. The qubit permutations generate n! different logical operations ( except for n = 4, just 6 operations). With the transversal application of the six one-qubit Clifford gates, up to Paulis, this gives 6(n!) different logical operations (or 36 for n = 4). Table 5.1 gives the sizes of various interesting subgroups of the Clifford group, for comparison. We next give fault-tolerant implementations for a logical Hadamard gate on a single encoded qubit, and for a logical CZ gate between two encoded qubits. These generate a large subgroup of the Clifford group, the (CNOT, H ) column in Table 5.1. 79 5.2 .2 CZ gate By Claim 10, a logical CZ1,2 gate can be implemented by Zn CZ2,3 CZ2,n CZ3,n : physical ~ J:1= n ciJll logical t X (5.5) However, this implementation is not fault tolerant. Some failures are detectable; for example, if the CZ2,3 gate fails as XI , then the final, detectable error is X 2 Zn. Others are not, e.g., if the CZ2,3 gate fails as XX , then the final X 2X 3 = .X\.X2 error is undetectable. The bad faults that can cause undetectable logical errors are as follows: CZ2,3 CZ2,n cz3,n Fault Error Fault Error Fault Error zz Z2Z3 zz Z2Zn zz Z3Zn xx X2X3 XY X2Z3Yn xx X3Xn yy Y2Y3 YX Y2Z3Xn yy Y3Yn In particular, all these bad faults are caught by the CZ gadget of Theorem 9. Therefore replacing each physical CZ gate in (5.5) with that gadget gives a fault-tolerant implementation of a logical CZ 1,2 gate. The circuit uses at most two ancilla qubits at a time. In fact, one can simplify the resulting circuit by using the same IO) ancilla to catch X faults on multiple CZ gates. The following circuit is also fault tolerant: 2 3 IOi-++-1---------------+++-0/ l n --------------- - --- ++-1--t--t- ----- 80 (5.6) The gadgets to catch Z faults can be merged, too. The following circuit is fault tolerant, and still requires at most two ancilla qubits at a time: I 0H+1-----------+1rr o /1 2 3 n -------------..-- -.- -t-t1"""11.--t--t-t-:,--- - -- Io i""t"t'.t----------t1tr o / 1 Perhaps further simplifications are possible. 5.2.3 Targeted Hadamard gate (5.7) A single encoded Hadamard gate can also be implemented fault tolerantly with two extra qubits. The black portion of the circuit below, with =t = ~ =:$ti!: , implements H 1 . The red and blue portions, analogous to Figure 3.7(a) and Figure 3.7(b) , respectively, catch problematic faults. X measurements should return + and Z measurements 0. 1 2 n - +1-~ a.--1-+i,.;"-----.._ .......... .._ __ --411--1 (5.8) The circuit's fault tolerance can be verified by enumerating all the ways in which single gates can fail. 81 5.2.4 Four-ancilla CCZ gate For n 2'. 6, a CCZ gate on encoded qubits 1, 2, 3 can be implemented by round-robin CCZ gates on {2,n} x {3,n} x {4,n}, by Claim 10: 2 3 4 n ~ (5.9) This circuit uses one Z, three CZ and four CCZ gates. To make it fault tolerant, use the gadget from Figure 5.2 for each CZ gate, and replace each CCZ with the gadget of Figure 5.4. Overall, this requires four ancilla qubits. Single gate faults are either caught by the gadgets or lead to an error that could also arise from a one-qubit fault between the gates in (5.9) . A one-qubit X or Y fault will be detectable at the end because it is copied only to linear combinations of Zs- the X component of the final error will still have weight one-and a one-qubit Z fault will be detectable because it commutes through the CZ and CCZ gates. Therefore the procedure is fault tolerant. 5.3 Flag computation for the Hamming [15, 7, 3] code The [15, 7, 3] Hamming code is a self-dual CSS, perfect distance-three code. Packing seven logical qubits into 15 physical qubits, it is considerably more efficient than more commonly used [7, 1, 3] and [9, 1, 3] CSS codes, although it tolerates less noise. We first give a presentation of the code and its symmetries following [HRll]. Then we give a two-ancilla-qubit method for fault tolerantly implementing the full Clifford group on the encoded qubits, and, to complete a universal gate set, a four-qubit fault-tolerant encoded CCZ gate. Two-qubit fault-tolerant procedures for state preparation and error correction were given in Section. 6.2.2 and Section. 4.1. 82 5.3.1 [1 5, 7, 3] Hamming code The [15, 7, 3] Hamming code has four X and four Z stabilizers each given by the parity-checks in Figure 4.2(a) . Index the qubits left to right from 1 to 15. Observe that the columns are t hese numbers in binary. As in [HRll ], we define logical operators based on the following seven weight-five strings: 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 0 1 0 0 (5.10) 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 From the first string, .X1 = XXIXIIIXIIIIIIX and Z1 = ZZIZIIIZIIIIIIZ. The remaining strings specify the logical operators X 2 , Z 2 through X 7 , Z 7 . 5.3.2 Transversal operations Transversal operations are automatically fault tolerant. Transversal Pauli operators implement logical transversal Pauli operators. Indeed, transversal X, i.e., X ® 15 , preserves the code and implements transversal logical X , i.e. , X ® 7, on the code space, and similarly for Y and Z. In fact , any one-qubit Clifford operator applied transversally preserves the code space and implements the same operator transversally on the encoded qubits. For example, since the logical operators are each self-dual, applying the Hadamard gates H ® 15 implements logical H ® 7 . 83 Of course, since the code is CSS, transversal CNOT gates between two code blocks implements transversal logical CNOT gates on the code spaces. Furthermore, [PR13] shows that on three code blocks transversal CCZ can be used to obtain a universal gate set. Here, however, we will consider only single code blocks and Clifford operations. 5.3.3 Permutation symmetries Permutations of the qubits are also fault tolerant, either by physically moving the qubits or by relabeling them. The code's permutation automorphism group has order 20,160, and is isomorphic to A 8 and GL(4,2) [HR11 , GR13]. It is generated by the following three 15-qubit permutations: a 1 = (1,2,3)(4, 14, 10)(5, 12,9)(6, 13, 11)(7, 15,8) a 2 = (1,10,5,2,12)(3,6,4,8, 9)(7,14,13,11,15) a 3 = (1,10,15,3,8,13)(4,6)(5 , 12, 11)(7, 14, 9) (5.11) These permutations fix the code space, but act nontrivially within it. The permutations a 1 and a 2 apply the respective permutations (1, 2, 3) and (3, 4, 5, 6, 7) to the seven logical qubits. Together, these generate the alternating group A 7 of even permutations. The logical effect of a 3 is not a permutation. It is equivalent to the following circuit of 24 CNOT gates, in which gates with the same control wire are condensed: (5.12) 84 1 2 3 (Y-1(1)=:!r 4 5 6 a-( i) 7 (a) (b) Figure 5.5: (a) If a is a permutation automorphism for a self-dual CSS code, then applying CZ gates along its cycles fixes the code space (Claim 11). (b) The logical effect for CZ gates following the permutation a3. Thus the first logical qubit is fixed , while for j E {2, ... , 7} and P E {X, Y, Z} , P 1 is mapped to (IT;= 2 P 1 )P 1 +1, wrapping the indices cyclically. This is a six-qubit generalization of a four-qubit operator studied in [Got98b, Section 6]. (Like permutations, this operation has the property of being a valid transversal operation on any stabilizer code.) 5.3.4 CZ circuits based on permutation symmetries Any permutation symmetry of the code can be turned into a CZ automorphism (Figure 5.5(a) ): Claim 11. For a self-dual CSS code, if a is a qubit permutation that fixes the code space, then the circuit with a CZ gate from i to a(i) , for all i -/=- a(i) , fixes the code space up to Pauli Z corrections. Proof. Z stabilizers commute with the CZ gates, so are preserved. An X stabilizer Xs = ITiES X i is mapped to rr iES (X; Zo-(i)Za-- l (i) ) = ± XsZa-(S) u o-- ' (S)· Up to sign, this is a stabilizer , since � For example, the physical circuit in (5.5) comes from the cyclic permutation (2, 3, n) of the [n, n - 2, 2] code. 85 Applying Claim 11 to CJ3 of (5.11) , the two CZ gates for the cycle (4, 6) cancel out, leaving the gates (CZ1,10CZ10,15 · · · CZ13,1)(CZ5,12CZ12,11CZ11,5) .... As shown in Figure 5.5(b) , the effect is that of logical CZ gates following the cycle (2 , 3, 4, 5, 6, 7). Notice that the logical effect necessarily consists of encoded CZ gates, because logical Z opera tors are unchanged and logical X operators pick up Z components. Also, the map from Claim 11 is not a homomorphism from permutations into unitary circuits. 5.3.4.1 CZ gates {8, 9} to {10, 11} and {12, 13} to {14, 15} The permutation (6, 7)(8, 10, 9, 11)(12, 14, 13, 15) fixes the code, and under Claim 11 corresponds to the eight CZ gates of Figure 5.6(a) . Figure 5.6(b) gives their logical effect. Using Magma [BCP97], we compute that the group generated by this operation, the permuta tions CJ1, CJ2, CJ 3 , and transversal H has the same size as the (CNOT, H ) group on six qubits (about 1.001 • 10 20 ). (Adding transversal G only triples the group size.) This hints that by working in a logical basis in which one qubit has X = X ® 15 and Z = Z ® 15 (operators fixed by the permutations and by Figure 5.6(a)), perhaps arbitrary combinations of CNOT and H can be applied to the other six qubits. But no, only half the (CNOT, H ) group can be reached. The circuit of Figure 5.6(a) is clearly not fault tolerant. (For example, an XX fault after the CZg,11 gate gives the error XgX11 , which is indistinguishable from X2.) We can use the gadgets from Figure 3.7 and Figure 5.2 for each CZ gate to obtain the circuit of Figure 5.6(c) , shown with the trailing error correction. Two ancilla qubits are needed. We claim that this compiled circuit is fault tolerant. This means that if the input lies in the code space, the compiled circuit has at most one fault (a two-qubit Pauli fault after a gate, or a one-qubit fault on a resting qubit), and the subsequent error correction is perfect; then the final outputs lie in the code space with no logical errors. To verify fault tolerance, there are two cases to check. 86 i i=++;; 11~ 12§ 13 14 15 (a) 10 ) " ' .., I+) +)- I - +/- I - 8 9 10 11 ...... - ~ , " ...... 10 ) I I'\ .. "" ...., I+) 12 13 14 15 ... +)- ·i - +/- I " ...., ...., .. -.. -.. ... - 1 2 3 4 5 6 - I - - I - 7----------- (b) , 0/ 1 ,,, +/- l+1 +/- +1 +/- 11'\ - ,, ,, ,, .. I ' ' ~ - , ' I0' , ' I ' I ' ,, 0/ 1 ' +/- I+ '. +/- +; +/- " " " - , , ...)., ., I ' ' ~ - , ' 101 ~,, ' ,, (c) ..... - .... - ' .... - ' .. - - ' .. - - ' ... - - , ' ... - ~ - , ' 0 •.--i ..+,,;) u Cl) ..L. ~ ~ - ~ 0 u - ~ ~ - ~ 0 - ,, ~ 0/ 1 ~ ~ .... - ' .. - - ' .. - - ' ... - - , ' 0/ 1 Figure 5.6: The physical CZ gates in (a) have t he logical effect of (b). (c) The circuit can be made fault tolerant by replacing the CZ gates with the gadgets from Figure 3.7 and Figure 5.2, and simplifying. 87 First, consider the case that, with at most one fault, all the gadget measurements give the trivial output (0 for a Z measurement, + for X). Since the gadgets catch two-qubit gate faults, we need only check possible one-qubit faults between gates. Inequivalent fault locations are marked with stars in Figure 5.6( c) . (Faults at other locations either cause the same errors, or will be caught.) In particular, entering error correction the possible error can be 1, X 1, Z1,Y 1, ... ,X15,Z15,Y 15-from the * locations. Or, from * locations, it can be XIZZ,YIZZ,IXZZ,IYZZ,ZZXI,ZZYI,ZZIX, ZZIY, and IZXI,IZYI,IZIX,IZIY from * locations, on qubits 8, 9, 10, 11- and similarly for qubits 12 to 15. This give 70 different errors total. All 70 have distinct syndromes, and therefore can be corrected. (This fact can be verified either by computing all the syndromes, or by observing from Figure 4.2(a) that Z8Z9Z 10Zn, Z12Z13Z14Z15, Z1Z6Z1, Z1Zs Z9 , Z1Z12Z13 and Z1Z14Z15 are logical operators. Thus, for example, if you observe the Z syndrome 1000, for error X 8 , and the X syndrome 0001, for error Z 1 , you can safely correct X 8Z1 0Zn. Z1X 8 cannot occur.) Note that the error-correction procedure needs to t ake into account the X and Z stabilizer syndromes together to decide what correction to apply. This can work because the [15, 7, 3] code is not a perfect stabilizer code: there are 2 8 possible syndromes but only 1 + 15 • 3 possible trivial or weight-one errors. (It is only perfect as a CSS code, i.e. , the 2 4 Z stabilizer syndromes are exactly enough to correct the 1 + 15 possible trivial or weight-one X errors, and similarly for Z errors.) This leaves room to correct some errors of weight more than one. Next, consider the case that, with at most one fault in Figure 5.6(c), one or more of the gadget measurements gives a nontrivial output. This case is much simpler, because the measurement results localize the fault, leaving only a few possibilities for the error entering error correction. One must verify that in all cases, these possibilities are distinguished by their syndromes. 88 For example, if the first Z measurement returns 1 and all other measurements are trivial, the errors from single faults that can occur are, on qubits 8, 9, 10, 11: IIII, ZIII, XIII, YIII , XIIZ, YIIZ, XIZZ, YIZZ, XZIX, XZIY, XZXZ, XZYZ, YZIX,YZIY,YZXZ, YZYZ These 16 possible errors all have distinct syndromes, so are correctable. (5.13) As another example, if the last two measurements, of qubits coupled to qubit 13, are nontrivial, then the possible errors from single faults are, on qubits 12, 13, 14, 15: IXII , IY II, IXIZ, IYIZ, IXIX, IXIY (5.14) Again, these have distinct syndromes. Other possible measurement outcomes are similar. We have used a computer to check them all. 5.3.5 Round-robin CZ circuits to complete the Clifford group The above operations do not generate the full seven-qubit logical Clifford group, and we have not been able to find a permutation for which applying Claim 11 enlarges any further the generated logical group. Instead, we turn to the round-robin construction of Claim 10. 5.3.5.1 CZ gates 4 to {5, 6, 7}, 8 to {9, 10, 11}, 12 to {13, 14, 15} Observe that Z{4,s ,12} and Z{4,5,6,7} ~ Z{s ,9,10,11} ~ Z{12,13,14,15} are logical operators, imple menting respectively Z{2, 5 , 7 } and Z{l,2 ,3 ,4}· By a minor extension of Claim 10, applying Z{ 4 ,8 ,12 } 89 IO) 0/ 1 0/ 1 IO) 0/1 4 5 6 7 0/ 1 IO) 8 9 10 11 IO) 0/ 1 0/ 1 IO) 0/1 12 13 14 15 Figure 5.7: Blue gates implement the logical gates as in (5.15) . Orange and red gadgets catch X faults. and nine CZ gates from 4 to each of qubits {5, 6, 7}, 8 to {9, 10, 11}, and 12 to {13, 14, 15} preserves the code space. See Figure 5.7. The logical effect is 1 2 3 4 5 6 7 - ~ - - I - (5.15) Together with permutations and transversal operations, this circuit completes the seven-qubit Clifford group, without needing the operation from Section. 5.3.4. To make the operation fault tolerant, we will transform it in three steps. 90 First, consider Figure 5.7, in which we have wrapped the CZ gates leaving qubits 4, 8 and 12 with overlapping gadgets to catch X faults. If at most one fault occurs and one or more of the Z measurements gives 1, then the errors that can occur are distinguished by their syndromes. For example, if the orange, first Z measurement off qubit 4 gives 1 and all others 0, then the possible errors entering error correction are, on qubits 4, 5, 6, 7: IIII, ZIII , XIZZ, XXZZ , XYZZ , XZZZ YIZZ,YXZZ , YYZZ , YZZZ These errors all have distinct syndromes. (5.16) The circuit in Figure 5.7 is not fault tolerant, however, because with at most one fault if all the Z measurements give 0, some inequivalent errors will have the same syndrome. We can list the problematic errors. For each of the following sets, the errors within the set are all possible, but have the same syndrome: {Z1 , Z4Z5 , ZsZg, Z12Z13} {Z2, Z4Z6 , Zs Z10 , Z13Z14} {Z3, Z4Z1 , ZsZn , Z12Z15} {X4, Y4Z5Z6Z1 }, {Y4, X4Z5Z6Z1} {Xs , Y sZ9Z10Zn}, {Y s, X sZ9Z10Zn} {X12, Y12Z13Z14Z15}, {Y12, X12Z13Z14Z15} (5.17) Next replace each of the blue CZ gates in Figure 5.7 with the Z Z fault gadget from Figure 3. 7(b) . This gadget has the property that, with at most one failure, a Z Z fault can only occur if the X measurement returns - . These measurements thus distinguish the errors in the first three sets above. 91 Yet the new circuit is still not fault tolerant. The gadget measurements cannot distinguish the errors in each of the last six sets in (5.17) . For example, consider an X 4 error before the circuit. It a Y4 error after the circuit, and no error-correction rules can correct for the possible logical error. Gadgets cannot protect against single-qubit faults that occur just before or after the circuit. This circuit is qualitatively different from the one we considered in Section. 5.3.4, and a new trick is needed to make it fault tolerant. Consider the following circuit, which is similar to the one in Figure 4.2(b) , ignoring for now the orange portion at top right. 4 5 6 7 12 13 14 15 .,,.. T - .... .... .... ., ., ., 0) r'\ ., - 'r - .,,.. ,. T ' - 0/1 +/- (5.18) This circuit fault-tolerantly extracts the syndrome of the Z{ 4 , 5 , 6 ,7 ,12 , 13 ,14 ,15 } stabilizer, in the sense that: • With no gate faults, the Z measurement gives the syndrome, and the X measurement gives+. • With at most one fault, if the X measurement gives +, then the data error has weight :c; l. 92 • With at most one fault, if the X measurement gives -, then the X component of the data error has weight :s; 1. The Z component can be any of Z4, Z{4,5}, Z{4,5,6}, Z{4,5,6,12} , Z{4,5,6,1,12} ~ Z{13,14,15} , Z{4,5,6,1,12,14} ~ Z{13,15}, Z{4,5,6,1,12,13,14} ~ Z1s, 1 (5.19) and these errors all have distinct syndromes. (The order of the CNOT gates ensures this property.) In Section. 4.1, this circuit was used in a two-ancilla-qubit fault-tolerant error-correction procedure. The circuit in (5.18) is useful for us now to detect an X 4 or Y4 error on the input to Figure 5. 7. However, it is not enough to measure the Z syndrome, or even to run full error correction, before applying the circuit Figure 5.7, because an X 4 or Y4 fault could happen after the syndrome measurement completes and before Figure 5.7. This problem is solved by the orange portion of (5.18) , which is meant to continue into Figure 5.7, replacing the first IO ) preparation and CNOT. It gives qubit 4 temporary protection, so that an X 4 or Y4 fault is caught by either the syndrome measurement or the orange Z measurement, or both. While the above arguments give intuition for the construction, they leave out the details. Let us now present the full fault-tolerant construction. 1. Start by applying (5.18) to extract the syndrome for Z{4,s,6,7 , 12,13,1 4, 15 }· If the Z or X measurement is nontrivial, then decouple the orange qubit with another CNOT, apply error correction, and finish by applying unprotected CZ gates 4 to {5, 6, 7} , 8 to {9, 10, 11} and 12 to {13, 14, 15}. (This is safe because one fault has already been detected.) 2. Next, if the Zand X measurements were trivial, apply the top third of circuit Figure 5.7, where the orange qubit wire continues from (5.18) , to implement protected CZ gates 4 to {5, 6, 7}. If any measurements are nontrivial, then finish by applying unprotected CZ gates 8 to {9, 10, 11} 93 and 12 to {13, 14, 15}, then error correction. We have argued already that this is fault tolerant; the extended orange flag is enough to catch X 4 or Y 4 faults between (5.18) and Figure 5.7. 3. If the measurements so far were trivial, then apply a circuit analogous to (5.18) to extract the Z{s, 9 ,10,11 ,12,13,14,15} syndrome. (Note that this is still a stabilizer, even though the CZ gates 4 to { 5, 6, 7} have changed the code.) If the Z syndrome or X measurement is nontrivial, then apply error correction- a simple error-correction procedure is to apply CZ gates 4 to {5, 6, 7} to move back to the [15, 7, 3] code and correct there-before finishing with CZ gates 8 to {9, 10, 11} and 12 to {13, 14, 15}. If the Z and X measurements were trivial, then apply the middle portion of Figure 5.7, where the orange qubit wire extends from qubit 8, to implement protected CZ gates 8 to {9, 10, 11 }. If any measurements are nontrivial, then finish by applying unprotected CZ gates from 12 to {13, 14, 15}, then error correction. 4. If the measurements so far were trivial, then extract the Z{s, 9 ,10 ,11 , 12,13,14,15} syndrome using (5.18) except with the data qubits in order 12, 13, 14, 15, 8, 9, 10, 11 top to bottom (so that the orange flag attaches to qubit 12). If the Z or X measurement is nontrivial, then with at most one fault whatever error there is on the data can be corrected. (The easiest way is to move forward to the [15, 7, 3] code using CZ gates 12 to {13, 14, 15} and correct there. Note that these CZ gates turn the weight-one errors X12,X13,X14,X15 into X12Z{l3, l4,i5},Z12X13,Z12X14,Z12X15, respectively, but these can still be corrected; e.g., if in X error correction you detect X 12 , apply the correction X 1 2Z{ 13, 14, 15}.) If the Zand X measurements were trivial, then apply the bottom portion of Figure 5.7 to implement protected CZ gates from 12 to {13, 14, 15}, and correct errors based on the measurement results. Observe that this procedure requires two ancilla qubits. 5.3.6 Four-qubit fault-tolerant CCZ for universality In order to realize a universal set of operations on the seven encoded qubits, we give a four ancilla-qu bit fault-tolerant implementation for an encoded CCZ gate. The idea is to start with a 94 circuit of round-robin CCZ gates to implement the encoded CCZ non-fault-tolerantly (Claim 10), then replace each CCZ with the gadget of Figure 5.4 to catch correlated errors. Finally, we intersperse X error correction procedures to catch X faults before they can spread, much like the pieceable fault-tolerance constructions of [YTC16] except on a single code block. (A similar approach can also be used to implement encoded CZ gates.) By Claim 10, an encoded CCZ gate can be implemented by round-robin CCZ gates on qubits {1, 4, 5} x {1 , 6, 7} x {1, 8, 9} (one Z , six CZ and 20 CCZ gates): 1 4 5 6 7 8 9 z - I - (5.20) To make this circuit fault tolerant, first replace each CZ gate with the gadget from Figure 5.2, and replace each CCZ gate with the gadget from Figure 5.4. After each gadget, apply X error correction, and at the end apply both X and Z error correction. (As in [YTC16], it might be possible to put multiple CCZ gadgets before each X error correction, but we have not tried to optimize this.) Observe that X error correction can be implemented even partially through the round-robin circuit because the code's Z stabilizers are preserved by CCZ gates. There are two cases to consider to demonstrate fault tolerance: either a gadget is "triggered" with a nontrivial, 1 or -, measurement outcome, or no gadgets are triggered. A gadget is triggered. If a gadget is triggered, then any Pauli errors can be present on its output data qubits. It is straightforward to check mechanically that for each CZ gate in (5.20) , all four possible X errors, II , IX, XI and XX , have distinct Z syndromes, and so can be corrected immediately in the subsequent X error correction, before the errors can spread. By symmetry, 95 the four possible Z errors have distinct syndromes. These errors commute through (5.20) and are fixed by the final Z error correction. Similar considerations hold for each CCZ gate: the possible X and Z error components have distinct syndromes, so an error's X component can be corrected immediately and the Z component corrected at the end. No gadgets are triggered. If there is a single failure in a CZ or CCZ gadget, but the gadget is not triggered, then the error leaving the gadget is a linear combination of the same Paulis that could result from a one-qubit X, Y or Z fault before or after the gadget. If the error has no X component, then as a weight-one Z error it commutes to the end of (5.20) , at which point Z error correction fixes it. If the error has X component of weight one, then the Z component can be a permutation of any of III,IIZ,IZZ,ZZZ on the three involved qubits (or of II,IZ,ZZ for a CZ gadget). As we have already argued, these Z errors have distinct X syndromes. The X error correction immediately following the gadget will catch and correct the error's X component, keeping it from spreading. The final Z error correction, alerted to the X failure, will correct the error's Z component. 96 Chapter 6 Other applications of the flag paradigm We have investigated several representative flag schemes for error correction and logical computation in Chapter 4 and Chapter 5. However, a convincing demonstration of fault tolerance should in principle consider full circuits that consist of logical state preparations and measurements, as well as logical gates [Got16]. In this chapter, we augment the applicability of the flag paradigm with schemes for error detection, logical state preparation and measurement, using the [n, n - 2, 2], [5, 1, 3] and [15, 7, 3] codes. These schemes are fault-tolerant by their corresponding criteria in Definition 3 and Definition 4, and have all been presented in [CR18b]. Supplemented with the gadgets provided in Chapter 4 and Chapter 5, it is possible to test versatile fault-tolerance schemes in the near future. In addition, we include a flag error-correction scheme using a Majorana loop stabilizer code [JMBN19] for efficient simulations of geometrically local fermionic systems, which might be of independent interests. 6.1 Flag error detection for [n, n - 2, 2] codes The idea of flagging faults that can spread badly is also useful for error-detecting codes. For even n, the [n, n - 2, 2] error-detecting code has stabilizers X ®n and z @n, and logical operators Xj = X 1XJ+ 1 , Zj = Zj+1Zn for j = 1, ... , n - 2. 97 IO ) ... ... , , , , ' I-' ' I-' ", ", ", ", * * (a) 0 /1 I+) IO) - l. " "" "' " " , "' "' ... (b) - + l. , "" ... / /1 0 Figure 6.1: (a) Circuit to extract the z @n syndrome. (b) Adding a flag makes it fault tolerant. Observe that extracting a syndrome with a single ancilla qubit is not fault tolerant because, for example, a Z fault at either location indicated with a * in Figure 6.l(a) results in an undetectable logical error. With a flag qubit, the circuit is fault tolerant; any single fault is either detectable or creates no data error. This approach works for any n. One way of interpreting it is that the ancilla is encoded into the two-qubit Z-error detecting code, with stabilizers XX and logical operators X = IX and Z = Z Z. This code detects the single Z faults that can propagate back to the data. In Section. 6.2.3 we give single-ancilla fault-tolerant circuits for initialization and projective measurement. 6.2 Flag state preparation and m easurem ent 6.2.1 State preparation and measurem ent for the [5, 1, 3] code 6.2 .1.1 State preparatio n The black portion of the circuit in Figure 6.2(a) prepares, up to Paulis, encoded I+), the five-cycle graph state with stabilizers ZXZII and its cyclic permutations. Then three of the syndromes are measured. Provided that there is at most one gate fault, and the syndrome (blue) 98 and flag (red) measurements are trivial, the output has at most a weight-one error. One can apply transversal Clifford operators to obtain encoded IO ). 6.2.1.2 Measurement Although logical Z is transversal, X = XX XX X , it is not fault tolerant to measure X transversally. The problem is that, as the [5, 1, 3] code is not CSS, the X measurements do not give sufficient information to correct errors. Fortunately, we can apply the same flag trick that we used for error correction. We give a two-ancilla-qubit fault-tolerant circuit for destructively measuring X. l. Let s 1 be the result of measuring XZIIZ using a flag, as in part I of Figure 6.2(b) . If the flag is raised, skip to part IV. Apply the five-CZ decoding circuit, measure the qubits and decode to get the answer. (Given that the flag was raised, the data error can be IIIII, IZIII , XZIII, YZIII or ZZIII before decoding, and IIIII,IZIII,XIIIZ, YIIIZ or Z Z I I I after. These errors can be distinguished and corrected for.) 2. Measure ZXZII with a flag, and call the result s 2 , as in part II of Figure 6.2(b) . If the flag is raised, then return s 1 . If the flag is not raised, and s 2 -/=- s 1 , then there has been a fault, which can mean a data error of weight :c; l. Skip to part IV: decode, measure and correct the result for the 16 possible errors II III, XII II, ... , IIIIZ. 3. Measure II Z X Z with a flag and call the result s3 , as in part III. If the flag is raised, then return s 1 = s 2 . Otherwise, if s 3 = s 1 = s 2 then return this value. If s 3 -/=- s 1 = s 2 , then in part IV decode, measure and correct the result for the 16 errors of weight :c; l. 99 0/ 1 +/ - + + + + + I+) +/ - I+) +/ - 10 0/ 1 10 0/ 1 (a) II 0/ 1 I s i III \ IV +/ - +/ - +/ - +/ - +/ - S1 I+) 83 0/ 1 \ I 10 0/ 1 \ (b) Figure 6.2: Fault-tolerant circuits to (a) prepare encoded I+), and (b) measure logical X , for the [5, 1,3] code. In (a) the measurement outcomes should all be trivial, I+) or I0), for the state to be acceptable. In (b), portions of the circuit may be skipped depending on the measurement results. This procedure is fault tolerant. For example, if the flag is raised while extracting s 2 , then, provided the circuit has only one fault, s 1 must have been correct. 6 .2.2 State preparation for the [15, 7, 3] code Figure 6.3 gives a fault-tolerant circuit to prepare 1 0 7 ) encoded in the [15, 7, 3] code. We have condensed CNOT gates with the same control wire. The state is accepted provided that the measurement returns I0 ). Note that since the code is perfect CSS, we need not worry about Z 100 It 10 I+ 0 0 0 I+ 0 0 0 0 0 0 0 0 ) I r,. I r,. I r-. /I'\ ... ... ... T - ,I"\ I"\ ... ... .... .... ... ... .... .... ... ... .... .... .... ... ... I-' I I"\ I I"\ ... ... I I"\ I I"\ I I"\ ... ... ... I I"\ I I"\ ... ... I I"\ I I"\ I I"\ ... ... ... I I"\ I I"\ I I"\ ... ... ... .... i,.. I r,. I"\ ... ... ... ... ""I" 'I" 'I"' 0 T' ' ' / 1 - Figure 6.3: CSS fault-tolerant preparation of encoded 1 0 7 ) . faults propagating and only need to check for X faults. (Any Z error is equivalent to either the identity or a weight-one error.) The circuit is fault tolerant only for X and Z faults considered separately. For example, if the CNOT 1 ,15 gate fails as ZX, the state will be accepted with the weight-two error Z 1X 15- but as the X and Z parts of this error each have weight one, the error is correctable. Other encoded computational basis states can be prepared by applying logical X operators 6 .2.3 State preparation and measurem ent for [n, n - 2, 2] codes We give one-qubit fault-tolerant circuits for state preparation and projective measurement, for the [n, n - 2, 2] codes. 101 6.2.3.1 State preparation Encoded 1 on- 2 ) is a cat state 1(1 0n) + lln)). It can be prepared fault tolerantly by I J f) -+++---------f-++- o / i 0 0 0 0 0 where t he Z measurement should return IO ). (6.1) Encoded states I + 1 on- 2 - 1 ) can be prepared by applying targeted logical Hadamard gates to encoded 1 on- 2 ) . However, it is easier to prepare them directly. For j odd, encoded I + 1 on- 2 - 1 ) is ½( l+H 1 ) + 1-1+1)) ® (l on-j-l) + 1 1n-j- 1 ) ), i.e. , t he tensor product of cat and dual cat states. The states can be prepared separately as in (6.1) . The following circuit for n = 6, j = 2 generalizes naturally to any even j: I+) +/ - - - ~ ~ l. ~ l. '" '-"'-V '-" '-J,I (6.2) ' I'"\ .... ' I'"\ 0 1 .... I The black portion prepares the state, while the red parts catch faults using postselected Z and X measurements. 102 6.2.3.2 Measurement The qubits can all be simultaneously be measured in the X or Z logical bases by transversal X or Z measurement. To projectively measure just Z 1 fault tolerantly, measure it twice using one ancilla: (6.3) Different results indicate an error. Similar circuits work for measuring zizj = zi+lzJ+l for i-/- j, and for measuring f1 1 Z 1 = Z1Zn and IJ#i Z 1 = Z1Zi+1· To projectively measure other parities, use a two-ancilla circuit as in Figure 6.1 (b) . Of course, symmetrical circuits work for measuring logical X operators. 6.3 Flag error correction for fermionic simulations In this section, we show that the flag paradigm can be used to correct errors when simulating fermionic systems using the Majorana loop stabilizer codes which have been recently proposed by Jiang et al. [JMBN19]. Material in this section is based on [CCJR20]. Fermionic quantum computing [OGKL0l , BK02] is widely regarded as one of the most promis ing applications in the noisy intermediate-scale quantum (NISQ) era [Pre18a]. One prominent example is the electronic structure problem of calculating the ground state energy of a molecule Hamiltonian [AGDLHG05, MEAG+ 20], which is a central topic in quantum computational chem istry 103 Simulation of fermionic systems starts from mapping fermionic Fock space and ladder operators into qubit Hilbert space and Pauli operators, respectively. Specifically, consider a Fock space consisting of m fermionic modes, with basis states represented as ni E {0,1}. (6.4) All physical fermionic operators can be generated by ladder operators { cp, 4};;'= 0 1 satisfying (6.5) Their actions on the Fock basis states are given by: I:p- 1 c lno n1 ··· n 1)=6 1(-l) q~onqlno n1 ··· n '"' 1 ··· n 1) p , , , m- np, , , , p w , , m- (6.6) t I:p- l c lno n1 ··· n 1)=6 o(- 1) q~onqlno n1 ··· n '"' 1 ··· n 1) p , , , m- np, , , , p w , , m- A valid fermion-to-qubit encoding should map the ladder operators and Fock basis states to certain P auli operators and qubit states such that the commutation relations in (6.5) and the actions in (6.6) are preserved. A large variety of encoding schemes have been provided. Examples include the Jordan- Wigner [JW93], parity [SRL12], Bravyi-Kitaev [BK02], Fenwick tree [HTWl 7], nonlinear [SW18], auxiliary fermion [WHT16] and generalized superfast [SBMW19] encodings. Particularly relevant to this section is the recent Majorana loop stabilizer codes [JMBN19], which is based on the Bravyi-Kitaev superfast encoding [BK02]. Broadly speaking, these various encoding schemes aim to minimize the number of qubits and the Pauli weights of encoded operators. There are usually some tradeoffs between the two figures of merit. 104 6.3.1 Majorana loop stabilizer codes The Bravyi-Kitaev superfast encoding and the more general Majorana loop stabilizer codes (MLSC) are particularly advantageous for simulating a system where the fermions can be arranged in a lattice and the Hamiltonian involves only terms of interactions between geometrically local fermions. Below we formally describe the MLSC. Consider the ladder operators { Cp, 4};1=r/ of m fermion modes. Define It is easy to verify that operators T/k and (jk satisfy T/k = T/k T/~ = I T/j'T/k = T/k'T/j (6.7) (6.8) (6.9) (6.10) Below we restrict ourselves to physical operators that preserve the parity of the number of particles, i.e., the occupation number, denoted by N. Therefore, it is without loss of generality to impose an additional constraint m-1 IT T/k = (- l)N = I (6.11) k=O which restricts to the Fock subspace of even particles. It can be proved that operators T/k and (jk can generate the algebra of all physical observables on the m modes. Consider a generic chemistry Hamiltonian H = L hijcjcj + L hijklcJc}ckcl (6.12) ij ijkl 105 which is a certain linear combination of products of T/k and ~jk· Then construct a simple undirected graph G = (V, E) such that V = { Vo,v1, ... ,Vm-l} (6.13) E = { (v;,vj) I fo appears in H} We refer to G as the interaction graph of H, T/k as vertex operators and ~jk as edge operators. Namely, each fermionic mode only interacts locally with its neighbors in the graph. Our goal is then to find qubit counterparts T/k of vertex operators T/k and [jk of edge operators ~jk that satisfy (6.8) , (6.9) , (6.10) and (6.11) . Consider the interaction graph G = (V, E) with IVI = m and IEI = n. To start the MLSC, place a qu bit at every edge of G. Let X ;j, YiJ, Z; 1 denote the Pauli operators acting on the edge (v;,vj) EE. Then consider the edge-to-vertex dual graph of G, i.e., the line graph L(G) = (E,F). For any e, e' E E and e -:/- e' , we have ( e, e') E F if and only if there exists v E V such that both e and e' are incident to v. Next, assign an arbitrary direction to each element in F, resulting in a directed graph £( G) = ( E, F). Then the vertex and edge operators of the MLSC can be defined as T/v = IT \/v EV e:eEE; e incide nt to v (6.14) ~e = Xe IT Ze, \/e EE e': e'EE; (e , e')EF where the angle bracket denotes a directed edge from e to e'. It is easy to verify that the above assignments preserve the rules of (6.8) , (6.9) and (6.11) , except for the anti-symmetry condition ~jk = -~kj · This can be easily fixed by assigning a random phase ± 1 to each edge operator. For example, for an edge e = ( Vj, vk) E E, let [jk = Ejk[e and [kj = Ekj[e, where Ejk = -Ekj = ± 1. 106 However, ( 6.10) are not automatically satisfied by ( 6. 7) . Define (6.15) Note that any operator Skoki···ki-i corresponds to a closed loop in the graph G. It is easy to check that loop operators Skoki···k= _ 1 commute with each other, and commute with all edge and vertex operators. One way to impose (6.10) is to restrict T/kJjk on a subspace which is stabilized by the loop operators. More specifically, denote S = \ skok1···k1 - 1 : kok1 · · · k1-1 ko is a closed loop in Q) . (6.16) S does not contain - I and thus can be regarded as a stabilizer group. Thus we can further define £, as the subspace stabilized by S, to which we restrict the actions of T/k and [jk· The number of independent stabilizer generators, i.e., the number of independent cycles in G is equal ton - m + l. Hence dim£ = 2m- 1 . In particular, £, can be identified with the even parity subspace of the fermionic Fock space. To summarize, the number n of qubits equals to the number of edges, and edge and vertex operators have Pauli weights O(d) where dis the maximum vertex degree of G. 6.3.2 Fault-tolerant error correction using the MLSC In [JMBN19], Jiang et al. construct a MLSC on a two-dimensional square lattice with an open boundary, and show that the code has distance three. Namely, their code can correct a single qubit error. Observe that a MLSC is fully specified by the directed line graph £( G) = ( E, F) according to (6.14) . Of particular interests are interaction graphs G that can be embedded in lattices, and their corresponding line graphs £( G) that have translation-invariant directions. In such cases, the 107 MLSC have stabilizer generators (associated to individual faces) , edge and vertex operators that are also all translation-invariant. In particular, it is relatively easy to check the code distance and to design the syndrome extraction circuits. Namely, it suffices to focus on a small local neighbor hood. Below we consider an example MLSC code defined on a rhombic lattice with distance three. We then provide a flag error-correction scheme that preserves the distance. Specifically, we consider a periodic rhombic lattice embeddable in a torus, for simplicity; see Figure 6.4(a) . Any MLSC defined on this lattice has distance at most 3, due to the exist ence of degree-3 vertices. There are several rhombic MLSC with distance 3. We randomly choose one which is defined by the directed line graph in Figure 6.4(b) , and whose three types of stabilizer generators are shown in Figure 6.4(c) . Below we give an error-correction scheme for this code that satisfies the fault-tolerance criteria in Definition 3. Ancilla qubits are needed to measure the stabilizer generators. Figure 6.5(a) and Figure 6.5(b) illustrate the layout of the data and ancilla qubits for the purple and gray types of stabilizer generators, respectively, as well as the qubit connectivity. The case for the brown type of generators is similar. Specifically, we place a syndrome ancilla (red) at the center of each rhombus cell, whose measurement outcome reveals the syndrome bit of the stabilizer associated to that cell. We also put a flag ancilla (green and blue) at each vertex, whose measurement outcome provides information about the incurred correlated data errors. Each syndrome ancilla can interact with the flag ancillas on the four vertices of the rhombus where it resides in. Each flag ancilla can interact with the three or six data qubits (black) associated to the edges incident to the vertex where it resides in. Given the qubit layout and connectivity, we now describe a flag syndrome-extraction circuit that measures all the syndrome bits and will flag as long as a single fault gives rise to correlated data errors. The circuit proceeds in three consecutive stages, and each stage measures the syndrome bits of all stabilizer generators of a same type (color) simultaneously. The order of the threes types is unimportant. Figure 6.5(c) and Figure 6.5(d) describe the detailed schedules of the 108 (a) (b) (c) Figure 6.4: An example rhombic MLSC. (a) Two tessellations of rhombi on a torus. Opposite sides are identical. We use the first tessellation for simplicity, which consists of an even number of hexagon columns . (b) The generator which can generate the whole directed line graph by translation. ( c) Three types of weight-8 stabilizer generators, up to translation, colored in gray, purple and brown. Red and blue edges represent Pauli Y and Z operators, respectively, supported on the corresponding qubits. 109 syndrome-extraction circuits for purple and gray types of generators, respectively. The circuit for the brown type of generators is symmetric to that for the purple. Specifically, for each cell, first couple the syndrome ancilla with the four adjacent flag ancillas using four time steps to prepare a five-qubit cat state. Then, couple each flag ancilla with its assigned data qubits to copy the data errors. Finally, decode the cat state, and measure the syndrome bit along with the flag outcomes. Circuits for measuring the syndrome bits of generators of a same type can be parallelized into ten time steps-1 for state preparation, 8 for gates and 1 for measurements. It is easy to verify that without circuit faults, the circuits in Figure 6.5 measure the syndrome bits correctly. In order to construct an error-correction protocol that satisfy the fault-tolerance criterion in Definition 3, it suffices to verify the detectability and distinguishability conditions. Namely, the flag pattern is nontrivial whenever a single fault results in at least two data errors, and the possible flagged errors are distinguishable by their syndromes. To see this, consider the circuit for the purple type of generators as in Figure 6.5(c) . The only nontrivial cases to verify are that (1) P 9 Y 12 Z 10 , Pi 2 Z 10 and Pio with PE {X, Y, Z} all have distinct syndromes, and (2) Z 14Y 11 Z 7 has nontrivial syndrome. These two cases correspond to two nontrivial flag patterns. For any other flag pattern, all the flagged errors are supported on at most two fixed qubits, which are always distinguishable for a distance-three code. The argument for the gray or brown type is similar. Interesting problems for future research include developing systematic methods for constructing MLSC with higher distances on two- or three-dimensional lattices, devising fault-tolerant error correction schemes for MLSC defined on small planar graphs with closed boundaries, or figuring out how to perform fault-tolerant time-evolutions of the edge or vertex operators under the geometric constraints. 110 16 10 (a) (b) 16 16 IO )G --+-+---t+it--e--+-e--+et+t-- 0/ 1 IO )r; 0/ 1 - - - - - ---- +!- 1+)3 I+) +/- 14 14 11 15 1 0)2 1 0)3 1/ 0 7 7 IO )i 11 9 IO ):i 0/ 1 12 12 10 10 1 0)4 -+-t--H+ ...... -f--tl>-te-Ht--=-- 0/ 1 1 0)4 0/ 1 1+)2 - ---------- -----+!- 1+)2 +/- 8 8 5 9 IO )i 1 0)2 1/ 0 1 1 IO )i 5 3 IO )i 0/ 1 (c) (d) Figure 6.5: Circuit for simultaneous syndrome extraction of all stabilizer generators of the purple or gray type; the case for the brown type is similar. (a) and (b) illustrate, respectively for measuring the purple and gray types of generators, the layout of the relevant data qubits (black) , syndrome ancillas (red) and flag ancillas (green and blue) , as well as the connectivity between them (brown lines). (c) and (d) describe the detailed circuit schedules for measuring the purple and gray types of generators, respectively. Both use 10 time steps, including state preparations and measurements. For illustration purposes, gates in different time steps are colored black or gray alternately, and the gates for measuring the stabilizer in the middle of (a) or (b) are enclosed by a purple curve. 111 Chapter 7 Fault-tolerant error correction with slow qubit reset As we have seen in previous chapters, typical flag schemes involve adaptive classical control that requires frequent and rapid qubit preparations and measurements. This will impose unrealistic restrictions for certain qubit systems that do not support fast qubit reset. Similar issues occur with Shor-, Steane- and Knill-style error corrections that involve extensive preparations and verifications of ancilla states. DiVincenzo and Aliferis [DA07] address this issue of slow qubit reset using, among other tricks, a decoding-based circuit to extract individual syndrome bits, as illustrated in Figure 3.4. Their scheme is particularly amenable for systems where the time for qubit preparation and measurement are significantly larger than that for gate and resting qubit error rates are non-negligible. In this chapter, we extend the DiVincenzo-Aliferis decoding method and provide a fault-tolerant error-correction scheme that allows slow qubit reset. Namely, each ancilla qubit is measured only once at the end of individual syndrome-extraction circuits. Our scheme applies to arbitrary distance-three codes, and requires max{3, I w /27} extra qubits, where w is the maximum weight of a stabilizer generator. As for comparison, Prabhu and Reichardt [PR20] have recently provided new flag error correction schemes that allow slow qubit reset and apply to arbitrary distance-three and -five codes, and require, respectively, O(log w) and 0( w) ancilla qubits. 112 Adaptive Slow qubit None reset Fast 0(1) for many codes reset Section. 4.1 , [CB18, TCL20] Non-adaptive iw/ 21 ford = 3 (Section. 7.1 ) O(log w) for d = 3 [PR20] iw/ 21 + 0(1) ford = 5 [PR20] S1(w) [Sho96, Ste97, Kni05b] min{d + 1, 2w + 2} for all d (Section. 4.2) Table 7.1: Numbers of ancilla qubits for different error-correction schemes. Here, dis the code distance and w is the maximum stabilizer generator weight. In Section. 4.1 and [CB18, TCL20], flag patterns can only detect or reveal partial information about the correlated data errors; adaptive syndrome measurement is further needed for full correction. In [Sho96, Ste97, Kni05b], correlated data errors cannot occur due to ancilla verification. In the other schemes in the t able, syndrome measurement circuits can be scheduled deterministically; (flag) ancilla patterns provide enough information to correct correlated errors. Different fault-tolerant error-correction schemes are summarized in Table 7.1. Specifically, the schemes by Shor, Steane and Knill all postselect ancilla states through verification, thus requiring fast qubit reset. Unlike previous flag schemes, e.g., those in Section. 4.1 and [CB18, TCL20], the flag scheme given in Section. 4.2 is non-adaptive, in the sense that the flag measurement outcomes alone provide enough information to correct correlated errors; no extra syndrome measurement is required. All the schemes that allow slow qubit reset are also non-adaptive; no postselection is needed. 7.1 Ancilla-decoding-based scheme for arbitrary distance- three codes In Section. 3.1, we have introduced Shor's method and DiVincenzo-Aliferis decoding method for error correction. Specifically, for a distance-three code, Shor's method uses w + l ancilla qubits to fault-tolerantly extract the syndrome of a weight-w stabilizer, by preparing and verifying a w-qubit cat state 113 For w = 4 and w = 7, DiVincenzo and Aliferis give circuits that use unverified w-qubit cat states, that interact with the data without waiting for a measurement to finish. Instead of measuring the cat state immediately after coupling it to the data, they first apply a carefully designed decoding circuit. See Figure 3.4. They conjecture the technique extends to arbitrary w. In fact , one can do better. Stephens [Ste14] has proposed that for w ~ 8, four ancilla qubits are enough to fault-tolerantly extract the syndrome, and Yoder and Kim [YKl 7] have shown that three qubits are enough for w = 4. We will show that in general, for a distance-three code, max{3, I w /21} qubits suffice to fault-tolerantly extract a weight-w stabilizer's syndrome. Unlike our two-qubit flag schemes, this method can also be "deterministic" [CDT09]. The basic idea is to follow the DiVincenzo-Aliferis method, except coupling two data qubits to each ancilla qubit; with appropriate corrections, this remains fault tolerant. In particular, the resulting circuit is 3-FT as defined in Definition 6. Without loss of generality, we take the measured stabilizer to be X ®w_ Figure 7.l(a ) sketches the technique for the minimum number, three, of ancilla qubits, and Figure 7 .1 (b) shows the construction for w = 10. The general case follows a similar pattern. Observe that in Figure 7.l(b) a failure of gate a can propagate to a data error AX2 for any PE { I, X , Y , Z}. A failure of gate b can create a P2 data error. The X 2 correction, applied when the Z measurements output 1000, ensures that at the end the data has an error of weight ~ 1. The corrections for Z measurements 0100, 0010, 0001 and 1111 are similar. Failures at locations c and d can cause data errors of weight four or six, respectively, but these are caught and corrected for with Z measurements 1100 or 1110. It is important that after the coupling to the data no single fault can cause the measurements to give 1100 or 1110. 114 I+) I~ 1 2 3 4 5 6 ~ - A- - ,, ' I I'\ 0 1 I "" 0/1 I+!- ,, ' (a) l+)....._-&,.;..;,tda-,;;c..__.....,_..._ _____ ----U,;+-----0/1 ~:Q::::::()c:::::Q::=$==.,,,,. 0 \ i , ; 0 / 1 =0==-==0==0=,.,, .... 0 > , ; 0 / 1 ~=0=$=:()::::::::1-==c~ 0 > I- 0 / 1 ~:Q::::::():::::$::=$==0==0 O> ,~ - +/ - , ... a b 1 ,, ,,,, ' ' ' 2 ---------t'Ti',......,.---i-i--t--t--t--t---t---------t1'~-t-t--t--t--t-T'H ''-t'Ti'~ ""' lo" ""' """ 3 ----------t'~'t-1-i--t--t--t--t---t----------i--t--t--t-T'H ''-t'Ti'~ ' ' ' 4 ---------H-t-+-+--+---1-1--+---------+Hl'\-+--+---l-+H'-t"tr ... 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Abstract (if available)
Abstract
Quantum computers will need protection from noise. A delicately designed circuit can correct errors in software—even tolerating faults within itself. However, while there have been experimental tests of quantum error-correcting codes, testing fault-tolerance remains a major challenge. A main difficulty is the substantial overhead
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Chao, Rui
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Flag the faults for reliable quantum computing
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Viterbi School of Engineering
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Doctor of Philosophy
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Electrical Engineering
Publication Date
06/27/2020
Defense Date
05/14/2020
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University of Southern California
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flag paradigm,OAI-PMH Harvest,quantum computing,quantum error correction,quantum fault tolerance
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Reichardt, Ben (
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ruichao@usc.edu,ruichao1102@gmail.com
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-c89-322486
Unique identifier
UC11663776
Identifier
etd-ChaoRui-8620.pdf (filename),usctheses-c89-322486 (legacy record id)
Legacy Identifier
etd-ChaoRui-8620.pdf
Dmrecord
322486
Document Type
Dissertation
Rights
Chao, Rui
Type
texts
Source
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Access Conditions
The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...
Repository Name
University of Southern California Digital Library
Repository Location
USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA
Tags
flag paradigm
quantum computing
quantum error correction
quantum fault tolerance