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Improving the speed-power-accuracy trade-off in low-power analog circuits by reverse back-body biasing

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Improving the speed-power-accuracy trade-off in low-power analog circuits by reverse back-body biasing

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Content Improving the Speed-Power-Accuracy Trade-O in Low-Power Analog Circuits by Reverse Back-Body Biasing by Aaron Curry A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulllment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) August 2019 Copyright 2019 Aaron Curry Dedication To my former advisor and friend, John Choma, who saw something great in me and encouraged pursuit of this path. i Acknowledgments I suppose my Ph.D. has been a bit of an unconventional path; however, I am grateful for all the experiences along the way, for shaping what the degree means to me, which is much more than this relatively-brief document. More importantly, I owe the following individuals many thanks for their help and involvement throughout the process. First, I have to thank my former Ph.D. advisor, Professor John Choma, who was an irreplaceable mentor from my rst circuits course with him, EE348L. His love for his work, his students, and the exploration of knowledge in order to share it with others was remarkable and contagious. Next, I have immense gratitude for my current Ph.D. advisor, Professor Edward Maby, who, in the wake of John's passing, rescued me, took over the reigns of my project, and vowed to help me reach the nish line by any means he could. When I frequently got lost in the weeds, he would help me step back and see the bigger picture so that I could get back on the right track. I would also like to thank my defense committee, for their continued support and helpful feedback during my system implementation: Professor Mike Chen, who was my Qualication Committee Chair and helped nd deciencies in my rst chip, Enigma; Professor Sandeep Gupta, who taught me digital basics such as logical eort and helped try to salvage Enigma; and Professor Ted Berger, who opened his lab up to me and who's research inspired my project. I would like to thank Professor Aluizio Prata, who was on my quali- fying exam committee and a challenging yet motivating electromagnetics instructor; I thoroughly enjoyed all four E&M courses I took from him. I would like to thank Professor Martin Gundersen and Professor Alan Willner, for their kindness and help when I was was exploring research in- terests. Working in Professor Gundersen's pulsed-power laboratory was an exciting experience, and Professor Willner made communication systems invigorating, and I miss going to his oce hours every week. ii I also want to thank USC's academic advisors Jaime Zelada and Dianne Demetras, for their kindness and goodwill throughout my time at USC. I want to thank MOSIS and their MOSIS Educational Program (MEP). If it weren't for their grants and support, I would not have been able to fabricate my proposed system. I don't think I can thank enough Susan and Bob Schober. They have been tremendous sources of knowledge, support and guidance throughout the implementation of my project. They have become inspirational col- leagues and friends and I am grateful to have met them through the Choma connection. Last, but certainly not least, I would like to thank my family, for their unconditional love and support: my parents, who taught me that hard work pays o and to never give up; my brothers, who have been a continual source of familiarity, feedback, and friendship; and most of all, my wife, who has always encouraged me to do what I think is best and to have faith in myself. iii Abstract Applications in the biomedical industry, Internet of Things, and other tech- nologies have spawned the need for ultra-low-power systems. Reduction of power consumption in analog circuits can be realized by reductions in their supply voltages and operating currents. Unfortunately, the latter makes re- liable circuit behavior dicult to achieve. Numerous factors inherent to IC fabrication lead to unpredictable threshold voltages, which makes biasing a dicult task at low power levels. The only resolutions that avoid a severe reduction in speed are post-fabrication compensation techniques. This work investigates the use of reverse back-body biasing in order to compensate for threshold voltage variation. The system regulates device currents through feedback by measuring the current osets caused by de- vice uncertainties and applying appropriate reverse-bias voltages at body terminals. An auto-calibration system on chip (SoC) interfacing with a eld- programmable gate array (FPGA) was built and tested to show proof of concept. Two current-mode test circuits were used for demonstrating the ability of the system. Results show that the implemented system is able to achieve 3 nA bias currents in 0.24 m channel-length devices with a nor- malized standard deviation of 1 %, which was the limit imposed due to second-order eects. Similar accuracy would be achieved by using devices with 1,200x area. Additionally, the system does not exhibit a drastic reduc- tion in accuracy for power supply variation so long as voltage headroom is not compromised. iv Contents Dedication i Acknowledgments ii Abstract iv Contents iv List of Figures viii List of Tables xii 1 Prospects and Perils of Low-Power Design 1 1.1 Low-Power Applications . . . . . . . . . . . . . . . . . . . . . 1 1.2 Low-Power Case Study: Spike Sorting . . . . . . . . . . . . . 2 1.3 Analog vs. Digital Implementation . . . . . . . . . . . . . . . 4 1.4 Low-Power Design: Subthreshold Operation . . . . . . . . . . 6 1.5 Mismatch Impact on Current-Mode Circuit Accuracy . . . . . 9 1.6 Speed-Power-Accuracy Trade-O . . . . . . . . . . . . . . . . 11 1.7 Current Methods vs Proposed Method to Mitigate the Eects of Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.7.1 Mismatch Sampling . . . . . . . . . . . . . . . . . . . 13 1.7.2 Mismatch Compensation . . . . . . . . . . . . . . . . . 15 2 Proposed System 20 2.1 Intuition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 The Underlying Goal: Having Equal Subthreshold Current Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 v 2.3 Compensation Using Negative Feedback . . . . . . . . . . . . 22 2.4 Dierential Feedback Compensation . . . . . . . . . . . . . . 24 2.5 Other Circuits Utilizing Power-Supply Sampling . . . . . . . 26 2.6 Reference Production . . . . . . . . . . . . . . . . . . . . . . 28 2.6.1 First Reference Production Method . . . . . . . . . . 29 2.6.2 Second Reference Production Method . . . . . . . . . 31 2.6.3 Reference Production Comments . . . . . . . . . . . . 33 2.7 Second-Order Eects During Calibration . . . . . . . . . . . . 33 2.7.1 Error in Calibration-Current Ratio . . . . . . . . . . . 34 2.7.2 Error in Calibration Operating Point . . . . . . . . . . 36 2.7.3 Lumped Impact of Second-Order Eects . . . . . . . . 37 2.8 Required Output Voltage Swing . . . . . . . . . . . . . . . . . 38 2.9 Accuracy Improvement of Proposed System . . . . . . . . . . 40 3 Implementation of Proposed System 41 3.1 Overall System Description . . . . . . . . . . . . . . . . . . . 41 3.2 The ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.1 Power-Supply Domains . . . . . . . . . . . . . . . . . 44 3.2.2 Implementation Block . . . . . . . . . . . . . . . . . . 45 3.2.3 On-Chip Long-Term Storage . . . . . . . . . . . . . . 55 3.2.4 ASIC Overview . . . . . . . . . . . . . . . . . . . . . . 61 3.3 O-chip Implementations . . . . . . . . . . . . . . . . . . . . 62 3.3.1 Power Supplies and Bias Voltage Generator . . . . . . 62 3.3.2 The Feedback Amplier . . . . . . . . . . . . . . . . . 62 3.3.3 The FPGA with Built-in ADC . . . . . . . . . . . . . 63 3.3.4 O-Chip Overview . . . . . . . . . . . . . . . . . . . . 65 3.4 System Calibration Considerations . . . . . . . . . . . . . . . 65 3.4.1 Feedback Loop Stability . . . . . . . . . . . . . . . . . 65 3.4.2 System Accuracy Considerations . . . . . . . . . . . . 67 4 Measurement Results 69 4.1 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . 70 4.1.1 Mismatch Accuracy . . . . . . . . . . . . . . . . . . . 70 4.1.2 Overall Accuracy . . . . . . . . . . . . . . . . . . . . . 74 4.1.3 Speed-Power-Accuracy Trade-O . . . . . . . . . . . . 74 4.2 Accuracy Results . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.2.1 Current Mirror Test Structures . . . . . . . . . . . . . 75 4.2.2 Vector Magnitude Test Structures . . . . . . . . . . . 76 4.3 Power Supply Variation . . . . . . . . . . . . . . . . . . . . . 77 4.4 Speed-Power-Accuracy Trade-O . . . . . . . . . . . . . . . . 77 vi 5 Conclusions and Future Work 85 References 88 vii List of Figures 1.1 Analog signal processing block that calculates the vector mag- nitude of two input currents. . . . . . . . . . . . . . . . . . . 3 1.2 Plot of required spent power (a) and area (b) to achieve cer- tain accuracy (SNR) for both analog and digital implemen- tations of a system. Reprinted from [3]. . . . . . . . . . . . . 5 1.3 The surface potential at the source with respect to the source- bulk bias versus gate-source and source-bulk voltages for an nMOS device. Values from the 0.5 m device parameters given in [7] as V fb = -627 mV, F = 450 mV, and = 450 m p V are used. The thermal voltage is approximated at room temperature as V t = 26 mV and the moderate inversion transition potential is estimated as z 4V t . Also shown are the boundaries between the dierent regions of operation as vertical planes. . . . . . . . . 8 1.4 The result of mismatch on the surface potential of a current- mode device for an applied gate-source voltage in weak inver- sion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 The I-V curves measured from 96 devices with the same gate- width-to-length ratio of 2 m/2 m for two dierent source- bulk potentials. Reprinted from [10]. . . . . . . . . . . . . . . 10 1.6 Methods to sample output current mismatch. (a) Sampling at the output and (b) proposed power-supply sampling method. 14 1.7 Drain current bias method to compensate mismatch eects. . 16 1.8 Gate voltage bias method to compensate mismatch eects. . . 17 1.9 Source voltage bias method to compensate mismatch eects. . 18 1.10 Proposed bulk voltage reverse-bias method to compensate mismatch eects. . . . . . . . . . . . . . . . . . . . . . . . . . 18 viii 2.1 Overview of proposed system. (a)Compensation uses reverse back-body biasing. (b)Power supply current sensing allows for calibration without loading the circuit. . . . . . . . . . . . 20 2.2 (a) Proposed negative feedback that generates the required bulk bias during calibration. The `sa' subscript denotes device voltages and current during mismatch sampling. (b) After V Bias is found, the feedback is removed and the device is allowed to operate normally. . . . . . . . . . . . . . . . . . . . 23 2.3 (a) Dierential feedback circuit that generates the required V Bias for matching two devices. (b) After the required bias voltage is found, the feedback is removed and the devices are allowed to operate normally. . . . . . . . . . . . . . . . . . . . 25 2.4 Dierential feedback to compensate two current-mode de- vices. The operating point during mismatch sampling does not have a closed-form solution. . . . . . . . . . . . . . . . . . 26 2.5 Using dierential sampling and single-ended feedback to com- pensate a current-mode device to a voltage-mode reference. (a) Feedback scheme during mismsatch sampling and com- pensation. (b) Circuit after feedback is removed. . . . . . . . 27 2.6 Proposed method of using power-supply sensing through V DD to program an nMOS dierential pair. (a) Circuit during mis- match sampling and compensation. (b) Circuit after feedback removal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.7 (a) Proposed rst method of reference production with single V ref . (b) Proposed method of producing the tail current in (a). 30 2.8 (a) Proposed method of producingR ref andV ref using a sin- gle R ref value. (b) Proposed method of producing I 1 and I 2 in (a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.9 Proposed method of calibration operating point compensa- tion implemented with the rst method of reference production. 38 2.10 Proposed power supply implementation for reverse-biased de- vices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 Current-mode test circuits implemented for testing the pro- posed biasing method. (a) A standard current mirror without circuit error compensations (cascode devices, feedback, etc.). (b) A 7-T translinear two-dimensional vector magnitude cir- cuit implemented with nMOS devices. . . . . . . . . . . . . . 42 ix 3.2 Block-level diagram of implemented system. Blocks imple- mented on the ASIC are outlined in green. Blocks imple- mented external to the ASIC are outlined in blue. . . . . . . 43 3.3 Power supply domains for implemented ASIC. . . . . . . . . . 45 3.4 Schematic view of the current mirror test structure imple- mented for back-body biasing. . . . . . . . . . . . . . . . . . . 47 3.5 Layout view of the current mirror test structures. . . . . . . . 48 3.6 Schematic view of vector magnitude test structures imple- mented for back-body biasing. . . . . . . . . . . . . . . . . . . 48 3.7 Layout view of vector magnitude test structures. . . . . . . . 49 3.8 Schematic view of unused vector magnitude test structures implemented for back-body biasing. . . . . . . . . . . . . . . 50 3.9 Schematic view of the reference generator. . . . . . . . . . . . 51 3.10 Layout view of the reference generator sense resistors and current mirrors. . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.11 Schematic view of the I/O interface. . . . . . . . . . . . . . . 53 3.12 Layout view of the I/O interface. . . . . . . . . . . . . . . . . 55 3.13 Layout view of the implementation block. . . . . . . . . . . . 56 3.14 Layout view of the 1.28 kb SRAM. . . . . . . . . . . . . . . . 57 3.15 Layout view of the 10-bit DAC. . . . . . . . . . . . . . . . . . 59 3.16 Layout view of the capacitor array. . . . . . . . . . . . . . . . 60 3.17 Fabricated ASIC. The layout view is on the left and the 10x microscope view of the chip with bonding work is on the right. 61 3.18 Schematic view of the implemented feedback amplier. . . . . 63 3.19 Cmod A7 with Artix-7 along with schematic view of analog front-end. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.20 ASIC test board with o-chip implementations shown. . . . . 66 3.21 Block diagram of the closed-loop transfer function during cal- ibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.1 Test bench setup with the Keithley 6514 electrometer and power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2 The mismatch accuracy for theory versus simulated (top) and measured (bottom) current mirror test structures. () De- notes a reverse back-body bias of 600 mV. () Denotes cali- brated devices using reverse back-body biasing. . . . . . . . . 79 4.3 The overall accuracy for simulated (top) and measured (bot- tom) current mirror test structures. () Denotes a reverse back-body bias of 600mV . () Denotes calibrated devices using reverse back-body biasing. . . . . . . . . . . . . . . . . 80 x 4.4 The mismatch accuracy for theory versus simulated (top) and measured (bottom) vector magnitude test structures. () De- notes a reverse back-body bias of 600 mV. () Denotes cali- brated devices using reverse back-body biasing. . . . . . . . . 81 4.5 The overall accuracy for simulated (top) and measured (bot- tom) vector magnitude test structures. () Denotes a reverse back-body bias of 600 mV. () Denotes calibrated devices using reverse back-body biasing. . . . . . . . . . . . . . . . . 82 4.6 The measured mismatch accuracy (top) and overall accuracy (bottom) of the current mirror test structures for a power supply variation of10%. . . . . . . . . . . . . . . . . . . . . 83 4.7 The measured mismatch accuracy (top) and overall accuracy (bottom) of the vector magnitude test structures for a power supply variation of10%. . . . . . . . . . . . . . . . . . . . . 84 xi List of Tables 1.1 Performance metrics and their current eciency for weak ver- sus strong inversion. . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Pros and cons to periodicity of mismatch mitigation. . . . . . 12 1.3 Pros and cons to mismatch mitigation bias methods. . . . . . 19 3.1 Pertinent mismatch parameters for thick-oxide (5.2 nm) de- vices. (*) Denotes devices with a reverse back-body bias of 600 mV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2 Pertinent matching properties of the implemented reference generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3 Table showing capable versus measurable -3 dB bandwidth of the implemented test structures. (*) Denotes devices with a back-body bias of 600 mV. (**) Values are given for 3 nA bias current. Increasing or decreasing the bias current by 10x increases/decreases values by 10x. . . . . . . . . . . . . . . . 54 3.4 Table showing the mapping from SRAM input to the dier- ential DAC output. . . . . . . . . . . . . . . . . . . . . . . . . 58 3.5 Table showing the 1 and 16 LSB drift time for dierent stored bias voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6 Important ASIC specications for implemented back-body bi- asing system. (*) Denotes the accuracy limitation of the sense resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.1 Pertinent mismatch parameters for thick-oxide (5.2 nm) de- vices. (*) Denotes devices with a reverse back-body bias of 600 mV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 xii 4.2 Table showing capable versus measurable -3 dB bandwidth of the implemented test structures. (*) Denotes devices with a back-body bias of 600 mV. (**) Values are given for 3 nA bias current. Increasing or decreasing the bias current by 10x increases/decreases values by 10x. . . . . . . . . . . . . . . . 75 4.3 Table showing the speed-power-accuracy trade-o for imple- mented test structures for input currents at 3 nA. . . . . . . 78 xiii Chapter 1 Prospects and Perils of Low-Power Design 1.1 Low-Power Applications The biomedical industry is a rapidly growing eld. It is fueled by the desire to improve human life through modern technology. When parts of the human body are destroyed or no longer work, it is desired to replace those parts with modern technology that restore functionality. Current examples are bionic limbs, pacemakers, knee or joint prosthetics, and many more. One particular branch of biomedical engineering that can bring about drastic improvements to human life is neural prosthetics. This branch deals with interfacing with the human brain and restoring brain function when it is lost. Retinal prosthetics which restore vision to the blind, cochlear implants which restore hearing to the deaf, and deep brain stimulators which reduce the negative eects of Parkinson's Disease all interface with the brain. Other proposed applications include seizure detection and prevention in epileptic patients, restored memory loss to Alzheimer's patients and more. When it is desired to restore brain functionality, one issue that presents itself is what technology will perform the new cognitive functions? This is where electrical engineers come into play. The most practical technol- ogy to attempt to replicate brain functionality is integrated circuits. Today, these chips are able to perform extremely complex functionality in very little space thanks to the drastic improvements in the integrated circuit industry. However, a very big issue with modern integrated circuits is they consume extremely high amounts of power to perform their tasks. For example, a modern cell phone (Samsung Galaxy S10) can go about a day and a half 1 Chapter 1 on a full charge, or play 11 hours of continuous video play. Clearly, modern cell phones are performing extremely complex functions simultaneously and battery life is not too much of a concern since one can simply plug in their phone when the battery gets low. However, if one were to implant an inte- grated circuit inside of their brain in order to improve their living conditions, they would not be able to simply plug in their brain when the battery gets low. Also, if the integrated circuit consumed so much power that the heat it produced actually damaged the cell tissues around it, it would be harming the brain more than it would be helping. Clearly, the power consumption of a neural implant is a very important concern. This leads to a research interest among electrical engineers of ultra-low- power circuits for biomedical implant systems. The direction of the eld is geared toward realizing ecient systems that consume very low power and are able to replicate cognitive functionality. The chips need to consume less than 800 W/mm 2 in order to prevent cell tissue damage and need to operate for years on a single battery. 1.2 Low-Power Case Study: Spike Sorting A necessary process of neural implants is interfacing with the brain. One step during this process is called spike sorting, which is a vital step in all brain-machine interfaces (BMI). When the implant is connected to the brain, it uses electrodes in order to detect brain activity. Each electrode is able to detect activity from multiple neurons within its vicinity. The challenge presented to the implant is that when brain activity is detected, it must know which neuron the activity came from. Spike sorting refers to the process of analyzing an action potential received by an electrode and determining which neuron it came from. Luckily, the action potentials from dierent neurons have dierent shapes to them and thus can be sorted out based on their shape features. The process of spike sorting can be summarized into three basic steps: spike detection, feature extraction, and spike clustering [1]. Spike detection involves distinguishing an action potential from background noise. Feature extraction involves measuring certain shape features of a spike, such as peak- peak voltage, spike duration, maximum rate of change, etc. Spike clustering involves determining which neuron red based on its feature values. One step in clustering is measuring the distance of an input action poten- tial to known action potentials and determining if it is within their threshold radius. The input point and the known points have spacial locations based 2 Chapter 1 Figure 1.1: Analog signal processing block that calculates the vector mag- nitude of two input currents. on the values of their extracted action potential features. The distance can be found by calculating the vector magnitude from the input to the known points. Then, the result can be compared to their threshold radius. One circuit that is an excellent candidate for clustering is shown in Fig. 1.1. This current-mode circuit calculates the vector magnitude of its input currents in real time, namely I out = q I 1 2 +I 2 2 : (1.1) As a result, this current-mode circuit is used as a test vehicle to investigate the results of this thesis. Along with the circuit shown above, there are a multitude of analog cir- cuits which can perform spike detection, feature extraction, and clustering. Since the process can be broken down into simple and relatively few analog blocks, the entire process can be done entirely in the analog domain without need to convert to and from the digital domain [2]. However, the major design challenge is the achievable system accuracy which is the focus for improvement of this thesis. 3 Chapter 1 1.3 Analog vs. Digital Implementation The physical nature of operating transistors in the analog domain makes them far superior to their digital counterpart in computing power. This is because of the complex relationship between current and voltage in analog circuits, and the physical ease of combining currents. When these complex I-V relationships are exploited for computing, complex processes can be per- formed with very few number of devices. For example, addition in the analog domain can be done by simply combining two wires, and multiplication can be done with only 3 transistors. In the digital domain, the addition of only a single bit requires28 transistors, and multiplication requires n 2 adders, where n is the number of bits. Additionally, digital signal processing requires conversion to and from the digital domain and analog-to-digital converters (ADCs) can be power hungry, especially for large numbers of bits. Despite analog's theoretical dominance in physical resources, digital sys- tems have the advantage of accuracy. Analog systems are hindered by noise and distortion. As the analog system becomes more complex and more steps in the signal processing chain are added, these errors add up and the system is ultimately unable to accurately perform its task. Digital systems pro- cess information in bits which are impervious to the errors caused in analog systems. The accuracy of digital systems is dependent on the number of bits used. For increasing number of bits, the number of devices increases drastically; however, very complex systems can be accurately implemented. For simple enough systems, such as the spike sorting neural application, the deciding factor between the two domains comes down to cost. System accuracy costs power and speed (speed is the inverse of area). Each imple- mentation's power and speed, or area, cost scales dierently with desired accuracy. This leads to a crossover between the two implementations for a given accuracy and system complexity. The analog-digital domain crossover point for a given system complexity can be approximated as a function of power and area [3]. Figure 1.2 shows plots of the required power and area to achieve a particular accuracy, which is represented by the signal-to-noise ratio (SNR), for both analog and digital implementations of a system. The gure shows that for relatively simple processing systems, implemen- tation in the analog domain can achieve reasonable accuracy at lower power and area requirements than its digital counterpart. Second, it shows that both power and area place fundamental limits on the maximum achievable SNR ratio in the analog domain. If the allocated area per device is reduced (its speed is increased), the fundamental accuracy limit (dashed line in (a)) 4 Chapter 1 Figure 1.2: Plot of required spent power (a) and area (b) to achieve certain accuracy (SNR) for both analog and digital implementations of a system. Reprinted from [3]. 5 Chapter 1 will shift to the left and reduce the fundamental limit that power has on in- creasing the accuracy. Similarly, if the allocated power per device is reduced, the fundamental accuracy limit (dashed line in (b)) will shift to the left and reduce the fundamental limit that area has on increasing the accuracy. These concepts give rise to the notion of a speed-power-accuracy trade- o that fundamentally limits analog circuit performance. If this limit is good enough and the task is simple enough, processing can be done in the analog domain, reducing the number of bits needed for digitization and/or avoiding the use of an ADC altogether. This work focuses on methods of improving the accuracy of analog cir- cuits in order to improve their fundamental speed-power-accuracy trade-o. It focuses on improving accuracy limitations caused by device area, allowing low-power analog systems to be further pushed in their speed capabilities for simple applications. 1.4 Low-Power Design: Subthreshold Operation The arguments in this section assume the reader has an understanding of weak and strong inversion operating principles. For background information on this topic, the reader is invited to read [4]-[6]. Low-power design refers to circuit designs which consume less power than others that perform the same functionality. Since power consumption is the product of the supply voltage and supply current, low power designs constitutes those that reduce the supply voltage, the supply current, or the rate at which supply current is pulled from the supply voltage. Low power design techniques can include but are not limited to: turning o circuit blocks when they are not used, reducing the amount of `o' or leakage current a circuit block uses, manipulating the clock to digital blocks so that they are not clocked when they do not need to be, operating circuits at lower supply voltages, and operating circuits at lower current levels. The focus of this work is on lowering the current level circuits oper- ate at for applications where thermal noise is not a limiting factor. This can be accomplished by reducing the gate-aspect ratio and/or reducing the overdrive voltage which leads to devices operating in weak inversion. Weak inversion operation maximizes device performance per unit of current spent which leads to more power ecient designs, so this thesis focuses on circuits operating in weak inversion. Supply voltage reduction is a method that can be investigated if the circuit topology has voltage headroom to spare. In fact, the system implemented in this work operates devices at half their 6 Chapter 1 maximum supply voltage; however, this tactic can be increasingly dicult as supply voltages scale with technology. Weak-inversion operation uses devices at gate-source voltages below their threshold voltage. Here, the surface potential ( s (0)), given implicitly by s (0) =V GS V fb +V SB r s (0) +V t e [ s(0)(2 F +V SB )] V t ; (1.2) is strongly controlled by the applied gate-source voltage since the exponen- tial term is negligibly small. For strong-inversion operation, the exponential term dominates and the surface potential sees little change for a change in applied gate-source voltage. Figure 1.3 plots the surface potential with respect to the source-bulk bias versus applied gate-source and source-bulk voltages. Borders between regions of operation are indicated by vertical planes. In weak inversion, the current through the device is exponentially related to the surface potential which leads to the rst-order I-V relationship of a device as I DSw I 0 e K(V GS V th ) V t : (1.3) In Eq. 1.3, I 0 is the null (null relates to when V GS = V th ) weak-inversion current density given by V 2 t (C dep =C ox ), K is the slope coecient given by C ox =(C ox + C dep ) which is usually 0.6-0.8 and often represented by 1/n, V th is the threshold voltage, and the channel conductance is considered a second-order eect. The exponential relationship between the drain current and the gate- source voltage for a device in weak inversion leads to dierent, more power- ecient performance metrics than when the device operates in strong in- version. These metrics are the Thevenin voltage gain (A vTh ), the transition frequency (f t ), the transition frequency current eciency (f t =I DS ), the gate- referred signal-to-noise ratio (SNRj Gate ), and the current eciency of the gate-referred signal-to-noise ratio (SNRj Gate =I DS ). These metrics are listed in Table 1.1 along with which region of operation yields better performance. The Thevenin voltage gain is a measure of how well of a voltage-controlled current source the device behaves. The table shows that devices behave more ideally in weak inversion than in strong inversion. The transition frequency is a measure of the device speed. The table shows that although devices can achieve faster speeds in strong inversion (smaller devices can achieve the same current), the current eciency of speed is optimal in weak inversion. 7 Chapter 1 Figure 1.3: The surface potential at the source with respect to the source- bulk bias versus gate-source and source-bulk voltages for an nMOS device. Values from the 0.5 m device parameters given in [7] as V fb = -627 mV, F = 450 mV, and = 450 m p V are used. The thermal voltage is approx- imated at room temperature as V t = 26 mV and the moderate inversion transition potential is estimated as z 4V t . Also shown are the bound- aries between the dierent regions of operation as vertical planes. Metric Performance Weak Inversion Strong Inversion A vTh 3 f t 3 ft I DS 3 SNRj Gate 3 SNR I DS j Gate 3 Table 1.1: Performance metrics and their current eciency for weak versus strong inversion. 8 Chapter 1 The gate-referred signal-to-noise ratio is a measure of the thermal noise accuracy of the device. Like speed, the table shows that while strong inver- sion can achiever better thermal noise accuracy (the carrier concentration is greater), the thermal noise accuracy per unit of current spent is optimal in weak inversion. The preceding results show that for low-power applications where power eciency is critical, the weak-inversion operating region should be used as much as possible. Unfortunately, a major concern for design in weak inver- sion is the accuracy limitation caused by unavoidable device mismatch. 1.5 Mismatch Impact on Current-Mode Circuit Accuracy The arguments in this section assume the reader has a basic understanding of the causes and eects of mismatch. For background information on this topic, the reader is invited to read [8]-[17]. Mismatch in devices is an unavoidable phenomenon that occurs during fabrication. It causes devices to have an unreliable surface potential for a given input which leads to unreliable device I-V behavior, signal distortion, and a degradation in circuit accuracy. For a current-mode device, which has an input applied at the gate and the output is the resultant drain current, this eect is shown in Fig. 1.4 where an applied gate-source potential results in a range of possible surface potentials. This causes blurring of the I-V characteristic curves among devices, shown in Fig. 1.5, which has a standard deviation based on device geometry and spacing. For voltage-mode devices, where the input is the drain current and the output is the resultant gate-source voltage, this causes a blurring of the resultant gate-source voltage and is also dependent on device geometry and spacing. The eects of mismatch can, at rst order, be linked to standard de- viations in device current factor () and threshold voltage. The latter is relatively the dominant cause of mismatch in weak inversion while the im- pact of former relatively increases for increasing gate-source voltage. Current-mode devices suer the most from mismatch in weak inversion and perform better for increasing gate-source voltage. Voltage-mode devices, on the other hand, suer the least from mismatch in weak inversion and perform worse for increasing gate-source voltage. Despite both types of devices being used in all circuit designs (since they are both necessary for 9 Chapter 1 Figure 1.4: The result of mismatch on the surface potential of a current- mode device for an applied gate-source voltage in weak inversion. Figure 1.5: The I-V curves measured from 96 devices with the same gate- width-to-length ratio of 2m/2m for two dierent source-bulk potentials. Reprinted from [10]. 10 Chapter 1 interfacing between each other), current-mode circuits suer the most from mismatch in weak inversion. The methods proposed in this thesis can be used on both current-mode and voltage-mode devices allowing for compensation of voltage-mode and current-mode circuits and improving their accuracy limitations. However, since current-mode circuits suer the most from mismatch in weak inversion, they are the focus of the implemented test structures of this thesis. Current-mode circuits are powerful building blocks that are used exten- sively in low-power applications. Addition and subtraction of currents can be implemented by utilizing KCL, multiplication and division can be im- plemented using translinear circuits, and conversion to/from the frequency domain can be implemented using log-domain lters. Current mirrors are also used extensively in current-mode design since current signals can usually only be distributed to a single device. The accuracy of current-mode circuits is strongly impacted by the ability of the devices to have matching currents for a given voltage. The normalized standard deviation in output current for a current-mode device in weak inversion at rst order depends on the area of the device and is approximated by I DS I DS WI g m I DS A Vth p WL : (1.4) In Eq. 1.4, g m =I DS is equal to K=V t in weak inversion where it is constant and at a maximum, and A Vth is a mismatch parameter which is technol- ogy dependent. Equation 1.4 implies that for good current matching and high accuracy (small standard deviations in current), area must be spent. The mismatch accuracy of a single device is the inverse of Eq. 1.4 and the overall accuracy of a current-mode circuit is proportionate to the mismatch accuracy of its devices. 1.6 Speed-Power-Accuracy Trade-O In section 1.3 it was shown that analog circuits have a linear relationship between speed, power, and accuracy. This is known as the speed-power- accuracy trade-o and is dened as Speed Accuracy 2 =Power. Increasing the accuracy requires decreasing the speed or increasing the power. For applications where thermal noise is not the limiting factor, the accuracy is limited by the mismatch accuracy. In low-power (weakly inverted) current- mode analog signal processing circuits, this trade-o is proportionate to that 11 Chapter 1 of a single device given by Speed(Acc MM ) 2 Power WI;CM 1 2 K Vt A 2 Vth V DD C ox (1K) : (1.5) In Eq. 1.5, the transition frequency is used for device speed, the mismatch accuracy is the inverse of Eq. 1.4, and the power consumption is the product of device current and supply voltage. Equation 1.5 shows that this funda- mental trade-o in weak inversion is independent of device area and current and depends only on technology parameters and supply voltage. The goal of this thesis is to improve the speed-power-accuracy trade- o by reducing the mismatch accuracy of devices in order to improve the performance of low-power analog circuits so that simple applications can be implemented while saving power. 1.7 Current Methods vs Proposed Method to Mit- igate the Eects of Mismatch Many methods to improve the mismatch accuracy in analog circuits have been proposed in the past [18],[19]. The process involves sampling the un- wanted eects caused by mismatch post-fabrication and then applying a compensation to reduce them. This process can be performed once for long operation times, called calibration, periodically during operation, and even continuously for some applications. Table 1.2 compares the three rates at which mismatch mitigation is im- plemented. Mitigation Method Sampling Power Storage Power 1/f Noise Compensation Dynamic Bias Compensation Circuit Oine Input Conditioning Calibration Negligible Required No No No No Periodic Periodic None Yes Yes Periodic No Continuous Continuous None Yes Yes No Yes Table 1.2: Pros and cons to periodicity of mismatch mitigation. Calibration has an advantage in that it reduces the sampling power to negligible levels since the sampling is performed once and then shut down. However, calibration requires long-term storage which leads to added power consumption. Still, this power consumption can be reduced to very small amounts if voltages are stored at high-impedance nodes. In fact, oating gate technology is able to remove storage power altogether at the cost of device speed degradation. Additionally, calibration circuits never go oine and place no conditioning on the inputs during operation. Other drawbacks 12 Chapter 1 to calibration are that it cannot remove low-frequency noise and it cannot compensate for dynamic biasing. Periodic sampling requires the most sampling power consumption since it is performed constantly during operation and requires fast settling times. With periodic sampling, the storage power is removed since re-sampling re- plenishes the stored value; however, sampling power costs more than storage power. Additionally, the circuit must be taken oine periodically in order to sample the mismatch. Advantages to periodic sampling are that it can remove low-frequency noise, compensate for dynamic biasing, and it does not place conditions on the inputs. Continuous sampling burns sampling power continuously. However, since sampling is performed at low-frequencies, fast settling times are not required. Combined with no required long-term storage power, this allows continuous mismatch mitigation to rival the power consumption of calibration systems. Additionally, it removes low-frequency noise, compensates for dynamic bi- asing, and does not require the circuit to go oine. The major drawback of continuous sampling is the conditioning it imposes on the inputs applied. First, the DC components of the inputs are removed, ruling out applica- tions that require DC information to be processed. Second, for multiple- input single-output (MISO) circuits such as the vector magnitude circuit in Fig. 1.1, further input conditioning (such as frequency of operation) is required in order to compensate for each input. The proposed system uses a calibration mismatch mitigation method since it does not impose conditions on the inputs applied to its test structures and is able to achieve the lowest power for implementation. 1.7.1 Mismatch Sampling The methods used to sample device mismatch depend on the application impacted by device mismatch. For example, if mismatch impacts the dier- ence in phase between two outputs, the dierence in phase can be measured and used to adjust the mismatch. If mismatch impacts the DC oset voltage of an Op-Amp, unity feedback can be used to measure the oset voltage to an error within the oset divided by its open-loop gain. For current-mode circuits, mismatch impacts the output currents owing through the output devices. In order to sample the output current, it must be removed from the operating circuit and sent through a known impedance. Alternatively if the output impedance is well known, the output voltage could be monitored to measure the current at the cost of loading. In order to preserve the speed, it is proposed in this thesis that mul- 13 Chapter 1 tiplexing device currents at the circuit power supplies for sampling would exhibit negligible loading on the device after the sampling takes place. This is because any added capacitance from multiplexing is located at the low- impedance power supply node. Figure 1.6(a) shows sampling the output current at the output of the device which loads the circuit and impairs the achievable speed. Figure 1.6(b) shows the proposed method of multiplex- ing at the low-impedance power supply nodes so that circuit speed is not impaired. Since this technique requires disconnecting the device from the power supply during sampling, it is best suited for calibration or periodic mismatch sampling. Figure 1.6: Methods to sample output current mismatch. (a) Sampling at the output and (b) proposed power-supply sampling method. 14 Chapter 1 1.7.2 Mismatch Compensation An assortment of proposed methods to remove mismatch at the device level have been oered. System-wide mismatch compensation applies device-level compensation to a few predetermined devices. These methods range from physical alteration of the integrated die to redundant fabrication to biasing schemes. Post-fabrication physical alteration Post-fabrication physical alterations such as laser trimming are high-cost and time-consuming methods to mitigate device mismatch. The LTC6078, an amplier used for implementation and discussed in Chapter 3, uses laser trimming to reduce the Op-Amp's oset voltage to below 25 V. This method allows for precise mismatch compensation without impacting the speed-power-accuracy trade-o since the device's matching properties is physically altered after fabrication. Drawbacks to this method include costs involved with post-fabrication physical alterations, time required to ne-tune each IC, and special IC pro- cesses necessary to allow physical alterations. Additionally, the compensa- tion technique can only be used for calibration. Redundancy Redundancy has been another approach used to mitigate mismatch eects. One method fabricates many pairs of devices where proper matching is de- sired. After fabrication, the matching of each pair is measured and a compar- ison algorithm selects the best-matched pair to be switched into the desired circuit for operation [20]. The major drawback to redundancy is the added parasitic capacitance required to route and switch each pair into its operating circuitry, limiting the speed that the circuit can achieve. Another drawback is the added layout area required to fabricate enough devices to ensure a specic accuracy. Last, this method is only suitable for mismatch mitigation via calibration. Biasing The most popular device-level technique to mitigate mismatch is to alter its biasing. Biasing has the advantage that it can be implemented for calibra- tion, periodic, or continuous mismatch mitigation. Usually the bias voltage 15 Chapter 1 is held at the gate of a device since its high impedance leads to the best storage capability. The rst method, shown in Fig. 1.7, places a device in parallel with the one being compensated and applies a bias voltage to its gate. This method is able to adjust the overall output current; however, it does not x the unknown surface potential of the main device and so its current is still unknown. Since the transconductance of a device is proportionate to its current, this leads to mismatch in transconductance. Additionally, the device in parallel requires a tunable current, which leads to added power dissipation for biasing. This compensation method is frequently used for voltage-mode or high-gain circuits such as OTAs and Op-Amps whose AC characteristics are set by precise devices placed in feedback. Figure 1.7: Drain current bias method to compensate mismatch eects. Another method applies a variable bias voltage to the gate of the device. This method, shown in Fig. 1.8, stores the bias voltage across the series capacitor at the input. In order to store the proper voltage across the series capacitor, gate circuitry is required (by switched-capacitor sampling or oating-gate calibration [21]) causing a degradation in device speed. Unlike the current biasing scheme this method is able to adjust the surface potential of the device and better suited for current-mode mismatch mitigation. The next method applies the bias voltage at the source of the device. Like gate biasing, this alters the device's gate-source (and source-bulk) bias 16 Chapter 1 Figure 1.8: Gate voltage bias method to compensate mismatch eects. voltage which compensates for the unknown surface potential. It can be implemented by adding a variable source-degenerative resistor; however, this requires a large bypass capacitor and the stored bias voltage depends on the device output current. A more accurate implementation puts a voltage buer (or similar) at the source at the cost of added power [22]. The proposed bias scheme of this thesis is to apply a reverse bias to the bulk of the device in order to adjust its surface potential by adjusting its threshold voltage. This method does not reduce the device speed since the biasing is done 'behind the scenes' at the bulk. Additionally, the added power competes with gate storage using a switch since both depend on leakage currents either through the switch or the biased device. A review of the current and proposed bias schemes with pros and cons is given in Table 1.3. The goal of this work is to improve the mismatch accuracy of devices while keeping their speed degradation and power consumption at a min- imum. Therefore, this work proposes a calibration scheme that samples current at the power supplies and uses reverse back-body biasing in order to mitigate the eects of mismatch. 17 Chapter 1 Figure 1.9: Source voltage bias method to compensate mismatch eects. Figure 1.10: Proposed bulk voltage reverse-bias method to compensate mis- match eects. 18 Chapter 1 Mitigation Method Surface Potential Compensation Speed Degradation Bias Power Consumption Current Bias 7 3 7 Gate Bias 3 7 3 Source Bias 3 3 7 Bulk Bias 3 3 3 Table 1.3: Pros and cons to mismatch mitigation bias methods. 19 Chapter 2 Proposed System It is proposed that the biasing method in this chapter will reduce inac- curacies caused by mismatch while minimally impacting device speed or power consumption, improving the speed-power-accuracy trade-o. This is achieved by sampling device currents at power-supply connections, shown in Fig. 2.1(a), which adds no loading to the device after sampling takes place. Additionally, reverse-biasing device bulks, shown in Fig. 2.1(b), is able to compensate the device surface potential to mitigate mismatch eects with- out reducing device speed and burning minimal bias power. Figure 2.1: Overview of proposed system. (a)Compensation uses reverse back-body biasing. (b)Power supply current sensing allows for calibration without loading the circuit. 20 Chapter 2 Although the proposed system uses calibration, the back-body biasing compensation can also be implemented with a periodic or continuously sam- pled system for their benets discussed in Chapter 1. Moreover, the sam- pling scheme does not require removing devices from their operating circuit for current sampling, which allows DC osets caused by circuit error to also be mitigated during sampling. 2.1 Intuition It is proposed that the device's threshold voltage dependence on its source- bulk potential should be utilized by altering the bulk voltage of a device to produce reliable I-V behavior. Usually, the bulk terminal is an unused node tied to the power supply or the device's source. Instead of wasting this node, it should be used to improve circuit behavior through the ne-tuning of the device's threshold voltage. This can be viewed as adjusting the device surface potential to counteract the variations caused by mismatch. In order to reverse-bias nMOS devices, a twin-well, triple-well, or similar process is required in order to isolate their bulks from the substrate. If this is not possible, reverse-biasing can be applied to just pMOS devices for circuit compensation. Throughout this work, nMOS devices are used for reverse biasing. 2.2 The Underlying Goal: Having Equal Subthresh- old Current Density A requirement for high circuit accuracy is for its devices to have dependable I-V behavior. However, Chapter 1 showed that this is dicult to achieve for small devices. To determine a solution, we recall the rst-order I-V equation of a device in weak inversion: I DSw I 0 e K(V GS V th ) V t : (2.1) Since the slope coecient (K) is a well-controlled parameter for a given surface potential (bias point) with negligible impact on device mismatch, errors in the I-V behavior of the device due to mismatch can be lumped together into the subthreshold current density (I w ) which is given by I w =I 0 e KV th V t : (2.2) 21 Chapter 2 Suppose now that the source-bulk potential is tuned so that the device has a specic subthreshold current density. The result is a device with dependable I-V behavior. In theory, this process could be repeated for every device, resulting in dierences in subthreshold current density being zero mean and having a standard deviation of zero (in reality, they are reduced to the accuracy limit of the implemented system dictated by second-order eects). In practice, only a few key devices need to be biased in order to compensate for inaccuracies of the overall circuit. Second-order eects such as the channel conductance due to channel- length modulation and drain-induced barrier lowering can also be lumped into the subthreshold current density. During threshold voltage tuning, errors they cause will also get compensated. 2.3 Compensation Using Negative Feedback Negative feedback is the most common method used for determining the bias voltage required for mismatch compensation. In theory, the result is a reduction in the eects of mismatch by the closed-loop gain. In practice, the accuracy is limited by second-order eects. Figure 2.2(a) shows a circuit topology that samples mismatch and uses negative feedback to reverse-bias the bulk of a current-mode nMOS device for an applied gate voltage. Similar methods can be used for pMOS devices. If the drain current is too large, the voltage produced across the reference resistor (R ref ) will be too large, causing the output of the amplier to swing low. Since g mb is positive, this causes the drain current to be reduced. Assuming the amplier is ideal and the device remains saturated during feedback, analysis of Fig. 2.2(a) yields I DSsa = V SS V ref R ref =I wB e KV GSsa V t : (2.3) In Eq. 2.3, I wB stands for the biased subthreshold current density. During calibration, the subthreshold current density is set by the references and applied gate voltage and is given by I wB = V SS V ref R ref e KV GSsa V t : (2.4) The negative feedback forces the drain current to be constant and dened by (2.3). In fact, this feedback can be used to boost the output impedance of a DC current mirror, similar to impedance-boosting techniques used at 22 Chapter 2 Figure 2.2: (a) Proposed negative feedback that generates the required bulk bias during calibration. The `sa' subscript denotes device voltages and cur- rent during mismatch sampling. (b) After V Bias is found, the feedback is removed and the device is allowed to operate normally. the gate of a cascode device. In order to allow normal operation, the reverse- bias voltage is stored and the feedback is removed, as seen in Fig. 2.2(b). After device calibration, its I-V characteristic becomes I DS =I DSsa e K(V G V Gsa ) V t ; (2.5) which gives a dependable I-V characteristic about the calibrated operating point. Using switches to sample the device current at the power supplies adds a benet after the device is returned to normal operation. Because the device remains connected to its load during sampling, Second-order eects caused by a nite channel conductance are compensated for at the operating point during mismatch sampling. The result is dependable behavior for a drain-source potential equal to its value during sampling. One might point out the simple solution to (2.4) of setting V Gsa = V SS , producing I wB = I DSsa . However, this does not compensate the device at its normal operating point, where after programming, the subthreshold cur- rent density may be poorly matched due to circuit error caused by a drift in the drain-source and/or source-bulk potential (for devices with source degeneration). Therefore, it is recommended to calibrate at the desired op- 23 Chapter 2 erating point. Knowledge of the operating point allows for proper reference production during calibration. 2.4 Dierential Feedback Compensation Systemically programming single devices can lead to more dependable circuit behavior; however, it is often desired to have pairs of devices matched to each other. When this is the case, a dierential approach can be used. Dierential feedback can alleviate the required amplier output swing and can cut down on the number of stored values for calibration since a single, dierential voltage can compensate two devices. Figure 2.3 shows dierential feedback being used to calibrate the match- ing between a current-mode device and a voltage-mode device, such as the basic current mirror circuit. An analysis of Fig. 2.3(a) produces expressions for the operating point and current ratio during mismatch sampling as V + Xsa =V ref1 +R ref1 I sa ; (2.6) and I DS2sa I DS1sa = V ref1 V ref2 V + Xsa V ref1 + 1 R ref1 R ref2 = I w2B I w1B (2.7) respectively. In order to ensure matching after calibration, it is necessary to set V + Xsa = V SS in Eq. 2.6. Additionally, it is usually desired to set the calibration current ratio to the ratio of gate-aspect ratios, N/M. If these conditions are met, after calibration the output current becomes I DS2 = N M I in ; (2.8) given that I sa = V SS V ref1 R ref1 (2.9) and N M = V ref1 V ref2 V SS V ref1 + 1 R ref1 R ref2 : (2.10) Equation 2.8 shows after calibration, the current mirror has its desired behavior. Furthermore, second-order eects causing a nite channel con- ductance are also sampled and compensated. A dierence in drain current 24 Chapter 2 Figure 2.3: (a) Dierential feedback circuit that generates the required V Bias for matching two devices. (b) After the required bias voltage is found, the feedback is removed and the devices are allowed to operate nor- mally. due to dierent drain-source potentials between devices is removed about the operating point during mismatch sampling. It is interesting to point out that without the injection of the sampling current into the voltage-mode device of the current mirror, the solution for the calibration operating point in Eq. 2.6 does not have a closed-form solution. For example, if both devices were current-mode devices shown by Fig. 2.4, dierential feedback will match their subthreshold current densities given by Eq. 2.7; however, the operating point, V Xsa , is dened by V + Xsa V ref1 R ref1 =I w1B e K ( V Gsa V + Xsa ) V t ; (2.11) which leads to an elusive design rule. One work-around is to use single-ended feedback for each device during mismatch sampling. Equation 2.11 coupled with the case in Eq. 2.6 where it is dicult to match the sampling current perfectly shed light upon the drawback of dif- ferential programming. This drawback is that it is dicult to accurately 25 Chapter 2 Figure 2.4: Dierential feedback to compensate two current-mode devices. The operating point during mismatch sampling does not have a closed-form solution. set the operating point during mismatch sampling, which depends on the applied sampling current/voltage and references. This can lead to accuracy error after calibration and will be addressed further in section 2.7 along with the proposed solution of using common-mode feedback to adjust the references during mismatch sampling. 2.5 Other Circuits Utilizing Power-Supply Sam- pling It is sometimes desired to match many current-mode devices to a single voltage-mode reference. However, the reference cannot be adjusted dur- ing each compensation, requiring single-ended feedback to be used to com- pensate each current-mode device. Fortunately, the dierential-sampling scheme can be used with single-ended feedback to ensure matching between each device and the reference. Figure 2.5 shows the proposed sampling and compensation scheme for single-ended feedback using a dierential-sampling scheme. This is also one work-around proposed for Fig. 2.4. One may argue that V + Xsa in Fig. 2.5(a) can be tied to V SS and the current through R ref1 does not need to be sampled. In other words, the 26 Chapter 2 Figure 2.5: Using dierential sampling and single-ended feedback to com- pensate a current-mode device to a voltage-mode reference. (a) Feedback scheme during mismsatch sampling and compensation. (b) Circuit after feedback is removed. single-ended sampling scheme in Fig. 2.2 could be used. However, the use of dierential sampling reduces the error in the calibration current ratio given in Eq. 2.7 since common-mode errors involved with current sampling are canceled with dierential sampling. Another circuit, which cannot use current sampling at the source, is the dierential pair since its pair of devices share the same source termi- nal. Instead, mismatch sampling of dierential pairs can be done at their drains. Figure 2.6 shows how a dierential pair of nMOS devices can use the proposed system by sampling current from V DD . During mismatch sampling in Fig. 2.6(a) the operating point is set by the tail current through the dierential pair. After the feedback is removed in Fig. 2.6(b), a drift in the tail current or input gate bias can cause a drift in matching. If dynamic biasing with high accuracy is desired, one solution may be to have the common-mode voltage of the stored dierential bias voltage be a function of the shared-source voltage. 27 Chapter 2 Figure 2.6: Proposed method of using power-supply sensing through V DD to program an nMOS dierential pair. (a) Circuit during mismatch sampling and compensation. (b) Circuit after feedback removal. 2.6 Reference Production The reference production is important since the mean accuracy of devices after calibration is dependent on the accuracy of the references used for mismatch sampling. In other words, the proposed system transfers the I- V accuracy of the devices being compensated to the I-V accuracy of the reference devices. In order to achieve accurate reference devices, the pro- posed work uses large-area MOSFET devices. Other implementations can use smaller passive devices available in CMOS processes which have much better matching than transistor threshold voltage [23]. In Eqns. 2.6 and 2.7 it was shown that in order to choose proper refer- ence values (V ref and R ref ), the sampling current and the ratio of gate-aspect ratios must be known. This cannot be avoided for the proposed sampling method of current-mode circuits. In order for proper mismatch compen- sation, the bias current and gate-aspect ratios of the compensated devices 28 Chapter 2 must be known and stored in the calibration control circuitry. With knowledge of I sa and M/N, the references can be produced with simple circuitry and controls. Two basic methods of reference production will be presented. In each method, it is assumed that the sampling current, or a fraction thereof, can be accurately reproduced on chip. This current (I ref ) is fed to the reference generator and satises I sa = L K I ref : (2.12) 2.6.1 First Reference Production Method In the rst method, the calibration current ratio, given by Eq. 2.7, is simpli- ed by setting V ref1 = V ref2 , which results in R ref1 =R ref2 = N=M. This allows tying the reference voltages together and multiplexing parallel resistors in order to set the current ratio. Figure 2.7(a) shows the method of using a single reference voltage and dierent reference resistors. R ref1 , R ref2 , and R vref are composed of many (T R ) unit-sized resistors allowing them to take values from R ref to R ref =T R . The reference voltage is set by making R vref = R ref1 and sending the same current through each resistor, ensuring V + Xsa = V SS . The tail current is set by using accurate current mirrors and shown in Fig. 2.7(b). M div and M mult2 are composed of many (T M ) unit-sized devices and M mult1 is composed of 2T M unit-sized devices. The input reference cur- rent is divided by KxM and then multiplied by 2xLxM and LxN to produce the proper sampling currents. Values F, m, and n in Fig. 2.7(a) are used to assure best resistor matching during mismatch sampling. Matching accuracy between devices is propor- tionate to the area used to produce each device. In order to assure the best possible matching, the most possible unit-sized devices should be used. To accomplish this, m and n are found by dividing M and N by their greatest common factor (GCF) respectively. F is then found as the largest-integer value satisfying F [max (m;n)]T R : For example, if M=2, N=5, and T R =10, we get m=2, n=5, max (m; n) = 5, and F=2. Thus, four and ten unit-sized reference resistors are used for set- ting the current ratio during calibration as opposed to two and ve, leading to better accuracy. It should be noted that T R hast to be at least max (m; n) for all pairs of devices (F must always be at least one). 29 Chapter 2 Figure 2.7: (a) Proposed rst method of reference production with single V ref . (b) Proposed method of producing the tail current in (a). 30 Chapter 2 Similar to selecting the reference resistors, the most possible unit-sized devices for the current mirrors should be used. Values G, k, and l in Fig. 2.7(b) are used to assure best accuracy in the tail current during mis- match sampling. Like before, k and l are found by dividing K and L by their GCF. G is then found as the largest-integer value satisfying G [max (km;l [max (m;n)])]T M : It should again be noted that G must be at least one, meaning T m has to be bigger than max (km; l [max (m; n)]) across all program pairs. These topologies support a range of current ampliers with calibration current ratios spanning N M = 1; 2;:::;T R 1; 2;:::;T R ; (2.13) and a range in sampling-to-reference current ratios spanning L K = 1; 2;:::;T M =n 1; 2;:::;T M =m : (2.14) 2.6.2 Second Reference Production Method The second proposed method of reference production simplies the cali- bration current ratio by setting (V SS V ref2 ) = (N=M) (V SS V ref1 ), which results in R ref1 = R ref2 . This allows using the same value for each refer- ence resistor and setting the current ratio by multiplexing parallel current mirrors. Figure 2.8(a) shows the second method of reference production by us- ing a single-valued reference resistor. The operating point is set by mak- ing R vref1 = R ref1 and sending the same current through each resistor to ensure V + Xsa = V SS . The second reference voltage is then set by making R vref2 = R vref1 and ensuring the current through R vref2 is N/M-times the current through R vref1 . When N=M, the switch is closed to allow for better matching. Figure 2.8(b) shows how the tail currents are produced in Fig. 2.8(a). M div is composed of many (T M ) unit-sized devices and M mult1 and M mult2 are composed of 2T M unit-sized devices. Similar to the rst method, the input reference current is divided and then multiplied to produce the sampling currents. In order to ensure the best possible matching of current mirrors, G, m, n, l, and k serve the same purpose and are found using the same procedure as 31 Chapter 2 Figure 2.8: (a) Proposed method of producing R ref and V ref using a single R ref value. (b) Proposed method of producing I 1 and I 2 in (a). 32 Chapter 2 in the rst method. These topologies support a range of current ampliers with calibration current ratios spanning N M = 1; 2;:::;T M 1; 2;:::;T M ; (2.15) and a range in sampling-to-reference current ratios spanning L K = 1; 2;:::;T M =n 1; 2;:::;T M =m : (2.16) 2.6.3 Reference Production Comments The larger/smaller N/M and L/K are, the poorer the reference generator accuracy will be since it limits the number of devices that can be used. In both methods, the accuracy of the calibration current ratio is im- pacted by the accuracy of the reference resistors. In the second method, the accuracy of the current mirrors also impacts the accuracy in the current ratio. Conversely, the accuracy of the current mirrors in the rst method only impacts the accuracy of the calibration operating point. Thus, the sec- ond method needs accuracy in both the reference resistors and the current mirrors for very precise current ratios during mismatch sampling. The implementation of the reference generator is limited only by the creativity of the designer. For example, a combination of the two methods described can be used to accommodate a wider range of calibration current ratios and sampling-to-reference current ratios. Usually, the calibration current ratio is more important than the operat- ing point. This is because small deviations in the operating point has a small impact in the calibrated current ratio in comparison to small deviations in the calibration current ratio. Additionally, common-mode feedback can be added in order to adjust the operating point during mismatch sampling which is addressed at the end of the following section. 2.7 Second-Order Eects During Calibration Unfortunately, during oset sampling and compensation systemic errors are unavoidable and can impact the overall accuracy of the proposed system. It is important to address these errors so that they can be mitigated during design. That way, their impact on circuit performance can be dramatically less than the impact of device errors due to mismatch. 33 Chapter 2 All of the systemic errors introduced during dierential feedback can be lumped into two eects on the feedback network. These eects are an error in the calibration current ratio and an error in the calibration operating point. Many causes for error are repeated since dierential errors impact the current ratio while absolute errors (called oset) impact the operating point. 2.7.1 Error in Calibration-Current Ratio An error in the calibration current ratio during mismatch sampling directly impacts the matching performance of the proposed system. A dierence in sampling currents from their desired values translates to I w2B =I w1B 6= N=M for reverse-biased devices after feedback removal. This creates a mean gain error in the desired output current and can be caused by any of the following phenomena. Mismatch in Reference Resistors This eect is important as the calibration current ratio given by Eq. 2.7 is directly proportionate to the ratio of reference resistors. This means the ability to sense the current through each device depends on the accuracy of the devices used to sense each current. Amplier Oset Voltage Another important eect on the mean matching accuracy is the amplier o- set voltage. All ampliers have an inherent oset voltage caused by process and temperature variations. Any oset voltage in the amplier input dur- ing mismatch sampling directly results in an error in the calibration current ratio. Feedback Removal Storage of the reverse-bias voltage for compensation presents complications in the matching accuracy. When the bulks are disconnected from the feed- back network, osets in each polarity of the stored voltage can be induced. If these osets are dierent, an error in the calibration current ratio is pro- duced. Additionally, the stored voltage may drift over time. If the drift of each bulk is dierent, an error in the current ratio increases with time. Solutions to these errors are to include the disconnection of the stored volt- age in the feedback loop during calibration, which can be viewed as having 34 Chapter 2 a sample and hold in the feedback, and to periodically refresh the stored reverse-bias voltage. Amplier Gain For a feedback amplier with nite gain, the dierence in the amplier's input voltages is a function of the closed-loop gain. This dierence in input voltage leads to an error in the ratio of the program currents. The larger the closed-loop gain is, the smaller this error is. The amplier gain must then be large enough to suppress the standard deviation in input voltage to be much less than the oset voltage of the amplier and the reference resistors. Dierence in Sampling Current A dierence in sampling current can be caused by leakage current from closed switches connected to the reference resistors, errors in the current mirrors within the reference production, and amplier input bias currents. This eect can be be made small with good design practices. In the implemented system of Chapter 3, very large diode-connected MOSFET devices are used to sample the mismatch current. Due to their large size, it is desirable to use the same devices for sensing many device pairs. During calibration, all pairs that are disconnected from the sampling resistors can induce a leakage current into the sense devices from the open switches. If there is an imbalance of leakage current into the two sense de- vices, this creates an error in the ratio of sense currents. During design, care should be taken so that each sense device has the same amount of discon- nections so that the leakage current is as balanced as possible to mitigate this error. Errors in the current mirrors within the reference production lead to dierential errors on the reference voltages. This will cause an error in the calibration current ratio unless implementation of the rst method for reference generation is used. For this reason, the implemented system in Chapter 3 uses the rst method of reference generation. In order to mitigate the imbalance of amplier input bias current, the connections to the amplier inputs should be made as symmetric as possible. Dierence in Switch `On' Resistance The switches connecting device pairs to the reference resistors during their calibration present an `on' resistance. If the `on' resistance of the two 35 Chapter 2 switches have a substantially dierent voltage drop during mismatch sam- pling, an error in the current ratio will occur. During design, the voltage drop produced by closed switches should be made much smaller than the allowable oset voltage of the amplier. 2.7.2 Error in Calibration Operating Point Errors in the calibration operating point during mismatch sampling means a shift in the source potential after the feedback is removed. This causes an increase in the mean gain error since both drain-source and source-bulk potential shifts after mismatch sampling and compensation. Error in the operating point can be caused by any of the following sources. Oset in Sampling Current When the current into the sampling resistors does not match the tail currents in the reference generator, an error in the program operating point occurs. This is caused by leakage currents from closed switches, errors in the current mirrors within the reference generation, and input bias current to the input of the amplier. Leakage currents and amplier input bias current impacts the lowest possible sampling current that can be used for mismatch sampling. For high accuracy, the mismatch sampling current should be an order of magnitude larger than the overall leakage current and the amplier input bias current. Current mirror errors within reference generation cause dierent errors in the operating point for dierent sampling currents. Oset in Reference Resistors An oset in the absolute value of the reference resistors produces an error in the program operating point. This can be seen in Eq. 2.6 where the operating point is dependent on the product of R ref1 and the mismatch sampling current. Switch `On' Resistance Switches that connect device pairs to the reference generator during mis- match sampling should not present a substantial `on' resistance or an error in the program operating point occurs. If the voltage drop caused by closed switches is much smaller than the allowed amplier oset voltage, this prob- lem should be mitigated. 36 Chapter 2 Noise During calibration, noise can impact both the program current ratio and the program operating point. Appropriate ltering should be used in the feed- back loop in order to mitigate the impacts of noise on the system accuracy. 2.7.3 Lumped Impact of Second-Order Eects The previously discussed second-order eects during mismatch sampling and compensation can be lumped into errors in the sampling current ratio and errors in the operating point. Errors that are consistent among all device pairs, such as those due to the amplier and references, cause a mean error in the system accuracy. Errors that are dierent between device pairs, like those due to switches, cause a standard deviation in system errors, degrading the mismatch accuracy of the system. After calibration, these errors impact the gain ratio and can be given by I out I in = N M 1 + N M f V + Xsa V SS : (2.17) In Eq. 2.17, the N=M term represents the error in the current ratio and f V + Xsa V SS represents the error in the operating point. It can be seen that errors in the current ratio directly impact the accuracy of the proposed system after calibration. The impact of the operating point causes additional errors in the gain ratio due to a dierence in the drain-source and source-bulk voltages after the feedback is removed. A shift in the drain-source voltage after mismatch sampling compromises the surface potential matching of reverse back-body biasing. In order to mitigate the eects of operating point errors after calibration, it is proposed that common-mode feedback can be used. During mismatch current sampling, the operating point can be measured and compared to V SS . Dierences between the two can produce a compensation current to the current mirrors proposed in section 2.6. Figure 2.9 shows operating point compensation during dierential mismatch sampling (enclosed by the bold rectangle) implemented with the rst method of reference generation. With the proposed reduction in operating point errors, only the gain ratio would contribute to signicant errors after device calibration. 37 Chapter 2 Figure 2.9: Proposed method of calibration operating point compensation implemented with the rst method of reference production. 2.8 Required Output Voltage Swing An important design criterion is implicated by the need for reverse-biasing device bulks, which can be seen by the supply connections of the feedback amplier. This reverse bias translates as a reduction in the subthreshold current density, namely I wB I w j V B =V SS : (2.18) This reduction can cause a shift in the desired operating point of the com- pensated devices. Therefore, it is recommended for design to be done with compensated devices having their bulk tied to the output common-mode voltage of the feedback amplier. This allows for positive and negative ad- justments to the subthreshold current density, without causing too drastic of a change in the required input bias for the desired operating point. In other words, devices should be designed with an estimated value for I wB as I wB = I w j V B =Vocm : (2.19) If instead, design is performed with device bulks tied to the power supply, the operating point of the device may be drastically dierent after calibration than expected. Moreover, the device may be operating in deep depletion. The ability of the feedback amplier to have enough output swing to ne-tune all the desired devices leads to the consideration of required output swing. This swing depends on the amount of error being compensated and 38 Chapter 2 on the ability the bulk has on adjusting device current (its bulk transcon- ductance, g mb ). It can be shown that the required swing for mismatch in threshold voltage for dierential feedback can be approximated by MAX (V Bias ) 3 (V th ) 2 +2 3 (V th ) s 2 F 3 4 3 (V th ) 2 : (2.20) Poorer device accuracy leads to large standard deviations in threshold volt- age, requiring a larger output swing. Smaller body eect leads to smaller bulk transconductance, also requiring a larger output swing. If large dif- ferences in drain-source voltage is expected during calibration, additional headroom should be added as this eect is also compensated for. Figure 2.10 shows the proposed power supplies required for reverse back- body biasing. The device sees a maximum increase in threshold voltage that is able to accommodate the maximum deviation in threshold voltage due to mismatch accuracy. Meanwhile, the added power supply domain is able to accommodate the maximum output swing of the feedback amplier. Figure 2.10: Proposed power supply implementation for reverse-biased de- vices. Other systems can impose dierent but similar requirements on the out- put swing. For example, the output common-mode voltage of the feedback amplier can be set to V SS , causing only one bulk (depending on the mis- match polarity) to be reverse-biased for matching while the other sits at the power-supply voltage. This would require design to be done with de- vice bulks set to the estimated mean in reverse-bias voltages, which can be approximated as (g m =g mb ) (V th ). 39 Chapter 2 2.9 Accuracy Improvement of Proposed System In the proposed system, feedback is used to ne-tune the matching of device pairs. It can be shown that the closed-loop input voltage to the feedback amplier is given as V in;CL = V in 1 1 +T +V off T 1 +T : (2.21) In Eq 2.21, V in is the dierential input voltage caused by device mismatch which has a standard deviation equal to (V th ) of the selected device pair (along with second-order eects). Meanwhile, V o is relatively constant and due to mismatch in the reference resistors, amplier built-in oset voltage, and other 2nd-order eects. The relationship between amplier input voltage and the calibration cur- rent ratio is N M = V in;CL g m I DS where g m =I DS in weak inversion is approximately constant. This leads to the accuracy in current ratio after calibration to be N M = g m I DS V in 1 1 +T +V off T 1 +T : (2.22) The proposed system improves the mismatch accuracy of the calibrated device pairs by the closed-loop gain of the feedback system. Meanwhile, the mean accuracy is given by the errors described in section 2.7. With a large enough loop gain, the reduction in mismatch accuracy vanishes below the system accuracy caused by standard deviations in errors described in section 2.7. 40 Chapter 3 Implementation of Proposed System In order to demonstrate the biasing method described in Chapter 2, a semi- autonomous self-calibrating system capable of biasing forty test structures was built. In addition, twenty-three reference cells were built with areas ranging from 1x-100x the area of the calibration structures to compare their accuracy performance. The two implemented current-mode test structures are shown in Fig. 3.1. The rst is a current mirror and the second is a seven- transistor (7-T) translinear circuit that computes the vector magnitude of two input currents. The system achieves a mismatch accuracy corresponding to a standard deviation in normalized output current of less than 1 %. In comparison to the accuracy of minimum-sized devices, this demonstrates an improvement in required area by a factor of 1,200. 3.1 Overall System Description The implemented mixed-signal system consists of an application-specic in- tegrated circuit (ASIC) interfacing with an o-chip eld-programmable gate array (FPGA) and feedback amplier. The entire system block diagram is shown in Fig. 3.2. The ASIC, outlined in green, contains test structures, an input-output (I/O) interface, reference generators, control logic, and long- term storage. O-chip implementations are outlined in blue. Along with the FPGA and feedback amplier, power-supply generation, a bias current generator, and FPGA controls were implemented o chip. The ASIC was built using Global Foundries' 130nm SiGe BiCMOS pro- 41 Chapter 3 Figure 3.1: Current-mode test circuits implemented for testing the pro- posed biasing method. (a) A standard current mirror without circuit error compensations (cascode devices, feedback, etc.). (b) A 7-T translinear two- dimensional vector magnitude circuit implemented with nMOS devices. cess. The FPGA used for implementation is the Xilinx Artix-7 which con- tains two 12-bit analog-to-digital converters (ADCs). The feedback amplier is implemented using the LTC6078 dual precision Op-Amps followed by two LTC6363 precision dierential Op-Amps. The reverse-bias voltages are stored digitally with ten-bit accuracy in a static random-access memory (SRAM). Their values are held by a capacitor and periodically refreshed using a digital-to-analog converter (DAC). During normal operation, input voltages are sent to the I/O interface to produce the input current(s). The output current is also sampled by the I/O interface. Both input and output currents are then amplied approximately one-thousand times and sent o chip for measurements. The exact ampli- cation can be measured by a calibration test site which sends the input current directly o chip. During auto-calibration of the test structures, the I/O interface is used to generate the sampling current and distribute it to the selected test structure and the reference generator. The voltages produced across the sense resistors within the reference generator are sent o chip to a feedback amplier. After amplication and low-pass ltering, the voltages are sampled by the FPGA's two ADCs. Their results are subtracted with 10-bit accuracy and 42 Chapter 3 Figure 3.2: Block-level diagram of implemented system. Blocks imple- mented on the ASIC are outlined in green. Blocks implemented external to the ASIC are outlined in blue. 43 Chapter 3 then written to the SRAM and refreshed by the DAC inside the long-term storage block. The control logic multiplexes the I/O interface and the reference gener- ator between the test structures to select which one to measure or calibrate. The long-term storage block stores and refreshes the reverse-biased bulk potentials of the forty test structures capable of mismatch compensation. 3.2 The ASIC The ASIC can be broken up into two main blocks, the implementation block and the long-term storage block. The long-term storage block can be seen directly in Fig. 3.2 and will be discussed after the implementation block which consists of everything else. Before the implementation block descrip- tion, the ASIC power supply domains will be addressed along with the use of thick-oxide and thin-oxide devices. 3.2.1 Power-Supply Domains The implemented system operates using two power-supply domains in order to reverse-bias device wells. The additional power-supply domain operates from 0V - 1.2V (V SS2 - V DD2 ). The biasing of the nMOS device wells and most of the long-term storage blocks operate within this domain. Analog ground (V DD2 =2) for dierential signals along with external controls for the maximum and minimum DAC output range are also present within this domain. The primary power-supply domain operates from 1.2 V - 2.4 V (V SS - V DD ). Most of the implementation block operates within this domain, including all of the test structures. Digital and analog supplies were kept separate to reduce digital noise. The result is a total of eleven power-supply voltages (seven analog and four digital) that power the ASIC and are shown in Fig. 3.3. The BiCMOS-8HP process used for ASIC implementation contains both thin-oxide (2.2 nm) and thick-oxide (5.2 nm) devices. Its training manual recommends that thin-oxide devices should not exceed 1.6 V across any two terminals, including drain-to-bulk. Similarly, thick-oxide devices should only sustain up to 2.7 V across any two terminals. Therefore, thick-oxide devices are used for the test structures since the implemented system can have a maximal drain-to-bulk voltage of 2.4V. Meanwhile, most of the long-term storage block is built using thin-oxide devices which only operate from 0 V - 1.2 V. 44 Chapter 3 Figure 3.3: Power supply domains for implemented ASIC. 3.2.2 Implementation Block The implementation block contains the test structures, I/O interface, refer- ence generator, and control logic that is run by the FPGA. In an attempt to achieve decent statistical data for mismatch, each chip contains sixty-three test locations. Unfortunately, multiplexing the I/O interface between so many test sites does not allow their speed capability to be tested. Instead, their simulated speed capability is used and given with the I/O interface description. Test Structures The test structures were implemented with nMOS devices using triple-well structures available in the BiCMOS-8HP process. Of the forty test struc- tures that can be calibrated, eight of them are current mirrors and thirty-two of them are vector magnitude circuits; however, sixteen of the vector magni- tude test structures were not used for measurements which is discussed be- low. Both were implemented using minimum-sized devices with gate-aspect ratios of 0.36 m/0.24 m. For both current mirror and vector magnitude circuits, there were three 45 Chapter 3 dierent reference test structures with increasing area that were built to compare to for accuracy considerations. They were implemented with minimum-sized devices along with devices with gate-aspect ratios of 0.94 m/0.94m and 3m/3m. This allowed for comparison between devices with areas increasing in order of magnitude. Pertinent matching properties for the implemented test structures are given in table 3.1. They were found using Monte Carlo simulations of the BiCMOS-8HP design kit, which includes mismatch due to device current density and threshold voltage and includes short-channel eects. Gate-Aspect Ratio [m/m] Area [m] 2 I DS I DS [ % ] (V th ) [ mV ] 0.36 / 0.24 0.0864 78 23 0.36 / 0.24 0.0864 79 23 0.94 / 0.94 0.8836 11 3.7 3 / 3 9 3.2 1.0 Table 3.1: Pertinent mismatch parameters for thick-oxide (5.2 nm) devices. (*) Denotes devices with a reverse back-body bias of 600 mV. Current Mirror Test Structures Figure 3.4 shows the current mirror test structure schematic imple- mented for back-body biasing. Single-ended feedback is used for adjusting the well bias of a single device because all of the dierential long-term stor- age locations were used for the vector magnitude test structures. In the implemented current mirrors, the voltage-mode device well is tuned, while the current-mode device well is held at the reference. The opposite could have been implemented with a reverse in the feedback polarity. The current mirror test structure requires only a single feedback cycle for calibration. The sources of M 1 and M 2 are connected to the reference generator and the sampling current is applied at the input while V b1 is tuned. An nMOS device is used for the switch to V SS2 and a pMOS device is used for the switch to the reference generator since each only pass a low or high voltage respectively. Transmission gates are used for the switches connected to the I/O interface. Current mirror test structures connected to the reference generator have a single connection to R ref1 and R ref2 so disconnected sites should have a minimal imbalance of leakage current. The layout view of the current mirror test structures are shown in Fig. 3.5. Back-body biasing requires the wells to be spaced, leading to a slight increase in used area. The minimum-sized reference test structures 46 Chapter 3 Figure 3.4: Schematic view of the current mirror test structure implemented for back-body biasing. were not implemented with current owing in the same direction which can lead to poorer matching properties. The larger reference test structures have better layout techniques and all of the reference structures use dummy devices. Vector Magnitude Test Structures The vector magnitude test structure implemented for back-body biasing is shown in Fig. 3.6. Dierential feedback is used for tuning both voltage- mode and current-mode device wells. Devices M 1 and M 2 along with M 3 and M 4 were placed in the same well to achieve a more compact layout. The vector magnitude test structure requires two feedback cycles for calibration. First, the sources of M 1 and M 5 are connected to the reference generator while V b2 and V b6 are tuned. During this time, the sampling current is applied at I in1 while I in2 is nulled so that it does not impact matching. Then, the same procedure is used to tune V b4 and V b7 . The result is a matched vector magnitude when a single input is applied, which leads to a small deviation from the calibrated operating point when both inputs are applied. The vector magnitude test structures use the same type of switches as the current mirror test structures. Each vector magnitude test structure connected to the reference generator contains two multiplexed connections 47 Chapter 3 Figure 3.5: Layout view of the current mirror test structures. Figure 3.6: Schematic view of vector magnitude test structures implemented for back-body biasing. 48 Chapter 3 to R ref1 and only one connection to R ref2 . In order to minimize the imbalance of leakage current of disconnected devices, half of the vector magnitude test structures have their connections to the reference generator reversed. Additionally the polarity of the feedback to their well voltages is reversed to maintain negative feedback. The layout view of the vector magnitude test structures is shown in Fig. 3.7. Similar to the current mirror layout, dummy devices are used on all references and the larger references have better layout techniques. Figure 3.7: Layout view of vector magnitude test structures. Unused Vector Magnitude Test Structures Sixteen vector magnitude test structures that were not used for mea- surements are shown in Fig. 3.8. The wells of M 1 and M 2 along with M 3 and M 4 were separated in an attempt to match the bias point of the lower devices and the upper devices to each other. Switches were added to bypass the upper devices while calibrating the lower devices. After chip fabrication, it was realized that the added complexity does not lead to added accuracy (along with lowering their maximum speed due to the added switches) and so they were not used for measurements. However, if the switches were removed and the wells of the upper devices were all tied to their 49 Chapter 3 Figure 3.8: Schematic view of unused vector magnitude test structures im- plemented for back-body biasing. source, this circuit implementation would achieve matching while removing the body eect from the upper devices. This leads to more accurate circuit behavior after calibration and is further addressed in Chapter 4. Reference Generator The reference generator was implemented using the single V ref scheme dis- cussed in Chapter 2 and shown in Fig. 3.9. In the implemented system, all test structures have a sampling current ratio of 1 allowing R ref1 , R ref2 , and R vref to maintain the same value across all test locations. The K = 2 switches were added for calibrating the unused vector magnitude test struc- tures. The reference generator mirrors the input current from both inputs of the I/O interface and then multiplexes their output for I X . It was later realized that multiplexing the input currents from the I/O interface would have saved space and produced the same I X error while calibrating each input. For accuracy concerns, the largest devices were used as the sense resistors to measure the dierence in sampling current since their matching directly impacts the calibration current ratio. Very large (90 m x 45 m) thick- oxide diode-connected pMOS devices are used for R ref1 , R ref2 , and R vref . 50 Chapter 3 Figure 3.9: Schematic view of the reference generator. pMOS devices were used so the diode-connection of their gate/drain node placed their large capacitance at V ref . This better ensures that this node appears as a virtual ground during small-signal analysis and alleviates the capacitance that the sense voltages see for o-chip measurements; however, nMOS devices would have allowed for better sampling accuracy. Large (10m x 10m) thick-oxide nMOS devices are used to mirror the sampling current to produce I X . They are not as large as the sense resistors since the operating point accuracy does not impact the calibration accuracy as much as the sampling current ratio (see chapter 2). The accuracy of the implemented reference generator for sampling cur- rent ratio and program operating point is given in table 3.2. The layout view of the reference generator is shown in Fig. 3.10. The devices used to sense and mirror the sampling currents were built using an interdigitated, common-centroid layout for matching purposes. I/O Interface An I/O interface was built to interface with the test structures. Its schematic is shown in Fig. 3.11. It uses two o-chip input voltages to generate input currents during normal operation and sampling currents during calibration. 51 Chapter 3 Error Culprit I DS I DS [%] (V th ) [mV ] R ref 0.3 0.11 I X 0.97 - Table 3.2: Pertinent matching properties of the implemented reference gen- erator. Figure 3.10: Layout view of the reference generator sense resistors and cur- rent mirrors. 52 Chapter 3 It also senses the output current and amplies both input and output cur- rents by approximately one-thousand before they are sent o chip for mea- surements. Figure 3.11: Schematic view of the I/O interface. During calibration, large input devices (10 m x 10 m) are used to generate the sampling current and accurately mirror it to the reference gen- erator. The accuracy of replicating the sampling current is given by I sa I sa = 2:1%: Combined with the reference generator current mirror accuracy, the overall standard deviation in I X during calibration is about 1.6 %. During normal operation, smaller devices (2 m x 1 m) are used to generate the input currents and mirror them to the o-chip current ampli- er. Smaller devices were used to lower the capacitive load on the input test structures; however, a large amount of parasitic capacitance was present in the system due to multiplexing between sixty-four test locations. This lim- ited the test speed for the implemented current density. A table of capable versus measurable -3 dB bandwidth for the various test structures is shown in Table 3.3. Simulated data is for implemented layouts with extracted parasitics. The I/O interface uses a small (1 m x 1 m) diode-connected pMOS load to sense the output current and then mirror it to the amplier. The output current sense and amplication topology was designed to minimize 53 Chapter 3 Topology Area [m] 2 Capable f 3dB [MHz] Measurable f 3dB [kHz] 0.0864 13 30 0.0864 9.7 30 Current Mirror 0.8836 3.1 24.5 9 0.58 23.4 0.0864 6.5 20 0.0864 5.1 20 Vector Magnitude 0.8836 1.2 18.3 9 0.26 17.8 Table 3.3: Table showing capable versus measurable -3 dB bandwidth of the implemented test structures. (*) Denotes devices with a back-body bias of 600 mV. (**) Values are given for 3 nA bias current. Increasing or decreasing the bias current by 10x increases/decreases values by 10x. the load on the test structures and to maximize the reliability of the ampli- cation. In order to determine the exact amplication of the o-chip current ampliers, a calibration test structure was used. When the calibration test structure is selected, the input and output currents going to/from the test structures are sent o chip through dummy devices in order to mimic the test structures. This allows the measurement of the test structure currents and the amplied output currents simultaneously. The I/O transmission gate switches used to multiplex the test structures to the I/O interface have a maximum on resistance of 80 k resulting in negligible voltage drops over the current ranges of interest. Their maximal leakage current is approximately 2.5 pA, leading to a total worst-case leakage current from the I/O interface due to o test structures to be less than 155 pA. For current levels of at least one order of magnitude larger than the total leakage (approximately 1 nA), the o-chip sense currents become a good approximation for the test structure currents (better than 90 % accurate). The layout view of the I/O interface is shown in Fig. 3.12. Interdigi- tated, common-centroid layout was used for reliable current mirroring and amplication. Control Logic and Overall Implementation The control logic was built in order to produce all of the switch controls for the implementation block. It multiplexes the test structures to the reference generator and I/O interface, and controls the switches within the reference generator and I/O interface. 54 Chapter 3 Figure 3.12: Layout view of the I/O interface. The entire implementation block is shown in Fig. 3.13. The control logic can be seen on the left and right sides. The test structures form the two rows along the top and bottom. The reference generator and I/O interface are on the left in-between the test structures. 3.2.3 On-Chip Long-Term Storage The on-chip long-term storage consists of a SRAM, DAC, and capacitor ar- ray. The SRAM stores digital values for long periods of time while the DAC periodically reads from the SRAM, and refreshes the value being temporar- ily held by a capacitor. The system is capable of storing 128 10-bit values. The DAC is able to update the analog value being held across a capacitor at a rate of 1 MHz. With an output range of1 V and 10-bit accuracy, the minimum step size (LSB) of is 2 mV. The DAC connects to a capacitor array with 128 52 fF capacitors capable of holding reverse-bias voltages for up to 10 ms. Half of the capacitor array storage capacitors are capable of storing dierential bias voltages and the other half are capable of storing single-ended bias voltages. All specications in the following sections are based on worst-case post- layout Monte Carlo simulations including process variation and mismatch. 55 Chapter 3 Figure 3.13: Layout view of the implementation block. The SRAM A 1.28 kb SRAM capable of storing 128 10-bit values was built for long- term storage. With read and write speeds of less than 10 ns, it is more than capable of providing data to the DAC at its 1 MSPS operation speed. The SRAM is shown in Fig. 3.14. The middle section contains the 6-T SRAM cells that are split into two 64 x 10-bit arrays. The address decoder runs along the left and right-hand sides of the SRAM array. The pre-charge circuit, write-enable circuit, sense ampliers, and read latches are all located at the bottom of the SRAM array. The logic-level converters and buers for the input-control logic are on the left-hand side. The DAC A 10-bit, 1 MSPS, charge-redistribution DAC was built to periodically con- vert the digitally-stored values in the SRAM and refresh their voltage being held by the capacitor array. In order to keep with the low-power theme of the implemented system, a charge-redistribution architecture was used. The DAC is split into two stages in order to minimize the parasitic load on 56 Chapter 3 Figure 3.14: Layout view of the 1.28 kb SRAM. the Op-Amps driving each stage. The rst stage is a 4-bit converter, fol- lowed by a 5-bit second stage. Since a dierential architecture is used, the polarity (tenth bit) is coded in the MSB of the input. To ensure a monotoni- cally increasing output, the capacitive ladders of each stage were built using a common-centroid layout of unit-sized 52 fF capacitors. Each stage uses a parasitic-insensitive, oset-compensating switched capacitor architecture described in Chapter 6 of [24]. A fully dierential Op-Amp designed for 10-bit accuracy was built to drive each stage of the DAC. It achieves 70 dB gain and has a unity-gain frequency of 20 MHz with 50 degrees of phase margin. It has a settling time of less than 0.3 s and consumes 35 W of static power. A two-stage folded-cascode architecture with compensation techniques described in [25] was used. The common-mode feedback uses N and P source-following buers on each output along with high resistance polysilicon resistors to sample the output common-mode voltage. The bias currents for each Op-Amp are generated using an o-chip bias voltage. The bias voltage is fed into large (10 m x 10 m) devices to be accurately mirrored three times. Two of the bias currents are distributed to 57 Chapter 3 the two Op-Amps and the third is fed o chip for sampling. The DAC input functions with values in signed-magnitude form while the SRAM stores values in their unsigned binary form. Therefore, a digital converter was built that converts inputs from unsigned binary to signed- magnitude and stores the converted code in ip- ops at the beginning of the conversion process. Table 3.4 shows the mapping for the conversion process of the stored SRAM code to the dierential DAC output value. Stored SRAM Code Signed-Magnitude DAC Input V out 11 1111 1111 11 1111 1111 511 LSB's 11 1111 1110 11 1111 1110 510 LSB's . . . . . . . . . 10 0000 0010 10 0000 0010 2 LSB's 10 0000 0001 10 0000 0001 1 LSB's 10 0000 0000 00 0000 0000 10 0000 0000 0 LSB's 01 1111 1111 00 0000 0001 -1 LSB's 01 1111 1110 00 0000 0010 -2 LSB's . . . . . . . . . 00 0000 0010 01 1111 1110 -510 LSB's 00 0000 0001 01 1111 1111 -511 LSB's Table 3.4: Table showing the mapping from SRAM input to the dierential DAC output. The output voltage range of the DAC is controlled by two voltages in- dependent of the DAC power supply. These voltages are generated o chip allowing external control of the output-voltage range. For matching the ADC input range, the output voltage range was set to1 V. The 10-bit fully-dierential DAC is shown in Fig. 3.15. On the left is the logic level-converter and buer for the input clock signal, the non- overlapping phase generator with reset and phase buers, and the input bit-code conversion with ip- ops and buers. On the top and bottom are the two 4-bit and 5-bit common-centroid capacitive ladders used for rst and second stage respectively. Between the capacitive ladders of each stage is the fully dierential Op-Amp driving them. The switch logic for both stages are located in between each stage near the center. The bias current generator for both Op-Amps is located on the bottom right. Monte Carlo simulations showed a worst-case INL of less than 1 LSB, demonstrating monotonically-increasing functionality. 58 Chapter 3 Figure 3.15: Layout view of the 10-bit DAC. The Capacitor Array A capacitor array of 128 52 fF capacitors was built for short-term ana- log storage. The storage time of the capacitor array is dependent on the voltage stored. The main source for stored-voltage drift is from leakage current through the switches used to connect each capacitor to the output of the DAC. Larger stored voltages cause more leakage current and faster drift times. Longer storage times can be obtained by better design of these switches. A list of worst-case (fast process corner) drift times for stored voltages is given in Table 3.5. Storage times for 6-bit accuracy (16 LSB t drift ) is also listed since this was the accuracy limitation of the implemented system. In practice, the capacitor array was able to store bias voltages for 10 ms without compromising accuracy. The capacitor array is shown in Fig. 3.16. The 64 capacitors used for single well storage are located in the top-left array. The 64 capacitors used for dierential well storage are located in the bottom-right array. The de- coders and switches controlling access from the output of the DAC to the capacitor location are located along the bottom-left and bottom-right. On the far right is the logic-level converters and buers for the input-control logic. 59 Chapter 3 Stored Voltage [mV] 1 LSB t drift [ms] 16 LSB t drift [ms] 250 5 80 500 2 32 750 0.25 4 1000 0.005 0.112 Table 3.5: Table showing the 1 and 16 LSB drift time for dierent stored bias voltages. Figure 3.16: Layout view of the capacitor array. 60 Chapter 3 3.2.4 ASIC Overview Figure 3.17 shows both layout view and microscope view (with a zoom of 10x) of the 2 mm x 2 mm fabricated ASIC. The implementation block is outlined in yellow and the long-term storage is outlined in red. Additional space was used for power-supply bypass capacitors outlined in purple. Bond- ing pads with ESD protection for HBM and CBM discharge were built and connected to an RC power clamp located in each corner. Figure 3.17: Fabricated ASIC. The layout view is on the left and the 10x microscope view of the chip with bonding work is on the right. The long-term storage block used up more area than expected due to the use of MIM-capacitors for the DAC capacitive ladder and the capacitor array. Signicant space can be saved if the long-term storage were implemented dierently as will be discussed in Chapter 5. Table 3.6 lists an overview of the implemented ASIC specications. The DAC was designed for 10-bit accuracy, but the accuracy limitations imposed by second-order eects can be achieved with only 6 bits. This means the long-term storage block was over-designed by a factor of 16x. With the removal of the rst stage of the DAC, the same accuracy could be achieved while cutting the power consumption in half. 61 Chapter 3 Block Specications Calibration Test Structures Mismatch Accuracy (V th ) = 23 mV Reference Generator Sense Accuracy (V Xsa ) = 100 V I/O Interface Max Speed 30 kHz SRAM Read/Write Speed 10 ns DAC Max Speed Power 1 MSPS 70 W Capcitive Array Storage Time 10 ms Table 3.6: Important ASIC specications for implemented back-body bias- ing system. (*) Denotes the accuracy limitation of the sense resistors. 3.3 O-chip Implementations 3.3.1 Power Supplies and Bias Voltage Generator The chip power supplies were generated externally using voltage regulators. The digital and analog supply lines use the LP38511-ADJ, and the long-term storage range uses the LT3082. The Op-Amp bias current generator uses an o-chip resistor to measure the bias current. The bias voltage is then adjusted using a potentiometer until the desired bias current is produced. 3.3.2 The Feedback Amplier The feedback amplier was implemented using three stages of gain and is shown in Fig. 3.18. The rst gain stage must be able to buer the input voltages with a very small amount of input-bias current so it does not com- promise the current sensing of the reference generator. Also, it must have a small input-oset voltage so as to minimize the sampling current ratio error. The LTC6078 dual precision Op-Amps were used for the rst stage. It has 1 pA input-bias current at room temperature and 25 V maximum-oset voltage per amplier. The second and third stages of gain use the LTC6363 precision dieren- tial amplier. It has 100V maximum-oset voltage and only 2.9 nV/ p Hz input-referred noise voltage. The nal stage of the feedback amplier is low-pass ltered to set the dominant pole of the feedback loop during calibration. A rst-order low- 62 Chapter 3 Figure 3.18: Schematic view of the implemented feedback amplier. pass lter was used with a pole frequency of 50 mHz. The overall transfer function of the feedback amplier can be shown to be: A amp (j!)A 0 1 1 + j! !p1 ! ; (3.1) where the DC gain is approximately 74,000 and the pole frequency is 50mHz. With such a large gain and low-frequency pole, the feedback amplier acts as a comparator. Its output voltage should be sampled fast enough so that its steady state during calibration ramps back-and-forth within the accuracy limitation of the implemented system. This is a qualitative perspective of ensuring closed-loop stability. 3.3.3 The FPGA with Built-in ADC The o-chip FPGA with built-in ADC was implemented using the Xilinx Artix-7. The Artix-7 is located on Digilent's Cmod A7, a 48-pin DIP form factor board built around the Artix-7. The Cmod A7 provides 52 digital FPGA I/O and 2 analog inputs that feed each of the two ADC's. The Cmod A7 also includes two push button inputs and is programmed using a Micro USB input. The analog front-end for each twelve-bit ADC located in the Artix-7 is included on the Cmod A7. It consists of a voltage divider (to step-down 63 Chapter 3 Figure 3.19: Cmod A7 with Artix-7 along with schematic view of analog front-end. from its 3.3 V analog input range to the Artix-7 ADC input range of 1 V) and an anti-alias lter. The voltage divider divides the input by 3.32 and the anti-alias lter has a -3 dB bandwidth of 95 kHz, well beyond the desired input frequency range. The programming of the FPGA, implemented in Verilog, can be broken down into two functions: sample and digitize the output of the feedback amplier during calibration, and produce the controls for the ASIC. The sampling and digitization consists of simultaneously sampling each input voltage using the two ADCs. Then, the 12-bit outputs of each ADC are read via the dynamic reconguration port (DRP). The two samples are then digitally subtracted with 10-bit accuracy and ready to be written to the SRAM on the next long-term storage refresh cycle. The ASIC controls produced by the FPGA consist of 38 Digital out- puts. Nine bits control the implementation block, twenty bits control the SRAM, one bit controls the DAC clock, and eight bits control the capacitive array. The number of control bits could have been reduced by thirteen by combining address bits on the ASIC. During normal operation, the FPGA refreshes the stored program values for the selected test structure at 100 Hz. Despite the worst-case simulation short-term storage time of 4 ms, the chips measured worked with storage 64 Chapter 3 times of 10 ms. With a DAC speed of 1 MSPS, this procedure takes 1 s to refresh each calibration. Thus, the DAC is capable of refreshing 10,000 calibration sites which yields a power consumption per calibration site of 7 nA. Theoretically, this could be cut down to 3.5 nA/cal if the DAC were implemented with six bits by removing the rst four-bit stage. During calibration, the ADCs sample at just under 100 kSPS and av- erage 64 samples to have an eective sampling rate of 1.5 kSPS. The DAC refreshes the stored program values at 10 kHz, leading to a maximal delay from sampling to refreshing of 100 s. Fourteen external controls are used to communicate with the FPGA. Six bits are used to select the desired test structure and eight bits are used to enable and troubleshoot calibration along with setting the DAC refresh rate. 3.3.4 O-Chip Overview The entire test board used for system implementation and measurements is shown in Fig. 3.20. The ASIC test chips connect to the DIP sockets surrounding the feedback amplier. The circuitry on the left controls the input voltages to the I/O interface and output impedance to measure the output currents with voltage probes. The input voltages can be adjusted logarithmically using potentiometers and an Op-Amp with feedback diode. This allows input currents to span four orders of magnitude. The output impedance can be adjusted across three orders of magnitude using potentiometers. In order to directly measure the output current, jumpers can be removed and an electrometer can be placed in series. 3.4 System Calibration Considerations During calibration there are two important things to consider. The rst is closed-loop stability during calibration and the second is the attainable accuracy of the implemented system. 3.4.1 Feedback Loop Stability During calibration it is important for the feedback loop to be stable in order to settle to within the systems capable accuracy. The closed-loop transfer function depends on the small-signal model of the selected test structure (H(j!)), the feedback amplier with low-pass lter and ADC front- 65 Chapter 3 Figure 3.20: ASIC test board with o-chip implementations shown. end (A(j!)), and the sampled-data system (F(j!)). The entire closed loop is shown in Fig. 3.21. The small-signal transfer function of the test structures (H(j!)) has a low-frequency gain proportionate to g mb =g m since the feedback is applied at the bulk. Single-ended feedback of the current mirrors has approximately half the feedback factor and thus overall gain as fully-dierential feedback of the vector magnitude circuit. The frequency response is dominated by the low-frequency pole caused by the large sense resistors and the parasitic capacitance of sending the sense voltages o chip. Its transfer function has a simulated worst-case low-frequency gain of approximately 22x10 3 and 40x10 3 for the current mirror and vector magnitude test structures respectively. During testing, they were measured as approximately 34x10 3 and 67x10 3 respectively. The simulated pole frequency was a few hundred hertz when a sampling current of 3 nA is used. When the ADC front-end is included with the amplier transfer function, 66 Chapter 3 Figure 3.21: Block diagram of the closed-loop transfer function during cali- bration. its low-frequency gain drops by a factor of 3.32. This leads to a low-frequency gain of approximately 22,300. The sampled-data system has an overall gain of unity since the ADC front-end and DAC output both have a range of1 V. The delay involved is due to the time between sampling and refreshing which has a worst-case value of 100 s. Its transfer function has unity gain and a phase response proportionate to its delay. The overall closed-loop transfer function, T (j!) can be expressed as: T (j!)T 0 1 1 + j! ! p1 ! 1 1 + j! ! p2 ! e j! G : (3.2) In Eq. 3.2, T 0 750 and 1,500 for the current mirror and vector magnitude test structures respectively,! p1 250 mHz,! p2 2100 Hz, and G 100 s. With the dominant pole set by the feedback amplier, the phase response of the sampled-data system has negligible impact on the closed-loop pass band and the non-dominant pole is high enough in frequency to ensure stability. 3.4.2 System Accuracy Considerations The system accuracy after calibration has a mean dependant on the accu- racy of the sampling devices within the reference generator and a standard deviation dened by the mismatch accuracy of the test structures divided by the closed-loop gain during sampling and compensation. 67 Chapter 3 The mismatch accuracy of the calibrated system, the target for this work, depends on the standard deviation in output current after reverse- biasing. For the implemented system, this improvement is theoretically about 1,500x and 750x for the current-mirror and vector magnitude circuits respectively. However, as it will be seen in Chapter 4, the limit of the accuracy improvement depends on second-order eects during calibration. For the implemented system, having the feedback loop go o-chip hindered the achievable improvement to about 85x and 42x for each test structure respectively. This means the feedback closed-loop gain was over-designed by about an order of magnitude. 68 Chapter 4 Measurement Results The test-bench setup is shown in Fig. 4.1. All current measurements were made using a Keithley 6514 electrometer. The implemented test structures have a current density that results in a weak-inversion operating current of less than 100 nA. Additionally, a diode-connected device can maintain saturation with currents above 100 pA. Therefore, devices are measured from 300 pA - 30 nA to ensure devices remain saturated and in weak inversion. Figure 4.1: Test bench setup with the Keithley 6514 electrometer and power supply. The measurement procedure is as follows. First, the I/O interface am- plication of output current was measured. The calibration test structure was selected and its output test current was adjusted from 69 Chapter 4 0.3 nA - 100 nA using potentiometers. Every 3x increase in current, the cor- responding amplied output current was measured to produce an accurate mapping of the amplication across its operating range. Next, the uncalibrated data were measured. This was done by rst se- lecting the calibration test structure to set the desired input current(s). The input voltages to the I/O interface were adjusted until each input current reached their desired value. Then, each test structure was multiplexed and its amplied output current was measured. This was repeated for each in- put data point for both current mirror and vector magnitude test structures. During these measurements, devices capable of back-body biasing had their wells biased at analog ground, or V SB = 600 mV. The devices were then calibrated. The calibration test structure was se- lected in order to set the desired sampling-current during calibration. Then, the auto-calibration cycle was enabled, storing the reverse-bias voltages for each of the twenty-four test structures used for implementation of the pro- posed method. The cycle takes under ve minutes to complete. The calibrated data were then measured in the same way that the un- calibrated data were. This process was then repeated two more times to measure the impact of power-supply variation of10 % on the calibrated test structures. Three test chips were used for measurements across the two orders of input-current magnitude. In order to reduce the number of measurements per chip, chip 1 was measured from 0.3 nA - 3 nA and calibrated at 1 nA, chip 2 was measured from 1 nA - 10 nA and calibrated at 3 nA, and chip 3 was measured from 3 nA - 30 nA and calibrated at 10 nA. 4.1 Performance Metrics Three performance metrics were measured for system improvement compar- isons. They consist of the mismatch accuracy, the overall accuracy, and the speed-power-accuracy (speed x accuracy 2 / power) trade-o. The data before calibration have overlapping data that combine for bet- ter statistical results. The data after calibration are not combined for over- lapping inputs since each chip was calibrated at dierent current levels. 4.1.1 Mismatch Accuracy The mismatch accuracy is inversely proportionate to the standard deviation in normalized output current due to an input current. It can be expressed as 70 Chapter 4 Acc MM = 1 (Iout) <Iout> : (4.1) In theory, the square of the mismatch accuracy of each test structure is at rst order proportionate to the area of the devices used for signal processing in the circuit. To show this, the expected expressions for the standard deviation in output current for the current mirror and vector magnitude before and after calibration are given in the following two sections. Current Mirror Test Structures The derivation for the standard deviation in output current starts with the large-signal output current given by I out =I w2 I in I w1 K 2 K 1 ; (4.2) where usually the approximation that K 2 K 1 is used. It is interesting to point out that if the subthreshold current density, I w , were treated as a Gaussian random variable, the standard deviation in output current in (4.2) would not be dened. This is because the distribution of the ratio of Gaussian random variables is a Cauchy distribution which has no dened expected value or variance. The work-around is to treat the partial derivative of the subthreshold current density as a Gaussian random variable which is zero-mean and has a variance described by the technology's mismatch parameters. First, the partial derivative of the output current due to each subthreshold current density is taken and normalized: I out I out I w2 I w2 I w1 I w1 : (4.3) Next, using the following set of identities: 2 P P = 2 2 P P ; 2 I DS I DS 2 I w I w ; and assuming that the mismatch in each device subthreshold current density is uncorrelated and equal, the standard deviation in the normalized output current can be given as: I out I out I DS I DS : (4.4) 71 Chapter 4 The result shows the standard deviation in output current is equal to the standard deviation in the dierence between subthreshold current densities, a seemingly obvious result which conrms the validity of the partial deriva- tive method for analyzing mismatch in circuits. For devices that are calibrated using reverse back-body biasing, the stan- dard deviation in normalized output current was shown in Chapter 2 to be reduced by approximately the feedback system's loop gain: I out I out CAL I DS I DS 1 1 +T : (4.5) Vector Magnitude Test Structures The multi-input single-output (MISO) nature of the vector magnitude test structures leads to a more complex relationship between the standard devi- ation in output current and each input. When the slope coecients of each device are approximated as equal, the output current is approximated by I out s I w5 I w6 I w1 I w2 I 2 in1 + I w5 I w7 I w3 I w4 I 2 in2 : (4.6) Using the same procedure as the current mirror test structure, the stan- dard deviation in normalized output current can be shown to be given by I out I out 1 2 I DS I DS s 3 2 ffI in1 ;I in2 g + 1 2 ; (4.7) where ffI in1 ;I in2 g = I w5 I w6 I w1 I w2 I 2 in1 2 + I w5 I w7 I w3 I w4 I 2 in2 2 I w5 I w6 I w1 I w2 I 2 in1 + I w5 I w7 I w3 I w4 I 2 in2 2 : (4.8) Despite the rather complicated appearance of (4.8), its range can be bro- ken down by input. When I in1 >> I in2 and vice versa, f (I in1 ; I in2 ) 1. When I in1 = I in2 , f (I in1 ; I in2 ) 1 2 . Therefore, it has a value in the range of 1 2 . f (I in1 ; I in2 ). 1. The result makes sense intuitively. When one input dominates, Eq. 4.8 is approximately 1 and the standard deviation in the output current is root-two times smaller that of the current mirror. This 72 Chapter 4 is because four devices are used to mirror the input current instead of two. Similarly, when each input contributes equally, Eq. 4.8 is approximately 1/2 and the standard deviation in the output current becomes just above a quarter ( q 5 16 ) that of the current mirror because seven devices are used to mirror and add the same input current. Just like the current mirror test structures, devices that are calibrated using reverse back-body biasing have their standard deviation in normalized output current reduced by approximately the feedback system's loop gain: I out I out CAL 1 2 I DS I DS 1 1 +T s 3 2 ffI in1 ;I in2 g + 1 2 : (4.9) BiCMOS8HP Mismatch Parameters The above derivations depend on pertinent matching properties of the im- plemented technology listed in Chapter 3 and reproduced in Table 4.1. Gate-Aspect Ratio [m/m] Area [m] 2 I DS I DS [ % ] (V th ) [ mV ] 0.36 / 0.24 0.0864 78 23 0.36 / 0.24 0.0864* 79 23 0.94 / 0.94 0.8836 11 3.7 3 / 3 9 3.2 1.0 10 / 10 100 0.97 0.32 Table 4.1: Pertinent mismatch parameters for thick-oxide (5.2 nm) devices. (*) Denotes devices with a reverse back-body bias of 600 mV. As discussed in Chapter 1, the standard deviation in device current is inversely proportionate to the square root of its area by the following set of identities: 2 I DS I DS g m I DS 2 2 (V th ) K V t 2 A 2 Vth WL : The previous derivations and this identity leads to the square of the mis- match accuracy of each test structure to be approximately proportionate to the area of the devices used. 73 Chapter 4 4.1.2 Overall Accuracy The overall accuracy depends on the standard deviation in the normalized output current along with the circuit gain error (CGE) and given by Acc OV = 100 <Iout> I out;I 1 3 (Iout) <Iout> [%]: (4.10) Normalizing the overall accuracy about 100% requires inverting the denom- inator for values less than 1. The CGE is dened as the ratio of the mean output current to the ideal output current: CGE = <I out > I out;I : (4.11) The CGE is dependent on the circuit topology used for implementation since it depends on circuit errors caused by device non-idealities such as nite channel conductance and the body eect. As device lengths increase for both test structures, their channel conductance diminishes leading to better (smaller) CGE for increasing areas. The CGE of the vector magnitude test structures is also impacted by the body eect since the top devices do not have their bulk tied to their source. Devices that are calibrated using reverse back-body biasing have their CGE reduced to the mean program accuracy at their calibration current. Assuming that the mean program accuracy is dominated by the matching properties of the sampling resistors in the reference generator, it can be expressed as CGE I CAL I DS I DS R ref T 1 +T : (4.12) As calibrated structures have their input current(s) stray from the calibra- tion current, their CGE increases. 4.1.3 Speed-Power-Accuracy Trade-O In order to compare the speed-power-accuracy trade-o, the capable speed of each implemented test structure given in Table 4.2 is used. For the power consumption before calibration, the overall current of the test struc- ture is multiplied by the power supply voltage. For the power consump- tion after calibration, the same method is used and then added to the 74 Chapter 4 power/calibration consumption of the DAC required for back-body biasing. The current mirror test structures have a single calibration stored while the vector magnitude test structures have two calibrations stored. For accuracy considerations, the mismatch accuracy from the measured data was used. Topology Area [m] 2 Capable f 3dB [MHz]** Measurable f 3dB [kHz]** 0.0864 13 30 0.0864* 9.7 30 Current Mirror 0.8836 3.1 24.5 9 0.58 23.4 0.0864 6.5 20 0.0864* 5.1 20 Vector Magnitude 0.8836 1.2 18.3 9 0.26 17.8 Table 4.2: Table showing capable versus measurable -3 dB bandwidth of the implemented test structures. (*) Denotes devices with a back-body bias of 600 mV. (**) Values are given for 3 nA bias current. Increasing or decreasing the bias current by 10x increases/decreases values by 10x. It should be pointed out that the spread in capable speed for the ex- tracted layout of the implemented test structures does not have the theo- retical spread it is expected to have. Each order of magnitude increase in area should decrease the speed by an order of magnitude (for square geome- tries) and simulations of the schematic view verify this trend. This should result in better trade-o values for larger devices since smaller devices are not as much faster as predicted. Better layout techniques can improve this; however, the spacing required for the triple-well process puts a fundamental limit on the speed of small devices. 4.2 Accuracy Results Three chips were measured to obtain 2421 data points. The mismatch ac- curacy and overall accuracy was calculated from the data before and after calibration. Their results are then compared with simulated and theoretical values. Figures 4.2-4.7 pertaining to these results can be found starting on page 79. 4.2.1 Current Mirror Test Structures Eight calibration test structures and twelve reference test structures were measured on each chip resulting in a total of 132 data points per chip. The 75 Chapter 4 mismatch accuracy measurement results are shown in the plot on the bottom in Fig. 4.2. They can be compared to the simulated and theoretical results shown in the plot on the top. The measurement results agree well with the theoretical and simulated results. The two larger-area reference structures have measured mismatch accuracy approximately an order of magnitude lower than predicted. This could be due to the lack of number of implemented test structures. The discrepancy in the theoretical and simulated mismatch accuracy after calibration can be explained by the fundamental limit in accuracy being set by the calibration system's non-idealities for very large loop gains. Measurement results show the mismatch accuracy of the devices being biased is improved by four orders of magnitude. The mismatch accuracy limit of the implemented system is 10 4 which relates to a standard deviation in output current of 1 %. For the BiCMOS8HP process, this would be the accuracy achieved if the current mirror were implemented by nMOS devices with an area of 100 [m] 2 , larger by a factor of approximately 1,200. The measurement results for the overall accuracy are shown on the bot- tom in Fig. 4.3 while the simulation results are shown on the top. The overall accuracy measurement results also agree well with the simulated val- ues. The larger two reference test structures have an overall accuracy about twenty percent lower than predicted. The calibrated test structures have an optimal accuracy at their calibrated input current and diminish as their dynamic range increases due to circuit error. 4.2.2 Vector Magnitude Test Structures Sixteen calibration test structures and eleven reference test structures were measured on each chip resulting in a total of 675 data points per chip. The mismatch accuracy measurement results are shown in the plot on the bottom of Fig. 4.2. The simulated and theoretical results are are shown in the plot on the top. The measurement results agree well with the theory and simulated data. Like the current-mirror test structures, the fundamental accuracy limit of 10 4 , which relates to a standard deviation in output current of 1 %, was also reached for the vector magnitude test structures. Because the vector magnitude circuit has better inherent accuracy performance than the current mirror, this accuracy relates to the circuit being implemented with devices having an area of approximately 28.8 [m] 2 , larger by a factor of about 360. The measurement results for the overall accuracy are shown on the bot- tom in Fig. 4.3 while the simulation results are shown on the top. The 76 Chapter 4 overall accuracy measurement results also agree well with the simulated val- ues. The vector magnitude plots show the degradation in accuracy due to circuit error as the input currents stray from their calibration point better than the current mirror test structure plots. 4.3 Power Supply Variation After calibration, the accuracy of the implemented system was tested for a power supply voltage varying by10%. The measured results for the current mirror test structures are shown in Fig. 4.6 and the results for the vector magnitude test structures are shown in Fig. 4.7. The power supply variation for the current mirror test structures caused a degradation of the mismatch accuracy by approximately an order of mag- nitude. However, the degraded accuracy was still better than the reference test structures with a hundred times the area. If it is necessary, the accuracy can be restored by running another calibration cycle after a certain drift in power supply voltage. The power supply variation for the vector magnitude test structures also did not have a large impact on the calibration accuracy except for when volt- age headroom became a problem. When the power supply voltage dropped by ten percent for input currents above 10 nA, the circuit headroom for sub- threshold operation was compromised. The stacked-transistor circuit topol- ogy requires at least two threshold voltages in order to support subthreshold input currents. For the implemented structures, this is approximately 1.2 V. When the supply voltage dropped to 1.1 V, the circuit no longer had the required headroom to operate for large input currents. 4.4 Speed-Power-Accuracy Trade-O The speed-power-accuracy trade-o results are listed in table 4.3. Results are shown for input currents of 3 nA. The current mirror test structures show an improvement of approximately 3,600 and the vector magnitude test structures show an improvement of approximately 820. As predicted from the capable speed simulation results, the trade-o is higher for larger devices since their speed degradation due to area is not as spread as predicted. Additionally, larger-area devices have better matching properties since they do not succumb to short-channel eects. These combined eects predict a better trade-o of about 8.5x, within the measurement results by less than a factor of two. 77 Chapter 4 Test Structure Area [m] 2 Speed-Power-Accuracy Speed-Power-Accuracy [MHz]/[nW] [MHz]/[nW] Before Calibration After Calibration (Chip 2) Current Mirror 0.0864 (13)(1:4) 2 =(7:2) = 3:5 - 0.0864* (9:7)(1:3) 2 =(7:2) = 2:3 (9:7)(110) 2 =(7:2 + 7) = 8; 300 0.8836 (3:1)(4:1) 2 =(7:2) = 7:2 - 9 (0:58)(11) 2 =(7:2) = 9:7 - Vector Magnitude 0.0864 (6:5)(2:1) 2 =(12) = 2:4 - 0.0864* (5:1)(2:6) 2 =(12) = 2:9 (5:1)(110) 2 =(12 + 14) = 2; 400 0.8836 (1:2)(17) 2 =(12) = 29 - 9 (0:26)(42) 2 =(12) = 48 - Table 4.3: Table showing the speed-power-accuracy trade-o for imple- mented test structures for input currents at 3 nA. 78 Chapter 4 Figure 4.2: The mismatch accuracy for theory versus simulated (top) and measured (bottom) current mirror test structures. () Denotes a reverse back-body bias of 600 mV. () Denotes calibrated devices using reverse back-body biasing. 79 Chapter 4 Figure 4.3: The overall accuracy for simulated (top) and measured (bottom) current mirror test structures. () Denotes a reverse back-body bias of 600mV . () Denotes calibrated devices using reverse back-body biasing. 80 Chapter 4 Figure 4.4: The mismatch accuracy for theory versus simulated (top) and measured (bottom) vector magnitude test structures. () Denotes a reverse back-body bias of 600 mV. () Denotes calibrated devices using reverse back-body biasing. 81 Chapter 4 Figure 4.5: The overall accuracy for simulated (top) and measured (bottom) vector magnitude test structures. () Denotes a reverse back-body bias of 600 mV. () Denotes calibrated devices using reverse back-body biasing. 82 Chapter 4 Figure 4.6: The measured mismatch accuracy (top) and overall accuracy (bottom) of the current mirror test structures for a power supply variation of10%. 83 Chapter 4 Figure 4.7: The measured mismatch accuracy (top) and overall accuracy (bottom) of the vector magnitude test structures for a power supply variation of10%. 84 Chapter 5 Conclusions and Future Work The implemented system shows that a dramatic improvement (85x for the current mirror test structure and 42x for the vector magnitude test struc- ture) in the accuracy of current-mode signal processing can be achieved with minimal theoretical degradation to device speed and increase in bias power from the proposed reverse-biasing method. However, the following concerns about the implemented system may arise and will now be addressed. Long-Term Storage Area Consumption A majority of the space used for the ASIC comes from the long-term stor- age system that was implemented. This is due to the are consumption of the metal-insulator-metal-capacitors (mim-capacitors) used in the charge- redistribution DAC's large common-centroid capacitor arrays and the ca- pacitor array holding the reverse-bias voltage. If each capacitor could be implemented using lower-metal layers to make the design more compact, space could be saved. However, the implemented system can refresh around 10,000 calibration locations, meaning a very large system can be compen- sated with the implemented long-term storage. In this sort of system, most of the space would be used by the area of the storage capacitors, and if they were made compact, the long-term storage area may become negligible in comparison to such a large system. Alternatively, instead of a single, relatively fast DAC refreshing many storage capacitors, it is proposed that many, slow, monotonically-increasing, ultra-low power, current-steering DACs each holding the stored bias voltage could be implemented without the need for the large-area mim-capacitors. 85 Chapter 5 This type of storage would be desired for smaller-scale systems of implemen- tation. Additionally, the area required to implement the DAC depends on the desired accuracy of the system. For example, a 6-bit DAC could have been implemented to achieve similar accuracy results, removing the entire rst- stage of the implemented 10-bit DAC and saving space along with reducing the power consumption by a factor of 2. Every Device Does Not Need to be Calibrated In the presentation of the proposed system, it may be assumed that each and every device needs to be compensated for mismatch accuracy in order to improve the system accuracy; however, this is not the case. Instead, only a few key pairs of devices need to be reverse-biased for compensation of the overall circuit. For example, a dierential OTA can have its output oset current compensated by calibrating two pairs of devices. For comparison, the cochlear implant in [26] uses 22 bits of long-term storage per channel to compensate for system performance. Additionally, these bits are split up into 7 bits, 7 bits, 3 bits, 3 bits, and 2 bits so that where more accuracy is needed, more bits are used. Voltage-Mode Compensation It was mentioned that the proposed method of reverse back-body biasing need not be implemented just for current-mode circuits. Instead of measur- ing device currents during sampling, output voltages can be sampled and feedback can be applied to the bulk in order to compensate for voltage- mode circuits. The only drawback is the need of a level-shifter in order to reverse-bias the bulks. Body Eect Impact on Devices With Source Degeneration Devices that do not have their source tied to the power supply may ex- perience a drift in their source voltage during operation. This eectively changes the compensated threshold voltage and thus surface potential of the reverse-biased device. The result is a reduction in dynamic range the device can achieve utilizing the proposed system. One solution is to tie the device source to its bulk (if allowed) and apply compensation to the source degenerative device instead. For example, the top transistors in the vector magnitude have their sources tied to their bulk, 86 Chapter 5 and during calibration the voltage-mode devices with their sources at the power supply are compensated. Some circuit topologies, such as dierential pairs, cannot apply the above solution. Instead, it is recommended that the common-mode voltage of their dierential-bulk bias be a function of their source voltage so that they maintain matching for a wide-bias range. Temperature Variation Impact on Proposed Method Unfortunately, the implemented test bench was not capable of measure- ments for varying temperature eects after reverse-biasing. For biomedical implants, this should not cause concern since the temperature variation of the circuit environment is very small. However, for applications that have a wide range in environmental temperature, a temperature sensor can be added and checked periodically. If it shows a large enough drift when checked, an auto-calibration cycle can be initiated. 87 References [1] S. Gibson, J. Judy, and D. Markovic, \Spike Sorting," IEEE SIGNAL PROCESSING MAGAZINE [124] JANUARY 2012. [2] A. Bonfanti, T. Borghi, R. Gusmeroli, G. Zambra, A. Oliyink, L. Fadiga, A.S. Spinelli, and G. Baranauskas, \A Low-Power Integrated Circuit for Analog Spike Detection and Sorting in Neural Prosthesis Systems," IEEE Biomedical Circuits and Systems Conference, p. 257- 260, November 2008. [3] R. Sarpeshkar, \Analog Versus Digital: Extrapolating from Electronics to Neurobiology," MIT Press Journal of Neural Computations, vol. 10, no. 7, p. 1601-1638, October 1998. [4] Sarpeshkar, Rahul. Ultra Low Power Bioelectronics. Cambridge Uni- versity Press; 1 edition (February 22, 2010). [5] Tsividis, Yannis, & McAndrew, Colin. Operation and Modeling of the MOS Transistor. Oxford University Press; 3 edition (September 24, 2010). [6] Mead, Carver. Analog VLSI and Neural Systems. Addison-Wesley; 1st edition (January 1, 1989). [7] Razavi, Behzad. Design of Analog CMOS Integrated Circuits. McGraw- Hill Education; 2 edition (January 20, 2016). [8] Jose Bastos, \CHARACTERIZATION OF MOS TRANSISTOR MIS- MATCH FOR ANALOG DESIGN" PhD diss., KATHOLIEKE UNI- VERSITEIT LEUVEN, May 1998. [9] Aleksandra Pavasovic, \Subthreshold region MOSFET mismatch anal- ysis and modeling for analog VLSI systems" PhD diss., The Johns Hopkins University, 1991. 88 [10] M. Chen, and J Ho, \A Three-Parameters-Only MOSFET Subthresh- old Current CAD Model Considering Back-Gate Bias and Process Vari- ation," IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 4, APRIL 1997. [11] M. Chen, J Ho, and T. Huang, \Dependence of Current Match on Back-Gate Bias in Weakly Inverted MOS Transistors and Its Model- ing," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 31, NO 2, FEBRUARY 1996. [12] P. Drennan, and C. McAndrew, \Understanding MOSFET Mismatch for Analog Design," EEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003. [13] M. Pelgrom, A. Duinmaijer, and A. Welbers, \Matching Properties of MOS Transistors," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, NO. 5, OCTOBER 1989. [14] F. Forti, and M. Wright, \Measurement of MOS Current Mismatch in the Weak Inversion Region," IEEE JOURNAL. OF SOLID-STATE CIRCUITS, VOL. 29, NO. 2, FEBRUARY 1994. [15] P. Kinget, and M. Steyaert, \Impact of transistor mismatch on the speed-accuracy-power trade-o of analog CMOS circuits," IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE. [16] K. Uyttenhove, and M. Steyaert, \Speed{Power{Accuracy Tradeo in High-Speed CMOS ADCs," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS|II: ANALOG AND DIGITAL SIGNAL PROCESS- ING, VOL. 49, NO. 4, APRIL 2002. [17] P. Kinget, \Device Mismatch and Tradeos in the Design of Analog Circuits," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005. [18] C. Enz, and G. Temes, \Circuit Techniques for Reducing the Eects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization," PROCEEDINGS OF THE IEEE, VOL 84, NO 11, NOVEMBER I996. [19] A. Bagheri, M. Salam, J. Velazquez, and R. Genov, \Low-Frequency Noise and Oset Rejection in DC-Coupled Neural Ampliers: A Review 89 and Digitally-Assisted Design Tutorial," IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 11, NO. 1, FEBRU- ARY 2017. [20] V. Gupta, and G. Rincon-Mora, \Achieving Less Than 2% 3- Mismatch With Minimum Channel-Length CMOS Devices," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS|II: EXPRESS BRIEFS, VOL. 54, NO. 3, MARCH 2007. [21] V. Srinivasan, G. Serrano, J. Gray, and P. Hasler, \A Precision CMOS Amplier Using Floating-Gates For Oset Cancellation," IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE. [22] V. Mangal, and P. Kinget, \28.1 A 0.42nW 434MHz -79.1dBm Wake- Up Receiver with a Time-Domain Integrator," 2019 IEEE International Solid-State Circuits Conference. [23] W. Wattanapanitch, M. Fee, and R. Sarpeshkar, \An Energy-Ecient Micropower Neural Recording Amplier," IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 1, NO. 2, JUNE 2007. [24] Gregorian, Roubik. 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Abstract (if available)

Abstract Applications in the biomedical industry, Internet of Things, and other technologies have spawned the need for ultra-low-power systems. Reduction of power consumption in analog circuits can be realized by reductions in their supply voltages and operating currents. Unfortunately, the latter makes reliable circuit behavior difficult to achieve. Numerous factors inherent to IC fabrication lead to unpredictable threshold voltages, which makes biasing a difficult task at low power levels. The only resolutions that avoid a severe reduction in speed are post-fabrication compensation techniques. ❧ This work investigates the use of reverse back-body biasing in order to compensate for threshold voltage variation. The system regulates device currents through feedback by measuring the current offsets caused by device uncertainties and applying appropriate reverse-bias voltages at body terminals. ❧ An auto-calibration system on chip (SoC) interfacing with a field-programmable gate array (FPGA) was built and tested to show proof of concept. Two current-mode test circuits were used for demonstrating the ability of the system. Results show that the implemented system is able to achieve 3 nA bias currents in 0.24 µm channel-length devices with a normalized standard deviation of 1%, which was the limit imposed due to second-order effects. Similar accuracy would be achieved by using devices with 1,200x area. Additionally, the system does not exhibit a drastic reduction in accuracy for power supply variation so long as voltage headroom is not compromised.

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Asset Metadata

Creator Curry, Aaron (author)

Core Title Improving the speed-power-accuracy trade-off in low-power analog circuits by reverse back-body biasing

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 08/06/2019

Defense Date 04/26/2019

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag back gate biasing,bulk biasing,CMOS mismatch,current mode circuits,device mismatch,integrated circuit mismatch,low power analog circuits,low power circuit accuracy,mismatch,OAI-PMH Harvest,reverse back body biasing,subthreshold circuits,well biasing

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Maby, Edward W. (committee chair), Berger, Ted William (committee member), Chen, Shuo-Wei (committee member), Gupta, Sandeep (committee member)

Creator Email acurry@usc.edu,acurry111@gmail.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c89-208041

Unique identifier UC11663041

Identifier etd-CurryAaron-7725.pdf (filename),usctheses-c89-208041 (legacy record id)

Legacy Identifier etd-CurryAaron-7725.pdf

Dmrecord 208041

Document Type Dissertation

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Rights Curry, Aaron

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA