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Silicon-based RF/mm-wave power amplifiers and transmitters for future energy efficient communication systems
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Silicon-based RF/mm-wave power amplifiers and transmitters for future energy efficient communication systems
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Content
SILICON-BASED RF/MM-WAVE POWER AMPLIFIERS AND
TRANSMITTERS FOR FUTURE ENERGY EFFICIENT
COMMUNICATION SYSTEMS
by
Aoyang Zhang
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulllment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2020
Copyright 2021 Aoyang Zhang
Dedication
To my dear mother and father
ii
Acknowledgements
This work could not have been done without the following supports.
First of all, I would like to express my gratitude from the bottom of my heart to
my academia father, advisor, friend, Prof. Mike Shuo-Wei Chen. I still remember
the rst time we met six years ago, I worried that if I could establish my research
without any tape-out experience. Prof. Chen then shared with me his research
philosophy, "The most important thing is not your starting point, but whether you
are willing to learn and keep improving yourself." I guess even Prof. Chen did
not thought how large impact this talk had to me, and this is how everything get
started! When we started our SHS PA project, we learnt together, built everything
from scratch and nally were able to build the prototypes and contribute to our
circuit society. I always enjoyed our discussions and chatting.I also very appreciate
that Prof. Chen is always willing to help me when I have any diculties. It is a
great honor to be one of "MC" group members! I wish that I can also make you
feel proud(Except those last-minute pressure that I put on you)!
I would like to extend special thanks to Prof. Hossein Hashemi for his always
help, advice and guidance. I took two integrated circuit courses from Prof. Hashemi
iii
and enjoyed his teaching! I appreciate Prof. Hashemi attended my design review
couple times and provided me valuable feedback. He has played a role equivalent
to that of a co-advisor.
I would like to acknowledge Prof. Lenian He from Zhejiang University and
Prof. Ali Niknejad and Dr. Jiashu Chen from UC Berkeley. Prof. He rstly
introduced me to the integrated circuit design world when I was an undergraduate,
and encourage me to continue pursuing my dreams. Prof. Niknejad and Dr. Jiashu
Chen oered me an summer intern opportunity to work at BWRC, and helped
me during my applications. It is a great experience to start the research of power
ampliers when I was there.
I would like to extend my sincere thanks to the members of my qualifying and
defense committees, including Prof. Hossein Hashemi, Prof. Mahta Moghaddam,
Prof. Andreas Molisch, Prof. Jayakanth Ravichandran and Prof. Constantine
Sideris. They shared their opinions sel
essly during all discussions. The most
important thing I learned from them is how to think about and deal with problems
outside of the box and how to explain the research and convey the ideas with other
experts in a dierent eld.
I am grateful to my seniors in Prof. Chen's research group, including Cheng-Ru
Ho, Jaewon Nam, Shiyu Su, and Tzu-Fan Wu, as they always helped me when I
face any problems and diculties. Special thanks to Cheng-Ru, Shiyu and Tzu-
Fan who always treat me like their younger brother. Cheng-Ru, my roommate,
iv
always support me when I have some problems. Shiyu, always encouraged me
to look forward when I am down, and discuss the research problems no matter
how busy he is. Tzu-Fan, always helped me when I have any technical issues and
share with me his tricks. I also appreciate all the help and technical support from
my other labmates, including Mohsen Hassanpourghadi, Pedram Teimouri, Sourya
Dey, Naveen Katem, Zisong Wang, Haolin Cong, Rezwan Rasul, Ce Yang, Qiaochu
Zhang, Mostafa Ayesh, Soumya Mahapatra and Juzheng Liu. It is worth to mention
our MIDAS team which includes Ce, Mostafa and Soumya. It is my pleasure to
work with you guys!
I wish to thank Dr. Run Chen, Dr. SungWon Chung, Dr. Kunal Datta, Dr.
Sushil Subramanian, Dr. Alireza Imani, Dr. Pingyue Song, Masashi Yamagata,
Samer Ideris, Vinay Chenna from Dr. Hashemi's research group as well, as I ben-
eted not only from the technical support but also the valuable experience they
shared.
Without funding support, none of my Ph.D. work would have been accom-
plished.I would like to acknowledge DARPA, NSF and ONR for their funding sup-
port.
Last but not least, without my family's support, I would not have been able
to proceed this far. Even though I am the only child in my family, my parents
still let me go abroad to fulll my dreams. I am deeply indebted to my parents
for their wholehearted love. My grandma, who did not go to school for even one
v
day, but always support her grandson to pursue the PhD degree. She sadly passed
away when I was taping out my rst chip, I wish I could make you feel proud!
Of course, I am indebted to my girlfriend, Sue, who is also a PhD student with
many works from her research but always support me with unconditional love and
company through many dicult times (especially now when COVID-19 is gripping
the world). I love you.
ii
Table of Contents
Dedication ii
Acknowledgements iii
List Of Tables vi
List Of Figures vii
Abstract xi
Chapter 1: Introduction 1
1.1 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Overview of Conventional Eciency Enhancement Techniques for
CMOS PAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Research Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2: A Subharmonic Switching Digital Power Amplier 5
2.1 SHS PA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Concept of SHS PA . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 SHS PA Eciency Enhancement . . . . . . . . . . . . . . . 11
2.1.3 SHS SCPA with Hybrid Class-G Operation . . . . . . . . . . 21
2.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.1 Digital SHS PA Architecture . . . . . . . . . . . . . . . . . . 23
2.2.2 Stacking Class-D PA Driver . . . . . . . . . . . . . . . . . . 25
2.2.3 Subharmonic PM Generation . . . . . . . . . . . . . . . . . 28
2.2.4 Matching Network . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.1 Continuous-Wave(CW) Measurement . . . . . . . . . . . . . 31
2.3.2 Modulated Signal Measurement . . . . . . . . . . . . . . . . 35
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
iii
Chapter 3: A Watt-Level Phase Interleaved Multi-Subharmonic Switch-
ing Digital Power Amplier 38
3.1 Multi-SHS PA Architecture . . . . . . . . . . . . . . . . . . . . . . 38
3.1.1 Multi-SHS PA Operation . . . . . . . . . . . . . . . . . . . . 39
3.1.2 Multi-SHS PA Eciency Enhancement . . . . . . . . . . . . 42
3.1.3 Phase-Interleaved Subharmonic Inherent
Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.1.4 Multi-SHS with Hybrid Class-G Operation . . . . . . . . . . 55
3.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.1 Multi-SHS Digital PA Architecture . . . . . . . . . . . . . . 57
3.2.2 Three-Way Power Combiner . . . . . . . . . . . . . . . . . . 59
3.2.3 Multi-Subharmonic PM Generation . . . . . . . . . . . . . . 62
3.3 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.1 Continuous-Wave (CW) Measurement . . . . . . . . . . . . 66
3.3.2 Phase-Interleaved Subharmonic Cancellation . . . . . . . . . 71
3.3.3 Modulated Signal Measurement . . . . . . . . . . . . . . . . 72
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Chapter 4: A Current Mode Subharmonic Switching Digital Power
Amplier 76
4.1 Eciency Enhancement of Current Mode
SHS PA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1.1 Eciency Enhancement Mechanism I:
Conduction Loss Saving . . . . . . . . . . . . . . . . . . . . 76
4.1.2 Eciency Enhancement Mechanisms II:
Improved Impedance Matching . . . . . . . . . . . . . . . . 78
4.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.2.1 Current Mode SHS PA Architecture . . . . . . . . . . . . . . 80
4.2.2 Coupled Inductor Based Subharmonic Trap . . . . . . . . . 82
4.3 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.1 Continuous-Wave (CW) Measurement . . . . . . . . . . . . 83
4.3.2 Modulated Signal Measurement . . . . . . . . . . . . . . . . 85
Chapter 5: A Mm-Wave Subharmonic Switching Class E/F
2;2=3
Power
Amplier with Harmonic and Subharmonic Tuning 87
5.1 SHS Class E/F
2;2=3
PA Architecture . . . . . . . . . . . . . . . . . . 87
5.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.2.1 Harmonic and Subharmonic Matching Network . . . . . . . 92
5.3 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.1 Continuous-Wave (CW) Measurement . . . . . . . . . . . . 94
5.3.2 Modulated Signal Measurement . . . . . . . . . . . . . . . . 96
iv
Chapter 6: Conclusions 98
6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
References 101
v
List Of Tables
2.1 Simplied PBO operation table . . . . . . . . . . . . . . . . . . . . 22
2.2 Comparison with other PBO eciency-enhanced CMOS digital PAs 37
3.1 An example of multi-SHS digital PA operation table . . . . . . . . 45
3.2 Performance comparison with other CMOS PAs . . . . . . . . . . . 75
4.1 The comparison with prior-art PAs with similar operating frequen-
cies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.1 The comparison with state-of-the-art CMOS and SiGe PAs . . . . 97
vi
List Of Figures
2.1 Conventional Class-D PA Operation in Peak Power Mode . . . . . 6
2.2 Conventional Class-D PA Operation in Power Back-O Mode . . . 7
2.3 Subharmonic switching class-D PA in power back-o mode . . . . . 9
2.4 Single PA architecture . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Digital PA architecture . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 (a) Conventional switched capacitor PA (SCPA) in PBO mode; (b)
SHS SCPA in PBO mode . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 SHS SCPA in dierent power regions . . . . . . . . . . . . . . . . . 18
2.8 SHS SCPA with hybrid class-G operation . . . . . . . . . . . . . . . 20
2.9 Block diagram of the proposed PA implementation . . . . . . . . . 24
2.10 Proposed PA unit cell . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11 Power and eciency contours . . . . . . . . . . . . . . . . . . . . . 27
2.12 PM generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.13 Single-ended on-board matching network . . . . . . . . . . . . . . . 30
2.14 Chip micrograph and testing board . . . . . . . . . . . . . . . . . . 31
2.15 Measured peak power and eciency versus frequency . . . . . . . . 32
vii
2.16 Measured PA output spectrum at -13dB PBO without any addi-
tional ltering. A 10-dB attenuator is used at the PA output in the
measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.17 Measured PA drain eciency (DE) at 2.25GHz versus PA output
power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.18 Measured AM-AM and AM-PM distortion . . . . . . . . . . . . . . 34
2.19 Measured EVM for real-time and hybrid class-G operation . . . . . 35
2.20 Measured spectrum for real-time SHS and hybrid class-G operation 36
3.1 Subharmonic switching digital PA operation . . . . . . . . . . . . . 39
3.2 Switching waveforms of the proposed multi-subharmonic operation . 41
3.3 Multi-SHS digital PA at dierent output power levels . . . . . . . . 42
3.4 Ideal eciency of multi-SHS PA architecture vs. Pout and for single-
SHS PA and conventional SCPA . . . . . . . . . . . . . . . . . . . . 46
3.5 Equivalent circuit model of ideal three-way phase interleaved multi-
SHS PA with dierent input switching waveforms . . . . . . . . . . 47
3.6 Complete phase-interleaved multi-SHS digital PA with hybrid class-
G operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.7 Block diagram of the PA prototype . . . . . . . . . . . . . . . . . . 57
3.8 Single-ended PA Matching Network . . . . . . . . . . . . . . . . . . 59
3.9 Simulated PA load impedance ZL versus frequency . . . . . . . . . 60
3.10 Three-way power combiner model in HFSS . . . . . . . . . . . . . . 61
3.11 Simulated S21 of the power combiner over the frequencies . . . . . . 61
3.12 Multi-SHS phase generator . . . . . . . . . . . . . . . . . . . . . . . 63
3.13 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
viii
3.14 Measured PA output power and eciency over the frequencies . . . 65
3.15 Measured PA drain eciency (DE) at 1.9GHz versus PA Pout . . . 66
3.16 Measured PA drain eciency (DE) at 2.2GHz versus PA Pout . . . 67
3.17 Measured AM-AM charateristic curve at 1.9 GHz . . . . . . . . . . 68
3.18 Measured AM-PM charateristic curve at 1.9 GHz . . . . . . . . . . 69
3.19 Measured PA output spectrum at -13 dB PBO for in-phase and phase
interleaved subharmonic operation with all the PA cells toggle at Fc/3 70
3.20 Measured PA output spectrum at -7 dB PBO for in-phase and phase
interleaved subharmonic operation with all the PA cells toggle at 2Fc/3 72
3.21 Measured EVM for real-time multi-SHS and hybrid class-G operation 73
3.22 Measured spectrum for real-time multi-SHS and hybrid class-G op-
eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.1 Eciency enhancement mechanism I: Conduction loss saving of the
proposed current-mode SHS PA architecture in the PBO region . . 77
4.2 Eciency enhancement mechanisms II:Improved impedance match-
ing of the proposed current mode SHS PA architecture in the PBO
region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3 Proposed coupled-inductor-based subharmonic trap and its equiva-
lent circuit model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4 Simplied block diagram of the proposed current-mode SHS PA pro-
totype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Die micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.6 The measurement results of the CW and modulation test signal . . 85
5.1 Concept of subharmonic switching Class E/F
2;2=3
PA with fractional
harmonic tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ix
5.2 Simplied block diagram of the proposed SHS Class E/F
2;2=3
digital
PA prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3 Proposed concurrent fractional harmonic tuning Class E/F
2;2=3
match-
ing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.4 Chip Micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.5 The measurement results of CW test signal and S-parameters . . . 95
5.6 Modulation measurement results with 64 QAM 0.5GS/s and 1GS/s
OFDM Signal at 25.5GHz . . . . . . . . . . . . . . . . . . . . . . . 96
x
Abstract
This thesis presents a new PA family, subharmonic switching (SHS) digital
power ampliers (PA), for enhancing power back-o (PBO) eciency. The family
of subharmonic switching power ampliers has been developed to enhance the e-
ciency from RF to mm-wave frequencies in bulk CMOS. Four dierent architectures
are proposed and demonstrated: rst, a subharmonic switching digital power am-
plier with hybrid class-G operation, the world's rst SHS digital PA architecture,
second, a watt-level multi-SHS digital power amplier, enabling multi-SHS opera-
tion, achiving watt level output power with bulk CMOS technology while cancelling
the unwanted subharmonic tones, third, a current mode SHS digital power ampli-
er architecture to extend the SHS PA architecture with dierent PA classes, and
forth, a millimeter-wave (mm-wave) class E/F SHS PA with harmonic and subhar-
monic tuning to extend the frequency range to mm-wave bands and maintain high
eciency for future communications.
xi
Chapter 1
Introduction
1.1 Thesis Organization
This thesis is organized as follows:
In Chapter 1, we rst discuss the background of highly ecient modern wireless
communications and existing solutions.
In Chapter 2, a new eciency enhancement technique, subharmonic switching
PA is discussed. Details of PA operation and implementation have been shown and
discussed. Finally, the measurement results showed a large amount of eciency
improvement at power back-o region.
In Chapter 3, a multi SHS PA architecture is discussed. Similar to the SHS
PA architecture, the eciency got improved by a great number of eciency peaks
thanks to the multi-SHS scheme. A phase interleaved architecture is also discussed
to show the eectiveness of subharmonic component cancellation. The implemen-
tation details and measurements results are presented.
1
In Chapter 4, a current mode SHS PA architecture are discussed. Unlike the
voltage mode SHS PA, the current mode SHS PA provides a new solution of ef-
ciency enhancement for high frequency applications. The proposed subharmonic
trap along with the magenetic eld are discussed. The corresponding measurement
results are presented.
In Chapter 5, a class E/F SHS PA architecture with both harmonic and subhar-
monic tuning is proposed for mm-wave applications, the 2nd harmonic of subhar-
monic is used to tune the PA waveform at PBO region. The circuit implementation
and measurement results are presented.
In Chapter 6, the results of this dissertation are summarized and the future
research directions are discussed.
1.2 Background
With the trend of increasing data throughput, modern wireless communication
systems prefer high spectral eciency modulations, often leading to high peak-
to-average-power ratios (PAPRs) for transmitted signals [1]{ [3]. To amplify the
large PAPR signals, power ampliers (PAs) thus need to operate in the power
back-o (PBO) region most of the time. Conventionally, PAs yield the highest
eciency at peak power, although eciency dramatically degrades as the PA output
power is scaled back. Addressing PA PBO eciency is critical for achieving a high
average power eciency. Because the PA is the most power-hungry block in RF
2
transceivers, high average power eciency will lead to longer battery life for wireless
communication systems [4]{ [7].
1.3 Overview of Conventional Eciency Enhancement
Techniques for CMOS PAs
To improve the average eciency of the PA or transmitter, there exist well-
known architectures or techniques. One useful architecture is the envelope-tracking
PA [8], [9], where the envelope detector takes the envelope of the modulated sig-
nal and controls the supply modulator while the supply modulator simultaneously
changes the PA supply. An envelope-tracking PA can achieve very high eciency
within the deep PBO region, although supply modulators with large bandwidths
and dynamic ranges remain a design challenge. Another approach is the Doherty
PA [10]{ [12], which can provide additional eciency peaks in the PBO region.
This type of PA has wide bandwidth but requires a large area for the power com-
biner to be implemented. Outphasing-based PA is another popular architecture for
enhancing PBO eciency [13]{ [16]. This has a larger bandwidth than is the case
with polar architecture, but to achieve good linearity, the mismatch of the two PAs
must be dealt with. Another technique is called load modulation [52], [18]. Theo-
retically, the technique can always provide maximum eciency at dierent output
3
power levels by tuning the matching network, but creating a wideband tunable
matching network remains very challenging.
1.4 Research Contributions
A family of Subharmonic switching power ampliers [19] have been proposed
to enhance power back-o (PBO) eciency. The SHS technique can be combined
with other eciency-enhancement techniques (such as class-G operation, Doherty
and load modulation) to further improve deep PBO eciency. The PA prototypes
achieved superior PBO eciency compared to state-of-the-art CMOS PAs.
4
Chapter 2
A Subharmonic Switching Digital Power
Amplier
2.1 SHS PA Architecture
The proposed SHS PA architecture is an alternative way to maintain high power
eciency in the PBO region [19]. We rst note that the harmonics of the switching
waveform have decreasing power magnitudes. As a result, if we toggle the switching
PA at the subharmonic component of the carrier frequency, we can lower the output
power while reducing the toggling frequency. We then use this unique property to
reduce the PA power loss (and hence higher power eciency) in the PBO. We refer
to this method as subharmonic switching (SHS) because the digital PA switches at
a certain subharmonic frequency, depending on PBO depth.
In terms of implementation complexity for SHS, the technique mainly requires
a frequency divider and a multiplexer to select the intended toggling frequency at
5
Figure 2.1: Conventional Class-D PA Operation in Peak Power Mode
the input of the digital PA as well as adding a notch in the matching network. The
added area and power overhead are relatively small within the entire PA system,
as is the case in our proof-of-concept silicon prototype. The added circuitry also
has the advantage of not preventing wideband operation for the PA core. Note
that, since the notch frequency of the matching network is xed via surface-mount
devices in this prototype, the maximal bandwidth for achieving high PBO eciency
is determined by the bandwidth of the notch provided by the matching network.
Finally, we demonstrate in the prototype that SHS can be combined with other
PBO techniques, such as class-G operation.
6
Figure 2.2: Conventional Class-D PA Operation in Power Back-O Mode
2.1.1 Concept of SHS PA
To introduce the SHS concept, we use a single-bit class-D switching PA as an
example and examine its peak power mode and PBO mode, as shown in Fig. 2.1
and Fig. 2.1. The NMOS and PMOS transistors are used as switching devices,
where the transistors operate in the triode region during the \on" state. The
PA output is toggled between V
DD
and V
GND
controlled by the input square wave.
Conventionally, the input switching frequency of a class-D PA is equal to the carrier
frequency. If the loaded quality factor (Q
L
) of the following matching network is
suciently high, then the voltage across the R
L
will be the fundamental frequency
7
of the input waveform, which surrounds the transmitter carrier frequency. In this
case, the output voltage amplitude is:
V
out
= (
2
)V
DD
(2.1)
In the peak power mode (Fig.2.1(a)), the maximum output power is:
P
out
=
2
2
V
2
DD
R
L
(2.2)
In conventional operation, when the single PA cell works in the PBO mode, as
shown in Fig.2.1(b), the output power can be reduced by changing the duty cycle.
The output voltage amplitude is determined by the duty cycle (d):
V
out
=
2
sin(d)V
DD
(2.3)
The output power then becomes:
P
out
=
2
2
V
2
DD
R
L
sin
2
(d) (2.4)
An examination of the switching waveform of the PA shows that it contains dierent
harmonics with deterministic amplitude. The higher the harmonics index, the lower
the signal energy. As a result, when the PA works in the PBO region, we can simply
use the subharmonic of the carrier frequency as the PA switching frequency and
rely on the harmonic component to carry the signal information. As an example
8
Figure 2.3: Subharmonic switching class-D PA in power back-o mode
(shown in Fig. 3), the input waveform is toggled at the third subharmonic of the
carrier frequency (i.e., fc/3), or fc, while the matching network still selects the fc
component. The output voltage amplitude at the carrier frequency is then:
V
out
=
1
3
2
V
DD
(2.5)
The output power at the carrier frequency is:
P
out
=
1
9
2
2
V
2
DD
R
L
(2.6)
The output PBO is -9.5 dB relative to the peak mode, i.e., when comparing
(2.2) and (2.6). In addition, we can utilize dierent subharmonics of the carrier
9
frequency to achieve dierent PBO levels. For the M-th subharmonic, the output
power at the carrier frequency is:
P
out
=
1
M
2
2
2
V
2
DD
R
L
(2.7)
In other words, the PA can achieve dierent PBO levels by toggling at dierent
switching frequencies. This SHS PA architecture potentially allows the selection
of dierent PA switching frequencies based on the required PBO. Section II. B
presents various eciency-enhancement mechanisms for SHS, all of which benet
from lower toggling speeds.
While the example used so far is single-bit switching PA, the proposed SHS
can be easily extended for digital PA architecture (i.e., using multi-bit input).
Essentially, this technique gives the PA system one more degree of freedom to
select both the amplitude control word (ACW) and the switching frequency control
word (SFCW) to achieve PBO. A conventional digital PA only relies on ACW,
and the output power in the PBO region is the maximum output power scaled by
(n/N)
2
, where n out of the total N number of PA unit cells are turned on. With
the assistance of SFCW, we can keep more PA unit cells turned on but toggled at
lower speed for the same output power, which helps improve PA back-o eciency.
Note that the SHS operation generates additional frequency components, which
might violate the requirement of the out-of-band spectral mask specications. To
suppress the subharmonic tone and other unwanted frequency components, a notch
10
Figure 2.4: Single PA architecture
lter response is included in the matching network with adds relatively little design
overhead. Section IV. D will present the matching network design for the SHS PA
prototype.
2.1.2 SHS PA Eciency Enhancement
Dierent mechanisms are analyzed for eciency enhancement in SHS PA ar-
chitectures. First, SHS technique can mitigate dynamic loss of the driver in the
PBO region for single-bit PA architecture. Second, the SHS operation helps with
11
PBO impedance matching and conduction loss of driver in digital PA architec-
ture. The output impedance dierence in peak power mode and PBO mode is
reduced, thus providing better impedance matching in the PBO region. Finally,
since we chose switched-capacitor PA (SCPA) implementation as the test vehi-
cle [20], [21], [13], [22]{ [26], SHS further helps reduce the energy loss in the
switched-capacitor bank. We will elaborate on these mechanisms in the follow-
ing subsections.
• Class-D PA Driver Loss
The Operation of Class-D PA is shown in Fig. 4. Assuming the matching
network is lossless and only selects the carrier frequency, we rst examine the
eciency of a single-bit class-D PA due to driver loss with and without SHS. The
root mean square (RMS) output current value of each transistor when the PA is in
peak power mode can be expressed as:
I
rms
=
s
1
2
Z
0
(I
m
sin!t)
2
d(!t) =
I
m
2
(2.8)
where Im is peak-to-peak amplitude of the output current waveform. The con-
duction power loss in each transistor is:
P
R
ON
=R
ON
I
rms
2
=
R
ON
I
m
2
4
(2.9)
where Ron is the turn-on resistance of the PA.
12
Another loss mechanism associated with the driver is the dynamic loss due to the
driver's output parasitic capacitance. Assuming the PA switching frequency is f and
the associated parasitic capacitance at the driver output is Csw for each pull-up and
pull-down devices, the total dynamic power loss dissipated in charging/discharging
the parasitic capacitance is:
P
SW
=fC
SW
V
DD
2
=
2
4
fC
SW
R
L
2
I
m
2
(2.10)
The input parasitic capacitance of the PA driver mostly aects the power loss
from the pre-driver, assuming the total parasitic capacitance in pre-driver is Cpre.
the power loss in pre-driver is:
P
pre
=fC
pre
V
DD
2
=
2
4
fC
pre
R
L
2
I
m
2
(2.11)
Hence, the overall eciency at peak power mode is:
D
=
P
o
P
o
+ 2P
R
ON
+ 2P
SW
+P
pre
=
R
L
R
L
+R
ON
+
2
2
fC
SW
R
L
2
+
2
4
fC
pre
R
L
2
(2.12)
When the PA works in the power back-o region (i.e., the output voltage is
M times smaller than the peak output voltage), the output power and conduction
power loss of the transistors are scaled down by a factor of M
2
. The dynamic
13
power loss is not scaled down, however, because only the duty cycle of the switching
waveform changes. The overall eciency in PBO mode is:
D
=
R
L
M
2
R
L
M
2
+
R
ON
M
2
+
2
2
fC
SW
R
L
2
+
2
4
fC
pre
R
L
2
(2.13)
Next, we derive the driver loss of SHS PA in the PBO region. In order to scale
down the output power by M times, the SHS technique is used to lower the switching
frequency of the PA driver by a factor of M (M equals 3 in our implementation).
The conduction power loss is thus scaled down by a factor ofM
2
, while the dynamic
power loss is M times lower due to the reduced hard switching speed. Hence, the
SHS PA eciency due to driver non-idealities is:
D
=
R
L
M
2
R
L
M
2
+
R
ON
M
2
+
2
2
f
M
C
SW
R
L
2
+
2
4
f
M
C
pre
R
L
2
(2.14)
Comparing (2.13) and (2.14), the single-bit SHS PA eciency is shown to have
improved, mainly due to the lower dynamic power loss of the driver. Note that,
in this single-bit scenario, there are some works [14], [24] that also reduce the
switching speed to mitigate dynamic loss of the single-bit driver, leading to eciency
improvement for single-bit driver operation. In the case of multi-bit digital PA,
Assuming the digital PA has N number of PA unit branches. We can follow similar
derivations as in the single-bit case. The overall eciency at peak power mode is:
14
Figure 2.5: Digital PA architecture
D
=
R
L
R
L
+R
ON
+
2
2
fC
SW
R
L
2
+
2
4
fC
pre
R
L
2
(2.15)
When the PA works in the PBO mode, assuming the output voltage scales down
M times, only (N/M) branches toggles and other PA unit branches turn o. The
output power is scaled down by M
2
, conduction loss and dynamic power loss scale
down by M. The eciency of the PBO of conventional digital PA by turning o
the driver unit cells is:
D
=
R
L
M
2
R
L
M
2
+
R
ON
M
+
2
2
f
M
C
SW
R
L
2
+
2
4
f
M
C
pre
R
L
2
(2.16)
In this case, we can observe less dynamic loss due to the energy savings from
the turned-o driver unit cells. When SHS PA is applied, we choose M-th order
subharmonic. Unlike the conventional digital PA, all the N branches toggles at
M-th harmonic to generate M times smaller voltage (M equals 3 in our real imple-
mentation). Note that, the conduction current
owing through each transistor is
reduced by M as we enabled M times more PA branches. Therefore, the conduction
15
loss can be further reduced (by a factor of M
2
). Although more driver cells are
toggled, the switching frequency is M times lower. The PBO power eciency for
SHS PA can be expressed as:
D
=
R
L
M
2
R
L
M
2
+
R
ON
M
2
+
2
2
f
M
C
SW
R
L
2
+
2
4
f
M
C
pre
R
L
2
(2.17)
When we compare (2.16) and (2.17), the multi-bit SHS PA eciency is found to
improve, mainly due to the lower conduction loss of the driver. In summary, SHS
technique helps reduce driver-caused power losses in both single- and multi-bit
digital PA congurations.
• Reduced Capacitor Switching Loss
The ideal SCPA model can achieve 100% eciency at peak output power, as-
suming ideal PA drivers. In the peak power mode, all capacitors toggle around
the RF carrier frequency, which is the fundamental switching frequency. When
the conventional SCPA operates in the PBO region, the power eciency starts to
decrease due to a charge loss through the capacitor array. For example, Fig. 2.6
shows that two-thirds of the capacitors are connected to ground to achieve a PBO
of 9.5 dB via a capacitor divider, and hence the charge loss. For convenience, the
conventional SCPA power and eciency equations from [20] are repeated here:
16
Figure 2.6: (a) Conventional switched capacitor PA (SCPA) in PBO mode; (b)
SHS SCPA in PBO mode
17
Figure 2.7: SHS SCPA in dierent power regions
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
SC
=
n(Nn)
N
2
CV
DD
2
f
P
out
=
2
2
(
n
N
)
2V
DD
2
R
L
D
=
Pout
Pout+P
SC
=
1
1+
4
(Nn)
n
1
Q
LOAD
Q
LOAD
=
2fL
R
L
=
1
2fCR
L
(2.18)
The key energy-loss mechanism involved is that the conventional SCPA reduces
the output voltage by capacitive division through the SC array, i.e., through charge
redistribution. When some of those capacitors are tied to ground, the charge stored
18
in those capacitors will be discharged and wasted. To avoid this charge loss, it is
better to avoid capacitive division as much as possible, which can be achieved via
the SHS technique.
Next, we will analyze this dynamic power loss and theoretical eciency in the
representative PBO regions to observe the improvement due to SHS using the third
subharmonic component (fc/3). When the PA operates between 0 dB and -9.5 dB
PBO, part of the PA cells toggle at fc/3, while the rest toggle at fc. This setup
occasionally results in capacitive division and hence introduces some energy loss in
the capacitor bank. As an example, as shown in Fig. 2.7 when the output power is
at -6 dB PBO, three branches toggle at fc/3 and one branch toggles at fc. Due to
the frequency dierence, the switched-capacitor bank can never toggle all together,
thus causing charge loss. Assuming that 3n cells toggle at fc/3 and that (N-3n)
cells toggle at fc, we can derive the power and eciency equations as:
8
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
:
P
SC
=
3n(N3n)
N
2
CV
DD
2
(f
f
3
)
P
out
=
2
2
(
3n
N
1
3
+
N3n
N
)
2V
DD
2
R
L
=
2
2
(
N2n
N
)
2V
DD
2
R
L
D
=
Pout
Pout+P
SC
=
1
1+
2
n(N3n)
(N2n)
2
1
Q
LOAD
(2.19)
When the PA operates at the<-9.5 dB PBO region, the PA cells either toggle at
fc/3 or are turned o. Compared to conventional SCPA (Fig. 2.7), three times more
cells toggle together to maintain the same output power. For the -12dB PBO case
shown in Fig. 2.7 three cells toggle at fc/3 and one cell ties to the AC ground, thus
19
Figure 2.8: SHS SCPA with hybrid class-G operation
creating capacitive division and hence charge loss. In this <-9.5dB PBO region,
the power and eciency equations are:
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
P
SC
=
3n(N3n)
N
2
CV
DD
2f
3
P
out
=
2
2
(
3n
N
2
1
9
=
2
2
(
n
N
)
2V
DD
2
R
L
D
=
Pout
Pout+P
SC
=
1
1+
4
n(N3n)
n
1
Q
LOAD
(2.20)
Compared to the conventional SCPA (i.e., Eqn (23) versus Eqn (25)), the e-
ciency in the<-9.5 dB PBO region is always better due to the dierence of toggling
cells (3n vs. n).
20
2.1.3 SHS SCPA with Hybrid Class-G Operation
Modern communications systems use various modulation signals with varying
peak-to-average-power ratios (PAPRs). One eciency peak in the PBO region is
not sucient to enhance the eciency of dierent PAPR signals. In this section, we
present an SHS digital PA with hybrid class-G operation for this purpose. The class-
G operation essentially changes the power supply of the PA driver cells in order to
scale dierent output power levels. In this prototype, we chose either 3VDD (3.6V)
or 2VDD (2.4V) and the third subharmonic frequency for SHS operation to achieve
more power eciency peaks in the PBO region.
As shown in Fig. 2.8, at 0 dB PBO (i.e., peak power mode), all the PA cells
toggle together at the carrier frequency using 3VDD. This setup achieves the highest
eciency, as discussed in Section II.B. When all the PA cells toggle at a lower supply
(2VDD) and carrier frequency, another eciency peak is achieved at the -3.5 dB
PBO point. At the -9.5 dB PBO, again, all the PA cells toggle at 3VDD but now
with the SHS frequency. The last eciency peak occurs at -13 dB PBO, when all
the PA cells toggle at lower supply and SHS frequency.
The combination of the SHS technique and hybrid class-G operation now yields
four eciency peaks in total. The average eciency of dierent PAPR signals can
thus be enhanced.
In addition, we compile a hybrid switching table that combines SHS and dual-
supply class-G operation for each PA cell to further optimize the eciency between
21
Table 2.1: Simplied PBO operation table
these peaks. The look-up table (LUT) optimizes the eciency for all the AM
codes. Fig. 2.9 shows a simplied LUT to illustrate the operation. (Note that
the actual LUT implementation is 8-bit.) To achieve better average eciency, the
general design guideline for this LUT is to turn on more PA unit cells simultane-
ously, which can minimize the PA driver conduction loss (Eqn (17)), oer better
impedance matching (Eqn (21)(22)), and reduce the dynamic loss (Eqn (24)(25)])
in the switched capacitor bank.
Specically, from 0 to -3.5 dB PBO, the hybrid class-G switching scheme en-
hances eciency. The PA cells' supply voltages gradually change from higher supply
to lower supply. This scheme uses both supply voltages simultaneously to achieve
better eciency. From -3.5 to -9.5 dB PBO, the PA cells start to operate at subhar-
monic frequency with a higher power supply. All the PA cells sequentially convert
to the combination of subharmonic and higher supply.
22
Between -9.5 dB PBO and -13 dB PBO, all the PA cells again change from higher
supply to lower supply with SHS frequency. Note that all the PA cells remain in
the \on" state from 0 to -13 dB PBO. The PA output impedance variation is small
within this range. When the output power level is lower than -13 dB PBO, some
of the PA cells start to turn o, thus degrading eciency. But since SHS helps to
keep more PA cells toggling compared to conventional digital PA, the eciency still
improves given the same PBO point, as discussed in Section II. B. In this prototype,
we use a behavioral model that includes all the power-loss mechanisms to help
determine the nal LUT. The LUT is implemented on-chip and fully synthesized
inside the SHS block.
2.2 Circuit Implementation
2.2.1 Digital SHS PA Architecture
Fig. 2.10 shows the overall block diagram of the digital PA prototype, which
utilizes polar architecture. The 8-bit AM signal path is clocked up to 400 MS/s
and is received o-chip via the low-voltage dierential signaling (LVDS) receiver.
Based on the AM code, a digital decoder block generates the proper amplitude,
phase, and supply-control codes according to the Fig. 2.9. Those control signals
are then properly retimed and phase-aligned for SHS operation.
23
Figure 2.9: Block diagram of the proposed PA implementation
The dierential PM signal is generated o-chip and passed through the CML-
to-CMOS buer. The phase generator then creates the divide-by-three PM signal
and delayed PM signal. A phase detector and tunable delays are implemented to
ensure that these two signals are phase-aligned. In order to avoid phase glitches,
the phase-control signal is retimed with the PM signal to create a glitch-free MUX
control signal. The high-speed MUX then selects the desired switching frequency
based on the phase-control code. The selected PM signal and amplitude control
code are combined with AND gate prior to the PA drivers. The outputs then
connect to an 8-bit segmented capacitor bank with 15-bit unary MSBs and 4-bit
binary LSBs. Note that non-overlapped control signals are used for PA drivers in
order to minimize short circuit currents (i.e., power loss). The following sub-sections
examine several key building blocks.
24
Figure 2.10: Proposed PA unit cell
2.2.2 Stacking Class-D PA Driver
One design challenge for class-D PA is that the output voltage swing is bounded
by the device breakdown voltage. To achieve higher output power, one way is to
reduce the PA load impedance RL. A few issues are associated with small load
impedance, however. First, given a 50-ohm antenna, the small PA load impedance
requirement increases the impedance conversion ratio, which degrades the match-
ing network eciency. Second, the routing parasitic resistance can easily degrade
overall PA eciency. Therefore, we stack multiple devices to allow a higher power
supply, and hence a larger output voltage swing instead of drastically reducing
the PA load impedance. Additionally, to support class-G operation, the PA driver
should work with two dierent supplies (3VDD and 2VDD in this work).
25
As shown in Fig. 2.11, when the driver operates in 3VDD mode, the non-
overlapping PM signals are sent to the MP1 and MN1 transistors to turn on either
the pull-up or pull-down paths, respectively. The output then toggles between
3VDD and ground. The gate of the MN4 transistor is biased at 2VDD to disable
the 2VDD mode and to avoid current leakage. When the driver works in the 2VDD
mode, MP1 and MP2 transistors are turned o, and the gate of the MN4 transistor
is biased at 3VDD to turn on the 2VDD mode. MP3 changes from 2VDD to VDD
to pass the signal. In this mode, the non-overlapping PM signals are sent to the
MN1 and MP4 transistors, which connect the driver output to either 2VDD or
ground.
To alleviate voltage stress when the stacked devices are turned on, deep N-well
devices are used to separate the NMOS transistors' bodies so that their bodies
and source terminals can be shorted together. The deep N-well (DNW) layer is
connected to 3VDD through large isolation resistance, which avoids forward biasing
and reduces the parasitic capacitance power loss associated with the diodes. In the
3VDD mode, when the devices turn on, we bias the gate of the stacked DNW
devices MN2 and MN3 at VDD to ensure that the voltage dierence between gate,
source, body, and the drain terminal equals the nominal supply voltage of VDD.
For PMOS transistors, the gates of PMOS transistors MP2 and MP3 are biased at
2VDD for the same purpose. When the devices are o, however, the voltage stress
of the MN3 and MP3 can be 2VDD. Fortunately, the transistor can sustain high
26
Figure 2.11: Power and eciency contours
voltage stress when the transistor is in the \o" state. If reliability is of particular
concern, this issue can be alleviated by implementing the self-bias control circuit
in the driver [25].
To optimize the tradeo between PA maximum output power and eciency,
we size the transistors according to the load pull simulation results (Fig. 2.12).
The load pull simulation includes all the 8-bit PA pre-drivers and nal output
driver stages. To achieve both eciency and output power, the matching network
impedance is designed as 4+1.9j to compromise between maximum eciency con-
tours and power contours.
27
Figure 2.12: PM generator
2.2.3 Subharmonic PM Generation
The PM generator takes in the external PM signal and uses a divide-by-three
block to create the subharmonic component of the PM signal for SHS operation
(Fig. 2.13). Note that, to keep the same phase information at carrier frequency,
the relative phase should be divided by three at subharmonic, which is naturally
achieved by the divide-by-three block. With the combination of the D
ip-
op
(DFF) outputs, the subharmonic PM signal is created by S-R Latch. A phase
alignment block is implemented to align both PM signals at fundamental and SHS
frequencies.
28
A non-overlapping control signal is created after the PM generator to mitigate
the crowbar current, which is another power-loss mechanism in a class-D PA. During
the switching transitions, the pull-down NMOS and pull-up PMOS transistors can
both be on momentarily, which leads to large crowbar current. To avoid this issue,
the non-overlapped PMH and PML signals are generated to control the pull-up
and pull-down devices of the output driver, respectively. Given the small relative
time delay, the crowbar current is then suppressed. A tunable delay is implemented
in this prototype to experiment on the tradeos between maximum eciency and
peak output power.
Notably, the duty cycle of the generated subharmonic aects the amplitude
at the carrier frequency. Ideally, a third subharmonic waveform with 50% duty
cycle provides 1/3 of the peak output voltage amplitude, However, the duty cycle
variation can cause output voltage amplitude to deviate. Theoretically, using fc/3
with duty cycle of d, the output voltage at the carrier frequency is:
P
out
=
2
2
V
2
DD
R
L
sin
2
(d)
Z
0
x
2
d!t (2.21)
where d is the duty cycle of the SHS signal. According to (26), if the duty cycle
changes from 50% to 45%, a 1 dB dierence in output power will result. Since the
duty cycle error introduces additional AM-AM and AM-PM non-linearity, the error
can be calibrated by the PA pre-distortion in this prototype.
29
Figure 2.13: Single-ended on-board matching network
2.2.4 Matching Network
The matching network is implemented on board by using Murata surface
mounted components. The single-end matching network schematic is shown in Fig.
2.14. The network converts the impedance from 50 ohms to the optimum impedance
value, which is determined by the PA load pull simulation. Based on the bandpass
frequency response, the notch response can be simply added by changing one of
the inductors to an LC tank that resonates at subharmonic frequencies (i.e., Fc/3
in this work). At the carrier frequency, the LC tank works as a capacitor, and the
matching response takes a second-order bandpass shape. At subharmonic frequency
Fc/3, the matching network becomes an open circuit for the frequency term, and the
input impedance of the matching network becomes suciently large. Ideally, the
impedance at the subharmonic will be suciently high to prevent power leakage, as
with other unwanted harmonics. The output power of those harmonics is negligible
(less than 1.5% compared to the carrier frequency). Compared to the conventional
second-order matching network, the additional loss is less than 0.3dB.
30
Figure 2.14: Chip micrograph and testing board
2.3 Measurement Result
The SHS PA prototype was fabricated using a 65-nm bulk CMOS process with
a die size of 2 mm x 1.71mm (Fig. 2.15). The silicon die was directly mounted and
bonded to a lower dielectric constant Nelco N4000 ("=3.4) PCB with an on board
matching network (Fig. 2.14). The measured matching network loss was found to
be 1.3 dB at 2.25 GHz.
2.3.1 Continuous-Wave(CW) Measurement
In the next step, a low-phase-noise sine wave and 12-bit 200MS/s baseband
PM digital codes were sent to an AD9779 evaluation board to generate the phase-
modulated signal. The chip also included a 200-MHz clock and a 200-MS/s base-
band AM digital stream from FPGA via the FMC interface. The PA output was
then connected to the power meter and spectrum analyzer for static and dynamic
31
Figure 2.15: Measured peak power and eciency versus frequency
measurements. For proper operation, a 10-MHz reference clock was used to syn-
chronize the sine-wave generator and FPGA reference clock.
First, we measured maximum PA output power (Psat) and peak drain eciency
by sweeping the frequency (Fig. 2.16). The PA was found to deliver 26.8 dBm
maximum output power and 49.3% peak drain eciency at 2.25GHz. The PA
achieved a 3dB bandwidth of more than 500MHz.
The measured subharmonic rejections at -13 dB PBO are shown in Fig. 2.17.
At -13 dB PBO, all the PA cells toggle at 3rd subharmonic, which generate the
largest subharmonic tones. With the o-chip matching network, the worst spur is
38 dB lower than the desired tone at the carrier frequency.
Fig. 2.18 shows the measured PA eciency versus dierent PBO levels. We can
observe four eciency peaks thanks to SHS with hybrid class-G operation. The
measured power eciency was found to improve by as much as 2.6x at -13dB PBO
over class-B PA, thus validating the eectiveness of the proposed SHS architecture.
32
Figure 2.16: Measured PA output spectrum at -13dB PBO without any additional
ltering. A 10-dB attenuator is used at the PA output in the measurement
Figure 2.17: Measured PA drain eciency (DE) at 2.25GHz versus PA output
power
33
Figure 2.18: Measured AM-AM and AM-PM distortion
The measurement is based on the pre-compiled LUT as described in Section III.
As an experiment, we have compared several dierent SHS/class-G combinations
that yield the same PA output level, i.e. multiple points at the same Pout level in
Fig. 2.18. It is found that the operation modes pre-compiled in LUT yields better
or similar eciency.
The AM-AM and AM-PM transfer function of the PA were measured by sweep-
ing the amplitude codes (Fig. 2.19). The AM-AM performance of the PA was
found to be superior because of the custom-designed precision of the MIM capaci-
tors. Note that the AM-PM characteristic showed a few ripples between codes 85
and 169. This eect was caused by changing supplies and input-switching frequen-
cies simultaneously between second- and third-eciency peaks (-3.5dB -9.5 dB
PBO), which agrees well with the correct operation. The AM-AM and AM-PM
characteristics were used to generate the LUTs for PA pre-distortion.
34
Figure 2.19: Measured EVM for real-time and hybrid class-G operation
2.3.2 Modulated Signal Measurement
For the modulated signal measurement, the PA was rst pre-distorted by the
memoryless LUTs to compensate AM-AM and AM-PM distortion. The entire pre-
distortion process was done on-chip. We tested the PA prototype with a 5 MHz, 52
sub-carrier, 16-QAM OFDM-modulated signal with 7.2dB PAPR. Under real-time
operation (i.e., transmitting a set of OFDM symbols on the
y), the PA achieved
an average drain eciency of 35.7%.
For linearity characterization, the PA in-band and out-of-band linearity values
were recorded under the same real-time operation. As shown in Fig. 2.20, the
measured EVM was found to be -26dB. Fig. 2.21 shows the measured close-in
PSD characteristics. The ACPR is -28 dBc before calibration and -34dBc after
35
Figure 2.20: Measured spectrum for real-time SHS and hybrid class-G operation
calibration. The linearity can be further improved by using advanced digital pre-
distortion (DPD) and memory eect calibration. The sample rate can be increased
to lower the noise spectral density. In addition, the PA linearity can be further
improved by real-time 2D-LUT and memory-eect calibration.
Table I compares the current work with state-of-the-art CMOS PAs with dif-
ferent PBO eciency-enhancement techniques. Our PA delivers 26.8dBm peak
output power with a 49.3% peak drain eciency. The -13dB PBO drain eciency
was found to be 27%. The proposed SHS with hybrid class-G operation achieved su-
perior PBO and average drain eciency with comparable maximum output power.
36
Table 2.2: Comparison with other PBO eciency-enhanced CMOS digital PAs
2.4 Summary
This work has proposed a subharmonic switching (SHS) power amplier (PA)
architecture to enhance power back-o (PBO) eciency. The SHS technique can be
combined with other eciency-enhancement techniques (such as class-G operation)
to further improve deep PBO eciency. We proposed a stacking class-D driver
to enlarge the output voltage swing. The PA prototype achieved superior PBO
eciency compared to state-of-the-art CMOS PAs.
37
Chapter 3
A Watt-Level Phase Interleaved
Multi-Subharmonic Switching Digital Power
Amplier
3.1 Multi-SHS PA Architecture
The SHS PA architecture naturally achieves PBO by toggling the switching
PA cells at the subharmoinic of the carrier frequency and enhances the eciency.
However, to eliminate the unwanted subharmonic tones, additional notch ltering
is required to remove those spurs, which potentially increases the order of the
matching network. Although the sharp notch response may be achieved with high-
Q o-chip components, doing so limits the PA bandwidth at the carrier frequency.
Therefore, we proposed a phase-interleaved architecture that inherently cancels the
undesired spurs. Meanwhile, this architecture can be used to increase the peak
output power of the PA, achieving watt-level output power. Moreover, based on
38
Figure 3.1: Subharmonic switching digital PA operation
the SHS concept, a multi-SHS technique is proposed to create a larger number of
eciency peaks over a deeper PBO region, which enhances the PA average eciency
as well as supports a higher PAPR signal. Finally, the proposed architecture can
still be further combined with other eciency enhancement techniques to improve
the average eciency.
3.1.1 Multi-SHS PA Operation
We rst brie
y review the concept of the SHS PA, as shown in Fig. 3.1. In the
peak power mode, the PA switching frequency equals the carrier frequency. The
matching network picks up the fundamental of the square waveform as the carrier
frequency. As we notice here, the input switching waveform is a square wave, and
it contains odd harmonic components, assuming it is a 50% duty cycle. The power
prole of the harmonics is in descending order (i.e., the third harmonic is lower
than the fundamental tone, and the fth harmonic is even lower).
39
The PA works in the SHS region when the PA toggles at a subharmonic of the
carrier frequency and chooses the harmonic as the carrier frequency. It naturally
achieves PBO without turning o the PA cells or reducing the power supply. For
example, if we use the third subharmonic, Fc/3, to toggle the PA cells, its third
harmonic component, i.e. Fc, equates the carrier frequency. In this case, the output
power at Fc is 10log10((1/3)2) dB lower due to the square switching waveform, and
hence achieves PBO. Extending from the SHS PA concept, we propose a multi-SHS
scheme by using multiple subharmonic switching waveforms. That is, there are
multiple toggling frequency candidates for each PA driver cell. The selection of the
actual toggling frequency depends on the intended PBO level. In other words, each
PA driver cell can toggle at Fc/3, 2Fc/3, or Fc. In the SHS PA, we have shown
that Fc/3 waveform can be generated via a divide-by-three circuit.
To generate 2Fc/3 for a multi-SHS PA, we propose a non-uniform gating scheme
to create the switching waveform. As shown in Fig. 3.2, if we non-uniformly gate o
one of the pulses at Fc, it naturally derives the frequency of 2Fc/3. All the PA driver
cells simultaneously toggle twice every three cycles. The output power possesses
10log10((2/3)2) less power compared to peak power mode. Assuming the PA unit
cell is lossless, the whole PA architecture can lead to an eciency peak at the -3.5
dB PBO point. More details of the eciency peak will be addressed in Section 3.1.2.
Note that the proposed non-uniform gating scheme allows a simple implementation,
as a window function can be directly gated with the original waveform at the
40
Figure 3.2: Switching waveforms of the proposed multi-subharmonic operation
41
Figure 3.3: Multi-SHS digital PA at dierent output power levels
carrier frequency (Fc), avoiding the need for a fractional-N frequency synthesizer.
In addition, the same scheme can be easily extended to use deeper subharmonics,
such as Fc/5, 2Fc/5, 3Fc/5, etc., and creates even more eciency peaks.
3.1.2 Multi-SHS PA Eciency Enhancement
In this sub-section, we analyze the eciency enhancement using a multi-SHS PA.
There are three eciency enhancement mechanisms in a SHS digital PA, including
PA conduction loss, impedance matching, and dynamic loss in a switched capacitor
bank. More detailed derivations can be found in [18]. A multi-SHS PA has the
same eciency enhancement mechanisms for PA conduction loss and impedance
matching. The switched capacitor dynamic loss is dierent compared to the SHS
digital PA. We focus on the dynamic loss savings to validate the multiple eciency
peaks created by the multi-SHS scheme.
42
Fig. 3.3 shows the multi-SHS switched-capacitor PA (SCPA) in dierent power
regions. The eciency can be improved by operating dierent subharmonics be-
tween the eciency peaks. To derive the power and eciency equations under
a multi-SHS scheme, the conventional SCPA output power and drain eciency
equations considering the switched capacitor dynamic loss are repeated here [20]:
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
SC
=
n(Nn)
N
2
CV
DD
2
(F
C
)
P
out
=
2
2
(
n
N
)
2V
DD
2
R
L
D
=
Pout
Pout+P
SC
=
1
1+
4
(Nn)
n
1
Q
LOAD
Q
LOAD
=
2F
C
L
R
L
=
1
2F
C
CR
L
(3.1)
where N is the total number of digital PA branches. Assuming the number of
toggling PA cells is n, dynamic power loss PSC and output power Pout are shown
in the equations(1).
Here, we will derive theoretical eciency and dynamic loss of multi-SHS in the
representative PBO. We assume that (N-M) and M of the PA cells will toggle at
frequency of FSH1 and FSH2, respectively. By design, FSH1 and FSH2 is the subset
of adjacent frequency candidates, namely fundamental, subharmonic frequencies
and 0, where FSH1 > FSH2. Note that, when the toggling frequency is zero,
it indicates that the PA cell does not toggle. Next, a generalized multi-SHS PA
dynamic loss, output power and eciency can be derived as:
43
8
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
:
P
SC
=
M(NM)
N
2
CV
DD
2
(F
SH1
F
SH2
)
P
out
=
2
2
(
NM
N
F
SH1
F
C
)
2V
DD
2
R
L
D
=
Pout
Pout+P
SC
=
1
1+
4
(M(NM)F
C
(F
SH1
F
SH2
)
[(NM)F
SM1
+MF
SM2
]
2
1
Q
LOAD
(3.2)
While (2) describes a general case of multi-SHS PA, our silicon prototype uses
the third subharmonic frequencies, i.e. the toggling frequency candidates include
Fc, 2Fc/3, Fc/3 and 0. As shown in Fig. 3.3, when the PA operates between 0
and -3.5 dB PBO, a portion of the PA cells starts to toggle at 2Fc /3, while the
rest toggle at Fc. The frequency dierence results in some charge redistribution
and thus introduces some energy loss in the capacitor bank. When the PA operates
between -3.5 and -9.5 dB PBO, the PA cells toggle at either 2Fc/3 or Fc/3. The
dynamic loss is smaller compared to that of the conventional SHS PA. When the
PA operates at the < -9.5 dB PBO region, a portion of PA cells start to turn o,
resulting in eciency roll-o. The PA eciency and output power follow those of
the SHS PA [18]. The ideal eciency under dierent PBO region can be expressed
as:
8
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
:
D
=
1
1+
4
n(NM)
(N
M
3
)
2
1
Q
LOAD
;P
out
2 03:5dB
D
=
1
1+
4
(Nn)
n
1
Q
LOAD
;P
out
23:59:5dB
D
=
1
1+
4
(Nn)
n
1
Q
LOAD
;P
out
29:513dB
(3.3)
44
Table 3.1: An example of multi-SHS digital PA operation table
Fig. 3.4 shows the 4-bit multi-SHS look-up-table (LUT) to illustrate the op-
eration, while the actual implementation is 8-bit with class-G. The general LUT
design guideline is to minimize the equivalent capacitance, which requires more PA
unit cells be turned on simultaneously. Note that at certain output power level,
the PA cells can operate with dierent subharmonics. With this hybrid operation,
eciency between the peaks can be optimized as well.
The eciency tradeos with Pout for multi-SHS, single-SHS digital PA and
conventional SCPA are plotted in Fig. 3.5. In this comparison, the loaded quality
factor QLoaded is xed to 1. The PBO eciency curve indicates that the multi-SHS
PA PBO eciency is always higher than other alternative architectures. Note that,
the multi-SHS can further combine with other eciency enhancement techniques
to improve the deep PBO eciency.
45
Figure 3.4: Ideal eciency of multi-SHS PA architecture vs. Pout and for single-
SHS PA and conventional SCPA
3.1.3 Phase-Interleaved Subharmonic Inherent
Cancellation
Unwanted subharmonics can violate the mask and degrade the PA eciency
if they appear at the transmitter output waveform. These spurs can cause recip-
rocal mixing or violate the emission mask [27]. Notch ltering embedded in the
matching network is required, which inevitably increases the matching order and
complexity. It becomes worse when we use the multi-SHS scheme, as there are
multiple subharmonic frequencies to be notched. We propose the phase-interleaved
PA architecture, to cancel the undesired subharmonics before the power combiner
without introducing additional power loss.
46
Figure 3.5: Equivalent circuit model of ideal three-way phase interleaved multi-SHS
PA with dierent input switching waveforms
Fig. 3.5 shows the phase-interleaved power combining under two dierent input
switching waveforms. Assuming the PA voltage signal is VPA,i (i = 1, 2, 3.),
and the PA output impedance is RPA,i, the current in the primary winding of
the transformers can be calculated by using the superposition theorem [28]. The
primary current of the three-way transformer-based combiner can be written as:
I
p;i
=
n
i
(n
1
V
PA;1
+n
2
V
PA;2
+n
3
V
PA;3
)
R
L
+ (n
2
1
R
PA;1
+n
2
2
R
PA;2
+n
2
3
R
PA;3
)
(3.4)
The output impedance is RL, and the transformer turn ratio is ni. The trans-
former impedance seen by each PA becomes:
Z
i
=
(R
L
+ (n
2
1
R
PA;1
+n
2
2
R
PA;2
+n
2
3
R
PA;3
))V
PA;i
n
i
(n
1
V
PA;1
+n
2
V
PA;2
+n
3
V
PA;3
)
R
PA;i
(3.5)
It is clear that the transformer impedance seen by each PA is related to load
impedance RL and the output voltage signal (the magnitude and the phase) of
all the PA cells. Based on the observation, if the summation of the three voltage
signals becomes zero, then the impedance seen by each PA is innity, which can
47
potentially reject the unwanted subharmonics. Assuming the turn ratio ni of the
three coils is equal to n, three PAs have the same output impedance RPA, when
the three PA voltage signals are in phase, the primary current of each PA cell can
be written as:
I
p
=
n
2
(A
PA;1
+A
PA;2
+A
PA;3
) sin(!t)
R
L
+ 3n
2
R
PA
(3.6)
The transformer impedance can be written as:
Z
i
=
(R
L
+ 3n
2
R
PA
)A
PA;i
n
2
(A
PA;1
+A
PA;2
+A
PA;3
)
R
PA
(3.7)
The current waveform and the voltage waveform are in phase. The transformer
impedance seen by each PA is identical. The power is combined at the secondary
winding side. If the three PA voltage signals are 120
apart, then primary current
becomes:
I
p
=
n
2
(A
PA;1
sin(!t) +A
PA;2
sin(!t +
2
3
) +A
PA;3
) sin(!t +
4
3
)
R
L
+ 3n
2
R
PA
(3.8)
As observed in (11), if three PAs present the same magnitude A, the primary
current becomes zero in this condition. In other words, output impedance Zi seen
by the PA is innity, and the unwanted signal gets rejected from the primary side
with the certain phase dierence. Although the voltage signal is non-zero, the power
loss, which equals the integration of the voltage multiplied by the current, becomes
48
zero due to zero primary current. More importantly, so long as the summation of
the three PA voltage signals becomes zero, the RL value will not aect the results
of the cancellation. In other words, the cancellation of the subharmonic component
is eective over dierent voltage standing wave ratio (VSWR).
Based on the discussions in this sub-section, if the desired carrier frequency
component is in phase, and the subharmonic frequencies are out of phase, we can
combine the output power at the desired frequency, and inherently cancel the un-
wanted subharmonics. The phasors in Fig. 3.5 show inherent cancellation in Fc/3
and 2Fc/3 frequency components while the Fc frequency components are added
coherently. The phase-interleaved Fc/3 and 2Fc/3 square waves contain Fc/3 com-
ponents 120
apart and 2Fc/3 components 240
apart, where the Fc components
are combined in phase. In conclusion, all the unwanted subharmonics components
are nullied, except for the residual errors due to magnitude and phase mismatches,
which will be discussed next.
• Amplitude Mismatch
So far, we assume all three PA banks are identical. However, in real imple-
mentation, there will be mismatches between dierent PA banks. PA magnitude
and phase errors can degrade the eectiveness of the inherent cancellation, as we
can observe from the measurement results. Here, we rst analyze the impact of
magnitude mismatches on the PA output spectrum. Considering one of the PA
49
magnitudes now becomes (A+ A), the corresponding current and voltage at Fc/3
derived from (7) can be written as:
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
I
p
(
!
C
3
t) =
n
2
R
L
+3n
2
R
PA
P
3
i=1
V
PA;i
!
C
3
t
V
PA;1
!
C
3
t = (A + A) sin(
!
C
3
t)
V
PA;2
!
C
3
t =A sin(
!
C
3
t +
2
3
)
V
PA;3
!
C
3
t =A sin(
!
C
3
t +
4
3
)
(3.9)
The subharmonic power, PSH,i, is the integration of the product of the voltage
and current at subharmonic:
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
P
SH;1
=
R
2
0
I
p
(
!
C
3
t)V
PA;1
!
C
3
t) =
A(A+A)n
2
R
L
+3n
2
R
PA
P
SH;2
=
R
2
0
I
p
(
!
C
3
t)V
PA;2
!
C
3
t) =
AAn
2
R
L
+3n
2
R
PA
P
SH;3
=
R
2
0
I
p
(
!
C
3
t)V
PA;3
!
C
3
t) =
AAn
2
R
L
+3n
2
R
PA
(3.10)
Assuming the transformer is lossless, the total subharmonic power PSH at the
undesired subharmonic can be written as:
P
SH
=
3
X
i=1
P
SH;i
=
A
2
n
2
R
L
+ 3n
2
R
PA
(3.11)
we can observe that the undesired power due to gain mismatch is proportional
to A
2
. The corresponding current and voltage amplitude at Fc are three times
smaller than the subharmonic.
50
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
I
p
(!
C
t) =
n
2
R
L
+3n
2
R
PA
A
3
sin(!
C
t)
V
PA;1
(!
C
t) =
(A+A)
3
sin(
!
C
3
t)
V
PA;2
(!
C
t) =
A
3
sin(!
C
t)
V
PA;3
(!
C
t) =
A
3
sin(!
C
t)
(3.12)
Similar to (10), the total output power considering the amplitude mismatch at
Fc becomes:
P
OUT
=
3
X
i=1
P
PA;i
=
(3A + A)
2
n
2
9(R
L
+ 3n
2
R
PA
)
(3.13)
Therefore, the amplitude mismatch induced SFDR becomes:
SFDR = 10lg
P
OUT
P
SH
= 20lg
3A + A
3A
(3.14)
From (14), one can calculate the amplitude mismatch requirement for this PA
architecture. As an example, when A=A 1%, SFDR is roughly 40 dB. To
meet the mask and EMI/EMC requirement, the proposed non-overlapping clock is
utilized to calibrate the amplitude dierence of each path.
• Phase Mismatch
Next, we discuss the eect of the phase error. Assuming all the three PAs are
matched, except that one PA presents a phase oset , the current and voltage
equations are:
51
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
I
p
(!
C
t) =
An
2
R
L
+3n
2
R
PA
P
3
i=1
V
PA;i
(!
C
t)
V
PA;1
(!
C
t) =A sin(!t + )
V
PA;2
(!
C
t) =A sin(omega
C
t +
2
3
)
V
PA;3
(!
C
t) =A sin(!
C
t +
4
3
)
(3.15)
Similarly, the subharmonic power of each PA can be expressed as:
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
P
SH;1
=
n
2
A
2
R
L
+3n
2
R
PA
(1 cos())
P
SH;2
=
n
2
A
2
R
L
+3n
2
R
PA
(
1
2
1
2
cos() +
p
3
2
sin())
P
SH;2
=
n
2
A
2
R
L
+3n
2
R
PA
(
1
2
1
2
cos()
p
3
2
sin())
(3.16)
As a result, the total subharmonic power PSH becomes:
P
SH
=
3
X
i=1
P
SH;i
=
2n
2
A
2
R
L
+ 3n
2
R
PA
(1 cos()) (3.17)
From (17), it shows that the power at the unwanted subharmonic frequency is
a function of cos(), which is relatively insensitive when phase error is small.
Similar to the derivation of amplitude mismatch, the total output power con-
sidering the amplitude mismatch at Fc becomes:
P
OUT
=
3
X
i=1
P
PA;i
=
n
2
A
2
(5 + cos(3))
9(R
L
+ 3n
2
R
PA
)
(3.18)
52
Therefore, the amplitude mismatch induced SFDR becomes:
SFDR = 10lg
P
OUT
P
SH
= 10lg
5 + 4 cos(3)
18(1 cos()
(3.19)
From (19), when equals 1.8 degree at Fc, it yields roughly 40-dB SFDR.
The phase detector and tunable delay cells are implemented on chip to calibrate
the phase mismatch between dierent channels. The delay cells have a 0.2 ps tuning
resolution with 2ns tuning range, i.e. 10-bit resolution.
Note that, the calculated SFDR due to both amplitude mismatch and phase
mismatch assume the matching network and antenna presents all-pass response. In
reality, additional attenuation can be achieved via matching network and antenna's
selectivity, which suggests better SFDR between fundamental and subharmonic
components.
In the real implementation, there are more mismatch sources, such as PA output
impedance RPA and transformer coupling factor ni, etc., which can be analyzed in
a similar analysis strategy. Additionally, due to the associated parasitic inductance
from the transformer, the current at the subharmonics is non-zero. Fortunately, the
current waveform remains 90
out-of-phase with the voltage waveform, and thus, it
still achieves the cancellation and zero power loss.
53
Figure 3.6: Complete phase-interleaved multi-SHS digital PA with hybrid class-G
operation
54
3.1.4 Multi-SHS with Hybrid Class-G Operation
The phase-interleaved multi-SHS operation can be further combined with other
existing eciency enhancement techniques to further improve the average eciency
under dierent PAPRs. All three PA banks must maintain the same input switch-
ing pattern and the same supply conguration to guarantee that the output power
of each PA bank is identical, which results in eective cancellation on all the sub-
harmonics, as the equations showed in Section II.
In this section, we introduce a multi-SHS digital PA with hybrid class-G op-
eration to optimize eciency for dierent PAPR signals. The class-G operation
changes the power supply of each PA driver to create dierent output power levels.
In the real implementation, we chose either 2VDD or 3VDD for class-G, and either
Fc/3 or 2Fc/3 for multi-SHS, to achieve ve ideal eciency peaks located at 0,
-3.5, -7.0, -9.5, and -13 dB (Fig. 3.6). The eciency between the peaks can be
further improved by toggling the cells of each PA with dierent supplies and input
switching frequencies.
In addition, the eciency between the peaks can be further improved by tog-
gling the cells of each PA with dierent supplies and input switching frequencies
(Fig .3.7). To optimize the eciency between the peaks, the general guideline is
to reduce the equivalent capacitance from the capacitor bank and minimize the
toggling overhead. From 0 to -3.5 dB PBO, the hybrid class-G operation is utilized
to create the PBO, and enhance the eciency. From -3.5 to -7 dB PBO, all the
55
PA cells are tied to 2VDD, but with dierent input switching frequencies. As an
example, shown in Fig. 3.6, two PA cells toggle with Fc, and one PA cell toggles at
2Fc/3 at -4.5 dB PBO. Note that all three PA banks must keep the same cong-
uration to maintain the same output power. Therefore, the subharmonic inherent
cancellation requirement can be satised.
Between -7 and -9.5 dB PBO, all the PA cells toggle at dierent supplies and
input switching frequencies. For example (Fig. 3.6), in each PA bank, two PA cells
toggle at 2Fc/3 with 2VDD, and one PA cell toggles at Fc/3 with 3VDD at -7.8 dB
PBO. From -9.5 and -13 dB PBO, all the PA cells have the same input switching
frequency, Fc/3, and dierent supplies. In Fig. 3.6, all the PA cells toggle at Fc/3
with the 2VDD and 3VDD supplies, which creates -11.7 dB PBO. Based on the
optimal eciency value, we determine the combination of dierent supplies and
switching frequencies. Note that, the phase-interleaved subharmonic cancellation
is eective for all amplitude levels, as the input waveforms of each PA bank are the
same except for the 120-degree phase shift between them. The compiled LUT is
fully synthesized in the multi-SHS block.
56
Figure 3.7: Block diagram of the PA prototype
3.2 Circuit Implementation
3.2.1 Multi-SHS Digital PA Architecture
Fig. 3.7 shows the top-level block diagram of the phase-interleaved multi-SHS
PA prototype. The prototype adopted the polar architecture with the considera-
tion of high eciency. The input paths contain amplitude modulation (AM) and
phase modulation (PM) paths. The dierential PM signal rst passes through the
current mode logic (CML) buers and converts to the rail-to-rail CMOS-type PM
signal. Then, the PM signal is distributed to three local phase generators with
dierent control settings. The phase generator creates three phase signals, includ-
ing a delayed original PM signal (Fc), a divide-by-three PM signal (Fc/3), and a
non-uniform gated PM signal (2Fc/3). To mitigate time skew between dierent
phase generators and dierent PM signals, phase detectors and tunable delays are
57
implemented. The generated phase signals then pass through the high-speed mul-
tiplexer (MUX). Note that the phase control signal is retimed with the original PM
signal to avoid phase glitches. Depending on the AM LUT, the MUX selects the
PM signals corresponding to the intended PA input switching frequency.
The 8-bit AM signal, and the clock signal are generated o-chip using the low-
voltage dierential signaling (LVDS) format. Depending on the modulated signal
bandwidth, the sample rate of the AM signals can be set up to 1 GS/s. The AM
signal is rst sent to a digital decoder, and generates the LUT for multi-SHS with
the hybrid class-G operation. The LUT outputs contain the amplitude code, phase
control word, and supply control word, and then control the phase-interleaved PA
core. All the control signals are properly retimed and phase-aligned for the multi-
SHS operation. An \H-tree" layout strategy is utilized to minimize the time skew
between dierent channels and control signals. Note that each PA bank must
maintain the same amplitude code to generate the same output power. It will
guarantee the subharmonic cancellation under all the dierent output power levels,
as we discussed in Section II.
The desired PM signal and amplitude code are combined in the polar combiner
before the PA drivers. The non-overlapping clock is implemented to generate non-
overlapped PA input signals to suppress the crowbar current, which can improve the
class-D driver peak eciency. It also achieves an equivalent resolution of 1.2mV in
58
Figure 3.8: Single-ended PA Matching Network
voltage domain to ne calibrate the unwanted subharmonic spurs. We use a three-
stacking class-D driver to enlarge the output voltage. Depending on the control
LUT, the driver can work in the 2VDD and 3VDD modes locally. The load pull
simulation includes all the PA drivers that are matched to the load which generates
the best eciency point. More implementation details about the triple stacking
drivers can be found in [25]. The PA driver outputs connect to the capacitor bank.
The custom-designed precise MIM capacitor is implemented to result in dierential
nonlinearity (DNL). Last, an on-chip three-way power combiner is used, which is
described in the following section.
3.2.2 Three-Way Power Combiner
The proposed transformer-based power combiner provides four main objectives
in this PA prototype: power combining, inherent subharmonic cancellation, dif-
ferential to single-ended conversion, and impedance matching. Fig. 3.8 shows
59
Figure 3.9: Simulated PA load impedance ZL versus frequency
the singled-ended equivalent circuit of the transformer. Firstly, each of the trans-
former will see a dierential RL/3 load (single-ended RL/6) due to the three-way
power combiner. There are two turns for both primary and secondary side to ob-
tain enough inductance. The transformer intrinsic inductance, together with the
switched capacitor bank will convert the load impedance to the PA optimum load
impedance at the carrier frequency.
Fig. 3.9 shows the simulated PA load impedance ZL versus the frequency. The
result shows that the impedance is around 5.5-ohms with 1-ohm variation from
1.45 GHz to 2.25 GHz, achieving wideband impedance transformation with low
loss. The matching load impedance is designed as 5.5-ohms to provide optimum
eciency and output power.
60
Figure 3.10: Three-way power combiner model in HFSS
Figure 3.11: Simulated S21 of the power combiner over the frequencies
61
The \gure 8" power combiner structure could be a potential candidate for a
high-eciency high-power PA design, as it helps reduce mutual coupling between
adjacent primary coils. However, for the \gure 8" structure, all the primary wind-
ings are not symmetric with respect to the secondary, thus introducing an inherent
amplitude and phase mismatch. Therefore, we choose the same 2:2 transformer
footprint to keep the impedance conversion ratio symmetric. The parasitic coupling
between the primary and secondary winding of the power combiner is minimized via
layout optimization. It reduces the ratio of direct subharmonic coupling to the PA
output, as it would have undermined the ecacy of subharmonic cancellation oth-
erwise. To make it symmetric, the secondary coil of each PA bank always connects
from the top side and connects to the adjacent channel. The coupling between the
primary and secondary coils is balanced. Note that, Additional calibration circuitry
are implemented to balance the asymmetric output trace of the transformer. The
three-way power combiner is modeled and simulated in HFSS (Fig. 3.10). It shows
less than 2 dB insertion loss over 1 GHz bandwidth (Fig. 3.11).
3.2.3 Multi-Subharmonic PM Generation
To generate the multi-SHS waveform, we use three local PM generators to cre-
ate three dierent subharmonics, Fc, 2Fc/3, and Fc/3. The same Fc signal is
distributed to three PM generators. For each PM generator shown in Fig. 3.12, it
contains a one-third divider, Fc/3 pulse generator, 2Fc/3 pulse generator, tunable
62
Figure 3.12: Multi-SHS phase generator
63
delay line and output MUX. The one-third divider rst generate the Fc/3 signals
from OUT1 to OUT6, which have 33% duty cycle with six dierent phases. The
2Fc/3 pulse generator and Fc/3 pulse generator will create the 2Fc/3 and Fc/3
subharmonics respectively. The tunable delay line delays the original PA signal to
align with these subharmonics. The layout is balanced for each building block to
reduce the phase skew between dierent channels. The output MUX selects the
desired phase and sends to each PA unit cell. The tunable delays are implemented
to calibrate the subharmonics mismatch which described in section 2.
3.3 Measurement Result
The phase-interleaved multi-SHS PA prototype is implemented in the 65-nm
bulk CMOS process with a die size of 3 mm x 2.4 mm (Fig. 3.13). The chip is
directly mounted on the PCB to minimize the bond wire inductance to the PA
supplies. The PA pre-drivers operate from 0 V to 1.2 V. The PA output drivers are
powered by either 2.4 V or 3.6 V, as described previously, i.e., 2VDD and 3VDD,
respectively. To test this digital PA, we send the 12-bit PM digital code to an
o-the-shelf evaluation board (AD9779) for generating the phase-modulated signal.
With technology scaling, additional bits could be implemented to pursue higher
linearity.
64
Figure 3.13: Chip micrograph
Figure 3.14: Measured PA output power and eciency over the frequencies
65
Figure 3.15: Measured PA drain eciency (DE) at 1.9GHz versus PA Pout
3.3.1 Continuous-Wave (CW) Measurement
We rst characterize the PA peak performance by measuring the PA peak output
power (Psat) and the peak drain eciency. The measured results under dierent
frequencies are shown in Fig. 3.14. The measured PA peak output power and
eciency are 30 dBm and 45.9%, respectively, for a center frequency of 1.9 GHz.
The measured 1 dB power bandwidth is more than 500 MHz. The eciency is more
than 40% between 1.8 GHz and 2.3 GHz. The reported drain eciency includes
all the phase generators, polar combiners, level shifters, pre-drivers, output stages,
and the transformer-based power combiner.
Fig. 3.15 and Fig. 3.16 show the measured PA back-o eciency under dif-
ferent output power levels. Compared to the simulation results, the eciency is
around 10% lower than the measurement results. There is a total of ve eciency
66
Figure 3.16: Measured PA drain eciency (DE) at 2.2GHz versus PA Pout
peaks, thanks to the pre-compiled multi-SHS with hybrid class-G operation LUT,
as described in Section III. At 1.9 GHz, the ve eciency peaks are located at 0,
-3.5, -7.0, -9.5, and -12 dB, indicating 45.9/41.3/35.3/32.2/24.2% output drain e-
ciency. The measured power eciency improves as much as twofold at -12 dB PBO
over the normalized class-B PA. At 2.2 GHz, a similar eciency roll-o curve has
been observed. The ve eciency peaks located at 0, -3.5, -7.0, -9.5, and -12 dB
indicate 42.4/36.1/30.8/27.3/20.7% output drain eciency. The measured power
eciency improves as much as 1.8X at -12 dB PBO over the normalized class-B via
the proposed architecture. Note that the measurement shows that the eciency
peaks are not exactly located at the theoretical PBO points. For example, the last
eciency peak is located at -12 dB PBO. However, the theoretical results indicate
-13 dB PBO. The reason for this oset is that the PA output saturates when the
output power is high. It makes all the PBO eciency points move closer to the
67
Figure 3.17: Measured AM-AM charateristic curve at 1.9 GHz
peak point, which leads to -12 dB in this case. The eciency roll-o curve is based
on the pre-calculated LUT, using MATLAB simulation results, which yield the best
eciency among all the other combinations.
The AM-AM and AM-PM non-linearities at 1.9 GHz are shown in Fig. 3.17 and
Fig. 3.18. They were measured by sweeping the amplitude codes. Note that, the
input code in Fig. 3.18 is
ipped compared to AM-AM characteristic curve. There
is wiggle shown in the AM-PM curve, because of the non-linearity from the dierent
PBO region of the PA operation, which matches the hybrid operation. Note that
the AM-PM non-linearity is relatively large, compared to that in other work [29].
One potential reason is that the watt-level PA cell yields larger footprint, which
leads to larger mismatch. This issue can be mitigated by the technology scaling
68
Figure 3.18: Measured AM-PM charateristic curve at 1.9 GHz
and better layout techniques. The discontinuities in AM-PM happened when the
PA switch to dierent PBO regions under the synthesized LUT, e.g. switching
from 3VDD to 2VDD due to hybrid class G operation. The AM-AM and AM-
PM characteristic curves are used to create pre-distorted input digital patterns for
the dynamic measurement. The chip has been tested under dierent voltage and
temperature corners. When the temperature increases from 25 degree to 100 degree,
the AM-PM variation is around 5 degrees. the AM-PM non-linearities with 1V,
1.2V and 1.4V supplies become 21 degrees, 25 degrees and 35 degrees respectively.
69
Figure 3.19: Measured PA output spectrum at -13 dB PBO for in-phase and phase
interleaved subharmonic operation with all the PA cells toggle at Fc/3
70
3.3.2 Phase-Interleaved Subharmonic Cancellation
To validate the proposed phase-interleaved operation, we measured the worst-
case spur under multi-SHS with a hybrid class-G operation. In this case, all the
PA cells toggle at the Fc/3 with the 2VDD supply. In Fig. 3.19, all the PA cells
rst toggle at Fc/3 with zero phase dierence. Although the matching network
provides a bandpass shape at the carrier frequency, the attenuation is not sucient
to suppress all the spurs. The output spectrum shows large unwanted tones located
at Fc/3 and 2Fc/3.
The eectiveness of performing subharmonic cancellation in the phase-
interleaved scheme is shown in Fig. 3.19. In this case, the three interleaved PA
channels toggle at Fc/3 with 120
apart. Only the Fc component is aligned in phase,
while the phases of the unwanted Fc/3 and 2Fc/3 components are theoretically
cancelled. As we can see from the output spectrum, the output power at the carrier
frequency remains the same. The worst-case spur is reduced by 37.2 dB, limited
by the matching property between the phase-interleaved paths. The dierence
between the desired tone and the largest unwanted subharmonic is around 50 dB,
which satises the mask requirement of most communication standards. Fig. 3.20
shows all the PA cells toggle at 2Fc/3. Similar to the Fc/3 case, the worst-case
spur is reduced by 40 dB, achieving 58 dB SFDR. Due to the large output power,
the EMI/EMC requirement may be violated. Antenna with frequency selectivity
can be implemented to provide additional attenuation.
71
Figure 3.20: Measured PA output spectrum at -7 dB PBO for in-phase and phase
interleaved subharmonic operation with all the PA cells toggle at 2Fc/3
3.3.3 Modulated Signal Measurement
The dynamic performance of the PA is evaluated using a 5 MHz, 52 sub-carrier,
16-QAM OFDM signal with a 7.2 dB PAPR. As noted, the PA is rst pre-distorted
by AM-AM and AM-PM LUTs. The average drain eciency achieves 31.2% under
real-time digital pre-distortion (DPD) operation (i.e., transmitting the modulated
signal under the complied LUT operation).
The PA in-band and out-of-band linearities have been characterized. It achieves
22.8 dBm average power with an EVM of -24.7 dB (Fig. 3.21). Fig. 3.22 shows the
72
Figure 3.21: Measured EVM for real-time multi-SHS and hybrid class-G operation
measured close-in PSD characteristics. The ACPR is -26.5 dBc before calibration,
and -35 dBc after calibration. The poor linearity is mainly because of the memory
eect when the PA generates large output power. The poor linearity can be im-
proved by reducing the output power level or using advanced digital pre-distortion
and memory eect calibration [30]{ [58].
Table I summarizes the measured performance compared to other state-of-the-
art CMOS PAs with dierent PBO eciency-enhancement techniques [36]-[43].
The PA prototype delivers 30 dBm peak output power with a 45.9% peak drain
eciency at 1.9 GHz. The table shows a comparison of the drain eciency at 0,
-3.5, -7.0, -9.5, and -12 dB PBO, where the PA prototype shows improved deep
PBO eciency. Compared to other CMOS watt-level power ampliers [40], [41],
73
Figure 3.22: Measured spectrum for real-time multi-SHS and hybrid class-G oper-
ation
the eciency improvement is even more signicant, where real-time multi-SHS with
hybrid class-G operation in this work achieves 31.4% average drain eciency.
3.4 Summary
This work presents a watt-level phase-interleaved multi-subharmonic switching
digital power amplier. A phase-interleaved structure is demonstrated for inherent
subharmonic cancellation. To achieve watt-level output power, stacking PA drivers
and power combining techniques are implemented. Multi-SHS is proposed to en-
hance PBO eciency. Multi-SHS can be combined with hybrid class-G to further
improve the average eciency. The PA prototype enables watt-level peak output
power with good PBO eciency compared to state-of-the-art CMOS PAs.
74
Table 3.2: Performance comparison with other CMOS PAs
75
Chapter 4
A Current Mode Subharmonic Switching Digital
Power Amplier
4.1 Eciency Enhancement of Current Mode
SHS PA Architecture
4.1.1 Eciency Enhancement Mechanism I:
Conduction Loss Saving
Fig. 4.1 shows the rst eciency enhancement mechanism due to conduction
loss. The conventional current-mode digital PA turns o a certain number of PA
cells to create dierent PBO levels. Due to the nite on-resistance (Ron) of a real
switch, the current (Im)
owing into the switch will dissipate Im2·Ron energy, i.e.
conduction loss. The key idea of a current-mode SHS PA is to reduce output power
by toggling more PA cells at a lower switching frequency. When the PA output
76
Figure 4.1: Eciency enhancement mechanism I: Conduction loss saving of the
proposed current-mode SHS PA architecture in the PBO region
77
power is between 0 and -9.5dB, every PA cell is toggled either at Fc or Fc/3. In
an embodiment targeting -6dB PBO (Fig. 1), three PA cells toggle at Fc/3 to
deliver the same current (Im) as a single PA cell toggling at Fc, i.e. only 1/3 of
Im
ows into each subharmonically toggled PA cell, dissipating just 1/9·Im2·Ron
energy. Likewise, when the output is equal to or less than -9.5dB, all of the PA cells
toggle at Fc/3 or turn o. In this deep PBO region, the conduction loss is reduced
by threefold because of the decreased overall on-resistance. Note that for the ease
of explanation, the analysis here assumes no mutual loading between dierent PA
cells. In real implementations, this loading eect would degrade eciency close
to 0dB PBO and can be mitigated by implementing a hybrid switching mode or
physically split PA cells.
4.1.2 Eciency Enhancement Mechanisms II:
Improved Impedance Matching
The second eciency enhancement mechanism of current-mode SHS PA is
achieved by providing better impedance matching at PBO (Fig. 4.2). Typically,
the PA is designed for a xed optimal load impedance for maximal eciency. Thus,
any PA output impedance variation would degrade the eciency. For conventional
digital PA, the PA output impedance increases with more PA cells being turned
o. Therefore, if the impedance matching is optimized at peak power mode, this
PA output impedance increase will lead to monotonically decreasing eciency with
78
Figure 4.2: Eciency enhancement mechanisms II:Improved impedance matching
of the proposed current mode SHS PA architecture in the PBO region
79
deeper PBO. On the other hand, the proposed current-mode SHS PA engages more
PA cells toggling in the PBO region, thereby reducing the output impedance vari-
ation. As shown in Fig. 4.2, when the output power is between 0 and -9.5dB, the
PA output impedance at Fc is roughly constant to the rst order, because all PA
cells toggle at either Fc or Fc/3. The output impedance starts to vary when the
output power is lower than -9.5dB; however, the proposed current-mode SHS PA
still toggles three times more cells compared to conventional digital PA, yielding
much less deviation for the load trajectory in deep PBO.
4.2 Circuit Implementation
4.2.1 Current Mode SHS PA Architecture
Fig. 4.4 shows the block diagram of the current-mode SHS PA implementation.
A phase-modulated (PM) signal at Fc is sent into the chip and divided by three
on the chip with proper delays to create phase-interleaved subharmonic compo-
nents. High-resolution digital-to-time converters are implemented to allow phase
calibration within 0.2ps accuracy. A high-speed multiplexer selects either the Fc
or Fc/3 PM signal for each PA cell. An on-chip look-up-table converts the 8-bit
amplitude code into a set of amplitude and phase controls signals. In addition, 50%
duty cycle subharmonic switching waveforms are used for proper operation of the
current-mode PA, as well as for minimizing the even harmonics of the switching
80
Figure 4.3: Proposed coupled-inductor-based subharmonic trap and its equivalent
circuit model
81
Figure 4.4: Simplied block diagram of the proposed current-mode SHS PA proto-
type
frequency. The layout of the power combiner aims to minimize the insertion loss
and is validated via EM simulation.
4.2.2 Coupled Inductor Based Subharmonic Trap
Fig. 4.3 shows the proposed coupled inductor based subharmonic trap as part
of the matching network to facilitate SHS operation. When PA toggling at Fc,
the subharmonic trap can be approximated as a capacitor that converts the 50-
ohm load into an optimal impedance at the PA driver output. Meanwhile, when
PA toggling at subharmonic frequency (Fc/3), the subharmonic trap appears as a
82
high impedance. As a result, it prevents unwanted subharmonic tone from feeding
through the PA output. Note that, the subharmonic trap eectively avoids the re-
verse conduction of the PA drivers, while providing extra rejection of subharmonic
component in addition to that from the phase-interleave architecture. In EM sim-
ulation, the magnetic eld of the proposed structure with dierential excitation at
Fc and Fc/3 is plotted in Fig. 4.3. They clearly show that the unwanted Fc/3 com-
ponent is trapped inside the LC tank while the Fc component propagates to the
output power combiner. Note that if any undesired common signal excites the LC
tank, e.g., the 2nd harmonic component (2Fc), the current will
ow in the opposite
direction, resulting in magnetic-
ux cancellation and thus, inherent common mode
rejection.
4.3 Measurement Result
4.3.1 Continuous-Wave (CW) Measurement
Fig. 4.5 shows measured results. The PA delivers a maximum of 27dBm peak
output power at 5.7GHz and 40.1% peak drain eciency at 5.4GHz with <1dB peak
power variation over 750MHz. Without using any additional harmonic rejection
lter, the PA output spectrum snapshot (between 1 and 18GHz) shows the low
harmonic emissions (less than -51 dBc at 2Fc and 3Fc) ascribed to the common-
mode rejection of the subharmonic trap, higher carrier frequency and 50% duty
83
Figure 4.5: Die micrograph
84
Figure 4.6: The measurement results of the CW and modulation test signal
cycle switching waveform. In the PA eciency measurement over dierent PBO
levels (at 5.4GHz), the PBO eciency peak (29.2% drain eciency) occurs at -
9dB PBO level (PBO level oset due to peak power saturation), demonstrating 2X
improvement over a measured conventional current mode digital PA.
4.3.2 Modulated Signal Measurement
The dynamic performance of the PA is rst evaluated by a 20MHz 256-QAM
single carrier signal, achieving EVM of -33.5dB and ACPR of 40.2dBc. In addition,
20/40/80MHz 64QAM ODFM signals with more than 8dB PAPR are used to eval-
uate real-time SHS operation. It achieves 28.5/28.7/28.1% average eciency with
85
Table 4.1: The comparison with prior-art PAs with similar operating frequencies
EVM of -32.5/-32.4/-30.4dB and ACPR of -41/-38.5/37.7dBc, respectively. The
performance of this PA achieves superior PBO eciency and compares favorably
with the state-of-the-art CMOS and BiCMOS PAs [42]{ [52] with similar carrier
frequency and bandwidth (Fig. 4.6). Fig. 4.7 shows a micrograph of the chip.
86
Chapter 5
A Mm-Wave Subharmonic Switching Class
E/F
2;2=3
Power Amplier with Harmonic and
Subharmonic Tuning
5.1 SHS Class E/F
2;2=3
PA Architecture
There is an increasing interest to perform sensing or communication using mm-
wave band, such as mm-wave 5G system and radar application. Those systems
typically employ an array of PAs while each PA operates at moderate output power
(Pout). In this case, the PA power eciency is crucial for better power and thermal
management. Due to the high peak-to-average power ratios of spectrum-ecient
modulations, the power back-o (PBO) eciency are increasingly important.
Class E/F switching PA is a favorable candidate at mm-wave frequency band,
as it can incorporate zero-voltage-switching (ZVS) and zero-derivative-switching
87
(ZdVS). It reduces the I/V overlap due to nite on-resistance by terminating dif-
ferent harmonics and leads to better peak eciency. Unfortunately, the eciency
roll-o still follows a typical class-B curve, resulting in relatively poor PBO e-
ciency. On the other hand, a voltage-mode subharmonic switching (SHS) digital
PA architecture has recently been demonstrated to improve PBO eciency by tog-
ging PA cells at subharmonic frequency to lower output power. To optimize both
peak and PBO eciency, we propose a SHS Class E/F
2;2=3
power amplier for mm-
wave operation that 1) allows the PA cells to toggle at much lower frequency (i.e.
subharmonic frequency) in PBO which facilitates square switching waveform and
reduces high frequency signal loss of clock routing, 2) utilizes both harmonic and
subharmonic tuning to reduce I/V overlap (i.e. power loss) for both peak and PBO
operation. At the circuit level, we propose an on-chip harmonic/subharmonic tun-
ing matching network, which can simultaneously provide optimal load impedance
of fundamental (Fc), 2nd harmonic (2Fc), subharmonic (Fc/3) and 2nd harmonic
of the subharmonic (2Fc/3) with a compact transformer footprint without any
tunable switches and elements.
Fig. 5.1 shows the proposed SHS Class E/F
2;2=3
PA architecture that combines
three key elements: SHS, subharmonic tuning technique and harmonic tuning based
on a Class E/F PA architecture. It has been proven that a conventional Class E/F
2
power amplier enhances the peak power eciency by employing an equivalent open
circuit at the second harmonic of the fundamental frequency while maintaining ZVS
88
Figure 5.1: Concept of subharmonic switching Class E/F
2;2=3
PA with fractional
harmonic tuning
89
and ZdVS condition. In this work, we further extend the harmonic tuning concept
and combine it with SHS operation. First of all, we apply SHS to the Class E/F PA
drivers, such that the drivers can toggle at a much lower frequency (only 1/3 of the
carrier frequency in this prototype) in PBO regime. To maximize power eciency,
an ideal Class E/F PA would prefer the input switching waveform close to a rail-
to-rail square wave in order to operate the transistor of PA driver in deep triode
mode rather than saturation mode, whenever it is supposed to turn on. However,
it is challenging to derive a rail-to-rail square waveform at mm-wave, due to the
device speed limitation as well as the inevitable routing parasitics. By performing
SHS, the lower toggling frequency of PA drivers helps mitigate this issue in PBO
regime. Secondly, we propose to introduce 2nd subharmonic tuning to form a Class
E/F
2=3
based output matching network in addition to ZVS and ZdVS during PBO
operation, analogous to the operation principle of Class E/F
2
. As a result, the
overall SHS Class E/F
2;2=3
PA structure not only leverages 2nd harmonic tuning
to improve the peak-power eciency, but also establishes appropriate terminations
at the fractional harmonic frequencies i.e. Fc/3 and 2Fc/3, which purposefully
improves PBO eciency at the same time.
5.2 Circuit Implementation
Fig. 5.3 shows the block diagram of the mm-wave SHS PA implementation.
A phase-modulated signal at either Fc or Fc/3 is rst sending into a wideband
90
Figure 5.2: Simplied block diagram of the proposed SHS Class E/F
2;2=3
digital PA
prototype
91
transimpedance amplier (TIA). Both shunt and series inductors are added to fur-
ther enlarge the bandwidth of the TIA and minimize the magnitude and phase
mismatch of Fc and Fc/3. A coupled inductor-based series peaking structure is
embedded in the pre-driver stage to overcome the bandwidth issue, enlarging sig-
nal swing and reducing passive area. A segmented 6-bit Class E/F PA array is
implemented on chip. A SHS operation table is synthesized on chip to convert
the 6-bit amplitude code into a set of amplitude controls signals. In addition, the
output matching network satisfy the reactance requirement at both harmonic and
subharmonic frequencies while incurring minimum insertion loss.
5.2.1 Harmonic and Subharmonic Matching Network
Fig. 5.2 shows the proposed harmonic and subharmonic tuning matching net-
work which concurrently provide desired load of harmonic and subharmonic fre-
quencies. This is a key circuit level enabler for Class E/F2/3 operation. The
matching network provides an optimal impedance at the fundamental frequency
(Fc) for achieving the maximum peak-power eciency while simultaneously creat-
ing a high impedance as seen by dierential signals at Fc/3 and a low impedance as
seen by common-mode signals at 2Fc/3 which facilitates the subharmonic switching
technique to alleviate the PBO eciency without the need for additional switches
or tunable passive elements. Additionally, all the passives including the capac-
itors in the matching network are custom-designed with the design objective of
92
Figure 5.3: Proposed concurrent fractional harmonic tuning Class E/F
2;2=3
match-
ing network
93
Figure 5.4: Chip Micrograph
minimizing insertion loss, as shown in Fig. 5.2, which nally leads to a very com-
pact transformer footprint which renders this design conducive to millimeter-wave
applications owing to its minimal parasitic.
5.3 Measurement Result
5.3.1 Continuous-Wave (CW) Measurement
Fig. 5.4 shows the chip micrograph with a core size of 0.3mm by 1 mm. The
chip is fabricated in 65nm CMOS technology. The prototype is bonded directly
94
Figure 5.5: The measurement results of CW test signal and S-parameters
to FR-4 PCB, and input/output signal is sent to/captured from the chip via a
dierential probe card.
The static performance of the prototype is rst characterized. Fig. 5.5 shows
the measured small-signal S-parameters from 16 to 32GHz.The peak S21 is 24dB
at 24GHz with 1dB power bandwidth more than 4GHz. The measured S11 is lower
than -10dB from 16GHz to 32GHz. The broadband gain
atness enables high-
speed modulations. The PA achieves 40.7% peak power added eciency (PAE)
with 18.1dBm Psat at 25.5GHz. The 1dB power bandwidth is over 4GHz. This
95
Figure 5.6: Modulation measurement results with 64 QAM 0.5GS/s and 1GS/s
OFDM Signal at 25.5GHz
prototype achieves a superior deep power-back-o eciency. The PAE at -9dB PBO
is 24% which is 1.64x over a normalized Class-B PA and 4.55x over a normalized
Class-A PA.
5.3.2 Modulated Signal Measurement
Fig. 5.5 shows modulation tests using OFDM 64-QAM signals with 0.5GS/s
and 1GS/s data rate, respectively. It achieves -26dB/-24.7dB rms EVM in its
SHS operation mode with an average eciency of 24.7%/23.4%. The proposed PA
architecture advances the linearity-eciency (peak/PBO)-modulation performance
96
Table 5.1: The comparison with state-of-the-art CMOS and SiGe PAs
envelope of mm-wave CMOS and SiGe PAs with similar frequency [53]{ [58], as
summarized in Table. 5.1.
97
Chapter 6
Conclusions
6.1 Summary
Future-generation wireless networks pose unmet challenges for conventional
communication circuits and systems. To satisfy the voracious demand for higher
data rates using scarce spectrum resources, modern wireless networks often em-
ploy sophisticated modulations such as high-order QAM. They routinely require
high-quality communication links. Consequently, energy eciency is often compro-
mised in conventional solutions. Conventional solutions also entail extraordinary
challenges when extended to future civilian and defense electronics featuring wide
bandwidth. My approaches to addressing these challenges fuse state-of-the-art
mixed-signal techniques with large-signal RF/mm-wave and holistically design ac-
tive circuits with onchip EM structures/networks by drawing on knowledge from
diverse disciplines including those pertaining to devices, EMs, and microwaves. My
research introduces new circuit topologies and system architectures that eliminate
98
the tradeos and the limits of conventional solutions. In addition, my approaches
are conducive to SoC in silicon for future-generation communication networks. In
the research of energy-ecient communication circuits and systems, my research
eliminates the tradeo between PA eciency and linearity by fusing state-of-theart
digital and analog (i.e., mixed-signal) techniques with large-signal RF. Furthermore,
162 my research demonstrates new hybrid mixed-signal PA/transmitter architec-
tures achieving signicant eciency enhancement. In the research of broadband
communication circuits and systems, my research innovates EM structures in sil-
icon to achieve RF/mm-wave passive components and networks with inherently
wide bandwidth. Mixed-signal-assisted large-signal RF operations further enable
in-eld recongurations and thus broadband operations for active circuits.
6.2 Future Work
My research has demonstrated the strength of mixed-signal-assisted large-signal
RF and mmwave circuits. The proposed SHS PA architecture can be further ex-
tended to dierent applications to enable high eciency communications. I envi-
sion that the holistic design philosophy of RF/mm-wave circuits and EM struc-
tures/networks will advance future electronics for communication and emerging
applications.
Mixed-signal-assisted RF/mm-wave architectures support low-cost and reliable
adaptive operation. In addition to energy eciency and bandwidth enhancement,
99
which have been demonstrated in my previous research, I believe they can also
enable many other signicant capabilities in future wireless systems. For example,
adaptive interference rejection can allow a wireless device to operate in a congested
and contested spectral environment. Software-dened reconguration can lead to
the design of upgradable and widely deployable military wireless infrastructures.
New mixed-signal-assisted RF/mmwave wireless communication systems can be
explored for both commercial and military applications. In parallel, intelligent
algorithms that leverage machine-learning techniques can be employed to reduce
computational cost for adaptive operations.
Future wireless communication systems are approaching higher frequencies,
which open untapped research opportunities for on-chip EM structures and net-
works, including not only passive components but also radiating elements. More-
over, designing on-chip EM structures/networks holistically with digital/analog/RF/mm-
wave circuits will enable new ways to create, manipulate, and detect the EM sig-
nals. This design methodology would enable remarkable features in future wireless
communication systems such as the integration of front-end modules in mm-wave
massive MIMO 5G systems.
100
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110
Abstract (if available)
Abstract
This thesis presents a new PA family, subharmonic switching (SHS) digital power amplifiers (PA), for enhancing power back-off (PBO) efficiency. The family of subharmonic switching power amplifiers has been developed to enhance the efficiency from RF to mm-wave frequencies in bulk CMOS. Four different architectures are proposed and demonstrated: first, a subharmonic switching digital power amplifier with hybrid class-G operation, the world's first SHS digital PA architecture, second, a watt-level multi-SHS digital power amplifier, enabling multi-SHS operation, achieving watt level output power with bulk CMOS technology while cancelling the unwanted subharmonic tones, third, a current mode SHS digital power amplifier architecture to extend the SHS PA architecture with different PA classes, and forth, a millimeter-wave (mm-wave) class E/F SHS PA with harmonic and subharmonic tuning to extend the frequency range to mm-wave bands and maintain high efficiency for future communications.
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Creator
Zhang, Aoyang
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Core Title
Silicon-based RF/mm-wave power amplifiers and transmitters for future energy efficient communication systems
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
12/08/2020
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Chen, Mike Shuo-Wei (
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), Moghaddam, Mahta (
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), Molisch, Andreas (
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), Ravichandran, Jayakanth (
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