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A study of junction effect transistors and their roles in carbon nanotube field emission cathodes in compact pulsed power applications

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A study of junction effect transistors and their roles in carbon nanotube field emission cathodes in compact pulsed power applications

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A STUDY OF JUNCTION EFFECT TRANSISTORS AND THEIR ROLES IN
CARBON NANOTUBE FIELD EMISSION CATHODES IN COMPACT PULSED
POWER APPLICATIONS

by

Qiong Shui

A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(MATERIAL SCIENCE)

May 2007

Copyright 2006 Qiong Shui
ii

Dedication

To my parents and my uncle
My husband
My sister
And my two brothers

iii

Acknowledgements

I would like to take this opportunity to thank my advisors, my colleagues, my friends
and important people in my personal life. This dissertation could not been possible
without their guidance, help and support.

Dr Gundersen: I first knew you from your “Quantum Mechanics” class. I was
wondering how you could explain so complicated things to the students with various
backgrounds in a relatively simply way. I was truly impressed by your wisdom and
your amiable face. Although you were at my father’s age, I loved your “big boy
smile”. After I joined your job, I have known more about you. Your doors are always
open for the students who want to get in. As a role model, you show us how to be a
serious, honest, persistent researcher. In front of you, we have the freedom to argue
with you about research, you never take it personally. You have a loving heart for
your students, caring about their research and their future in your every thought and
deed. When I was frustrated with my research, you translated your caring into
understanding, encouragement and action. “Two steps forward, one step backward”,
you showed me, and comforted me by giving me a hug. Your sincere caring helped

iv
me get through it. Your style, grace, kindness and generosity have touched my mind
and heart in many ways. I feel so fortunate to have such a father-like PhD advisor!

Dr. Ryan Umstattd: You became my co-advisor when we started the research on
“field emission emitters”. As a program manager in AFOSR you are pretty young,
but you are knowledgeable. It is my great joy to discuss research with you every time
since you always elaborate your thoughts rather clearly in your magnetic voice. You
teach me to face failure and see the bright side of it. Your energy and enthusiasm for
this research are contagious. I also thank you for your financial support in this
research.

I would like to acknowledge Dr. Edward Goo and Dr. Eun Sok Kim for serving on
both my qualifying exam committee and dissertation committee. I would also like to
thank Dr. Florian B. Mansfeld and Dr. Dr. Terence G. Langdon for serving on my
qualifying exam committee.

In the topic of “4H-SiC JFETs Design and Simulation”, I would like to acknowledge
Dr. Charlie Myles at Texas Tech University for his guidance, encouragement and
support. In the topic of “Si JFET-controlled CNT Field Emitter Arrays”, I would like
to acknowledge Dr. Jonathan Shaw (Naval Research lab in Washington) for his
suggestions and help on the device design as well as device testing; Dr. Alan Cassell
(NASA Ames Research Center) and Dr. Chongwu Zhou (USC) for their help in

v
multiwall carbon nanotube growth; Dr. Andras Kuthi for the pulsed mode testing; Dr.
Tom Vernier for sharing ideas about research; Dr. Dan Goebel (JPL) for his
guidance in the vacuum chamber design and plasma physics; Dr. Neville Luhmann
(UC Davis) for his financial support.

I would also like to acknowledge my friends with whom I have worked closely:
Xianyue Gu, Hao Zhang, Joe Luo, Bo Lei, Yinghua Sun, Hongyu Yu, Wei Pang,
Zhen Peng, Matthew Behrend, Steve Farrell, Meng-tse Chen, Alex Lee, Shih-Jui
(Ray) Chen … I would also like to thank my other colleagues at USC pulsed power
group and other friends. Thank you all for helping me, accompanying me and
making my life more enjoyable.

I would also like to express gratitude to our former secretary, Noreen Tamanaha, for
her help and care both in my research and my life.

This acknowledgement is incomplete without recognizing the most important people
in my personal life ― my family members.

My parents: It is you that brought me to this wonderful world. Your love for your
kids and other people teaches me that love is giving without expecting rewards. You
teach your kids how to be a man with pride and dignity. Whenever I want to give up
my work, you are always standing by me, encouraging me and teaching me to really

vi
understand the meaning of a famous Chinese proverb “Perseverance could turn a rod
of iron into a needle” (That is my father’s favorite motto). I have grown up with your
values.

I still remember when I was trying to continue my graduate study in China, my
father, you were seriously ill in hospital. You asked our family members to hide it
from me, and required them to support me no matter what would happen to you.
Every time I think of this I can’t control my feelings… Your love and higher and
higher expectations motivated me to come to America to pursue my PhD degree.
Mom and dad, I want to say: “No words in this word can express my love and
respects for you”.

My uncle (2
nd
uncle): I left you when I entered 5
th
grade in the elementary school and
lived with my parents. However there are some things that I will never forget. When
I was a little girl, you taught me how to read, how to do math, how to use abacus,
how to write diaries…You played with me, and told me lots and lots of stories. Your
love for your mother (my grandmother) deeply touched my little heart, which has
influenced me for my whole life. You always believe that I will succeed. You are
always proud of me. I am so grateful to your love.

My husband: You are full of life. Your face is always flowing with smiles. When I
feel blue, you always teach me to see the bright sides. You are my fresh breeze and

vii
bright sunshine. When I am busy with my work, you are like a babysitter: buy my
favorite food in Chinatown, drive me to school at night and pick me up from school
at night. I know I have some weaknesses. In your eyes, my weakness can become my
virtues. I feel so fortunate to find you among billions of people to share my life with.
You are the one.

My sister and two brothers: Since I am the youngest, you always take good care of
me in my life. You are always supportive in my study. Because of you, I can set my
mind on study here, since I know you are always taking good care of our parents. I
am so grateful to have you as my siblings.

Finally I would like to thank you all for making my PhD study at USC an exciting
voyage of discovery.

viii

Table of Contents

Dedication………………………………………………………………………...ii
Acknowledgements……………………………………………………………....iii
List of Tables ……………………………………………………………………x
List of Figures…………………………………………………………………....xi
Abstract………………………………………………………………………… xvi
Chapter1. Introduction…………………………………………………...………1
1.1 SiC Power Devices………………………………………………………..2
1.1.1 Bulk Growth and Epitaxy…………………………………………..5
1.1.2 Processing Technology……………………………………………..6
1.2 Field Emission……………………………………………………………10
1.2.1 Theory.……………………………………………………………..10
1.2.2 Research Status……………………………………………………14
1.3 Thesis Organization………………………………………………………18

ix
Chapter 2. 4H-SiC JFETs Design and Simulation……………………………...20
2.1 Introduction………………………………………………………………20
2.2 2-D Simulator ATLAS…………………………………………………...22
2.3 Simulation Parameters And Models……………………………………...24
2.3.1 Mobility Models…………………………………………………...24
2.3.2 Carrier Generation-Recombination Models……………………….29
2.3.3 Impact Ionization model…………………………………………...31
2.4 Device Structure and Operation………………………………………….32
2.5 Device Design and Simulation Results…………………………………..34
2.6 Device Modeling…………………………………………………………46
2.7 Conclusion………………………………………………………………..50

Chapter 3. Metal-Oxide-SiC Capacitors with Al
2
O
3
and TiO
2

As Gate Materials………………………………………………………………..52
3.1 Introduction………………………………………………………………52
3.2 Experimental Procedure………………………………………………….54
3.3 Results and Discussion…………………………………………………...56
3.3.1 Film Morphology………………………………………………….56
3.3.2 Electrical Characterization………………………………………...58
3.4 Conclusion and Future Work…………………………………………….63

Chapter 4. Si-JFET Controlled Carbon Nanotube Field Emitter
Cathode Arrays ………………………………………………………………….64
4.1 Introduction………………………………………………………………64
4.2 Design and Simulation of Si-JFETs……………………………………...66
4.2.1 Ion Implantation…………………………………………………...67
4.2.2 Simulation of JFETs by ATLAS…………………………………..79
4.3 Device Fabrication Process………………………………………………86
4.3.1 Basic Fabrication Sequence of Si JFETs…………………………..86
4.3.2 Main Fabrication Processes………………………………………..92
4.4 Results and Discussion of First Batch of Samples……………………….98
4.5 Results and Discussion of Second Batch of Samples…………………..104
4.6 Conclusion………………………………………………………………109

Chapter 5. Summary and Future Work………………………………………..110

Reference List………………………………………………………………….115

x

List of Tables

Table 1.1 Physical properties of Si, GaAs and SiC…………………………….3

Table 1.2 Recent progress of SiC power devices performance………………...9

Table 2.1 Parameters of models used for 4H-SiC VJFETs simulation……….31

Table 4.1 The ion range distribution created by 200 keV boron in Si was
computed by SRIM program. The tilt angle is 7 º…………………72

xi

List of Figures

Fig.1.1 The tetragonal bonding of a carbon atom with the four nearest
silicon neighbors. The distances of a and C-Si are approximately
3.08 Å and 1.89 Å, respectively.

5
Fig.1.2 (a) Image charge and electric field lines at a metal-dielectric
interface. (b) Distortion of the potential barrier due to image
forces with zero electric field and (c) with a constant electric
field.

12
Fig.1.3 Various shapes of field emitters and their figures of merit. (a)
Rounded whisker. (b) Sharpened pyramid. (c) Hemi-
spheroidal.(d) Pyramidal.

16
Fig.2.1 Fitted 4H-SiC low-field electron mobility ( ⊥ c-axis) as a function
of doping concentration at T=300 K.

25
Fig.2.2 Fitted 4H-SiC low-field electron mobility (// c-axis) as a function
of doping concentration at T=300 K.

26
Fig.2.3 Fitted 4H-SiC electron mobility ( ⊥ c-axis) as a function of
temperature at N
d
=1.2×10
17
cm
-3
.

27
Fig.2.4 Fitted 4H-SiC electron mobility (// c-axis) as a function of
temperature at N
d
=1.2×10
17
cm
-3
.

27
Fig.2.5 Fitted 4H-SiC electron drift velocity (// c-axis) as a function of
electric field at T=300 K

29

xii
Fig.2.6 Schematic of a half-cell of the 4H-SiC VJFET (Unit is µm). 33
Fig.2.7 Current flow lines of 4H-SiC at V
GS
=2.7V. 34
Fig.2.8 Predicted Breakdown voltage and current density dependence on
the lateral channel doping concentration shown in (a) and vertical
channel doping concentration shown in (b).

36
Fig.2.9 Predicted Breakdown voltage as a function of drift region
thickness for VJFETs. N-drift region thickness is in µm.

37
Fig.2.10 Electric field strength (y axis on the left) and impact generation
rate (y axis on the right) along the cutline. It was cut from (2.03, -
0.0112) to (2.03, 4.99) in a 40- µm drift region VJFET that was
shown in the inset.

38
Fig.2.11 Predicted I-V characteristics of the 4H-SiC VJFET at 300K.

40
Fig 2.12 Predicted Gate current density and drain current density of 4H-
SiC VJFET at V
DS
=10V. Predicted gate current density at
V
DS
=3000V was also shown.

41
Fig.2.13 Current flow lines of the 4H-SiC VJFET at V
GS
=2.9V.

44
Fig.2.14 The predicted switching performance of the 4H-SiC VJFET.

45
Fig.2.15 The predicted turn-on time of the 4H-SiC VJFET.

46
Fig.2.16 Simulated and fitted I-V characteristics of the proposed 4H-SiC
VJFET at 300K.

49
Fig.3.1 (a)The schematic structure of investigated 4H-SiC MIS capacitors.
(b) Different Patterns of MIS capacitors taken by SEM.

55
Fig.3.2 (a) An AFM image (10 µm × 10 µm) of the starting material (4H-
SiC n- epilayer).(b) An AFM image (10 µm ×10 µm) of 500 Å
Al
2
O
3
deposited on 4H-SiC n- epilayer.(c) An AFM image (10
µm ×10 µm) of 500Å Al
2
O
3
deposited on Si substrate.

57
Fig.3.3 (a) Capacitance-voltage characteristics of Metal-Al
2
O
3
(500 Å)-
SiC capacitors measured at 10kHz.(b) Capacitance-voltage characteristics
of Metal-TiO
2
(500 Å)-SiC capacitors measured at 10kHz.

59

xiii
Fig.3.4 Current-voltage characteristics of MIS capacitors. The capacitor
area is 150 µm × 150 µm and the thicknesses of Al
2
O
3
and TiO
2
are
all 500 Å.

61
Fig.4.1 Current-voltage characteristics of MIS capacitors. The capacitor
area is 150 µm × 150 µm and the thicknesses of Al
2
O
3
and TiO
2
are
all 500 Å.

66
Fig.4.2 The crystalline nature of the Si substrate.

69
Fig.4.3 The crystalline nature of the Si substrate.

70
Fig.4.4 Boron impurity distribution in Si simulated by SRIM-2003.

71
Fig.4.5 Predicted lateral projected range and lateral straggling by SRIM-
2003.

72
Fig.4.6 Profiles of 5×10
15
/cm
2
boron implants at a tilt angle of 5º-7º
along the <100> axis onto Si before post-implant annealing (the
curve in purple) and after post-implant annealing (the curve in
blue). The curve in purple and the curve in blue are derived from
Eq. (4.5) and (4.7) , respectively, using matlab.

77
Fig.4.7 Cross sectional view of our simulated Si JFET. The Si post
height=0.35 µm. The inset at the right bottom is the schematic
representation of JFET-controlled CNTs emitters.

80
Fig.4.8 (a) left: Simulated Boron distribution vs. distance in the vertical
direction from (3.5 µm, 0 µm) to (3.5 µm, 1.05 µm). (b) Right:
Simulated Boron distribution vs. distance in the lateral direction
from (4.25 µm, 0.5 µm) to (7.75 µm, 0.5 µm).

81
Fig.4.9 I
d
Vs. V
s.
at different Si post heights. The breakdown voltage of
JFET increases as Si post increases.

82
Fig.4.10 Simulated Id Vs. Vs. at Vds=0V, 2V, 5V, 7V, and 10V,
respectively.

83
Fig.4.11 Current flowlines of the Si JFET when Vgs=0V, and Vds=20V.
The arrows represent the , i. e, the electrons flow from the
source to the drain.
total
J

84

xiv
Fig.4.12 Current flowlines of the Si JFET when Vgs=-8V, and Vds=20V.
The arrows represent the , i. e, the electrons flow from the
source to the drain.
total
J

84
Fig.4.13 Simulated Id Vs. Vds at different Vgs for the Si JFET.

85
Fig.4.14 0.5 µm and 0.48 µm were defined by Shipley 1813 using standard
photolithography.

93
Fig.4.15 The thinnest finger pattern of the alignment marks has a width of
2 µm which is well defined by using a bilayer resist LOL2000 +
S1813 and lift-off.
96
Fig.4.16 The SEM images show the Si posts after ECR etching (a) without
O
2
descum (the top image), and with O
2
descum (the bottom
image).

97
Fig.4.17 CNTs were grown on 100 × 100 array emitter sites by PECVD at
700 ºC for 115 s.

99
Fig.4.18 CNTs were grown on 50 × 50 array emitter sites by PECVD at
700 ºC for 80 s.

99
Fig.4.19 Schematic diagram of the device testing setup.

100
Fig.4.20 Emission current of CNTs on a 50×50 array as a function of the
extraction gate voltage at anode voltage of 300 V. Inset
corresponds to Fowler-Nordheim (F-N) plot of the emitter array.

101
Fig.4.21 Emission current Vs. Extraction gate voltage. All the I-V plots
show a bit of hysteresis.

102
Fig.4.22 Emission current as a function of anode voltage. The extraction
gate voltage was held constant at 27 V.

102
Fig.4.23 Anode current Vs. the extraction gate voltage at different control
voltages.

103
Fig.4.24 (a)The leakage current of SiO
2
for 4×4 emitter array.(b) The
leakage current of SiO
2
for 10×10 emitter array.(c) The leakage
current of SiO
2
for 50×50 emitter array.(d) The leakage current of
SiO
2
for 100×100 emitter array.

104
Fig.4.25 I-V characteristics of p+/n junction for 50×50 array measured 106

xv
before CNT growth.

Fig.4.26 SEM images show that CNTs were barely grown on 4×4 emitter
sites of the second batch of devices.

107
Fig.4.27 SEM images show no CNTs were grown on 100×100 emitter sites
of the second batch of devices. Most of the emitter sites were
damaged by plasma arcing during CNT growth.

107
Fig.4.28 SEM images indicate that plasma arcing caused SiO
2
breakdown
during SiO
2
.

108

xvi

Abstract

This thesis is focusing on a study of junction effect transistors (JFETs) in compact
pulsed power applications. Pulsed power usually requires switches with high hold-
off voltage, high current, low forward voltage drop, and fast switching speed. 4H-
SiC, with a bandgap of 3.26 eV (The bandgap of Si is 1.12eV) and other physical
and electrical superior properties, has gained much attention in high power, high
temperature and high frequency applications. One topic of this thesis is to evaluate if
4H-SiC JFETs have a potential to replace gas phase switches to make pulsed power
system compact and portable. Some other pulsed power applications require
cathodes of providing stable, uniform, high electron-beam current. So the other topic
of this research is to evaluate if Si JFET-controlled carbon nanotube field emitter
cold cathode will provide the necessary e-beam source.

In the topic of “4H-SiC JFETs”, it focuses on the design and simulation of a novel
4H-SiC normally-off VJFET with high breakdown voltage using the 2-D simulator
ATLAS. To ensure realistic simulations, we utilized reasonable physical models and
the established parameters as the input into these models. The influence of key

xvii
design parameters were investigated which would extend pulsed power limitations.
After optimizing the key design parameters, with a 50-µm drift region, the predicted
breakdown voltage for the VJFET is above 8kV at a leakage current of 1 ×10
-5
A/cm
2
.
The specific on-state resistance is 35 m Ωּcm
2
at V
GS
= 2.7 V, and the switching
speed is several ns. The simulation results suggest that the 4H-SiC VJFET is a
potential candidate for improving switching performance in repetitive pulsed power
applications. To evaluate the 4H-SiC VJFETs in pulsed power circuits, we extracted
some circuit model parameters from the simulated I-V curves. Those parameters are
necessary for circuit simulation program such as SPICE. This method could be used
as a test bench without fabricating the devices to minimize the unnecessary cost.

As an extended research of 4H-SiC devices, Metal-Insulator-SiC (MIS) structures
were utilized to evaluate the high dielectric constant materials — TiO
2
and Al
2
O
3
, as
possible gate dielectrics for SiC devices. TiO
2
and Al
2
O
3
were chosen because of
their high dielectric constants and bandgap energies as well as the acceptance of Ti
and Al in most modern CMOS fabrication facilities. MIS devices were fabricated
and both their I-V and C-V characteristics were measured and discussed. Our
research showed that Al
2
O
3
deposited by e-beam evaporation could be considered as
a promising material among the gate insulators for high power SiC devices.

In the topic of “Si JFET-controlled carbon nanotube field emitter cathode arrays”,
stability, controllability and lifetime are the main issues waiting to be addressed

xviii

before field emitters find their wide applications. The ideas of connecting Si or metal
field emitters with external MOSFETs or built-in active devices were attempted by
other researchers, and those devices showed effectiveness in controlling and
stabilizing the emission current. We presented the design, simulation, and the
fabrication of Si JFETs monolithically integrated with CNTs field emitters. The Si
JFET was designed to control and improve the emission of carbon nanotube field
emitter arrays. Its electrical characteristics were simulated by the device simulator
ATLAS. The fabrication process was developed to be compatible with the last step
of growing multiwalled carbon nanotubes at 700 ºC. Carbon nanotubes field emitters
were grown by PECVD (Plasma Enhanced Chemical Vapor Deposition).
Preliminary field emission tests were conducted with 50 × 50 emitter arrays, with a
resultant emission current of 3 µA (~40 mA/cm
2
) at an extraction gate voltage of 50
V and an anode voltage of 300 V. Experimental data shows the linear relationship
between ln(I/V
2
) and 1/V consistent with Fowler-Nordheim electron tunneling. Some
challenging issues were also discussed.

1

Chapter 1

Introduction

This thesis describes research into junction field effect transistors with two main
objectives. One is aimed at the design and simulation of a novel SiC JFET structure
for pulsed power applications, and the other is to design, simulate and fabricate
power Si JFET integrated with carbon nanotube (CNT) field emitting structures, and
to test the device’s field emission characteristics for applications to high power
cathodes. In this chapter background information about these devices is provided.
Material issues for pulsed power switching devices are described that leads to studies
of SiC as a pulsed power junction device for switching applications. Background in
field emission devices is presented, and the choice of CNTs for this study is
explained. Finally, an integrated Si JFET – CNT cathode with controlled emission
characteristics is described, providing an introduction to an experimental research
program to design, engineer and test Si JFET-controlled CNT emitter cathode
structures for high power cathode applications.

2
1.1 SiC Power Devices
In 1906, the American inventor, Lee De Forest, developed a triode in a vacuum that
could amplify signals. However, the vacuum tube used too much power and
produced too much heat, and its amplification was unreliable. Mervin Kelly, Bell
Lab’s director of research, realized that a better solution might lie in
“semiconductors”. A team of scientists was formed to develop a semiconductor
switch to replace the problematic vacuum tube. In 1948, Bell Labs unveiled their
invention of a first Germanium point-contact transistor and a Germanium junction
transistor. In 1954, Si transistor was brought into production by Texas Instruments
(TI). In 1959, a planar technology was developed and this new process made
commercial production of ICs possible in Si substrates. Transistor devices began as
small signal devices and later developed into ICs, and then broadened their
application to power devices. Si power metal oxide semiconductor field-effect
transistors (MOSFETs) were commercially introduced in the 1970s. As power
MOSFET technology matures, a new class of power devices, MOS-controlled
thyristor [Temple, 1984] and the insulated-gate transistor (IGT/IGBT), emerged in
the 1980s [Baliga, 1987]. They exhibit the important features of a high input
impedance and a very high power handling capability for a given chip size. In 2000,
a 4.5kV-2000A flat-packaged IGBT devices were reported [Fujii, 2000].

3
Table 1.1 Physical properties of Si, GaAs and SiC [www1.1, www1.2, www1.3].

Si GaAs 6H-SiC 4H-SiC 3C-SiC

Crystal Structure

Diamond

Zinc
Blende
(Cubic)

Hexagonal

Hexagonal

Cubic
Lattice Constant
( Ǻ)
5.43 5.65 a=3.08
c=15.12
a=3.08
c=10.05
4.36

Melting Point
(°C)

1412

1240

3103

3103

3103
Bandgap
(eV)
g
E
@T=300K

1.12

1.43

3.03

3.26

2.3
Intrinsic Carrier
Concentration
i
n
(cm
-3
)

1.5×10
10

2.1×10
6

2.3×10
-6

8.2×10
-9

6.9
Breakdown
Electrical Field
c
E (V/cm)

3×10
5

4×10
5

3×10
6

3×10
6

2×10
6

Electron
Mobility
n
µ (cm
2
/V-s)
1350 8500 400 (//c axis)
85 ( ⊥c axis)
960 (//c axis)
800 ( ⊥c axis)
1000
Hole Mobility
p
µ (cm
2
/V-s)
450 400 50 100 40
Saturated
Electron Drift
Velocity
sat
V
(cm/s)

10
7

8×10
6

2×10
7

2×10
7

2×10
7

Dielectric
Constant (static)
11.8 12.9 9.7 10 9.66
Thermal
Conductivity
λ (W/cm. ºC)
@T=300K

1.5

0.55

4.9

4.9

5
Commercial
Wafers (inches)
12 6 2 4 None

Although today’ market is still dominated by Si devices, Si is generally limited to
operation at junction temperatures below 200 °C and to devices with voltage blocking
4
capabilities of less than a few kilovolts due to its intrinsic physical properties
[Johnson et al., 2001]. Theoretical analysis and experiments demonstrated that
silicon power-switching devices are reaching their theoretical limits of performance.
Other wide bandgap semiconductor materials, such as gallium arsenide, silicon
carbide and diamond, offer significant potential for improving power FET
performance. Table 1.1 lists the physical properties of those semiconductors.

During the last decade, silicon carbide (SiC) has received remarkable attention as a
promising device material for high temperature, high frequency, and high power
devices because its properties include a bandgap energy of 3.26eV (resulting in
higher hold off voltage, as compared to GaAs (1.43eV) and Si (1.12eV)), breakdown
electric field of 3MV/cm, saturation electron drift velocity of 2.2 ×10
7
cm/s and
thermal conductivity of 4.9 W/cm·K [Baliga, 1989; Cooper et al., 2002; Palmour et
al., 1997].

From the Johnson’s figures of merit in a review article [Davis et al., 1990], SiC is
only surpassed by diamond in performance. While diamond has the highest mobility,
large-area single-crystal diamond substrates are not available, and diamond has no n-
type dopants. The recent rapid developments of SiC bulk growth and epitaxy, and the
processing technology, are the building blocks of SiC power devices.

5
1.1.1 Bulk Growth and Epitaxy
Silicon carbide has many different polytypes. All polytypes have a hexagonal frame.

Fig. 1.1 The tetragonal bonding of a carbon atom with the four nearest silicon neighbors.
The distances of a and C-Si are approximately 3.08 Å and 1.89 Å, respectively [www1.4].

The carbon atom is positioned at the center of mass of the tetragonal structure
outlined by the four neighboring Si atoms so that the distance between the C atom to
each of the Si atoms (Fig. 1.1) is the same [www1.4]. The three most common
polytypes are 3C, 4H, and 6H.

In 1978, a seeded sublimation growth method was discovered to grow SiC substrates
[Tairov et al., 1978]. In 1987, a research group at North Carolina State University
(NCSU) announced the successful implementation of a seeded-growth sublimation
process [Carter et al., 1987]. Afterwards, students from the NCSU group founded a
small company, Cree Research, to produce SiC wafers commercially. The
introduction of 25 mm single crystal wafers of 6H-SiC by Cree in 1990 accelerated
SiC diameter increase from 25 mm to 100 mm in about half the time that it took in Si
6
and GaAs technologies [Spencer et al. 2002]. Micropipes have been the main
obstacle to the production of high quality SiC substrates, but recent progress is
changing this. Cree's commercial product of 4H-SiC with 76.2 mm in diameter has
less than 5 micropipes/cm
2
. Its commercial micropipe density for 100 mm 4H-SiC
wafers is 16-30 /cm
2
[www1.5], while in 1997, the average micropipe density for a
50 mm diameter 4H-SiC wafers is around 90 /cm
2
[Müller, 2000]. Polytype
inclusions (usually 3C-SiC) are a common type of crystalline defect in 4H- and 6H-
SiC epitaxial layers grown by CVD. It was found that 6H-SiC layers without 3C-SiC
inclusions can be grown by CVD on {0001}6H-SiC substrates with small tilt angles
(0.1º-0.6º). In the 4H-SiC epitaxial layers, 3C-SiC inclusions are almost eliminated if
substrates have a tilt angle of 8º [Spencer et al., 2002]. In-situ doping is
accomplished by the introduction of nitrogen (for n-type) and trimethylaluminum or
triethylaluminum (for p-type). Recently, the development of site-competition epitaxy
has extended the doping range achievable by CVD, with dopings as low as 1x10
14

cm
-3
and as high as >1x10
19
cm
-3
having been reported [www1.6].

1.1.2 Processing Technology
SiC doping is accomplished by ion implantation, since the diffusion coefficients of
aluminum and nitrogen are so low that thermal diffusion below 2000 °C is
impractical. Usually aluminum (Al) and boron (B) are for p-type, and nitrogen (N)
and phosphorus (P) are for n-type. Implanted impurities have to be activated by
annealing between 1000° and 1700°C. Sheet resistivity of nitrogen-doped 6H-SiC at
7
temperatures of 1200 C and above can be less than 1000 ohm/square [Pan et al.,
1997]. Activation of nitrogen implants in 4H-SiC requires higher anneal
temperatures. Efficient activation requires annealing at temperatures above 1650 °C
[Capano et al., 1998]

Ohmic contacts are important for power devices because high current densities will
give rise to large voltage drops across even small resistances. Contact resistivities of
the order of 10
-5
Ω cm
2
have been proven to be applicable to both n-type and p-type
4H-SiC [Johnson et al., 2001] The contacts are annealed at high temperatures,
typically between 850 - 1050 C, in argon or vacuum. Ni is the most widely used
metal for n-type SiC because of its low contact resistivity and high reproducibility as
well as its stability at high temperatures. Ti/Au is usually used for p-type 4H-SiC.
Some research has been on Schottky contacts. Experimental results show that Ni
provides the best overall compromise between forward and reverse characteristics
for n-type 4H-SiC. [Cooper et al., 2002].

In SiC power devices, sometimes it is necessary to etch SiC to form deep trenches
for mesa etch terminated diodes and U-trench MOSFETs. Owing to the high
chemical stability of SiC, wet etching is impossible. Dry etching, such as RIE
(Reactive ion etching), ICP (Inductively Coupled Plasma Etching), ECR (Electron
Cyclotron Resonance) in fluorinated gases, were under active investigation [Cao et
al., 1998; Wolf et al., 1996; Xie et al., 1995]. ICP is effective to form deep trenches.
8
It was found that the etch rate increases with ICP power and substrate dc bias, and an
etch rate exceeding 200 nm/min can be obtained at about100 V substrate dc bias. The
etch rate is as high as 20 nm/min, even when there is no substrate bias. It provides
anisotropic etch profiles and clean smooth surfaces.

SiC, like Si, is a material, which can be oxidized to form a stable surface layer of
SiO
2
. Although the surface density in the SiO
2
-SiC interface is higher than that in the
SiO
2
-Si interface, recent work has shown progress. Interface state densities of 10
11
/
cm
-2
eV
-1
on n-type SiC and of 10
11
cm
-2
eV
-1
range on p-type SiC were reported
[Shenoy et al., 1995; Das et al., 1998]. Other research shows that post-oxidation high
temperature annealing in nitric oxides helps reduce the interface trap density by one
order of magnitude [Chung et al., 2001]. The dielectric constant of SiO
2
is ~3.9
whereas it is ~10 for SiC. To make full use of the benefit of ~ 2.5 MV/cm
breakdown field of SiC, the oxide must withstand 6.25 MV/cm. Other researches
were attempting to utilize higher dielectric constant materials to replace SiO
2
as gate
insulators. Our study of Al
2
O
3
and TiO
2
grown by e-beam evaporation as possible
gate materials is part of it. The background of research on gate insulators was
covered in detail in the “Introduction” of Chapter 3.

The great strides made in SiC technology, from material growth and epitaxy to
fabrication techniques, facilitate the performances of SiC power devices. It is
9
necessary to take a look at the range and performance of the recently fabricated
devices shown in Table 1.2.

Table 1.2 Recent Progress of SiC Power Devices Performance.

SiC
Power
Devices
Performance Reference
4.9 kV Schottky Diode (4H), R
sp,on
=43 m Ω-
cm
2

[McGlothlin et al.,1999]
8.6 kV PiN Diode (100 µm drift region) [Singh et al., 2000]
Diode
19 kV PiN Diode (200 µm drift region with
8*10
-13
cm
-3
), 6.5 V @ 100 A/cm
2

[Sugawara et al., 2001]
2.6 kV LDMOS (Lateral Double-implanted
MOS)
[Spitz et al., 1998]
1.4 kV UMOS (10 µm drift region),
R
sp,on
=15.7 m Ω-cm
2

[Tan et al., 1998]
MOSFET
6.1 kV SIAFET (Static Induction-injected
accumulated FET), R
sp,on
=732 m Ω-cm
2

[Takayama et al., 2001]
600-1000V, normally-on, R
sp,on
=14-40 m Ω-
cm
2

[Mitlehner et al., 1999]
1.8 kV, R
sp,on
=24 m Ω-cm
2
[Fridrichs et al., 2000]

JFET
5.5 kV, normally-off, R
sp,on
=218 m Ω-cm
2
[Asano et al., 2001]
1.8 kV BJT (4H), R
sp,on
=7.0 m Ω-cm
2
[Ryu et al., 2001(a)]
BJT
3.2 kV BJT (4H), R
sp,on
=78 m Ω-cm
2

[www1.7]
1 kV blocking voltage, forward voltage
drop is 3.35 V @ 500 A/cm
2
.
[Seshadri et al., 1998]

Thyristor 3.1 kV forward-blocking capability GTO
thyristors (4H), forward current of 12 A
(300 A/cm
2
) with a voltage drop of 4.97 V,
power rating is 62 kW
[Ryu et a., 2001 (b)]

Based on the previous achievements and pulsed power requirements, SiC JFET was
chosen as our study object. Our detailed motivations would be covered in the
“Introduction” of Chapter 2.

10
1.2 Field Emission
1.2.1 Theory
The transistor is probably the most important invention of the 20
th
century. It has
gradually replaced thermionic devices (vacuum tubes) in many applications. In
recent years, there has been a growing interest in vacuum tubes, in the form of cold
cathode field emitters. The transistor’s mission for our study is not to replace cold
cathode field emitters, it will work with them shoulder to shoulder in hopes of
improving field emission.

Field emission has wide applications. It can be used in flat-panel display, microwave
tubes, pulsed power systems, X-ray sources, and E-beam sources for SEM and E-
beam lithography. In the field of vacuum electronics, field emission is seen as an
alternative to thermionic emission. Thermionic emission occurs when electrons are
emitted due to the elevated temperature (> 1000 ºC) of the emitting metal or metal
oxide surface. The emission current density is governed by the Richardson-
Dushmann relation:
) / )(
10 16 . 1
exp( 120
) / )(
10 16 . 1
exp( 10 2 . 1 ) exp(
4
2
4
2
2
4
2 6 2
3
2
cm A
T
T J
m A
T
T
T k
e
T
h
ek m
J
B
B e
Φ × −
= ⇒
Φ × −
× =
Φ −
=
π

where T is temperature, m is free electron mass, k is the Boltzmann constant, and
is the work function of the cathode material. Efficient thermionic emission
e B
Φ
11
requires a high temperature, which has a strict demand for high temperature metals
with relatively low work function. Extra circuit for heating is also needed. Field
emission is much more attractive. It promises more robust and compact devices,
much higher efficiency, less scattering of emitted electrons, and faster turn-on times.
Besides that, electrons can be extracted at room temperature and the output current is
voltage controllable. “Field emission” is a phenomenon of electrons quantum-
mechanically tunneling through the barrier, where a high electric field between the
anode and the cathode causes a deformation and the thinning of the potential barrier
at the surface of a metal or semiconductor. Fig. 1.2 helps us understand the theory of
field emission from a metal. An electron in vacuum at a distance x from the metal
will create an electric field. The field lines must be perpendicular to the metal surface
and will be the same as if an image charge, + , is located at the same distance from
the metal surface, but inside the metal [Neamen, 2002, 3
e
rd
edition]. The image
potential experienced by the electron without external electrical field as it escapes
from the surface is
x
e
4
2
− where x is the distance from the metal surface. It was
shown in a solid curve in Fig. 1.2 (b). When an electric field E is applied to the
metal surface, the potential energy the electron experienced is modified and can be
written as
x
e
4
2
− -eEx , where eEx is the potential due to the external electric field
used to attract electrons over to the collector. The total potential energy of the
12
electrons (shown by the solid line in Fig.1.2 (c)) is [Nordheim, 1928; Fowler, 1928;
Guth, 1941]:

Fig. 1.2. (a) Image charge and electric field lines at a metal-dielectric interface. (b)
Distortion of the potential barrier due to image forces with zero electric field and (c) with a
constant electric field [Neamen, 2002, 3
rd
edition].

0 tan = = t Cons U ( 0 ≤ x )
W U = eEx
x
e
− −
4
2
( ) 0 > x
where W is the given energy for electrons incident from the left on a surface. The top
of the potential energy is rounded off by the image effect. The potential barrier is
13
lowered by combined effects of the image force and the applied electric field. The
potential lowering (known as Schottky effect) can be calculated by:
s
eE
πε
φ
4
= ∆
The lowering and the thinning of the potential barrier allow electrons to quantum-
mechanically tunnel through the barrier. The emission current I is given by:
I=
∫
∞
0
) ( ) ( dW W D W N
Where is the number of electrons with energy W normal to the emitting
surface. Its value is given by the density of allowed quantum states times the
probability that a state is occupied by an electron. is the transmission
coefficient for electrons incident on the potential barrier at the metal surface with
energy W normal to the surface. Fowler and Nordheim predicted the emission of
electrons from a metal-vacuum in the presence of high electric fields as [Fowler et al.,
1928; Spindt, 1976]:
) (W N
) (W D







 Φ
− = ) ( exp
) (
2 / 3
2
2
y
E
B
y t
AE
J υ
φ
A/cm
2

where
A =1.54×10
-6
, B =6.87×10
7
, =3.79×10 y
-4
Φ /
2
1
E ,
) (
2
y t =1.1,
2
95 . 0 ) ( y y − = ν
α
I
J = α : the emitting area
14
V E β = β : Local field conversion factor at the emitting surface
()












Φ
× −
Φ
−
Φ
= = ⇒
−
V
V
B
V A
J I
β
β
β α
α
2
4
2 / 3 2 2
10 79 . 3 95 . 0 exp
1 . 1








 Φ
− Φ ×
Φ
=
− −
V
B
B
V A
β
β α
2 / 3
2 / 1 7
2 2
95 . 0
10 44 . 1 exp
1 . 1

( )








⋅
Φ
−








Φ
×
Φ
=
−
V
B
V
B V A 1 95 . 0
exp
10 44 . 1
exp
1 . 1
2 / 3
2
2 / 1
7 2 2
β
β α

Assume a =
( )








Φ
×
Φ
=
−
2 / 1
7 2 2
10 44 . 1
exp
1 . 1
B V A β α
, = b
β
2 / 3
95 . 0 Φ B

) exp(
2
V
b
aV I − = ⇒
According to the Fowler-Nordheim model, Fowler-Nordheim plot, 





2
V
I
log vs
V
1
,
produces a straight line, although sometimes experimental F-N plots deviate from
straight lines due to nanoscale tips, space-charge effects, and adsorbates.

1.2.2 Research Status
Since Fowler-Nordheim theory was introduced in 1928, some experimental studies
were carried out by many other researchers with attempts to confirm and modify the
theory. In 1970s Spindt and his co-workers produced arrays of microfabricated
conductive Mo tips, integrated with extraction gates [Spindt, 1968]. The Mo emitter
arrays were patterned by E-beam microlithography and were capable of producing
high current density (10 A/cm
2
). The invention of Spindt microtip cold cathodes,
15
along with the mature fabrication technology developed for solid state devices, led to
interest in the pursuit of field emission electron beam sources for flat panel displays,
and vacuum microelectronics devices. Si is a promising material from which FEA
could be made since advanced integrated circuit manufacturing technologies can be
utilized. The first ungated Si field emitter arrays (FEAs) fabricated by microetching
techniques were demonstrated by Tomas et al. in 1972 [Thomas et al., 1972]. Stable
emission was obtained at anode voltages in the 1- to 8-kV range although emission
patterns showed local regional uniformity. Using standard silicon microelectronics
processing, a new vacuum-solid state planar field-effect transistor based on field
emitter arrays were developed by Gray et al. in 1986 [Gray et al., 1986].
Subsequently, Si emitter tips could be precisely controlled by thermal oxidation
technique and atomically sharp microtips became possible. For most metals and Si
emitters electrons must overcome a certain potential barrier to be emitted from the
surface. In diamond, this potential barrier is very small since it has negative electron
affinity (NEA). Besides that, it has high thermal conductivity, large intrinsic
breakdown filed and chemical inertness. The unique properties of diamond have
attracted some growing interest among some researchers in making diamond FEAs.
Even if the surface of a diamond film has a NEA, no stable, continuous and efficient
low-field emission may be observed, since the diamond film may not have enough
conduction electrons to be supplied to the emitting surface [Xu et al., 2005]. This is
ascribed to diamond’s high resistivity, which makes it hard to dope donor-type
dopants into the material. Diamond field emitters still have a long way to go.
16

Fig. 1.3 Various shapes of field emitters and their figures of merit. (a) Rounded whisker. (b)
Sharpened pyramid. (c) Hemi-spheroidal.(d) Pyramidal.

As early as in 1991, Utsumi compared different geometrical shapes of field emitters
in terms of “Figure of Merit”[Utsumi, 1991]. He concluded that the rounded whisker
shape is the closest to the “idea” filed emitter [Fig.1.3]. Since the discovery of
carbon nanotubes (CNTs) in the same year, much attention has been paid to explore
use of this whisker-like 1-D nanomaterials in field emission applications. CNTs are
stable at high temperatures, have high aspect ratio, and can have high electrical and
thermal conductivity ( ρ=10
-4
· Ω•cm, λ=~ 2000 W/m•K at room temperature).
Because of its nearly one-dimensional electronic structure, they exhibit ballistic
electron transport (i.e., without scattering) in metallic single-walled CNTs (SWCNTs)
and multiwalled CNTs (MWCNTs). This enables them to carry high currents with
essentially no heating [Baughman et al., 2002]. Single wall CNTs can be either
semiconducting or metallic-like depending on their chirality. Multiwall CNTs are
non-semiconducting (i.e., semi-metallic like graphite) in nature. Vertically-aligned
CNTs for field emission can be grown by PECVD (plasma enhanced chemical vapor
deposition) at ~ 700 ºC with acetylene and ammonia gases. The CNTs density is
17
controlled by the catalyst layer thickness [Rupesinghe et al., 2003]. Ni, Co, Mo and
Fe are the commonly used catalyst materials. A thin metal layer or SiO
2
is
sandwiched between the substrate and the catalyst layer to act as a barrier layer,
preventing back-diffusion. To minimize the electrical field shielding, it is necessary
to have individual vertically aligned tubes spaced apart by twice their height [Milne
et al., 2004]. Some groups [Merkulov et al., 2001; Teo et al., 2002;] produced
controlled arrays of CNTs using the e-beam lithography to pattern the catalyst dots.
Recently, the growth of vertically aligned CNTs at temperatures as low as 120 ºC
was reported [Hofmann, 2003]. It could allow direct growth of CNTs onto low-
temperature substrates and facilitate the integration in nanoelectronic devices.

Emission uniformity, reliability and controllability are the main issues to be
overcome before FEAs could find wide applications. To improve the stability and
efficiency of silicon emitters, coatings, including diamond-like-carbon, refractory
metals, silicides, silicon carbide, palladium, have been tried. Some researchers have
tried to connect Si FEAs to a constant current source, such as TFT, MOSFET and
JFET [Yokoo et al., 1994; Matsukawa et al., 1999; Shimawaki et al., 2002].
Experimental results did show that those transistors enhanced the stability and
uniformity of Si emitters. Although CNT has a bright future in field emission
applications, it faces the same difficulties. Another issue is when the emission
current reaches 0.2mA, catastrophic failure would happen on CNTs. [Cheng et al.,
2003]. As a possible solution, Si JFET, monolithically integrated with CNTs, was
18
proposed in our work to supplement electrons emitted from CNTs. The voltage on
the p+/n junction of Si JFETs controls the channel width. By adjusting the applied
voltage on the control gate (p+ region), we can precisely control the electron supply
to the CNTs to prevent disruptively excessive emission current.

1.3 Organization of the Thesis
Chapter 1 provides the background for “SiC JFET” and “Si JFET-controlled CNTs
field emission” research that is the subject of this thesis. The first chapter begins with
the background of Si transistors, and describes the background for a new promising
material, SiC, in pulsed power application. Then an overview of choosing SiC as
potential pulsed power semiconductor material, from bulk material growth and
epitaxy, fabrication techniques, to the recent achievements of some SiC power
devices, was presented. As an extension of this research, the background of studying
TiO
2
and Al
2
O
3
as gate insulators for SiC capacitors was also explained. To better
understand Si JFET-controlled CNTs field emission, Fowler-Nordheim theory was
explained in detail. This was followed by a historic perspective of the development
of field emitters, in terms of emitter materials, and active devices for controlling the
field emission.

In Chapter 2, a two-dimensional device simulator ATLAS was used to simulate a
novel 4H-SiC JFET structure. After introducing the proper physical models and
19
model parameters into ATLAS, the device performance dependence on key design
parameters was simulated and discussed in detail. Circuit parameters, for SPICE
implementation, were extracted and optimized based on simulation results.

Chapter 3 started with the motivations of choosing TiO
2
and Al
2
O
3
as gate insulator
materials for MIS capacitors. The devices were fabricated and their I-V and C-V
characteristics were tested. We concluded that Al
2
O
3
was a potential gate insulator
material for power semiconductor devices.

Chapter 4 first outlined the research status of field emitters, and brought up the
existing issues of their wide application in the near future. Then active devices, Si
JFETs, were proposed in our work to be monolithically integrated with CNTs emitter
cathodes. The design issues along with JFET simulation by ATLAS were analyzed
and discussed. The most time-consuming and difficult part of this project is the
device fabrication. A lot of efforts were made in explaining the process flow,
associated with SEM (Scanning Electron Microscopy) images. Finally field emission
performance of those devices were tested and analyzed.

Chapter 5 summarized our work and suggested future directions.

20

Chapter 2

4H-SiC JFETs Design and Simulation

2.1 Introduction
Pulsed power applications often require switches with hold-off voltage considerably
in excess of 10 kV, peak currents of kA to many kA, and turn-on in 10's of
nanoseconds, for varying pulse lengths. Gas phase switches, such as the pseudospark,
spark gap, and thyratrons are widely used in the technical pulsed power community,
and semiconductor switches are under development for these applications
[Gundersen, 1991; Schamiloglu et al., 2004], including commercial Si MOSFETs
and IGBTs. Si thyristors are now used for applications requiring 4-6 kV hold off
voltage and peak current as high as several kA. However, the switching time, or
diffusion technology, limits applications to pulses longer than several microseconds,
and series connections are normally required to achieve hold off voltage in excess of
a few kV.

21
4H-SiC is under consideration because its properties include a bandgap energy of
3.26eV (resulting in higher hold off voltage, as compared to GaAs (1.43eV) and Si
(1.12eV)), breakdown electric field of 3MV/cm, saturation velocity of 2.2 ×10
7
cm/s
and thermal conductivity of 4.9 W/cm·K [Baliga, 1989; Cooper et al., 2002; Palmour
et al., 1997]. Recently, significant progress in SiC power devices has been reported
by Tan et al. [Tan et al., 1998] and Khan et al. [Khan et al., 2002] including the
fabrication of UMOSFETs with breakdown voltages of 1400V (10µm drift region)
and 5050V (100µm drift region) respectively. Mitlehner et al. have fabricated
normally-on VJFETs with blocking voltages between 600 and 1000V with specific
on-resistance R
on, sp
in the range of 18 to 40 m Ωּcm
2
in 1999 [Mitlehner et al., 1999].
Mihaila et al. have reported a theoretical and numerical investigation of SiC JFETs
and MOSFETs at 6.5kV[Mihaila et al., 1999]. Asano et al. have reported the
fabrication of 5.5kV low R
on,sp
4H-SiC SEJFETs with a 50um drift layer [Asano et
al., 2001; Takayama et al., 2001, Sugawara et al., 2000]. Zhao et al. have presented a
VJFET with a blocking voltage of 1644V (10µm drift region) with specific on-
resistance of 4.8 m Ωּcm
2
[Zhao et al., 2003]

With the rapid development of SiC devices in recent years, SiC devices are gaining
more and more attention in pulsed power community. The conflicting simultaneous
requirements of high hold-off voltage, high current density, low forward voltage
drop and fast switching speed limit the current Si power devices application in the
pulsed power technology. In order to analyze the capability of SiC devices in pulsed
22
power, an advanced 4H-SiC VJFET structure representing the current trend of the
enhancement mode (normally-off) VJFET [Asano et al., 2001; Zhao et al., 2003] is
proposed and tested numerically using the 2-D simulator ATLAS. 4H-SiC VJFETs
are of interest. On the one hand the electron mobility in 4H-SiC is about 10 times
higher than that in 6H-SiC parallel to c-axis (
/ / e
µ ). On the other hand SiC VJFETs
avoid several current issues with SiC MOSFETs, such as oxide breakdown, oxide
long-term reliability, and low channel electron mobility [Cooper et al., 2002]. The
predicted high hold-off voltage (8kV), low specific on-state resistance, and fast
switching time of the VJFET show that 4H-SiC VJFETs have the potential to extend
the pulsed power switching limitations. Our analysis focuses on (a) how the
electrical characteristics of the devices change with the design parameters, (b)
optimizing the structure for pulsed power applications, and (c) modeling the VJFET
for integrated circuit simulation where high voltage, high current, and fast switching
speeds are required. (c) is important to our other research where all necessary SPICE
parameters of 4H-SiC VJFETs are to be loaded into a circuit model and the VJFETs
are to be put into a typical transmission line pulsed power circuit.

2.2 2-D Simulator ATLAS
Numerical simulation is a powerful tool in predicting the performance of
semiconductor devices. Realistic simulations require the implementation of
reasonable physical models and the use of established parameters as the input into
23
these models. Our study used the 2-D simulator ATLAS (from Silvaco International)
to simulate the VJFETs of interest. This package uses Poisson’s Equation along with
the continuity and drift-diffusion equations to simulate the device.
• Poisson’s equation: Relates variations in electrostatic potential to the space
charge density.
E
x
V ⋅ −∇ = − = ∇
ε
ρ ) (
2
(3-D)
dx
dE
dx
V d
− = − =
ε
ρ
2
2
(1-D)
• Carrier continuity equations: Describe the way that the electron and hole
densities evolve as a result of transport processes, generation processes, and
recombination processes.
n n
R G
q t
n
− + ⋅ ∇ =
∂
∂
n
J
1

p p
R G
q t
p
− + ⋅ ∇ =
∂
∂
p
J
1

• Drift-diffusion equations: describes the electron drift and diffusion currents, and
hole drift and diffusion currents.
n qD qn J
n n n
∇ + =
n
E µ (3-D)
p qD qn J
p p p
∇ − =
p
E µ (3-D)
dx
dn
qD qn J
n n n
+ =
x
E µ (1-D)
24
dx
dp
qD qn J
p p p
− =
x
E µ (1-D)
where V is the electrostatic potential, ε is the dielectric permittivity, ρ is the space
charge density, q is the electronic charge, n represents the number of electrons and
holes, and are vectors of the electron and hole current density, G and G are
the generation rates for electrons and holes, R and are the recombination rates
for electrons and holes,
n
J
p
J
n p
n p
R
n
µ and
p
µ are the mobilities for electrons and holes, D
and are the diffusion coefficient for electrons and holes, respectively.
n
p
D

2.3 Simulation Parameters And Models
The equations and physical models used are identical to those used in Si simulations.
As the input, the parameters for 4H-SiC VJFETs were extracted from the recent
literature. The most important physical models [ATLAS User’s Manual, 2002] for
4H-SiC devices employed in the simulations are as follows:
2.3.1 Mobility Models

1. The Analytic Low Field Mobility Model

The Caughey−Thomas approximation was used to model the doping- and
temperature-dependent low field mobilities. In this approximation, the following
analytic functions are used for the electron and hole mobilities:
25
n
n
n n
n
crit
n
n n
n n
N
N
K
T
K
T
K
T
K
T
σ
γ
α β
α
µ µ
µ µ














+






− 





+ 





=
300
1
300 300
300
min max
min
0
Eq.(2.1)
p
p
p p
p
crit
p
p p
p p
N
N
K
T
K
T
K
T
K
T
σ
γ
α β
α
µ µ
µ µ














+






− 





+ 





=
300
1
300 300
300
min max
min
0
Eq.(2.2)

where
0 n
µ and
0 p
µ are the low field electron and hole mobilities, respectively. N is
the total doping concentration. T is the temperature in degrees Kelvin. The others
are fitting parameters.

Fig. 2.1 The fitted 4H-SiC low-field electron mobility (⊥ c-axis) as a function of doping
concentration at T=300 K.

26

Fig. 2.2 The fitted 4H-SiC low-field electron mobility (// c-axis) as a function of doping
concentration at T=300 K.

The current flow in our simulated VJFETs is primarily oriented along c-axis, so the
fitting parameters in the above models listed in Table 2.1 are for electron and hole
mobilities parallel to the c-axis. For devices fabricated on the Si (0001)-face of n-
type 4H-SiC substrate, the ratio of electron mobility perpendicular to the c-axis to
the electron mobility parallel to the c-axis is ~0.8, that is,
⊥ e
µ /
// e
µ =0.8 [Schadt et al.,
1994; Roschke et al., 2001]]. The commonly measured data are for
⊥ e
µ . Therefore,
an attempt was made to fit the experimental data for
⊥ e
µ shown in Fig. 2.1 and Fig.
2.3 [Roschke et al., 2001; Schaffer et al., 1994; Kinoshita et al., 1998; Joshi et al.,
1995; Khan et al., 2000] and
// e
µ was calculated to be 1.25
⊥ e
µ shown in Fig. 2.2 and
27

Fig. 2.3 The fitted 4H-SiC electron mobility (⊥ c-axis) as a function of temperature at
N
d
=1.2×10
17
cm
-3
.

Fig. 2.4 The fitted 4H-SiC electron mobility (// c-axis) as a function of temperature at
N
d
=1.2×10
17
cm
-3
.

28
Fig. 2.4. The parameters of the hole mobility at low electric field were similarly
obtained.

2. High Field Mobility Model
At low electric field, the carrier drift velocity almost linearly increases with the
applied electric field according to E µ υ = . At high electric fields, the drift velocity
deviates substantially from linearity. The electron drift velocity for 4H-SiC saturates
at approximately 2-3×10
7
cm/s at an electric field of approximately 5×10
5
V/cm
[Roschke et al., 2001; Khan et al., 2000; Nilsson et al., 1999]. An expression used
for modeling a smooth transition between low-field and high field behavior is
[ATLAS user’s manual, 2002].
()
n
satn
n
n
V
E
E
β
µ
µ
1
0
1
1






















+
=
,
()
p
satp
p
p
V
E
E
β
µ
µ
1
0
1
1






















+
=
Eq.(2.3)

where
0 n
µ and
0 p
µ are the low field electron and hole mobilities, respectively. The
values of the electron and hole saturation velocities V , , and the other
parameters used in our simulations were extracted shown in Fig. 2.5 and were listed
in Table 2.1.
satn satp
V
29

Fig. 2.5 The fitted 4H-SiC electron drift velocity (// c-axis) as a function of electric field at
T=300 K

2.3.2 Carrier Generation-Recombination Models
1. Shockley-Read-Hall (SRH) Recombination
Since SiC is not a perfect single crystal material, defects will create discrete
electronic energy states (deep levels or traps) within the forbidden-energy gap.
Shockley-Read-Hall theory assumes that: (1) the deep levels capture electrons from
the conduction band or holes from the valence band; (2) The electrons or holes
occupying the traps are emitted into the valence band or conduction band, thus
completing the recombination process. Since few papers have dealt with SRH
recombination in SiC, it is assumed that a single trap located in the intrinsic Fermi
level exists that corresponds to the most efficient recombination center [ATLAS
30
user’s manual, 2002]. This trap is incorporated into the SRH model, and the SRH
recombination rate is then













 −
+ +














+
−
=
kT
E
n p
kT
E
n n
n pn
R
trap
ie n
trap
ie p
ie
SRH
exp exp
0 0
2
τ τ
Eq.(2.4)

where is the difference between the trap energy level and the intrinsic Fermi
level, is the intrinsic carrier concentration, the
trap
E
ie
n
0 p
τ and
0 n
τ are the electron and
hole lifetimes. The values for these are listed in Table 2.1.

2. Auger Recombination
Auger recombination is a process involving three particles. An electron and a hole
recombine in a band-to-band transition, and this process transfers energy to another
electron or hole. The rate for the Auger process is commonly modeled by:
( ) ( )
2 2 2 2
ie p ie n Auger
pn np C nn pn C R − + − = Eq.(2.5)
The values of C and we have used are listed in Table 2.1. To our knowledge,
there have been few studies of Auger recombination in 4H-SiC, so in our simulations
we utilize the values for these parameters found in 6H-SiC[Lades, 2000].
n p
C

31
2.3.3 Impact ionization model
At high electric fields, the electrons and holes moving across the space charge region
acquire sufficient energy to create additional electron-hole pairs when collisions
occur with the atoms in the depletion region. The newly created electrons and holes

Table 2.1 Parameters of models used for 4H-SiC VJFETs simulation.

Electron
mobility models

Value SRH recombination
min
n
µ
(cm
2
/V.s) 20
0 n
τ
(s) 8×10
-8

min
p
µ
(cm
2
/V.s) 1
0 p
τ
(s) 2×10
-8

max
n
µ
(cm
2
/V.s) 1100
trap
E
(eV) 0
max
p
µ
(cm
2
/V.s) 140 Auger recombination
n
α

(cm
2
/V.s)
-0.5
n
C
(cm
6
/s) 3×10
-29

p
α

(cm
2
/V.s)
-0.5
p
C
(cm
6
/s) 3×10
-29

n
β

(cm
2
/V.s)
-2.4 Impact ionization
p
β

(cm
2
/V.s)
-2.4

n
γ

0
n
a
=7.628×10
6
(T/300)
2
+1.506×10
6
(T/300)
-4.184×10
6
(cm
-1
)
4.95×10
6

p
γ

0

p
a
=6.3×10
6
-1.07×10
4
T (cm
-1
) 3.25×10
6

n
σ

0.69
n
b
(V/cm) 2.58×10
7

p
σ

0.69
p
b
(V/cm) 1.71×10
7

crit
n
N
(cm
-3
) 2×10
17
Other material parameters
crit
p
N
(cm
-3
) 1×10
17

Dielectric constant,
r
ε
9.76
Vsatn
(cm/s) 2.75×10
7
Band-gap energy at 300K (eV) 3.26
Vsatp
(cm/s) 4×10
6
Thermal conductivity (W/cm. K) 4.9
n
β

0.98 E
a
(eV) [Zhao et al., 2003; Mihaila et al.,
2003]
0.191
p
β

0.95 E
d
(eV) [Zhao et al., 2003; Mihaila et 0.066

32
move in the opposite direction, add to the existing reverse-bias current, and also
ionize other atoms. If the generation of these electron-hole pairs is sufficiently high,
the process will lead to avalanche breakdown [ATLAS user’s manual, 2002]. The
carrier generation rate in this process is described by the equation:
p p n n
J J G α α + = Eq.(2.6)
Here
n
α and
p
α
are the impact ionization coefficients for electrons and holes, and J
and are electron and hole current densities. The ionization coefficients can be
described by Selberherr model [ATLAS user’s manual, 2002; Selberherr, 1984;
Raghunathan et al., 1997]:
n
Jp














=
n
n
n n
E
b
a
β
α exp
,
















=
p
p
p p
E
b
a
β
α exp
, Eq.(2.7)
Where E is the electric field in the direction of current flow, and a , , ,
,
n p
a
n
b
p
b n β and p β are fitting parameters. The values of these fitting parameters are listed in
Table 2.1.

2.4 Device Structure and Operation
Fig. 2.6 shows a schematic cross section of the half-cell structure of an enhancement
(normally-off) 4H-SiC VJFET that we have proposed for our simulation. From Fig.
2.6, it can be seen that an n- epilayer (lateral channel) is sandwiched between the
source and the gate. A vertical channel is on the right side of the gate. The
thicknesses and widths of both lateral and vertical channels are chosen so that, at
33
zero gate bias, the depletion regions are extended into the vertical and lateral
channels by the p+/n- junction built-in potentials [Asano et al, 2001; Takayama et al.,
2001; Sugawara et al., 2000]. The source is connected to the ground. By forward
biasing the gate, the depletion regions shrink and currents flow from the drain to the
source when a positive voltage is applied on the drain. This is how this normally-off
VJFET operates. The flowlines in Fig. 2.7 show that when the VJFET is turned on,
the current flows from the drain to the source through the channels at V =2.7V.
GS

Fig. 2.6 Schematic of a half-cell of the 4H-SiC VJFET (Unit is µm)

34

Fig. 2.7 Current flow lines of 4H-SiC at V
GS
=2.7V.

2.5 Device Design and Simulation Results
In the VJFET design process, a high blocking voltage V
break
is the primary goal we
want to achieve for pulsed power technology. At the same time, low on-state
resistance, and fast switching speed were also simultaneously considered. The
temperature in all simulations was assumed to be 300 K since few data for high
temperature are available.

Both the lateral channel and the vertical channel play an important role in
determining the voltage that the device can support. Where not otherwise specified,
the n- drift region in these simulations has a doping concentration of 5×10
14
cm
-3
and
a thickness of 50µm. The simulation results show that as the lateral channel
35
thickness (5×10
14
cm
-3
) increases from 0.2 µm to 0.6 µm, V
break
varies from 5 kV to
8.5 kV. Taking into account the high breakdown voltage and the practicality of a
relatively easy dry etching process, 0.6µm was selected in our simulations. How the
doping concentrations in the lateral channel and vertical channel influence both the
breakdown voltage and the drain current is shown in Fig 8(a) and 8(b). The
simulation predicts that as the doping concentration increases from 5.0×10
14
cm
-3
to
1×10
15
cm
-3
, the drain current intensity increases very slowly and the breakdown
voltage decreases very slowly. This is due to the still large built-in p+/n- junction
potential. However, when the doping concentration of the vertical channel continues
increasing to 5×10
15
cm
-3
, the current density rapidly increases from 60 A/cm
2
to 170
A/cm
2
because of the formation of a wider vertical channel. However the influence
4
5
6
7
8
9
5.0E+14 2.5E+15 4.5E+15
Doping Concentration (cm
-3
)
Vbreak (kV)
30
40
50
60
70
I
D
(A/cm
2
)
(a)

36
4
5
6
7
8
9
5.0E+14 2.5E+15 4.5E+15
Doping Concentration (cm
-3
)
Vbreak (kV)
30
60
90
120
150
180
I
D
(A/cm
2
)
(b)

Fig. 2.8 Predicted Breakdown voltage and current density dependence on the lateral channel
doping concentration shown in (a) and vertical channel doping concentration shown in (b).

of the doping concentration in lateral channel on the current density is not so strong,
and the current density increase is only 15A/cm
2
. The vertical channel opening is
also an important parameter. The wider it is, the more current it allows, but the less
voltage it can support. As a result, a 0.5µm opening is chosen not only to achieve a
high breakdown voltage but also a relatively large operating current density. In
addition, high-voltage devices require deep junctions. The electric field lines of
deeper junction devices show much less crowding due to the junction curvature. The
electric field lines will spread out along a wide junction contour instead of being
located at a point close to the surface as happens to shallow junctions [Baliga, 1987].
Thus, a 1 µm-deep gate was selected for our analysis. It can be accomplished by a
high-energy implanter [Stief, 1998]. The implanted p+/n- junction should be able to
support the desired drain voltage.

37
0
2
4
6
8
10
0 102030 405060
N- Drift Region Thickness
Vbreak (kV)

Fig. 2.9 Predicted Breakdown voltage as a function of drift region thickness for VJFETs. N-
drift region thickness is in µm.

Lowering the N- drift region doping concentration is necessary to achieve a higher
holdoff voltage. A doping concentration in the n-drift region as low as 2×10
14
cm
-3
is
now achievable [Cooper et al., 2002]. Since high breakdown voltage of the device is
a primary concern, the doping concentration of n- drift region is set to 5×10
14
cm
-3
.
Our simulations predict an almost linear relationship between the breakdown voltage
and the drift region thickness. As can be seen in Fig. 2.9, the breakdown voltage
increases with the drift region thickness. At a leakage current of 1×10
-5
A/cm
2
, it has
values of 1.9kV, 3.56kV, 5.1kV, 6.6kV and 8.1kV for drift region thicknesses of 10

38

Fig. 2.10 Electric field strength (y axis on the left) and impact generation rate (y axis on the
right) along the cutline. It was cut from (2.03, -0.0112) to (2.03, 4.99) in a 40-µm drift
region VJFET that was shown in the inset.

µm, 20 µm, 30 µm, 40 µm and 50 µm, respectively. The breakdown voltage is
15.2kV when the drift region of the device is 100um. To study the breakdown
phenomenon, a cutline from (2.03, 0.0112) to (2.03, 4.99) in a 40-µm drift region
4H-SiC VJFET was shown in Fig. 2.10. The impact generation rate reveals that the
most intense avalanche multiplication is in the vicinity below the p+ gate, especially
near the corner of the trench. High electric field strength as high as 2.5×10
6
V/cm
occurred in the depletion region at the corner of the trench. The depletion region
39
formed between the p+ gate and n-drift region is not strong enough to withstand the
high electric field from the drain.

The lengths of both source and gate have little effect on the blocking voltage of the
device. Their values can be increased by 0.5-1µm at the convenience of fabrication.
However, the relative position of the source and the gate influences the breakdown
voltage. Our simulation results predict that if the source is inset from the edge of the
gate region by 0.1 µm or 0.2 µm, V
break
will decrease. If the source extends and
passes the edge of the gate by 0.1 µm or 0.2 µm (the length of gate is 2.1 µm ~ 2.2
µm), V
break
increases but simultaneously specific on-resistance increases. A 2.0 µm-
long gate was used as a starting point for our simulations. In this case, the source is
in line with the edge of the gate region. Considering the tolerance of mask alignment
and easy fabrication, the gate length can be elongated to pass the source by up to
1µm while the vertical channel length remains the same. The half-cell length of the
device is increased by up to 1 µm correspondingly, that is, from 2.5 µm to 3.5 µm.
The blocking voltage of VJFETs increases in this case since the electrical field
crowding near the corner of the trench is reduced, and higher electrical field strength
of 2.67×10
6
V/cm can be achieved from our simulation. One drawback with this
tolerance is that the resultant current density is lower, which was shown by two lines
with markers in Fig. 2.11 at a gate-source voltage of 2.7 V and 2.75 V, respectively.
This problem can be mitigated by elongating the source as long as the edge of the
elongated source region is inset from or inline with the edge of the gate region.
40

0.00E+00
5.00E+01
1.00E+02
1.50E+02
2.00E+02
2.50E+02
3.00E+02
02 46 8 1
V
D S
(V)
I
D
(A/cm
2
)
Vgs =2.8 V
Vgs =2.75 V
Vgs =2.7 V
Vgs =2.6 V
Vgs =2.5 V
0

Fig.2.11 Predicted I-V characteristics of the 4H-SiC VJFET at 300K.

The drain current I versus drain-to-source V voltage was simulated for a series
of gate-to-source V voltages. When a positive voltage bigger than threshold
voltage V is applied to the p+ gate, the gate-to-channel pn junctions become forward
biased. At a very small V , the space charge region narrows as V increases, and
both lateral and vertical n channels widen uniformly. The channels behave like
resistors, increases linearly with V and the slope of I versus V increases as
increases, as can be seen in Fig 2.11. When V increases further, there is a large
voltage drop along the vertical channel, and the space charge region narrows
progressively from the drain side to the source side. Similar to MOSFETs, the
channel length modulation could explain I -V behavior in the saturation region.
With 50-µm drift region with a doping concentration of 5×10
D
GS
DS
DS
th
I
DS GS
DS D DS D
GS
V
DS
D
14
cm
-3
, at V =2.8 V
GS
41
and V =5 V, the 4H-SiC VJFET is capable of handling a current density of 185
A/cm
DS
2
.

1.0E-12
1.0E-10
1.0E-08
1.0E-06
1.0E-04
1.0E-02
1.0E+00
1.0E+02
1.0E+04
1.0E+06
01 23
VGS (V)
I

(A/cm
2
)
Ig_Vds 1 0
Id_Vds 1 0
Ig_Vds 3000

Fig. 2.12 Predicted Gate current density and drain current density of 4H-SiC VJFET at
V
DS
=10V. Predicted gate current density at V
DS
=3000V was also shown.

In the forward conduction mode, for forward biased p+ gate to n- layer, the gate
current of the JFETs has to be considered. Fig. 2.12 shows a comparison of the
predicted gate and drain current densities as a function of gate voltage for the 4H-
SiC VJFETs. The built-in p+/n- junction potential at our given concentration for
simulation is calculated to be around 2.9V. When the gate to source voltage (V ) is
less than the threshold voltage 1.9V(V ), the device doesn’t turn on and both the
gate and the drain currents are very small.
V
was determined by plotting
GS
th
th DS
I
versus V . At a V of 10V, as V increases, increases rapidly but also
increases due to the forward biased p+(gate)-n junction. At a gate bias of 2.6 V, the
current gain I is 1000. It decreases to 50 at a V of 2.8 V where the gate
GS DS
G
I
GS D
I
G
I
D
/
GS
42
current density is 5A/ µm
2
. When V is 2.9 V, which is equal to the built-in p+/n-
junction potential, the gate current density is comparable to the drain current density.
One drawback of the enhancement VJFETs is that they are restricted to very limited
gate voltage swings because larger gate voltage will draw larger gate currents due to
the forward biased gate junction. The maximum gate voltage that can be applied is
controlled by the p+/n- junction built-in potential and is also dependent, to some
extent, on the expected current gain and current density. It is also observed from Fig.
2.12 that at a V of 3 kV, the gate current is almost the same as that at a V of 10V.
almost has no effect on the gate current at a given gate bias.
GS
DS
I
DS DS
V I −
DS
V

The specific on-resistance R
on, sp
is an important device parameter since it
determines the current rating, the voltage drop for a given current density and the
power dissipation. R
on,sp
is the product of on-state resistance R
on
and the device
active area. R
on
is defined as V , which is the inverse slope of the curves
in the linear region at low voltages [Baliga, 1987]. R
DS
/
on
is determined by the
contributions of all the regions along the current path in the structure. Fig. 2.7 shows
the on-state current flow lines in the SiC VJFET. The current tends to flow primarily
through the vertical channel. The total on-state resistance along the current path for
our VJFET structure is:
R
on
= R
c
+ R
lch
+ R
vch
+ R
drift
+ R
n+
Eq.(2.8)
43
where R
c
is the contact resistance from the source and the drain, R
lch
is lateral
channel resistance, R
vch
is vertical channel resistance, R
drift
is the drift region
resistance, and R
n+
is the substrate resistance.

In SiC, good ohmic contacts with resistance as low as 10
-5
Ωּcm
2
can be achieved
[Cole et al., 2001; Constantinidis, 1997]. Therefore, in our simulations, good ohmic
contacts are assumed and R
c
is neglected. In comparison with the remaining
resistances, R
n+
is relatively small and it is in the range of 10
-3
-10
-4
m Ωּcm
2
. This is
also neglected in the simulation for simplicity. Therefore, the total on-state
resistances mainly come from the channel and the drift region. The inset in Fig. 2.11
shows the I characteristics of the VJFET in the linear region. It can be calculated
that at a V of 2.8 V, Ron,sp is 21 m Ωּcm
V −
GS
2
. This value is a little less than the
theoretical value of unipolar 4H-SiC devices predicted by the researchers [Baliga,
1987]. This simulation result could be explained by several reasons: (1) In the on-
state operation, electrons are injected from the source into n- drift region; (2) At
=2.8 V, comparable to the p+/n- junction built-in potential, minority carriers are
injected from the gate into the n- doped region. The carrier injections mentioned
above increase the carrier concentrations in the n- doped region which reduces R
GS
V
on
.
(3) At the same time, due to a forward biased p+/n- gate junction [Asano et al., 2001],
the reduction of depletion region around the p+ gate in the channel current path also
result in decrease of R
on
. Reason (2) also explains the high gate current and low
44
current gain of 50 mentioned above. The carrier injection phenomenon is obvious at
=2.9V, which is clearly shown in Fig. 2.13. As V is decreased to 2.7 V, R
GS
V
GS on,sp
increases to 35 m Ωּcm
2
due to the decrease of gate current and drain current.

(b)
Fig. 2.13. Current flow lines of the 4H-SiC VJFET at V
GS
=2.9V.

The switching characteristics of the proposed half-cell of SiC VJFET with a resistive
load have been simulated at I of 100 A/cm
D
2
. The waveforms for the drain-source
voltage and drain current are shown in Fig. 2.14. The magnitude of the applied gate
pulse was 2.7 V; the rise and fall times were both 2 ns. That is, the selected dV /dt
is 1.37×10
GS
9
V/s. The turn-on time and turn-off time are several ns. As dV /dt rate
becomes smaller, the slower switching time is expected. At a dV /dt rate of 1×10
GS
GS
7

V/s, a turn-on time of 204ns and a turn-off time of 139ns were found in the
45
simulation [Zhao et al., 2003], whereas at a dV /dt rate of 1×10
GS
8
V/s, a turn-on time
of 24ns and a turn-off time of 40ns were achieved [Zhao et al., 2003]. For one die
where tens or hundreds of unit cells are connected together, the switching speed
decreases since both capacitance and resistance increase. Our simulation predicts that
the switching speed of such die for our used 4H-SiC VJFETs is on the same order of
the reported value with 17ns fall-time [Asano et al., 2001]. The simulated gate
current density during switching was shown in Fig. 2.15.
0E-08
me (s)
µ m
µ m
µ m
µ m

0
500
1000
1500
2000
2500
0.0E+00 2.0E-08 4. 6.0E-08
Transient ti
V
D S
(V)
0.0E+00
1.0E-04
2.0E-04
3.0E-04
4.0E-04
5.0E-04
6.0E-04
7.0E-04
I
D
(A)
W=1 00
W=200
W=300
W=1 00

Fig. 2.14 The predicted switching performance of the 4H-SiC VJFET.

46
0
500
1000
1500
2000
2500
0.0E+00 1.0E-08 2.0E-08
Transient time (s)
V
D S
(V)
0.0E+00
1.0E-04
2.0E-04
3.0E-04
4.0E-04
5.0E-04
6.0E-04
7.0E-04
ID (A)
W=1 00 µ m
W=200 µ m
W=300 µ m
W=1 00 µ m

Fig. 2.15. The predicted turn-on time of the 4H-SiC VJFET.

2.6 Device Modeling
To evaluate the 4H-SiC VJFETs in pulsed power circuits, developing proper circuit
models and extracting the necessary parameters from the electrical characteristics of
these switches are important for circuit simulation program such as SPICE. Here we
extracted some circuit model parameters from the simulated I curves. This
method could be used as a test bench without fabricating the devices to minimize the
unnecessary cost. Although in our former numerical simulations reasonable physical
models as well as their corresponding established parameters were used, the
predicted curves by simulation don’t represent the exact characteristics of the
real device. To better represent the performance of the real devices, more
complicated and complete physical models, and more stringent fabrication processes
are required. Therefore, our modeling of the simulated 4H-SiC VJFETs is more
V −
V I −
47
focused on predicting the device characteristic trends correctly than on matching the
simulated I-V curves precisely.

The physics of the proposed 4H-SiC VJFET is similar to the traditional enhancement
mode GaAs MESFETs. For the long channel GaAs MESFETs, the following
assumptions are made [29]: (1) a uniformly doped n- region, (2) gradual channel
approximation, (3) abrupt depletion layer, and (4) constant mobility. For one-sided n
channel GaAs enhancement MESFETs, starting with Ohm’s law, their drain current
relationship to V and V derived from semiconductor physics is:
GS DS


















−
+








− +
−








=
2 / 3
0
2 / 3
0 0
2 2 3
p
GS bi
p
GS bi DS
p
DS
p D
V
V V
V
V V V
V
V
I I
Eq.(2.9)
where
L
Wa qN
I
d n
p
ε
µ
6
) (
3 2
≡
(pinchoff current) Eq.(2.10)
ε 2
2
0
d
p
N qa
V =
(pinchoff voltage) Eq.(2.11)
where is the p+/n built-in junction potential,
bi
V
n
µ , , , W , , , and q
d
N L a ε are
electron mobility, electronic charge, n region doping concentration, channel width,
channel length, channel depth and dielectric constant, respectively. The threshold
voltage for an enhancement mode FET is approximately V . Using Taylor
series expansion at V , the drain current in the saturation region is:
th
V
bi
V −
p
=
0
th GS
V =
2
) (
) (
th GS sat D
V V I − = β Eq.(2.12)
48
where
aL
W
n
2
ε µ
β =
(transconductance coefficient) Eq.(2.13)
The analytical model presented by Curtice [Curtice, 1980] for GaAs MESFETs
considered non-ideal effects of the devices-channel length modulation. His use of the
hyperbolic tangent function provides the smooth transition from the linear region to
the saturation region. His proposed analytical function describing the drain-source
current in both linear and saturation regions is:
( )
DS DS th GS D
V V V V I α λ β tanh ) 1 ( ) (
2
+ − = Eq.(2.14)
Where λ is channel length modulation coefficient, and α is a constant. To model the
current for the 6H-SiC JFETs, Zappe et al. [Zappe et al., 1998] introduced a gate-
source voltage-dependent saturation voltage parameter ( )
GS
V α to modify the current
expression in equation (14). The modified form of the drain-source current is:
( ) ( )
DS GS DS th GS D
V b aV V V V I
1 2
tanh ) 1 ( ) (
−
+ + − = λ β Eq.(2.15)
The fitting data using equation (15) can describe their measured characteristics of
6H-SiC JFETs in a very satisfying manner.

Based their work and Rode’s work [Rode, 1987], we introduced another parameter
in our modeling to improve the transition from the linear region to the
saturation region defined by tanh( function. Only non-negative values of the
function were considered in the curve fitting. The analytical model for the
VGS
E
) x
) tanh(x
49
drain current of our simulated 4H-SiC VJFETs was described by the following
hyperbolic tangent model:
( ) ( )
DS GS DS th GS VGS D
V b aV V V V E I
1 2
tanh ) 1 ( ) (
−
+ + − = λ β Eq.(2.16)
The parameters β , λ , and were obtained by the nonlinear optimization using
MATLAB. V is 1.9V from the above explanation. The drain current is proportional
to the channel width. In order to describe the spectrum of VJFETs with different
widths by one set of model parameters, the channel width W is set to 1 µm. Fig. 2.16
shows the curves by simulation and modeling. In this optimization, the average
absolute difference between the simulated and fitted drain currents was minimized.
To better fit the simulated curves, the
V
used is 1.98 V instead of 1.9V. The mean
error of the curve fitting is 1.75×10
a b
th
V − I
th
-9
A, and the standard deviation is 2.01×10
-8
A.
The extracted parameters are listed in Table 2.2.

0.0E+00
3.0E-07
6.0E-07
9.0E-07
1.2E-06
01 2 345
V
D S
(V)
I
D
(A)
s imula tio n da ta
fitting da ta
Vgs =2.75 V
Vgs =2.72 V
Vgs =2.70 V
Vgs =2.68 V
Vgs =2.65 V

Fig. 2.16. Simulated and fitted I-V characteristics of the proposed 4H-SiC VJFET at 300K.
50

Table 2.2 Extracted model parameters from simulated I-V characteristics.

Symbol Parameter Value
Unit
s
β

Transconducta
nce coefficient
4.48×10
-5
A/V
2

VGS
E

GS
V

Controlling
factor
0.76
λ

Channel
length
modulation
coefficient
0.10 1/V
th
V

Threshold
voltage
1.98 V
a

Constant 11.04
b

Constant 29.04 V

2.7 Conclusion
A typical and advanced normally-off 4H-SiC VJFET structure has been described
and simulated using 2-D simulator ATLAS. The channel doping concentration, the
channel thickness, drift region thickness, the relative position between the source and
the gate, and the length tolerance of the gate and the source for easy fabrication were
studied in terms of their influences on the device breakdown voltage and the drain
current. This advanced device has a predicted breakdown voltage above 8 kV and a
low specific on-state resistance of 35 m Ωּcm
2
at V =2.7V. The device has a
switching speed of several ns. One drawback with this forward biased gate VJFET is
that the current gain is low when the gate to source voltage is comparable to the
built-in p+/n junction potential. An analytical model for the drain to source current
GS
51
was developed based on other researchers’ previous work. Some circuit parameters
were extracted by fitting the I V − curves of the simulation data and minimizing the
error between the simulation data and the fitting data using MATLAB. The
simulation, design and the modeling of the 4H-SiC make it possible for the next
evaluation of the 4H-SiC VJFETs in a typical pulsed power circuit.

52

Chapter 3

Metal-Oxide-SiC Capacitors with Al
2
O
3
and TiO
2
as
Gate Materials

3.1 Introduction
It is important to develop solid-state-based pulsed power switches with hold-off
voltage considerably in excess of 10 kV, peak currents of kA to many kA, and turn-
on in 10's of nanoseconds, for varying pulse lengths. 4H-SiC is an attractive
candidate at this time because it has a large bandgap energy (3.26eV) relative to
GaAs (1.43eV) and Si (1.12eV), breakdown electric field strength of 3-4 MV/cm,
electron saturation velocity of 2.2 ×10
7
cm/s and thermal conductivity of 4.9 W/cm.K
[Baliga, 1989; Cooper et al., 2002]. Up to now, 5kV 4H-SiC MOSFETs with 100-
µm N- drift region [Khan et al., 2002] and VJFETs with several kilovolts have been
proposed [Mitlehner et al., 1999; Mihaila, 1999; Asano, 2001; Tone, 2003; Shui et
al., 2003]. 4H-SiC-based switches are thus of interest as potentially efficient, low-
cost, and compact alternatives to gas phase switches [Gundersen, 1991]. MOSFETs,
the most widely used power devices, have poor oxide quality and oxide breakdown
53
which has thus far limited the performance of 4H-SiC MOSFETs [Cooper et al.,
2002], and the high breakdown field strength of SiC has not been fully exploited.
Utilizing a material with higher dielectric constant will reduce the electric field
across the dielectrics [Lipkin et al., 1999], and provides a possible solution to the
above-mentioned problems.

The relatively large lattice mismatch between Al
2
O
3
or TiO
2
and SiC substrates
restricts the use of these layers in SiC technology as SiO
2
and AlN. So far, very
limited research has been done in this field [Gao et al., 2003; Werbowy et al., 2003].
Nevertheless, Al
2
O
3
( ε =8-15, E
g
=6-9eV) and TiO
2
( ε =20-110, E
g
=3-5eV) have
higher dielectric constants and high bandgap energies as well as the acceptance of Ti
and Al in most modern CMOS fabrication facilities. A band alignment of Al
2
O
3
on
4H-SiC with offsets of 2.2 for the valence bands and 1.5eV for the conduction bands
further makes it a potentially serious competitor to SiO
2
[Gao et al., 2003].

In this paper, we study Al
2
O
3
and TiO
2
grown by e-beam evaporation as possible
gate dielectrics for SiC devices. E-beam evaporation is a high vacuum and low-
temperature process (T<200ºC), thus it is effective in limiting the formation of the
interfacial SiO
2
layer between the SiC and Al
2
O
3
as well as the formation of high-
temperature induced defects. Surface morphology of Al
2
O
3
or TiO
2
were
54
investigated by AFM, and both Al
2
O
3
and TiO
2
MIS capacitors were fabricated to
evaluate their potentials as gate dielectrics in pulsed power SiC devices.

3.2 Experimental Procedure
4-8 µm-thick n-layer (~1 ×10
16
cm
-3
) and 0.3 µm-thick buffer layer, grown on the
(0001) Si-faced 4H-SiC substrate (~1 ×10
19
cm
-3
), were provided by Mississippi State
University. Fig.3.1(a) illustrates the schematic structure of the MIS capacitors. Fig.
3.1 (b) shows the SEM images of fabricated capacitors with different areas. Only one
mask was used to fabricate these capacitors. Before the deposition of nickel and gate
dielectric materials, the samples were cleaned and dipped in buffered oxide etch (7:1)
for 1min. A layer of 2000 Å-thick nickel was e-beam evaporated and RTA (Rapid
Thermal Annealing) annealed at 900 ºC for 1min to form backside ohmic contacts.
500 Å thickness of Al
2
O
3
and TiO
2
were also e-beam deposited on the front side of
samples, respectively. The chamber temperature is less than 200 ºC. Top gate
electrodes were pattern by standard photolithography, then 200 Å thick Ti was
deposited as an adhesion layer before depositing 1500 Å Au as a gate electrode
material. Ti (200 Å) and Au (1500Å) were chosen as top gate electrodes. After lift-
off of the metal and O
2
descum of the photoresist residue, the samples were annealed
at 450ºC for 30s by rapid thermal annealing.

55

Fig. 3.1(a) The schematic structure of investigated 4H-SiC MIS capacitors.

Fig.3.1(b) Different Patterns of MIS capacitors taken by SEM.

56
The capacitance-voltage (C-V) measurements of these MIS capacitors were done by
a HP 4263 LCR meter at a frequency of 10kHz. The small ac voltage is 1V on an
applied dc gate voltage. Dielectric constants of Al
2
O
3
and TiO
2
grown by e-beam
evaporation were calculated. Current-voltage (I-V) characteristics of the gate
materials were measured by using a HP 4145B semiconductor parameter analyzer on
150 µm ×150 µm gate patterns.

3.2 Results and Discussion
3.2.1 Film Morphology
Fig. 3.2(a) shows the surface morphology of the n-layer (~1 ×10
16
cm
-3
) grown on
heavily doped 4H-SiC substrate. The surface shows a regular terrace structure with a
width of about 1 µm. The surface mean height is 84 Å. An AFM image was also
taken after the deposition of Al
2
O
3
or TiO
2
(Fig. 3.2(b)). We found that the surface
morphology improves and the surface mean height is about 74 Å. We also measured
Al
2
O
3
(500 Å) deposited by the same e-beam evaporator on Si substrate, and the
surface mean height is 4-7 Å (Fig.3.2(c)). It is obvious that the surface morphology
not only depends on the growth conditions, but also depends on the substrate. We
conclude that from the point of surface morphology, high vacuum and low-
temperature e-beam evaporation proves to be a simple and reliable way for the
growth of good surface morphology of Al
2
O
3
and TiO
2
gate dielectrics.
57

Fig. 3.2(a) An AFM image (10 µm × 10 µm) of the starting material (4H-SiC n- epilayer).

Fig. 3.2(b) An AFM image (10 µm ×10 µm) of 500 Å Al
2
O
3
deposited on 4H-SiC n-
epilayer.

58

Fig. 3.2(c) An AFM image (10 µm ×10 µm) of 500Å Al
2
O
3
deposited on Si substrate.

3.2.2 Electrical Characterization
Fig. 3.3(a) and 3.3(b) show the C-V characteristics of metal-Al
2
O
3
-SiC and metal-
TiO
2
-SiC capacitors measured on different contact areas, 120 µm × 120 µm and 100
µm × 100 µm, respectively. Measurements were performed at a frequency of 10kHz
at room temperature. Since an n- epilayer is below the gate insulators, at positive
voltages majority carrier electrons would experience a force toward the oxide-
semiconductor interface. At large positive voltages, the capacitance saturates,
indicating that an accumulation layer is formed below the gate materials. The
capacitance
C
for the MIS capacitor in the accumulation mode is just the oxide
acc

59

Fig. 3.3(a) Capacitance-voltage characteristics of Metal-Al
2
O
3
(500 Å)-SiC capacitors
measured at 10kHz.

Fig. 3.3(b) Capacitance-voltage characteristics of Metal-TiO
2
(500 Å)-SiC capacitors
measured at 10kHz.

60
effective capacitance. The oxide effective capacitance may also include the
contribution made by a very thin layer of SiO
2
formed in the subsequent 450 °C gate
electrode annealing process. A minimum capacitance
min
C at large negative voltages
in Fig. 3.3(a) and 3.3(b) means that a maximum depletion width is reached. We
first assume that there is no thin interfacial SiO
dT
x
2
layer formed, the dielectric
constants for Al
2
O
3
and TiO
2
on two different areas are consistent and they are 9 and
20, respectively, based on the accumulation capacitance
C
. The theoretical flat-
band capacitance then can be determined from the following equation [Neamen, 3
acc
rd

edition]:
























+
=
a
SiC
SiC
ox
ox
ox
FB
qN q
kT
t
A
C
ε ε
ε
ε
ε ε
0
0
Eq.(3.1)
We note that the calculated flat-band capacitance for Al
2
O
3
(A=120 µm × 120 µm) is
13.5pF. This value is even below
min
C , indicating that a thin interfacial layer SiO
2
is
in series with the Al
2
O
3
and that it reduces the effective dielectric constant of the
insulating systems. Similarly, the theoretical value of
FB
C
for TiO
2
(A=120 µm × 120
µm) is determined to be 20 pF. This value is also below our expected value deduced
from the experimental data in Fig. 3.3 (b). Since the dielectric constant TiO
2
is
several times larger than that of Al
2
O
3
, the thin SiO
2
layer doesn’t reduce the
dielectric constant of TiO
2
/SiO
2
system as much as it does for Al
2
O
3
/SiO
2
system.
There are two approaches to determine the thicknesses of SiO
2
and Al
2
O
3
or TiO
2
.
61
The first is to fabricate another set of MIS capacitors with different thicknesses of
Al
2
O
3
or TiO
2
under the same fabrication conditions. The second is to employ
material characterization equipments, such as AES (Auger Electron Spectroscopy),
SIMS (Secondary Ion Mass Spectrometry) and TEM (Transmission Electron
Microscope). That is part of our future work.

Fig. 3.4 Current-voltage characteristics of MIS capacitors. The capacitor area is 150 µm ×
150 µm and the thicknesses of Al
2
O
3
and TiO
2
are all 500 Å.

Leakage currents were measured on MIS capacitors with area of 150 µm × 150 µm.
From Fig. 3.4 it is found that the leakage current is dependent on the polarity of the
gate bias. The dielectric of Metal-Al
2
O
3
-SiC capacitors even doesn’t break down at a
gate voltage of 40V, which corresponds to an electric field strength of 8MV/cm.
62
Al
2
O
3
has band offsets of 2.2eV for the valence band, and 1.5eV for the conduction
band [Gao, 2003]. These band offsets promise higher barriers for both electrons and
holes. Fig.3.4 also shows that Al
2
O
3
is highly resistive, and its resistivity is more
than 1 ×10
11
Ω⋅cm. The experiments demonstrate that Al
2
O
3
is a low-leakage current
gate material. TiO
2
has a higher leakage current at negative gate voltages than Al
2
O
3
.
This can be explained by the observations that materials with higher dielectric
constants tend to suffer from higher leakage currents due to smaller bandgaps
[Jammy et al., 2000; Campbell et al., 1997; Wilk et al., 2001]. It is known that the
bandgap of TiO
2
is 3-5eV, the smaller bandgaps lead to lower band offsets with
respect to 4H-SiC.

Nitridation is widely used in silicon technology and it is usually achieved by
annealing the sample in nitric oxide(NO), nitrous oxide (N
2
O) or NH
3
atmosphere.
Nitridation is not only very effective in limiting the formation of an unnecessary
interfacial SiO
2
, but also reduce the Si dangling bonds and Si-O-Si strained bonds at
the interface, hence decreasing the leakage current. To gain insight into the role that
NO plays at the interface between the insulator Al
2
O
3
and 4H-SiC, after depositing
Ni and alloying of the backside Ni ohmic contacts at 900ºC with RTA, the samples
were subjected to annealing in NO at 1000ºC for 10min in a furnace, then dipped in
buffered oxide etch (7:1) for 1min. The subsequent fabrication conditions are the
same as described above. We found that
C
decreases to 16.8pF for a 120 µm × 120
acc
63
µm capacitor. We think that a thicker SiO
2
is formed and nitric oxide doesn’t seem to
limit the formation of SiO
2
in this case. I-V tests show that the leakage currents
remain almost the same.

3.3 Conclusion and Future Work
We have performed e-beam deposition of Al
2
O
3
and TiO
2
on 4H-SiC for the purpose
of pulsed power application. High-vacuum and low-temperature e-beam evaporation
shows a mean height of about 4-7 Å on Si substrate. The MIS C-V characteristics
show that the dielectric constant of Al
2
O
3
is more than 9, and that of TiO
2
is more
than 20. I-V curves show that Al
2
O
3
is highly resistive and has much lower leakage
current than TiO
2
due to its large band gap offsets. Therefore, Al
2
O
3
deposited by e-
beam evaporation can be considered as a promising material among the gate
insulators for high power SiC devices which will be used in pulsed power in the
future.

Further research is needed to identify detailed information of gate materials by X-
Ray Diffraction (XRD), TEM, etc. Dielectric constants, flat-band voltage, fixed
oxide charges, and interface trapped charge densities need to be determined.

64

Chapter 4

Si-JFET Controlled Carbon Nanotube Field Emitter
Cathode Arrays

4.1 Introduction
Pulsed power and microwave vacuum devices often require cathodes capable of
providing peak current density of kA/cm
2
to many kA/cm
2
. Traditional thermionic
cathodes are limited to tens of A/cm
2
for reasonable lifetimes[Fisher et al., 1998].
Plasma cathodes are an attractive alternative where higher current density, longer
lifetime and higher efficiency are required. However, the maximum stable current
density that can be extracted from the plasma is about 100 A/cm2, and plasma
cathodes usually have high threshold fields in excess of 100 kV/cm [Fisher et al.,
1998; Umstattd et al.,2001; Oks et al., 1999].

With the introduction of Spindt microtip cold cathodes [Spindt, 1968], research has
included investigation of Mo, Si, SiC, diamond, GaN, and CNTs integrated with Si
devices as cathodes to achieve high current density and low voltage operation. CNTs
are promising among these materials because they have a threshold field as low as 1-
65
2V/µm, and a field emission current of 0.1mA can be obtained from one multiwall
nanotube [Rupesinghe et al., 2003]. In addition, CNTs are stable at high
temperatures, and can have high electrical and thermal conductivity, high mechanical
strength and a high aspect ratio. Utsumi analyzed different emitter tip shapes and
concluded that the ideal field emission tip should be a rounded whisker-like shape
[Utsumi, 1991]. A corresponding key issue is the improvement of emission stability
and controllability of the emitters of different materials. Active devices, such as
MOSFETs and JFETs, integrated with Si or metal microtips, were experimentally
proven effective in improving emission current stability when the active device
operates in the saturation region [Matsukawa et al., 1999; Shimawaki et al., 2002].

Goals of the work include achieving high emission current density and evaluation of
the potential for the active device—a junction field effect transistor (JFET),
monolithically integrated with CNT field emitter elements, to control and stabilize
field emission. Towards this end, this study describes a technical approach to the
realization of the novel device: JFET-controlled carbon nanotube (CNT) field
emitter arrays. Field emission current is extremely sensitive to the local surface
electrical field and work function, and the purpose of the JFET is to limit and
stabilize this emission including preventing disruptively excessive emission current.
The design of built-in JFETs requires the successful interleaving of both the
fabrication processes and the semiconductor physics.

66
The work may be summarized as follows: JFETs were designed using the 2-D device
simulator ATLAS (from Silvaco International). Si JFETs integrated with CNTs were
fabricated. MWCNTs were successfully grown on the Si posts of the device. The
preliminary field emission test was done on a 50 × 50 array, and the maximum
emission current (anode current) obtained was about 3 µA (~40mA/cm
2
). This work
also addresses some challenging issues, such as plasma arcing in the large area of
exposed SiO
2
during CNT growth at 700 ºC in dc plasma. This work demonstrates a
promising pathway towards the development of high current cathode with uniform
emission controlled by active devices.
4.2 Design and Simulation of Si-JFETs

N- Si substrate

Cr/Ni SiO
2
Cr
P+
CNTs

N+

Fig. 4.1 Schematic drawing of Si JFET-controlled CNT field emitter arrays.

Our study used the 2-D simulator ATLAS (from Silvaco International) to design and
simulate the Si VJFETs. The simulator is effective in predicting the electrical
67
behavior of specified semiconductor structures, and providing insight into the
internal physical mechanisms associated with device operation. The models and the
required parameters for simulating Si devices are well established. In our device, we
need dope boron (B
+
) to form p+ region in Si substrates (Fig. 4.1). SRIM 2003 was
used to simulate the boron distribution in Si substrates. After ion implantation, the
samples went through high temperature cycles in the following processes, and the
dopants diffused vertically and laterally. Combined effects of ion implantation and
high temperature impurity diffusions were considered, and the final boron impurity
distribution profile was imported into the deck of ATLAS to ensure realistic
simulations.

4.2.1 Ion Implantation
There are two common ways to introduce impurity atoms into Si wafer: Diffusion
and Ion Implantation. Diffusion requires high temperatures since diffusion
coefficients D depend exponentially on temperatures and follow the Arrhenius
relationship:
) / exp(
0
kT E D D
A
− = Eq.(4.1)
where is a prefactor, and it is 10.5 cm
0
D
2
/s for both B ( boron) and P (phosphorus);
is activation energy; and k is Boltzmann constant. At a given temperature, there
is a solid-solubility limit for the impurities.
A
E

68
In comparison with diffusion, although ion implantation requires very expensive
equipment ($1M or more), it has the following main advantages:
• It is a low-temperature process that permits the use of a wide variety of
materials as barrier layers to mask the implantation, such as photoresist and
some metals. It also minimizes the impurity movement by diffusion.
• Dose control is very precise at all levels and the excellent doping uniformity
is achieved across the wafer and from wafer to wafer.
• Ion implantation permits the use of a much wider range of impurity species
than diffusion. In principle, any element that can be ionized can be
introduced into the wafer using implantation.
• High dose is not limited by solid-solubility limit values for ion implantation.
Low dose introduction less than 5×10
13
atoms/cm
2
is impossible to achieve
by using diffusion. Ion implantation can go down to 1×10
11
atoms/cm
2
.

Boron is so light that it does not produce an amorphous layer even at relatively high
doses, unless the substrate is deliberately cooled [Jaeger, 1993]. In this study, boron
is implanted using ions of the heavier BF
2
molecule. To minimize channeling effects,
the tilt angle between the incident ion beam and the normal of the sample surfaces
was set to 7°. The ion distribution was simulated by the widely-used software SRIM
2003. Then we introduced standard mathematical model for ion implantation and
compare the results predicted by SRIM method. To better understand those, we will
69
explain the following terms: “Dose”, “(Longitudinal) Projected Range”, “Lateral
Projected Range” “(Longitudinal) Straggling”, and “Lateral Straggling”. More
detailed information can be found in [Jaeger, 1993; www4.1]

Fig. 4.2. The crystalline nature of the Si substrate [www4.2]

Dose (Q ): The implant dose is the number of ions implanted per unit area (cm
2
) of
the wafer.
(Longitudinal) Projected Range ( ): it is the average distance an ion travels
before it stops in x direction:
p
R
x N x R
i p
= ≡
∑
/ Eq.(4.2)
Lateral Projected Range ( ): it is the average distance an ion travels before it
stops in y direction:
p
R
y N y R
i p
= ≡
∑
/ Eq.(4.3)
(Longitudinal) Straggling (
p
R ∆ ): It represents the standard deviation of the spread
of the distribution of the ions in x direction:
[] [ ]
2 / 1
2
2 / 1
2
/ ) ( / ) (
∑ ∑
∆ = − = ∆
i
i
i
p i p
N x N R x R Eq.(4.4)
70
Lateral Straggling ( ): It characterizes the behavior of the distribution near the
edge of the window in y direction (windows are opened in a barrier material
wherever impurity penetration is desired).
⊥
∆R

SRIM-2003 codes are based on LSS theory developed by Lindhard, Scharff, and
Schiott. The theory assumes that the implanted ions go into an amorphous material
where the atoms of the target material are randomly positioned. The distribution
approximates Gaussian profile shown in Fig. 4.2. This assumption is not valid for a
single crystal Si substrate. The regular arrangement of atoms in the crystal lattice
leaves a large amount of open space in the crystal, if the incident ion flux is
improperly oriented with respect to the crystal plane, the ions will tend to miss the
silicon atoms in the lattice and will “channel” much more deeply into the material
than the LSS theory predicts [Fig. 4.3] [Jaeger, 1993]. To minimize channeling
effects, usually the ion implantation was performed at an angle of 5°-7° off the
normal to the sample surfaces.

Fig. 4.3. The crystalline nature of the Si substrate [www4.3]

71
4.2.1.1 Boron Distribution Before High Temperature Cycles
(a) Boron Distribution Simulated by SRIM-2003

Ion Projected Range
1.0E+18
1.0E+19
1.0E+20
1.0E+21
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Depth (micrometer)
Impurity Concentration
(atoms/cm
3
)

Fig. 4.4 Boron impurity distribution in Si simulated by SRIM-2003.

Fig.4.4 shows the boron depth distribution in Si (i.e., in x direction) without post-
implant annealing predicted by SRIM-2003. The boron dose of 5×10
15
/cm
2
and the
ion energy of 200 keV were employed in our study. The profile approximates
Gaussian shape. The simulated mean projected range and straggling are 5656 Å and
1047 Å, respectively. Fig. 4.5. shows the ion lateral distribution (i.e., in y direction)
as a function of target depth.

72

0
1000
2000
3000
4000
0 0.2 0.4 0.6 0.8 1
Target Depth (micrometer)
Distance (Angstrom)
Lateral
Projected
Range
Lateral
Straggling

Fig. 4.5 Predicted lateral projected range and lateral straggling by SRIM-2003.

Table 4.1 The ion range distribution created by 200 keV boron in Si was computed by
SRIM program. The tilt angle is 7 º.

Projected
Range
(Å)
Straggling
(Å)
Longitudinal 5656 1047
Lateral 1195 1473
Skewness: –1.1303 Kurtosis: 5.0902

The predicted lateral projected range and lateral straggling are 1195 Å and 1473 Å,
respectively. The above-mentioned four parameters shown in Table 4.1 are important
because they are needed to create analytical doping profiles for our 2-D numerical
Si-JFET device simulation using ATLAS. Skewness and kurtosis are two other
important parameters to describe the implanted profile. The skewness tells whether
73
the peak is skewed towards the surface (negative values) or away from the surface
(positive values) [www4.1]. That is, negative skewness indicates that the most
probable depth (the peak position) is greater than the mean depth, and positive values
indicate the reverse. Kurtosis indicates the extent of the distribution tails, with a
value of 3.0 indicating a Gaussian distribution. In general, values from 0 to 3 indicate
abbreviated tails, and values above 3 indicate broad tails. In our case, the simulated
skewness is –1.1303, which means that the peak is skewed toward the surface.
Kurtosis is 5.0902, indicating that the profile has broader tails than the ideal
Gaussian distribution.

(b) Boron distribution Calculated by the Standard Mathematical Model
Based on LSS theory, the implanted impurity profile in an amorphous material can
be approximated roughly by the Gaussian distribution function listed below [Jaeger,
1993]:








∆
−
− =
2
2
2
) (
exp ) (
p
p
p
R
R x
N x N , with
p
p
R
Q
N
∆
=
π 2
Eq.(4.5)
where is the impurity peak concentration, R is the projected range,
p
N
P P
R ∆ is
straggling, and is lateral straggling.
⊥
∆R

(1) Find the peak concentration ( ).
p
N
From Fig 5.3 in the reference[Jaeger, 1993], in the case of boron implantation, when
E=200 keV, Q =5×10
15
/cm
2
, we have:
74
Projected range: =0.52 µm
P
R
Longitudinal range: =0.092 µm
P
R ∆
Transverse straggle: =0.18 µm
⊥
∆R
p p
R N Q ∆ = π2
⇒ 5×10
15
atoms/cm
2
=
4
10 092 . 0 2
−
× × ×
p
N π cm
⇒ atoms/cm
20
10 168 . 2 × =
p
N
3

(2) Impurity concentration ( ) at
0
N 0 = x








∆
−
− =
2
2
2
) (
exp ) (
p
p
p
R
R x
N x N
⇒








∆
− =
2
2
2
exp ) 0 (
p
p
p
R
R
N N
⇒






× ×
×
− × =
−
−
2 4
2 4
20
) 10 092 . 0 ( 2
) 10 52 . 0 (
exp 10 168 . 2 ) 0 ( N
⇒ atoms/cm
13
10 505 . 2 ) 0 ( × = N
3

The calculated peak concentration N is similar to the simulated result by SRIM,
however, the calculated surface impurity concentration N is much lower. Real
implanted profiles are more complicated than a simple Gaussian distribution. Light
ions (e.g. B), backscatter and the profile is skewed towards the surface. Heavy ions
(e.g. Sb) scatter deeper and the profile is skewed towards the bulk. Light ions travel
further and have a broader distribution than the heavy ions. The methametical
p
0
75
Gaussian model doesn’t consider skewness and kurtosis. if we consider negative
skewness and and a broad tail of the implanted profile for our boron implantation
predicted by SRIM, the surface concentration should be around >10
17
atoms/cm
3
, 4
orders of magnitude larger than 2 atoms/cm
13
10 505 . ×
3
(please see Fig. 4.4). After
ion implantation, the samples will go through a combined high temperature
activation-oxidation process. That is, dopants are activated when the furnace
temperature goes from 600 ºC – 900 ºC for 30min in N
2
ambient (It will take 30 min
for our furnace to increase from 600 ºC to 900ºC), then the samples go through 50
min wet oxidation at 900ºC. A thin layer of 950 ―1000 Å SiO
2
is produced in wet
oxidation process. It will be removed in buffered oxide etchant (BOE) to minimize
the Si surface damage caused by ECR etching and ion implantation. Because of the
removal of the oxidized Si and the ion redistribution during this high temperature
process, the surface impurity concentration will be high enough to form ohmic
contacts.

More accurate ion distribution can be calcualted by Pearson IV distribution function
or Mante Carlo Simulation.

4.2.1.2 Boron Distribution After High Temperature Cycles
As mentioned before, after ion implantation, samples will go through a 50-min-wet-
oxidation process at 900ºC to get a ~0.1 µm SiO
2
. This layer was then etched to
minimize the Si surface damage caused by ECR etching and ion implantation. This
76
process includes the post-implant annealing step when the furnace temperature goes
from 600 ºC – 900 ºC in N
2
ambient (It will take 30 min for our furnace to increase
from 600 ºC to 900ºC). However, the main diffusion process is contributed by a 50
min wet-oxidation process at 900ºC.As our experiments found out later, we have to
grow ~ 0.2 µm SiO
2
in wet O
2
beneath a 0.5 µm PECVD SiO
2
to reduce the gate
insulator leakage current. This high temperature process lasts for 2 hours and 30
mins and also contributes to the ion diffusion.

The final ion distribution affected by the aforementioned two-step high temperature
cycles was taken in account and approximated by using the standard mathematical
models shown below and imported to ATLAS for device simulation.

(1) Ion distribution after post-implant annealing
Impurity diffusion follows the Arrhenius relationship:
( ) kT E D D
A
/ exp
0
− = Eq.(4.1)

where is diffusion coefficient and is activation energy. D
A
E

For successive diffusions, ( )
tot
Dt is the sum of the Dt products for all high-
temperature cycles affecting the diffusion:

()
∑
=
i
i i tot
t D Dt Eq.(4.6)

The Typical diffusion coefficient values for the impurity boron in silicon are:
77
5 . 10
0
= D cm
2
/s; 69 . 3 =
A
E eV
When T=900 ºC=900+273=1173 K, diffusion time t =50 min+ 2h 30 min=12000 s,
we have:
() s
K K eV
eV
s cm t kT E D Dt
A
12000
1173 ) / 10 617 . 8 (
69 . 3
exp / 5 . 10 ] / exp [
5
2
0
×
















× ×
−
= − =
−

⇒
2 11
10 2 . 1 cm Dt
−
× =

Fig. 4.6 Profiles of 5×10
15
/cm
2
boron implants at a tilt angle of 5º-7º along the <100> axis
onto Si before post-implant annealing (the curve in purple) and after post-implant annealing
(the curve in blue). The curve in purple and the curve in blue are derived from Eq. (4.5) and
(4.7) , respectively, using matlab.

78
After post-implantation annealing, the concentration distribution of the dopants can
be roughly described by the following equation:
()
()
( )








+ ∆
−
−
+ ∆
=
Dt R
R x
Dt R
Q
t x N
P
P
P
2 2
exp
2 2
) , (
2
2
2
π
Eq.(4.7)
The surface concentration (When 0 = x Å, t =12000s)
⇒ (0 Å , 12000s)=2.3×10 N
15
atoms/ cm
3

⇒ (1000 Å, 12000s)=1.2×10 N
16
atoms/ cm
3

The standard mathematical models above don’t consider the skewness and kurtosis
of the Gaussian profile, so it only roughly predicts the ion distribution. However, this
model is very effective in predicting the trend of ion distribution during high
temperature treatments. Fig. 4.6 shows the ion distribution profiles before and after
the post-implant annealing.

(2) Calculate the lateral diffusion length and vertical diffusion length during post-
implantation annealing
4
3 18
3 15
0
10 1
/ 10 1
/ 10 1
−
× =
×
×
=
cm atoms
cm atoms
N
N
B

Where is background concentration, is surface concentration. Considering the
skewness and kurtosis of the Gaussian profile, we assume that the surface
concentration is ~ 10
B
N
0
N
19
atoms .
3
/ cm
79
For limited-source diffusion, from Fig 4.10(b) in the reference[Jaefer, 1993], the
ratio of lateral diffusion to vertical diffusion is 2.2./2.7=0.815.
Lateral diffusion length : y
2 . 2
2
=
Dt
y
⇒ m cm cm y µ 184 . 0 10 84 . 1 10 75 . 1 4 . 4
5 2 11
= × = × =
− −

Vertical diffusion length x =(2.7/2.2)×0.184 m µ =0.23 m µ

4.2.2 Simulation of JFETs by ATLAS
Numerical simulation was used for predicting the performance of semiconductor
devices, and providing insight into the internal physical mechanisms associated with
device operation. The study used the 2-D simulator ATLAS to simulate the JFETs of
interest. This package uses Poisson’s equation along with the continuity and drift-
diffusion equations to simulate the current-voltage characteristics. The equations and
physical models for Si devices are well established. SRIM 2003 was used to simulate
the boron distribution in Si substrates after ion implantation. To activate dopants and
grow a layer of thin SiO
2
, the samples went through high temperature cycles in the
following processes which were explained above. The dopants diffused vertically
and laterally. Combined effects of ion implantation and high temperature impurity
diffusions were considered and calculated, and the final boron impurity distribution
profile was imported into the deck of ATLAS to ensure relatively realistic
simulations.

80

Si post height=0.35 µm

Fig. 4.7 Cross sectional view of our simulated Si JFET. The Si post height=0.35 µm. The
inset at the right bottom is the schematic representation of JFET-controlled CNTs emitters.

The structure of the JFET-controlled CNTs field emitter array is shown as an inset in
Fig. 4.7. CNTs were grown on Si posts on top of which Cr and Ni were patterned as
the buffer layer and catalyst layer, respectively. Extraction gates were fabricated
surrounding the CNTs. Bias on the control gate controls the PN junction. During
field emission tests, there is a positive voltage drop across the CNTs/posts. Therefore,
to simplify the JFET simulation, the CNTs were regarded as the drain of the
transistor. The different colors in Fig. 4.7 represent different doping concentrations.
81
A boron dose of 5×10
15
/cm
2
at an ion energy of 200 keV was employed in our study.
The boron distributions simulated in vertical and lateral directions are shown in Fig.
4.8 (a) and Fig. 4.8 (b), respectively. The trend and the peak of dopants are similar to
that calculated considering both the ion implantation process and high temperature
cycles, which suggests that the ion implantation parameters employed in the ATLAS
deck are reasonable. The high temperature processes are described below in the
device fabrication.

Fig. 4.8 (a) left: Simulated Boron distribution vs. distance in the vertical direction from (3.5
µm, 0 µm) to (3.5 µm, 1.05 µm) (see Fig.4.7 for the device structure). (b) right: Simulated
Boron distribution vs. distance in the lateral direction from (4.25 µm, 0.5 µm) to (7.75 µm,
0.5 µm) (see Fig.4.7 for the device structure).

82

1.E+01
1.E+02
1.E+03
1.E+04
0 10203040506070
Drain Voltage (V)
Id (A/cm
2
)
2 um
1.5 um
Vgs=0 V 1 um

Fig. 4.9 I
d
Vs. V
ds
at different Si post heights. The breakdown voltage of JFET increases as
Si post increases.

Si posts in these devices serve two purposes: to allow the flexibility in controlling
CNT length [Hsu et al., 2002] and to increase the breakdown voltage of JFETs
shown in Fig. 4.9. It was initially planned to etch 1-2 µm-high Si posts to enhance
the breakdown voltage in comparison with no Si post structure, however, the longer
the samples are in the ECR system, the rougher the resulting Si surface. On the other
hand, increase of Si post height requires the increase of SiO
2
thickness or decrease of
CNTs’ aspect ratio. Although increasing the SiO
2
thickness improves the gate
insulator’s breakdown voltage, a longer time is needed to etch SiO
2
. Cr with a
thickness of 0.1 µm beneath the photoresist AZ5214, required for the extraction gate
electrode, is found to more readily crack in the buffered oxide etch (BOE 7:1)
solution. Therefore, for these studies, a ∼0.35 µm-high Si post was etched as a proof-
of-concept.

83

1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
1.0E+03
-8 -6 -4 -2 0
Gate Voltage (V)
Id (A/cm
2
)
V
ds
=10 V
V
ds
=7V
V
ds
=5V
V
ds
=2V

Fig. 4.10 Simulated Id Vs. Vgs at Vds=0V, 2V, 5V, 7V, and 10V, respectively.

Fig. 4.10 shows the current flow through a typical Si JFET at different drain-source
voltages for a given gate-source voltage. As the gate-source is more negatively
biased, depletion regions of the pn junction extend more into the channel, and the
channel shrinks. By controlling the gate-source voltage V , one is able to control
the width of the channel through which the current is flowing, thereby controlling the
electron supply from the source to the drain. Since the diameter of Si posts is about
3.5 – 4 µm, relatively large reverse bias is needed to pinch off the channel. Fig. 4.11
and Fig. 4.12 show the current flow at different gate-source voltage when drain-
source voltage is 20 V. When gate-source voltage is more negatively biased at V =-
GS
gs
84
8V, depletion regions of pn junction extend more into the channel, and channel
shrinks. Fig. 4.12 shows less current is flowing through the channel.

Fig. 4.11 Current flowlines of the Si JFET when Vgs=0V, and Vds=20V. The arrows
represent the , i. e, the electrons flow from the source to the drain.
total
J

Fig. 4.12 Current flowlines of the Si JFET when Vgs=-8V, and Vds=20V. The arrows
represent the , i. e, the electrons flow from the source to the drain.
total
J

85
Long-channel JFETs typically show pentodelike I-V characteristics [Baliga, 1989].
That is, at higher drain voltages, the characteristics show current saturation, and the
saturated drain current is a strong function of the gate bias voltage. The saturated
drain current acts like a constant current source and supplies the missing electrons
due to field emission, thus theoretically improving the uniformity and stability of
emission current. For the convenience of our fabrication and as a proof-of-concept,
our JFET design has a small channel length in comparison to the channel width. The
drain potential in this case can penetrate into the channel [Baliga, 1989]. That may
explain why our simulated I-V curve doesn’t saturate at higher drain-source voltages
as shown in Fig.4.13. Although the integrated active device was predicted to be
effective in controlling the drain current, testing will reveal whether JFETs will
stabilize the field emission.

0.0E+00
1.0E+02
2.0E+02
3.0E+02
4.0E+02
5.0E+02
0 5 10 15 20
Drain Voltage (V)
Id (A/cm
2
)
V
gs
=0 V
V
gs
=-2V
V
gs
=-4 V
V
gs
=-6 V
V
gs
=-10 V

Fig. 4.13 Simulated Id Vs. Vds at different Vgs for the Si JFET.

86
4.3 Device Fabrication Process
There are three approaches to integrating carbon nanotubes and Si JFETs. Si JFETs
fabrication can be done before growing carbon nanotubes, or after growing carbon
nanotubes, or fabrication steps of Si JFETs and growing CNTs can be interleaved.
CNTs-first and interleaving the processes can cause the catalyst for growing CNTs
poisoned. The other resulting issue is that CNTs are easy to get damaged in liquid.
However, we know the etching process or lift-off in acetone and clean samples are
necessary in fabricating Si JFETs. Si JFETs-first is the most desirable approach since
the catalyst for growing CNTs and the grown CNTs remain intact before the field
emission measurement. One of the challenges is to choose a metal for electrodes
which could go through the final high temperature growth of CNTs at 700 ºC and
could be etched easily. Restricted by our facilities, Cr was chosen as the electrode
material of our devices and it was deposited by E-beam evaporator. Our fabrication
process developed was based on our simulation results and our current facilities. All
the fabrication steps except ion implantation were done at USC Photonics cleanroom.
Ion implantation was done in Kroko Implant Service, Tustin, CA.

4.3.1 Basic Fabrication Sequence of Si JFETs
(1) Start with n-type Si wafer. Thickness is ≈300 µm. Resistivity is 1-10 Ω.cm.
(impurity concentration is about 1×10
15
/cm
3
). The front-side of the wafer is polished,
the backside is not polished.
87

N- Si substrate

(2) Mask 1 is used to pattern 4 µm dots of Cr. The bilayer photoresist LOL2000
+S1813 is used.
Deposits Cr/Au (50 Å/0.35µm) by E-beam evaporator.
Lift-off.

Cr/Au
N- Si substrate

(3) Electron Cyclotron Resonance (ECR) Etching is used to form ~0.35-µm-high Si
posts.

N- Si substrate

Cr/Au

(4) Ion implant phosphorus (P+) to form n+ layer on the backside of the wafer.
Dose=5×10
15
/cm
2
, Energy=200 keV.
B+ implant dopes gate areas of the JFETs. Dose=5×10
15
/cm
2
, Energy=200 keV.
88

P+
N- Si substrate
Cr/Au

N+

(5). Etch Au and Cr by wet etching (The original 4 µm Si post becomes ~3.5 µm).
Grow 0.1µm nm thermal oxide: 50 min wet oxidation @ 900 ºC. The thickness
was measured by the software “FILMeasure”, and then remove it in BOE (7:1)
etchant.
The above high temperature process includes “post-implantation annealing”.

P+
N- Si substrate

N+

(6) Grow a thin layer of SiO
2
in dry O
2
and deposit ~ 1µm SiO
2
by PECVD at 350 ºC.
(After measuring the first batch of samples, we found leakage current is large. From
the second batch of samples, we first thermally grow ~0.2 µm SiO
2
in a dry-wet-dry
atmosphere, then e-beam deposit 0.5 µm SiO
2
. The detailed information is covered
in the following “Results and Discussion”).
E-beam deposit Cr electrodes on the front side of the sample (0.1 µm), then use
mask 2 to etch Cr on the edge and between the extraction gate and control gate. Or:
*Use mask 2 to pattern the area for Cr, deposit 0.1µm Cr and do lift-off.
89

N- Si substrate

SiO
2
Cr
P+

N+

(7) Mask 3 is used to pattern the areas for JFET control gates with the photoresist
AZ5214; Wet etch SiO
2
; Deposit 0.1 µm Cr, then do lift-off.

N- Si substrate

SiO
2
Cr
P+

N+

(8) Deposit Cr (0.1 µm) on the backside of the N+ region.

N- Si substrate

SiO
2
Cr
P+

N+

90
(9) The sample is annealed in the forming gas for about 30 s at 450 °C to form ohmic
contacts.

N- Si substrate

SiO
2
Cr
P+

N+

(10) Mask 3 is used to open the 2-µm circular areas for growth of CNT emitters. The
bilayer photoresist LOL2000 +S1813 is used.

N- Si substrate
SiO
2
Cr
P+
PR

N+

(11) Apply PR on the backside of the sample to protect the electrodes from Cr
etchant, then wet etch Cr on the front side.

91

N- Si substrate
SiO
2
Cr
P+
PR

N+

(12) Wet etch SiO
2.

N- Si substrate

SiO
2
Cr
P+
PR

N+

(13) Deposit Cr/Ni (40nm/20nm) for growing vertically aligned CNTs.

N- Si substrate

Cr/Ni SiO
2
Cr
P+ PR

N+

92
(14) Do lift-off.

N- Si substrate

Cr/Ni SiO
2
Cr
P+

N+

(15) Grow carbon nanotubes at 700 °C with acetylene and ammonia by plasma
enhanced chemical vapor deposition (PECVD).
N- Si substrate

Cr/Ni SiO
2
Cr
P+
CNTs

N+

4.3.2 Main Fabrication Processes
4.3.2.1 Photolithography and lift-off
Photolithography is used to transfer patterns from masks to the photoresist on the
surface of wafers. Standard photolithography technique — contact printing, was used
in our experiments. The first photolithography and the last one need to achieve a
linewidth of 2 µm in the device. Shipley 1800 series can achieve a linewidth of
0.48µm shown in Fig. 4.14.
93

Fig. 4.14 0.5 µm and 0.48 µm were defined by Shipley 1813 using the standard
photolithography [www4.4].

The first photolithography and the last one were used to serve lift-off process. To
achieve a good lift-off, it is necessary to have a clear separation between the
deposited film on the top of the resist surface and the film on the substrate surface in
the opened pattern areas. Conventionally it can be done by three approaches. The
first way is to choose a negative photoresist which will creat a negative slope for
good lift-off. The second way is to use an image reversal process which turns a
positive slope into negative by reversing everything. A third way is to use a double-
layer photoresist system where the bottom layer provides a separation between the
film on the sidewall of the first layer of photoresist and the film on the opened
substrate areas [www4.5; www4.6]. Shipley 1813 (S1813) is a positive photoresist
and it creates a positive slope, so it alone is not appropriate for achieving a good lift-
off in small-feature-size device. As far as we know, S1813 is hard to achieve an
image reversal process. Therefore a double-layer photoresist process, involving
94
S1813+LOL2000, was developed for our purpose. The LOL-2000 is a non-
photosensitive material which dissolves in photoresist developer in a controlled way.
It is placed under the normal photoresist. After the photoresist is fully developed and
the dissolution of the photoresist stops, the developer continues to dissolve the LOL-
2000 layer in the open areas and further in under the resist edge, producing the

(a) Spin LOL2000 and S1813 (b) Pattern and develop PR
S1813 LOL2000
Metals Substrate

(c) Deposit metals by E-beam
evaporator
(d) Lift-off

clearance necessary for lift-off. Dissolution rate is dependent on baking temperature
and time. Our developed photolithography and lift-off process are as follows:

(a) Photolithography
Clean samples, dehydration bake the samples for 2 min and let it cool down
(1) LOL2000: 500rpm+3s, 3krpm+30s
95
Thickness: 0.2 µm
(2) Prebake at 140 ºC for 5 min on the hotplate
(3) S1813: 500rpm+3s, 5krpm+30s
Thickness: 1.3 µm
(4) Prebake: 110 ºC for 2 min on the hotplate
(5) Remove PR on the backside
(6) Exposure: 80 mJ/cm
2
= 4mW/cm
2
×20 s
(7) Develop in MF321: 48s – 1min 20s
(8) Oxygen descum: 60W/200mT/30s
(9) Deposit metals by an E-beam evaporator

(b) Lift-off
(1) Immerse the samples in acetone for 30-60min
(2) Use a syringe to help lift-off
(3) Remove LOL2000 in the developer MF321 for 10-20s
(4) Clean the samples with acetone, methanol, isopropanol, DI water and blow it
dry.
By following the above fabrication steps developed by us, after the lift-off of the
metal, a 2-µm feature size is well defined which is shown in Fig. 4.15. The thinnest
finger pattern has a width of 2 µm.

96

Fig. 4.15 The thinnest finger pattern of the alignment marks has a width of 2 µm which is
well defined by using a bilayer resist LOL2000 + S1813 and lift-off.

4.3.2.2 ECR etching of Si posts and O
2
descum influence on ECR etching
Our masks were designed to etch a 0.3 µm- to 0.8 µm-high Si post to test the concept
of the whole device. There are RIE (Reactive Ion etching) and ECR (Electron
Cyclotron Resonance) available at USC cleanroom. Conventional rf RIE processes
can cause higher surface damage in comparison to ECR since ECR plasma etching
has higher reactive ion density, lower ion energy and lower working pressure. BCl
3

and Ar are used to etch Si. BCl
3
is a reactive gas which reacts with Si. Ar is used to
bombard the surface to remove the polymer product produced by BCl
3
and Si. The
flowrates of BCl
3
and Ar are set to be 20 sccm and 10sccm in our etching,
respectively. The actual value is 17.2 sccm BCl
3
and 7.7 sccm for Ar. A higher
power increases the etching rate, it also increases the surface damage. After
97
optimizing our etching process, the microwave power used is 300 W and RF Power
is 60-65 W. The chamber pressure during etching is about 4mTorr.

Fig. 4.16 The SEM images show the Si posts after ECR etching (a) without O
2
descum (the
top image), and with O
2
descum (the bottom image).

The quality of ECR etching on the vertical walls of Si posts was not only affected by
the lift-off quality, it is also affected by O
2
descum process after development. Fig.
98
4.16 demonstrates that O
2
descum process plays an important role in determining the
quality of vertical walls of Si posts.

4.4 Results and Discussion of First Batch of Samples
Studies were conducted to understand CNT growth activity from various pairings of
buffer layers and transition metal catalyst layers by PECVD [Cassell et al., 2004]. It
was found that the catalyst layer Ni and its underlayer Cr showed a high activity and
good growth quality. Based on this research, A 40nm-thick Cr layer was e-beam
deposited as a buffer layer which would prevent the diffusion / reaction of the
catalyst with Si. Then a 20-nm thick Ni layer was e-beam deposited as the catalyst.
The catalyst Ni first went through a pretreatment in an ammonia ambient using hot-
filament heating. The Ni film separated into small islands. Acetylene was added into
the growth chamber and the pressure was adjusted to 4 Torr. The DC plasma was
ignited for 1-2 mins. Detailed growth conditions can be found in [Cassell et al., 2004;
Cruden et al., 2003; Meyyappan et al., 2003].

Multiwall carbon nanotubes were successfully grown on the devices by Dr. Cassell
in NASA Ames Research Center, CA. All the emitter sites are spaced 15 µm from
center to center. Fig. 4.17 shows CNTs grown on 100 × 100 array field emitter sites.
The growth time is 115 seconds. Statistically, CNTs’ length in the center varies from
99
700-900 nm, and the diameter varies from 50-90 nm. CNTs near the edge have a
relatively large height variation, from 50nm to 600nm,

60º View

Fig. 4.17 CNTs were grown on 100 × 100 array emitter sites by PECVD at 700 ºC for 115 s.

85º View
60º View

Fig. 4.18 CNTs were grown on 50 × 50 array emitter sites by PECVD at 700 ºC for 80 s.

100
and their diameters vary from 15nm to 40 nm. The growth time is 80 seconds for a
50 × 50 emitter array shown in Fig. 4.18. SEM images suggest a clean growth with
clean delineation between the extraction gate and the CNTs.

Fig. 4.19 Schematic diagram of the device testing setup.

After Dr. Cassell finished growing CNTs on the devices, the samples were shipped
to Dr. Shaw at NRL for testing. A DC testing arrangement was employed for initial
studies, conforming to previous studies of cathode emission characteristics. Fig.
4.19 shows a schematic diagram of the device testing setup. Detailed testing
conditions can be found in [Hsu et al., 2002]. V , V , and V represent the anode,
control gate, and extraction gate voltages, respectively. The anode is a tungsten wire,
which is 1-2 mm above the CNTs. The anode voltage varies from 100 V to 600 V,
and the extraction gate voltage varies from 17 V to 50 V. Fig. 4.20 shows our
preliminary test results of emission current on a 50 × 50 emitter array at an anode
voltage of 300 V. The emission current is ~3 µA at V =50 V and V =0, and the
corresponding current density is ~40 mA/cm
a c ext
ext c
2
. At very low extraction gate voltages
101
(< 25V), field emission phenomenon barely occurs, corresponding to the flat tail of
the inset in Fig. 4.20. The linear relationship between ln( and 1 is consistent
with a Fowler-Nordheim tunneling model [Fowler et al., 1928; Spindt, 1968]. I-V
characteristics were measured by sweeping the extraction gate voltage. All the I-V
plots in Fig. 4.21 showed a bit of hysteresis. The higher currents were obtained when
the extraction gate voltage was being reduced, and the lower currents at the same
gate voltage were obtained when the extraction gate voltage was rising. We suggest
that the nanotubes become hot, and this improves the field emission. Fig. 4.22 shows
the emission current almost increases linearly as anode voltage increases.
) /
2
V I V /

20 25 30 35 40 45 50
1x10
-11
1x10
-10
1x10
-9
1x10
-8
1x10
-7
1x10
-6
1x10
-5

Anode Current (A)
Extraction Gate Voltage (V)
-3 0
-2 8
-2 6
-2 4
-2 2
-2 0
0 0 .0 2 0 .0 4 0 .0 6
1/V g
Ln(I/Vg
2
)
Fig. 4.20 Emission current of CNTs on a 50×50 array as a function of the extraction gate
voltage at anode voltage of 300 V. Inset corresponds to Fowler-Nordheim (F-N) plot of the
emitter array.

102

20 25 30 35 40 45
1x10
-9
1x10
-8
1x10
-7
1x10
-6
1x10
-5
Anode Current (A)
Extraction Gate Voltage (V)

Fig. 4.21 Emission current Vs. Extraction gate voltage. All the I-V plots show a bit of
hysteresis.

0 100 200 300 400 500 600
1x10
-9
2x10
-9
3x10
-9
4x10
-9
5x10
-9
6x10
-9
7x10
-9
Anode Current (A)
Anode Voltage (V)

Fig. 4.22 Emission current as a function of anode voltage. The extraction gate voltage was
held constant at 27 V.

The field emission results shown above did not consider the influence of the control
gate in the device. One of the ultimate goals of this research is to study how the
emission current will be affected and controlled by the active device, JFETs. That is,
103
to see if the uniformity of field emission will be improved by JFETs. Based on
semiconductor physics and our simulation results, as control gate is more negatively
biased, the channel through which the current flows shrinks, and fewer electrons will
be supplied to the CNTs. Therefore, less emission current should be expected. Our
test in Fig. 4.23 shows the opposite. Later we test the p+/n junction of the device, we
found that the junction shows a resistor-like I-V characteristics. This may be related
to the heavy damage caused by our first ion implantation process and ECR etching,
since our second batch of samples show a diode-like I-V curve.

20 25 30 35 40 45 50
1x10
-11
1x10
-10
1x10
-9
1x10
-8
1x10
-7
1x10
-6
1x10
-5
Control Gate Voltage
-6
-4
0

Anode Current (A)
Extraction Gate Voltage (V)

Fig. 4.23 Anode current Vs. the extraction gate voltage at different control voltages.

While testing the field emission of the first batch of samples, we found that the
extraction gate current was on the scale of mA. High extraction gate current suggests
104
that the SiO
2
deposited is quite leaky. It restrains us from applying higher extraction
gate voltage.

By testing our first batch of samples, we got the field emission from the carbon
nanotubes. It also indicates that the fabrication procedure developed based on our
existing cleanroom facilities is workable. The arising new issues are to make p+/n
junctions work and to improve the quality of SiO
2
.

4.5 Results and Discussion of Second Batch of Samples
To reduce the leakage current of the extraction gate, we first largely reduce the
extraction gate metal area of the second batch of samples. In addition, a 0.2 µm thick
SiO
2
layer was grown in a dry-wet-dry atmosphere at 900 ºC for 1.5 hr, then 0.5 µm
0 2040 608
0
1x1 0
-10
2x1 0
-10
3x1 0
-10
4x1 0
-10
Current (A)
V oltage (V )
0 0 20406080
0
5x 1 0
-11
1x 1 0
-10
1x 1 0
-10
2x 1 0
-10
2x 1 0
-10
Current (A)
V o ltage (V )
Fig. 4.24(b) The leakage current of SiO
2
for 10×10 emitter array.
Fig. 4.24(a) The leakage current of SiO
2
for 4×4 emitter array.

105
0 2040608
0
5x10
-10
1x10
-9
1x10
-9
2x10
-9
2x10
-9
3x10
-9
3x10
-9
4x10
-9
Current (A)
Vo ltag e (V )
0
0 2040 608
0
4x10
-10
8x10
-10
1x10
-9
2x10
-9
Current (A)
Voltage (V)
0
Fig. 4.24(d) The leakage current of SiO
2
for 100×100 emitter array.

Fig. 4.24(c) The leakage current of SiO
2
for 50×50 emitter array.

thick SiO
2
was e-beam deposited. The gate leakage currents of different emitter
arrays were measured using a semiconductor parameter analyzer. The leakage
current is less than 0.4 nA both on 4 × 4 array and 10 × 10 emitter arrays shown in
Fig. 4.24 (a) and Fig. 4.24 (b), and is less than 4 nA on 50 × 50 and 100 × 100
emitter arrays in Fig. 4.24 (c) and Fig. 4.24 (d) at an extraction gate voltage of 80 V.
We also measured the leakage current of 1 µm thick SiO
2
deposited by the new
PECVD at UCLA, it is also on the nA at 80V. That is another choice to consider for
the future fabrication

As we know from the test results of the first batch of devices, p+/n junctions work
like resistors. We measured the I-V curve of pn junctions for the second batch of
106
samples, it shows a diode-like performance. Under the microscope, from the color,
we can tell this time p+ region has less damage than the previous devices, either
because the height of Si post etched by ECR decreases from 0.7µm to 0.35 µm, or
because less damage was introduced during the ion implantation. An I-V curve for
the p+/n diode was measured before CNT growth. The reverse saturation current
shown in Fig. 4.25 for 50 × 50 array is 200 µA at –4V and 52 µA at –2V. The
forward current is 44 mA at 2V.
-4 -2 0 2
0
1x10
-2
2x10
-2
3x10
-2
4x10
-2
5x10
-2
Current (A)
Voltage (V)
Fig. 4.25 I-V characteristics of p+/n junction for 50×50 array measured before CNT growth.

Our emission tests of the second batch of samples show no field emission. Our first
guess was maybe the CNTs were shorted with the surrounding extraction gate. The
SEM images taken before sending the samples to Dr. Cassell for CNT growth show
the gaps between the Si posts and the extractions are about 2 µm, whereas the
maximum our grown CNT length is about 1 µm. This doesn’t support our guess. In
addition, Dr. Shaw in NRL measured the leakage current of SiO
2
as low as nA at 80
further proves that there is no such short. After we get the devices back, we checked
107

ig. 4.26 SEM images show that CNTs were barely grown on 4×4 emitter sites of the
cond batch of devices.
ig. 4.27 SEM images show no CNTs were grown on 100×100 emitter sites of the second
atch of devices. Most of the emitter sites were damaged by plasma arcing during CNT
rowth.

F
se

F
b
g

108

SiO
2
breakdown in 4×4 array

ig. 4.28 SEM images indicate that plasma arcing caused SiO2 breakdown during SiO
2
.
e devices under SEM. We found that CNTs were barely grown on 4×4 array shown
of
samples. No CNTs were grown on other arrays, such as 100×100 array shown in Fig.
4.27. Plasma arcing not only damaged some areas of the emitter sites but also SiO
which is shown in Fig. 4.28. We guess the failure of CNTs growth this time is that
the oxide is now very good relative to the first batch, and the metal-covered area was
reduced. Because there are no shorts between the substrate and the gate metal, the
path for current to flow between the substrate and plasma have now been effectively
blocked. In addition, this time we changed the catalyst thickness from 20 nm to 10
nm. We are a little concerned that reduced thickness may also contribute to the non-
CNT growth using the same growth conditions as those for 20 nm-thick nickel. To
narrow down the adverse factors, we will keep the same thickness of Cr/Ni
(40nm/20nm) as that on the first batch of samples. To avoid this plasma arcing issue

F

th
in Fig. 4.26. The quality of CNTs was not as good as those on the first batch
2
109
this study, we have designed and fabricated a novel carbon nanotube field emitter
orating vertical JFETs at each micron-scale emitter site to
in the future, a method is being investigated that will use another mask to deposit Cr
to cover most of the exposed SiO
2
area, and ground it along with extraction, control
gates in the place which is 3mm away from the emitter arrays. After CNT growth,
the ground node can be removed or wet etched.

4.6 Conclusion
In
array cathode incorp
control the local emission current. The JFETs have the potential to control the
maximum emission current at each aperture, improving the scalability of the total
emission current and improved uniformity. The fabrication steps were designed and
developed to be compatible both with JFET manufacturing and CNT growth at 700
ºC. MWCNTs were successfully grown on the built-in Si JFETs. The preliminary
field emission test shows that the linear relationship between ln(I/V
2
) and 1/V is
consistent with Fowler-Nordheim tunneling theory. Further study will explore the
emission current modulation by the control gate voltage both DC and pulsed modes.

110

Chapter 5

Summary and Future Work

This thesis mainly addresses two import topics which has potential applications in
pulsed power technology: (1) Design, Simulation and Evaluation of 4H-SiC Vertical
Junction Effect Transistors; (2) Actively controlled-Carbon Nanotube (Si JFET-
controlled) Field Emitter Cathode Arrays.

(1) 4H-SiC Vertical Junction Effect Transistors
SiC is a promising material for high temperature and high power applications due to
its superior properties. ATLAS was used in our study to simulate how the device
electric characteristics change with the different design parameters theoretically. The
results provide guidelines on the optimization of the device based on our application.
To model the 4H-SiC VJFETs in pulsed power circuits, the necessary parameters
were extracted from the simulated electrical characteristics of the device for circuit
simulation program such as SPICE. Simulation and device modeling are two
important approaches, which could be used as a test bench without fabricating the
111
devices to minimize the unnecessary cost. Our study investigated fundamental
limitations of 4H-SiC material and our novel VJFET device structure. The device
demonstrated a 8kV-breakdown-voltage and several ns switching speed, showing
that 4H-SiC VJFETs are promising in the future pulsed power applications.

To more accurately predicate SiC device performance, further experimental and
theoretical work are required to perfect the models in the simulation. For example,
some experimental data for generation-combination models, impact ionization
coefficients at high temperatures, and carrier-carrier scattering at high current ratings
are still not complete. With the development of bulk growth and epitaxy of SiC as
well as the device technology, more accurate simulation and model becomes possible,
which will boost the SiC device technology as a return.

(2) Si JFET-Controlled CNT Field Emitter Cathode Arrays
For the first time, carbon nanotube field emitter cathode arrays were integrated with
the conventional Si JFET in this study. It includes the design and simulation of Si
JFET, mask design, process flow development, CNT growth and device testing. Our
preliminary test results show field emission from those CNTs on the Si posts. To
evaluate if Si JFET will improve the uniformity and stability of the emission current
eventually, we need figure out a way to avoid plasma acing during CNT growth
since plasma arcing prevents CNT growth, damages emitter arrays, and deteriorates
the quality of SiO
2
and performance of p+/n junction.
112
If the prototype of this Si JFET-controlled CNT field emitter cathode works, next
step is to increase the emission current density to several A/cm
2
. Further work can be
mainly carried on in the following three directions:

(a) Device Redesign and Fabrication Process
To some extent, the dimensions and fabrication process of Si JFET-controlled CNT
emitter cathode prototypes were designed to fit the existing facilities in the USC
cleanroom. As a proof of concept, the height of Si posts of our prototype is ~ 0.35
µm. Based on our simulation results, the breakdown voltage of Si JFET increases
with the height of Si posts. If time and the funding allows, deep RIE could be used to
easily etch several µm deep trench with less surface damage.

The diameter of Si post is designed to be 4 µm for relatively easy fabrication. A
good contact aligner can reduce the diameter to 1-2 µm in the future work. It has
several advantages: First, less diameter means narrower channel width, less reverse
bias on pn junctions is needed to pinch off the channel through which the current
flows. Secondly, less ion implantation energy is needed to implant the boron to form
p+ region since less lateral projected range of the ions is required.

To reduce the leakage current of extraction gates, a layer of 0.2 µm-thick thermally-
grown SiO
2
is sandwiched between 0.5 µm PECVD-deposited SiO
2
and Si substrates.
113
SiO
2
deposited by our old PECVD system is quite leaky, and its role is to increase
the gate height so that CNTs could be as long as 1 µm. Although increasing the
thickness of thermal SiO
2
would increase the gate height and allows applying higher
extraction gate voltage, it has several resulting disadvantages: (1) consumes the
depth of p+ region; (2) allows longer time to wet-etch SiO
2
. Cr deposited by E-beam
evaporator is more easily to crack in BOE (Buffered Oxide Etchant). Etching SiO
2
in
BOE isotropic, thicker SiO
2
means larger undercut. Cr on SiO2 sticking out is more
easily to crack at large electric field strength. One possible approach is to deposit
several µm-thick SiO
2
by using a PECVD (which can produce high quality SiO
2
).
Then etch it later in some areas with deep RIE in a controlled way so that only a thin
layer of SiO
2
is left and the rest can be etched away in BOE. Usually the gases etch
SiO
2
also etch Si (the etching speed is different, though), it is not easy to stop etching
before the gas etches Si. It is easier to leave a thin layer of SiO
2
to be wet-etched.

(b) MWCNT growth
The distance between carbon nanotubes and CNT height relatively to the extraction
gates greatly influence field emission currents. Screening of the equi-potential lines
of dense CNTs were observed [Milne et al., 2004]. This electric field shielding
effects can be minimized by having individual vertically aligned tubes spaced apart
by twice their height. Future work is needed to investigate and optimize MWCNT
growth on different thickness of Ni catalyst material. Controlling CNT growth height
is also important. If CNT is too high above the extraction gates or too low below the
114
extraction gate, less electric field is on the CNT tip and thus less field emission
current. A balance of the CNT height can be first be simulated or modeled to provide
some guidelines for the real experiments.

(c) Device Testing
A lot of research has been done on DC measurements of the field emitters. The
ultimate goal of this research is to evaluate and test if Si JFET-controlled CNT could
be used as a cold cathode in pulsed power application, providing uniform, stable and
high emission current. Future work is needed to test the emission current in pulse
modes.
115

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Abstract (if available)

Abstract This thesis is focusing on a study of junction effect transistors (JFETs) in compact pulsed power applications. Pulsed power usually requires switches with high hold-off voltage, high current, low forward voltage drop, and fast switching speed. 4H-SiC, with a bandgap of 3.26 eV (The bandgap of Si is 1.12eV) and other physical and electrical superior properties, has gained much attention in high power, high temperature and high frequency applications. One topic of this thesis is to evaluate if 4H-SiC JFETs have a potential to replace gas phase switches to make pulsed power system compact and portable. Some other pulsed power applications require cathodes of providing stable, uniform, high electron-beam current. So the other topic of this research is to evaluate if Si JFET-controlled carbon nanotube field emitter cold cathode will provide the necessary e-beam source.

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Asset Metadata

Creator Shui, Qiong (author)

Core Title A study of junction effect transistors and their roles in carbon nanotube field emission cathodes in compact pulsed power applications

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Materials Science

Defense Date 12/05/2006

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag junction field effect transistors (JFETs),OAI-PMH Harvest

Language English

Advisor Gundersen, Martin A. (committee chair), Goo, Edward K. (committee member), Kim, Eun Sok (committee member)

Creator Email qshui@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-m303

Unique identifier UC1436272

Identifier etd-Shui-20070228 (filename),usctheses-m40 (legacy collection record id),usctheses-c127-310870 (legacy record id),usctheses-m303 (legacy record id)

Legacy Identifier etd-Shui-20070228.pdf

Dmrecord 310870

Document Type Dissertation

Rights Shui, Qiong

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Repository Name Libraries, University of Southern California

Repository Location Los Angeles, California

Repository Email cisadmin@lib.usc.edu