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Test generation for capacitance and inductance induced noise on interconnects in VLSI logic

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Test generation for capacitance and inductance induced noise on interconnects in VLSI logic

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Content TEST GENERATION FOR CAPACITANCE AND INDUCTANCE INDUCED NOISE
ON INTERCONNECTS IN VLSI LOGIC
by
Arani Sinha
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2006
Copyright 2006 Arani Sinha
ii
Dedication
To my parents,
Asok and Basabdatta
iii
Acknowledgments
I would like to thank Prof. Melvin A. Breuer and Prof. Sandeep K. Gupta for serving
as my dissertation research advisors, for their insights and their careful attention to detail
that helped shape this work and for their support during my stay in graduate school. I
would also like to thank Prof. Kenneth Alexander, Prof. Won Namgoong and Prof. Mas-
soud Pedram for participation in my dissertation and qualifying examination committees.
Thanks to my colleagues at USC for their friendship during our time in graduate
school. They are Aiguo, Chenhuan, Dhiraj, I-de, Ishwar, Lei, Liang-chi, Nabil, Roger,
Seelan, Shahdad, Shahin, Suhrid, Suriya, Wei-Yu, Yi-Shing, and Zhi-gang. What I cherish
most from those times are the lively technical discussions that helped me develop my abil-
ities as a researcher. Fortunately for me, those discussions continue even today.
I worked on crosstalk and on-chip inductance during my summer internships at Intel
and Motorola. I was introduced to the area of inductance at Intel. I would like to thank
Salim Chowdhury, T. M. Mak and Mohiuddin Mazumder for guidance in those areas. I
would like to thank Prof. Antonio Rubio at Universitat Politecnica de Catalunya, Barce-
lona for his many helpful comments on this work. I would like to thank UMC for allowing
me to use 130 nm process data for my simulation studies. Thanks also to Erik Jan Marinis-
sen for being my mentor at Philips, Eindhoven. I would also like to thank my managers
and colleagues at Cadence for providing me the flexibility to work on the many drafts dur-
ing the final stages of this work.
Attending graduate school took many years of preparation and I am fortunate to have
been influenced by so many people who helped me grow. Unfortunately, lack of space will
iv
allow me to thank only a few of my teachers and friends. I would like to thank Sr. Titus
who taught me at Holy Cross School, Silchar, and Ajit Sengupta, Amol Maharaj, and the
late Ajit Chatterjee who taught me at Ramakrishna Mission Vidyalaya, Narendrapur. I
would like to thank Bhargab Bhattacharya and Subhas Nandy, my M. Tech. thesis advisors
at Indian Statistical Institute, Kolkata, and Debashish Bhattacharya and Jean-Marc
Delosme, who taught me at Yale University, New Haven. I would like to thank Anindya,
Arindam, Krishnendu, Sanjay, Sayan, Shamik and Subir and my other buddies from the
days at Jadavpur University, Kolkata. Thanks to Debashree, Koushik and Milind, who
were my classmates at Indian Statistical Institute, Kolkata.
I would also like to thank Om, Prokriti, Sripad, Surajeet and the rest of the gang for
creating the comforts of a home away from home at Bonsallo Avenue, Los Angeles, where
I lived for the most part of my graduate career. Thanks to Alex who unfortunately will not
see the completion of this task. Thanks to Anjana-di, Photon, Rana, Sangita, Santosh, and
Soumya-da for many a word of encouragement. Thanks also to the Dining Philosophers
especially Diogenes, Ebru, Erin, Hendrik, Mohammed and Peyman, for the cheerful dis-
tractions. Thanks to Manishita for being a true compadre.
I would like to convey my gratitude to Bhaskar, Brinda and Nikhil for considering me
a member of their family, for the frequent dinners and endless chats that have nourished
my body and soul, and for the unwavering support and encouragement without which this
work would probably not have seen the light of day.
I would like to express my gratitude to my family. Thanks to my many uncles and
aunts and cousins who never gave up their faith in me. I would like to thank my brother,
Anustup, and my sister, Atasi, for being the affectionate siblings that they are. Talking to
v
my nieces, Aditi and Shreya, always makes my day! I would especially like to thank my
parents, Asok and Basabdatta, for their undying love and support during those difficult
graduate school years. My parents continue to inspire me by their lives. Coming as they do
from the academic world themselves, they brought me up with a love for academics. They
taught me to dream and to reach out for those dreams. It is to them that I dedicate this
work.
vi
Table of Contents
Dedication............................................................................................................................ii
Acknowledgements............................................................................................................iii
List of Tables.......................................................................................................................ix
List of Figures.....................................................................................................................xi
Abstract..............................................................................................................................xv
Chapter 1: Introduction.....................................................................................................1
1.1 Physics of capacitance and inductance ........................................................1
1.2 Origin of interconnect capacitance and inductance .....................................3
1.3 Inductance modeling and extraction ............................................................7
1.4 Technology trends........................................................................................9
1.5 Previous Work............................................................................................12
1.5.1 Test generation for crosstalk noise.................................................12
1.5.2 On-chip inductance ........................................................................14
1.6 Scope of dissertation..................................................................................14
Chapter 2: An enhanced test generation system for crosstalk delay faults..................19
2.1 Introduction................................................................................................19
2.2 Background................................................................................................20
2.2.1 Delay and timing computations .....................................................20
2.2.1.1 Delay model...................................................................................20
2.2.1.2 Arrival and required time...............................................................21
2.2.1.3 Timing simulation for specified input values.................................23
2.2.2 Crosstalk test generation................................................................24
2.2.2.1 Overview........................................................................................24
2.2.2.2 Test generation algorithm ..............................................................25
2.3 Motivation..................................................................................................27
2.3.1 Enhanced propagation conditions..................................................27
2.3.1.1 Transitions......................................................................................27
2.3.1.2 Hazards ..........................................................................................27
2.3.2 Timing conditions for fault propagation ........................................28
2.4 9-valued algebra.........................................................................................29
2.5 Timing analysis..........................................................................................31
2.5.1 Timing ranges for hazards..............................................................31
2.5.2 Example .........................................................................................33
2.5.3 Crosstalk delay effect.....................................................................34
2.6 Logic propagation conditions ....................................................................35
2.6.1 Factors affecting propagation.........................................................35
vii
2.6.1.1 Hazards ..........................................................................................36
2.6.1.2 Transitions......................................................................................37
2.6.2 New propagation conditions ..........................................................38
2.6.2.1 Fault effect propagated as transitions.............................................38
2.6.2.2 Fault effect propagated as transitions and static hazards ...............40
2.7 Timing conditions for propagation ............................................................41
2.7.1 Timing conditions ..........................................................................41
2.7.2 Conditions for algorithm termination ............................................44
2.8 Undetectability of faults.............................................................................44
2.9 Experimental results...................................................................................45
2.10 Conclusion .................................................................................................50
Chapter 3: A complete test generation system for crosstalk delay fault effects...........51
3.1 Introduction................................................................................................51
3.2 Motivation..................................................................................................52
3.2.1 Need for a new algebra ..................................................................52
3.2.2 Need for modifications to test generation algorithm......................56
3.2.2.1 Extensions required for new algebra..............................................56
3.2.2.2 Extensions required for timing issues............................................57
3.3 Proposed algebra........................................................................................59
3.3.1 Factors influencing choice of algebra ............................................59
3.3.1.1 Basis values:...................................................................................60
3.3.1.2 Conditions for propagating crosstalk delay as transitions .............61
3.3.1.3 Conditions for propagating crosstalk delay as static hazards ........62
3.3.1.4 Test generation method ..................................................................62
3.3.2 Truth tables for multi-valued algebra.............................................63
3.3.3 Timing ranges for composite values ..............................................64
3.3.4 Timing computation for multi-valued algebra ...............................64
3.3.5 Transitive closure ...........................................................................67
3.3.5.1 Propagation by transitions only .....................................................67
3.3.5.2 Propagation by transitions and static hazards ................................68
3.3.5.3 Timing based closure .....................................................................69
3.4 Algorithm for test generation.....................................................................71
3.4.1 Modified search procedure.............................................................71
3.4.1.1 Proof of correctness .......................................................................72
3.4.1.2 Search complexity..........................................................................74
3.4.2 Backtracing procedure based on depth first search........................75
3.4.3 Converting Type B fault effect to Type A fault effect....................80
3.4.4 Timing based resolution of logic values ........................................87
3.5 Experimental results...................................................................................91
3.6 Conclusion ...............................................................................................100
Chapter 4: Inductance induced noise on single interconnects....................................101
4.1 Circuit Model...........................................................................................101
viii
4.2 Motivation................................................................................................102
4.2.1 Oscillatory noise ..........................................................................102
4.2.2 Noise Effects................................................................................106
4.3 Process Variation......................................................................................111
4.4 Interconnect length...................................................................................112
4.5 Impact of edge-rate ..................................................................................114
4.6 Analytical Model of noise........................................................................115
4.7 Test and Validation issues ........................................................................118
4.7.1 Test Generation Example.............................................................119
4.7.2 Need for a new test methodology ................................................121
4.8 Conclusions..............................................................................................122
Chapter 5: Inductance Induced Noise on Adjacent Interconnects.............................124
5.1 Introduction..............................................................................................124
5.2 Experimental setup..................................................................................125
5.3 Inductance induced noise........................................................................130
5.3.1 Crosstalk pulse.............................................................................130
5.3.2 Crosstalk slowdown and speedup ...............................................132
5.3.3 Combination of oscillatory noise and crosstalk..........................137
5.4 Interconnect length..................................................................................138
5.5 Signal edge-rate and skew.......................................................................139
5.6 Spot defect and process variation.............................................................142
5.7 Dependence on logic values on adjacent lines.........................................144
5.8 Conclusion: Results in terms of test and validation.................................149
5.8.1 Motivation for the test generation problem for inductance
induced noise...............................................................................149
5.8.2 Noise and delay characteristics for test vector
determination...............................................................................150
Chapter 6: Future Work................................................................................................152
6.1 Timing analysis........................................................................................152
6.2 Test generation .........................................................................................152
6.2.1 Learning algorithms.....................................................................152
6.2.2 Propagation conditions for pulse and oscillatory noise ...............153
6.2.3 Test generation for validation ......................................................154
6.3 Modeling for inductance induced noise...................................................156
6.3.1 Analytical model for noise computation......................................156
6.3.2 Analytical model for oscillatory noise propagation.....................156
Bibliography....................................................................................................................158
ix
List of Tables
TABLE 1-1. Projections from SIA Roadmap [52] ...........................................................9
TABLE 2-1. AND operation for 9-valued algebra .........................................................31
TABLE 2-2. OR operation for 9-valued algebra.............................................................31
TABLE 2-3. NOT operation for 9-valued algebra..........................................................31
TABLE 2-4. Timing information associated with each logic value................................33
TABLE 2-5. Fault coverage for Type A faults................................................................46
TABLE 2-6. Fault coverage on 10 faults with 1 million backtrack limit .......................47
TABLE 2-7. Average computation time for detected faults ...........................................48
TABLE 2-8. Fault coverage for Type B faults................................................................48
TABLE 2-9. Fault coverage with zero delay ..................................................................49
TABLE 3-1. Basis for the algebra...................................................................................60
TABLE 3-2. Propagation conditions for fault effects as transitions ...............................61
TABLE 3-3. Propagation conditions for fault effects as transitions and static
hazards.......................................................................................................62
TABLE 3-4. Other initial composite values ...................................................................62
TABLE 3-5. AND operation for elements in basis.........................................................63
TABLE 3-6. OR operation for elements in basis............................................................63
TABLE 3-7. NOT operation for elements in basis .........................................................64
TABLE 3-8. 57 valued algebra .......................................................................................68
TABLE 3-9. Additional values in 73 valued algebra......................................................68
TABLE 3-10. Logic objectives to increase min arrival time (NAND output) ..................83
x
TABLE 3-11. Conditions that trigger timing based logic resolution................................88
TABLE 3-12. Timing objectives.......................................................................................91
TABLE 3-13. Type A Fault coverage comparison............................................................92
TABLE 3-14. Undetectable faults.....................................................................................92
TABLE 3-15. Increase in fault coverage due to timing procedure ...................................94
TABLE 3-16. Search spaces covered................................................................................94
TABLE 3-17. Computation time (in seconds) ..................................................................95
TABLE 3-18. Computation time of sub-procedures.........................................................95
TABLE 3-19. Summary of fault coverage from XGEN-E and XGEN-C ........................96
TABLE 3-20. Comparison on equal runtime basis...........................................................96
TABLE 3-21. Type A fault coverage with random exploration of solution space............97
TABLE 3-22. Type B fault coverage with random exploration of solution space............98
TABLE 3-23. Summary of fault coverages from random exploration .............................99
TABLE 4-1. Projections from SIA Roadmap...............................................................104
TABLE 4-2. Some parameters from MOSIS process files. ..........................................104
TABLE 4-3. Characteristics at the FE of the line. ........................................................107
TABLE 4-4. Impact of process variation -- Example 1 ................................................111
TABLE 4-5. Impact of edge-rate on undershoot ..........................................................115
TABLE 4-6. Comparison of SPICE simulation and model. .........................................118
xi
List of Figures
FIGURE 1-1. The charging of a capacitor..........................................................................2
FIGURE 1-2. A current produces a flux φ..........................................................................3
FIGURE 1-3. Interconnect structure...................................................................................4
FIGURE 1-4. An example showing the return paths..........................................................5
FIGURE 1-5. Magnitude of current at receiver input.........................................................6
FIGURE 1-6. Power and ground mesh structure...............................................................7
FIGURE 2-1. PODEM based algorithm used in XGEN [13]...........................................26
FIGURE 2-2. Fault effect can be propagated only with a transition on a side input........27
FIGURE 2-3. Fault effect can be propagated only with a hazard on a side input ............28
FIGURE 2-4. Timing computation prunes search space and increases efficiency ...........28
FIGURE 2-5. Minimum and maximum arrival time for a dynamic hazard .....................32
FIGURE 2-6. Arrival time in presence of hazards ...........................................................34
FIGURE 2-7. Delay effect propagated to an output as a static hazard.............................36
FIGURE 2-8. Delay effect propagated to an output as a dynamic hazard (a) fault
definitely detected (b) fault may or may not be detected...........................37
FIGURE 2-9. Propagation of multiple fault effects..........................................................38
FIGURE 2-10.Propagation conditions for an NAND gate (a) to-noncontrolling faulty
transition (b) to-controlling faulty transition.............................................39
FIGURE 2-11.Propagation conditions for propagating a fault effect either as a
transition or a static hazard........................................................................40
FIGURE 2-12.Pairs of arrival time and required time.......................................................41
FIGURE 2-13.Required time for Type B fault effect ........................................................43
xii
FIGURE 2-14.A logic objective may be satisfied if timing relationships are
considered..................................................................................................45
FIGURE 2-15.Change in fault status for c1355 ................................................................47
FIGURE 3-1. Use of multi-valued algebra.......................................................................55
FIGURE 3-2. Backtracing procedure for one logic objective ..........................................56
FIGURE 3-3. Converting Type B fault effect to Type A fault effect................................57
FIGURE 3-4. Converting Type B fault effect to Type A fault effect................................59
FIGURE 3-5. Hazards at input may increase arrival time range at an output ..................60
FIGURE 3-6. Shortcoming of out timing analysis procedure ..........................................64
FIGURE 3-7. Relationship between arrival times of falling and rising transitions
of a hazardous rising transition...................................................................66
FIGURE 3-8. Timing based closure .................................................................................69
FIGURE 3-9. Modified search algorithm .........................................................................73
FIGURE 3-10.Backtracing of objective at gate output not possible .................................76
FIGURE 3-11.Modified backtracing procedure ................................................................77
FIGURE 3-12.Modified search for recursive backtracing.................................................78
FIGURE 3-13.Example illustrating modified backtracing algorithm................................80
FIGURE 3-14.Modified objective determination procedure .............................................82
FIGURE 3-15.Algorithm to determine logic objectives for increasing minimum
arrival time at output....................................................................................84
FIGURE 3-16.Converting Type B fault effect to Type A fault effect................................85
FIGURE 3-17.Type B to Type A .......................................................................................86
FIGURE 3-18.Underlying transistor phenomenon............................................................87
xiii
FIGURE 3-19.A logic objective may give rise to a timing objective................................88
FIGURE 3-20.A logic objective may be determined traditionally or by a timing
objective ....................................................................................................88
FIGURE 3-21.Modified backtracing procedure ................................................................90
FIGURE 3-22.Change in fault status for c1355 ................................................................93
FIGURE 4-1. Interconnect circuit and model.................................................................103
FIGURE 4-2. Circuit response at far end with rise time variation at input IN...............106
FIGURE 4-3. Impact of oscillation on domino latch .....................................................108
FIGURE 4-4. Impact of oscillation on transmission gate...............................................109
FIGURE 4-5. Impact of oscillation on static inverter -- 0.25 mm process.....................109
FIGURE 4-6. Impact of oscillation on static inverter -- 0.18 mm process.....................110
FIGURE 4-7. Impact of process variation -- Example 2 ................................................113
FIGURE 4-8. Variation of oscillatory noise with interconnect length ...........................114
FIGURE 4-9. Example to illustrate test vector generation algorithm ............................119
FIGURE 5-1. Interconnect configurations......................................................................125
FIGURE 5-2. Circuit model and parameter matrices .....................................................127
FIGURE 5-3. Interconnect parameters...........................................................................128
FIGURE 5-4. Circuit used to study crosstalk .................................................................130
FIGURE 5-5. Crosstalk pulse.........................................................................................131
FIGURE 5-6. Crosstalk slowdown: Aggressor and victim switch in opposite
direction...................................................................................................133
FIGURE 5-7. Crosstalk speedup: Aggressor and victim switch in the same direction..134
xiv
FIGURE 5-8. Crosstalk slowdown: aggressor and victim switch in same direction
and inductive coupling dominates capacitive coupling...........................136
FIGURE 5-9. Combination of oscillatory noise and crosstalk.......................................137
FIGURE 5-10.Variation of noise with length..................................................................138
FIGURE 5-11.Variation of crosstalk pulse amplitude with edge-rate.............................139
FIGURE 5-12.Variation of crosstalk delay as a function of aggressor edge-rate and
skew.........................................................................................................141
FIGURE 5-13.Impact of spot defect on crosstalk pulse..................................................142
FIGURE 5-14.Impact of process variation on crosstalk pulse ........................................143
FIGURE 5-15.Circuit configuration used for study on pattern dependence ...................145
FIGURE 5-16.Crosstalk delay at victim for different values of static inputs on
adjacent lines............................................................................................146
FIGURE 5-17.Crosstalk pulse at victim for different values of static inputs on
adjacent lines............................................................................................147
FIGURE 5-18.V oltages at victim driver input and output when I1=0, I4=0 ...................148
FIGURE 6-1. Pulses propagated by transitions..............................................................153
FIGURE 6-2. Incremental validation .............................................................................154
xv
Abstract
Advancements in integrated circuit technologies have made it possible to reduce phys-
ical dimensions of devices and interconnects, increase switching speeds of devices, and
reduce power supply voltages. As a result, capacitance and inductance effects can create
severe on-chip noise on VLSI interconnects. Noise such as crosstalk glitch and delay,
overshoots, and undershoots, can lead to functional errors.
In this dissertation I have studied (i) test generation methods for capacitance induced
delay for enhanced efficiency and accuracy, and (ii) inductance induced noise from a test
and validation perspective.
We have used hazards and transitions to extend logic conditions for propagating
faults. We have employed new timing conditions for pruning search spaces during test
generation. We have introduced a relaxed criterion for fault detection based on timing.
Further, we have proposed different algebras for test generation. We have implemented
test generators in software based on 9-valued and 57-valued algebras. The algebras were
developed in light of timing based test generation. We have developed a methodology for
primary input assignments to control signal arrival times on circuit lines. With respect to
standard benchmark circuits, our results are superior to previous findings.
We have also studied characteristics of oscillatory noise, and inductance induced
crosstalk noise and delay. We have shown that inductance aggravates noise. We have
shown that process variation and spot defects can significantly increase noise. To facilitate
test generation, we have derived analytical expressions for the magnitude and time of
occurrence of oscillatory noise as a function of rise and fall time. We have shown that the
xvi
value of static signals on interconnects adjacent to the aggressor and victim lines can
impact the magnitude of noise and delay. Finally, we have discussed the impact of these
observations on test and validation of inductance induced noise.
1
Chapter 1 Introduction
Advancements in integrated circuit technologies have made it possible to reduce the
physical dimensions of devices and interconnects, increase the switching speed of devices,
and reduce the power supply voltage. As a result, capacitance and inductance effects often
create severe on-chip noise. Such noise, e.g. crosstalk, overshoots, undershoots and
ground bounce can lead to functional errors. This necessitates the study of capacitance and
inductance induced noise on signal lines. Whereas capacitance induced noise has been
studied [13], inductance induced noise has not been addressed in terms of test generation.
In this dissertation, I have studied (i) enhanced test generation methods for capacitance
induced noise, and (ii) inductance induced noise from a test and validation perspective. In
this chapter, I discuss the basics of on-chip capacitance and inductance (Section 1.1-Sec-
tion 1.3), motivate the problem of studying interconnect noise, especially inductance
induced noise (Section 1.4), describe background work in the area of test generation for
noise (Section 1.5), and, finally, discuss the scope of work addressed in this dissertation
(Section 1.6).
1.1 Physics of capacitance and inductance
Figure 1-1 explains the basic physics of a capacitor. The accumulation of positive charge
on the top plate results in the accumulation of negative charge on the bottom plate. The
field E is given as , where ε is a constant known as permittivity, A is the area of
the plates, and q is the charge flowing into the plate. The voltage drop across the capacitor
is given by , where d is the distance between the plates. Thus, ,
E
q
εA
---- - =
VEd = qCV =
2
where the capacitance C is defined by . The current flowing through the capaci-
tance is given by or . We will show in the next section how the parallel
plates are formed in VLSI circuits.
Next, we consider the physics of inductance. It is known that the flow of a current i
through a loop produces a magnetic flux (Figure 1-2). The magnitude of the flux Φ is
given as , thus the flux is proportional to the current. The inductance of the
loop, in three dimensional space, can be defined as which can be rewritten as
[23]. In this equation, µ is the permeability of the surround-
ing medium, dl
1
and dl
2
are two current elements (vectors), r
12
is the distance between
them and C is the contour of integration. Thus the inductance of a conductor is dependent
on the permeability of the surrounding medium and the configurations and dimensions of
its structure.
FIGURE 1-1. The charging of a capacitor
+
V
-
+ q
E
- q
C
εA
d
---- - =
i
dq
dt
---- - = iC
dV
dt
----- - =
Φ t () Li t () =
L
Φ t ()
i t ()
--------- - =
L
loop
µ 4π
----- -
l d
1
l d
2
⋅
r
12
------------------ -
c
∫
c
∫
=
3
It is known that a change in current with time through a loop produces a change in the
magnetic flux (with time). Also, a change in magnetic flux (with time) produces an elec-
tromagnetic force (emf). The magnitude of the emf e is given by Faraday’s law as
, which can be rewritten as .
Also, it is known from Lenz’s law that the direction of the produced emf is such that it
opposes the source that produced it and is therefore called the back-emf. This conforms to
the law of conservation of energy. The back-emf opposes the applied source voltage,
increases the transient delay and gives rise to oscillations. Further, the flux produced by
one current loop may be linked with another current loop, thus inducing crosstalk and
affecting the latter’s performance. We will now discuss how the “parallel plates” and cur-
rent loops are formed in VLSI circuits.
1.2 Origin of interconnect capacitance and inductance
There are two kinds of interconnect capacitances, one is formed between the intercon-
nect and the ground plane, known as line or self capacitance, and the other between the
two interconnects, known as mutual capacitance (Figure 1-3). The SiO
2
material acts as a
dielectric. The capacitances can be extracted by electrostatic solvers. We use the values of
self and mutual capacitances from process files.
FIGURE 1-2. A current produces a flux φ
e
dΦ
dt
------ - – = eL
di
dt
---- - – =
i
Φ
r
12
dl
1
dl
2
4
The inductance of a line is determined by the various areas of the return paths of the
current that flows through the line, and how the current in the line is distributed through
the return paths. The driving point impedance is the combination of the inductances of
these loops. In a VLSI chip, the current loops are formed by the paths along which a cur-
rent flows. We illustrate the concept of current loops using the example shown in Figure 1-
4. We will call the straight signal line x from nodes A to B as the signal path. The driver
drives the signal at one end of this signal path. The other end of the signal path is con-
nected to a receiver. Both driver and receiver are connected to the power/ground mesh. A
switching driver induces a current in the signal path. In this scenario, one return path is
composed of the interconnect (α), the path through the gate-to-substrate capacitance of the
p-transistor of the receiver (β), the substrate (γ), the power line (δ) and the path through
the source-to-drain resistance of the p-transistor of the driver (ω). Another return path is
completed by the interconnect, the path through the n-transistor of the receiver, the sub-
strate, the ground line, the decoupling capacitance, the power line and the path through the
p-transistor of the driver. When a single signal line switches, there are numerous return
paths that are formed in this manner. The number of paths is large -- since the power
(ground) lines are shorted by means of contact vias, the return paths spread out over the
FIGURE 1-3. Interconnect structure
SiO
2
dielectric layer
Silicon ground plane
Interconnects
line
capacitance
mutual capacitance
5
entire power (ground) mesh, i.e., δ is a set containing a large number of physical paths.
Thus, we see that the power/ground mesh plays an important role in determining the return
paths. The conductors associated with these return paths in the power and ground mesh
constitute the closed loops. These return loops are formed across all three dimensions.
It should be noted that the formation of return loops is dependent on the physical lay-
out. It is dependent on the periodicity (or closeness) of the power/ground lines. For exam-
ple, the higher the periodicity, the smaller the return loops and smaller the inductance.
However, there are constraints on periodicity. In the first metal layer, the periodicity of the
power/ground lines is constrained by the height of the cells from the cell library. In the
higher metal layers, the periodicity is constrained by the width and the number of the sig-
nal lines routed between the power and ground lines. The value of inductance is also
dependent on the length of the line because return loop area increases with length. The
FIGURE 1-4. An example showing the return paths
interconnect
ground
power
interconnect
ground
decoupling
capacitance
power
decoupling
capacitance
I
1
I
2
parasitic
capacitances
parasitic
capacitances
A B
x
α
β
γ
δ
ω
GC
6
value of inductance is also dependent on how decoupling capacitances are distributed
since many loops are formed by decoupling capacitances.
Figure 1-5 shows the typical magnitude of current at the input of the receiver for the
topology shown in Figure 1-4. The scale on the left hand side of the figure shows the cur-
rent and the one on the right hand side shows the voltage. The figure shows that this cur-
rent is large, i.e., of the order of milli-Amperes. The voltages at the input of the driver and
at the output of the receiver are also shown. Large drivers and receivers are used, the trans-
mission line length is 8000 µ m, and the process data from a 0.18 µ m process from UMC is
used [57]. HSPICE is used for simulation.
The current return paths are primarily determined by the structure of the power and
ground mesh. For the sake of illustration, a typical two layered power and ground mesh is
shown in Figure 1-6(a). The current flowing through an interconnect flows through the
FIGURE 1-5. Magnitude of current at receiver input
Voltages (lin)
-200m
-100m
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
1.4
1.5
Currents (lin)
-5.5m
-5m
-4.5m
-4m
-3.5m
-3m
-2.5m
-2m
-1.5m
-1000u
-500u
0
500u
Time (lin) (TIME)
4n 4.02n 4.04n 4.06n 4.08n 4.1n 4.12n 4.14n 4.16n 4.18n 4.2n 4.22n 4.24n 4.26n 4.28n 4.3n 4.32n
* pattern dependence of xtalk delay *
V oltage input to driver
V oltage output
receiver (C)
Current I
2
at
input of
receiver
at
(G)
7
entire power/ground mesh. The power and ground lines are alternated and the lines in two
consecutive layers are orthogonal to each other. The orthogonal power (ground) lines are
shorted wherever they cross each other (Figure 1-6(b)). A chip can have several layers of
power/ground lines where the topmost layers are shorted to ideal power/ground. Such an
assumption on the power and ground lines is reasonable [20], [62].
1.3 Inductance modeling and extraction
Inductance can be modeled either as loop inductance or partial inductance. Inductance
is normally associated with a loop, but in a VLSI environment, where the current return
paths are not known a priori, inductance of each part of the loop is calculated separately
[61]. This is known as partial inductance. Self partial inductances are associated with each
partial element and mutual partial inductances are associated with every pair of partial ele-
ments, where the loop is divided into a number of partial elements. The current through
the different partial elements is determined by the inductive, capacitive and the resistive
impedances of each fragment. This in turn determines the voltages at the different nodes in
FIGURE 1-6. Power and ground mesh structure
layer 1
Power Signal Ground
Power to ground spacing
Interlayer
Dielectric
Thickness
layer 2
(a) (b)
Power Ground
Power
Ground
Via
layer 2
layer 1
Signal
8
the circuit. Approaches that use loop inductances instead of partial inductances normally
results in slight inaccuracies in voltage-current characteristics.
In this work, we are interested in studying qualitative characteristics of inductance
induced phenomena and not in computing the exact magnitude of inductance induced
noise. Therefore, we have assumed a priori knowledge of current return path through
nearest power and ground lines and have modeled the inductances as loop inductances. We
have ignored current return paths through the substrate. We have noticed, via simulation
experiments, that the return paths through the substrate has very little impact on the mag-
nitude of inductance. This is understandable since the resistance of the substrate is orders
of magnitude higher than the resistance of interconnects.
There are two frequency dependent phenomena that determine the magnitude of
inductance: (i) proximity effect, and (ii) skin effect [37]. We have ignored both these phe-
nomena in this study. Proximity effect is the phenomenon due to which current returns
through paths in close proximity. Skin effect is the phenomenon due to which current
tends to crowd near the surface of an interconnect. As a result of skin effect, the resistance
of an interconnect increases and its inductance decreases. A measure of skin effect is skin
depth, which is defined as the depth of the interconnect material penetrated by 37% of the
current [77]. Skin and proximity effect may play a role in inductance determination in
future generation chips because of increase in clock frequency.
The inductances are computed using the inductance extraction tool FASTHENRY [35].
A power and ground grid is used for inductance extraction. It is assumed that the current
returns through the nearest power and ground lines in the mesh. Details of geometric
parameters are discussed, wherever appropriate.
9
1.4 Technology trends
The Roadmap of the Semiconductor Industry Association should be discussed to ana-
lyze technology trends [52]. This version was published in 1997 and was a 15-year projec-
tion of the integrated circuit characteristics required to maintain the current rate of
performance and cost improvement. Table 1-1 shows some of the projections made by the
Roadmap.
We see that the feature size will decrease from 250nm to 50nm and the clock fre-
quency will increase by a factor of 13. Chip size is also expected to increase as is total
length of interconnect. The minimum width of an interconnect will decrease and its
height-to-width aspect ratio will increase. The minimum separation between interconnects
will decrease. Further, the resistivity of the interconnect material will decrease. Associated
with these changes is the decrease in the power supply voltage.
TABLE 1-1. Projections from SIA Roadmap [52]
Year 1997 1999 2001 2003 2006 2009 2012
Feature size (nm) 250 180 150 130 100 70 50
On-chip local clock
(GHZ)
.75 1.25 1.5 2.1 3.5 6 10
Microprocessor chip
size (mm
2
)
300 340 385 430 520 620 750
Minimum metal width
(nm)
250 180 150 130 100 70 50
Metal height/width
aspect ratio -- logic
1.8 1.8 2.0 2.1 2.4 2.7 3.0
Minimum con-
tacted/non-contacted
separation between
adjacent metal lines
(nm)
390/
340
280/
240
250/
210
210/
170
160/
140
120/
100
90/
80
Metal effective resis-
tivity (µΩ -cm)
3.3 2.2 2.2 2.2 2.2 < 1.8 < 1.8
Minimum logic Vdd
(V)
1.8-2.5 1.5-1.8 1.2-1.5 1.2-1.5 .9-1.2 .6-.9 .5-.6
10
The impact of these changes on capacitance and inductance induced noise is as fol-
lows. One of the most important reasons why such noise is of concern is the increase in
clock frequency. Increased frequency implies increased crosstalk charge transfer from one
interconnect to another (Q= ). Increased frequency also implies increased inductive
impedance (Z = 2πfL, where f is the frequency, and L is the inductance), decreased damp-
ing factor that results in increased oscillatory noise, and increased crosstalk noise voltage
V = , where is the rate of change of current. Another important factor affecting
noise on interconnects is the length of interconnects. A rule of thumb measure for the
average length of a global interconnect is given as , where A is the area of the chip
[70]. With increase in the average length of the chip size, the average length of intercon-
nects is expected to increase. Decrease in metal width will decrease the self capacitance of
the line. The increase in the aspect ratio increases the mutual capacitance. Decrease in sep-
aration between lines also increases the mutual capacitance between them. Decrease in
power supply voltage implies a decrease in noise margin -- therefore the devices will be
more susceptible to noise and more likely to cause functional failure.
We should discuss the impact of another recent change in the fabrication process, that
is, the use of copper in place of aluminum for interconnects. Moving from aluminum to
copper has the effect of reducing interconnect delay. Since copper has a lower resistivity
compared to aluminum, decrease in resistance may aggravate the impact of parasitic
capacitances and inductances. Had we continued using aluminum, the chances of noise
would have been less, at the expense of increased delay.
C
dV
dt
------ -
L
di
dt
---- -
di
dt
---- -
A
3
------- -
11
We now focus on the discussion on inductance induced noise in the Roadmap. The
Roadmap stresses the importance of building circuit models with inductance (pg 187):
“The importance of interconnect is increasing in process and design. At high frequen-
cies one needs to deal with RLC, transmission-line, and long range coupling effects on
semiconductor substrates.”
Additionally, the Roadmap projects that inductance induced noise can be significant
(pg 192):
“The interconnect delay is more than 60% of the critical path delay in 350 nm technol-
ogy and increasing with scaling. The accuracy of interconnect models depends on the
interconnect geometry and the material properties, requiring accurate extraction and phys-
ical simulation. At 500 MHz clock frequency, complex electrical effects will be significant
such as inductive coupling, ground bounce, transmission line and skin effects.”
Finally, the Roadmap stresses the need to test for such new, high frequency phenom-
ena (pg 36):
“Signal integrity and electromagnetic phenomena (EM) will become an increasingly
important test issue as chips and test equipment become complex. New fault models
(including soft error models) that incorporate the effects of EM fields must be developed.
Relationships between design constraints and manufacturability and testability must be
developed for different design domains. Test generators must be sensitive to signal integ-
rity issues.”
12
1.5 Previous Work
1.5.1 Test generation for crosstalk noise
A large amount of noise or delay on an internal line does not necessarily result in a cir-
cuit’s failure. To cause a failure in a circuit employing static logic, the noise or delay at an
output must be greater than some threshold and occur at a time related to the clock sam-
pling time. During the design phase, it is important to ensure that, for an aggressive
design, no sequence of events will produce a circuit failure. However, it is not feasible to
guarantee that via exhaustive simulation.
A common practice is to start with an aggressive design, simulate the noise site with
appropriate test data, and redesign the circuit if the noise or delay is deemed to have an
unacceptable value. However, the noise or delay at a noise site may not cause a failure
because it may be filtered out along paths to all circuit outputs, or because the stimuli that
excite it may prohibit it from propagating to a circuit output. Redesigning the circuit gen-
erally involves increasing the separation between adjacent interconnects, inserting buffers,
sizing up the victim drivers, sizing down the aggressor drivers and increasing the resis-
tance of the interconnects. The first three redesigning methods result in increased area, and
the last two result in performance degradation. Thus, unnecessary redesign based on simu-
lation of partial circuit results in a conservative design, and even in performance degrada-
tion. Therefore, the entire circuit should be taken into consideration for noise analysis.
Since simulation of the entire circuit using all vectors is impractical, the problem of deter-
mining test sequences that excite the “worst case” noise or delay at a circuit output needs
investigation. The generated test vectors can then be used for validating the circuit.
13
The noise or delay in a fabricated circuit may still exceed the threshold because of
changes in circuit parameters caused by spot defects and process variation. Therefore,
these tests can also be used during silicon debugging and manufacturing test.
It is assumed that a list of target interconnects susceptible to oscillation and associated
circuit parameters are available. It is also assumed that the circuit is combinational with
static CMOS logic gates. A synchronous, sequential circuit can be decomposed into
blocks of combinational logic and the test generation method can be applied to each com-
binational logic block with the assumption that its inputs (which are primary inputs or flip-
flop outputs) are deterministically controllable and the outputs (which are primary outputs
or flip-flop inputs) are observable. Thus a scan design architecture is assumed.
The methodology presented in [13] proposed analytical models for capacitive
crosstalk and noise propagation through static CMOS gates. These techniques were then
integrated in a mixed-signal test generation procedure. This procedure modeled noise
effects as new logic values, and considered analog information to propagate the noise.
This ATPG algorithm included the concept of gate delay, signal arrival time, signal
strength, and rise/fall times. The work presented conditions for worst case coupling and
propagation. A branch and bound test generation procedure was proposed, that was mod-
eled on PODEM [13]. A test generator called XGEN was developed. Experimental results
showed that this approach can generate tests for circuits of reasonable sizes. However, the
test efficiency was low and the test generation procedure required a large amount of com-
putational time.
A few other studies on test generation for capacitive crosstalk noise have been carried
out [43], [60], [47]. Neither of the two works in [43], [60] considered the analog properties
14
of the pulse, rather the pulse was modeled with full voltage swing. Whereas [43] consid-
ered the arrival time of pulses, it was ignored in [60]. The analog properties of the pulse
was considered in [47] but timing was ignored. In contrast, the work described in [13] con-
sidered both pulse width and height, and its time of arrival. In addition, it also addressed
the test generation problem for crosstalk delay.
1.5.2 On-chip inductance
The problem of inductance extraction has been addressed in the literature [34], [69].
Efficient circuit simulation with inductance was addressed in [22], [39], [61]. The impact
of inductance on noise was considered in [19], [20], [21], [29]. The impact of inductance
on delay computation and repeater insertion was discussed in [30], [31], [74]. The need for
test generation for inductance induced noise on inter-core interconnects was discussed in
[53]. However, studies addressing test generation for inductance induced noise has not
been reported [16].
1.6 Scope of dissertation
It is understood that the parasitic inductance of on-chip interconnects may give rise to
undesired noise, such as overshoots and undershoots caused during an oscillatory transi-
tion. The oscillation is due to increased inductance of the interconnect. An overshoot and
undershoot during a transition is a transient pulse above or below the power supply or
ground voltage. A second kind of noise is crosstalk. Crosstalk is the phenomenon when a
transition on one interconnect impresses a voltage on a second adjacent interconnect. This
is due to mutual inductances and capacitances between the interconnects. Crosstalk can
give rise to a spurious pulse on the adjacent interconnect that is supposed to have a static
15
value, or may slow down or speed up a transition on an adjacent interconnect. Finally,
oscillatory noise and crosstalk can combine and increase the magnitude of noise. Due to
skew between signal lines, the oscillatory noise on an interconnect may coincide with
crosstalk on an adjacent line, and increase the magnitude of overshoot and undershoot.
In Chapter 2 we address the problem of test generation for capacitive crosstalk delay
for enhanced fault coverage and decreased computation time. Two drawbacks of XGEN
are (i) tests are not found for some crosstalk faults for which tests exist, and (ii) the test
generation procedure is slow and thus often aborts. We have proposed new propagation
conditions that consider transitions and hazards. We have incorporated timing conditions
for fault propagation. We have proposed a relaxed condition for fault detection. We refer
to the strict and relaxed criteria as Type A and Type B fault effects, respectively. We have
implemented these ideas in a software system called XGEN-E.
In Chapter 3 we propose a new 57-valued algebra for crosstalk delay faults. This alge-
bra takes timing based issues into consideration. We have developed a new backtracing
procedure that meets the requirement of our test generation algorithm. We have also iden-
tified two new issues in timing based test generation. First, a fault may be propagated log-
ically to an output but the timing range may be such that the minimum arrival time is less
than the clock sampling time and the maximum arrival time may be greater than the clock
sampling time. Secondly, it is possible that a logic objective at the output of a gate may
only be satisfied by certain relationships between arrival time ranges at its inputs, which in
turn are satisfied by certain primary input assignments. Without considering these two
timing based issues, a logically undetectable fault may not be truly undetectable. We have
16
discussed these issues in this chapter. We have implemented these ideas in a software sys-
tem called XGEN-C.
Our work on inductance is early exploratory work on test generation for inductance
induced noise. In Chapter 4, we present characteristics of oscillatory noise. We first show,
by trend analysis, that the magnitude of oscillatory noise is expected to increase in future
technologies. Its impact on CMOS circuits is also discussed. We demonstrate that process
variation may cause oscillatory noise to vary by +20%. We show that oscillatory noise first
increases and then decreases with an increase in interconnect length. We illustrate that
oscillatory noise can be a problem in medium length interconnects in combinational logic
blocks. Oscillatory noise normally increases with a decrease in transition times of input
stimulus. A slight non-monotonicity is noticed, but is small enough to be ignored for test
generation in current technologies. To facilitate vector generation, analytical expressions
for the magnitude and time of occurrence of undershoots and overshoots as a function of
rise and fall time are derived. Further, a delay criterion, called settling time, is proposed
for circuits that exhibit oscillatory noise.
In Chapter 5 we study characteristics of crosstalk noise and delay. We show that
crosstalk effects induced by a combination of mutual capacitance and inductance can be
larger than those induced by mutual capacitance alone, even if capacitive crosstalk domi-
nates over inductive crosstalk. We observe that oscillatory noise can combine with
crosstalk pulse under certain skew conditions and give rise to a large magnitude of noise.
We also show that crosstalk can be a problem in medium length interconnects. Because
such interconnects can occur in combinational logic blocks, generation of suitable vectors
for test and validation of such logic blocks is of concern. We demonstrate that the magni-
17
tude of crosstalk is affected by spot defects and variation in process parameters. We fur-
ther show that the magnitude of crosstalk induced pulse and delay vary non-monotonically
with variation in timing parameters of transitions at the inputs of aggressor and victim
lines. Further, we show that the value of static signals on interconnects adjacent to the
aggressor and victim lines can impact the magnitude of noise and delay. Additionally, the
value of static signals on interconnects adjacent to aggressor and victim can have a bigger
impact on the magnitude of noise and delay when parasitic inductances are considered.
For certain combinations of electrical parameters, signals on non-adjacent aggressors that
switch in the same direction as the adjacent aggressors can increase the magnitude of
noise and delay when parasitic inductances are involved. Finally, we discuss the impact of
these observations on test and validation of inductance induced noise and delay.
In Chapter 6 we propose future work. The concept of static and dynamic learning that
was used for efficient test generation for stuck at faults should be extended for crosstalk
faults. Further, the concept of learning should be extended to the timing ranges, that is,
timing range at a set of circuit lines can be used to reach inferences about timing ranges at
other circuit lines.
The contributions of this dissertation are two-fold: (i) we look into improved test gen-
eration methods for efficiency and accuracy, and (ii) we explore the need for test genera-
tion for inductance induced noise.
Parts of the work presented here have been published [63], [64], [67], [68]. Further, the
author has studied other problems in the area of on-chip inductance such as designing
power and ground grid for reduced inductance, fast determination of approximate values
of on-chip inductance [62], testing for inductance induced noise in multi-drop buses [65],
18
and a novel technique for reducing power dissipation using the inductance of long inter-
connects [66].
19
Chapter 2 An enhanced test generation system for crosstalk
delay faults
2.1 Introduction
As described earlier, a test generation methodology, called XGEN, was previously
developed to generate tests for capacitance induced crosstalk faults [13]. These tests can
be used for validation and production testing. The conceptual drawbacks of XGEN test
generation methodology for crosstalk delay faults are: (i) restricted logic conditions are
used for propagating fault effects, (ii) timing requirements for propagating fault effects are
not fully explored, (iii) inadequate timing analysis is employed because a restricted pin-to-
pin delay model is used, (iv) crosstalk computation cannot handle timing ranges, (v) a
constrained system of logic values is used, and (v) no attempt is made to satisfy desired
timing relationships by making logic assignments. We address items (i), (ii), (iii) and (iv)
in this chapter, and (v) and (vi) in the next chapter.
We begin by summarizing the contributions described in this chapter. Previously, in
theory, static values were used on off-path inputs to propagate crosstalk induced delay
effects [13]. However, other propagation conditions exist. We have considered new propa-
gation conditions that increase the likelihood of finding a test. Thus, fault coverage and
test efficiency are increased, and runtime decreased. In addition, we have enhanced XGEN
by extending its 5-valued algebra to a 9-valued algebra which distinguishes between haz-
ardous and non-hazardous logic values. We have also refined the timing requirements for
propagating fault effects. We have developed a new relaxed criterion of fault coverage,
which can be used if tests that satisfy the strict criterion cannot be found. We refer to the
strict and relaxed criteria as Type A and Type B fault effects, respectively.
20
We have also incorporated (i) a more accurate delay model that was developed
recently and considers simultaneous to-controlling transitions [7], and (ii) a methodology
for timing analysis that handles arrival time ranges (in contrast to single arrival time val-
ues) for crosstalk computation at the inputs of the aggressor and victim line drivers [27].
We have incorporated several of these techniques in two test generation software sys-
tems. The first uses the static propagation conditions used in XGEN reported previously
[12], and the second uses our new propagation conditions and the improved timing
requirements for propagating fault effects. Both use the 9-valued algebra, new delay
model, crosstalk computation with ranges, and the same timing analysis routines. We refer
to the system employing the “static” propagation conditions as XGEN-S and to the second
“enhanced” version as XGEN-E. Note that the results from XGEN should not be com-
pared with the results from XGEN-E, as the underlying delay model, timing analysis and
crosstalk computation routines are different. We will compare the results from XGEN-S
and XGEN-E.
2.2 Background
2.2.1 Delay and timing computations
2.2.1.1 Delay model
The controlling value of a multi-input primitive gate is the value that, when applied to
any input of the gate, completely determines its output. The corresponding value at the
output is called the controlled response. The Boolean complement of the controlling value
is the non-controlling value of the gate. When all the inputs to a gate have a non-control-
ling value, the value at the output is called the non-controlled response. A to-noncontrol-
21
ling transition is one that changes from a controlling value to a noncontrolling value; a to-
controlling transition is defined similarly. Due to transistor effects, simultaneous to-con-
trolling transitions at inputs of a primitive gate decrease gate delay, and simultaneous to-
noncontrolling transitions at inputs of a primitive gate increase gate delay. We use the
modifications proposed in [7] as our underlying delay model. This incorporates the change
in delay only due to simultaneous to-controlling transitions, and is an extension to the
classical pin-to-pin delay model. The software that supports simultaneous to-noncontrol-
ling transitions was not available at the time we integrated our software. We assume that
the arrival and transition time ranges at gate inputs, and the load at the gate outputs are
known. We also assume that each gate has a single delay value (not a range), and that cir-
cuit lines that do not have any capacitive coupling have zero delays.
2.2.1.2 Arrival and required time
The arrival time of a transition on a circuit line is the 50% point of the signal change
time on the circuit line. This arrival time is given by a range and we have separate ranges
for a rising transition and a falling transition. The minimum arrival time of a transition on
a circuit line is the minimum delay of a transition along all the paths from the primary
inputs to that line, and the maximum arrival time is the maximum delay of a transition
along all the paths from the primary inputs to that line. At a primary input, the arrival time
of a transition is defined as time zero, hence all primary inputs that switch do so at the
same time. At a gate’s output, the arrival time of a transition is a function of the arrival and
transition times at the gate’s inputs, as well as the capacitive load at the output. When the
input patterns to a gate are not completely specified, the arrival time of a transition at the
22
output is expressed by a range (which is not a point). Starting from the primary inputs, the
arrival time on lines in a circuit can be calculated by a forward breadth-first traversal.
The maximum required time associated with a line is the minimum time such that, if
the arrival time of a transition on this line is greater than this value, and if this transition
can be logically propagated to some output, it will arrive after the clock sampling time.
Thus, an output error is created. The minimum required time associated with a line is the
maximum time such that, if the arrival time of a transition on this line is less than this
value, and if this transition is propagated to any output, it will arrive before the clock sam-
pling time. If the arrival time of a transition is greater than the minimum required time but
less than the maximum required time, then if this transition can be logically propagated to
some output, then it may or may not arrive after the clock sampling time. The required
time on primary outputs is given by a single value, i.e, the clock sampling time. However,
the required times on all other lines can be a range. The minimum required time on a fan-
out stem is defined as the minimum of the minimum required time among all of its fan-out
branches, and the maximum required time on a fan-out stem is defined as the maximum of
the maximum required times among all its fan-out branches. On all other lines the mini-
mum required time is defined as the minimum required time at the gate output minus the
maximum gate delay, and the maximum required time is defined as the maximum required
time at the output minus the minimum gate delay (assuming simultaneous transition).
Note that due to the presence of multiple paths, the minimum required time and the maxi-
mum required time each can be a range. However, the actual minimum required time is the
minimum value in minimum required time range, and the maximum required time is the
maximum value in maximum required time range.
23
The required time on all circuit lines is calculated by a backward breadth-first traversal
starting from the primary outputs. In the pin-to-pin delay model, the required time at the
input of each gate depends on the required time at the output and the gate delay, and can be
computed in a straightforward manner. In the simultaneous switching delay model, the
required time at an input also depends on the arrival time at the other inputs, and we have
to use an iterative procedure at each gate.
An iterative procedure has been proposed to determine the required time at each gate
input [27]. The iterative nature of this algorithm makes this computation time consuming.
It is especially expensive to recompute required times after every primary input assign-
ment during the test generation procedure. Therefore, we will compute required time
based on the results of static timing analysis.
Had we updated the required time after every primary input assignment during test
generation, required time ranges could shrink due to the following two reasons. First, as
more primary inputs are assigned specific values, certain propagation paths become
blocked. As a result, only a subset of previous propagation paths remain viable and only
their delays determine the required time values. Secondly, the delay from an input to the
output of a gate depends on the arrival and transition times at the other inputs of the gate.
Therefore, as the arrival and transition time ranges at the off-path inputs get refined, the
gate delays get more specific and so do the required times.
2.2.1.3 Timing simulation for specified input values
Static timing analysis provides a min-max range of arrival times, transition times and
required times on each line, when all input values are unspecified. When inputs are com-
24
pletely specified, timing simulation provides specific values of signal arrival and transition
times for all lines in the circuit (we assume that no hazard is present, and we will discuss
timing simulation involving hazards later). Timing analysis for partially specified vectors
(TA-PSV) is an analysis method that is intermediate between these two scenarios. When
input values are partially specified, arrival times, transition times and required times are
still given by ranges [9]. These ranges, however, reduce in size as more input values
become specified. Our test generation system employs TA-PSV .
2.2.2 Crosstalk test generation
2.2.2.1 Overview
XGEN is a mixed-signal, timing-based automatic test pattern generator for combina-
tional logic circuits [13]. XGEN uses the branch and bound strategy of PODEM, i.e., logic
values are only assigned to primary inputs, and forward implication performed to deter-
mine logic values on internal lines. This tool maintains crosstalk information by recording
analog information. For example, with each transition, the arrival and transition times are
recorded. A test for a crosstalk delay fault must satisfy the condition that the arrival time
of a transition (emanating from the delay fault) on at least one primary output must be
greater than the clock sampling time.
XGEN is the first test generator to bring together the satisfaction problems of both
logic and analog constraints. At the heart of XGEN is a crosstalk noise model. The magni-
tude of noise is determined as a function of arrival and transition times on the victim and
aggressor lines, line and load capacitances, and driver and line resistances. The noise
25
effect is first excited by suitable assignments on primary inputs. The noise is then propa-
gated to a primary output by means of further logic assignments.
2.2.2.2 Test generation algorithm
In Figure 2-1, we present high level pseudo-code for the modified PODEM algorithm
used in XGEN. The required conditions on the aggressor and victim lines are first chosen
as logic objectives. Once these objectives are satisfied, then a propagation condition is
chosen from the set of gates in the noise frontier. (The noise frontier of a crosstalk delay
effect is similar to the D-frontier [1]). By means of backtracing, primary input assign-
ments are found. Once an input assignment is made, logic implication and timing analysis
are performed and the noise frontier is updated. Then, a recursive call to the modified
PODEM procedure is made. If the recursive call returns FAILURE, then an alternative
assignment is made on the last input that was assigned a value. Thus, we enumerate all
possible logic values (s0,s1,cr,cf) at every primary input (where s0 is static 0, s1 is static 1,
cr is clean (hazard free) rising, and cf is clean falling). If none of the assignments lead to a
test, then the unknown (or unspecified) value is assigned, and the procedure returns FAIL-
URE to the calling procedure, which is either another copy of the same procedure or an
external procedure that initiated the recursion. Similarly, if a copy of the procedure returns
SUCCESS, then this value is returned up the function call chain.
26
FIGURE 2-1. PODEM based algorithm used in XGEN [13]
if terminating condition reached
return;
(v,line) = determine_logic_objective();
(v
a
,input
a
)= backtrace(v,line);
logic_implication();
TA-PSV();

update_noise_frontier();
if (xpodem() == SUCCESS)
return SUCCESS;
assign v
b
on input
a
, v
b
is in {s0,s1,cr,cf}-v
a

logic_implication();
TA-PSV();
update_noise_frontier();
if (xpodem() == SUCCESS)
return SUCCESS;
assign v
c
on input
a
,

v
c
is in {s0,s1,cr,cf}-{v
a
,v
b
}

logic_implication();
TA-PSV();
update_noise_frontier();
if (xpodem() == SUCCESS)
return SUCCESS;
assign v
d
on input
a
,v
d
is in {s0,s1,cr,cf}-{v
a
,v
b
,v
c
}

logic_implication();
TA-PSV();
update_noise_frontier();
if (xpodem() == SUCCESS)
return SUCCESS;
assign vxx on input
a
logic_implication();
TA_PSV();
return FAILURE;
}
xpodem()
{
update_noise_frontier();
27
2.3 Motivation
2.3.1 Enhanced propagation conditions
2.3.1.1 Transitions
We present an example to show the benefits of using new propagation conditions. Fig-
ure 2-2 shows a circuit where a delay effect can only be propagated through the NOR gate
by means of a transition on the side input. Note that a static 0 is not achievable at the side
input of the circled NOR gate. The reader can verify that only a clean or hazardous transi-
tion is possible on the side input. Whether the delay effect on the victim line is actually
propagated through the NOR gate can only be determined through additional timing com-
putations. Thus, allowing transitions on side inputs expands the space in which a test can
be found.
2.3.1.2 Hazards
In Figure 2-3, we show an example of how a hazard can be used to propagate a
crosstalk delay effect. Again, a static non-controlling value is not achievable at the side
input of the circled NAND gate. Note that the hazard might actually propagate the
FIGURE 2-2. Fault effect can be propagated only with a transition on a side
input
s1
s1
victim
aggressor
side input
28
crosstalk delay effect to the output. Again, whether the delay effect is actually propagated
will depend on the timing conditions.
The propagation conditions are defined comprehensively in Section 2.6.2.
2.3.2 Timing conditions for fault propagation
Using the circuit shown in Figure 2-4, we next show how required time ranges can be
used to prune the search space. We are attempting to detect the fault as a Type A fault
effect. In this figure, arrival time ranges are shown in round brackets and required time
FIGURE 2-3. Fault effect can be propagated only with a hazard on a side input
FIGURE 2-4. Timing computation prunes search space and increases efficiency
aggressor
victim
delay effect
side input
(0,2)
(3,5)->(7,9)
[6,9]
victim
aggressor
(12,14)
[11,11]
(16,18)
[15,15]
(12,14)
[15,15]
(10,12)
[13,13]
W
X
G1
G2
G3
Y
Z
s1
s1
s1
s0
s1
G4
{5}
{4}
{2}
{3}
s0
{3}
29
ranges in square brackets. The delay through each gate of interest is shown inside curly
braces. Assume the required time at the victim is [6,9]. In addition, assume that the
crosstalk effect adds 4 units of delay to the victim line. Therefore, the arrival time range at
the victim line increases from (3,5) to (7,9). Suppose we first try to propagate the delay
effect through gate G1. The arrival time on line W is (10,12). If we further propagate this
effect through gate G3 to the output, we see that the clock sampling time at the output X,
which is 15 units, is not violated. However, this last propagation attempt through gate G3
is not required. This is because, on line W, the maximum arrival time is less than the mini-
mum required time, which implies that propagation along this path will not lead to a Type
A fault effect at a circuit output. We see that propagation through gate G2 to a primary out-
put Z will lead to an error. Note that at the victim line, the delay effect is such that there is
an overlap between arrival time and required time ranges, and at line Y, the delay effect is
such that the minimum arrival time is greater than the maximum required time. The delay
effect on line W does not cause the arrival time to exceed the required time. This is why
delay effect propagation through gate G3 is not needed and our algorithm will not consider
this propagation. We will discuss timing conditions for propagation in Section 2.7.1.
2.4 9-valued algebra
In this section, we present a 9-valued algebra. The motivation for using this algebra is
that it is the minimum set of values that distinguishes between hazardous and non-hazard-
ous values. For crosstalk delay faults XGEN used a 5-valued algebra, namely s0, s1, cr, cf
and xx. These values represented a static 0 (low), a static 1 (high), a clean rising transition,
a clean falling transition, and the unspecified value, respectively.
30
Since we want to distinguish between hazardous and non-hazardous values, we intro-
duce four new values, namely 00, 11, 01, and 10, which represent, respectively, a hazard-
ous 0, hazardous 1, a hazardous rising transition, and a hazardous falling transition. After
each timing analysis routine, our timing simulator checks whether a hazardous value can
be refined to the corresponding non-hazardous value.
A hazardous 0 (1) implies that the initial and final values are 0 (1), but the signal might
temporarily attain the value 1 (0). We refer to this temporary phenomenon as a glitch. A
hazardous 0 or 1 value is referred to as a static hazard. A hazardous rising transition (haz-
ardous falling transition) implies that the initial and final values are 0 (1) and 1 (0), how-
ever falling (rising) transitions might occur before the signal reaches steady state. In
general, a hazardous rising (falling) transition has n falling (rising) transitions and n+1 ris-
ing (falling) transitions, where . A hazardous rising transition or a hazardous falling
transition will be referred to as a dynamic hazard.
We show the truth tables for 2-input AND, OR and NOT operations for the 9-valued
algebra in Table 2-1, Table 2-2 and Table 2-3, respectively. The truth tables ignore timing.
Thus, for the AND operation of two values, 01 and 10, the result is 00, implying that a
glitch might occur. In an actual circuit, the presence of a glitch can only be determined via
timing analysis (which is why logic analysis is followed by timing analysis). Truth tables
for other operations, such as NAND and NOR operations, can be derived from these truth
tables.
n 0 ≥
31
Finally, note that the algebra is complete since the AND, OR and NOT operations on
any two values belonging to the algebra results in a value which also belongs to the alge-
bra.
2.5 Timing analysis
2.5.1 Timing ranges for hazards
Previously in XGEN, all values were either clean transitions or hazard free static val-
ues. Extensions to XGEN are required to incorporate hazards.
TABLE 2-1. AND operation for 9-valued algebra
s0 s1 cr cf 00 11 01 10
s0 s0 s0 s0 s0 s0 s0 s0 s0
s1 s0 s1 cr cf 00 11 01 10
cr s0 cr cr 00 00 01 01 00
cf s0 cf 00 cf 00 10 00 10
00 s0 00 00 00 00 00 00 00
11 s0 11 01 10 00 11 01 10
01 s0 01 01 00 00 01 01 00
10 s0 10 00 10 00 10 00 10
xx s0 xx xx xx 00 xx xx xx
TABLE 2-2. OR operation for 9-valued algebra
s0 s1 cr cf 00 11 01 10
s0 s0 s1 cr cf 00 11 01 10
s1 s1 s1 s1 s1 s1 s1 s1 s1
cr cr s1 cr 11 01 11 01 11
cf cf s1 11 cf 10 11 11 10
00 00 s1 01 10 00 11 01 10
11 11 s1 11 11 11 11 11 11
01 01 s1 01 11 01 11 01 11
10 10 s1 11 10 10 11 11 10
xx xx s1 xx xx xx 11 xx xx
TABLE 2-3. NOT operation for 9-valued algebra
s0 s1 cr cf 00 11 01 10 xx
s1 s0 cf cr 11 00 10 01 xx
32
Definition 1: The minimum rising transition time for a static or dynamic hazard associ-
ated with a signal line is the minimum of the rising transition times among all possible ris-
ing transitions on this line. The maximum rising transition time is defined in a similar
manner and so are the minimum and maximum falling transition times.
Definition 2: Considering all possible value assignments at the inputs to a combinational
circuit that are currently unspecified (xx), the minimum arrival time for a static or dynamic
hazard on a circuit line is the minimum arrival time of the first possible transition on this
line, and the maximum arrival time is the maximum arrival time of the last possible transi-
tion on this line. Note that arrival time computation uses transition time of rising and fall-
ing transitions.
As an example, in Figure 2-5 we show the minimum and maximum arrival time on a
line based upon three hazardous transitions that occur due to three different input patterns
on the same line. The abstracted arrival time range based on these three transitions is also
shown. The arrival time range for a falling transition is reproduced in a similar way. Table
2-4 lists the information recorded for various types of signals.
FIGURE 2-5. Minimum and maximum arrival time for a dynamic hazard
Abstracted arrival time range
Maximum arrival time
Minimum
arrival time
for rising transition
33
Next, we consider the computation of arrival time ranges for static hazards. Consider a
hazardous rising transition and a hazardous falling transition at the two inputs of an AND
gate. A hazardous 0 (00) may be present at its output. As shown in Table 2-4, information
is stored for both rising and falling transitions for the 00 value. The arrival time range is
determined from the minimum arrival time of the rising transition and the maximum
arrival time of the falling transition. Thus, for hazards, with knowledge of the logic value
at the output, the minimum and maximum of the appropriate transitions are considered to
determine the arrival time range. For static 1 hazard, the minimum arrival time is deter-
mined by the first falling transition, and the maximum arrival time is determined by the
last rising transition.
2.5.2 Example
The reader will find examples illustrating iterative timing refinement in [7]. Here, we
present an example to show that when we consider hazards, even if the inputs are com-
pletely specified, the arrival time may be given by a range. In Figure 2-6(a), no hazard
exists in the circuit. In Figure 2-6(b), hazards are present on lines X and Y. Assume that
TABLE 2-4. Timing information associated with each logic value
Logic value
Rising transition information
(Min and max arrival time,
min and max transition time)
Falling transition information
(Min and max arrival time,
min and max transition time)
s0 no no
s1 no no
cr yes no
cf no yes
00 yes yes
11 yes yes
01 yes yes
10 yes yes
xx yes yes
34
the transitions at the inputs of the NAND gate in Figure 2-6(b) are spaced far apart with
the rising transition occurring before the falling transition. Further, assume that the delay
from each of the inputs to the output of the NAND gate is 2 units. Thus, a glitch is present
on line X. Note that if the rising transition preceded the falling transition on line X (spuri-
ous and carried over from the previous timing analysis procedure), then the hazardous 1
value could be refined to a static 1 value. This, in turn, would imply a clean transition on
line Y. If the transition on line Z occurs at time 1, and the delay from each input of the
AND gate to its output is 4 units, then on line Y we have rising transitions at times 5 and 9,
and a falling transition at time 6. This example shows that, in the absence of hazards, when
inputs are completely specified, arrival times on circuit lines are given by single values,
and in the presence of hazards, even if inputs are completely specified, arrival times may
be ranges.
2.5.3 Crosstalk delay effect
Definition 3: A Type A effect is a crosstalk delay effect on a circuit line for which the
minimum arrival time of a transition is greater than the maximum required time.
FIGURE 2-6. Arrival time in presence of hazards
s0
s1
X
Y
X
Y
(a)
(b)
0
3
2 5
1
1
Z
Z
5
5 6 9
35
Definition 4: A Type B effect is a crosstalk delay effect on a circuit line for which there is
an overlap between the arrival time range and the required time range.
Assume that for a given fault a test vector is generated. Three possibilities arise. First,
the vector might produce a Type A fault effect at one or more outputs. In such a case, the
vector is guaranteed to detect the fault. Secondly, the vector does not cause a Type A effect
at any output but causes a Type B effect at one or more outputs. In this case, the vector
may or may not detect the fault. Thirdly, the vector does not cause a Type A effect or a
Type B effect at any output. In other words, at every output with a transition, the maxi-
mum arrival time for the transition is less than the clock sampling time. Clearly, in such a
case the vector will not detect the given fault. Hence at outputs, only Type A effects can
guarantee detection.
We can accelerate test generation by dealing differently with Type A and Type B
effects on internal lines during fault effect propagation. This can be done by propagating
Type A effects by side input conditions which do not speed up the fault effect, as timing
computation can be completely shut off in this scenario and it will still guarantee that a
Type A fault effect at the input of a gate will remain a Type A effect at its output.
2.6 Logic propagation conditions
2.6.1 Factors affecting propagation
In Section 2.3.1, we provided the motivation for enhanced propagation conditions.
Here, we discuss the propagation conditions in more details.
36
2.6.1.1 Hazards
Fault coverage can be increased and test generation runtime decreased by allowing
propagation conditions to include hazards on off-path inputs.
If a static hazard occurs at a primary output, the clock sampling time might be less
than the minimum arrival time, or greater than the maximum arrival time. For these two
situations, the delay effect carried by a static hazard is definitely not detected (Figure 2-
7(a),(b)). However, if the clock sampling time is greater than the minimum arrival time
and less than the maximum arrival time (Figure 2-7 (c)), then the delay effect carried by a
hazard might be detected. Thus, static hazards at a circuit output can never lead to a Type
A effect, the only type of effect that actually guarantees detection.
As shown in Figure 2-8, dynamic hazards at an output can give rise to both Type A and
Type B fault effects. We will define conditions for propagation of the fault effect both as
transitions and static hazards. Since detection via Type B effects is uncertain, in this work,
we will only use propagation conditions on side inputs such that the fault effect is carried
either by a clean transition or by a dynamic hazard (Figure 2-8). By not considering static
hazards, we may lose some fault coverage. However, since every test we miss could only
cause Type B effects, none of the tests we miss would have guaranteed detection. By
FIGURE 2-7. Delay effect propagated to an output as a static hazard
clock sampling time
delay effect may or (c)
A
min
A
max
clock sampling time
delay effect will not be (b)
detected
A
min
A
max
clock sampling time
delay effect will not be
(a)
detected
A
min
A
max
may not be detected
37
ignoring static hazards, we will also not be able to determine if a fault is truly undetect-
able. In this work, we will call a fault undetectable if it is undetectable as a Type A fault
effect.
2.6.1.2 Transitions
A transition on a side input can speed up a faulty to-controlling transition at the output
of a gate. This speed-up can result in the crosstalk slowdown effect not being detected at
an output. The issue is whether to allow the to-controlling transition carrying a crosstalk
delay effect to be sped up by another transition. Two situations can occur. First, if the fault
effect arrives at an output sufficiently late despite such a speedup, the fault effect will be
detected. This can happen either because the magnitude of speedup is small or because the
side input transition is itself delayed (because of the same fault effect or another one). Sec-
ondly, it is possible that certain delay effects can be propagated through a gate only if a
side input also carries the same delay effect, i.e., both transitions are in the same direction,
with one possibly speeding up the other (Figure 2-9). Therefore, even though speed up of
crosstalk delay effect is not desirable, we will allow transitions on side inputs in the hope
that this new propagation condition will detect new faults. Note that static conditions were
used in XGEN, hence this issue was not of any importance.
FIGURE 2-8. Delay effect propagated to an output as a dynamic hazard (a)
fault definitely detected (b) fault may or may not be detected
clock sampling time clock sampling time

A
min
A
max
A
min
A
max
(a) (b)
38
2.6.2 New propagation conditions
We describe the new propagation conditions below. The objective in defining these
propagation conditions is to propagate a crosstalk delay fault effect of interest. In doing so,
we may sensitize the fault effect by other fault effects present in the circuit. Thus, we are
accommodating the propagation of multiple fault effects. We must consider the sensitiza-
tion by means of other fault effects since the simultaneous presence of the two effects may
cause the circuit to fail. Because of this reason, when a fault effect is detected at the output
and the circuit fails to meet the clock period, the failure may be because of the fault effect
that we have been attempting to propagate, or because of the fault effect in the circuit that
we used to sensitize the fault effect of interest.
2.6.2.1 Fault effect propagated as transitions
We now present the propagation conditions that propagate fault effects as transitions.
We assume that a circuit is comprised of NAND, NOR, and NOT gates. To propagate a to-
noncontrolling delay effect at the input of a gate, any of the following four values are
allowed on a side input: a static noncontrolling value, a hazardous noncontrolling value, a
non-hazardous to-noncontrolling transition, or a hazardous to-noncontrolling transition.
To propagate a to-controlling delay effect at an input of a gate, any of the following four
values are allowed on a side input: a static noncontrolling value, a hazardous noncontrol-
FIGURE 2-9. Propagation of multiple fault effects
fault
site
delayed
delayed
39
ling value, a non-hazardous to-controlling transition, or a hazardous to-controlling transi-
tion. Note that each of these conditions results in either a clean or a hazardous transition at
the output; and not a static value or a static hazard. The propagation conditions for a
NAND gate are shown in Figure 2-10.
Lemma 2.1: The above set of propagation conditions define a complete set of condi-
tions for propagating a crosstalk delay effect embedded in a transition.
Proof: First, consider a to-controlling transition carrying a delay effect at an input of a
gate. A static controlling value on any of the side inputs of the gate will block propagation
of the delay effect. A hazardous controlling value or a to-noncontrolling transition, clean
or hazardous, can create a hazardous controlled value at the output, but not a transition.
Thus, the fault effect is either blocked or propagated in the form of a static hazard which
can only lead to a Type B effect at a circuit output and hence cannot guarantee detection.
A similar observation holds for a to-noncontrolling transition carrying a delay effect.
Q.E.D.
FIGURE 2-10. Propagation conditions for an NAND gate (a) to-noncontrolling
faulty transition (b) to-controlling faulty transition
(delay effect)
(delay effect)
(a) (b)
40
2.6.2.2 Fault effect propagated as transitions and static hazards
For to-noncontrolling transitions, the propagation conditions remain the same. We
cannot propagate the to-noncontrolling fault effect as a static hazard since the to-noncon-
trolling transition can only determine the minimum arrival time of the static hazard at the
output and not the maximum arrival time. If the other input also carries a fault effect and
determines the maximum arrival time of the static hazard at the output, that fault effect at
the other input would be propagated when it is specifically targeted.
For a to-controlling transition, we will add three more propagation conditions, namely,
a clean to-noncontrolling transition, a hazardous to-noncontrolling transition, and control-
ling static hazard. For a NAND gate, the logic values at the side input for propagating the
to-controlling fault effect either as a transition or a static hazard are shown in Figure 2-11.
Finally, we have to consider the conditions for propagating a static hazard since the
fault effect may be a static hazard -- both a to-controlling static hazard or a to-noncontrol-
ling static hazard. When we propagate a fault effect as a static hazard, we would like to
have the last transition of the hazard carry the fault effect. The propagating conditions for
a static hazard for which the last transition is a to-noncontrolling transition are the same as
FIGURE 2-11. Propagation conditions for propagating a fault effect either as a
transition or a static hazard
(delay effect)
41
those for a to-noncontrolling transition (shown in Figure 2-10(a) for a NAND gate). The
propagating conditions for a static hazard for which the last transition is a to-controlling
transition are the same as those for a to-controlling transition (shown in Figure 2-11 for a
NAND gate).
2.7 Timing conditions for propagation
In Section 2.3.2, we provided the motivation for new timing conditions for fault prop-
agation. Here we discuss them in more details. We assume that fault effects are propagated
as transitions only.
2.7.1 Timing conditions
We next define a timing condition that specifies which noise effects, among those that
exist on different circuit lines, should be propagated. This is based on the relationship
between arrival time and required time. All possible relationships between the two ranges
are shown in Figure 2-12. Figure 2-12(d) shows a Type A fault effect, and Figure 2-12(b),
(c), (e), (f) show Type B fault effects. Figure 2-12(a) shows a situation where either the
fault effect has not been excited or the fault effect has disappeared during propagation or is
too small to create a failure.
FIGURE 2-12. Pairs of arrival time and required time
R
min
R
max
A
min
A
max A
min
A
max
A
min
A
max
A
min
A
max
A
min
A
max
(b)
(c)
(d)
(e)
(f)
Required time range
A
min
A
max
(a)
Arrival time
ranges
42
Previously in XGEN, if a fault effect was excited, it was always thought of as a fault
effect as it was propagated towards a primary output [10]. In contrast, we consider the pos-
sibility that as a fault effect is being propagated, the situation depicted in condition (a) in
Figure 2-12 can occur and the fault effect can disappear. We next consider the following
important properties of fault effects.
Lemma 2.2: If the maximum arrival time of a transition on a circuit line is less than
the minimum required time, then, if logically propagated, the delay effect on that circuit
line will not be detected at any output.
Proof: Note that the minimum required time on a circuit line corresponds to the maxi-
mum delay of a path from the circuit line to an output. Thus, if the maximum arrival time
of the delay effect is less than the minimum required time, then the fault effect will defi-
nitely not be detected. Q.E.D.
Lemma 2.3: A Type A effect will be detected at a circuit output if the effect can be
logically propagated without speedup to the output, via any path.
Proof: The maximum required time of a circuit line corresponds to the minimum
delay from the circuit line to the primary outputs. A Type A fault effect is one where, by
definition, the minimum arrival time is greater than the maximum required time. There-
fore, if the delay effect can be logically propagated to any output such that the effect is not
sped up, the delay effect is definitely detected. Q.E.D.
Lemma 2.4: A Type B effect may be detected at a circuit output if the transition can be
propagated to the output.
43
Proof: This observation is explained using Figure 2-13. Let X-X’ denote an arbitrary
time that intersects both the arrival time range and the required time range at the points P
and Q, respectively. If, as more assignments are made on inputs, the arrival time shrinks to
an interval within (Amin, Q), and the required time shrinks to an interval within (P,
Rmax), it is no longer possible for the delay effect to create an error. If on the other hand,
the arrival time shrinks to an interval within (Q, Amax) and the required time shrinks to an
interval within (Rmin, P), the delay effect becomes Type A. It is possible that the two win-
dows will overlap even after shrinking. Thus, a Type B effect may be detected. Q.E.D.
We can summarize the above results by the following theorem. We include delay
effects in the noise frontier only if the following condition is satisfied.
Theorem 2.1: A delay effect may be detected if the maximum arrival time is greater
than the minimum required time.
The reason for distinguishing between Type A fault effects and Type B fault effects is
that a test that detects a fault as a Type A effect at an output is qualitatively better than a
test that detects a fault as a Type B effect. In the next chapter, we will describe an algo-
rithm to convert (when possible) a Type B fault effect at an output to a Type A. Also, it is
possible to propagate Type A fault effect in a timing independent manner.
FIGURE 2-13. Required time for Type B fault effect
Rmin Rmax
Amin
Amax
X
X’
P
Q
44
2.7.2 Conditions for algorithm termination
The XGEN algorithm terminates if (i) the minimum arrival time of a transition that
propagates a fault effect to some output is greater than the clock sampling time, or (ii) the
maximum arrival times of all transitions that propagate the fault effect are less than the
clock sampling time at all outputs where the fault effect can reach. In the first case, there is
a Type A fault effect at an output, and in the second case, the fault is undetectable.
Only a slight modification is required to accommodate Type B fault effects. If the fault
effect is propagated to an output but the minimum arrival time is less than the clock sam-
pling time and the maximum arrival time is greater than the clock sampling time (i.e. a
Type B fault effect), then the test vector that produced this condition is noted and the
search for a test for Type A effect continues. If no test is eventually found that detects the
fault as a Type A effect, then the vector that demonstrates a Type B effect can be useful.
2.8 Undetectability of faults
A test for a fault is constructed by attempting to convert unspecified values, xx, on pri-
mary inputs to specified values. This is done by repeating two steps till a test is found,
namely, objective determination and backtracing. During the objective determination pro-
cedure, an objective is chosen for a line that is assigned the value xx. During the backtrac-
ing procedure, lines having the value xx are again chosen. Note that timing relationships
are ignored during this process.
Figure 2-14 shows part of a circuit. Suppose that the logic objective on line E is a s0.
The backtracing procedure specifies a local logic objective of s0 for line A. Suppose that
this logic objective can be satisfied, however, A = s0 does not imply E = s0 (only A = D =
45
s0 implies E = s0). The logic value s0 might be achieved on line D if the minimum arrival
time of the falling transition on line C is greater than the maximum arrival time of the ris-
ing transition of line B. This might be achieved by appropriate transitions on primary
inputs in the input cones for lines B and C. This possibility is unexplored in our current
algorithm but will be addressed in the next chapter.
Note that, as a result, a fault that is determined undetectable by the algorithm
described in this chapter might not be truly undetectable. When we call a fault undetect-
able, we use this limited notion of undetectability.
2.9 Experimental results
We now report experimental results on ISCAS ‘85 benchmark circuits. We have modi-
fied the circuits so that each AND gate, OR gate and buffer are replaced by a NAND gate
and an inverter, a NOR gate and an inverter, and two inverters, respectively. This helps to
use the delay model discussed earlier. We chose 100 targets randomly in each circuit such
that the victim line is located on one of the top few critical paths. We chose a backtrack
limit of 10,000. In the following discussion, if we have not shown the results on a circuit,
it is because no change in fault coverage is observed on that circuit.
FIGURE 2-14. A logic objective may be satisfied if timing relationships are
considered
xx
xx
00
A
B
C
D
E
obj = s0
s0.00 is not s0
46
First we will compare two versions of XGEN, each using the 9-valued algebra. The
first version only employs static propagation conditions on side inputs; the second version
allows both static and hazardous conditions as well as transitions. Both versions are tim-
ing-based, and use the improved gate delay model and support crosstalk computation for
ranges. The first version is called XGEN-S (‘S’ for static as it employs static propagation
conditions only) and the second version is called XGEN-E (‘E’ for extended as it extends
propagation conditions and timing based propagation). Table 2-5 shows the results for
c880, c1355 and c1908 with respect to Type A faults only.
Detected faults: For each of c880 and c1355, the number of detected faults increased
by 6 using the enhanced system. For c880, 7 of the previously aborted faults are now
detected. For c1355, 1 of the previously undetectable faults, 1 fault previously detected as
Type B fault, and 5 of the previously aborted faults become newly detectable. For each of
c880 and c1355, only one of the previously detected faults is now aborted by the new con-
ditions. There is no change in the number of detected faults for c1908.
Undetectable faults: In c880, the number of undetectable faults remain the same. In
c1355, the number of undetectable faults decreased. This is because many targets were
determined to be undetectable using XGEN-S because of the stricter static condition. Cer-
tain faults that were previously thought to be undetectable with static side input condi-
TABLE 2-5. Fault coverage for Type A faults
Circuit
Detectable faults Undetectable faults Aborted faults
Computation time
(seconds)
XGEN-S XGEN-E XGEN-S XGEN-E XGEN-S XGEN-E XGEN-S XGEN-E
c880 26 32 12 12 62 56 10743 9473
c1355 12 18 14 4 74 78 26392 20780
c1908 5 5 8 4 87 91 45059 42030
Total 43 55 34 20 223 225 82194 72283
47
tions, might, in fact, be detected given the enhanced propagation conditions. For c1355,
one of the faults previously thought to be undetectable is now detected, as previously men-
tioned. Also, 4 faults found undetectable in XGEN-S are now aborted in XGEN-E, and 5
faults found undetectable in XGEN-S are now detected as Type B fault effects. For c1908
again, there is a decrease in the number of undetectable faults.
The migration of faults from one class to another, for circuit c1355, is shown in Figure
2-15. Note that one fault that was previously thought undetectable is now detected. Fur-
ther, 5 of the previously aborted faults are now detected as Type A faults, and 14 of the
previously aborted faults are now detected as Type B faults.
We also ran both XGEN-S and XGEN-E with a backtrack limit of 1 million on ten
faults in c1355 that were aborted in both the systems. We show the results in Table 2-6. It
is seen that XGEN-E detects 1 fault while XGEN-S does not detect any, and also XGEN-S
labels 3 faults as undetectable erroneously when they are actually not.
FIGURE 2-15. Change in fault status for c1355
TABLE 2-6. Fault coverage on 10 faults with 1 million backtrack limit
Circuit
Detected faults Undetectable faults Aborted faults
XGEN-S XGEN-E XGEN-S XGEN-E XGEN-S XGEN-E
c1355 0 1 3 0 7 9
12 14
18
4
11
1
4
5
1
Detected Undetectable Type B Aborted
XGEN-S
XGEN-E
19
33
55
45
1
5
14
4
13
5
36
48
While the increase in fault coverage is small, the enhanced version is faster. We report
the computation time when both employ a backtrack limit of 10,000 (Table 2-5). The test
generation times for c880, c1355 and c1908 reduced by 12%, 21% and 7%, respectively,
and the average reduction is 12%.
The average computation time for faults detected as Type A effects is shown in Table
2-7. It is seen that the computation time for the detected faults decrease with the enhanced
system. The average computation time for detected faults reduces by 18%. We do not
compare average computation time for undetectable faults since XGEN-S skips portions
of the solution space where a test may lie and therefore might have a lower computation
time. However, as we have seen, XGEN-S might reach a wrong conclusion that the fault is
undetectable. Similarly, we do not compare average computation time for aborted faults,
since again, portions of the solution space are ignored by XGEN-S.
TABLE 2-7. Average computation time for detected faults
Circuit XGEN-S (seconds) XGEN-E (seconds)
c880 6.54 4.64
c1355 8.19 6.71
c1908 4.27 4.17
Total 19.00 15.52
TABLE 2-8. Fault coverage for Type B faults
Circuit XGEN-S XGEN-E
c432 5 9
c880 17 20
c1355 19 33
c1908 18 34
c2670 16 19
c3540 14 13
c5315 22 32
c7552 30 31
Total 141 191
49
Next, we discuss detection as Type B transition fault effects. The results are shown in
Table 2-8. It is seen that for all circuits except for c3540, there is an increase in the number
of faults detected as Type B effects. The average increase in Type B fault coverage is
6.5%.
Experiments with zero delay model
As stated previously, these test systems employ both Boolean and temporal analysis.
We can turn off the temporal analysis and consider generating a test just based on the
Boolean constraints, such as activate the transitions at A and V , and propagate the effect to
an output. We ignore all gate delays, arrival and required times, and skew. We refer to this
mode of operation as our 0-delay model, and the program as XGEN-0E or XGEN-0S. In
Table 2-9, we compare our results with from XGEN-0E and XGEN-0S. First, note that
XGEN-0E detects more faults than XGEN-0S. We see that in all cases, XGEN-0E
(XGEN-0S) detects more faults than XGEN-E (XGEN-S). This is obviously the case
because XGEN-0E (XGEN-0S) only tries to satisfy the Boolean constraints, which is a
necessary but not a sufficient condition for a test. In other words, fault coverages obtained
TABLE 2-9. Fault coverage with zero delay
Circuit
name
Detected Undetectable Aborted
XGEN-0S XGEN-0E XGEN-0S XGEN-0E XGEN-0S XGEN-0E
c432 44 48 0 0 56 52
c880 82 91 0 0 18 9
c1355 49 79 10 0 41 21
c1908 54 76 5 1 41 23
c2670 65 76 2 1 23 23
c3540 42 62 5 3 53 35
c5315 73 91 0 0 27 9
c7552 60 84 2 2 38 14
Total 469 607 24 7 307 186
50
for XGEN-0S and XGEN-0E are overestimates of actual coverage. Again, as for undetect-
able faults, in all cases XGEN-0E reports fewer undetectable faults than XGEN-0S.
2.10 Conclusion
We have extended an existing test generation methodology for crosstalk fault in the
following ways: (i) in addition to static conditions used previously, clean and hazardous
transitions as well as static hazards are used on side inputs to propagate delay effects, (ii)
the search space is pruned by considering the relationship between arrival and required
times, (iii) a 9-valued algebra is employed. We have also incorporated a simultaneous to-
controlling delay model, whereas only a pin-to-pin delay model was considered before.
Crosstalk computation can now handle timing ranges. Further, we have proposed a relaxed
definition of fault coverage since crosstalk fault coverage tends to be low.
We have seen a 4% increase in fault coverage for Type A fault effects, and a 6.5%
increase in fault coverage for Type B fault effects. Further, the average test generation time
is lower by 12%. Most importantly, our results are more accurate in the sense that previ-
ously some undetectable faults turn out to be detectable.
51
Chapter 3 A complete test generation system for crosstalk delay
fault effects
3.1 Introduction
In the previous chapter, we described a 9-valued algebra used in the generation of tests
for stimulating substantial crosstalk induced delay. We discussed relaxed propagation con-
ditions and improved timing conditions. We noticed, however, that a large number of
faults were aborted. To reduce the number of aborted faults, we have developed a 57-val-
ued algebra and modified our test generation algorithm accordingly.
We start with a set of basis values and derive an algebra with 57 values, including
many composite values. The assignment of a composite value to a circuit node indicates
that any of the basis values comprising the composite value is possible. Using composite
values postpones making a decision until one is absolutely necessary. In one respect, this
makes the search for a test more efficient as it reduces the number of conflicting assign-
ments, hence backtrack steps. On the other hand, it may make the methodology slower
because of the time required to process a large multi-valued algebra. We will discuss the
57-valued algebra, and its derivation, in this chapter. This algebra is derived in a manner
such that it is suitable for timing based test generation.
In addition to this algebra, we will describe other modifications to the test generation
algorithm. First, we have modified the search process. Secondly, we will present an exam-
ple to illustrate how our algebra can lead to situations where the backtracing procedure
cannot progress, and describe how we have modified the backtracing algorithm to handle
this issue by introducing depth first search for an assignment on a primary input. Thirdly,
we consider two issues that are unique to timing based test generation, and related to the
52
interplay between logic and timing. The first issue involves Type B fault effects that are
logically propagated to an output but the timing range at the output line is such that the
minimum and maximum arrival times are respectively less than and greater than the clock
sampling time. We propose a technique to assign more specified values on primary inputs
with incompletely specified values so as to increase the minimum arrival time at the out-
put, that converts a Type B fault effect to a Type A fault effect. The second issue is that a
local logic objective at the output of a gate may be satisfied only by achieving certain tim-
ing relationships at the inputs of the gate. We have developed a procedure to make logic
assignments on primary inputs such that timing relationships necessary for the logic
objective can be satisfied. Further, ignoring these timing based issues result in a limited
notion of undetectability of faults, as a fault that is thought to be undetectable as a Type A
fault effect at an output can actually be detectable as a Type A fault effect.
3.2 Motivation
3.2.1 Need for a new algebra
The assignment of a composite value on a line means that any of the basic values com-
prising the logic value are possible on that line. Consider a case where we know that it is
necessary to assign one of a set of values on a line to detect a target fault. If we arbitrarily
assign a single value from this set to the line, the assignment can lead to a conflict with
values needed at other lines to detect the fault. When this occurs, the test generator has to
backtrack. In contrast, assignment of multiple values keeps possibilities of more specific
assignments open. This allows the implication procedure to capture the interactions
between the values necessary at different lines and eliminate some of the inconsistent
53
choices without any backtrack. Thus, using composite values reduces the number of
unnecessary backtracks. One consequence of using a multi-valued algebra is that it may
increase the amount of space searched. We present an example to illustrate both benefits of
multi-valued algebra (Figure 3-1).
We first present a synopsis of the algebra. In this algebra, we will distinguish between
a hazard and a glitch. A glitch is an unwanted pulse at the output. A circuit with the poten-
tial for a glitch is said to have a hazard. In other words, a circuit with a hazard can some-
times produce a glitch, depending on the input patterns and the electrical characteristics of
the circuit. We will represent a 0 value with an positive pulse by g0, a 1 value with a nega-
tive pulse by g1, a rising transition with a glitch by gr, and a falling transition with a glitch
by gf. A static 0 and a static 1 value are represented by s0 and s1, and a clean rising and a
clean falling transition are represented by cr and cf, respectively. A static 0 hazard is repre-
sented by {s0,g0}, a static 1 hazard by {s1,g1}, a dynamic hazard with a rising transition
by {cr,gr} and a dynamic hazard with a falling transition by {cf,gf}. For steady values and
static hazards, each possible value (s0, g0, {s0, g0}, s1, g1, {s1,g1}) is represented explic-
itly in the algebra. For transitions, clean and hazardous transitions are legal values in the
algebra (cr, {cr,gr}, cf, {cf,gf}). Glitched transitions (gr, gf) cannot occur individually on
circuit lines (we will explain this further).
Suppose that a crosstalk delay effect on the victim line is to be propagated through
gate 1 as shown in Figure 3-1. One question is whether it can be propagated by means of a
s0 value on line D -- this will be the objective that PODEM will try to satisfy. If we use the
9-valued algebra described in Section 2.4, then PODEM algorithm will assign values, by
means of backtracing, to primary inputs P, Q, R, as shown in Figure 3-1(a). The results
54
from forward logic implication on internal lines are also shown. Because C=s1, we are
unable to propagate the delay effect through gate 2 because the noise frontier disappears.
The delay effect might be propagatable if a rising transition (cr or gr) is chosen as the
objective on line D. The alternative logic values are shown in Figure 3-1(b). Once the first
objective, i.e., s0 on line D is determined to not leading to a test, computationally costly
backtracking steps are required before the noise is propagated at the output of gate 2. It is
thus best to keep all logic options open when choosing an objective.
If we choose the composite value {s0, g0, cr, gr} as our objective on line D, then we
leave open the possibility of propagating the fault effect at the output of gate 2 without any
conflict. The resulting values on primary inputs (where hazards are assumed not to exist)
and on internal lines are shown in Figure 3-1(c). We need an additional step -- that of
refining the logic value on line C from {s1,cf,gf} to {cf,gf} to achieve the test -- this can
be done by assigning {cr} on P and {cf} on Q. Note that we do not have a backtrack.
We mentioned that this 57-valued algebra also impacts the space searched. Referring
back to Figure 3-1, there are 5 inputs and each can have one of 4 values -- s0, s1, cr, cf. So,
the total number of vectors is 625 (i.e. 4
5
). In Figure 3-1(a), an initial assignment is made,
and then s0 on P is changed to a cr. This covers 2 vectors. Further, the assignment s1 on Q
is changed to a cf to get a test. Thus, 3 vectors are covered. On the other hand, in Figure 3-
1(c), we start with 2-tuples on each of P, Q and R and refine them. Thus, we cover 8 vec-
tors. We see that the use of multi-valued algebra searches more of the space in this case.
55
FIGURE 3-1. Use of multi-valued algebra
affecting
victim
1
D
C
2
s0
s1
s1
{s1,g1}
{s0,g0}
s0
s1
{s0,g0}
{s0,g0}
P
Q
R
delay effect
affecting
victim
1
D
C
2
cf
cf
{s1,g1}
{cr,gr}
{cr,gr}
{cf,gf}
{cr,gr}
{cr,gr}
cr P
Q
R
affecting
victim
1
D
C
2
{s1,cf}
{s1,cf}
{s1,g1}
{s0,g0,cr,gr}
{s0,cr,gr}
{s1,cf,gf}
{s0,g0,cr,gr}
{s0,g0,cr,gr}
{s0,cr} P
Q
R
(a) Not logically propagated
(b) Logically propagated
(c) Logically propagated with multi-valued algebra
{cr,gr}
{s0, g0}
{cf,gf}
cf
s1
{cf,gf}
56
3.2.2 Need for modifications to test generation algorithm
We modified the test generation algorithm in two ways. First, we incorporated modifi-
cations that are required to integrate the new algebra, and, secondly, we extended it to han-
dle the new timing issue.
3.2.2.1 Extensions required for new algebra
Our algebra is such that, aside from singletons, the only composite values that can be
described as {a,b} are assigned to primary inputs, where and .
Hazardous values are not assigned to primary inputs. Modifications to the search proce-
dure are needed to handle composite values, as we must ensure that after backtracking,
only values in the cross product set S = {s0,s1}x{cr,cf} - {a,b} are assigned to a primary
input, where {a,b} is defined above. The two values in S are assigned individually for an
exhaustive search, if necessary. We will prove that the search procedure is correct, that is,
the entire search space is visited.
Additional modifications are required because our algebra can lead to situations during
backtracing when the local logic objective cannot be backtraced further. In Section 3.4.2,
we will present an example of when backtracing cannot progress along a path to a primary
input. Thus, our backtracing procedure is based on backward depth first search of the input
FIGURE 3-2. Backtracing procedure for one logic objective
as0 s1 , () ∈ bcrcf , () ∈
logic
objective
cannot progress
further
cannot progress
further
reached primary
input
1
2
3
4
5
6
7
8
9
10
57
cone of the location of the first objective. If we cannot find a backtracing objective at the
input of a gate starting from its output, we search other paths in the input cone (of the loca-
tion of the objective). We search in a recursive depth first manner until a primary input is
reached. If no primary input assignment can be made starting with a certain logic objec-
tive, then we look at another logic objective. We thus consider all logic objectives. This
depth first search along paths starting from a circuit node is illustrated in Figure 3-2 where
the numbers show the order in which backtrace explored circuit gates and lines. In Section
3.4.2, we will present an algorithm to handle these types of situations.
3.2.2.2 Extensions required for timing issues
Based on logical conditions, a fault effect can be propagated to a circuit output. Once
timing is considered, the fault effect might be Type B or even undetectable. If it is a Type
B fault effect, it is desirable to make further assignments so as to convert it, if possible, to
a Type A fault effect. We will discuss algorithms for this problem in Section 3.4.3.
In this section, we present an example to illustrate the above point. In Figure 3-3, we
show that replacing the composite value {s1,cr} by {cr} at the first input of the NAND
gate increases the minimum arrival time of the falling transition at the output of the gate
FIGURE 3-3. Converting Type B fault effect to Type A fault effect
cf
{s1,cr}
cr (faulty)
CLK
cf
cr
cr (faulty)
CLK
(a) logically detected but may
(b) logically detected and
not violate timing
violates timing
58
(this follows from the details of the transistor level model) which, in turn, increases the
minimum arrival time at the output of the NOR gate so that it exceeds the clock sampling
time.
We may also want to achieve a logic condition on an internal line to achieve certain
timing effects at output where this logic condition on the internal line, in turn, depends on
timing ranges of arrival times at the input cone. In Figure 3-4, assigning logic values at the
inputs of the input cone of line W may create timing ranges at the input of the NAND gate
such that it refines the {s1,g1} into {s1} on line W. A logic value of {s1} on line W
implies that the minimum arrival time at the output Y depends on the transition on line X,
and not on any transition on line W. In this case where the effect of the hazard on line W
decreased the minimum arrival time on line Y, converting {s1,g1} to {s1} at W makes the
fault detectable.
Just so that the reader can understand why the hazard on line W may decrease the
arrival time of the transition on line Y, we use another example (Figure 3-5). Suppose that
the input to output delay for the NAND gate is 2 units, that the transitions are far apart, and
simultaneous switching does not have an effect on the output delay. In Figure 3-5(a), the
minimum arrival time of the hazard (labeled ‘A’) determines the minimum arrival time of
the rising transition at the output, and in Figure 3-5(b), the minimum arrival time of the
falling transition on the second input (labeled ‘B’) determines the minimum arrival time of
the rising transition at the output. Note that in Fig 3.5(a), the hazard on A occurs before
the transition on B, and as a result, the arrival time range at the output is wider.
59
In the absence of procedures to handle these issues, a fault may have erroneously been
thought to be undetectable. In both of these examples, we would think that the faults are
not Type A detectable when they actually are.
3.3 Proposed algebra
We have developed an algebra with the objective of using it in a PODEM-like timing
based crosstalk test generator. Besides considering the propagation conditions for
crosstalk delay faults, our proposed algebra considers timing based closure. We are not
aware of any other algebra for test generation that has been developed with timing consid-
erations.
3.3.1 Factors influencing choice of algebra
The new 57-valued algebra takes into consideration the following:
(i) set of basic logic values, (ii) new propagation conditions, and (iii) test generation
method.
FIGURE 3-4. Converting Type B fault effect to Type A fault effect
cr
cr (faulty)
{s1,g1}
line W
line X
line Y
CLK
cr
cr (faulty)
s1
line W
line X
line Y
CLK
(a) logically detected but may
(b) logically detected and
not violate timing
violates timing
60

3.3.1.1 Basis values:
The set of eight values that form the basis of the algebra is shown in Table 3-1. Sepa-
rate values are not used to indicate faulty transitions, as we distinguish such transitions
using a tag. Unlike the 9-valued algebra (Section 2.4), {g0} and {g1} are elements of the
57-valued algebra. The composite values {s1,g1}, {s0,g0}, {cr,gr}, {cf,gf} in this algebra
are equivalent to 11, 00, 01, and 10 in the 9-valued algebra, respectively. For the compos-
ite value {s1,g1}, if the maximum arrival time for the falling transition is less than the
minimum arrival time for the rising transition, then we will refine the value to be {g1}.
Similarly, if the minimum arrival time of the falling transition is greater than the maximum
FIGURE 3-5. Hazards at input may increase arrival time range at an output
TABLE 3-1. Basis for the algebra
Basic element Symbol
Static 0 s0
Static 1 s1
Glitched 0 g0
Glitched 1 g1
Clean rising cr
Clean falling cf
Glitched rising gr
Glitched falling gf
(a)
(b)
s1
5 6
5 6
1 2
3 8
7 8
A
BB
61
arrival time of the rising transition (such spurious arrival time ranges may be carried over
from a previous assignment), we can also refine {s1,g1} to {s1}. This is supported by our
timing analysis routines.
Similarly, we can refine {cr,gr} ({cf,gf}) to {cr} ({cf}), however, we cannot refine
{cr,gr} ({cf,gf}) to {gr} ({gf}). We will later see that a glitched transition, rising or falling,
cannot exist as a singleton on a circuit line in our system. This is a shortcoming of our tim-
ing analysis procedure. In other words, {gr} and {gf}, even though they are part of the
basis of the algebra, they cannot occur without the corresponding clean value.
3.3.1.2 Conditions for propagating crosstalk delay as transitions
Table 3-2 lists all eight of the conditions for propagating a fault effect as a transition.
These propagation conditions were described in Section 2.6.2.1.
TABLE 3-2. Propagation conditions for fault effects as transitions
Value Explanation
{s0,g0,cr,gr} Condition on internal line to propagate a faulty
rising transition through an OR gate
{s0,g0,cf,gf} Condition on internal line to propagate a faulty
falling transition through an OR gate
{s1,g1,cr,gr} Condition on internal line to propagate a faulty
rising transition through an AND gate
{s1,g1,cf,gf} Condition on internal line to propagate a faulty
falling transition through an AND gate
{s0,cr} Condition on primary input to propagate a
faulty rising transition through an OR gate
{s0,cf} Condition on primary input to propagate a
faulty falling transition through an OR gate
{s1,cr} Condition on primary input to propagate a
faulty rising transition through an AND gate
{s1,cf} Condition on primary input to propagate a
faulty falling transition through an AND gate
62
3.3.1.3 Conditions for propagating crosstalk delay as transitions
According to the conditions described in Section 2.6.2.2, additional propagation con-
ditions are required for propagating fault effects as static hazards. These conditions for an
OR gate and an AND gate are described in Table 3-3.
3.3.1.4 Test generation method
The PODEM algorithm only uses forward implication, whereas the D-algorithm uses
both forward and backward implications [1]. Thus, we need to deal with values that can
occur due to forward implication. (We would like to point out that previously, algebras
that are closed only with respect to forward implication only have been used with the D-
algorithm [3], [25].)
TABLE 3-3. Propagation conditions for fault effects as transitions and static
hazards
Value Explanation
{g0,g1,gr,gf,s0,cr,cf} Condition on an internal line to propagate a
faulty rising transition through an OR gate or a
faulty static 1 hazard through an OR gate
{g0,g1,gr,gf,s1,cr,cf} Condition on an internal line to propagate a
faulty falling transition through an AND gate or
a faulty static 0 hazard through an AND gate
{s0,cr,cf} Condition on primary input to propagate a
faulty rising transition through an OR gate
(static hazards cannot exist at primary inputs)
{s1,cr,cf} Condition on primary input to propagate a
faulty falling transition through an AND gate
TABLE 3-4. Other initial composite values
Value Description
{s0,g0,s1,g1,cr,gr,cf,gf} Unspecified value on any line
{s0,s1,cr,cf} Unspecified value on primary input
63
3.3.2 Truth tables for multi-valued algebra
Please refer to Table 3-5, Table 3-6 and Table 3-7 for AND, OR and NOT operations
involving the elements in the basis of the algebra. Suppose composite values v
1
, v
2
,..., v
k
exist at the inputs of a k-input Boolean gate that implements the function f, where f is
AND, OR, NAND or NOR. Also, let , where each e
ij
is a basis ele-
ment. Then, the composite value at the output of the gate is given by
.
The union is taken over all j, l,..., m. If f is the function NOT, then
.
TABLE 3-5. AND operation for elements in basis
s0 s1 cr cf g0 g1 gr gf
s0 s0 s0 s0 s0 s0 s0 s0 s0
s1 s0 s1 cr cf g0 g1 gr gf
cr s0 cr cr g0 g0 gr gr g0
cf s0 cf g0 cf g0 gf g0 gf
g0 s0 g0 g0 g0 g0 g0 g0 g0
g1 s0 g1 gr gf g0 g1 gr gf
gr s0 gr gr g0 g0 gr gr g0
gf s0 gf g0 gf g0 gf g0 gf
TABLE 3-6. OR operation for elements in basis
s0 s1 cr cf g0 g1 gr gf
s0 s0 s1 cr cf g0 g1 gr gf
s1 s1 s1 s1 s1 s1 s1 s1 s1
cr cr s1 cr g1 gr g1 gr g1
cf cf s1 g1 cf gf g1 g1 gf
g0 g0 s1 gr gf g0 g1 gr gf
g1 g1 s1 g1 g1 g1 g1 g1 g1
gr gr s1 gr g1 gr g1 gr g1
gf gf s1 g1 gf gf g1 g1 gf
v
i
e
i1
e
i2
, … , e
iu
i
{} =
fv
1
v
2
… v
k
,, , () fe
1 j
e
2l
… e
km
,, , () 1 jv
1
≤≤ 1 lv
2
… 1 mv
k
≤≤ ,, ≤≤ , ∀
∪
=
f v1 () fe
11
() fe
12
() …fe
1u
1
( ∪∪ =
64
3.3.3 Timing ranges for composite values
Suppose we have a composite value consisting of a static value and a transition. Then
the arrival time for that value is the arrival time for the transition on that line. If a compos-
ite value consists of elements that have one or more transitions, then the minimum arrival
time of the rising (falling) transition for that composite value is the minimum of the arrival
times for all rising (falling) transitions, and the maximum arrival time of the rising (fall-
ing) transition for that composite value is the maximum of the arrival times for all rising
(falling) transitions. If a composite value consists of a static value and at least another
value which has transitions, then the transitions of the non-static values determine the
minimum and maximum arrival and transition times.
3.3.4 Timing computation for multi-valued algebra
Whenever an assignment is made on a primary input, logic implication is first carried
out, followed by forward timing analysis. Since we record only minimum and the maxi-
mum arrival times, we lose the ability to identify transitions that definitively have glitches.
TABLE 3-7. NOT operation for elements in basis
s0 s1 cr cf g0 g1 gr gf
s1 s0 cf cr g1 g0 gf gr
FIGURE 3-6. Shortcoming of out timing analysis procedure
R
F
65
We explain this in more detail with the situations depicted in Figure 3-6. Suppose per-
forming logic implication on the NAND gate gives us an output value of {cr,gr}. By con-
sidering the logic values at the inputs as well as their timing and additionally input to
output delays, the output logic value can be reduced to {gr}. This is possible if we record
the arrival time for each individual transition. However, our logic and timing analysis pro-
cedures does not record the arrival time for each individual transition, and cannot make
this refinement. In our example, the arrival time range for the rising transition will span the
minimum arrival time of the first rising transition and the maximum arrival time of the sec-
ond rising transition. The range for the rising transition is denoted by R. Similarly, the
range for the falling transition is given by F. We have ranges of arrival times associated
with transitions because the transition can arrive at any time in that range. We also lose the
information that we have more than one transition of the same type during this range (for
the rising transition). Thus, the falling transition may precede the rising transition entirely
thus resulting in a clean transition. Therefore, the procedure cannot predict that the glitch
is actually present during the transition. On the other hand, if rising transition precedes the
falling transition entirely, then, again, a glitch cannot occur on a circuit line. Thus, even
though {gr} and {gf} form the basis of the algebra, they are not elements of the algebra.
We describe this in more detail using Figure 3-7.
Assume that logic implication returns {cr,gr} on a circuit line. We go through different
combinations of arrival time ranges of rising and falling transitions. Let the arrival time
range for the rising transition be (A
R
min
, A
R
max
) and the arrival time range for the falling
transition be (A
F
min
, A
F
max
). Six possible situations can arise:
66
(i) A
F
max
< A
R
min
: This situation is impossible as that would imply a clean transition.
(ii) A
F
min
> A
R
max
: Same as above.
(iii) A
R
min
< A
F
min
< A
R
max
< A
F
max
: Both a clean and a hazardous rising transition
are possible.
(iv) A
F
min
< A
R
min
< A
F
max
< A
R
max
: Same as above.
(v) A
R
min
< A
F
min
< A
F
max
< A
R
max
: Same as above.
(vi) A
F
min
< A
R
min
< A
R
max
< A
F
max
: Same as above.
FIGURE 3-7. Relationship between arrival times of falling and rising
transitions of a hazardous rising transition
A
R
min A
R
max
A
F
min
A
F
max
A
F
min
A
F
min
A
F
min
A
F
min
A
F
min
A
F
max
A
F
max
A
F
max
A
F
max
A
F
max
(i)
(ii)
(iii)
(iv)
(v)
(vi)
67
Cases (i) and (ii) describe the situations when the falling transitions are spurious and
should be ignored. In none of these cases, we can say that a glitched transition definitely
occurs.
3.3.5 Transitive closure
The transitive closure procedure ensures that an algebra is complete. That is, for any
allowable set of values belonging to the algebra at the input of a gate and a valid gate oper-
ation, the value formed by applying the operation to the set of input values also belongs to
the algebra. Transitive closure guarantees that the resulting algebra meets the complete-
ness criterion [3], [25]. In our case, there are four possible operations: (i) NAND, (ii)
NOR, (iii) NOT, and (iv) timing. We will shortly describe the timing based operations. We
determined the transitive closure, starting with 16 initial values. These 16 values consist of
all values shown in Table 3-1 and Table 3-2, and, additionally, the unspecified values as
shown in Table 3-4. The process of transitive closure ensures that the resulting value is an
element of the algebra (i) for any two values and the NAND and NOR operation, (ii) for
any value for the NOT operation, and (iii) for timing based operations. We used an auto-
mated program to determine the transitive closure.
3.3.5.1 Propagation by transitions only
We first present the algebra for propagation by means of transitions only. The algebra
consists of 56 values. We also use an additional value which is the null value. Thus the
algebra has 57 values. We considered the propagation conditions shown in Table 3-2. The
algebra is shown in Table 3-8. The seventh logic value is the (completely) unspecified
value and will also be denoted as vxx.
68
3.3.5.2 Propagation by transitions and static hazards
When we determine the transitive closure for values shown in both Table 3-2 and
Table 3-3, we obtain a 73-valued algebra. The new values are shown in Table 3-9. Note
that these values are not used in the test generator implemented in software but are pre-
sented for use in future implementations. Also, note that the propagating the crosstalk
TABLE 3-8. 57 valued algebra
# Values # Values # Values
1 s0 20 gf cf 39 g0 gr gf s0 s1 cr cf
2 s1 21 g0 g1 gr gf s0 cr cf 40 g1 gr gf s0 s1 cr cf
3 cr 22 g0 g1 gr gf s1 cr cf 41 g1 s0 cr cf
4 cf 23 g0 s0 s1 cr cf 42 g0 s1 cr cf
5 g0 24 g1 s0 s1 cr cf 43 g0 g1 gr s0 s1 cr cf
6 g1 25 g1 gr cr 44 g0 g1 gf s0 s1 cr cf
7 g0 g1 gr gf s0 s1 cr cf 26 g1 s1 cr 45 g1 cr
8 g1 gr s1 cr 27 g1 gf cf 46 g1 cf
9 g1 gf s1 cf 28 g1 s1 cf 47 g0 cf
10 g0 gf s0 cf 29 g0 gf cf 48 g0 cr
11 g0 gr s0 cr 30 g0 s0 cf 49 g1 gr s0 s1 cr cf
12 s0 cr 31 g0 gr cr 50 g1 gf s0 s1 cr cf
13 s0 cf 32 g0 s0 cr 51 g0 gf s0 s1 cr cf
14 s1 cf 33 gr s0 cr 52 g0 gr s0 s1 cr cf
15 s1 cr 34 gf s0 cf 53 g0 g1 gf s0 cr cf
16 s0 s1 cr cf 35 gf s1 cf 54 g0 g1 gr s0 cr cf
17 g0 s0 36 gr s1 cr 55 g0 g1 gr s1 cr cf
18 g1 s1 37 g1 gr gf s0 cr cf 56 g0 g1 gf s1 cr cf
19 gr cr 38 g0 gr gf s1 cr cf 57 Null
TABLE 3-9. Additional values in 73 valued algebra
# Values # Values
1 s0 cr cf 9 g1 s1 cr cf
2 s1 cr cf 10 g1 gr s1 cr cf
3 gr gf s0 cr cf 11 g1 gf s1 cr cf
4 g0 gr gf s0 cr cf 12 g0 gf s0 cr cf
5 g0 s0 cr cf 13 g0 gr s0 cr cf
6 g0 gr gf cr cf 14 g0 cr cf
7 gr gf s1 cr cf 15 g1 cr cf
8 g1 gr gf s1 cr cf 16 g1 gr gf cr cf
69
delay fault effect both as transition and hazards is one of the issues that makes the test gen-
erator complete.
3.3.5.3 Timing based closure
It is not possible to tell a priori the timing relationships in a circuit. For example, we
cannot tell, without knowledge of circuit delays and input patterns, whether or not a glitch
will appear on a line. The timing relationships between arrival time ranges of rising and
falling transitions on a circuit line will be known only as the test generation process
unfolds. Therefore, we will have to allow for both the possibilities of a glitch existing and
not existing on a circuit line. Thus, new logic values can be created from an existing logic
value due to timing conditions. As an example, the value {g1,cr} was included in our alge-
bra when it was generated from the value {s1,g1,cr} because there is a possibility that the
line on which this value exists may actually have a glitch. This is shown in Figure 3-8.
Definition 5:. The timing based operation ensures that for every composite value that
contains a subset {a,g} where and g is the corresponding value with a
glitch: (i) the value a along with the remaining values other than g in the composite value
must belong to the algebra, and
FIGURE 3-8. Timing based closure
{s1, g1, cr}
{s1, cr} {g1,cr}
(already in algebra
as shown in Table 3.2)
(new value and
included in algebra)
a s0 s1 cr cf ,, , {} ∈
70
(ii) g (unless it is gr or gf) along with the remaining values other than a in the compos-
ite value must belong to the algebra. The values gr and gf are not included in a new value
without the corresponding glitch free value since, as we discussed before, gr (gf) cannot
exist on a line unless cr (cf) also exists on the line.
To the best of our knowledge, no other algebra has considered timing based transitive
closure. Next, we want to prove that the timing based operation does not affect logical
detectability of a fault. To that end, we define the following.
Definition 6:. The hazard-free value of a basis value v belonging to the algebra is defined
as:
v, if ,
s0, if v = g0,
s1, if v = g1,
cr, if v = gr, and
cf, if v = gf.
Definition 7: The hazard-free value for a general composite value , where v
i
are basis values, is
where hazard-free value of basis v
i
is defined in Definition 6.
Lemma 3.1: The timing based operation does not make a logically detectable fault
undetectable.
v s0 s1 , cr , cf , {} ∈
vv
i
∪
=
hazardfreevalue v
i
()vv
i
∪
= ,
∪
71
Proof: The timing based operation introduces two new values for every value of the
type {a, g, v
1
, v
2
,..., v
k
}. These two values are {a, v
1
, v
2
,..., v
k
} and {g, v
1
, v
2
,..., v
k
}
(assuming g is neither gr nor gf in which case only one new value, {a, v
1
, v
2
,..., v
k
}, is
introduced). Note that in Definition 5, the hazard-free value of a glitch free element a and
the hazard-free value of g, the corresponding glitched value, are the same, namely, a. It is
the hazard-free value that determines logical detection. Thus, if a fault is logically
detected when the logic value is not refined based on timing, it will also be logically
detected when timing based refinement is carried out. Q.E.D.
3.4 Algorithm for test generation
3.4.1 Modified search procedure
In this section we describe the modified search procedure that employs this 57-valued
algebra (see Figure 3-9).
Recall that if a composite value {a,b} is assigned to a primary input, where
and (note that {s0,s1} and {cr,cf} do not belong to the algebra
and cannot be assigned to an input), then after backtracking, only assignments of values in
the set {s0,s1,cr,cf} - {a,b} need to be attempted. For example, if {s0, cr} is assigned to a
primary input and the algorithm backtracks, then only singleton values in the set {s0, s1,
cr, cf} - {s0, cr} are attempted, i.e., {s1} and {cf} are assigned individually.
If a singleton value a is first assigned to the primary input and the algorithm back-
tracks, then all three values in {s0, s1, cr, cf} - {a} are considered individually. Note that
there is no logic value of the form {a,b,c} in the algebra where each of a, b and c belongs
to the set {s0, s1, cr, cf}.
as0 s1 , () ∈ bcrcf , () ∈
72
Thus, only non-hazardous singleton values or composite values comprising of two
basic and non-hazardous elements are assigned to primary inputs.
3.4.1.1 Proof of correctness
Lemma 3.2: If a primary input assignment exists which is a logical test for a given
fault, then our search methodology detects the fault, either as a Type A or a Type B fault
effect, assuming that we allow for sufficient number of backtracks.
Proof: If a composite value {a,b} is assigned to a primary input, then the two values in
the set {s0,s1,cr,cf} - {a,b} are assigned to the input if the composite value does not lead
to a test. Similarly, if a singleton value {a} is assigned first, then the other three values in
the set {s0,s1,cr,cf} - {a} are attempted during the search. Thus, all possible logical
assignments are made and if a logical test exists for a fault, the fault will be logically
detected either as a Type A fault effect or Type B fault effect.
Further, note that the algorithm backtracks only when the noise frontier is empty or the
fault excitation conditions cannot be satisfied. Therefore, if we have an assignment {a,b}
on a primary input which does not lead to a test, however the singleton {b} leads to a test,
then the test generator does not backtrack from the state with the assignment {a,b} but
subsequent assignments refine the assignment {a,b} to {b}. This ensures that the test is
found. Q.E.D.
The search algorithm only guarantees that a fault will be detected logically. Thus, the
fault may be detected as a Type B fault effect when a test exists that detects it as a Type A
fault effect. We will discuss algorithms to convert Type B fault effect at an output to Type
A fault effect later in this chapter.
73

FIGURE 3-9. Modified search algorithm
modified_xpodem()
{

if terminating condition reached
return;
(v,line) = determine_logic_objective();
(v
a
,input
a
)= backtrace(v,line);
if (xpodem() == SUCCESS)
return SUCCESS;
switch(v
a
):
case {s0 cr}:
assign s1 on input
a
;
logic_and_timing_implication();
if (xpodem() == SUCCESS)
return SUCCESS;

assign cf on input
a
;
logic_and_timing_implication();
if (xpodem() == SUCCESS)
return SUCCESS;
case {s0 cf}:
case {s1 cr}:
assign vxx on input
a;
logic_and_timing_implication();
return FAILURE;
break;
case {s1 cf}:
case {s0}:
case {s1}:
case {cr}:
case {cf}:
}
........
........
........
........
........
........
........
74
3.4.1.2 Search complexity
One issue is whether the branching options, and in effect the space searched, is depen-
dent on the number of values in the algebra. Every logic value that can be assigned to a
primary input starting with a partial set of primary input assignments is a branching option
from that partial assignment.
Note, from the algorithm described in Figure 3-9, that if a composite value is assigned
to a primary input and it does not lead to a test, then two additional values may be tried on
the same input. If a single value gets assigned and it does not lead to a test, then three more
values may be tried on that input. Thus, only a small number of values are used by the
search procedure. In other words, the worst-case search complexity is independent of the
number of logic values in the algebra. The worst-case search complexity is dependent on
the number of assignments that can be made on primary inputs, as is characteristic of
PODEM.
However, the size of the truth table increases with the number of values in the algebra,
and therefore the complexity of the backtracing procedure increases since this procedure
has to consider all the entries in the truth table to determine a backtracing objective. We
will describe the backtracing procedure in the next section.
One last issue is the impact of the size of the algebra on the logic implication proce-
dure. Note that logic implication is based on the truth table lookup, so implication takes
constant time and is independent of the number of logic values.
75
3.4.2 Backtracing procedure based on depth first search
We first discuss the traditional backtracing procedure. In XGEN-E, propagation objec-
tives are assigned to lines that are currently unspecified. Given a gate output whose output
value is unspecified, backtracing is performed such that an input of the gate is chosen, and
this procedure continues until a primary input is reached. This procedure guarantees that
the value vxx at a primary input is always reached and can be refined, and that a primary
input assignment can be made starting with a logic objective. Thus, the search for a test
vector can evolve until a vector is found or the fault is proven to be undetectable, assuming
the backtrack limit is not reached. However, our algebra complicates the backtracing pro-
cedure.
For fault excitation, {cr} and {cf} are chosen on the aggressor line and {cr, gr} and
{cf,gf} are chosen on the victim line as objectives. The difference is because we want a
sharp transition on the aggressor line and a hazardous transition may not be sharp. For
fault propagation, the objective on a circuit line is chosen by set intersection between the
existing logic values and a value appropriate for the faulty transition and the gate through
which propagation is attempted, as described in Table 3-2. The existing logic value on the
line on which the logic objective is chosen may not be vxx, and also the values on the
inputs to the gate to which this is an output may not be vxx (they may be composite values
that are subsets of vxx). Given this scenario, we have to ensure that a logic assignment can
be found on the gate’s input, and if not, we should search the entire input cone of the gate
so as to satisfy the logic objective. The reader should refer to Figure 3-10, where we dem-
onstrate that backtracing may not lead to logic values at the inputs of a gate. No combina-
76
tion of allowable subsets of existing values at the inputs can result in the objective at the
output.
For the convenience of the reader, we first describe the baseline backtracing algorithm
for multi-valued algebra which we adopted [32]. The inputs to this algorithm are: (i) a
gate, (ii) a local logic objective at its output, and (iii) a gate input of interest. The following
is done within the procedure determine_objective() in Figure 3-11. Given the
existing logic value at the output and the local logic objective at the same line, the two val-
ues are intersected to determine a new logic value, say v. If this is a null value, then the
procedure returns FAILURE. Otherwise we search the truth table of the gate for any one
combination of logic values at the inputs of the gate for which the exact value v is possible
at the output (not a subset or superset of v). We then intersect these logic values with the
existing logic values at the respective inputs of the gate. If any of the values obtained from
set intersection at the inputs is the null value, then that input combination is not accept-
able. If the set intersection does not refine the logic value at the input of interest, then that
input combination is not acceptable (refinement is necessary so that the state of the test
generator can evolve -- otherwise the algorithm is stuck in an infinite loop). Otherwise,
among all possible choices for refined, non-null combinations at the inputs of the gate, we
choose the one which has the maximum set size at the input of interest, i.e., has the maxi-
FIGURE 3-10. Backtracing of objective at gate output not possible
()
{g0,s1,cr,cf} -> {s1,cr}
s1
{g1,cr}
{s1,cf}
77
mum number of basis elements. This is done to keep the maximum number of possibilities
open after assignment such that a subsequent choice is less likely to lead to a conflict. The
reader is referred to [32] for an example of this algorithm. The problem to which this base-
line backtracing algorithm was applied did not need a recursive depth first search.
FIGURE 3-11. Modified backtracing procedure
xbacktrace(piassign,obj)
{
if (obj.node.type is primary_input)
{
if (obj.node.value is refined from value on primary_input)
{

piassign = obj;
return SUCCESS;
}
else
return FAILURE;
}
else
{
for (i=0; i < obj.gate.num_inputs; i++)
{
value = determine_objective(obj,gate at input i);
if (xbacktrace(obj_new,piassign) == SUCCESS)
return SUCCESS;
if (value is refined from value on line i)
{
}
}
return FAILURE;

}
}
if not last objective
else
{
retval = force_pi_assignment(obj, piassign);
if (retval == SUCCESS)
return SUCCESS;
else

return FAILURE;
}
78
Next, we discuss how we have modified this algorithm. Once an objective is deter-
mined, we search the entire input cone of the objective line until a primary input is found
to which a refined, non-null logic value assignment can be made. We do this by proceed-
ing along a gate input of interest from the location of the logic objective. If no input on
which an assignment can be made is found for a logic objective, then we proceed with
another gate input of interest at whose output the logic objective has to be satisfied. This is
a recursive procedure that searches the entire input cone. If no primary input can be found
on which an assignment can be made, then we proceed with another logic objective. Thus,
we search the entire list of objectives. If no objective can be found for which an assign-
ment can be made, then we force a primary input assignment arbitrarily. This, in turn,
forces the test generator to evolve. Thus, our backtracing procedure searches the input
FIGURE 3-12. Modified search for recursive backtracing
flag = FALSE;
while (flag == FALSE)
{
logic_obj = choose_objective();
if (logic_obj is NULL)
return FAILURE;
if ((pi_assignment = backtrace(logic_obj)) != SUCCESS)
{
if (excitation mode) or (all objectives searched)
return FAILURE;
else
exclude logic_obj
}
else
flag = TRUE;
}
make pi_assignment and proceed with search

determine_all_logic_objectives()
from further consideration;
79
cone of a logic objective. This algorithm is described in Figure 3-11. Note that in the itali-
cized portion of the algorithm, all gate inputs are searched for a new objective. Also, note
that the algorithm is recursive.
In a traditional PODEM algorithm, the objective determination procedure is followed
by the backtracing procedure. In the case that an objective cannot be identified, the
PODEM procedure backtracks. For example, if the noise has already been excited and the
noise frontier is empty, then no logic objective can be found. In our case, we repeat the
objective determination and backtrace procedures in an iterative loop until a primary input
assignment is made, one that refines the existing logic value at that input. If such an
assignment cannot be made, then the PODEM procedure backtracks. We describe this part
of the algorithm in Figure 3-12.
In Figure 3-13, we illustrate the execution of this algorithm. At input A of gate 2,
{s1,g1,cr,gr} is chosen as the logic objective to propagate the faulty transition (obtained
from Table 3-2). After intersection with the existing value there (which is {g0,s1,cr,cf}),
we derive the logic objective {s1,cr}. However, note that this is not achievable at the out-
put of gate 1. The reader can verify that no combination of logic values at the inputs of
gate 1 will satisfy {s1, cr} at the output. Thus, another logic objective, namely, {s1,cf} on
input B is identified. Note that {s1,cf} can be satisfied on this line, and will propagate the
faulty transition through gate 4. This example is taken from an actual run of our software.
Note that depth first search can be exponential if there are exponential number of paths
between the location of a logic objective and a primary input. However, we can avoid the
exponential complexity by assigning flags to nodes that have already been visited. We will
show in the experimental section that the computation time for our proposed backtracing
80
procedure is very small compared to the overall test generation time. Hence, we did not
need to implement this idea of using flags.
3.4.3 Converting Type B fault effect to Type A fault effect
Often a fault effect is logically propagated to a circuit output by a test, but the desired
timing requirement that the minimum arrival time be greater than the clock sampling time
is not met, that is, the arrival time range at that output “straddles” the clock sampling time.
Since the arrival time of a transition at an output depends on the input stimulus, the
problem is to refine the input assignments while preserving the assignments in the partial
vector that met the logic requirements (i.e. we do not discard assignment and search else-
where in the space). The goal is to have the minimum arrival time be greater than the
clock sampling time. There is, however, a possibility that the additional assignments to the
FIGURE 3-13. Example illustrating modified backtracing algorithm
{g0,s1,cr,cf}
s1
{g1,cr}
{s1,cf}
{s0,s1,cr,cf}
{s1}
{s0,s1,cr,cf}
(faulty)
(faulty)
A
1
2
34
B
81
partial vector that we achieve does not make the minimum arrival time greater than the
clock sampling time may not exist in the subspace. Furthermore, such an assignment may
exist elsewhere in the search space. In the following, we discuss our proposed solution to
this problem that preserves the current partial assignment.
Every time a new input assignment is made and timing analysis is performed, the
arrival time of the crosstalk delay effect at an output is compared with the clock sampling
time to see whether the fault has been detected or cannot be detected. If the minimum
arrival time of the propagated transition is greater than the clock sampling time at some
primary output, then the fault is considered detected. If the maximum arrival time of prop-
agated transition is less than the clock sampling time at all circuit outputs, then the fault
cannot be detected by any assignment obtained by refining the current assignment. At the
same time, we check whether it has logically propagated to an output and the straddling
timing condition occurs -- if so, a flag is set and the outputs where the straddling cases
occur are recorded.
If this flag is set, the PODEM procedure continues in a range-shrinking search mode
where we try to determine additional input assignments so that the minimum arrival time
range at the output will increase and the vector will meet the timing requirement of a test.
The function for objective determination that determines a new objective for fault excita-
tion or propagation has been modified to choose a primary output and a logic objective.
We have italicized a portion of this algorithm in Figure 3-14 for determination of logic
objectives to show how the procedure has been modified. Note that, if the range shrinking
flag is set, increasing minimum arrival time at an output is given higher precedence, com-
pared to choosing an objective from the noise frontier. This is desired because, at this
82
point, the fault has been detected as a Type B fault effect, and a Type A effect may be
achieved with only a few additional assignments.
The function choose_primary_output_with_straddling() chooses an
output heuristically, i.e., it selects a primary output associated with a Type B effect having
the largest value of Amin.
We now describe the procedure for generating the set of logic objectives for increasing
Amin. We consider a single two input NAND gate. Suppose that the objective is to
increase the minimum arrival time of the falling transition at its output. The inputs of the
gate are scanned sequentially, and the following procedure applies to each input of the
gate. If the input under consideration has a value that is a rising transition (clean or hazard-
ous) or a hazardous 1 value, then the procedure is called recursively with the objective of
increasing the minimum arrival time at that input. Suppose that the input under consider-
FIGURE 3-14. Modified objective determination procedure
OBJ xobjective( void )
{
if (logic objective not set at aggressor)
OBJ = objective at aggressor;
else if (logic objective not set at victim)
OBJ = objective at victim;
else if (range_shrinking_flag is set)
{
po = choose_primary_output_with_straddling();
determine_logic_objectives_
list =

OBJ = an element from list;
}
else if (noise frontier is not empty)
{
OBJ = choose gate from noise frontier
}
}
and corresponding logic value;
for_increasing_min_arrival(po);
83
ation has a rising transition and at least one other value. Then a rising transition on that
line is chosen as the logic objective. This follows from the transistor level property that
simultaneous rising transitions result in maximum arrival time of the output falling transi-
tion for a NAND gate, among all possible input combinations of the gate, assuming that
the transitions at the different inputs occur reasonably close in time. Choosing a rising
transition on the input thus keeps the possibility of achieving simultaneous rising transi-
tions open. Note that this will not work with a pin-to-pin delay model since skew does not
have an impact on the gate delay. The recursive procedure stops at primary inputs.
We now describe how the algorithm works at every logic gate. The complete set of
decisions for a NAND gate is shown in Table 3-10. If the value at the output of the gate is
{s0,g0} or {s1,g1}, and we want to increase the minimum arrival time, in effect, we
attempt to increase the minimum arrival time of the first transition, i.e., a rising transition
for {s0,g0} and a falling transition for {s1,g1}. The algorithm
determine_logic_objectives_for_increasing_min_arrival(), which
is essentially described in Table 3-10, is shown in Figure 3-15. The overall objective is to
increase the minimum arrival time at the output of the NAND gate. The reader can verify
TABLE 3-10. Logic objectives to increase min arrival time (NAND output)
Current logic
value at
output Current logic value at input Decision taken
cr or {cr,gr} cf, {cf,gf} recursive call from input node
composite value containing s1 s1 on input is a logic objective
cf or {cf,gf} cr, {s1,g1} recursive call from input node
composite value containing cr cr on input is a logic objective
{s0,g0} cf, {cf,gf} recursive call from input node
composite value containing s1 s1 on input is a logic objective
{s1,g1} cr, {s0, g0} recursive call from input node
composite value containing cr cr on input is a logic objective
84
FIGURE 3-15. Algorithm to determine logic objectives for increasing minimum
arrival time at output
determine_logic_objectives_for_increasing_min_arrival(gate)
{
if (gate is primary input)
return;
else
{
switch(gate->type)
{
case NAND:
switch (gate->logic_value)
{
case {cr}:
case {cr,hr}:
for (i=0; i < gate->inputs; i++)
{
if (gate->input[i]->logic_value is cf, {cf,gf})
determine_logic_objectives_for_increasing_min_arrival(gate->input[i]);
else if (gate->input[i] is composite and contains s1)
s1 on gate->input[i] is a possible logic objective;
}
break;
case {cf}:
case {cf,gf}:

for (i=0; i < gate->inputs; i++)
{
if (gate->input[i]->logic_value is cr or {s1,g1})
determine_logic_objectives_for_increasing_min_arrival (gate->input[i]);
else if (gate->input[i] is composite and contains cr)
cr on gate->input[i] is a possible logic objective;
}
break;
case {s0,g0}:
same as case {cr}, {cr,gr} since minimum arrival time
of rising transition has to be increased
break;
case {s1,g1}:
same as case {cf}, {cf,gf} since minimum arrival time
of falling transition has to be increased
break;
}
case NOR:
{
.......
}
}// switch (gate->type)
}
}
//case NOR
//else
85
that when the output is {cr} or {cr,gr}, if the input has a {cf} or {cf,gf} or {s1,g1}, then a
recursive call is made from that input; else if there is a composite value containing s1, then
s1 on that input is chosen as the logic objective.
Note that we are attempting to use the transistor level properties to increase the mini-
mum arrival time at the output. Thus, for a to-controlling transition at the output, we
would like to achieve as many to-noncontrolling values on the inputs as possible. For a to-
noncontrolling transition at the output, we would like to achieve as many static noncon-
trolling values at the inputs as possible. This results in increasing the gate delay. For a 2-
input NAND gate, when we have a rising transition at an input and a falling transition at
the output, we would like to achieve a rising transition at the second input. It is possible
that, in this example, a rising transition value on the first input, combined with a static 1
value on the second, would result in a larger minimum arrival time at the output, as the
vector at circuit inputs that produces this second combination may result in a larger mini-
mum arrival time for the transition at the first input and, therefore the output. However,
choosing a rising transition on the second input instead of a static 1 (according to the algo-
rithm) does not exclude the possibility of later considering a static 1 on that second input,
since the search procedure can backtrack from the resulting input assignment.
FIGURE 3-16. Converting Type B fault effect to Type A fault effect
cf
{s1,cf}
A
B
C
W
X
86
We present an example that illustrates the algorithm (Figure 3-16). To increase the
minimum arrival time of the falling transition at the output C, we choose s1 as a logic
objective on line B. Next, the test generation algorithm will seek an assignment on a pri-
mary input cone in X such that the logic objective {s1} can be satisfied on line B. Note
that choosing a primary input assignment in the input cone X is no different from choosing
a primary input assignment starting with a logic objective for fault excitation or propaga-
tion.
We present yet another example to illustrate the approach in Figure 3-17. Note that cr
at the second input of the NAND gate might increase the minimum arrival time at the out-
put, so a logic objective of cr on this second input of the NAND gate would backtrace to a
cr on line B.
We now explain why {cf} on line A and {s1} on line B in Figure 3-16 increase the
minimum arrival time at the output. In other words, we explain the underlying transistor
phenomenon. In Figure 3-18(a) and Figure 3-18(b), we show the situation when the transi-
tion on the top input is not affected by crosstalk delay. We see that, in both cases, the clock
FIGURE 3-17. Type B to Type A
s1
{s1,cr}
{s1,cr}
A
B
C
87
sampling time is met. The arrival time at the output for case (b) is less than that for case
(a). We assume that the arrival times are t1 and t2, respectively. With crosstalk delay, the
same observation is true, but the s1 on the second input may push the arrival time at the
gate output past the clock sampling time (Figure 3-18(c)).
Finally, the reader should note that our delay model considers simultaneous to-control-
ling transitions but not simultaneous to-noncontrolling transitions. So, we present the han-
dling of simultaneous to-noncontrolling transitions to convert a Type B fault to a Type A
fault in this section (as in Figure 3-17) only for the sake of completeness. The implemen-
tation of this idea is part of future work.
3.4.4 Timing based resolution of logic values
We present an example to illustrate the issue and then we will present a solution.
Assume a 2-input NAND gate with clean rising and clean falling transitions at its two
FIGURE 3-18. Underlying transistor phenomenon
s1
clock sampling
time
(a)
(b)
No crosstalk delay
s1
clock sampling
time
(c)
(d)
Crosstalk
delay
Crosstalk
delay
With crosstalk delay
t1 t2
t2 t1
88
inputs, and {s1, g1} at its output. Suppose the local backtracing objective at the gate out-
put is to refine the output value to s1. The s1 value at the output might be achieved if cer-
tain timing conditions are satisfied at the inputs. This situation is shown in Figure 3-19.
The {s1,g1} at the output of the NAND gate can be refined to {g1} if the maximum arrival
time of the falling transition is less than the minimum arrival time of the rising transition.
It can be refined to a {s1} if the minimum arrival time of the falling transition is greater
than the maximum arrival time of the rising transition.
Our objective is to design a procedure for determining the logic objectives at the input
cone of C so that the value {s1,g1} ({s0,g0}) can be refined to either s1 or g1 (s0 or g0).
FIGURE 3-19. A logic objective may give rise to a timing objective
FIGURE 3-20. A logic objective may be determined traditionally or by a timing
objective
TABLE 3-11. Conditions that trigger timing based logic resolution
Existing logic value Objective
{s0,g0} {s0}
{s0,g0} {g0}
{s1,g1} {s1}
{s1,g1} {g1}
{s1,g1}
A
B
C
{s1,g1,cr,gr}
{cr}
{s1,g1}
{cr}
{cf,gf}->cf {cf,gf}->cf
{s1,cr}
{s1}
89
We need not consider refining {cf,gf} to cf and {cr,gr} to cr. Since dynamic hazards at
the output of a primitive Boolean gate cannot exist without static hazards at its inputs [24]
(unless the dynamic hazard is propagated from the input to the output), the objective of
refining {cr,gr} ({cf,gf}) to cr (cf) can either be satisfied by a logic objective chosen tradi-
tionally, or by one of the timing objectives described in Table 3-11. We show an example
of each in Figure 3-20. In the first case, the logic objective of {s1,cr} on the first input will
satisfy the logic objective at the output, and in the second case {s1} on the first input will
satisfy the logic objective at the output.
We next discuss our algorithm for converting a logic objective to a timing objective.
This is a part of the backtracing procedure. We show further modifications to the backtrac-
ing procedure in Figure 3-21. This procedure is triggered only if none of the inputs can be
logically refined and the objective and existing logic value at the output of the gate satisfy
the condition in Table 3-11. A list of logic objectives is determined and then they are
stepped through until a primary input assignment can be made.
Next, we focus on the procedure for determining logic objectives,
determine_logic_timing_objectives(). We describe the portion of this pro-
cedure when the existing logic value is {s1,g1} and the local logic objective is s1. First,
we collect, in a set S1, all logic objectives in the fan-in cone that would increase the mini-
mum arrival time of the existing value {s1,g1} using the algorithm described in the previ-
ous section (Section 3.4.3). Similarly, we collect, in set S2, all logic objectives in the fan-
in cone that would decrease the maximum arrival time by an algorithm similar to the one
described in Section 3.4.3. This is done because {s1,g1} may be converted to {s1} by
increasing the minimum arrival time of the falling transition, or by decreasing the maxi-
90
mum arrival time of the rising transition. The different procedures invoked for collecting
logic objectives for this timing objective are shown in Table 3-12.
FIGURE 3-21. Modified backtracing procedure
xbacktrace(piassign,obj)
{
if (obj.node.type is primary_input)
{
if (obj.node.value is refined from value on primary_input)
{

piassign = obj;
return SUCCESS;
}
else
return FAILURE;
}
else
{
for (i=0; i < obj.node.fin; i++)
{
value = determine_objective(obj,i);
if (xbacktrace(obj_new,piassign) == SUCCESS)
return SUCCESS;
if (value is refined from value on line i)
}
}
return FAILURE;

}
}
obj_new = (i,value);
{
if (logic_timing_condition(obj)
{
list = determine_logic_timing_objectives(obj);
if (xbacktrace(obj_new,piassign) == SUCCESS)
return SUCCESS;
while (list is not empty)
{
obj_new = item from list;
}
}
91
If is non-empty, we select an element in S using the following heuristic.
To increase the minimum (maximum) arrival time, simply choose the logic objective at the
node such that the transition at the output has the highest value of minimum (maximum)
arrival time. To decrease the maximum (minimum) arrival time, choose the logic objective
so that the transition at the output has the smallest value of maximum (minimum) arrival
time.
As shown in Figure 3-21, we recursively backtrace with this new logic objective and
keep a record of this objective. If the recursive call to the backtracing procedure returns
FAILURE, then we ignore this logic objective and choose a new objective from S using
the same heuristic. If S is empty, we return FAILURE. If the recursive call to the backtrac-
ing procedure returns SUCCESS, then we are done with a primary input assignment.
3.5 Experimental results
We implemented the ideas presented in a system called XGEN-C (‘C’ stands for com-
plete). We compare the results from XGEN-C with those from XGEN-E, the crosstalk test
generator with nine valued algebra discussed in the previous chapter. The experiments are
done using the ISCAS’85 benchmark circuits. These circuits are combinational, and we
TABLE 3-12. Timing objectives
Timing objective Procedures invoked
{s1,g1} to s1 increase minimum arrival time,
decrease maximum arrival time
{s1,g1} to g1 decrease minimum arrival time,
increase maximum arrival time
{s0,g0} to s0 increase minimum arrival time,
decrease maximum arrival time
{s0,g0} to g0 decrease minimum arrival time,
increase maximum arrival time
SS
1
S
2
∪ =
92
have modified them by replacing each AND gate by a NAND-inverter combination, and
each OR gate by a NOR-inverter combination. For each circuit, 100 aggressor-victim pairs
are generated randomly where the victims are on the critical path.
The change in Type A fault coverage is shown in Table 3-13. The first column shows
the circuit name. The second column shows the Type A fault coverage with XGEN-E. The
third column shows the Type A fault coverage with XGEN-C. We see that the total Type A
fault coverage increases by 32 faults (4%).
Next, we discuss undetectable faults. These results are shown in Table 3-14. The first
column shows the circuit name, the second column shows the number of undetectable
TABLE 3-13. Type A Fault coverage comparison
Circuit XGEN-E XGEN-C
c432 2 18
c880
33
37
c1355
24
36
c1908
9
8
c2670 0 1
c5315 0 1
c7552 2 1
Total 70 102
TABLE 3-14. Undetectable faults
Circuit name
Number of
undetectable faults in
XGEN-E
Number of
undetectable faults
in XGEN-C
c432 0 6
c880 7 1
c1355 0 7
c1908 1 2
c2670 1 4
c3540 6 11
c5315 0 7
c7552 1 7
Total 16 45
93
faults in XGEN-E, the third column shows the number of undetectable faults in XGEN-C.
We see that the number of undetectable faults are more in XGEN-C by 29 faults (3.5%).
Note that, in XGEN-E, a fault labeled undetectable may not be truly undetectable as it
does not have the ability to satisfy timing relationships by logic assignments. However, a
fault labeled undetectable in XGEN-C is truly undetectable as it is a complete algorithm.
Here, when we call a fault undetectable, we mean undetectable as a Type A fault
effect. Traditionally, when the efficacies of two test generation methods are compared, test
generation efficiency, i.e., the sum of detected and undetectable faults are compared. How-
ever, in our case, the notion of undetectability is restricted and therefore, we have not
made that comparison.
In Figure 3-22, we present a diagram to show how the fault status changes for c1355
when we use XGEN-C instead of XGEN-E. We see that 9 faults that were previously
detected as Type B faults are now detected as Type A faults. Of the previously aborted
faults, 9 are now detected as Type A faults and 7 of the faults are now detected as Type B
FIGURE 3-22. Change in fault status for c1355
24
0
50
36 7
40
18
0
Type A Undetectable Type B Aborted
29
XGEN-E
XGEN-C
26
17
9
7
3 9
8
3
7
2
5
94
faults. The fault coverage numbers are a little different for XGEN-E compared to those
presented in previous chapter because the timing analysis routines are slightly different.
We also present the change in fault coverage due to the procedures that handle the new
timing issues discussed in Section 3.4.3 and Section 3.4.4. These results are presented in
Table 3-15. We see that 5 faults detected as Type A fault effects would not be detected if
these procedures were not incorporated in the algorithm. Thus, incorporating the timing
based search procedures increases the Type A fault coverage, even though by a small
amount.
Next, we compare the average search spaces covered for each algorithm (Table 3-16).
Columns 2 and 3 shows the average search space covered in XGEN-E and XGEN-C. This
is determined by adding the search space for each fault and dividing the sum by the total
number of faults. Column 4 shows the ratio of the search space covered by XGEN-C to
that covered by XGEN-E. We see that, except for c880, the average space searched in
TABLE 3-15. Increase in fault coverage due to timing procedure
Circuit name
Increase in the
number of Type A
fault effects
c432 4
c1355 1
Total 5
TABLE 3-16. Search spaces covered
Circuit XGEN-E XGEN-C Ratio
c432 5.2e18 5.84e20 112.3
c880 1.18e35 6.34e34 0.54
c1355 3.46e22 1.02e24 29.48
c1908 1.44e18 9.34e18 6.49
c2670 4.81e92 1.76e93 3.66
c3540 1.24e29 4.73e29 3.81
c5315 6.04e104 1.40e106 23.18
c7552 5.84e122 5.62e123 9.62
95
XGEN-C is larger for each of the circuits. The average space searched, considering all cir-
cuits, increases by a factor of 22.
Next, we present a comparison of computation time in Table 3-17. The computation
time in XGEN-C is either comparable with that in XGEN-E or larger. The total computa-
tion time for all circuits in larger in XGEN-C by 12% approximately. Note that for a mere
12% increase in computation time, XGEN-C searched 22 times more search space.
We also show the computation times for two sub-procedures, namely, backtracing and
timing simulation (Table 3-18). We see that a very small amount of time is spent on back-
tracing and a large amount of time is spent on timing simulation.
TABLE 3-17. Computation time (in seconds)
Circuit XGEN-E XGEN-C
c432 16720 16939
c880
7808
8819
c1355
12510
13687
c1908
30890
38389
c2670 36370 39731
c3540 65280 68737
c5315 78820 86960
c7552 87931 102338
Total 336329 375600
TABLE 3-18. Computation time of sub-procedures
Circuit Backtracing (s) Timing simulation (s)
Total computation
time (s)
c432 9 15952 16939
c880 10 6496 8819
c1355 39 10243 13687
c1908 66 26798 38389
c2670 735 16840 39731
c3540 1521 31488 68737
c5315 1238 33377 86960
c7552 282 39778 102338
96
We summarize the total number of faults resolved as Type A, Type B and undetectable
faults using both XGEN-E and XGEN-C. The results are shown in Table 3-19. Thus, a
total of 17% of all faults are detected as Type A fault effects, 5% of all faults are identified
as undetectable faults (as Type A fault effects) and 21% of all faults are detected as Type B
fault effects. The total count for Type B faults excludes faults that are detected as Type B
fault effects in XGEN-E but as Type A effects in XGEN-C, and vice versa. If a fault is
detected as a Type A fault effect in one system and as a Type B fault effect in another, then
we count it as a Type A effect.
Next, we compared XGEN-S with XGEN-E and XGEN-C on equal runtime basis. We
increased the number of backtracks for XGEN-S until the runtime equaled the total runt-
ime of XGEN-E and XGEN-C. We report the fault coverages in Table 3-20. It is seen that
XGEN-S detects 60 faults as Type A fault effects when the runtimes are equal, however,
TABLE 3-19. Summary of fault coverage from XGEN-E and XGEN-C
Circuit Type A Type B Undetectable
c432 20 7 6
c880 54 10 1
c1355 42 24 7
c1908 13 29 2
c2670 1 14 4
c3540 0 13 11
c5315 1 38 7
c7552 3 29 7
Total 134 164 45
TABLE 3-20. Comparison on equal runtime basis
Circuit
Type A Type B
XGEN-S XGEN-E+C XGEN-S XGEN-E+C
c432 2(2) 20 9(5) 15
c880 29(26) 54 13(17) 13
c1355 22(12) 42 18(19) 26
c1908 7(5) 13 21(18) 26
Total 60(45) 129 61(59) 80
97
XGEN-E and XGEN-C together detect 129 faults as Type A fault effects. Similarly,
XGEN-S detects 61 faults as Type B fault effects when the runtimes are equal, and
XGEN-E and XGEN-C together detect 80 faults as Type B fault effects. For XGEN-S, we
show, in brackets, the numbers when the backtrack limit was set to 10,000.
Since we are not satisfied with the test efficiency, we did an experiment in which we
increased the backtrack limit to 100,000. Further, after every 10,000 backtracks, we ran-
domly assigned logic values to 10% of the primary inputs (the remaining inputs have the
completely unspecified value). By doing this, we explored different areas of the solution
space. We see that a larger number of faults are detected as Type A faults (Table 3-21). A
total of 102 faults are detected as Type A faults with 10 K backtrack limit and a total of
177 faults are detected as Type A faults with 100 K backtrack limit using XGEN-C. This
experiment shows that the fault coverage can be further increased by increasing the back-
track limit. We have also shown the Type A fault coverage from XGEN-E when the back-
track limits are 10K and 100K. The benefits of XGEN-C over XGEN-E are obvious.
TABLE 3-21. Type A fault coverage with random exploration of solution space
Circuit
10 K backtrack limit 100 K backtrack limit
XGEN-E XGEN-C XGEN-E XGEN-C
c432 2 18 6 24
c880
33
37 47 41
c1355
24
36 40 56
c1908
9
8 12 32
c2670 0 1 0 5
c3540 0 0 0 3
c5315 0 1 0 11
c7552 2 1 6 5
Total 70 102 111 177
98
Next, we show the increase in Type B fault coverage (Table 3-22). We see that the
Type B fault coverage increases by a smaller number for XGEN-C but by a larger number
for XGEN-E. We also see that the Type B fault coverage is low in XGEN-C compared to
XGEN-E. One reason is that some of the faults detected as Type B faults in XGEN-E are
detected as Type A faults in XGEN-C.
Another reason is the following. In 9-valued algebra, there is only one unspecified
value (vxx). In the 57-valued algebra, we have an unspecified value (vxx) but many of the
composite values can also be thought of as unspecified values. For example, {s0,cr} can be
thought of as an incompletely specified value since either of s0 and cr may be assigned. In
the 9-valued algebra, the nearest equivalent for {s0,cr} is vxx, however, {s0,cr} is more
refined. We also know that refining values leads to tighter timing ranges of arrival times
[7]. Thus, arrival time ranges can be tighter when 57-valued algebra is used and leads to
fewer “straddling” scenarios at circuit outputs. This can lead to an increase in Type A fault
coverage and to an increase in undetectable faults, and also to situations where the maxi-
mum arrival time is always less than the clock sampling time. This results in fewer Type B
TABLE 3-22. Type B fault coverage with random exploration of solution space
Circuit
10 K backtrack limit 100 K backtrack limit
XGEN-E XGEN-C XGEN-E XGEN-C
c432 6 2 31 12
c880
18
1 33 11
c1355
26
17 41 16
c1908
30
6 38 7
c2670
10
5 29 10
c3540
10
3 36 14
c5315 38 0 61 1
c7552 28 1 43 4
Total 166 35 312 75
99
fault effects using 57-valued algebra. when we are exploring the search space randomly,
we do not cover the entire search space.
Note that the number of undetectable faults cannot be compared in this last experiment
since when we are exploring the search space randomly, we do not cover the entire search
space.
We finally present the summary of Type A and Type B fault coverages from XGEN-E
and XGEN-C combined obtained with random exploration of search space and compare
that with the Type A and Type B fault coverages from XGEN-S obtained with random
exploration. The results are shown in Table 3-23. We see that the number of faults detected
as Type A fault effects have nearly doubled and the number of faults detected as Type B
fault effects have increased by a small amount.
Finally, we summarize the test efficiency from XGEN-E and XGEN-C using random
exploration. A total of 24.75% faults are detected as Type A fault effects and a total of
32% faults are detected as Type B fault effects.
TABLE 3-23. Summary of fault coverages from random exploration
Circuit
XGEN-S XGEN-E+C
Type A Type B Type A Type B
c432 7 24 25 23
c880 43 28 54 27
c1355 37 30 60 23
c1908 9 27 33 22
c2670 1 24 6 29
c3540 0 17 0 37
c5315 0 54 11 55
c7552 3 37 9 40
Total 100 241 198 256
100
3.6 Conclusion
In this chapter, we have developed a 57-valued algebra for test generation using
PODEM for crosstalk delay faults. This algebra is transitively closed and considers tim-
ing. We have also modified the test generation algorithm in two ways so that this algebra
can be used. We have modified the search procedure and adopted a recursive depth first
search for backtracing. Further, we have proposed a method for converting Type B fault
effects to Type A fault effects and have introduced an algorithm for timing based resolu-
tion of logic values. Our algorithm is a complete algorithm for Type A fault effects. We
have shown that the methodologies proposed in this chapter increases the fault coverage.
The increase in fault coverage is shown as being even higher if we increase the backtrack
limit and search the space randomly.
101
Chapter 4 Inductance induced noise on single interconnects
In this chapter, we study characteristics of oscillatory noise with the objective of gen-
erating validation and test vectors to detect functional errors caused by overshoots and
undershoots. Oscillatory noise on VLSI interconnects has been discussed in [53], [55].
However, test and validation issues for oscillatory noise has not been addressed.
In the near future, signal overshoot and undershoot are expected to increase in magni-
tude and occur more frequently. This noise may propagate to a primary output or a latch
input and create logic-value (permanent) errors. By considering technology trends we
have shown that such noise in local interconnects embedded in combinational logic block
may exceed the threshold voltage in 0.13 µ m technology (this work was done when 0.25
µ m technology was prevalent). This motivates the validation problem. The impact of pro-
cess variation on noise has been discussed in [51]. The severity of the impact of process
variation on noise depends on the aggressiveness of a design. For example, a technique to
design interconnects that reduces the output delay by a large amount by causing a small
overshoot has been presented in [5]. An aggressive design that employs such a trade-off
may exhibit a large overshoot or undershoot in a fabricated circuit due to process varia-
tion. This motivates the test generation problem.
4.1 Circuit Model
Inductance is associated with a current loop. In a VLSI chip, when a single signal line
switches, numerous current loops are formed through the interconnect substrate, power
and ground lines [62].
102
A conventional transmission line assumes only one current return path. We can use
conventional transmission line analysis if we assume that there is no transient potential
drop on the return paths. We can then combine all return paths into a single terminal. The
interconnect circuit and model are shown in Figure 4-1. The driver resistance is modeled
as a constant linear resistance, denoted by R
source
. The receiver can be one of the follow-
ing: (i) a static gate, (ii) a transmission gate, (iii) a pass transistor, or (iv) a domino gate.
The load can be modeled as a capacitance (in the case of a static inverter, domino gate, and
non-conducting pass transistor or transmission gate) or a resistance (conducting pass tran-
sistor or transmission gate) and is assumed constant and is denoted by C
load
or R
load
. One
section of the transmission line is shown in the figure, where r, l and c are the resistance,
inductance and capacitance per unit length. Since the resistance of the dielectric is high,
the shunt conductance in a conventional transmission line model is ignored. The symbols
IN, NE, FE and OUT refer to the input to the driving buffer, the near end of the intercon-
nect, the far end of the interconnect and the output of the receiver, respectively.
4.2 Motivation
4.2.1 Oscillatory noise
An oscillatory response is created by the mismatch of impedances between the inter-
connect and the driver, and between the interconnect and the receiver. Further, the attenua-
tion of the interconnect must be such that the oscillation is not damped. For a rising
response, an overshoot occurs if its magnitude at some instance of time is larger than the
final stable value. An undershoot occurs if, once the response initially reaches a voltage
103
equal to its steady state value, it drops below this value. The definitions for a falling
response are similar.
The settling time is the time after which the oscillatory circuit response does not devi-
ate from its final value by more than a certain fraction of the final value [41]. The 50%-
input to 50%-output change is a popular delay metric for RC interconnects in VLSI cir-
cuits. By this criterion, the output of a RLC interconnect may have less delay than an RC
interconnect, but the receiver gates may switch several times due to signal oscillation. In
this scenario, the settling time is a more meaningful delay criterion than 50%-input to
50%-output delay.
We conducted an experiment to see how the magnitude of overshoot, undershoot and
settling time change with changes in rise (fall) times of the input stimulus. The intercon-
nect model in Figure 4-1(b) with a capacitive load is used for this study. To justify the
FIGURE 4-1. Interconnect circuit and model
Transmission line

r l
c
Interconnect
IN NE FE OUT

R
source
IN NE FE
V
dd
GND
V
dd
GND

OUT
R
load

or
C
load
OUT
clock
clock
a
a
GND
(a)
(b)
104
parameters used in our experiments we looked at technology trends predicted by the SIA
Roadmap and MOSIS [52], [56].
Table 4-1 shows projections for the power supply voltage, on chip clock frequency,
microprocessor chip size and interconnect thickness from the SIA Roadmap [52]. Table 4-
2 shows a few parameters that have been collected from MOSIS process files along with
the projections for the 0.13 µ m technology (shaded row) using the collected data [56].
Columns 2 and 3 show the sum of area and fringe capacitances of the N-active and the P-
active layers. Column 4 shows the substrate capacitance of the third metal layer. Column 5
shows the product of the mobility and the gate oxide capacitance. The channel resistance
of a transistor is shown in Column 6 and is calculated as , where
k is a constant and considered equal to 1, V
gs
is the gate to source voltage, V
t
is the thresh-
old voltage, and L and W are the length and width of the transistor, respectively. The W/L
ratio is chosen to be 70 (a fast driver), and its resistance estimated as 30 Ω . Based on the
data collected for 1.2 µ m, 0.8 µ m, 0.5 µ m, 0.35 µ m technologies, each of the N-active and
TABLE 4-1. Projections from SIA Roadmap.
Year 1997 1999 2001 2003
Feature size (nm) 250 180 150 130
Logic Vdd (V) 1.8-2.5 1.5-1.8 1.2-1.5 1.2-1.5
On-chip local clock (GHz)
.75 1.25 1.5 2.1
Microprocessor chip size
(mm
2
)
300 340 385 430
Line Thickness (µ m)
.45 .324 .3 .273
TABLE 4-2. Some parameters from MOSIS process files.
Feature
Size
(µ m)
N-active
capacitance
(aF/µ m
2
)
P-active
capacitance
(aF/µ m
2
)
Metal 3
capacitance
(aF/µ m
2
)
µ 0
. C
ox
(µ A/V
2
)
Channel
Resistance
(Ω )
Logic
Vdd
(V)
Threshold
V oltage
(V)
1.2 357 463 -- 69 52 5 1
.8 755 1032 -- 106 34 5 1
.5 798 1013 12 112 32 5 1
.35 826 1072 7 176 31 3.3 .7
.13 1100 1100 5 496 30 1.2 .24
R
k
µ 0
C
ox
V
gs
V
t
– ()
-------------------------------------------- -
L
W
---- -


=
105
the P-active capacitances in 0.13 µ m technology are estimated to be 1100 aF/µ m
2
. The
load capacitance of a receiver with an n-transistor whose W/L ratio is 100 and a p-transis-
tor whose W/L is 200 is calculated to be about 5 fF. The distribution of interconnect
lengths in a chip is bimodal, and assuming that the length of each edge of a chip is 2 cm
(Table 4-1), the distribution has two peaks, one at around 2500-3000 µ m (intramodule)
and another at around 15000 µ m (intermodule) [36]. We assume an interconnect length of
2500 µ m. We further assume that its width is 3µ m, and its thickness is 0.27 µ m (Table 4-
1). Assume that the interconnect material is copper with a conductivity of 58.8/Ω -µ m and
resistance per unit length of 0.02 Ω /µ m. The substrate capacitance of the third metal layer
is estimated to be 5 aF/µ m
2
(Table 4-2). The interconnect is assumed to be on the third
metal layer and therefore its capacitance per unit length is 0.015 fF/µ m. The value of
inductance per unit length depends on the design of the power-ground mesh (since current
returns through the mesh) and therefore a single value cannot be estimated for all designs.
We will assume a value of 1 pH/µ m. Inductance values with similar and higher magni-
tudes have been reported in the literature [21]. It should be noted that in reality resistance
(inductance) values are slightly larger (smaller), due to frequency dependent skin and
proximity effects, which we have ignored [37]. The magnitude of the power supply volt-
age is assumed to be 1.2 V (Table 4-1). Assuming a clock frequency of 2 GHz (Table 4-1),
the rise time can be approximated as 50 ps (= (1/10)*(1/2 GHz)). For this experiment, the
input was modeled by an exponential function and the rise time was varied from 25 ps to
100 ps in steps of 25 ps.
Several simulations were performed using Spice3. Figure 4-2 shows the response at
the far end and Table 4-3 summarizes the results. The settling time measures the time for
106
the response to reach within 10% of its final value (i.e., between 0.9 Vdd and 1.1 Vdd)
starting from its initial value. We see that with an increase in input rise time, initially the
settling time decreases and then increases. This implies that the rise (fall) time of the input
stimulus should ideally be that which corresponds to an optimum settling time (shaded
rows). Assuming that the threshold voltage is 0.24 V (=0.2Vdd), the magnitude of the
overshoot in the first case is larger than the threshold voltage. The undershoots in the first
two cases are greater than the threshold voltage. The overshoots and undershoots are
absent if the input signal rise time is 75 ps or greater.
We thus predict a higher magnitude of oscillatory noise in future technologies. This
follows from the analysis presented in this section that implies that this noise will be larger
than the threshold voltage presented in 0.13 µ m technology.
4.2.2 Noise Effects
Assume that a static inverter is driving a transmission line that has one of the following
three receivers, a transmission gate, a domino latch, or a static inverter. We will see how
the outputs differ for each of these cases.
FIGURE 4-2. Circuit response at far end with rise time variation at input IN
time
0.0 50.0 100.0 150.0
pS
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
75 ps input rise time
100 ps input rise time
50 ps input rise time
25 ps input rise time
V oltage (V)
Time (ps)
107
An undershoot in case of a rising response and an overshoot in case of a falling
response should be avoided at the far end of the interconnect (FE in Figure 4-1), especially
if their magnitudes are greater than V
tp
and V
tn
, respectively, where V
tp
and V
tn
are the
threshold voltages of the p and n transistors of the gate at the far end. This is because such
a situation may propagate the noise.
An overshoot in the case of a rising response and an undershoot in the case of a falling
response do not propagate via static CMOS logic. An overshoot (undershoot) at the input
of the static inverter makes the falling (rising) transition at its output faster by a small
amount, but not sufficiently enough to speed up the output. Thus, an overshoot in the case
of a rising response and an undershoot in the case of a falling response do not create any
problem in static CMOS logic.
There are, however, families of logic that are adversely affected by overshoots for a
rising response and undershoots for a falling response. For example, in the case where FE
drives the source/drain of a transmission gate, assume that the gate input of a n pass tran-
sistor is at 0 V. An undershoot of magnitude greater than the threshold voltage of the n-
transistor at FE will discharge the charge stored at its output [76]. This is because the gate
to source voltage exceeds the threshold voltage. Similarly, an overshoot at the source of a
p-transistor can cause it to discharge.
TABLE 4-3. Characteristics at the FE of the line.
Input rise
time (ps)
Maximum
overshoot (V)
Maximum
undershoot
(V)
Settling time
(ps)
25 0.42 0.32 100
50 0.06 0.28 63
75 -- -- 70
100 -- -- 106
108
The following simulations were done using HSPICE and 0.25 µ m process files from
MOSIS. In this technology, the power supply voltage is 2.5 V and the threshold voltage is
0.6 V . We have increased the magnitude of the inductance to increase the magnitude of the
oscillation. In later technologies, the magnitude of the threshold voltage will be lower, and
therefore, a more subdued oscillation may have a similar impact. The transmission line
resistance, capacitance and length are 0.02 Ω /µ m, 15 aF/µ m and 5000 µ m, respectively. A
fast driver is used in each case and the transmission line inductance is discussed for the
specific simulation.
Figure 4-3 shows the results at the output of a domino latch that is sensitive to an over-
shoot in the case of a falling response. The input to the evaluation transistor has a falling
transition just before the clock goes high, such that the oscillation persists after the clock
changes. The magnitude of the overshoot is high enough to degrade the output voltage
level. The magnitude of the interconnect inductance is 5 pH/um.
FIGURE 4-3. Impact of oscillation on domino latch
Voltages (lin)
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
3
Time (lin) (TIME)
input to
driver
clock
oscillation
at far end
no oscillation
at far end
receiver output with
oscillation at far end
receiver output with no
oscillation at far end
V oltage (V)
Time
21 ns 21.6 ns
109
Figure 4-4 shows the results for a transmission gate that discharges the stored charge,
even though the gate inputs to the n and p transistors of the transmission gate are low and
high respectively. This occurs because the magnitude of the undershoot is greater than the
threshold voltage of the n-transistor. Again, the magnitude of the interconnect inductance
is 5 pH/µ m.
Figure 4-5 shows the noise at the far end of two transmission lines that have identical
receivers. The first transmission line has an inductance of 10 pH/µ m and the second 20
pH/µ m. The noise at the output of the receiver has a higher magnitude in the second case.
FIGURE 4-4. Impact of oscillation on transmission gate
FIGURE 4-5. Impact of oscillation on static inverter -- 0.25 µ m process
Voltages (lin)
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
Time (lin) (TIME)
8n 9n 10n
n transistor
p transistor
transmission
gate output with
no oscillation
at far end
clock
clock
no oscillation
at far end
oscillation
at far end
transmission
gate output
at far end
input to
driver
with oscillation
V oltage (V)
Time
Wave Type Design
Voltages (lin)
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
Time (lin) (TIME)
1.8n 2n 2.2n 2.4n 2.6n 2.8n 3n 3.2n 3.4n
input
driver
case 1
case 1
case 2
case 2
signal at
far end
(L=10pH/sum)
signal at far end (L=20pH/um)
signal at receiver
output
to
signal at receiver
output
Time
V oltage (V)
110
For static gates, we also simulated oscillatory noise for 0.18 µ m process from UMC
[57]. A line length of 2000 µ m was used, and the inductance value used is only twice the
real value. The interconnect parameters are extracted with the assumption that the inter-
connect is on metal layer 4 and above substrate. The interconnect is 3 µ m wide. The self
capacitance for this second circuit is 36 aF/µ m, the self inductance is 1.2 pH/µ m (the
inductance value extracted for this particular configuration is 0.6 pH/µ m), and the inter-
connect resistance is 0.004 Ω /µ m. The simulation response is shown in Figure 4-6. Even
though the process parameters for the 0.25 and those for 0.18 µ m process come from dif-
ferent sources, we see that the inductance magnitude has to increase by a smaller factor (a
factor of 2, compared to a factor of 20 for the previous process) for this later technology to
achieve a higher magnitude of noise at the receiver output. This, again, makes us believe
that in near future oscillatory undershoot may cause problem for realistic values of induc-
tance.
FIGURE 4-6. Impact of oscillation on static inverter -- 0.18 µ m process
Voltages (lin)
0
200m
400m
600m
800m
1
1.2
1.4
1.6
Time (lin) (TIME)
5n 5.02n 5.04n 5.06n 5.08n 5.1n 5.12n 5.14n 5.16n 5.18n
5.2n
first
undershoot
first
overshoot
V oltage
V oltage
at IN
at OUT
111
4.3 Process Variation
The impact of process variations on inductance can be assumed to be negligible
because the area of the loops are large compared to changes in dimensions due to process
variations. However, oscillatory response can still vary significantly due to variations in
other circuit parameters. We illustrate this with the example described in Section 4.2.1.
Table 4-4 shows the nominal values and the values under process variations. (Process vari-
ation data for newer technologies are not available to us.) The percentage variations are
assumed to be the same as that in the 0.8 µ m process reported in [51]. The percentage vari-
ations cover 98% of all measured data points implying that process variation effects can be
more severe than that reported here.
We see that for a 2500 µ m long line, the magnitudes of undershoot and settling time
change significantly with variation in parameters (shaded rows). The magnitudes of the
maximum overshoot do not change significantly for this specific example and are not
shown. This implies that a fabricated design may have significant overshoot and under-
shoot even if it is designed to suppress such noise. Assuming that the threshold voltage is
0.24 V, the undershoot for the combination of minimum values of parameters is much
larger than the threshold voltage and can cause a logic-value error. Hence, it is necessary
to treat this situation as a test problem.
TABLE 4-4. Impact of process variation -- Example 1
Parameters %Variation Minimum Nominal Maximum
Source Resistance
(Ω )
+15 25.5 30 34.5
Load Capacitance
(fF)
+5 4.75 5 5.25
Trans.
Line
r (Ω /µ m) +15 0.017 0.02 0.023
c (fF/µ m) +30 0.0105 0.015 0.0195
Maximum undershoot (V)
(% Variation about nominal)
0.34
(21)
0.28 0.22
(21)
Settling time (ps)
(% Variation about nominal)
69
(10)
63 87
(38)
112
We also simulated process variation effects for a 2000 µ m line in the 0.18 µ m process
[57]. The interconnect parameters were extracted with the assumption that the intercon-
nect is on metal layer 6, and running parallel to metal layer 1 interconnect underneath it.
Again, the interconnect is 3 µ m wide. The self capacitance for this second circuit is 150
aF/µ m, and the self inductance is 1.4 pH/µ m (the inductance value extracted for this par-
ticular configuration is 0.7 pH/µ m). Three different values of interconnect resistances
were used, and the variation values were taken from the process files. The minimum value
is 0.002 Ω /µ m, the average value is 0.004 Ω /µ m, and the maximum value is 0.006 Ω /µ m.
For each of these values, five different process corners for transistors were used: (i) typical
p-transistor and typical n-transistor corner (or typical-typical corner), (ii) fast-fast corner,
(iii) slow-slow corner, (iv) fast-slow corner, and (v) slow-fast corner. The value for the typ-
ical parameters and the minimum and the maximum values are shown in Figure 4-6. The
magnitude of the undershoot for typical values of parameters is 0.74 V. The minimum
magnitude (0.32 V) occurs when the interconnect resistance is the highest, and the transis-
tor process corner is slow-slow. The maximum magnitude (1.21 V) occurs when the inter-
connect resistance is the lowest, and the transistor process corner is fast-fast. The
percentage variation in the magnitude of the undershoot is about 60% around the nominal
value.
4.4 Interconnect length
The impact of interconnect length on oscillatory noise is now addressed. Since the
interconnects that occur in a single logic block are not very long, one question is whether
oscillatory noise in such blocks need be considered in validation and/or test.
113
In this experiments, the line length is increased from 1,000 µ m to 10,000 µ m, and two
different sets of interconnect parameters for a 0.25 µ m process are used [57]. The first set
(circuit 1) was extracted with the assumption that the interconnect is on metal layer 4 and
above substrate. The interconnect is 3 µ m wide. The self capacitance for this second cir-
cuit is 36 aF/µ m, the self inductance is 0.6 pH/µ m, and the interconnect resistance is 0.004
Ω /µ m. The second set (circuit 2) of interconnect parameters was extracted with the
assumption that the interconnect is on metal layer 6, and running parallel to metal layer 1
underneath it. Again, the interconnect is 3 µ m wide. The self capacitance for this second
circuit is 150 aF/µ m, the self inductance is 0.7 pH/µ m, and the interconnect resistance is
0.004 Ω /µ m. The inductance is extracted by the tool FASTHENRY assuming a power and
ground mesh as described in [35]. The results are plotted in Figure 4-8. We assume that
the longest interconnects in combinational logic blocks are about 2000 µ m long, and we
pay special attention to magnitude of noise for interconnects of this length.
FIGURE 4-7. Impact of process variation -- Example 2
Voltages (lin)
-400m
-200m
0
200m
400m
600m
800m
1
1.2
1.4
1.6
Time (lin) (TIME)
5n 5.02n 5.04n 5.06n 5.08n 5.1n 5.12n 5.14n 5.16n
5.18n
** studying the impact of risetime on signal reflection **
typical value
of parameters
minimum
maximum
114
For both circuits the magnitude of the first undershoot first increases and then
decreases. All inductance values are twice the realistic value. For the first circuit, the max-
imum occurs for 5000 µ m and is equal to 1.36 V. For the first circuit, for an interconnect
length of 2000 µ m, the magnitude of the peak voltage of the first undershoot is more than
twice the threshold voltage. For the second circuit, the maximum occurs for 2000 µ m, and
is more than the threshold voltage.
4.5 Impact of edge-rate
The edge-rate of the input signal is varied from 0 ps to 100 ps. The circuit parameters
are the same as for the first circuit described in Section 4.4, and the line length is 5000 µ m.
The results are shown in Table 4-5. The magnitude of the peak undershoot is maximum for
an edge-rate of 25 ps, and is higher than that when the edge-rate is 0 ps.
FIGURE 4-8. Variation of oscillatory noise with interconnect length
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
0
0.2
0.4
0.6
0.8
1
1.2
1.4
undershoot,
circuit 1
undershoot,
circuit 2
noise
magnitude
length
115
We see a very slight non-monotonic behavior in the magnitude of the undershoot. For
test generation purposes, we will try to achieve an input stimulus with an appropriate tran-
sition time at the input of the driver driving an interconnect that displays oscillatory
behavior.
4.6 Analytical Model of noise
In this section we derive an (approximate) expression that describes the response at
node FE of the circuit in Figure 4-1. We also determine the magnitudes and times of
occurrences of the undershoots and overshoots and the settling time. These expressions
can be used in a test generation process. They can also be used to guide the design process.
For detailed analysis of transmission line equations, please refer to [15].
Let the length of a transmission line be h, and its resistance, capacitance and induc-
tance per unit length be r, l and c. Let R = rh, C = ch and L = lh. The propagation constant
of a transmission line is and its characteristic impedance is
. Let its source resistance be R
s
and load impedance be Z
l
. The trans-
fer function of this network is given by [33]
. (4-1)
TABLE 4-5. Impact of edge-rate on undershoot
Edge-rate (ps)
Magnitude of peak
undershoot (V)
0 1.35
25 1.38
50 1.32
100 1.18
γ RsL + ()sC =
Z
0
RsL + () sC () ⁄ =
Hs () γh () cosh
R
s
Z
o
----- - γh () sinh +
1
Z
l
---- - Z
0
γh () sinh R
s
γh () cosh + [] +
1 –
=
116
Taking the Maclaurin series expansion of the denominator about s=0, we determine
the first two moments of the expression M
1
and M
2
, where
M
1
= R
s
C + R
s
Z
l
+ RC/2 + RZ
l
, (4-2)
and
M
2
= R
s
RC
2
/6 + R
s
RCZ
l
/2 + R
2
C
2
/24 + R
2
CZ
l
/6 + LC/2 + LZ
l
. (4-3)
We will approximate the transfer function by these first two moments since these are
the dominant ones. Thus, the approximate transfer function can be written as
. (4-4)
Assuming that the input is of the form , the output can be written as
. (4-5)
We can rewrite as
, (4-6)
where and . Here, ζ and w are the approximate damping
factor and the natural frequency of the system [41]. Since we are addressing oscillatory
noise, we will assume an underdamped system, hence ζ < 1 (ζ = 1 and ζ > 1 correspond to
critically damped and overdamped systems, respectively). By means of the inverse
Laplace transform, the output is
(4-7)
where , , and .
H
′
s () 11 M
1
sM
2
s
2
++


⁄ =
1 e
at –
–
Cs () H
′
s () 1 s ⁄ 1 sa + () ⁄ –() =
H′ s ()
H
′
s () w
2
s
2
2ζws w
2
++ () ⁄ =
w 1 M
2
() ⁄ = ζ M
1
M
2
() ⁄ =
Ct () 1 = Ae
a – t
Aae
σ – t
w
d
t () sin
w
d
--------------------- - –1 A – ()
e
σ – t
1 ζ
2
–
------------------ - w
d
t () sin ζ w
d
t () cos 1 ζ
2
– +


– – –
σζw = w
d
w 1 ζ
2
– = Aw
2
w
2
2ζwa a
2
+ –() ⁄ =
117
To determine the time of occurrence of the overshoots and undershoots, we determine
the value of t for which is 0. Because the input has almost reached its final value
when the peak of the overshoot or undershoot occurs, we will assume that Ae
-at
is equal to
0 when this peak occurs. This assumption helps to determine a closed form solution. The
overshoots and undershoots occur at , where n=1,2,3,...,
, and q = Aa. By substitut-
ing these values of t into C(t), we can determine the magnitudes of the overshoots and
undershoots. The settling time can be found by determining when the exponential decay
term in C(t) is within a bounded value, and can be expressed as
, (4-8)
where b is a bound, , and . The
magnitude of the settling time may be in error by at most half the period of oscillation.
In Table 4-6 we compare the values predicted by our model with those determined by
Spice3 simulations, for the case where the bound b=10. The circuit parameters and the rise
times are shown in the first and second columns of Table 4-6. The maximum magnitude of
the error is about 25%. If one is interested in a more accurate model, one may consider
additional moments of the transfer function. In spite of the error, this is a better approxi-
mation than the values determined using a lumped parameter approximation.
This approximation is also more accurate than a step input approximation. For exam-
ple, for the set of parameters shown in Table 4-6 and a step input, and considering the first
t d
d
Ct ()
tnπθ + () w
d
⁄ =
θ ArcCos p p
2
q
2
+


⁄


= p 1 A – ()σ
2
w
d
⁄ w
d
+


Aaσ () w
d
⁄ + =
t 1 – ()σ ⁄ () b 100 ⁄() 1 ζ
2
–


K
1
2
K
2
2
+


⁄ ⋅ log =
K
1
ζ Aa 1 ζ
2
–


w
d
⁄ Aζ + – – = K
2
A 1 – () 1 ζ
2
– =
118
two moments of the transfer function, the approximate magnitudes of the overshoot,
undershoot and settling time are 0.55 V , 0.31 V and 979 ps, respectively. If the input has a
rise time of 250 ps, the errors in approximating those quantities are 67%, 48% and 21%. In
comparison, the errors predicted by our model are 24%, 24% and 2%, respectively.
To see how using the step input approximation leads to a conservative design, let us
assume that in the first example, an overshoot greater than 0.1 V cannot be tolerated, and
that it is decided to change the source resistance alone to satisfy this constraint. The step
input approximation suggests using a source resistance of magnitude 72 Ω . Based on the
exponential model for the input, a 43 Ω source resistance is sufficient. Via Spice3 simula-
tions for a 72 Ω and a 43 Ω source resistance, the settling times for the response to reach
0.9 V are 309 ps and 251 ps, respectively. Therefore, modifying the design on the basis of
a step input approximation increases the delay by 58 ps (23%).
4.7 Test and Validation issues
The process of validation deals in part with generating and simulating test vectors
whose application excites the worst case noise. If this noise creates an error, the circuit
TABLE 4-6. Comparison of SPICE simulation and model.
Circuit
Parameters
Rise
time
(ps)
First Overshoot First Undershoot
Settling time
(ps)
Magnitude (V)
Time of
occurrence (ps)
Magnitude (V)
Time of
occurrence (ps)
Spice
model
(%
error)
Spice
model
(%
error)
Spice
model
(%
error)
Spice
model
(%
error)
Spice
model
(%
error)
R=.003Ω /µ m
L=1 pH/µ m
C=.1 fF/µ m
Length=1cm
Rs=10 Ω Cload=.1 pF
Vdd=1 V
25 0.6 0.55
(8.3)
275 261
(5)
0.36 0.3
(17)
486 511
(5)
966 985
(2)
50 0.58 0.53
(8.6)
250 272
(4.8)
0.35 0.29
(17)
421 522
(24)
954 984
(3)
250 0.33 0.25
(24)
318 335
(5.3)
0.21 0.16
(24)
543 585
(8)
812 793
(2)
119
should be redesigned. Alternatively, tests can be generated to test fabricated chips to iden-
tify noise induced errors missed during validation and the effects of process variation. In
this section we address the problem of generating tests to be used for both design valida-
tion and testing. The problems targeted are the effects of oscillation i.e., overshoot and
undershoot that may cause an erroneous value to be stored in latches/flip-flops. These
noise effects may not be detected by conventional two-pattern tests. We will generate tests
using an ATPG system that is an extension of an existing mixed signal test generator for
crosstalk [13].
4.7.1 Test Generation Example
In this section we illustrate the requirements of the ATPG algorithm with the aid of an
example. We determine a test for the undershoot generated during the rising transition on
line 16 in Figure 4-9. Assume that transitions at the primary inputs occur simultaneously.
Also assume that each gate has a delay of 100 ps and the clock sampling time at the output
is aggressively set at 325 ps.
The undershoot on line 16 must occur at 225 ps for its effect to reach the output at the
sampling time. The rising transition on line 16 can be achieved in several ways. Among
those assignments at the inputs that produce a rising transition on line 16, a falling transi-
tion on line 2 is avoided, because it will cause the signal to arrive on line 16 at 100 ps and
FIGURE 4-9. Example to illustrate test vector generation algorithm
1
3
6
2
7
8
9
11
10
14
15
16
19
20
21
22
23
120
therefore the undershoot on line 16 will occur a little after 100 ps. If we use this assign-
ment, the undershoot will propagate to an output a little after 200 ps and the signal will
stabilize before the clock sampling time. As a result, the noise effect will not be detected.
Thus, line 2 is assigned the value of static 1. This demonstrates that in our ATPG algo-
rithm, we need a method to determine when an undershoot or an overshoot must occur so
that it propagates to an output at the clock sampling time. Thus, the test generation method
has to be timing oriented. The rising transition on line 16 can be achieved by means of a
falling transition on line 11. One way of achieving this is by having rising transitions on
both lines 3 and 6. Thus, by means of backtracing from line 16, we have determined val-
ues on lines 3, 6 and 2, that results in excitation of the undershoot. The magnitude of the
undershoot can be calculated by the procedure described in Section 4.6.
Next, we want to determine conditions for propagation of the undershoot to an output.
By using the equivalent inverter model which replaces a logic gate by an inverter of equiv-
alent p and n transistors [11], we can determine whether the undershoot propagates to lines
22 and 23, and if so, their magnitudes after propagation. The equivalent inverter model
was developed for bitonic pulses and smooth transitions, it has to be updated for non-
monotonic, oscillatory noise. Suppose that the gates on line 22 and 23 amplify the noise
and can potentially cause an erroneous value to be latched, and that it is decided to propa-
gate the noise to line 23. A static 1 value or a rising transition on line 19 is required for this
purpose. A rising transition on line 19 can be achieved by a rising transition on one input
of the AND gate and a static 1 value on the other, or by rising transitions on both inputs. A
static 1 value on line 19 can be achieved by having static 1 values on both of its inputs.
Neither the static 1 value nor the rising transition on line 19 is achievable as we had
121
assigned a falling transition on line 11. To resolve this conflict, we are required to back-
track from our last assignment. We now try to propagate the undershoot to line 22. This
requires a static 1 value or a rising transition on line 10. A static 1 value on line 10 can be
achieved by providing a static 0 value on line 1. Thus, the test that we determined is as fol-
lows: static 0 value on line 1, static 1 value on line 2, and rising transitions on lines 3 and
6; there is no requirement on line 7.
Similarly, to test for the overshoot generated by a falling transition on line 16, we need
rising transitions on both lines 11 and 2. The rising transition on line 11 can be achieved in
one of the following ways: (i) a falling transition on line 3 and static 1 on line 6, (ii) a fall-
ing transition on line 6 and static 1 on line 3, and (iii) falling transitions on both lines 3 and
6. In Section 4.5, we saw that the faster the transition, the larger the magnitude of the
noise. Therefore, we will opt for the third alternative. This will result in a faster transition
on line 11 and consequently, more noise on line 16. The test can be propagated by a static
0 value on line 1, as before.
The two pattern tests generated by the above procedure can be applied using the slow-
fast application scheme commonly used to apply robust path delay tests.
4.7.2 Need for a new test methodology
In this section we illustrate, by means of the circuit in Figure 4-9, the reason why
oscillatory noise effects cannot be completely detected by conventional tests based on
classical faults, such as path and gate delay, bridging faults and crosstalk faults.
Assume that the undershoot during the rising transition on line 10 is to be tested. Let
us further assume that the undershoot has a magnitude that results in an error only when
122
there are falling transitions on both lines 1 and 3, because two falling transitions at the
input of the NAND gate result in a faster rise time at the near end of line 10, compared to
only one falling transition. Consider the tests for robust path delay faults that result in a
rising transition on line 10 [44]. One test has a falling transition on line 1 and a static 1
value on line 3, the other test has a falling transition on line 3 and a static 1 value on line 1.
Thus, robust path delay tests may not cover oscillatory noise effects.
To see the differences with tests for transition faults, let us assume that a rising transi-
tion on line 16 is to be tested. We want to see if this can create an error at an output. This
may be excited by a falling transition on line 2 and static 1 value on line 11. However, we
saw in the previous section that a falling transition on line 2 cannot be a test for the under-
shoot generated by the rising transition on line 16.
Crosstalk occurs when one signal line (affecting line) induces an undesired voltage
level on another (victim line). Crosstalk test patterns cannot be used for our purpose
because these patterns create a fast transition at an affecting line and propagate noise
effects from the victim line to an output [11]. Test patterns for Iddq testing do not propa-
gate fault effects from fault sites and therefore do not detect the noise effects being consid-
ered [70]. Also, test vectors for ground bounce are not sufficient because the objective of
these vectors is to maximize the transient switching current [6].
4.8 Conclusions
We have shown, by trend analysis, that the magnitude of oscillatory noise is expected
to increase in future technologies. Its impact on CMOS circuits has also been discussed. It
is seen that process variation may cause oscillatory noise to vary by +20%. It is also seen
123
that oscillatory noise first increases and then decreases with increase in interconnect
length. We see that oscillatory noise can be a problem in medium length interconnects in
combinational logic blocks. Oscillatory noise normally increases with a decrease in the
transition time of input stimulus. A slight non-monotonicity is noticed, but it is ignored for
test generation in current technologies.
To facilitate the test generation method, we have derived analytical expressions for (i)
the magnitude of overshoots and undershoots, and (ii) the settling time, i.e., the time
required by the circuit response to settle to a bound close to the final value. The analytical
expressions can also be used by a designer to guide design decisions and help reduce the
number of circuit simulations that must be performed during design. We have modeled the
input as an exponential function with arbitrary rise times (time required by the input to
change from 10% to 90% of its final value) and fall times, in contrast to previous research-
ers who have used a step input approximation [33], [73]. Using step input to model the
magnitude of oscillatory noise is less accurate than using an exponential input and any
design that attempts to eliminate all noise problems via step input analysis will be conser-
vative.
124
Chapter 5 Inductance Induced Noise on Adjacent Interconnects
5.1 Introduction
In this chapter we present experimental results with a focus on crosstalk noise induced
by inductance. Even though the observations presented here can be applied to different
areas of VLSI design, we are primarily concerned with their implications on test genera-
tion. First, we conduct a comparative analysis of capacitive and inductive noise to derive
an understanding of the impact of inductance induced noise. Test generation for induc-
tance induced noise is needed because, as we will show, this noise creates effects that are
different from capacitance induced noise. Second, we study the severity of noise in
medium length interconnects in combinational logic blocks. We will show that such noise
can be quite large and hence should be targeted for validation and test generation. Third,
we study the impact of edge-rate (or transition time) and skew on the magnitude of noise.
Fourth, we study the impact of process variations and spot defects on noise to understand
whether there is a need to consider noise during post fabrication testing. Finally, we study
the impact on noise and delay of static signal values on adjacent interconnects. This is
done to characterize the logic conditions that a test vector must satisfy on interconnects
adjacent to aggressor and victim lines.
We use the simulation tool HSPICE. The transistor parameters and interconnect resis-
tances and capacitances are obtained from process files. Loop inductances are used and are
obtained by extraction. Since the same set of values of interconnect and timing parameters
do not cause each of the different phenomena that are studied here, where necessary, we
choose different sets of parameters to study the different phenomena. It is known that
125
inductance and resistance vary as a function of frequency. However, this effect is not
incorporated in this study.
5.2 Experimental setup
For the case of multiple interconnects, where a signal transition on one interconnect
can affect the state of adjacent lines, we focus on (i) a crosstalk induced pulse, signal tran-
sition speedup and slowdown, and (ii) combinations of crosstalk noise and oscillation. We
use the simulation tool HSPICE.
For our studies, we use a 0.18 µ m copper process from UMC, a fabrication facility in
Taiwan [57]. The power supply voltage (Vdd) is 1.5 V in this technology, and the transis-
tor threshold voltages are roughly 25% of Vdd. It is assumed that there are several metal
layers available for the power and ground grid, and the interconnects. Each interconnect is
3 µ m wide. The thickness of an interconnect is about 1 µ m on the last metal layer in this
technology, and about 30% of that value on the first metal layer. Two different intercon-
nect configurations are used for all experiments discussed in this chapter (Figure 5-1). For
the first configuration (Figure 5-1(a)), the interconnects are on metal layer 4 and directly
over the substrate. The interconnect spacing used is 0.5 µ m. For the second configuration
FIGURE 5-1. Interconnect configurations
metal 1
metal 4
substrate
Cm
Cs Cs
substrate
metal 6
Cm
Cs
Cs
(a)
(b)
126
(Figure 5-1 (b)), the interconnects are on metal layer 6 and run parallel to metal layer 1.
The interconnect spacing is 0.24 µ m. The metal layer of an interconnect has a profound
impact on its capacitance values. There are two capacitance values associated with each
interconnect: (i) self capacitance, formed between the interconnect and the upper and
lower metal layers and substrate, denoted by Cs, and (ii) mutual capacitance formed
between two adjacent interconnects, denoted by Cm. Capacitance and resistance values of
interconnects at a DC voltage, obtained from process files, are used.
Loop inductance values are used in the simulations. The tool FASTHENRY is used for
extracting inductance values [34], [35]. The self inductance of an interconnect, and the
mutual inductance between interconnects is extracted when the interconnect or a set of
interconnects is surrounded by a power and ground grid. The magnitude of inductance is
dependent on the choice of the power and ground grid, since the current return loops are
formed through the power and ground grid. Each power and ground line is 3 µ m wide and
separated by 17 µ m. There are several layers of power and ground lines, and the power
and ground lines on one layer run orthogonal to the power and ground lines on the next
layer. On each layer, power and ground lines occur alternately. Whenever two orthogonal
power (ground) lines on two consecutive layers cross each other, they are connected by a
via. Thus, a three-dimensional power and ground grid is used. Such a power and ground
grid is not only realistic, but also represents a well-designed grid used by many high-end
circuit designers to minimize the impact of inductance on circuit operation [20], [62]. As a
result, in our experiments the magnitude of inductance is low. This in turn tends to reduce
the magnitude of inductance-induced effects.
127
It is assumed that the current returns through the entire grid. The current return paths
through the substrate are ignored since the resistivity of the substrate is several orders of
magnitude higher that of the metal layers. We also ignore the effect of switching of other
interconnects on the magnitude of inductance.
In this chapter, we primarily study noise for transition times at around 25 ps. The signif-
icant frequency for a trapezoidal pulse with a transition time T
r
is defined as 0.34/T
r
, and
about 85% of a signal’s frequency components are at frequencies below this frequency
[14]. It has been shown that inductance extracted at this frequency leads to quite accurate
results. Hence, inductance values are extracted at the corresponding significant frequency
of 14 GHz. Slower transition times correspond to lower significant frequency, and since
the magnitude of inductance is dependent on frequency, extracted inductance values
increase slightly with a decrease in the significant frequency.
A transmission line model is used for the simulation of circuits (Figure 5-2). An exam-
ple of how parameter matrices are formed for the case of two interconnects is also shown.
R
A
, C
A
, and L
A
are the resistance, capacitance, and inductance per unit length for line A,
and R
B
, C
B
, and L
B
are the same parameters for line B. C
AB
and L
AB
are the mutual
FIGURE 5-2. Circuit model and parameter matrices

R
A
L
A
R
B
L
B
C
A
C
B
C
AB
one stage of transmission line L
A
L
AB
L
AB
L
B
L=
C
A
+C
AB
-C
AB C=
-C
AB
C
B
+C
AB
R
A
0
R=
0 R
B
L
AB
Line A
Line B
128
capacitances and inductances, respectively. When three or more interconnects are consid-
ered, the matrices are defined in a similar way.
The interconnect parameters are shown in Figure 5-3. For the first interconnect configu-
ration (Figure 5-1(a)), the interconnect spacing is 0.5 µ m. When two interconnects are
used, the parameters are shown in Figure 5-3(a). When three adjacent interconnects are
used, the parameters are shown in Figure 5-3(b). For the second configuration (Figure 5-
1(b)), the interconnect spacing is 0.24 µ m. The parameters for the two interconnect case
and the four interconnect case are shown in Figure 5-3(c) and Figure 5-3(d), respectively.
The units of the interconnect parameters are as follows: inductance is expressed in pH/µ m,
capacitance in aF/µ m, and resistance in Ω /µ m. Interconnect lengths of 3000 µ m, and 8000
µ m are considered. The longer length is only used for studies on logic values on intercon-
nects adjacent to aggressor and victim.
Two aggressor driver sizes are used: (i) W
p
/L
p
= 36/0.18, W
n
/L
n
=36/0.18 (the ratio of
36/0.18 is the largest transistor size allowed in this technology), and (ii) W
p
/L
p
= 18/0.18,
FIGURE 5-3. Interconnect parameters
0.6 0.4
0.4 0.6
L=
100 -64
C=
-64 100
.004 0
R=
0 .004
0.6 0.36 0.25
0.36 0.6 0.36
L=
0.25 0.36 0.6
103 -64 -3
C=
-3 -64 103
0.63 0.4
0.4 0.63
L=
230 -80
C=
-80 230
.004 0
R=
0 .004
0.004 0 0
0 0.004 0
R=
0 0 0.004
0.63 0.4 0.29 0.18
0.4 0.63 0.4 0.29
L=
0.29 0.4 0.63 0.4
0.004 0 0 0
0 0.004 0 0
R=
0 0 0.004 0
0.18 0.29 0.4 0.63
0 0 0 0.004
236 80 5 1
80 236 80 5
C=
5 80 236 80
1 5 80 236
(a) (b) (c) (d)
-64 103 -64
129
W
n
/L
n
=36/0.18, where W
p
and W
n
are the width of the p and n transistors, respectively.
The second driver size is only used for the study of non-monotonic variations of crosstalk
pulse with rise time. Two victim driver sizes are used: (i) W
p
/L
p
= 2.4/0.18,
W
n
/L
n
=1.2/0.18, and (ii) W
p
/L
p
= 18/0.18, W
n
/L
n
=9/0.18. The second victim driver size is
only used for experiments on slowdown and speedup. Even if mismatched driver imped-
ances are not used in a design, they may get mismatched due to process variations and spot
defects. Two sizes of receiver are used: (i) W
p
/L
p
= 9/0.18, W
n
/L
n
=4.5/0.18, and (ii)
W
p
/L
p
= 9/0.18, W
n
/L
n
=9/0.18. The second receiver is only used for the study of non-
monotonic variation of crosstalk pulse with rise time.
Timing parameters, such as edge-rates or transition times and skews between transi-
tions, are specified separately for each experiment. The magnitude of skew is zero unless
stated otherwise. As stated earlier, we attempt to study noise for transition times at around
25 ps. Assuming that the same transition time is achieved by the circuit clock, and that
transition time is one-tenth of a clock cycle, the clock frequency of the circuit can be
assumed to be about 4 GHz.
It is known that inductance and resistance vary as a function of frequency [15]. How-
ever, since HSPICE does not support the simulation of frequency dependent inductance,
this effect could not be incorporated in this study. Ignoring frequency dependence, and
also using loop inductance instead of partial inductance produces somewhat inaccurate
results. However, the qualitative conclusions that we draw -- including (i) the differences
between noise induced by parasitic capacitances, and noise induced by parasitic capaci-
tances and inductances, (ii) dependence of noise on length, timing parameters, logic val-
ues on interconnects adjacent to aggressor and victim, and process variations and spot
130
defects -- will not be altered if the simulation model incorporated frequency dependence
and partial inductances. In our ongoing work, we will exploit the above qualitative conclu-
sions to generate tests. The generated tests can then be validated using more accurate sim-
ulation models.
Further, for models used in validation and testing, it is critical that the model overesti-
mates the magnitude of noise rather than underestimate it. This is because if the magni-
tude of noise is underestimated, potential problems may be ignored. During validation, if
the magnitude of noise is underestimated, then there is no guarantee that the design is
functionally correct. During testing, if the magnitude of noise is underestimated, then no
test may be sought for a potential problem. As a result, the circuit may pass the test proce-
dure, but may malfunction in the field.
5.3 Inductance induced noise
5.3.1 Crosstalk pulse
We conduct a comparative study on the amplitude of crosstalk induced pulse. The cir-
cuit shown in Figure 5-4 is used. The input to the aggressor line driver at A is excited with
a ramp input changing from low to high and the input to the victim line driver at input B is
FIGURE 5-4. Circuit used to study crosstalk
36:0.18
36:0.18
9:0.18
4.5:0.18
2.4:0.18
1.2:0.18
9:0.18
4.5:0.18
5 fF
5 fF
A
B
D
aggressor
victim
131
held constant at zero. The magnitude of the pulse at the victim output, line D, is measured.
The interconnect length is 3000 µ m. The two interconnects are separated by 0.5 µ m, and
the interconnect parameters correspond to those in Figure 5-3(a). The first aggressor
driver, the first victim driver, and the first receiver are used.
The following four cases are considered: (i) all inductances are ignored, denoted by
(Cs,Cm,Ls,Lm), (ii) the mutual capacitance between the interconnects is ignored
(Cs,Cm,Ls,Lm), (iii) the mutual inductance between the interconnects is ignored
(Cs,Cm,Ls,Lm), and (iv) all inductances and capacitances are considered (Cs,Cm,Ls,Lm).
The simulation results are shown in Figure 5-5. A crosstalk pulse is induced on the victim
line due to a transition on the aggressor line. Except for case (i), the crosstalk pulse is
oscillatory. In general, oscillation is observed whenever the rise time is small or the ratio
of inductance to capacitance is high. The value of the noise is maximum for case (iv), and
FIGURE 5-5. Crosstalk pulse
Voltages (lin)
-200m
-100m
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
1.4
1.5
Time (lin) (TIME)
5n 5.02n 5.04n 5.06n 5.08n 5.1n 5.12n 5.14n 5.16n 5.18n
Case (iv)
Case (iii)
Case (i)
Case (ii)
(Cs,Cm,Ls,Lm)
(Cs,Cm,Ls,Lm)
(Cs,Cm,Ls, Lm)
(Cs,Cm,Ls,Lm)
Input
at A
132
is slightly larger than the power supply voltage. This magnitude is more than twice as
large as the pulse for case (i). This demonstrates that crosstalk induced by a combination
of mutual inductance and capacitance can be more severe than that due to capacitive cou-
pling alone. The magnitude of the pulse in case (ii) is very small. This implies that the
crosstalk without the presence of mutual capacitance may not be a problem. However,
even when capacitive coupling is dominant over inductive coupling, the presence of induc-
tance can significantly affect the noise. The peak magnitude of the pulse for case (iii) is a
little less than that for case (iv). From a comparison of the pulses in cases (i) and (iii), we
see that self inductance causes the pulse to have a steep initial slope. In general, the self
inductance of the victim causes the crosstalk pulse to have a small rise time, and also the
self inductance of the aggressor causes the aggressor signal to have a steep rise time. Both
of these effects increase the magnitude of the pulse. We believe this is the primary reason
why the combination of capacitive and inductive coupling results in a larger crosstalk
pulse, compared to the case of only capacitive coupling [21]. Also, for cases (ii) and (iii),
the oscillation start out in opposite phases, and for the most part of the response, when the
pulse due to (ii) changes direction, so does the pulse due to (iii). However, the two direc-
tions in which the two pulses move are usually opposite to each other, and is attributed to
the phase difference between inductive and capacitive voltages. It is clear from these
results that when inductance is considered, new design issues must be considered.
5.3.2 Crosstalk slowdown and speedup
We present a comparative study of capacitive and inductive crosstalk with the objective
of understanding the increase in the magnitude of crosstalk slowdown and speedup when
parasitic inductance is considered. We will discuss three experiments. For these experi-
133
ments, delay is defined as the time elapsed between 50% of input change and 50% of out-
put change.
For the first two experiments, the circuit in Figure 5-4 is again used. The first aggressor
driver, the second victim driver, and the first receiver is used. The interconnect parameters
are as shown in Figure 5-3(a). For the first experiment, the inputs to the victim and the
aggressor drivers have rising and falling transitions, respectively, with transition times of
25 ps each. Additionally the aggressor input changes 25 ps after the victim input. The fol-
lowing four cases are considered: (i) all inductances are ignored and the aggressor is not
switched (Cs, Cm, Ls, Lm, Vic, Agg), (ii) all inductances are ignored and the aggressor is
switched (Cs, Cm, Ls, Lm, Vic, Agg), (iii) all inductances are considered and the aggres-
sor is not switched (Cs, Cm, Ls, Lm, Vic, Agg), and (iv) all inductances are considered
and the aggressor is switched (Cs, Cm, Ls, Lm, Vic, Agg). Simulation results are shown in
FIGURE 5-6. Crosstalk slowdown: Aggressor and victim switch in opposite
direction
Voltages (lin)
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
1.4
1.5
Time (lin) (TIME)
5n
5.02n 5.04n 5.06n 5.08n 5.1n 5.12n
5.14n
* transsim comparing the effects on speedup of inductance, capac
Case (i)
Case (ii)
Case (iii)
Case (iv)
(Cs,Cm,Ls,Lm,Vic,Agg)
(Cs,Cm,Ls,Lm,Vic,A
(Cs,Cm,Ls,Lm,Vic,Agg)
(Cs,Cm,Ls,Lm,Vic,Agg)
Input to
victim
134
Figure 5-6. The difference in delay, i.e., the slowdown in a transition at the output of the
victim receiver when the aggressor is not switched versus when it is switched with all
inductances ignored (i.e. case (i) and case (ii)) is 40 ps. When all inductances are consid-
ered (i.e. case (iii) and case (iv)), the slowdown is 46 ps. Not only is the absolute magni-
tude of the delay higher (about 15%), but the inductance induced slowdown causes the
latest occurring transition among all four cases. Thus, the magnitude of crosstalk slow-
down may increase when parasitic inductances are considered.
In the second experiment, crosstalk speedup is studied. The same circuit is considered.
The inputs to the victim and the aggressor drivers now have rising transitions, with transi-
tion times of 100 ps and 25 ps, respectively. Again, four cases are considered: (i) all induc-
tances are ignored and the aggressor is not switched (Cs, Cm, Ls, Lm, Vic, Agg), (ii) all
inductances are ignored and the aggressor is switched (Cs, Cm, Ls, Lm, Vic, Agg), (iii) all
FIGURE 5-7. Crosstalk speedup: Aggressor and victim switch in the same
direction
Voltages (lin)
-200m
-100m
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
1.4
1.5
Time (lin) (TIME)
5.02n 5.04n 5.06n 5.08n 5.1n 5.12n 5.14n
* transsim comparing the effects on speedup of inductance, capac
Case (iv)
Case (ii)
Case (iii)
Case (i)
(Cs,Cm,Ls,Lm,Vic,Agg)
(Cs,Cm,Ls,Lm,Vic,Agg)
(Cs,Cm,Ls,Lm,Vic,Agg
(Cs,Cm,Ls,Lm,Vic,A
Input
135
inductances are considered and the aggressor is not switched (Cs, Cm, Ls, Lm, Vic, Agg),
and (iv) all inductances are considered and the aggressor is switched (Cs, Cm, Ls, Lm,
Vic, Agg). The output is shown in Figure 5-7. The difference in delay, i.e., the speedup
between case (i) and case (ii) is 42 ps. When all inductances are considered (case (iii) and
case (iv)), the speedup is 66 ps. Again, not only is the absolute magnitude of the speedup
higher (about 57%), but also the inductance induced speedup causes the earliest occurring
transition among all four cases. Thus, the magnitude of crosstalk speedup may increase
when parasitic inductances are considered.
For the third experiment, three parallel interconnects are considered. The interconnect
in the middle is driven by a driver that is sized similarly to the victim driver, and its input
is static zero. One of the outer interconnects is the aggressor and the other is the victim.
The interconnect parameters are as shown in Figure 5-3(b). The transitions at the inputs of
victim and aggressor are in the same direction, with transition times of 50 ps and 100 ps,
respectively.
In this case, the mutual inductance has a moderate value but the mutual capacitance is
very low. The same four cases are considered and simulation results are shown in Figure
5-8. Case (ii) leads to a speedup of 7 ps with respect to case (i). When all inductances are
considered (case (iii) and (iv)) switching the aggressor increases the delay of the victim by
about 6 ps.
When the ratio of mutual inductance to mutual capacitance is high, slowdown occurs
even though the aggressor and victim inputs transition in the same direction. For an expla-
nation of this phenomena, please refer to Section 5.3.1.
136
Recall that inductive and capacitive voltages move in directions opposite to each other.
Since mutual capacitance is negligible, mutual inductance determines the nature of the
waveform, hence creating the slowdown. A similar phenomenon for a specific layout was
observed in [59]. Even though this slowdown effect may not be significant in current tech-
nologies, it may cause errors in future generations of circuits.
Next, the transition time at the aggressor is set to 100 ps, and there is a speedup of 22
ps. This is an interesting result, in that it illustrates that depending on the input transition
rate, one can observe speedup or slowdown.
FIGURE 5-8. Crosstalk slowdown: aggressor and victim switch in same
direction and inductive coupling dominates capacitive coupling
Voltages (lin)
-100m
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
1.4
1.5
Time (lin) (TIME)
5.02n 5.04n 5.06n 5.08n 5.1n 5.12n 5.14n 5.16n
*transsim -- lines moving in the same direction slow each other
Case (i)
Case (iii)
Case (iv)
Case (ii)
(Cs,Cm,Ls,Lm,Vic,Agg)
(Cs,Cm,Ls,Lm,Vic,Agg)
(Cs,Cm,Ls,Lm,Vic,Agg)
(Cs,Cm,Ls,Lm,Vic,Agg
Input
137
5.3.3 Combination of oscillatory noise and crosstalk
We next consider how the skew between the aggressor and the victim signals affects the
combination of oscillatory and crosstalk noise.
The circuit used is similar to the one in Section 5.3.1, but now all inductance values are
doubled (as in the studies on oscillatory noise in Chapter 4), and the aggressor driver is
used to drive both lines. The following cases are considered: (i) only the victim switches,
and (ii) the aggressor and victim switch in the opposite direction. Several values of skew
are used. For all cases, the output of the victim receiver has some oscillation (Figure 5-9).
In Figure 5-9, a negative skew implies that the aggressor leads the victim. For case (i), the
maximum value of the undershoot is negligible. For case (ii), the undershoot is a function
of skew. The largest value of the undershoot occurs when the aggressor lags the victim by
80 ps and is equal to 1.1 V (> Vdd/2).
FIGURE 5-9. Combination of oscillatory noise and crosstalk
Voltages (lin)
-600m
-400m
-200m
0
200m
400m
600m
800m
1
1.2
1.4
1.6
Time (lin) (TIME)
5.02n 5.04n 5.06n 5.08n 5.1n 5.12n 5.14n 5.16n 5.18n 5.2n 5.22n
* transsim comparing the effects of skew on combined effect of
Case (i)
Case (ii),
skew=-100 ps
Case (ii),
skew = 100 ps
input
Case (ii),
skew = -80 ps
138
Clearly, the magnitude of noise is a function of skew. However, the value of skew that
maximizes the noise is different for different circuits. Once again, such noise may be
insignificant in current technologies but may be a problem in the near future.
5.4 Interconnect length
The impact of interconnect length on crosstalk pulse is now studied. We are primarily
interested in test generation for combinational blocks. Since the interconnects that occur in
such blocks are not very long, one question is whether inductance induced noise in such
blocks need be considered in validation and/or test.
In the next series of experiments, the line length is increased from 1,000 µ m to 10,000
µ m, and two different sets of interconnect parameters are used. The first set (circuit 1) of
FIGURE 5-10. Variation of noise with length
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
crosstalk pulse amplitude,
circuit 2
crosstalk pulse amplitude,
circuit 1
undershoot,
circuit 1
undershoot,
circuit 2
139
parameters is shown in Figure 5-3(a). The second set (circuit 2) of interconnect parameters
is shown in Figure 5-3(c). The results are shown in Figure 5-10.
Focusing first on crosstalk pulses, for the first circuit, the crosstalk pulse amplitude first
increases and then decreases. The maximum occurs at 3000 µ m, and is more than three
times the threshold voltage. For the second circuit, the crosstalk pulse saturates at a volt-
age that is a little higher than the power supply voltage.
Assuming that the longest interconnects in combinational blocks are 3000 µ m long, we
may observe a significant amount of crosstalk for interconnects below this length.
5.5 Signal edge-rate and skew
We study the impact of timing parameters, such as transition times and skew.
FIGURE 5-11. Variation of crosstalk pulse amplitude with edge-rate
0 10 20 30 40 50 60 70
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
Aggressor rise time (ps)
Voltage (V)
140
The impact of edge-rate on a crosstalk pulse is first considered. It is seen that the maxi-
mum magnitude of the pulse changes non-monotonically with edge-rate (Figure 5-11).
The interconnect parameters used for this study are the ones obtained for the first configu-
ration (Figure 5-3(a)), where the aggressor and the victim interconnects are driven in
opposite directions (i.e. the aggressor is driven from left to right, as in Figure 5-4, and the
victim is driven from right to left), and the interconnect length is 2900 µ m. The second
aggressor driver, the first victim driver and the second receiver are used. It is assumed that
the transmission line model is valid for very fast edge-rates. The edge-rate of the input sig-
nal is varied from 1 ps to 70 ps. The peak magnitude when the input edge-rate is 20 ps is
higher than the magnitude of the pulse when the input edge-rate is 10 ps. Even though
such edge-rates are very fast and not seen in current technologies, such fast edge-rates will
be possible in future technologies. Since other parameters will also change in future tech-
nologies, whether this non-monotonic effect becomes significant or remains an uncom-
mon effect can only be verified when data from future processes are available.
The combined impact of edge-rate and skew on crosstalk delay is considered next. The
circuit used for this study is the same as the ones used for the first two experiments in Sec-
tion 5.3.2. The edge-rate of the aggressor driver is varied from 0 ps to 200 ps, in steps of
50 ps. The skew between the two signals is varied from -150 ps to 100 ps, in steps of 50
ps. The minimum delay is 61 ps and the maximum is 104 ps. The delay at the victim out-
put when the aggressor does not switch is 55 ps. Again, the delay varies non-monotoni-
cally with the values of edge-rate and skew. The variation of delay at the output of the
victim receiver with changes in aggressor edge-rate and skew is shown in Figure 5-12. The
average delay is 75 ps which is less than the maximum delay by about three gate delays.
141
We further observe that crosstalk delay varies non-monotonically both when inductance
is and is not considered. However, when the interconnect inductances are modeled, the
variation in delay is higher. The larger variation in crosstalk delay due to inductance sug-
gests that a significant leverage can be obtained by designing a test generator that maxi-
mizes the crosstalk delay as a function of timing parameters.
The optimal test vectors used to excite and detect such noise effects should try to excite
the “best” value of the combination of edge-rate and skew. Since the non-monotonic
behavior of crosstalk pulse is not significant, a test generator for crosstalk pulse can ignore
this non-monotonic behavior. For crosstalk delay, however, the variation is significant, and
a test generator should consider the non-monotonic characteristics.
FIGURE 5-12. Variation of crosstalk delay as a function of aggressor edge-rate
and skew
−150
−100
−50
0
50
100
0
50
100
150
200
60
65
70
75
80
85
90
95
100
105
skew (ps)
aggressor rise time (ps)
noise (V)
142
5.6 Spot defect and process variation
We now consider the impact of spot defects and process variation on crosstalk pulse.
Our objective is to determine how much the magnitude of inductance induced noise can
increase due to variations and spot defects caused by the fabrication process. We conduct
these experiments for both interconnect configurations. We show the results for the config-
uration shown in Figure 5-1(b). The interconnect parameters are as shown in Figure 5-
3(c). The first aggressor driver, the first victim driver and the first receiver are used.
Spot defects, such as those that reduce the strength of the victim driver, can increase the
magnitude of the crosstalk pulse at the victim output. For a specific circuit in which the
strength of the victim driver is reduced to half its original value (simulated by re-sizing a
transistor), the magnitude of the crosstalk pulse increases by about 20% (Figure 5-13). It is
FIGURE 5-13. Impact of spot defect on crosstalk pulse
Voltages (lin)
-100m
-50m
0
50m
100m
150m
200m
250m
300m
350m
400m
450m
500m
550m
600m
650m
700m
750m
800m
850m
900m
950m
Time (lin) (TIME)
5.05n
5.06n 5.07n 5.08n 5.09n 5.1n 5.11n 5.12n 5.13n
5.14n
* studying the impact of rise time on inductive crosstalk *
Pulse when
spot defect
is present
Pulse when
spot defect is absent
143
conceivable that a near-break on the interconnect just following the victim driver in the
layout of the design will result in a similar increase in noise.
The impact of process variations on inductance can be assumed to be negligible because
the area of the loops are large compared to changes in dimensions due to process varia-
tions. However, inductance induced noise can still vary significantly due to variations in
other circuit parameters, as shown in the following example. It is assumed that two differ-
ent and uncorrelated sources of process variation are present: (i) the sheet resistance of the
interconnect, and (ii) the gain factors of the transistors. Three different realistic values of
sheet resistances as found in the process files are used. Five different process corners for
transistors are used: (i) typical p-transistor and typical n-transistor corner (or typical-typi-
cal corner), (ii) fast-fast corner, (iii) slow-slow corner, (iv) fast-slow corner, and (v) slow-
fast corner. These lead to fifteen different combinations. It is assumed that all other circuit
FIGURE 5-14. Impact of process variation on crosstalk pulse
Voltages (lin)
-100m
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
Time (lin) (TIME)
5.05n 5.06n 5.07n 5.08n 5.09n 5.1n 5.11n 5.12n 5.13n 5.14n 5.15n
** impact of process variation on crosstalk slowdown **
Crosstalk pulse
for nominal
parameters
Maximum
crosstalk pulse
Minimum
crosstalk pulse
144
parameters remain the same. The maximum magnitude of the crosstalk pulse occurs for
the minimum value of sheet resistance and the slow-fast corner (Figure 5-14). This value
is more than twice the value for nominal set of parameters. This experiment shows that
when inductance is considered, process variation has a huge impact on crosstalk.
Traditionally, gate delays due to process variation are determined by simulating a gate
at worst case process corners. However, interconnect delays are significant in present and
future technologies, and it has been shown that worst case interconnect delays cannot be
captured by simulating the circuit at worst case/best case process corners [45]. This is
because the worst case interconnect delays are context sensitive. This observation implies
that, even after validating the design at different process corners, the fabricated circuit may
still fail due to unforeseen process variation.
5.7 Dependence on logic values on adjacent lines
In this section, we illustrate how the magnitude of noise is affected by input stimulus
applied to interconnects adjacent to a coupling circuit. The circuit in Figure 5-15 is used
for this purpose. The self and mutual capacitances, the self and mutual inductances, and
the self resistances are obtained for the second interconnect configuration (Figure 5-1(b)).
The parameters are as shown in Figure 5-3(d). The interconnect length for these experi-
ments is 8000 µ m. When an interconnect length of 3000 µ m is used for the same set of
parameters, the effect is much less pronounced.
The impact of switching signals on adjacent interconnects has previously been
addressed [50], [18]. For the capacitive only case, it was shown in [18] that when all
aggressors switch in the same direction, the crosstalk pulse is the largest. For the capaci-
tive and inductive case, it was shown in [50] that, when the nearest aggressors switch in
145
one direction, and the other non-adjacent aggressors switch in the opposite direction, then
the crosstalk pulse is the largest. We have also seen that among all possible patterns, sig-
nals on non-adjacent aggressors that switch in the same direction as that on the adjacent
aggressors can create the largest pulse. Further, the input pattern that creates the largest
pulse depends on the circuit parameters. In this section, we address the more interesting
case when signals on adjacent interconnects are static. The impact at the victim output of
static signals on adjacent lines has not been previously addressed in the literature.
Two cases are considered: (i) capacitive coupling, and (ii) combination of capacitive
and inductive coupling. We first focus on crosstalk delay. The inputs to the aggressor and
the victim drivers were switched in opposite directions, with transitions times of 25 ps and
100 ps, respectively. For each of these two cases, the following static values are applied on
the nodes I1 and I4: (a) I1=0, I4=0, (b) I1=0, I4=1.5 V, (c) I1=1.5 V, I4=0, and (d) I1=1.5
V, I4=1.5 V, where Vdd=1.5 V. The magnitude of crosstalk delay for case (i) varies by 73
FIGURE 5-15. Circuit configuration used for study on pattern dependence
36:0.18
36:0.18
9:0.18
4.5:0.18
2.4:0.18
1.2:0.18
9:0.18
4.5:0.18
5 fF
5 fF
D
Line2, aggressor
Line3, victim
4.5:0.18
2.4:0.18
4.5:0.18
5 fF
I4
9:0.18
4.5:0.18
2.4:0.18
4.5:0.18
5 fF
I1
9:0.18
s0
or
P
Line 1
Line 4
I2
I3
146
ps. An exactly similar variation in crosstalk delay is noticed for case (ii). This increase in
delay from sub-case (a) to sub-case (d), for each of case (i) and (ii), is about 3%. We thus
see that the crosstalk delay is dependent on values of static signals on adjacent lines, both
for cases (i) and (ii). From the waveforms for case (ii), shown in Figure 5-16, we see that
the maximum delay occurs for case (d). Even though the impact shown here is small, the
impact can be large, as we shall see for the case of a crosstalk pulse.
One explanation of this phenomenon is based on the impedances presented to each of
the aggressor and victim inputs for each of the four subcases (a)-(d). For each of these sub-
cases, different transistors in the drivers and receivers are conducting. For example, for
sub-case (a), the p-transistors of the drivers in the adjacent lines and the n-transistors in the
receiver are conducting. Thus, the impedance is different from the case in sub-case (d)
when the n-transistors of the drivers and the p-transistors in the receivers are conducting.
FIGURE 5-16. Crosstalk delay at victim for different values of static inputs on
adjacent lines
Voltages (lin)
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
1.4
1.5
Time (lin) (TIME)
5n 6n 7n
* pattern dependence of xtalk delay *
Input at victim
I1=0, I4=0
I1=1.5,
I4 =1.5
147
Therefore, because of the difference in impedance presented to the switching aggressor
signal, the amount of crosstalk on the victim line is different. Also, the variation is due to
the differences in impedance that the lower static line presents to any signal induced on the
victim line. Because the combined effects of mobility and transistor sizing make the p-
transistors weaker than the n-transistors, and because, in this case, the driver transistors
have a higher impact on the impedance presented to the current than the receiver transis-
tors (we verified this observation for this particular circuit by simulation), we see that the
noise is maximum for sub-case (d). Additionally, signal oscillation can play a role, as we
shall see for the case of a crosstalk pulse.
The variation in the magnitude of the crosstalk pulse for each of the cases is shown in
Figure 5-17. We see that the capacitive crosstalk pulse is quite small, and the static signals
values have a negligible impact. The crosstalk pulse resulting from a combination of
FIGURE 5-17. Crosstalk pulse at victim for different values of static inputs on
adjacent lines
Voltages (lin)
-50m
0
50m
100m
150m
200m
250m
300m
350m
400m
450m
500m
550m
600m
650m
700m
750m
800m
850m
900m
950m
1
1.05
1.1
Time (lin) (TIME)
4.12n 4.14n 4.16n 4.18n 4.2n 4.22n 4.24n 4.26n 4.28n 4.3n 4.32n 4.34n
* pattern dependence of xtalk delay *
I1=0, I4=0 (1.09V)
I1=1.5, I4=0
I1=0, I4=1.5
I1=1.5, I4=1.5
capacitive cases
(1.01 V)
(0.96 V)
(0.87 V)
Inductive
cases
148
capacitive and inductive crosstalk is significantly affected by the static values on the adja-
cent lines. The variation in the magnitude of the pulse is as large as 22% about the mean
magnitude.
To understand why there is a difference in magnitude between the capacitive crosstalk
pulse and the capacitive and inductive crosstalk pulse, we have to look into the voltage at
the victim receiver input, namely node P, in Figure 5-15. These voltages are shown in Fig-
ure 5-18. We see that due to oscillation, the voltage at node P (i.e. victim receiver input) is
quite large for case (ii), but not for case (i). This demonstrates that the combination of
oscillation, crosstalk and difference in load impedances causes a variation in the magni-
tude of the crosstalk pulse. The voltages at node D (victim receiver output) are also shown.
It is obvious that the large pulse at P for case (ii) causes a large pulse at the output.
FIGURE 5-18. Voltages at victim driver input and output when I1=0, I4=0
Voltages (lin)
-200m
-100m
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
1.4
1.5
Time (lin) (TIME)
4n 4.05n 4.1n 4.15n 4.2n 4.25n 4.3n 4.35n 4.4n 4.45n 4.5n 4.55n 4.6n 4.65n 4.7n
* pattern dependence of xtalk delay *
Aggressor
input Victim output for
inductive case
Victim output for
capacitive case
V oltage at P
for inductive case
V oltage at P for
capacitive case
149
5.8 Conclusion: Results in terms of test and validation
The problems targeted by test generation are the effects of inductance on adjacent sig-
nal interconnects: (i) crosstalk pulse, (ii) crosstalk speedup and slowdown, and (iv) combi-
nation of crosstalk and oscillatory noise. Such noise may cause an erroneous value to be
stored in latches/flip-flops. These noise effects may not be detected by conventional two
pattern tests, such as delay fault tests and transition fault tests. In this section we will first
motivate the need for generating tests for such faults, and then discuss the noise character-
istics that will be used in determination of test vectors.
5.8.1 Motivation for the test generation problem for inductance induced noise
By means of a comparative study of pulse induced by parasitic capacitances, and para-
sitic capacitances and inductances, we observed (in Section 5.3.1) that the magnitude of
crosstalk pulse may be higher when inductance is considered. Crosstalk induced slow-
down is caused by input transitions in opposite directions for circuits where mutual capac-
itance dominates mutual inductance, and by input transitions in the same direction for
circuits where mutual inductance dominates mutual capacitance (Section 5.3.2). A similar
observation holds for crosstalk speedup. Further, the same circuit may exhibit slowdown
for certain values of timing parameters, and speedup for other values of timing parameters.
The magnitude of slowdown when transitions move in the opposite directions (speedup
when transitions move in same direction) is significant and should be addressed for test
generation. This implies that similar to the test generation problem for capacitive crosstalk
and ground bounce [11], [43], [6], we should also generate tests for inductance induced
150
pulse, slowdown (transitions in opposite directions), and speedup (transitions in same
directions) for on-chip interconnects.
The magnitude of slowdown when transitions move in the same direction (speedup
when transitions move in the opposite direction) is not very significant in current technol-
ogies and need not be addressed (Section 5.3.2). We observed (in Section 5.3.3) that oscil-
latory behavior can be superimposed onto a crosstalk pulse to create a high magnitude of
noise.
It has been argued by others that inductance induced problems are most pronounced in
long buses, and that there is no need to study such noise in medium length interconnects.
We observed (in Section 5.4) that, in current technology, interconnects in combinational
logic blocks are long enough to give rise to significant crosstalk induced errors. Therefore,
inductance induced noise should be considered during test generation for combinational
blocks with medium length lines.
We observed (in Section 5.6) that noise can be affected by spot defects and variations in
process parameters. Therefore, we should also generate test vectors so that we can test
fabricated chips to identify noise induced errors missed during validation and the effects
of spot defects and process variation.
5.8.2 Noise and delay characteristics for test vector determination
We observed (in Section 5.5) that the magnitude of a crosstalk pulse is a non-monotonic
function of input rise time when parasitic inductances are involved, which is not true when
only parasitic capacitances are considered. However, both seem to be insignificant in cur-
rent technologies. This slight non-monotonic behavior in crosstalk pulse can be ignored by
test generator for noise in current technologies, but may have to be addressed in the future.
151
However, we observed (in Section 5.5) that the variation of crosstalk delay as a function
of transition times and skew values is non-monotonic whether or not inductance is consid-
ered. Furthermore, when inductance is considered, the variation in crosstalk delay due to
changes in transition times and skews tends to be larger than when inductance is not con-
sidered. A test generator for crosstalk delay should take this non-monotonicity into
account. If crosstalk delay is a monotonic or bitonic function of timing parameters, then
single ranges of arrival and transition times at aggressor and victim inputs need to be tar-
geted for producing noise greater than a certain threshold. However, if this function is nei-
ther monotonic nor bitonic, then, conceivably, for disjoint ranges of timing parameters, the
noise may be greater than the threshold. Thus, several ranges of arrival and transition
times may have to be targeted. As an example, if we want to create timing conditions for
the delay to be greater than 95 ps in Figure 5-12, then there are three alternative ranges
that the test generator should consider: (i) skew is 0 ps and aggressor rise time is between
0 ps and 50 ps, (ii) skew is -50 ps and aggressor rise time is between 50 ps and 100 ps, and
(iii) skew is 0 ps and aggressor rise time is 200 ps.
We observed in Section 5.7 that the values of static signals on interconnects adjacent to
the aggressor and victim can have an impact on the magnitude of noise and delay, for both
the capacitive case and the capacitive and inductive case. Thus, a test generator should not
only assign logic values on aggressor and victim lines to create worst case noise effects,
but also assign appropriate logic values on lines adjacent to the aggressor and victim.
152
Chapter 6 Future Work
6.1 Timing analysis
The timing analysis routines have to be more sophisticated to be able to support a tim-
ing based test generator. First, the delay model incorporating simultaneous to-controlling
transition is not available in software. As a result the test generator works with an incom-
plete delay model and, therefore, we haven’t been able to see a true picture about the effi-
cacy of the test generator. Secondly, the timing analysis routines cannot currently handle
false paths. As a result, some timing ranges are erroneously wider than they should be.
This has an effect on the detectability of faults. Thirdly, the required time computation is
computationally inefficient. As a result, we compute the required time once with unknown
values on the primary inputs and use the required time range throughout the procedure.
The required time range computation should be based on table lookup.
6.2 Test generation
6.2.1 Learning algorithms
Static and dynamic learning have been used to infer logic conflicts early, given a logic
assignment, for the stuck-at fault model [1]. Recently, a more powerful algorithm, known
as recursive learning, was proposed for the same [41]. We think that learning algorithms
should be developed for crosstalk test generation. This will increase the efficiency of test
generation and reduce unnecessary search.
153
6.2.2 Propagation conditions for pulse and oscillatory noise
Besides static non-controlling values on side-inputs, we can use hazardous non-con-
trolling values and transitions to propagate pulses. We illustrate the case for transitions in
Figure 6-1. Suppose that a pin-to-pin delay model is used and the delays from each input
to the output are equal. Thus at the output, we see transitions that carry the noise effect and
also hazards that carry the noise effect. Transitions and hazardous values were not used to
propagate pulses in previous work [13].
For propagation of oscillatory transitions, again we can use transitions as well as static
and hazardous values at side inputs for propagation of the fault. For static gates, an oscilla-
tory transition is similar to a transition carrying a pulse effect. Note that an overshoot
above the power supply voltage and an undershoot below the reference voltage are filtered
out by static gates.
FIGURE 6-1. Pulses propagated by transitions
154
6.2.3 Test generation for validation
In [26], a technique was proposed for adaptive validation. Given a circuit for valida-
tion, a small sub-circuit around the crosstalk site is chosen, and test generation is carried
out around this sub-circuit. If no test is found, then the crosstalk noise effect cannot lead to
an error. If a test is found, then a bigger sub-circuit is chosen which contains the sub-cir-
cuit from the previous stage, and the test generation procedure is again carried out. This
procedure is repeated until either no test is found at some stage, implying that the crosstalk
noise is benign, or a test is found in the original circuit. From a sub-circuit at one stage, a
sub-circuit at the next stage is formed by adding lines that impose new logic constraints.
Thus, the test generation problem is made progressively more difficult.
Given this scenario, the problem that we want to address is to reuse computation when
test generation is carried out in a sub-circuit that contains sub-circuits from previous
stages. We propose an algorithm that combines the D-algorithm and PODEM. When a test
is found for a sub-circuit, new lines are identified as primary inputs and outputs, and a
recursive call to the algorithm is made for the next stage sub-circuit. Also, logic values are
FIGURE 6-2. Incremental validation
PI
1
PI
2 PI
3
155
assigned only on lines that are primary inputs for some sub-circuit. The algorithm is
described using Figure 6-2.
When we generate tests for the innermost circuit, we assign values only to the primary
input lines PI
1
. Thus, for the innermost circuit, the algorithm is essentially PODEM based.
When we generate tests for the intermediate circuit, we assign values to lines in the set PI
1
and PI
2
. Similarly, when we generate tests for the entire circuit, we assign values to the
lines in the sets PI
1
, PI
2
, and PI
3
. Thus, for the second circuit, the branch and bound tree
for the innermost circuit and the values on the lines in the set PI
1
are used. Similarly, for
the third circuit, the branch and bound tree used for the second circuit and values assigned
to PI
1
and PI
2
are used. Thus, the method of test generation for the last two circuits are not
conventional PODEM because conventional PODEM algorithm assigns values to primary
inputs only. Similarly, this method is not conventional D-algorithm because D-algorithm
assigns values on internal lines. We do not use the conventional PODEM procedure
because we want to reuse the values computed and the history of backtracks from sub-cir-
cuit stages. Similarly, we do not use conventional D-algorithm because assigning values
on internal lines, as a D-algorithm does, increases the search space.
This method can also be applied to validate circuits with gate delay faults, transition
delay faults and faults that can be modeled as a missing gate, an additional gate or an erro-
neous gate in the Boolean realization of a function.
156
6.3 Modeling for inductance induced noise
6.3.1 Analytical model for noise computation
In [10], an analytical model for capacitive crosstalk was developed. Given a pair of
interconnects such that interconnect resistances, interconnect capacitances, driver resis-
tances and load capacitances are known, along with the transition times and skew between
transitions at the inputs, the magnitude of the noise at the output of the victim can be
determined. A similar model should be developed which incorporates interconnect induc-
tances. Several models for noise with interconnect inductance have been developed. How-
ever, these models are simplistic. For example, the model proposed in [14] is a one-stage
model. It is well known that a one-stage model is a good approximation for capacitive
lines but a poor approximation for inductive lines. Further, the mutual capacitance was
ignored. However, we saw in our simulations in Section 5.3 that the mutual capacitance
plays a significant role in determining the noise. Thus, the proposed model results in sig-
nificant error. Yet another model was proposed in [72]. This model assumed that the two
adjacent lines have the same resistance, capacitance and inductance. Again, this is a sim-
plistic assumption. Therefore, there is a need for a crosstalk model which considers both
inductance and capacitance.
6.3.2 Analytical model for oscillatory noise propagation
In [11], a model for propagation of capacitive crosstalk noise was proposed. This
involves forming an equivalent inverter of the gate, determining the transfer function of
the equivalent inverter, and determining the output for the noise function. The noise at the
input is approximated by a linear function. When inductance is involved, the noise is oscil-
157
latory. Therefore, the noise function has to be approximated by a different linear function
and this linear function has to be determined.
158
Bibliography
[1] Abramovici, M., Breuer, M. A., Friedman, A. D.: Digital systems testing and testable
design, Computer Science Press, 1990.
[2] Bakoglu, H.B.: Circuits, Interconnections and packaging for VLSI, Addison-Wesley
Publishing Company, 1990.
[3] Bose, S., Agrawal, P., Agrawal, V . D.: Deriving logic systems for path delay test gen-
eration, IEEE Trans. on Computers, vol. 47, no. 8, pp. 829-846, 1998.
[4] Breuer, M. A., Gupta, S.K.:Process aggravated noise (PAN): new validation and test
problems, Proc. Int’l Test Conf., pp. 914-923, 1996.
[5] Brews, J.R.: Electrical modeling of interconnections, in SubMicron Integrated Cir-
cuits, ed. R. Watts, John-Wiley and Sons, pp. 269-331, 1989.
[6] Chang, Y ., Gupta, S.K., Breuer, M. A.: Test generation for maximizing ground bounce
for internal circuitry with reconvergent fan-outs, Proc.VLSI Test Symposium, pp. 95-104,
1999.
[7] Chen, L. C., Gupta, S., Breuer, M. A.: A new framework for static timing analysis,
incremental timing analysis, and timing simulation, Proc. Asian Test Symposium, pp. 102-
107, 2000.
[8] Chen, L. C., Gupta, S. K., Breuer, M. A.: A new gate delay model for simultaneous
switching and its applications, Proc. Design Automation Conference, pp. 289 -294, 2001.
[9] Chen, L. C.: Timing oriented test generation for worst delay excitation, Dissertation
proposal, Dept. of EE-Systems, University of Southern California, Los Angeles, 2001.
[10] Chen, W.Y ., Breuer, M. A., Gupta, S.K.: Analytic delay for crosstalk delay and pulse
analysis for non-ideal inputs, Proc. Int’l Test Conference, pp. 809-818, 1997.
[11] Chen, W.-Y ., Gupta, S., Breuer, M. A.: Test generation in VLSI circuits for crosstalk
noise, Proc. Int’l. Test Conf., pp. 641-650, 1998.
[12] Chen, W.-Y ., Gupta, S., Breuer, M. A.: Test generation for crosstalk induced delay in
integrated circuits, Proc. Int’l. Test Conf., pp. 191-200, 1999.
[13] Chen, W.-Y .: Test generation for crosstalk noise in VLSI circuits, Ph.D. Dissertation,
Dept. of EE-Systems, University of Southern California, Los Angeles, CA 90089.
[14] Cheng, C.-K., Lillis, J., Lin, S., Chang, N.: Interconnect analysis and synthesis,
Wiley, 1999.
159
[15] Cheng, D. K.: Field and wave electromagnetics, Addison-Wesley Publishing Com-
pany, 1992.
[16] Cheng, K.-T., Dey, S., Rodgers, M., Roy, K.: Test challenges for deep sub-micron
technologies, Proc. Design Automation Conference, pp. 142-149, 2000.
[17] Cheng, K.-T., Krstic, A., Chen, H.-C.: Generation of high quality tests for robustly
untestable path delay faults, IEEE Trans. on Computers, vol. 45, no. 12, pp. 1379-1392,
1996.
[18] Cuviello, M., Dey. S., Bai, X., Zhao, Y .: Fault modeling and simulation for crosstalk
in system-on-chip interconnects”, Proc. Intl. Conf. Computer-Aided Design, pp. 297-303,
1999.
[19] Deutsch, A. et al: High speed signal propagation on lossy transmission lines, IBM
Journal of Research and Development, vol 34, no. 4, pp. 601-615, 1990.
[20] Deutsch, A. et al: Modeling and characterization of long interconnections for high
performance microprocessors, IBM Journal of Research and Development, vol 39, no. 5,
pp. 547-567, 1995.
[21] Deutsch, A. et al: When are transmission line effects important for on-chip intercon-
nections?, IEEE Transactions on Microwave Theory and Techniques, vol 45, no. 10, Octo-
ber, pp. 1836-1846, 1997.
[22] Devgan, A., Ji, H., Dai, W.: How to efficiently capture on-chip inductance effects:
introducing a new circuit element K, Proc. Int’l. Conf. on Computer-Aided Design, pp.
150-155, 2000.
[23] Feynman, R.P., Leighton, R.B., Sands, M.: The Feynman lectures on Physics, V ol II,
Addison-Wesley Publishing Company, 1964.
[24] Friedman, A. D., Menon, P.:Theory and design of switching circuits, Computer Sci-
ence Press, 1975.
[25] Fuchs, K., Fink, F. Schulz, M. H.: DYNAMITE: An efficient automatic test pattern
generation system for path delay faults, IEEE Trans. Computer-Aided Design, vol. 10, no.
10, pp. 1323-1335, 1991.
[26] Gupta, S., Breuer, M. A.: An adaptive validation technique for crosstalk, SRC report,
1999.
[27] Huang, I-D., Gupta, S.K., Breuer, M. A.: Efficient static timing analysis with
crosstalk, SRC report, 2002.
[28] IEEE standard delay format specification version 3.0, http://vhdl.org/vi/sdf.
160
[29] Ismail, Y .I., Friedman, E. G., Neves, J. L.: Figures of merit to characterize the impor-
tance of on-chip inductance, Proc. Design Automation Conference, pp. 560-565, 1998.
[30] Ismail, Y . I., Friedman, E.G.: Equivalent Elmore delay for RLC trees, IEEE Trans.
Computer-Aided Design, vol. 19, pp. 83-97, 2000.
[31] Ismail, Y .I., Friedman, E. G., Neves, J. L.:Repeater insertion in tree structured induc-
tive interconnect, IEEE Trans. Circuits Syst. II, vol. 48, pp. 471-481, 2001.
[32] Jha, N. K., Gupta, S. K.: Testing of digital systems, Cambridge University Press,
2003.
[33] Kahng, A.B., Muddu, S.: An analytical delay model for RLC interconnects, IEEE
Trans. on CAD of Integrated Circuits and Systems, vol. 16, no. 12, pp. 1507-1513, 1997.
[34] Kamon, M., Tsuk, T. J., White, J. K.: FASTHENRY: A multipole accelerated 3-D
inductance extraction program, IEEE Trans. on Microwave Theory and Techniques, vol.
42, no. 9, pp. 1750-1758, 1994.
[35] Kamon, M., Smithsiler, C., White, J. K.: FastHenry User’s Guide, Research Labora-
tory of Electronics, Dept. Of Electrical Engg. and Computer Science, Massachusetts Insti-
tute of Technology, 1996.
[36] Kang, S.: Metal-metal matrix (M
3
) for high-speed MOS VLSI layout, IEEE Trans.
Computer-Aided Design, vol CAD-6, pp. 886-891, 1997.
[37] Kraus, J. D.: Electromagnetics, McGraw-Hill, New York, 1991.
[38] Krauter, B., Mehrotra, S.: Layout based frequency dependent inductance and resis-
tance extraction for on-chip interconnect timing analysis, Proc. Design Automation Con-
ference, pp. 303-308, 1998.
[39] Krauter, B., Pileggi, L.: Generating sparse partial inductance matrices with guaran-
teed stability, Proc. Intl. Conf. on Computer-Aided Design, pp. 45-52, 1995.
[40] Krstic, A., Cheng, K.-T.: Delay fault testing for VLSI circuits, Kluwer Academic
Publishers, 1998.
[41] Kunz, W., Pradhan, D.: Recursive learning: a new implication technique for efficient
solutions to CAD problems: test, verification and optimization, IEEE Trans. on Computer-
Aided Design, vol. 13, no. 9, pp. 1143-1158, 1994.
[42] Kuo, B.C.: Automatic control systems, Prentice-Hall Inc, 1975.
[43] Lee, K. T., Nordquist, C. Abraham, J. A.: Automatic test pattern generation for
crosstalk glitches in digital circuits, Proc. VLSI Test Symposium, pp. 34-39, 1998.
161
[44] Lin, C.J., Reddy, S. M.: On delay fault testing in logic circuits, IEEE Trans. on Com-
puter-Aided Design, vol. 6, pp 694-703, 1987.
[45] Y . Liu, S. R. Nassif, L. T. Pileggi, A. J. Strojwas, “Impact of interconnect variations
on the clock skew of a gigahertz microprocessor,” in Proc. Design Automation Conf., pp.
168-171, 2000.
[46] Matick, R.E.: Transmission lines for digital and communication Networks, IEEE
Press, 1998.
[47] Moll, F., Roca, M. Marche, D., Rubio, A: Detectability of spurious signals with lim-
ited propagation in combinational circuits, IEEE Third Asian Test Symposium, pp. 175-
181, 1994.
[48] Moll, F., Roca, M., Rubio, A: Inductance in VLSI interconnection modeling, IEE
Proceedings of Circuits, Devices and Systems, vol. 145, no. 3, 1998.
[49] S. V . Morton, “On-chip inductance issues in multi-conductor systems,” in Proc.
Design Automation Conf., pp. 921-926, 1999.
[50] Naffziger, S.:Design methodologies for interconnect in GHZ+ ICs, Tutorial in Intl.
Solid-State Circuits Conference, 1999.
[51] Natarajan, S., Gupta, S. K., Breuer, M. A.:Process variations and their impact on cir-
cuit operation, Proc. Int’l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 73-
81, 1998.
[52] The National technology roadmap for semiconductors, Semiconductor Industry
Association, http://www.sematech.org, 1997.
[53] Nordholz, P. et al.: Signal integrity problems in deep submicron arising from inter-
connects between cores, Proc.VLSI Test Symposium, pp. 28-33, 1998.
[54] Pillage, L.T., Rohrer, R. A.: Asymptotic waveform evaluation for timing analysis,
IEEE Trans. on Computer-Aided Design, vol 9, no. 4, pp. 352-366, 1990.
[55] Priore, D. A.: Inductance on silicon for sub-micron CMOS VLSI, Proceedings of
IEEE Symposium VLSI Circuits, pp. 17-18, 1993.
[56] Process Parameters from MOSIS, http://www.mosis.org.
[57] Process Parameters from UMC, Taiwan, Confidential document.
[58] Rajski, J., Cox, H.: On necessary and nonconflicting assignments in algorithmic test
pattern generation, IEEE Trans. on Computer-Aided Design, vol. 13, pp. 515-530, 1994.
162
[59] Restle, P., Ruehli, A., Walker, S. G., Papadopoulos, G.: “Full-Wave PEEC time-
domain method for the modeling of on-chip interconnects”, IEEE Trans. on Computer-
Aided Design, vol. 20, pp. 877-887, 2001.
[60] Rubio, A., Itazaki, N., Xu, X., Kinoshita, K.: An approach to the analysis and detec-
tion of crosstalk faults in digital VLSI circuits, IEEE Trans. on Computer-Aided Design,
vol. 13, pp. 387-395, 1994.
[61] Ruehli, A. E.: Inductance calculations in a complex integrated Circuit environment,
IBM Journal of Research and Development, vol 16, no. 5, pp. 470-481, 1972.
[62] Sinha, A., Chowdhury, S.:Mesh structured on-chip power/ground: design for mini-
mum inductance and characterization for fast R, L extraction, Proc. of Custom Integrated
Circuits Conf., pp. 461-464, 1999.
[63] Sinha, A., Gupta, S.K., Breuer, M. A.: Validation and test generation for oscillatory
noise for VLSI interconnects, Proc. of Int’l. Conf. on Computer-Aided Design, pp. 289-
296, 1999.
[64] Sinha, A., Gupta, S.K., Breuer, M. A.: Validation and test generation for inductance
induced noise on VLSI interconnects, IEEE Workshop on Signal Propagation on Intercon-
nects, 2001.
[65] Sinha, A., Gupta, S.K.: Validation and test generation for crosstalk noise on multi-
point nets, TECHCON, 2000.
[66] Sinha, A. et al: Copper interconnects for high-speed, low power static memories,
Semiconductor Research Corporation Design Contest, 2000.
[67] Sinha, A., Gupta, S.K., Breuer, M. A.: Validation and test issues related to noise
induced by parasitic inductances of VLSI interconnects, IEEE Transactions on Advanced
Packaging, vol. 25, no. 3, pp 329- 339, 2002.
[68] Sinha, A., Gupta, S.K., Breuer, M. A.: Enhanced test generation for capacitive
crosstalk delay faults, Proc. of Asian Test Symposium, pp. 174-177, 2003.
[69] Shepard, K. L., Tian, Z.: Return-limited inductances: a practical approach to on-chip
inductance extraction”, IEEE Trans. Computer-Aided Design, vol. 19, pp. 425-435, 2000.
[70] Soden, J. M., Hawkins, C.F., Gulati, R.K., Mao, W.: Iddq testing: a review, Journal
of Electronic Testing: Theory and Applications, pp. 5-17, 1992.
[71] Sorkin, G.: Asymptotically perfect trivial global routing: A stochastic analysis, Proc.
IEEE Trans. on Computer Aided Design, vol. 6, pp. 820, 1987.
[72] Tang, K. T., Friedman, E. G.: Peak crosstalk noise estimation in CMOS VLSI cir-
cuits, Proc. IEEE Int’l Conf. on Electronics, Circuits and Systems, pp. 1539-1542, 1999.
163
[73] V oranantakul, S., Prince, J. L.: Efficient computation of signal propagation with
overshoot- and undershoot-control in VLSI interconnections, IEEE Trans. on Compo-
nents, Hybrids and Manufacturing Technology, vol. 16, no. 1, pp. 146-151, 1993.
[74] Yang, X., Ku, W.-H., Cheng, C.-K.: RLC interconnect delay estimation via moments
of amplitude and phase response, Proc. Intl. Conf. Computer-Aided Design, pp. 208-213,
1999.
[75] Weeks, W.T., Wu, L.L., McAllister, M.F., Singh, A.: Resistive and inductive skin
effect in rectangular conductors, IBM Journal of Research and Development, vol. 23, no.
6, pp. 652-660, 1979.
[76] Weste, N. H. E., Eshraghian, K.: Principles of CMOS VLSI design, 2nd Edition,
Addison-Wesley Publishing Company, 1992.
[77] Wheeler, H.A.: Formulas for skin effect, Proc. of the Institute of Radio Engineers,
vol 30, pp. 412-424, 1942.

Abstract (if available)

Abstract Advancements in integrated circuit technologies have made it possible to reduce physical dimensions of devices and interconnects, increase switching speeds of devices, and reduce power supply voltages. As a result, capacitance and inductance effects can create severe on-chip noise on VLSI interconnects. Noise such as crosstalk glitch and delay, overshoots, and undershoots, can lead to functional errors.

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Asset Metadata

Creator Sinha, Arani (author)

Core Title Test generation for capacitance and inductance induced noise on interconnects in VLSI logic

School Andrew and Erna Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Degree Conferral Date 2006-12

Publication Date 11/28/2006

Defense Date 07/28/2006

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag ATPG,crosstalk,inductance,interconnects,OAI-PMH Harvest,VLSI

Language English

Advisor Breuer, Melvin A. (committee chair), Alexander, Kenneth S. (committee member), Gupta, Sandeep K. (committee member)

Creator Email aranisinha@ieee.org

Permanent Link (DOI) https://doi.org/10.25549/usctheses-m194

Unique identifier UC1195328

Identifier etd-Sinha-20061128 (filename),usctheses-m40 (legacy collection record id),usctheses-c127-40950 (legacy record id),usctheses-m194 (legacy record id)

Legacy Identifier etd-Sinha-20061128.pdf

Dmrecord 40950

Document Type Dissertation

Rights Sinha, Arani

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Repository Name Libraries, University of Southern California

Repository Location Los Angeles, California

Repository Email cisadmin@lib.usc.edu