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University of Southern California Dissertations and Theses
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Bidirectional neural interfaces for neuroprosthetics
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Bidirectional neural interfaces for neuroprosthetics
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Bidirectional Neural Interfaces for Neuroprosthetics by Aria Samiei A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2022 Copyright 2022 Aria Samiei Acknowledgements I would like to thank my PhD advisor, Professor Hossein Hashemi, for his mentorship and support. I would also like to thank my qualifying examination and dissertation committee members Professors Ellis Meng, Dong Song, Mike Shuo-Wei Chen, Eun Sok Kim, Con- stantine Sideris and Dr. Manuel Monge. I am especially grateful for the collaboration opportunity provided by Professors Dong Song, Ellis Meng, and their research laboratory members especially Wenxuan Jiang, James Yoo, Huijing Xu, Xuechun Wang and Eugene Yoon. I would like to extend my gratitude to my former and current labmates, whom I had the privilege to work with, especially Masashi Yamagata, Samer Idres, Pingyue Song and Vinay Chenna. I am very grateful for the support of my family especially my parents and parents-in-law. Finally, I dedicate this dissertation to my wife, Sepideh, who gave me unconditional support and love during this long journey. ii Table of Contents Acknowledgements ii List of Tables vi List of Figures vii Abstract xix Chapter 1: Introduction 1 Chapter 2: Neural Recording and Stimulation Integrated Circuits 6 2.1 Electrode-Tissue Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Recording System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.3 Implementations of Neural Recording Channels . . . . . . . . . . . . 15 2.2.3.1 OTA-based Amplifier with Capacitive-Feedback . . . . . . . 15 2.2.3.2 Front-end Oversampling ADCs . . . . . . . . . . . . . . . . 17 2.2.3.3 Multi-Channel Neural Recording System Architectures . . . 18 2.3 Stimulation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.1 Multi-Channel Neural Stimulation Architecture . . . . . . . . . . . . 26 Chapter 3: Stimulation Artifact 29 Chapter 4: Stimulation Artifact Canellation with Adaptive IIR Filters 40 4.1 Modeling the Stimulation Artifact . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 System-Level Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3.2 Recording Channel Circuitry . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.3 Operation of the AFE with the Adaptive IIR Filter . . . . . . . . . . 56 4.3.3.1 Learning (Training) Phase . . . . . . . . . . . . . . . . . . . 56 4.3.3.2 Acquisition Phase . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.4 Clock Generation and Timing Circuitry . . . . . . . . . . . . . . . . . 63 4.3.5 ESD Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . 63 iii 4.3.6 Test Chip and PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.1 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.2 AFE measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.3 ADC measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.4 Stimulation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.4.5 Stimulation Artifact Canceler Performance . . . . . . . . . . . . . . . 78 4.4.5.1 Single Channel Stimulation . . . . . . . . . . . . . . . . . . 78 4.4.5.2 Dual Channel Stimulation . . . . . . . . . . . . . . . . . . . 87 4.4.5.3 In Vitro Measurements . . . . . . . . . . . . . . . . . . . . 88 4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Chapter 5: Multi-Point Stimulation Artifact Cancellation 98 5.1 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.1.1 Two-Point Artifact Cancellation . . . . . . . . . . . . . . . . . . . . . 103 5.1.2 SAR-based Artifact Estimation Algorithm . . . . . . . . . . . . . . . 104 5.1.2.1 First-Point Artifact Estimation and Cancellation . . . . . . 109 5.1.2.2 Second-Point Artifact Estimation and Cancellation . . . . . 110 5.1.3 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.1.3.1 LNA Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.1.3.2 Switched-Capacitor LPF . . . . . . . . . . . . . . . . . . . . 115 5.1.3.3 PGA and Voltage Buffer . . . . . . . . . . . . . . . . . . . . 118 5.1.3.4 Buffer Offset Calibration . . . . . . . . . . . . . . . . . . . . 121 5.1.3.5 Switched-Capacitor PGA Circuitry . . . . . . . . . . . . . . 125 5.1.3.6 Capacitive DACs and SAR ADC . . . . . . . . . . . . . . . 132 5.1.3.7 Artifact Estimation Digital Circuitry . . . . . . . . . . . . . 136 5.1.3.8 Stimulation Circuitry. . . . . . . . . . . . . . . . . . . . . . 139 5.1.3.9 Chip Programming, Data Transmission, and Test Plan . . . 142 5.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.2.1 Recording channel characterization . . . . . . . . . . . . . . . . . . . 148 5.2.2 Characterization of the Two-Point Stimulation Artifact Canceler . . . 153 5.2.3 Two-Chip Stimulation Artifact Cancellation . . . . . . . . . . . . . . 158 5.2.4 In Vitro Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.2.4.1 Same-electrode Simultaneous Recording and Stimulation . . 164 5.2.5 In Vivo Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.2.6 Powerline Noise Interference and Mitigation . . . . . . . . . . . . . . 169 5.3 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Chapter 6: Conclusion and Future Work 175 References 177 Appendix A Neural Stimulator with Dynamic Supply Voltage Modulation . . . . . . . . . . . . 188 iv Appendix B Chopper-Stabilized Neural Recording Amplifier . . . . . . . . . . . . . . . . . . . 199 B.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 B.2 System Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 B.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 B.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 B.4.1 Linearity Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 B.4.2 Noise Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 B.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Appendix C Future Direction: Scalable Bidirectional Interfaces . . . . . . . . . . . . . . . . . . 215 C.1 Case Study 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 C.2 Case Study 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 C.3 Proposed Current-Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . 221 C.4 Limitations and Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 v List of Tables 2.1 Typical Specifications for A Neural Recording System . . . . . . . . . . . . . 28 2.2 Typical Specifications for A Neural Stimulation System . . . . . . . . . . . . 28 3.1 Qualitativecomparisonofdifferentstimulationartifactcancellation/mitigation techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1 Performance Summary and Comparison with the State-of-the-art Bidirec- tional Neural Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1 Performance Summary and Comparison with the State-of-the-art Bidirec- tional Neural Interfaces Resilient to Artifact . . . . . . . . . . . . . . . . . . 172 B.1 Simulated and calculated coefficients for the CFA and RCF amplifiers.. . . . 210 B.2 Noise contribution of R int and G m3 in the 1− 200Hz frequency band . . . . . 212 B.3 Performance Summary and Comparison with State-of-the-art Bio-potential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 C.1 Target Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 vi List of Figures 1.1 Stimulation and recording electrodes interfacing neural population. . . . . . 2 1.2 Advances in neural recording during the past half a century. . . . . . . . . . 3 1.3 An example of a peripheral nerve prosthetics: A closed-loop brain-computer interface to control a robotic arm. . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 A conceptual diagram of a brain prosthesis which mimics the functionality of the damaged brain tissue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Conceptual block diagram of an implantable neural interface system. STM: stimulator, AMP: amplifier, WG: waveform generator, Tx: transmitter, Rx: receiver, PMU:powermanagementunit, OSC:oscillatorandclockgeneration circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 The electrode-tissue interface and its first-order and higher order models. . . 8 2.3 Simplified block diagram of a conventional neural recording system. . . . . . 9 2.4 (a) A high-pass filtered recording of the hippocampus in a rat’s brain (b) An isolated spike waveform (c) A 1-minute recording showing the local field potential. This data was recorded in collaboration with Dr. Dong Song’s laboratory at the University of Southern California. . . . . . . . . . . . . . . 10 2.5 Signal and noise flow diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Effect of sampling on a low-pass filtered white noise. . . . . . . . . . . . . . 12 2.7 Noise model of the recording system including the effect of noise aliasing. . . 12 2.8 Serialdatatransmission. Thereceiverinthisexampleisafield-programmable gate array (FPGA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.9 LNA and PGA implementation as OTA-based amplifiers with capacitive- feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 Simplified amplifier circuitry for noise calculations. . . . . . . . . . . . . . . 16 2.11 Concept of the chopping technique. . . . . . . . . . . . . . . . . . . . . . . . 17 vii 2.12 (a) Block diagram of a first-order ∆Σ ADC (b) Example of a CT-∆Σ. . . . . 19 2.13 Frequency shaping techniques (a) Front-end differentiation followed by back- end integration, (b) ∆-modulation and demodulation. . . . . . . . . . . . . . 20 2.14 Neural recording multiplexing techniques (a) Digital multiplexing after the ADC, (b) Analog multiplexing before the ADC. . . . . . . . . . . . . . . . . 21 2.15 Concept of electrical neural stimulation. . . . . . . . . . . . . . . . . . . . . 22 2.16 Strength-duration curves for two different neurons. . . . . . . . . . . . . . . 22 2.17 Switched-capacitor stimulation. . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.18 Voltage-mode stimulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.19 (a) Current-mode stimulation. (b) Timing diagram for biphasic stimulation. (c) Possible timing scenarios.. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.20 Time-multiplexed multi-channel stimulation. . . . . . . . . . . . . . . . . . . 27 2.21 Multidimensionaldesignspaceofabidirectionalneuralinterface. Thespecific contribution of my previously designed chips are highlighted [DR: dynamic range,Z in : inputimpedance,Z elec : electrodeimpedance,THD:totalharmonic distortion, CMRR: common-mode rejection ratio, BW: bandwidth]. . . . . . 27 3.1 (a) Conceptual diagram of a bidirectional neural interface. (b) Stimulation artifactinterfereswiththeneuralsignal. (c)Possibleartifact-couplingpathways. 30 3.2 Recording of (a) a neural signal and (b) a neural signal contaminated with stimulation artifact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 Typical cancellation points for stimulation artifact. . . . . . . . . . . . . . . 32 3.4 Back-end stimulation artifact cancellation. . . . . . . . . . . . . . . . . . . . 32 3.5 Stimulation artifact front-end mitigation techniques. (a) Artifact blanking. (b) High resolution ADCs. (c) Delta-modulated front-ends. (d) Front-end adaptive filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 DC leakage current due to artifact blanking. . . . . . . . . . . . . . . . . . . 35 3.7 Stimulation-side artifact cancellation. (a) Without cancellation. (b) With the dipole cancellation. Contour lines enclose the region where the artifact saturates the recording channels. . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1 (a) Artifact measurement test bench and proposed RC model (geometrical details of the electrode can be found in [79]). (b) RC model output displayed with the measured stimulation and artifact voltages. (c) Fitted RC model parameters. (d) Stimulation artifact waveform and filter response. . . . . . . 41 viii 4.2 Block diagram and comparison of the FIR [73] and the proposed IIR cancel- lation filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 (a) Simplified block diagram of the front-end configuration. (b) Differential- mode artifact cancellation at the LNA input and common-mode limitation (V CMST : body bias voltage). . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4 Noise and dynamic range analysis. (a) Signal flow diagram of the artifact, desired signal and noise. (b) Effect of the front-end (FE) cancellation on the dynamic range (DR). (c) Required DR for the recording system. . . . . . . . 45 4.5 Neural interface SoC block diagram.. . . . . . . . . . . . . . . . . . . . . . . 49 4.6 Detailed circuitry of the AFE. (a) LNA and CDAC configuration (b) PGA (c) ADC driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.7 CMFB circuitry for LNA (a) first stage and (b) second stage.. . . . . . . . . 52 4.8 (a) SAR ADC schematic. (b) Simulated SAR operation for one sample. . . . 54 4.9 ADC data serializer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.10 (a) Comparator schematic. (b) Test input and output waveforms to simulate the comparator offset. (c) Histogram of the offsets (Monte-Carlo simulation). 55 4.11 (a) Digital level-shifter schematic. (b) Functionality across process corners [ss: slow-slow, tt: typical-typical, ff: fast-fast (NMOS-PMOS), sch: schematic]. 57 4.12 Front-end IIR LMS filter principle of operation. (a) Learning phase. (b) Acquisition phase. The disabled blocks are shown in a light gray color. . . . 60 4.13 Simulationoftheadaptiveartifactcanceler(a)Input-referredresidualartifact voltage. (b) The LNA output voltage.. . . . . . . . . . . . . . . . . . . . . . 61 4.14 Simulation of the adaptive artifact canceler to recover a neural signal (a) Stimulation current and artifact voltage. (b) Injected neural signal to the input. (c) Recording output when the canceler is OFF. (d) Recording output when the canceler is ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.15 (a)Digitalrelaxationoscillator. (b)Waveformoftheoscillatorinternalnodes. (c) Oscillator startup as the supply voltage ramps up for different frequency settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.16 Timing generation circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.17 ESD protection circuitry strategy for analog and digital I/O pins. . . . . . . 65 4.18 Test chip (a) micrograph and (b) block diagram. . . . . . . . . . . . . . . . . 66 4.19 (a) Schematic of the SSF and buffer. (b) Simulated AC response of the AFE+SSF+buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ix 4.20 SoC microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.21 PCB carrying the test and main chips. . . . . . . . . . . . . . . . . . . . . . 69 4.22 (a) Chip total power consumption breakdown. (b) Supply voltage currents in different operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.23 (a) Test bench for noise and differential-mode gain measurements. (b) Raw transient output of the amplifier in response to a 10kHz input signal. . . . . 70 4.24 (a) AFE frequency response. (b) AFE input-referred noise for the maximum gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.25 Common-mode (CM), differential-mode (DM) and CM-to-DM transfer func- tions (simulated and measured). . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.26 (a) LNA schematic with parasitic capacitors at the virtual ground. (b) Par- asitic capacitance extraction of the layout. (c) CM-to-DM conversion gain of the schematic (sch), parasitic-extracted (pex) and schematic with added parasitic capacitors (sch+C par ). . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.27 Simplified model of the LNA for CMRR analysis. . . . . . . . . . . . . . . . 73 4.28 (a) Test bench for ADC characterization. Fourier transform of the ADC output under (b) non-coherent sampling and (c) coherent sampling. . . . . . 76 4.29 ADC output spectrum across different input frequencies. . . . . . . . . . . . 77 4.30 Simulated and measured SNDR and ENOB for (a) f s = 19.53kHz, V REF =1V, (b) f s = 78.12kHz, V REF =3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.31 (a) Binary-weighted current DAC. (b) The variability of the output current versus the load voltage. (c) Current waveform programmability. . . . . . . . 79 4.32 Characterizationofbothstimulatorsonthechip(a)Outputcurrentvs. input code. (b) DNL/INL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.33 Different modes of stimulation artifact coupling into the amplifier input (a) Differential (b) Common-mode (c) Single-ended. The off-chip circuitry that generates each mode is also included. . . . . . . . . . . . . . . . . . . . . . . 80 4.34 (a) Measurement setup for testing the performance of the artifact canceler. (b)Off-chipvoltagesummationcircuitry. (c)Timingdiagramofthesuccessive operation cycles and phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 x 4.35 (a) Stimulation artifact. (b) Single-tone input signal. (c) Residual artifact waveform recorded during Φ acq1 . (d) Recorded signal contaminated with the residual artifact during Φ acq2 . (e) The recovered amplified input signal (The timewindowthattheFFTisperformedonisshownwitharedrectangle). (f) Frequency spectrum of the recovered signal. The FFT of the recorded signal in the absence of the stimulation signal is also plotted. The representative waveforms are shown for channel 0. . . . . . . . . . . . . . . . . . . . . . . . 83 4.36 (a)Effectivegainand(b)SNRasafunctionoftheinputartifactpeak-to-peak voltage, measured for single-ended, differential and common-mode artifact waveforms. The error-bars show± 1σ variation across the 8 recording channels. 85 4.37 Effect of the canceler on the amplifier recovery time from saturation due to a 2.5 V pp artifact (a) Recorded signal contaminated with the residual arti- fact (Sliding time windows are labeled as A-D). (b) Recovered signal. (c) Frequency spectrum of the recovered signal in different time windows. (d) Effective gain and (e) SNR measured in different time windows following the stimulation event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.38 Dependence of the IIR filter coefficients on the stimulation signal parameters. (a) Amplitude (b) Duty cycle (c) Pulse width. . . . . . . . . . . . . . . . . . 87 4.39 Test bench for measuring the cancellation performance in the presence of 2 overlapping stimulation signals. . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.40 (a) Stimulation currents shown on top of the resultant artifact waveform. (b) The recovered amplified input signal (shown for channel 0). (c) Frequency spectrum of the recovered signal. (d) Effective gain and SNR measurement of the recovered signal across different channels. . . . . . . . . . . . . . . . . . 89 4.41 Invitro measurementsetupfortestingtheperformanceoftheartifactcanceler in1xPBS.Theac-couplingcapacitanceC ac =220nFpreventsanyDCleakage currentthroughtheelectrodes,whichcanpotentiallydeterioratetheelectrode performance or even result in its failure. 2 microelectrode arrays were used in this testbench to investigate the artifact coupling in different configurations. 90 4.42 Photograph of the in vitro test in PBS. . . . . . . . . . . . . . . . . . . . . . 91 4.43 Performance of the canceler on a single-tone signal in vitro. (a) Stimulation artifact waveform, recovered signal and its frequency spectrum cross different channels. (b) Effective gain and (c) SNR across different channels. The input artifact amplitude is also shown for each electrode. . . . . . . . . . . . . . . 92 xi 4.44 Performance of the canceler on a pre-recorded neural signal in vitro. (a) The neuralsignalgeneratedbyafunctiongenerator. Thetimingofthestimulation current is also shown. (b) Recovered signal across different channels in 3 conditions: stimulation OFF, stimulation ON + canceler OFF, stimulation ON + canceler ON. The test bench and the artifact levels are the same as the in vitro single-tone test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.45 Scalability of the IIR filter output in response to stimulation with different parameters in vitro. (a) Stimulation current and artifact during training and acquisition. (b) Recovered signal in 3 conditions: canceler OFF, canceler ON + filter retraining, canceler ON + coefficient scaling. The FFT window is highlighted with a shadow. (c) Frequency spectrum of the recovered signal. (d) Performance summary of the artifact cancellation scheme. The represen- tative plots are from channel 0. . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.1 Conceptual diagram of (a) one-point and (b) two-point artifact suppression techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2 Concept of artifact waveform storage and cancellation. . . . . . . . . . . . . 99 5.3 (a) Direct quantization of the artifact. (b) Nonidealities added to the system. Red dotted lines are active only during artifact estimation. . . . . . . . . . . 101 5.4 (a) Closed-loop artifact quantization. (b) Nonidealities added to the system. Red dotted lines are active only during artifact estimation. . . . . . . . . . . 102 5.5 Conceptual block diagram of the proposed two-point stimulation artifact can- cellation technique. The gray components are active only during artifact es- timation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.6 Simplified block diagram of the implemented 4-channel bidirectional inter- face with two-point artifact cancellation scheme (PGA: programmable gain amplifier, BUF: buffer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.7 (a) SAR-based artifact estimation algorithm. (b) An example of the SAR operation to quantize an artifact sample. . . . . . . . . . . . . . . . . . . . . 105 5.8 LNA model during the artifact estimation and cancellation.. . . . . . . . . . 106 5.9 The effect of DC removal on the artifact waveform and the length of the artifact estimation required for sufficient cancellation. . . . . . . . . . . . . . 107 5.10 (a) Stimulation current scaled down during artifact estimation. (b) Stimula- tion current scaled up to the desired value during the normal operation. . . . 109 5.11 ProblemofCMstimulationartifactremainsunresolvedinthepresenceofDM artifact cancellation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 xii 5.12 Reconfiguration of the front-end for (a) CM artifact estimation and (b) DM artifact estimation. The light gray lines/blocks are inactive. . . . . . . . . . 111 5.13 Implementation ofthe SAR-based artifact estimation algorithm at thesecond cancellation point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.14 Complete chip block diagram (single-ended view is shown for simplicity). . . 113 5.15 (a)Capacitorvaluesandpowerconsumptionbreakdown. (b)Timingdiagram of all the clock phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.16 Simulated sequential operation of the two-point estimation and cancellation algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.17 LNA schematic (i= 1,2,3,4 is the channel number). . . . . . . . . . . . . . . 116 5.18 Resistive ladder to control the high-pass corner. . . . . . . . . . . . . . . . . 117 5.19 (a) SC-LPF circuitry. (b) The schematic of the transmission gate switches and their control circuitry. (c) Non-overlapping clock generation circuitry. . . 118 5.20 (a) SC-LPF AC response. (b) SC-LPF transient response. (c) Simulated switch resistance across different input voltages. . . . . . . . . . . . . . . . . 119 5.21 PGA schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.22 Schematic of g m3 used in the unity-gain voltage buffer. . . . . . . . . . . . . 121 5.23 (a) Concept of offset calibration in a unity gain buffer. (b) Offset calibration in a differential circuitry and (c) Simulated SAR-based calibration algorithm. 122 5.24 Monte-Carlosimulationofthebufferoffset(a)beforecalibrationand(b)after calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.25 Theimplementationofthebufferoffsetcalibrationina4-channeltime-multiplexed system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.26 Monte-Carlo simulations of the amplifier chain output (a) before calibration and (b) after calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.27 (a) SC-PGA with correlated double sampling. Amplifier configuration in phase (b) Φ 1 and (c) Φ 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.28 (a) Schematic of the OTA used in the SC-PGA. Dependence of the (b) OTA intrinsic gain and (b) Slew rate on the I 1 I 0 ratio. . . . . . . . . . . . . . . . . 129 5.29 (a)ImplementationoftheSC-PGA1. (b)Timingdiagramoftheclockphases to control the switch configurations. . . . . . . . . . . . . . . . . . . . . . . . 131 5.30 (a) Schematic of the SC-PGA 1 OTA (g m4 ). . . . . . . . . . . . . . . . . . . 132 xiii 5.31 Stability of the (a) differential SC-PGA 1 and (b) CMFB circuitry. . . . . . 133 5.32 Implementation of the SC-PGA 2. . . . . . . . . . . . . . . . . . . . . . . . . 134 5.33 (a) Schematic of the SC-PGA 2 OTA (g m5 ). . . . . . . . . . . . . . . . . . . 135 5.34 Transient simulation of the full 4-channel recording chain with different gain settings per channel for the SC-PGAs 1 and 2. The waveforms are demulti- plexed at the output of the SC-PGA 2. G1 and G2 show the gain setting of SC-PGAs 1 and 2 respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.35 Schematic of (a) CDAC 1 and (b) CADC 2. . . . . . . . . . . . . . . . . . . 136 5.36 Dynamicperformanceat10kHz, full-scaleoutput(a)CDAC1and(b)CADC 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.37 (a) Schematic of the SAR ADC. (b) Detailed schematic of the buffer and the calibration current DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.38 Dynamicperformanceoftheparasitic-extractedSARADC(a)beforecalibra- tion and (b) after calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.39 Circuitry of the SAR logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.40 Architecture of the memory blocks and data access during the artifact can- cellation phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.41 Memory unit cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.42 Stimulation circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.43 Schematic of the OTAs used in the stimulator (a) g mp (b) g mn . . . . . . . . . 142 5.44 Simulation of (a) stimulator output impedance and (b) charge balancing. . . 143 5.45 Programming strategy of the implemented bidirectional chip. . . . . . . . . . 144 5.46 (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.47 (a) Modifications to the recording chain for in-situ testability. (b) Schematic of the OTA in the output buffer.. . . . . . . . . . . . . . . . . . . . . . . . . 146 5.48 Customized serial data transmission protocol. . . . . . . . . . . . . . . . . . 147 5.49 Die micrograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.50 (a) Test bench block diagram. (b) PCB top view. . . . . . . . . . . . . . . . 149 5.51 Measured serial data and clock output. The data packets were deserialized and demultiplexed into 4 channels in MATLAB offline. . . . . . . . . . . . . 150 xiv 5.52 Direct measurement of the SC-PGA 2 differential output (all the inputs are grounded), before and after the offset auto-calibration. . . . . . . . . . . . . 151 5.53 (a) ADC output before and after calibration. (b) Residual offset referred to the SC-PGA 1 input (voltage buffer output). . . . . . . . . . . . . . . . . . . 152 5.54 Differential-mode gain measurement test bench and output spectrum. . . . . 153 5.55 Common-mode gain measurement test bench and output spectrum. . . . . . 154 5.56 Performanceofthefullrecordingchain(a)ACresponseand(b)input-referred noise spectral density at the maximum gain setting. (c) Linearity measurement.155 5.57 Tunability of the AFE AC response. Three measured examples of different (a) gain settings and (b) high-pass corners are shown. . . . . . . . . . . . . . 156 5.58 Crosstalkmeasurements(a)Testsetup,(b)Leakagefromchannel1tochannel 2 at different input levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.59 Different testing modes of artifact coupling to the recording channels. . . . . 157 5.60 400-mV pp input CM artifact measured at the SC-PGA 2 output. . . . . . . . 158 5.61 Performance of the cancellation circuitry (a) 400-mV pp CM artifact and (b) 800-mV pp DM artifact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.62 (a) Test bench for 1kHz signal amplification in the presence of a CM artifact. (b) ADC output, before and after artifact cancellation. . . . . . . . . . . . . 160 5.63 ADC output and its Fourier transform: 1kHz signal added to (a) 400-mV pp CM artifact, (b) 800-mV pp DM artifact. . . . . . . . . . . . . . . . . . . . . 161 5.64 Summary of the two-pint artifact cancellation performance in recovering a 1kHz signal contaminated with different magnitudes of CM, DM or SE artifact.161 5.65 Chip-to-chip Stimulation artifact coupling in a multi-chip implementation. . 162 5.66 Test bench to quantify cancellation of the artifact coupled from chip 1 to chip 2.162 5.67 Performanceofthecancelerinrecoveringsignalfromstimulationartifactgen- erated by another chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.68 (a) In vitro testbenchforcharacterizingthecancellationperformance. Apre- recorded neural spike is periodically applied to the solution. (b) ADC output showing the recorded waveform in the absence of stimulation. . . . . . . . . 164 5.69 (a) The chip cancels the contaminating stimulation artifact and recovers the underlying signal in vitro. For comparison, the chip recording output in the absence of stimulation is also plotted. . . . . . . . . . . . . . . . . . . . . . . 165 xv 5.70 (a) Test configuration for simultaneous stimulation and recording from the same electrode in vitro. (b) Stimulation artifact cancellation. . . . . . . . . . 166 5.71 (a) In vivo test configuration for simultaneous stimulation and recording in a rat’s brain. Recorded signal baseline from the (b) anesthetized and (c) euthanized rat. The amplitudes are input-referred.. . . . . . . . . . . . . . . 167 5.72 In vivo simultaneous stimulation and recording. The figures show the voltage of the recording and reference electrodes, and the recorded ADC output in the absence or presence of the artifact cancellation circuitry for stimulation current intensity of (a) 122 µ A and (b) 64 µ A. . . . . . . . . . . . . . . . . . 168 5.73 Test bench to investigate and mitigate the powerline noise(a) Powerline noise at the ADC output when the source impedance is high (e.g. 1 MΩ). (b) Lowering the source impedance by using a voltage buffer suppresses the 60Hz noise. (c) Modeling the 60Hz noise coupling to the recording system. . . . . 171 5.74 Scaling up the two-point cancellation scheme to a system with N recording and stimulation channels.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.75 Time-sharingbothstagesofatwo-pointartifactcancellationschemetoreduce chip area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 A.1 Block diagram of the neural stimulator. . . . . . . . . . . . . . . . . . . . . . 189 A.2 Conversion ratio decision circuitry (shown for the anodic phase). . . . . . . . 190 A.3 (a)Relaxationoscillatorschematic. (b)Regenerationoscillatorschematic. (c) Performance summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 A.4 CurrentDACschematic. (a)PMOSandNMOSDACschematic,(b)Measured static linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 A.5 Bandgap voltage and reference current generation circuitry.. . . . . . . . . . 193 A.6 Reconfigurable switched-capacitor DC-DC converter. . . . . . . . . . . . . . 194 A.7 DC-DC converter configuration for different conversion ratios. . . . . . . . . 195 A.8 DC-DC converter configuration for different conversion ratios. . . . . . . . . 196 A.9 Chip microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 A.10Test PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 A.11(a) Measured energy efficiency versus the load current. (b) Measured versus simulated DC-DC converter output. . . . . . . . . . . . . . . . . . . . . . . . 197 A.12Representative measured output voltage waveforms and corresponding mod- ulated supply voltage. (a) Pure resistive load and (b) Platinum electrode. . . 198 xvi B.1 Boosting the input impedance of chopping amplifiers: (a) Prior art: positive feedback added to a capacitive feedback chopping amplifier, (b) Prior art: feed-forward axillary path added to the input of a capacitive feedback chop- pingamplifier,(c)Proposedscheme: feed-forwardauxiliarypathaddedtothe input of a current feedback chopping amplifier. . . . . . . . . . . . . . . . . . 200 B.2 Complete implementation of the chopper stabilized current feedback amplifier.201 B.3 Detailed schematic of the front-end trans-conductance amplifier: (a) G m1 along with the feedback trans-conductance amplifier G mf and the DC servo loopfeedbacktrans-conductanceamplifierG m4 ,(b)CMFBamplifierschematic, differential and common-mode transfer functions of G m1 . . . . . . . . . . . . 202 B.4 Simplified block diagram and stability analysis. . . . . . . . . . . . . . . . . 204 B.5 Core 1MHz oscillator schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 205 B.6 Die micrograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 B.7 Test bench for input impedance measurement. . . . . . . . . . . . . . . . . . 207 B.8 Measured transfer functions: (a) voltage gain with different settings, (b) voltage gain variation as a function of the input offset voltage, (c) input impedance, (d) input referred noise. . . . . . . . . . . . . . . . . . . . . . . . 208 B.9 Simplified schematic of the CFA for linearity analysis. . . . . . . . . . . . . . 208 B.10 Simplified schematic of a regular capacitive-feedback (RCF) amplifier. . . . . 209 B.11 (a) Simplified block diagram of the chopper amplifier for noise analysis and (b) the schematic of G m3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 B.12 Input-referred noise spectral density derived from simulation and analysis. . 212 C.1 Acute murine brain recording test bench and a conceptual diagram of simul- taneous recording configuration from across the brain. . . . . . . . . . . . . . 216 C.2 The Neuropixels: Conventional signal conditioning and quantization approach.217 C.3 Crosstalk issue (a) Geometry of 2 adjacent traces on a probe. (b) Simplified model of the impedances involved in crosstalk. (c) Estimated model parame- ters at 1kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 C.4 Possible configurations of chronic neural interface implants. (a) Single chip (b) Dual chip with front-end amplification, voltage multiplexing and delivery (c) Dual chip with the proposed sensing array front-end. The microelectrode arrays can be depth or surface electrodes. . . . . . . . . . . . . . . . . . . . . 219 C.5 The Argo system architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . 220 xvii C.6 (a) Conventional recording AFE front-end (b) Proposed voltage-to-current conversion sensor array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 C.7 Multiplexing clock Φ 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 C.8 Output voltage waveforms in the conventional and proposed scheme.. . . . . 223 C.9 Output voltage waveforms in the conventional scheme with 2 different buffer driving capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 C.10 Block diagram of the proposed architecture (top) and a possible implemen- tation as an active probe (bottom). Inside the pixels, block D represents the digital circuitry for timing and the x10 is the front-end amplification (M: shank count). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 C.11 Proposedneuralrecordingplatformusingthecurrent-multiplexedsensorarray and the back-end receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 C.12 Simulation test bench for the proposed current-multiplexed AFE. . . . . . . 227 C.13 Input and output voltage waveforms in the system for channels 1 to 4 (a) Input. (b) Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 xviii Abstract Closed-loop brain-machine interfaces have become critical components in neuroscience re- search and clinical applications. These systems record the neural activity, perform signal processing algorithms, and generate a specific spatiotemporal pattern to stimulate the neu- rons in the brain. Unfortunately, stimulation of the brain tissue introduces an artifact at the recording channels, which can significantly degrade the received signal quality. This dissertation introduces two approaches to mitigate the stimulation artifact. One approach is a front-end (FE) cancellation scheme that incorporates a least-mean squares (LMS) engine that adapts the coefficients of a two-tap infinite-impulse-response (IIR) filter to replicate the stimulation artifact waveform and subtract it at the FE. Measurements demonstrate the efficacy of the canceler in mitigating artifacts up to 700 mV pp and reducing the FE amplifier saturation recovery time in response to a 2.5-V pp artifact. Each recording channel houses a pair of adaptive IIR filters, which enables the cancellation of the artifacts generated by the simultaneous operation of the two on-chip stimulators. The analog FE consumes 2.5 µ W of power per channel and has a maximum gain of 50 dB and a bandwidth of 9.0 kHz with 6.2- µ V rms integrated input-referred noise. The existing FE cancellation techniques provide a limited artifact suppression (< 40dB) which reduces a 1000 mV pp artifact to about 10 mV pp swing. This residual artifact is still 1-2 orders of magnitude larger than the neural spikes and local field potentials, which can potentially saturate the amplifiers. The second proposed approach is a multi-channel neural interface with a two-point stimulation artifact cancellation technique which boosts xix thecommon-modeanddifferential-modestimulationartifactsuppressionto68.5dBand58.1 dB, while handling artifacts as large as 1200 mV pp and 700 mV pp , respectively. xx Chapter 1 Introduction Ourbrainisacomplexensembleofneuronsandglialcells,whichworkcloselytomaintainthe healthystateofthebrain. Ourexperienceandinteractionwiththesurroundingenvironment are processed and perceived via a network of chemical and electrical activities among the 100B neurons that reside in the brain. Neurons receive signals via dendrites which are branches projected out of the cell body or soma as shown in Fig. 1.1. If the summation of thesignalsthatthedendritesreceiveandtransfertothesomapassesacertainthreshold, the neurons generate fast voltage impulses, called spikes (also referred to as action potentials or AP). The action potentials are carried along the axons and are relayed by neurotransmitters at the neuron-neuron junctions (synapse), as shown in Fig. 1.1. Thanks to the advances in electrophysiology in the past century, neuroscientists have been able to study the neuronal mechanisms underlying learning, memory formation and complex behavioral tasks. In such studies, metallic electrodes are used as tiny voltage sensors in the proximity of the target neurons to measure the extracellular potential. To modulate or perturb the neural activity, a stimulation electrode can be used to apply a certain current or voltage into the tissue to excite nearby neurons, as demonstrated in Fig. 1.1. Up to the mid 20th century, these studies were limited to a few hours of recording from singleneuronsinthebrain,mostlyinanesthetizedanimals [1]. Inanefforttostudythebrain in its conscience state, during the late 1950’s, 4-6 stainless steel microwires were implanted in squirrels’ brains and single unit spikes were recorded for a duration of several days in 1 Figure 1.1: Stimulation and recording electrodes interfacing neural population. the unanesthetized animals [2]. In the 1980’s and 90’s, stereotrodes [3], [4] tetrodes, silicon-based 3-dimensional microelectrode arrays (Utah array [5]) and planar microprobes (Michigan probes [6]) were developed that could enable recording and isolating single-unit activities in larger groups of neurons. The Utah array with 96 recording sites remains the only implantable neural probes approved by the US Food and Drug Administration (FDA) that has been used for chronic human studies [7]. Nonetheless, in a rigorous effort to understand the neuronal circuitry in the brain, researchers have doubled the simultaneously interrogated neurons in almost every 7 years, as shown in Fig. 1.2 1 . During this journey, collaboration of engineers, neuroscientists and physicians have cul- minated in brain-computer interfaces (BCI), also known as brain-machine interfaces (BMI), which can benefit quadriplegic individuals or patients with amputated limbs. As shown in Fig. 1.3, an array of recording electrodes sends the sensed neural activity from the motor cortexor the spinalcord toa back-end processor todecode theneural signals. Subsequently, the processor sends control commands to a robotic limb to perform the intended task by the user [8]. To provide feedback to the user (such as the tactile sensation [9]), the signals from 1 Raw data available at https://stevenson.lab.uconn.edu/scaling/ 2 Figure 1.2: Advances in neural recording during the past half a century. Figure 1.3: An example of a peripheral nerve prosthetics: A closed-loop brain-computer interface to control a robotic arm. the sensors on the fingertips are encoded into a stimulation pattern applied to the sensory area of the brain, which evokes the sense of touch in the individual. 3 Moreover, BCIs have the potential to benefit patients suffering from certain neurode- generative diseases and help them maintain a high quality of life. Alzheimer’s, Parkinson’s and Huntington’s diseases are examples of age-dependent neurodegenerative diseases which cause progressive neuronal loss in the brain, and unfortunately they are currently incurable. Depending on the location of the neuronal damage, the affected individual can suffer from progressive memory loss (Alzheimer’s) and motor disorders (Parkinson’s and Huntington’s). Currently, more than 6 million Americans are living with Alzheimer’s, which is predicted to reach about 13 million by 2050 with a projected annual cost of $1.1 trillion 2 . One possible approachtorestorethelostfunctionalityinsuchdiseasesistodesignadevicethatcanmimic the functionality of the damaged brain tissue. For instance in a patient who has difficulty in forming new memories, this device should continuously monitor the neural activity in the CA3regionofthehippocampus,andsendstherecordeddatatoacomputerforanonlinedata processing such as spike detection and sorting. A multiple-input multiple-output (MIMO) model can be trained to map the spatiotemporal relationship between CA3 and CA1, which is the neuronal pathway for encoding short-term memory [10]. Subsequently, the proces- sor sends commands to the device to stimulate CA1 based on the predicted spatiotemporal pattern, as shown in Fig. 1.4. The functionality of such interfaces have been demonstrated in both non-human and human studies. Unfortunately, the equipment used in these implementations usually occupy a large area and offer limited flexibility [10]. In order to design BCIs which can be used by patientsfreelyoutsidearesearchlaboratory,keyrequirementsmustbemetsuchassmallform factor and low power consumption. Recent advances in the integrated circuits have paved the way for the implementation of complex systems on a tiny complementary metal-oxide semiconductor (CMOS) chip, which has enabled an unprecedented miniaturization of neural interface electronics. This dissertation discusses the design trade-offs in neural recording and stimulation circuits in Chapter 2. Chapter 3 introduces the issue of stimulation artifact 2 https://www.alz.org/alzheimers-dementia/facts-figures 4 Figure 1.4: A conceptual diagram of a brain prosthesis which mimics the functionality of the damaged brain tissue. in bidirectional neural interface circuits and examines different techniques to overcome the artifact. Chapter 4 discusses an adaptive infinite impulse response (IIR) filter which cancels the artifact at the front-end. To achieve superior artifact suppression, the concept of multi- point artifact cancellation is introduced in Chapter 5, which further discusses a two-point artifact cancellation system as a proof-of-concept. 5 Chapter 2 Neural Recording and Stimulation Integrated Circuits A bidirectional neural interface system consists of microelectrode arrays interfaced with multi-channel neural stimulation and recording integrated circuits (IC) as shown in Fig. 2.1. The design of neural interface circuits requires a deep understanding of the end-to-end sys- tem,whichincludestheelectrodesinterfacingthebiologicaltissue,recordingandstimulation systems, system controller, data acquisition and processing. This chapter discusses the core parameters and considerations in the design of bidirectional neural interfaces. 2.1 Electrode-Tissue Interface Figure 2.2illustratesequivalentcircuitsmodelingtheelectrochemicalprocessesofametallic electrode inside a biological tissue, which behaves as an electrolyte carrying different ions at different concentrations. In its simplified 1st-order model, also known as the Randles equivalent circuit, R S captures the electrical field distribution and is commonly known as the spread resistance, C DL models thedouble layer capacitancedue tothe iondisplacements andR CT modelsthefaradaicreactions(reductionandoxidation)attheelectrode-electrolyte interface [11]. In a more comprehensive model, C DL is replaced with a constant-phase element(CPE)withanimpedancegivenby A CPE (jω) n , whereω istheangularfrequency, A CPE is a frequency-independent constant and n describes the nonideality of the capacitance (n=1: ideal capacitor, n=0: pure resistor) [12,13]. In a more realistic scenario, the faradaic 6 Figure 2.1: Conceptual block diagram of an implantable neural interface system. STM: stim- ulator, AMP: amplifier, WG: waveform generator, Tx: transmitter, Rx: receiver, PMU: power management unit, OSC: oscillator and clock generation circuitry. reactions are limited by the rate of the diffusion of the reactants to the electrode surface, which is modeled by the Warburg element impedance Z W = A W (jω) 0.5 (A W is the Warburg coefficient) [14]. To increase spatial resolution of neural recording (selective recording from single or a few neurons), the size of the electrode should reduce which implies an increase in the electrode impedance Z EL . The increase in the electrode impedance has 2 major consequences: (1) increase of the electrode thermal noise due the real part of Z EL and (2) signal attenuation due to the voltage division between Z EL and the input impedance of the recording system Z in , as shown in Fig. 2.2. 2.2 Recording System A simplified block diagram of a traditional neural recording system is shown in Fig. 2.3, which has an amplifier, a band-pass filter, a sampler, an analog-to-digital converter (ADC), followed by data transfer for processing. The main purpose of this system is to convert the 7 Figure 2.2: The electrode-tissue interface and its first-order and higher order models. analog neural waveform into a digital representation for data processing in a computer. The amplifier has the responsibility of amplifying the 10 µ V-1mV neural signals to the full-scale range of the ADC, while adding minimum electrical noise to the signal and maintaining the signal integrity with minimal distortion. Depending on the proximity of the recording elec- trode to a neuron, the maximum received signal varies; hence, a fixed gain for the amplifier may not be an efficient approach. Therefore, the amplifier in the recording systems usually hasatunablegainsuchthattheamplifiedsignalmeetsthefull-scalerangeoftheADC,with- out saturating the amplifier. The amplifier is usually accompanied with band-pass filtering to select the desired frequency band, and the filtered signal is sampled with a switch. An important consequence of sampling is aliasing, which is the folding of portions of frequency spectrum back into the desired signal band, contaminating the neural signal. To overcomes this, the sampling rate of the ADC (f s ) must be equal to at least the Nyquist rate, which is twice the signal’s highest frequency component (2f H ≤ f s ). Thus, a low-pass filtering is required to band-limit the signal before quantization. The frequency spectrum of neural signals usually starts from very low frequencies ( 1 Hz) and carries components up to about 10 kHz. This spectrum is divided into two major categories: Local-field potentials (LFP) 8 Figure 2.3: Simplified block diagram of a conventional neural recording system. with frequencies below 200 Hz and action potential (AP) or spikes with frequencies above 200 Hz. An example recording of neural signals is shown in Fig. 2.4, which is recorded fromrat’shippocampus. Ahigh-passfilteringisalsorequiredtoeliminatetheDCoffsetand the low-frequency drift of the electrode potential (f L <1 Hz). The maximum signal-to-noise ratio (SNR) at the input of the recording system dictates the resolution required by the ADC, which is given by N ≥ SNR(dB)− 1.76 6.02 . 2.2.1 Noise The main contributors to the total noise in the system are the electrode thermal noise v n,electrode , the biological background noise v n,bio which includes the activity of far neurons in the tissue, the 50/60Hz power line interference v n,60Hz , the thermal noise of the amplifier v n,amp , the sampling switch noise v n,samp , and the ADC quantization noise v n,q (Fig. 2.5). There could also be unwanted in-band interference from various source such as any electro- magnetic coupling from adjacent electronics, from vibrations of the electrodes and wires or even the muscle activity, which can be lumped as an additional noise source v n,other . The noise power spectral density of the electrode can be calculated according to S v n,electrode =4kTRe{Z EL }, (2.1) where k is the Boltzmann constant, and T is the absolute temperature in Kelvin. Re{Z EL } is the real part of the electrode impedance, which can be approximated from the first order 9 Figure 2.4: (a) A high-pass filtered recording of the hippocampus in a rat’s brain (b) An isolated spike waveform (c) A 1-minute recording showing the local field potential. This data was recorded in collaboration with Dr. Dong Song’s laboratory at the University of Southern California. Figure 2.5: Signal and noise flow diagram. modelinFig. 2.2asR S + 1 4π 2 f 2 R CT C 2 DL andisusuallydominatedbythespreadresistance R S in the frequency band of interest (R S = ρ 4r , ρ ≈ 72Ω cm is the resistivity of the physiological saline and r is the radius [15]. Physiological saline (such as phosphate-buffered saline or 10 PBS) is a solution of salts which is isotonic with the body fluids and is usually used for characterizing neural interface systems before conducting in-vivo experiments). Amplifier is an active circuitry which uses transistors to boost the input voltage. The noise of a complementary-metal-oxide semiconductor (CMOS) amplifier has two major com- ponents: a thermal noise which has a white spectrum and a frequency-dependent flicker noise, as given by S vn,amp = 4kTγα 1 g m + Kα 2 C ox WLf , (2.2) where g m , W and L are the transconductance, width and length of the input devices of the amplifierrespectively, C ox isthegatecapacitanceperunitarea, γ isthenoisefactorwhichis technologydependent(forlong-channeldevices, γ ≈ 2 3 ),K isaprocess-dependentparameter and α 1 ,α 2 >1 are parameters that depend on the amplifier topology. Considering the full recording chain, the sampler folds back noise into the signal band- width due to aliasing, which increases the integrated noise of the system. To simplify the analysis, we limit our analysis to white noise at the input of a first-order low-pass filter with a gain of G, and a corner frequency of of ω H followed by sampler, as shown in Fig. 2.6 . The equivalent noise power at the output of the sampler can be calculates as [16], S vn,o = πG 2 f H f s S vn,w , (2.3) which implies that the output sampled noise power spectral density increases linearly by the ratio of f H fs . Therefore, a Nyquist sampling rate increases the root-mean-square (rms) thermal noise voltage by about 25%. Fig. 2.7 shows a more accurate flow diagram of the noise sources. To evaluate the noise performance of the recording system, the input-referred noise power spectral density of the systems can be calculated as 11 Figure 2.6: Effect of sampling on a low-pass filtered white noise. Figure 2.7: Noise model of the recording system including the effect of noise aliasing. S v n,in =S v n,bio +S v n,electrode +S v n,60Hz +S v n,other + Kα 2 C ox WLf + 4kTγα 1 g m πf H f s + kT C ADC fs 2 G 2 + V 2 FS 12× 2 2N fs 2 G 2 , (2.4) where G is the gain of the amplifier, C ADC is the ADC sampling capacitor, V FS and N are theADCfull-scalerangeandresolutionrespectively(thelasttwotermsareS vn,samp andS vn,q respectively). 12 2.2.2 Power Consumption An implantable device has limited space for energy storage such a battery or a capacitor. In addition,thedissipatedpowerinthetissuemayincreasethelocaltemperaturewhichcanlead to cellular damage. Hence, the power consumption of the neural recording system is critical. There are several system specifications that determine the total power consumption, such as noise, ADC resolution and sampling rate, and data transmission. As can be observed in Eq. 4.4, the only noise component in the recording system that can be reduced by increasing the power consumption is the thermal noise of the amplifier. For a metal-oxide-semiconductor field-effect transistor (MOSFET), when operated in the weak inversion (or subthreshold) regime, the current I and transconductance g m are related as g m = I nV T , where V T = kT q is the thermal voltage (q is the elementary charge) and n = 1 ∼ 2 is the slope factor, which is technology dependent. Hence, the thermal noise voltage scales inversely with the square root of the current of the input devices in the amplifier. The noise-power trade-off of neural amplifiers are usually compared using the noise efficiency factor (NEF) defined as [17] NEF =v n,in,rms r 2I AMP πV T 4kTBW , (2.5) where I AMP is the amplifier current, BW = f H − f L is the bandwidth of the amplifier, and v n,in,rms includes both the flicker and thermal noise of the amplifier. State-of-the-art amplifiers achieve NEF of about 2 ∼ 3. Since a lower NEF does not necessarily imply a lower power consumption, power efficiency factor (PEF) is also used to evaluate the noise- power performance of a design, which is defined as PEF =NEF 2 VDD (VDD is the supply voltage of the amplifier). ADCs also consume power to find the digital representation of an analog signal, which scales linearly with the sampling rate and exponentially with the resolution, as shown by P ADC =FOM× 2 N × f s , (2.6) 13 whereN istheADCresolution,f s isthesamplingrate,andFOMistheADCfigure-of-merit which is an indication of its performance in terms of the energy used per conversion step. Data transmission is usually the most power hungry block in a neural interface system. Thedigitaldataisserialized,packetizedandsentviaacable(wirelinecommunication)orvia an antenna (wireless communication). For short-range radio-frequency (RF) transmission, ultra-wide band (UWB) transmitters can achieve energy per bit as low as 10’s of pJ/bit [18–20]. To find the energy efficiency of a wireline transmission, we can consider a simplified serial communication where the data is sent over one line and another line carries the clock signal which marks the sampling time of the data line, as shown in Fig. 2.8. Every half clock cycle, the load capacitance C L which is the net capacitance from the transmitter outputtotheground, ischargedtoC L VDD anddischargedinthefollowinghalfclockcycle. Therefore, the average current that the clock buffer draws from the power supply is C L VDD T CLK . The current drawn by the data buffer depends on the transmitted bit pattern. Assuming that bits 0 and 1 occur with an equal probability, every two clock cycles, the capacitance on the data line is charged and discharged; hence, the average current drawn by the data buffer is C L VDD 2T CLK . The total transmit energy per bit can be roughly approximated as 1.5C L VDD 2 (For a more comprehensive calculation, the power consumed by the buffer internally, such as the short-circuit current of the inverters, should be considered). Assuming C L =10pF and VDD =1.5V, the wireline transmit energy per bit can be found to be 33.8 pJ/bit. The powerconsumedforthetransmissionoftherecordeddatafromN ch channels,eachquantized to N bits at sampling rate f s is P TX =Energy/bit× N× N ch × f s . (2.7) At high data rates, low-voltage differential signaling (LVDS) can provide a more efficient wireline data transfer [21]. In general, parameters such as data rate, target transmission range, link characteristics, receiver’s sensitivity, maximum specific absorption rate [22] and power budget should be considered when designing the communication interface. 14 Figure 2.8: Serial data transmission. The receiver in this example is a field-programmable gate array (FPGA). 2.2.3 Implementations of Neural Recording Channels 2.2.3.1 OTA-based Amplifier with Capacitive-Feedback Figure 2.9showstheschematicofaconventionalneuralrecordingamplifier. Thefirststageis alow-noiseamplifier(LNA)whichusuallydeterminesthenoiseperformanceoftherecording systemandhasafixedgain. TheLNAisfollowedbyaprogrammable-gainamplifier(PGA), which is also referred to as a variable-gain amplifier (VGA). This stage is usually designed to have tunable gain and bandwidth. Both stages consist of operational transconductance amplifiers (OTA) configured in a negative capacitive feedback. The transfer function of the LNA can be derived as V mid V in = sC 1 R 2 (1− sC 2 gm ) (1+ s ω L,1 )(1+ s ω H,1 ) . Therefore, the midband gain of the LNA is given by G 1 = C 1 C 2 and the high-pass and low-pass corners are given by ω L,1 = 1 R 2 C 2 and ω H,1 = gm C 1 +(1+G 1 )(Co+C 3 ) respectively (The PGA would have a similar transfer function). The input-referred noise of the LNA can be derived as S v n,LNA = s ( C 1 +C 2 +C p,1 C 1 ) 2 S v n,OTA1 + 4kT ω 2 R 2 C 2 1 , (2.8) where C p,1 is the net parasitic capacitance at the virtual ground of the LNA and the second term is generated by the thermal noise of R 2 . Due to the division by the gain of the LNA 15 Figure 2.9: LNA and PGA implementation as OTA-based amplifiers with capacitive-feedback. Figure 2.10: Simplified amplifier circuitry for noise calculations. stage, the noise of the PGA does not usually contribute much to the total input-referred noise of the amplifier. 16 Figure 2.11: Concept of the chopping technique. As highlighted in the previous sections, the noise of the amplifier at high frequencies is dominated by the thermal noise, which can be reduced by increasing the amplifier current. However, reducing the low-frequency flicker noise would require increasing the size of the devices in the OTA, which may limit the density of the recording array. To overcome this, the chopping technique can be used to up-convert the flicker noise out of the signal band, whichisfilteredbyalow-passfilterasshowninFig. 2.11. Thedesignofachopper-stabilized amplifier is discussed in Appendix B [23]. 2.2.3.2 Front-end Oversampling ADCs Instead of amplifying the neural signal to meet the full-scale range of the ADC, a high- resolution ADC can be placed at the front-end to directly digitize the neural signal. This implementation can also boost the tolerable dynamic range to maintain linearity in the presenceofundesirablelargesignalssuchasmotionartifacts. Anstraightforwardimplemen- tation is to operate an ADC with a sampling rate f s much higher than the Nyquist rate 17 f s,Nyq . This lowers the quantization noise spectral density in the signal band and a low-pass filtering removes the out-of-band noise. The effective SNR due to oversampling is given by SNR(dB)=6.02N +1.76+10log(OSR), (2.9) where OSR = fs f s,Nyq is the oversampling ratio and N is the ADC resolution. It is possible to reducethein-bandnoisefurtherbyshapingthequantizationnoisebyintroducingafeedback such as in ∆Σ ADCs [Fig. 2.12(a)], where the achievable SNR is boosted to 6 .02N− 3.41+ 30log(OSR) . Since sampling at the very front-end would create leakage current drawn from the electrode and also add significant kT/C sampling noise, a continuous-time (CT) ∆Σ implementation is preferred, as shown in Fig. 2.12(b). Capacitor C 1 integrates the difference between the input current and the feedback current and a comparator quantizes the integrated voltage into two levels. Another approach to efficiently make use of the ADC dynamic range is to equalize the neural signal frequency spectrum. Front-end differentiators and ∆-modulators can take advantage of the 1/f 1∼ 3 power spectral density of the neural data [24–28], as shown in Fig. 2.13. These modulators produce differences of consecutive samples and attenuate the slowly-varying contents of the signal; hence, shaping the frequency spectrum. 2.2.3.3 Multi-Channel Neural Recording System Architectures In most neural interface scenarios, we are interested to record from different neurons in the brain. Therefore, the neural recording system should be able to continuously monitor the neural signals received at all the electrodes. An straightforward implementation is to have a full recording chain per channel and serialize the data after the ADCs before the data transmission, as shown in Fig. 2.14(a). When scaling up the neural recording system to 10s or 100s of channels, this architecture can potentially consume a significant silicon area. To make the design more scalable, one can share multiple blocks of the recording chain among 18 Figure 2.12: (a) Block diagram of a first-order ∆Σ ADC (b) Example of a CT-∆Σ. several channels. For example in Fig. 2.14(b), the ADC is shared between M recording channels; thus, saving the chip area. However, the ADC has to sample its input M times faster compared to the case in Fig. 2.14(a). This implies that the buffers preceding the multiplexing switches should operate faster to meet the reduced available settling time per channel. Therefore, a higher power consumption is inevitable when sharing the ADC among several channels. 2.3 Stimulation System A common method to excite neurons in a tissue is via applying an electric field locally. This can be achieved by accumulating electric charges temporarily on a metallic electrode 19 Figure 2.13: Frequency shaping techniques (a) Front-end differentiation followed by back-end integration, (b) ∆-modulation and demodulation. implanted in the tissue, as shown in Fig. 2.15. Depending on the type of the excitable element (dendrite, soma or axon) and the distance of the elctrode to the target neuron, a minimum current should be injected for a certain amount of time to excite the tissue [29]. If the stimulus strength is below a certain value (referred to as rheobase), even an infinite duration of stimulus cannot excite the tissue. This can be shown on a strength-duration curve [30] as in Fig. 2.16. In this figure, for a stimulus duration of T 0 , neuron A is activated with a weaker stimulus signal. This shows that to activate nerves selectively, the exact current and duration of the stimulus should be controlled. Moreover, electrodes can tolearte a maximum charge density (e.g. for platinum, 50-150 µ C/cm 2 for a 0.2ms biphasic pulse [31]), beyond which irreversible redox reactions may occur. Therefore, a stimulation method that provides a fine control over the injected charge into the electrode is preferred. 20 Figure 2.14: Neural recording multiplexing techniques (a) Digital multiplexing after the ADC, (b) Analog multiplexing before the ADC. There are three major techniques to send electric charges to the electrode, which are briefly discussed here. One method is to use a storage capacitance to deliver charges to the electrode, which is referred to as switched-capacitor stimulation (Fig. 2.17) [32]. In the first phase, the storage capacitor C charge is initially charged. In the second phase, the charging path is disabled and the storage capacitor is connected to the electrode for a 21 Figure 2.15: Concept of electrical neural stimulation. Figure 2.16: Strength-duration curves for two different neurons. certain duration τ . Finally, the electrode is discharged to the ground through a switch. For a predictable stimulation event, the amount of charge injected to the electrode should be known. However, this method cannot control the amount of charge delivered to the tissue because the amount of delivered charge depends on the electrode-tissue capacitance C DL , as given by Q DL = C charge C DL C charge +C DL V STIM (assuming R CT C DL ≫ τ and R s C DL ≪ τ ). 22 Figure 2.17: Switched-capacitor stimulation. Another method to stimulate neurons is direct connection to a voltage source, as shown inFig. 2.18 [33,34]. Thisapproachdoesnotneedanexplicitcapacitorunliketheswitched- capacitor method, but the issue of uncertainty in the amount of charge delivered to the electrode still exists. Thewidelyusedmethodwhichcanideallysendanexactamountofchargetotheelectrode is the current-mode stimulation [35]. In this method, a current source delivers a fixed current to the electrode for a specific amount of time. Figure 2.19(a) illustrates a biphasic implementationofthecurrent-modestimulation,andFig. 2.19(b)showsthetimingdiagram 23 Figure 2.18: Voltage-mode stimulation. of the electrode current, voltage and charge. In the anodic phase, the top current source turns on and delivers an exact amount of charge Q DL =I STIM,a T a to the electrode. During thecathodicphase,thetopcurrentsourceisdisabledandthebottomcurrentsourceturnson anddischargestheelectrode,whichimpliesthatI STIM,a T a =I STIM,c T c (referredtoascharge- balancedstimulation). Thereasonforhavingthedischargephaseisthatanyresidualcharge ontheelectrodebuildsupduringconsecutivestimulationcycles. Thisaccumulationofcharge increases the residual voltage across the double-layer capacitance, and if this voltage passes the water window limits (-0.6V to 0.8V for metallic electrodes [36]), water hydrolysis at the electrode-tissue will occur which can irreversibly damage the electrode and the surrounding tissue. Different possible timings for the cathodic and anodic phases are shown in Fig. 2.19(c). 24 Figure 2.19: (a) Current-mode stimulation. (b) Timing diagram for biphasic stimulation. (c) Possible timing scenarios. The required amount of current and the duration per stimulation phase depends on the electrodes (size and material), the tissue, and the proximity of the electrode to nearby neurons. Another important parameter is the maximum (and minimum) electrode voltage that still allows the stimulator to operate, which is referred to as the compliance voltage. If 25 the tissue is biased at half the supply voltage V MID = V DD 2 , the maximum current that can be applied to the tissue can be calculated as (assuming R CT C DL ≫ T phase ) I STM,max = V DD 2 − V OD R S + T phase C DL , (2.10) where V OD is the voltage headroom required across the current sources for normal operation and T phase is the duration of the first phase (either T a or T c ). Lower impedance electrodes allow for higher stimulation currents for a given compliance voltage. Therefore, the target application and the electrode parameters should be decided prior to the design of the stimu- lator. Appendix A discusses a technique that improves the efficiency of a current stimulator using adaptive supply voltage modulation [35]. 2.3.1 Multi-Channel Neural Stimulation Architecture Similar to the recording system, we are usually interested to stimulate neurons in different locations. Therefore, multiple electrodes are implanted in the target areas and each can be connected to one stimulation circuitry. However, the current sources, which are usually implemented as current digital-to-analog converters (DAC), consume chip area and having one for each channel may not be a scalable solution. Since the stimulation signals are relatively short current pulses, a possible mitigation is to share one current DAC among multiple channels and deliver required charges to target electrodes in a time-multiplexed implementation, as shown in Fig. 2.20. Fig.2.21showsasummaryofthecoreparametersthatshouldbeconsideredinthedesign of a bidirectional neural interface circuitry. Overlapping circles show parameters that are directly related. Table 2.1 and Table 2.2 show typical specifications for neural recording and stimulation systems respectively. 26 Figure 2.20: Time-multiplexed multi-channel stimulation. Figure2.21: Multidimensionaldesignspaceofabidirectionalneuralinterface. Thespecificcontri- bution of my previously designed chips are highlighted [DR: dynamic range, Z in : input impedance, Z elec : electrodeimpedance, THD:totalharmonicdistortion,CMRR:common-moderejectionratio, BW: bandwidth]. 27 Table 2.1: Typical Specifications for A Neural Recording System Parameters Specifications Supply voltage 1.0 V 3-dB Bandwidth 1Hz-10kHz ADC sampling rate > 20kSa/s Input-referred Noise < 5µ V rms NEF < 4 Dynamic range > 40dB THD < 1% CMRR > 60dB Power consumption for signal conditioning and quantization per channel < 5µ W Power consumption for data transmission per channel < 10µ W Area per channel < 0.1 mm 2 Table 2.2: Typical Specifications for A Neural Stimulation System Parameters Specifications Maximum current > 100 µ A Current DAC resolution < 5µ A Timing resolution < 10µ s Repetition rate 1Hz∼ 1kHz Area per channel < 0.1 mm 2 28 Chapter 3 Stimulation Artifact Bidirectional brain-computer interfaces (BCI) have become integral components in research and clinical settings [10,37–39]. Responsive neurostimulation (RNS) is an example of such a closed-loop system that monitors the brain activity continuously in patients with epilepsy using 4 recording channels [40]. When the onset of a seizure activity is detected, stim- ulation pulses are sent to specific regions of the brain to possibly prevent a seizure. For a chronic implantation of these bidirectional systems in patients suffering from neurode- generative disorders (e.g. Alzheimer’s and Parkinson’s diseases), a customized low-power integrated-circuit (IC) that can communicate bidirectionally with the neurons in the brain is needed [Fig. 3.1(a)]. This IC should be able to simultaneously stimulate different re- gions of the brain while amplifying and recording the neural activity through high-density micro-electrode arrays (MEA) [41,42]. Figure 3.1(b) depicts a simplified model of how the delivery of the stimulation current (I STM )intothetargettissuemayleadtoanundesirableartifactvoltage a(t)attherecording electrode. Since the tissue is conductive, the stimulation current that enters the electrode spreads into the medium (R s1 and R s2 ), as shown in Fig. 3.1(c). This creates a voltage profile in the surrounding tissue, which is received by the nearby recording electrode (Path 1). However, the scenario can become more complex when stimulation and recording are performed using shared electronics and electrode arrays. As shown in Fig. 3.1(c), due to the impedance which naturally exists at the electrode-tissue interface, the stimulation 29 Figure 3.1: (a) Conceptual diagram of a bidirectional neural interface. (b) Stimulation artifact interferes with the neural signal. (c) Possible artifact-coupling pathways. current induces a stimulation voltage (V STIM ) at the stimulating electrode. V STIM may leak directly to the input amplifier through the parasitic elements that exist in the system, e.g. via a parasitic capacitance (C p ) across adjacent long wires connecting the stimulation and recording electrodes to the bidirectional interface electronics (Path 2). This artifact voltage 30 Figure3.2: Recordingof(a)aneuralsignaland(b)aneuralsignalcontaminatedwithstimulation artifact. may reach a few volts at the location of the stimulation, which can easily saturate the low-noise amplifier (LNA) that is conventionally designed to handle µ V-level neural signals [23,43–50],asillustratedinFig. 3.2. Consideringtheseizuredetectionapplication,thesignal loss and reduced SNR can potentially lower the success rate of the biomarker detection. If a 1 V pp artifact contaminates a 10 µ V p neural signal, the system will need to handle a dynamic range of at least 100 dB, which is equivalent to >16b of effective number of bits (ENOB). Different techniques have been proposed to address this issue, which can be categorized into two general approaches: stimulation-side cancellation and recording-side cancellation/mitigation (Fig. 3.3). The recording-side mitigation can be further divided into the front-end and back-end mitigation solutions [51]. The front-end techniques aim to prevent the neural signal dis- tortion by addressing the artifact before quantization. The back-end cancellation tries to restore neural information from the contaminated data by using data reconstruction [52] 31 Figure 3.3: Typical cancellation points for stimulation artifact. Figure 3.4: Back-end stimulation artifact cancellation. or component decomposition techniques such as the principle component analysis (PCA) and the independent component analysis (ICA) [53], which are computationally expensive and usually performed off-chip (Fig. 3.4). As more efficient methods, artifact template averaging [54] and back-end stimulation artifact rejection using adaptive digital filters has been implemented [55,56] . It is critical to note that without any front-end artifact mitigation, the back-end data processing cannot restore the distorted or lost neural data. A straight-forward front-end mitigation technique is to disconnect the amplifier input when the stimulation current is applied, preventing the artifact to appear at the front-end [57–59], as shown in Fig. 3.5(a). However, the artifact blanking method suffers from slow transient settling due to the low high-pass cutoff frequency of the amplifier. A more severe drawback is the complete loss of the neural data during the stimulator activity, which worsens as the number of the stimu- lation channels increases. Another possible downside of this approach, arises from periodic 32 switching at the amplifier input in the presence of periodic stimulation, which leads to a DC current drawn from the electrode (Fig. 3.6), given by I EL,DC =f STM C in V offset , (3.1) where I EL,DC is the electrode DC current, f STM is the stimulation repetition rate, and V offset is the electrode DC offset. Assuming reasonable values for these parameters such as f STM =100Hz, C in = 10pF, and V offset =100mV [60], the electrode DC current will be 0.1 nA, which can lead to sustained electrolysis and electrode potential drift. To prevent losing any neural signal, high resolution ADCs [61] can be implemented to accommodate the full range of the artifact voltage, as shown in Fig. 3.5(b). ∆Σ-modulator front-ends [62–64] use a high oversampling ratio (OSR) to achieve the required ENOB, which results in additional power consumption during the decimation and post-processing of the over-sampled data. As an alternative to the voltage-domain quantization, a front- end voltage-controlled oscillator (VCO) can translate the full-scale voltage variations into time-encoded data, which relaxes the analog front-end (AFE) circuitry design by removing the need for voltage amplification [65–68]. Since the voltage-to-frequency conversion is a highly nonlinear process, a nonlinearity correction block is needed to compensate for the added distortion. An alternative method to suppress the VCO nonlinearity is to embed the VCO and quantizer in a feedback loop [69]. High resolution ADCs with competitive power consumption (including the decimation circuitry) have been demonstrated mainly for input frequencies up to 500 Hz, which are only suited for recording the local field potentials (LFP) and not the action potentials (AP). However, recording the AP or spikes, which oc- cupy frequencies up to a few kHz, is critical for neuroscientists to understand how neuronal units and populations communicate with each other to function properly (e.g. short-term memory encoding [70]). Scaling these systems to handle a larger input bandwidth signifi- cantly adds to the power consumption and system complexity, since the switching frequency required at the front-end quantizer and the back-end digital circuitry for decimation and/or 33 Figure 3.5: Stimulation artifact front-end mitigation techniques. (a) Artifact blanking. (b) High resolution ADCs. (c) Delta-modulated front-ends. (d) Front-end adaptive filters. non-linearity correction scales linearly with the maximum bandwidth of the input signal. Moreover, increasing the ADC resolution from a conventional 10b to 15b (equivalent to 30 34 Figure 3.6: DC leakage current due to artifact blanking. dB boost in dynamic range) would drastically increase the energy required for the raw data transmission or on-chip back-end digital processing for artifact removal. In another effort to handle a wide input dynamic-range, front-end differentiators and ∆-modulators have been proposed to take advantage of the 1/f 1∼ 3 power spectral density of the neural data [24–28]. As Fig. 3.5(c) shows, ∆-modulation flattens the signal power over the neural signal bandwidth by amplifying the low-power high-frequency components (AP) 35 more than the high-power low-frequency components (LFP). This can relax the dynamic range requirement of the quantizer. The main drawback of this scheme for stimulation artifact cancellation is that the artifacts can have large fundamental and harmonic spectral components in the kHz range [71], which can not be mitigated by front-end ∆-modulation. Past in vivo measurements have demonstrated a less than 10% variation in the artifact waveform during a stimulation session [72]. This suggests that a periodic stimulation signal would generate a periodic artifact, implying that the recording system does not necessar- ily need to quantize the full artifact waveform at every stimulation cycle. If a replica of the artifact waveform is periodically subtracted from the incoming contaminated signal be- fore quantization, the DR requirements of the recording ADC can be significantly reduced. Consequently, adaptive artifact mitigation in the front-end has been proposed, which can potentially provide a flexible, scalable and low-power solution for artifact cancellation in a high-density neural-interface platform. It reduces the dynamic range at the AFE input and enables the use of conventional successive-approximation-register (SAR) ADCs with ENOB <11, while preserving both the LFP and AP neural data [54,73–76]. The concept of the adaptive filtering scheme is shown in Fig. 3.5(d). When the stimulation signal s[n] is activated, the stimulation current enters the electrode-tissue interface, creating an artifact voltage at the stimulating electrode surface. This artifact voltage is picked up by the record- ing electrodes as a[n], corrupting the received neural data x[n]. In order to suppress the undesirable large-signal artifact, which can potentially saturate the front-end amplifiers, an on-chip digital filter H m (z) is used to mimic the response of the electrode-tissue interface. This digital filter generates a replica of the artifact voltage y[n] and applies it to the LNA input, suppressing the artifact waveform at the front-end. The cancellation filter H m (z) can be realized either with a finite impulse response (FIR) or an infinite impulse response (IIR) configuration. Before choosing the most suitable configuration, we should first investigate the possibility of developing a simple model that can mimic the artifact waveform, which will be discussed early in the next chapter. 36 Figure 3.7: Stimulation-side artifact cancellation. (a) Without cancellation. (b) With the dipole cancellation. Contour lines enclose the region where the artifact saturates the recording channels. A recent technique focuses on the stimulation-side artifact cancellation [77,78] . Let us consider a recording electrode grid placed next to a stimulation electrode array, as shown in Fig. 3.7(a). In this example, bipolar stimulation voltages (V STM+ ,V STM- ) are applied to electrodes A and B. As we go further away from the stimulating electrodes, the artifact voltagedrops. Thedottedcontourshighlighttheboundarywhereontheoutside,theartifact voltage is less than the maximum tolerable input voltage V in, MAX . Electrodes E and F are inside the boundary; thus, their respective recording channels will be saturated. To push the saturation boundary of V in, MAX away from the recording array, one can create a dipole to induce a counter electric-field to reduce the net artifact voltage on the recording electrodes, as illustrated in Fig. 3.7(b). Here, the canceling dipole is electrodes C and D which are fed with V CANC- ,V CANC+ respectively. Since the resultant contour does not enclose any recording electrodes, all the recording channels can maintain their linearity while experiencing a residual artifact. However, this implementation requires a dedicated stimulation grid such that an optimum dipole can be found from that grid by running an optimization algorithm [78]. Therefore, there exists a geometrical constraint on how the recording and stimulation electrodes can be arranged. 37 Table 3.1: Qualitative comparison of different stimulation artifact cancellation/mitigation tech- niques Inconclusion, aqualitativecomparisonofdifferentstimulationartifactcancellationtech- niques that were discussed in this chapter is shown in Table 3.1. In general, two or more of the aforementioned techniques can be combined to realize systems with more resilience to the stimulation artifact. Since preserving the neural signal data during the stimulation phase is of critical im- portance, the oversampling method and front-end adaptive filtering are the most promising solutions to maintain the signal inetgrity at all times. If the target is to mitigate time- varying artifacts from sources that are unpredictable (such as motion or neuromuscular activity), oversampling the received waveform to digitize the full dynamic range may be the optimum solution. However, the stimulation artifact, which is usually the dominant source of interference in bidirectional neural interfaces, carries a periodic waveform synchronous with the stimulation signal. Increasing the ADC resolution from a conventional 10b to 15b 38 (equivalent to 30 dB boost in DR) to quantize a large-swing periodic waveform would dras- tically increase the energy required for the raw data digitization and transmission or on-chip back-enddigitalprocessingforartifactremoval. Therefore,aschemethatcancelstheartifact at the front-end would significantly relax the system compelxity and power consumption. 39 Chapter 4 Stimulation Artifact Canellation with Adaptive IIR Filters Before choosing the filter architecture and parameters for an adpative stimulation artifact cancellation,wecanobtainusefulinsightbyinvestigatingtheartifactwaveforminapractical bidirectional implementation. 4.1 Modeling the Stimulation Artifact Fig.4.1(a)showstheexperimentalsetupthatwasusedforcharacterizingtheartifactvoltage. A parylene-based microelectrode array [79] was used to investigate the challenging case of stimulation and recording from electrodes on a single shank, spaced just 2 mm apart. A biphasic 35 µ A stimulation current, with 330 µ s per phase, was applied to electrode 4 (E 4 , withadiameterof210µ m),whilethewaveformofelectrode2(E 2 ,withadiameterof60µ m) was measured as the target recording site in this example. Fig. 4.1(b) plots the stimulation voltage and the resultant artifact waveform. Due to the similarity between the waveform of the stimulation and artifact voltages, a simple series RC network (R m ,C m ) was examined as a potential model for the artifact waveform [Fig. 4.1(a)]. Through computer simulations, the optimized RC parameters that recreated the waveform of the artifact voltage were found [Fig. 4.1(c)]. The simulated response of the RC model (V model ) is plotted in Fig. 4.1(b). 40 Figure 4.1: (a) Artifact measurement test bench and proposed RC model (geometrical details of the electrode can be found in [79]). (b) RC model output displayed with the measured stimulation and artifact voltages. (c) Fitted RC model parameters. (d) Stimulation artifact waveform and filter response. Examining the difference between V model and V in demonstrates that during the stimulation phase, the model can emulate the artifact with a maximum of 50 mV discrepancy (For 70% of the stimulation time, this discrepancy is less than 20 mV). Hence, in this example, if we could physically create V model and subtract it from V in before amplification, the dynamic range (DR) that the AFE needs to accommodate reduces from 380 mV to 50 mV, which is a factor of 7 or equivalently 3 bit improvement in the required DR for the AFE+ADC signal path. After the stimulation phase, due to the mismatch between anodic and cathodic currents, there is a residual charge on the stimulation electrode which discharges slowly as canbeseeninFig.4.1(b). Chargebalancingtechniques [80]canbeimplementedtosuppress this slowly decaying waveform, which is beyond the focus of this dissertation. 41 An straightforward way to implement the model is to physically realize R m and C m on chip. However, implementing a nF-range capacitance on-chip and copying the stimulation current to regenerate the artifact waveform is not an efficient solution. It may be possible to implement the RC network in the digital domain with a more compact footprint. The transfer function of the RC model can be written as H m (s) = 1+sRmCm sCm . Through a bilinear transformation, by substituting s with 2 Ts 1− z − 1 1+z − 1 (T s : sampling period), the Z-domain transfer function can be derived as, H m (z)= b 0 +b 1 z − 1 1− z − 1 , (4.1) where b 0 and b 1 are functions of T s , R m and C m . Approximating the continuous V model with a discrete-time waveform (V replica ) introduces residual artifact. The value of T s should be chosen small enough to reduce the residual artifact voltage [i.e. V residue = V model - V replica , as shown in Fig. 4.1(d)] sufficiently below the level that would saturate the front-end LNA. This criterion sets the minimum required sampling speed of the digital filter as a function of the peak stimulation current and the electrode-tissue capacitance, I peak C DL T s < VDD G . (4.2) Assuming I peak = 100 µ A, C m = 30 nF, the LNA supply voltage VDD = 1.0 V and the LNA gain G = 25, the upper limit for T s can be derived as 12 µ s. Past work has implemented adaptive FIR filters to replicate and cancel the artifact waveform at the front-end. However, this topology requires a large number of taps [73] to reproducetheartifactwaveform,whichcanbeattributedtotheexistenceofapoleinH m (z). Inhigh-densityMEAswhererecordingandstimulationelectrodesareclose, theartifactlevel may reach a few volts, which is an order of magnitude above the performance limits of the existing FIR schemes [54,73–76]. However, an IIR implementation of the digital filter realizes a pole which can better approximate the electrode response and drastically improve the cancellation performance. The reduced number of coefficients in the IIR implementation 42 Figure 4.2: Block diagram and comparison of the FIR [73] and the proposed IIR cancellation filters. carries the following additional advantages: (1) reduced silicon area for filter realization and (2) reduced computational power, both by an order of magnitude as shown in Fig. 4.2. Here we present an adaptive IIR stimulation artifact canceler; Section 4.2 discusses different aspects of the design strategy, section 4.3 describes the system operation, and section 4.4 shows the AFE characterization and canceler performance in different scenarios. 4.2 System-Level Analysis Fig. 4.3(a) shows the simplified configuration of the amplifier chain with the cancellation capacitive DAC (CDAC). An artifact waveform appearing at the amplifier input consists of differential-mode(DM)andcommon-mode(CM)components[Fig.4.3(b)]. Sincethecancel- lation filter injects the artifact replica ( y[n]) to the LNA input differentially, the differential componentoftheartifactiscanceled; however,theCMcomponentisnotaffected,whichcan deteriorate the AFE linearity by perturbing the device biasing. To quantify the tolerable common-mode artifact, let us consider the front-end of an AFE with the cancellation DAC capacitors (C DAC ) connected to the virtual ground, as shown in Fig. 4.3(b). Assuming that the operational transconductance amplifier (OTA or g m cell) has a common-mode gain of 43 Figure 4.3: (a) Simplified block diagram of the front-end configuration. (b) Differential-mode artifact cancellation at the LNA input and common-mode limitation (V CMST : body bias voltage). A OTA,CM , any input common-mode signal experiences a capacitive division at the virtual ground according to V i,OTA,CM = C 1 C 1 +C DAC +C FB1 (1+A OTA,CM ) V in,CM , (4.3) where the parasitic capacitance at the OTA input is assumed negligible. Considering a conventional inverter-based g m cell, the input common mode range can be given by, V OV,6 +V GS,1 <V i,OTA,CM <VDD− V OV,5 − V SG,3 . (4.4) Assuming VDD = 1V,V OV,5 = V OV,6 = 100mV and V GS,1 = V SG,3 = 350mV, the input- common mode range of the OTA can be calculated as 0.45V < V i,OTA,CM < 0.55V. This 44 Figure 4.4: Noise and dynamic range analysis. (a) Signal flow diagram of the artifact, desired signal and noise. (b) Effect of the front-end (FE) cancellation on the dynamic range (DR). (c) Required DR for the recording system. sets a limit on the maximum input common-mode range that the amplifier can tolerate as shown below, V in,CM,max ≈ (1+ C DAC C 1 )(100mV), (4.5) where reasonable assumptions of A OTA,CM < 1 and C FB1 ≪ C 1 are made. Noise, area and power consumption should also be considered when adding additional circuitry to the front- end. Fig. 4.4(a) shows the simplified signal flow diagram and noise sources in the system. The total input referred noise can be derived as, v 2 n,in,total =v 2 n,bio +v 2 n,elec +v 2 n,amp + v 2 n,kT/C ADC +v 2 n,q G 2 , (4.6) 45 where v n,bio is the biological background noise, v n,elec corresponds to the electrode thermal noise, v n,amp is the input-referred noise of the amplifier, v n,kT/C ADC captures the ADC sam- pling noise, v n,q is the ADC quantization noise and G is the gain of the amplifier. The amplifier noise v n,amp can be derived from the circuitry in Fig. 4.3, v n,amp = C 1 +C DAC +C FB1 C 1 v n,OTA , (4.7) v n,OTA = s 4kTγBW g m , (4.8) where γ is the MOSFET noise factor, T is the temperature in Kelvins, k is the Boltzmann constant, BW isthesystem’seffectivebandwidthandg m isthetransconductanceofM 1,2,3,4 . Also, the flicker noise is considered negligible compared to the thermal noise, but should be included for a more thorough analysis. Assuming that the devices in the OTA are biased in weak inversion for maximum efficiency, gm I 1 = 1 nV T , where I 1 is the DC current in each branch of the OTA, n is the sub-threshold factor and V T is the thermal voltage. The biological background and electrode noise depends on the electrode and the live tissue conditions, and not the electronics circuitry. Hence, in the following discussion, the focus will be on the noise contribution of the electronics, namely the amplifier and ADC. Assuming C FB1 <<C 1 (LNA typically has a gain>>1), v n,in,total can be rewritten as, v 2 n,in,total = 2kT C ADC + ∆ 2 12 G 2 +(1+ C DAC C 1 ) 2 4kTγnV T BW I 1 , (4.9) where C ADC is the ADC single-sided sampling capacitance and ∆ is the magnitude of the least-significantbit(LSB)oftheADC.TheLSBisafunctionoftheADCfull-scaledifferential voltage(inthiscase2VDD)andresolution(N),asgivenby∆= 2VDD 2 N . Fig.4.4(b)showsthat without stimulation artifact cancellation, the maximum input the system receives increases fromthemaximumdesiredsignal(x max ,usuallyafewmVintheLFPband)tothemaximum artifactlevel(a max ,uptoafewVolts). Therefore,assumingthattheminimumdesiredsignal 46 to be detected is as low as the noise floor, the additional required number of bits imposed by the artifact is log 2 ( amax xmax ). However, if a replica of the artifact (y) is subtracted from the input signal, the swing of the input waveform reduces to the the magnitude of a residual artifact, a res =a− y, which depends on the accuracy of the artifact prediction model. Using such an artifact mitigation approach reduces the required ENOB by log 2 ( amax ares,max ), as shown in Fig. 4.4(c). Therefore, reducing an artifact amplitude from 500 mV to 50 mV at the front-endisequivalenttoa3.3-bitreductionintherequiredENOBfortherecordingsystem. On the other hand, the maximum residual artifact limits the maximum gain the AFE can accommodate before saturating the amplifier, as given by G max = VDD ares,max . Under these conditions, (4.9) can be rewritten as, v 2 n,in,total = 2kT C ADC ( a res,max VDD ) 2 + a 2 res,max 3(2 2N ) +(1+ C DAC C 1 ) 2 4kTγnV T BW I 1 . (4.10) Equation (4.10) provides the basis for evaluating the trade-off that exists between the noise floor, ADC resolution, AFE power, C DAC and C ADC values (area) and maximum residual artifact. a res,max dependsontheaccuracyofthetrainingmodel,anddependingonthetarget setupandexperimentalconditions,itshouldbemeasuredearlyinthesystemdesignprocess. Larger residual artifacts (or equivalently the estimation error) require a higher ENOB and a larger sampling capacitor for the ADC to maintain the noise performance. On the other hand, if the amplifier noise is dominant, even though a larger C DAC provides a higher input CM resilience as suggested by (4.5), the AFE should consume more power to maintain the target noise level. A larger C DAC would also occupy more chip area. To evaluate the noise performance of the system, let us assume that the system should be resilient to CM artifacts up to 200 mV, which according to (4.5) requires C DAC = C 1 . For a target requirement of the area, noise and power consumption of the system, the design parameters should be optimized. In this work, the main focus is on the implementation of the proposed front-end 47 cancellation scheme as a proof-of-concept, which by itself can potentially reduce the burden on the recording system as discussed before. Therefore, the design parameters were chosen based on the conventional front-ends: N = 10,C ADC = 2.5pF,VDD = 1V,I 1 = 1µA,n = 1.5,γ =2/3. Followingthediscussioninsection 4.1, a res,max isassumedtobe50mV.Under these assumptions, the input-referred noise in (4.10) can be calculated as, v n,in,total = p (2.9µV ) 2 +(28.2µV ) 2 +(4.2µV ) 2 , (4.11) which yields v n,in,total = 28.6µV rms . In this scenario, the ADC quantization noise (28.2 µ V) dominates the overall noise performance. Depending on the target application and the minimum signal level to be detected, higher resolution ADCs may be needed to reduce the quantization noise, preferably below the thermal noise of the amplifier. In fact, if an ADC with N-bit resolution is used, by adding the proposed front-end cancellation scheme, which can potentially reduce a 500 mV artifact to 50 mV residual artifact, the input-referred total ENOB accommodated by the system would increase to N+3.3 bits. 4.3 Circuit Implementation 4.3.1 System Architecture Fig. 4.5 shows the implemented SoC which consists of two identical subsystems, each having four recording front-ends (REC) and a biphasic neural stimulator 7b-current DAC (IDAC). Afront-endswitchingmatrix(SW i- ,SW i+ ,i=0-7)canreconfigurethestimulatorconnection to any of the recording electrodes on-the-fly. This enables reusing the electrodes for both recording and stimulation, which can potentially prevent additional electrode routing and placement in the brain and reduce the damage to the tissue. The digitized outputs of all the 8 recording channels are serialized, packetized and transmitted via 2 serial lines (Serial out andCLK out ). Fixedpreambleandpostamblebitpatternsareaddedtothebit-streamtoflag 48 Figure 4.5: Neural interface SoC block diagram. the start and end of the consecutive data packets. An on-chip 25 MHz RC digital relaxation oscillator generates a tunable core clock for the chip, which is used to create proper timing fortheoperationofthesuccessiveapproximationregister(SAR)ADC,stimulationcircuitry, LMS-IIR filter and data transmission. Low-dropout regulators combined with the bandgap voltage circuitry generate 3 main supplies for proper chip operation, namely the core analog and digital supply voltages AVDD and DVDD (both equal to 1 V) in addition to the 3 V supplyvoltageAVDDST.SincethestimulationIDACoperateswithin3Vand0Vlimits,the tissue should be biased to half this range to achieve the maximum headroom for source and sink transistors in the IDAC. Hence, a unity-gain buffer is designed to set the body voltage 49 at V CMST = 1.5 V, which is half AVDDST. IDAC is designed with 7-bit binary-weighted PMOS and NMOS current sources, providing up to 127 µ A maximum current with 1 µ A resolution. 4.3.2 Recording Channel Circuitry The detailed block diagram of the REC block is shown in Fig. 4.12. All blocks are fully differential; but, for simplicity, the single-ended version is depicted. Each REC block in- corporates a front-end 2-stage LNA, followed by a programmable gain amplifier (PGA). As shown in Fig. 4.6(a), the first stage of the LNA has an inverter-based topology to provide a power-efficient low-noise front-end. It is followed by a Miller-compensated active-load differ- entialpairwithaswitchabletailcurrent. Tosavethechiparea,theLNAisreusedduringthe training phase to amplify the difference between the artifact and its replica, which requires a faster settling in this phase. Hence, the LNA can be switched between regular-bandwidth andhigh-bandwidthmodes. Thecommon-modefeedback(CMFB)circuitryisshowninFig. 4.7. ThePGAprovidesatunablegainandalsoactsasananti-aliasingfilterfortheADC,by limitingthesignalbandwidthtoabout10kHztorejecttheout-of-bandnoiseanddistortions [Fig. 4.6(b)]. The low-pass corner of the PGA is determined by the mid-band gain ( C 2 C FB2 ), transconductance of the OTA (g m2 ), and the capacitive load of the SAR ADC (C ADC ) as BW= g m2 2π C 2 C FB2 C ADC . The transconductance is tunable to meet the minimum bandwidth re- quirement for different gain settings. The output stage of g m2 accommodates a wide-swing differential output during the signal acquisition. To ensure that the PGA can maintain the maximumoutputswing(V FS =1V)intheavailabletrackingtimeoftheADC,whichisabout 70% of the sampling period in this design (T s =50µ s), the DC current of its output stage (I o ) should be at least C ADC V FS 2 0.7Ts , which requires I o >34 nA. The SAR ADC is implemented fully deferentially to eliminate any common-mode noise or interference coupled to the input and reference lines. A split-capacitor DAC is used to reduce the ADC area, as shown in Fig. 4.8(a). In the tracking phase (Φ track =1), the 50 Figure 4.6: Detailed circuitry of the AFE. (a) LNA and CDAC configuration (b) PGA (c) ADC driver. 51 Figure 4.7: CMFB circuitry for LNA (a) first stage and (b) second stage. 52 bottom-plate of the capacitors are all connected to the input voltage (V in+ and V in- ) while thetop-platesoftheMSB-sideareconnectedtothecommon-modevoltage(V REF /2). When the input voltage is sampled on the capacitors, the searching phase starts: The top-plate switch is opened (Φ track =0) and the bottom-plate of all capacitors is connected to V REF /2. The result of the comparison between the voltages of V c+ and V c- determines the MSB of the sampled data. Subsequently, the digital logic changes the status of the bottom-plate switches of the MSB capacitors to either V REF or GND depending the comparison outcome. This creates a charge redistribution among the capacitors, changing V c+ and V c- , as shown in Fig. 4.8(b). In subsequent comparison cycles, the remaining bits (MSB-1, ..., LSB) are found. AmathematicalillustrationoftheSARoperationisshownin [81]. Attheendofthe conversion, the 10 digital bits are serialized using multiplexers and flip-flops (FF) as shown in Fig. 4.9. The ADC comparator is implemented as a dynamic latch-based configuration to reduce the static current, as shown in Fig. 4.10(a). A pre-amplifier/buffer is added to serve two main purposes: (1) It reduces the kick-back noise coupled from the comparator input FETs backtotheoutputoftheCDACand(2)allowsthecomparatortoaccommodateawideinput dynamicrange(upto3V).Thebufferalsoslightlyhelpsreducingthecomparatoroffset. The offset of the comparator is estimated using the Monte-Carlo simulation. A differential ramp is applied to its input while the comparator clock is running at its nominal speed. The time point that the comparator output is flipped indicates the input voltage offset, as shown in Fig. 4.10(b). To obtain a more accurate statistical estimation of the comparator offset, the simulation was done for 40 Monte-Carlo runs to include process variations. The 3σ value of the offset was estimated as 0.4 mV Fig. 4.10(c). Since the artifact voltage may appear with different amplitudes at the input of each recording channel depending on the distance of the electrode to the stimulation site, each 53 Figure 4.8: (a) SAR ADC schematic. (b) Simulated SAR operation for one sample. Figure 4.9: ADC data serializer. 54 Figure 4.10: (a) Comparator schematic. (b) Test input and output waveforms to simulate the comparator offset. (c) Histogram of the offsets (Monte-Carlo simulation). 55 recordingchannelisequippedwithanindependentadaptivecancellationfilter. A10bbinary- weighted split-array capacitive DAC (CDAC) converts the digital filter output to a differ- ential artifact replica, which is applied to the LNA input terminals, as illustrated in Fig. 4.6(a). Since the digital blocks operate at 1 V, level-shifters are needed to provide 3 V control signals for driving the switches in the CDAC. The CDAC output capacitance at the virtual ground terminals of the LNA degrades the input-referred noise. Therefore, during the acquisition phase and in the absence of any stimulation signal, the CDAC capacitors can be open-circuited to improve the AFE noise performance. As mentioned before, digital level shifters are used to boost the control signals of the CDACs (in the ADC and at the front-end), from the core 1V to 3V. The level shifters are realized in a latch-based topology as shown in Fig. 4.11(a). Extra care should be taken whensizingthedevicestoensurethatthebottomNMOSpairisstrongenoughtochangethe status of the top PMOS latch. The functionality of the design was simulated across different process corners for the schematic versus the parasitic extracted circuit [Fig. 4.11(b)]. 4.3.3 Operation of the AFE with the Adaptive IIR Filter Weusedthesimplifiedtransferfunctionoftheelectrode-tissueinterfaceasoursystemmodel to be trained: H m (z) = b 0 +b 1 z − 1 1− z − 1 . The implemented adaptive algorithm adjusts the filter coefficients using the equation-error approach [82]. Such configuration guarantees global convergence as with an adaptive FIR filter. 4.3.3.1 Learning (Training) Phase During the training phase the PGA is disconnected, as shown in Fig. 4.12(a). The input voltage V in is directly buffered to the ADC through the ADC driver [Fig. 4.6(c)], gener- ating the quantized artifact signal a[n]. The unity-gain ADC driver is used to isolate the recording electrodes from the switching transients during the sampling period of the SAR ADC operation. The driver also removes the input common-mode component and provides 56 Figure 4.11: (a)Digitallevel-shifterschematic. (b)Functionalityacrossprocesscorners[ss: slow- slow, tt: typical-typical, ff: fast-fast (NMOS-PMOS), sch: schematic]. 57 a differential waveform at the ADC input. In this phase, the ADC operates with V reference = 3 V to accommodate the high-voltage artifact. Its sampling rate should match the clock frequency of the digital filter and the CDAC switching speed, which is set to f s,train = 78.4 kHz. This high sampling rate reduces the residual artifact at the AFE input below the saturation limit of the amplifier, as was derived in Eq. (4.2). Moreover, the chosen f s,train reduces the quantization noise power injected by the CDAC in the ADC’s Nyquist band- width (f < 10 kHz) during the acquisition phase. To accommodate a high slew-rate during comparison,theLNAisswitchedtothehigh-bandwidthmode. Itoperatesasapre-amplifier for the equation-error comparator, which generates the 1-bit equation-error e[n] based on the comparison between V in and V replica . To simplify the hardware implementation of the LMS algorithm, a sign-sign scheme is realized [73,74]. For each stimulator, the sign of each stimulation signal is represented with 2 bits ([s 10 , s 11 ] for stimulator 1 and [s 20 , s 21 ] for stimulator 2), to accommodate 3 possibilities of anodic (positive), cathodic (negative) and disabled current stimulation. All the mathematical operations are performed in a 2’s complementsystemtoaccommodatenegativenumbers. Toenablesimultaneouscancellation of2independentstimulationsignals,eachchannelhas2pairsof10bcoefficients[ b 10 ,b 11 ]and [b 20 , b 21 ], which are independently adapted to their corresponding stimulation signals s 1 [n] and s 2 [n]. In a general scheme with N stimulators, the coefficients are updated according to, b j0 [n] b j1 [n] = b j0 [n− 1] b j1 [n− 1] +µsign s j [n] s j [n− 1] e[n], (4.12) where j is the stimulator index (j= 1...N). In this implementation, the adaptation constant µ is set to 1 for hardware simplification. It should be emphasized that for a guaranteed coefficient convergence, the coefficients corresponding to each stimulator need to be trained separately, when all other stimulators are disabled. However, during the acquisition phase the stimulators can be activated simultaneously and there is no timing constraint. In the example shown in Fig. 4.12(a), [b 10 , b 11 ] are being adapted to [s 10 , s 11 ], while the second 58 stimulator is disabled, [s 20 , s 21 ]= 0. The artifact replica y[n] at each cycle is estimated by the summation of the delayed quantized artifact a[n− 1] and the digital filter output, according to, y[n]=a[n− 1]+ b j0 [n] b j1 [n] . s j [n] s j [n− 1] . (4.13) Since the adaptation constant is fixed, the training time scales linearly with the artifact peak-to-peak voltage, at a rate of 20 mV pp per stimulation pulse applied to a resistive load. For instance, for a 200 mV pp artifact, 10 stimulation cycles are needed to train the filter coefficients. 4.3.3.2 Acquisition Phase When the training phase is complete and the filter coefficients are adapted to their corre- sponding stimulation signals, the system enters the acquisition phase [Fig. 4.12(b)]. The IIR filter generates the artifact replica waveform in response to the stimulation signals, given by y[n]=y[n− 1]+ N X j=1 b j0,opt b j1,opt . s j [n] s j [n− 1], . (4.14) where [b j0,opt , b j1,opt ] are the converged filter coefficients. The LNA is switched back to the regular-bandwidth mode and the PGA is switched into the amplification chain, connecting the LNA output to the ADC. The equation-error comparator and the ADC driver are dis- abled and disconnected from the rest of the circuitry. In this phase, the sampling rate of the SAR ADC reduces to f s,acq = 19.6 kHz, which is sufficient to accommodate the neural signal bandwidth, while preventing any excess power consumption for digitization and data trans- mission. The ADC also operates with V reference = 1 V, which is sufficient to accommodate the amplified neural signal and the residual stimulation artifact. Figure 4.13showsasimulatedoperationoftheadaptivefilterwhenappliedtoaperiodic biphasic stimulation artifact. The residual artifact reduces after each cycle is reduced and 59 (a) (b) Figure 4.12: Front-endIIRLMSfilterprincipleofoperation. (a)Learningphase. (b)Acquisition phase. The disabled blocks are shown in a light gray color. 60 Figure 4.13: Simulation of the adaptive artifact canceler (a) Input-referred residual artifact voltage. (b) The LNA output voltage. reaches its minimum after about 20 cycles in this example. To ensure that the cancellation does not affect the quality of the neural signal, a pre-recorded neural signal was added to the artifact after the artifact learning phase, as shown in Fig. 4.14(b). It can be seen that in the absence of the cancellation [Fig. 4.14(c)], the output of the ADC (after off-chip software-based residual artifact subtraction) does not show any neural waveform due to the saturation of the amplifier. However, enabling the canceler maintains the recording system linearity and the neural spike is detectable at the output of the ADC, as shown in Fig. 4.14(d). 61 Figure4.14: Simulationoftheadaptiveartifactcancelertorecoveraneuralsignal(a)Stimulation current and artifact voltage. (b) Injected neural signal to the input. (c) Recording output when the canceler is OFF. (d) Recording output when the canceler is ON. 62 4.3.4 Clock Generation and Timing Circuitry The chip incorporates a digital relaxation oscillator which generates a nominal 20MHz clock signal, asshowninFig. 4.15(a). TheclockfrequencyinverselydependsontheR clk C clk time constant. C clk is implemented as a capacitor bank to make the clock frequency tunable and compensate for process variation. During the steady state, V y and V o are in complementary digital states (0V or 1V). In each clock phase, V x undergoes an exponential decay until it changes the status of the following inverter stage, which would invert the state of both V y and V o subsequently, as shown in Fig. 4.15(b). To provide the flexibility of using an external oscillator, the on-chip oscillator is power gated and a transmission gate disconnects it from the timing circuitry if needed (Fig. 4.16). The timing circuitry has clock dividers and delay elements to generate all the necessary control signals on chip. A timing diagram of the oscillator output at the startup is Fig. 4.15(c). 4.3.5 ESD Protection Circuitry Since the chip handles both low-voltage (1V) and high-voltage (3V) I/O pads, special care should be given to the electrostatic discharge (ESD) protection circuitry design. Double- diodesareaddedtoprovidelow-impedancedischargepathfromtheI/Opadstothepositive supply rail and from the ground line to the I/O pads, as shown in Fig. 4.17. Power clamps should also be added to provide discharge path from the supply lines to the ground. This implementation provides low-impedance discharge path if an ESD event happens between any two pads of the chip during the machine or human handling. 4.3.6 Test Chip and PCB To evaluate the performance of the critical building blocks of the system, the standalone AFE, timing circuitry and SAR ADC were facbricated on a test chip shown in Fig. 4.18. 63 Figure 4.15: (a) Digital relaxation oscillator. (b) Waveform of the oscillator internal nodes. (c) Oscillator startup as the supply voltage ramps up for different frequency settings. To avoid loading of the measurement devices on the performance of the amplifier, a unity-gain buffer is inserted after the PGA on-chip to drive the output pads. For linearity measurements (such as the total harmonic distortion or THD), and to guarantee that the 64 Figure 4.16: Timing generation circuitry. Figure 4.17: ESD protection circuitry strategy for analog and digital I/O pins. linearity of the full chain is determined by the main amplification stages, enough headroom from the supply rails needs to be maintained. To accommodate the signal upswing, the supply voltage of the buffer is increased to 3V. For the downswing, a super source follower (SSF) [83] is added to shift the DC voltage at the output of the PGA from 0.5 V to about 1.5 V, while maintaining the linearity of the measurement path, as shown in Fig. 4.19(a). The amount of the voltage shift is equal to V SG1 , and to ensure high linearity, V SG1 must be relatively independent of the input voltage. In this configuration, V SD1 is forced to be equal to V GS2 to mitigate the effect of channel length modulation. This ensures a relatively constantV SD across M1, and hence, avoltage shift thatis predominantly setby the currents 65 Figure 4.18: Test chip (a) micrograph and (b) block diagram. and sizes of M 1 and M 2 . The simulated AC response of the recording FE followed by the SSF and buffer is shown in Fig. 4.19(b), which shows that the SSF and buffer addition does not perturb the gain and bandwidth of the AFE under test. 66 Figure 4.19: (a) Schematic of the SSF and buffer. (b) Simulated AC response of the AFE+SSF+buffer. 67 Figure 4.20: SoC microphotograph. 4.4 Measurements 4.4.1 System Performance The integrated circuits (ICs) were fabricated in a 0.18µ m-CMOS process and the micropho- tographofthe SoC isshowninFig. 4.20.TheICswerepackaged inquadflatno-lead(QFN) packages and a custom-designed printed circuit board (PCB) connected the test and main chips with peripheral measurement devices and voltage regulators, as shown in Fig. 4.21. The SoC occupies 11.4 mm 2 of area and consumes a total of 206 µ W of power when all therecordingchannelsareintheacquisitionmodeandonestimulatorisdeliveringabiphasic 40 µ A peak current with cathodic and anodic pulse widths of 300 µ s and a period of 2 ms. The power consumption breakdown is shown in Fig. 4.22(a). The current consumption of different supply voltages in different operation modes is also plotted in Fig. 4.22(b). 4.4.2 AFE measurements TomeasuretheAFEdifferentialgain,anexternalunity-gaindifferentialamplifier(LTC6363- 1) converts a single-ended input signal to a differential waveform, which is applied to the LNA inputs on the test chip, as shown in Fig. 4.23(a). A pair of 2.5pF capacitors are 68 Figure 4.21: PCB carrying the test and main chips. attached to the PGA output which model the equivalent input capacitance of the SAR ADC. High-impedance probes are connected to the output buffers and the time-domain graphs are monitored on an oscilloscope [Fig. 4.23(b)]. To find the transfer function, a single tone signal is applied to the AFE input and its frequency is swept, while the amplitude of the output signal is measured (the peak output 69 Figure 4.22: (a) Chip total power consumption breakdown. (b) Supply voltage currents in different operation modes. Figure4.23: (a)Testbenchfornoiseanddifferential-modegainmeasurements. (b)Rawtransient output of the amplifier in response to a 10kHz input signal. should remain well below the saturation level of the amplifier to ensure the linearity of the recording chain). Fig. 4.24(a) shows the measured frequency response of the AFE (LNA in the regular-bandwidth mode+PGA) for different gain settings. To measure the noise performance of the AFE, both inputs of the LNA are short-circuited to the ground. Off-chip amplification stages are added to amplify the amplifier’s noise to dominate the noise floor 70 Figure 4.24: (a) AFE frequency response. (b) AFE input-referred noise for the maximum gain setting. Figure 4.25: Common-mode (CM), differential-mode (DM) and CM-to-DM transfer functions (simulated and measured). of the oscilloscope. The recorded waveform undergoes a Fourier transform, followed by a division by the amplifier’s gain, which yields the input-referred noise spectral density, as shown in Fig. 4.24(b). The AFE achieves a 9 kHz bandwidth, an integrated input-referred noise of 6.2 µ V rms and a common-mode-rejection-ratio (CMRR, defined as the ratio of the differential gain to the CM-to-DM conversion gain) of 43.2 dB at the maximum differential gain of 50.0 dB (Fig. 4.25). The parasitic extracted simulation suggested that the mismatch between the parasitic capacitance at the virtual ground of the LNA is the main reason behind the limited CM 71 Figure 4.26: (a) LNA schematic with parasitic capacitors at the virtual ground. (b) Para- sitic capacitance extraction of the layout. (c) CM-to-DM conversion gain of the schematic (sch), parasitic-extracted (pex) and schematic with added parasitic capacitors (sch+C par ). rejection of the design [Fig. 4.26(a)]. To verify this, the layout-extracted capacitance at the virtual ground of the LNA (C p,1 , C p,2 ) was found as shown in Fig. 4.26(b). Explicit capacitorswiththevaluesequaltotheextractedvalueswereaddedtotheschematic. Subse- quently, the LNA CM-to-DM conversion gain was simulated. The plots confirmed that after addingthecapacitorstothevirtualground, theCM-to-DMconversiongainoftheschematic and the parasitic-extracted layout matched, as shown in Fig. 4.26(c). To verify the simulation and measurement results, a simplified schematic of the LNA (Fig. 4.27) is analyzed here. We can write KCL at the virtual ground nodes of the LNA as sC 1 (V in − V g1 )=sC p V g1 +sC 2 (V g1 − V o1 ), (4.15) sC 1 (V in − V g2 )=sC p V g2 +sC 2 (V g2 − V o2 )+s∆ CV g2 . (4.16) 72 Figure 4.27: Simplified model of the LNA for CMRR analysis. The subtraction of the two equations yields V x =− ∆ C C 1 +C p +C 2 (1+A 0 ) V g2 , (4.17) where A 0 is the OTA’s open-loop voltage gain, V g1 − V g2 = V x and V o2 − V o1 = A 0 V x . Assuming ∆ C <<C p , V g2 ≈ C 1 C 1 +C p +C 2 V in . (4.18) 73 We can combine equations 4.17 and 4.18 to find the CM-to-DM conversion gain which can be approximated as A CM− to− DM ≈ 1 β ∆ C C 1 , (4.19) where β = C 2 C 1 <<1 is the feedback factor. The DM closed-loop gain of the LNA is given by A DM = A 0 1+βA 0 ≈ 1 β . (4.20) Hence, the CMRR which is the equal to A CM− to− DM A DM can be approximated as CMRR≈ ∆ C C 1 . (4.21) Using the values used in the design, β = 0.04, ∆ C C 1 = 0.008 and A 0 = 400, the estimated CMRR is 42 dB which agrees closely with both the simulated and measurement results. In future designs, a more careful layout of the LNA with a better routing symmetry of the virtual ground should achieve a higher CMRR. The AFE was originally designed to achieve sub-Hz high-pass cutoff frequency by using switchable pseudo-resistors around the g m cells [refer to Fig. 4.6(a)]. However, the n-well to p-substrate leakage current disrupted the feedback DC path around the LNA and PGA when the pseudo-resistors were enabled (V R = 1 V). For proper DC biasing, the pseudo- resistors had to be shorted (V R = 0 V), which resulted in a high-pass cutoff frequency of 200 Hz (sufficient to record the AP but not the LFP). The increase in the high-pass corner alsocontributedtothedegradationoftheinput-referrednoise. Forfuturedesigns, especially those with TΩ-range effective resistances, substrate leakage compensation techniques should be implemented [84]. The dynamic linearity performance of a stand-alone SAR ADC was measured in 2 different settings corresponding to the different modes of operation: (1) Sam- pling speed f s = f s,train and V reference = 3 V, (2) f s = f s,acq and V reference = 1 V. At the Nyquist frequency, the ADC maintains an SFDR and ENOB of 62 dB and 8.6b for f s,acq and 56 dB 74 and 7.6b for f s,train . The stand-alone CDAC could not be characterized with the available setup; however,theparasiticextractedsimulationsshowedthatitmaintainedaspurious-free dynamic range (SFDR) of 68 dBFS for a 10 kHz output signal. 4.4.3 ADC measurements The test single-tone signal is generated from an arbitrary function generator (AFG3252) which is fed into a differential driver (LTC6363-1) to generate a fully differential waveform centered around a common-mode voltage (either 0.5V or 1.5V depending on the mode of the operation), as shown in Fig. 4.28(a). An anti-aliasing RC LPF with a 10.6 kHz corner frequency is added to reject the out-of-band noise. The ADC samples the data and sends the serial data out in a packet with fixed preamble and postamble bit patterns (these extra bits are added to highlight the start and end of a digitized sample). A transmit clock is also generated on-chip which is synchronized with the transmitted data and its rising edge can be used by an external circuitry to sample the data line. An oscilloscope with an internal storage of 1M points (MSO 2024) was used to acquire the ADC output and transfer the recorded waveform to a PC for data analysis with MATLAB. There are two methods to provide the core clock for thechip during the characterization. Initially, the on-chip oscillator was used to generate a 18 kHz sampling clock. A 995mV p , 1 kHzsignalwasappliedtotheADCinput(V REF =1V)anda2048-pointfast-Fourier-transform (FFT) of the ADC output was calculated, which is shown in Fig. 4.28(b). The FFT shows a spectral leakage from the fundamental tone to the adjacent frequency bins, which happens due to non-coherent sampling. To remove the spectral leakage or the skirt, FFT should be computed in a window that encompasses an integer number of the input signal cycles, which ensures periodicity (coherent sampling). In a second try, the on-chip oscillator was disabled and the second channel of the AFG3252 was used to apply a 20 MHz clock into the chip, which creates a 19.53 kHz sampling clock. A 1.6785 kHz input signal was applied to the ADC and a 128-point FFT of its output was calculated over a duration exactly equal to 75 Figure 4.28: (a) Test bench for ADC characterization. Fourier transform of the ADC output under (b) non-coherent sampling and (c) coherent sampling. 76 Figure 4.29: ADC output spectrum across different input frequencies. 11 periods of the input signal [Fig. 4.28(c)]. It can be observed that coherent sampling removes the spectral leakage and yields a clean FFT plot. Therefore, the characterization of the ADC and the rest of the system was performed using the off-chip core clock. The frequency of the input signal to the ADC was swept and the output spectrum was recorded (Fig. 4.29). From the FFT plots, the signal-to-noise-and-distortion ratio (SNDR) and the effective-number-of-bits (ENOB) were calculated, which are compared with simula- tion results in Fig. 4.30 for different sampling rate and full-scale voltages. 4.4.4 Stimulation circuitry A7-bitNMOSbinary-weightedcurrentDACgeneratesaprogrammablesinkcurrent[Fig.4.31(a)] anda7-bitPMOSarraygeneratesasourcecurrent. Acascodeconfigurationisusedtoboost 77 Figure 4.30: Simulated and measured SNDR and ENOB for (a) f s = 19.53kHz, V REF =1V, (b) f s = 78.12kHz, V REF =3V. the output impedance. This architecture also improves the dependence of the output cur- rent on the load voltage as shown in Fig. 4.31(b). The current DACs can generate a fully programmable biphasic waveform as shown in Fig. 4.31(c). Static nonlinearity of the current DACs of both stimulators was characterized and sum- marized in Fig. 4.32. Maximum measured DNL/INL was 0.25/ -1.4 bits. 4.4.5 Stimulation Artifact Canceler Performance 4.4.5.1 Single Channel Stimulation Depending on the relative location of stimulation and recording sites in the tissue, the stimulation artifact can couple into the amplifier input in 3 different modes: differential, common-mode and single-ended, as demonstrated in Fig. 4.33. In the following benchtop characterization, an off-chip circuitry was implemented to artificially generate each mode, as shown in Fig. 4.33. 78 Figure 4.31: (a) Binary-weighted current DAC. (b) The variability of the output current versus the load voltage. (c) Current waveform programmability. Figure 4.32: Characterization of both stimulators on the chip (a) Output current vs. input code. (b) DNL/INL. 79 Figure 4.33: Different modes of stimulation artifact coupling into the amplifier input (a) Differ- ential (b) Common-mode (c) Single-ended. The off-chip circuitry that generates each mode is also included. ThefunctionalityoftheadaptiveIIRfilterwasfirstinvestigatedinthepresenceofsingle- ended artifact generated from a single-channel stimulation, as shown in Fig. 4.34(a). An arbitrary function generator (AFG) generated a 400 µ V p , 3.05 kHz sinusoidal signal x(t) (mimicking the neural signal), which was applied to all the recording channels with the AFE gain programmed to 27.6 dB. With this setting, the signal-to-noise ratio (SNR) of the recorded signal is about 10 dB, when averaged across channels. In the training phase, the AFG was disconnected and the stimulation signal (stim en) enabled stimulator 1 to apply a balanced biphasic 19 µ A stimulation current, with 330 µ s duration per phase and repetition rate of 140 Hz, into an off-chip 9.5 kΩ resistor to generate a biphasic artifact waveform. The generated artifact waveform a(t) was fed to the recording channels and all the 8 REC blocks were allowed sufficient time for training their IIR filter coefficients during Φ train . At the beginning of the acquisition phase during Φ acq1 , the chip output, which carried the residual artifact V residue , was stored in MATLAB. During Φ acq2 , which was the final phase of the testing cycle, the AFG and stimulator 1 were both active and x(t) was summed with a(t) artificially using an off-chip op-amp circuitry shown in Fig. 4.34(b). The stored V residue was 80 Figure 4.34: (a) Measurement setup for testing the performance of the artifact canceler. (b) Off-chip voltage summation circuitry. (c) Timing diagram of the successive operation cycles and phases. subtracted from the chip output (V acq ) and divided by the system AFE gain in this phase to recover the input-referred sinusoidal signal (V rec ). The resultant artifact and input sinusoidal signals are depicted in Fig. 4.35(a)-(b). The goaloftheexperimentwastorecoverthe3.05kHzsignalwithminimaldistortion,whilemain- taining the signal amplitude. The functionality and efficacy of the implemented front-end adaptive cancellation was investigated by comparing the recovered signal when the canceler IIR filter was enabled (canceler ON) versus when the filter was disabled (canceler OFF), while the back-end cancellation remained active in both cases. Fig. 4.35(c) demonstrates that the front-end IIR filter is mitigating the artifact, resulting in a minimal V residue . The ADC output during the acquisition phase shows a reduced artifact on top of the sinusoidal signal [Fig. 4.35(d)]. The recovered signal in Fig. 4.35(e) shows that without the front-end 81 canceler, thesinusoidalwaveformiscompletelylostinthebackgroundnoiseduringthestim- ulation phase. A time window of 32 samples, equivalent to 1.6 ms starting from the onset of thestimulationsignal, waschosenforspectralanalysis. BycomparingtheFouriertransform of the recovered signals in Fig. 4.35(f), a complete recovery of the fundamental tone was observed when the IIR filter was active. When the front-end canceler is off, the large-swing artifact saturates the LNA, which results in increased distortion and failure to detect any underlyingsignal. Itisimportantto notethattheselected 1.6msdurationfor thetimewin- dowisabout theaverage durationofaneural spike. Hence, withoutthe canceler, anyneural spike which is coincident with the stimulation signal could be easily lost in this scenario. The same characterization steps were performed for differential and common-mode stim- ulation artifacts as well. To evaluate the efficacy of the proposed cancellation scheme in suppressing different artifact intensities, the stimulation current was swept from 1 µ A to 35 µ A, while the load impedance was an off-chip 9.5 kΩ resistor. Figure. 4.36(a) plots the mea- suredsystemeffectivegain(definedastheratiooftheintensityoftherecoveredfundamental tone to the input signal) as a function of the artifact peak-to-peak voltage. To quantify the signal distortion and noise introduced by the artifact, the SNR was also measured using the frequency spectrum of the recovered signal, which is shown in Fig. 4.36(b). Both the effective gain and SNR metrics were measured for all the 8 channels and the average val- ues with ± 1σ variation across the channels are shown in Figure. 4.36. For differential and single-ended modes, at medium-level artifact amplitudes (< 200 mV pp ), the effective gain of the system is slightly improved (< 2 dB) when the front-end canceler is enabled. SNR also shows similar behavior with an improvement of < 4 dB for small artifact amplitudes. As the artifact level increases to about 400 mV pp , for both the single-ended and differential modes, the amplifier is significantly saturated and the effective gain drastically drops by about 10 and 6 dB, respectively. However, enabling the canceler restores the effective gain and prevents signal attenuation. Moreover, the front-end canceler also improved the SNR by more than 8 dB for artifact amplitudes above 200 mV pp . Assuming a 0-dB SNR is the 82 Figure 4.35: (a)Stimulationartifact. (b)Single-toneinputsignal. (c)Residualartifactwaveform recorded during Φ acq1 . (d) Recorded signal contaminated with the residual artifact during Φ acq2 . (e) The recovered amplified input signal (The time window that the FFT is performed on is shown with a red rectangle). (f) Frequency spectrum of the recovered signal. The FFT of the recorded signal in the absence of the stimulation signal is also plotted. The representative waveforms are shown for channel 0. limit for a likely detection of spikes [85], these measurements suggests that the canceler can recover 400 µ V high-frequency signals in the presence of 600 mV pp single-ended and > 700 mV pp differentialartifacts. Preservingthegainforlargeartifacts( >700mV pp )alsosuggests that the canceler is suppressing the artifact and preventing the saturation of the amplifier. In this region, the SNR degradation can be attributed to the increased noise and distortion introduced by the cancellation CDAC. All these measurements were performed under the 83 challenging scenario of exact alignment of the artifact with the signal. As discussed earlier, inthecurrentimplementation,thecancellationfiltercannotcaptureandcancelthecommon- mode artifact. The only suppression that occurs is the capacitive division at the LNA input. Common-mode artifacts larger than 100 mV pp degrades both the gain and SNR. Any CM stimulation artifact converted to a differential mode due the low CMRR of the front-end, will be automatically included in the pattern stored for the residual artifact in the back-end during the acquisition of the residual artifact [Φ acq1 in Fig. 4.34(c)]. During the acquisition phase, this stored waveform, which includes both the residual differential artifact and the CM-to-differential converted component of the stimulation artifact, is subtracted from the recorded signal and cancels the CM-to-differential converted artifact. In a closed-loop neural interface, recording an evoked potential is critical since it carries information about the response of the neuronal network to the stimulation pulse. An evoked neuralresponsecanoccurasearlyas1msfollowingthestimulus [86]. Therefore,itbecomes critical for the front-end amplifier to recover from saturation and restore its linearity soon after the stimulation phase. To investigate the canceler’s performance in such scenarios, a 2.5 V pp artifact was emulated (30 µ A stimulation current delivered to a 41 kΩ resistor) and applied to the recording channel inputs in a single-ended configuration. The acquired waveformattheADCoutputandtherecoveredsignalsareshowninFig.4.37(a-b). Itcanbe observed that the amplifier recovery from saturation happens almost two times faster when the canceler is active. Fourier transform of sliding time windows of the recovered signals also suggest that during window B, the amplifier is still recovering from a deep saturation state in the absence of the front-end cancellation [Fig. 4.37(c)]. In the same time window, the canceler has recovered both the effective gain and SNR, as shown in Fig. 4.37(d-e). This suggeststhatifaneuralspikehappensjustafterthestimulationsignal,withoutthefront-end cancellation, it can go undetected. The dependence of the IIR filter coefficients on different stimulation parameters was also studied using the test bench in Fig. 4.34(a). Fig. 4.38(a) shows a linear relationship between 84 Figure 4.36: (a) Effective gain and (b) SNR as a function of the input artifact peak-to-peak voltage, measured for single-ended, differential and common-mode artifact waveforms. The error- bars show± 1σ variation across the 8 recording channels. 85 Figure 4.37: Effect of the canceler on the amplifier recovery time from saturation due to a 2.5 V pp artifact (a) Recorded signal contaminated with the residual artifact (Sliding time windows are labeled as A-D). (b) Recovered signal. (c) Frequency spectrum of the recovered signal in different time windows. (d) Effective gain and (e) SNR measured in different time windows following the stimulation event. the adapted filter coefficients and the artifact amplitude, as is suggested by (4.13). On the other hand, the coefficients have no significant dependence on the stimulation current duty cycle and pulse width, as can be observed in Fig. 4.38(b)-(c). Since the IIR filter is 86 Figure 4.38: Dependence of the IIR filter coefficients on the stimulation signal parameters. (a) Amplitude (b) Duty cycle (c) Pulse width. based upon the empirical model in (4.1), it resembles an LTI RC network and is therefore independent of the timing properties of the applied balanced biphasic stimulation signal. 4.4.5.2 Dual Channel Stimulation In a high-density neural interface platform, concurrent multi-channel neural stimulation is inevitable in order to investigate how neuronal populations respond to timing differences of such stimuli and map the brain networks in more detail [87]. The past implementations of the adaptive-filter techniques for artifact mitigation [73,74] were designed to train the filter coefficients to only 1 independent stimulation channel. To demonstrate cancellation of an artifact due to the simultaneous operation of independent stimulation channels, the 2 on-chipstimulatorswereactivatedandprogrammedinsuchawaythattheiroutputcurrents overlap in time. Stimulator 1 was connected to an RC load and stimulator 2 was tied to a resistiveload. The2artifactsandasinusoidalsignalweresummedoff-chip,andwereapplied to all the 8 recording inputs as shown in Fig. 4.39. The stimulation currents (I stim1 =19 µ A and I stim2 =10 µ A, with 330 µ s pulse width) and the resultant artifact are shown in Fig. 4.40(a). The recovered signal and its Fourier transform are shown in Fig. 4.40(b) and (c) respectively. The effective gain increased by 87 Figure 4.39: Test bench for measuring the cancellation performance in the presence of 2 overlap- ping stimulation signals. more than 10 dB when the front-end canceler was activated, suggesting that the canceler was able to keep the AFE in its linear region of operation. Fig. 4.40(d) shows the effective gain and SNR for the 8 recording channels. The average effective gain was boosted from 18.1 to 27.6 dB. The SNR was also improved from -3.8 to 5.0 dB in average. 4.4.5.3 In Vitro Measurements Figures 4.41 and 4.42 show the in vitro measurement setup for testing the performance of theartifactcancelerin1xphosphate-bufferedsaline(PBS),whichcanmimicthebraintissue electricalproperties. Ametallicwirewith<1mmexposedtipwasinsertedinthesolutionfor injectingthedesiredsignalintothesolution(asingletoneat3.05kHzinthefirstexperiment and a pre-recorded neural waveform in the second experiment). The solution was biased to V CMST via another piece of wire with a few cm of exposed tip. Two sets of flexible parylene- based micro-electrode arrays (MEA) with platinum disc electrodes [79,88,89] were used to interface the 8 recording channels with the solution. The microelectrodes had different 88 Figure 4.40: (a) Stimulation currents shown on top of the resultant artifact waveform. (b) The recovered amplified input signal (shown for channel 0). (c) Frequency spectrum of the recovered signal. (d) Effective gain and SNR measurement of the recovered signal across different channels. exposed diameters ranging from 30 to 160 µ m. A biphasic 35 µ A stimulation current with 330 µ s pulse width was injected into the solution via the largest electrode (diameter=210 µ m). The artifact waveforms received at different electrodes are shown in Fig. 4.43(a). A counter-intuitive observation is that channel 0, which is farther away from the stimulation electrode compared to channel 2, experiences a larger artifact. This suggests that, as we mentioned earlier, the artifact coupling mechanisms and pathways are not limited to the solution and tissue itself, but they may arise from the hardware and device properties. The recovered signal and their corresponding frequency spectrum are also shown in Fig. 4.43(a). For channels 0 and 1 which experience the largest artifacts, the cancellation scheme recov- ered the underlying signal, with 10 dB improvements in both gain and SNR, as shown in Fig. 4.43(b-c). As the amplitude of the artifact reduces below 10 mV pp , which is the case for 89 Figure 4.41: In vitro measurement setup for testing the performance of the artifact canceler in 1x PBS. The ac-coupling capacitance C ac = 220nF prevents any DC leakage current through the electrodes, which can potentially deteriorate the electrode performance or even result in its failure. 2 microelectrode arrays were used in this testbench to investigate the artifact coupling in different configurations. channels 3-7, the amplifier is not saturated with the artifact and the cancellation circuitry has negligible effect on the system performance. Finally, pre-recordedneuralspikesweregeneratedandinjectedintothesolution, without changing the existing test bench. Therefore, the artifact waveforms are the same as those shown in Fig. 4.43(a). The output of the function generator and the overlapping stimulation current is shown in Fig. 4.44(a). Similar to the single-tone experiment, for channels 0 and 1 the neural signal is lost due to the amplifier saturation, as shown in Fig. 4.44(b). However, the cancellation filter can recover the neural spike in these channels, which experience the largest artifact levels (up to a 900 mV pp artifact). 90 Figure 4.42: Photograph of the in vitro test in PBS. Table 4.1 compares the performance of the chip with the state-of-the-art bidirectional neural interfaces. Since the performance of the artifact cancellation depends on a diverse set of experimental conditions such as the stimulation parameters (current intensity, pulse duration and frequency, charge balancing, etc), the electrode impedance, hardware setup and the time window that the spectral analysis is performed, it may be hard to provide a faircomparisonbetweendifferentarchitecturessolelybasedontheirmaximumpeak-to-peak artifact level handling. Nonetheless, with the presented measurement setup and conditions, the implemented SoC suppresses stimulation artifacts with amplitudes measured up to 700 mV pp , while maintaining competitive noise and power performance. About half of the area of the recording channels is occupied with the digital circuitry. Implementation in a more advanced node and utilizing an automated logic synthesis tool may potentially shrink the area of the digital blocks and routing. Moreover, for an area-optimized design, multiplexing ADCs between channels should be considered. In fact, it may be possible to integrate 91 Figure 4.43: Performance of the canceler on a single-tone signal in vitro. (a) Stimulation artifact waveform, recovered signal and its frequency spectrum cross different channels. (b) Effective gain and(c)SNRacrossdifferentchannels. Theinputartifactamplitudeisalsoshownforeachelectrode. the cancellation technique discussed here in a fully digital front-end, following the trends suggested in [90]. The 2-tap IIR filter implementation demonstrated in this work can potentially reduce the silicon area needed for storing the filter coefficients, compared to an FIR implementation with 30 or more taps. Inascaled-upsystemwithN recordingandM stimulationchannels,theproposedscheme requires storing 2MN IIR digital coefficients, which can be conveniently accommodated by thetechnologyscaling. Alltherecordingchannelscanbetrainedsimultaneouslywithrespect 92 Figure 4.44: Performance of the canceler on a pre-recorded neural signal in vitro. (a) The neural signal generated by a function generator. The timing of the stimulation current is also shown. (b) Recovered signal across different channels in 3 conditions: stimulation OFF, stimulation ON + canceler OFF, stimulation ON + canceler ON. The test bench and the artifact levels are the same as the in vitro single-tone test. to each stimulation channel, which adds up to a total training time of MI stim Rm f stim (10 mV cycle ) , where f stim is the repetition frequency of the stimulation current waveform (cycles/s), R m is the series resistance in the empirical model in Fig. 4.1(a), and I stim is the stimulation current. 93 Table 4.1: Performance Summary and Comparison with the State-of-the-art Bidirectional Neural Interfaces If the stimulation artifact shows an LTI response in the target in vivo environment [72], the coefficients can be trained with a scaled-down stimulation current to prevent an unde- sirable neural response. Moreover, the decreased stimulation intensity carries an additional 94 advantage of reducing the training time. During the learning phase, the frequency of the stimulation signal can also be increased to further shorten the training time. During the acquisition phase, the coefficients should be linearly scaled up with the same ratio as the stimulation currents are scaled [Fig. 4.38(a)], and the stimulation pattern can be tuned to the desired duty cycle and pulse duration without the need to retrain the filter coefficients [Fig. 4.38(b)-(c)]. This was verified experimentally in the same in vitro setup as before (Fig. 4.41) but with a larger ground electrode. The recording channels were initially trained to a stimulation current of 20 µ A with a pulse width of 100 µ s applied at a rate of 1.22 kHz. In the acquisition phase, the stimulation current was doubled to 40 µ A, while the pulse width and frequency were tuned to 400 µ s and 152 Hz respectively, as demonstrated in Fig. 4.45(a). To test the scalability of the canceler as was discussed before, the trained coefficients were multiplied by 2 and the performance of the artifact cancellation to recover a single-tone signal was measured [Fig. 4.45(b)-(c)]. The response of the canceler directly trained to the scaled-up current was also measured for comparison. Comparing the gain and SNR of the recovered signal in Fig. 4.45(d) shows that a linear scaling of the filter coeffi- cients is sufficient to cancel the artifact generated by a stimulation current with different amplitude, pulse duration and duty cycle. This suggests that the stimulation parameters can be tuned on-the-fly without the need to retrain the filter coefficients of the canceler. 4.5 Conclusion A multi-channel bidirectional neural interface with an adaptive stimulation artifact canceler was implemented in a 180-nm CMOS process. The fabricated SoC demonstrated a 2-tap IIR filter, which was trained with a sign-sign LMS algorithm and could extend the dynamic range of the existing neural recording front-ends by accommodating stimulation artifacts up to 700 mV pp while retaining competitive noise and power performance. The canceler could also reduce the recovery time of a saturated front-end amplifier from a 2.5 V pp artifact by 95 Figure 4.45: Scalability of the IIR filter output in response to stimulation with different param- eters in vitro. (a) Stimulation current and artifact during training and acquisition. (b) Recovered signal in 3 conditions: canceler OFF, canceler ON + filter retraining, canceler ON + coefficient scaling. The FFT window is highlighted with a shadow. (c) Frequency spectrum of the recovered signal. (d) Performance summary of the artifact cancellation scheme. The representative plots are from channel 0. a factor of 2, which allows for the detection of a fast evoked potential. The implemented front-end canceler could mitigate up to 2 concurrent and independent stimulation artifacts appearing on all the 8 recording channels. The IIR implementation of the active filter significantly reduced the required number of filter coefficients compared to an FIR filter, which can potentially lead to a reduction in the computational power consumption and chip area for local storage of the filter coefficients. Moreover, the IIR filter coefficients are independentofthetimingpropertiesofthestimulationcurrent,whiletheyscalelinearlywith thestimulationamplitude. Thisallowsfortheon-the-flytuningofthestimulationwaveform without the need to retrain the filter coefficients. However, there are certain shortcomings associated with this approach: (1) buffer introduces gain error that degrades the artifact estimation precision, (2) training time is artifact dependent, (3) the filter implementation 96 can only accommodate scenarios where a symmetric biphasic stimulation current is applied to a medium with a first-order transfer function (Randles model). 97 Chapter 5 Multi-Point Stimulation Artifact Cancellation The existing front-end cancellation techniques provide a limited artifact suppression (< 40 dB) which reduces a 1000-mVpp artifact to about 10-mVpp swing. The LNA amplifies this residual artifact, which is about 1-2 orders of magnitude larger than the neural signals, and can potentially saturate the later amplification stages (such as the PGA) in the recording chain, as shown in Fig. 5.1(a). To maintain the linearity of the recording chain throughout the amplification stages, the remaining artifact should be suppressed at the intermediate nodes,asshowninFig. 5.1(b). Thistechniquerequiresanalgorithmthatinitiallyestimates theartifactwaveformateachofthecancellationpointsinthesystem. Assuggestedbyinvivo experiments [72],thestimulationartifactismostlytime-invariantduringagivenstimulation session (it is not expected to have the geometric relationships among electrodes in the tissue vary significantly over time). Moreover, the timing of the artifact is predictable because the bidirectional system generates the corresponding timing for the stimulation circuitry. Therefore, a simple method to cancel the artifact would be to (1) quantize and store the exact shape of an artifact event (estimation phase), and (2) generate an artifact replica, whichistime-alignedwiththestimulationsignal. Thisreplicaissubtracteditfromthesignal contaminated with the artifact waveform (cancellation/acquisition phase), as illustrated in Fig. 5.2. A straightforward method to quantize the artifact waveform is to employ an ADC to digitizetheartifactwaveforma(t)andstorethequantizeddataw[n]inamemory. Avoltage 98 Figure5.1: Conceptualdiagramof(a)one-pointand(b)two-pointartifactsuppressiontechniques. Figure 5.2: Concept of artifact waveform storage and cancellation. 99 buffer is needed to prevent any distortion of the artifact waveform by the ADC sampling operation, as shown in Fig. 5.3(a). In the cancellation phase, A DAC converts the digital data into an analog representation of the artifact replica y(t), which is subtracted from the a(t) at the canceling point and produces a residual error e(t), which is amplified and propagated through the recording path. In a physical implementation, there are certain nonidealities that may limit the performance of this cancellation scheme. As shown in Fig. 5.3(b), the buffer and DAC can introduce gain errors ( ε 1 and ε 2 respectively) in the system, andtheADCaddsquantizationnoiseq[n]. Theeffectofthesenonidealitiesontheestimation error can be calculates as follows w =a(1+ε 1 )+q, (5.1) y =(1+ε 2 )w, (5.2) e≈− a(ε 1 +ε 2 )− q(1+ε 2 ). (5.3) This suggests that the estimation error has an artifact-dependent component and a term that is determined by the ADC quantization noise. We can modify the scheme by removing the voltage buffer, and bringing the DAC and recording amplifier into the quantization loop as shown in Fig. 5.4(a). The loop starts with a coarse approximation of the artifact and during successive approximations, a finer estimate is achieved. In this configuration, instead of using an explicit multi-bit ADC, a two-level quantizer (comparator) is employed which determines the sign of the amplified estimation error Ge(t) in each approximation, where G is the gain of the amplification stage. Assuming G >>1, the estimation error can be derived as y≈ a+ q(1+ε 2 ) G , (5.4) e≈ − q(1+ε 2 ) G . (5.5) 100 Figure 5.3: (a) Direct quantization of the artifact. (b) Nonidealities added to the system. Red dotted lines are active only during artifact estimation. 101 Figure 5.4: (a) Closed-loop artifact quantization. (b) Nonidealities added to the system. Red dotted lines are active only during artifact estimation. 102 Figure 5.5: Conceptual block diagram of the proposed two-point stimulation artifact cancellation technique. The gray components are active only during artifact estimation. Comparison of ( 5.3) and ( 5.5) suggests that the closed-loop artifact quantization is a better choice since it eliminates the input-dependent error term and scales down the quanti- zation noise by the gain of the amplifier. The remainder of this chapter discusses the design and physical implementation of a two-point stimulation artifact cancellation scheme, which employs a closed-loop artifact estimation technique at each of the cancellation points. 5.1 Circuit Implementation 5.1.1 Two-Point Artifact Cancellation The concept of the proposed 2-point cancellation technique is shown in Fig. 5.5. The first stage estimates the artifact waveform a(t) and subtracts a coarse approximation of the artifact (y1) from the received signal at the input of the low-noise amplifier (LNA). At this stage, the input artifact is sampled and quantzied at a rate f s,FE equal to four times the Nyquist rate of the neural signal (f s,Nyq =19.5 kS/s) to accommodate the high-frequency components of the stimulation artifact. The residual artifact is subsequently amplified in the continuous-time (CT) domain, low-pass filtered and sampled at f s,Nyq , which takes the signal to the discrete-time (DT) domain. The residual artifact a res [n] in each contaminated sampleisestimated(y2)andsubtractedfromthesampledsignalattheinputoftheswitched- capacitor programmable-gain amplifier (SC-PGA). 103 Figure 5.6: Simplified block diagram of the implemented 4-channel bidirectional interface with two-point artifact cancellation scheme (PGA: programmable gain amplifier, BUF: buffer). Consequently,theoutputoftheSC-PGAcarriesthesamplesoftheamplifiedneuralsignal with minimal amount of residual artifact to a 10b successive-approximation register (SAR) ADC for quantization. Moving from CT to DT signal conditioning allows for time-sharing the second-point cancellation and ADC among multiple recording channels. The proposed two-point cancellation technique was implemented in a CMOS chip with 4 recording and 4 stimulation channels as shown in Fig. 5.6. The details of the artifact estimation and cancellation algorithm, circuitry of the recording amplifiers, and current stimulator will be discussed in the following sections. 5.1.2 SAR-based Artifact Estimation Algorithm A SAR-based algorithm is proposed for both the CT and DT estimation of the artifact, as showninFig. 5.7(a). Atthebeginningoftheestimationphase,thefront-endCTestimation loop is enabled, while the back-end DT loop is disabled. The desired stimulation signal is periodicallyappliedtothetissue,whichcreatesaperiodicartifactwaveforma(t). Inthefirst stimulation cycle, a comparator detects the sign of the consecutive samples of the artifact (a[1], a[2], ..., a[64]), which determines the status of the most significant bit (MSB) of each 104 Figure 5.7: (a) SAR-based artifact estimation algorithm. (b) An example of the SAR operation to quantize an artifact sample. sample (a 1,9 , a 2,9 , ..., a 64,9 ). During the second stimulation cycle, a 10b capacitive DAC (CDAC 1) reconstructs the first estimate of the artifact (which only includes the MSB of the samples) and subtracts it from the received artifact. The LNA amplifies the estimation error and feeds it back to the comparator to determine the MSB-1 bits (a 1,8 , a 2,8 , ..., a 64,8 ). 105 Figure 5.8: LNA model during the artifact estimation and cancellation. This loop operates for 10 stimulation cycles to determine all the 10 bits of the artifact samples, as shown in Fig. 5.7(b). Then, the CT estimation loop is disabled, while the artifact template (y1) that is stored in an on-chip memory subtracts the coarse estimation of the artifact from the original artifact waveform. Subsequently, the DT estimation loop is initiated to create a template from the amplified residual artifact samples a res [n]. Using the same SAR-based algorithm, after 10 stimulation cycles, 16 samples of the residual artifact (perrecordingchannel)areestimatedandstoredinthememorywith10bresolution. During the signal acquisition phase, both the estimation loops are disabled, while the CDAC 1 and CDAC 2 cancel the artifact in two points along the signal amplification chain. Aperiodicartifactwaveforma(t)attheLANinputmaycontainaDCcomponenta DC (t) (Fig. 5.8), which gets rejected by the high-pass response of the LNA and only the AC component a AC (t) is amplified to G LNA a AC (t) as shown in Fig. 5.9. Examining the a AC (t) waveform suggests that the artifact is not limited to the duration of the stimulation current pulse (t 2 -t 9 ) and it contaminates all the data samples. To determine the number of the samples required for estimating the artifact waveform, two cases are discussed here. In case 1, a AC (t) is quantized and stored for 11 consecutive samples [y 1 (t)], starting from t 1 , which is a clock cycle before the beginning of the stimulation current pulse I STM (t) at t 2 . In this example, t 11 is the time when the tail of the artifact settles, which happens about two clock cycles after the end of the stimulation pulse at t 9 . The estimation error e(t) shows that the artifact is suppressed during the t 1 -t 11 period, but for the rest of the interpulse interval after 106 Figure 5.9: The effect of DC removal on the artifact waveform and the length of the artifact estimation required for sufficient cancellation. t 12 , the artifact remains uncanceled. However, the LNA removes the DC component of e(t) and causes an upward shift in its AC component e AC (t), which introduces additional error in the t 1 -t 11 interval. Therefore, to ensure that e(t) does not contain a DC term after the cancellation, y 1 (t) should be extended to contain all the samples of a AC . This can be readily achieved by 107 replicating the last sample which was estimated when the artifact was settled (at t 11 ) for the rest of the interpulse interval (t 12 -t 19 ), as shown for case 2 in Fig. 5.9. The approach of reusing the last sample to cancel the remaining artifact in the interpulse interval carries two advantages: (1) It eliminates the need for additional memory space to store the samples during the full interpulse interval and (2) it avoids potential signal loss. Since the artifact is estimated when the electrodes are implanted in the tissue, a correlated neural spike or evokedpotentialmayoccurafterthestimulationpulse. Thus, storingandsubtractingalong time-window of the waveform as an artifact template can potentially remove the underlying neural response (unless there is a filter that detects and removes the neural signal from the storedartifactwaveform). Theseconstraintsimposeanupperlimitonthemaximumnumber of artifact samples that can be stored. Artifact estimation and storage for a duration less than 1 ms should be short enough to avoid the inclusion of any evoked neural spike [91]. Nonetheless, there may be scenarios that the artifact waveform does not settle for at least a few ms after the stimulation pulse (such as during a slow discharge of the residual charge on the stimulation electrode with a time constant of R s C DL ). This necessitates quantization and storage of the samples for a longer duration which can potentially include evoked neural responses. In such scenarios, a reduced stimulation current (e.g. four times less than the intendedintensity)whichdoesnotexcitethenearbytissuemaybeappliedduringtheartifact estimation phase. Then, during the acquisition phase, assuming that the tissue behaves as a linear system, the estimated artifact can be scaled up with the same proportion as the stimulation current. An example of such scenario is shown in Fig. 5.10. To maintain the effective resolution of the second-point cancellation, a PGA can be used after the LNA to compensate for the reduction in the artifact intensity during the second-point artifact estimation [G PGA =4 during artifact estimation as shown in Fig. 5.10(a)]. In the acquisition phase, when the artifact is scaled up (in this example by a factor of four), the G PGA is reduced to 1 as shown in Fig. 5.10(b). This approach preserves an effective 2-bit of the CDAC 2 resolution for 108 Figure 5.10: (a) Stimulation current scaled down during artifact estimation. (b) Stimulation current scaled up to the desired value during the normal operation. artifact cancellation. This technique can also be used if the excitation of the neural tissue during the artifact estimation is not desirable. The physical implementation discussed in this chapter does not include the digital multiplier for scaling up the first-point estimated samples [Fig. 5.10(b)]. 5.1.2.1 First-Point Artifact Estimation and Cancellation In general, the stimulation artifact that is coupled to the differential input of the front- end (FE) has both common-mode (CM) and differential-mode (DM) components. The CM componentcanreadilyreachseveralhundredsofmV,perturbthebiasingoftheFEtranscon- ductance cell of the LNA (g m1 ), and degrade the linearity (Fig. 5.11). 109 Figure 5.11: Problem of CM stimulation artifact remains unresolved in the presence of DM artifact cancellation. This necessitates the FE mitigation of the CM artifact in addition to the DM artifact cancellation. To address this requirement, transmission gate switches are added to the input capacitors of the LNA (C 1 /2), which allow switching between DM and CM sensing of the incoming artifact, as shown in Fig. 5.12. Using the SAR-based algorithm discussed before, the CM component (V in,CM ) is initially estimated and stored in the memory block M1-CM during Φ CM . In the next phase (Φ DM ), the CM artifact cancellation is enabled (The CM component of the samples are loaded from the memory) and the DM component of the artifact (V in,DM ) is estimated and stored in the memory block M1-DM. After the DM estimation is complete, the switches stay in the ϕ DM configuration, while the comparator and SAR algorithm block are reconfigured to perform the second-point can- cellation at the input of the SC-PGA. 5.1.2.2 Second-Point Artifact Estimation and Cancellation The four recording front-ends are time-multiplexed into a shared SC-PGA. The estimation algorithm is run for only 10 stimulation cycles to quantize 16 consecutive samples of the 110 Figure 5.12: Reconfiguration of the front-end for (a) CM artifact estimation and (b) DM artifact estimation. The light gray lines/blocks are inactive. residual artifact per channel. A capacitive DAC (CDAC 2) is employed to subtract the 111 Figure 5.13: Implementation of the SAR-based artifact estimation algorithm at the second can- cellation point. artifactestimatefromthecorrespondingrecordingchannelatanygiventimepoint,asshown in Fig. 5.13. 5.1.3 System Architecture Fig. 5.14 shows the single-ended view of the chip block diagram, which was implemented fully-differentially across all the gain, cancellation, and quantization stages. The FE in- cludesfourparallelrecordingandstimulationchannels,eachcontaininganLNA,aswitched- capacitor low-pass filter (SC-LPF), and a PGA followed by a unity-gain voltage buffer. The four recording front-ends are time-multiplexed into two cascaded stages of SC amplifiers, which amplify the DT signal and drive a 10b SAR ADC. The DC offset of the voltage buffers in each channel is calibrated using a SAR-based algorithm which controls a shared current DAC at the input of the SC-PGA1. The capacitance values, power consumption of the transconductance cells and the timing diagram of the clock phases (generated on chip) are shown in Fig. 5.15. The sequential estimation and cancellation of a stimulation artifact (V in1 ), which has CM and DM components is simulated and illustrated in Fig. 5.16. 112 Figure 5.14: Complete chip block diagram (single-ended view is shown for simplicity). 113 Figure 5.15: (a) Capacitor values and power consumption breakdown. (b) Timing diagram of all the clock phases. 5.1.3.1 LNA Circuitry The LNA is implemented as a two-stage OTA in a capacitive feedback configuration (more detailcanbefoundinchapter2)asshowninFig. 5.17. ThefirstOTA(g m1a )determinesthe noise performance of the LNA while g m1b satisfies the large-swing (slew-rate) requirement of the LNA especially during the first-point artifact estimation (Φ EST,1,i , i is the channel 114 Figure 5.16: Simulated sequential operation of the two-point estimation and cancellation algo- rithm. number), when the LNA acts a preamplifier for the comparator in the estimation algorithm. TheLNAhasafixednominalgainof27.6dB.TheLNAiscompensated(phasemargin >60 ◦ ) withtheMillercapacitanceC c1 andnullingresistorsR c1,1 andR c1,2 . Separatecommon-mode feedback(CMFB)circuitryisusedforeachOTAtostabilizethecommon-modeDCvoltages of the intermediate and output nodes. The virtual ground of the LNA (g m1a input) is connected to the CDAC 1 output to subtract the artifact replica from the input waveform. The high-pass corner of the LNA is tunable by controlling the gate voltage (V HPC ) of the pseudo-resistors in the feedback (3Hz∼ 200Hz). An analog multiplexer can be programmed to select V HPC from an array of voltages (0V, ..., 1V) generated by a resistive ladder as shown in Fig. 5.18. 5.1.3.2 Switched-Capacitor LPF Since the second-point cancellation is performed in the discrete-time domain after the signal is sampled, an anti-aliasing filter must be implemented to prevent noise fold-back into the frequency band of interest. The low-pass corner (f LP ) should be about 10kHz to pass the useful features of the neural spike waveform. If realized with a simple RC configuration with a 1pF capacitor, a 15.9 MΩ resistor is needed which would consume a large silicon area. 115 Figure 5.17: LNA schematic (i= 1,2,3,4 is the channel number). However, it is possible to use a switched-capacitor circuitry to mimic the response of a large resistor as shown in Fig. 5.19(a). The pole of this circuitry lies at f LP = 1 2π C M C L f sw , (5.6) where f sw is the switching frequency, C M is the capacitance that controls the amount of charge flow, and C L is the load capacitance. The switches are realized as transmission gates to provide low on-resistance (R ON ) for the full range of the input voltage as shown in Fig. 116 Figure 5.18: Resistive ladder to control the high-pass corner. 5.19(b). A balanced switch control scheme is implemented to turn off both the NMSO and PMOSgatessimultaneouslytoavoidsignaldistortion. Thetwonon-overlappingclockphases required to control the switch gates are generated using the circuitry in Fig. 5.19(c). The switch sizes are chosen to allow settling of the output waveform to meet the target precision of N B +1 bits according to R ON C L (N B +1)ln(2)< T sw 2 , (5.7) where N B =10 is the ADC resolution, T sw = 1.6 µ s is the switching period, and C L =1.2pF. These parameters sets an upper limit of R ON < 90kΩ. The simulated AC response of the SC-LPF is plotted on Fig. 5.20(a) (C M =120fF), which shows the LP corner at 10 kHz (for comparison, the response of the filter using ideal switches is also illustrated). The transient response of the filter to a 1kHz tone is shown in Fig. 5.20(b). The on and off resistance of the transmission gate switches is simulated across different input voltages and shown in Fig. 5.20(c). The maximum R ON (happens at about 0.5V) reaches about 20 kΩ which satisfies the settling requirement. 117 Figure 5.19: (a) SC-LPF circuitry. (b) The schematic of the transmission gate switches and their control circuitry. (c) Non-overlapping clock generation circuitry. 5.1.3.3 PGA and Voltage Buffer The PGA is implemented with the same topology as the LNA using a capacitive feedback configuration. The feedback capacitor is realized as a capacitor bank to accommodate a 118 Figure 5.20: (a) SC-LPF AC response. (b) SC-LPF transient response. (c) Simulated switch resistance across different input voltages. 119 Figure 5.21: PGA schematic. tunable gain of 0− 12dB. The details of the schematic and CMFB circuitry is shown in Fig. 5.21. 120 Figure 5.22: Schematic of g m3 used in the unity-gain voltage buffer. To drive the time-multiplexing switches of SC-PGA 1 input, a unity-gain voltage buffer was implemented after the PGA. The low output impedance of the buffer allows a fast settling during the tracking time allocated to each channel (Φ 1,i duration∼ 6µ s). Since the buffer is disconnected from the output for about 88% of the time, the current of g m3 (the OTA inside the buffer) is duty-cycled to reduce the net power consumption (Fig. 5.22). 5.1.3.4 Buffer Offset Calibration Process variation during fabrication can introduce mismatch between the input NMOS pair of g m3 in the voltage buffer (Fig. 5.22). This creates a DC offset which can be modeled with a series DC voltage source (V OS ) as shown in Fig. 5.23(a). Since the SC-PGA stages that follow the buffer amplify their input DC component, even a 1mV offset at the buffer stage can introduce a 100mV offset at the ADC input. Therefore, the buffer offset has to be calibrated before propagating into the successive stages. A simple yet effective solution is 121 Figure 5.23: (a) Concept of offset calibration in a unity gain buffer. (b) Offset calibration in a differential circuitry and (c) Simulated SAR-based calibration algorithm. to inject a small current (I cal ) at the output of the buffer to shift the buffer output voltage V out . 122 The amount of voltage shift, governed by the Ohm’s law, is R out × I cal , where R out = 1 gm is the output resistance of the buffer. Hence, the exact calibration current needed to cancel the offset is I cal =g m V OS . (5.8) It is critical to note that the assumption of R out = 1 gm is only valid for small voltage swings. However, the buffer which is at the intermediate stage in the amplification chain is not ex- pectedtoexperiencealargevoltageswing. Thesameconceptcanbeappliedtocalibratethe offset in a differential scheme as shown in Fig. 5.23(b). The calibration current is generated from a pair of current DACs (I cal+ and I cal- ). A SAR-based algorithm is implemented to automatically find the correct calibration current in successive approximation cycles. The example shown in Fig. 5.23(c) demonstrates how the circuitry calibrates a 5mV differential offset at the input of the buffers in 6 consecutive clock cycles (V out+ reaches V out- at the end of the auto-calibration procedure). The efficacy of this approach was further validated with Monte-Carlo simulations (number of runs=50) as shown in Fig. 5.24. An output± 3σ offset of ± 9.6mV is reduced to ± 0.6mV which is an order-of-magnitude reduction in the output offset. The ± 3σ offset determines the maximum current that the calibration current DAC should be able to provide. The resolution of the current DAC is determined by the residual offset that can be tolerated by the succeeding amplifications stages (In this design, a 0.5mV residual offset at the buffer output, which is amplified to a maximum of 5% of the output full-swing, was set as the specification: g m3 = 12.5 µ S→ I cal ≤ 6.25 nA). Since the buffer outputs of the 4 recording channels are time-multiplexed, the offset calibration current DAC can be shared among different channels, as shown in Fig. 5.25. It is also possible to use a single current DAC (instead of two) to calibrate the offset in the differential buffer pair. Depending on the initial comparison of the buffer output terminals (V M+ and V M- ), the SAR algorithm steers the current DAC to the output node that is more positive and tries to lower its voltage and closer to the other node. The current DAC is 123 Figure 5.24: Monte-Carlo simulation of the buffer offset (a) before calibration and (b) after calibration. implemented as a 6-bit binary-weighted NMOS array with I LSB = 5nA, and an additional bit determines the configuration of the steering switches SW+ and SW-. Tosuppressthecomparatoroffsetandnoiseduringthecalibration,theamplifiedoffsetat theoutputoftheSC-PGA1isfedintotheSARalgorithmasshowninFig. 5.25. Theefficacy of this implementation was further verified with Monte-Carlo simulations. Single tones of 100 µ V p at 1.1, 2, 9.5 and 0.56 kHz were applied to the input of channels 1 to 4 respectively, and the transient response at the SC-PGA 2 output (output of the amplification chain) was plotted across multiple simulation runs. Fig. 5.26(a) shows that without calibration, 124 Figure 5.25: The implementation of the buffer offset calibration in a 4-channel time-multiplexed system. the output offset can saturate the amplifiers and severely degrade the signal quality. After running the auto-calibration algorithm, the output offset is suppressed and the amplifiers maintain their linearity as shown Fig. 5.26(b). 5.1.3.5 Switched-Capacitor PGA Circuitry The SC-PGAs are designed to perform correlated double sampling [Fig. 5.27(a)], which preventstheoffsetoftheg m -cellsfrompropagatingtotheoutputport [92]. Theprincipleof operation is as follows: The amplifier works with two non-overlapping clock phases. During Φ 1 (sampling phase), the input capacitor C 1 is connected to the input voltage and the total charge Q(n+ 1 2 ) stored on the top plates of the capacitors (virtual ground terminal) at the end of phase Φ 1 is Q(n+ 1 2 )=C 2 V OS +C 1 [V OS − V in (n+ 1 2 )]. (5.9) 125 Figure 5.26: Monte-Carlo simulations of the amplifier chain output (a) before calibration and (b) after calibration. During Φ 2 (amplification phase), C 1 is disconnected from the input and grounded while C 2 closes the feedback around the OTA. The total charge Q(n+1) stored on the top plates of the capacitors at the end of phase Φ 2 is Q(n+1)=C 1 V OS +C 2 [V OS − V out (n+1)]. (5.10) 126 Conservation of charge implies that the total charge at the virtual ground should remain constant when transitioning from Φ 1 to Φ 2 . Therefore, Q(n+1)=Q(n+ 1 2 ) which yields V out (n+1)= C 1 C 2 V in (n+ 1 2 ). (5.11) The analysis shows that the offset voltage does not appear in the output voltage, while the input voltage is amplified by the ratio of C 1 C 2 . The schematic of a differential OTA (used in SC-PGA), which accommodates a wide output swing is shown in Fig. 5.28(a). The OTA should meet certain specifications which are explained below. The intrinsic gain of the OTA (A 0 ) should be much higher than the desired closed-loop gain of the SC-PGA (A CL ), since the gain error of the closed-loop configurationisapproximately A CL A 0 . Thesmall-signalgainoftheOTAshowninFig. 5.28(a) can be estimated as A 0 = 1 2λnV T 1 1− 2I 1 I 0 , (5.12) whichassumesthatthetransistorsoperateintheweakinversionregion. Inthisequation, V T is the thermal voltage, n is the nonideality factor, λ models the channel length modulation and determines the drain-source resistance of a MOS transistor r o = 1 λI d (I d is the MOS current). Figure 5.28(b)plotsthedependenceofthegainonthe I 1 I 0 ratio, whichimpliesthat for a higher intrinsic gain, less current should be used in the output transistors compared to the input pair. To have a stable feedback configuration, we assume the pole at the output node is the dominant pole: ω p1 = 1 RoCo , where R o is the output resistance and C o is the net output capacitance. The non-dominant pole is located at the gate of the top PMOS transistors: ω p2 = g m4 C gd7 Rog m7 , where g m7 and C gd7 are the transconductance and gate-drain capacitance of the M7(M5). To meet a phase margin > 60 ◦ , the non-dominant pole should be at least 127 Figure 5.27: (a) SC-PGA with correlated double sampling. Amplifier configuration in phase (b) Φ 1 and (c) Φ 2 . 1.7 times larger than unity-gain bandwidth: 1.7A 0 ω p1 < ω p2 . This implies the following condition on the circuit parameters N r < 1 1.7A 0 C o C gd7 , (5.13) 128 Figure5.28: (a)SchematicoftheOTAusedintheSC-PGA.Dependenceofthe(b)OTAintrinsic gain and (b) Slew rate on the I 1 I 0 ratio. whereN r isthetopPMOSmirrorratio. Thetemporalresponseoftheamplifierisdetermined byboththesettlingtime(small-signalbehavior)andslewrate(SR,large-signalbehavior)of the OTA. During Φ 2 , which is the amplification phase, the OTA should be able to shift the output voltage per side (V out+ and V out- ) by VDD 2 during the phase duration T phase . Hence, SR = N r I 0 2 C 0 (1− 2I 1 I 0 )> VDD 2 T phase , (5.14) which is plotted on Fig. 5.28(c). A trade-off can be observed here: Increasing the I 1 I 0 ratio reduces the SR but increases the intrinsic gain, which calls for choosing an optimum value 129 for I 1 I 0 . The settling time of the unity-gain feedback configuration should be smaller than the phase duration which yields 2C o N r T phase (1+N B )V T ln(2)<I 0 , (5.15) where N B is the ADC resolution (N B +1 is the target precision) and T phase is the phase duration (Φ 2 ). These relationships impose design constraints on the circuit parameters, which should be satisfied for a proper operation of the amplifier. The SC-PGA 1 is designed to have a tunable gain, nominally 3.5− 27.6 dB, which is accommodated by the capacitor bank (C 8 ) in the feedback path, as shown in Fig. 5.29(a). Since the signal sensed by each channel may have different amplitudes, the user may need to apply different gain settings per channel. In this time-shared implementation, the configura- tion of the feedback capacitor can be programmed to change during each consecutive phase (Φ 2,1 , Φ 2,2 , Φ 2,3 , Φ 2,4 ) such that different C 7 C 8 ratios are achieved per phase and hence, per channel. ThetimingoftheclockphasesusedforcontrollingtheswitchesisillustratedinFig. 5.29(b). The switches in the feedback path (Φ 1,e ) are opened earlier than the input switches (Φ 1 ) to avoid input-dependent charge injection onto the sampling capacitors C 7 [93]. The switches at the virtual ground Φ 1,eq ) are opened slightly later than Φ 1,e (but before Φ 1 ) to absorb the charge injected by the Φ 1,e switches. The schematic of the OTA in the SC-PGA 1 is shown in Fig. 5.30. To satisfy the gain, stability and speed requirements, the current of the devices change with respect to the gain setting. The loop gain magnitude and phase of the SC-PGA 1 and its CMFB circuitry for minimum and maximum gain settings during both Φ 1 and Φ 2 are shown in Fig. ??. The plots suggest a stable design with the SC-PGA 1 loop and CMFB obtaining phase margin >60 ◦ . The schematic of the SC-PGA 2 and its OTA circuitry are shown in Fig. 5.32 and Fig. 5.33respectively, whichissimilartotheSC-PGA1circuitry. TheSC-PGA2accommodates a tunable gain of 0− 12 dB. 130 Figure 5.29: (a) Implementation of the SC-PGA 1. (b) Timing diagram of the clock phases to control the switch configurations. To test the full recording chain, single tones with 100 µ V p amplitude were applied at the input of channels 1-4 with frequencies 1.1kHz, 2kHz, 9.5kHz and 560Hz, respectively. The PGA gain for all the channels was set at the highest gain, while the SC-PGAs had different 131 Figure 5.30: (a) Schematic of the SC-PGA 1 OTA (g m4 ). gain settings per channel. Figure 5.34 shows the simulated response of each channel at the SC-PGA 2 output (time-demultiplexed). 5.1.3.6 Capacitive DACs and SAR ADC The cancellation CDAC 1 and CDAC 2 are implemented as 10-bit binary-weighted arrays with split capacitors to reduce the total area, as shown in Fig. 5.35. Since CDAC 2 is shared among multiple channels and is at the intermediate cancellation point, a larger unit capacitor is chosen for it. The CDACs were tested with 10kHz tone at full-scale (differential 3V p and 1V p for CDACs 1 and 2 respectively) and the dynamic performance both schematic and parasitic-extracted view is shown in Fig. 5.36. Parasitic-extracted CDAC 1 and 2 showed simulated SFDR of 52.8 and 60.5 dB respectively. A 10b SAR ADC was implemented using a 9b split-capacitance CDAC as shown in Fig. 5.37(a). A unity-gain voltage buffer attached to a calibration current DAC buffered the voltage of the CDAC to a dynamic comparator [Fig. 5.37(b)]. This buffer was used to (1) reduce the kick-back noise from the comparator coupled to the CDAC output and (2) calibrate for any offset introduced by the comparator. The principle of operation and 132 Figure 5.31: Stability of the (a) differential SC-PGA 1 and (b) CMFB circuitry. calibration logic is similar to the calibration of the buffer (after the PGA) in the recording path, which was discussed before. Split array CDACs with fractional bridge capacitor reduces both input capacitance and area. However,thefractionalbridgecapacitor(C B )suffersfrompoormatchingwiththeother capacitors, which degrades the ADC linearity. It is possible to compensate for the mismatch 133 Figure 5.32: Implementation of the SC-PGA 2. bysettingC B slightlylargerthantheidealfractionalvalue( 16 15 C u ),andintroducingatunable capacitor C C in parallel with the LSB side [94], which was implemented in this design [Fig. 5.37(a)]. TheparasiticextractedSARADCwassimulatedwitha1kHzfull-scale(1V p differential) input signal as shown in Fig. 5.38. After calibration, the simulated SNDR and SFDR improved by about 10 dB to 54.5 and 65.8 dB respectively (ENOB improved from 7.0 to 8.8 bits). 134 Figure 5.33: (a) Schematic of the SC-PGA 2 OTA (g m5 ). Figure5.34: Transientsimulationofthefull4-channelrecordingchainwithdifferentgainsettings per channel for the SC-PGAs 1 and 2. The waveforms are demultiplexed at the output of the SC- PGA 2. G1 and G2 show the gain setting of SC-PGAs 1 and 2 respectively. 135 Figure 5.35: Schematic of (a) CDAC 1 and (b) CADC 2. 5.1.3.7 Artifact Estimation Digital Circuitry The SAR logic in the artifact estimation algorithm was implemented as shown in Fig. 5.39. At every clock cycle corresponding to consecutive sampling time points (CLK j is a clock 136 Figure 5.36: Dynamic performance at 10kHz, full-scale output (a) CDAC 1 and (b) CADC 2. whichsamplestheartifactattimej,wherej=1,...,64isthesamplenumber),thecomparator output is registered in a sequence of flip-flops for temporary storage of the artifact estimate (a j,9 , ...,a j,0 ). The comparator used for artifact estimation his a copy of the one in the ADC. At the end of the estimation phase, the estimates are written in the memory blocks. During the artifact cancellation phase, at every cycle of Φ 2 , a counter is incremented to determine the correct sample number, which selects the corresponding row of the memory blocksfordataaccess. TheCMandDMcomponentsoftheaccessedsamplearecombinedto digitally reconstruct the artifact waveform and delivered to the CDAC 1 in each channel for 137 Figure 5.37: (a) Schematic of the SAR ADC. (b) Detailed schematic of the buffer and the calibration current DAC. the first-point cancellation. At the same time point, the corresponding sample is accessed from the memory block M-2 and sent to CDAC 2 to cancel the residual artifact, as shown in Fig. 5.40. The memory unit cells are designed as back-to-back connected inverters, with control transmission gates for data write, read and store (Fig. 5.41). A representative timing diagram of data write and store is also shown. 138 Figure 5.38: Dynamic performance of the parasitic-extracted SAR ADC (a) before calibration and (b) after calibration. Figure 5.39: Circuitry of the SAR logic. 5.1.3.8 Stimulation Circuitry Each channel is equipped with a stimulation circuitry which is realized using a 7-bit NMOS currentDAC(IDAC),whichhasatunableLSBcurrentof1− 4µ A.Thestimulationcathodic current is directly generated from the NMOS array (phase Φ c ) and for the anodic current, the current of the IDAC is rerouted to a PMOS mirror on top (phase Φ a ) as shown in Fig. 5.42. A regulated cascode configuration is implemented for the top and bottom current sources to boost the output impedance of the stimulator. The schematic of the OTAs 139 Figure 5.40: Architecture of the memory blocks and data access during the artifact cancellation phase. Figure 5.41: Memory unit cell. that drive the cascode transistors is shown in Fig. 5.43. This implementation ensures a constant V DS across the current source devices for a wide output voltage swing. The large output impedance of the stimulator brings in an important advantage which is simultaneous recording and stimulation from a shared electrode, which is critical in scenarios where the number of implanted electrodes is limited. 140 Figure 5.42: Stimulation circuitry. The output impedance of the stimulator is simulated and plotted (I STM = 127, 505 µ A) across a wide frequency range in Fig. 5.44(a). The graph show that the stimulator achieves aminimumof9MΩDCoutputimpedanceatitsmaximumoutputcurrentof0.5mA.There- fore, the stimulator can be interfaced with electrodes that have less than 1 MΩ impedance at low frequencies (such as [95]) while limiting the signal attenuation to less than 10%. A potential issue during periodic stimulation is the charge accumulation on the electrode due to an imbalance between the injected and depleted charges during the anodic and ca- thodicphasesrespectively. Ifthevoltageacrosstheelectrode-tissueinterfacepassesacertain window, irreversible reactions may damage the electrode and tissue. Therefore, for charge 141 Figure 5.43: Schematic of the OTAs used in the stimulator (a) g mp (b) g mn . balancing, at the end of every stimulation pulse, the electrode is short-circuited to V CMH to deplete any residual charge (Φ discharge ) as shown in Fig. 5.43. The efficacy of this approach was simulated as follows: The electrode was modeled as a Randles circuit with C DL = 10 nF and R s = 1 kΩ, I STM = 100 µ A, Tpulse= 100 µ s/phase, and stimulation rate = 100 Hz. As illustrated in Fig. 5.44(b), after 5 stimulation pulses and without charge balancing, the magnitude of the residual voltage increased to 31.3 mV, while with the discharge switch, the residual voltage increased slightly to 30 µ V. 5.1.3.9 Chip Programming, Data Transmission, and Test Plan The chip is programmable via on-chip shift registers that load the desired bit sequence in the target registers to control different settings in the recording, stimulation and artifact estimation blocks. The chip has a total of 480 programmable registers (278 bits for the recording and biasing blocks), which would take about 5 ms to program if all the bits are programmed sequentially via one path with a serial clock of 100 kHz. For certain applica- tions that require a fast control over the stimulation protocol such as turning on and off the stimulator instantaneously or delivery of a controlled number of stimulation cycles, the programming path of the recording and stimulation circuitry is separated, as shown in Fig. 5.45. The artifact estimation control and stimulation parameters such as the pulse duration and repetition rate are stored in a memory block, which can be accessed independently by 142 Figure 5.44: Simulation of (a) stimulator output impedance and (b) charge balancing. the row address. To verify that all the registers are programmed sequentially, a fixed pream- ble sequence is added to the programming pattern, which after passing through all the shift registers should appear at the serial out pad. The circuitry of the shift registers and the positive-edge triggered flip-flop that is used in the digital circuitry throughout this design is shown in Fig. 5.46. Fortroubleshootingpurposesandtoaccommodatetestingthefunctionalityoftherecord- ing amplifier chain and ADC independently, the SC-PGA 2 output is tapped out and con- nectedtoapairofbufferswhichdrivetheexternalmeasurementdevicethatwillbeattached 143 Figure 5.45: Programming strategy of the implemented bidirectional chip. to the pads (Fig. 5.47). Switches are included to disconnect the SC-PGA 2 output from the ADC and drive the ADC input externally. The ADC output is serialized, packetized and transmitted outside the chip via a cus- tomized serial interface. Each packet of data consists of an 8b preamble pattern, a 10b quantized data, followed by a fixed 8b postamble pattern. To distinguish between the data from different channels, the channel number is encoded in 2 bits of the preamble sequence (p 0 , p 1 ) as shown in Fig. 5.48. 144 Figure 5.46: (a) . 5.2 Measurements The chip is fabricated in a 0.18µ m CMOS technology (Fig. 5.49) and is packaged in a 10× 10 mm 2 QFN with 72 leads. A printed circuit board (PCB) was designed and fabricated to characterize the chip performance as shown in Fig. 5.50. The PCB accommodated two of the neural interface chips to test cross-chip artifact cou- pling cancellation. An external DC power supply (DP832A) and on-PCB voltage regulators 145 Figure 5.47: (a) Modifications to the recording chain for in-situ testability. (b) Schematic of the OTA in the output buffer. provided the supply voltages for the chip. For precise characterization of the chip perfor- mance, anarbitraryfunctiongenerator(AFG3252)generatedthecore20-MHzclockforthe 146 Figure 5.48: Customized serial data transmission protocol. chips,whichisdivideddowntoa19.5-kHzsamplingclockfortheon-chipADCs. TheAFG’s second channel was used to generate a single tone or a pre-recorded neural spike waveform for amplifier and artifact-cancellation characterization. An Arduino Due micro-controller was used to program the chips. For data acquisition, a 5M-point storage oscilloscope (TBS 2000B) was used to save the ADC serial data and clock output waveform for a limited time window. The saved data was transferred to a PC and a MATLAB script sampled the serial data at the rising edge of the serial clock, detected the data packets (via the postamble/preamble sequence), deserialized and demultiplexed the 10b data into 4 channels for spectral analysis and data visualization, as shown in Fig. 5.51. The buffered SC-PGA 2 differential output terminals were buffered again on the PCB, before being probed by the oscilloscope. 147 Figure 5.49: Die micrograph. 5.2.1 Recording channel characterization Each recording channel, which includes the amplification stages, CDAC 1, CDAC 2, and the ADC, consumes 5.2 µ W of power and 0.35 mm 2 of area (the area and power consumption of SC-PGAs, CDAC 2 and ADC is divided by 4 to normalize their performance per channel). The cancellation digital circuits including the memory blocks consume 2.7 µ W per channel. All the blocks are driven from a 1V supply, except the stimulator and CDAC 1 which are operated with a 3V supply. At the beginning of the chip operation, the input of all the channels were grounded, the recording path was programmed to its maximum gain setting, and an auto-calibration command was sent to the chip, which performs the offset calibration for the buffers in the recording chain and comparators. A screenshot of the oscilloscope, probing the SC-PGA 2 differential output before and after the calibration, is shown in Fig. 5.52. The graph illustratesoutputofchannels1to4periodically(duringΦ 1 theoutputistheamplifiedsignal 148 Figure 5.50: (a) Test bench block diagram. (b) PCB top view. and during Φ 2 the differential output becomes zero). The ADC output better demonstrates the efficacy of the calibration scheme in reducing the offset per channel, as shown in Fig. 5.53(a). The results support the functionality of the calibration implementation, showing that an offset of 8.9 mV on channel 4 is reduced to 0.6 mV at the SC-PGA 1 input after the SAR-based auto-calibration, as shown in Fig. 5.53(b). 149 Figure 5.51: Measured serial data and clock output. The data packets were deserialized and demultiplexed into 4 channels in MATLAB offline. Amplification of the recording channels was measured with 100 µ V pp differential signal at 991.8 Hz applied to the input channels, programmed to the maximum gain setting. The spectral response (Fourier transform) of the channels at the ADC output is shown in Fig. 5.54. The common-mode (CM) to differential-mode (DM) conversion was also measured with a common single tone (10mV pp ) applied to both the positive and negative (reference) 150 Figure 5.52: Direct measurement of the SC-PGA 2 differential output (all the inputs are grounded), before and after the offset auto-calibration. inputs of the channels. The output spectrum and the calculated common-mode-rejection ratio (CMRR) is shown in Fig. 5.55. The maximum measured DM gain and CMRR were 75.3 dB and 51.7 dB respectively (parasitic extracted simulation of the LNA showed a 55.7 dB CMRR). The measured AC response and input-referred noise spectral density of the recording chain at the maximum gain setting was measured and is plotted in Fig. 5.56(a-b). The 3-dB low-pass corner is at 9 kHz, while the high-pass corner is below 10 Hz (the lowest 151 Figure 5.53: (a) ADC output before and after calibration. (b) Residual offset referred to the SC-PGA 1 input (voltage buffer output). measured frequency was limited by the maximum data storage of the oscilloscope). The integrated input-referred noise is 9.8 µ V rms in a bandwidth of 10 Hz− 9 kHz. For linearity measurements, a 1kHz signal at 250µ V p was applied to the recording channel with a gain set at 63.8 dB, which achieved a total-harmonic-distortion (THD) of 1.8%, as shown in Fig. 5.56(c). The AFE was designed to have tunable gain and high-pass corner as shown Fig. 5.57. Since the channels time-share a portion of the recording chain, it is possible that a signal fromonechannelleakstothenextduetoresidualchargefromthepreviouslysampledsignal at the shared capacitors. To measure the crosstalk, a 1kHz signal was applied at the channel 1 input, while the input of the other channels was grounded, as shown in Fig. 5.58(a) (all the channels were at their maximum gain setting). The input tone was increased from 100µ V pp to 100mV pp and the spectrum of the channel 2 output was measured as shown in Fig. 5.58(b). The measured crosstalk from channel 1 to 2 was -56 dB. 152 Figure 5.54: Differential-mode gain measurement test bench and output spectrum. 5.2.2 CharacterizationoftheTwo-PointStimulationArtifactCanceler Tomeasurethechipperformanceinartifactcancellation,abiphasicstimulationcurrentwith a pulse width of 102.4µ s per phase and repetition rate of 152.6 Hz was generated on-chip and applied to an off-chip 10-kΩ resistor, which was connected to the biasing voltage V CMH at 1.5V (mid-supply). The artifact was coupled to the input of the recording channels in 3 different test configurations: common-mode (CM), differential-mode (DM) and single-ended (SE) as illustrated in Fig. 5.59. The gain of the recording channels was set to 52.3 dB. The functionality of the implemented artifact estimation and cancellation algorithm was initially tested on a 400-mV pp common-mode artifact input. The measurements show that the SC-PGA 2 output is suppressed after the artifact cancellation as shown in Fig. 5.60. Foramoreprecisecomparison,theADCoutputisplottedinFig. 5.61(a). Thegraphshows 153 Figure 5.55: Common-mode gain measurement test bench and output spectrum. that without artifact cancellation, the output swing reaches the supply rail. However, after enabling artifact estimation and cancellation, the output swing is significantly reduced to about 60mV pp , which is equivalent to 150µ V pp input-referred residual artifact. The cancel- lation circuitry was further tested on a 800-mV pp input DM artifact and the ADC output is shown in Fig. 5.61(b). The graph supports the functionality of the cancellation circuitry to suppress the DM artifact to 1mV pp input-referred residual artifact. It should be highlighted thatwithoutartifactcancellation, theoutputoftherecordingchannelissaturatedevendur- ing the inter-pulse interval (as was discussed in 5.1.2). Consequently, the amount of artifact suppression can be calculated as 68.5 and 58.1 dB for CM and DM artifacts respectively. A 154 Figure 5.56: Performance of the full recording chain (a) AC response and (b) input-referred noise spectral density at the maximum gain setting. (c) Linearity measurement. demo of the chip operation is recorded and available at https://drive.google.com/file/ d/17c-o6X6c-JlS_QP7-qy5mRcPK9zFGJPk/view?usp=sharing. To verify whether the two-point cancellation circuitry preserve the signal quality, a 200- µ V p 1-kHz tone was added to 400-mV pp CM artifact as shown in Fig. 5.62(a). The ADC 155 Figure 5.57: Tunability of the AFE AC response. Three measured examples of different (a) gain settings and (b) high-pass corners are shown. output in Fig. 5.62(b) shows that the contaminated artifact is removed from the amplified sinusoidal signal. To quantify the cancellation performance, Fourier transform is performed on the ADC output and the signal-to-noise ratio (SNR) is calculated (the noise power also captures the distortion introduced by the artifact or cancellation circuitry). Comparing the output signals in the frequency domain shows that the canceler has boosted the SNR by 20.5 dB, as shown in Fig. 5.63(a). The same procedure was performed on a 800-mV pp DM artifact. As shown in Fig. 5.63(b), the two-point canceler prevented the saturation of the amplifiers and could recover the underlying 1kHz signal and increase the SNR by 23.8 dB. For DM artifact generation, external buffers were used as shown in Fig. 5.59 which 156 Figure 5.58: Crosstalk measurements (a) Test setup, (b) Leakage from channel 1 to channel 2 at different input levels. Figure 5.59: Different testing modes of artifact coupling to the recording channels. introduced powerline noise (60Hz) into the system, which can be observed in both the time and frequency response in Fig. 5.63(b). To exclude the 60Hz noise and its spectral leakage tonearbyfrequencybinsforSNRcalculations,thenoisepowerwascalculatedforfrequencies 157 Figure 5.60: 400-mV pp input CM artifact measured at the SC-PGA 2 output. above 500Hz (the spectrum was high-pass filtered) for both the recorded signals with and without the cancellation. The experiment was repeated for different amplitudes of the artifact (by changing the stimulation current) in 3 different configuration that were mentioned before (CM, DM and SE). The SNR of a 200-µ V p , 1-kHz recorded signal with no added artifact and without cancellation was considered as the baseline for evaluating the SNR degradation of the cases underinvestigation. AscanbeseeninFig. 5.64,withoutthecanceler,theSNRdegradation ismorethan20dBforCM/SEartifactlevelsabove400-mV pp . ForDMconfiguration,evena 25-mV pp artifact severely degrades the signal quality. However, the implemented two-point canceler can reliably recover the signal contaminated with 800-mV pp CM, or 1200-mV pp DM/SE, with a reasonable penalty of up to 6-dB SNR degradation (equivalent to 1-bit). 5.2.3 Two-Chip Stimulation Artifact Cancellation Inascaled-upimplementation, multiplechipsmaybeusedtointerfacewithdifferentregions of the brain. In such scenario, the recording channels of a chip can pick up an artifact coupled from the stimulation of another chip, as shown in Fig. 5.65. The implemented artifact canceler has the capability to accommodate such scenarios, which was tested in a 2-chip implementation shown in Fig. 5.66. The stimulator on chip 1 generated the artifact by applying a biphasic current to a resistive load and the cancelers on chip 2 estimated and canceled the artifact coupled to their inputs and recovered the underlying 1kHz signal with a 17-dB boost in SNR, as shown 158 Figure 5.61: Performance of the cancellation circuitry (a) 400-mV pp CM artifact and (b) 800- mV pp DM artifact. in Fig. 5.67. The requirement for effective cancellation is that both chips should operate from a shared core digital clock (an external reference or the internal clock in one of them). 159 Figure 5.62: (a) Test bench for 1kHz signal amplification in the presence of a CM artifact. (b) ADC output, before and after artifact cancellation. Theexactstimulationcommandprogrammedonchip1shouldalsobedeliveredtochip2such that it can synchronize its artifact estimation and cancellation timing with the stimulation event. 5.2.4 In Vitro Measurements Asimpleresistiveloadcannotfullymodeltheactualartifactwaveformgeneratedinatissue. Therefore,thenextstepafterbench-topcharacterizationwastestingthesysteminasolution that mimics the bodily fluid: phosphate buffer saline (PBS). As illustrated in Fig. 5.68(a), 6 insulated tinned-copper wires with 0.3 mm diameter and 5 mm exposed tip were used to interface the neural chip with the saline: (1) one electrode delivered the stimulation current (I STM ), (2) four electrodes were connected to the 4 recording channels on chip, and (3) one 160 Figure 5.63: ADC output and its Fourier transform: 1kHz signal added to (a) 400-mV pp CM artifact, (b) 800-mV pp DM artifact. Figure 5.64: Summary of the two-pint artifact cancellation performance in recovering a 1kHz signal contaminated with different magnitudes of CM, DM or SE artifact. electrode was used to apply a pre-recorded neural spike into the solution. An additional electrode with 1 cm exposed tip, was also used to set the biasing voltage of the solution to 161 Figure 5.65: Chip-to-chip Stimulation artifact coupling in a multi-chip implementation. Figure 5.66: Test bench to quantify cancellation of the artifact coupled from chip 1 to chip 2. V CMH , which was also connected to the reference input of the recording channels. Initially, before applying the stimulation current, the neural waveform was periodically generated 162 Figure 5.67: Performance of the canceler in recovering signal from stimulation artifact generated by another chip. by the AFG and applied to the solution, while the received signal from the channels was recorded as shown in Fig. 5.68(b) (All the channels were programmed to a gain of 52.3 dB). In the next step, a periodic 35-µ A biphasic stimulation current was applied to the saline while the AFG was generating the neural response periodically. Figure 5.69 shows that the artifact saturates the amplifier during the stimulation; however, exploiting the canceler suppresses the artifact and the underlying neural signal is restored. 163 Figure 5.68: (a) In vitro test bench for characterizing the cancellation performance. A pre- recorded neural spike is periodically applied to the solution. (b) ADC output showing the recorded waveform in the absence of stimulation. 5.2.4.1 Same-electrode Simultaneous Recording and Stimulation The system was further examined in a configuration where the stimulation and recording is performed via a shared electrode as shown in Fig. 5.70(a). A 20-µ A biphasic stimulation current was applied to the saline while the AFG generated and applied a 1kHz test signal to the solution. The ADC output waveform in Fig. 5.70(b) shows that (1) the cancellation circuitry was successful in suppressing the stimulation artifact and (2) the 1kHz signal was recordedwhilethestimulationcurrentwasappliedtotherecordingelectrode,whichsupports the efficacy of the stimulation current circuitry carrying a high output-impedance. 164 Figure 5.69: (a) The chip cancels the contaminating stimulation artifact and recovers the under- lying signal in vitro. For comparison, the chip recording output in the absence of stimulation is also plotted. 5.2.5 In Vivo Measurements All procedures were performed in accordance with protocols approved by the Institutional AnimalCareandUseCommitteeoftheUniversityofSouthernCalifornia. AfemaleSprague- Dawley rat (215 g, 11 weeks) was used for electrophysiology recordings. The animal was anesthetized with a ketamine (75 mg/kg) and xylazine (10 mg/kg) cocktail after a brief 165 Figure 5.70: (a) Test configuration for simultaneous stimulation and recording from the same electrode in vitro. (b) Stimulation artifact cancellation. induction with 4% isoflurane and 95% oxygen. During the surgery, 1.5% isoflurane and 95% oxygen at 1L/min was administered to maintain a constant level of anesthesia, which was assessed by the breathing rate and the toe-pinch reflex. The animal was mounted on a stereotaxic frame by ear bars and a nose cone. Craniotomy was performed above the right hemisphere to expose the cortex. Dura mater was carefully removed. Apairofstraightenedinsulatedtinned-copperwireswith1mmspacing,0.3mmdiameter, and 5 mm exposed tip was implanted in the cortex using the micromanipulators (Bregma coordinates: ML 2.45 mm, AP -2.46 mm, 2.17 mm deep). One electrode was used to inject the stimulation current (I STM ), while the other one recorded the neural activity from the nearby tissue (V REC ), as illustrated in Fig. 5.71(a). The biasing wire (connected to V CMH ) 166 Figure 5.71: (a) In vivo test configuration for simultaneous stimulation and recording in a rat’s brain. Recorded signal baseline from the (b) anesthetized and (c) euthanized rat. The amplitudes are input-referred. and reference wire (V REF , connected to the reference input of the amplifier) were placed in the hindbrain. The gain of the recording channel was set to 52.3 dB and its high-pass corner was set to its minimum (<10Hz). The baseline activity of the brain was recorded for a maximum recording time of 80 ms which was limited by the available data acquisition system,asshowninFig. 5.71(b). Asacontrolexperiment,thebrainrecordingwasrepeated when the animal was euthanized, which is shown in Fig. 5.71(c). A background powerline 60-Hznoiseispresentinbothrecordingswithanamplitudeofinput-referred70-µ V pp , which does not affect the linearity of the recording system. Since the low-frequency voltage drift 167 Figure 5.72: In vivo simultaneous stimulation and recording. The figures show the voltage of the recording and reference electrodes, and the recorded ADC output in the absence or presence of the artifact cancellation circuitry for stimulation current intensity of (a) 122 µ A and (b) 64 µ A. observed in the anesthetized rat is not present in the euthanized rat, it may be an indication of a neural activity. In practice, a few seconds of continuous recording is usually needed to detectlocalfieldpotentials,whichwillbefulfilledbyimprovingtheexternaldataacquisition system in the future. Aperiodicbalanced-biphasicstimulationcurrentwithapulsewidthof102.4µ sperphase and repetition rate of 152.6 Hz was applied to the anesthetized rat. The recording circuitry 168 whichwassettoagainof52.3dBwascontinuouslymonitoringtheelectrodepotentialV REC . Theperformanceoftheimplementedtwo-pointartifactcancellationcircuitrywastestedwith two different stimulation current intensities: 122 µ A and 64 µ A, as shown in Fig. 5.72. The 122-µ Astimulationcurrentgeneratedartifactsatboththerecordingandreferenceelectrodes (V REC and V REF ), which can be decomposed into an equivalent 160mV pp DM component and 260mV pp CM component at the differential input of the recording amplifier, as shown in Fig. 5.72(a). The ADC output shows that without using the cancellation circuitry, the amplified signal has saturated the amplifier (clipped output at ± 1V). However, enabling the canceler suppressed the artifact level to a residual artifact swing of 250-µ V pp input-referred, which is equivalent to a 60-dB suppression of the input artifact. The canceler also prevented the recording amplifier from saturation and restored the recording system’s linearity (which is suggested by the recovery of the background 60-Hz noise in the recorded waveform with artifact cancellation, as opposed to the case without the canceler, which resulted in the system’s saturation and complete loss of the the background 60-Hz noise). The same results were achieved with a lower stimulation current of 64 µ A as shown in Fig. 5.72(b). During the recordings, no action potentials could be detected due to the large surface area of the implantedelectrodes(insertedtiplength∼ 2mm). Infuturetrials,asmallerelectrodeshould be used to record single or multi-unit activities. 5.2.6 Powerline Noise Interference and Mitigation Inthebenchtopcharacterization,itwasobservedthatsmallerelectrodes(higherimpedance) contributed to more powerline noise in the recorded signal, which was further investigated. To remove any potential source of the powerline noise into the recording channels, a 5-V battery replaced the external DC power supply, and the internal core clock (instead of the AFG) was used. Since long wires may pick up the stray electromagnetic fields from the powerline cables in the walls, short wires were used to connect the input of the recording system to a 1 kΩ resistor (modeling the impedance of the reference electrode) and a 1 MΩ 169 resistor (modeling the impedance of a small recording electrode) terminated to the biasing voltage V CMH (generated on the PCB), as shown in Fig. 5.73(a). The recorded waveform suggested that the powerline noise is still present with a significant input-referred amplitude of 1.7 mV pp . Theonlyremainingpartofthemeasurementsystemthatcouldpotentiallyleakthepow- erline noise was the data acquisition probes connected to the oscilloscope (with a shared ground with the PCB). To overcome this issue in future experiments, an FPGA-based mi- crocontroller(whichcanbeoperatedonbatteries)shouldbeused(insteadofanoscilloscope) to buffer the serial data to a PC. An alternative approach to reduce the coupled noise into the recording channel is to reduce the source impedance, which can be achieved by inserting a unity-gain voltage buffer between the electrode and the recording channel. As shown in Fig. 5.73(b), such implementation reduced the powerline noise to 0.25 mV pp input-referred. The thermal noise overhead of the added buffer (NTE859) is about 10% of the recording system. These experiment suggest a model for the coupling of the powerline noise to the input of the recording system, as shown in Fig. 5.73(c). During the experiments mentioned above, the amplifiers were programmed to record the full bandwidth (high-pass corner < 10Hz). However, if recording the action potentials is the only target, the high-pass corner of the recording amplifier can be increased to have a higher suppression of the 60-Hz noise. Future experiments should focus on reducing the powerline noise in the measurement test bench, which will improve both the recording quality and the performance of the artifact estimation and cancellation. 5.3 Conclusion and Future Work Table 5.1 compares the performance of this work with state-of-the-art neural interfaces resilient to artifacts. This work implemented a two-point artifact suppression technique 170 Figure 5.73: Test bench to investigate and mitigate the powerline noise(a) Powerline noise at the ADC output when the source impedance is high (e.g. 1 MΩ). (b) Lowering the source impedance by using a voltage buffer suppresses the 60Hz noise. (c) Modeling the 60Hz noise coupling to the recording system. that estimates and cancels the stimulation artifact in two points along the signal amplifica- tion stages using a SAR-based algorithm, boosting the common-mode and differential-mode stimulation artifact suppression to 68.5 dB and 58.1 dB respectively, which is an order of 171 Table 5.1: Performance Summary and Comparison with the State-of-the-art Bidirectional Neural Interfaces Resilient to Artifact magnitudehigherthanthecurrentstate-of-the-art. Moreover,theproposedSAR-basedarti- factestimationalgorithmcarriesthefollowingadvantagescomparedtotheadaptiveIIR-filter 172 approach discussed in the previous chapter: (1) no additional front-end buffer (ADC driver) isneeded,(2)trainingtimeisfixed(equaltotheDACresolution)andnotartifact-dependent, (3)thistechniqueisapplicabletoanystimulationcurrentandartifactwaveform. Apotential limitation in the current system is that the artifact estimation procedure is performed only once to estimate the artifact waveform, which can make the artifact susceptible to random background noise. To reduce the effect of random noise or an uncorrelated neural signals on the estimation of the stimulation artifact, an averaging of multiple rounds of estimation loop can be performed to improve the accuracy of the estimated artifact. This chip or multiples of it can be readily used in the neural interface applications where the electrode-count is limited. For instance, in responsive neurostimulation systems for seizure detection in patients with epilepsy, the brain activity is continuously monitored using four recording channels [40]. In another application, the implemented chip can be used in peripheral nerve prosthetics to interface with the sciatic nerve using 8-channel cuff electrodes [95]. Nonetheless, the proposed two-point cancellation scheme has the potential to be scaled up: Each recording channel must have a dedicated LNA, CDAC 1, PGA and buffer which add up to 0.26 mm 2 /channel. The area of the time-shared blocks (SC-PGA 1+2, CADC 2, ADC and the digital estimation algorithm) can be amortized among several channels (e.g. 0.04 mm 2 /channel if time-shared between 8 channels). However, the physical space required for the storage of the quantized artifact samples scales quadratically with the number of stimulation/recording channels: A scaled-up system with N recording and N stimulation channels will require (80samples × 10bits/sample) × N 2 bits of memory. For N=100, adigitalmemoryof1MBisneededwhichcanbeimplementedasadenseSRAM.In a more advanced technology node such as 65-nm, a 6T-SRAM cell size of about 0.5 µm 2 can be achieved [96], which translates into 0.04 mm 2 /channel, increasing the total area of each recording channel to 0.34 mm 2 (The AFE is mostly occupied by the metal-insulator-metal (MIM) capacitors, which can be miniaturized using technologies which offer high-density MIM capacitors (as high as 20fF/µm 2 in a 14nm-node). In the 180-nm technology used in 173 Figure 5.74: Scaling up the two-point cancellation scheme to a system with N recording and stimulation channels. Figure 5.75: Time-sharing both stages of a two-point artifact cancellation scheme to reduce chip area. thisproject,theMIMcapacitordensitywas2fF/µm 2 ). Hence,a100-channelimplementation would result in a 6mm× 6mm chip, which is a reasonable size. A block diagram of such implementationisshowninFig. 5.74. Itisalsopossibletotradeadditionalnoiseandpower consumption for a smaller footprint by multiplexing the front-end CDAC 1 as shown in Fig. 5.75. Each channel is equipped with a front-end voltage buffer with a low gain ( < 1− 2) to drive an analog multiplexer which is shared among 8 recording channels in this example. The signals from the multiplexed 8-channels undergo the first-point artifact cancellation at the LNA-CDAC 1 interface and a second-point cancellation at the SC-PGA-CDAC 2 stage. 174 Chapter 6 Conclusion and Future Work This dissertation described the design considerations for an integrated bidirectional neural interface, while focusing on the issue of stimulation artifact and potential mitigation tech- niques. Chapter 4 discussed a novel adaptive IIR filter which could replicate the artifact waveformandsubtractitatthefront-endoftherecordingchain(Thisworkwaspublishedin the Journal of Solid-State Circuits [97]). The measured performance of this scheme showed that the amount of artifact suppression is not sufficient and may still degrade the record- ing system’s linearity at high gain settings. Chapter 5 proposed the concept of multi-point artifact cancellation which can significantly improve the artifact suppression. A two-point artifact canceler was implemented and its performance was validated in vivo (This work is currentlybeingsubmittedforpublication). Themeasurementssupportedthatincorporating an additional canceling point in the signal recording chain boosts the artifact suppression by at least an order of magnitude. The end-application of the neural interface plays a major role in deciding the artifact mitigation technique. Some of the determining parameters are: Electrode configuration : Ifthe stimulationand recordingarrays areimplantedspa- tially apart in the tissue, it may be possible to mitigate the artifact at the stimulation side; thus, removing or relaxing the burden on the recording system [77,98]. 175 Recording channel count: The existing front-end cancellation techniques (such as the proposed two-point canceler) occupy a relatively-large area per channel. Unless optimized for a smaller footprint, they are currently suited for applications with low channel-counts such as epilepsy monitoring systems [40] or peripheral nervous pros- thetics [95,99]. Higher channel-count systems, which are required in brain-computer interfacesrecordingfrom100’sto1000’selectrodessimultaneously,favormorecompact solutions such as oversampling ADCs. The high-DR of these ADCs accommodate not only the stimulation artifact, but also artifacts originated from various sources such as motion. However, such schemes are deemed low-power for low-bandwidth signals. For instance, [28] implemented a ∆ 2 Σ ADC which occupies a small footprint of 0.023 mm 2 and consumes 1.7 µW per channel. However, this scheme only accommodates local field potentials (BW=500Hz). If this implementation is scaled to cover action potentials (BW=10kHz), for example by increasing the ADC sampling rate, the power consumption will scale to at least 34 µW per channel, which is an order-of-magnitude higher than the recording systems which use FE artifact cancellation and Nyquist-rate ADCs [97]. A high power-consumption per channel may not be acceptable due to the system total power budget and the maximum allowable heat that can be dissipated in the tissue. This calls for investigating new approaches to address such trade-offs in a dense neural interface. Finally, it may be possible to achieve a superior area-noise-power trade-off by combining two or more of the artifact mitigation methods discussed in this dissertation. For instance, stimulation-sideandrecording-sideartifactcancellationtechniquescanbecombined. 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ASAIO journal (American Society for Artificial Internal Organs: 1992), 40(3):M514–7, 1994. 187 Appendix A Neural Stimulator with Dynamic Supply Voltage Modulation Acompactneuralstimulatorusuallyconsistsofacontrollablecurrentsource,mostlyrealized as a current digital-to-analog converter (IDAC). Since the stimulation current range and resolution of the IDAC depends on the target application, the power consumption of the stimulator depends mainly on the supply voltage. In a conventional current stimulation circuitry, the supply voltages are fixed and set by the highest voltage value that is expected to be created across the neural tissue [49]. In other words, even if the voltage created across thetissueissmall, thesupplyvoltageremainsatahighvalue; therefore, thepowerorenergy consumption of the current stimulator will be unnecessarily high. To overcome this issue, a supply modulation technique using a series-parallel switched-capacitor DC-DC converter was designed and implemented, which achieved high conversion efficiencies ( >80%). This work, inpart, waspublishedin [35]. Here, amorecomprehensivediscussiononthecircuitry and measurements is provided. The proposed neural stimulator chip, targeting retinal stimulation of rats for experi- ments in visual cortex/mid-brain and hippocampal plasticity, consists of a 7-bit current DAC capable of supplying up to ± 127 µ A current with a variable supply voltage driven by a reconfigurable switched-capacitor DC-DC converter within ± 3 V (Fig. A.1). An array of comparators monitors the electrode voltage continuously and determines the appropriate 188 Figure A.1: Block diagram of the neural stimulator. conversion ratio such that a minimum of 150-mV voltage headroom is maintained across the IDAC transistors [Fig. A.2]. The generated reference voltages are 0.4, 0.8, 1.2, 1.6 and 2 V during the anodic phase (or their negative values during the cathodic phase). The clock signals Φ 1 and Φ 2 for the DC-DC converter are created using on-chip 2-3MHz relaxationoscillators[Fig. B.5(a)]andnon-overlappingclockgeneratorcircuits. Togenerate anindependenttimingforthecurrentstimulationwaveform,aregenerationoscillatorisused as shown in Fig. B.5(b), which generates a 80-kHz clock. In this circuitry, the oscillation frequency depends on the current source (I c ), V ref and capacitors (C). Figure B.5(c) shows a summary performance of the oscillators. The current DAC is realized as a parallel array of binary-weighted NMOS and PMOS transistors. The channel length of each transistor is large (5µ m) to increase the output resistance without requiring cascode to increase the voltage headroom and efficiency. An additional current source with half the size of unit cell is added to improve the linearity and compensate for the supply jumps during specific DAC current transitions. The schematic 189 Figure A.2: Conversion ratio decision circuitry (shown for the anodic phase). and measured linearity performance of the 7-bit current DAC are shown in Fig. A.4. The unit element currents I LSB,p and I LSB,n are generated on chip using bandgap voltage and reference current circuitry as shown in Fig. A.5. The chip can generate a biphasic current waveform, whose parameters can be programmed and stored on the chip, as well as any generic current waveform that is dynamically loaded into the chip. A reconfigurable switched-capacitor DC-DC voltage converter is designed to generate the necessary DC power supplies (Fig. A.6). It accommodates voltage conversion ratios of 5:1, 3:1, 2:1, 3:2 and 6:5 for both positive rail (VDD = 3V) when Φ a is active (anodic phase) and negative rail (VSS = -3V) when Φ c is active (cathodic phase). A total of 34 switches are used in this scheme to choose the proper series-parallel configuration of the flying capacitors to achieve the required conversion ratio. S1, S22, S23, S24, S25, S31, 190 Figure A.3: (a) Relaxation oscillator schematic. (b) Regeneration oscillator schematic. (c) Performance summary. S33 are PMOS switches, while S3, S6, S9, S12, S15, S32, S34 are NMOS switches and the remainingswitchesaretransmissiongates(TG).AsshowninFig.A.7, toachieveconversion ratios of 6:5 and 5:1, five independent flying capacitors, each 50 pF, are used, while these 191 Figure A.4: CurrentDACschematic. (a)PMOSandNMOSDACschematic,(b)Measuredstatic linearity. capacitors are combined for other conversion ratios to boost the efficiency. The switching frequency, size of the switches and the flying capacitors are optimized for minimizing the bottom-plate capacitance and gate-drive losses. The output capacitor value is chosen as 500 pF to reduce the ripple to less than one LSB. 192 Figure A.5: Bandgap voltage and reference current generation circuitry.. Since the bulk of the chip is connected to VSS (-3 V), extra caution should be taken to avoid transistor breakdown. Gate-source, gate-drain and gate-body breakdown voltages are 3.6 V for thick-gate oxide devices; therefore, triple-well NFETs are used to handle positive voltages safely. Depending on the state of the system, the DAC maybe operating between positive rails or negative ones. In order to switch between these supply rails reliably, and prevent transistor breakdown, the circuitry shown in Fig. A.8 was used, which converts {3V,0} logic to{0,-3V} logic. The neural stimulator chip was fabricated in a 130 nm CMOS process (Fig. A.9). The chip was interfaced with an Arduino microcontroller board for programming the stimulation waveforms (Fig. A.10). The stimulation current was measured with Keithley 2002 digital multimeter. Themeasuredpowerefficiencyofthecurrentstimulatorforaresistiveloadvalue of Rs = 17.26 kΩ confirms the improvement over conventional approaches with a constant supply voltage [Fig. A.11(a)]. A maximum of 20% improvement was observed for a 30 µ A output current. Figure A.11(b) shows the DC-DC converter output levels for different 193 Figure A.6: Reconfigurable switched-capacitor DC-DC converter. conversion ratios. The DC-DC converter maintains an efficiency above 60% (85% peak) in its range of operation. A demo of the chip operation is recorded and available at https://drive.google. com/file/d/1khi4EyTHLoxF07Dji6XGIrDrROsvvM51/view?usp=sharing. Figure A.12(a) demonstrates a periodic balanced biphasic and a sinusoidal current waveform, applied to a resistive load of 17.26 kΩ along with the dynamically changing supply voltage value. The functionality of the neural stimulator interfaced with parylene-based microelectrodes was also investigated. The platinum electrode diameter was 160 µ m and it was immersed in a 1Xphosphate-bufferedsaline(PBS)solution. Biphasic( ± 5µ A)andsinusoidal(30µ Apeak, 40 Hz frequency) current waveforms were generated and electrode voltages were recorded, as shown in Fig. A.12(b). 194 Figure A.7: DC-DC converter configuration for different conversion ratios. A neural stimulator chip, capable of supplying pre-programmed biphasic or dynamically- programmed arbitrary current waveforms having peak values of ± 127 µ A with 7-bit reso- lution, featuring dynamic supply modulation for power efficiency improvement, is demon- strated in a 130 nm CMOS technology. 195 Figure A.8: DC-DC converter configuration for different conversion ratios. Figure A.9: Chip microphotograph. 196 Figure A.10: Test PCB. Figure A.11: (a) Measured energy efficiency versus the load current. (b) Measured versus simu- lated DC-DC converter output. 197 Figure A.12: Representative measured output voltage waveforms and corresponding modulated supply voltage. (a) Pure resistive load and (b) Platinum electrode. 198 Appendix B Chopper-Stabilized Neural Recording Amplifier B.1 Background Capacitive feedback amplifiers are commonly used in neural amplifiers because the gain is set accurately by the ratio of capacitors, and the input impedance is high at low frequencies [100–102]. To remove the effect of operational amplifier’s low-frequency noise and DC offset, chopping is used where the low-frequency bio-signals are up-converted to a carrier frequency (f ch ) away from the DC offset and the flicker noise [103]. The up-converted signal, after bandpass amplification, is down-converted to its original frequency while the DC offset and flicker noise are up-converted away from this signal. However, chopping front-ends suffer from low input impedance at DC due to periodical charging and discharging of the large input capacitors that have values set by the gain considerations. A DC input impedance of larger than 1 GΩ is needed to reduce the input DC current that can damage the tissue [104] or deteriorate the electrodes, especially in long-term implants. Furthermore, given the typically large electrode impedance value (e.g., around 100 MΩ close to DC), a larger input impedance of the neural amplifier is always beneficial to reduce the gain drop due to input voltage division across the impedances which leads to a reduced sensitivity. One way to improve the input impedance of a chopper scheme is by using positive feed- back capacitors wired around a traditional capacitive-feedback amplifier [105]. The positive feedback loop can potentially become unstable if GΩ-resistance is desired [Fig. B.1(a)]. Past 199 FigureB.1: Boostingtheinputimpedanceofchoppingamplifiers: (a)Priorart: positivefeedback addedtoacapacitivefeedbackchoppingamplifier,(b)Priorart: feed-forwardaxillarypathaddedto the input of a capacitive feedback chopping amplifier, (c) Proposed scheme: feed-forward auxiliary path added to the input of a current feedback chopping amplifier. work has shown a self-calibration scheme that controls the positive feedback capacitance [106] . An alternative approach is implementing an auxiliary-path pre-charge buffer that re- duces the charge supplied by the electrodes to the input capacitors, thus boosting the input 200 Figure B.2: Complete implementation of the chopper stabilized current feedback amplifier. impedance [104]. The input DC resistance in these architectures is upper-bounded by the minimumcapacitance(C1)whichsatisfiesthegainrequirement[Fig.B.1(b)]. Here,acurrent feedback amplifier architecture is proposed and implemented [Fig. B.1(c)] which reduces the input capacitance, thereby achieving the highest input impedance reported in the literature for chopper amplifiers. This work, in part, was published in [23]. This appendix covers a more comprehensive discussion on the circuitry and measurements. B.2 System Implementation The proposed neural amplifier (shown in Fig. B.2) consists of three components, namely, an inputimpedance(Z in )booster,acurrentfeedbackamplifier(CFA),andaprogrammablegain amplifier (PGA). In the current feedback amplifier, G m1 and G m2 form the direct gain path while R f1 and R f2 create a resistor divider for the output voltage and the feedback current is generated by G mf . The gain of this stage is given by (G m1 /G mf )(1+2R f2 /R f1 ), where in this implementation G m1 /G mf =10 and R f2 /R f1 = 5. To ensure a small gain variation in the 201 Figure B.3: Detailed schematic of the front-end trans-conductance amplifier: (a) G m1 along with the feedback trans-conductance amplifier G mf and the DC servo loop feedback trans-conductance amplifier G m4 , (b) CMFB amplifier schematic, differential and common-mode transfer functions of G m1 . presence of process mismatches, a common centroid layout is used for trans-conductances G m1 andG mf andforresistorsR f2 andR f1 . Inverter-baseddesignsareusedtorealizeG m1 and G mf , as shown in Fig. B.3(a). This enables lowering of the supply voltage without sacrificing its bias current. Therefore, noise and power consumption can be lowered simultaneously. Supply voltage V DDL (0.6V) is generated from the main supply voltage V DDH (1.2V) using a 90% efficient on-chip switched-capacitor DC-DC converter. The removal of the tail current source in an inverter-based amplifier can drastically reduce the common mode rejection ratio (CMRR), making the differential and common- mode gains equal in all frequencies. However, a common-mode feedback (CMFB) amplifier can mitigate this issue by pushing the common-mode gain high-pass corner ω HP− CM to a higher frequency away from the differential gain high-pass corner ω HP− DIFF [Fig. B.3(b)]. Chopping only upmodulates the differential signal while the common mode signal remains in the baseband. The proposed inverter-based amplifier rejects the common-mode signal for frequencies less than 8.6kHz, while amplifying the upmodulated differential signal at 202 62.5kHz. The 1-100 GΩ-range resistances (R BLK , R INT , R DC and R BIAS ), that are needed for biasing this amplifier, are realized using duty-cycled resistors (DCR) for achieving high linearity and noise performance [104]. Each such DCR consists of a series connection of a polysilicon resistor R, with a value less than 1 MΩ, and an NMOS switch with a gate driven by an independent pulse generator with controllable duty cycle (Fig. B.2). Monte Carlo simulationsofaDCRformedwitha1MΩpolyresistorinserieswithaW/L=400nm/180nm NMOS switch operating at 0.001 duty cycle result in 3σ value of 14 MΩ, which is equivalent to 1.4% variation from the nominal value of 1 GΩ. Duty cycle can vary by 20% due to the global process variations, which is compensated by including tunable capacitor banks in the pulse generators. To remove the DC offset and drift introduced by the electrodes, a current feedback DC servo loop (DSL) is added to the design. The maximum electrode offset that can be toleratedisdeterminedbytheratioof G m4 G m1 . Inthisdesign,atypicalvalueof50mVelectrode offset is considered. The stability of the proposed amplifier, especially given the two current feedback loops used for setting the gain and removing the input DC offset, must be carefully considered. The conventional techniques for stability analysis of LTI systems (e.g., Nyquist criterion) cannot be used for time-variant periodic systems such as the proposed chopping amplifier. For a time-variant system, a set of state equations [dynamic matrix A(t)] can be derived which describe the system’s behavior in time domain. Starting with the Floquet theorem, it can be shown that the necessary and sufficient condition for stability is that all the eigenvalues of the dynamic matrix have non-positive real parts [107]. This analysis is performed on the simplified block diagram as shown in Fig. B.4. The derived eigenvalues for this system are all non-positive, which ensures the stability of the proposed CFA. An auxiliarypathpre-chargeassist [104]isusedtofacilitatecharginganddischargingtheinput capacitance C in , which is dominated by the Miller capacitance at the input terminal of G m1 . A single-stage trans-conductance cell is used as a buffer (G m0 ) with a duty-cycled current to save power. Required clock signals CLKA and CLKB are generated on-chip using a 1-MHz 203 Figure B.4: Simplified block diagram and stability analysis. oscillator (Fig. B.5) and digital delay circuitry consuming 240 nW. A programmable gain amplifier(PGA),followingthechopperfront-end,amplifiesthesignalupto20dB.Capacitor C 1 has a fixed value of 1 pF and capacitor bank C 2 can be programmed to provide 2− 20 dB of variable gain. 204 Figure B.5: Core 1MHz oscillator schematic. B.3 Measurement Results The chopper CFA amplifier was fabricated in a 0.18 µ m CMOS technology Fig. B.6. The entire amplifier consumes 2.6 µ W from a 1.2 V supply. The schematic and picture of the printed circuit board, used for measuring the input impedance, are shown in Fig. B.7. Extra care was given to the PCB design to minimize the input trance length and parasitic capac- itance. To measure the input impedance, a pair of off-chip 100 MΩ resistances are placed in series with the differential inputs and a pair of high-impedance voltage buffers with >1 205 Figure B.6: Die micrograph. TΩ input resistance are used to tap-off the voltage at the amplifier input. The measured buffered voltage reflects the voltage divider between the amplifier input impedance and the off-chip 100 MΩ series resistances. Fig. B.8 shows measured voltage gain, input impedance, and input-referred noise versus frequency. The graph shows that the input impedance reaches a maximum of 3 GΩ below 0.1 Hz. The transfer functions for different gain and high-pass corner settings as well as for different input offset voltages are shown. The pulse width for R INT is changed from 0.7-7 ns to adjust the high-pass corners. Any offset introduced by G m1 is chopped and appears at the amplifier input as a large signal, which compresses the apparent small signal gain of the amplifier due to the third-order nonlinearity, as shown in Fig. B.8(b). 206 Figure B.7: Test bench for input impedance measurement. B.4 Discussion B.4.1 Linearity Analysis One downside of the proposed scheme is that, the open-loop nature of G m1 limits the overall linearity. Consequently, compared with capacitive-feedback amplifiers, the total harmonic distortion (THD) of this scheme is worse, which will be discussed in full detail below. AsimplifieddiagramoftheCFAforlinearitycalculationsisshowninFig.B.9. Consider- ing contribution of G m1 and G m2 to nonlinearity of the system and assuming the third-order nonlinearity as the dominant higher order term, I 1 =a 1 V in +a 3 V 3 in , (B.1) 207 Figure B.8: Measured transferfunctions: (a)voltagegain with different settings, (b)voltagegain variation as a function of the input offset voltage, (c) input impedance, (d) input referred noise. Figure B.9: Simplified schematic of the CFA for linearity analysis. I 2 =b 1 V x +b 3 V 3 x . (B.2) The V in − V o relationship can be derived as follows, V o =b 1 R x R o (a 1 V in +a 3 V 3 in − αG mf V o )+b 3 R 3 x R o (a 1 V in +a 3 V 3 in − αG mf V o ) 3 , (B.3) 208 Figure B.10: Simplified schematic of a regular capacitive-feedback (RCF) amplifier. where R o =R f2 + R f1 2 and α = R f1 2R f2 +R f1 . The amplifier’s THD can be derived and approxi- mated as, THD CFA ≈ a 3 a 1 V 2 in . (B.4) This result implies that linearity of the CFA is limited by the linearity of G m1 . To compare the proposed CFA’s nonlinearity with a regular capacitive feedback (RCF) amplifier, let us consider a simplified schematic for such a circuit as as hown in Fig. B.10, where β is the feedback factor. Following the same derivation and approximations, THD can be approximated as THD RCF ≈ a 2 1 R 2 x 1 (1+βa 1 b 1 R x R o ) 3 b 3 b 1 V 2 in , (B.5) which implies that the nonlinearity of the RCF is dominated by G m2 . To verify the results, a capacitive feedback amplifier with similar closed loop gain of 100 was designed using the same G m cells as the proposed CFA but in a capacitive feedback architecture with C 1 =10pF and C 2 =100fF. Taylor series coefficients of G m1 and G m2 were simulated and derived independently: V out,Gm1 =50V in,Gm1 − (2.5× 10 4 )V 3 in,Gm1 , (B.6) V out,Gm2 =150V in,Gm2 − (1.7× 10 5 )V 3 in,Gm2 . (B.7) 209 Table B.1: Simulated and calculated coefficients for the CFA and RCF amplifiers. Assuming the following input-output relationship for the closed-loop amplifiers, V o =c 1 V in − c 3 V 3 in , (B.8) the simulated and calculated coefficients for CFA and RCF amplifiers are derived and shown in Table B.1. Fora1mV p inputtoneat1kHz, thesimulatedTHDfortheCFAandRCFconfigurations is-56dBand-96dBrespectively. WecanconcludethatthelinearityoftheproposedCFAis limited by the linearity of G m1 and not enhanced by the loop gain. However, in a capacitive feedback architecture, the linearity is determined by G m2 and enhanced by the loop gain. B.4.2 Noise Analysis As can be seen from the noise spectral density in Fig. B.8(d), there is a residual 1/f noise even after the chopping. At low frequencies, R int and G m3 in the DSL path dominate the input-referrednoise. UsingthesimplifiedschematicshowninFig.B.11(a),theinput-referred noise due to R int and G m3 , can be derived as follows, S vn,in = 1 A 2 4kTR int 1+(ωC int R int ) 2 + 1 A 2 ( G m4 G mf ) 2 1+(ωC int R int ) 2 1+(αωC int R int ) 2 S vn,Gm3 , (B.9) S vn,in ≈ 4kTR int A 2 ( ω HP ω ) 2 +S vn,Gm3 ( G m4 G m1 ) 2 , (B.10) whereA= G m1 αG mf isthemid-bandclosed-loopgain, ω HP = 1 R int C int isthehigh-passcorner, α = R f1 2R f2 +R f1 , S vn,Gm3 is the input-referred noise of G m3 and the approximation is valid for the pass-band. The equation shows that the input-referred noise spectral density due to R int 210 Figure B.11: (a) Simplified block diagram of the chopper amplifier for noise analysis and (b) the schematic of G m3 . is shaped by the integrator and follows a 1 ω 2 behavior. Simulation and analysis results are 211 Figure B.12: Input-referred noise spectral density derived from simulation and analysis. Table B.2: Noise contribution of R int and G m3 in the 1− 200Hz frequency band plotted in the Fig. B.12 , for R int =1TΩ and C int t=1pF. Convergence of simulation and analysis plots at lower frequencies validates the dominance of the noise due to R int and G m3 . Simulated contribution of R int and different transistors in G m3 towards the total inte- grated input-referred noise in the 1− 200Hz band is shown in Table B.2. R int and G m3 contribute to 76.8% of the total noise. For a given ω HP = 1 R int C int , which is typically set by the application requirements, the input-referred noise due to R int can be reduced by de- creasing the value of R int and in turn increasing the value of C int . This will increase the chip size which is undesirable for the envisioned multi-electrode system application. The input-referred flicker noise due to G m3 can be reduced by increasing the transistor sizes, which again will increase the chip size. 212 B.5 Conclusion Table B.3 summarizes the performance of this neural amplifier front-end in comparison with the current state-of-the-art reported designs. The combination of voltage gain, noise, input impedance, area and power consumption are favorable for this design, confirming the usefulness of the proposed scheme. In future designs, a low-power voltage buffer may be added in the feedback path to reduce the size of R f1,2 without loading G m2 , hence reducing the area of this design by around 0.02 mm 2 . The total input-referred noise of the scheme will still be dominated by G m1 . Compared to chopper amplifiers which support similar bandwidth and/or gain require- ment,theachievedNEFissuperiororatleastcompetitive. Stackedinverter-basedamplifiers [100] can potentially be used to further improve the NEF of the front-end amplifier (it can be used as G m1 in this scheme). However, there exist some limitations to the vertically stacked inverter-based amplifier: (1) Vertically stacking N inverters require N output cur- rent branches to combine, increasing the peripheral power consumption. (2) There is a limit onNandtheamountthattheinputAC-couplingcapacitancecanbesplitsincethetransistor gate capacitance can cause voltage division causing signal attenuation in the front-end.This sets a trade-off between the minimum channel area and noise performance. (3) As the num- ber of the channels increases, routing multiple biasing wires across the chip can become complicated. 213 Table B.3: Performance Summary and Comparison with State-of-the-art Bio-potential Amplifiers This work [100] JSSC’18 [101] JSSC’18 [103] JSSC’15 [105] ISSCC’16 [106] CICC’17 [104] JSSC’17 Target Signals AP, LFP AP, LFP AP, LFP LFP EEG, LFP ECG AP, LFP Technology 180 nm 180 nm 180 nm 65 nm 180 nm 180 nm 40 nm Supply (V) 0.6, 1.2 1 0.5, 1.0 0.5 0.2, 0.8 0.8 1.2 Channels 1 1 128 64 1 1 8 Input Referred Noise (µ V rms ) AP: 3.2, LFP: 2.0 5.5 (250Hz- 10kHz) 3.32 (0.5Hz- 12.7kHz) 1.3 (1Hz- 500Hz) 0.94 (0.5Hz- 670Hz) 8.26 (1Hz- 400Hz) AP: 5.3, LFP: 1.8 Power/Ch (µ W) 2.6 a 0.25 1.22 c 2.3 0.79 0.255 2.8 NEF AP: 3.2, LFP: 9.9 1.07 3.02 4.76 2.1 7.01 AP: 4.4, LFP: 7.4 3dB-BW (Hz) 0.5 - 5k 4 - 10k 0.4 - 10.9k 1 - 500 DC - 670 <400 0.1 - 5k Gain (dB) 41-59 25.6 37.5-52.9 N/A 50.8-57.8 34 25.7 CMRR (dB) 70 84 >60 88 85 66 77 THD (%) 1.7 b 1mV pp,in 1kHz N/A 0.02 d 3mV pp,in 1 kHz 0.4 1mV pp,in 40 Hz 0.3 b 1.5mV pp,in 100Hz N/A 0.3 80mV pp,in 1 kHz Area/Ch (mm 2 ) 0.08 a 0.29 0.05 0.025 1 0.581 0.069 Z in (DC) 3.0 GΩ ∞ ∞ 28 MΩ 116 MΩ e 200 GΩ 1.6 GΩ Z in (100 Hz) 500 MΩ 200 MΩ 80 MΩ N/A N/A 10 GΩ 800 MΩ Electrode Offset Removal Current feedback DSL AC coupled AC coupled DAC feedback DSL No DSL RC integrator DSL Action Potential (AP): 200 Hz – quoted bandwidth, Local Field Potential (LFP): 1 Hz - 200 Hz. a excludes clock and DC-DC converter circuitries. b maximum gain setting. c LNA and PGA blocks are considered only. d LNA stage only. e estimated. 214 Appendix C Future Direction: Scalable Bidirectional Interfaces Tofindbetteranswersforthecauseoftheneurologicaldisorders,wehavetoachieveabetter understanding of the complex neuronal networks in the brain. In a recent study reported by the neuroscientists at University College London [108], the multidimensional representa- tions of behavior in electrophysiological recordings were investigated. Implementation of 8 Neuropixelsprobes [109]allowedforsimultaneousrecordingsfrom∼ 3000neuronsacrossthe brain, namely the frontal, sensorimotor, and retrosplenial cortex, hippocampus, striatum, thalamus, and midbrain [Fig. C.1]. The analysis of this simultaneously recorded data across the brain suggested that the integration of sensory inputs with motor actions occur as early as primary sensory cortex. This and other similar findings justify the need for simultaneous recordings from different regions of the brain with high spatial and temporal resolutions, which can help in decoding the firing patterns and the correlation between the activity of the neurons in complex neuronal circuitries. C.1 Case Study 1 As the density of the neural recording and stimulation micro-electrodes increases, the size of the neural interface electronics can become a limiting factor for an implantable bidirectional neural interface. Multiplexing the recording front-ends might seem an intriguing solution to save the silicon area; however, for a simultaneous reading of all the channels, a periodic 215 Figure C.1: Acute murine brain recording test bench and a conceptual diagram of simultaneous recording configuration from across the brain. switchingandsamplingatthefront-end(beforeamplification)folds-backthethermalnoiseto the signal bandwidth, which drastically reduces the SNR. Another disadvantage would be a reductionin the inputimpedance andDC leakage currentsthrough therecording electrodes. Therefore,thedesignersusuallydedicateanamplifiertoeachchannelandtheymultiplexthe signals in 2 steps: analog multiplexing before quantization and digital multiplexing before datatransmissionasdepictedinFig.C.2. ArecentlydevelopedactiveCMOS-basedprobeis reported in [48], which can record from 384 electrodes simultaneously out of an addressable 5120 sites available on 4 shanks (a denser version of the Neuropixels probes developed by IMEC). Each shank is 10 mm long and 70 µ m wide. To accommodate a packed routing of the signals from the electrodes to the base, 2 metal layers were used with a center-to-center pitchof 0.36µ m. Ifallthe 1280electrodes were tobe routedon each shankfor simultaneous recordings of all the channels, and assuming having access to no more than 2 metal layers for routing, the shank width would have to be increased undesirably to 230 µ m (a factor of 3 degradation). Longer shanks and more electrodes will undoubtedly exacerbate the routing challenge. Another potential issue rises from crosstalk between closely spaced traces. For the mentioned active probe, the worst case measured crosstalk (from all channels to one) was -36.4 dB (1.5%) at 1kHz, which can be problematic in spike sorting and single-unit 216 Figure C.2: The Neuropixels: Conventional signal conditioning and quantization approach. detection. This crosstalk is mostly due to the capacitive coupling (C xc ) between neighboring metal traces as demonstrated in Fig. C.3(a). The electrode and front-end interface can be modeled as in Fig. C.3(b). Z e,1 and Z e,2 are electrode-tissue impedances, while C in is the net input capacitance to the front-end electronics. A 0.2µ m trace thickness (h) and a 0.2µ m trace spacing (g), which are dictated by the fabrication process and design rules, result in a coupling capacitance of 0.35 pF/cm assuming a silicon dioxide substrate with dielectric constant of 3.9. For large mammalian experiments, and potentially for humans, the shank length may even reach 10 cm. This results in a significant coupling capacitance of 3.5 pF. Let us assume having platinum electrodes with 20 µ m diameter, with 1 MΩ impedance at 1kHz [41]. Assuming a reasonable value of C in =3.5 pF, the impedances can be simplified to Fig. C.3(c) at 1kHz frequency. This network of impedances result in -33 dB leakage from side-to-side traces. Assuming electrode 2 is picking up signals from a close-by neuron with magnitude 400 µ V, while electrode 1 is receiving signals from a farther neuron with 10 µ V amplitude, channel 1 would receive the 2 signals with almost the same magnitude. This gets much worse considering all other traces which are potentially recording from spatially-apart regions of the brain. C.2 Case Study 2 The active probes on silicon may be promising for acute experiments in animal models, but for a potential chronic implantation of a neural interface, other possible configurations 217 Figure C.3: Crosstalk issue (a) Geometry of 2 adjacent traces on a probe. (b) Simplified model of the impedances involved in crosstalk. (c) Estimated model parameters at 1kHz. should be investigated, which are shown in Fig. C.4. As can be seen with the FDA-approved and clinically-available responsive neurostimulation (RNS) system, the device can be placed in or on top of the skull as shown in Fig. C.4(a). This geometry allows for low-power data telemetry with an external wand due to the closer proximity to the surface; however, future complex implants (such as visual cortex implants for perfect visual perception restoration) mightrequirerecordingandstimulatingthousandsorevenmillionsofneuronsfromdifferent regions of the brain. Scaling the routing effort for 8 wires (in RNS) to 1000 may not be feasible with such scheme. Fig. C.4(b) shows a more promising solution, which relaxes the routing burden by local amplification, buffering, and multiplexing the analog waveforms on the front-end chips. A back-end chip quantizes the signals and transmits the data out. A 65,536-channel recording system (The Argo) with such configuration has been recently reported [110](the simplified block diagram of the system is shown in Fig. C.5), but due to the insufficient published details on the system specifications, further analysis is needed to study the potential shortcomings of such architecture, which is presented below. To examine the scalability of the analog-voltage multiplexing platform, a simple test bench is examined in Fig. C.6(a), where only 1 channel is shown for simplicity. After a front-end amplification, the full-scale signal is buffered and multiplexed. The buffer should 218 Figure C.4: Possible configurations of chronic neural interface implants. (a) Single chip (b) Dual chipwithfront-endamplification,voltagemultiplexinganddelivery(c)Dualchipwiththeproposed sensing array front-end. The microelectrode arrays can be depth or surface electrodes. be able to drive the load capacitance (C L ), which is the summation of the input capacitance of the PGA that follows and any stray capacitance (a reasonable capacitance of 10 pF is assumed in this example). As the number of the parallel channels (N) increases, the buffer 219 Figure C.5: The Argo system architecture. FigureC.6: (a)ConventionalrecordingAFEfront-end(b)Proposedvoltage-to-currentconversion sensor array. shouldchargetheloadcapacitanceinashortertimebecausethesamplingperiodperchannel should remain constant (T s ). Assuming a settling requirement of 0.25 LSB for the buffer 220 output during the sampling period, one can find the relationship between the channel count and the required current for the buffer, e − Ts/N C L /gm <2 − (N B +2) , (C.1) where N B is the ADC resolution. Transconductance g m is a function of the device current g m = f(I B ), which simplifies the equation to, (N B +2)ln(2)C L f s N <f(I B ), (C.2) where f s =1/T s is the sampling speed per channel. With a limited area for the buffer per channel, which is set by the design constraint, increasing the number of the channels would need a higher g m and hence a larger current, which pushes the MOS devices into the strong inversion region, where a square-law governs the I-V relationship and g m ∝ √ I B . This suggests that I B ∝ N 2 , which shows a quadratic growth of current as a function the channel count. [110] has implemented a current sharing scheme, which is equivalent to duty cycling thebuffer: Turningthebufferononlyduringthesamplingduration,whichisT s /N.However, this would only reduce the square-law dependence of the buffer current on the channel count toalinearrelationshipI B ∝N.Ingeneral,animplanteddenseelectronicshasapowerbudget per pixel since the local tissue has a limited capacity for distributing the generated heat. Therefore,thelinearscalingofthepowerconsumptionperpixelwiththetotalchannelcount is not desirable. C.3 Proposed Current-Multiplexing Scheme The summary of the existing issues is as follows: Trace routing 221 – Implantable probes: Routing individual electrodes from the shanks to the base limits the shank width in large scale arrays. – Dual chip Configuration: Routing thousands of wires from the front-end chip to the back-end platform is not practical. Crosstalk – Implantable probes: Capacitive coupling due to the long traces with small spac- ing becomes more severe as the number of simultaneously recordable electrodes increases. – Dual chip Configuration: Capacitive coupling may also be an issue with parallel wires running from the front-end chip to the back-end platform. Existing solution – Multiplexing the voltage signals has been proposed before to solve the issues mentioned previously; however, it is not scalable due to the power consumption constraints. Here, I propose an alternative scheme, which can mitigate the aforementioned issues lim- iting the scalability of the dense front-end architectures at low power. As demonstrated in Fig. C.4(c), instead of delivering the amplified signal directly in the voltage domain, which puts the burden of driving the capacitive loads on the resource-limited pixel array, an operational transconductance amplifier (OTA or g m cell) can convert the voltage to an output current. The currents from individual pixels are multiplexed and transferred to a transimpedance amplifier (TIA) at the receiver. The TIA output can further be amplified and quantized at later stages. The simplified model for one channel is shown in Fig. C.6(b). This architecture offers the following advantage: Since the g m cell is interfaced with a low- impedancenode,whichisthevirtualgroundoftheTIA,anystraycapacitanceonthislinehas little effect on the drive capability of the transconductance cell. Replacing the voltage buffer 222 Figure C.7: Multiplexing clock Φ 1 . Figure C.8: Output voltage waveforms in the conventional and proposed scheme. with an OTA driver would make the power consumption per pixel independent of the total channel count. It is worthwhile to compare the noise performance of the 2 schemes. In both schemes, the front-end amplifiers contribute to the majority of the noise. The input-referred noiseaddedbynextstagesisdividedbythegainofthefirststage. Giventhelow-impedance output node, the driver OTA g m can be reduced to even save more power; however, its noise contribution and the noise-folding by the multiplexing switch will dominate at some point and limit further g m reduction. The test bench in Fig. C.6 is simulated assuming multiplexing between N=1000 channels and f s =20 kHz. The total gain for both schemes are made equal to 100. The switching clock Φ 1 for channel 1 is plotted in Fig. C.7, which shows a periodic pulse with 50 ns width and 50 µ s period. Fig. C.8 shows the output voltage of the conventional (V buff,out ) and proposed 223 Figure C.9: Output voltage waveforms in the conventional scheme with 2 different buffer driving capability. schemes (V isense,out ), assuming similar g m for both the voltage buffer and the driver OTA, and V amp,out is the ideal output voltage waveform. It can be observed that with the same load capacitance and power consumption, the buffered voltage cannot follow the original waveform during the short pulse duration. However, the output current in the proposed scheme can recreate the sampled ideal output waveform. A factor of 10 increase in the g m of the buffer, which is equivalent to at least 10 times more current, improves the transient response, as can be seen in Fig. C.9. The realization of the proposed approach on an active probe is shown in Fig. C.10. A distributedarrayofamplifiersandOTAsacrosstheshanksconvertstheinputvoltagesignals into current-domain signals. The generated currents (i 1 , i 2 , etc) are combined into a single line with a total current of i out for each shank. These single traces from the shanks can be routed to the base of the probe with a relaxed spacing requirement given the significantly- reduced number of parallel lines. An array of TIAs at the front-end of the receiver converts theinputcurrentintovoltage, andthefollowingPGAscanprovideadditionalgainandanti- aliasing filtering for the ADC. For a scalable design, the individual pixels should generate the multiplexing pulses locally. The same core clock must be used at the receiver for proper ADCsamplingintervals. Thisarchitecturepotentiallymitigatesthechannelcrosstalk,which was due to the closely-packed long traces on the shanks. However, further simulations and 224 Figure C.10: Block diagram of the proposed architecture (top) and a possible implementation as an active probe (bottom). Inside the pixels, block D represents the digital circuitry for timing and the x10 is the front-end amplification (M: shank count). analysis are needed to quantify the crosstalk due to multiplexing and how it affects the total system performance. A proof-of-concept prototype of the proposed scheme with 4x4 parallel recording chan- nels will be implemented in a CMOS technology, as shown in Figure. C.11. Commercially available TIA, ADC and FPGA will be used to interface the sensor array with a PC. The system has been simulated in Cadence assuming ideal components, as shown in Fig. C.12. The front-end amplifier, OTA and the back-end TIA determine the overall voltage gain of the system, which is assumed 100 in this case. For 16 pixels and 20 kHz sampling speed per channel, the pulse duration for multiplexing is 3.125 µ s. The input voltage waveforms of 4 of the channels and their corresponding outputs are shown in Fig. C.13. 225 Figure C.11: Proposed neural recording platform using the current-multiplexed sensor array and the back-end receiver. C.4 Limitations and Mitigation There is lack of experimental data on how brain responds to chronic heating by an implant, but the central nervous system tissue is generally known to be very sensitive to temperature increases (neuronal death in animal models has been observed after 1 hour of heating at 40.5 ◦ C [111]). Studies of implants in lung and muscle tissues [112] have suggested that a maximum surface heat source density of 40 mW/cm 2 is tolerated by the local tissue (<2 ◦ rise in temperature). This limit provides us with a starting point to find the constraints on the power and area consumed by the sensing pixels. Assuming 4 µ W of power consumed per pixel, which is a reasonable value to meet the noise requirements, a minimum area of 0.01 mm 2 per pixel is required for sufficient heat distribution across the surrounding tissue. There are also other considerations regarding the proposed approach using OTAs as output drivers that need to be addressed: 226 Figure C.12: Simulation test bench for the proposed current-multiplexed AFE. Vulnerability to PVT variations: Implementing a constant-G m biasing for the driver OTAs mitigates process, voltage and temperature variations. Linearity: Giventhenormalrangeofneuralsignals(belowafewmV),andgiventhat the OTA drives a low-impedance node, the linearity will be determined by the later stages such as the PGA similar to the conventional architecture. DC offset : Another important factor is the higher offset in an open-loop OTA, which should be fully analyzed and considered using Monte Carlo simulations. CMRR: Common-mode rejection in the conventional capacitive-feedback voltage am- plifier scheme, depends on the device matching and layout, especially the metal- insulator-metal (MIM) capacitors. Clock feedthrough: The capacitive coupling of the multiplexing clock signals to the outputlinecanbemitigatedbychoosingsmallerMOSswitches. Thisisnotusuallyan 227 Figure C.13: Input and output voltage waveforms in the system for channels 1 to 4 (a) Input. (b) Output. option in voltage multiplexing, which requires a large switch for fast transient settling. On the other hand, since the clock is leaked to a low impedance node, it will not be input-signal dependent and during demultiplexing, it will be down-converted to DC and harmonics of the fundamental, which can be filtered in the digital domain. Noise: Similar to the conventional scheme, the front-end g m cell is the dominant noise contributor. Power: Power consumption in the pixels will be determined mainly by the noise considerations (input g m cell) and given the low speed of the digital blocks, the digital power consumption is negligible. TIA speed: As the number of channels increase, the TIA’s bandwidth needs to scale linearly and this limits its maximum transimpedance resistance, which has 2 possible solutions: 228 Table C.1: Target Specifications Parameters Specifications Supply 1.0 V Channels 16 BW -3dB 1Hz-10kHz IRN < 5µ V rms Gain (Amp+OTA+TIA) > 40dB THD < 0.1% CMRR > 60dB Z in (1kHz) > 50MΩ Sensor array power/pixel < 4µ W Sensor array area/pixel 0.01 mm 2 Crosstalk <-50dB – IncreasingthepixelOTAg m ,whichmaynotbeanoptiongiventhepowerdensity requirement. – Dividing the pixel outputs into multiple wires to reduce the switching speed on each line, and interface them with an array of TIAs (similar to the scheme shown in Fig. C.10). Crosstalk: Crosstalk depends on how fast the output line is settled, and for the proposed scheme, the TIA bandwidth will limit the crosstalk. Table C.1showsthesuggestedtargetspecificationsfortherecordingsensorarray. Future physical implementation of this scheme can further examine the scalability of this approach in neural interfaces. 229
Abstract (if available)
Abstract
Closed-loop brain-machine interfaces have become critical components in neuroscience research and clinical applications. These systems record the neural activity, perform signal processing algorithms, and generate a specific spatiotemporal pattern to stimulate the neurons in the brain. Unfortunately, stimulation of the brain tissue introduces an artifact at the recording channels, which can significantly degrade the received signal quality. This dissertation introduces two approaches to mitigate the stimulation artifact. One approach is a front-end (FE) cancellation scheme that incorporates a least-mean squares (LMS) engine that adapts the coefficients of a two-tap infinite-impulse-response (IIR) filter to replicate the stimulation artifact waveform and subtract it at the FE. Measurements demonstrate the efficacy of the canceler in mitigating artifacts up to 700 mVpp and reducing the FE amplifier saturation recovery time in response to a 2.5-Vpp artifact. Each recording channel houses a pair of adaptive IIR filters, which enables the cancellation of the artifacts generated by the simultaneous operation of the two on-chip stimulators. The analog FE consumes 2.5 μW of power per channel and has a maximum gain of 50 dB and a bandwidth of 9.0 kHz with 6.2- μVrms integrated input-referred noise. ❧ The existing FE cancellation techniques provide a limited artifact suppression (< 40dB) which reduces a 1000 mVpp artifact to about 10 mVpp swing. This residual artifact is still 1-2 orders of magnitude larger than the neural spikes and local field potentials, which can potentially saturate the amplifiers. The second proposed approach is a multi-channel neural interface with a two-point stimulation artifact cancellation technique which boosts the common-mode and differential-mode stimulation artifact suppression to 68.5 dB and 58.1 dB, while handling artifacts as large as 1200 mVpp and 700 mVpp, respectively.
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Samiei, Aria
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Bidirectional neural interfaces for neuroprosthetics
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Viterbi School of Engineering
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Doctor of Philosophy
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Electrical Engineering
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2022-05
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01/12/2022
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adaptive filter
multi-point stimulation artifact suppression
neural recording
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