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III-V semiconductor heterogeneous integration platform and devices for neuromorphic computing

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III-V semiconductor heterogeneous integration platform and devices for neuromorphic computing

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Content III-V Semiconductor Heterogeneous Integration Platform and Devices for Neuromorphic Computing by Jun Tao A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) August 2022 Copyright 2022 Jun Tao ii Dedication To my fiancée Nuo Wang, and to my parents, Zhixin Tao and Caiping Bao. iii Acknowledgments When I got the admission letter from USC back to the Chinese spring festival 2017, I was thrilled and excited, but cannot picture this journey very well. Now I look back, it’s a fantastic adventure filled with moments of failure, lost, exhaustive, hesitation, and self-denial, but more of motivation, dedication, growth, and small achievements. I feel blessed to meet and work with so many outstanding faculties, colleagues, and friends, without whom I cannot go through this wonderful experience and have the invaluable memory in my lifetime. First, I’d like to present my heartiest appreciation to my research advisor Prof. Rehan Kapadia. Throughout my Ph.D. program, he not only supported and inspired my research work with insightful academic advice and guidance, but also focused on cultivating me as an independent researcher. He didn’t blame me when I messed up precious equipment, when I was stuck in my hometown due to the visa issue, or when I triggered a toxic gas alarm from MOCVD lab, but faced and solved these difficulties and many others together with me. Additionally, he trained me on how to write an academic paper properly, how to communicate efficiently, and even how to present properly in conference meetings. There are endless examples I cannot enumerate here to describe his efforts in constructing me into a better researcher. I’ll take all the lessons and strive in my future life. I was very fortunate to get the chance to work with Prof. Paul Daniel Dapkus, who is among the pioneers inventing the MOCVD technique, and being trained up as a user for the system. His rich experience, knowledge, and anecdotes from the golden era of semiconductor research always remind me to be scientific and solid in research but stay robust and humorous in life. It’s impossible to finish much of my work without Prof. Steve Cronin’s generously sharing of many equipment from his lab, and I learned a lot from being a TA for his semiconductor physics class. I’d like to iv thank Prof. Ravichandran, from whom I learned many deep insights about semiconductors growth and characterization, and Prof. Wu, from whom I learned nanofabrication techniques. I’d like to thank Prof. Yang for serving on my committee for the qualify and defense exam, and I learned a lot from his work in memristors. I’d like to thank Prof. Han Wang, who shared lab equipment as well. Special thanks to professors, from whom I took courses like Prof. Levi, Prof. Prata, and Prof. Tanguay. A large portion of my time was spent in Nanofabrication Lab and Core Nano Imaging center, where I got support and help from many staff and scientists including Dr. Donghai Zhu, Alfonso Jimenez, Dr. Shiva Bhaskaran, Joey Vo, Dr. Avishai, and John Curulli. Special thanks to Megan Utley and Anthony Rodriguez. Next, I would like to appreciate my colleagues and peers. Dr. Debarghya Sarkar trained me on every equipment and led me into many interesting projects, and co-authored many research papers. Dr. Mitchell Dreiske trained me for MOCVD and helped out with many trouble shootings. Dr. Qingfeng Lin let me join his family dinner and shared ideas about his career path. Dr. Fatemeh Rezaeifar taught me being focus and persist in the work at hand. Hyun Uk Chae, who started the journey at a similar time and built a special bond with me, we shared many research ideas, personal life, and important life moments. Ragib Ahsan always brings joyful talks, discussions of interesting research ideas and fundamental physics. Previous lab member Salil Kale offered a lot of help with device measurement. Juan Vanzquez, Subrata Das, Zezhi Wu, and Anika Priyoti are the lab juniors who offered a lot of help in research work as well. Hope they will achieve great results from our research projects and publish impactful papers. Many colleagues from other research groups like Huandong Chen, Boyang Zhao, Mythili Surendran, Dr. Jiangbin Wu, Dr. Xiaodong Yan, Hefei Liu, Zhonghao Du, Nan Wang, Jiahui Ma, Hyung-Yu Chen, Max Lien, v Hongming Zhang, Dr. Hai Liu, Dr. Yongkui Tang, Jaehoon Lee, Mashnon Sakib, Dr. Boxiang Song, Dr. Hao Yang, Deming Meng, Buyun Chen, Yunxiang Wang, Pan Hu, Tse-Hsien Ou, Zerui Liu, Dr. Haotian Shi, Dr. Yu Wang, Bofan Zhao, Zhi Cai, Boxin Zhang, Sizhe Weng, Ruoxi Li, Dr. Fanqi Wu, Mingrui Chen, Dingzhou Cui, Lucas Jordao, Biran Feng, Daniel Goodelman, Dr. Shiyu Su, Qiaochu Zhang, and Ye Zhuo all kindly offered great help to my research work. This list can go on with thankfulness in my mind. I’d like to appreciate the help from the department’s administrators who played the important role in our research work, including Kim Reid, Ana Chan, Esrath Rumki, Susan Zarate, Jennifer Ramos, Andy Chen, Diane Demetras, Tracy Charles, Jennifer Gerson, and Cathy Huang. Finally, I’d like to express my deepest gratitude to my fiancée Nuo Wang, who support, encourage, and trust me unconditionally. She sacrificed many aspects of her life to love me, help me out when I’m upset or depressed from research work, and be committed to embracing the future with me. I also would like to thank my parents Zhixin Tao and Caiping Bao, who always keep me in mind and support all my decisions. I sincerely dedicate my dissertation to my fiancée and parents. vi Table of Contents Dedication ...................................................................................................................................... ii Acknowledgments ........................................................................................................................ iii List of Tables .............................................................................................................................. viii List of Figures ............................................................................................................................... ix Abstract ........................................................................................................................................ xv Chapter 1 Introduction ................................................................................................................ 1 1.1 Motivation of hardware-based neuromorphic computing ........................................................... 1 1.2 State of the art emerging devices ................................................................................................. 7 1.3 Opportunities of III-V based devices ......................................................................................... 12 1.4 Overview of the thesis proposal ................................................................................................. 16 Chapter 2. BEOL compatible monolithic III-V integration on amorphous substrates ....... 17 2.1 Introduction ................................................................................................................................ 17 2.2 Large area single crystalline III-V integration ........................................................................... 19 2.3 Low-temperature high mobility InAs ........................................................................................ 26 2.4 Summary .................................................................................................................................... 32 Chapter 3. III-Vs heterogeneous epitaxy on Si by TLP and MOCVD .................................. 33 3.1 Introduction ................................................................................................................................ 33 3.2 MOCVD InP on Si substrate ..................................................................................................... 33 3.3 Crystal orientation alignment and defect filtering by TLP ........................................................ 40 3.4 Summary .................................................................................................................................... 49 Chapter 4. Artificial synapse emulated by InP FETs .............................................................. 50 vii 4.1 Introduction ................................................................................................................................ 50 4.2 InP synaptic device .................................................................................................................... 50 4.3 Gate dielectric engineered InP synaptic device ......................................................................... 57 4.4 Summary .................................................................................................................................... 66 Chapter 5. Optical Synapse by FG-PFETs for Machine Vision ............................................. 67 5.1 Introduction ................................................................................................................................ 67 5.2 Floating-gate PFETs .................................................................................................................. 67 5.3 ONN Constructed from FG-PFETs for colorful image recognition .......................................... 75 5.4 Summary .................................................................................................................................... 79 Chapter 6. Conclusion and outlook ........................................................................................... 80 6.1 Conclusion ................................................................................................................................. 80 6.2 Outlook ...................................................................................................................................... 82 References .................................................................................................................................... 84 viii List of Tables Table 3. 1 MOCVD epitaxy recipe of InP on Si with GaAs nucleation buffer ............................ 38 Table 4. 1 Fitting results for PSC after N pulses .......................................................................... 62 ix List of Figures Figure 1. 1 Annual size of global datasphere source: IDC. ............................................................ 1 Figure 1. 2 A schematic of the organizational principles of the brain. From ref 9 . ........................ 3 Figure 1. 3 Architecture of LeNet-5 from ref 15 . ............................................................................. 5 Figure 1. 4 Real-time multi-object recognition on TrueNorth. Modified from ref 22 . .................... 6 Figure 2. 1 State-of-the-art technologies to integrate III-V semiconductors on Si wafer. Modified from ref 55 . ..................................................................................................................................... 18 Figure 2. 2 TLP approach directly integrate InP on Mo foil ........................................................ 18 Figure 2. 3 Overview of the large area TLP growth of crystalline compound semiconductors. (a) Schematic of TLP growth process. (b) Representative optical microscope. ................................ 20 Figure 2. 4 Electron backscatter diffraction (EBSD) map of Hall elements ................................ 21 Figure 2. 5 Optoelectronic Characterization (a) Photoluminescence of InP and (b) Raman spectrum of InAs. .......................................................................................................................... 22 Figure 2. 6 Scanning electron microscope (SEM) image of (a, b) as grown pattern, (c, d) after selective side-growth etch pattern, (e, f) after top capping layer etch pattern, (g) after electrodes deposition pattern. (h) Schematic of complete device for Hall measurement. ............................. 23 Figure 2. 7 (a) Hall mobility of TLP InAs, (b) Sheet resistance of TLP InAs, (c) Hall mobility of TLP InP, (d) Sheet resistance of InP. ............................................................................................ 25 Figure 2. 8 (a) InAs mobility with and without surface roughness fitted to experimental data, (b) InP mobility with and without surface roughness fitted to experimental data. ............................ 25 Figure 2. 9 Schematic of a dual-zone furnace system for LT-TLP. ............................................. 26 Figure 2. 10 Overview of the LT-TLP growth of III-V semiconductor ....................................... 27 x Figure 2. 11 (a) SEM of a fully fabricated InAs hall element, (b) EBSD map of InAs hall element, (c) AFM map of surface roughness, (d) Raman spectrum of LT-TLP InAs. ............................... 28 Figure 2. 12 (a) Experimental and theoretical Hall mobility, (b) Sheet carrier density, (c) Theoretical calculation of InAs mobility with and without surface roughness scattering, (d) InAs electron mobility as a function of RMS surface roughness. ......................................................... 29 Figure 2. 13 Comparison plot for electron mobilities of different material families monolithically integrated on amorphous dielectrics. ............................................................................................ 31 Figure 3. 1 Sketch of the APB formation in the {111} and {110} lattice planes of the GaP zinc- blende structure due to the presence of mono-layer steps 64 .......................................................... 34 Figure 3. 2 TEM images of InAs and InAs1-xSbx nanowires showing defect-free regions of wurtzite and zinc-blende structures and the various planar defects that are observed in both structures 65 . ....................................................................................................................................................... 35 Figure 3. 3 SEM images of 45° tilted InP on (100) Si substrate (a) without GaAs nucleation layer (b) with GaAs nucleation layer before the InP nucleation step. Scale is 1 𝜇𝑚. ........................... 39 Figure 3. 4 TEM of MOCVD InP and Si interface with GaAs nucleation step at (a)190,000 (b) 820,000 magnification. (b) is the white square area in (a). Arrows indicate annihilation of APBs. ....................................................................................................................................................... 39 Figure 3. 5 Schematic of process. (a) Pretreated Si substrate. (b) InP epitaxy layer on (100) Si wafer. (c) Evaporate templated In and SiO2 capping layer. (d) TLP growth with hydride gas. (e) Remove side growth by III-V etcher. (f) Remove capping layer by dry or wet etch. .................. 40 Figure 3. 6 (a) SEM image of InP by TLP growth on epitaxy InP on Si. Scale is 2𝜇𝑚. (b) TEM image of partially grown InP by TLP. (c) TEM image at three phase boundary as indicated by the xi white square in (b). STEM image of InP after TLP growth (d) without doping source, (e) with Sn doping layer evaporated after In, (f) with Sn doping layer evaporated before In. Scale is 1𝜇𝑚. . 42 Figure 3. 7 STEM and TKD of InP on epitaxy InP on Si. (a-i) STEM image of InP without Sn doping. (a-ii) to (a-iv) TKD of InP without Sn along Z (perpendicular to paper), Y(upward), and X(right) direction. (b-i) STEM image of InP with Sn evaporated after In. (c-i) STEM image of InP with Sn evaporated before In. (b,c-ii) to (b,c-iv) corresponding TKD along Z, Y, and X. .......... 43 Figure 3. 8 TKD of InP on epitaxy InP on Si (a) with (b) without Sn doping at the interface. (c) and (d) Point-to-point disorientation verse the distance from the beginning of analyzing line corresponding to the white line in (a) and (b). .............................................................................. 43 Figure 3. 9 (a) SEM image of 5 pieces 90×2 𝜇𝑚 2 InP channel on epitaxy p-type InP on Si. (b) EDS map of In. (c) EDS map of P. (d-f) Overlapped band contrast, grain boundary, and EBSD map along Z (perpendicular to paper), Y(upwards), and X(right) direction. The scale is 25 𝜇𝑚. 44 Figure 3. 10 (a) Overlapped band contrast, grain boundary, and EBSD map along Z (perpendicular to paper). (b) Point-to-point disorientation from the dash line in (a). ........................................... 45 Figure 3. 11 (a) PL spectrum of TLP InP on epitaxy InP layer on Si, and epitaxy InP by MOCVD on Si. Insert is the SEM of InP mesa measured for the PL map in (b). (b) Peak intensity map of InP mesa. (c) Normalized PL spectrum for InP grown by TLP on epitaxy InP layer and the epitaxy InP by MOCVD. (d) Time-resolved PL spectrum of specimens with or without TLP InP on epitaxy InP. ................................................................................................................................................ 46 Figure 3. 12 TLP growth mechanism on epitaxial substrate. (a) TLP growth with subcritical dewetting region. (b) TLP growth without subcritical dewetting region. (c) TEM image of interface between In and MOCVD InP. (d-e) TEM images of interface between TLP InP and MOCVD InP (d) with (e) without subcritical dewetting region. ........................................................................ 48 xii Figure 3. 13 (a) SEM image of 20×20 𝜇𝑚 2 InAs mesa on epitaxy InP on Si. (b-d) EDS maps of P, As, In. (e) Phase map. (d-f) Overlapped band contrast, grain boundary, and EBSD map along Z (perpendicular to paper), Y(upwards), X(right) direction. Scale is 5 𝜇𝑚. .................................... 49 Figure 4. 1 (a) Schematic of a biological synapse showing communication of signal between neurons by release of neurotransmitters from the presynaptic neuron causing diffusion of Na ions into the postsynaptic neuron. (b) Schematic of the InP channel FET on silicon as the synaptic device. ........................................................................................................................................... 51 Figure 4. 2 (a) Transient PSC before and after application of presynaptic pulse. (b) Short-term and long-term synaptic weight change for different values of presynaptic voltage pulse. .................. 52 Figure 4. 3 (a) Increased potentiation of synapse succeeding a depressing priming comparing to potentiating priming. (b) Increased depression of synapse succeeding a potentiating priming compared to depressing priming. (c) STP weight change for different values of presynaptic voltage pulse. ............................................................................................................................................. 54 Figure 4. 4 (a) PSC before and after application of varying pulse number (b) Variation of STP relaxation time constant with different number of action potentials (c, d) long-term and short-term weight change for different number of action potentials. ............................................................. 55 Figure 4. 5 (a) Waveforms representing back-reflected postsynaptic action potential and presynaptic action potential for STDP measurement. (b) LTP weight change for different values of time offset between pre and post synaptic action potentials. ................................................... 56 Figure 4. 6 Schematic of InP synaptic transistor with heterostructured gate dielectrics .............. 58 Figure 4. 7 (a) Ids-Vgs of InP synaptic transistor with Vds at 0.1 to 2.1V. (b) Ids-Vds of InP synaptic transistor with Vgs increased from 0.1 to 3.1V. (c) Dual-sweep of Ids-Vgs at Vds=1V. (d) Dual- sweep of Ids-Vgs at Vds =0.1 and 2V. ............................................................................................. 59 xiii Figure 4. 8 (a) The milestone psychological model of human memory. (b, c) Band diagram of InP synaptic transistor when applied (b) singe and (c) multiple negative voltage pulses showing STP and LTP behaviors. ....................................................................................................................... 60 Figure 4. 9 (a) Measured and fitted pre-and post-synaptic current after N pieces of gate voltage pulses with -5V amplitude, 100 µs period and 50% duty cycle. (b) Stacked bar chart of sensor register-related (aREG), STP-related(aSTP), and LTP-related (aLTP) weight factor. ........................ 61 Figure 4. 10 Normalized PSC of the InP synaptic transistor when applied with (a) 5 identical gate pulses with -5V peak, 2µs pulse width and 10 s pulse interval; (b) 5 identical gate pulses with -5V peak, 50µs pulse width and 10 s pulse interval; (c) 10 identical pulses with -6V peak, 10µs width and 10s interval; (d) 10 identical pulses with -6V peak, 10µs width and 2s interval. .................. 64 Figure 4. 11 (a) PSC when applied with a series of 200 identical negative and 200 identical positive pulses, 100µs width, 1s period. (b) PSC of 4000 cycles of switching between high conductance state and low conductance status. (c) Measured and fitted PSC after 100 pieces of potentiation pulse (-5V, 100µs width, 500ms period ) and 100 pieces of depression pulse (5V, 100µs width, 1s period). (d) 10 cycles of PSC current, where same condition as (a) was applied for each cycle. 65 Figure 5. 1 Schematic and post-synaptic current of FG-PFETs. (a) Schematic of FG-PFETs and the cross-section film stack. (b) PSCs with one -5V Vprog pulse in dark, and illumination of three wavelengths (𝜆 =655,532,𝑎𝑛𝑑 445 𝑛𝑚 ). (c) PSCs with one +4V Vprog pulse in dark, illumination of three wavelengths (𝜆 =655,532,𝑎𝑛𝑑 445 𝑛𝑚). ............................................... 69 Figure 5. 2 Programmable responsivities of FG-PFETs. (a) PSCs with 20 pieces of -5V Vprog pulse and ~10s light pulse (𝜆 =655 𝑛𝑚) 20s after the Vprog. (b)-(e) The relationship of responsivities of FG-PFETs extracted from (b) increased number of potentiation Vprog pulses, (c) increased xiv number of depression Vprog pulses, (d) decreased amplitude of Vprog in the negative region, and (e) increased amplitude of Vprog in the positive region. ..................................................................... 71 Figure 5. 3 The mechanisms behind the FG-PFETs. (a) Ids-Vgs sweep before and after applying 20 +7V and -7V Vprog pulses. (b) Dependency of Iph to Vgs with 655 nm irradiation and transconductance swept at the same range. (c) Band diagram corresponding to the three working regions in (b). ................................................................................................................................ 72 Figure 5. 4 Variation and duration of programmed responsivity. (a) Responsivities of FG-PFETs when circulating +6V Vprog pulse train and -6V Vprog pulse train. (b) Responsivities of FG- PFETs extracted from 2, 5, and 8s after illuminating the light pulse, and their dependencies to interval time between Vprog and irradiation. (c) and (d) Histogram of HRS and LRS, and their Gaussian distribution fitting curve. ............................................................................................... 74 Figure 5. 5ONN built with FG-PFETs. (a) Examples of stacked MNIST digits, working as the color-mixed input images to the ONN. (b) Schematic of the ONN built with FG-PFETs. (c) Schematic of pixel array, and pixel with color filters. (d) Circuit diagram of first 3 pixels, each pixel contain 6 FG-PFETs and three color filters. ........................................................................ 77 Figure 5. 6 (a) Accuracy and (b) loss of the simulated ONN over 40 epochs of training and testing. ....................................................................................................................................................... 79 xv Abstract The exponential increase of connected devices by the internet is requiring more powerful computing units to process and store the unexpected volume of data. Difficulties from device scaling, large power consumption, heating issue, and von Neumann bottleneck motivated researchers to study and mimic our brain to explore more efficient computing structures. Neuromorphic computing, pioneered by Carver Mead provided a vast avenue for emerging electronic devices to contribute to the next generations of computation processors. Competitive candidates such as metal-oxide random access memory (RRAM), ferroelectric field effective transistor (FeFET), phase change memory (PCM), spin transfer torque magnetic random access memory (STT-MRAM), and devices built on 2D materials have been demonstrated from different research groups. The III-V semiconductor based neuromorphic devices also demonstrated ultrafast resistance switching speed and outstanding light response, however, their developments are limited due to the concern in the high-cost epitaxial integration process and challenges in CMOS backend compatibility. In this dissertation, we successfully remove the constraints from back-end-of-line compatibility by a low temperature – templated liquid phase (LT-TLP) approach and demonstrate single crystalline III-V semiconductors like InP and InAs can be directly integrated on the amorphous substrate. With this technique, the highest room-temperature electron mobilities among materials from the non-epitaxially growth approach were demonstrated from LT-TLP grown InAs, which can increase further with a smoother surface. xvi The templated liquid phase (TLP) approach can enable heterogeneous integration of III-Vs on Si substrate as well, with a III-V layer epitaxially grown on Si substrate. By this approach, the III-Vs mesas from TLP growth not only demonstrated unified crystal orientations but showed an extensive decrease in defect density. Importantly, the approach allows a variety of compound semiconductors (III-Vs and II-VIs) monolithically integrated on Si substrates without complex defect filtering techniques. Integrated by the BEOL compatible approach, InP-based FETs were designed and engineered to mimic a variety of synaptic behaviors, including elasticity, potentiation, depression, metaplasticity, spiking-number dependent plasticity, and spiking-timing dependent plasticity. This allowed the InP FETs to work as a computing element for spiking neural networks. To handle the sequential information better, heterogenous gate dielectric layers were utilized to construct InP floating-gate FETs. This structure significantly increased the dynamic weight tuning range, improved device endurance, and prolonged retention time. Even more complicated behavior like memory consolidation can be emulated as well. The capability of in-sensor computing was shown in the floating-gate phototransistor (FG-PFETs) built with TLP grown InP. Programmable responsivity and high responsivity to the visible wavelengths allowed the InP FG-PFETs to sense and process the light signal simultaneously. The simulated optical neural network constructed from the performance of these devices achieved ~94% accuracy for mixed-color image recognition. 1 Chapter 1 Introduction 1.1 Motivation of hardware-based neuromorphic computing The exponentially increased number of connected and controlled devices by the internet is demonstrating the unleashed momentum of the Internet of Things (IoT), which is dramatically influencing our daily life. The global IoT market is expected to reach a value of USD 1,386.06 billion by 2026 from USD 761.4 billion in 2020. This technology diminishes the barrier of communication between different smart devices and increases the efficiency of data sharing. The application of IoT across end-user industries, such as smart homes, autonomous vehicles, healthcare, manufacturing, traffic management, etc. This results in the generation of enormous amounts of data that need to be stored, processed, and presented in a seamless, efficient, and easily interpretable form. As reported in IDC white paper, the global datasphere is expected to grow from 23 Zettabytes (ZB) in 2017 to 175 ZB by 2025. One zettabyte is equivalent to a trillion gigabytes (GB). And importantly, nearly 30% of the global datasphere will be real-time information. Figure 1. 1 Annual size of global datasphere source: IDC. To address the exponential surge of the data volume, more advances in computing capability are demanded. Historically, device scaling following Moore’s law can match the requirement. 2 However, with the increased fabrication cost and anticipated fundamental physical limits, desired performance won’t be achievable. In addition, the conventional computing architectures face challenges including the heat wall, the memory wall, and the von-Neumann bottleneck. 1 2 The heat wall includes the self-heating from excessive heat confinement due to their small size and three- dimensional geometries of FinFETs and gate-all-around FETs (GAAFETs), and the data transport heat generated in interconnection metal wires. The heating issue can reduce speed, increase leakage and accelerate aging. 3 The memory wall describes the performance gap between the processor and memory that has grown steadily over the last several decades. To be specific, when the memory latency and bandwidth cannot provide processors with sufficient instructions or data to continue the computation, processors will be stalled waiting on memory. 4 5 As for the von Neumann bottleneck, it’s the high energy and speed costs associated with constant data movements between the memory and processor. Due to this, caching, multi-threading, and memory access optimizations have been proposed and implemented to optimize the system towards less von Neumann architecture. But the more revolutionary approach is desired to change the game. 6 Neuroscience offers a munificent source of inspiration for novel hardware architecture algorithms. Although our brain hasn’t been completely understood, we know that it works in a very different protocol compared to the conventional central processing unit (CPU), as shown in Fig 1.2. First, it’s composed of neurons and synapses instead of transistors and metal wires. Second, the information is stored in an analog way rather than in bits. Third, the components of the brain are noisy and not of high precision. Forth, the brain can process multiple jobs dynamically instead of following a single clock. Last but not least, the neural connections evolve with time instead of 3 having limited reconfigurability. These fundamental differences drive scientists and engineers to explore the benefits of emulating these physical principles. 7-9 Neuromorphic computing is the concept coined by Carver Mead from Caltech in the late 1980s, describing analog, digital, mixed-mode very-large-scale integration (VLSI), and software systems that implement models of neural systems. 10, 11 It takes the inspiration of the brain for designing computer chips and merge memory with processing. The most critical advantage of neuromorphic computing is the energy efficiency, especially in the cognitive functions like image recognition and unsupervised classification built on artificial neural network (ANN) or spiking neural network (SNN). The reasons behind this will be introduced in the following paragraphs. Although neuromorphic computing might not entirely replace digital computing, it can imitate the architecture of the brain and provides a path to build smart chips that consume less energy and accelerate the computation. Figure 1. 2 A schematic of the organizational principles of the brain. From ref 9 . 4 The prevailing thrive of ANN benefits the data-driven industry and academic fields more than any time in the past several decades. Its application includes autonomous vehicle control, game playing, image recognition, medical diagnosis, e-mail spam filtering, data mining, and signal classification. All the thrilling progress was starting from the neural network composed of a computational neuron model. The inspiration taken from biology is that roughly 10 11 neurons are connected with each other via 10 14-15 synapses. Each neuron receives input signals 𝑥 ! from its dendrites and produces output signals along its axon. These signals travel along the axons and interact with the dendrites 𝑤 !" of the other neuron, and the dendrites carry the signal to the cell body soma where they get summed 𝒘 # 𝒙 𝒏 . If the final sum is above a certain threshold (membrane potential threshold), the neuron can fire. And the firing rate of the neurons is modeled by an activation function. This first computational model of neuron was proposed by Warren MuCulloch and Walter Pitts in 1943. 12 The beauty of the algorithm lies in the learning process by adjusting weights on each iteration. It is guaranteed to converge to a consistent function if the data is linearly separable with the gradient descent on the squared error (𝑦 ! −𝑦 %&' ) ( and updating rule for weights with 𝑤 ! ) =𝑤 ! +𝛼(𝑦 ! −𝑦 %&' )𝑥 ! . However, the difficulty in computing XOR by single-layer network, proposed by Minsky and Papert, 13 almost killed the community. Fortunately, it also drove the invention of a multi-layer neural network for non-linear decision surfaces. Based on the multi-layer neural network, a varity of robust network frameworks including convolutional neural network (CNN), recurrent neural network (RNN), and Hopfield neural network (HNN) bloomed in all the application fields. 2, 14, 15 5 Figure 1. 3 Architecture of LeNet-5 from ref 15 . As another candidate for more efficient computing technology, SNNs are more close to the actual emulation of the brain and behaviors of neurons. 16 The reason behind this is that the biological neurons compute with asynchronous spikes that signal the occurrence of some event by temporally precise action potentials. However, ANNs are mostly non-linear but built with continuous functions that work on a common clock cycle. SNNs were originally studied as models of biological information processing, in which neurons exchange information via spikes. Based on this, input signals can be encoded by different protocols such as spike firing frequencies, the relative timing of pre-and postsynaptic spikes, and particular firing patterns. And the identity of the synapse, indicating whether the synapse is excitatory or inhibitory, plays an important role. That is because the synaptic behavior as short-term plasticity or long-term plasticity is directly related to the synaptic strength. Different from the continuous activation function in ANNs, the membrane potential and its firing events are more vividly modeled in SNNs with a varity of neuron models such as the leaky integrate-and-fire model 17, 18 and Hodgkin-Huxley model. 19 When the membrane potential integrated from currents from arriving spikes reach the threshold, a new spike will be generated and the membrane potential will be reset. SNNs have the cutting-edge advantage in power efficiency because of the spatio-temporal event-based information from neuromorphic sensors. In another word, whenever there is little information recorded, the SNN doesn’t compute, only when bursts of activity are recorded, the SNN then generate more spikes. In short, SNNs 6 enabled the sparse and asynchronous binary signals to be communicated and processed in a massively parallel fashion and exhibited favorable properties as low power consumption, fast inference, and event-driven information processing. The superior properties of SNNs lead to novel hardware designs such as Neurogrid from Stanford University 20 , SpikNNaker from the University of Manchester 21 , TrueNorth from IBM 22 , and Loihi from Intel 7 . Figure 1. 4 Real-time multi-object recognition on TrueNorth. Modified from ref 22 . At the algorithm level, ANNs and SNNs have already demonstrated their profound impact on complex jobs such as computer vision, natural language processing (NLP), voice recognition, and autonomous vehicle. However, most of the algorithms are still running on the conventional chips which are not optimized to handle large matrix multiplication or store large size data. Consequently, many researchers and developers utilize graphic processing units (GPU), and tensor processing 7 units (TPU) to accelerate the computation by processing multiple computations parallelly and taking advantage of the memory bandwidth of GPU and TPU. However, to fully unleash the power of neural networks, there is no better solution than directly building the structure with devices that can emulate biological neurons and synapses. 1.2 State of the art emerging devices Some prototypes of hardware neuromorphic systems have already been built using existing CMOS technology. 10, 11, 20, 23 Neuronal spiking and synaptic behavior have been emulated using CMOS- based circuits containing at least six transistors depending on the specific functionality and robustness of the design. The expensive footage cost and relatively large energy consumption restricted the ubiquitous application of the hardware-based neuromorphic system. With this motivation, novel materials and emerging device structures are proposed and investigated to emulate the neuronal spiking and synaptic behavior with a single device. 1.2.1 Synaptic behavior emulation Synaptic behavior emulation has been pioneered by Diorio et al in 1996 based on hot-electron injection and electron tunneling in a floating-gate silicon metal-oxide-semiconductor (MOS) transistor, 11 and followed by other emerging non-volatile memory (eNVM) synaptic devices such as phase change memory (PCM), 24 resistive random access memory (RRAM), 25 Conductive- bridge random access memory (CBRAM), 26 ferroelectric transistor (FeFET), 27 spin-transfer torque magnetic random access memory (STT-MRAM) 28 , and 2D material-based devices. 29 8 1.2.1.1 Phase change memory In PCM, large resistivity contrast between crystalline (set state) and amorphous (reset state) phases are utilized. Typically, as fabricated PCM is in the crystalline and low-resistance state, and a large electrical current pulse is applied to reset the PCM cell into an amorphous state since the short current will melt and quench the material. The resulted amorphous region in series with other crystalline regions enabled the control of effective resistance. To set the PCM into the crystalline phase, a medium electrical current pulse is applied to anneal the material at a temperature between crystallization and melting for a relatively long time to crystallize the programming region. To avoid the state disturbance, small reading current need to be applied. Although for some materials the difference between the resistance in the set and reset can reach five orders of magnitude, several key issues like large programming current and heat disturbance require advanced device structure design and thermal design. Memory cell selection devices are also needed to minimize static power dissipation. 24, 30 1.2.1.2 Resistive random access memory RRAM, also referred to ReRAM or OxRAM, describes the devices that exhibit resistive switching between a high-resistance state (HRS) and a low-resistance state (LRS). The device structure is simply an oxide material sandwiched between two metal electrodes. The heavily studied and promising metal oxide materials include HfOx, AlOx, NiOx, TiOx, and TaOx. The subscript “x” is used because the oxides here are often nonstoichiometric. When these oxide materials are combined with different material-based top and bottom electrodes, the devices can show either unipolar or bipolar switching characteristics. No matter whether the switching mechanism is built on the thermal dissolution model or ionic migration model, oxygen migration presents in the 9 switching process and plays an important role. Typically, an electrical forming/set process for as- fabricated samples is required and seen as the dielectric soft breakdown, to initiate the switching behavior. The reason behind this is that oxygen ions drift to the anode interface under a high electric field, and they are discharged as neutral non-lattice oxygen if the anode materials are noble metals or react with oxidizable anode material to form an interfacial oxide layer. During the reset process (LRS to HRS), oxygen ions migrate back to the bulk either to recombine with oxygen vacancies or to oxidize the metal precipitates and return to the HRS. For the unipolar switching devices, Joule heating from the current thermally activates the diffusion of oxygen ions. As for bipolar switching devices, the interfacial oxide layer presents a significant diffusion barrier and requires a reverse electric field. RRAM-enabled crossbar structure can facilitate the matrix multiplication operation which is quite expensive in conventional digital logic units and is seen as the most promising next generation of memory technology. However, a large-scale memory array with RRAM needs to integrate a memory cell selection device to avoid the sneak leakage current. Non-linear elements such as diodes, Schottky diode, bidirectional diode, and the transistor can work as the selection device, but its conductivity needs to be carefully engineered to balance with RRAM itself. 25, 31, 32 1.2.1.3 Conductive-bridge random access memory Although CBRAM belongs to RRAM, switching between LRS and HRS, the mechanism is quite different. CBRAM is also a two-terminal device with the top and bottom electrodes, but the switching materials in between can be chalcogenides, oxides, and bilayers. In addition, one metal electrode needs to be chemically active or can be oxidized under external positive bias, thus Ag or Cu are typically utilized. Another electrochemically inert electrode can be fabricated with Pt, Au, 10 W, or TiN. When switching the CBRAM from HRS to LRS, a positive voltage is applied to the anode, and metal is oxidized to form Cu + ions or Ag + ions, which drift through the solid switching layer under electric field, discharge at cathode, and build metallic filament or “conductive bridge”. Polarity-reversed voltage results in the chemical dissolution of the conductive bridge, resetting the device from LRS to HRS. Similar to RRAM introduced previously, CBRAM face the challenge in uniformity, endurance, retention, multi-bit operation, scaling trend, and current compliance- dependent reliability issue. 26, 33 1.2.1.4 Ferroelectric transistor FeFET is built as a logic transistor but uses the ferroelectric material as the gate dielectric. Doped hafnium oxide (HfO2) and (Hf, Zr)O2 (HZO) thin films with a typical thickness of ~10nm can work as dielectrics. Different from charge trap flash (CTF) devices, where threshold voltage shift Vth is governed by the amount of charge trapped in the trapping layer, in the FeFET, the uncompensated ferroelectric polarization charge is the source of Vth shift. To be specific, in FeFET, one of the electrodes is the semiconductor channel, in which the carrier concentration is lower than that of metal. At the interface of metal and ferroelectric layer, metal layer provides sufficient screening charge, but the thickness of accumulation and inversion layer in semiconductor is finite. Such incomplete charge compensation at the interface fundamentally caused the emergence of the depolarization effect and induced the Vth shift. Sourav Dutta et al reported the FeFET-based analog synapse is realized using voltage-dependent partial polarization switching in multi-domain ferroelectric thin film. 27 But to represent of 3-bit equivalent analog weight cell, eight non- overlapping conductance states need to be selected, indicating multi-bit operation, as well as other 11 issues (limited endurance, low memory window, and charge trapping), are limiting the wider application of FeFET. 34 1.2.1.5 Spin-transfer torque magnetic random access memory STT-MRAM is an advanced type of MRAM device. MRAM uses magnetic tunnel junction (MTJ) which is composed of two ferromagnetic material layers (a free layer and a pinned layer) to store data. The spin of a free layer can be switched from one direction to another which tunning the resistance state of the device. STT-MRAM replaced the magnetic field required for writing by applying current. The principle behind this is that, if the magnetization direction needs to be changed from antiparallel to parallel, electrons are sent from pinned layer to free layer, among which, the minority of electrons get scattered and majority pass through to the free layer. When polarized electrons reach free layer, spin angular momentum exerts a torque on the magnetization of layer that is oriented antiparallel to the pinned layer and results in the change of direction from antiparallel to parallel. When the direction of the current is reversed, the transfer of spin angular momentum between the reflected electrons and the magnetization results in an antiparallel magnetization configuration. Relatively, STT-RAM has higher endurance compared to RRAM because the spintronic device does not use milting or filament which impacts material stability. But it also has its disadvantage, especially in thermal stability. 28, 35 1.2.2 Neural behavior emulation Several neural models have been proposed by drawing inspiration from neuroscience. For example, Hodgkin-Huxley model (H&H model), 19 Izhikevich model, 36 and the leaky-integrate-and-fire (LIF) neuron model. 17 The H&H model describes the relationship between the flow of ionic current across the neuronal cell membrane and the membrane potential of the cell, using a set of nonlinear 12 differential equations to approximate the electrical characteristics of neurons. But H&H model typically leads to high simulation costs which impose limits on the scale of network models. Izhikevich spiking neuron model combines the biological plausibility of H&H model dynamics and the computational efficiency of LIF neurons. It can reproduce a wide range of neural behaviors qualitatively, and firing pattern classes while still being computationally efficient. Although LIF model may be seen as oversimplified for neuroscientists because it cannot capture the wide range of dynamics observed in the hippocampus, it still reflects the diffusion of ions through the membrane and allows electrical engineers to use the minimum number of circuits element to mimic the behavior of the biological neuron. The neural spiking emulation is implemented digitally by IBM TrueNorth 22 and Intel Loihi, 7 or in analog with complicated circuit design based on a conventional CMOS process, such as reconfigurable SNN processor reported by Ning Qiao et al, 37 LIF neuron circuit by Giacomo Indiveri, 38 and asynchronous micro-pipelined LIF array transceiver by Jongkil Park. 39 As for the neural spiking emulation by a single emerging device combined with a few circuit elements like a capacitor integrating pre-synaptic signals, some novel structures were reported by Sourav Dutta et al, using FeFETs based circuits, 27 Matthew D. Pickett et al, and Xumeng Zhang et al, based on NbO2 Mott memristors, 40 41 Wei Yi et al, applying VO2 memristors, 42 and Sangya Dutta et al, utilizing Si-based floating-body MOSFET. 43 1.3 Opportunities of III-V based devices Currently, not many reports of neural spiking and synaptic behaviors are built on devices with non- oxide switching materials like III-V semiconductors. There are several possible reasons behind: 13 a. Material synthesis of III-V semiconductors typically requires a high growth temperature (typically above 600 ℃), which is not compatible with back-end-of-line CMOS process. It potentially limited the large-scale integration with conventional digital logic units. b. Epitaxial growth mechanism needs single crystalline substrates to eliminate the crystal parameter mismatch issue, which may cause high defect density. c. High cost for equipment like MOCVD or MBE. If these above constraints can be eliminated with an advanced material integration approach, III- V materials may potentially become competitive candidates. Three main reasons are explained in the following. 1.3.1 Fast switching Although III-V semiconductor-based devices are seldomly reported to work as synapses or neurons in the artificial neural network, among the published ones, they are demonstrating superior properties and potential. Steven Lin et al, 44 in 1993, pioneered a simple optoelectronic circuit integrated monolithically in GaAs to implement sigmoidal neuron responses, in which light- emitting diode, transistor, and photodetectors are integrated. Byung Joon Choi, et al, 45 reported AlN-based memristors exhibited reversible and reproducible memristive switching characteristics, demonstrating ultra-high switching speed (85 ps), low switching current (sub 15 𝜇𝐴 ) and scalability to the nanoscale for nitride memristors. Yuanyang Guo, et al, 46 reported a synaptic device based on a TiN/AlN/Pt memristor, showing long retention (> 10 4 s) and relatively linear weight update. Fran Kurina et al, 47 reported photonic resistance switching behavior from polycrystalline GaP directly grown on Si substrate. The On/Off ratio reach ~10 4 and is attributed 14 to the formation of filaments along the grain boundaries. Bang Li et al, 48 and Yiming Yang et al, 49 reported an InAs nanowire(NW) based phototransistor, showing novel negative photoconductivity and exhibiting synaptic behavior under photonic stimuli. Light-assisted hot electron trapping was accused as the origin of the negative photoconductivity. It needs to be noted that, III-V semiconductors not only can be utilized as the resistance switching materials, but their optoelectronic, photonic properties may also enable them as the key elements in the photonic neuromorphic computing system. 1.3.2 Optical properties for neuromorphic photonics Photonic circuits/processors are well suited to high performance implementations of the neural network, which require low latency, high bandwidth and low energies. To emulate the layout of connections between pairs of artificial neurons, optical signals can be multiplied by transmission through tunable waveguide elements, then can be added through wavelength-division multiplexing (WDM) by accumulation of carriers in semiconductors, electronic currents, or change in the crystal structure of a material induced by photons. On the other side, III-V semiconductors based photonic elements can be implemented in a variety of applications, such as nanolaser diodes, ring resonators, Mach-Zehnder modulators, memories for flip-flow operations, or all-optical switches. 50, 51 Among the reported neuromorphic photonic integrated circuits work, III-V material based devices already work as key elements. Bin Shi et al, 52 reported that InP photonic neural network has been realized and demonstrated based on semiconductor optical amplifier (SOA) technology. In which SOAs are operated in a linear regime, working as weighted attenuators. In addition, to implement a nonlinear photonic neuron, an optical/electrical/optical (O/E/O) neuron is one of the options. In 15 this structure, E/O nonlinearities for photonic neuron is demonstrated using modulators or lasers. As for the input light-matter interaction (O/E), various photodetectors in different wavelength is required. No matter for laser diodes, photodetectors, or electroabsorption modulators, III-V based photonic devices are outstanding candidates. 51, 53 1.3.3 Elimination of sneak current The third reason why III-V semiconductor based devices are crucial for hardware neuromorphic computing is that it can work as the perfect memory cell selector for memory cell crossbar array. Although crossbar array provides a cost-effective approach for achieving high-density integration of two-terminal functional devices, the sneaking current issue resulted by leakage current from unselected cell can lead to read/write disturbance, increase of statistic energy dissipation, and the drop of accuracy of computation. To solve this issue, multiple structures are proposed. Two- terminal nonlinear selection devices at each cross point node (1S1R), and three-terminal transistor at each memory cell position (1T1R) are the two dominant solutions. As for the two-terminal selection device, asymmetry and nonlinearity are the two requirements for suppressing the leakage current. Consequently, diodes and Schottky junctions such as such as NiOx/TiOx, CuOx/InZnOx, Ag/ZnO/TiAu, Ni/TiOx/Ni/HfOx/Pt are the structures utilized for solving the issue. 31 54 The side effect of utilizing the two-terminal selector is that the maximum current density might be limited, and lower than the programming requirement for the RRAM. And the thermal stability of the selector may also impact the practical performance of the crossbar array. More than that, the conductivity of the selector needs to be balanced with the conductivity of the memory cell, which requires lots of detailed material engineering to achieve good performance. 16 On the other side, the most effective way is still using a transistor to clamp the current, and it’s used in plenty of reported works. Because of its mature technology, high on/off ratio, and gate modulation capabilities, 1T1R structure can minimize the statistical energy consumption. III-V semiconductor based high electron mobility transistors (HEMT) built on GaN, InxGa1-xN can potentially provide high switching speed and drive high voltage or current needed for memory cell programming. 45 One of the typical concern is the high process temperature for material synthesis. However, low-temperature TLP approach enabled monolithic III-V semiconductor integration discussed in the later chapter can remove the constrain. 1.4 Overview of the thesis proposal This thesis consists of six chapters. Chapter 1(this chapter) begins with the motivation of hardware- based neuromorphic computing and the state-of-the-art emerging devices, from which the opportunities and strength of III-V semiconductor-based devices are illustrated. Chapter 2 presents the back end of the line (BEOL) compatible monolithic III-V material integration approach enabled by the low-temperature templated liquid phase (TLP) method. Chapter 3 proposed a new heterogenous III-Vs integration method that allow the unified crystalline orientation and decreased defect density by the TLP approach on MOCVD epitaxial III-Vs layer on Si substrates. Chapter 4 presents the complex synaptic behavior emulation by InP-based field effective transistors (FETs). Chapter 5 shows InP floating-gate phototransistor can enable the in-sensor computation and work for optical neural network to do mixed-color image recognition. Chapter 6 will conclude this dissertation by providing an overview of the main findings in this work and a brief discussion of several interesting further research directions. 17 Chapter 2. BEOL compatible monolithic III-V integration on amorphous substrates 2.1 Introduction Heterogeneous integration of high-quality III-V crystalline semiconductor materials on Si and merging their domain in photonics and electronics has been an ultimate goal of device scientists for a very long time. State-of-the-art techniques are centered on chip-based integration, where multiple chips are bonded and connected via through-silicon vias (TSV), or epitaxially transfer, where the desired material is grown on a monocrystalline wafer and then transferred by release or lift-off and wafer-bonding. Directly growth was also actively investigated, including the growth of buffer layers to accommodate the lattice mismatch, epitaxial lateral overgrowth, aspect-ratio- trapping techniques, and interfacial misfit array formation. All the techniques produce excellent quality heterogeneously integrated devices, but usually come at the price of dramatically increased integration complexity and high cost. 55, 56 18 Figure 2. 1 State-of-the-art technologies to integrate III-V semiconductors on Si wafer. Modified from ref 55 . A new approach recently being introduced as a potential candidate for heterogeneous material integration on Si back-end dielectrics and metals and simultaneously addressing the cost, scalability, and material quality issue, is the templated liquid phase (TLP) growth. It has been demonstrated that single crystals of compound semiconductors can be non-epitaxially directly grown on multiple metallic and amorphous substrates in deterministic geometries and locations by the TLP approach. 56 Figure 2. 2 TLP approach directly integrate InP on Mo foil 19 Although the TLP approach has been demonstrated as an outstanding option for heterogeneous III-V semiconductors integration, there are several challenges or constraints that need to be solved to pave the way toward the Si back-end of the line (BEOL) commercial implementation. Those challenges include: a. Previously reported dimensions of single-crystalline mesa grown by the TLP method were generally smaller than 10 µm. But being a robust material integration approach, it’s typically required to synthesize a high uniform template with dimensions larger than 100 um for different kinds of applications. b. Currently, the growth by TLP approach uses a high growth temperature( ~550 to 650 ℃ ) for InP and InAs. However, to prevent damage to the bottom active layer, BEOL thermal budget is commonly set at 400℃. Consequently, low-temperature process needs to be developed. In the following sections, the results for solving the issues above are demonstrated, which are largely based on the peer-reviewed papers. 57 2.2 Large area single crystalline III-V integration To demonstrate the large area single crystalline III-V semiconductor growth by TLP approach, double crosses geometry Hall-bar templated area with 100 µm length 5 µm channel width was patterned on Si/SiO2 substrates by photolithography. 20 Figure 2. 3 Overview of the large area TLP growth of crystalline compound semiconductors. (a) Schematic of TLP growth process. (b) Representative optical microscope. Indium layer with 225 nm thickness is sandwiched by thermal evaporated 5nm molybdenum oxide (MoOx) and E-beam evaporated SiO2 capping layer, as shown in Fig 2.3 (a)-(i). Here MoOx works as a buffer layer to facilitate In wet the substrate during growth. Then the specimen was loaded into a single-zone tube furnace, and heated to the growth temperature around 550 ℃, when group V hydride gas (phosphine or arsine) flows in. At the growth temperature, In layer melt but maintained the geometry as-deposited, and hydride gas decomposed to corresponding group V gas phase (phosphorus and arsenic) diluted with a carrier gas (H2) as indicated in Fig 2.3 (a)-(ii). With optimal control of hydride gas flow rate by mass flow controller (MFC), just enough positive supersaturation for III-V material to precipitate as a single nucleus in each mesa is achieved. Once the first nucleation event happens in a single pool of indium, the balance between the rate of growth and the rate of nucleation determined by group V flux and diffusion of the group V species in 21 liquid group III metal leads the to the growth of the first nucleation and prevents other nucleation in the same template. Consequently, with time, the entire group III-mesa is transformed into a III- V semiconductor area. This process is verified by stopping the growth at different timing as indicated in Fig 2.3 (b)-(i) to (b)-(v). The crystallinity of the grown materials is characterized utilizing the electron backscattering diffraction (EBSD) map. EBSD enables us to create an image map of the out-of-plane crystallographic orientation of grown materials, with the resolution limited by the electron beam spot size. As shown in Fig 2.4, the six representative hall elements all demonstrate uniform single color geometry matching their own dimension, indicating their single out-of-plane crystallographic orientation, and single crystallinity. Figure 2. 4 Electron backscatter diffraction (EBSD) map of Hall elements To be noted, this single out-of-plane orientation of nuclei is distributed across mesas on the same chip, and there is a natural distribution of (111), (101), and (100) on each sample. To align these crystal orientations, a different process flow will be discussed in chapter 3. 22 Optoelectronic characterization of TLP-grown materials is carried out by performing steady-state photoluminescence (PL) measurements and Raman spectrum analysis. The PL curves of the TLP InP on SiO2/Si and a commercially purchased single-crystal n-type (5-6×10 16 cm -3 ) InP wafer are shown in Figure 2.5 (a). Identical peak position (1.34 eV) and negligible full width at half-maxima (FWHM) indicate excellent quality of the grown material. As shown in the Raman spectrum of TLP grown InAs in Figure 2.5 (b), transverse (TO) mode and longitudinal (LO) mode peaks are observed at 218.4 cm -1 and 239.5 cm -1 respectively, which are consistent with the TO and LO modes of bulk InAs surface at ~218 cm -1 and 239 cm -1 . 58 The excellent match of the optoelectronic properties of the grown materials with that of the reference values points to the high crystalline quality which can be achieved despite these materials being grown on non-epitaxial substrates. Figure 2. 5 Optoelectronic Characterization (a) Photoluminescence of InP and (b) Raman spectrum of InAs. Different steps in the fabrication of the Hall elements are shown by representative scanning electron microscope (SEM) images in Figures 2.6 (a) through (g). The “side-growths” may be considered as growth artifacts, and would adversely affect charge transport by surface roughness 23 scattering. Using a self-aligned etch process where the SiO2 cap acts as an etch mask, the vapor- phase InP is selectively etched using BCl3-Cl2 plasma etching. The top oxide cap is then etched away using either dilute hydrofluoric acid (50% HF: H2O=1:10) or CHF3-Ar plasma to yield the III-V Hall element on the SiO2 substrate, as represented in Figures 2.6 (e) and (f). Electrodes are then defined on the Hall bridge arms, using photolithography, metal evaporation (Ni/Au) and liftoff, and annealed at 300 ℃ to improve contact resistance. Figure 2.6 (g) is a representative SEM image of a fully fabricated Hall element, while Figure 2.6 (h) is a schematic representation of the device indicating the current injection and voltage measuring paths. Figure 2. 6 Scanning electron microscope (SEM) image of (a, b) as grown pattern, (c, d) after selective side-growth etch pattern, (e, f) after top capping layer etch pattern, (g) after electrodes deposition pattern. (h) Schematic of complete device for Hall measurement. The electron mobility of the III-V templated films was extracted from Hall effect measurements over a temperature range of 2 to 300 K, using Physical Property Measurement System (PPMS). The mobility of a representative InAs Hall element is shown in Fig 2.7 (a), and the sheet resistance measured by the van der Pauw method is shown in Fig 2.7 (b), with the carrier concentration to be around 1 x 10 17 cm -3 . The median peak mobility of 5100 cm 2 /V-s is measured at 100 K. The room 24 temperature mobility measured under these conditions is 3200 cm 2 /V-s. Notably, the shape of the curve is typical for any single-crystal 3D semiconductor, and the temperature region for peak mobility occurs around the same temperature as that seen in epitaxially grown InAs of similar carrier concentration. 59 This further corroborates the fact that our grown material is indeed single crystalline, where the mobility is not limited by scattering at grain boundaries (which should manifest itself with reducing mobility with reducing temperature), but rather primarily from temperature-independent surface roughness scattering. To validate our hypothesis, we calculated the temperature-dependent mobility of bulk InAs and could fit the experimental data with the calculated temperature-dependent curve scaled by a constant value that we empirically ascribe to surface roughness scattering as indicated in Fig 2.8 (a). 60 The electron mobility measured from the InP templated films is plotted in Fig 2.7 (c) along with a similar fitting function. The qualitative similarity of temperature dependence indicates single crystallinity, and peak mobility of 370 cm 2 /V-s is measured, also primarily limited by surface roughness. The sheet resistance is shown in Fig 2.7 (d). At 100 K, an inflection point indicates that ionized impurity scattering becomes significant as compared to the surface roughness scattering. Calculated curves with and without surface roughness scattering for InP are shown in Fig 2.8 (b). 25 Figure 2. 7 (a) Hall mobility of TLP InAs, (b) Sheet resistance of TLP InAs, (c) Hall mobility of TLP InP, (d) Sheet resistance of InP. Figure 2. 8 (a) InAs mobility with and without surface roughness fitted to experimental data, (b) InP mobility with and without surface roughness fitted to experimental data. 26 In this part of work, single crystal growth of III-V semiconductors on a very thin (<5 nm) amorphous buffer layer of molybdenum oxide on thermal SiO2/Si carrier wafer in areas exceeding 1500 µm 2 is achieved, by carefully tuning the growth conditions. Electron mobility exceeding 5000 cm 2 /V-s at low temperature, and 3200 cm 2 /V-s at room temperature, were measured in 225 nm thick InAs grown by this method. InP electron mobility was measured to be 370 cm 2 /V-s at 100 K, and 200 cm 2 /V-s at room temperature. 2.3 Low-temperature high mobility InAs To remove the temperature constrain of BEOL compatible material growth by the TLP approach, a dual-zone tube furnace system is built to do the low-temperature TLP (LT-TLP) growth of III-V materials. As indicated in Fig 2.9, up-stream (where carrier gas and group V hydride gas flow in) and down-stream ( right half close to exhaust) temperatures can be controlled independently. In this furnace system, templated specimens are loaded into low-temperature zone, where temperature is maintained below 400 ℃, and high-temperature zone in up-steam is needed for decomposing the group V hydride gas. Figure 2. 9 Schematic of a dual-zone furnace system for LT-TLP. 27 The process to conduct the LT-TLP growth is similar to high-temperature TLP explained in previous section. In this part of work, In layer with 270 nm thickness was evaporated directly on aluminum oxide substrate and capped with E-beam evaporated SiO2 layer. The interfacial layer of MoOx used before was removed, since it's considered as a relatively unstable material. With the control of the aspect ratio of templated mesa, In still can wet the area during the growth without the help from MoOx. Figure 2. 10 Overview of the LT-TLP growth of III-V semiconductor As shown in Fig 2.10 (a), during the growth cracked arsenic flux is optimally controlled by tuning the flow rate of arsine and upstream temperature to achieve just enough positive supersaturation to maintain the single nucleus in each mesa. With time, the nucleus grows into a single crystalline InAs mesa. Microscopic images in Fig 2.10 (b)-(i) to (v) taken from different timing along the growth process can further support the growth mechanism. And the side growth can be etched by self-align RIE etch as mentioned previously, shown in Fig 2.10 (b)-(vi). 28 More characterizations like the SEM image, out-of-plane crystallographic orientation, surface roughness, and the Raman spectrum of a cross-shape InAs for van der Pauw and Hall mobility measurements are included in Fig 2.11. Figure 2. 11 (a) SEM of a fully fabricated InAs hall element, (b) EBSD map of InAs hall element, (c) AFM map of surface roughness, (d) Raman spectrum of LT-TLP InAs. The single uniform color shown by the EBSD map is indicating single out-of-plane crystallographic orientation and single crystallinity. The surface roughness map, shown in Fig 2.11(c), of a representative area, is obtained by atomic force microscopy (AFM). RMS roughness is measured to be 1.8 nm, which is dictated by the surface roughness of the deposited indium. And a typical Raman spectrum with TO, LO mode peaks observed at 221.7 cm -1 and 231.5 cm -1 is consistent with observation from bulk InAs. 29 Figure 2. 12 (a) Experimental and theoretical Hall mobility, (b) Sheet carrier density, (c) Theoretical calculation of InAs mobility with and without surface roughness scattering, (d) InAs electron mobility as a function of RMS surface roughness. Similar with last section, the temperature dependent Hall measurement is conducted. Electron mobility is extracted and shown in Fig 2.12 (a). A median peak mobility of 6750 cm 2 /V-s is measured at 50 K, and a mobility of 5878 cm 2 /V-s at room temperature. A sheet charge density of ~1.53 ×10 13 cm -2 is measured and is found to be independent of temperature between 2 to 300 K (Fig 2.12 (b)). InAs is known to demonstrate a surface electron accumulation layer due to pinning of the surface electron chemical potential above the conduction band minimum. 61 Here, InAs surface is not gated, and have a relatively thin layer of InAs (270 nm). Thus, the mobility will be 30 almost entirely dominated by the surface accumulation layer, and its temperature independence can thus be also explained. It is well established that surface roughness scattering often dominates the mobility of accumulation and inversion layers. To understand whether the mobility of these devices could be quantitatively explained by surface roughness scattering, we carry out detailed electron scattering modeling to quantitatively match the experimentally measured mobility and subsequently predict the highest achievable mobility. The electron mobility of InAs is calculated by considering ionized impurity scattering, acoustic phonon scattering, non-polar optical phonon scattering, polar optical phonon scattering, and surface roughness scattering. First, we calculated the mobility limited by phonon and ionized impurity scattering only. This gives us the expected temperature dependent mobility of a perfectly smooth InAs film, shown by the continuous red curve in Fig 2.12 (c). We also calculated the mobility limited only by surface roughness as a function of RMS roughness and correlation length. An RMS roughness of 1.8 nm is used, as measured by our AFM inspection of the sample. We then fitted the experimental electron mobility values with the calculated electron mobility using the correlation length as a parameter, where the resulting fit is shown by the black dotted curve in Fig 2.12 (c). The difference in the mobility values between that of a perfectly smooth film and of a film with 1.8 nm RMS roughness can thus be clearly visualized. Critically, we see a nearly ideal fit between the model and experiment across the wide temperature range of 2K to 300K, providing strong support for the accuracy of this model. However, this also suggests that we can expect the mobility to be higher if the surface roughness can be reduced. To quantitatively identify what mobilities could be achieved, we calculate the expected mobility of our grown materials as a function of the surface roughness as shown in Fig 2.12 (d). and find that mobility of up to 20,000 31 cm 2 /V-s could be achieved for the same material geometry if a surface roughness of 0.5 nm or lower is achieved. Fig 2.13 is compiled to illustrate where the performance of these materials falls within the spectrum of equivalent material systems grown on non-epitaxial substrates, which is showing the highest electron mobilities reported from different material families which have been grown directly on amorphous dielectric surfaces. Figure 2. 13 Comparison plot for electron mobilities of different material families monolithically integrated on amorphous dielectrics. This is shown as a function of growth temperature, and include 2D materials, conductive oxides and nitrides, polycrystalline III-Vs, and solid phase crystallized silicon, as well as previously reported TLP grown III-Vs. It is seen thus far that the mobilities of monolithic 2D materials have been limited to below 50 cm 2 /V-s, and still require a temperature much higher than the 400 ° C threshold for back-end integration compatibility. Conductive oxides such as indium gallium zinc oxide (IGZO) and solid phase crystallized silicon (SPC-Si) have been successfully realized at very low integration temperatures, below 200 ° C, but the mobility is also limited to within 200 cm 2 /V- 10 1 10 2 10 3 10 4 Electron Mobility (cm 2 /V-s) 1000 800 600 400 200 0 Growth Temperature (ºC) poly-Si IGZO ZnO:Al WSe 2 WS 2 MoS 2 SnS 2 TF-VLS InP TLP InP poly-InAs In 2 O 3 poly-InP Zn 3 N 2 SnO 2 TLP InAs (this work) TLP InAs (projected) 32 s. InP grown via TLP growth exhibits mobilities in the ~500-750 cm 2 /V-s range. However, the InAs demonstrated in this work reaching room temperature values of ~5800 cm 2 /V-s, is the highest thus far, among any material families that can be monolithically integrated on amorphous dielectric surfaces at any growth temperature. As a brief summary of this sub-section, high mobility single crystal InAs mesa with room temperature mobility reaching ~5800 cm 2 /V-s have been realized on amorphous dielectric substrates and integrated with LT-TLP approach. Mobility modeling fitted to the experimental data suggests that the limiting factor for these materials is not the intrinsic material quality but surface roughness. By reducing the surface roughness of the grown material, it is projected that mobilities of 15,000-20,000 cm 2 /V-s can be achieved with this approach for 270 nm thick samples. 2.4 Summary The two constraints for BEOL compatible III-V compound semiconductors integration (1) large area integration, and (2) 400℃ can be eliminated by optimizing TLP growth recipe such as group V hydride gas partial pressure, and implementing LT-TLP method enabled by dual-zone furnace. Both techniques attained single crystalline semiconductor materials, and demonstrate high electron mobilities. The InAs mesa grown by LT-TLP approach showed electron mobility ~5800 cm 2 /V-s on amorphous dielectric substrates at room temperature. And through mobility modeling, the mobilities are projected to reach 15,000-20,000 cm 2 /V-s with reduced surface roughness. Clearly, LT-TLP paved the way for III-V compound semiconductors systematical integration on Si back-end process and opened a new avenue for III-V and Si-based hybrid photonic integrated circuits. 33 Chapter 3. III-Vs heterogeneous epitaxy on Si by TLP and MOCVD 3.1 Introduction In chapter 2, LT-TLP can directly integrate monolithic III-V templates on the amorphous substrate with the fine control of hydride gas flow rate to ensure a single nucleus in each mesa. The inverse pole figure from EBSD shows the single crystallinity for each template, however, due to the absence of crystal substrate the initial nucleus crystal direction is randomly distributed across the substrate as indicated in reference paper 62 . To achieve unified device performance, the aligned crystal orientation of templates across the whole chip is preferred. This chapter proposes a new heterogeneous epitaxial integration approach to grow III-Vs on Si substrate. To be specific, the TLP growth approach will be used to synthesize the InP and InAs on the MOCVD III-Vs/Si substrate and yield high-quality materials with aligned crystal orientations and low defect density. The process and technique demonstrated here can potentially provide a broad heterogeneous integration platform for III-Vs and even II-VIs on Si. 3.2 MOCVD InP on Si substrate In this project, metalorganic chemical vapor deposition (MOCVD) was used to epitaxially grow III-Vs on Si substrate. In MOCVD of compound semiconductors, one or more precursors consist of organic groups bonded to a metal atom (such as trimethylindium) thermally decompose and combine with the product of another source, typically a non-metal hydride precursor such as phosphine. The use of these metalorganic precursors allows for stoichiometric material deposition by exploiting their product’s lower vapor pressure compared to both the reactant and product of the nonmental source, as long as the more volatile source is in excess. 34 Heteroepitaxy III-Vs on Si often yield a high density of various defects caused by material dissimilarities, such as large lattice mismatch, polar-on-nonpolar growth, and different coefficient of thermal expansion 63 . Among these defects, antiphase boundary, threading dislocations, and stacking faults are the most frequently observed. 3.2.1 Defects commonly observed for III-V heteroepitaxy on Si The antiphase boundary (APBs) originated from the nature of polar and nonpolar nature of III-Vs and Si, and the mono-atomic step of (001) surface. Each terrace edge of the (001) surface initiates APBs in III-V layer. The crystal model in [110] projection shows the possible APB configurations in Fig 3.1. Figure 3. 1 Sketch of the APB formation in the {111} and {110} lattice planes of the GaP zinc- blende structure due to the presence of mono-layer steps 64 The threading dislocations (TDs) caused by large lattice mismatch like 4% between GaAs and Si, and 8% between InP and Si, introduce a build-up of strain energy on the epitaxial layer during the growth. When the film thickness is above the critical thickness, the strain energy is relaxed through 35 the formation of misfit dislocations (MDs) along the heterointerface and TDs toward the surface. TDs introduce the electronic states in the bandgap of III-V semiconductor which acts as nonradiative recombination center 63 . The stacking faults are partial displacement affecting the regular sequence in the stacking of the lattice planes, which are commonly found in close-packed crystal structures like face-centered cubic (fcc) and hexagonal close-packed (hcp) structures. Intrinsic stacking faults result from a vacant plane while extrinsic stacking faults are due to the insertion of an extra plane in sequence. As shown in Fig 3.2, in the wurtzite structure, there are two types of intrinsic faults and one type of extrinsic fault. In the zinc-blende structure, there is one type of intrinsic stacking fault and one type of extrinsic fault 65 . Figure 3. 2 TEM images of InAs and InAs1-xSbx nanowires showing defect-free regions of wurtzite and zinc-blende structures and the various planar defects that are observed in both structures 65 . 36 3.2.2 Approaches for high-quality III-V on Si The aspect ratio trapping (ART) with selective area growth (SAG) has been developed to reduce the defect density 66 . The principle behind this is that the threading dislocation that arises from mismatched growth usually propagates along <111> direction, and forms 54.7° angle with (100) substrate. As result, with a high aspect ratio (narrow opening and high mask thickness), the threading dislocations that form at the III-Vs/Si interface impinge on the sidewalls of the mask layer and are annihilated before penetrating into the bulk of the film. The typical mask material can be SiO2 or SiNx. Due to the lateral diffusion of precursor molecules on the dielectric mask, the growth rate enhancement is typically observed and leads to more complex growth parameter optimization. The two-step growth method was proposed to mitigate the defect density and was widely adopted in GaAs/Si 67 . The two-step growth starts with low temperature (LT) growth around 400℃, followed by annealing and growth of III-Vs at typical growth temperature between 550 and 600℃. The motivation behind this is that, at low temperature, high density GaAs islands distribute uniformly and more easily to coalesce into a continuous layer at the later high-temperature step 63 . Another approach to reduce the defect density arising from the material dissimilarity is using an intermediate buffer layer that is more close to the Si substrate. For example, Ge 68 , GaAsP 69 and InGaP 70 were utilized as intermediate buffer layer for GaAs/Si heteroepitaxy. The Ge layer was widely used because of its miscibility with Si and nearly the same lattice constant with GaAs. Alternatively, strained-layer superlattices (SLSs) structure was proposed to reduce the dislocation density. Matthews et al demonstrated that GaAsP-GaAs superlattice turned aside the propagating 37 TDs 71 . In SLSs, multiple pairs of two lattice-matched layers alternately under compression and tension. The stain field of SLSs can bend over and force the dislocations propagating upward to move laterally toward the edge of the sample, then leading to dislocation coalescence and annihilation 63 . In our work, TLP approach was adopted to integrate III-Vs on MOCVD heteroepitaxy III-V/Si substrate. To be noted, the defects in III-Vs layer from MOCVD growth barely propagate into the III-Vs layer grown by TLP. The results will be shown in the following sections. 3.2.3 MOCVD InP on Si with GaAs nucleation layer Before the MOCVD growth, the Si wafer was firstly cleaned with acetone, IPA, and DI water, then etched by HF: H2O = 1:10 solution for 2 min to remove the natural SiO2 layer immediately before loading the wafer into the growth chamber. The growth recipe is shown in Table 3.1. In the first step, the high temperature H2 annealing can remove the native SiO2 on the Si wafer surface. The As ambient annealing leads to the formation of a stable As monolayer on the Si surface. This monolayer can improve the GaAs nucleation density, when TMGa precursor reaches the substrate surface. It is also reported that the surface rearrangement of Si (100) caused by interaction with arsenic can form As-As dimers, which is depending on the annealing time and temperature 72 . A low-temperature GaAs nucleation step is conducted to accommodate the large lattice mismatch between InP and Si. Then instead of two- step growth, an intermediate temperature growth at 560℃ is added to potentially decrease the density of defects. 38 Table 3. 1 MOCVD epitaxy recipe of InP on Si with GaAs nucleation buffer Steps Temperature (℃) PH3 (sccm) AsH3 (sccm) TMIn (sccm) TMGa (sccm) V/III ratio Time (sec) Annealing in H2 920 0 0 0 0 NA 60 Annealing in AsH3 920 0 100 0 0 NA 60 GaAs nucleation 400 0 100 0 30 100 180 InP nucleation 400 300 0 100 0 1430 300 InP growth 560 180 0 280 0 350 300 InP growth 610 180 0 280 0 350 1500 The SEM images of epitaxy InP on (100) Si wafer with and without the GaAs nucleation step are shown in Fig 3.3. Both samples are tilted 45° to show better contrast, and the thickness of both films are around 1 𝜇𝑚. Clearly, the InP epitaxy layer with GaAs nucleation layer yielded with better smoothness and fewer pits at the surface. The irregular polygons on the surface of the sample in Fig 3.3 are the APBs propagated from the interface of GaAs and Si. 39 Figure 3. 3 SEM images of 45° tilted InP on (100) Si substrate (a) without GaAs nucleation layer (b) with GaAs nucleation layer before the InP nucleation step. Scale is 1 𝜇𝑚. Although the GaAs nucleation layer improved the surface roughness of InP epitaxy layer on Si, numerous APBs and SFs are still presented at the interface of InP/GaAs and Si interface as shown by the TEM image in Fig 3.4. Some of the APBs annihilated each other as discussed before were indicated by the arrows in Fig 3.4 (a) and (b), but many of the partially annihilated APBs and SFs propagated upwards and form the typical 54.7° angle with the substrate. Figure 3. 4 TEM of MOCVD InP and Si interface with GaAs nucleation step at (a)190,000 (b) 820,000 magnification. (b) is the white square area in (a). Arrows indicate annihilation of APBs. 40 3.3 Crystal orientation alignment and defect filtering by TLP Upon the InP epitaxy layer on (100) Si wafer, templated In (500 to 1000nm) and SiO2 layer (300 nm) were deposited by thermal evaporator and e-beam evaporation respectively. As shown in Fig 3.5, the TLP growth as discussed in Chapter 2 and removing the capping layer through etching were carried out to integrate III-Vs (InP on InP, or InAs on InP) on the InP epitaxial substrate. At the step of template evaporation shown in Fig 3.5 (b), doping sources like Sn, Ge, Zn can be evaporated as well to achieve n-type or p-type III-Vs. In our work, templates with Sn evaporation before In or after In were prepared to investigate its role during TLP growth. Figure 3. 5 Schematic of process. (a) Pretreated Si substrate. (b) InP epitaxy layer on (100) Si wafer. (c) Evaporate templated In and SiO2 capping layer. (d) TLP growth with hydride gas. (e) Remove side growth by III-V etcher. (f) Remove capping layer by dry or wet etch. The integrated 20×20 𝜇𝑚 2 InP mesa on epitaxy InP on Si is shown in Fig 3.6(a). The surface morphology of the mesa is inherited from the epitaxy InP substrate during In evaporation. The gap 41 between the mesa and epitaxy InP substrate around the mesa edges were formed during the III-V etch to remove the side growth. The transmission electron microscopy (TEM) images of partially grown InP mesa without Sn doping are shown in Fig 3.6 (b) and (c). As demonstrated in Fig 3.4, at the InP/GaAs and Si interface, various defects can be observed. Some of the defects propagate to the surface of epitaxial InP layer, but most of them are terminated at the TLP grown InP and MOCVD grown InP interface. As shown in Figure 3.6(c), the InP by TLP growth strictly followed the epitaxial InP lattice structure and none of the planar defects such as stacking fault or twinning boundaries were observed in this area. To observe a relatively larger area, the scanning transmission electron microscopy (STEM) images for this structure are shown in Fig 3.6 (d)-(f). Similarly, InP without Sn doping layer in Fig 3.6(d) and InP doped by Sn from the top in Fig 3.6(e) show much fewer defects than the epitaxial InP layer on Si, only one planar defect and one propagated stacking fault were observed respectively. However, when Sn doping layer was evaporated before In evaporation, numerous of stacking faults and tunning boundaries were observed in Fig 3.6(f). This is suggesting the Sn layer can significantly impact the surface energy of epitaxy InP substrate during the TLP growth. 42 Figure 3. 6 (a) SEM image of InP by TLP growth on epitaxy InP on Si. Scale is 2𝜇𝑚. (b) TEM image of partially grown InP by TLP. (c) TEM image at three phase boundary as indicated by the white square in (b). STEM image of InP after TLP growth (d) without doping source, (e) with Sn doping layer evaporated after In, (f) with Sn doping layer evaporated before In. Scale is 1𝜇𝑚. The transmission Kikuchi diffraction (TKD) map can reveal the crystal orientations and distribution with high resolution. As shown in Fig 3.7. For the In template without Sn doping layer and In template with Sn doping layer on top of it, the InP from TLP growth exactly followed the substrate orientation as shown in Fig 3.7 (a,b-ii) - (a, b-iv), which are the inverse pole figures from TKD map along Z (perpendicular to the paper), Y (upward), and X (right) direction. The two blue color grains shown in Fig 3.7 (a-iii) are the 60° rotation twins, which can be verified by the point- to-point misorientation analysis data in Fig 3.8 (a) and (c). The twinning energy is intrinsically low for InP compared with other III-Vs 73 . As for the In template with Sn doping layer evaporated first, the InP from TLP growth show a much larger number of twinning boundaries as supported by data from Fig 3.8 (b) and (d). The distinct crystal orientation results from the structure of the template suggest that the Sn doping didn’t lower the stacking fault energy, but directly impacted the surface energy. Otherwise more twinning boundaries and stacking faults are expected from TKD data in Fig 3.7 (b). Another possible reason behind that is the Sn layer was oxidized before the evaporation of In, which can be seen as a thin amorphous substrate that InP was grown on. The distinct effective substrate property caused a large number of stacking faults and twinning boundaries in the sample shown in Fig 3.7 (c). These results suggest that different doping source (like Ge and Zn) on top of In template can achieve the doping and good crystal alignment simultaneously. 43 Figure 3. 7 STEM and TKD of InP on epitaxy InP on Si. (a-i) STEM image of InP without Sn doping. (a-ii) to (a-iv) TKD of InP without Sn along Z (perpendicular to paper), Y(upward), and X(right) direction. (b-i) STEM image of InP with Sn evaporated after In. (c-i) STEM image of InP with Sn evaporated before In. (b,c-ii) to (b,c-iv) corresponding TKD along Z, Y, and X. Figure 3. 8 TKD of InP on epitaxy InP on Si (a) with (b) without Sn doping at the interface. (c) and (d) Point-to-point disorientation verse the distance from the beginning of analyzing line corresponding to the white line in (a) and (b). In addition to the 20×20 𝜇𝑚 2 square mesa pattern, 90×2 𝜇𝑚 2 stripes can achieve outstanding growth as well. As shown by Fig 3.9(a), the representative five pieces 90×2 𝜇𝑚 2 channels are integrated on p-type epitaxy InP layer on Si. The EDS maps of In and P corresponding to this area confirmed the composition of channels and substrates. Fig 3.9 (d-f) are the overlapped band contrast, grain boundary, and EBSD map of the channels along Z, Y, and X directions. The sample 44 was tilted 70° to collect the EBSD map, as a result of it, the signals from the substrate immediately below the bottom of each channel are blocked by the thickness of channels. The uniform color in Fig 3.9 (d-f) suggest the identical crystal orientations from substrate to etch channels. Only 4 pieces of twinning grain in size of ~ 0.1×2 𝜇𝑚 2 were observed in the second and middle channel in Fig 3.9(d). The point-to-point disorientation is plotted in Fig 3.10(b) by analyzing the midchannel as shown in Fig 3.10(a), from which 60° disorientation verified that the grains observed in EBSD maps are twins. Figure 3. 9 (a) SEM image of 5 pieces 90×2 𝜇𝑚 2 InP channel on epitaxy p-type InP on Si. (b) EDS map of In. (c) EDS map of P. (d-f) Overlapped band contrast, grain boundary, and EBSD map along Z (perpendicular to paper), Y(upwards), and X(right) direction. The scale is 25 𝜇𝑚. 45 The static photoluminescence (PL) and time-resolved photoluminescence (TRPL) spectrum were carried out to characterize the material quality. A constant-power 532 nm laser was used as the excitation source for PL spectrum. As shown in Fig 3.11 (a), the peak intensity measured from InP grown by TLP on top of the epitaxial InP substrate on Si is more than two orders of magnitude higher than that from the epitaxial InP by MOCVD. This contrast can be uniformly observed as the mapped PL peak intensity over the 30×30 𝜇𝑚 2 scanning region shown in Fig 3.11 (b). Figure 3. 10 (a) Overlapped band contrast, grain boundary, and EBSD map along Z (perpendicular to paper). (b) Point-to-point disorientation from the dash line in (a). At high-level injection, the total recombination can be described by R = An+Bn 2 +Cn 3 , where A is the Shockley-Read-Hall (SRH) recombination rate, B is the radiative recombination rate, and C is the Auger recombination rate. Given the unintentionally doped carrier concentration (~10 17 cm -3 ) and low Auger recombination coefficient, the contribution from Auger recombination can be neglected. And for the measurement excited with the same excitation power, the TLP grown InP 46 on MOCVD InP showed 10 to 100 folds higher peak intensity than that from the MOCVD grown InP on Si. This indicates the much lower contribution of trap-assisted non-radiation recombination and suggests significantly lower defect density in the TLP grown InP layer. For the TRPL measurement, 80MHz pulses laser with 700nm wavelength were used. As plotted in Fig 3.11 (d), the 1/e lifetime of the specimen with TLP InP mesa (0.45 ns) is clearly longer than the specimen only with MOCVD grown InP layer on Si (0.28 ns). In this measurement, the light spot is larger than the size of TLP InP mesa, which included the signal from substrate as well. As a result, we believe with a smaller spot size the difference of 1/e lifetime will be more significant. Figure 3. 11 (a) PL spectrum of TLP InP on epitaxy InP layer on Si, and epitaxy InP by MOCVD on Si. Insert is the SEM of InP mesa measured for the PL map in (b). (b) Peak intensity map of InP mesa. (c) Normalized PL spectrum for InP grown by TLP on epitaxy InP layer and the 47 epitaxy InP by MOCVD. (d) Time-resolved PL spectrum of specimens with or without TLP InP on epitaxy InP. Based on the structural and optical data, clearly, TLP grown InP on epitaxial InP substrate demonstrated much higher material quality, and considerably lower defect density. To understand the reason behind, a subcritical dewetting assisted defect filtering mechanism is proposed to model the TLP growth process. First of all, during the TLP growth, the layer-by-layer growth along the epitaxial InP substrate was not observed. Instead, oriented nucleation with {111} and {110} growth front facet will be formed as typical TLP growth in Chapter 2, then followed by lateral growth until consuming all In template. And notably, as shown in Fig 3.6 and 3.7, for the samples without Sn beneath the In layer before the TLP growth, we constantly observe small voids at the interfaces between indium and MOCVD InP, and interfaces between TLP InP and MOCVD InP. This suggests the MOCVD InP surface is not a surface with sufficiently high surface energy that allows the fully wetting of liquid phase indium. However, with the capping layer and large liquid In volume, at the growth temperature, some subcritical dewetting regions were formed and observed. As a result, the upward propagated SFs and APBs can be terminated as shown in Fig 3.12 (a). This assumption is also supported by the TEM images shown in Fig 3.12 (c) and (d). While for the region without the subcritical dewetting voids, the SFs may still propagate through the interface and enter the TLP InP layer as observed in Fig 3.12 (e). However, this model suggests more subcritical dewetting voids can filter out more defects reaching the surface of MOCVD InP layer. But an extreme large number of subcritical dewetting regions will decrease the number of bonds between TLP and MOCVD grown InP layer, and eventually 48 diminish the adhesion between them. In addition, the subcritical dewetting voids may impact the device's performance if it’s vertically structured. Figure 3. 12 TLP growth mechanism on epitaxial substrate. (a) TLP growth with subcritical dewetting region. (b) TLP growth without subcritical dewetting region. (c) TEM image of interface between In and MOCVD InP. (d-e) TEM images of interface between TLP InP and MOCVD InP (d) with (e) without subcritical dewetting region. This integration approach also allows the synthesis InAs on InP epitaxy layer on Si, which can be implemented by switching the hydride gas from PH3 to AsH3 as indicated in Fig 3.5 (d). A nearly full growth of InAs mesa is shown in Fig 3.13 (a), with the EDS maps of P, As, In shown by Fig 3.13 (b-d). The phase map in Fig 3.13 (e) clearly shows two blue areas are the remaining In inside the mesa. A finer tuning of gas flow of AsH3 and longer growth time can help to achieve full growth. The overlapped band contrast, grain boundary, and EBSD maps are shown in Fig 3.13 (f- h). A few twinning grains are observed across the mesa area. It might be caused by rougher InP epitaxial substrate. 49 Figure 3. 13 (a) SEM image of 20×20 𝜇𝑚 2 InAs mesa on epitaxy InP on Si. (b-d) EDS maps of P, As, In. (e) Phase map. (d-f) Overlapped band contrast, grain boundary, and EBSD map along Z (perpendicular to paper), Y(upwards), X(right) direction. Scale is 5 𝜇𝑚. 3.4 Summary In this chapter, the high quality III-Vs with unified crystalline orientation were achieved by TLP growth on Si substrate with MOCVD deposited epitaxy layer. The defect density in TLP grown III-Vs layer is considerably lower than that in MOCVD layer due to the lattice mismatch. The doping source can be added on top of the template to engineer the material properties. In addition, The subcritical dewetting region assisted defect filtering mechanism is proposed to explain the lower defect density. Notably, the integration approach demonstrated in this chapter doesn’t require complicated ARTs and SLSs design, or a thick buffer layer to mitigate the defect density. It potentially provided another platform for high-quality and cost-effective III-Vs integration on Si. 50 Chapter 4. Artificial synapse emulated by InP FETs 4.1 Introduction As discussed in chapter 1.2 of this thesis, emulation of synaptic activity with a single device has been widely demonstrated in the floating gate Si MOS transistor, and memristor-based synaptic devices from metal oxides, phase-change materials, ferroelectricity, and ferromagnetism. Synaptic behaviors emulation based on time-dependent threshold voltage shifting arising from charging and discharging of traps in the semiconductor, at the insulator-semiconductor interface, or ion migration in the gate dielectric in MOSFETs has been reported. But due to the fundamental limitations on the growth of high-quality crystalline material on amorphous material substrates, current 3-D approach integrated III-V based devices are rarely reported. Since the process constraints have been eliminated as discussed in chapter 2, in this section, the scalable, back-end compatible, artificial synapse emulation is presented by InP based FETs, where InP channels were grown by TLP approach. The following content are largely based on the peer- reviewed papers. 74 4.2 InP synaptic device In Fig 4.1 (a), a synapse junction between two neurons is schematically shown. The connections between two neurons can evolve over time and are plastic. Depending on the dynamics of the neural network, the synaptic weight can remain unchanged, increased, or decreased, which are corresponding to the biological concepts for elasticity, potentiation, and depression. Although many details haven’t been completely uncovered, it’s widely believed that these change in synaptic 51 weights are crucial ingredients for learning and memory. The synaptic weight change is also time dependent, and based on the lift time of the plasticity, two categories: short-term plasticity and long-term plasticity are defined. Short-term plasticity often refers to behavior on the milliseconds to seconds time frame, while long-term plasticity refers to behaviors on time frame of hours to years. 8, 75 The InP based FET device being used to emulate the synaptic behavior is schematically shown in Fig 4.2 (b). The InP channel is 100nm-thick and top gated with 60nm Al2O3 working as the gate dielectric. Here, the Al2O3/InP stack can be seen as the synapse junction, connecting the pre-synaptic neuron (gate electrode) to the cell membrane of postsynaptic neuron (drain electrode). Presynaptic action potentials are applied as pulses to the gate electrode, source-drain current is measured as post-synaptic current (PSC), and the synaptic strength is the conductance of the semiconductor channel. Figure 4. 1 (a) Schematic of a biological synapse showing communication of signal between neurons by release of neurotransmitters from the presynaptic neuron causing diffusion of Na ions into the postsynaptic neuron. (b) Schematic of the InP channel FET on silicon as the synaptic device. 52 Based on this structure, the application of a voltage pulse train on the gate leads to charging or discharging of traps in the oxide or at the oxide/semiconductor interface, and shifting in threshold voltage. As the results of it, the PSC at the same gate voltage before and after the voltage pulse might be different. The effect of amplitude of gate pulse in changing the electrostatics of channel and the artificial synapse behavior is shown in Fig 4.2. The amplitude of the gate pulses is interpreted to be proportional to the probability of exocytosis for neurotransmitter release. Higher amplitude pulse signifies the higher probability of release of neurotransmitters. As for device physics level, higher gate voltage pulse causes higher energy traps to be accessed. Figure 4. 2 (a) Transient PSC before and after application of presynaptic pulse. (b) Short-term and long-term synaptic weight change for different values of presynaptic voltage pulse. Fig 4.2 (a) shows the transient PSC before (t<0 s) and after (t>0 s) applying the presynaptic pulse, where rectangular pulse train of 40 pulses of width 500 µs and 50% duty cycle with 0V baseline 53 was applied. Three behaviors are obtained: elasticity (with pulse amplitude of 0.1V), potentiation (with pulse amplitude of -5V), and depression (with pulse amplitude of 5V). The synaptic weight change is also indicated by Fig 4.2 (b), where we define STP as the difference between the average PSC over the first 1 s after pulse and that before pulse, and LTP as the difference between average PSC between 10 and 40 s after pulse and that before pulse. Clearly, the magnitude of plasticity increases with increasing amplitude, which can be modeled with exponential functions: ∆𝑤 =𝐴×𝑒 * !" /* # where Vgp is the peak gate voltage, and Va is the activation voltage for the traps. The physical implication of a nonzero plasticity is that a future signal would be transduced with the modified weight, which leads to selectivity of pathway for transduction of signal to converge to an optimal solution in a neural network. Needs to be noted that, the synaptic weight change at time t is actually a function of synaptic weight at t and the neuronal activity at that time. It can be represented as: ∆𝑤 ' =𝑓(𝑤 ' ,𝜃 ' ) Where 𝑤 ' is the synaptic weight, 𝜃 ' is the neural activity at time t. In another word, initial condition of synapse can influence the same neuronal activity and results in different PSC. This observation is named as metaplasticity in neuron science. 54 Figure 4. 3 (a) Increased potentiation of synapse succeeding a depressing priming comparing to potentiating priming. (b) Increased depression of synapse succeeding a potentiating priming compared to depressing priming. (c) STP weight change for different values of presynaptic voltage pulse. As shown by Fig 4.3, metaplasticity of our synaptic device was emulated by applying the same gate voltage pulse but preceded by different “priming” gate voltage pulses to emulate prior brain activity. The gate voltage pulse trains consisted of 10 pulses of 5 ms width and 6 ms period, and 2.5 V pulse as depressing priming pulse and -2.5 V pulse as potentiating priming pulse. From Fig 4.3 (a), it’s shown that the same -4.5 V pulse train gives a higher relative change of PSC when it follows depressing priming, and similarly, in Fig 4.3 (b), +4.5 V pulse train gives a smaller depression when it follows potentiating priming. Fig 4.3 (c) shows the short-term synaptic weigth changing extracted from the PSCs for gate voltages ranging between -5V and +5V, for three different initial conditions of no priming, depressing priming, and potentiating priming. It is suggesting that a reduction in potentiation weight change occurs for an initially potentiated synapse, while an increased potentiation occurs for an initially depressed synapse. The number neurotransmitters is dependent on the number of action potentials, and this can be emulated by increasing the identical pulse number. Here the +5 V and -5V gate pulses with 5ms 55 width and 5.5ms period is applied to the devices. As shown in Fig 4.4 (a), some representative potentiation and depression curves are plotted. Figure 4. 4 (a) PSC before and after application of varying pulse number (b) Variation of STP relaxation time constant with different number of action potentials (c, d) long-term and short- term weight change for different number of action potentials. Clearly, both potentiation and depression are increased with increased number of action potentials, and when fitted with equation 76 : 𝑃𝑆𝐶 =𝐼 ,, +0.5×(𝐼 '-. −𝐼 ,, )×(𝑒 /'/0 +𝑒 /'/1 ) Iss is the steady-state current value, It=0 is the initial current value before action potential, c and d are the two fitted decay constant pointing to fast and slow decay rate. The PSC decay time constant is plotted in Fig 4.4 (b), which indicating the relaxation rate initially decreases and gradually saturate with increase in the number of action potentials. Long-term and short-term synaptic weight change are respectively illustrated in Fig 4.4 (c) and (d). Their gradual increase and saturation behavior can be understood by relating it to the traps states population. When action 56 potential number starts to increase, fast traps are first populated, then followed by slower traps gradually filled with increased pulse number, and eventually saturate due to the finite total number of trap states. Figure 4. 5 (a) Waveforms representing back-reflected postsynaptic action potential and presynaptic action potential for STDP measurement. (b) LTP weight change for different values of time offset between pre and post synaptic action potentials. Synaptic modification arising from the correlated activity of pre- and postsynaptic neuron was first introduced by Hebb 77 in 1949 and later refined by other researchers such as Bienenstock-Cooper- Munro in 1982. 78 Spike-timing dependent plasticity or STDP is one of the most well-known version of Hebbian learning rule, which is also the training rule for spiking neural network (SNN). A commonly implemented STDP behavior is the potentiation of the synapse when the postsynaptic action potential succeeds the reflected presynaptic action potentials and depression when the reflected postsynaptic action potential precedes the presynaptic action potential. The highest magnitude of plasticity occurs for the shortest time offset between the pre and postsynaptic action potentials. Here we designed the presynaptic action potential as a pulse goes from 0 to +2.75V to -5V to 0V with a total width of 10ms. The reflected postsynaptic action potential is a pulse with a 57 baseline 1.5V, ramping up to 2.1V in 100ms, ramping down to 0.9V in 20ms, and again ramping up to 1.5V in 100ms, as shown in Fig 4.5(a). And consequently the Fig 4.5 (b) is demonstrated as expected that, when prolong the time gap between pre and post synaptic action potentials, the LTP weight change decays down to elasticity, but when the time gap is small, the highest magnitude of LTP weight change is achieved. 4.3 Gate dielectric engineered InP synaptic device As elaborated in the previous section, trapping state charging and discharging behaviors at the gate dielectric or dielectric/InP channel interface affected by the gate pulses are the key mechanism enabled the modulation of PSC. In this section, the band structure of dielectric layer is further engineered to facilitate more complicated synaptic behavior emulation. Another important functionality observed in biological synapses, but not demonstrated by the device architecture in a CMOS compatible approach previously is the conversion from short-term to long-term memory, which is also referred as memory consolidation. The short-term memory (STM) results from a transient strengthening of pre-existing synaptic connections due to the modification of pre-existing proteins, whereas long-term memory (LTM) results from a persistent strengthening of synaptic connections caused by alternation in gene expression, the synthesis of new proteins, and the growth of new synaptic connections. 8, 79 Here, a heterostructured gate oxide is utilized to mimic the memory consolidation behavior. A thin “energy well” of TiO2 is inserted between an Al2O3 “cladding layer” to enable long-term electron 58 trapping in TiO2 and short-term electron trapping and release in the Al2O3. The schematic of the InP synaptic transistor is shown in Fig 4.6. Figure 4. 6 Schematic of InP synaptic transistor with heterostructured gate dielectrics Here the channels with dimension 25µm length, 2µm width, and 100nm thickness, are top-gated with Al2O3/TiO2/Al2O3 (2nm/5nm/53nm) dielectric film stack. Similar with the FET in previous section, presynaptic neuronal action potentials are emulated by gate voltage pulses and the source- drain current is interpreted as post-synaptic current. Accordingly, the synaptic weight is quantified by the conductance of the InP channel. The transfer characteristic curve sof un-intentionally n- type doped InP synaptic FET is shown in Fig 4.7 (a), indicating On/Off ratio is greater than 10 3 and peak extrinsic transconductance of 7.6µS. A peak effective electron mobility of 445 cm 2 /Vs is extracted by curve fitting. As illustrated in Fig 4.7 (c) Hysteresis increases with greater gate voltage range as the higher electric field across the oxide will increase the tunneling probability of electrons and holes from the InP channel into the TiO2, and simultaneously increase the population of electrons or holes at the surface. The dual-sweep characteristic of the InP transistor at Vds=0.1V and 2.0V is shown Fig 4.7 (d). The clockwise gate hysteresis attributed to the screening of the electric field, results from the charge trapped in the gate dielectric layers. 59 Figure 4. 7 (a) Ids-Vgs of InP synaptic transistor with Vds at 0.1 to 2.1V. (b) Ids-Vds of InP synaptic transistor with Vgs increased from 0.1 to 3.1V. (c) Dual-sweep of Ids-Vgs at Vds=1V. (d) Dual- sweep of Ids-Vgs at Vds =0.1 and 2V. Researchers in disciplines ranging from psychology to molecular biology have studied the physical basis of learning and memory. It is believed that the dynamic change of neural networks based on the synaptic connections underlies the development of human memory. In one accepted model of human memory, proposed in 1968, Atkinson and Shiffrin 80 suggest that memory can be divided into three components: the sensory register, the short-term store, and the long-term store as shown in Fig4.8 (a). In this model, sensory register is the place where incoming information enter first but decay rapidly and are lost, while selected inputs from sensory register go into the short-term store, from where rehearsal can maintain the retention of the information, and further rehearsal can consolidate them into the long-term store, which is a relatively longer repository for information. 60 One important assumption in this model is that the probability of transition from short-term store to long-term store increases with rehearsal repetition, which is congruent with what many humans experience. In neuroscience, the memory consolidation can be distinguished into two processes, one is the synaptic consolidation, which is the same with the late-phase long-term potentiation. Another one is system consolidation, describing the gradual move of memory trace into neocortex area and become hippocampus independent. The memory consolidation behavior can be emulated by an InP synaptic FET with modulated gate pulse number and modeled respect to relaxation time. Figure 4. 8 (a) The milestone psychological model of human memory. (b, c) Band diagram of InP synaptic transistor when applied (b) singe and (c) multiple negative voltage pulses showing STP and LTP behaviors. The heterogenous structured gate dielectrics shown in Fig 4.8 (b) and (c) enables us to selectively inject charge into long-term TiO2 layer through repeated constant-amplitude voltage pulses on the gate. Once the carriers are injected, they are energetically confined, and results in long-term memory of the artificial synapse. This mechanism is supported with PSC measured with increased gate pulse number increased from 1 to 100, demonstrated in Fig 4.9 (a). 61 Figure 4. 9 (a) Measured and fitted pre-and post-synaptic current after N pieces of gate voltage pulses with -5V amplitude, 100 µs period and 50% duty cycle. (b) Stacked bar chart of sensor register-related (aREG), STP-related(aSTP), and LTP-related (aLTP) weight factor. When N=1 the current potentiation spike is caused by the negative voltage pulse resulting holes from InP channel tunnel into the hole traps in Al2O3 adding a net positive charge to the gate dielectric and changing the threshold voltage. The net positive dielectric charge rapidly decay as the traps causing this current potentiation are fast, and the current returns to the same level as before. However, when pulse number is increased to 100, holes are bing sequentially injected into Al2O3 and pumped into the TiO2 layer, which result in an offset of PSC with much longer retention time. The PSCs are model with three exponential decay elements with equation: (1) 𝑃𝑆𝐶(𝑡)=𝐼 2 +(𝑎 345 ∙𝑒 / $ % &'( +𝑎 6#7 ∙𝑒 / $ % )*+ +𝑎 8#7 ∙𝑒 / $ % ,*+ ) where 𝐼 2 is the PSC before the first gate pulse applied to the device, 𝜏 345 ,𝜏 6#7 , and 𝜏 8#7 are the retention constants indicating relaxation time for charges detrapped from the three trapping energy states at Al2O3/InP interface, Al2O3 body, and TiO2 well, respectively. In our fitting, sensory register related retention time constant (𝜏 345 =0.57 𝑠), and STP related retention time constant 62 (𝜏 6#7 =13.65 𝑠) are fixed, matching the time scale of the biological signal stored in corresponding behavior. The values of aREG, aSTP, aLTP, and 𝜏 8#7 are attained and listed in Table 4.1. Table 4. 1 Fitting results for PSC after N pulses Pulse Number aREG aSTP aLTP 𝛕REG (s) 𝛕STP (s) 𝛕LTP (s) 1 0.1308 0.0017 0.0023 0.57 13.65 9.38E+03 5 0.3941 0.1118 0.2069 0.57 13.65 9.39E+05 10 0.5824 0.2090 0.5092 0.57 13.65 9.79E+05 20 0.8987 0.3354 0.7101 0.57 13.65 5.43E+05 50 1.4200 0.5834 1.3120 0.57 13.65 5.43E+05 100 1.9630 0.8550 1.7760 0.57 13.65 1.06E+05 Based on the fitting results, when N≥5, the 𝜏 8#7 is over 1×10 9 seconds, the PSC of which can be seen as long-term memory. And the weight factors of each components after N pieces of gate pulses are plotted in Fig 4.9 (b), demonstrating the increase of each components especially for the LTP. This observation is matching the mechanism we assumed as the behavior when voltage pulse number increase. Importantly, for N=1, there is no contribution from long-term behavior, indicating that the carriers are injected into the short-term traps, which are not able to hop into the long-term traps. Thus, increasing the pulse number or other method which increase the number of trapped carriers in TiO2 layer is necessary for the memory consolidation. Fortunately, we found that increase the pulse width and pulse frequency can achieve the memory consolidation. As shown in Fig 4.10 (a) and (b), PSC for the same device exposed to two different 63 pulses trains with different pulse width (2µs and 50 µs) with -5V amplitude and 10 s period, minimal change of the current is observed from PSC with shorter pulse width. While for long pulse width, the LTM behavior is observed and curved fitted retention time is larger than 5.57×10 9 𝑠. This observation is suggesting that for a given pulse period, increasing the time of exposure allows more charge to be injected across the Al2O3 layer and into the TiO2 layer. This is also consistent with the model proposed, as a greater time under electric field for the dielectric allows more charge hopping across the short-term traps. Another approach to realize the memory consolidation is shrinking the pulse interval time, or increase the pulse frequency. Fig 4.10 (c) and (d) is showing the same devices when applied with same pulse trains but one with 10 s interval, another with 2 s interval. Then retention time fitted from Fig 3.10 (c) is around 287 s, indicating the long-term traps are not accessed due to insufficient charge pumping. On the other hand, increased pulse frequency led to the retention time of 5.57×10 9 𝑠, suggesting the LTM behavior is achieved. This is also consistent with the charge decay model proposed, since the shorter pulse interval time meaning fewer carriers in the short- term scale trapes have the chance to detrap before the coming of next pulse. 64 Figure 4. 10 Normalized PSC of the InP synaptic transistor when applied with (a) 5 identical gate pulses with -5V peak, 2µs pulse width and 10 s pulse interval; (b) 5 identical gate pulses with - 5V peak, 50µs pulse width and 10 s pulse interval; (c) 10 identical pulses with -6V peak, 10µs width and 10s interval; (d) 10 identical pulses with -6V peak, 10µs width and 2s interval. 65 Figure 4. 11 (a) PSC when applied with a series of 200 identical negative and 200 identical positive pulses, 100µs width, 1s period. (b) PSC of 4000 cycles of switching between high conductance state and low conductance status. (c) Measured and fitted PSC after 100 pieces of potentiation pulse (-5V, 100µs width, 500ms period ) and 100 pieces of depression pulse (5V, 100µs width, 1s period). (d) 10 cycles of PSC current, where same condition as (a) was applied for each cycle. Working as the computing note in neural network for neuromorphic computing, the active status number, endurance, variability, and stability are all seen as crucial parameters for synaptic devices. Fig 4.11 (a) is showing the PSC tuning range with a series of 200 identical negative pulses (-5V, 100µs width, 1s period), followed by a series of 200 identical positive pulses (-5V, 100µs width, 1s period). Due to the screening effect and the finite charge trapping states can be accessed, the PSC of InP synaptic transistor trends to saturate at large pulse number. The nonlinear conductance tunning behavior may not be desired for implementation in cross bar structure to facilitate the matrix multiplication operation, it can be utilized in probability neural network or Hopfield neural 66 network. Fig 4.11 (b) shows the two distinct conductance status when 4000 cycles of switching pulses are applied (one +5V pulse followed by one -5V pulse with 0 V baseline). The non-overlap and stable conductance value are indicating excellent endurance of the device. And the LTM retention time after 100 pieces depression or potentiation pulse train were measured and plotted in Fig 4.11 (c). The retention time is greater than 10 5 sec, matching with the relaxation time model discussed before. In Fig 4.11 (d), 10 cycles of representative PSCs when applied with a series of identical pulses are shown, which is suggesting good stability across all the cycles. 4.4 Summary In this chapter, we demonstrate that a wide range of synaptic behaviors including elasticity, potentiation, depression, metaplasitcity, spiking-number dependent plasticity, spiking-timing dependent plasticity, short-term memory, long-term memory, and memory consolidation can either be mimic by traditional InP FETs or by InP FETs with modified gate dielectric structure. When combined with LT-TLP material integration approach introduced in Chapter 2 and 3, it enable the new avenue for directly integrating synaptic devices or even more complicated III-V based circuits to the Si back-end process. 67 Chapter 5. Optical Synapse by FG-PFETs for Machine Vision 5.1 Introduction In Chapter 4, it is demonstrated that InP FETs can mimic the biological synapses and work as a computational element in spiking neural networks. However, with the advantage of outstanding optoelectronic properties at visible wavelength spectrum, InP based FET hasn’t fully unleash its potentials. In this chapter, we explore the properties and performance of InP floating-gate phototransistor (PFETs) working as optical synapses. The following content are largely based on the peer-reviewed papers. 81 5.2 Floating-gate PFETs The FG-PFETs were directly integrated on Si/SiO2 wafer using a similar device architecture as discussed in chapter 4. The cost effective TLP approach (discussed in chapter 2) removed the requirement for single crystalline substrate, and enabled the monolithic InP integration directly on amorphous substrate even at low growth temperature. As shown by the schematic in Fig 5.1 (a), the heterogeneous structured dielectric stack composed of 5 nm Al2O3, 5 nm TiO2, and 50 nm Al2O3 were deposited by atomic layer deposition (ALD) at 200℃, it enabled the devices with both static and time dependent programmable conductance in a wide temporal scale of 10 -3 to 10 5 s. This dielectric stack is similar with Oxide-Nitride-Oxide (ONO) structure used in industry. 82 And the indium tin oxide (ITO) was deposited as the gate electrode to enable the interaction between InP channels and optical stimulations, due to its wide bandgap (3.5- 4.3 eV) and the high transmission in the visible light spectrum. 68 The synaptic behavior under electrical and optical stimulation was investigated by exposing the gate terminal to programming voltage pulses (Vprog), while maintaining the source drain bias, Vds = 0.4V, and illuminating the device with wavelengths of 655, 532, and 445 nm. The post-synaptic currents (PSCs) are measured when light is incident on the channel area. The synaptic potentiation and depression of the device under illuminations are shown in Fig 5.1(b) and Fig 51(c). For this measurement, the optical signal with 0.3 mW/cm 2 power density was kept on during the measurement, and a single 10 ms long -5V/+4V Vprog pulse was applied. Independent of the illumination condition, the PSCs showed modulated conductance of the channels up to 50s after the Vprog pulse, suggesting the number of trapped or detrapped carriers in the heterogeneous dielectric structure sustained more than 50s. Notably, the segregated PSCs resulting from the wavelength of irradiations is expected due to the wavelength dependent absorption coefficient for the thin InP channels. 69 Figure 5. 1 Schematic and post-synaptic current of FG-PFETs. (a) Schematic of FG-PFETs and the cross-section film stack. (b) PSCs with one -5V Vprog pulse in dark, and illumination of three wavelengths (𝜆 =655,532,𝑎𝑛𝑑 445 𝑛𝑚). (c) PSCs with one +4V Vprog pulse in dark, illumination of three wavelengths (𝜆 =655,532,𝑎𝑛𝑑 445 𝑛𝑚). Unlike the floating-gate photo synapses that rely on the injection of carriers into the floating-gate via optical pulses 83 , the responsivity of FG-PFETs can be directly programmed by electrical spikes, which potentially enables fast and energy efficient image recognition. To demonstrate this property, electrical and optical stimuli are split in temporal space as shown in the upper panel of Fig 5.2(a). Twenty -5V Vprog pulses were applied to the gate of the FG-PFETs and followed by a 10s optical pulse with 20s interval time. As indicated by the bottom graph in Fig 5.2(a). The FG-PFETs demonstrated good overall responsivity of 55.6 A/W. The responsivity was calculated by measuring the PSC under the dark and light and then subtracting the values. The relationships between responsivity and Vprog pulse number and amplitude are extracted and shown in Fig 5.2(b) to (e). Clearly, the responsivities of the FG-PFETs can be tuned up by the increased number of - 5V Vprog pulses, and can be tuned down with +5V amplitude. Here we argue that the charge trapping in the dielectric gate modifies the transconductance of the channel at a fixed gate bias, thus modifying the photogating effect. Additionally, photoexcitation of the channel provides additional carries which may be trapped in the dielectric/at the interface. Therefore, the responsivities demonstrated saturation behavior in Fig 5.2(b) and (c) with increased pulse number. It is observed that the responsivity changes more dramatically when the pulse number is small (<20), and then begins to saturate when the pulse number is larger than 20. The behavior versus programming pulse voltage does not show any saturation, as shown in Fig 5.2(d) and (e), as the increase Vprog amplitude enables a greater density of carriers to be trapped or detrapped from the charge-trapping dielectric. For each measurement, pre-conditioning electrical stimuli were applied 70 to reset the FG-PFEs to ground states. Here, the wavelength-related segregation was also observed and generally matches the trends observed in Fig 5.1(b) and (c). Here we argue that the tunable responsivity in FG-PFETs is attributed to the combination of charger trapping in the heterostructured gate dielectric and the photogating mechanism of the InP channel region. As discussed in Chapter 4, a TiO2 layer in an Al2O3 “cladding layer” provides a potential well, and allows long-term carrier trapping. The total trapped charge in the TiO2 layer is modified by the Vprog pulses applied to the gate, modifying the threshold voltage as shown in Fig 5.3(a). Photoconductive gain is widely observed in the low-dimensional semiconductor-based photoconductors 84 . The equation 𝐺 = 𝜏 𝜏 ' Q (𝜏 is the minority carrier lifetime, 𝜏 ' is the carrier transit time) is commonly used to estimate the gain. Another way is using 𝐺 = (𝐼 7: /𝑒)/(𝑃𝐴∙ 𝜂/ℎ𝜈), where 𝑃 is the incident power density, ℎ𝜈 is the incident photon energy, 𝐴 is the irradiated area, and 𝜂 is the quantum efficiency defined as the product of light absorption efficiency and charge transfer efficiency 84, 85 . Taking the measured results from the FG-PFETs shown in Fig 5.2(a) and assumed 𝜂~ 45.1% into the equation resulted in a photoconductive gain 𝐺~230. Conventionally, photoconductive gain originated from the distinct mobility of electrons and holes. The net photocurrent ∆𝐼 =Δ𝜎𝐴 * ; =𝑞[∆𝑛∙𝜇 < +∆𝑝∙𝜇 = ]𝐴 * ; , where ∆𝑛 and ∆𝑝 are the excess electron and hole concentrations, 𝜇 < and 𝜇 = are the electron and hole mobilities, 𝐴 is the semiconductor channel cross-section area, 𝑙 is the channel length, and 𝑉 is the bias provided. Consider the low-level injection, then the excess electron or hole (∆𝑛 = ∆𝑝) concentration can be described by 𝜕∆𝑛 𝜕𝑡 Q =𝑔(𝑡)− ∆𝑛 𝜏 < Q , where 𝑔(𝑡) is the net optical generation rate, and 𝜏 < is the 71 excess electron lifetime. If 𝑔(𝑡) is independent of time, and at 𝜕∆𝑛 𝜕𝑡 Q =0 state, then ∆𝑛 =𝑔𝜏 < . With additional assumption: 𝜇 < ≫𝜇 = , and transit time of electrons 𝜏 ' = ; > - = ; . ? - * , it yields: ∆𝐼 ≅𝑞𝜇 < 𝑔𝜏 < 𝐴 * ; =𝑞𝑔𝑙𝐴 @ - @ $ , and the term @ - @ $ is in the same photoconductive gain expression for 𝐺 . It can be understood that with incident light, electron-hole pairs are generated and separated by the applied bias. A fraction of the electrons and holes recombine immediately, and a fraction move in the opposite direction due to the electric field. However, if the transit time for an electron is shorter than the excess minority carrier lifetime, when excess electrons reach the anode, the same amount of electrons enter the photoconductor from the cathode to maintain the charge neutrality until the electrons recombine with the holes. Figure 5. 2 Programmable responsivities of FG-PFETs. (a) PSCs with 20 pieces of -5V Vprog pulse and ~10s light pulse (𝜆 =655 𝑛𝑚) 20s after the Vprog. (b)-(e) The relationship of responsivities of FG-PFETs extracted from (b) increased number of potentiation Vprog pulses, (c) increased number of depression Vprog pulses, (d) decreased amplitude of Vprog in the negative region, and (e) increased amplitude of Vprog in the positive region. 72 As for the photogating effect, although the equation of gain 𝐺 = 𝜏 𝜏 ' Q is identical, it describes the phenomenon that one type of the photogenerated carriers (holes in our case) is trapped in localized states, and work as a local gate voltage that influences the channel conductance. These states in the FG-PFETs may come from the inhomogeneous potential caused by defects and interfacial trap states. The relationship between the photocurrent and the local gate voltage can be written as: ∆𝐼 = AB /0 A* ! ∆𝑉 C =𝑔 D ∆𝑉 C . For the FG-PFETs in this work, when plotting the measured gate voltage- dependent photocurrent and transconductance with the same range shown by Fig 5.3(b), the photocurrent under 655nm illumination closely followed the transconductance trajectory during the Vg sweep from -2V to 6V. It suggests that photogating effect is the dominant mechanism in the devices. Figure 5. 3 The mechanisms behind the FG-PFETs. (a) Ids-Vgs sweep before and after applying 20 +7V and -7V Vprog pulses. (b) Dependency of Iph to Vgs with 655 nm irradiation and transconductance swept at the same range. (c) Band diagram corresponding to the three working regions in (b). 73 For the better understanding, we can divide the gate voltage-dependent photocurrent into three regions, and the corresponding band diagram are demonstrated in Fig 5.3(c). When the negative gate voltage is applied to the device, Fermi level is close to mid-gap. The trap states above the Fermi level can capture electrons, and the states with energies below the Fermi level are able to capture holes. At this condition, the numbers of trap states for electrons and holes are close to each other, which results in a similar number of both kinds of carriers and small photocurrent (region I in Fig 5.3(c)). With the increased Vg, the Fermi level move closer to the conduction band causes the increase of the electrons in the channel region, therefore, more electron trap states are occupied. On the other side, the decreased number of holes causes most hole traps to be accessible. In this condition, more photogenerated holes are trapped than photogenerated electrons and it causes the strong photogating effect manifested by the higher photocurrent with increased Vg as show in region II in Fig 5.3(c). However, when the Vg increases to a higher value (region III), due to the finite number of hole traps and decreased carrier transport efficiency because of the higher metal- semiconductor barrier, photocurrent reaches its maximum point and starts to drop. In short, due to the modulation of the number of available trap states for carriers and the carrier transport efficiency, the responsivity of the device demonstrates strong dependency of Vg. This also explained why the Vprog pulse number and amplitude can program the responsivity with the heterogeneous gate dielectrics structure in the devices. The variation for programming the responsivity of the FG-PFETs was examined by circulating positive and negative Vprog pulses. Twenty +6V Vprog pulses were applied first to the gate electrode with 0.4V bias between the source and the drain, and 655 nm laser with power density 0.3 mW/cm 2 74 was irradiated to the channel region 20s after the last piece of Vprog pulse. The duration of the illumination is 10s. After 30s, twenty -6V Vprog pulses were applied to the gate with the same Vds and illumination. This measurement was looped 20 times and the results are shown in Fig 5.4(a). Two distinct responsivity levels, high responsivity state (HRS) around 50 A/W, and low responsivity state (LRS) around 9.8 A/W are demonstrated. The variations for both states are low, and their distribution are fit using a Gaussian distribution as illustrated in Fig 5.4(c) and (d). This results in the mean (𝜇) and standard deviation (𝜎) to be 𝜇 :36 =50.39, 𝜎 :36 =3.33 and 𝜇 836 = 9.83, 𝜎 :36 =1.39, respectively. The values here were also used for estimate noise in the neural network simulation discussed in the later section. Figure 5. 4 Variation and duration of programmed responsivity. (a) Responsivities of FG-PFETs when circulating +6V Vprog pulse train and -6V Vprog pulse train. (b) Responsivities of FG- PFETs extracted from 2, 5, and 8s after illuminating the light pulse, and their dependencies to interval time between Vprog and irradiation. (c) and (d) Histogram of HRS and LRS, and their Gaussian distribution fitting curve. To work as a programmable photosensor and carry out image processing offline, the programmed responsivities in the FG-PFETs need to persist till the input images are illuminated on the device 75 array. In Fig 5.4 (b), the responsivities are extracted when the interval time between the last piece of Vprog pulse and illumination was varied from 2 to 100s. The preconditioning and Vprog pulse train (20 pieces of +6 V Vprog pulses with 20s resting time, then followed by 20 pieces of -7V Vprog pulses) were applied to the devices, and 𝑡 !<'EF>G; (= 2, 5, 10, 20, 50, 100s) after the last pulse, a 655 nm laser is irradiated for 10s. The responsivities were sampled at 2, 5, and 8s after the rising edge of the synaptic current caused by illumination. As shown in Fig 5.4(b), the responsivities measured 100s after the Vprog slightly dropped to 87%-93% of their value measured at 2s after the Vprog. And the sampling timing only causes a 7% difference in the worst case (at 𝑡 !<'EF>G; = 10s). 5.3 ONN Constructed from FG-PFETs for colorful image recognition Human beings can distinguish colorful objects or disentangle the overlayed colorful images without much effort. This task can be finished as well using sensor arrays built by InP-based FG- PFETs. The optical neural network (ONN) constructed by FG-PFETs was simulated as shown in Fig 5.5 The MNIST dataset 86 was modified to generate input images for the ONN. As the examples in Fig 5.5(a), 1500 handwritten number “7” and “1” images were picked out and stacked into red (R), green (G), and blue (B) channels, and generated 6 classes of input images (R7G1, R7B1, G7R1, G7B1, B7G1, and B7R1). The ONN was developed with the simple two-layer structure as indicated in Fig 5.5(b). The input layer contained 784 neuron arrays with color-filtering function to mimic the biological cone cells of human vision system, this step can be implemented by directly illuminating the colorful images to the 28×28 pixel array consists of 28×28×6 FG-PFETs and color filters. As shown in Fig 5.5(c), in each pixel, the input signal is separated by red, green, and blue filters, then sensed and processed by 6 FG-PFETs at the same pixel position. The synaptic connections between the input layer and output layer are corresponding to the responsivity values of the 784×6 FG-PFETs. Each output node is fully connected to one of the subpixels. 76 Consequently, when the colorful image is directly irradiated to the FG-PFETs array, the sensing process and Kirchhoff’s law conducted the matrix multiplication 𝑃∙𝑅 =𝐼. After subtracting the dark current, the results can be processed by the SoftMax activation function: 𝜙 D (𝐼)= 𝑒 B 1 H ∑ 𝑒 B 2 H I J-. h where 𝜉 is a scaling factor, and cross-entropy 𝐿𝑜𝑠𝑠 = − . I ∑ 𝑦 D log [𝜙 D (𝐼)] I D-. is used to calculate the loss from the output 𝜙 D (𝐼) and the label 𝑦 D . 77 Figure 5. 5ONN built with FG-PFETs. (a) Examples of stacked MNIST digits, working as the color-mixed input images to the ONN. (b) Schematic of the ONN built with FG-PFETs. (c) Schematic of pixel array, and pixel with color filters. (d) Circuit diagram of first 3 pixels, each pixel contain 6 FG-PFETs and three color filters. The circuit diagram of the first three pixels is shown in Fig 5.5(d). The other 781 pixels and corresponding output current that will merge with them are not shown here. At each pixel position, 6 FG-PFETs with 3 color filters sense and process the different wavelength signals and output 6 current values. Each current node measures the sum of 784 current values from each pixel due to parallel connection, then the current values will be processed by the SoftMax activation function in the software. Here the gate voltage Vnm, where n is pixel number, m is sub-pixel number, is 0 V for reading operation, and Vprogram during the programming operation. This circuit is different with the crossbar array since the three-terminal devices are used, and the voltage values applied to the crossbar array typically carry the input information through parameters like amplitude, frequency, and duty cycles. For each training and testing epoch, 1200 training images and 300 test images were shuffled, and the backpropagation and gradient descent approaches were implemented to know the tuning direction for the responsivity of each FG-PFET. The initial responsivities of the devices are randomly generated between the Rmax and Rmin with uniform distribution. We implemented the stepped updating rule based on the fitting curves of the measured responsivities dependency to Vprog pulse number 87 . More specifically the rules are: When 𝑑(𝐿𝑜𝑠𝑠) 𝑑𝑅 Q >0:𝑅 <K. = 𝑅 < +∆𝑅 = = 𝑅 < + 𝛼 = 𝑒 /L " & - 3& 14- & 1#5 3& 14- When 𝑑(𝐿𝑜𝑠𝑠) 𝑑𝑅 Q =0: 𝑅 <K. = 𝑅 < When 𝑑(𝐿𝑜𝑠𝑠) 𝑑𝑅 Q <0: 𝑅 <K. = 𝑅 < +∆𝑅 N = 𝑅 < − 𝛼 N 𝑒 /L 6 & 1#5 3& - & 1#5 3& 14- 78 Where 𝑅 <K. is the target updating responsivity, 𝑅 < is the current responsivity, 𝛼 = and 𝛼 N are the fitting factors from the potentiation and depression curve, 𝛽 = and 𝛽 N are the non-linear factors, 𝑅 DGO and 𝑅 D!< are the turning range of the responsivities. When the 𝑅 <K. is out of the range between 𝑅 DGO and 𝑅 D!< , clipping is applied during the value updating. In addition, the updating noise based on the measured results and gaussian distribution fitting curve in Fig 5.4(a) was included for the simulation. The resulted accuracy and loss over 40 training and testing epochs are shown in Fig 5.6(a) and (b), plotted with projected results from the devices having lower updating noise. Clearly, within 10 training epochs, the accuracy can reach up to ~94%, and the loss drops rapidly even for the devices with the highest update noise. However, after 10 epochs, lower update noise led to higher accuracy and more stable performance. This is due to the update noise contributing more to the overall number of available states and effect of small weight updates 88 . Overall, the simulation results based on the measured performance of FG- PFETs suggest that the ONN constructed by FG-PFETs can be developed for color-mixed handwritten digits recognition, and the accuracy can be further improved by lowering the responsivity updating noise. 79 Figure 5. 6 (a) Accuracy and (b) loss of the simulated ONN over 40 epochs of training and testing. 5.4 Summary In this chapter, top-gated FG-PFETs based on single crystalline InP channels grown by the TLP approach were reported. A floating gate is shown to modify the responsivity of the device by tuning the photogating effect, and enabling programming of the responsivities of the FG-PFETs. Using this behavior, the FG-PFETs was shown to perform the sensing and classification simultaneously when working as the computing element in an ONN. The constructed ONN shows a steep decline of loss and the image recognition accuracy ramp-up to ~94% during training and testing epochs. 80 Chapter 6. Conclusion and outlook 6.1 Conclusion In this dissertation, we started from single-zone HT-TLP approach to integrate a large area of single-crystalline InP and InAs on the amorphous substrate and then moved to the dual-zone LT- TLP growth approach. It not only removed the requirement for expensive single crystalline substrates, but avoid the potential damage caused by high process temperature. The integrated InAs demonstrated the highest electron mobility at room temperature among the non-epitaxially grown semiconductors on amorphous substrates. In addition to the amorphous substrates, the TLP approach allows us to integrate monolithic III- Vs on Si substrates as well. With a III-V buffer layer epitaxially grown by MOCVD, the doped and undoped InP mesas with aligned crystal orientation were successfully integrated on Si substrate. From the cross-section TEM and STEM images, various defects like APBs, SFs, and TDs originating from the lattice mismatch were barely observed in the TLP grown InP layer. To understand it better, a sub-critical dewetting area assisted defect filtering mechanism is proposed. Meanwhile, the doping source stacked on top of In template before TLP growth can dope the template and not increase the defect densities. This approach enabled a platform for a wide range of III-Vs and II-VIs monolithic integration on Si, and provided another pathway to filter out the defects during the heteroepitaxy instead of complicated ARTs, SLSs, or thick grading layer structures. 81 Built on the high quality III-Vs can be synthesized by TLP approach, InP FETs were integrated on Si/SiO2 substrates and can work as artificial neural synapses. A variety of synaptic behaviors like elasticity, potentiation, depression, metaplasticity, spiking-number dependent plasticity, and spiking-timing dependent plasticity can be mimicked by the trapping states at the InP and Al2O3 interfaces. With this knowledge, a heterogeneous dielectric stack (as a floating gate structure) was engineered to enable carrier trapping in a longer time scale. It broadened the conductivity tunning range, improved the device endurance, and prolonged the retention time. More importantly, the sequential data related short-time memory, long-time memory, and the complicated memory consolidation behavior were also emulated by the devices with this structure. To leverage the optoelectronic property of our III-Vs based devices, the control gate metal was switched to ITO. This allowed the visible light signal directly interact with the InP channel in InP FG-PFETs, which can sense and process the signal simultaneously. This behavior fits well with the crossbar structure that can simplify the time complexity of matrix and vector multiplication to constant time. A two-layered simple optical neural network was constructed and simulated based on the InP FG-PFETs performance. The responsivities of InP FG-PFETs were trained and stored at the sensor level, thus the sensor array itself can conduct image sensing and analog computation. The color-mixed MNIST handwritten digits were used to train and test the ONN, and ~94% accuracy was achieved within 40 training and testing epochs. 82 6.2 Outlook With the material synthesis approach discussed in chapter 2 and 3, many optical elements like photodetectors, laser diodes, and resonators can be designed and integrated on amorphous or Si substrates. By the time when this thesis was written up, many batches of devices with the vertical p-i-n structure were explored to achieve high performance photodetectors. The main difficulty that blocked the pathway was the proper isolation layer between the top and bottom electrodes. The leakage pathway through the sidewall of film stacks needs to be further investigated and eliminated. Meanwhile, a lateral structured device can be taken into consideration to avoid a similar issue. In chapter 3, the MOCVD buffer layer still used high-temperature process which didn’t fulfil the temperature requirement for back-end compatibility. If a low temperature (near 400℃) MOCVD nucleation steps can be engineered to have a relatively smooth layer on top of Si, then the high- temperature growth step is not necessary, which can enable this pathway also fully BEOL compatible. For the InP synaptic devices, the performance and results discussed in this thesis are device level, but not system level. It caused difficulty and inaccuracy for estimate the system energy consumption for the actual neural network built with these elements. Additionally, a test platform with peripheral circuits like ADC, DAC, sense amplifier, and switch controls can be helpful to evaluate the higher-level device array performance when handling more complicated jobs. 83 Last but not least, many solid-state devices were proposed to mimic the dynamic behavior of neurons. Potentially a hardware neural network coupled with the artificial synapses and artificial neurons can be interesting to implement event-driven spiking neural network and handle the sequential data. This can be a good starting point for hardware long short-term memory (LSTM) model in the recurrent neural network, which is powerful in natural language processing and machine vision. 84 References (1) Zidan, M. A.; Strachan, J. P.; Lu, W. D. The future of electronics based on memristive systems. Nature Electronics 2018, 1 (1), 22-29, Review. DOI: 10.1038/s41928-017-0006-8. Vashi, S.; Ram, J.; Modi, J.; Verma, S.; Prakash, C.; Ieee. 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Abstract (if available)

Abstract The exponential increase of connected devices by the internet is requiring more powerful computing units to process and store the unexpected volume of data. Difficulties from device scaling, large power consumption, heating issue, and von Neumann bottleneck motivated researchers to study and mimic our brain to explore more efficient computing structures. Neuromorphic computing, pioneered by Carver Mead provided a vast avenue for emerging electronic devices to contribute to the next generations of computation processors. Competitive candidates such as metal-oxide random access memory (RRAM), ferroelectric field effective transistor (FeFET), phase change memory (PCM), spin transfer torque magnetic random access memory (STT-MRAM), and devices built on 2D materials have been demonstrated from different research groups. The III-V semiconductor based neuromorphic devices also demonstrated ultrafast resistance switching speed and outstanding light response, however, their developments are limited due to the concern in the high-cost epitaxial integration process and challenges in CMOS backend compatibility.
In this dissertation, we successfully remove the constraints from back-end-of-line compatibility by a low temperature – templated liquid phase (LT-TLP) approach and demonstrate single crystalline III-V semiconductors like InP and InAs can be directly integrated on the amorphous substrate. With this technique, the highest room-temperature electron mobilities among materials from the non-epitaxially growth approach were demonstrated from LT-TLP grown InAs, which can increase further with a smoother surface.
The templated liquid phase (TLP) approach can enable heterogeneous integration of III-Vs on Si substrate as well, with a III-V layer epitaxially grown on Si substrate. By this approach, the III-Vs mesas from TLP growth not only demonstrated unified crystal orientations but showed an extensive decrease in defect density. Importantly, the approach allows a variety of compound semiconductors (III-Vs and II-VIs) monolithically integrated on Si substrates without complex defect filtering techniques.
Integrated by the BEOL compatible approach, InP-based FETs were designed and engineered to mimic a variety of synaptic behaviors, including elasticity, potentiation, depression, metaplasticity, spiking-number dependent plasticity, and spiking-timing dependent plasticity. This allowed the InP FETs to work as a computing element for spiking neural networks. To handle the sequential information better, heterogenous gate dielectric layers were utilized to construct InP floating-gate FETs. This structure significantly increased the dynamic weight tuning range, improved device endurance, and prolonged retention time. Even more complicated behavior like memory consolidation can be emulated as well.
The capability of in-sensor computing was shown in the floating-gate phototransistor (FG-PFETs) built with TLP grown InP. Programmable and high responsivity to the visible wavelengths allowed the InP FG-PFETs to sense and process the light signal simultaneously. The simulated optical neural network constructed from the performance of these devices achieved ~94% accuracy for mixed-color image recognition.

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Asset Metadata

Creator Tao, Jun (author)

Core Title III-V semiconductor heterogeneous integration platform and devices for neuromorphic computing

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Degree Conferral Date 2022-08

Publication Date 07/23/2022

Defense Date 06/06/2022

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag III-V semiconductors,neuromorphic computing,OAI-PMH Harvest,synaptic devices

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Kapadia, Rehan (committee chair), Ravichandran, Jayakanth (committee member), Yang, Joshua (committee member)

Creator Email juntao@usc.edu,juntao0528@gmail.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-oUC111375424

Unique identifier UC111375424

Legacy Identifier etd-TaoJun-10938

Document Type Dissertation

Format application/pdf (imt)

Rights Tao, Jun

Type texts

Source 20220728-usctheses-batch-962 (batch), University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

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Repository Name University of Southern California Digital Library

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