University of Southern California Dissertations and Theses

Design and implementation of frequency channelized ultra-wide-band (UWB) transceivers

(USC Thesis Other)

Design and implementation of frequency channelized ultra-wide-band (UWB) transceivers

PDF

Download a page range

Download transcript

Copy asset link

Request this asset

Transcript (if available)

Content DESIGN AND IMPLEMENTATION OF FREQUENCY CHANNELIZED
ULTRA-WIDE-BAND (UWB) TRANSCEIVERS
by
Ali Medi
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
August 2007
Copyright 2007 Ali Medi
ii
Epigraph
"Although my senses were searching the desert fatiguelessly; discovering nothing
although finding a lot; my soul was illuminated by a thousand suns; but could never ever
touch the perfection of a single atom."
Ali Ibn Sina (980-1037 AD)
iii
Dedication
This dissertation is dedicated to my mother and father
for their support and encouragement throughout my life.
I also want to dedicate this to the memory of my grandfather,
who emphasized the importance of education. He instilled in me
the inspiration to set high goals and confidence to achieve them.
iv
Acknowledgements
I would like to express my sincere gratitude to Professor Won Namgoong for his
invaluable support and guidance throughout the course of this work.
I am most grateful to the members of my committee, Professor John Jr. Choma,
Professor Eun Sok Kim, Professor K. Sandeep Gupta and Professor Peter A. Beerel for
their time, encouragement, and expertise all through this project.
Special thanks to Professor Robert A. Scholtz, Professor John O’Brien, Professor
Hossein Hashemi and the UltRa Lab staff for allowing me to use their labs and
equipments. Thanks are due to Professor Vasilias Maremrelis and Professor Ramez
Shehada for teaching me precious lessons while I was researching at Alfred Mann
Institute. I extend many thanks to Dr. Hooman Darabi and Mohammad Nariman for what
they thought me during my rather lengthy internship at Broadcom Corporation.
I would like to thank many people in the Sharif University of Technology for teaching
me the fundamentals and giving me the confidence that I needed. Sincere thanks goes to
Professor Homayoun Hashemi, Professor Forouhar Farzaneh and Professor Shahrokh
Ghaemmaghami for being my role models. Special thanks goes to Professors Jahanbeglo,
Fotowat-Ahmadi, Alavi, Jahed, Vosoghi-Vahdat, Nayebi, Sadooghi, Shamsollahi and
Etemady. I also wish to thank my colleagues at the Sharif Electronic Research Center, Mr.
Sheikhaei, Golmohammadi and Milani.
Most importantly, none of this would have been possible without the love and patience
of my family. They have been a constant source of love, encouragement, concern,
support and strength throughout this endeavor. I would like to express my heart-felt
gratitude to my family.
v
Table of Contents
Epigraph ii
Dedication iii
Acknowledgements iv
List of Tables vii
List of Figures viii
Abbreviations xi
Abstract xiii
CHAPTER I. INTRODUCTION 1
CHAPTER II. FREQUNCY CHANNELIZED RECEIVER 6
A. Concept 6
B. Architecture 12
C. LNA Design 16
D. Down-Conversion 20
E. Baseband Amplification and Filtering 22
F. Analog-to-Digital Conversion and Storage 27
G. Digital Signal Processing of Channelized Signals 29
CHAPTER III. UWB TRANSMITTER 31
A. Architecture 31
B. Circuit Design 34
CHAPTER IV. MULTI-OUTPUT FREQUNCY SYNTHESIZER 38
A. Architecture 38
B. Quadrature VCO and VCO Buffer 40
C. Single-Sideband Mixers 46
D. Frequency Dividers & Loop Components 50
CHAPTER V. EMBEDDED MEMORY 52
A. Architecture 52
B. Memory Cell 54
C. Memory Control Logic 55
D. Memory Clocking and Data 56
E. Memory Write Cycle 57
F. Memory Read Cycle 58
G. Digital and Analog Isolation 59
vi
CHAPTER VI. CONTROL AND TEST CIRCUITRY 61
A. Digital Programmability 62
B. LNA Test Buffer 65
C. VCO Buffer 67
D. Divider Chain Test Output 68
E. Baseband Amplifier/Filter Test Structure 69
F. Baseband Outputs 70
CHAPTER VII. MEASUREMENT RESULTS 71
A. Input Matching 72
B. Low Noise Amplifier Gain 74
C. Signal Path Transfer Function 76
D. Noise Figure 77
E. Linearity 81
F. VCO Phase Noise 85
G. SSB Mixer Spurs 87
H. Transmitter Performance 89
I. Error Vector Magnitude (EVM) 93
J. Interference Effect 94
K. Summary and Comparison 96
CHAPTER VIII. CONCLUSION 99
References 100
Alphabetized Bibliography 105
vii
List of Tables
Table I: Simulated Spur Levels at the Output of SSB Mixers 48
Table II: Measured Spur Levels at the Output of SSB Mixers 87
Table III: Measurement Results of the Receiver Blocks 96
Table IV: UWB Transceiver Comparison 98
viii
List of Figures
Figure 1: UWB Spectrum Mask 3
Figure 2: Ideal Frequency Channelized Receiver 8
Figure 3: Proposed Frequency Channelized Architecture 10
Figure 4: Example of Digital Section of the Receiver 11
Figure 5: Receiver Architecture 14
Figure 6: Wideband Low Noise Amplifier 17
Figure 7: Second Stage LNA 18
Figure 8: LNA Layout Photo 19
Figure 9: Signal-Path Mixer 21
Figure 10: Baseband Amplifier Stage 23
Figure 11: Baseband Amplifiers Layout Photo 25
Figure 12: Differential Sampler 28
Figure 13: Transmitter Pre-Driver 34
Figure 14: Transmitter Core 35
Figure 15: Transmitter Layout Photo 36
Figure 16: Multi-Output Frequency Synthesizer 39
Figure 17: Quadrature VCO 41
Figure 18: Quadrature Error – Phase Noise Tradeoff 43
Figure 19: VCO & VCO Buffer Layout 44
Figure 20: Single-Sideband (SSB) Mixer 47
Figure 21: Layout of Single-Sideband Mixers 49
Figure 22: Analog Differential Flip-Flop 50
ix
Figure 23: Memory Architecture 53
Figure 24: 1-Bit Memory Cell Section 54
Figure 25: Column Select Logic 55
Figure 26: Memory Structure in Read-Mode 58
Figure 27: Memory/Analog Isolation Structure 59
Figure 28: Memory/Analog Isolation Side-View 60
Figure 29: Single Bit Programming Section 63
Figure 30: Controllable Current Block 64
Figure 31: Controllable Voltage Block 64
Figure 32: LNA Test Buffer 65
Figure 33: LNA Test Buffer Layout 66
Figure 34: VCO Buffer with Auxiliary Input (I-Channel) 67
Figure 35: Divider Chain Test Point 68
Figure 36: Typical Test-points of a Baseband Subband 70
Figure 37: Chip Micrograph 71
Figure 38: Low Noise Amplifier Test Structure 72
Figure 39: Measure Input Matching (S11) 73
Figure 40: Measured LNA Gains 74
Figure 41: Channel Transfer Functions 76
Figure 42: Direct Conversion Receiver 78
Figure 43: Measured Receiver Noise Figure 80
Figure 44: Input 1-dB Compression Point 81
Figure 45: Third Order Intermodulation in Direct Conversion Receivers 82
Figure 46: Extrapolation of the Input Third-Order Intermodulation 82
x
Figure 47: Measured Receiver Signal Path P
1dB
and IIP3 84
Figure 48: Measured Phase Noise 86
Figure 49: Measure Time-Domain Transmit Pulses 90
Figure 50: Transmitter Output Spectrum (Fixed Data) 91
Figure 51: Transmitter Output Spectrum (Pseudo-Random Data) 91
Figure 52: Transmitter Filtered Output Spectrum 92
Figure 53: Measurement Setup in the Presence of Interferes 94
Figure 54: Measured SNR in the Presence of Interferers 95
xi
Abbreviations
UWB Ultra Wideband
UWB-IR Ultra Wideband – Impulse Radio
CMOS Complementary Metal Oxide Semiconductor
TX Transmitter
RX Receiver
EVM Error Vector Magnitude
dB Decibel
dBm Decibel-Milliwatt
RF Radio Frequency
ISM band Industrial Scientific and Medical band
IIP3 Input Referred Third Order Intercept Point
Gbps Giga Bit Per Second
Mbps Mega Bit Per Second
USB Universal Serial Bus
SNR Signal to Noise Ratio
ADC Analog to Digital Converter
OFDM Orthogonal Frequency Division Multiplexing
FCC Federal Communication Commission
U-NII band Unlicensed National Information Infrastructure band
IEEE Institute of Electrical and Electronics Engineers
WPAN Wireless Personal Area Network
xii
WLAN Wireless Local Ares Network
MB-OFDM Multi Band Orthogonal Frequency Division Multiplexing
MBOA Multi Band Alliance
MMSE Minimum Mean Squared Error
LO Local Oscillator
HFB Hybrid Filter Bank
WiMax Worldwide Interoperability for Microwave Access
DNW Deep N-Well
LNA Low Noise Amplifier
BPF Bandpass Filter
LPF Lowpass Filter
AGC Automatic Gain Control
PLL Phase Locked Loop
SSB Single Side Band
VCO Voltage Controlled Oscillator
RFIC Radio Frequency Integrated Circuit
xiii
Abstract
A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25 - 4.75 GHz
band designed for low power high data rate communication is implemented in 0.18 μm
CMOS technology. Operating at 1 Gbps data rate, it dissipates 98 mW (98 pJ/b) in the
receive-mode and 108 mW (108 pJ/b) in the transmit-mode from a 1.8-V supply while
achieving a combined TX/RX EVM of -32 dB. The combination of the frequency
channelized architecture, high-linearity RF circuits, aggressive baseband filtering and low
local oscillator spurs results in an interference-tolerant receiver, having the ability to co-
exits with systems operating in the 2.4 GHz and 5 GHz ISM bands as well as systems in
its unlicensed band of operation of the receiver. The receiver provides maximum gain of
82 dB, overall noise figure in the range of 4.5 - 5.4 dB, IIP3 of -5 to -10 dBm, and 47 dB
channel to channel isolation. The receiver suffers a performance degradation of less than
3 dB in EVM in the presence of in-band and out-of-band interferers as large as -20 dBm
and 0 dBm, respectively. The mostly digital transmitter delivers output swing of 800
mVpp to a 50-ohm antenna at rates as high as 1.5 Gbps.
1
CHAPTER I. INTRODUCTION
The last decade has witnesses a tremendous growth in wireless technologies. As
highly integrated radios become cheaper, short-range communication systems with
ranges of up to 10 meters are becoming popular in replacing cables and in enabling
new consumer applications. UWB has emerged as one of the most promising
wireless systems lately, its main foreseen application being very high data rate short
range communication, and low data rate coupled to localization, targeting both low
cost and low power implementations.
The prospect of wireless data transmission at rates of hundreds of mega bit-per-
second (Mbps) has ignited the interest of consumer electronics in UWB systems.
Examples of possible applications include wireless USB, high definition video
streaming and home networking. The narrowband systems have, however, a limited
data rate, typically about 1 Mbps, which is insufficient for the applications
mentioned above.
The signal bandwidth of the ultra-wideband (UWB) radio is at least an order of
magnitude wider than in existing narrowband radios. This intrinsically wide signal
bandwidth enables UWB systems to efficiently achieve very high data rates (e.g., 1
Gbps). Instead of employing a high order modulation with low symbol rate as in
narrowband systems, Shannon channel capacity suggests that higher data rates are
more efficiently afforded in an UWB system, where the symbol rate is raised while
using low-order modulation. As Shannon channel capacity shows a linear relation
2
with bandwidth and only a logarithmic relation with signal to noise ratio (SNR), a
higher bandwidth is preferred over a larger SNR for increasing the data rate.
Moreover, the need for simultaneous operation of many of these systems in the same
environment requires low transmit power levels. Thus, power amplifiers are not
needed and the design of the T/R switches is simplified.
The intrinsically wide signal bandwidth of UWB radio enables systems to
efficiently achieve data rates in excess of 1 Gbps. However, the wide signal
bandwidth coupled with the need to support the large in-band interferers that are
inevitably present in the unlicensed UWB band (e.g., 3 – 5 GHz) pose several
implementation challenges. Primary among them is the need for an extremely high
sampling rate and dynamic range ADCs. The wide bandwidth and high dynamic
range requirements of the ADC have led UWB systems to be scaled down to operate
at a greatly reduced bandwidth, compromising the benefits of the UWB radio (e.g.,
Multiband OFDM Alliance proposal [1]).
Ultra-wideband (UWB) radio systems are defined as those with a 10 dB bandwidth
that exceed 20 % of the center frequency or with a total bandwidth of more than 500
MHz. The benefits of using the UWB radio are derived from its large bandwidth.
Increasing the data rate by expanding the bandwidth is generally much more efficient
than by resorting to higher order modulation schemes with sophisticated error control
coding. In addition, its wide bandwidth provides the UWB signals with significant
multipath diversity, resulting in greater robustness to fading.
3
Figure 1: UWB Spectrum Mask
The Federal Communication Commission (FCC) has recently approved the 3.1
GHz – 10.6 GHz band for UWB deployment (Figure 1). Because the ISM and U-NII
bands (5.15 GHz – 5.85 GHz in the United States and 4.9 GHz – 5.1 GHz in Japan)
lie right in the middle of the allocated spectrum, the UWB spectrum can be broken
into two distinct and orthogonal bands that are free of ISM and UNII-band
interferers: 3.1 GHz – 4.8 GHz and 6.0 GHz – 10.6 GHz. We subsequently refer to
these two bands as the lower and upper UWB bands, respectively. Since operating at
lower frequencies generally relaxes the implementation requirements, the initial
1.99
3.1 10.6
0.96 1.61
GPS
Band
4
deployment of the UWB systems will most likely use the lower UWB band. Thus,
the proposed transceiver is designed to operate in this band.
UWB is now becoming an industrial standard in the 3.1 – 10.6 GHz frequency
range under IEEE 802.15.3a (WPAN). At present, both direct-sequence impulse
communication and multi-band orthogonal frequency division multiplexing (MB-
OFDM) UWB systems are under consideration for this standard. The multi-band
OFDM alliance (MBOA) proposal divides the spectrum into 14 channels (bands)
with spacing of 528 MHz, while impulse radio communication covers the whole
bandwidth. Therefore, the latter potentially provides higher rates although it has to
coexist with other systems occupying the band of operation continuously. The
receiver should also be tolerant to in-band interferences as well as out-of-band
interferences, to allow co-existence with systems operating in its unlicensed band
and systems operating in adjacent bands such as WLAN in the 2.4 GHz ISM band
(IEEE 802.11 b/g), Bluetooth in the 2.4 GHz ISM band and WLAN in the 5 GHz
ISM band (e.g. IEEE 802.11a).
To achieve a low-cost solution suitable for consumer market, a highly integrated
transceiver architecture is required, with minimal number of external components.
Due to the large signal bandwidth, direct conversion is the most promising
architecture for the UWB radio and consequently the local oscillator (LO) needs to
provide quadrature signals at the center frequency.
In this dissertation, we describe a fully integrated frequency channelized UWB
transceiver that dissipates very low energy per bit compared to the existing solutions
5
while remaining robust to interferers. In Chapter II, the frequency channelized
receiver will be discussed. In Chapter III, we will discuss the mostly digital
transmitter in detail, while Chapter IV describes the multi-output frequency
synthesizer. Chapter V and VI deals with the design of the embedded memory,
control and test circuitry. Measurement results as well as comparison are presented
in the Chapter VII and Chapter VIII concludes this dissertation.
6
CHAPTER II. FREQUNCY CHANNELIZED RECEIVER
A. Concept
Although great headway has recently been made in efficient implementation of
narrowband radios, the UWB signal has fundamentally different signal
characteristics, making the use of existing receiver circuits and architectures ill
suited. Compared to existing narrowband radios, the signal bandwidth of the UWB
radio is at least an order of magnitude greater. Furthermore, the UWB radio must
coexist with many other narrowband systems operating in the same band or its close
proximity. Consequently, a UWB radio has intrinsically different sensitivity,
selectivity, and bandwidth requirements, which imply radio circuit and architectural
designs that are also substantially different.
There are numerous implementation challenges in the UWB radio. Chief among
them is the extremely high-sampling and large dynamic range requirements of the
analog-to-digital converter (ADC). Other design challenges include wideband
amplification and the generation of narrow pulses at the transmitter. Frequency
channelization technique relaxes the ADC requirements in the UWB radio.
The bandwidth and dynamic range requirements of the ADC appear to have led to
two alternative development paths. In the first, the UWB system is scaled down to
operate at a greatly reduced bandwidth, compromising the benefits of the UWB radio.
An example of such system is the time-frequency interleaved OFDM radio proposed
in the IEEE 802.15 WPAN standard. In the other development path, receiver
functions such as correlation are preformed in the analog domain before digitizing at
7
a much reduced sampling frequency [2]. Such analog receivers are less flexible and
suffer from circuit mismatches and other non-idealities. These circuit deficiencies
limit the number of analog correlators that can be practically realized on an
integrated circuit. Since many correlators are required to exploit the diversity
available in an UWB system, analog receivers do not perform well. These circuit
non-idealities also preclude the use of sophisticated narrowband interference
suppression techniques, which can greatly improve the receiver performance in
environments with large narrowband interferers such as in UWB systems.
To achieve high reception performance, therefore, the UWB signal needs to be
digitized at the signal Nyquist rate of several gigahertz, so that all of the receiver
functions are preformed digitally. In addition, as digital circuits become faster and
denser with constant scaling of CMOS technology, simplifying the analog circuits as
much as possible and distributing as much of the analog operation to the digital
domain should prove more beneficial.
Since designing a single ADC to operate the signal Nyquist rate with reasonable
power budget is not practical, parallel ADC architectures with each ADC operating
at a fraction of the effective sampling frequency need to be employed. To sample at a
fraction of the effective sampling frequency, the received UWB signal can be
channelized either in the time or frequency domain. An approach that has been used
in high-speed digital sampling oscilloscopes is to employ an array of M ADCs each
triggered successively at 1/M the effective sampling rate of the parallel ADC. A
fundamental problem with an actual implementation of such time-interleaved
8
architecture is that each ADC sees the full bandwidth of the input signal. This causes
great difficulty in the design of the sample/hold circuitry. Furthermore, in the
presence of strong narrowband interferers, each ADC requires an impractically large
dynamic range to resolve the signal from the narrowband interferers.
Instead of channelizing by the time-interleaving, the received signal can be
channelized into multiple frequency subbands with an ADC in each subband
operating at a fraction of the sampling frequency. A filter band view of the frequency
channelized ADC is shown in Figure 2. A band-limited analog input signal is split
into M subband signals using M bandpass filters. The resulting signals are sampled
at f
S
/ M, where f
S
is the effective sampling frequency, and digitized using M ADCs.
Signal reconstruction is achieved by up-sampling (expanding) the digitized samples
by a factor of M, passing through discrete synthesis filters and then summing [3].
Figure 2: Ideal Frequency Channelized Receiver
9
In the absence of narrowband interferers, the performance of the time-interleaved
and frequency channelized receivers are nearly identical. However, when finite
resolution ADCs are employed in the presence of large narrowband interferers, the
frequency channelized receiver significantly outperforms the time-interleaved
receiver. As shown in [3], for example, an SNR difference of approximately 20 dB is
observed when 4-bit ADCs are used compared to the time-interleaved receiver
assuming minimum mean-squared error (MMSE) detectors are employed.
This large performance difference arises because the frequency channelization
process better isolates the effects of the narrowband interferer by raising the
quantization noise floor mostly in the subband containing the interferers. Since
significant interference noise is already present in these subbands, the additional
quantization noise does not greatly increase the total noise power relative to the
signal power. By contrast, a narrowband interferer in the time-interleaved receiver
increases the quantization noise floor across the entire signal spectrum. Thus, even in
frequencies with no interference, the quantization noise floor is significantly raised
relative to the signal power, resulting in large overall performance degradation. The
ability to isolate the narrowband interferer significantly improves the performance of
the frequency channelized receiver compared to the time-interleaved receiver,
especially when low resolution ADCs are employed.
Instead of using bandpass filters with high center frequencies, channelization can
be achieved using a bank of M mixers operating at equally spaced frequencies and M
lowpass filters to decompose the analog input signal into M subbands. In addition to
10
obviating the need to design high frequency bandpass filters, channelizing the
received signal using this approach greatly relaxes the design requirements of the
sample/hold circuitry. The sample/hold circuitry in this architecture sees only the
bandwidth of the subband signal; whereas in the bandpass channelization approach,
the sample/hold circuitry sees the uppermost frequency in the high subbands.
Consequently, the required sampling aperture, which is the amount of the time
required for the sampler to capture the input value, is much more relaxed in the
proposed channelization approach as shown in Figure 3.
Baseband Amp./
Multi-order LPF
0 250
f
(MHz)
f f
(GHz)
3.5 4.5 4
Digital
Signal
Process.
Sampler
@ f
S
/M
Sampler
@ f
S
/M
Sampler
@ f
S
/M
WBLNA
f
(GHz)
3.25 4.75
Analog
Domain
Digital
Domain
Figure 3: Proposed Frequency Channelized Architecture
In the frequency channelized receiver, signal detection can be achieved by first
reconstructing the channelized signal then processing the sampled full-band signal as
in the conventional receivers. Design of perfect reconstruction or approximately
perfect reconstruction hybrid filter banks (HFB) have been explored [4, 5]. A
potential problem with this approach is that designing the digital synthesis filters
11
requires accurate knowledge of the transfer functions of the analog signal path,
which may be unavailable in practice because of the variations resulting from
temperature and fabrication process uncertainties.
Unlike existing HFBs that attempt to perfectly reconstruct the received signal, the
objective of the proposed receiver is to optimally estimate the transmitted signal for
data detection (Figure 4). The synthesis filters, therefore, are designed to perform
minimum mean-squared error (MMSE) estimates of the transmitted signal in the
presence of additive noise, narrowband interferences, and aliasing from sampling. A
novel approach for designing such synthesis filters and quantifying the resulting
performance can be found in [3, 6]. The distortion caused by the propagation channel
and the analog signal path can be compensated by employing adaptive synthesis
filters to recover the transmitted signals.
1
1
N

Figure 4: Example of Digital Section of the Receiver
12
B. Architecture
Robust UWB communication requires that a device can receive data from a
transmitter, which is at a certain distance, in the presence of in-band interferers such
as WiMax and nearby interferers such as 802.11a/b/g WLAN. The desired UWB
signal at 10 meters away will be received at a power level of -73 dBm. In the
presence of narrowband interferers, the victim receiver may see WiMax, 2.4 GHz
ISM and 5 GHz ISM blockers that are 17 dB, 67 dB and 47 dB larger than the
desired signal, respectively. This co-existence constraints the design of the receiver
signal path in numerous ways, such as maximum gain of the LNA, linearity of the
front-end, dynamic range of the analog-to-digital converters (ADCs) and the spectral
purity of the local oscillator signals. As it is explained in [7], UWB receivers require
minimum IIP3 of -9 dBm to operate in the presence of the interferers. In addition, it
is suggested that the phase noise of the LOs have to be less than -100 dBc/Hz to
ensure less than 0.1 dB degradation in SNR.
Recovering the weak UWB received signal that might be buried in large
interferences requires highly linear front end followed by multi-gigahertz high
dynamic range ADCs. In order to avoid the need for such high complexity ADCs
that would dissipate very large power (few watts), alternative approaches such as
time-interleaved or frequency channelized receivers can be employed. Using time-
interleaved approach the clock rate of the ADC will be reduced while the dynamic
range requirement would still be the same, while frequency channelized technique is
able to relax both of those requirements. In a frequency channelized receiver each
13
ADC has to sample only a portion of the desired signal bandwidth which is less
probable to contain a large interference signal. In contrast to conventional receivers,
in the presence of very large interferes only a portion of the signal bandwidth will be
compromised, leaving a good chance for the data to be recovered.
In order to break the input signal into subbands, a bank of band-pass filters (BPFs)
is needed, however, realization of these band-pass filters at such a high frequency
with good selectivity on-chip is not possible. Passive integrated filters suffer from
large area and low selectivity due to the limited Q of the inductors, while active
integrated filters are too noisy, power hungry and hard to design at few gigahertz. In
theory a BPF is a transformed version of a low-pass filter (LPF) in the frequency
domain, which can be realized by a down-conversion followed by a LPF and an up-
conversion. In the proposed UWB receiver, the up-conversion after the low-pass
filter is moved to the digital domain to simplify the analog part of the design and
digitization. Thus, after the low-pass filter, signal is converted to digital and the rest
will be done using digital signal processing techniques.
In this dissertation, we propose an UWB receiver that efficiently digitizes a 1 Gbps
BPSK UWB signal (3.25 – 4.75 GHz) while remaining robust to in-band/out-of-band
interferers. To relax the ADC requirements, the received signal is channelized into
three frequency subbands using a bank of mixers and lowpass filters before
digitization as shown in Figure 5. As the overlapping subband signals provide
sufficient statistics, the samples can then be efficiently processed digitally to achieve
the performance of an ideal full-band receiver as explained before.
14
Figure 5: Receiver Architecture
The channelized receiver is more robust to both in-band and out-of-band interferers
compared to a full-band receiver. Compared to a full-band receiver, the reduced
baseband signal bandwidth of the channelized receiver provides greater attenuation
of out-of-band interferers for the same filter order. Because of the reduced filter
corner frequency (i.e., -3dB bandwidth), the ratio of the interferer frequency after
mixing to the filter corner frequency is increased in the channelized receiver. Since
the filter attenuation depends logarithmically on the corner frequency, this increased
ratio suggests that greater attenuation of out-of-band interferer is possible for the
same filter order in the proposed receiver. The channelized receiver is also less
sensitive to in-band interferers, since their effects can be mostly isolated to a single
subband while retaining the signal information of the remaining two subbands. The
isolation enables the use of significantly fewer ADC bits for each channel compared
to a conventional full-band receiver with comparable performance [3]. This reduced
15
ADC bit requirements in the frequency channelized receiver greatly minimizes the
receiver power consumption, since ADC consumes most of the receiver power in the
wideband digital receivers and its power dissipation is to the first order exponentially
related to the number of bits.
Proposed receiver architecture consists of a low noise amplifier followed by a set
of mixers selecting different subbands of the input signal. Low power nature of the
received UWB signal necessitates some amplification before mixers, thus a two
stage LNA is being used in order to amplify the signal and suppress the noise of the
mixers. The second stage of the LNA is composed of three tuned amplifiers each
tuned at different frequencies to provide some selectivity before the mixers as well as
preventing LO leakage to adjacent subbands. Baseband amplifiers and low-pass
filters are used to increase the amplitude of the signal and reject the unwanted parts
of the band which have been down-converted. Generally, baseband amplification and
filtering are done separately, however, in this design since the bandwidth of the
baseband signal is wide, the role off of the amplifying stages is used to accomplish
the filtering task. This will save a considerable amount of power and area from the
design. In the proposed design 1-bit ADCs have been used to reduce complexity and
power dissipation of the receiver.
16
C. LNA Design
One of the major challenges in designing wideband communication systems is to
design a wideband LNA. Since LNA is the first active element in the receive chain,
in order to decrease the overall noise figure of the whole receiver, LNA must feature
reasonable gain and minimum noise figure (NF) possible. Moreover, it should
provide wideband input matching to a 50-ohm antenna for noise optimization as well
as filtering of out-of-band interferers, good linearity, and low power consumption.
Also, a well-designed LNA omits the need for the off-chip matching networks that
are costly and degrade the overall noise performance of the receiver.
Traditionally, wideband LNA designs relied on bipolar junction transistors or high
electron-mobility transistor technologies, because of their superior noise
performance. In recent years one of the major goals was to achieve a fully integrated
transceiver and since most of the digital part of the designs was in CMOS, most of
the designers started to use the BiCMOS process [7, 8]. The high cost of BiCMOS
process drives a tendency toward fully integrated CMOS transceivers. However,
because of low transconductance of CMOS transistors and their high gate resistance,
CMOS LNAs suffer from low gain and high noise figure compared to the other
competing technologies for the same power consumption.
The designed LNA for this receiver is composed of two stages; the first stage is a
wideband differential inductive-degenerated cascode stage that provides more than 8
dB amplification across the band. Cascode configuration improves the stability and
eases the input matching, while the degeneration inductor enhances the noise
17
performance [9]. The fully integrated wideband LNA topology is shown in Figure 6.
To avoid the use of off-chip matching components, the input of the wideband LNA is
matched to 50-ohm resistance by taking into account the effect of the pad capacitance
(~300 fF) and the bonding wire inductance variations (2 – 3 nH). The LNA is designed
differentially in order to reject noise traveling in the substrate as well as the supply
noise.
Figure 6: Wideband Low Noise Amplifier
The wideband LNA is followed by three cascode tuned amplifiers tuned at 3.5
GHz, 4 GHz and 4.5 GHz to provide additional 15 dB amplification and prevent LO
leakage to adjacent subbands. The main purpose of the second stage LNA is to boost
the gain of the LNA and further suppress the noise of the following stages. The gain
of the second stage LNA is digitally controllable, which can be used to flatten the
18
overall LNA gain in the absence of interferers and to attenuate the channel
containing large interferers. The cascode configuration of the second stage LNA
isolates the input and output, which helps improve isolation between subbands as
well as LO leakage suppression. Figure 7 shows the topology of the second stage
LNA.
Figure 7: Second Stage LNA
Transistors used in the design of the LNA are all placed in a deep-nwell (DNW) to
isolate them from the noise traveling through the substrate. Dummy transistors and
similar layouts have been used to lower any mismatch caused by layout and stress
effects. The whole LNA is surrounded by a grounded guard ring to isolate the high
frequency section from other blocks.
19
Size of the wideband LNA and second stage LNA stages makes the placement of
these blocks critical. The differential output of the wideband LNA has to be fed to
the differential input of all second stage LNA sections, while the difference in the
length of the two differential signals is minimized to avoid any loss. Figure 8 shows
the placement of the LNA blocks. The output of the wideband LNA is AC-coupled
to the input of the second stage LNA. In order to avoid over-loading the wideband
LNA with the capacitive load caused by the large input capacitance of the second
stage LNA stages and the long connection between these two blocks, AC-coupling
capacitor is chosen to somewhat isolate the large load from the wideband LNA. This
causes some attenuation due to the capacitive divider effect between the AC-
coupling capacitor and the load, which is accounted for in the design process and
measurements. Performance verification and output tunings have been done
considering layout parasitics in post-layout simulations.
Figure 8: LNA Layout Photo
20
D. Down-Conversion
The channelization of the input spectrum is mainly done by down-conversion to
baseband and filtering using a set of lowpass filters (LPFs). To ensure no loss of
information, the content of each channel is down-converted using a set of quadrature
LO signals, which are generated simultaneously by the frequency synthesizer. This
part of the receiver can also be viewed as three simultaneous direct-conversion
receivers.
The goal in the design of the mixers is to achieve good linearity and low noise
figure while dissipating small amount of power. The linearity of the mixer is the
limiting factor in the channel to channel isolation, and therefore interference
tolerance of the whole receiver. The noise figure of the mixer is also important,
although it would be suppressed by the amplification achieved in the LNA to some
extent. Thus, the noise figure of the mixer has to be reasonably low.
Down-conversion of the desired frequency bands has been done using six AC-
coupled double-balanced Gilbert cell mixers to three complex baseband subbands.
Double-balanced mixers have been used to improve the conversion gain and to avoid
RF/LO leakages to the output of the mixer, as the RF signal can contain very large
interferers. Presence of these large interferers at the output of the mixer can cause
gain suppression and un-intended intermodulation terms. The linearity of the mixers
has been further improved by using resistive loads and low conversion gain.
Performance of the mixers is optimized by sizing and biasing the transconductance
21
and switching transistors properly. Figure 9 shows an example of the signal-path
mixers.
Mixers are laid out carefully and symmetrically to avoid any asymmetry between
the two sides of the double balanced mixer as well as mismatches in the quadrature
LO input loadings and connections. This will further suppress the LO/RF leakage
and improves the IQ matching of the synthesizer outputs. The mixer down-
converting contents of each subband is placed across from its second stage LNA as
shown in Figure 8. The quadrature baseband outputs of the mixers are fed into the
baseband amplifier through an AC-coupling, which removes offset voltages caused
by local oscillator (LO) self mixing of the mixer and its low frequency flicker noise.
LOp
LOn
RFp
LOp
LOn
RFn
Figure 9: Signal-Path Mixer
22
E. Baseband Amplification and Filtering
Additional channelization is achieved using 250MHz fifth-order lowpass filters
(LPFs). A sharper filter better isolates the effects of strong in-band/out-of-band
interferers, further relaxing the ADC quantization requirements. In narrowband
systems, the amplification and filtering are being done separately by employing a
multi-order filter followed by a high-gain narrowband baseband amplifier. However,
in wideband systems design of each one of these two blocks is challenging if not
impossible within reasonable power budget. Multi-order active filters require
amplifiers with bandwidth many times bigger than the signal bandwidth, which
would be well into gigahertz range in wideband systems and are power consuming.
Passive lossless multi-order filters occupy large area, which is more of an issue in
channelized receivers that need many baseband filters for different subbands. High-
gain baseband amplifiers covering wide bandwidth require very high gain-bandwidth
product, which is generally limited by the process, parasitics and the power budget.
In this design, the inherent poles of the amplifying stages are used to perform
filtering. Baseband amplifier/filter is composed of five identical amplification stages,
which provide a roll-off sharper than 100 dB/dec to suppress the potentially large
interferes present in the adjacent subbands. Baseband stages are composed of an AC-
coupled linear common-source stage followed by a source-follower as shown in
Figure 10. Common-source differential pairs provide the amplification needed, while
the source follower sets the bandwidth of each stage. The pole of the common-source
stages is at very high frequency due to the low gain achieved in each stage (small R)
23
and buffering of the load provided by the source follower (small C). The pole at the
output of the source follower sets the bandwidth of each stage, which is equal to the
transconductance of the source-follower divided by its load. The load of the source-
follower is composed of the input capacitance of the common-source, the
capacitance due to the Miller effect, source-follower parasitics and bottom plate
capacitance of the AC-coupling capacitor. Transconductance of the source-follower
is designed to be small to lower its power dissipation. This causes some minor
attenuation, which has been accounted for in the overall design.
Outp
Inn
Outn
Inp
I
Buf
I
Buf
I
CS

Figure 10: Baseband Amplifier Stage
Thus, variable current of the common-source stage and source-follower stage are
used to control the gain and the bandwidth of each one of the stages, respectively.
Changing the current of the common-source varies its transconductance and
24
therefore effects the gain, while the current of the source follower control its
transconductance and consequently the bandwidth. Low gain resistive loaded gain-
stages have been used to provide the required linearity and dynamic range. The
bandwidth of the AC-coupling is designed such that it removes the low-frequency
DC offset caused by the mismatches and reduces the flicker noise, with a small
sacrifice of information bandwidth. Baseband amplifier gain and bandwidth can be
controlled digitally between 0 – 60 dB and 150 – 350 MHz respectively.
Digitally controllable gain and bandwidth can be employed to compensate the
process variations as well as active equalization. Amplification stages are designed
such that their power dissipation is proportional to their gain-bandwidth product.
Thus, reduction in the gain of the subbands containing large interferers in order to
reduce leakage of the blockers to other subbands and supply noise results in saving
power. An extra baseband amplifier path is also fabricated along with the receiver to
calibrate baseband amplifier/filter bandwidth and gain.
In the baseband approach used here, the baseband signal is being filtered as it gets
amplified. Although the use of single-bit samplers diminishes the need for automatic
gain control (AGC), but saturation of the amplifying stages should be prevented to
assure proper filtering. Thus, depending on the power of the input signal and the
interferers coming with it, different amplification schemes can be used. In the case
that the signal is weak and interferes are either at large offset frequencies or weak,
the gain of the early stages can be increased to lower the overall noise figure of the
baseband amplifier, this causes the linearity of the amplifier to degrade. In the case
25
that the incoming signal is accompanied with large interferers, lower gain in earlier
stages prevents the saturation of the amplifier and improves its linearity, while the
overall noise figure is degraded. The optimum gain and bandwidth setting of the
baseband stages has to be set by the digital back-end after processing the received
signal.
Figure 11: Baseband Amplifiers Layout Photo
Figure 11 shows the layout of the baseband amplifiers as it can be seen in section
of the chip micrograph. The I and Q baseband amplifier channels of each subband
are located next to each other. The baseband signals are coming to the amplifier from
the mixers located in the RF section (top) and the sampled outputs of the baseband
subbands goes to the memory (bottom) as well as off chip for measurements. Next to
each quadrature baseband amplifier the programming block used for biasing
26
generations and control signals is located. Between the baseband sections, RF and
baseband power supply by-pass capacitors have been laid out to suppress the supply
noise and coupling through the power supply. By-pass capacitors are composed of
MOS capacitors covered with fringe capacitors to increase the density of the
capacitance as well as helping to pass the metal density rules imposed by the
manufacturer.
27
F. Analog-to-Digital Conversion and Storage
Frequency channelization relaxes the required dynamic range and reduces the
bandwidth of each subband, which results in smaller number of bits and lower
sampling rate needed for digitization. After channelization each one of the outputs of
the baseband amplifier are band-limited signals with bandwidth of 250 MHz, thus
the Nyquist sampling rate required is 500 MHz. In this prototype, the I and Q
channels of each subband are sampled using over-sampling 1-bit ADCs at 1 Gsps.
The channelized architecture of the receiver enables the use of 1-bit ADCs, which is
the main source power reduction in the design. Over-sampling of the signal prevents
aliasing errors and improves the performance of the samplers. A 1-bit ADC with
sampling rate that is twice the Nyquist rate, is equivalent to an ADC that has 1.5-bit
and operates at the Nyquist rate. Comparator outputs are stored in an embedded
memory, so that the required signal processing can be performed off-chip.
Figure 12 shows the differential samplers used in this design. Differential samplers
have been used to properly load the baseband amplifier and reduce the generated
switching noise by the samplers. The digital outputs of the samplers are both
buffered, but only one of them has been used eventually. The sampler is composed
of a differential amplifier with cross-coupled complementary load that is only
operational when the clock is high. During the time that clock is low, internal nodes
are properly shorted to avoid any imbalance in the operating points. At the rising
edge of the clock, the input data forces the output to go to either one or zero based on
its input value. The sampling clock is provided from off-chip to increase the
28
flexibility and testability of the design. Clock signal along with the output signals of
the samplers are buffered and fed into the embedded memory as it is explained in
more detail in Chapters V and VI.
Clk
Clk
Clk
Inp
Clk
Outp
Inn
Clk
Outn
Figure 12: Differential Sampler
29
G. Digital Signal Processing of Channelized Signals
After digitizing the channelized signals, the objective is to equalize the distortions
caused by the propagation channel and to detect the transmitted signal. An obvious
approach is to reconstruct the channelized signal and then perform conventional
equalization and detection. However, reconstructing the received signal is difficult,
since the distortions caused by the channelization process may not be exactly known
due to uncertainties in process and temperature variations. Instead, by equalizing the
channelized signal directly, the adaptive equalizer can compensate jointly for
distortions caused by the frequency channelized receiver and the propagation
channel [3, 6].
Although the channelized receiver can be used with any modulation scheme, the
proposed UWB radio employs single-carrier cyclic prefix (SC-CP) modulation. In
SC-CP system, a block of data symbols is transmitted with the last P symbols of each
block copied to the beginning to form cyclic prefix. The presence of cyclic prefix
enables efficient frequency domain equalization at the receiver. Frequency domain
equalization offers better performance-complexity tradeoff than time domain
equalization for channels with large amounts of multipath such as in UWB systems.
In addition, SC-CP modulation simplifies data collection for testing as it enables
block-by-block processing. The adaptive equalization algorithm that we employed to
test the proposed UWB system is based on the approach described in [3]. As the
details of this algorithm are beyond the scope of this dissertation, the algorithm is not
discussed further. The computational complexity of this algorithm, however, is
30
slightly higher than in a full-band receiver using conventional equalization and
detection. Thus, the power dissipation of the digital signal processing section would
be similar to the full-band case.
31
CHAPTER III. UWB TRANSMITTER
A. Architecture
The FCC restrictions for the UWB band that affect most high data rate
communication systems are the average emission mask with maximum of -41.3
dBm/MHz between 3.1 – 10.6 GHz and the minimum signal bandwidth requirement
of 500 MHz within this band. The bandwidth of a UWB signal is defined as the
difference between frequencies where the signal power is 10 dB below its maximum
level. More of a factor for low pulse repetition frequency (PRF) transmitters, the
peak power limit set by the FCC is 20log(RBW/50) dBm, where RBW is the
spectrum analyzer resolution bandwidth in megahertz.
Several pulse-based modulation schemes are found in literature such as pulse
amplitude modulation (PAM), on-off keying (OOK), pulse-position modulation
(PPM) or bit-position modulation (BPM), binary phase-shift keying (BPSK), and
transmitted reference. BPSK has an advantage over pulse amplitude and position
modulation due to an inherent 3 dB increase in separation between constellation
points. In the single-user case, TH-BPSK (time-hopping BPSK) and DS-BPSK
(direct-sequence BPSK) showed similar performance, while in the multi-user case
DS-BPSK outperformed time-hopping schemes.
UWB pulse generators have commonly been developed for radar applications so
far, but without integration constraint on a single chip. With the emergence of low
cost low power and high data rate applications, the development of system-on-chip
for this purpose becomes mandatory. Consequently, research is getting active for
32
achieving integration of such UWB pulse generators in single-chip CMOS
technology. Thus far the designed UWB pulse generators are either not fully
integrated, or can operate at very low data rates. Pulse based architectures can be
broadly grouped into two categories defining how the pulse energy is generated in
the 3.1 – 10.6 GHz UWB band.
The first category includes transmitters that generate a pulse at baseband and up-
convert it to a center frequency in the UWB band by mixing with a local oscillator
(LO). The transmitter may not have an explicit mixer that performs the up-
conversion mixing. This architecture is easiest identified by having an LO at the
center frequency of the pulse. The up-conversion generally offers more diversity and
control over the frequency spectrum, but at the cost of higher power since an LO
must operate at the pulse center frequency. In most cases also a power amplifier is
needed to amplify the up-converted signal.
Second category includes transmitters that generate a pulse that directly falls in the
UWB band without requiring frequency translation. The pulse width for these types
of transmitters is usually defined by the delay elements that may be tunable or fixed,
as opposed to oscillators. A baseband impulse may excite a filter that shapes the
pulse, or the pulse may be directly synthesized at RF with no additional filtering
required. Transmitter designed in this category can dissipate low power, as they can
be designed mostly digital and the power amplifier is not needed in most cases. The
transmitter discussed here fall into this category.
33
The proposed UWB transmitter is designed to convey information for high data
rate communication applications using BPSK modulation, by generating symmetric
complementary pulses. Transmitter digitally generates a very narrow current pulse
with very broad frequency contents. By converting this wideband current to voltage
using a low Q tank circuit, the UWB pulses are created. Tank circuit provides some
spectral shaping to fit the output spectrum in the UWB emission mask to some extent,
further spectral shaping has been done off-chip. The output of this transmitter is
differential and in order to connect it to a single ended antenna, an off-chip balun has
been used. The off-chip filtering and balun will be replaced by an on-chip
transformer in the future versions. Transmit data can be either provided from an off-
chip source or from a pseudo-random generator implemented on-chip. Transmitter is
capable of transmitting at arbitrary rates up to 1.5 Gbps.
In this transmitter the width of the narrow current pulse and therefore the
frequency content of the output pulse are controlled by the delay between
independent edges of two distinct signals. Thus, the relative delay between the two
edges can be controlled arbitrarily. This can be used to control the profile of the
pulse and compensate for the CMOS process variations.
34
B. Circuit Design
The UWB transmitter consists of three major blocks. Digital pre-driver (Figure 13)
is designed to generate appropriate signals for the transmitter core by gating the
clock based on the transmit data. Transmitter core is composed of two cascaded
switches which are generating the narrow current pulse followed by the current to
voltage conversion block. The current to voltage conversion consists of an on-chip
inductor, pad capacitance, bonding wire and 50-ohm off-chip termination or antenna.
The transmitter core is shown in Figure 14. Because of the digital nature of the
receiver, arbitrary clock rates can be used and the power dissipation of the
transmitter is directly proportional to the rate which the transmitter is operating.
Data
Clk
A
B
Data
Clk
C
D
Data
Clk
C
D
I
Out
V
Out
A
B
Figure 13: Transmitter Pre-Driver
35
The width of the current pulses generated in the transmitter core can be digitally
controlled by changing the delay between the independent edges of the two signals
generated in the pre-driver. Transmitter core is generating a current pulse, which its
width is equal to the difference between the rising edge of A (C) and the falling edge
of B (D). This difference is determined by the extra delay caused by the side load
capacitance on the path to B (D) in the pre-driver. The side load capacitance is
composed of a 3-bit binary weighted switched capacitors to control the width of the
current pulse. This programming capability can also be used for changing the output
amplitude as well as compensating for the process variations if necessary.
B
A
D
C
+- Out

Figure 14: Transmitter Core
To increase reliability and avoid oxide breakdown of the transistors in the
transmitter core, a third transistor is added to the stack of the transistors to isolate the
output node from the switching transistors. Using a differential output stage for the
36
transmitter, symmetric positive and negative pulses are generated. In order to convert
the differential output of the transmitter, an off-chip balun has been used, which can
be replaced by an on-chip transformer in later versions.
A multiplexer has been used on the data path of the transmitter to select to either
transmit the data generated in the pseudo-random generator or the external data. The
pseudo-random generator can generate 31-bit random sequences at rates as high as
1.5 Gbps. The pseudo-random generator is supplied with the transmitter clock. In the
mode that the external data input is selected as the input for the transmitter, the
pseudo-random generator goes to the reset mode and stops generating the random
sequence.
Figure 15: Transmitter Layout Photo
37
Figure 15 shows the layout of the transmitter. The transmitter is placed on the
corner of the transceiver and at the furthest distance from the input of the receiver to
avoid coupling of the two as much as possible. The whole transmitter has been
separated from the rest of the design by a set of guard rings to avoid any coupling to
the receiver. Separate supply pins has been used for the transmitter and its supply
node has been by-passed using a set of by-pass capacitors. The by-pass capacitors
are composed of MOS capacitors covered with multi-layers of fringe capacitors to
increase the density of the capacitor and therefore increase the capacitance for the
area used. A grid of multi-layer metals has been used to connect the transmitter core
to the supply and ground, as the core needs to be supplied with large amounts of
current at the switching instances. This decreases the resistance and inductance of
these nodes and increases their capacitance. The output nodes of the transmitter have
been connected to the pins using stacked metal layers to increase the current
capability of the output nodes, lower its series resistance and avoid electro-migration.
38
CHAPTER IV. MULTI-OUTPUT FREQUNCY SYNTHESIZER
A. Architecture
In contrast with conventional Homodyne receivers, that need one quadrature local
oscillator signal (LO), in channelized UWB receivers many quadrature LO signals
have to be generated simultaneously. To avoid large power dissipation of multi
channel receivers, it is important that the power dissipated for generation of each
additional LO to be low. In this design, since there are only three channels, three
quadrature LO signals have to be generated concurrently to decompose the received
signal into three subbands. Spectral purity is especially important in isolating the
effects of interferers, as it prevents folding of interferences into an interferer-free
subband.
Straightforward frequency synthesizer architecture would be to use three separate
phase locked loops (PLL) to generate these signals independently. This option has
not been pursued because of power and area considerations as well as the risk of
oscillator pulling. In contrast a direct frequency synthesis approach can be used to
avoid having multiple loops. Local oscillator frequencies are carefully planned to
avoid spurs at the frequencies of the large blockers and simplify the design. The
synthesizer is composed of an integer-N PLL operating at 4 GHz and a set of single-
sideband (SSB) mixers to generate the 3.5 GHz and 4.5GHz LO signals as shown in
Figure 16. Quadrature voltage-controlled oscillator (VCO) and quadrature single-
sideband (SSB) mixers have been used to accurately generate the I and Q LO signals.
39
In fully integrated phase-locked loops (PLLs), the VCO output frequency should
be tunable over a wide range of frequencies, covering the desired range of the
synthesizer output frequencies, for all processing variations and operating conditions.
A wide tuning range realized by boosting the control voltage gain of the VCO
(K
VCO
) has unwanted effect of increasing the phase noise at the output of the VCO,
and hence the PLL as well. Increased K
VCO
amplifies the effect of noise and spurs
present at the input of VCO. In this synthesizer, the wide tuning range is realized by
digitally controlled tuning of the VCO. The PLL is only required to pull the
oscillator output frequency to account for the digital quantization, temperature
variations and some margin. This allows the K
VCO
to be small which is helpful in
reduction of phase noise and spurious tones at the output of VCO [10].
Reference
Frequency
Quad.
VCO
VCO
Buffer
÷ 4
PFD CP
Loop
Filter
÷ 16
Quad.
SSB
Mixers
Quad.
4 GHz
Quad.
3.5 GHz
Quad.
4.5 GHz
Control Bits
7.8125 MHz
÷ 2
500 MHz 1 GHz 4 GHz
Sampling Clk
/TX Ref.
Figure 16: Multi-Output Frequency Synthesizer
40
B. Quadrature VCO and VCO Buffer
In direct synthesis frequency synthesizers, phase noise of all LO signals generated
are closely related to the noise performance of the main oscillator, while the spectral
purity of the output of the single-sideband mixers are effected by the accuracy of the
VCO quadrature. Thus, a set of low phase noise quadrature sinusoidal signals have to
be generated with low IQ mismatch, in the main VCO.
Many different architectures have been used to generate quadrature LO such as
poly-phase filter, balanced divide-by-two, and quadrature VCO. Poly-phase filters
suffer from inaccuracy of the passive components at high frequencies and large size
at low frequencies, also sufficient buffering has to be done to avoid loading the main
VCO and compensate for the loss presented by the lossy filter. In the divide-by-two
approach, VCO has to operate at twice the required frequency and the balanced
divide-by-two circuitry generates the quadrature signal while dividing the frequency
[8]. This approach suffers from high power dissipation, as the VCO and the divider
have to operate at twice the frequency and also the noise introduced by the divider
has to be minimized. The alternative approach would be to use quadrature VCOs.
The IQ matching of the output of the quadrature VCO is superior to the other
approaches, while it dissipates less power. Although the size of the quadrature VCO
is generally larger than the area used in other approaches due to extra inductor
needed, but it is more favorable in low power designs if the extra area can be
afforded.
41
Although the phase noise of the quadrature VCO is worse than stand-alone
oscillators dissipating the same power due to the fact that they operate off-resonance,
but the overall phase noise performance of the quadrature signal can be comparable
as there are no other extra noise sources in this approach (i.e. buffers, resistors,
transistors). In quadrature VCOs, two stand-alone VCOs are coupled together by
means of some extra circuitry, creating a global loop. The coupling between these
two oscillators effects the phase noise and the IQ accuracy of the output. At high
coupling factors the oscillators operating point moves further off-resonance, while
the IQ inaccuracy caused by the component mismatches is minimized.
Figure 17: Quadrature VCO
In this synthesizer, a differential quadrature VCO optimized for operation at 4 GHz
has been designed to accurately generate the I and Q signals with low phase noise.
The noise performance of the oscillator is improved by separating the tail transistors
42
of the cross-coupled section and the coupling section as well as lowering the
coupling current as show in Figure 17.
Coupling factor, which can be defined as either the ratio of the coupling current
(I
Coup
) and the cross-coupled current (I
Bias
) or the ratio of the transconductance of the
coupling transistors and the transconductance of the cross-coupled transistors,
directly effects the IQ mismatch and the phase noise of the VCO [11]. Lowering the
coupling factor minimizes the phase noise degradation due to the off-resonance
operation of the VCO, while it reduces its ability to suppress the effect of component
mismatches in the IQ matching. Advanced layout techniques have been used to
minimize the component mismatches and therefore lower the required coupling
factor. The VCO transistors and especially current sources are carefully laid out for
good matching considering the layout stress effects. Also large transistors have been
used in the current sources to lower their mismatches, as it is the primary source of
quadrature inaccuracies.
High coupling factor improves the quadrature accuracy, while it increases the
power dissipation and the phase noise as it can be seen in Figure 18. However in case
that the quadrature accuracy of the VCO is minimized, the mismatches and
inaccuracies of the other parts of the design such as mixers and dividers dominates
and diminishes the effect of the VCO in the overall IQ mismatch or image rejection
in the case of SSB mixers. Thus, the extra power that has been used in the VCO does
not bring any significant benefit to the quadrature accuracy of the whole receiver,
while it deteriorates the phase noise. In the designed VCO, low phase noise penalty
43
and sub-degree IQ accuracy have been achieved by using a coupling current that is
three times smaller than the current used in the cross-coupled section. Overall IQ
mismatches in the design has been improved by carefully designed symmetric layout
and loading on the quadrature nodes of the design.
0.01
0.1
1
10
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Coupling Factor (Ohm/Ohm)
Quadrature Error (Deg) '
0
2
4
6
8
10
12
14
16
Phase Noise Penatly (dB)
Phase Noise Penalty
Quadrature Error
Figure 18: Quadrature Error – Phase Noise Tradeoff
The separation of the tail transistors of the cross-coupled and coupling section adds
a degree of freedom to the design and improves the noise performance of the VCO
by increasing the impedance of the common-source nodes. To isolate the VCO from
the noise and spurs coupling in from other parts of the design through the biasing
circuitry, an RC LPF has been added at the gate of the tail transistors. In addition, a
switch is added in parallel with the resistor of the filter to decrease the time needed
to charge its capacitor and avoid startup problems. A 25% tuning range has been
44
achieved by a four-bit binary-weighted digitally controlled switched capacitor bank,
this allows a low control voltage gain (K
VCO
), which helps to reduce the spurious
tones as well as noise contribution of the loop components in the overall phase noise
of the PLL. The VCO is followed by a tuned cascode buffer to suppress the kick-
back noise of the frequency dividers and drive single-sideband mixers as well as
dividers. A set of switched capacitors has also been used to improve the tuning range
of the output of the VCO buffer and compensate for process variations and modeling
inaccuracies. VCO buffer is explained in more detail in Chapter VI.
Figure 19: VCO & VCO Buffer Layout
45
Figure 19 shows the layout of the quadrature VCO, its switched capacitor banks
and the quadrature VCO buffer. The VCO is placed away from the signal path of the
receiver and close to the pads. Having supply pads close to the VCO reduces the
series resistance and inductance of the supply node and therefore improves the phase
noise of the VCO. Since the VCO is very sensitive to both low frequency and high
frequency noises, the resistance of the supply node is as important as its inductance.
Low frequency noises and spurs leaking to the output node of the VCO will be up-
converted by the VCO to the frequency of the operation of the VCO, while the high
frequency disturbances can cause extra spurs. The supply node of the VCO is
properly by-passed using a set of by-pass capacitors. By-pass capacitors are
composed of MOS capacitors covered with layers of fringe capacitors to improve the
density of the capacitance. An extra pin has been dedicated to the bias point of VCO,
so that external by-passing capacitors can be used to further reduce the noise at the
gate of the tail transistor if needed, to avoid up-conversion of disturbances.
46
C. Single-Sideband Mixers
In order to generate quadrature LO signal, a set of two SSB mixers has been used
at each frequency. The spectral purity of the output of the SSB mixers can be
effected by the IQ mismatch of its two inputs and its linearity. To lower the IQ
mismatch of the inputs, quadrature VCO and carefully designed analog frequency
dividers have been employed. Linearity of SSB mixers is further enhanced by using
a resistive degeneration in its transconductance stage to lower spurs of its lower
frequency input (500 MHz). This suppression improves the channel isolation of the
receiver further. Figure 20 shows the topology of the one of the SSB mixers.
Degeneration resistor lowers the effective transconductance of the under-stage of the
mixer and therefore decreases the overall conversion gain. Therefore, to boost the
conversion gain the current of the mixers has to be increased; this increases the
power dissipation of the mixer to some extent.
The single-sideband (SSB) mixers used in the frequency synthesizer consists of
two double-balanced Gilbert multiplier-based mixer cores whose outputs are added
together as currents loaded by a tank circuit to suppress undesired spurs and increase
the output amplitude. In the under-stage of the mixers, the 500 MHz signals
generated by the dividers are converted into currents. Applying the lower frequency
to the transconductance stage of the mixers increases the overall conversion gain of
the mixer. Resistor degeneration is used here to obtain reasonable linearity in order
to suppress the spurs caused by the 500 MHz input. This suppression improves the
channel isolation of the receiver further. The output current of the under-stage, which
47
consists of a DC component and a signal component, is switched at the 4 GHz
frequency in the upper-stage of the mixer. The double-balanced mixer consists of
two single-balanced circuits that are connected anti-parallel for 4 GHz signal, thus
the 4 GHz parts of the signals are summed to zero.
4G_I+ 4G_I- 4G_I+
500M_I- 500M_I+
Other Half 4.5G_Q Output

Figure 20: Single-Sideband (SSB) Mixer
Table I discusses the size of the spurs before and after applying the local feedback
using the degeneration resistor. The spurs caused by the third order non-linearity of
the transconductance stage are suppressed due to the linearization achieve by the
local feedback. These two spurs are located at very critical frequencies and can cause
the large interferers at those frequencies (2.4 GHz / 5 GHz ISM bands) to down-
convert to the baseband and saturate the baseband amplifiers. The spurs caused by
48
the leakage of the 4 GHz LO and the image of the output (3.5 GHz) contribute to the
overall channel to channel isolation of the receiver. These two are of particular
importance, since they can cause the large interferer to leak from one channel to
other and corrupt the entire received signal. These spurs are suppressed by using
large transistors and carefully designed symmetric layout. The complete double
balanced architecture of the mixers increases the conversion gain of the mixer, while
it also helps suppressing the spurs caused by the second order nonlinearities and
input leakages. Chapter VII presents the measured power of the spurs and compares
the measured values with the simulation results seen below.
Table I: Simulated Spur Levels at the Output of SSB Mixers
Freq.
(GHz)
Source
Power (dBc)
Without R
Power (dBc)
With R
DC Self mixing Negligible Negligible
0.5 Leakage of low frequency input Negligible Negligible
2.5 3
rd
order non-linearity of g
m
block -20 -50
3 2
nd
order non-linearity of g
m
block Negligible Negligible
3.5 Input I/Q imbalance, mismatches -45 -45
4 Leakage of high frequency input -70 -70
4.5 Desired output 0 0
5 2
nd
order non-linearity of g
m
block Negligible Negligible
5.5 3
rd
order non-linearity of g
m
block -22 -50
7.5/8.5
2
nd
order non-linearity of switches
Negligible Negligible
49
Figure 21 shows the layout of the SSB mixers and their placement with respect to
the other blocks. The SSB mixers are placed between the VCO buffer and the RF
section. This configuration makes the distance between the SSB mixers and the
signal path mixers short, so that the maximum amount of LO power can be delivered
to the mixers with best IQ accuracy. The middle channel LO (4 GHz) which is
coming directly from the VCO buffer has a longer path. Due to the stronger drive of
the VCO buffer compared to the SSB mixers, some extra attenuation can be afforded
on this path. The I and Q channels of the SSB mixers are placed next to each other,
since they can share their inputs. AC-coupling filters seen on the bottom of the
picture are used to properly bias the switching inputs of the signal path mixers.
Figure 21: Layout of Single-Sideband Mixers
50
D. Frequency Dividers & Loop Components
A reference frequency of 7.8125 MHz has been chosen for the main PLL. This
allows a loop bandwidth of 500 kHz, thus suppressing the close-in phase noise of the
oscillator (VCO) and the spurs of the loop. As mentioned above a set of high
frequency analog dividers with good IQ matching has been used to provide
appropriate signals for the SSB mixers followed by a set of digital dividers to
generate the input to the phase frequency detector (PFD). Analog dividers are based
on resistive-loaded differential latches (Figure 22) driven by reversed clock phases
that create balanced outputs in quadrature at the divided frequency. Differential PFD
and charge pump (CP) has been used to lower the supply noise. The delay in the PFD
loop and the charge pump current are designed to be digitally programmable, so that
the parameters of the loop can be properly adjusted.
Figure 22: Analog Differential Flip-Flop
51
On-chip loop filter is also implemented to avoid having extra off-chip components.
The second order loop filter is composed of two sets of switched capacitors and a set
of switched resistors, so that the loop bandwidth can be controlled digitally. Loop
filter capacitors are composed of MOS capacitors, covered with multi layers of
fringe capacitors to decrease the area occupied by the loop filter. Narrow un-doped
poly resistors are used in the loop filter to further compact the size of the on-chip
loop filter. To increase the reliability of the design a pin has been assigned to the
control voltage of the VCO, this way external components can be added to the loop
filter if needed and the VCO control voltage can be forced to a fix value when it is
necessary.
52
CHAPTER V. EMBEDDED MEMORY
A. Architecture
Digital samples of the baseband subbands have been generated by the samplers at 1
Gsps rate. Since most digital analyzers are not capable of acquiring a signal at this
rate, a two-port memory block has been designed and embedded with the design. The
samples generated by the samplers will be stored in the embedded memory at the
rate that they are generated and it would be read by the logic analyzer externally at
the rate defined by the clock of the logic analyzer. The main constraint on the design
of this memory block is the switching noise generated by this block. Thus, a low
switching and low noise memory block has been designed. The embedded memory
works based on the last in first out (LIFO) structure.
Figure 23 show the overall architecture of the embedded memory used to store one
of the digital outputs of the receiver. The memory is composed of 12 rows of
memory cells, each row composes of 110 memory cells. Only one of the memory
rows is active at every given time to lower the switching noise generated. Row select
and column selects are basically a shift register that at most one of their outputs are
one at a given time. Input data is conditioned based on the row select signals and is
only active on the row that is performing storage. The size of the memory block is
around 3 mm by 250 μm. Thus, long lines have to be buffered accordingly and a
return path for the column select logic is designed to accurately emulate the column
select output. The return path for the column select logic provides clock to the row
select, so that the active row switches when storage in the current row is finished. In
53
the read-mode all of the memory cells are connected like a long shift register and the
data can be read at the output node of the memory while it is clocked out by the read
clock input. A reset signal is used to refresh the content of the memory when needed,
while a read/write signal changes the modes of the operation of the memory between
read and write modes. The reset, read/write and read clock inputs are provided from
off-chip, while the outputs of the six memory blocks (I/Q of three subbands) go off-
chip.
Row Selection
Data Conditioning
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Column Selection
Row 7
Row 8
Row 9
Row 10
Row 11
Row 12
Return Column Selection
Return Column Selection
Data (Row 1 & 2)
Clock
Reset
Read
Ouput
Input
Data
Data (Row 11 & 12)
Data (Row 9 & 10)
Data (Row 7 & 8)
Data (Row 5 & 6)
Data (Row 3 & 4)
250 um ‘
3 mm ‘
Figure 23: Memory Architecture
54
B. Memory Cell
Figure 24 shows a single bit section of the designed memory. Each two bits share a
data line, while the rest of their control signals are designated to only the row that
they belong to. In the write-mode the row and column select signals enable one of
the bits to accept the content of the data line. In the read-mode the data is pushed out
through the shift register chain till it reaches the output node.
Figure 24: 1-Bit Memory Cell Section
55
C. Memory Control Logic
Figure 25 shows the column select logic designed to control the embedded memory.
At the start of the write procedure, all of the flip-flops of the column select logic are
reset to zero except the first one that is set to one. The write clock then shifts the one
present on the first bit of the shift register through the whole chain. When the 1-
clockcycle positive pulse reaches the very end of the column select logic, it is used to
clock the row select logic and move on to the next row. Again, the whole column
select logic is reset to perform the storage process on the next row. The row select
logic is similar to the column select logic. The column select logic and the memory
cells are designed in chunks of 10-bit and every 10-bit all of the signals are buffered
and pipelined using the clock provided by the column select logic.
Figure 25: Column Select Logic
56
D. Memory Clocking and Data
As described before, to lower the switching noise the clock only goes through the
column select logic. Since the column select logic is located in the middle of the
memory block, the effect of the clock switching noise would be minimal on the
blocks close to the memory. At a given time only one of the column select signals
switches from one to zero and only one from zero to one.
The other signal that can cause switching noise is the data due to its fast activity,
thus the data is only provided to the only active row. In addition, the data line is
shared by the two adjacent rows to isolate it from the outside. For test purposes, a
multiplexer has been implemented on the data line, so that the external data can be
stored in the memory as well. This feature can be used to write and read known data
to verify the operation of the memory during the test process. A control bit has been
used to select internal/external data to be written in the memory blocks.
57
E. Memory Write Cycle
The write cycle starts with the reset signal going from zero to one when the
read/write signal is in the write mode. The first bit of the row and column selection
goes to one while all of the other ones are zero. The data of the row 1 & 2 will be
valid and the write process starts with the next rising edge of the clock. After the first
row is completed, the output of the column selection logic shifts the row select
indicator to the next row (emulated by the column select return path). This process
continues till the whole memory is updated, then all of the row and column selects
bits go to zero and the data will be kept in the memory till the next write process. At
this point, the memory goes in the halt mode waiting for reset signal to start re-
writing. Since the memory bits are all using static logic, there is no need for
refreshing and data will be kept till it is overwritten by new values. The designed
memory blocks have been tested individually by Spectre simulations and the whole
memory has been tested for functionality using Nanosim. Simulations show that the
memory can be operated with clocks as fast as 1.5 GHz.
58
F. Memory Read Cycle
The read cycle starts when the read/write signal is in the read-mode and the read
clock is valid. The design demands a read clock that is much slower than the write
clock (few hundred megahertz). While the read/write signal is in the read-mode, the
memory acts as a long shift register, the clock and data is going through the
beginning of the each row to its end and then they go to the beginning of the next
row. This way all of the data stored in the memory would be shifted out through the
output of the last bit. The memory is being filled with zeros as the data is being
shifted out. Along with the data, the output clock is also going off-chip for test
purposes. Figure 26 shows the structure of the memory in the read-mode.
Figure 26: Memory Structure in Read-Mode
59
G. Digital and Analog Isolation
Although the designed memory generates low switching noise, but the switching
noise generated can still effect the performance of the analog and RF circuitry. Thus,
a guard ring has been designed to separate the memory and digital blocks from the
analog and RF blocks. Figure 27 show the top view of the designed guard. The guard
is composed of interleaved substrate connections and deep n-wells (DNW). The first
set is connected to the ground/supply of the analog section, the mid section is
connected to a designated ground/supply nodes used for isolation, while the last
section is connected to the ground/supply of the memory block. The part of the
switching noise which is not absorbed by the guard-ring of each section, is then
absorbed by the isolation ground/supply, which are down-bonded to the board. The
length of the bonding wire and therefore the inductance of the down-bonded
connections are smaller than the other pins.
Memory
p+ (Memory Gnd)
DNW (Memory Vdd)
p+ (Isolation Gnd)
DNW (Isolation Vdd)
p+ (Isolation Gnd)
DNW (Analog Vdd)
p+ (Analog Gnd)
Analog

Figure 27: Memory/Analog Isolation Structure
60
Figure 28 show the side-view of the designed guard used to separate the
analog/digital sections of the chip. The use of deep n-well sections increases the
substrate resistance between the memory and the analog blocks, while low
impedance ohmic connections to the ground/supply absorb the noise traveling
through the substrate.
Figure 28: Memory/Analog Isolation Side-View
In addition to the isolating structure built between the analog and digital section,
the supply of the each section has been by-passed within the block. A set of by-pass
capacitors composed of MOS capacitors covered with fringe capacitors has been
used through out the design to suppress the noise traveling through the supply.
61
CHAPTER VI. CONTROL AND TEST CIRCUITRY
Digital control blocks for tuning the VCO frequency, LNA gain, baseband gain and
bandwidth as well as the transmitter parameters have been integrated with the design.
Digital control bits are used to optimize the design, compensate for the process
variations and utilize the auxiliary test circuitry. Programmable currents, voltages
and switched capacitances are controlled digitally using the control bits. The main
advantage of the controllable circuitry is to make the design more flexible and to
provide the ability to test.
Integrating the whole receiver and transmitter has the advantage of being able to
test the whole design as a system, while it can be disadvantageous in test and
debugging process. Therefore, often the designers fabricate and test the high-
frequency analog blocks prior to the integration despite the fact that several
fabrications can be costly and time consuming. Thus, in our design extra circuitries
have been added to the transceiver to ease the test, characterization and debugging of
the different blocks.
Employing the test point circuitries embedded with the design, the performance of
the transceiver blocks are optimized and measured individually. The baseband
amplifier/filter is evaluated using the spare path that was implemented along with the
transceiver. Test point circuitry is designed to avoid loading the internal nodes of the
receiver while accessing them.
62
A. Digital Programmability
In order to control the current setting, biasing voltages, gain values, bandwidths
and tuning of different parts of the design, a set of digitally controllable blocks has
been added to the design. Three different kinds of digital controllable blocks have
been designed and used throughout the design. Digitally controllable current sources
are used to control the current of the different blocks based on a fix current provided
externally. Digitally controllable voltages has been used to control the biasing
voltages of the sensitive blocks. Control bits have been used to turn on/off some
parts of the design as needed as well as changing the value of the switched capacitor
and resistors used in some parts of the design.
Digital programming of the chip has been done using a two-phased clocking
scheme through a distributed shift register to be cautious. Digital bits along with
clocks and control signals are fed into the design externally. To increase the
reliability of the design a default value is assigned to each bit by hard wiring the
default pin of each bit to either supply or ground based on the designed value used in
simulations. In order to avoid having some of the analog circuitry going into an un-
defined and un-expected state while programming the chip, an extra latch has been
used to strobe the data in after the whole shift register values are set. Thus, to control
the programming section 5 external signals has been used, which are compose of two
clocks, reset, strobe and data. The last bit of the distributed shift register is going off-
chip to verify its functionality. Figure 29 shows a section of the distributed shift
register that is used to program the control bits of the chip. Clk_A and Clk_B are
63
used to clock the data stream in, Strobe is used to latch in the data after the whole
shift register chain values are set, while Reset sets the output value of each section to
its hard-wired default value.
Figure 29: Single Bit Programming Section
Control bits have been used to control the controllable currents and voltages.
Programmable current sources provide a current that is an integer multiplication of
an external current which has been provided from off-chip. In order to avoid wasting
a lot of power in the biasing section, a small current value of 10 uA has been used.
Figure 30 shows a controllable current source section. The amount of current
consumed in the corresponding block and the size of its tail transistor is used to
calculate the size of the diode connected transistor in the variable current section.
64
Tail
Tail Ref
I W W
L 16 I L

=

Figure 30: Controllable Current Block
Controllable voltages are generated using a set of binary weighted resistors. Figure
31 shows a generic controllable voltage block that has been used throughout the
design. Large resistor values have been used to lower the power dissipation of these
blocks. Proper capacitive by-passing has been used wherever needed.
b0 b1
b5 b3 b4
b2
R2R 4R
R2R 4R
To The
Biasing
Point
VDD

Figure 31: Controllable Voltage Block
65
B. LNA Test Buffer
Low noise amplifier characteristics can be effected by parasitics and model
inaccuracies due to its high frequency of operation. Thus, a three input buffer has
been designed to help characterizing the LNA. One of the inputs has been used to
measure the performance of the LNA buffer itself and factor out its characteristics
form the measurements. The other two have been used to measure performance of
the wideband LNA and one of the second stage LNA sections. Figure 32 shows the
topology of the LNA buffer. Switches in the current source and the cascode
configuration have been used to further isolate the inputs. The output of the LNA
buffer is designed to drive pad capacitance, bonding wire and an off-chip 50-ohm
load.
Figure 32: LNA Test Buffer
66
The gain of the first stage LNA (WBLNA) can be calculated by subtracting the
gain of the LNA buffer from the combined gain of the WBLNA and the LNA buffer.
Using the same strategy the gain of the one of the second stage LNA stages can be
found (3.5 GHz-band). Since the architecture of the second stage LNA stages are the
same and the required frequency of their operation is close to each other, the profile
of the other two second stage LNA sections can be estimated. Knowing the
approximate profiles of the LNAs, second stage LNA gains can be adjusted to adjust
uneven gain of the WBLNA. The LNA buffer is located between the 3.5 GHz-band
second stage LNA and the pads. Figure 33 shows the layout of the LNA buffer and
its placement.
Figure 33: LNA Test Buffer Layout
67
C. VCO Buffer
VCO Buffer has been mainly designed to isolate the dividers and SSB mixers form
the sensitive VCO output nodes. In order to increase the reliability of the design, an
extra input has been added to the designed VCO buffer so that it can be driven by an
off-chip quadrature signal source in case that the main VCO fails to work as
predicted. Luckily, the main VCO performed as expected and the external signal
source was not needed. The aux input was only used to compare the performance of
the main VCO with an external signal source with known characteristics. Figure 34
shows the topology of the VCO buffer. Switches in the current source and the
cascode configuration have been used to further isolate the inputs and output.
Figure 34: VCO Buffer with Auxiliary Input (I-Channel)
68
D. Divider Chain Test Output
In order to measure the phase noise and frequency of the main VCO, a divided
version of the VCO output has been provided off-chip after proper buffering. Since
buffering and off-chip measurement can be done easier at lower frequency, a divided
version of the VCO output was chosen for measurements. The VCO phase noise can
be found by adding 12 dB to the measured phase noise at every offset frequency of
the 1 GHz output signal. The phase noise of the divided signal is equal to the phase
noise of the input of the divider divided by the division factor, assuming that the
noise of the divider is negligible. Figure 35 shows the divider chain test point.
Dividers and buffers are designed such that they do not contribute noticeable amount
of noise to the off-chip output, thus the measured phase noise represents the phase
noise of the main VCO.
4 ÷
Figure 35: Divider Chain Test Point
69
E. Baseband Amplifier/Filter Test Structure
The gain and bandwidth of the baseband amplifier/filter stages are designed to be
programmable using digitally controlled current sources. In order to characterize the
performance of the baseband amplifier/filter in different gain/bandwidth settings and
be able to program the baseband amplifier/filters used in the signal paths, an extra
baseband amplifier/filter followed by a sampler is implemented with the design.
Using the analog output of the replica baseband amplifier at different settings, the
gain, noise figure and linearity of the baseband amplifier in different configurations
can be measured. Using this structure the performance of the sampler can also be
verified and evaluated.
70
F. Baseband Outputs
The outputs of the baseband amplifier are provided off-chip before and after the
samplers for test purposes. Even though the baseband amplification has been done in
lower frequencies than the RF section, but still frequencies are high due to the large
bandwidth of the incoming signal. Thus, to improve testability of the designed chip,
some of the analog outputs of the baseband amplifier has been buffered to drive the
pad/package parasitics. In addition, all of the outputs of the samplers have been
buffered and going off-chip to provide the ability to by-pass the on-chip memory if
needed. Figure 36 shows the test-points designed for each one of the subbands.
Figure 36: Typical Test-points of a Baseband Subband
71
CHAPTER VII. MEASUREMENT RESULTS
The described transceiver has been designed in 0.18μm 1P6M TSMC CMOS
technology. A chip micrograph is shown in Figure 37. The chip with a total area of
4.3 mm by 3.5 mm has been mounted on a carefully designed four-layer FR4 board.
Digital control blocks for tuning the VCO frequency, LNA gain, baseband gain and
bandwidth as well as the transmitter parameters have also been implemented. The
circuit is tested with a 1.8-V supply.
Figure 37: Chip Micrograph
72
A. Input Matching
Input impedance matching is one the major requirements of any RF circuit. Input
impedance of the receivers and the antennas are designed to be 50-ohm in most of
the high frequency applications. Impedance matching between input of the receiver
and the antenna minimizes the reflections and maximizes the power transfer from
antenna to the receiver. In addition, this will simplify the design of the printed-circuit
boards (PCB) used to mount the receiver on it. Matched input of the receiver and a
50-ohm transmission line on the board assures the input impedance of the board to
be 50-ohm regardless of the length of the transmission line (neglecting the losses).
The small signal performance of the LNA was determined using 2-port
S-parameters measurements by a network analyzer. The test structure that has been
used to perform the measurements is show in Figure 38. To measure the input
matching, reflection coefficient of the input port (S
11
) has been measured by
connecting the Port 1 of the network analyzer to the input of the receiver.
Figure 38: Low Noise Amplifier Test Structure
73
Figure 39 shows the measured input matching over the band of operation. The
measured input return loss (|S
11
|) of the LNA is varying between -10 dB and -21 dB
over the operation band of the receiver (3.25 – 4.75 GHz). This measurement
includes the effect of the pad, bonding wire and the printed-circuit board (PCB). The
matching condition of |S
11
| < -10 dB is satisfied between 2.85 – 4.81 GHz. This
condition means that the reflected signal from the receiver is at least 10 times smaller
than the signal going toward the receiver (incident signal).
-25
-20
-15
-10
-5
0
2 2.5 3 3.5 4 4.5 5 5.5 6
Frequency (GHz)
S11 (dB)
Figure 39: Measure Input Matching (S11)
74
B. Low Noise Amplifier Gain
The transfer function of the LNA buffer is measured by connecting Port 1 of the
network analyzer to the auxiliary input of the LNA buffer and Port 2 to the output of
the LNA buffer as shown in Figure 38. Knowing the transfer function of the LNA
buffer, the wideband LNA (WBLNA) gain and the gain of one of the second LNA
stages have been measured by connecting Port 1 of the network analyzer to the
receiver input and Port 2 to the output of the LNA buffer. Proper input select settings
have been used to switch between three inputs of the LNA buffer.
0
4
8
12
16
1 23 45 67
Frequency (GHz)
LNA Gain (dB) "
WBLNA
LNA 2s
Figure 40: Measured LNA Gains
LNA buffer is designed to probe only one of the outputs of the second LNA stages
(3.5 GHz-band), therefore the gain of the other two paths of the second stage LNA
75
has been estimated. Proper gain settings for different paths of the second stage LNA
has been used to compensate for the gain variations of the wideband LNA over the
band of operation. Figure 40 shows the measured gain of the WBLNA and the gain
of second LNA stages in different bands. Wideband LNA has relatively low gain of
8 – 11 dB and provides input matching in the band of interest. The second stages of
the LNA provide additional gain, help flattening the overall gain and suppress the
LO leakage between channels.
76
C. Signal Path Transfer Function
The transfer function of the signal path has been measured by applying a single
tone at the input of the receiver and measuring the output power of the tone mixed
with the LOs at the output of three baseband channels. The gain of the each baseband
path has been set to compensate for gain differences between the paths and achieve
equal gains in all three channels. Figure 41 shows the transfer function of the three
subbands. The bandwidth of the AC coupling is measured to be 7 MHz.
-30
-20
-10
0
10
20
30
40
50
60
70
2.5 3.5 4.5 5.5
Frequency (GHz)
Channel Transfer Function (dB)
Figure 41: Channel Transfer Functions
77
D. Noise Figure
Noise figure is a measure of the effect of inherent receiver noise, which degrades
the signal-to-noise ratio of the incoming RF signal as it traverses the radio receiver
signal path. The linear system noise figure determines the minimum detectable signal
or the sensitivity of the receiver. The linear version of the noise figure, the noise
factor (F), is a unitless quantity which compares the total output receiver noise with
the noise that would be present assuming noiseless receiver.
Total output noise power
F
Output noise power due to input noise

The noise factor can equivalently be expresses in terms of the signal to noise ratio
(SNR) at the input and the output of the receiver by
Input signal-to-noise ratio
F
Output signal-to-noise ratio

Therefore the noise factor is always greater than or equal to one where a noise
factor of one corresponds to a system with no internal noise. The receiver noise
figure (NF) can be obtained from its noise factor by
NF 10 Log(F) =
Where the noise figure is expresses in units of dB.
In a receiver signal path, such as the one shown Figure 42, the overall system noise
figure depends on the noise figure and gain of each block. The total noise factor of a
cascaded system is given by the Friis formula.
3 2
Signal Path 1
1 1 2
F 1 F 1
F F + +
G G G

=
78
Figure 42: Direct Conversion Receiver
Where F
n
is the noise factor of the n
th
stage with respect to the driving impedance of
the preceding stage, and G
n
is the available power gain of the n
th
stage. Form the
equation above it can be concluded that the receiver noise figure is dominated by the
noise figure of the first stage, assuming that the gain of the first stage is large enough
to suppress the noise of the following stages. In the down-conversion process, the
received signal-to-noise ratio is degraded by the high noise figure of the mixers
(typically in the range of 6-15dB). Consequently, LNA should provide large gain and
low noise figure to the receiver by suppressing the noise introduced by the mixers.
Also the receiver noise figure determines the receiver sensitivity. Sensitivity is
defined as the minimum signal level that the system can detect with acceptable
output signal to noise ratio (SNR). The sensitivity of the receiver in units of dBm can
be calculated by
System Out Out min
Sensitivity[dBm] 174dBm/Hz NF 10 • Log(BW) 10 • Log(S /N ) = ++ +
where the first term is the available antenna noise power at 290˚ K, NF
System
is the
system noise figure, BW is the channel bandwidth and the last term is the minimum
79
acceptable output signal to noise (SNR) ratio in dB. In the case of digital
modulations, the minimum acceptable output signal-to-noise ratio is a function of the
required bit error rate or packet error rate and the modulation scheme.
The overall noise figure of the LNA and the receiver signal path has been
measured using Y-factor method. Due to the large gain of the two stage LNA, the
difference between the noise figure of the LNA and the receive chain is negligible.
In Y-factor method, using a noise source the internal noise of the device under test
(DUT) can be determined and therefore the noise figure of the DUT can be
calculated. The noise source provides two known noise levels when it is on or off,
these two known noise levels can be used to estimate the noise added by the DUT. In
most of the noise sources, the off-state noise is equal to the noise generated by a 50-
ohm resistor at the room temperature. The ratio of the on/off state noise levels is
called the excess noise ratio (ENR) of the noise source, which is generally provided
by the manufacturer. With the noise source connected to the input of the DUT, the
output power can be measured corresponding to the noise source on (N
2
) and off
(N
1
) states. The ratio of these two powers is called the Y-factor. The noise power at
the output of the DUT is measured using a spectrum analyzer. The absolute power
level accuracy of the measuring device is not important since a ratio is to be
measured.
2
1
N
Y
N
=
sometimes this ratio is measured in dB units, in this case:
80
dB
Y
10
Y 10 =
The Y-factor and the excess noise ratio (ENR) of the noise source can be used to
find the noise factor of the DUT.
DUT
ENR
F
Y 1
=

Traditionally the noise figure of narrowband systems is only measured and
reported at the center frequency of the receiver, while in wideband system the noise
figure has to be measured across the band of operation. Figure 43 shows the
measured noise figure of the receiver across the band. The NF of the receive chain is
varying between 4.5 – 5.4 dB between 3.25 – 4.75 GHz.
-15
-10
-5
0
5
10
15
20
01 23 45 6
Frequency (GHz)
NF (dB)
Figure 43: Measured Receiver Noise Figure
81
E. Linearity
The linearity performance of the receiver limits the maximum signal level that can
be detected and the amount of interference that can be tolerated. Receiver signal path
exhibits gain compression and intermodulation characteristics, which are measured
by the input 1-dB compression point (P
1dB
), illustrated in Figure 44, is defined as the
input signal level that causes the small signal gain drop by 1 dB.
Figure 44: Input 1-dB Compression Point
The intermodulation is also cause by the nonlinear behavior of the receiver signal
path. It can be measured by applying two closely spaced tones (at f
1
and f
2
) at the
input of the receiver and measure the intermodulation terms (mf
1
± nf
2
). Since some
of the third order modulation terms fall near to the two closely spaced input tones,
the third order intermodulation (IP3) is more interesting than the others. In a direct
conversion (Homodyne) receiver the output frequency corresponding to the two
82
closely spaced input tone are at f
1
– f
LO
and f
2
– f
LO
, while the third order
intermodulation terms are at 2f
1
– f
2
– f
LO
and 2f
2
– f
1
– f
LO
. Thus, the fundamental
outputs and the third order intermodulation terms are very close to one another as
shown in Figure 45.
Figure 45: Third Order Intermodulation in Direct Conversion Receivers
Figure 46: Extrapolation of the Input Third-Order Intermodulation
Figure 46 shows a plot of the fundamental and the third-order intermodulation
product as a function of the input power in units of dBm. Due to the linear and
83
quadratic relation of the input fundamental and third order intermodulation term to
the output, the fundamental has a slope of 1 and the third-order intermodulation term
has a slope of 3. The output power at which the extrapolated fundamental and the
third-order output powers are equal, is called the output-referred third-order
intermodulation point (OIP3) and the input amplitude corresponding to this point is
called the input-referred third-order intermodulation point (IIP3).
In a radio receiver signal path consisting of a cascade of analog blocks, as shown in
Figure 42, the system IIP3 depends on the IIP3 and gain of each block. Assuming the
amplitude of the distortion products add directly (in phase) the following
conservative (worst-case) estimate for the overall IIP3 of a cascaded system is
obtained
1 1 2
Signal Path 1 2 3
G G G 1 1
IIP3 IIP3 IIP3 IIP3
=+ +
where IIP3
n
is the input-referred third-order intercept point of stage n and G
n
is the
power gain of stage n. Thus, the latter stages bear a greater burden due to the gain of
the preceding stages. Due to the linear design of the baseband amplifier and the large
gain of the LNA in the proposed receiver, mixer is the main contributor in the overall
receiver signal path non-linearity. Thus, the IIP3 of the mixer is the dominant factor
in the equation above.
The overall receive path performance measures such as 1-dB intercept point and
IIP3 are measured across the band of operation using single/double tone techniques
at different frequencies. Figure 47 shows the measured P
1dB
and IIP3 plots of the
84
receive chain versus frequency. In the band of operation (3.25 – 4.75 GHz), the IIP3
varies between -5 to -10 dBm and P
1dB
is changing between -12 to -16 dBm.
-20
-15
-10
-5
0
5
10
15
20
12 3 4 56 7
Frequency (GHz)
IIP3 (dBm), P1dB (dB) '
IIP3
P1dB
Figure 47: Measured Receiver Signal Path P
1dB
and IIP3
85
F. VCO Phase Noise
Ideally, frequency sources used in a communication system should be comprised of
a pure sine wave carrier. This would be represented in the frequency domain by a
single line. All real sources have unwanted amplitude or phase modulated noise
components. These phase-modulated components are known as phase noise.
The amplitude components are likely to be of a lower level than the phase
modulation component. This is due to the compressed amplifiers found following
signal sources and the inherent degradation in phase noise due to frequency
multiplication. Therefore, in communication system signal sources the predominant
form of noise is phase noise.
For RF oscillators this noise is most commonly expressed in terms of single
sideband phase noise. This is a relative measurement of the noise measured in a 1 Hz
bandwidth, at a frequency offset from the carrier, relative to the carrier power. The
units are dBc/Hz.
Spectrum analyzer is used to measure phase noise here, since the resolution
bandwidth (RBW) of the spectrum analyzer is not equal to 1 Hz, its effect has to be
factored out. Thus,
Phase Noise [dBc/Hz] Noise[dBc] 10 Log(RBW[Hz]) =
where RBW is the spectrum analyzer resolution bandwidth and Noise is the
measured noise at every offset frequency. The output from a spectrum analyzer
displays the summation of the amplitude and phase noise of the source under test and
the analyzer's own phase noise. This makes measuring low phase noise oscillators
86
difficult as the performance is often limited by the spectrum analyzer. For low phase
noise sources, alternative methods must be utilized, such as frequency discriminators
or phase noise test systems.
Figure 48 shows the measured phase noise performance at the output of the
synthesizer. The phase noise is below -119 dBc/Hz at 1 MHz offset frequency, while
the PLL is operating at 4GHz. The phase noise at the outputs of the SSB mixers are
also similar to the PLL output, as the noise added by the mixers is negligible.
-160
-140
-120
-100
-80
-60
-40
0.001 0.01 0.1 1 10 100
Offset Frequency (MHz)
Phase Noise (dBc/Hz)
Figure 48: Measured Phase Noise
87
G. SSB Mixer Spurs
Local oscillator spurs cause down-conversion (folding) of un-wanted signals into
the band of operation. High power signals in the ISM bands, large interferers in the
un-licensed band of operation and low UWB emission limit makes UWB receivers
more vulnerable to this effect. Large channel to channel isolation requires low spur
levels in a frequency channelized receiver. Although the spurs caused by the loop are
negligible due to the filtering in the PLL, the spurs caused by the SSB mixers has to
be considered carefully. The measured spur level of the SSB mixer are shown in
Table II. The SSB mixers shows in excess of 35 dB image rejection.
Table II: Measured Spur Levels at the Output of SSB Mixers
Freq.
(GHz)
Source Power (dBc)
Simulated
Power (dBc)
Measured
DC Self mixing Negligible Negligible
0.5 Leakage of low frequency input Negligible -60
2.5 3rd order non-linearity of g
m
block -50 -45
3 2nd order non-linearity of g
m
block Negligible -62
3.5 Input I/Q imbalance, mismatches -55 -37
4 Leakage of high frequency input -70 -59
4.5 Desired output 0 0
5 2nd order non-linearity of g
m
block Negligible -58
5.5 3rd order non-linearity of g
m
block -50 -43
7.5/8.5 2nd order non-linearity of switches Negligible -63
88
The spurs at frequencies far from band of operation such as the ones at 500 MHz,
7.5 GHz and 8.5 GHz, do not cause serious performance degradation as the signal at
those frequencies are attenuated by the front-end. Spurs at 2.5 GHz, 5 GHz and 5.5
GHz are very important as they cause the ISM band interferers that can be very large,
to fold in the passband of the receiver. The measurement results show large
attenuation of these spurs, which make the receiver more tolerant to these interferers.
The in-band spurs that are at 3.5 GHz and 4 GHz are the main causes of channel to
channel leakage. These spurs can compromise the channelized operation of the
receiver and cause the large interferers to leak to all channels resulting in corruption
of other channels. Carefully designed symmetric layout and the use of double-
balanced architectures resulted in low spur levels at these frequencies and therefore
large channel to channel isolation.
89
H. Transmitter Performance
Transmitter is composed of the pseudo-random data generator, pre-driver and the
core. The pseudo-random data generator has been tested to verify its functionality
and the generated sequence. The output of the pseudo-random generator has been
recorded using a fast logic analyzer at different rates and the results shows proper
operation at rates as high as 1.5 GHz. The pseudo-random generator generates a 31-
bit long random sequence.
Due to the digital nature of the transmitter and its high frequency of operation, no
test point has been implemented within the pre-driver and the core. Thus, the output
nodes of the transmitter have been used to evaluate the transmitter. To verify the
performance of the transmitter, time-domain and frequency domain measurements
have to be done to evaluate the shape of the output pulse, its frequency spectrum, the
maximum rate that it can operate properly and its power dissipation. It is important
that the length of the generated pulse in the time-domain would be short to avoid
mix-up of the adjacent transmitted bits. The output spectrum of the transmit pulses
has to be within the allowed FCC spectrum to prevent mask violation.
Transmitter has been tested in time-domain by connecting its output to a digital
sampling oscilloscope. Time-domain pulse templates acquired by averaging the
subtraction of the differential outputs. Figure 49 shows the typical positive and
negative pulse templates generated by the transmitter. The measured pulse shapes are
consistent with the simulation results.
90
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1 1.5 2
Time (ns)
Voltage (V)
Figure 49: Measure Time-Domain Transmit Pulses
The output spectrum of the transmitted pulses is measured by connecting the
transmitter output to a spectrum analyzer through an external balun. Figure 50 shows
the output spectrum of the transmitted pulses while transmitter is transmitting fix
data at 1 Gsps rate. Due to the repetitive nature of the pulse the spectral lines can be
seen at multiples of 1 GHz. The spectral line at 4 GHz has the highest amplitude, as
the output tuning of the transmitter is designed to peak around 4 GHz. In order to
measure the continuous output spectrum of the transmitter, the output spectrum of
the transmitter has also been measured while transmitting pseudo-random data at 1
Gsps rate as it is shown in Figure 51.
91
-50
-40
-30
-20
-10
0
10
20
30
40
02 4 68 10
Frequency (GHz)
TX Output Power (dBm)
Figure 50: Transmitter Output Spectrum (Fixed Data)
-35
-25
-15
-5
5
15
12 3 4 56 78
Frequency (GHz)
TX Output Power (dBm)
Figure 51: Transmitter Output Spectrum (Pseudo-Random Data)
92
Due to the wide bandwidth of the transmitted pulses, an off-chip bandpass filter
has been used to fit the generated transmit pulses into the allowed UWB spectrum
and avoid mask violation. Figure 52 shows the output spectrum of the filtered
transmitter pulses. Transmitter can be further integrated by using an on-chip
transformer to convert the differential output to single-ended and an on-chip
bandpass filter for additional spectral shaping.
-35
-25
-15
-5
5
15
12 3 4 56 78
Frequency (GHz)
Filtered TX Output Power (dBm)
Figure 52: Transmitter Filtered Output Spectrum
Transmitter draws 60 mA from a 1.8-V supply of which 10 mA is consumed by the
digital components and 50 mA is dissipated in its core, while it is operating at 1 GHz
clock rate. Transmitter is capable of operating at rates as high as 1.5 Gsps.
93
I. Error Vector Magnitude (EVM)
Error Vector Magnitude (EVM) is a figure-of-merit for a measure of signal to
noise and distortion ratio. The error vector is obtained by subtracting the received
signal from an ideal reference signal. The setup consists of generating an RF signal
using a signal generator, feeding it into the receiver, and acquiring it from the
interfaces of interest using a logic analyzer. The ideal reference signal is created by
means of software. EVM provides an insight into the signal’s quality that other
performance measurements such as the eye diagram or BER measurements do not
cover. One of the advantages is the simplicity of the measurement setup, since there
is no need for an entire communication system. It possesses a direct relation with the
signal to noise and distortion ratio (SNDR) and can be used to determine the physical
error introduced at different stages of a communication system, helping the designer
to troubleshoot specific problems.
The overall transceiver performance has been experimentally verified by
connecting the attenuated output of the transmitter through a cable to the receiver
input and collecting the data from the digital output of the receiver. An attenuation of
60 dB has been used in the transceiver measurements to avoid saturating the receiver.
Off-chip digital signal processing shows an EVM of -32 dB in the absence of
interferers.
94
J. Interference Effect
The proposed UWB channelized receiver is tolerant to in-band and out-of-band
interferences. The effect of interferences is suppressed by the means of channelized
architecture with isolated subbands, linear RF circuitry and aggressive filtering. To
explore the performance of the transceiver in the presence of the large narrowband
interference signals, the signal to noise ratio (SNR) of the received signal has been
measured, while applying interferers at different frequencies (Figure 53). The
frequencies of the interferers are chosen to fully characterize the performance of the
receiver and show the effect of the interference in different cases.
UWB
Transmitter
Logic Analyzer
UWB
Receiver
Digital
Signal
Processing
Interference
Source
Input Clock
Attenuator
Figure 53: Measurement Setup in the Presence of Interferes
Out-of-band interference at 2.4 GHz and 5.2 GHz have been chosen to emulate the
effect of ISM band interferers. In case of the in-band interference, three cases have
been chosen, one in the middle of one of the side subbands (3.5 GHz), one in the
95
middle of the middle subbands (4 GHz) and one between two subbands (3.75 GHz).
The measured SNR in different cases have been shown in Figure 54. Since the
measurement results for 3.5 GHz and 4 GHz as well as 2.4 GHz and 5 GHz were
very similar, only one of the two plots is plotted representing both. Measurement
results show that the receiver can tolerate out-of-band and in-band interferences as
large as 0 dBm and -20 dBm with minimal SNR degradation, respectively.
0
5
10
15
20
25
30
35
-40 -30 -20 -10 0 10 20 30
Interference Power (dBm)
Output SNR (dB)
3.5GHz / 4GHz
3.75GHz
2.4GHz / 5.2GHz
Figure 54: Measured SNR in the Presence of Interferers
96
K. Summary and Comparison
Employing the test point circuitries embedded within the design, the performance
of the LNA, mixer and the synthesizer are measured, while the baseband
amplifier/filter is evaluated using the spare path implemented in the transceiver. The
wideband LNA has a gain of more than 8 dB and provides input matching in the
band of interest. The phase noise is below -119 dBc/Hz at 1 MHz offset frequency
and SSB mixers achieve in excess of 35 dB image rejection. Block level
measurement results of the transceiver are summarized in Table III.
Table III: Measurement Results of the Transceiver Blocks
The complete receiver draws less than 55 mA from a 1.8-V supply of which 37 mA
is consumed by the receive signal path and 18 mA is dissipated by the frequency
synthesizer. The overall receive path performance metrics such as noise figure and
97
IIP3 are measured using known techniques. The maximum gain and the minimum
NF are 82 dB and 4.5 dB, respectively.
Transmitter draws 60 mA from a 1.8-V supply of which 10 mA is consumed by the
digital components and 50 mA is dissipated by the core when operating at 1 GHz
clock rate. An off-chip filter has been used to fit the generated transmit pulses into
the allowed UWB spectrum and avoid mask violation.
The overall transceiver performance has been experimentally verified by
connecting the attenuated output of the transmitter through a cable to the receiver
input and collecting the data from the digital output of the chip. Off-chip digital
signal processing shows an EVM of -32 dB. To measure the amount of interference
the receiver can tolerate, tone interferers of varying magnitude values were applied at
different frequencies. Measurement results show that the receiver can tolerate out-of-
band interferers (at 2.4 GHz and 5.2 GHz) and in-band interferers (within 3.25 – 4.75
GHz) that are as large as 0 dBm and -20 dBm, respectively, while suffering an EVM
degradation of less than 3 dB.
Table V compares the performance of this work to recently published UWB
transceivers [7, 8, 12-17]. Most of the transceiver designs published are composed of
the analog signal path only, whereas this design also includes frequency synthesizer
and ADCs (which are 1-bit samplers). Table V shows that this design dissipates less
power than comparable designs while the achieved energy per bit performance is
much better (by >2X for receiver).
98
Table IV: UWB Transceivers Comparison
Table V: UWB Transceivers Comparison
99
CHAPTER VIII. CONCLUSION
An energy-efficient 1 Gbps UWB receiver that is robust to in-band and out-of-band
interferers is presented. The proposed UWB system efficiently achieves the high data
rate by increasing the symbol rate while using simple BPSK modulation. The UWB
receiver dissipates only 98pJ/bit, which represents less than half of the lowest value
reported to date. Furthermore, the proposed frequency channelized architecture
enables the receiver to be robust to both in-band and out-of-band interferers while
using 1-bit ADCs. The multi-output synthesizer employs direct frequency synthesis
approach to provide spectrally pure LO signals, which are essential for preventing
folding of the large interferences into an interferer-free subband in the frequency
channelized receiver. The use of BPSK modulation enables the use of simple low-
power transmitter. The transmitter benefits from the digital techniques combined
with analog concepts to generate template pulses that are needed. The performance
of the transmitter can be further optimized to achieve lower power dissipation and
higher level of integration in subsequent silicon iterations. As the comparison
presented before shows the transceiver dissipates exceptionally low energy-per-bit
while operating at gigabit rates.
100
References
[1] “Multi-band OFDM physical layer proposal for IEEE 802.15 task group 3a,”
IEEE P802.15 Working Group for Wireless Personal Area Networks, March
2004.
[2] R. D. Wilson, and R. A. Scholtz, “Comparison of CDMA and modulation
schemes for UWB radio in a multipath environment,” GLOBECOM 2003, Vol.
2, pp. 754-758, 2003.
[3] W. Namgoong, “A Channelized Digital Ultra-Wideband Receiver,” IEEE
Transactions on Wireless Communication, Vol. 2, pp. 502-510, May 2003.
[4] S. Velazquez, T. Nguyen, S. Broadstone, and J. Roberge, ”A hybrid filter band
approach to analog-to-digital conversion,” in Proc. IEEE-SP International
Symposium Time-Frequency Time-Scale Analysis., October 1994, pp 116-119.
[5] O. Oliaei, “Asympototically perfect reconstruction in hybrid filter banks,” in
Proc. IEEE International Conference Acoustics, Speech, Signal Processing,
Vol. 3, 1998, pp. 1829-1832.
[6] L. Feng, and W. Namgoong, “An adaptive maximally decimated channelized
UWB receiver with cyclic prefix,” IEEE Transactions on circuits and systems
I, Vol. 52, pp. 2165-2172, October 2005.
[7] R. Roovers, D. M. W. Leenaerts, J. Bergervoet, K. S. Harish, R. C. H. Van de
Beek, G. Van der Weide, H. Waite, Zhang Yifeng, S. Aggarwal, and C.
Razzell “An Interference-Robust Receiver for Ultra-Wide-Band Radio in SiGe
BiCMOS Technology,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12,
pp. 2563-2572, December 2005.
[8] A. Ismail, and A. A. Abidi “A 3.1- to 8.2-GHz Zero-IF Receiver and Direct
Frequency Synthesizer in 0.18-μm SiGe BiCMOS for Mode-2 MB-OFDM
UWB Communication,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12,
pp. 2573-2582, December 2005.
[9] J. Lerdworatawee, and W. Namgoong, “Wideband CMOS low-noise amplifier
design based on source degeneration topology,” IEEE Transactions on circuits
and systems I, Vol. 52, pp. 2327-2334, November 2005.
[10] W. B. Wilson, U. K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS Self-
Calibrating Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, Vol.
35, No. 10, pp. 1437-1444, October 2000.
101
[11] L. Romano, S. Levantino, A. Bonfanti, C. Samori, and A. L. Lacaita, “Phase
noise and accuracy in quadrature oscillators,” in Proceedings of ISCAS 2004,
Vol. 1, May 2004, pp. 23-26.
[12] B. Razavi, T. Aytur, C. Lam, Yang Fei-Ran, Li Kuang-Yu, Yan Ran-Hong,
Kang Han-Chang, Hsu Cheng-Chung, and Lee Chao-Cheng “A UWB CMOS
Transceiver,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, pp. 2555-
2562, December 2005.
[13] C. Sandner, S. Derksen, D. Draxelmayr, S. Ek, V. Filimon, G. Leach, S.
Marsili, D. Matveev, K. Mertens, H. Paule, M. Punzenberger, C. Reindl, R.
Salerno, M. Tiebout, A. Weisbauer, I. Winter, and Z. Zhang “A
WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB,” IEEE Journal
of Solid-State Circuits, Vol. 41, No. 12, pp. 2787-2794, December 2006.
[14] S. Lo, I. Sever, S. P. Ma, P. Jang, A. Zou, C. Arnott, K. Ghatak, A. Schwartz,
L. Huynh, V. Phan, and T. Nguyen “A Dual-Antenna Phase-Array UWB
Transceiver in 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, Vol.
41, No. 12, pp. 2776-2786, December 2006.
[15] S. Lida, K. Tanaka, H. Suzuki, N. Yoshikawa, N. Shoji, B. Griffiths, D. Mellor,
F. Hayden, I. Butler, and J. Chatwin, “A 3.1 to 5GHz CMOS DSSS UWB
Transceiver for WPANs,” IEEE International Solid-State Circuits Conference
Digest of Technical Papers, pp. 214-215, February 2005.
[16] A. Takana, H. Okada, H. Kodma, and H. Ishikawa,”A 1.1V 3.1-9.5 GHz MB-
OFDM UWB transceiver in 90nm CMOS,” in IEEE International Solid-State
Circuits Conference Digest of Technical Papers, pp. 398-407, February 2006.
[17] B. Shi, and M. Y. W. Chia,”A 3.1-10.6 GHz RF front-end for Multi-band
UWB wireless receivers,” in IEEE Radio-Frequency Integrated Circuits
Digest of Papers, pp. 343-346, Jun. 2005.
[18] A. Bevilacqua, and A. M. Niknejad, “An Ultrawideband CMOS Low-Noise
Amplifier for 3.1-10.6-GHz Wireless Receivers,” IEEE Journal of Solid-State
Circuits, Vol. 39, No. 12, pp. 2259-2268, December 2004.
[19] A. Ismail, and A. A. Abidi, “A 3-10-GHz Low-Noise Amplifier With
Wideband LC-Ladder Matching Network,” IEEE Journal of Solid-State
Circuits, Vol. 39, No. 12, pp. 2269-2277, December 2004.
[20] F. Lee, and A. Chandrakasan, “A 2.5nJ/b 0.65V 3-to-5GHz Subband UWB
Receiver in 90nm CMOS,” IEEE International Solid-State Circuits
Conference Digest of Technical Papers, February 2007.
102
[21] B. Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE
Journal of Solid-State Circuits, Vol. 39, No. 9, pp. 1415-1424, September
2004.
[22] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of
Solid-State Circuits, Vol. 31, No. 3, pp. 331-343, March 1996.
[23] A. Demir, and A. L. Sangiovanni-Vicentelli, “Simulation and Modeling of
Phase Noise in Open-Loop Oscillators,” IEEE 1996 Custom Integrated
Circuits Conference, pp. 453-456, 1996.
[24] Chih-Kong Ken Yang, Vladimir Stojanovic, Siamak Modjtahedi, Mark A.
Horowitz, and William F. Ellersick, “A Serial-Link Transceiver Based on 8-
GSamples/s A/D and D/A Converters in 0.25-/mi CMOS,” IEEE Journal of
Solid-State Circuits, Vol. 36, No. 11, pp. 1684-1692, November 2001.
[25] B. Razavi, “Architectures and Circuits for RF CMOS Receivers,” in
Proceedings of Custom Integrated Circuits Conference 1998, May 1998, pp.
393-400.
[26] B. Razavi, “Challenges in the Design of Frequency Synthesizers for Wireless
Applications,” in Proceedings of Custom Integrated Circuits Conference 1997,
May 1997, pp. 395-402.
[27] P. J. Sullivan, B.A. Xavier, and W. H. Ku, “Low Voltage Performance of a
Microwave CMOS Gilbert Cell Mixer,” IEEE Journal of Solid-State Circuits,
Vol. 32, No. 7, pp. 1151-1155, July 1997.
[28] Hooman Darabi, and Asad A. Abidi, “Noise in RF-CMOS Mixers: A Simple
Physical Model,” IEEE Transactions on Solid State Circuits, Vol. 35, No. 1,
pp. 15-25, January 2000.
[29] Jung-Suk Goo, Hee-Tae Ahn, Donald J. Ladwig, Zhiping Yu, Thomas H. Lee,
and Robert W. Dutton, “A Noise Optimization Technique for Integrated Low-
Noise Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp.
994-1002, July 1997.
[30] Hooman Darabi, and Asad A. Abidi, “A 4.5-mW 900-MHz CMOS Receiver
for Wireless Paging,” IEEE Transactions on Solid State Circuits, Vol. 35, No.
8, pp. 1085-1096, August 2000.
[31] Adiseno, Mohammad Ismail, and Hakan Olsson, “A Wide-Band RF Front-End
for Multiband Multistandard High-Linearity Low-IF Wireless Receivers,”
IEEE Journal of Solid-State Circuits, Vol. 37, No. 9, pp. 1162-1168,
September 2002.
103
[32] Payam Heydari, “Analysis of the PLL Jitter Due to Power/Ground and
Substrate Noise,” IEEE Transactions on circuits and systems I, Vol. 51, No.
12, pp. 2404-2416, December 2004.
[33] Pietro Andreani, Andrea Bonfanti, Luca Romano, and Carlo Samori, “Analysis
and Design of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE Journal of
Solid-State Circuits, Vol. 37, No. 12, pp. 1737-1747, December 2002.
[34] Manolis T. Terrovitis, and Robert G. Meyer, “Noise in Current-Commutating
CMOS Mixers,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, pp. 772-
783, June 1999.
[35] Jianjun J. Zhou, and David J. Allstot, “Monolithic Transformers and Their
Application in a Differential CMOS RF Low-Noise Amplifier,” IEEE Journal
of Solid-State Circuits, Vol. 33, No. 12, pp. 2020-2027, December 1998.
[36] Reza Navid, and Robert W. Dutton, “The Physical Phenomenal Responsible
For Excess Noise in Short-Channel MOS Devices,” in Proceedings of
International Conference on Simulation of Semiconductor Processes and
Devices 2002, September 2002, pp. 75-78.
[37] Alper Demir, Amit Mehrotra, and Jaijeet Roychowdhury, “Phase Noise in
Oscillators: A Unifying Theory and Numerical Methods for Characterization,”
IEEE Transactions on Circuits and Systems I: Fundamental Theory and
Applications, Vol. 47, No. 5, pp. 655-674, May 2000.
[38] Thomas H. Lee, and Ali Hajimiri, “Oscillaor Phase Noise: A Tutorial,” IEEE
Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 326-336, March 2000.
[39] Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, and Sang-
Gug Lee, “An Ultra-Wideband CMOS Low Noise Amplifier for 3-5 GHz
UWB Systems,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, pp. 544-
547, February 2005.
[40] Behzad Razavi, Kwing F. Lee, and Ran H. Yan, “Design of High-Speed, Low-
Power Frequency Dividers and Phase-Locked Loops in Deep Submicron
CMOS,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 2, pp. 101-109,
February 1995.
[41] William F. Egan, “Modeling Phase Noise in Frequency Dividers,” IEEE
Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 37,
No. 4, pp. 307-315, July 1990.
104
[42] Won-Hyo Lee, Sung-Dae Lee, and Jun-Dong Cho, “A High-Speed, Low-
Power Phase Frequency Detector and Charge-Pump Circuits for High
Frequency Phase-Locked Loops,” IEEE Design Automation Conference 1999,
Vol. 1, pp. 269-272, January 1990.
[43] Y. Park, S. Chakraborty, C. H. Lee, S. Nuttinck, and J. Laskar, “Wide-band
CMOS VCO and Frequency Divider Design for Quadrature Signal
Generation,” in IEEE MTT-S International Microwave Symposium Digest
2004, June 2004, pp. 1493-1496.
[44] Hirad Samavati, Hamid R. Rategh, and Thomas H. Lee, “A 5-GHz CMOS
Wireless LAN Receiver Front End,” IEEE Journal of Solid-State Circuits, Vol.
35, No. 5, pp. 780-787, May 2000.
[45] Farbod Behbahani, Yoji Kishigami, John Leete, and Asad A. Abidi, “CMOS
Mixers and Polyphase Filter for Large Image Rejection,” IEEE Journal of
Solid-State Circuits, Vol. 36, No. 6, pp. 873-887, June 2001.
[46] Manop Thamsiriaunt, and Tadeusz A. Kwasniewski, “CMOS VCO’s for PLL
Frequency Synthesis in GHz Digital Mobile Radio Communications,” IEEE
Journal of Solid-State Circuits, Vol. 32, No. 10, pp. 1511-1524, October 1997.
[47] Xiaodong Zhang, S. Ghosh and M. Bayoumi, “A Low Power CMOS UWB
Pulse Generator,” in Proceedings of 48
th
Midwest Symposium on Circuits and
Systems 2005, August 2005, pp. 1410-1413.
105
Alphabetized Bibliography
Adiseno, Mohammad Ismail, and Hakan Olsson, “A Wide-Band RF Front-End
for Multiband Multistandard High-Linearity Low-IF Wireless Receivers,” IEEE
Journal of Solid-State Circuits, Vol. 37, No. 9, pp. 1162-1168, September 2002.
Pietro Andreani, Andrea Bonfanti, Luca Romano, and Carlo Samori, “Analysis
and Design of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE Journal of Solid-
State Circuits, Vol. 37, No. 12, pp. 1737-1747, December 2002.
Farbod Behbahani, Yoji Kishigami, John Leete, and Asad A. Abidi, “CMOS
Mixers and Polyphase Filter for Large Image Rejection,” IEEE Journal of Solid-
State Circuits, Vol. 36, No. 6, pp. 873-887, June 2001.
A. Bevilacqua, and A. M. Niknejad, “An Ultrawideband CMOS Low-Noise
Amplifier for 3.1-10.6-GHz Wireless Receivers,” IEEE Journal of Solid-State
Circuits, Vol. 39, No. 12, pp. 2259-2268, December 2004.
Hooman Darabi, and Asad A. Abidi, “Noise in RF-CMOS Mixers: A Simple
Physical Model,” IEEE Transactions on Solid State Circuits, Vol. 35, No. 1, pp.
15-25, January 2000.
Hooman Darabi, and Asad A. Abidi, “A 4.5-mW 900-MHz CMOS Receiver for
Wireless Paging,” IEEE Transactions on Solid State Circuits, Vol. 35, No. 8, pp.
1085-1096, August 2000.
Alper Demir, Amit Mehrotra, and Jaijeet Roychowdhury, “Phase Noise in
Oscillators: A Unifying Theory and Numerical Methods for Characterization,”
IEEE Transactions on Circuits and Systems I: Fundamental Theory and
Applications, Vol. 47, No. 5, pp. 655-674, May 2000.
A. Demir, and A. L. Sangiovanni-Vicentelli, “Simulation and Modeling of Phase
Noise in Open-Loop Oscillators,” IEEE 1996 Custom Integrated Circuits
Conference, pp. 453-456, 1996.
William F. Egan, “Modeling Phase Noise in Frequency Dividers,” IEEE
Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 37,
No. 4, pp. 307-315, July 1990.
L. Feng, and W. Namgoong, “An adaptive maximally decimated channelized
UWB receiver with cyclic prefix,” IEEE Transactions on circuits and systems I,
Vol. 52, pp. 2165-2172, October 2005.
106
Jung-Suk Goo, Hee-Tae Ahn, Donald J. Ladwig, Zhiping Yu, Thomas H. Lee,
and Robert W. Dutton, “A Noise Optimization Technique for Integrated Low-
Noise Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 994-
1002, July 1997.
Payam Heydari, “Analysis of the PLL Jitter Due to Power/Ground and Substrate
Noise,” IEEE Transactions on circuits and systems I, Vol. 51, No. 12, pp. 2404-
2416, December 2004.
A. Ismail, and A. A. Abidi, “A 3-10-GHz Low-Noise Amplifier With Wideband
LC-Ladder Matching Network,” IEEE Journal of Solid-State Circuits, Vol. 39,
No. 12, pp. 2269-2277, December 2004.
A. Ismail, and A. A. Abidi “A 3.1- to 8.2-GHz Zero-IF Receiver and Direct
Frequency Synthesizer in 0.18-μm SiGe BiCMOS for Mode-2 MB-OFDM UWB
Communication,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, pp.
2573-2582, December 2005.
Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, and Sang-
Gug Lee, “An Ultra-Wideband CMOS Low Noise Amplifier for 3-5 GHz UWB
Systems,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, pp. 544-547,
February 2005.
F. Lee, and A. Chandrakasan, “A 2.5nJ/b 0.65V 3-to-5GHz Subband UWB
Receiver in 90nm CMOS,” IEEE International Solid-State Circuits Conference
Digest of Technical Papers, February 2007.
Thomas H. Lee, and Ali Hajimiri, “Oscillaor Phase Noise: A Tutorial,” IEEE
Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 326-336, March 2000.
Won-Hyo Lee, Sung-Dae Lee, and Jun-Dong Cho, “A High-Speed, Low-Power
Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-
Locked Loops,” IEEE Design Automation Conference 1999, Vol. 1, pp. 269-272,
January 1990.
J. Lerdworatawee, and W. Namgoong, “Wideband CMOS low-noise amplifier
design based on source degeneration topology,” IEEE Transactions on circuits
and systems I, Vol. 52, pp. 2327-2334, November 2005.
S. Lida, K. Tanaka, H. Suzuki, N. Yoshikawa, N. Shoji, B. Griffiths, D. Mellor,
F. Hayden, I. Butler, and J. Chatwin, “A 3.1 to 5GHz CMOS DSSS UWB
Transceiver for WPANs,” IEEE International Solid-State Circuits Conference
Digest of Technical Papers, pp. 214-215, February 2005.
107
S. Lo, I. Sever, S. P. Ma, P. Jang, A. Zou, C. Arnott, K. Ghatak, A. Schwartz, L.
Huynh, V. Phan, and T. Nguyen “A Dual-Antenna Phase-Array UWB
Transceiver in 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 41,
No. 12, pp. 2776-2786, December 2006.
W. Namgoong, “A Channelized Digital Ultra-Wideband Receiver,” IEEE
Transactions on Wireless Communication, Vol. 2, pp. 502-510, May 2003.
Reza Navid, and Robert W. Dutton, “The Physical Phenomenal Responsible For
Excess Noise in Short-Channel MOS Devices,” in Proceedings of International
Conference on Simulation of Semiconductor Processes and Devices 2002,
September 2002, pp. 75-78.
O. Oliaei, “Asympototically perfect reconstruction in hybrid filter banks,” in
Proc. IEEE International Conference Acoustics, Speech, Signal Processing, Vol.
3, 1998, pp. 1829-1832.
Y. Park, S. Chakraborty, C. H. Lee, S. Nuttinck, and J. Laskar, “Wide-band
CMOS VCO and Frequency Divider Design for Quadrature Signal Generation,”
in IEEE MTT-S International Microwave Symposium Digest 2004, June 2004,
pp. 1493-1496.
B. Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE
Journal of Solid-State Circuits, Vol. 39, No. 9, pp. 1415-1424, September 2004.
B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of
Solid-State Circuits, Vol. 31, No. 3, pp. 331-343, March 1996.
B. Razavi, “Architectures and Circuits for RF CMOS Receivers,” in Proceedings
of Custom Integrated Circuits Conference 1998, May 1998, pp. 393-400.
B. Razavi, “Challenges in the Design of Frequency Synthesizers for Wireless
Applications,” in Proceedings of Custom Integrated Circuits Conference 1997,
May 1997, pp. 395-402.
B. Razavi, T. Aytur, C. Lam, Yang Fei-Ran, Li Kuang-Yu, Yan Ran-Hong, Kang
Han-Chang, Hsu Cheng-Chung, and Lee Chao-Cheng “A UWB CMOS
Transceiver,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, pp. 2555-
2562, December 2005.
Behzad Razavi, Kwing F. Lee, and Ran H. Yan, “Design of High-Speed, Low-
Power Frequency Dividers and Phase-Locked Loops in Deep Submicron
CMOS,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 2, pp. 101-109,
February 1995.
108
L. Romano, S. Levantino, A. Bonfanti, C. Samori, and A. L. Lacaita, “Phase
noise and accuracy in quadrature oscillators,” in Proceedings of ISCAS 2004,
Vol. 1, May 2004, pp. 23-26.
R. Roovers, D. M. W. Leenaerts, J. Bergervoet, K. S. Harish, R. C. H. Van de
Beek, G. Van der Weide, H. Waite, Zhang Yifeng, S. Aggarwal, and C. Razzell
“An Interference-Robust Receiver for Ultra-Wide-Band Radio in SiGe BiCMOS
Technology,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, pp. 2563-
2572, December 2005.
Hirad Samavati, Hamid R. Rategh, and Thomas H. Lee, “A 5-GHz CMOS
Wireless LAN Receiver Front End,” IEEE Journal of Solid-State Circuits, Vol.
35, No. 5, pp. 780-787, May 2000.
C. Sandner, S. Derksen, D. Draxelmayr, S. Ek, V. Filimon, G. Leach, S. Marsili,
D. Matveev, K. Mertens, H. Paule, M. Punzenberger, C. Reindl, R. Salerno, M.
Tiebout, A. Weisbauer, I. Winter, and Z. Zhang “A WiMedia/MBOA-Compliant
CMOS RF Transceiver for UWB,” IEEE Journal of Solid-State Circuits, Vol. 41,
No. 12, pp. 2787-2794, December 2006.
B. Shi, and M. Y. W. Chia,”A 3.1-10.6 GHz RF front-end for Multi-band UWB
wireless receivers,” in IEEE Radio-Frequency Integrated Circuits Digest of
Papers, pp. 343-346, Jun. 2005.
P. J. Sullivan, B.A. Xavier, and W. H. Ku, “Low Voltage Performance of a
Microwave CMOS Gilbert Cell Mixer,” IEEE Journal of Solid-State Circuits,
Vol. 32, No. 7, pp. 1151-1155, July 1997.
A. Takana, H. Okada, H. Kodma, and H. Ishikawa,”A 1.1V 3.1-9.5 GHz MB-
OFDM UWB transceiver in 90nm CMOS,” in IEEE International Solid-State
Circuits Conference Digest of Technical Papers, pp. 398-407, February 2006.
Manolis T. Terrovitis, and Robert G. Meyer, “Noise in Current-Commutating
CMOS Mixers,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, pp. 772-
783, June 1999.
Manop Thamsiriaunt, and Tadeusz A. Kwasniewski, “CMOS VCO’s for PLL
Frequency Synthesis in GHz Digital Mobile Radio Communications,” IEEE
Journal of Solid-State Circuits, Vol. 32, No. 10, pp. 1511-1524, October 1997.
S. Velazquez, T. Nguyen, S. Broadstone, and J. Roberge, ”A hybrid filter band
approach to analog-to-digital conversion,” in Proc. IEEE-SP International
Symposium Time-Frequency Time-Scale Analysis., October 1994, pp 116-119.
109
R. D. Wilson, and R. A. Scholtz, “Comparison of CDMA and modulation
schemes for UWB radio in a multipath environment,” GLOBECOM 2003, Vol. 2,
pp. 754-758, 2003.
W. B. Wilson, U. K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS Self-
Calibrating Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, Vol.
35, No. 10, pp. 1437-1444, October 2000.
Chih-Kong Ken Yang, Vladimir Stojanovic, Siamak Modjtahedi, Mark A.
Horowitz, and William F. Ellersick, “A Serial-Link Transceiver Based on 8-
GSamples/s A/D and D/A Converters in 0.25-/mi CMOS,” IEEE Journal of
Solid-State Circuits, Vol. 36, No. 11, pp. 1684-1692, November 2001.
Xiaodong Zhang, S. Ghosh and M. Bayoumi, “A Low Power CMOS UWB Pulse
Generator,” in Proceedings of 48
th
Midwest Symposium on Circuits and Systems
2005, August 2005, pp. 1410-1413.
Jianjun J. Zhou, and David J. Allstot, “Monolithic Transformers and Their
Application in a Differential CMOS RF Low-Noise Amplifier,” IEEE Journal of
Solid-State Circuits, Vol. 33, No. 12, pp. 2020-2027, December 1998.
“Multi-band OFDM physical layer proposal for IEEE 802.15 task group 3a,”
IEEE P802.15 Working Group for Wireless Personal Area Networks, March
2004.

Abstract (if available)

Abstract A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25 - 4.75 GHz band designed for low power high data rate communication is implemented in 0.18 µm CMOS technology. Operating at 1 Gbps data rate, it dissipates 98 mW (98 pJ/b) in the receive-mode and 108 mW (108 pJ/b) in the transmit-mode from a 1.8-V supply while achieving a combined TX/RX EVM of -32 dB. The combination of the frequency channelized architecture, high-linearity RF circuits, aggressive baseband filtering and low local oscillator spurs results in an interference-tolerant receiver, having the ability to co-exits with systems operating in the 2.4 GHz and 5 GHz ISM bands as well as systems in its unlicensed band of operation of the receiver. The receiver provides maximum gain of 82 dB, overall noise figure in the range of 4.5 - 5.4 dB, IIP3 of -5 to -10 dBm, and 47 dB channel to channel isolation. The receiver suffers a performance degradation of less than 3 dB in EVM in the presence of in-band and out-of-band interferers as large as -20 dBm and 0 dBm, respectively. The mostly digital transmitter delivers output swing of 800 mVpp to a 50-ohm antenna at rates as high as 1.5 Gbps.

Linked assets

University of Southern California Dissertations and Theses

Conceptually similar

PDF

Frequency channelized receiver for ultra-wideband and serial-link systems

PDF

Real-time channel sounder designs for millimeter-wave and ultra-wideband communications

PDF

High frequency ultrasonic phased array system and its applications

PDF

Digital to radio frequency conversion techniques

PDF

Silicon-based wideband & mm-wave power amplifier architectures and implementations

PDF

Low-power, dual sampling-rate, shared-architecture ADC for implantable biomedical systems

PDF

Highly integrated 2D ultrasonic arrays and electronics for modular large apertures

Asset Metadata

Creator Medi, Ali (author)

Core Title Design and implementation of frequency channelized ultra-wide-band (UWB) transceivers

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 07/27/2007

Defense Date 03/21/2007

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag analog,circuit,OAI-PMH Harvest,RF,UWB

Language English

Advisor Choma, John, Jr. (committee chair), Namgoong, Won (committee chair), Kim, Eun Sok (committee member), Meshkati, Najmedin (committee member)

Creator Email alimedi@yahoo.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-m699

Unique identifier UC1301498

Identifier etd-Medi-20070727 (filename),usctheses-m40 (legacy collection record id),usctheses-c127-521607 (legacy record id),usctheses-m699 (legacy record id)

Legacy Identifier etd-Medi-20070727.pdf

Dmrecord 521607

Document Type Dissertation

Rights Medi, Ali

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Repository Name Libraries, University of Southern California

Repository Location Los Angeles, California

Repository Email cisadmin@lib.usc.edu