University of Southern California Dissertations and Theses

Architectures and integrated circuits for RF and mm-wave multiple-antenna systems on silicon

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Architectures and integrated circuits for RF and mm-wave multiple-antenna systems on silicon

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Content ARCHITECTURES AND INTEGRATED CIRCUITS FOR RF AND MM-WAVE MULTIPLE-ANTENNA SYSTEMS ON SILICON by Harish Krishnaswamy A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulllment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2009 Copyright 2009 Harish Krishnaswamy Dedication To my wife, Syantani Chatterjee ii Acknowledgments One of the many truths that I have learnt over the past ve and a half years of doctoral study is that it takes the support of many a well wisher and loved one to earn a doctoral degree. No one knows this better than my wife, Syantani. Although she has faced as many challenges in her professional career as I have, she has always stood by my side patiently and lovingly. She has celebrated my successes and mourned my failures with the empathy that only a truly loved one can summon. She is my soulmate, my best friend, my partner in crime, my agony aunt - the list is endless. I dedicate this thesis to her. One of the largest in uences on my life over the past ve and a half years has been my advisor, Dr. Hossein Hashemi. The impact that he has had on me has only been apparent to me over the past two and a half years. Under his tutelage, I have achieved academic highs that I could never have dreamed of. This world turns on brand names, and when quizzed about my academic credentials, I only say that I am Hossein Hashemi's student. I only hope that after our time together, he is proud to claim me as well. I would also like to thank my qualifying exam and dissertation defense committee members, Dr. Tony Levi, Dr. John Choma, Dr. Aluizio Prata, Dr. Stephan Haas, Dr. John O'Brien and Dr. Keith Chugg. In particular, Dr. Levi, Dr. Choma and Dr. Prata iii have taken a keen interest in my academic career and shaped my academic vision for the future. Most of doctoral life is spent in the trenches. Most of it is not pretty, and it is then that you learn who your true comrades are. This doctoral work would not have been possible without the support of Ankush Goel, who has probably been my closest friend over the duration of my doctoral studies. I am also indebted to Ta-shun Chu, Firooz A atouni, John Roderick, Masashi Yamagata and Zahra Safarian. They have each displayed a sel essness at crucial times that I am eternally grateful for. Finally, I would like to thank my parents and my brother. While the last ve and a half years have certainly been a turning point in my life, their love and sacrices have made me who I am today. iv Table of Contents Dedication ii Acknowledgments iii List Of Tables vii List Of Figures ix Abstract xxii Chapter 1: Introduction 1 1.1 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chapter 2: Passive Components on Silicon at mm-Wave Frequencies 5 2.1 Impact of Passive-Element Loss on Dierent RF Building Blocks . . . . . 6 2.2 Survey of State-of-the-Art Passive Elements on Silicon . . . . . . . . . . . 10 2.3 A Coplanar Stripline-based Complementary Current-Sharing Oscillator at 26GHz in a 0.18m CMOS process . . . . . . . . . . . . . . . . . . . . . . 18 2.4 Transformer-based Integrated RF Oscillators . . . . . . . . . . . . . . . . 25 2.5 Quantifying the Impact of Passive-Element Loss on LNA Noise Figure . . 37 2.6 Topics for Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 3: Integrated Phased Arrays for Commercial Wireless Commu- nication and Radar 56 3.1 History of the Phased Array . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2 Phased Arrays for Commercial mm-Wave Applications . . . . . . . . . . . 58 3.3 Phased Array Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.4 Phased Arrays versus Timed Arrays . . . . . . . . . . . . . . . . . . . . . 66 3.5 Conventional Phased Array Architectures . . . . . . . . . . . . . . . . . . 74 3.6 The Eect of Mismatch in Phased Arrays . . . . . . . . . . . . . . . . . . 79 3.7 The Eect of Quantization Error in Phased Arrays . . . . . . . . . . . . . 87 3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 v Chapter 4: A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Arrays 93 4.1 The Variable-Phase Ring Oscillator and PLL Architecture . . . . . . . . . 94 4.2 Linearity of the VPRO-PLL Receiver . . . . . . . . . . . . . . . . . . . . . 112 4.3 Phase Noise of Tuned Ring Oscillators . . . . . . . . . . . . . . . . . . . . 114 4.4 Sensitivity of the VPRO-PLL Phased-Array Receiver . . . . . . . . . . . . 126 4.5 VPRO Performance in the Presence of Process Mismatches . . . . . . . . 131 4.6 A 4-Channel 24GHz Phased-Array Transceiver in 0.13m CMOS . . . . . 144 4.7 An UWB 4-Channel 24-27GHz VPRO-PLL Phased-Array Transmitter in 0.13m CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.8 Topics for Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . 174 4.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Chapter 5: An RF-Multibeam Spatio-Temporal RAKE Transceiver Ar- chitecture for Radar 180 5.1 Wireless Communication in Multipath Fading Channels . . . . . . . . . . 181 5.2 Multipath in Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.3 The RF-Multibeam Spatio-Temporal RAKE Transceiver Architecture . . 187 5.4 Code Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.5 Baseband Implementation - Analog versus Digital . . . . . . . . . . . . . . 195 5.6 A 4-Channel 24-26GHz RF-Multibeam ST-RAKE Transceiver for Vehicular Radar in 90nm CMOS . . . . . . . . . . . . . . 214 5.7 Topics for Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Chapter 6: Conclusions 240 6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 6.2 Topics for Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . 243 References 246 Appendix: Characterization of Process Technologies Used 258 A.1 IBM's 8HP 0.13m SiGe BiCMOS . . . . . . . . . . . . . . . . . . . . . . 258 A.2 IBM's 8RF 0.13m CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 A.3 IBM's 9RF-LP 90nm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . 267 vi List Of Tables 2.1 Survey of state-of-the-art oscillators/VCOs operating above 10GHz. . . . 24 2.2 Phase noise performance and oscillation frequency of the two oscillators for a variety of bias currents. . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.3 Performance summary of the E-band LNA. . . . . . . . . . . . . . . . . . 53 2.4 Performance comparison of state-of-the-art silicon-based LNAs operating above 60GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1 Comparison of conventional antenna arrays suitable for military applica- tions versus the emerging commercial applications. . . . . . . . . . . . . . 59 3.2 Comparison of discrete and integrated transceiver designs for 22-29GHz and 77GHz vehicular radar. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.1 Comparison of measured pattern for normal transmission to theory and 8RF-DM Monte Carlo simulations. . . . . . . . . . . . . . . . . . . . . . . 156 4.2 Performance summary of the 4-channel, 24GHz 0.13m CMOS phased- array transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.3 Comparison with prior silicon-based phased-array implementations at 24GHz.161 4.4 Performance summary of the UWB 4-channel, 24-27GHz 0.13m CMOS phased-array transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.1 FCC-mandated specications for the vehicular-radar application space [34]. 197 5.2 Application-specic performance requirements for the vehicular-radar ap- plication space [51]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 vii 5.3 RF performance specications for a phased-array radar for 22-29GHz ve- hicular applications based on FCC specications assuming pulsed-sinusoid operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 5.4 Survey of moderate-dynamic-range ADCs with sampling rates larger than 1 GSa/s (courtesy [125]). ENOB is derived from (5.6). . . . . . . . . . . 202 5.5 Survey of digital matched-lter designs. The references with an asterisk(*) are designs with I and Q channels. Therefore their power dissipation is halved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.6 Comparison of the power consumptions of the analog- and digital-baseband approaches for vehicular radar. The bandwidth is assumed to be 3GHz, the duty cycle is 0.4% and the required dynamic range is 30dB. FOM ADC is assumed to be 8.2TSa/J and FOM corr is taken as 3.410 8 . . . . . . . 213 5.7 Summary of the simulated performance of the implemented 90nm CMOS 24-26GHz RF-multibeam ST-RAKE radar. . . . . . . . . . . . . . . . . . 236 viii List Of Figures 2.1 (a) Generalized block diagram of negative-resistance oscillators and the impact of noise and loss on the spectrum. (b) Reciprocal mixing in receivers due to phase noise. (c) Interference in transmitters due to phase noise. . . 7 2.2 (a) A spiral inductor in a typical silicon-based process. (b) A survey of prior art in the area of high-quality passive components, including both conventional silicon-based processes and processes with advanced process- ing steps/options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 (a) On-chip microstrip. (b) On-chip coplanar waveguide. (c) On-chip coplanar waveguide with oating metal strips. (d) On-chip coplanar waveg- uide with grounded metal strips. . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Q versus frequency for on-chip microstrips in TSMC's 0.18m CMOS pro- cess. The top metal layer, M6, is 0.99m thick, and the bottom metal layer, M1, is 0.53m thick. The spacing between them is approximately 6.5m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 On-chip coplanar stripline (CPS). . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Characterization of a few on-chip CPS structures in TSMC's 0.18m CMOS process across dierent values of width (W ) and spacing (S). (a) Induc- tance per unit length (L). (b) Resistance per unit length (R). (c) Capaci- tance per unit length (C). (d) Conductance per unit length (G). . . . . . 16 2.7 (a) Q magnetic and Q electric for on-chip CPS structures in TSMC's 0.18m CMOS process across dierent values of width (W ) and spacing (S). (b) Overall resonator Q as a function of width (W ) and spacing (S). . . . . . 17 2.8 (a) An oscillator utilizing a quarter-wavelength transmission-line resonator and a cross-coupled nMOS pair. (b) Resonator Q vs. length at 26GHz for a CPS with W=75m and S=150m. . . . . . . . . . . . . . . . . . . . . 19 ix 2.9 (a) Proposed transmission-line inductor (underlying metal strips not shown). (b) Proposed transmission-line inductor with 2 nMOS negative-Gm cells. (c) Proposed oscillator with the symmetric current-sharing active topol- ogy and nMOS open-drain output buers. The desired oscillation mode is shown. (d) Proposed oscillator with the current sharing active topology. The undesired common-mode oscillation is shown. . . . . . . . . . . . . . 20 2.10 Chip microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.11 Measured phase noise at a supply voltage of 1.8V. . . . . . . . . . . . . . 24 2.12 (a) A transformer-based resonator with in-phase currents in the primary and secondary. (b) An alternative transformer-based resonator with out- of-phase primary and secondary currents. (c) An inductor-based resonator. All Q values assume k = 1 and are calculated at the common resonance frequency of 1 p 2LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.13 (a) Spiral inductor layout and physical model. (b) Frlan transformer lay- out and physical model. The two windings are perfectly symmetric. (c) Rabjohn balun layout and physical model. The intertwined windings are asymmetric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.14 Comparison between the resonatorQs of 3 Frlan transformers, baluns and the corresponding scaled spirals. . . . . . . . . . . . . . . . . . . . . . . . 31 2.15 (a) Double-layer spiral layout. (b) Stacked transformer layout. . . . . . . 33 2.16 Resonator Q for single- and double-layer spirals and a stacked transformer with OD = 150m, w = 10m, s = 10m, n = 2. . . . . . . . . . . . . . . 34 2.17 (a) Circuit diagrams for the single-inductor- and balun-based 5 GHz oscil- lators. (b) Chip microphotograph of the two oscillators. . . . . . . . . . . 35 2.18 Measured phase noise of the two oscillators for I bias =1.28mA and V dd = V bias =1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.19 (a) Generalized LNA block diagram. (b) Matching network design for optimum NF in the lossless case. (c) Equivalent circuit for the matching network when the components have loss. . . . . . . . . . . . . . . . . . . . 39 2.20 Domain of impedances that a 50 reference can be transformed to using only inductors. The gray segments of the upper half of the Smith Chart requires the use of ideal transformers. . . . . . . . . . . . . . . . . . . . . 43 2.21 Potential E-band receiver architectures. . . . . . . . . . . . . . . . . . . . 45 x 2.22 (a) Maximum power gain for a single HBT common-emitter stage and a cascode-common-emitter pair. The emitter length of all devices is 7.5m and the bias current is 3mA. (b) NF min at 79GHz as a function of the emitter length and bias current for a cascode-common-emitter HBT pair. Both transistors of the cascode are assumed to have the same device size. 46 2.23 (a) Two possible matching networks for the optimal design point - inductor- based and transmission-line-based. (b) Noise gure (NF ) of the optimal design point with the inductor- and transmission-line-based matching net- works as Q L is varied. NF min;p is also plotted. . . . . . . . . . . . . . . . 47 2.24 LNANF for the transmission-line based matching network in the presence and absence of loss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.25 Circuit diagram of the E-band LNA. . . . . . . . . . . . . . . . . . . . . . 49 2.26 Chip microphotograph of the E-band LNA. . . . . . . . . . . . . . . . . . 50 2.27 (a) Simulated small signal gain, NF and re ection coecients for a control voltage value of 0V. (b) Simulated small signal gain, NF and re ection coecients for a control voltage value of 2V. . . . . . . . . . . . . . . . . . 50 2.28 (a) Measured small-signal S-parameters of the E-band LNA for a varac- tor control voltage of 0V. The S-parameters are measured using a 110GHz VNA. The gain is also measured using a V-/W-band scalar measurement setup. (b) Measured small-signal S-parameters for a varactor control volt- age of 2.1V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.29 Post-measurement simulation of the NF of the E-band LNA for varactor control voltage values of 0V and 2.1V. . . . . . . . . . . . . . . . . . . . . 52 3.1 Basic phased-array receiver block diagram. . . . . . . . . . . . . . . . . . 62 3.2 4-channel receiver array factor for dierent values of , namely 4! , 2 4! ... 8 4! . The inter-antenna spacing is assumed to be 2 , where is the free-space wavelength at the frequency of operation !. . . . . . . . . . . . . . . . . . 64 3.3 (a) Timed array. (b) Phased array. . . . . . . . . . . . . . . . . . . . . . . 67 3.4 The eect of the phase-shift approximation in a phased array that uses pulsed sinusoids with 5GHz of bandwidth around 25.5GHz. . . . . . . . . 69 xi 3.5 Normalized array patterns for phased arrays operating at 25.5GHz. Timed- and phased-array implementations as considered. A pulsed-sinusoid signal is assumed with a center frequency of 25.5GHz. The angle of incidence is assumed to be 60 o . (a) 8-element array with a pulse width of 200ps. (b) 16-element array with a pulse width of 200ps. (c) 16-element array with a pulse width of 500ps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.6 Architecture of the 1-13GHz SiGe UWB variable delay element. . . . . . . 72 3.7 System-level diagram of the 3-bit tapped-delay trombone line. . . . . . . . 72 3.8 The RF phase-shifting phased-array architecture. . . . . . . . . . . . . . . 75 3.9 The LO phase-shifting phased-array architecture. . . . . . . . . . . . . . . 77 3.10 The digital array architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.11 (Sample 4-element array factor (normalized to the ideal peak array gain of 16) in the presence of amplitude and phase errors. (a) Array factor in linear scale and polar coordinates. (b) Array factor in dB scale and Cartesian coordinates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.12 Standard deviation of the beam-pointing error as obtained from (3.11) and 300-iteration Monte-Carlo simulations of a conventional RF-phase-shifting array with phase =5 and 10 . The nominal phase shift of each channel is 0 , resulting in a nominal pointing angle that is normal to the array. . . . 82 3.13 (a) Standard deviation of the SLRR in a conventional RF-phase-shifting array as obtained from (3.20) and Monte-Carlo simulations. The nominal beam-pointing angle is normal to the array. (b) Theoretical 1- condence interval for the SLRR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.14 N-element RF-phase-shifting homodyne phased-array receiver with quadra- ture downconversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.15 EVM degradation, caused by discrete phases, as a function of the incidence angle, phase-shifter bits and number of elementsN. A Simulink simulation of a 16-QAM input incident on an 8-element quadrature RF-phase-shifting homodyne receiver is also shown. SNR o = 33:2dB and 3-bit phase-shifters are assumed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.1 (a) Block diagram of the Variable-Phase Ring Oscillator (VPRO). (b) MOSFET-based dierential pair implementation of a VPRO element, and the \saturation block" model for the dierential pair. (c) Dependence of VPRO oscillation frequency (! osc ) on the inter-element phase shift (). 95 xii 4.2 (a) Oscillation amplitude of an 8-element 24GHz VPRO with 0 o phase progression versus bias current. (b) Oscillation amplitude of a 24GHz VPRO versus phase progression - the phase progression is generated by considering rings of dierent sizes and incorporating 180 o sign inversion prior to feedback ( = 180 o N ). . . . . . . . . . . . . . . . . . . . . . . . . 98 4.3 Voltage waveforms of successive nodes in a 24GHz 8-element VPRO with no external phase shift. (a) All element voltages are in phase. (b)45 o phase shift between successive nodes. . . . . . . . . . . . . . . . . . . . . . 100 4.4 Principle of operation of the VPRO-PLL architecture in transmit (TX) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.5 Dependence of the 24GHz PLL PM transfer function -3dB bandwidth on the PLL division ratio, N div . The loop lter capacitances C 1 and C 2 are scaled up linearly with N div to maintain a constant ratio of PLL loop bandwidth to reference frequency. . . . . . . . . . . . . . . . . . . . . . . . 103 4.6 Principle of operation of the VPRO-PLL architecture in receive (RX) mode.105 4.7 (a) VPRO with injected and fundamental components of intrinsic currents added in vector form. (b) Taylor series approximation for LC phase-shift around the free-running frequency. . . . . . . . . . . . . . . . . . . . . . . 106 4.8 (a) Small signal model of the VPRO-PLL architecture in receive mode. (b) Simulink simulations of a 24GHz 4-channel VPRO-PLL receiver - spatial selectivity in the 0 o mode. (c) Simulink simulations of a 24GHz 4-channel VPRO-PLL receiver - frequency selectivity. . . . . . . . . . . . . . . . . . 110 4.9 (a) Input referred 1-dB compression point - theory versus Simulink sim- ulations. The nonlinear varactors are replaced with perfectly linear ones in the Simulink model to eliminate the eect of a nonlinear K vco tuning curve. (b) Eect of a nonlinear K vco tuning curve on linearity. . . . . . . 114 4.10 Graphical illustration of the time instants where V i crosses V th for = 0 o .119 4.11 Comparison of theoretical PPV with Cadence simulations using the \Direct Measurement of Impulse Response" method for a 5-element ring with 180 o phase inversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.12 (a) Time-varying small-signal equivalent noise model for a dierential pair. (b) Dierential pair NMF B. . . . . . . . . . . . . . . . . . . . . . . . . . 121 xiii 4.13 (a) Theoretical and simulated phase noise for an 8-element ring with no phase shift. (b) Phase noise dierence at 1MHz oset for rings with and without 180 o phase-inversion. . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.14 (a) Simulated phase noise at 1MHz oset for rings of dierent sizes with no phase shift (I bias = 5mA per element). (b) Simulated phase noise at 1MHz oset with a xed current budget (I bias = 50 N mA per element). . . . 125 4.15 (a) Summary of the noise processes in the VPRO-PLL receiver. (b) Injec- tion of the noise power of the reference impedance to determine NF . . . . 126 4.16 (a) Simulink dierential pair noise model. (b) ArrayNF versus device for zero inter-element phase shift andg m =10mS. (c) ArrayNF versus device g m for zero inter-element phase shift and =3. The parallel resistance of the tuned loads, and hence the Q, is scaled inversely with g m to keep the output amplitude A constant. (d) Array NF versus inter-element phase shift for g m =10mS and =3. . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.17 Standard deviation of the phase error of each element for 24GHz VPROs of dierent sizes, 0 o phase progression and independent normally-distributed capacitance errors with a standard deviation of 1%. . . . . . . . . . . . . . 134 4.18 (a) Standard deviation of the beam-pointing error versus the number of elements as obtained from (4.49) and Monte-carlo simulations of 24GHz VPROs of dierent sizes ( cap = 2fF (1%) and ext = 0 o ). (b) Standard deviation of the beam-pointing error as obtained from (4.49) and Monte- Carlo simulations of a 4-element VPRO for dierent nominal element phase shifts. The resultant nominal beam-pointing angle is also shown. . . . . . 136 4.19 Theoretical standard deviation of the beam-pointing error of a 4-element, 24 GHz, linear, nearest-neighbor-coupled oscillator array for dierent ca- pacitance errors and coupling strengths. . . . . . . . . . . . . . . . . . . . 138 4.20 (a) Depiction of the function r ij . (b) Theoretical estimate of amplitude standard deviation (normalized to the nominal amplitude) versus Simulink simulations for a 4-element 24GHz VPRO. Element capacitance errors i.i.d N(0, 2 cap ) with cap = 2fF. Theoretical amplitude standard deviation is also shown for N=6 and 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.21 SNR Reduction in the normal pointing direction due to process mis- matches in the VPRO. Maximum SNR degradation due to the quanti- zation error introduced by 4- and 5-bit phase-shifters is also shown. . . . . 142 xiv 4.22 (a) Standard deviation of the SLRR as obtained from theory and Monte- Carlo simulations of VPROs of dierent sizes ( ext =0 o ). (b) Theoretical 1- condence interval for the SLRR. . . . . . . . . . . . . . . . . . . . . . 144 4.23 Chip microphotograph and block diagram of the 4-channel 24GHz 0.13m CMOS VPRO-PLL phased-array transceiver. . . . . . . . . . . . . . . . . 145 4.24 (a) Block diagram of the VPRO. (b) Circuit diagram of each element along with input and output buers. . . . . . . . . . . . . . . . . . . . . . . . . 146 4.25 Close-in view of the VPRO layout. . . . . . . . . . . . . . . . . . . . . . . 147 4.26 (a) Measured frequency tuning characteristics of the VPRO. (b) Measured free-running phase noise of the VPRO for dierent steering angles. . . . . 147 4.27 (a) Digital frequency divider employing master-slave latches with inverted- output feedback. (b) Circuit realization of each latch. . . . . . . . . . . . 148 4.28 Circuit diagram of the implemented charge pump and loop lter. . . . . . 148 4.29 Measured spectrum of the locked VPRO. . . . . . . . . . . . . . . . . . . 149 4.30 (a) Circuit diagram of the PA of each channel. (b) Close-in view of the layout of each PA. (c) Measured large signal performance of the PA at 22GHz. (d) Measured PA small signal S-parameters. . . . . . . . . . . . . 150 4.31 (a) Circuit diagram of the LNA of each channel. (b) Close-in view of the LNA layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.32 (a) Measured gain and noise gure of the LNA. (b) Measured LNA input and output matching. (c) LNA large signal performance at 22.75GHz. . . 151 4.33 (a) Normalized VPRO spectrum when a 7MHz, small signal is applied at the PLL baseband input. (b) Normalized PLL PM response as a function of the baseband modulation frequency in transmit mode. . . . . . . . . . . 152 4.34 Measured receiver gain for a single channel. The VPRO-PLL lock fre- quency is xed at 23.37GHz and the RF input is swept in frequency. . . . 152 4.35 (a) Phase noise of a 182.6MHz reference signal generated by the Agilent E4433B Signal Generator. (b) Single-sideband (SSB) array NF of the prototype using two dierent PLL references - the Agilent E4433B Signal Generator and the UMJ-231-D14 low-noise VCO from Universal Microwave Corporation (UMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 xv 4.36 (a) Measured, single-channel, single-tone, receiver output power versus in- put power for dierent VPRO bias levels. (b) Measured single-channel, input-referred, 1-dB compression point for dierent VPRO bias levels. . . 154 4.37 (a) Probability distribution function (PDF) of the capacitance of a 100fF varactor through Monte Carlo simulations using mismatch data from IBM's 8RF-DM process. (b) PDF of the beam-pointing error from theory and Monte Carlo simulations of the implemented VPRO. . . . . . . . . . . . . 155 4.38 (a) Measurement setup for the on-wafer amplitude and phase character- ization. (b) Calibration accuracy for the on-wafer amplitude and phase characterization. Ideally, a phase dierence of 180 o and amplitude dier- ence of 0dB should be seen between the two paths. (c) Simulated nominal VPRO outputs for 0 o inter-element phase shift (normal or broadside trans- mission) and comparison with measured results. . . . . . . . . . . . . . . . 156 4.39 Measured and simulated nominal array patterns for broadside transmission and two other steering angles. . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.40 (a) Test mm-wave package for 4-channel pattern measurement. (b) Mea- surement setup for 4-channel pattern measurement. . . . . . . . . . . . . . 158 4.41 Array patterns for the packaged prototype 24GHz CMOS 4-channel VPRO- PLL transceiver in transmit mode. . . . . . . . . . . . . . . . . . . . . . . 159 4.42 Chip microphotograph and block diagram of an UWB 4-channel 24-27GHz VPRO-PLL phased-array transmitter in 0.13m CMOS. . . . . . . . . . . 162 4.43 Normalized Fourier Transform of a linear FM chirp withf 0 =24GHz,T =10ns and T =3GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.44 (a) PA circuit diagram. (b) Measured small-signal parameters for 0/180 o paths. (c) 1-bit sign inversion from small-signal S-parameter measure- ments. (d) Measured large-signal performance. . . . . . . . . . . . . . . . 164 4.45 (a) Squarer circuit diagram. (b) Simulated output power at 24GHz for a 12GHz input with varying large-signal amplitude. (c) Simulated output power versus input frequency for a xed dierential input peak amplitude of 1.6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.46 Circuit diagram of the wideband VPRO. . . . . . . . . . . . . . . . . . . . 166 xvi 4.47 SpectreRF simulation of the VPRO and its output buers when the control voltage is ramped up linearly with time to generate a chirp. The (a) instantaneous frequency, (b) instantaneous phase dierence between the VPRO node outputs and the buer outputs, (c) instantaneous amplitude of the VPRO node outputs and buer outputs and (d) frequency response of the VPRO node outputs and buer outputs are shown for two cases - the frequency control of the buers is connected to that of the VPRO/held constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.48 (a) Narrowband array patterns at 24.75GHz measured through RF probing for two active channels. (b) Measured spectra of the transmitted UWB FM beam along the expected peak and null directions when the beam is steered to -42 o . Two elements are active and two dierent signal bandwidths are considered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.49 (a) Circuit diagram of the on-chip reference oscillator. (b) Measured phase noise of the reference oscillator for various bias currents. . . . . . . . . . . 170 4.50 Measured spectrum of the on-chip reference oscillator when locked to an o-chip 93.75MHz reference. The resultant PLL lock frequency is 12GHz. 171 4.51 (a) Circuit diagram of the quadrature all-pass lter (QAF). (b) Circuit diagram of the I/Q baseband mixer. . . . . . . . . . . . . . . . . . . . . . 171 4.52 Circuit diagram of the analog mixer that serves as the phase detector for the primary dividerless PLL. . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.53 (a) Block diagram of the Variable Phase Array Oscillator (VPAO). (b) Simulink model of each VPAO element. (c) 3-D beam patterns generated from a 24 GHz 3x3 VPAO. . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.54 The VPRO-PLL combination used in a conventional RF-phase-shifting ar- chitecture for power combining and downconversion. . . . . . . . . . . . . 177 5.1 Linear beamforming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.2 Space-time coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.3 Spatial multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.4 The use of point-like foreground scatterers for more comprehensive imaging of the desired object. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.5 Spatial diversity radar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 xvii 5.6 The RF-multibeam spatio-temporal RAKE architecture. Separate I/Q paths in the baseband section are omitted for simplicity. . . . . . . . . . . 188 5.7 Timing diagram for the operation of the RF-Multibeam Spatio-Temporal RAKE architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 5.8 Communication-theoretic description of the RF-multibeam Spatio-Temporal RAKE architecture. While the transmitter and the receiver are typically co-located for radar, and share most of their resources in the RF-multibeam ST-RAKE architecture, they are represented separately in this gure as is typically done in communication systems. . . . . . . . . . . . . . . . . . . 190 5.9 2D RAKE receiver proposed for CDMA systems [64]. The slice correspond- ing to the i th user is depicted. N antennas are employed and L i multipaths are resolved for the i th user. . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.10 (a) Cross-correlation properties of modied bipolar Walsh-Hadamard se- quences of length 16. The diagonal matrix used to modify the Walsh- Hadamard matrix has the following diagonal elements: -1 1 1 1 1 -1 1 -1 -1 -1 -1 1 -1-1 -1 -1. (b) Auto-correlation properties of the modied Walsh-Hadamard sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . 194 5.11 (a) A simplied single-antenna, single-correlator, pulse-based radar with analog baseband processing. (b) Single-antenna, single-correlator, pulse- based radar with digital baseband processing. (c) A single-antenna, pulse- based radar with multiple correlators for simultaneous scanning of multiple range bins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.12 An analog correlator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 5.13 (a) SpectreRF simulations of an analog correlator implemented in IBM's 8RF 0.13m CMOS process. The schematic of the correlator is provided in Fig. 5.12. The pulse width is 200ps andC=1pF. is determined to be 2/3 from the process models. (b) Simulated dynamic range computed as the ratio of the output-referred -1dB compression point to the RMS sampled output noise voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 5.14 Block diagram of a typical digital correlator. . . . . . . . . . . . . . . . . 209 5.15 Comparison of the power consumptions of a 6GSa/s ADC, an analog corre- lator handling a 333ps pulse with = 3,V od = 0:175V andV dd = 1:2V, and a digital matched lter with a code length of 8, f CLK = 3GHz, L = 80nm and V dd = 1:2V. The gures of merit for the ADC and digital matched lter are obtained from the surveys presented earlier. . . . . . . . . . . . . 212 xviii 5.16 Chip microphotograph of the experimental 90nm CMOS 24-26GHz RF- multibeam ST-RAKE radar. . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.17 Block diagram of an experimental 90nm CMOS 24-26GHz RF-multibeam ST-RAKE radar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 5.18 Circuit diagram of the T/R switch. . . . . . . . . . . . . . . . . . . . . . . 217 5.19 Chip microphotograph of the T/R switch. The coupled CPWs are bent substantially to minimize their area consumption. . . . . . . . . . . . . . . 218 5.20 (a) Simulated small-signal performance of the T/R switch. Port 3 is en- abled and port 2 is disabled. (b) Simulated large-signal T/R switch per- formance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.21 (a) Circuit diagram of the four-stage LNA. (b) Chip microphotograph of the LNA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 5.22 (a) Circuit diagram of the single-stage pseudo-dierential PA. (b) Chip microphotograph of the PA. . . . . . . . . . . . . . . . . . . . . . . . . . . 221 5.23 (a) Simulated small-signal S-parameters of the PA-LNA-T/R switch com- bination in receive mode. (b) Simulated large-signal performance of the PA-LNA-T/R switch combination in receive mode. . . . . . . . . . . . . . 222 5.24 (a) Simulated small-signal gain of the PA-LNA-T/R switch combination in transmit mode. (b) Simulated large-signal performance of the PA-LNA- T/R switch combination in transmit mode. . . . . . . . . . . . . . . . . . 223 5.25 (a) The Blass Matrix. (b) Chu's mulitbeam architecture for the simple case of two antennas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 5.26 (a) A 4-input, 4-output Butler matrix. (b) Implemented -3dB quadrature branchline hybrids. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 5.27 (a) Chip microphotograph of the implemented -3dB quadrature branchline hybrid. (b) Simulated insertion loss to through and coupled ports. (b) Simulated re ection coecient and isolation to the isolated port. (d) Phase dierence between through and coupled ports. . . . . . . . . . . . . . . . . 226 5.28 Synthesized normalized UWB array patterns of the 44 Butler matrix from measured S-parameter data. . . . . . . . . . . . . . . . . . . . . . . . 227 5.29 Chip microphotograph and block diagram of each beam's baseband block - transmit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 xix 5.30 Chip microphotograph and block diagram of each beam's baseband block - receive mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 5.31 (a) Schematic diagram of the passive mixer in each baseband I/Q sub- block. (b) Simulated large-signal downconversion performance of the pas- sive mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.32 Schematic diagram of the 25GHz VCO employed for I/Q LO generation. . 230 5.33 Circuit diagram of the LO distribution network. . . . . . . . . . . . . . . 231 5.34 (a) Measured frequency tuning characteristic of the I/Q VCO. All calibra- tion bits are set to 0/1. The simulated tuning range when all bits are 0 is also depicted. (b) Simulated and measured phase noise performance when the control voltage is set to 1.2V and all calibration bits are set to 0. . . . 233 5.35 Simulated I/Q phase dierence as a function of mismatch capacitance. . 233 5.36 (a) Circuit diagram of the TX modulator. (b) Circuit diagram of the analog correlator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.37 Circuit diagram of the analog integrator. . . . . . . . . . . . . . . . . . . 235 A.1 (a) g m for dierent emitter length and bias current values. (b) C b for dierent emitter length and bias current values. . . . . . . . . . . . . . . . 259 A.2 Parasitic emitter, base and collector resistances (r e ,r b andr c ) as a function of the emitter length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 A.3 (a)f max for dierent emitter length and bias current values. (b)NF min for dierent emitter lengths. The bias current is 3mA for an emitter length of 2.5m, 10mA for 7.5m and 20mA for 15m. These bias currents maximize the f max for each emitter length. . . . . . . . . . . . . . . . . . . . . . . . 260 A.4 Metallization stack of 8HP. Metal layers M1 through MQ are copper. LY and AM are aluminium. . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 A.5 Characteristics of a few 8HP CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, AM, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. (a) Characteristic impedance (Z 0 ). (b)Q of a quarter- wavelength CPS resonator, computed as 2 . (c) Attenuation constant (). (d) Wavelength (). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 xx A.6 Metallization stacks for the DM and LM avors of 8RF. All metal layers are copper, except for MA, which is aluminium. . . . . . . . . . . . . . . . 263 A.7 (a) Drain current versus V ds for a 1000.48m/120n IBM 8RF nFET for dierent V gs values. (b) g m versus V gs for a 1000.48m/120n IBM 8RF nFET for dierent V ds values. . . . . . . . . . . . . . . . . . . . . . . . . 264 A.8 (a) Gate capacitance and gate resistance for dierent number of ngers. The total width is kept constant at 48m. (b) Maximum oscillation fre- quency (f max ) as function of the device bias current and the device aspect ratio. The total device width is kept constant at 48m. . . . . . . . . . . 264 A.9 (a) Drain-current thermal noise as a function of the device bias point for a 1000.48m/120n nFET. (b) Device excess noise factor ( ) as a function of V gs for a 1000.48m/120n nFET with V ds =1.2V. . . . . . . . . . . . . 265 A.10 Characteristics of a few 8RF-LM CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, LM, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. (a) Characteristic impedance (Z 0 ). (b) Q of a quarter-wavelength CPS resonator, computed as 2 . (c) Attenuation constant (). (d) Wavelength (). . . . . . . . . . . . . . . . . . . . . . . 266 A.11 (a) Drain current versus V ds for a 1000.36m/100n IBM 9RF-LP nFET for dierent V gs values. (b) g m versus V gs for a 1000.36m/100n IBM 9RF-LP nFET for dierent V ds values. . . . . . . . . . . . . . . . . . . . 268 A.12 (a) Gate capacitance and gate resistance for dierent number of ngers. The total width is kept constant at 36m. (b) Maximum oscillation fre- quency (f max ) as function of the device bias current and the device aspect ratio. The total device width is kept constant at 36m. . . . . . . . . . . 268 A.13 Minimum noise gure (NF min ) for a 500.72m/100n 9RF-LP nFET for dierent bias currents. V ds =1.2V and V gs is varied to achieve the bias currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 A.14 Metallization stack for 9RF-LP. All metal layers are copper. . . . . . . . . 270 A.15 Characteristics of a few 9RF-LP CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, LB, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. (a) Characteristic impedance (Z 0 ). (b)Q of a quarter- wavelength CPS resonator, computed as 2 . (c) Attenuation constant (). (d) Wavelength (). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 xxi Abstract This thesis presents unique architectures for the implementation of multiple-antenna sys- tems at millimeter-wave frequencies on silicon-based processes. Passive components play a key role in virtually every RF building block of a wire- less transceiver. An overview of distributed passive components that are suitable for millimeter-wave operation on silicon-based processes is provided in this thesis. A 0.18m CMOS 26GHz complementary current-sharing oscillator topology is presented that, in conjunction with a high-quality coplanar-stripline-based resonator, achieves state-of-the- art phase-noise performance. The use of transformers to build high-quality integrated resonators is investigated. It is found that, contrary to prior claims, integrated trans- formers achieve no improvement over single spiral inductors in resonator quality factor (Q) when subject to area and eective-inductance constraints. A theoretical formulation for the impact of passive loss on the noise performance of low-noise ampliers (LNAs) is also developed. A 0.13m SiGe E-band low-noise amplier is implemented to support the formulation. A Variable-Phase Ring Oscillator and Phase-Locked Loop (VPRO-PLL) architec- ture for integrated phased arrays is presented. The nonlinear multi-functional circuit xxii eliminates key phased-array-transceiver building blocks, such as mixers, power split- ters/combiners and phase shifters, by harnessing the injection-locking properties of a tuned ring oscillator locked in a PLL. A detailed theoretical analysis of performance metrics, such as sensitivity, linearity and array performance in the presence of process mismatches, is given. Experimental results from two highly-integrated phased-array pro- totypes, implemented in 0.13m CMOS and operating in the vicinity of 24GHz, are pro- vided. The prototypes achieve similar functionality to prior works at the same frequency, but consume a fraction of the area and power. An RF-Multibeam Spatio-Temporal RAKE (ST-RAKE) transceiver architecture for radar is proposed. The architecture exploits orthogonal codes in conjunction with an RF- multibeam matrix to isolate not only line-of-sight re ections but multipath re ections as well to glean more information about the scene being imaged. A highly-integrated, 4- channel, 90nm CMOS, 24-26GHz prototype that targets vehicular-radar applications is implemented to validate the principle of the architecture. The prototype is expected to serve as a testbed for future studies pertaining to code and waveform design for such MIMO radars. xxiii Chapter 1 Introduction We live in the information age. This is an age where information is more valuable than most physical commodities, an age where the public's desire for information is the closest thing to a truly innite entity. As a result, from the point of view of wireless systems, most avenues of research attempt to enhance the information capacity of the link. A direct way to enhance the capacity of a wireless link is to increase the bandwidth. It is this thirst for bandwidth that motivated the desire of both industry and academia to push silicon into the millimeter-wave regime, as larger bandwidths are a direct con- sequence of higher carrier frequencies. The rapid scaling of silicon-based technologies has resulted in silicon-based transistors that are capable of operating reliably at these frequencies. There are other fringe benets associated with millimeter-wave operation as well. The smaller wavelengths at these frequencies imply smaller components, which in turn reduces cost. These advantages have started a wave of commercial millimeter-wave applications that range from multi-gigabit-per-second personal area networks for home multimedia to vehicular-radar sensors for collision avoidance and parking assistance. 1 The investigation of silicon-based millimeter-wave systems has, in turn, sparked an interest in multiple-antenna systems. Virtually every commercial millimeter-wave appli- cation has to rely on multiple-antenna systems for reliable operation. Multiple-antenna systems enhance the reliability of a wireless link in several ways. The simplest multiple- antenna system, namely, the phased array, enhances the signal-to-noise ratio (SNR) through the formation of electronically-steerable directional beams at the transmitter and/or receiver that focus the signal in the desired direction. The phased array also oers spatial immunity to interference. This thesis presents novel architectures for the implementation of multiple-antenna systems on silicon-based processes. These architectures harness the power of silicon in- tegration to enhance functionality or oer functionality at a reduced area and power consumption. The contributions of this thesis include not only a detailed theoretical treatment of the architectures, but experimental implementations as well that validate the theoretical ndings. 1.1 Organization The performance of passive components on silicon is limited by the conductive nature of the silicon substrate and the interconnect stack available in commercial silicon-based processes. As frequencies of operation enter the millimeter-wave regime, the conventional lumped passive components that are popular at lower frequencies must be abandoned in favor of distributed elements such as transmission lines. In Chapter 2, a survey of dis- tributed silicon-based passive components is provided. A complementary current-sharing 2 oscillator topology is introduced that enables the realization of a high-quality coplanar- stripline-based resonator for enhanced phase-noise performance. A 26GHz prototype that achieves state-of-the-art phase-noise performance is implemented in a 0.18m CMOS pro- cess. The use of integrated transformers to build high-quality passive resonators is inves- tigated. While circuit theory predicts the potential for quality-factor (Q) enhancement, it is shown that on-chip constraints, such as substrate parasitics and area constraints, pre- vent transformer-based resonators from achieving any improvement in Q over resonators based on lumped spiral inductors. A theoretical formulation for the impact of passive loss on the noise performance of low-noise ampliers (LNAs) is also developed. This formula- tion leads to a new minimum-noise-gure metric (NF min;p ) for processes that combines the characteristics of the active and passive devices available in the process. Guidelines to achieveNF min;p are included. An E-band LNA is implemented in a 0.13m SiGe process to support the formulation. In Chapter 3, an overview of the history of phased arrays is provided and the need for silicon-based millimeter-wave phased arrays for commercial applications is motivated. The state of the art in silicon-based phased arrays is brie y reviewed, and various system- level characteristics, such as the eect of mismatch on array performance and quantization error, are studied. Chapter 4 describes the Variable-Phase Ring Oscillator and Phase-Locked Loop (VPRO- PLL) architecture for integrated phased arrays. The architecture achieves full phased- array-transceiver functionality using nothing more than a modied tuned ring oscillator locked in phase-locked loop. This is accomplished by harnessing the nonlinear injection- pulling characteristics of the locked tuned ring oscillator. A detailed theoretical analysis 3 of performance metrics, such as sensitivity, linearity and array performance in the pres- ence of process mismatches, is given. Experimental results from two highly-integrated phased-array prototypes are provided. The prototypes achieve similar functionality to prior works at the same frequency, but consume a fraction of the area and power. The rst is a narrowband, 4-channel, 0.13m CMOS, VPRO-PLL phased-array transceiver operating in the vicinity of 24GHz, The second is a 4-channel, 0.13m CMOS, VPRO- PLL phased-array transmitter that extends the VPRO-PLL architecture to support UWB modulation. Chapter 5 introduces an RF-multibeam Spatio-Temporal RAKE transceiver architec- ture for radar. The architecture is inspired by Multiple-Input, Multiple-Output (MIMO) communication techniques, and utilizes orthogonal codes in conjunction with an RF- multibeam spatial lter to isolate the Line-of-Sight (LoS) and multipath re ections. It is anticipated that the collection and separation of LoS and multipath re ections will not only simplify the radar image-reconstruction problem in a multipath environment, but also provide additional information regarding the objects in the environment. Multibeam transceivers are potentially power hungry since each beam requires a separate baseband signal processor. To this end, the trade-os between analog and digital signal process- ing for radar are studied. These trade-os are particularly signicant in the context of technology scaling to determine the optimal partitioning of signal processing across the analog and digital domains for future applications. A highly-integrated, 4-channel, 90nm CMOS, 24-26GHz prototype that targets vehicular-radar applications is implemented to validate the principle of the architecture. Finally, Chapter 6 concludes this thesis by summarizing the technical contributions. 4 Chapter 2 Passive Components on Silicon at mm-Wave Frequencies Passive elements are critical components in the design of radio-frequency (RF) building blocks such as oscillators, low-noise ampliers (LNAs) and power ampliers (PAs). In- deed, the quality of passive components on silicon has been a signicant research topic for the past decade and a half [137], [81]. Traditonally, at frequencies below the millimeter- wave regime 1 , lumped passive components, such as inductors and capacitors, have been favored in the design of silicon-based RF building blocks. The lumped spiral inductor has been the performance-limiting element, and hence, the target of research eorts. However, as silicon-based technologies have pushed their way into the millimeter-wave regime, distributed passive components, such as transmission lines, have become viable design components. This chapter describes an investigation of the fundamental loss mechanisms in passive components on silicon, with a focus on distributed passive components. A complemen- tary, current-sharing oscillator architecture is then introduced that enables the realization of a high-quality transmission-line resonator. The combination of the architecture and 1 The millimeter-wave regime is dened as the range of frequencies over which the free-space wavelength ranges from 1 to 10mm. Therefore, it extends from 30GHz to 300GHz. 5 the high-quality resonator enable the realization of a low-phase-noise 26GHz oscillator in a 0.18m CMOS process. The use of integrated transformers to realize high-quality resonators is then investigated. Finally, the chapter ends with a formulation that quan- ties the impact of passive-element loss on the noise gure (NF ) of LNAs. A new minimum-NF metric (NF min;p ) for processes is proposed that incorporates the quality of the passive elements available in the process. An E-band LNA is implemented in a 0.13m SiGe process to support the formulation. 2.1 Impact of Passive-Element Loss on Dierent RF Building Blocks In LNAs and PAs, passive components are utilized for input- and output-impedance matching or impedance transformation. The quality of the passive components 2 has a direct impact on the noise performance of the LNA. This is especially true of the passive components employed in the input matching circuit. In the case of PAs, the quality of the passive components employed in the output impedance transformation limits the output power delivered by the PA, and hence, the PA's eciency. Fig. 2.1(a) depicts a generalized view of negative-resistance RF oscillators. Passive elements are used to construct a resonator at the desired frequency of operation, and active devices are used to generate a negative resistance. An oscillation is sustained across the resonator since the negative resistance replenishes the energy that is lost in the resonator in each cycle due to the loss of the resonator. Ideally, the spectrum of such 2 The quality of a passive component is usually determined by the amount of loss present. Ideally, passive elements should exhibit no loss. 6 Figure 2.1: (a) Generalized block diagram of negative-resistance oscillators and the impact of noise and loss on the spectrum. (b) Reciprocal mixing in receivers due to phase noise. (c) Interference in transmitters due to phase noise. an oscillator is a single tone at the oscillation frequency. However, the noise and loss associated with the active and passive devices cause a spreading of the spectrum of the oscillator, also depicted in Fig. 2.1(a). In the context of wireless transceivers, this spectral spreading has several adverse con- sequences. In receivers, it can cause reciprocal mixing (Fig. 2.1(b)) - a strong interference signal that is close in frequency to a weak, desired signal masks the desired signal when downconverted by a noisy local oscillator (LO). In transmitters, it results in interference, which, in principle, is the same as reciprocal mixing. A powerful transmitter can mask a weak transmitter due its spread transmitted spectrum (Fig. 2.1(c)). 7 2.1.1 Phase Noise and Resonator Quality Factor The most commonly-used metric to characterize the spectrum of an oscillator is the single-sideband noise spectral density that is dened as Lf!g = P (! 0 + !; 1Hz) P carrier ; (2.1) whereP (! 0 +!; 1Hz) is the power contained in a 1Hz bandwidth at an oset of ! from the carrier at ! 0 and P carrier is the total carrier power. This quantity is the cumulative eect of uctuations in the amplitude and phase of the output signal. However, for practical electrical oscillators, the contribution of phase uctuations dominates over that of amplitude uctuations, in part due to the amplitude-limiting action of the nonlinear active devices [57]. Therefore,Lf!g is commonly referred to as phase noise. The quality of a passive resonator, on the other hand, is quantied through its Quality Factor (Q resonator ), which is dened as Q resonator =! 0 E stored P loss ; (2.2) where ! 0 is the resonance frequency, E stored is the energy stored in the resonator and P loss is the power lost due to resistive parasitics. It should be noted that denition of the quality factor of a resonator is distinct from the denition of the quality factor of a single passive component, such as an inductor or capacitor. The latter is typically dened as the absolute value of the ratio of the imaginary portion of the input impedance/admittance to the real portion. The input admittance of a passive one-port network, at sinusoidal steady-state, is given by 8 G in +jB in = 2P loss + 4j!(E E E H ) j Vj 2 ; (2.3) where P loss , E E and E H are the power dissipated, average stored electric energy and average stored magnetic energy, respectively, in that network at the frequency of operation !, and V is the voltage vector at the port [102]. Therefore, the quality factor of a component, such as an inductor or a capacitor, is given by Q ind=cap = 2!jE E E H j P loss : (2.4) The physical meaning of this denition is similar to that of the quality factor of a res- onator, except that it is related to the stored energy in only the desired mode 3 . For a simple inductor L with a series parasitic resistance R at a frequency of !, this de- nition reduces to Q ind = !L R . Furthermore, for a resonator that is essentially a parallel combination of a lossy inductor and capacitor, one may obtain 1 Q resonator = 1 Q ind + 1 Q cap : (2.5) For the remainder of this thesis, the term \quality factor" and the symbol Q will be used for both denitions, and the meaning will either be stated explicitly or can be determined implicitly from the context. Several theories have been proposed to explain the phase-noise behavior of electrical oscillators [57],[79],[36]. Some of these theories are visited in greater detail in the Chapter 3 For a pure inductor, the desired mode is magnetic energy storage and EE = 0. Capacitive parasitics in an inductor cause a reduction in Q ind . Correspondingly, for a pure capacitor, EH = 0. 9 4. For the purposes of this chapter, it suces to mention that an improvement in the Q of the passive resonator of a negative-resistance oscillator results in an improvement in the phase-noise performance, which explains the extensive research eorts that have been dedicated to high-quality silicon-based passive elements. 2.2 Survey of State-of-the-Art Passive Elements on Silicon To understand the limitations imposed by current silicon-based fabrication processes on the achievable Q of passive components, it is instructive to take a eld-theoretic view of Q. From Maxwell's equations, for a resonator, we have E stored = 1 2 Z V jEj 2 dV + 1 2 Z V jHj 2 dV; (2.6) P loss = Z S m 2 jH tan j 2 dS + 1 2 Z V d jEj 2 dV + Radiation Loss : (2.7) The volumeV represents the region of space over which the elds of the resonator extend, E and H are the electric- and magnetic-eld intensities, respectively, and , and d are the material permittivity, permeability and conductivity, respectively. The surface S represents the conductor surfaces used to construct the resonator, m and are the conductor's resistivity and skin depth, respectively, andH tan is the magnetic eld strength tangential to the conductor surface. 10 The limitations imposed by current silicon-based processes can be classied into two categories - geometric limitations and material limitations. The appendix contains a char- acterization of several silicon-based processes employed in the various works described in this thesis. Included are the Back-End-Of-The-Line (BEOL) metallization stacks avail- able in each of these processes. The limited vertical spacing between the various metals (a geometric limitation) restricts the volume available to store electromagnetic energy. Further, the resonator loss is limited by the nite conductivities of the metals available, typically aluminium or copper, and the dielectric loss of the silicon substrate (material limitations). Figure 2.2: (a) A spiral inductor in a typical silicon-based process. (b) A survey of prior art in the area of high-quality passive components, including both conventional silicon-based processes and processes with advanced processing steps/options. As was mentioned earlier, the traditional approach to the design of integrated res- onators at frequencies below the millimeter-wave regime involves the use of lumped in- ductors and capacitors, with the inductor conventionally realized as a spiral. Fig. 2.2(a) depicts the parasitics associated with a spiral inductor in a typical silicon-based process. The nite conductivity of the metal layer used to realize the spiral results in a series 11 resistance. Due t0 skin and proximity eects, this series resistance typically increases with frequency. In addition, the silicon substrate contributes resistive and capacitive par- asitics that degrade the Q, especially at higher frequencies. Finally, an induced current ows on the surface of the silicon substrate (the so-called eddy current) and this produces additional loss. Fig. 2.2(b) depicts the optimum Q that is achievable in TSMC's 0.18m CMOS process as a function of frequency. The metallization stack of this process features a top metal layer, M6, that is 0.99m thick and 7.8m above the substrate. The opti- mization is performed in ASITIC [94], an inductor- and transformer-optimization tool, and the desired inductance value is scaled down linearly with frequency, ranging from 5nH at 1GHz to 100pH at 50GHz. The area used for the spiral is swept as a part of the optimization. Fig. 2.2(b) also depicts state-of-the-art inductor/resonator Qs from the literature in both conventional silicon-based processes and processes with advanced processing steps/features. As is expected, extremely high Qs are possible in advanced processes, which typically employ insulating substrates such as sapphire or borosilicate glass. The works that employ conventional silicon-based processes, aside from a few innovative outliers, tend to follow the optimum-spiral-inductor curve. At high frequencies, as wavelengths become smaller, on-chip distributed resonator topologies relying on various forms of transmission lines, such as microstrips, become viable design options. Figs. 2.3(a)-(d) depict several on-chip transmission-line structures. The rst is the microstrip, which consists of a signal conductor atop a ground plane. The signal conductor is typically implemented in the top metal layer, due its increased thickness in conventional silicon processes, and the ground plane is implemented in the lowest metal layer. Fig. 2.3(b) depicts the coplanar waveguide, where the return path 12 Figure 2.3: (a) On-chip microstrip. (b) On-chip coplanar waveguide. (c) On-chip coplanar waveguide with oating metal strips. (d) On-chip coplanar waveguide with grounded metal strips. is implemented as lateral ground shields on either side of the signal conductor. Figs. 2.3(c) and (d) show variants of the coplanar waveguide. In the transmission line depicted in Fig. 2.3(c), oating metal strips are included underneath the waveguide [25]. These strips increase the capacitance per unit length of the transmission line, and hence reduce the wave velocity. As a result, a shorter length of line is required to obtain a given delay or phase shift, which reduces the insertion loss. Furthermore, the strips shield the transmission line from the lossy substrate, which improves the quality factor and further reduces the insertion loss. In the transmission line depicted in Fig. 2.3(d), these strips are connected to the lateral ground shields, which slows the wave further. 13 Figure 2.4: Q versus frequency for on-chip microstrips in TSMC's 0.18m CMOS process. The top metal layer, M6, is 0.99m thick, and the bottom metal layer, M1, is 0.53m thick. The spacing between them is approximately 6.5m. For quarter-wavelength, resonant on-chip microstrips, if the conductor width, W , is reasonably larger than the vertical distance between the metal layers, d, the Q can be approximated with Q = 1 R !L + G !C = !d 1 1 + 2 2 : (2.8) R, L, C and G are the resistance, inductance, capacitance and conductance per unit length, respectively. is the permeability of silicon oxide, 1 and 2 are the resistivities of the metal layers used for the signal and ground conductors, respectively, and 1 and 2 are the skin depths of the signal and ground metals, respectively, at the frequency of interest !. As can be seen in (2.8), the quality factor of on-chip microstrip resonators is largely independent of the conductor widthW and is limited by the vertical distance between the 14 metal layers (geometric limitation). Fig. 2.4 depicts the theoretical microstrip resonator Q in TSMC's 0.18m CMOS process from (2.8), assuming the signal and ground lines are in the top and bottom metal layers, respectively 4 , and compares it with electromagnetic (EM) simulations in IE3D, a Method-of-Moments based EM simulator 5 [84]. Figure 2.5: On-chip coplanar stripline (CPS). Fig. 2.5 depicts the coplanar stripline, which is the dierential version of the coplanar waveguide, with oating strips underneath. Coplanar structures promote more exible control over the RLCG parameters, which allows for higher Q values. Series resistance (R) in these structures primarily depends on the width of the conductors (W ). Series inductance (L) is primarily a function of the horizontal spacing (S) between the conduc- tors, since it depends on the available area for magnetic ux linkage. Shunt capacitance (C) is primarily attributable to the parallel-plate capacitance between the conductors and the shielding strips, and hence depends on W . The shunt loss (G) is mainly caused by the substrate loss and increases with W and S, due to an increased coupling to the substrate. Figs. 2.6(a)-(d) present a characterization of a few CPS structures in TSMC's 4 A conductor width of 50m is assumed. The top metal layer, M6, is 0.99m thick, and the bottom metal layer, M1, is 0.53m thick. The spacing between them is approximately 6.5m. 5 IE3D simulations are used to obtain the two-port Y-parameters of a certain length of the microstrip. From the two-port Y-parameters, the RLCG transmission-line parameters are determined. Q is then determined using the formula Q = 1 R !L + G !C . 15 Figure 2.6: Characterization of a few on-chip CPS structures in TSMC's 0.18m CMOS process across dierent values of width (W ) and spacing (S). (a) Inductance per unit length (L). (b) Resistance per unit length (R). (c) Capacitance per unit length (C). (d) Conductance per unit length (G). 0.18m CMOS process for dierentW andS values at 26GHz 6 , based on electromagnetic simulations in IE3D. The two signal lines are implemented in M6, and the oating strips are in M1 and are 10m wide and 10m apart. In any resonator, energy is stored in the electromagnetic eld and alternates between the magnetic and electric components. One can dene the quality factor of each energy- storing component as 6 26GHz is the operating frequency of the coplanar-stripline-based current-sharing low-noise oscillator presented later in this chapter. 16 Figure 2.7: (a) Q magnetic and Q electric for on-chip CPS structures in TSMC's 0.18m CMOS process across dierent values of width (W ) and spacing (S). (b) Overall resonator Q as a function of width (W ) and spacing (S). Q magnetic =! 2E H P loss H ; Q electric =! 2E E P loss E ; (2.9) where E H , P loss H , E E , and P loss E are the stored energy and loss associated with the magnetic and electric elds, respectively. The resonator Q can then be expressed as Q = 1 1 Q magnetic + 1 Q electric : (2.10) For quarter-wavelength, transmission-line resonators, Q magnetic = !L R and Q electric = !C G . The design of an optimal CPS resonator involves a trade-o between Q magnetic and Q electric . As can be seen from Fig. 2.7(a), CPSes with large W and S have good magnetic energy storage capability, while CPSes with small W and S have good electric energy storage capability. In TSMC's 0.18m CMOS process, the optimal dimensions for 17 a quarter-wavelength CPS resonator at 26GHz are W =100m and S=100m, resulting in a quality factor of about 42. 2.3 A Coplanar Stripline-based Complementary Current- Sharing Oscillator at 26GHz in a 0.18m CMOS process This section describes a CPS-based oscillator topology that is capable of achieving low phase noise at extremely-high frequencies. The prototype oscillator uses a complementary, current-sharing active topology and a high-Q CPS inductor in TSMC's 0.18m CMOS process, which does not oer any advanced process features such as a thick analog metal layer. The 26GHz prototype achieves a phase noise of -110dBc/Hz at 1MHz oset, while drawing a current of 3.36mA from a 1.8V supply. 2.3.1 CPS-based Resonator Design Fig. 2.8(a) depicts an oscillator utilizing a quarter-wavelength transmission-line resonator and a cross-coupled nMOS pair. At high frequencies, the active devices in the oscillator add a considerable capacitance to the resonator that lowers the oscillation frequency. On the other hand, a transmission line of length less than 4 would behave inductively and can resonate with the parasitic capacitance of the active devices. It can be seen from (2.10) that, as the transmission line length is reduced (and the active device size increased to maintain a constant resonance frequency), the resonatorQ would approach !L R , assuming that the parasitic capacitances of the actives have insignicant loss associated with them. This can be explained by the fact that, as the length is reduced, a greater portion of the 18 electric energy is stored in the actives. Further, if the transmission line is implemented as a CPS, since the line is only expected to store magnetic energy, one can now design a CPS with large W and S that achieves a high Q magnetic value. Fig. 2.8(b) shows the variations of the resonator Q at 26GHz with length for such a CPS with W=75m and S=150m. At low lengths, the resonator Q is around 55, which is substantially higher than the optimum Q of 42 achieved by the 4 resonator 7 . Figure 2.8: (a) An oscillator utilizing a quarter-wavelength transmission-line resonator and a cross-coupled nMOS pair. (b) Resonator Q vs. length at 26GHz for a CPS with W=75m and S=150m. Reducing the CPS length reduces the equivalent parallel inductance, and therefore parallel resistance, of the resonator. A larger bias current is then needed to maintain rail- to-rail swing for the reduced-length CPS resonator. Therefore, a xed current budget establishes a lower-bound on the CPS length. Based on a rst-order current budget of 7 The active parasitic capacitances can no longer be assumed to be lossless as the oscillation frequency approaches the fmax of the active devices. At the frequency of interest, namely 26GHz, the loaded Q (which factors in the loss of the actives), determined from small-signal schematic simulations, reduced from 55 to 44 in the case of the low-length CPS inductor, and from 42 to 34 in the case of the optimal 4 resonator. 19 Figure 2.9: (a) Proposed transmission-line inductor (underlying metal strips not shown). (b) Proposed transmission-line inductor with 2 nMOS negative-Gm cells. (c) Proposed oscillator with the symmetric current-sharing active topology and nMOS open-drain out- put buers. The desired oscillation mode is shown. (d) Proposed oscillator with the current sharing active topology. The undesired common-mode oscillation is shown. 2.5mA, a length l of 250m was chosen for the CPS with W=75m and S=150m for the prototype chip. The CPS needs to be tapered inwards to facilitate connection to the transistors inside the oscillator core. The choice of the \taper height" (h, as shown in Fig. 2.9(a)) is not straightforward. Assuming that the CPS inductor primarily stores magnetic energy, the total inductance, L t , and resistance, R t , can be computed, to rst-order, as 20 L t = Z l 0 L(S(z)) cos((z))dz; R t = Z l 0 R(S(z))dz: (2.11) The inductance and resistance per unit length (L(S(z)),R(S(z))), as functions of the spacing, are obtained through the aforementioned electromagnetic simulations. The inductance integral is weighted with a cosine term to account for the fact that only the vertical components of the currents in either conductor couple with each other. The goal is to nd a taper height that maximizes Q magnetic = !Lt Rt . There exists a trade-o in the choice of h; choosing h to be small minimizes the region that possesses a low L R ratio but also worsens the coupling in that region, since the vertical components of the currents are smaller. For the chosen CPS, a taper height of 70m was found to be optimal. The implementation of a perfect electrical short circuit (Fig. 2.9(a)) is a signicant challenge, especially when large W and S are used. Andress et al. dealt with this problem by strapping all underlying metal layers under the short circuit to reduce the series resistance [8]. In the case of our CPS inductor, the rather long \short" circuit represents a transmission-line segment whose magnetic eld does not couple well with the rest of the CPS. To address this problem, a topological solution is employed - the CPS is re ected vertically to form two inductors that share their current. The symmetry of the inductors provides a virtual perfect short circuit, and each inductor can be connected to a negative-Gm cell. The schematics of the proposed topology are shown in Figs. 2.9(b)-(d). A nal EM simulation of the chosen dual-CPS structure, with a total length of 500m, revealed an unloaded Q of 47 at 26GHz. 21 2.3.2 Current Sharing Oscillator Topology The dual-CPS structure requires two negative-Gm cells, one for each inductor. Two options present themselves as possible solutions - two nMOS cells, as shown in Fig. 2.9(b), and a complementary nMOS-pMOS structure, as shown in Fig. 2.9(c). In the rst topology shown in Fig. 2.9(b), with two nMOS cross-coupled dierential pairs, the oscillator is able to sustain a low-frequency parasitic mode formed through the wirebonds. These parasitic oscillations can be killed through on-chip resistances placed in series with the wire-bonds. This topology also requires twice the current needed by the design shown in Fig. 2.9(c) in order to sustain the same voltage swing. In the latter, the nMOS and pMOS cross-coupled dierential pairs share their DC current, as opposed to rst option, where each nMOS pair draws DC current from the supply 8 . In addition, the complementary, current-sharing structure performs better icker-noise ( 1 f - noise) cancellation [78], leading to substantially better phase-noise performance. This was veried through SpectreRF simulations in Cadence. Hence, the complementary structure is the preferred choice. No explicit current source was implemented in the prototype and the bias current is purely determined by the device sizes and the V dd value. This was done to eliminate the noise associated with the current source and the voltage drop across it, thus providing more voltage headroom and allowing for larger bias currents. The larger bias current leads to larger voltage swings, improving phase-noise performance [61]. 8 For the same device sizes, the maximum voltage swing of the oscillator in Fig. 2.9(b) is two-times larger when compared to the oscillator in Fig 2.9(c) at the expense of quadrupling the current. 22 The complementary, dual-CPS-based oscillator suers from a potential DC latch-up problem as there is no mechanism to prevent one side from settling at V dd and the other side at ground. To prevent this from happening, the two sides of the CPS are connected at their central points (A and B), forcing them to be at the same DC potential. This central connection could, however, result in a common-mode oscillation, with the currents adding up in the central connection as shown in Fig. 2.9 (d). To kill the common-mode oscillation, a 100 resistor is added in series with the central connection. The quality factor in the desired dierential mode remains unaected, since nodes A and B are virtual grounds in that mode; this was veried through EM simulations. 2.3.3 Experimental Verications The prototype chip was fabricated in TSMC's 0.18m CMOS process [68]. The chip dimensions are 1.0mm x 0.6mm (Fig. 2.10). Figure 2.10: Chip microphotograph. The nMOS open drain buers shown in Fig. 2.9(c) were connected to a spectrum analyzer with a built-in phase noise measurement system via RF GS probes, cables and 23 Figure 2.11: Measured phase noise at a supply voltage of 1.8V. bias tees. The oscillator core drew a current of 3.36mA from a 1.8V supply, and the oscillation frequency was measured to be 26.096GHz. The phase noise was measured to be -110dBc/Hz at 1MHz oset. Measurements were also carried out for a supply voltage of 1.5V; the core drew a current of 1.65mA and achieved a phase-noise performance of -104dBc/Hz at 1MHz oset from the 26.215GHz oscillation. The measured phase noise has been shown for 1.8V supply in Fig. 2.11. Table 2.1: Survey of state-of-the-art oscillators/VCOs operating above 10GHz. Work f osc f L (f) P dc FOM Technology VCO? (GHz) (MHz) (dBc/Hz) (mW) [26] 39.75 1 -108.65 6 -192.86 0.18m CMOS Yes This Work 26.2 1 -110 6.05 -190.55 0.18m CMOS No [124] 28.14 1 -112.9 14.4 -190.30 0.13m CMOS Yes [66] 10.8 1 -118.67 11.83 -188.61 0.18m CMOS Yes [43] 21.8 1 -116 27 -188.46 0.12m SiGe Yes [8] 15 1 -110 4.68 -186.82 0.18m CMOS No [22] 32.74 1 -99 2.64 -185.09 0.12m SiGe Yes [43] 67.3 1 -102 24 -184.76 0.12m SiGe Yes Table 2.1 contains a survey of state-of-the-art oscillators and VCOs operating above 10GHz. The denition of the Figure of Merit (FOM) employed in Table 2.1 is 24 FOM =L (f) 20log 10 f osc f + 10log 10 P dc 1mW ; (2.12) whereL (f) is the phase noise at an oset of f, f osc is the frequency of oscillation andP dc is the power consumption of the oscillator core. The prototype CMOS oscillator at 26GHz achieves one of the lowest reported phase-noise performances at a low power consumption, conrming the eectiveness of the proposed ideas. 2.4 Transformer-based Integrated RF Oscillators A number of publications have proposed the use of transformers to design high-Q res- onators for low-phase-noise integrated oscillators [119],[11]. The magnetic coupling be- tween the transformer windings can potentially increase the stored energy in the res- onator, leading to higher Q. Such publications argue that transformer-based resonators achieve an improvement factor of 1 +k in Q over the traditional inductor-based res- onator, where k is the coupling coecient of the two-winding transformer employed. In this section, a design strategy will be presented for on-chip inductor-based resonators that have similar or better Q compared to transformer-based topologies, given a silicon-area constraint. In the following subsections, it will be shown that transformer-based resonator Q strongly depends on the specic topology; both Q enhancement and reduction are possi- ble. It is then demonstrated that, for a given area constraint, on-chip resonators based on planar transformers (like the Frlan [46] or Shibata [114] transformers or the Rabjohn 25 balun [100]) can oer no Q improvement over single-inductor-based resonators. Stacked- transformer-based resonators exhibit inferior Q performance compared to single-spiral- based resonators, while single spirals stacked over multiple layers can achieve Q improve- ment, depending on the interconnect structure of the process, thus eliminating the need for true transformer-based resonator topologies. Measurement results of prototype oscil- lators, implemented at 5GHz, are presented to validate these claims. 2.4.1 Circuit Theoretic Analysis As was discussed earlier in this chapter, the energy-based denition relates Q to the ratio of the resonator's stored energy (E stored ) to the resonator's power loss (P loss ). At resonance, the magnetic stored energy (E H ) equals the electric stored energy (E E ). This magnetic stored energy, for resonators composed of lumped elements, is partly comprised of the energy stored in the self inductance of the various inductors and partly the energy stored in the mutual inductance of the various coupled pairs. As a result, we have E stored = 2E H = N X n=1 L n I 2 n + N X m=1 N X n=1 M mn I m I n cos( mn ); (2.13) whereL n andI n are the self inductance and current magnitude (rms) of then th inductor, respectively, and M mn and mn are the mutual inductance and current phase dierence of the m th and n th inductors, respectively. In the resonator depicted in Fig. 2.12(a), the currents in the coupled inductors are in phase (assuming low loss and k = 1). Hence, the mutual magnetic stored energy is positive. This results in an increase in the stored energy, 26 and hence the Q, compared to the inductor-based resonator of Fig. 2.12(c). However, in the resonator depicted in Fig. 2.12(b), the currents in the coupled inductors are out of phase. Hence, the mutual magnetic energy is negative and reduces the stored energy and theQ. Therefore, while circuit theory demonstrates that transformers have the potential to enhance theQ over inductor-based resonators, theQ of a transformer-based resonator is topology-dependent. Figure 2.12: (a) A transformer-based resonator with in-phase currents in the primary and secondary. (b) An alternative transformer-based resonator with out-of-phase primary and secondary currents. (c) An inductor-based resonator. All Q values assumek = 1 and are calculated at the common resonance frequency of 1 p 2LC . Consider a resonator with N inductors, each with value L and parasitic series resis- tance R, and a certain number of lossless capacitors. Every inductor pair has a coupling coecient ofk. Further, the placement of all inductors in the resonator is perfectly sym- metric. From symmetry, the current through each inductor must be the same 9 with rms-value I. At resonance, 9 In Fig. 2.12(a), under the low-loss assumption, the current drawn from the resonator terminals is negligible, making the resonator symmetric. 27 E stored = 2E H = 2 [N 1 2 LI 2 + N(N 1) 2 kLI 2 ];P loss =NI 2 R; (2.14) Q =! E stored P loss = !L R (1 + (N 1)k): (2.15) Hence, an improvement factor of 1 + (N 1)k is seen over a resonator based on a single inductor due to the magnetic coupling between various inductors. It must be noted that, in general, transformer-based resonators are higher-order systems and can exhibit multiple resonance modes. In these discussions, the mode of interest is the one with highest impedance magnitude. However, on-chip inductors and transformers exhibit far more complicated charac- teristics than can be captured in a simple L-R series model. Fig. 2.13 depicts physical layouts and lumped equivalent physical models for various types of on-chip planar induc- tors and transformers. Hence, a fair comparison between inductor- and transformer-based resonators requires a consideration of on-chip parasitics and area and eective-inductance constraints 10 . 2.4.2 Inductor-Planar Transformer Comparison Consider a planar Frlan transformer with the following dening parameters : n (number of turns for each winding),w (conductor width),s (inter-turn spacing) andOD (transformer 10 The inductance of the equivalent second-order parallel RLC circuit that approximates the behavior of the resonator at resonance. 28 Figure 2.13: (a) Spiral inductor layout and physical model. (b) Frlan transformer layout and physical model. The two windings are perfectly symmetric. (c) Rabjohn balun layout and physical model. The intertwined windings are asymmetric. outer dimension). The main advantage of the Frlan transformer (Fig. 2.13(b)) is that the two windings are perfectly identical. Assuming the resonator topology depicted in Fig. 2.12(a), under the low loss assump- tion, Q frlan = ! r L(1 +k) R + R 2 +w 2 r L 2 (1+k) 2 2R sh ; (2.16) whereL andR are the inductance and the series resistance of each winding, respectively, k is the coupling coecient of the transformer, and R sh is the (frequency dependent) 29 equivalent shunt resistance of the C ox ;C Si , and R Si substrate parasitic network lumped at each terminal of each winding. w r is the desired resonant frequency. It must be noted that the inter-winding capacitance has no eect on the resonator Q of Fig. 2.12(a). Now, for comparison, consider a single spiral with the following layout parameters to ensure equal chip area: n single =n;w single = 2w;s single = 2s;OD single =OD. The Q for a parallel LC resonator can be written as Q single = ! r L single R single + R 2 single +w 2 r L 2 single 2R shsingle ; (2.17) where L single , R single , and R shsingle are the corresponding parameters for the spiral inductor. This spiral inductor is constructed to have the same inner and outer dimensions as each winding of the Frlan transformer and also has the same number of turns. Since these are the factors that dominate the self inductance [77],L single L. Further, the parasitics to the substrate are the same in both cases, except for the fact that they would have to be distributed in parallel across 4 terminals in the case of the Frlan, as opposed to 2 in the case of the spiral. Hence R sh 2R shsingle . Finally, at low frequencies, R single = R 2 , since the spiral has twice the conductor width as the Frlan. At low frequencies, where series loss dominates, Q single = !rL single R single and Q frlan = !rL(1+k) R . These two values should be comparable, because the (1 +k) factor, in the best case of k = 1, osets the advantage enjoyed by the single spiral in R single . At high frequencies, where substrate loss dominates,Q single = 2R shsingle !rL single andQ frlan = 2R sh !rL(1+k) . Once again, when k = 1, these two values are the same. If k < 1, the Frlan 30 transformer would have a slightly-better high-frequencyQ value (by a factor of 2 1+k ), but its low-frequency Q would degrade below that of the single spiral by the same factor. Figure 2.14: Comparison between the resonator Qs of 3 Frlan transformers, baluns and the corresponding scaled spirals. Simulations were performed in IE3D on Frlan transformers with various dimensions and the correspondingly-scaled spirals. These structures were implemented in the top metal layer of IBM's 0.18m 7RF process 11 , which has a thickness of 2m and a height of 9.77m above the silicon substrate. Fig. 2.14 depicts the comparison of the resonatorQs. It can be clearly seen that, in agreement with the preceding analysis, the Q of the Frlan- transformer-based resonator is not higher compared to that of the spiral-based resonator, when subject to the same eective-inductance and area constraint. While the preceding analysis assumed a symmetric planar transformer, the conclusion holds good for asymmetric planar transformers as well, such as the Rabjohn balun (Fig. 2.13(c)). In this case, the primary and secondary windings of the transformer are not 11 This is the process used for the 5GHz prototypes described later. 31 identical, and hence the choice of terminal capacitancesC 1 andC 2 at each winding is not straightforward. Assuming low loss and k = 1, and ignoring substrate parasitics, it can be shown that ! r = 1 p L 1 C 1 +L 2 C 2 (2.18) and Q =! r L 2 1 C 2 1 +L 2 2 C 2 2 + 2L 1 L 2 C 1 C 2 L 1 R 1 C 2 1 +L 2 R 2 C 2 2 : (2.19) Maximizing Q with respect to C 1 and C 2 under the constraint that ! r must remain constant, we obtain R 1 C 1 =R 2 C 2 : (2.20) This design equation, coupled with (2.18) to obtain the desired frequency of resonance, dictates the choice of C 1 and C 2 for optimal Q for a given asymmetric transformer. Fig. 2.14 also includes the EM-simulated Q for such optimally-designed asymmetric- transformer-based resonators. In all cases, the peak Qs of the single inductor- and Rab- john balun-based resonators are within 12% of each other. 2.4.3 Inductor-Stacked Transformer Comparison Stacked transformers exploit the multiple metal layers oered by modern processes to conserve chip area. The windings are implemented on dierent metal layers, one above 32 Figure 2.15: (a) Double-layer spiral layout. (b) Stacked transformer layout. the other (Fig. 2.15(b)). This, however, results in an asymmetric structure; the self inductances of the windings are similar to rst order, but the series resistance is higher for the lower metal layer, due to its reduced thickness in standard silicon processes. Further, stacked structures experience more severe and asymmetric substrate parasitic eects due to the greater proximity of the lower metal layer to the substrate. Also, the presence of each winding deteriorates the quality of the other due to the proximity eect 12 . Finally, the achievable coupling coecients are largely a function of the separation between the metal layers used (Fig. 2.16). Due to these mitigating factors, stacked-transformer-based resonators are generally found to exhibit inferior Q when compared to spiral-inductor- based resonators. The Q of inductors can be improved by strapping multiple metal layers together us- ing vias [118]. These multi-layer spirals are expected to have higher resonator Qs than single-layer spirals because the (low-frequency) series resistance reduces to the parallel 12 Proximity eect is the phenomenon of current crowding in a conductor due to the close proximity of another conductor. 33 Figure 2.16: Resonator Q for single- and double-layer spirals and a stacked transformer with OD = 150m, w = 10m, s = 10m, n = 2. combination of the resistances of the upper, lower, and via metals. The extent of im- provement is process dependent, and is governed by the relative quality of the strapped layers, via thickness and increased substrate eects. EM simulations were performed on single-layer and double-layer spiral inductors and stacked transformers in two dierent silicon processes. The results are depicted in Fig. 2.16. In both processes, the stacked transformer exhibits inferior performance when compared to the single-layer spiral. The double-layer spiral outperforms its single-layer counterpart substantially in process A (7RF). This is largely due to the substantial via thickness between the top two metal layers, which greatly reduces the series resistance. In process B (TSMC's 0.18m CMOS process), the via thickness is signicantly lower. Further, the closer proximity of the upper layers to the substrate indicates that substrate loss is a more dominant factor in inductor Q for process B. As a result, the double-layer spiral performs only comparably to the single-layer spiral. 34 Figure 2.17: (a) Circuit diagrams for the single-inductor- and balun-based 5 GHz oscil- lators. (b) Chip microphotograph of the two oscillators. 2.4.4 Experimental Results To validate these claims, two 5GHz oscillators using spiral- and Rabjohn balun-based resonators were implemented in IBM's 7RF 0.18m CMOS process (Fig. 2.17) [69]. The oscillator active core and all other parameters are kept equal. Hence, a comparison between their phase noise is a direct indication of resonator Q. The tank capacitors are implemented using MIM capacitors, and the negative-Gm cell is implemented using complementary cross-coupled nMOS-pMOS pairs to improve phase noise. nMOS open- drain buers are employed to isolate the oscillators from the measurement setup. Eective-inductance and area constraints of 3nH and 250m 250m were set for both cases, respectively. The primary winding of the Rabjohn balun was selected to achieve the highest stand-aloneQ through optimizations in ASITIC. The primary winding has OD = 250m, n = 3, W = 7:5m and S = 3:75m. The secondary winding has the 35 same dimensions, but only 2 turns. EM simulations in IE3D, followed by the tting of the S-parameters into the model described in Fig. 2.13(c), reveal that the model parameters are : L 1 =3.14nH, L 2 =1.64nH, R 1 =7.21 , R 2 =5.45 and k = 0:79. The optimal values for terminal capacitors were selected using (2.18) and (2.20). Simulation results predict an optimal Q of 18.95 when C 1 =215fF and C 2 =255.8fF. The eective inductance at resonance is 2.73nH. The correspondingly-scaled spiral inductor was also simulated in IE3D, and the resul- tant S-parameters were t into the inductor model described in Fig. 2.13(a). The main model parameters were found to be L=3.11nH and R=6.06 . The Q was found to be 18.3 with an eective inductance of 2.66nH. Clearly, the single-inductor-based resonator is found to perform comparably to the transformer-based resonator, when subject to the same area and eective-inductance constraint. Figure 2.18: Measured phase noise of the two oscillators for I bias =1.28mA and V dd = V bias =1.8V. The chip dimensions are 460m 600m for each oscillator. The RF pads were wire- bonded to 50 traces on a printed circuit board and connected to the spectrum analyzer 36 Table 2.2: Phase noise performance and oscillation frequency of the two oscillators for a variety of bias currents. I bias L dBc=Hz (1M) L dBc=Hz (10M) f tran f ind FOM mA Trans. Ind. Trans. Ind GHz GHz 0.6 -116 -116 -135.3 -136.9 5.12 5.14 -190 1.00 -117 -116.5 -138.1 -136.9 5.11 5.12 -190 1.28 -117.5 -118.7 -138.2 -138.4 5.11 5.12 -192 1.50 -118.7 -120 -138.3 -138.4 5.11 5.12 -194 using RF cables. The phase-noise performances of both oscillators were measured for a variety of bias currents at a supply voltage of 1.8V. Fig. 2.18 depicts the measured phase noise of each oscillator versus the oset frequency for one bias current. Table 2.2 shows the phase noise at typical oset frequencies for a variety of bias currents and the equal FOMs of both oscillators as dened earlier in this chapter. It is clear that the phase noise performances of both oscillators are nearly iden- tical, validating the claim that for a xed silicon area and eective-inductance con- straint, transformer-based resonators do not exhibit superior performance compared to inductor-based designs. Further, the eorts to optimize the Q of the transformer- and corresponding-spiral-based resonators have resulted in FOMs that compare favorably to recently reported state-of-the-art oscillators. 2.5 Quantifying the Impact of Passive-Element Loss on LNA Noise Figure Sections 2.3 and 2.4 of this chapter have focussed on the design of high-Q resonators for integrated low-phase-noise oscillators. However, as was discussed earlier in this chapter, 37 the nite quality of integrated passive elements impacts the noise performance of low- noise ampliers (LNAs) as well. This is particularly true of the passive elements used in the input-impedance matching network of the LNA. In this section, the impact of nite passive-element Q on the NF of LNAs is quantied independent of LNA and match- ing network topology using circuit-theoretic techniques. A new minimum-NF metric (NF min;p ) for processes is proposed that incorporates the quality of the passive elements available in the process. The formulation also provides design guidelines for LNA input- matching networks to achieve NF min;p . In practice, capacitive parasitics of integrated inductors degrade theNF fromNF min;p . An E-band LNA is implemented in IBM's 8HP 0.13m SiGe process to support the formulation. 2.5.1 Prior Art Prior research into the impact of passive-element loss on the NF of LNAs has been limited to specic topologies. In [111], the authors analyze the inductor-degenerated LNA topology and incorporate the nite Q of the input-matching inductors into the optimization process. There has been work in the past on impedance matching in the presence of lossy components [49]. In [49], the author provides design guidelines for lossy matching net- works to maximize the power delivered to the load. While such a formulation may prove useful for integrated power ampliers to maximize the output power, it is inappropriate for minimizing the NF of LNAs. 38 Figure 2.19: (a) Generalized LNA block diagram. (b) Matching network design for optimum NF in the lossless case. (c) Equivalent circuit for the matching network when the components have loss. 2.5.2 Quantitative Formulation for NF min;p Fig. 2.19(a) depicts the block diagram of a typical LNA. The antenna impedance is typically either transformed to the conjugate impedance (power match) or the optimal noise impedance (noise match) of the active device through a passive (and ideally lossless) matching network. When the matching network contains loss,NF deteriorates. Hence, it is desirable to determine the lowest achievable NF given the characteristics of the active device and the quality of the passive elements. It is also desirable to determine how the matching network must be designed to achieve this lowest achievable NF . Let us assume that the antenna's impedance at the frequency of operation is Z 0 (typically 50 ), and that the matching network is composed of inductors and capacitors of quality factor Q L and Q C , respectively (independent of value). The active device is represented by the classical, two-port noise parameters R n , G opt , B opt and NF min [123]. NF min is the minimum noise gure of the active device, G opt and B opt are the optimal source-admittance components and R n is the noise resistance. It should be noted that 39 these parameters are sucient to capture the noise performance of the two-port active device. Specically, if a lossless matching network transforms Z 0 to the admittance G s +jB s , the NF of the LNA can be computed as [123] NF =NF min + R n G s [(G s G opt ) 2 + (B s B opt ) 2 ]: (2.21) In the lossless case, optimum NF is achieved when the lossless matching network trans- forms Z 0 to the admittance G opt +jB opt at the frequency of operation (2.19(b)), causing NF to become NF min . The topology of the matching network (L-match, -match etc.) does not matter. To analyze the case where the matching network is lossy, it is useful to recall that for sinusoidal steady-state, G in +jB in = 2P loss + 4j!(E E E H ) j Vj 2 ; (2.22) where G in +jB in is the input admittance of a one-port passive network, P loss , E E and E H are the power dissipated, average stored electric energy and average stored magnetic energy, respectively, in that network at the frequency of operation!, and V is the voltage vector [102]. When this result is applied to a lossless matching network that transforms Z 0 to G opt +jB opt , we have G opt +jB opt = 2P loss + 4j!(E E E H ) j Vj 2 : (2.23) The loss P loss in this case is purely in Z 0 . If the inductors and capacitors used in the matching network are lossy and have quality factors of Q L and Q C respectively, then 40 P loss will include those losses as well 13 . If the losses are small, it can be assumed that the presence of losses does not signicantly alter the currents and voltages across the elements of the matching network. E E and E H will then not be signicantly altered. P loss will increase to include the losses of the matching network in addition to the unaltered loss of Z 0 . The loss in the matching network may be computed to be 2!( E E Q C + E H Q L ) from (2.4). The fact that E E and E H remain unaltered and P loss increases by this quantity implies that the lossy matching network is equivalent to the corresponding lossless matching network with an extra shunt conductance G loss , as shown in Fig. 2.19(c). The value of G loss is given by G loss = 4!( E E Q C + E H Q L ) j Vj 2 : (2.24) Based on this equivalent circuit, the NF when the active device is preceded by the lossy matching network may be computed to be NF = 1 + G loss G opt 2 NF min + R n G opt +G loss G 2 loss 1 + G loss G opt 2 NF min + R n G opt G 2 loss : (2.25) The reasoning behind (2.25) is as follows. NF min + Rn Gopt G 2 loss is theNF of the active device from (2.21) due to the presence of a source impedance of G opt +G loss +jB opt . A factor of 1 + G loss Gopt arises from a renormalization of this noise gure to the real source 13 Typically, inductor loss is modeled with a series resistance. In the case of capacitors, a parasitic shunt resistance typically models the loss. 41 impedance of G opt +jB opt . A nal additional factor of 1 + G loss Gopt arises from the noise associated with loss resistor G loss . Equations (2.23)-(2.25) together allow us to compute minimum achievable noise gure NF min;p given the active-device parameters and the quality of the matching components. Typically, B opt is negative. This is because the input impedance of an active device is usually capacitive, causing the optimal source impedance for NF to be inductive in nature. It follows from (2.23)-(2.25) that G loss , and hence NF , would be minimized if E E = 0 and E H = jBoptjj Vj 2 4! . Any positive value of E E would result in an increased E H to match to B opt . This would increase G loss and hence NF . In other words, only magnetic-energy-storage elements (such as inductors) should be used in the matching network, and no electric-energy-storage elements (such as capacitors) should be used, irrespective of the relative values of Q L and Q C 14 . The resultant minimum G loss is jBoptj 2Q L . Hence, NF min;p is given by NF min;p = 1 + jB opt j 2G opt Q L 2 NF min + R n 4G opt Q 2 L B 2 opt : (2.26) As was mentioned earlier,NF min;p can be viewed as a new minimum achievable noise gure that combines the capability of the active device with the quality of the passive components available in the process. The design guideline to achieve NF min;p , once the active device and its bias condition have been selected, dictates the use of only magnetic- energy-storage components as long asB opt is negative. This formulation can also be used in an optimal LNA design procedure that includes selection of the active device and its bias point as well. Rather than selecting the device and bias point with minimumNF min , 14 If Bopt were positive, the opposite argument would hold true and only capacitors should be used in the matching network. 42 Figure 2.20: Domain of impedances that a 50 reference can be transformed to using only inductors. The gray segments of the upper half of the Smith Chart requires the use of ideal transformers. it is benecial to select the device and bias point with minimum NF min;p , given the Q L of the process. Practical integrated inductors have parasitic capacitances associated with them. The eects of the parasitic capacitances are more pronounced at high frequencies. As a result, designs at millimeter-wave frequencies tend to employ transmission lines rather than lumped components. The use of transmission lines or inductors with signicant capacitive parasitics will cause the noise gure to degrade from the fundamental limit of NF min;p due to the presence of electric-energy storage elements. It should be noted, however, that the use of only inductors in the matching network places a restriction on the source impedances that a reference impedance of 50 can be transformed to (Fig. 2.20). The movements along the Smith Chart have been traced for a shunt-series inductor-based matching network. The regions of the upper half of the Smith Chart that are shaded in gray cannot be accessed through any matching network 43 that employs inductors alone. However, the use of transformers enables matching into these regions. 2.5.3 A 0.13m SiGe E-Band LNA Design Example The FCC has opened up the 71-76GHz and 81-86GHz frequency bands for high-data- rate wireless communication [33]. These frequency bands are being investigated for a number of applications such as last-mile bre replacement and backhaul applications. This subsection describes the design of a 0.13m SiGe E-band LNA that is suitable for 71-76GHz, 81-86GHz wireless receivers [71]. The LNA was implemented in IBM's 8HP 0.13m SiGe BiCMOS process 15 to provide experimental evidence for the formulations presented earlier in this section. 2.5.3.1 E-band Receiver Architectures Fig. 2.21 depicts proposed E-band wireless-receiver architectures that operate either con- currently or in a switched manner in the 71-76GHz and 81-86GHz bands. The received sig- nal is amplied by an LNA and downconverted using quadrature 78.5GHz local-oscillator signals. Both bands are downconverted to an IF range of 2.5-7.5GHz. These IF signals may be further processed, for example, using commercial 3-10GHz UWB chipsets, thus easing deployment. A switched E-band receiver would employ an LNA that is capable of switching between the 71-76GHz and 81-86GHz bands. A concurrent receiver, on the other hand, requires either a concurrent dual-band LNA [60] or a wideband 71-86GHz LNA. A distinct dual-band response is challenging due to the close proximity of the two 15 A characterization of 8HP is available in Appendix A.1. 44 Figure 2.21: Potential E-band receiver architectures. bands and the nite quality of on-chip passive components. Hence, a wideband 71-86GHz LNA is preferred for concurrent applications. In the concurrent case, quadrature down- conversion with the 78.5GHz LO separates the lower (71-76GHz) and upper (81-86GHz) sidebands. Quadrature demodulation within each individual band can be handled in the 3-10GHz chipset. 2.5.3.2 0.13m SiGe E-Band LNA Design At millimeter-wave frequencies, power gain is often an important concern, as the devices operate at a signicant fraction of the maximum oscillation frequency (f max ). Fig. 2.22(a) depicts the maximum power gain of a single HBT common-emitter stage and that of a cascode-common-emitter pair in IBM's 8HP process. The emitter length of the HBTs is chosen to be 7.5m and the bias current is 3mA. In the case of the cascode-common- emitter pair, the base of the cascode transistor is biased at Vdd, which is 1.8V. The single common-emitter stage has a maximum power gain of approximately 7dB at 79GHz, which lies in the middle of the two frequency bands of interest. This power gain would be further 45 degraded by passive-element loss at the input and output, and by an attempt to noise- match the input, as opposed to a power match. The resultant power gain is unlikely to be enough to immunize the LNA to the noise of the second stage in a cascade of common-emitter stages. The cascode-common-emitter pair on the other hand achieves 18dB of maximum power gain. Another advantage of the cascode-common-emitter pair over a cascade of common-emitter stages is power consumption, as the current is shared between the two HBTs. Therefore, the cascode-common-emitter pair is chosen as the starting point for the LNA design. Figure 2.22: (a) Maximum power gain for a single HBT common-emitter stage and a cascode-common-emitter pair. The emitter length of all devices is 7.5m and the bias current is 3mA. (b)NF min at 79GHz as a function of the emitter length and bias current for a cascode-common-emitter HBT pair. Both transistors of the cascode are assumed to have the same device size. Fig. 2.22(b) depicts the NF min of a cascode-common-emitter pair at 79GHz as a function of the device size and the bias current. An emitter length of 7.5m and bias current of 3mA are chosen for the design. The corresponding NF min is 4.9dB, which is among the lowest in the device-size and bias-current sweep. Ideally, as was noted earlier, NF min;p , and not NF min , should be used to choose the optimal device and bias current. 46 However, for the technology and frequency band of interest, it is seen that the optimal design point does not shift for Q L > 10. Figure 2.23: (a) Two possible matching networks for the optimal design point - inductor- based and transmission-line-based. (b) Noise gure (NF ) of the optimal design point with the inductor- and transmission-line-based matching networks as Q L is varied. NF min;p is also plotted. The chosen design point exhibits G opt =14.5mS, B opt =-13.3mS and R n =48.5 . A noise match can be achieved using a series 63pH inductor and a shunt 450pH inductor (Fig. 2.23(a)). Fig. 2.23(b) plots NF min;p as a function of Q L from (2.26). The plot also contains a simulation of the NF of the chosen design point with the inductor-based matching network asQ L is varied (through variance of the series resistance of the induc- tors). An excellent match is seen, conrming the validity ofNF min;p and the guideline to achieve it. For a conservative Q L value of 5, NF min;p degrades to 5.7dB from an NF min value of 4.9dB. As was mentioned earlier, integrated inductors exhibit capacitive parasitics which are especially signicant at millimeter-wave frequencies. As a result, millimeter-wave designs tend to be transmission-line-based. A transmission-line-based matching network is also possible for the chosen design point (Fig. 2.23(a)). The transmission-line parameters 47 of Z 0 =69 and r =4.25 correspond to a microstrip implemented in AM, the 4m-thick top analog metal layer of 8HP, with the ground plane stacked from MQ, a 0.6m-thick intermediary metal layer, to the bottom metal layer. The conductor width is 5m and the AM-MQ separation is 9.5m. This microstrip is used throughout the LNA design. Fig. 2.23(b) depicts the NF when the transmission-line-based matching network is used as a function of Q L 16 . It can be seen that, as expected, the transmission-line-based network results in a deterioration from the fundamental limit of NF min;p due to the capacitive components of the line. The microstrip used in the design exhibits a Q L of 23, and the corresponding noise gure is 5.3dB. For reference, NF min;p for Q L =23 is 5.1dB. Figure 2.24: LNA NF for the transmission-line based matching network in the presence and absence of loss. Although designed at 79GHz, the transmission-line-based matching network is able to provide a wideband noise match from 71-86GHz. Fig. 2.24 shows theNF in the presence and absence of loss across the entire bandwidth. The single-stage NF that is achieved in the presence of passive loss ranges from 4.8-5.1dB in the 71-76GHz band and 5.4-5.8dB in the 81-86GHz band. 16 QL is changed by changing the resistance per unit length of the line. 48 Figure 2.25: Circuit diagram of the E-band LNA. Fig. 2.25 depicts the circuit diagram of the E-band LNA. The LNA consists of two virtually identical cascode-common-emitter stages. Since the transmission-line-based matching network at the input of the rst stage provides a wideband noise match from 71-86GHz, no tuning is employed on the input side for band selection 17 . Tuning var- actors are incorporated at the output of each stage to select between the 71-76GHz and 81-86GHz bands in a switched fashion. Control voltages of 0V and 2.1V tune the design to the 71-76GHz and 81-86GHz bands, respectively. The biasing of the LNA is per- formed using a scaled replica device. The core of the LNA consumes 6mA from a 1.8V supply. The chip microphotograph of the LNA is shown in Fig. 2.26. The chip occupies 660m770m of silicon area. Fig. 2.27(a) shows the simulated small-signal performance parameters of the LNA when the control voltage is set to 1, which selects the 71-76GHz band. The simulated 17 It should be noted that the transmission-line lengths are slightly modied to account for layout parasitics. 49 Figure 2.26: Chip microphotograph of the E-band LNA. Figure 2.27: (a) Simulated small signal gain, NF and re ection coecients for a control voltage value of 0V. (b) Simulated small signal gain, NF and re ection coecients for a control voltage value of 2V. power gain per stage is 10dB. Based on the single-stage NF range of 4.8-5.1dB, the two- stageNF is expected to vary from 5.1dB-5.4dB. The simulatedNF ranges from 5.8-6dB and is deteriorated mainly due to capacitive layout parasitics. Fig. 2.27(b) shows the simulated small-signal performance parameters when the control voltage is set to 2V, which selects the 81-86GHz band. The expected two-stageNF ranges from 5.7dB-6.1dB, and the simulated NF ranges from 6.2-6.6dB. 50 Figure 2.28: (a) Measured small-signal S-parameters of the E-band LNA for a varactor control voltage of 0V. The S-parameters are measured using a 110GHz VNA. The gain is also measured using a V-/W-band scalar measurement setup. (b) Measured small-signal S-parameters for a varactor control voltage of 2.1V. Fig. 2.28 depicts the measured gain and re ection coecients of the LNA for varac- tor control voltages of 0V and 2.1V. The measurements are performed using an Agilent 110GHz Vector Network Analyzer (VNA). In addition, gain measurements are also per- formed using a scalar waveguide-based setup in the V and W bands. The scalar gain measurements agree reasonably with the VNA measurements, but exhibit a gain ripple that is likely caused by mismatch at the DUT input and output 18 . The measured current consumption of the LNA was observed to be 20% below the designed value. Investigations indicate that the reduction in current is likely caused by an increase in the parasitic emitter resistance of the HBTs by 5 over the 2 that is predicted by the design-kit model. The current was restored to the desired 6mA through control of V ref in the biasing circuitry. In addition, the re ection-coecient measurements indicate 18 Directional couplers were not available to be included at the input and output of the DUT in the scalar setup. Therefore, the mismatches at the input and output were not measured. 51 that the output match is tuned 10GHz too high. Post-measurement analysis reveals that a reduction in the capacitance of the output matching network by 15fF produces a good correlation between simulations and measurements (Fig. 2.28). As a result of the frequency error inS 22 , the LNA achieves a stagger-tuned wideband response with a peak gain of approximately 10dB and -3dB bandwidth from 69-86GHz for a varactor control voltage of 0V. Variation of the varactor control voltage does tune S 22 but produces little change in S 21 because of stagger tuning. This observed LNA performance renders it suitable for concurrent 71-76GHz, 81-86GHz receivers. The cause for the reduced capacitance at the output node is yet to be determined. Candidates include inaccurate varactor models, MiM capacitor models that do not cor- rectly model the self-resonance of the capacitor and inaccurate device models. Figure 2.29: Post-measurement simulation of the NF of the E-band LNA for varactor control voltage values of 0V and 2.1V. TheNF measurement of the LNA is in progress. Fig. 2.29 depicts the expected NF for varactor control-voltage values of 0V and 2.1V based on post-measurement simula- tions. TheNF is expected to range from 6.3-8.5dB over the -3dB bandwidth of 69-86GHz 52 Table 2.3: Performance summary of the E-band LNA. Implementation Technology 130nm SiGe BiCMOS Supply Voltage 1.8V Current Consumption (LNA core) 6mA E-band Performance Peak Gain (V ctrl =0V) 9.7dB NF (V ctrl =0V) 6.3-8.5dB (sim.) -3dB Bandwidth (V ctrl =0V) 69-86GHz Table 2.4: Performance comparison of state-of-the-art silicon-based LNAs operating above 60GHz. Work Technology Freq. Power Diss. Gain NF (GHz) (mW) (dB) (dB) [6] 0.12m BiCMOS 59 8.1 14.5 4.1 [32] 90nm CMOS 60 3.9 15 4.4 [129] 65nm CMOS 60 34.8 19.3 6.1 [43] 0.12m BiCMOS 61.5 10.8 15 4.5 [10] 0.12m BiCMOS 77 61.25 23.8 5.7 This Work 0.12m BiCMOS 69-86 10.8 9.7 6.3-8.5 (sim.) [7] 0.12m BiCMOS 91 8.1 13 5.1 for a varactor control voltage of 0V. The NF is degraded towards the higher end of the bandwidth due to insucient gain in the rst stage of the stagger-tuned LNA. However, it is anticipated that the NF towards the lower end of the bandwidth will corroborate the NF min;p formulation presented earlier. Table 2.3 summarizes the performance of the implemented LNA for a varactor control voltage of 0V, and Table 2.4 compares its performance to prior works. It is seen that capacitive parasitics associated with integrated inductors, input pads and other such layout components degrade the NF from NF min;p . Therefore, techniques to minimize the parasitic capacitance associated with integrated inductors would further lower the NF of the implemented LNA. In addition, the base resistance of the HBTs of the process are a signicant contributor towards the noise performance of the device. Techniques to 53 lower the base resistance, such as multi-nger device layouts and the usage of multiple devices in parallel, can be used to lower the NF . 2.6 Topics for Future Research As was discussed earlier in this chapter, the achievable Qs in commercial silicon-based processes are limited by material and geometric limitations. An interesting line of inves- tigation would be that of the existence of a fundamental limit on the achievable Q of a resonator given the parameters of a fabrication process. Aside from providing designers with an upper bound on achievable performance, such a line of investigation might reveal new passive structures that come closer to this upper bound than the structures that are currently known and used. As operating frequencies approach the f max of the process technology, the Q of the passive component/resonator degrades due to the parasitics present in the active devices. The loaded Q of the CPS resonator in Section 2.3 was investigated through small-signal circuit simulations. In the context of oscillators, small-signal performance is often not relevant, especially in relation to large-signal performance criteria, such as phase noise. A formulation that captures the degradation of the Q of a resonator due to the losses of the active devices of an electrical oscillator is another important topic for future research. Such a formulation is likely to be topology-dependent, and hence may reveal preferred topologies for near-f max operation. 54 2.7 Summary This chapter focussed on the implementation of high-quality passive components in silicon-based processes at millimeter-wave frequencies. A complementary, current-sharing oscillator architecture was introduced that enables the realization of a high-quality CPS resonator. The use of integrated transformers to realize high-quality resonators for low- phase-noise oscillators was investigated. Finally, a new minimum-noise-gure metric for integrated processes that combines the quality of the active and passive devices avail- able in the process was proposed. The design techniques and guidelines introduced in this chapter are used extensively in the implementations described in the chapters that follow. 55 Chapter 3 Integrated Phased Arrays for Commercial Wireless Communication and Radar Phased-array wireless transceivers have attracted signicant research interest over the last ve years in the silicon-based integrated-circuit community [55], [91], [136], [90], [89]. The emergence of commercial millimeter-wave applications, such as high-data-rate 60GHz wireless personal area networks (WPANs) and vehicular radar in the 22-29GHz and 76-77GHz bands, has provided the impetus for this trend. Phased arrays alleviate the stringent link-budget requirements of these applications. The spatial selectivity aorded by phased arrays also aids in mitigating the adverse eects of multipaths and interference. This chapter 1 is intended to provide a system-level view of integrated phased arrays and begins with an overview of the history of the phased array. A distinction is then drawn between the archetypal phased array that has been used in military applications for the last half century, and the new generation of silicon-based phased arrays that target commercial millimeter-wave applications. The basic operating principle of a phased array 1 Several sections of this chapter have been reproduced with permission from [70], which was co- authored by the author of this thesis. 56 is then detailed. The following section dierentiates between phased arrays and timed arrays, which employ variable true time delays as opposed to phase shifts to enable instantaneous wideband operation. A 1-13GHz ultra-wideband (UWB) variable delay element implemented in a 0.18m SiGe process is then presented brie y. The variable true time delay element is intended for use in UWB timed arrays for high-resolution imaging, and achieves 64ps of total variable delay with 4ps resolution. Conventional phased-array architectures are then described, and their relative merits and demerits are listed. This is followed by an analysis of the eect of channel mismatches, arising either from packaging or the fabrication process, on phased-array performance. This analysis equips the system designer with simple expressions that predict the performance that can be expected from integrated phased arrays, and motivates the need for on-chip array-calibration techniques. The chapter concludes with an analysis of the impact of phase-quantization error on array performance. Again, the system designer is provided with simple expressions that aid in the choice of the phase-shifter resolution. 3.1 History of the Phased Array The use of multiple antennas, or antenna arrays, to enhance the performance of wireless- communication and radar systems has been known for a long time. Antenna arrays are widely used under a variety of names such as phased arrays, beam-forming arrays, spatial-diversity and MIMO transceivers. As is the case with most fundamental discoveries, the origin of the antenna array is shrouded in some doubt. Some point to Nobel Prize-winning scientist Guglielmo Marconi 57 and his landmark transatlantic wireless-communication experiment in December 1901 [15]. The original antennas conceived for the experiment consisted of an array of twenty aerials. These were unfortunately destroyed by devastating storms, and hence mere two- element arrays were used, through which a repeated Morse Code signal representing the letter 'S' was successfully transmitted from Poldhu in Cornwall, United Kingdom to St. Johns in Newfoundland, Canada. The credit for the invention of the electronically-steered, linear, phased array is uni- versally given to another Nobel Prize-winning scientist Luis Alvarez [127]. His invention was primarily motivated by the U.S. war eort in WW-II and formed the basis for Ea- gle, the rst radar-based bombing system. Even today, the use of phased arrays is most widespread in the realm of defense, with most warships and ghter planes featuring phased-array radars. 3.2 Phased Arrays for Commercial mm-Wave Applications The current trend of integration of phased arrays on silicon for commercial applications is characterized by a completely dierent set of challenges when compared to the archetypal phased array for military applications (Table 3.1). Military phased arrays are tradition- ally used in high-performance radar systems and hence employ thousands of elements to achieve a ne spatial resolution. Beam-scanning is used to locate and track multiple targets simultaneously. These phased arrays have traditionally been built using discrete modules based on compound semiconductors. The modular design style guarantees ro- bustness towards failure of individual elements. Unit cost has not been a concern, and 58 Table 3.1: Comparison of conventional antenna arrays suitable for military applications versus the emerging commercial applications. Conventional (> 50 years) Emerging (5 years) Applications Military Radar Wireless Communications Automotive Radar Typical Range Long Range (> 1km) Short Range (< 50m) Array Size Large (100-10000) Small (4-64) Why an Array? * Focussed, High-Power Beam * SNR Improvement in RX * Multiple, Simultaneous Beams * Relaxed PA Requirement * Spatial Interference Cancellation * Link Reliability (Comm.) * SNR Improvement in RX * Spatial Selectivity (Radar) Driver (in order) * Performance * Cost * Size * Size * Cost * Power Consumption Architecture Module-based Monolithic Semiconductor III-V Silicon Technology the physical size of the array is dictated by the aperture size which is set by the required spatial resolution. On the other hand, the burgeoning commercial millimeter-wave applications, such as high data rate wireless communications for WPANs at 24GHz and 60GHz [116] and vehicular radar at 22-29GHz [34] and 77GHz [35], are have relatively lower performance requirements when compared to military systems in terms of beamwidth, transmitted power and receiver sensitivity. This is largely due to the fact that the link distances involved are of the order of tens of meters. As a result, these commercial phased arrays will likely employ tens of radiating elements, rather than thousands. The unit cost is a critical issue for high-volume market success, and hence, integration onto silicon-based technologies, particularly CMOS, is critical. This is rendered feasible by the lower re- quired performance, in terms of EIRP and array sensitivity for example, and the ability 59 of the latest generation of silicon-based technologies to handle millimeter-wave frequen- cies. Further, silicon-based technologies boast the advantage of being able to integrate millions of devices onto a single chip with near-zero incremental device cost and high reliability. This can be harnessed to increase system functionality and implement digital signal processing and calibration circuitry to ne-tune system performance at virtually no extra cost. The latter is particularly important as the low-cost packaging of a silicon chip with an antenna array at millimeter-wave frequencies introduces element mismatches that deteriorate array performance. Calibration circuitry enable the correction of pack- aging mismatches, and hence can greatly reduce packaging eort and cost. Moreover, calibration circuitry is required to guarantee the desired performance of silicon circuits at millimeter-wave frequencies across process, voltage and temparature (PVT) variations. Finally, single-chip integration often signicantly reduces the power consumption when compared to a modular design approach as a large segment of the power consumption is spent in transporting the signal across chip-to-chip or module-to-module interfaces. Single-chip integration oers exibility in the design of block-to-block interfaces, which can be exploited to lower the power consumption. Table 3.2 summarizes recent publications that have reported transceiver designs for automotive-radar applications in the 22-29GHz and 77GHz frequency bands. Both modular- type and fully-integrated silicon-based works have been considered. The power consump- tion is uniformly lower in the fully-integrated implementations. Furthermore, the large area and power consumption associated with modular-type transceivers precludes the im- plementation of multiple channels for commercial vehicular radar. Much in the same way that advancement in silicon integration and mixed-signal IC design led to the dramatic 60 Table 3.2: Comparison of discrete and integrated transceiver designs for 22-29GHz and 77GHz vehicular radar. Work Integration Channels Freq. Output Power NF (Single Power (GHz) per Channel Channel) Diss. [5] Discrete 1 24 6dBm 1.5dB 1.2W comp. on PCB (LNA) [85] Modular TX: 1 24 10-16dBm Not 20W a Assembly RX: 2 Reported [101] 0.25 MESFET 1 77 15dBm No RX 2.8W Modular [121] 0.15m GaAs 1 77 14.5dBm Not 1.1W Monolithic Reported [55] 0.18m SiGe 8 24 No TX 7.4dB 0.91W Monolithic [91] 0.18m SiGe b 4 24 14dBm No RX 1.97W Monolithic [136] 0.13m CMOS 4 24 No TX 6.5dB 120mW Monolithic c [59] 225/330GHz 1 77 No TX 11.5dB 440mW SiGe Monolithic [93] 0.12m SiGe 1 77 5.8dBm 11.5dB 740mW Monolithic [44] 0.18m SiGe 4 d 77 7dBm 17.7dB 3.3W Monolithic [10], 0.13m SiGe 4 77 10dBm 8dB TX:2.2W [90] Monolithic RX:1.3W a Includes array baseband processing. b The power ampliers were implemented using CMOS transistors only. c Does not include a local oscillator or downconversion mixers. d Does not include steering capability. cost reduction and performance enhancement of commercial wireless-communication sys- tems, silicon-based antenna arrays are likely to play a key role toward the wide deployment of future millimeter-wave communication and sensing systems. 61 3.3 Phased Array Basics A phased array is a multiple-antenna system that electronically modies the direction of transmission/reception of the electromagnetic beam. This is done by introducing a variable time delay in each antenna's signal path to compensate for the path dierences in free space. Fig. 3.1 depicts the block diagram of an N-channel phased-array receiver. The uniform antenna spacing is assumed to bed, and each antenna's signal path contains a variable delay block, following which the dierent signal paths are combined. A plane- wave electromagnetic beam is assumed to be incident on the array at an angle of in to the normal direction. Because of the spacing between the antennas, the beam will experience a time delay equal to d sin in c , where c is the speed of light in free space, in reaching successive antennas. Hence, if the incident beam is a sinusoid at frequency ! with an amplitude of A, the signals received by each of the antennas can be written as Figure 3.1: Basic phased-array receiver block diagram. S i (t) =A cos !(t (i 1) d sin in c ) : (3.1) 62 The incident plane wave experiences a linear delay progression in arriving at the successive antennas. Therefore, to compensate for this, the variable delay blocks must be set to a similar but reverse delay progression. Fig. 3.1 shows the i th delay block set to (N i + 1). This would perfectly compensate for the incident progression if = d sin in c . Therefore, the signal in each channel at the output of the variable delay block can be written as S i;delayed (t) =GA cos !(t (i 1) d sin in c (Ni + 1)) ; (3.2) whereG is the gain of each channel's front end. We are now in a position to compute the Array Factor (AF ) of this phased-array receiver. AF is dened as the additional power gain achieved by the phased-array receiver over the power gain of a single channel. After summingS i;delayed (t) across the dierent channels and determining the ratio of the power of the summed signal to that of the signal in each channel, AF can be found to be AF (; in ) = 0 @ sin N(! !d c sin in ) 2 sin ! !d c sin in 2 1 A 2 : (3.3) When = d sin in c , an additional power gain of N 2 is achieved by the phased array as the path dierences in free space are perfectly compensated for and the received sinusoids are added coherently. AF is lower for other angles of incidence, and hence the angle of incidence of peak gain, called the beam-pointing angle, can be written in terms of as m = sin 1 c d : (3.4) 63 Figure 3.2: 4-channel receiver array factor for dierent values of , namely 4! , 2 4! ... 8 4! . The inter-antenna spacing is assumed to be 2 , where is the free-space wavelength at the frequency of operation !. The fact that AF is lower for other angles of incidence indicates that the phased-array receiver possesses spatial selectivity. This can be benecial in wireless systems that are interference-limited - a strong interferer that is located in a direction that is dierent from the desired transmitter can be rejected by a phased-array receiver. For radar and imaging systems, the spatial selectivity enables high spatial-resolution imaging. Fig. 3.2 shows AF versus the angle of incidence for dierent values of , namely 4! , 2 4! ... 8 4! . A 4-element phased-array receiver is considered with the inter-antenna spacing set to 2 , where is the free-space wavelength at the frequency of operation !. Each setting of results in a dierent beam-pointing angle. Hence, the changing of the value of the variable delay elements in each signal path allows us to electronically steer the beam 2 . From antenna theory, the -3dB beamwidth (in radians) of a radiating aperture is approximately equal to D , whereD is the width of the aperture. In the case of a phased 2 2 is the most commonly-used inter-antenna spacing. A smaller spacing reduces the array's spatial selectivity. A larger spacing results in multiple main lobes. 64 array with a half-wavelength inter-antenna spacing, the total width is (N 1) 2 , and hence the -3dB beamwidth is given by Beamwidth 2 N 1 : (3.5) An increase in the number of elements results in a narrower beam. As can be seen from the array patterns of Fig. 3.2, there are incidence angles where the received signal completely vanishes. These are called nulls and occur because the signals from the dierent channels cancel each other. In the formulation of this section, all channels are assumed to have the same gain. However, by modifying the gain of the individual channels, it is possible to arbitrarily set the location of the nulls, which is useful for interference cancellation. In addition, there are local maxima in the array pattern away from the main lobe. These are called sidelobes or grating lobes. The number of sidelobes increases with an increase in the number of array elements. For the 4-element example in Fig. 3.2, there are two sidelobes, one on either side of the main lobe. In addition to spatial selectivity, phased-array receivers have the ability to improve the receiver sensitivity. In the direction of peak gain, a phased array achieves an addition power gain of N 2 over that of a single channel. This N 2 factor is fundamentally an enhancement in antenna gain due to the increased aperture size. However, if one assumes that each antenna picks up uncorrelated noise from the ambient surroundings, then the total output noise after the combining of the dierent channels is only N times larger than that of a single channel. Therefore, the signal-to-noise (SNR) ratio improves by a factor ofN in anN-channel phased array. This SNR-improvement is also seen when the 65 noise of the channel front-end dominates over the input noise (high noise-gure receivers), as the front-end noise is uncorrelated across the dierent channels. Since the array factor may also be viewed as an enhancement of antenna gain, phased arrays are also called active antennas, as the directionality of this enhancement can be electronically controlled. In the context of transmitters, the implementation of an N-channel phased-array transmitter implies that each channel must generate 1 N 2 times the power of a single-element transmitter to maintain the same received power level in the direction of maximum radiation. Thus, the total transmit-power that needs to be generated is N times lower than the single-element case. This is specially signicant in silicon-based technologies, specically CMOS, as the low breakdown voltages render power generation challenging. 3.4 Phased Arrays versus Timed Arrays As was described in section 3.3, a phased array modies the direction of transmis- sion/reception of the electromagnetic beam by introducing a variable time delay in each antenna's signal path to compensate for the path dierences in free space. Integrated variable-time delay blocks are dicult to implement in practice, particularly monolith- ically on silicon. Therefore, in narrowband systems, the required variable time delay is often approximated with a variable phase shift, and the variable delay elements are re- placed with phase shifters. The term phased array is actually a misnomer when variable delay elements are used and applies to arrays that use the narrowband approximation 66 (Fig. 3.3(b)). A more appropriate term for an array that employs variable delay elements is timed array (Fig. 3.3(a)). Figure 3.3: (a) Timed array. (b) Phased array. The validity of the delay-phase approximation in phased arrays naturally depends on the instantaneous bandwidth of the system. The approximation begins to fail when the instantaneous bandwidth of the system becomes large. Since timed arrays do not employ the delay-phase approximation, their functionality is theoretically unaected by the signal bandwidth. Let us assume that an electromagnetic beam is incident on the phased array of Fig. 3.3(b) at an angle in . If one assumes that the signal received by the rst antenna is of the form S 1 (t) =A(t) cos(!t +(t)), then the signal received by the i th antenna can be written as S i (t) =A t (i 1) d sin in c cos !(t (i 1) d sin in c ) +(t (i 1) d sin in c ) : (3.6) 67 Assuming that the antenna spacing,d, is equal to one half of the free-space wavelength at the frequency of operation, S i (t) reduces to S i (t) =A t (i 1) d sin in c cos !t (i 1) +(t (i 1) d sin in c ) ; (3.7) where = sin in . To receive this incident beam with maximum sensitivity, the phase shifters must be set to compensate for the free-space path dierence. Specically, i must be set to (i 1). Assuming that the second harmonic generated by downconver- sion is ltered out, the resultant downconverted baseband signal then becomes S BB (t) = N X i=1 A t (i 1) d sin in c cos (t (i 1) d sin in c ) 2 : (3.8) Equation (3.8) reveals that the delay experienced by the modulation signal in reaching the dierent antennas is not compensated for. To view the eect of this, the 22-29GHz vehicular-radar frequency band is used as an example. The radar range resolution is in- versely proportional to the signal bandwidth; a signal with 5GHz bandwidth can achieve a theoretical range resolution of 3cm . One simple radar signal is the pulsed sinusoid, which is nothing but a sinusoid running at the carrier frequency multiplied by a narrow, time- limited pulse. Consider a pulsed sinusoid with a center frequency of f = ! 2 =25.5GHz and 200ps pulse width for an automotive radar system. The bandwidth of this signal is roughly 1/200ps or 5GHz. In order to have a beamwidth of 7.5 , a 16-element array is needed. The time delay between successive array elements, given by sin( in )=2f for half- wavelength antenna spacing, is 16.9ps for in = 60 o . As can be seen from Fig. 3.4, there 68 time A1 A2 A12 A13 A14 A15 A16 A3 A1 time A2 time A3 time A12 time A13 time A14 time A15 time A16 T~1/BW (n-1) x sin( ) / (2f 0) =60 o 1/f 0 d = /2 n=16 Figure 3.4: The eect of the phase-shift approximation in a phased array that uses pulsed sinusoids with 5GHz of bandwidth around 25.5GHz. is no overlap between the signals of the last ve elements (A12-A16) and the rst element (A1) for a 60 incidence angle. A broadband phase shifter will align the sinusoids so that they add up coherently, only if they have some overlap. Delay elements are needed to shift the signals in time domain and align them. In this example, the 16-element array for the 60 incident angle will behave like a 12-element one at best. The need for variable delay elements versus variable phase shifters increases with the signal's fractional bandwidth, array size, and/or the maximum scanning angle. Figs. 3.5(a)-(c) depict the normalized array patterns produced by timed and phased arrays receiving a pulsed sinusoid with 25.5GHz center frequency. The angle of incidence is 69 Figure 3.5: Normalized array patterns for phased arrays operating at 25.5GHz. Timed- and phased-array implementations as considered. A pulsed-sinusoid signal is assumed with a center frequency of 25.5GHz. The angle of incidence is assumed to be 60 o . (a) 8-element array with a pulse width of 200ps. (b) 16-element array with a pulse width of 200ps. (c) 16-element array with a pulse width of 500ps. assumed to be 60 o , and the delay elements/phase shifters are set appropriately to steer the beam towards the angle of incidence. In Figs. 3.5(a) and (b), the number of array elements is changed from 8 to 16, and the pulse width is 200ps. As the number of array elements increases, the array performance degrades in the case of the phased array. The eect of the degradation is primarily seen in the reduced peak gain 3 , which corresponds to a reduced SNR. In Figs. 3.5(b) and (c), a 16-element array is considered and the pulse 3 The reduced peak gain is a direct result of the lack of overlap between the pulses received by the rst and last elements. 70 width is varied from 200ps to 500ps. It is clear that for larger signal bandwidths, the deterioration in the phased array's performance is greater. While this discussion focussed on radar systems, the arguments in the case of commu- nication systems are very similar. The lack of compensation of the delay experienced by the modulation signal in a phased array results in an Array-Induced Inter-Symbol Inter- fence eect when the various channels are combined. This degrades the SNR and Error Vector Magnitude (EVM) [70]. 3.4.1 A 1-13GHz SiGe UWB Variable Delay Element for Timed Arrays This section brie y describes the implementation of a 1-13GHz SiGe UWB variable delay element that can be used in timed arrays for high-performance radar and imaging systems. The dierence between timed and phased arrays, and the challenges involved in the implementation of a variable delay element on silicon are underscored. The prototype variable delay element accomplishes 4-bit delay variation for a total of 64ps of variable group delay with a 4ps resolution. In addition, the delay element features a maximum gain of 10dB, 5dB gain variation in 1dB steps, and a worst case -3dB gain bandwidth of 13GHz. The prototype chip was fabricated in IBM's 7HP 0.18m BiCMOS SiGe process [105], [106]. A system-level representation of the UWB delay element is presented in Fig. 3.6. The variable delay is achieved through the implementation of a tapped-delay trombone line (Fig. 3.7). There are two fundamental ways through which the delay of signal can be modied - variation of the distance travelled and variation of the propagation velocity. The tapped-delay trombone line employs input and output quasi-distributed transmission 71 Figure 3.6: Architecture of the 1-13GHz SiGe UWB variable delay element. Figure 3.7: System-level diagram of the 3-bit tapped-delay trombone line. lines, which are connected at various tap points using transconductance ampliers. Only one transconductance amplier is on at any time, and the selection of dierent ampliers varies the distance travelled by the signal from the input to the output, and hence the delay. The implementation of a large variable delay with a ne resolution requires a large number of sections in the trombone line. As the number of sections is increased, the loss of the line and the variations in group delay with frequency due to the discrete 72 nature of the line increase. Therefore, only 32ps of variable delay at 4ps resolution is realized in the trombone line. The most-signicant bit (MSB) of variable delay (32ps) is achieved through a 1-bit coarse-tuning element that uses an amplier that switches between the input and output of a coplanar stripline (CPS) with 32ps of delay. In order to conserve chip area, the coplanar stripline is folded several times over without modifying its transmission-line characteristics. The gain of the ampliers in the trombone line is limited by the input- and output- capacitance budget aorded by the discrete transmission lines present in the trombone line. To boost the gain of the overall system and achieve gain variability to combat the delay-setting-dependent loss of the trombone line, a variable-gain distributed amplier (VGDA) is implemented as the rst block of the system. In achieving the 64ps of variable delay at 4ps delay resolution over 13GHz of band- width with a system gain of 10dB, the prototype occupies 1.6mm 2 of silicon area and consumes 87.5mW of power from a 2.5V supply. The area and power consumption of the prototype are larger than the requirements of narrowband phase shifters operating at any frequency upto 13GHz. The area consumption is a direct result of the large number of inductors that are used in the quasi-distributed transmission lines employed in the trombone line and VGDA and the 32ps CPS used in the MSB delay element. The power consumption is a direct result of the multi-stage ampliers used in the trombone line, VGDA and the MSB delay element. Multiple stages are needed to achieve gain over a wide bandwidth given a limited input and output capacitance budget. This underscores the challenges involved in the implementation of monolithic broadband variable delay blocks on silicon. 73 This work was the result of a collaboration with John Roderick, currently a graduate student in the Electrical Engineering department at the University of Southern California (USC), and Kenneth Newton, formerly of USC. The contributions of the author of this thesis include the design of the VGDA, the MSB delay block, the delay-line passives and the conception of a broadbanding technique that was used in the trombone-line ampliers. The reader is referred to [106] for additional details. This work has inspired future work in the area of integrated timed arrays for high-resolution imaging [30],[29] 4 . 3.5 Conventional Phased Array Architectures The phase-shifters required to achieve phased-array functionality can be incorporated in dierent parts of the transmitter/receiver chain. This results in three distinct phased array architectures - RF Phase-shifting, LO Phase-shifting and Digital Arrays. This section examines the trade-os involved in these three architectures in detail 5 . 3.5.1 RF Phase-shifting Fig. 3.8 illustrates the RF phase-shifting architecture for phased arrays. In this architec- ture, the signals in the various channels are phase-shifted and combined in the RF domain. The combined signal is then downconverted to baseband using any generic receiver such as heterodyne, homodyne or other image rejection architectures. RF phase-shifting has traditionally been the most widespread phased-array architecture because of its ability 4 A more detailed description of the multi-beam timed-array architecture described in [29] is provided in Chapter 5. 5 Although all schematics represent receiver arrays, the basic principles apply to transmitter arrays as well. 74 Figure 3.8: The RF phase-shifting phased-array architecture. to insulate a larger portion of the receiver chain from strong, in-band interferers, as is shown in Fig. 3.8. A weak, desired signal and a strong, in-band interferer are assumed to be incident on the RF phase-shifting array, with the interferer incident along a null direction. Since the combining point occurs prior to downconversion in this architecture, the interferer is cancelled prior to the downconversion mixer. Therefore, the dynamic range requirements on the mixer and the blocks that follow it are alleviated. The main challenge in this architecture is the implementation of RF phase-shifters in silicon. Passive implementations tend to be lossy while active phase shifters must be designed with sucient linearity to accomodate strong interferers. An active phase shifter with insucient linearity essentially negates the advantage that the RF phase- shifting architecture enjoys in interference rejection. In addition, the noise performance of the phase shifter is critical as the phase shifter lies in the RF signal path and hence can potentially degrade the system noise gure. Another design choice is the implementation 75 of variable true-time-delay elements for wideband timed arrays versus phase shifters for narrowband phased arrays. As was mentioned earlier, control of the individual channel amplitudes is desirable as it allows for the modication of the null locations in the array pattern. Since the spatial ltering is done completely in the RF domain in this architecture, the variable- gain ampliers required for individual amplitude control must be placed in the RF domain. This is challenging as RF blocks are usually parasitic-sensitive, and hence a change in the gain usually is accompanied by a change in the phase response. Therefore, careful VGA design is required to ensure that gain change is not accompanied by phase change. Alternatively, the RF variable-gain ampliers can work in conjunction with the RF phase- shifters to set the null location while not altering the primary beam-pointing direction. Several silicon-based RF phase-shifter topologies have been investigated over a wide range of operating frequencies [89], [86], [87], [58], [21], [138], [67], [31], [2], [3]. For a comparative study of these topologies, the reader is directed to [70]. 3.5.2 LO Phase-shifting Fig. 3.9 displays the LO phase-shifting architecture for phased arrays. Since the mixing of the RF signal with the LO essentially results in a subtraction of their phases, phase- shifting of the LO of each signal path is equivalent to phase-shifting the RF signal. The advantage of this architecture over the RF phase-shifting approach is that the phase- shifters are removed from the RF signal path. As a result, the nonlinearity, loss and the noise performance of the phase-shifters no longer have a direct impact on the system performance. Furthermore, the variable gain that is required in each signal path for 76 Figure 3.9: The LO phase-shifting phased-array architecture. control of null locations can be placed in the IF domain. However, as is depicted in Fig. 3.9, strong, in-band interferers are cancelled only after the combining point, which occurs after the downconversion mixers. As a result, the mixers must have sucient dynamic range to withstand the interferers, which usually requires a large power dissipation. Any RF phase shifter may be used in the LO path to phase shift the LO signal for each channel. In general, the performance requirements on LO-path phase shifters are more relaxed when compared to RF-path phase shifters, and hence they can be expected to consume less area/power. Other techniques, including tuned ring oscillators [55],[91] and coupled oscillator arrays [17], have also been investigated for this architecture on silicon. The reader is directed to [70] for a comparative study. 77 The delay-phase approximation is inherent in the LO phase-shifting architecture as the LO is a single tone and cannot compensate for the delay progression of the received signals over a wide bandwidth. 3.5.3 Digital Arrays In the digital array architecture, which is depicted in Fig. 3.10, each phased-array channel is digitized using an Analog-to-Digital Converter (ADC) and the bits of all channels are then processed using a Digital Signal Processor (DSP), where the spatial ltering is performed. Therefore, strong intereferers get spatially cancelled only after digital signal processing, and hence the RF mixer and ADC of each channel and the DSP unit must have sucient dynamic range to handle the interferers. Furthermore, virtually the entire RF chain, except for the synthesizer, which is shared, is replicated for each channel. These two factors result in a rather power-hungry design. As a result, digital arrays are mainly suitable for applications that demand only a small number of elements (2-4), such as low-frequency WLAN [13],[92]. The main advantage of the digital array is its versatility. A wide variety of com- plex signal-processing algorithms can be implemented using DSPs. This is useful for smart antennas, which are extensively used in the cellular-phone industry. Examples of smart-antenna algorithms include those for multi-beam and multiple-input-multiple- output (MIMO) functionality. For a tutorial on smart antennas and common signal- processing algorithms that they employ, the reader is directed to [28]. 78 Figure 3.10: The digital array architecture. 3.6 The Eect of Mismatch in Phased Arrays The performance in the presence of channel mismatches is a critical parameter of any phased array. These variations result in amplitude and phase mismatches in the ra- diated/received signals and hence adversely aect the beam pattern [20],[112]. As an example, Fig. 3.11 shows the simulated array factor of a 4-element array in the presence of the deterministic amplitude and phase errors mentioned in the gure. The nominal beam-pointing direction is normal to the array, and the errors cause a deviation from this direction. The array also shows reduced peak gain. Most importantly, one of the sidelobe levels is higher and the nulls at angles of incidence of90 o have completely disappeared. For reference, 15 of phase variation corresponds to approximately 250m of length at 24GHz, assuming an eective dielectric constant of 4 6 . 6 The dielectric constant of silicon oxide is 4.1. 79 Figure 3.11: (Sample 4-element array factor (normalized to the ideal peak array gain of 16) in the presence of amplitude and phase errors. (a) Array factor in linear scale and polar coordinates. (b) Array factor in dB scale and Cartesian coordinates. In this section, the eect of phase mismatches between the channels of a conventional RF-phase-shifting array is analyzed. Simple equations are presented to quantify the eect of mismatches on various facets of array performance, including beam-pointing angle and sidelobe-rejection ratio (SLRR). In a monolithic phased array, these mismatches arise from multiple possible sources. The rst source is the intra-chip variation that is inherent to any process technology. The second source, which is particularly pronounced at millimeter-wave frequencies, arises from packaging mismatches in the interface between the integrated phased array and the o-chip antennas. A third source is mismatches between the o-chip antennas themselves. 3.6.1 Beam-pointing Error For phased arrays that employ the delay-phase approximation and utilize half-wavelength- spaced antennas, the array factor of (3.3) can be rewritten as 80 AF (; in ) = sin N( sin in ) 2 sin sin in 2 ! 2 ; (3.9) where is the phase progression introduced in the array. The beam-pointing angle can then be written as m = sin 1 . In [20] and [112], the eect of channel mismatches on the beam-pointing angle of a conventional RF-phase-shifting array is analyzed. The authors demonstrate that, to rst order, amplitude mismatches between phased array channels do not aect the beam- pointing angle, and only phase deviations need to be considered. The eect of phase errors on the beam-pointing angle can be summarized as m N X m=1 N X n=1 ( m n )(mn) cos m (N1)N 2 (N+1) 6 ; (3.10) where m is the beam-pointing error, m is the beam-pointing angle in the absence of errors and m is the phase error in the m th phased-array channel. This formula is derived for antennas that are half-wavelength apart, and considers only the linear terms of a Taylor Series expansion. For additional details on the formulation and derivation, the reader is directed to [112]. If each channel sustains phase errors that are small, independent and identically dis- tributed with a distribution of N(0; 2 phase ), the variance of the beam-pointing error can be computed from (3.10) to be 2 beam = 12 2 phase 2 cos 2 m (N 1)N(N + 1) : (3.11) 81 Figure 3.12: Standard deviation of the beam-pointing error as obtained from (3.11) and 300-iteration Monte-Carlo simulations of a conventional RF-phase-shifting array with phase =5 and 10 . The nominal phase shift of each channel is 0 , resulting in a nominal pointing angle that is normal to the array. Fig. 3.12 depicts beam as obtained from (3.11) and 300-iteration Monte-Carlo simu- lations of a conventional RF phase-shifting array with phase =5 and 10 . The nominal phase shift of each channel is 0 , resulting in a nominal pointing angle that is normal to the array. It is interesting to note that from (3.11) and Fig. 3.12, the variance of the beam-pointing error is seen to fall at the rate of 1 N 3 as N is increased. 3.6.2 Sidelobe Rejection Ratio Sidelobes are a feature of all phased arrays. In the absence of errors, the locations of the main lobe, sidelobes and nulls in the array factor can be determined by dierentiating (3.9) with respect to in and setting the derivative equal to zero. The locations of the main lobe and the sidelobes are the solutions to 82 tan N( sin in ) 2 =N tan sin in 2 : (3.12) The trivial solution of = sin in corresponds to the main lobe. Solving this transcendental equation for the rst or any other sidelobe is dicult. However, we have found that sin lobe N;lobe , where N;lobe = 2:929 N (3.13) proves to be an excellent approximation for the location of the rst sidelobes on either side of the main lobe. The sidelobe-rejection ratio (SLRR), dened as the ratio of the power of the main lobe to the power of these rst sidelobes, can now be computed as 7 SLRR 0 = N 2 AF (; lobe ) = N 2 sin 2 ( N;lobe 2 ) sin 2 ( N N;lobe 2 ) : (3.14) In order to determine the SLRR in the presence of channel mismatches, the array factor in the presence of mismatches is written as AF err (; in ;A 1 ::A N ; 1 :: N ) = N X i=1 (1 + A i A )e j((i1)( sin in )+ i ) 2 ; (3.15) where A i A = A i A A is the normalized amplitude error of each element, i is the phase error of each element and is the array's phase progression. The deterioration in the SLRR due to small amplitude and phase errors can be determined using the Taylor Series 7 The subscript of 0 signies that mismatches and process variations are absent. 83 AF err (; lobe ;A 1 ::A N ; 1 :: N ) =AF (; lobe ) + N X k=1 dAF err dk jall i ;A i =0 k + N X k=1 dAF err dA k jall i ;A i =0 A k : (3.16) The derivatives in the equation shown above may be computed from (3.15), and are found to be dAF err dk jall i ;A i =0 = 2 sin N N;lobe 2 sin (k N+1 2 ) N;lobe sin N;lobe 2 ; (3.17) dAF err dA k jall i ;A i =0 = 2 sin N N;lobe 2 cos (k N+1 2 ) N;lobe A sin N;lobe 2 : (3.18) If amplitude errors are absent and the channel phase errors are small, independent and identically distributed with a distribution ofN(0; 2 phase ), the variance ofAF err (; lobe ) can be computed from (3.16) to be 2 AFerr (; lobe ) = 2 2 phase sin 2 N N;lobe 2 sin 2 N;lobe 2 N sinN N;lobe sin N;lobe : (3.19) The standard deviation of the SLRR = N 2 AFerr (; lobe ) can then be computed to be 2 SLRR == 2 AFerr (; lobe ) SLRR 4 0 N 4 = 2N 4 2 phase sin 6 N;lobe 2 sin 6 N N;lobe 2 N sinN N;lobe sin N;lobe : (3.20) 84 Figure 3.13: (a) Standard deviation of the SLRR in a conventional RF-phase-shifting array as obtained from (3.20) and Monte-Carlo simulations. The nominal beam-pointing angle is normal to the array. (b) Theoretical 1- condence interval for the SLRR. Fig. 3.13(a) depicts SLRR as obtained from (3.20) and 300-iteration Monte-Carlo simulations of a conventional RF-phase-shifting array with phase =2.5 and 5 . The nominal phase shift of each channel is 0 . For large array sizes, from (3.20), SLRR 138:6 phase p N and hence reduces with an increase in array size. Fig. 3.13(b) presents another visualization, depicting the theoretical 1- condence interval for theSLRR in dB-scale. 3.6.3 Implications on Array Packaging As was discussed earlier in this chapter, there are two fundamental reasons that motivate the use of phased arrays in commercial wireless-communication applications and radar. The rst includes the increase in the transmitted power and the improvement in SNR at the receiver, which alleviate link-budget requirements. The second is the improved direc- tionality of the wireless link, which minimizes spatial interference and multipath eects. For applications that wish to harness the former, the accuracy of the beam-pointing angle 85 is of importance as an error in the direction of transmission/reception would deteriorate the link budget. On the other hand, in environments where spatial interference and mul- tipath eects dominate, the sidelobe-rejection ratio is a critical parameter. The analyses and simulations in this section indicate that channel mismatches have a greater impact on sidelobe rejection than beam-pointing angle for typical array sizes and mismatch values. This implies that packaging is a greater concern for applications that are dominated by interference and multipath eects. Accurate, robust and repeatable packaging techniques, especially for multiple-antenna systems, have yet to be developed at millimeter-wave fre- quencies. Techniques such as ip-chip antenna bonding [98] and on-chip antennas [10] show promise in combating this problem. 3.6.4 Array Calibration The mismatch between channels, induced by the process, packaging, connection to the antennas, and channel-to-channel signal coupling, deteriorates the antenna-array perfor- mance and is often calibrated in factory in high-performance military-type phased arrays. Process mismatches aside, a phase error of15 at millimeter-wave frequencies corre- sponds to a few tens of microns of length variation in a wirebond, printed-circuit-board traces, chip-antenna connections, or antennas themselves if implemented o-chip. Varia- tions of this order, even if calibrated at the time of manufacturing, might occur during the lifetime of a commercial system as the temparature and other ambient conditions change. In order to realize robust silicon-based single-chip antenna arrays for commercial com- munication and sensing applications, on-chip testing and calibration techniques must be developed that measure the deterioration of array performance and appropriately correct 86 the amplitudes and phases. Such on-chip testing and calibration techniques would also greatly reduce test cost, which is critical for commercial millimeter-wave applications. In a communication system, measurement of array performance can be done at the system level where the gains and phases are adjusted to maximize the SNR. In a sensing array such as the automotive-radar application, calibration through the sending of a training sequence between the transmitter and receiver, e.g., smart-antenna concepts, is not pos- sible. Calibration techniques similar to [41] and [9] that rely on the mutual coupling between the antenna elements may be utilized, although the eect of on-chip coupling though the substrate must be considered as well. The development of such calibration techniques is an important research direction for the future. 3.7 The Eect of Quantization Error in Phased Arrays Practical phase shifters and delay elements have a nite number of settings and hence yield a discrete set of phases/delays. As a result, the steering angles achievable in practical phased arrays are also quantized. This can lead to a mismatch between the direction of arrival of the desired signal and the beam-pointing angle, which causes a reduction in the SNR. Furthermore, while calibration techniques can correct for process and packaging mismatches, the nite delay/phase settings of practical phase shifters limits the extent of correction. Therefore, the phase-shifter resolution must be chosen with the calibration of process and packaging mismatches in mind. Fig. 3.14 depicts an N-element, RF-phase-shifting, homodyne phased-array receiver with quadrature downconversion and half-wavelength-spaced antennas. The variable 87 Figure 3.14: N-element RF-phase-shifting homodyne phased-array receiver with quadra- ture downconversion. phase-shifters for each signal path are assumed to be controlled by n digital control bits, giving rise to 2 n phase-shift settings. For example, a 3-bit phase shifter can sus- tain shifts of180 o ,135 o , 90 o ... 135 o , corresponding to a phase-shifting resolution of res = 360 o 2 n = 45 o and a beam-steering resolution of res = sin 1 res = sin 1 1 2 n1 = 14:48 o . An incoming quadrature amplitude-modulated (QAM) signal of the formi(t) sin(!t)+ q(t) cos(!t) is assumed, where i(t) and q(t) are the in-phase (I) and quadrature (Q) information signals. The I and Q LO signals are assumed to be sin(!t) and cos(!t) respectively, and the RF phase-shifter k is set to (k 1) (with set to the discrete phase dierence closest to the incoming phase dierence of sin in ). The nal combined signals in the I and Q channels can be determined to be I comb (t) = i(t) 2 p AF (; in ); (3.21) 88 Q comb (t) = q(t) 2 p AF (; in ): (3.22) where AF is the array factor dened in (3.9). A number of assumptions are implicit in the above equation. The second harmonics produced by the mixers are assumed to be ltered out. Secondly, the bandwidth of the information signal is assumed to be small compared to the carrier frequency to eliminate the Array-induced ISI eect. Finally, if the discrete phase-shifter settings are not able to perfectly compensate for the delay in free space (6= sin in ), the recovered constellation is rotated due to leakage of I into the Q channel and Q into the I channel. This systematic rotation is assumed to be undone in the receiver. When the discrete phase-shifter settings are not able to perfectly compensate for the delay in free space,AF (; in )<N 2 , the peak array power gain, causing the receiver to show reduced gain and hence, reduced SNR. This is a direct result of the fact that the direction of arrival of the incoming signal and the beam-pointing angle are mismatched. The resultant SNR degradation can be quantied as SNR =SNR o AF (; in ) N 2 ; (3.23) where SNR o is the SNR in the absence of the eect of discrete phases, and includes the input SNR, receiver front-end noise gure (NF ) and the 10log 10 (N) phased-array improvement 8 . 8 The 10log10(N) SNR improvement assumes that each antenna picks up uncorrelated noise from the surroundings. It is also true when the receiver front-end NF dominates over the input noise, as the front-end noise would be uncorrelated between dierent signal paths. 89 The SNR reduction can be related to a degradation in the Error Vector Magnitude (EVM ) as EVM = 1 p SNR = 1 p SNR o N p AF (; in ) : (3.24) Figure 3.15: EVM degradation, caused by discrete phases, as a function of the incidence angle, phase-shifter bits and number of elementsN. A Simulink simulation of a 16-QAM input incident on an 8-element quadrature RF-phase-shifting homodyne receiver is also shown. SNR o = 33:2dB and 3-bit phase-shifters are assumed. Fig. 3.15 shows the theoretical EVM -degradation factor, i.e., the N p AF -term in (3.24), as a function of the angle of incidence for 4- and 8-element arrays, with 3- and 4-bit phase shifting in each case. A Simulink simulation of an 8-element quadrature RF-phase-shifting homodyne receiver with 3-bit phase-shifters receiving a 16-QAM input is also included. SNR o is set to be 33.2dB (corresponding to, for instance, an input SNR of 30.2dB and a receiver front-end NF of 6dB, along with the 10log 10 (8) array SNR improvement), resulting in EVM o =1.5%. 90 As can be seen in Fig. 3.15(a), the maximum degradation in EVM occurs when the progressive phase-shift of the incoming wave in space lies right between the phase-shifting resolution of the receiver. This maximum degradation can be computed to be EVM EVM o max = N sin res 4 sin Nres 4 : (3.25) As N, the number of elements, is increased, for a xed phase-shifting resolution, the maximum EVM degradation increases. This is because the beam becomes narrower, resulting in a higher gain and SNR penalty when the incoming direction and the beam- pointing angle are mismatched. This eect is re ected in Fig. 3.15(a). Therefore, for a practical phased array, the choice of the number of phase-shifter bits is governed by N and the desired upper bound on EVM degradation. A larger number of bits is required for larger arrays. The extent of process and packaging mismatches and their calibration must also be kept in mind when choosing the phase-shifter resolution. 3.8 Summary In this chapter, a historical perspective of the phased array was provided, and the con- ventional military phased array was compared and constrasted to the silicon-based arrays that are being investigated for commercial millimeter-wave applications. A distinction between phased arrays and timed arrays as made, and a 1-13GHz UWB variable delay element for timed arrays, implemented in a 0.18m SiGe process, was presented. The variable delay element has inspired future work in the area of integrated timed arrays for high-resolution radar applications. Analyses to capture the impact of process and 91 packaging mismatches and phase-quantization error on array performance were also pro- vided in this chapter. These analyses provide the system designer with simple expressions that predict the performance that can be expected from integrated phased arrays, and motivate the need for on-chip array-calibration techniques. Silicon-based processes are a dierent playground when compared to the realm of dis- crete components based on III-V compound semiconductors. While the performances of both active and passive devices are often inferior in silicon-based processes, the reliability of the process enables the integration of larger systems and more devices onto a single chip. As a result, it becomes possible to integrate digital signal processing and calibration circuitry to increase functionality and ne-tune system performance. Furthermore, one may envision alternate phased-array architectures that dier from the conventional archi- tectures that were described in this chapter and harness these silicon-specic advantages to improve performance metrics, such as the power and area consumption. These are metrics that were of limited importance for conventional military applications, but are critical for the emerging commercial applications. Chapter 4 presents such an architecture that diers from the conventional phased-array architectures presented in this chapter. 92 Chapter 4 A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Arrays Chapter 3 provided an introduction to phased arrays and motivated the integration of phased-array transceivers in silicon for commercial millimeter-wave communication and radar applications. Although silicon, specically CMOS, boasts a signicant cost and yield advantage, the integration of phased arrays on silicon is fraught with challenges. The large area and power requirements that result from the implementation of multiple signal paths call for the formulation of innovative architectures that alleviate these requirements. Furthermore, as was discussed in Chapter 2, the conductive nature of the substrate makes the implementation of blocks such as passive elements, power combiners/splitters and phase shifters challenging, especially at millimeter-wave frequencies. This chapter describes a Variable-Phase Ring Oscillator (VPRO) and Phase-Locked Loop (PLL) phased-array transceiver architecture [72],[74],[75]. This architecture achieves full phased-array functionality by exploiting the nonlinear injection-pulling properties of tuned ring oscillators locked in a PLL. The area and power requirements are reduced through the elimination of a number of key phased-array building blocks, such as mixers, 93 power splitters/combiners and phase shifters. The VPRO-PLL phased-array transceiver is essentially a nonlinear multi-functional circuit that uses the power of silicon integration to harness a nonlinear phenomenon that is conventionally viewed to be a nuisance factor. Various performance metrics of the architecture, including sensitivity, linearity and array performance in the presence of process mismatches, are theoretically analyzed. Exper- imental results from two highly-integrated CMOS prototypes operating in the vicinity of 24GHz, one narrowband and one ultra-wideband, are presented, and topics for future research are outlined. 4.1 The Variable-Phase Ring Oscillator and PLL Architecture 4.1.1 VPRO Concept The VPRO (Fig. 4.1(a)) consists of a number of elements connected in a ring congu- ration, with each element comprising a nonlinear gain block driving a tuned load. Fig. 4.1(b) shows a MOS implementation of each element, where the gain block is realized through a dierential pair. The VPRO is similar to the conventional tuned ring oscillator ([55], [91], [82], [109]) save for the fact that an electrically-tunable phase shifter is intro- duced in the ring. The phase boundary condition asserts that the total phase shift in the ring be an integral multiple of 2. Assuming identical elements, the phase shift across each element (from V i1 to V i ) must then be given by = 2k ext N ;k2Z; (4.1) 94 Figure 4.1: (a) Block diagram of the Variable-Phase Ring Oscillator (VPRO). (b) MOSFET-based dierential pair implementation of a VPRO element, and the \satura- tion block" model for the dierential pair. (c) Dependence of VPRO oscillation frequency (! osc ) on the inter-element phase shift (). where ext is the extra phase introduced by the electrically-tunable phase shifter andN is the number of elements in the VPRO. Hence, through control of the external phase shifter, an electrically-tunable linear phase progression is established, which is the requirement for beam-steering. It must be noted that to sustain this phase shift across each element, the oscillator has to operate at a frequency that is o the LC center frequency. This is depicted qualitatively in Fig. 4.1(c), which shows the oscillation frequencies for dierent inter-element phase shifts and an LC center frequency of 24GHz. As was mentioned in the previous chapter, the conventional tuned ring oscillator has been employed to generate multiple LO phases for LO phase-shifting phased ar- rays [55], [91]. The conventional tuned ring oscillator employs phase inversion, through ipping of dierential signals, in the place of the external phase shifter. As a result, 95 only a static phase progression is established, and all LO phases must be routed to all phased-array channels, where the appropriate phase is selected locally. The resultant LO phase-distribution network is rather area and power hungry. The VPRO's tunable phase progression implies that each VPRO node needs to be routed only to a single channel, thus eliminating the LO phase-distribution network. To quantitatively determine the steady-state oscillation parameters of the VPRO, let us assume that the steady-state VPRO oscillation frequency is! osc , andV i =A i cos(! osc t+ i ), where A i and i are constant with time. The nMOS-based dierential pair may be modeled as a \saturation-block" (Fig. 4.1(b)). The dierential current is directly pro- portional (with slope g m ) to the input dierential voltage when the latter is less than a voltage threshold (V th ). Outside the threshold, the dierential current saturates, since all the current has swung to one branch of the nMOS pair. Hence, g m V th = I bias 2 . Let us denote the nonlinear saturation-block transconductance as the functionf. The nonlinear dierential equations governing the i th unit cell are C i d 2 V i dt 2 + V i L i + 1 R i dV i dt = df(V i1 ) dt : (4.2) Substituting for V i , we have df(V i1 ) dt = 1! 2 osc L i C i L i A i cos(! osc t + i ) ! osc A i sin(! osc t + i ) R i : (4.3) L i and C i are the inductance and capacitance of the i th unit cell and R i is the equiva- lent parallel resistance of the resonant tank representing all of the tank loss. Transistor parasitics may be incorporated into C i and R i in the above equations. The right hand 96 side of (4.3) is a nonlinear function of a sinusoid. This function may be replaced with its fundamental Fourier component under the assumption that each resonant tank boasts a high Quality Factor (Q) and substantially attenuates higher order harmonics. This fundamental component of df(V i1 ) dt may be computed to be df(V i1 ) dt fund = g m A i1 ( i1 + sin( i1 ))! osc sin(! osc t + i1 ); (4.4) where i1 = 2 sin 1 ( V th A i1 ). Assuming that all elements are identical (L i = L;C i = C and R i =R,8 i2 1::N), we may equate the phase of both sides of (4.3) to obtain i i1 = = tan 1 R ! osc L (1 ! 2 osc ! 2 0 ) ; (4.5) where! 0 = 1 p LC . Equation (4.5) in conjunction with (4.1) determines the steady-state os- cillation frequency! osc . If all unit cells are identical, then from symmetry, all amplitudes are equal. This oscillation amplitude (A) can be obtained by equating the amplitudes of both sides of (4.3), and is the solution to g m R cos ( + sin()) = 1: (4.6) The oscillation amplitude reduces to A = 2 I bias R cos for A >> V th , as sin 2V th A . It does not depend on the number of stages, and linearly increases with bias current as expected. The presence of a limiting supply voltage has not been taken into account in this formulation, and will eventually restrict the oscillation amplitude. The amplitude 97 decreases as increases, as the tuned loads function farther o their center frequency and present lower impedance. Figure 4.2: (a) Oscillation amplitude of an 8-element 24GHz VPRO with 0 o phase pro- gression versus bias current. (b) Oscillation amplitude of a 24GHz VPRO versus phase progression - the phase progression is generated by considering rings of dierent sizes and incorporating 180 o sign inversion prior to feedback ( = 180 o N ). To verify these results, simulations are carried out in the Cadence SpectreRF envi- ronment using IBM's 8RF 0.13m CMOS process. The dierential pair of each element consists of nMOS transistors with 100 ngers of width 0.48m each, and an ideal tail current source is used. The tuned-load component values are L = 167pH,R = 240 and C = 200fF, resulting in a center frequency (! 0 ) of approximately 24GHz 1 and Q=10. Fig. 4.2(a) depicts the oscillation amplitude of an 8-element ring with 0 o element phase shift for dierent bias currents, while Fig. 4.2(b) depicts the amplitude for I bias =5mA for dierent element phase shifts 2 . 1 Device parasitics contribute another 80fF approximately. 2 The \saturation-block" parameters gm and V th are computed for the dierent bias currents using standard short-channel MOSFET device equations. 98 The sustainable phase shift across an RLC-load ranges from -90 o to +90 o . However, in practice, achievable element phase shifts in a VPRO are limited by the oscillator's start-up requirement. This is because the RLC-impedance decreases with an increase in phase shift, resulting in a deterioration of the gain of each tuned amplier. The current of the dierential pairs can be increased to recover gain only till the point of velocity saturation. A further increase in the transconductance of the devices can only be achieved by increasing the device size, which is limited by the nite capacitance budget aorded by the tuned load. For IBM's 8RF 0.13m CMOS technology, the achievable phase shifts are seen to range from approximately -60 o to +60 o . This range corresponds to a steering capability of20 o < m < 20 o for half-wavelength-spaced antennas. However, the dierential nature of the VPRO implies that the complementary phase shift (180 o - ) is inherently available through phase inversion of alternate VPRO nodes. As a result, element phase shifts of -180 o to -120 o and 120 o to 180 o can also be achieved. This leads to an additional steering capability of90 o < m <40 o and 40 o < m < 90 o . Later in this chapter, a half-rate VPRO-PLL phased-array-transmitter architecture is described that achieves full beam-steering coverage. The VPRO is implemented at half of the desired output operating frequency and frequency doublers are interposed between the VPRO and the transmitter output stages. The doublers not only double the operating frequency but also the inter-element phase shift. When coupled with dierential phase inversion, this technique provides full beam-steering coverage. The fact that the total phase shift in the ring can be any integral multiple of 2 can lead to multiple possible modes of oscillation, particularly in rings of large sizes. These modes correspond to dierent integer values of k in (4.1), and exhibit dierent element 99 Figure 4.3: Voltage waveforms of successive nodes in a 24GHz 8-element VPRO with no external phase shift. (a) All element voltages are in phase. (b)45 o phase shift between successive nodes. phase shifts. For example, an 8-element VPRO with ext = 0 o can sustain oscillations with = 0 o ; 45 o and45 o corresponding to k = 0; 1 and1 respectively. The steady- state mode that is achieved depends on the initial condition of the oscillator. Fig. 4.3 shows the 0 o and45 o modes of a 24GHz 8-element VPRO, achieved in simulation through appropriate assignment of the element initial conditions. As is clear from the gure, and from (4.5) and (4.6), modes with dierent element phase shifts have dierent amplitudes and oscillation frequencies. Throughout this chapter, the focus will be on the fundamental mode corresponding to k = 0. For large array sizes, techniques that force the desired mode of oscillation must be investigated. 4.1.2 Transmit Mode The presence of a tunable linear phase progression across the elements of the VPRO implies that, in transmit (TX) mode, the output of each element can simply be connected to an antenna through an output stage to accomplish beam-steering. Fig. 4.4 shows the block diagram of the VPRO-PLL architecture in TX mode, with each element's output connected to a power amplier and antenna. 100 Figure 4.4: Principle of operation of the VPRO-PLL architecture in transmit (TX) mode. Equation (4.5) and Fig. 4.1(c) reveal that when the external phase shifter's value is changed to steer the beam, the oscillation frequency of the VPRO changes as the phase shift across each tuned load changes. The incorporation of a PLL around the VPRO, shown in Fig. 4.4 with frequency dividers, phase-frequency detector (PFD), charge pump (CP) and a loop lter, ensures that the operating frequency remains constant while maintaining the desired phase progression 3 . The modulation of information onto the carrier may also be accomplished through the PLL. As is shown in Fig. 4.4, a signal injected in the current domain (I in ) into the loop lter in parallel with the charge pump's output current gets phase-modulated (PM) 3 PLLs have been used to generate phase shifts for phased-array applications in the past. In [62], the authors present an architecture that employs a VCO and PLL for each antenna path. The phase of the VCO of each path is controlled by adding a controllable DC oset to the output of the phase detector of each PLL. 101 onto the carrier. Fig. 4.4 also depicts the small signal model of the PLL, withK vco ,N div , K PD and F (s) representing the VPRO tuning gain, frequency-division ratio, PFD-CP gain and loop lter transfer function respectively. in and I in are the reference phase and injected modulation current respectively. The VPRO phase vpro may be computed to be vpro (s) = K PD K vco N div F (s) sN div +K PD K vco F (s) in (s) + K vco N div F (s) sN div +K PD K vco F (s) I in (s): (4.7) From the expression above, it is clear that the injected current gets directly translated to the phase of the VPRO through a transfer function. The bandwidth of the VPRO-PLL architecture in transmit-mode is limited by this transfer function. When dividers are included in the architecture, the PLL PM bandwidth scales down with the division ratio. Fig. 4.5 depicts the theoretical PLL PM -3dB bandwidth as a function of the division ratio for typical 24GHz VPRO-PLL loop parameters. K vco is assumed to be 3.72Grad/s and the charge pump current is assumed to be 1mA, resulting in K pd =0.16mA/rad. The loop lter resistance (R lf ) is assumed to be 30k and the loop lter capacitances C 1 and C 2 are scaled up linearly with N div as C 1 =15fFN div and C 2 = C 1 10 to maintain a constant ratio of PLL loop bandwidth 4 to the reference frequency. Since the PLL PM transfer function has the same dependence on frequency as the PLL loop transfer function in (4.7), the PLL PM bandwidth also reduces linearly with an increase in N div . Of the two prototypes operating in the vicinity of 24GHz described later in this chapter, the 4 The PLL loop bandwidth is the bandwidth of the transfer function from in to vpro in (4.7). 102 rst employs a divide-by-128 PLL resulting in a low PLL PM bandwidth. In order to achieve PLL PM bandwidths in excess of 1GHz for high data rates, the second prototype utilizes an on-chip, high-frequency reference oscillator to which the VPRO is locked in a divider-less primary PLL. The on-chip reference is further locked to a stable, o-chip, low-frequency reference in a secondary, divide-by-128 PLL. Since the divider-less primary PLL performs the phase modulation, high data rates may be achieved. For ultra-wide bandwidths, the overall system bandwidth is also aected by the bandwidth of the tuned blocks that follow the VPRO, such as the power ampliers and antennas. Figure 4.5: Dependence of the 24GHz PLL PM transfer function -3dB bandwidth on the PLL division ratio, N div . The loop lter capacitances C 1 and C 2 are scaled up linearly with N div to maintain a constant ratio of PLL loop bandwidth to reference frequency. The PLL phase-modulation approach is also extensively used in polar transmitters for the GSM standard [40],[117]. The nonlinearity of the oscillator's K vco prole can cause variations in the modulation gain and bandwidth and self-calibration techniques have been developed for GSM polar transmitters to tackle this problem. In [40], one such 103 scheme is described, wherein theK vco nonlinearity is measured and then compensated for through the charge pump current using on-chip circuitry. Such techniques may be applied to the VPRO-PLL architecture as well. Support for amplitude-modulation schemes, such as QAM, can also be introduced in a manner similar to GSM polar transmitters through the incorporation of RF variable-gain ampiers (VGAs) in each channel after the VPRO to provide envelope information to the signal. It should be noted that such an implementation at 24GHz is challenging and deserves further research. 4.1.3 Receive Mode The block diagram of the VPRO-PLL architecture in receive mode is depicted in Fig. 4.6 when a plane wave is incident on the array. The signals received by the antennas are amplied by LNAs and then are injected into each element of the VPRO in the current domain. The VPRO and PLL phase-shift and power-combine the received signals to accomplish phased-array spatial selectivity, and then downconvert the combined signal at the control voltage, thus fullling all the requirements of a phased-array receiver. Consider anN-element generalization of the VPRO depicted in Fig. 4.6, with currents injected into everyLC tank (Fig. 4.7(a)). The injected signals are assumed to be sinusoids with frequency ! inj , which is close to the free-running frequency of the VPRO, and a constant phase progression , representing an incident plane wave. Therefore, I inj;i = I inj cos(! inj t + (i 1)). As was noted in Chapter 3, is related to the angle of incidence in as = sin in . Further, let the element voltages of the VPRO be represented in the form V i = V cos(! inj t + (i 1) + i ). No assumptions are made about i , which is, in general, a function of time. Therefore, there is no loss of generality. 104 Figure 4.6: Principle of operation of the VPRO-PLL architecture in receive (RX) mode. The nonlinear gain block of thei th element is driven by the previous element's voltage and hence generates a current whose fundamental component can be written as I cos(! inj t + (i 2) + i1 ). Fig. 4.7(a) represents these currents in vector form. The total current that ows into the LC tank, assuming weak injection ( = I inj I+I inj I inj I << 1), becomes I total;i I cos(! inj t + (i 2) + i1 + sin( i1 )): (4.8) The rst element is an exception to the above equation since the voltage driving it is the phase-shifted version of the last element. For the rst element, we have 105 I total;1 I cos(! inj t + (N 1)N + N + sin(N (N 1) N )): (4.9) Figure 4.7: (a) VPRO with injected and fundamental components of intrinsic currents added in vector form. (b) Taylor series approximation for LC phase-shift around the free-running frequency. The free-running frequency of the VPRO in the absence of injection, ! osc , is given by (4.1) and (4.5). The phase shift of the LC tank at a frequency ! in the vicinity of ! osc may be determined using the rst-order term of a Taylor-expansion with respect to frequency (as shown in Fig. 4.7(b)) and is equal to 2 R !oscL +tan 1+tan 2 !!osc !osc . The instantaneous frequency of the VPRO is ! inj + d 1 dt 5 . The phase shift of the LC tank at the instantaneous frequency must equal the phase dierence between the total current entering the tank and the element voltage. In other words, we have 5 When the injection is weak, we may assume that the injected signals do not disturb the phase distribution of the VPRO. Hence, i + as i + represents the phase dierence between Vi andVi1. Another implication of this is that i is independent of time, which means that all elements of the VPRO have the same instantaneous frequency equal to !inj + d 1 dt . 106 2 R !oscL +tan 1+tan 2 ! inj + d 1 dt !osc = + i sin( i1 ) for i6= 1; =N (N 1) + 1 N sin(N (N 1) N ) for i = 1;(4.10) where ! inj = ! inj ! osc and i = i i1 . Summing up (4.10) for all values of i and using the fact that i for weak injection, we have N 2Q + tan 1 + tan 2 ! inj + d 1 dt ! osc ! = N X i=1 sin( 1 + (i 1)( )); (4.11) where Q = R !oscL . Equation (4.11) can be simplied to yield d 1 dt =! inj ! osc (1 + tan 2 ) 2Q + tan sin N 2 ( ) N sin 2 ! sin( 1 + (N 1) 2 ()): (4.12) Let us rst consider the case of a free-running VPRO under external injection. Like all electrical oscillators, the VPRO may lock to the frequency of the injected signals if that frequency lies within a locking range. This phenomenon of injection locking was rst studied by Adler [1]. In the case of the VPRO, the locking range may be determined by setting d 1 dt =0 in (4.12) so that the frequency of the VPRO is ! inj , and then nding the maximum value of ! inj as 1 is varied. The result is straightforward and given by 107 ! lock = ! osc (1 + tan 2 ) 2Q + tan sin N 2 ( ) N sin 2 ! : (4.13) The second term in the expression for the locking range sin N 2 () N sin 2 is identical to the normalized array factor of a phased array of N elements, with being the progressive phase shift introduced in the receiver and the progressive phase shift of the received signals due to the path dierences in air in the direction of interest. Hence, the VPRO exhibits intrinsic beamforming tendencies which are manifested in its locking range. The constant multiplicative factor reduces to Adler's locking range result when all elements are in phase, i.e., = 0. When a VPRO stabilized by a PLL is subjected to external injection, the response is even more interesting. In [104], the author analyzes the response of a PLL-stabilized oscillator under external injection. The same is now done for the VPRO, but the analysis is performed in the frequency domain. In the absence of injection, =0, and hence 1ss =! inj t (the subscript denotes steady state). The phase of the rst element of the VPRO then becomes! osc t, indicating that the VPRO is oscillating at its free-running frequency. In the presence of injection, 1 can be written as 1ss + 1dev , where 1dev represents the deviation in 1 from its steady-state value. From (4.12), we have d 1dev dt =! lock sin( 1ss + 1dev + (N 1) 2 ( )): (4.14) Assuming weak injection, one may ignore the 1dev in the argument of the sine function leading to the following solution for 1dev : 108 1dev = ! lock ! inj cos(! inj t + (N 1) 2 ( )): (4.15) To determine the response of the PLL to injection, the traditional small-signal PLL model is considered and depicted in Fig. 4.8 (a). The phase deviation due to injection 1dev is modeled as an additive component. Using this model, the response at the control voltage (V ctrl ) can be determined to be V ctrl = sK pd F (s) sN div +K pd K vco F (s) 1dev : (4.16) From (4.16), it is clear that under injection, an oscillation is seen in the control voltage at the frequency dierence between the injection frequency and the lock frequency of the PLL. In other words, the VPRO-PLL receiver downconverts the injected signals at the control voltage. The imaginary frequency variable s represents the frequency of the deviations from the steady-state locked operation of the PLL, which is nothing but ! inj . HencejV ctrl j, the amplitude of the V ctrl oscillation, becomes jV ctrl j I inj = ! PLL (1 + tan 2 ) I(2Q + tan ) sin N 2 ( ) N sin 2 ! K pd F (j! inj ) j! inj N div +K pd K vco F (j! inj ) ; (4.17) where ! PLL is the lock frequency of the PLL and hence the operating frequency of the system. As was mentioned before, I inj is the amplitude of the current injected into each VPRO element andI is the amplitude of the intrinsic fundamental current of each VPRO element. 109 Figure 4.8: (a) Small signal model of the VPRO-PLL architecture in receive mode. (b) Simulink simulations of a 24GHz 4-channel VPRO-PLL receiver - spatial selectivity in the 0 o mode. (c) Simulink simulations of a 24GHz 4-channel VPRO-PLL receiver - frequency selectivity. From (4.17), the amplitude of the oscillation at V ctrl shows phased-array spatial se- lectivity. Hence, full phased-array receiver functionality, namely downconversion with spatial power combining, is achieved by using V ctrl as the output node. The received signal at V ctrl is also directly proportional to the injected signal strength I inj . This im- plies that the VPRO-PLL receiver has linear, small-signal downconversion gain, making it suitable for amplitude- and phase-modulation schemes. The DC value of the small-signal downconversion gain is ! PLL (1+tan 2 ) KvcoI(2Q+tan ) sin N 2 () N sin 2 . In order to verify the theoretical derivations, a Simulink model for a 4-channel, 24GHz VPRO-PLL receiver is created. The model for each VPRO element consists of a saturation block withg m =10mS andV th =0.5V and anLC tank with component values ofL=200pH, R=450 andC=195fF. The corresponding resonance frequency is approximately 24GHz and the Q is 14. A PLL is created with models for a standard tri-state PFD, charge-pump and a loop lter identical to the one shown in Fig. 4.6. To ease the simulation time, no dividers are included, resulting inN div =1. Varactors are included in each VPRO element for frequency control, and the VPRO tuning gain K vco is determined to be 3.72Grad/s 110 when the external phase shifter is set to zero. The charge-pump current, loop-lter resistance (R lf ) and capacitance (C 1 ) are chosen to be 1mA, 1k and 13.5pF respectively. The shunt capacitance of the loop lter (C 2 ) is chosen to be C 1 10 . Signals with a varying phase progression , representing dierent angles of incidence, are injected into each of the four elements of the VPRO with an injection strength=0.01 and the control voltage is monitored. Fig. 4.8(b) shows the strength of the received signal at the control voltage as a function of , with the VPRO in 0 o -mode. A good agreement with theory is seen, verifying phased-array functionality. 4.1.4 Bandwidth of the VPRO-PLL Receiver From (4.17), the downconverted and spatially-combined signal at the control voltage has a frequency response that is governed by the PLL design parameters, such as N div , K pd , K vco andF (s). Fig. 4.8(c) shows the strength of the received signal at the control voltage as a function of the oset frequency ! inj . Once again, the VPRO is in the 0 o -mode and is also set to 0 o . A good match is seen between the simulation results and the theoretical prediction of (4.17). There is some peaking in the simulated response that is unexplained by the theory. In general, the frequency response is low-pass for traditional loop lters. It is interesting to note that this frequency response is identical to the PLL PM transfer function in transmit mode. As is the case with transmit-mode operation, the bandwidth of this frequency response reduces as the PLL is designed with higher division ratios. There is also a bandwidth associated with the quality of the spatial power-combining. In Section 4.1.3, the Taylor Expansion for the phase-shift of the LC tank is a valid 111 approximation only when the rst-order term is much smaller than unity. In other words, j! inj j << ! PLL (1+tan 2 ) 2Q+tan . This restriction is most stringent when =0 o . Assuming that the Taylor Expansion is valid as long as the rst-order term is less than 0.1, we have j! inj;max j = ! PLL 20Q : (4.18) For a 24GHz phased-array receiver with a quality factor of 10, this results in a double- sided bandwidth of 240MHz, which is sucient to cover the 250MHz ISM (Industrial, Scientic and Medical) band at that frequency. Finally, the system bandwidth is also aected by the bandwidth of the tuned blocks that precede the VPRO, such as the LNAs and input buers. However, the single- sided bandwidth of a tuned block functioning at ! PLL is given by ! PLL 2Q tuned 6 , whereQ tuned is the quality factor of the tuned block. This bandwidth is ten times larger than the VPRO-PLL spatial-power-combining bandwidth for the same quality factor. Therefore, the bandwidth of the tuned blocks is not a dominant factor in determining the system bandwidth. 4.2 Linearity of the VPRO-PLL Receiver The linearity of the VPRO-PLL receiver is seen to depend on two factors - the bias-current level in the VPRO and the linearity of the VPRO's tuning prole. In Section 4.1.3, the principle of operation of the VPRO-PLL receiver is detailed. The analysis is predicated on the assumption that I inj I+I inj I inj I << 1, where I inj is the 6 This assumes a second-order LC response. 112 amplitude of the currents injected into each VPRO element andI is the fundamental com- ponent of the nonlinear dierential current in each element. As I inj increases and begins to violate this assumption, the downconverted output begins to compress and harmonics are generated. While deriving the nonlinear response of the VPRO-PLL receiver when this assumption is violated is a daunting mathematical exercise, a rst-order estimate of the injection-current level at which the gain compresses by 1dB may be obtained through I inj;1dB I +I inj;1dB = 0:89 I inj;1dB I : (4.19) The factor of 0.89 is the multiplicative equivalent of -1dB. This yields an input-referred 1-dB compression level of I inj;1dB I 8 . When the oscillation amplitude A >> V th , I 2I bias , and hence the input-referred 1-dB compression level becomes I inj;1dB I bias 4 : (4.20) In order to verify this theoretical formulation, the Simulink model described in Section 4.1.3 is considered. To eliminate the eect of a nonlinearK vco tuning curve, the nonlinear varactors are replaced with perfectly linear ones. The inter-element phase shift is 0 o and in-phase currents are injected into each VPRO element at a 50MHz oset from the PLL lock frequency. The injection-current level at which the 50MHz output at the control voltage compresses by 1dB is determined for dierent bias-current levels in the VPRO 7 . The results of the simulation are summarized in Fig. 4.9(a) and a good agreement with 7 The bias current levels are varied by changing gm and keeping V th constant. 113 Figure 4.9: (a) Input referred 1-dB compression point - theory versus Simulink simula- tions. The nonlinear varactors are replaced with perfectly linear ones in the Simulink model to eliminate the eect of a nonlinear K vco tuning curve. (b) Eect of a nonlinear K vco tuning curve on linearity. (4.20) is seen. The input-referred 1-dB compression point increases linearly as the bias current per VPRO element is increased. The linearity of the K vco tuning curve of the VPRO also can play an important role. Fig. 4.9(b) illustrates a typical K vco tuning prole. The linear portion of the prole represents the linear-output operating region. Therefore, it is desirable to design the VPRO to have sucient linear tuning range for all angles of steering. 4.3 Phase Noise of Tuned Ring Oscillators An analysis of the noise performance of the VPRO-PLL phased-array receiver requires a formulation for the phase noise of the VPRO. This section begins with an overview of contemporary phase-noise theories and then analyzes the phase noise of tuned ring oscillators that employ 180 o phase inversion ([55], [91], [82], [109]). The phase noise of the VPRO, and therefore the NF of the VPRO-PLL receiver, require an extension to 114 this formulation that is dependent on the implementation of the tunable phase shifter. The following section, which formulates the NF of the VPRO-PLL receiver, considers a specic implementation of the phase shifter. The formulation of this section is also useful for other applications that employ tuned ring oscillators, such as phased arrays based on LO phase shifting [55], [91], clock and data recovery [109] and quadrature LO generation for sideband rejection [82]. 4.3.1 Review of Two Contemporary Phase Noise Theories Phase noise in oscillators has traditionally been an extremely popular eld for research [57],[79],[36]. In the context of electrical oscillators, one of the most widely accepted phase-noise theories is the Linear Time-Variant (LTV) theory developed by Hajimiri and Lee [57]. While this theory yields design insights and explains some observed (and hithero-unexplained) phenomena, such as the eect of waveform symmetry on icker- noise suppression and the cyclostationary noise eect in a Colpitts oscillator, the math- ematical shortcomings result in some anomalies. Firstly, this theory cannot explain the phenomenon of injection locking. Secondly, the theory predicts innite output power at the carrier, which is unphysical 8 . These short-comings are addressed in a more mathematically-rigorous theory devel- oped by Demir and Roychowdhury [36]. A brief review of this theory is presented below. Consider an oscillator with random perturbations. Using the state-equation formula- tion, the perturbed oscillator can be written as 8 The prediction of innite power at the carrier frequency is related to the manner in which the power spectral density (PSD) of the oscillator's voltage is determined once the spectral properties of the phase are known. Therefore, this aw is not fundamental to the LTV formulation, and is easily rectied. 115 dx(t) dt =f(x(t)) +B(x)b(t); (4.21) where x2 R n is the vector of state-variables, f( : ) : R n ! R n is the nonlinear function representing the active devices of the oscillator, B( : ) :R n !R np represents the instan- taneous modulation of the noise sources andb( : ) :R!R p is the vector of noise sources in the system. It should be noted thatB is the equivalent of the Noise Modulation Function dened in LTV theory. Let the steady-state solution to the unperturbed oscillator be denoted byx s (t), periodic with time-period T. Linearizing around this unperturbed solu- tion, we can form the dierential equations for the deviation w(t) from the unperturbed steady state. dw(t) dt = @f(x) @x j xs(t) w(t) +B(x s (t))b(t): (4.22) @f(x) @x j xs(t) is called the Jacobian (henceforth denoted by A(t)) and is T-periodic as well. The authors introduce a vector called the Perturbation Projection Vector (PPV) v(t), which plays the role of the Impulse Sensitivity Function (ISF) of LTV theory 9 . Loosely speaking, the PPV represents the time-varying sensitivity of the system to noise/perturbations to the various state variables. v(t) is the periodic solution (with period T) to the Adjoint System dw(t) dt =A T (t)w(t), normalized so thatv T (0)x 0 s (0) = 1. The phase deviation (t) is then given by the following stochastic dierential equation. 9 In [122], the authors demonstrate the equivalence of the PPV and the Impulse Sensitivity Function (ISF) employed in LTV theory. Hence, the PPV may also be determined through circuit simulations using the \Direct Measurement of Impulse Response" technique described in [57]. 116 d(t) dt =v T (t +(t))B(x s (t +(t)))b(t): (4.23) A stochastic characterization of this phase deviation under the assumption thatb(t) is a vector of uncorrelated white-noise sources (so thatE[b(t 1 )b T (t 2 )] =I p (t 1 t 2 )) reveals that the single-sideband phase-noise spectrum of the oscillator in dBc/Hz is given by L (f) 10log 10 ( f 2 o c 2 f 4 o c 2 + f 2 ) (4.24) for ff o , where f o = 1 T is the oscillation frequency and c = 1 T Z T 0 v T ()B(x s ())B T (x s ())v()d: (4.25) 4.3.2 PPV for the VPRO The dierential equation governing each node of the VPRO is given in (4.2). To obtain a system of rst-order dierential equations, let us choose the node voltage and its integral (normalized to the oscillation frequency ! osc ) as the state variables, so that x 2i1 = ! osc R V i dt and x 2i =V i for i2 1::N. Assuming all elements are identical, we have C dx 2i dt + 1 ! osc L x 2i1 + x 2i R =f(x 2i1 ) +B i (x s (t))b i (t); (4.26) 1 ! osc dx 2i1 dt =x 2i : (4.27) 117 b i (t) is the noise source injected in parallel to each tank. Possible sources of this noise include the FETs in the dierential pair and the parallel tank resistance. The unperturbed steady-state solution, as discussed earlier, is given by x 2i1s =A sin(! osc t + (i 1)), x 2is = A cos(! osc t + (i 1)). The dierential equations for the deviation from the unperturbed steady state (valid for t2 [0;T ]) are C dw 2i dt + w 2i1 ! osc L + w 2i R = [u(tt i 1 )u(tt i 2 )+u(tt i 3 )u(tt i 4 )]g m w 2i1 +B i (x s (t))b i (t); (4.28) 1 ! osc dw 2i1 dt =w 2i ; (4.29) where u(t) is the unit step function and t i 1 = 1 !osc cos 1 ( V th A ) i1 !osc , t i 2 = T 2 1 !osc cos 1 ( V th A ) i1 !osc , t i 3 = T 2 +t i 1 and t i 4 = T 2 +t i 2 (Fig. 4.10). These are the time instances where V i crosses V th causing all the current to swing to one side of the dierential pair. The resultant adjoint system is dw 2i dt =! osc w 2i1 + w 2i RC [u(tt i+1 1 )u(tt i+1 2 ) +u(tt i+1 3 )u(tt i+1 4 )] g m C w 2i+2 ; (4.30) dw 2i1 dt = ! 2 osc ! 0 w 2i : (4.31) 118 Figure 4.10: Graphical illustration of the time instants where V i crossesV th for = 0 o . The normalized periodic solution to the adjoint system (PPV) can be determined in a manner similar to the approach described in Chapter 4.1.1. Under the high-Q assumption, this turns out to be v 2i1 = 1 NA! osc cos cos(! osc t + (i 2)); (4.32) v 2i = 1 NA! osc cos sin(! osc t + (i 2)): (4.33) Noting that there is no noise associated with (4.29) (which renders the odd-indexed components of the PPV immaterial), the stochastic dierential equation for the phase deviation becomes d(t) dt = 1 CNA! osc cos N X i=1 sin(! osc (t+(t))+(i2))B i (x s (t+(t)))b i (t): (4.34) 119 Figure 4.11: Comparison of theoretical PPV with Cadence simulations using the \Di- rect Measurement of Impulse Response" method for a 5-element ring with 180 o phase inversion. It is interesting to note that the PPV for thei th node is 90 o out-of-phase from the input to the node rather than the node's output. This deviates from the traditional result, which holds for LC oscillators operating at their center frequency. The amplitude dependence of the PPV is as expected. A higher amplitude of oscillation results in greater immunity to perturbations due to noise or any other form of injection. The 1 N dependence is interesting and its implications are discussed later in this chapter. Finally, the PPV deteriorates (becomes larger) by a factor of cos() as the element phase shift is increased, resulting in a greater sensitivity to noise as the oscillator functions farther o the center frequency. To verify these results, a 5-element ring with 180 o phase inversion (element phase shift = 36 o ) is constructed in Cadence. The dierential pair of each element consists of nMOS transistors from IBM's 8RF design kit with 100 ngers of width 0.48m each, and an ideal 5mA tail current source is used. The tuned load's component values are L = 4nH, R = 240 and C = 6:33pF, resulting in a center frequency of approximately 1GHz and 120 Q=10. The PPV component for the voltage of the rst element is determined using the \Direct Measurement of Impulse Response" technique and is compared to the theory in Fig. 4.11. An excellent agreement is seen. 4.3.3 Dierential-Pair Noise Modulation Function To determine the NMF, B, we must nd the dierential output noise current of the dierential pair of Fig. 4.12(a) as a function of the instantaneous currents and voltages. Note that only the drain-current thermal noise is considered in this treatment. Other noise sources, such as gate-resistance noise, can be treated in a similar fashion. Flicker noise is ignored in this formulation, and therefore, the results are only valid in the 1 f 2 - region. Performing small signal analysis at a general time instant, we have, Figure 4.12: (a) Time-varying small-signal equivalent noise model for a dierential pair. (b) Dierential pair NMF B. 121 I dn;out = g m1 (t)I dn2 g m1 (t) +g m2 (t) + g m2 (t)I dn1 g m1 (t) +g m2 (t) ; (4.35) where I dn1 and I dn2 are the time-varying drain thermal-noise currents of the devices in the rms sense. The time-dependent device transconductances (g m1 (t) and g m2 (t)) can be determined using standard short-channel device models. The bias-dependent drain- current thermal-noise power of the FETs of IBM's 8RF 0.13m process is characterized and presented in Appendix A.2. There is a strong dependence onV gs , while the variation with V ds is weak, as expected. Hence, for analysis purposes, in Appendix A.2, the noise power is approximated with a piecewise linear t with respect to V gs . Since the device transconductance also primarily depends on V gs , the dierential output noise current I dn;out of stage i is primarily a function of the input voltage x 2i2 = V i1 . Fig. 4.12(b) shows the theoreticalI dn;out as a function ofV i1 and compares it to Cadence simulations for I bias =5 mA. A reasonable match is observed and this curve is the NMF B(x 2i2 (t)) for the i th element. The output noise is maximum when the dierential input is 0, and decreases as the input swings. When all the current has swung to one side, say FET 2, the output noise current drops to 0, since g m 1 = 0 and I dn 1 = 0. The PPV/ISF is also maximum when the dierential input is 0. Hence, due the alignment of the peaks of the PPV and the NMF, the dierential-pair-based ring oscillator does not possess good cyclo-stationary noise properties. 122 4.3.4 Phase Noise of the Tuned Ring Oscillator Using these formulations for the PPV and the NMF, the single-sideband phase-noise spectrum of the tuned ring oscillator in the 1 f 2 -region in dBc/Hz is given by L (f) 10log 10 ( f 2 c f 2 ); (4.36) where c = 1 2NC 2 A 2 ! 2 cos 2 Z 2 0 sin 2 B(A cos)d; (4.37) andf = ! 2 . As expected, phase noise improves with an increase in amplitudeA. Further, as N is increased, the phase noise improves by a factor of 10log 10 N. This is because the PPV's inverse-N dependence causes a 10log 10 N 2 phase-noise drop, but the number of noise sources in the circuit increases by a factor of N. Finally, as the inter-element phase shift is increased, the phase noise deteriorates due to the cos 2 term in the denominator, the reduction of oscillation amplitude (which contributes another cos 2 as seen in section I) and the integral term. Fig. 4.13(a) depicts the theoretical and simulated phase noise of a ring with 8 ele- ments, no inter-element phase shift 10 andI bias =5mA. The circuit parameters are identical those listed in Section 4.3.2. An close match is seen in the 1 f 2 -region, revealing that the theory is able to predict the phase noise to an accuracy of 1.5dB. Fig. 4.13(b) depicts the phase-noise dierence for rings of dierent sizes with and without boundary phase inver- sion at 1MHz oset (which lies in the 1 f 2 -region) to determine the eect of inter-element 10 In other words, boundary phase inversion is absent. 123 Figure 4.13: (a) Theoretical and simulated phase noise for an 8-element ring with no phase shift. (b) Phase noise dierence at 1MHz oset for rings with and without 180 o phase-inversion. phase shift. Again, I bias =5mA. Note that Fig. 4.13(b) also depicts the contribution of A 2 cos 2 in the denominator of (4.37) to the phase-noise degradation; the remaining degradation is due to the integral term. Fig. 4.14(a) depicts the phase noise improvement of rings of dierent sizes with I bias =5mA and no boundary phase inversion over a single element ring 11 . Once again, there is an extremely good match to the theoretical prediction. Fig. 4.14(b) shows the simulated phase noise at 1MHz oset for rings of dierent sizes without boundary phase inversion for a xed current budget of 50mA (I bias = 50 N mA per element). The resonant load parameters are scaled as L = N 0:4nH and C = 63:3 N pF to maintain a constant oscillation frequency. Assuming a constant quality factor of 10, the parallel resistance would scale as R = N 24 and the oscillation amplitude would remain the same. Equation (4.37) then dictates that the phase noise would remain roughly constant as the NMF,B, would scale down by a factor of N due to the decreasing current in each stage, 11 A 1-element ring with no boundary phase inversion is nothing but a cross-coupled LC oscillator 124 Figure 4.14: (a) Simulated phase noise at 1MHz oset for rings of dierent sizes with no phase shift (I bias = 5mA per element). (b) Simulated phase noise at 1MHz oset with a xed current budget (I bias = 50 N mA per element). thus cancelling the eect of NC 2 in the denominator. If boundary phase inversion is present, rings of lower sizes would experience phase noise deterioration due to the larger inter-element phase shift. This deterioration would be identical to that depicted in Fig. 4.13(b). The simulation results conrm these conclusions. Hence, if a phase resolution of 36 o is desired for an application with a xed current budget, the phase noise is better (by 5.5dB in this case) if one uses alternate node voltages of a 10-element ring with boundary phase inversion as opposed to a 5-element ring. Such an implementation, however, would be accompanied by an area penalty due to larger number of elements and larger inductor sizes. In this section, a comprehensive formulation for the phase noise of tuned ring oscil- lators was developed and supported by extensive simulations. The reader is referred to [73] for experimental results from low-frequency 50MHz discrete prototypes that further validate the formulation. 125 Figure 4.15: (a) Summary of the noise processes in the VPRO-PLL receiver. (b) Injection of the noise power of the reference impedance to determine NF . 4.4 Sensitivity of the VPRO-PLL Phased-Array Receiver Fig. 4.15(a) summarizes the noise processes in the VPRO-PLL receiver. Received input noise that is picked up by the antenna of each channel is amplied by the LNAs and injected into each element of the VPRO. This noise is converted into VPRO phase noise. Since the VPRO is locked in a PLL, this phase noise is downconverted to baseband at the control voltage by the PLL [56]. In order to determine the noise gure (NF ) of the VPRO-PLL phased-array receiver, it is necessary to determine the contributions of (a) the noise injected by the LNAs and (b) the noise of each VPRO element itself to the total noise seen at baseband at the control voltage. The noise contributions of the PLL components, such as the reference, frequency dividers and the PFD, also impact the overall NF . Their eect is included using the PLL noise formulation provided in [56]. 126 4.4.1 Contribution of VPRO Phase Noise In the previous section, the free-running phase noise of a conventional tuned ring oscillator is derived using the Demir-Roychowdhury phase-noise theory. The result directly applies to the VPRO as well if the noise contribution of the external phase shifter is ignored 12 . To determine NF , uncorrelated noise sources, equal in power to the noise of the dierential reference impedance Z o =100 , are assumed to be injected into each element of the VPRO, as shown in Fig. 4.15(b). The phase noise of the VPRO now becomes L (f) 10log 10 ( f 2 c 0 f 2 ); c 0 = Z 2 0 sin 2 I 2 n (A cos)d + Z 2 0 sin 2 kT Z o d 8 3 NC 2 A 2 f 2 cos 2 = Z 2 0 sin 2 I 2 n (A cos)d + kT Z o 8 3 NC 2 A 2 f 2 cos 2 : (4.38) The injected noise sources remain constant over the integration period (i.e., are not cyclostationary), resulting in a simpler contribution to the overall phase noise. If the noise contributions of the PLL components are negligible, the transfer function from the VPRO phase noise to the baseband control-voltage noise does not aect NF , as it is the same for both the reference impedance noise and the noise of the VPRO elements. Hence, the NF may now be directly computed from (4.37) and (4.38) to be 12 Later in this section, the noise contribution for a specic phase-shifter implementation is taken into account. The implementation corresponds to the ones used in the prototypes described later in this chapter. 127 NF = c 0 c 0 c = 1 + Z 2 0 sin 2 I 2 n (A cos)d kT Zo : (4.39) It should be noted that the formulation above represents the array NF , as the to- tal output noise is normalized to the output noise generated by reference impedance terminations at all N array inputs. In order to verify this formulation, simulations are performed on the Simulink model described in Section 4.1.3. The external phase shifter is implemented as four additional tuned stages that are identical to the original four. The external phase shift introduced by these additional elements is modied through their varactor control 13 . The noise model used for each dierential pair is described in Fig. 4.16(a). The dierential output noise current is equal to 4kT g m when the input voltage lies within the threshold voltage, and 0 otherwise. is the transistor's excess noise factor and is equal to 2/3 in large-channel devices. It is usually higher for short-channel devices. For this simplied model, assuming that the amplitude of oscillation A>>V th , the NF can be evaluated to be NF 1 + 32 g m V th Z 0 A : (4.40) Recalling from Section 4.1.1 that A 4gmV th R cos when A>>V th , the expression for NF can further be simplied to NF 1 + 8 Z 0 R cos : (4.41) 13 The external phase shifters in the prototypes described later in this chapter is also implemented in the same way. 128 Figure 4.16: (a) Simulink dierential pair noise model. (b) Array NF versus device for zero inter-element phase shift and g m =10mS. (c) Array NF versus device g m for zero inter-element phase shift and =3. The parallel resistance of the tuned loads, and hence the Q, is scaled inversely with g m to keep the output amplitude A constant. (d) Array NF versus inter-element phase shift for g m =10mS and =3. It should be noted the additional four tuned stages that act as the external phase shifter contribute as much noise as the primary four stages. This has been taken into account in the two equations above. Figs. 4.16(b)-(d) compare the NF as simulated in Simulink to the theoretical prediction of (4.41) for dierent values, g m values and inter-element phase shifts. In Fig. 4.16(b), as is expected, the NF increases with an increase in . g m =10mS and the external phase shift is set to 0 for this comparison. Fig. 4.16(c) depicts the variation of NF with g m . V th is assumed to remain constant at 0.5, is assumed to be 3 and there is no inter-element phase shift. The parallel resistance of the tuned loads, and hence the Q, are scaled inversely with g m to keep the output amplitude A constant. 129 As is predicted by (4.40), the NF increases with g m as the inversely-scaling Q prevents an increase in A 14 . Finally, in Fig. 4.16(d), the variation of NF with the inter-element phase shift is shown. g m is set to 10mS and to 3 for this comparison. NF increases with the inter-element phase shift due to the cos term in the denominator. However, the resultant degradation in sensitivity when the beam is steered away from the normal direction should be minimal, as the increase in NF is not signicant. 4.4.2 Contribution of PLL Components The noise contributions of the PLL components, such as the reference, frequency dividers and the PFD, also aect the overall NF . Let the variance of the reference phase at an oset frequency of f be denoted by 2 in;n (f). Phase-frequency detectors, when designed properly, seldom contribute signicantly towards the noise in a PLL [56]. Digital frequency dividers on the other hand may have a signicant impact. An ideal digital- divider chain improves the VCO phase noise by 20log(N div ) purely due to frequency scaling, whereN div is the division ratio. Real dividers degrade the phase noise below this ideal performance and their noise contribution may be included in the PLL small-signal model as an additive output phase-noise power n 2 div (f) as shown in Fig. 4.15(a) [56]. Following the analysis in [56] to include reference and divider noise, the overall NF may be computed to be NF = c 0 +N 2 div f 2 f 2 h n 2 div (f) + 2 in;n (f) i c 0 c : (4.42) 14 If gm is increased and Q is constant, the NF would remain constant due to a linearly-increasing amplitude as long as one remains in the current-limited regime. 130 In a standard digital frequency divider, the phase-noise deterioration reduces as the input swing increases. Therefore, the eect of the digital-divider chain can be mitigated by ensuring that the VPRO output swing presented to the dividers is large. The eect of reference phase noise is presented in Section 4.6 through measured NF plots for two dierent references. It should be pointed out that the array NF formulated in this subsection applies to the VPRO-PLL spatial-power-combining and downconversion scheme. The eect of this NF on the overall receiver arrayNF is reduced by the gain of the LNAs that precede the VPRO-PLL. For reference, the single-sideband (SSB) NF of conventional CMOS mixers at these frequencies ranges from 8dB to 17.5dB [39],[133],[38],[54]. Conventional phase shifters and power combiners contribute additional loss and/or noise. In practice, theNF of the VPRO-PLL spatial-power-combining and downconversion scheme is also degraded by factors that have not been included in the analysis of this section, such as icker noise at low oset frequencies. 4.5 VPRO Performance in the Presence of Process Mismatches As discussed in Chapter 3, the performance in the presence of mismatches is a critical parameter of any phased-array scheme. These variations result in amplitude and phase mismatches across the channels that adversely aect the beam pattern. This section ana- lyzes performance of the VPRO in the presence of process mismatches, and the resultant eect on the beam pattern [76]. 131 4.5.1 VPRO Phase Mismatch in the Presence of Process Mismatches Consider an N-element VPRO with the external phase-shifter set to ext =N. Each element produces a progressive phase shift of in the absence of mismatches. Thei th element's tuned load has a shunt resistance R, inductanceL and capacitanceC i ; the process mismatches are assumed to manifest themselves in the capacitance. This is a reasonable assumption because on-chip inductors are implemented using spirals, the in- ductances of which are primarily a function of their number of turns and size. The size of an on-chip spiral is usually of the order of 100s of microns, and hence is not signicantly aected by process mismatches. On the other hand, on-chip capacitance is either realized through metal-insulator-metal (MIM) structures, whose capacitance is highly sensitive to the small spacing between the plates, or, at mm-wave frequencies, the parasitic capaci- tance of the active devices, which is strongly aected by process mismatches. [24] presents the measured intra-die matching characteristics of MIM capacitors in a typical 0.18m CMOS process. The standard deviation of capacitance errors is shown to be lower than 0.1%. [115] and [47] show the intra-die standard deviation of MOSFET capacitance errors to lie between 0.1% and 1%. In this section, a conservative assumption of 1% standard deviation of capacitance errors is employed. The center frequency of the i th resonant tank is given by ! i = 1 p LC i .The nominal center frequency of each LC tank is ! 0 = 1 p LC , where C is the nominal value of C i . The center frequency error of each element ! i =! i ! 0 can be related to the capacitance error of each element through a rst-order Taylor Series expansion that results in ! i ! 0 = C i 2C . 132 As was seen in Section 4.1.1, i = i i1 = tan 1 R ! osc L (1 ! 2 osc ! 2 i ) ; (4.43) where ! osc is the nal operating frequency. ! osc may be determined using the boundary condition N X i=1 i =N. Under the simplifying assumption that all C i 's deviate only slightly from the desired value of C, the individual phase shifts may be computed using the rst-order terms of a multi-variate Taylor Series expansion. i = + N X j=1 d i d! j jall ! j 's=! 0 ! j : (4.44) Evaluating the various derivatives, the expression for the phase-shift error across the i th element, denoted by ( i ), can be derived to be 15 ( i ) = i 2Q 1 + tan 2 0 @ ! i ! 0 N X j=1 ! j N! o 1 A : (4.45) The error in the absolute phase of each element, relative to the phase of the rst element, may then be computed as i = i X k=2 ( k ) = 2Q 0 @ i X k=2 ! k ! 0 i 1 N N X j=1 ! j ! o 1 A 1 + tan 2 : (4.46) Since the phase of the rst element is considered as the reference, 1 =0. If the node capacitances are subject to small, independent and identically-distributed (i.i.d) errors 15 This formula assumes a high Q value. The exact expression is more complex. 133 Figure 4.17: Standard deviation of the phase error of each element for 24GHz VPROs of dierent sizes, 0 o phase progression and independent normally-distributed capacitance errors with a standard deviation of 1%. with anN(0; 2 cap ) distribution, the resultant center-frequency errors are also i.i.d with a distribution ofN(0; 2 cap ! 2 0 4C 2 ). The variance of the phase error of each element can then be computed to be i = Q cap (1 + tan 2 )C r (i 1)(Ni + 1) N : (4.47) To verify this equation, 300-iteration Monte-Carlo simulations are run on 24GHz VPROs of dierent sizes in Simulink. Each element is modeled as an ideal saturation block (Fig. 4.1(b)) with g m =10mS and V th =0.5V driving a tuned tank with R=450 , L=200pH and C=195.41fF. The resultant Q at resonance is 14. ext = 0 o and hence the element phase shift is nominally 0 o . cap is set to 2fF (1%). Fig. 4.17 compares the standard deviation of the phase error of each element with the theoretical prediction of 134 (4.47) 16 . Interestingly, when the phase is referred to the rst element, the phase error is maximum towards the center of the ring. These phase errors are not independent of each other, but are correlated. 4.5.2 VPRO Beam-pointing Error The expression for the beam-pointing error as function of the element phase errors was presented in Chapter 3. The VPRO phase errors from (4.46) can be substituted in (3.10) to obtain m 2Q 2 4 N X j=1 ! j ! 0 6 N 2 1 N X i=1 (i 1)(Ni + 1) ! i ! 0 3 5 (1 + tan 2 )N cos m : (4.48) If the node capacitances are subject to small, i.i.d errors with an N(0; 2 cap ) distribu- tion, the resultant variance of the beam-pointing error can be computed to be 2 beam = Q 2 2 cap 2 C 2 cos 2 m (1 + tan 2 ) 2 N 2 + 11 5N(N 2 1) : (4.49) The beam-pointing error worsens with an increase in Q, as a larger Q corresponds to a sharper phase-shift prole versus frequency for an RLC tuned load. This leads to a larger phase-shift error for a given center-frequency error. Therefore, there exists a trade- o between beam-pointing accuracy and other oscillator parameters such as start-up and free-running phase noise, which improve with a larger Q. 16 It is customary to accomodate for2 variation in IC design. Therefore, while this section and the ones that follow depict the standard deviations of the various array parameters, it is recommended to account for twice the depicted values. 135 Figure 4.18: (a) Standard deviation of the beam-pointing error versus the number of ele- ments as obtained from (4.49) and Monte-carlo simulations of 24GHz VPROs of dierent sizes ( cap = 2fF (1%) and ext = 0 o ). (b) Standard deviation of the beam-pointing error as obtained from (4.49) and Monte-Carlo simulations of a 4-element VPRO for dierent nominal element phase shifts. The resultant nominal beam-pointing angle is also shown. Equation (4.49) indicates that 2 beam reduces with an increase in N at the rate of 1 N . To verify this, 300-iteration Monte-Carlo simulations are run on 24GHz VPROs of dierent sizes with the same parameters as considered in Section 4.5.1. cap = 2fF (1%) and ext = 0 o . Fig. 4.18(a) compares the theoretical prediction to the simulation results 17 . From (4.49), 2 beam is expected to reduce with an increase in (which corresponds to steering the beam away from the normal direction). This is because as is increased, the slope of the RLC phase-shift prole reduces as the operating frequency moves away from the center frequency. Fig. 4.18(b) compares this theoretical prediction to Monte- Carlo simulations of a 4-element VPRO with varying . It should be noted that for 17 This reduction in 2 beam with N is not seen in the case of coupled-oscillator arrays, another phase- shifterless phased-array scheme. In coupled oscillator arrays, the variance is seen to increase with N, making phase-error management a larger burden [112]. A more detailed comparison between the VPRO and coupled-oscillator arrays is provided shortly. 136 large , i.e., large angles of steering (not shown in the graph), the cos 2 m term in the denominator takes over and causes 2 beam to increase with . 4.5.3 Comparison with the Beam-pointing Error of Coupled-Oscillator Arrays Coupled oscillators represent another phase-shifterless beam-steering technique. Multiple free-running oscillators may be coupled to each other to synchronize their oscillations and introduce the linear phase progression required to electronically steer the beam. One such coupling scheme is nearest-neighbor coupling in a linear array of oscillators, described in [135]. In [112], the authors have derived expressions for the phase error and beam-pointing error of a linear array of N nearest-neighbor-coupled oscillators. Fig. 4.19 shows the theoretical standard deviation, as computed from the expressions derived in [112], of the beam-pointing error for a 4-element, linear, nearest-neighbor- coupled oscillator array with 0 o phase progression and the same tuned load parameters as the VPRO of Section 4.5.1. Dierent coupling gains, denoted by, and capacitance errors are considered. The sensitivity of the coupled oscillator array to process mismatches is expected to improve with an increase in the coupling gain, which is re ected in Fig. 4.19. Fig. 4.19 also shows beam of the 4-element 24GHz VPRO of Section 4.5.1 for 0 o phase progression. The performance of the VPRO is almost 27 times better than the coupled oscillator array with = 0:1. In fact, the beam-pointing error shown for the coupled oscillator array for both values is merely an extrapolation of the linearized equations in [112] to large error levels - in reality, the coupled oscillator array would fundamentally fail to lock for the vast majority of the process-mismatch values considered. 137 Figure 4.19: Theoretical standard deviation of the beam-pointing error of a 4-element, 24 GHz, linear, nearest-neighbor-coupled oscillator array for dierent capacitance errors and coupling strengths. This greater resistance of the VPRO to process mismatches can be loosely explained by the fact that the VPRO is similar to a coupled oscillator array with the coupling gain increased to the limiting value of 1. Each element's signal strength is completely derived from the element coupling to it and there is no signal strength due to self-oscillation. This heightened sensitivity of coupled oscillators to mismatches limits their use to LO distribution in integrated phased arrays, and precludes their use for multiple-phase generation and beam-steering [17], unless calibration or other complex, power-hungry compensation techniques are used [126],[83]. 4.5.4 Amplitude Errors in the Presence of Process Mismatches Although amplitude mismatches do not aect the beam-pointing angle to rst order, they do have an eect on other aspects of the array pattern, such as the sidelobe-rejection ratio. 138 As before, assuming small process mismatches, element amplitude errors may be computed using the rst-order terms of a multi-variate Taylor Series expansion as A i =A + N X j=1 dA i d! j jall ! j 's=! 0 ! j : (4.50) In order to compute the requisite derivatives, a transformation of variables ( i = sin 1 ( V th A i )) is employed. In Section 4.1.1, to determine the nominal amplitude of oscilla- tion, the amplitudes of both sides of (4.3) are equated assuming all elements are identical. If the element capacitances (C i ,i2 1::N) are assumed to deviate from the nominal value of C, resulting in variations in the element center frequencies (! i , i2 1::N), we obtain V th cosec i = 2g m R cos i cosec i1 i1 + sin(2 i1 ) 2 : (4.51) The derivatives of i with respect to ! j , j2 1::N, may be computed from (4.51) and (4.45). The derivatives of A i may then be computed to be dA i d! j j! j =! 0 8j = 2QV th tan F r ij 1F N 1 N(1F ) ! 0 sin(1 + tan 2 ) ; (4.52) where is the value of all i 's in the absence of errors, r ij is the number of elements between i andj moving opposite to the direction of coupling in the ring (shown in Fig. 4.20(a)) and F = gmR cos [2 sin(2)]. If the element capacitance errors are i.i.d N(0; 2 cap ), then the variance of element amplitudes (equal for all nodes) can be computed using (4.52) and (4.50). To verify this theoretical formulation, a 300-iteration Monte-Carlo simulation is run on the 4-element 139 Figure 4.20: (a) Depiction of the function r ij . (b) Theoretical estimate of amplitude standard deviation (normalized to the nominal amplitude) versus Simulink simulations for a 4-element 24GHz VPRO. Element capacitance errors i.i.d N(0, 2 cap ) with cap = 2fF. Theoretical amplitude standard deviation is also shown for N=6 and 8. VPRO of Section 4.5.1. is varied and cap = 2fF (1%). A comparison between the theoretical estimate for the standard deviation of each element's amplitude and the simulation result is shown in Fig. 4.20(b). It is interesting to note that to rst order, when no external phase shift is present, process mismatches bring about no amplitude error. The simulation results show a non-zero standard deviation at 0 o element phase shift due to the contribution of second-order terms. The theoretical standard deviation of the element amplitudes is also shown forN=6 and 8. It is seen that amplitude errors increase with the VPRO size. In practice, phased arrays may employ variable-gain elements in each antenna's signal path to compensate for the amplitude mismatches. 4.5.5 SNR Reduction due to Process Mismatches In wireless communication systems, the SNR and EVM are critical parameters. Hence, it is necessary to evaluate the reduction in SNR in the desired beam-pointing direction due to process mismatches in the VPRO. 140 For simplicity, let us assume that ext =0 o . As was seen in the previous subsection, to rst order, there are no amplitude errors for the normal pointing direction. Therefore, only phase errors need to be considered. The SNR reduction (equal to the array factor reduction in the normal direction due to phase errors) is given by SNR SNR o = N X i=1 e j i 2 N 2 1 N X i=1 N X j=1 ( i j ) 2 2 N 2 ; (4.53) where i ;i 2 1::N are the small element phase errors and SNR o is the SNR in the absence of process mismatches. Substituting for i from (4.46) and assuming that the node capacitances are subject to small, i.i.d errors with an N(0; 2 cap ) distribution, we obtain E SNR SNR o = 1 Q 2 2 cap 12NC 2 (N + 1)(N 1); (4.54) where E SNR SNRo is the mean value of SNR SNRo . To verify this equation, Fig. 4.21 shows the results of Monte-Carlo simulations on VPROs of dierent sizes with cap = 2fF (1%). The VPRO parameters are the same as those described in Section 4.5.1. The mean SNR reduction is shown as a % reduction, i.e., 1E SNR SNRo 100. Since second- order amplitude errors are present in reality and have been neglected in this analysis, the mean SNR reduction from the Monte-Carlo simulations is higher than the theoretically predicted value. If the second-order amplitude errors are articially removed from the simulation results, a perfect match to theory is seen. Nevertheless, the second-order amplitude errors do not disturb the linear dependence of the SNR reduction on N. 141 Figure 4.21: SNR Reduction in the normal pointing direction due to process mismatches in the VPRO. Maximum SNR degradation due to the quantization error introduced by 4- and 5-bit phase-shifters is also shown. As was seen in Chapter 3, practical phase-shifters have a discrete set of phase settings that can be achieved. The resultant quantization error also leads toSNR degradation as quantied in (3.23). Fig. 4.21 depicts the maximum SNR degradation due to the use of 4- and 5-bit phase-shifters (typical in a practical system) as a function of N. For small array sizes, the degradation due to process mismatches in the VPRO is comparable to the degradation due to the quantization error. As N increases, the degradation due to quantization error rises rapidly and becomes the dominating factor. This indicates that process mismatches are not the array-performance bottleneck for phased arrays based on the VPRO. 142 4.5.6 Change in Sidelobe Levels due to Process Mismatches We now examine the eect of process mismatches on the sidelobes of a VPRO-based array. The sidelobe-rejection ratio is a critical parameter in wireless communication as it represents the worst-case spatial-interference cancellation that the array aords. Co- channel interference is often the limiting factor for channel capacity. The Taylor-Series expansion for the array factor at the rst-sidelobe location in the presence of mismatches is given in Chapter 3 in (3.16). The derivatives present in the expansion are given in (3.17) and (3.18). To determine the SLRR deterioration due to process mismatches in the VPRO, ext is assumed to be 0 o for simplicity. As before, to rst order, there are no amplitude errors. Substituting for i from (4.46) in (3.16) and assuming that the node capacitances are subject to small, i.i.d errors with an N(0; 2 cap ) distribution, the variance ofAF err (; lobe ) may be obtained. The variance of theSLRR can then be computed as 2 SLRR = SLRR 2 0 N 4 2 AFerr (; lobe ) . Monte-Carlo simulations are run on VPROs of dierent sizes for dierent cap values. The VPRO parameters are the same as those described in Section 4.5.1. Fig. 4.22(a) compares SLRR as obtained from the Monte-Carlo simulations to theory. Fig. 4.22(b) depicts the theoretical 1- condence interval for the SLRR for dierent VPRO sizes. It is seen that SLRR increases with the array size. This can be attributed to the fact that the element phase errors in the VPRO are correlated. Further, as SLRR increases, a greater discrepancy is seen between the simulations and the rst-order Taylor Series approximation, as expected. 143 Figure 4.22: (a) Standard deviation of the SLRR as obtained from theory and Monte- Carlo simulations of VPROs of dierent sizes ( ext =0 o ). (b) Theoretical 1- condence interval for the SLRR. 4.6 A 4-Channel 24GHz Phased-Array Transceiver in 0.13m CMOS Based on the VPRO-PLL phased-array transceiver architecture, a prototype, 4-channel, 24GHz phased-array transceiver was implemented in IBM's 8RF-DM 0.13m CMOS pro- cess [72], [75]. The process oers 8 metal layers, with 2 thick upper metal layers for RF routing, inductors and transmission lines. For more details on the process, the reader is directed to Appendix A.2. The block diagram of the transceiver and the chip microphoto- graph are shown in Fig. 4.23. The elimination of mixers, power splitters/combiners and phase shifters led to an extremely compact implementation that only occupies 2.35mm 2.15mm of chip area. The transceiver can operate in either transmit or receive mode at a given time (time- division duplexing). O-chip T/R switches, duplexers or circulators are needed if a single array of antennas is to be used for both transmit and receive modes. 144 Figure 4.23: Chip microphotograph and block diagram of the 4-channel 24GHz 0.13m CMOS VPRO-PLL phased-array transceiver. The block diagram of the implemented VPRO is shown in Fig. 4.24(a). The external phase shifter is realized through four additional tuned elements whose varactor tuning voltage is used as an externally-set, analog phase control. This boosts the symmetry of the ring oscillator and prevents end elements from seeing a dierent loading. Each element of the VPRO is implemented as a dierential pair driving a tuned load, is designed to draw 7.5mA of current, and is equipped with a low-noise input buer and an output PA driver, the schematics of which are shown in Fig. 4.24(b). The 108pH inductor of each stage's tuned load is implemented as a short-circuit-terminated CPS in MA, the top metal layer, withW =35m,S=35m and metal strips in M1. AQ of 29 is achieved. Varactors are included in the tuned matching networks to account for frequency mismatches due to process mismatches and modeling errors. However, no tuning was exploited in the 145 Figure 4.24: (a) Block diagram of the VPRO. (b) Circuit diagram of each element along with input and output buers. reported measurement results. The low-noise input buer consumes 2.5mA of current while the PA driver dissipates 13mA. A close-in view of the layout of the VPRO is depicted in Fig. 4.25. The measured frequency-tuning characteristics of the VPRO with respect to the control voltage and the phase control are depicted in Fig. 4.26(a). As is expected, the frequency characteristics of the VPRO are symmetric with respect to the control voltage and the phase control. The measured free-running phase noise, seen in Fig. 4.26(b), lies between -97dBc/Hz and -105dBc/Hz at a 1MHz oset for all angles of steering. 146 Figure 4.25: Close-in view of the VPRO layout. Figure 4.26: (a) Measured frequency tuning characteristics of the VPRO. (b) Measured free-running phase noise of the VPRO for dierent steering angles. The VPRO is locked in a divide-by-128 PLL that employs seven digital frequency di- viders implemented using master-slave latches with inverted-output feedback. The block diagram of the dividers is provided in Fig. 4.27(a), and the circuit realization of the latches is depicted in Fig. 4.27(b). The latches that operate in the rst divider employ large devices and consume 21.6mA of current each to enable 24GHz operation. The cur- rents and device sizes are reduced as one moves down the divider chain, as is indicated in the table provided in Fig. 4.27(b). A standard, tri-state phase-frequency detector and charge pump are also employed. Fig. 4.28 shows the circuit schematic of the charge pump 147 and implemented loop lter. The baseband input and output buers contribute an addi- tional shunt capacitance to the loop lter. The loop-lter component values are chosen to achieve a loop bandwidth of approximately 10MHz. Fig. 4.29 shows the measured spectrum of the locked ring oscillator, with a reference spur rejection of 30dB 18 . Figure 4.27: (a) Digital frequency divider employing master-slave latches with inverted- output feedback. (b) Circuit realization of each latch. Figure 4.28: Circuit diagram of the implemented charge pump and loop lter. Each channel's PA employs a single-stage, pseudo-dierential pair topology. Cascode transistors are employed for reverse isolation and the tail-current transistor is eliminated to allow a higher voltage swing. Lumped spiral inductors and MIM capacitors are used 18 As can be seen in Fig. 4.28, no special attempt was made to make the charge-pump response symmetric. 148 Figure 4.29: Measured spectrum of the locked VPRO. for the input and output matching networks. The PA is biased for class AB operation and draws 82.5mA from 1.5V in small-signal amplication mode. The circuit diagram, layout, small-signal and large-signal measurements of the power amplier are presented in Fig. 4.30. The PA achieves a peak small-signal gain of 11dB and saturated output power in excess of 12.9dBm at 22GHz, with a peak drain eciency of 19%. The LNA of each channel is implemented as a two-stage, inductor-degenerated, common- source design with a total current consumption of 25mA. The input stage is designed for optimal noise performance given a power-match requirement and the inter-stage interfaces are matched to a dierential impedance of 100 . Fig. 4.31 shows the circuit diagram and layout of the LNA. Fig. 4.32 depicts the measurement results of the LNA, which achieves a peak gain in excess of 8dB and a minimum noise gure lower than 6dB. The input-referred 1-dB compression point of the LNA is -7.5dBm at 22.75GHz. In order to test the PLL phase-modulation functionality for transmit mode, a small sinusoidal signal with varying frequency is applied to the PLL baseband input and the 149 Figure 4.30: (a) Circuit diagram of the PA of each channel. (b) Close-in view of the layout of each PA. (c) Measured large signal performance of the PA at 22GHz. (d) Measured PA small signal S-parameters. Figure 4.31: (a) Circuit diagram of the LNA of each channel. (b) Close-in view of the LNA layout. 150 Figure 4.32: (a) Measured gain and noise gure of the LNA. (b) Measured LNA input and output matching. (c) LNA large signal performance at 22.75GHz. spectrum of the VPRO is monitored. The locked frequency of the VPRO is 22.68GHz. As is expected for small-signal, sinusoidal phase modulation, two sidetones appear on either side of the locked frequency at an oset that is equal to the phase-modulation frequency. Fig. 4.33(a) shows the measured VPRO spectrum for a baseband frequency of 7MHz. The normalized strength of these sidetones as a function of the baseband frequency represents the PLL phase-modulation bandwidth, and is shown in Fig. 4.33(b). Fig. 4.34 illustrates the measured receiver gain for a single channel. The LO frequency, i.e., VPRO-PLL lock frequency, is xed at 23.37GHz and the RF input is swept in frequency. A peak gain of 31dB is measured which corresponds to an inferred array gain 151 Figure 4.33: (a) Normalized VPRO spectrum when a 7MHz, small signal is applied at the PLL baseband input. (b) Normalized PLL PM response as a function of the baseband modulation frequency in transmit mode. Figure 4.34: Measured receiver gain for a single channel. The VPRO-PLL lock frequency is xed at 23.37GHz and the RF input is swept in frequency. of 43dB. The high selectivity achieved in both transmit and receive modes is a direct result of the high division ratio of the PLL. To determine the arrayNF of the prototype, the total output noise of the receiver is determined at various baseband osets. This output noise is normalized with the output noise generated by input reference-impedance terminations at all 4 array inputs, which is calculated using the measured single-channel receiver gain (Fig. 4.34). Two dierent PLL references are used for this measurement - an Agilent E4433B signal generator and 152 Figure 4.35: (a) Phase noise of a 182.6MHz reference signal generated by the Agilent E4433B Signal Generator. (b) Single-sideband (SSB) array NF of the prototype using two dierent PLL references - the Agilent E4433B Signal Generator and the UMJ-231-D14 low-noise VCO from Universal Microwave Corporation (UMC). a UMJ-231-D14 low-noise VCO from Universal Microwave Corporation. The phase noise of a 182.6MHz reference signal generated by the E4433B is shown in Fig. 4.35(a). When used as the reference for the prototype, its phase noise becomes the dominant source of noise in the array due to the high PLL division ratio (Fig. 4.35(b)). The UMJ-231-D14 on the other hand exhibits lower phase noise: -159dBc/Hz at a 1MHz oset compared to -141dBc/Hz from the E4433B. When the UMJ-231-D14 is used as the reference, the noise performance of the array is dominated by the VPRO-PLL spatial-power-combining and downconversion scheme, which is simulated to be approximately 16.7dB. Flicker noise is one of the causes for the high NF of the VPRO-PLL block, especially at low oset frequencies. The array NF is dominated by the noise performance of the VPRO-PLL block because of insucient LNA gain - an additional 10dB of gain in the LNA would reduce the array NF to 8dB. Figs. 4.36(a) and 4.36(b) summarize the measured, single-channel, single-tone, linear- ity performance of the receiver for dierent VPRO bias levels. For low VPRO bias levels, 153 Figure 4.36: (a) Measured, single-channel, single-tone, receiver output power versus input power for dierent VPRO bias levels. (b) Measured single-channel, input-referred, 1-dB compression point for dierent VPRO bias levels. the linearity of the receiver is dominated by the VPRO-PLL spatial-power-combining and downconversion scheme. In this regime, as is predicted by the theoretical formulation in Section 4.2, the input-referred 1-dB compression level increases linearly with an increase in VPRO bias current. As the VPRO bias current approaches the design value of 7.5mA, the receiver linearity becomes dominated by the linearity of the baseband buer that fol- lows the VPRO-PLL. Hence, a further increase in VPRO bias current does not improve the input-referred 1-dB compression level. The single-channel input-referred third-order intercept point, measured for two tones that are 50kHz apart, is determined to be -34dBm. To verify the VPRO's performance in the presence of process mismatches, Monte- Carlo simulations are run on the implemented VPRO in SpectreRF using the mismatch data of the process for ext =0 o . A characterization of the varactors used in the design reveals that the device capacitances are subject to a normal distribution with cap =0.5% due to across-chip mismatch (Fig. 4.37(a)). Fig. 4.37(b) depicts the probability distri- bution function (PDF) of the beam-pointing error from theory ((4.49)) and Monte-Carlo 154 Figure 4.37: (a) Probability distribution function (PDF) of the capacitance of a 100fF varactor through Monte Carlo simulations using mismatch data from IBM's 8RF-DM process. (b) PDF of the beam-pointing error from theory and Monte Carlo simulations of the implemented VPRO. simulations. A good agreement is seen. It should be noted that N = 8 is used in the theoretical expressions to more closely represent the system as the external phase shifter is implemented using 4 additional identical tuned stages. The simulated 1 condence interval of the SLRR is 11.6-11.9dB, while the theoretical interval is 10.8-11.7dB 19 . To measure the accuracy of on-chip amplitudes and relative phases, and eventually the array patterns, on-wafer RF probing is performed on the prototype in transmit mode. Due to the chip layout, only two channels, on opposite sides of the chip, could be probed at a time. To determine the phase relationship between the dierent channels, the channels are probed pairwise and a 180 o -hybrid is used to subtract one output from another. Variable delay elements are included prior to the hybrid in the two paths, and the delay element of one path is varied until a minimum power in the combined output is seen. The 19 It should be noted that in the Monte Carlo simulations, the VPRO outputs are monitored after the outputs buers, which have an amplitude-limiting eect. This does not aect the match between theory and simulations because the theoretical formulations for beam-pointing error and SLRR in the case of ext=0 o ignore amplitude errors. Furthermore, amplitude errors are absent in the VPRO to rst order when ext=0 o . 155 Figure 4.38: (a) Measurement setup for the on-wafer amplitude and phase characteriza- tion. (b) Calibration accuracy for the on-wafer amplitude and phase characterization. Ideally, a phase dierence of 180 o and amplitude dierence of 0dB should be seen be- tween the two paths. (c) Simulated nominal VPRO outputs for 0 o inter-element phase shift (normal or broadside transmission) and comparison with measured results. Figure 4.39: Measured and simulated nominal array patterns for broadside transmission and two other steering angles. extent by which the delay element needs to be varied to achieve the minimum gives the phase dierence between the two channels. It is necessary to calibrate the two paths to ensure equal electrical length prior to measurement. The delay elements are used during the calibration step to compensate for cable mismatches due to bends, hybrid mismatches, etc. To determine the amplitude of each channel, the channels are probed one at a time. Table 4.1: Comparison of measured pattern for normal transmission to theory and 8RF- DM Monte Carlo simulations. Measured 8RF-DM Theory Theory Monte Carlo cap =0.5% cap =1% Beam-pointing error -2.1 o 0.18 o 0.24 o 0.48 o SLRR (dB) 12, 12.5 11.6-11.9 10.8-11.7 10.4-12.1 156 Fig. 4.38(a) depicts the measurement setup, while Fig. 4.38(b) shows the calibration of the two paths in terms of both amplitude and phase. In the vicinity of the operating frequency, the phase and amplitude mismatches between the two paths are within5 o and 0:3 dB respectively. These represent the tolerances of the amplitude and phase measurements. Fig. 4.38(c) displays the simulated nominal outputs of the four channels for 0 o inter-element phase shift. The small amplitude and phase errors in simulation are due to the layout mismatch between elements 2 and 3 of the VPRO, due to the bending of the interconnect between them (Fig.4.25). Fig. 4.38(c) also compares the simulated nominal amplitude and phase distribution to the measured results. Fig. 4.39 compares the array patterns (in logarithmic scale and cartesian coordinates) extrapolated from the measured amplitudes and phases to the simulated nominal patterns for normal transmission (depicted in the center) and two other steering angles. The measured array performance lies within the limits predicted by the theory and simulations in Fig. 4.37 (Table 4.1) within the accuracy of the measurement setup 20 . The array performance of the chip is also tested in a package that is fabricated in- house (Fig. 4.40(a)). The prototype is mounted onto a brass substrate using silver epoxy and the RF inputs, outputs and DC connections are wirebonded to a high-frequency Duroid PC board that is also mounted on the substrate. The substrate and the traces on the PC board are gold plated to facilitate wirebonding. The length of the RF wirebonds is minimized to prevent deterioration of input/output matching. The array performance in transmit mode is measured using the setup described in Fig. 4.40(b). The propagation 20 The 5 o of measurement phase mismatch across the channels contributes 0.7 o of additional pointing error. 157 Figure 4.40: (a) Test mm-wave package for 4-channel pattern measurement. (b) Mea- surement setup for 4-channel pattern measurement. delay of the electromagnetic wave in free space is emulated using variable delay elements, allowing the array performance to be assessed independent of antenna properties. The measured 4-channel transmit patterns of the packaged 24GHz prototype are pre- sented in Fig. 4.41 in linear scale and polar coordinates. It should be emphasized that no calibration steps were used to compensate for wirebond and other packaging mismatches. Hence, the patterns include their eect. The authors of [63] report 6-7 o of phase mis- match between phased-array channels due to packaging alone in the Ku-band. The phase mismatch is expected to be even higher in our package, due to the higher frequency of operation and the limitations of our in-house packaging capability. The measured 4- channel patterns do show performance deterioration due to the packaging limitations but still verify beam-steering functionality. For reference, an inter-element phase variation of phase =10 o in the mm-wave package (external to the VPRO) leads to beam =1.4 o for a 158 Figure 4.41: Array patterns for the packaged prototype 24GHz CMOS 4-channel VPRO- PLL transceiver in transmit mode. 4-channel phased array set to the normal direction. SLRR may be determined to be 6 resulting in a 1- SLRR condence interval of 8.12dB - 12.9dB. Assuming a relative di- electric constant of 1 for a 50 wirebond transition, 10 o corresponds to 0.35mm variation in wirebond length at 24GHz. Table 4.2 summarizes the performance of the 24GHz, 4-channel, phased-array transceiver, while Table 4.3 compares the measured performance to prior, silicon-based, phased-array implementations at 24GHz [55],[91]. Comparable performance is achieved at a lower chip area and power consumption. This validates the potential of the VPRO-PLL architecture in the quest for low-cost, low-power, integrated phased arrays. It should be mentioned that the prior implementations support arbitrary amplitudes and phases in each chan- nel, while the 24GHz, 4-channel, phased-array transceiver described here provides only linear phase progressions. However, techniques to extend the VPRO-PLL architecture to support arbitrary amplitudes and phases are discussed in Section 4.8.3. 159 Table 4.2: Performance summary of the 4-channel, 24GHz 0.13m CMOS phased-array transceiver. Implementation Technology 130nm CMOS Die Area 1.25mm 2.35mm Supply Voltage 1.5V Transmitter Performance Maximum PA Output Power > 12.9dBm (Limited by measurement equipment) 4-element EIRP > 24.9dBm Peak PA Drain Eciency > 19% IF Double-Sided -3dB Bandwidth 13MHz Receiver Performance Receiver Gain 31dB Total Array Gain 43dB Array Noise Figure (Limited by low LNA gain) 15dB LNA Gain 8dB Input-referred 1-dB Compression Point -42dBm IF Double-Sided -3dB Bandwidth 10MHz LO Path Performance VPRO Free-running Phase Noise @1MHz -97 to -105dBc/Hz RF Path Current Consumption PAs 482.5mA=330mA LNAs 428mA=112mA VPRO-PLL Current Consumption VPRO Elements 87.5mA=60mA VPRO Input Buers 82.5mA=20mA VPRO Output Buers 814mA=112mA Divider Chain 75mA Charge Pump 15.5mA Baseband Buers Current Consumption Baseband Output Buer 30mA Baseband Input Buer 10mA Biasing Circuits Current Consumption 10mA Total Power Consumption (TX Mode) 653mA1.5V=0.98W Total Power Consumption (RX Mode) 346.5mA1.5V=0.52W 160 Table 4.3: Comparison with prior silicon-based phased-array implementations at 24GHz. [55] [91] This work Frequency 24GHz 24GHz 24GHz Functionality RX TX TX+RX Number of Channels 8 4 4 Technology 0.18m SiGe 0.18m SiGe a 0.13m CMOS EIRP N/A 26dBm >24.9dBm PA Peak PAE N/A 6.5% > 12.3% Power Consumption 0.91W 1.97W RX: 0.52W, TX:0.98W Area 11.6mm 2 14.28mm 2 5.1mm 2 a The power ampliers were implemented using CMOS transistors only. 4.7 An UWB 4-Channel 24-27GHz VPRO-PLL Phased- Array Transmitter in 0.13m CMOS The prototype described in Section 4.6 suers from two drawbacks. The high division ratio of the PLL limits the modulation and demodulation bandwidths. Secondly, as was described in Section 4.1.1, the achievable phase shifts across an RLC load are limited by the loop-gain requirement of the VPRO. In practice, the achievable phase-shift range is typically -60 o to +60 o . While dierential phase inversion does enhance the beamsteering coverage that can be achieved with this phase-shift range, the resultant coverage is not complete. To overcome these drawbacks, a second prototype was implemented in IBM's 8RF-LM 0.13m CMOS process [74]. For more details on the process, the reader is directed to Appendix A.2. The prototype is a 4-channel phased-array transmitter that is designed to operate in the 24-27GHz frequency range. The chip microphotograph and block diagram are depicted in Fig. 4.42. The chip occupies 2.7mm 1.8mm of die area and draws approximately 750mA from a 1.5V supply when all channels are enabled. 161 Figure 4.42: Chip microphotograph and block diagram of an UWB 4-channel 24-27GHz VPRO-PLL phased-array transmitter in 0.13m CMOS. The VPRO is designed to operate at half of the desired operating range, and frequency doublers, in the form of squarers, are interposed between the VPRO nodes and PAs of each channel. In addition to doubling the frequency, the squarers double the phase dierence between successive VPRO nodes. In such an architecture, an inter-element phase-shift range of only -45 o to +45 o needs to be achieved in the VPRO. Frequency doubling enhances this range to -90 o to +90 o . In conjunction with dierential sign inver- sion, implemented in the PAs in this prototype, this results in complete beam-steering coverage. In order to enhance the transmitter modulation bandwidth, a dual-PLL architecture is employed. A 12GHz on-chip reference oscillator is implemented that is locked to a stable, o-chip, low-frequency reference in a divide-by-128 PLL. A quadrature all-pass lter (QAF) is employed and the resultant quadrature reference-oscillator signals are mixed with the quadrature baseband inputs to generate the modulated signal. The VPRO is 162 Figure 4.43: Normalized Fourier Transform of a linear FM chirp withf 0 =24GHz,T =10ns and T =3GHz. then locked to this modulated signal in a high-speed dividerless PLL. Since no dividers are present in this primary PLL, high-speed phase/frequency modulation can be achieved. This prototype is designed to target the 22-29GHz vehicular-radar application space. A popular waveform for radar is the linear frequency-modulated (FM) chirp, which is nothing but a sinusoid with a linearly-increasing instantaneous frequency. The functional representation is S chirp (t) = sin(2f 0 t +t 2 ). If T is duration of the chirp, the in- stantaneous frequency of the chirp increases from f 0 tof 0 +T . The normalized Fourier Transform of a sample chirp withf 0 =24GHz,T =10ns andT =3GHz is given in Fig. 4.43. The bandwidth is strongly correlated to the chirp range (f 0 to f 0 +T ). For the UWB VPRO-PLL transmitter prototype being described in this section, the tracking range of the VPRO-PLL governs the chirp range that can be supported. The PLL loop bandwidth governs the chirp rate T . For radar applications, the chirp range T is typically wide for high range resolution. The chirp rate is typically slow with T usually of the order of microseconds. Therefore, for the vehicular-radar application space, a wide tracking 163 Figure 4.44: (a) PA circuit diagram. (b) Measured small-signal parameters for 0/180 o paths. (c) 1-bit sign inversion from small-signal S-parameter measurements. (d) Measured large-signal performance. range is important. On the other hand, if the prototype is to be used for high-data-rate communication in the 24GHz ISM band using a modulation scheme such as high-speed phase-shift-keying (PSK), the PLL loop bandwidth becomes signicant. The circuit diagram of the PA of each channel is presented in Fig. 4.44(a). To achieve 1-bit sign inversion, two dierential pairs with inverted inputs are used. Each pair may be enabled through its tail transistor, and the drains of both are tied to each other. A cascode pair is used to enhance reverse isolation and both ports are matched to a dierential impedance of 100 through lumped inductors. Figs. 4.44(b)-(d) present the measured PA performance. Wideband performance between 24GHz and 27GHz is seen for small- and large-signal drive and 1-bit sign inversion is achieved. Each PA draws 86.4mA 164 from a 1.5V supply during linear operation and achieves a saturated output power in excess of 12.1dBm at 26GHz, corresponding to a peak drain eciency greater than 13%. The frequency doubler is implemented as a squarer and is designed as a pseudo- dierential, current-commutating, doubly-balanced mixer. The output of the squarer is matched to a dierential reference impedance of 100 to drive the PA. Each squarer consumes 34mA from Vdd. The circuit diagram and simulated performance of the squarer are summarized in Fig. 4.45. Figure 4.45: (a) Squarer circuit diagram. (b) Simulated output power at 24GHz for a 12GHz input with varying large-signal amplitude. (c) Simulated output power versus input frequency for a xed dierential input peak amplitude of 1.6V. Fig. 4.46 depicts the circuit diagram of the VPRO. For symmetry purposes, as is the case with the previous prototype, the extra phase shifter is implemented as 4 additional tuned stages. Each stage is equipped with 2-bit, binary-weighted switched capacitors so that the top- and bottom-four elements may be detuned to accomplish phase shifting and hence beam steering. This, coupled with the 1-bit sign-inversion capability incorporated in the PAs, allows the 4-channel array to achieve 3 bits of beam-steering resolution. Each tuned element is also equipped with varactors for PLL frequency control, with the size of the varactors chosen to maximize the Q and the Cmax C min tuning ratio [19]. Although the 165 Figure 4.46: Circuit diagram of the wideband VPRO. VPRO needs 1.5GHz of tuning range for 24-27GHz system operation, the bandwidth is increased beyond 2GHz to provide margin and ensure a linear tuning characteristic in the desired range. This amount of tuning range is signicant, given that a large portion of the capacitance budget is used toward phase shifting. Each VPRO element is connected to an output buer that drives the squarer of each channel. The current consumption of each element is 6.5mA, while that of each buer is 13mA. The simulated VPRO tuning range extends from approximately 11.2 to 13.8GHz for all beam-steering settings, while the measured range extends from 10.3GHz to 12.9GHz. This corresponds to a center- frequency error of 0.9GHz or 7.2%. While the VPRO has a wide tuning range to support wideband chirp signals, the blocks that follow the VPRO, such as the output buers, the squarers and the PAs, must have sucient bandwidth as well. The design of UWB RF blocks is challenging as a large number of passive elements is usually needed to match ports to a desired impedance and achieve a wideband transfer function. An alternative is to design narrowband blocks with 166 lowQ, as the bandwidth of an RLC tuned load is inversely proportional to itsQ. However, this comes with the penalty of low gain, or, alternatively, a larger current consumption to main the same gain and output-power levels. In this work, a new UWB design paradigm is proposed that takes advantage of the known shape and characteristics of the waveform(s) being used. The UWB VPRO-PLL architecture generates UWB signals that are phase- or frequency-modulated (such as the linear FM chirp for radar). The control voltage of the VPRO is a measure of the signal's instantaneous frequency. Therefore, the tuned blocks that follow the VPRO, such as the output buers, squarers and PAs, may be designed to be high-Q, tunable-narrowband systems, whose center frequency is also controlled by the control voltage. In other words, the transfer function of the RF chain tracks the instantaneous frequency of the signal, achieving wideband performance while being instantaneously narrowband in nature. Fig. 4.46 shows the frequency control of the buer, V tune op , achieved through varac- tors, being connected to the control voltage of the VPRO. Fig. 4.47 depicts the result of a SpectreRF simulation of the VPRO and its buers when the control voltage is linearly ramped with time to produce a chirp. Fig. 4.47(a) shows that a linear ramp in the control voltage results in a linearly-increasing instantaneous frequency. Figs. 4.47(b)-(d) show how the tuning of the buers along with the VPRO leads to tracking of amplitudes and phases between the buer outputs and VPRO node outputs, thus minimizing the distortion between the two in the frequency response. When the buers are not tracked, signicant distortion is introduced between VPRO node outputs and the buer outputs. As the simulations and measurements presented earlier indicate, the squarers and PAs are capable of supporting the desired bandwidth without a signicant gain or power 167 Figure 4.47: SpectreRF simulation of the VPRO and its output buers when the control voltage is ramped up linearly with time to generate a chirp. The (a) instantaneous frequency, (b) instantaneous phase dierence between the VPRO node outputs and the buer outputs, (c) instantaneous amplitude of the VPRO node outputs and buer outputs and (d) frequency response of the VPRO node outputs and buer outputs are shown for two cases - the frequency control of the buers is connected to that of the VPRO/held constant. penalty. Therefore, they are not tuned using the PLL control voltage. If a larger band- width is desired, the squarers and PAs may also be designed as tunable-narrowband systems. This design paradigm is similar to the technique described in [103], which reports a dynamically-tuned LNA for Multi-Band Orthogonal Frequency-Division Multiplexing (MB-OFDM) UWB receivers. In order to experimentally validate the beam-steering capability of the VPRO, nar- rowband array patterns are measured at 24.75GHz with two elements active through RF 168 Figure 4.48: (a) Narrowband array patterns at 24.75GHz measured through RF probing for two active channels. (b) Measured spectra of the transmitted UWB FM beam along the expected peak and null directions when the beam is steered to -42 o . Two elements are active and two dierent signal bandwidths are considered. probing. The propagation of the transmitted beam in free space is emulated using variable delay elements in each probed path. The two paths are then combined using a power combiner and the resultant signal is monitored on a spectrum analyzer. Fig. 4.48(a) shows the results of these measurements for two dierent beam-steering settings, assum- ing half-wavelength antenna separation. To assess UWB beam-steering functionality, wideband FM waveforms of varying bandwidths are generated by direct FM modulation of the VPRO control voltage with a 5MHz sinusoid of varying amplitude. Once again, two channels are enabled and the transmitted beam in dierent directions is measured. Fig. 4.48(b) shows the measured normalized spectrum when the beam is steered to -42 o 169 Figure 4.49: (a) Circuit diagram of the on-chip reference oscillator. (b) Measured phase noise of the reference oscillator for various bias currents. (corresponding to the second narrowband pattern in Fig. 4.48(a)) for two dierent signal bandwidths along the expected peak and null directions. Indeed, the power spectral den- sity (PSD) in the null direction is suppressed by approximately 10 dB when compared to the peak direction. Fig. 4.49(a) depicts the circuit diagram of the implemented on-chip reference os- cillator. A cross-coupled LC-oscillator topology is utilized. The cross-coupled cell is implemented using pMOS transistors only, due to their reduced icker-noise corner when compared with the nMOS transistors available in the process. The bias current of the oscillator is set by digitally-controllable tail-current resistors. A tail-current transistor is avoided due to icker-noise considerations. The bias current may be varied from 4.6mA to 9.8mA. The measured phase noise of the reference oscillator for dierent bias-current settings is depicted in Fig. 4.49(b). The measured phase noise ranges from -96 to - 102dBc/Hz at a 600kHz oset. The reference oscillator is locked in a divide-by-128, digital PLL that utilizes static frequency dividers, a standard, tri-state, phase-frequency detector and a charge pump. 170 Figure 4.50: Measured spectrum of the on-chip reference oscillator when locked to an o-chip 93.75MHz reference. The resultant PLL lock frequency is 12GHz. The phase-frequency detector and charge pump are identical to those described in Section 4.6. The seven static dividers are similar to the dividers described in Section 4.6 as well, but only consume a total of 41.6mA due to the elimination of the power-hungry 24GHz divider. Fig. 4.50 depicts the measured spectrum of the on-chip reference oscillator when locked to an o-chip 93.75MHz reference. The resultant PLL lock frequency is 12GHz. Figure 4.51: (a) Circuit diagram of the quadrature all-pass lter (QAF). (b) Circuit diagram of the I/Q baseband mixer. 171 Figure 4.52: Circuit diagram of the analog mixer that serves as the phase detector for the primary dividerless PLL. Fig. 4.51(a) depicts the circuit diagram of the quadrature all-pass lter (QAF) that generates quadrature outputs from the reference oscillator's signal. A single-stage RC- CR lter driven by a cascode-dierential-pair amplier is employed. The dierential-pair amplier consumes 11mA from the supply. Tuning varactors are used to compensate for frequency mismatches that result from modeling errors. Fig. 4.51(b) depicts the circuit diagram of the I/Q baseband mixer. The quadrature signals generated by the QAF are mixed with quadrature baseband inputs in a pair of doubly-balanced, current-commutating mixers. The outputs of the I and Q mixers are tied together to combine their signals in the current domain to generate the modulated reference signal for the VPRO-PLL. Once again, tuning varactors are incorporated in the output tuned load to compensate for frequency mismatches. The I/Q baseband mixer consumes 4mA from the supply. 172 Table 4.4: Performance summary of the UWB 4-channel, 24-27GHz 0.13m CMOS phased-array transmitter. Implementation Technology 130nm CMOS Die Area 1.8mm 2.7mm Transmitter Performance Maximum PA Output Power > 12.1dBm (Limited by measurement equipment) 4-element EIRP > 24.1dBm Peak PA Drain Eciency > 13% Array Performance Beamsteering Resolution 3 bits 12GHz Reference Path Performance VPRO Free-running Phase Noise @600kHz -102dBc/Hz RF Path Current Consumption Power Ampliers 486.4mA=345.6mA Squarers 434mA=136mA VPRO-PLL Current Consumption VPRO Elements 86.5mA=52mA VPRO Output Buers 813mA=104mA Primary PLL Mixer 19.2mA Reference Path Current Consumption 12GHz Reference Oscillator 9.8mA I/Q Baseband Mixer 4mA Quadrature All-Pass Filter 11mA Secondary PLL Dividers 41.6mA Secondary PLL Charge Pump 13.5mA Biasing Circuits 6mA Total Power Consumption 743mA1.5V=1.11W Fig. 4.52 shows the circuit diagram of the analog mixer that serves as the phase detector for the primary dividerless PLL. The rst stage is a doubly-balanced current- commutating mixer that mixes a VPRO output with the modulated reference signal that is generated by the I/Q baseband mixer. The result is then amplied through two stages before it is fed back to the VPRO control voltage. The nal stage's load resistance must not be too large as the resistance, in conjunction with the capacitance seen looking into the VPRO control voltage, sets the bandwidth of the eective low-pass loop lter. This 173 bandwidth must be large to enable a large PLL loop bandwidth to support high-speed modulation. From simulations, a resistance of 30 results in a PLL loop bandwidth of 250MHz, which is sucient to cover the 24GHz ISM band. In addition, the output of the nal stage must be able to swing over the range of voltages that covers the entire tuning range of the VPRO. This sets the current consumption of the nal stage at 17.7mA. Table 4.4 summarizes the measured performance of the prototype. 4.8 Topics for Future Research There are several lines of investigation still open with respect to the VPRO-PLL archi- tecture for integrated phased arrays. 4.8.1 Multiple Oscillation Modes of the VPRO As was discussed in Section 4.1.1, the VPRO has multiple possible modes of oscillation that arise from the fact that the total phase shift in the ring can be any integral multiple of 2. The multi-mode problem becomes progressively more severe as the number of elements in the ring is increased. As a result, techniques that force the desired mode of oscillation must be devised. The mode of oscillation that is achieved in steady state depends on the initial condi- tion of the VPRO. In the simulations depicted in Section 4.1.1, the modes are achieved through appropriate assignment of initial conditions to the various VPRO node voltages. Therefore, it may be possible to force the desired mode of oscillation in the VPRO-PLL phased-array transceiver by designing start-up circuitry that enforces the appropriate initial conditions for the desired mode. 174 Figure 4.53: (a) Block diagram of the Variable Phase Array Oscillator (VPAO). (b) Simulink model of each VPAO element. (c) 3-D beam patterns generated from a 24 GHz 3x3 VPAO. 4.8.2 Extension to 2D Arrays The VPRO can be extended to form a Variable-Phase Array Oscillator (VPAO) that produces linear phase progressions in two dimensions for 2-D phased arrays, as shown in Fig. 4.53(a). The number of phase shifters required is M +N, where M is the number of rows and N is the number of columns, as opposed to MN in an RF-phase-shifting implementation of a 2-D array. Each unit cell in the gure consists of a nonlinear gain cell that adds its two inputs and lters the output through an LC resonant tank. In the steady state of the fundamental mode, the phase of the (i;j) th element's output is(i 1) ext M (j 1) ext N , and the phase shift across the LC tank (i.e., the phase shift between the sum of the inputs and the output) is 2N 2M . This phase shift determines 175 the oscillation frequency. Note that rst element is assumed to be the reference with a phase of 0. Fig. 4.53(b) depicts a Simulink model for each unit cell and Fig. 4.53(c) shows the 3-D beam patterns produced from the Simulink model of the VPAO with M = N = 3. The nonlinear gain cell of each element consists of an ideal adder followed by a saturation block with g m =10mS and V th =0.5V. The LC tank has component values of L=200pH, R=450 andC=195fF for a resonance frequency of approximately 24GHz and a Q of 14. The external phase shifters are replaced by ideal time-delay cells, and the beam patterns are computed assuming an antenna array with 2 spacing along both dimensions. The patterns correspond to two dierent settings - all elements in phase (all time-delay blocks have no delay) and a phase progression of approximately 30 o in each dimension. Similar to the VPRO-PLL phased-array transceiver architecture, a VPAO-PLL archi- tecture for 2-D phased-array transceivers may be envisioned. 4.8.3 Support for Arbitrary Element Phases The VPRO produces a linear phase progression for beam-steering. However, support for arbitrary element phases, as opposed to a linear progression, is often useful in phased arrays. Such a feature enables the calibration and compensation of phase mismatches introduced by the process and/or packaging across the phased-array channels. In addition, in environments characterized by the presence of multipath, support for arbitrary element phases enables the maximization of the SNR of the communication link, as the formation of a physical beam at the transmitter and/or receiver is no longer optimal. Therefore, 176 Figure 4.54: The VPRO-PLL combination used in a conventional RF-phase-shifting ar- chitecture for power combining and downconversion. incorporating support for arbitrary element phases in the VPRO is an important topic for future investigation. The phase shift across each element of the VPRO is the same as the RLC loads of the elements are identical. By controlling the element capacitances separately, it may be possibly to generate non-identical phase shifts across the elements. However, further investigation is required to determine the extent of arbitrariness that can be introduced in the element phase distribution through such a technique. In addition, the multi- mode phenomenon is likely further complicated by such a technique and would require additional investigation. Alternately, the VPRO-PLL combination can be used in a more conventional RF- phase-shifting architecture for power combining and downconversion with the external phase shifter eliminated and independent phase shifters in each channel (Fig. 4.54). 177 Arbitrary gains are also desirable for each channel, especially to control the locations of the spatial nulls. This can be incorporated into the VPRO-PLL architecture through the implementation of variable gain in the front-end LNAs/PAs. 4.8.4 Incorporation of I/Q Functionality As was discussed earlier in this chapter, the VPRO-PLL phased-array receiver supports amplitude-, phase- and frequency-modulation techniques, while the VPRO-PLL trans- mitter supports only phase- and frequency-modulation schemes. The incorporation of amplitude-modulation capability in the transmitter can be achieved in a manner simi- lar to GSM polar transmitters through the incorporation of RF variable-gain ampiers (VGAs) in each channel after the VPRO to provide envelope information to the sig- nal. It should be noted that such an implementation at millimeter-wave frequencies is challenging and deserves further research. In addition, the incorporation of I/Q capability into the architecture for both transmit and receive modes is an open problem. The straightforward approach involves the use of two VPRO-PLL blocks, one for the I path and one for the Q path. However, such an approach is potentially power- and area-inecient. 4.9 Summary In this chapter, a Variable-Phase Ring Oscillator and Phase-Locked Loop (VPRO-PLL) architecture for integrated phased-array transceivers was presented. The architecture ex- ploits the nonlinear injection-pulling properties of a VPRO locked in a PLL to realize com- plete phased-array-transceiver functionality while eliminating conventional phased-array 178 building blocks, such as mixers, power splitters/combiners and phase shifters. As a result, the architecture lends itself to compact and power-ecient integrated implementations. The architecture is suitable for phase-, frequency- and amplitude-modulation schemes in both transmit and receive modes. Experimental results from two fully-integrated 0.13m CMOS phased-array implementations, operating in the vicinity of 24GHz, were presented. These prototypes perform comparably with prior implementations in the same frequency range while consuming a fraction of the area and power, and validate the potential of integrated nonlinear multi-functional circuits at millimeter-wave frequencies. 179 Chapter 5 An RF-Multibeam Spatio-Temporal RAKE Transceiver Architecture for Radar Multipath interference is an important factor that limits the performance of wireless- communication transceivers and radars alike. In wireless-communication transceivers, multipath interference results in fading and Inter-Symbol Interference (ISI), which de- grade the Bit-Error Rate (BER). In radar, multipath interference can result in false alarms or \ghost" artifacts. Phased arrays combat multipath interference by using multi- ple antennas to form a directional beam to reject the undesired multipaths arriving from other directions. This chapter describes a multi-antenna radar architecture that harnesses multipath re ections to gather more information about the scene being imaged. The chapter begins with an overview of communication systems that operate in multipath-rich environments. For such scenarios, multi-antenna techniques that com- bat the multipath-rich nature of the environment to enhance the data rate are known and will be reviewed. This is followed by a discussion of radar techniques that can har- ness multipath scattering to obtain more information about the scene. An RF-multibeam 180 spatio-temporal RAKE transceiver architecture is then presented that is capable of col- lecting not only Line-of-Sight (LoS) re ection information but multipath information as well for radar. Two system-level design considerations in this architecture are the design of appropriate orthogonal codes that are central to the operation of the architecture, and the partitioning of the baseband signal processing between the analog and digital domains. Code design is a topic that is beyond the scope of this thesis. Hence, it is introduced as a topic for future research. The analysis of the partitioning of baseband signal processing reveals that the power dissipation of a digital-baseband approach is dominated by the high-resolution, high-speed ADC that is required. The prohibitive power consumption of such an ADC renders the analog-baseband approach preferable. Finally, results from a prototype, implemented in a 90nm CMOS process and operating in the 24-26GHz frequency range for automotive-radar applications, are presented. 5.1 Wireless Communication in Multipath Fading Channels Many wireless-communication environments, such as typical indoor environments, are characterized by the presence of numerous multipath scatterers. As a result, the signal that is sent by the transmitter appears at the receiver along with multiple duplicate copies or \echos" that have dierent delays, amplitudes or even shapes. If the number of scatterers is large, the superposition of an LoS signal and all such multipath echos can result in a signal amplitude that varies quite rapidly with the distance between the transmitter and the receiver. This phenomenon is termed as fading. 181 The presence of multipath scatterers can also result in ISI - a delayed echo of a transmitted symbol interferes with the symbol that follows it, degrading the BER. ISI can be mitigated by introducing guard intervals between symbols at the expense of lower data rate or through the implementation of equalizers. The usage of multiple antennas at the receiver and/or the transmitter can also mitigate the adverse eects of multipath interference. This can be accomplished in several ways that are discussed below. In general, such systems are called Multiple-Input, Multiple- Output (MIMO) systems. 5.1.1 Linear Beamforming Figure 5.1: Linear beamforming. Linear beamforming (Fig. 5.1) involves the usage of linear processing at the trans- mitter and/or the receiver to typically enhance the Signal-to-Noise Ratio (SNR) of the wireless link. The signal transmitted/received by each antenna is weighted with an appro- priate complex gain so that the SNR of the combined signal at the receiver is maximized. Beamforming on the transmitter side may require knowledge of the channel characteristics and might require feedback from the receiver to the transmitter to achieve maximization of SNR. However, schemes that work without channel knowledge are also available. In 182 the absence of multipath re ections, beamforming reduces to the formation of directional beams at the transmitter and the receiver that point towards each other 1 . In the presence of multipath re ections, the denition of an array pattern has little signicance. When employed at the transmitter, linear beamforming is sometimes called precoding, and when employed at the receiver, it is called decoding in the wireless communications community [108]. The improvement in SNR that is achieved is commonly termed as array gain in the antennas and propagation community. 5.1.2 Space-Time Coding Figure 5.2: Space-time coding. In the event that the transmitter does not have access to Channel State Information (CSI), space-time codes enable MIMO systems to extract spatial-diversity gain through appropriate construction of the codes transmitted from each antenna in space and time [4],[120]. Diversity refers to the establishment of multiple independent links in time, frequency or, in this case, space over which the same information is sent in a redundant fashion. Diversity is a critical resource that allows wireless links to function reliably in 1 The transmitter and receiver are then called phased arrays in the antennas and propagation community. 183 the face of multipath fading. Space-time codes essentially code the signal redundantly across space (i.e., across the dierent antennas) and time (Fig. 5.2). This redundancy allows the receiver, which may be either a single-antenna or multi-antenna system, to reconstruct the data stream with far less amplitude variability if the N T N R links between the transmitting and receiving antennas fade independently, where N T and N R are the number of transmitting and receiving antennas, respectively. 5.1.3 Spatial Multiplexing Figure 5.3: Spatial multiplexing. MIMO systems can also increase the channel capacity linearly by a factor equal to min(N T ;N R ) for no additional transmitted-power and bandwidth expenditure. This is accomplished through Spatial Multiplexing (Fig. 5.3), where independent data streams are transmitted from the dierent transmitter antennas [97],[45]. In the presence of rich scattering, the receiver array can separate the data streams sent by the dierent transmitter elements, yielding a linear increase in capacity. This gain is referred to as spatial-multiplexing gain. 184 5.2 Multipath in Radar Multipath re ections in radar can result in false alarms or \ghost" images, as signals return with a misleading time of ight. However, if it is possible to isolate the multi- path re ections from the primary LoS re ections, they can be harnessed to glean more information about the scene being imaged. The primary reason for this is the fact that multipath re ections allow radar transceivers to probe a desired object from directions that are not visible from the LoS. In [23], the authors develop a method for imaging an object when extra point-like scatterers are present in the foreground. The natures and positions of these scatterers are determined from the initial re ections that are received from them. Once their natures and positions are known, re ections o these scatterers impinge on the desired object from directions not visible from the LoS, thus yielding more information about the object of interest (Fig. 5.4). Figure 5.4: The use of point-like foreground scatterers for more comprehensive imaging of the desired object. A similar idea is used for the ultrasonic imaging of tissues of the human body. To facilitate inverse-scattering image reconstruction, transmission data is required for a full 360-degree rotation of the body. In order to mitigate this restriction, a re ector plate 185 is placed behind the body, and transmission and re ection data are measured for a half rotation [65]. The presence of the re ector plate behind the body essentially allows the backside to become accessible. As is the case in wireless-communication systems, multiple antennas can be used to handle, and even harness, the presence of multipath in radar. Such systems fall under the broad class of MIMO radar, a burgeoning research area that attempts to employ multiple- antenna techniques that are inspired by MIMO research for communication systems to radar [37],[42]. Below is a brief overview of some classes of MIMO-radar systems. 5.2.1 Phased-Array Radar As was discussed in Chapter 3, phased-array radars have been extremely popular, partic- ularly in military applications, since World War II. Phased-array radars typically employ a linear phase progression across a linear array of antennas to form a directional beam that focusses on the desired target, enabling the rejection of interferences and multipath re ections from undesired directions. Virtually all modern warships and ghter planes feature phased-array radars. 5.2.2 Spatial-Diversity Radar Fig. 5.5 depicts a Spatial-Diversity Radar [42], where multiple transmitters and receivers are employed to smoothen out target Radar-Cross-Section (RCS) fading or scintillations. The transmitters and receivers are well-separated so that they experience an angular spread (i.e., variability in target RCS with aspect ratio). The elements of the transmitting array emit orthogonal waveforms. Each receiver element employs a bank of matched 186 Figure 5.5: Spatial diversity radar. lters to isolate the waveforms from each transmitter, and the outputs are collected and processed in a non-coherent fashion. Essentially, N T N R independent transmitter- receiver links are established that each see an uncorrelated target RCS, where N T and N R are the number of transmitters and receivers respectively. The outputs may then be processed to generate a received signal that exhibits far-less fading. 5.3 The RF-Multibeam Spatio-Temporal RAKE Transceiver Architecture Fig. 5.6 depicts the proposed RF-multibeam spatio-temporal RAKE (ST-RAKE) archi- tecture for radar. At the center of the architecture is an NB RF multibeam matrix. The function of this matrix is to form multiple (B), xed, simultaneous, narrow beams with dierent spatial orientations, each with its own input, across its N outputs. Several multibeam- matrix architectures are known in the literature and are discussed later in this chapter. 187 Figure 5.6: The RF-multibeam spatio-temporal RAKE architecture. Separate I/Q paths in the baseband section are omitted for simplicity. It should be noted that the multiple beams need not be xed in spatial orientation - some amount of steering on each beam can be incorporated to ensure full spatial coverage. To illustrate the principle of operation of the architecture, a timing diagram is pro- vided in Fig. 5.7. At transmit time, B orthogonal codes are transmitted along the dierent beams. In Fig. 5.7, this period is represented by the signal TX turning on. During this period, the beam inputs of the RF multibeam matrix are excited by orthog- onal codes (represented in Fig. 5.7 by the rather trivial code sequences 110 and 010) modulated onto the carrier signal. In the absence of multipath, each transmitted code would return only along the direction in which it was sent. However, in the presence of multipath, as is shown in Fig. 5.6, codes may return along other directions as well. At receive time, represented by the signal RX turning on, the architecture \listens" for the return of all codes along all beams. This is achieved by employing a bank of correlators matched to all the transmitted codes on each beam input. This enables the architecture 188 Figure 5.7: Timing diagram for the operation of the RF-Multibeam Spatio-Temporal RAKE architecture. to isolate LoS re ections from multipaths for enhanced scene reconstruction. The time interval between the transmit and receive periods is set by the desired time of ight (i.e., LoS/multipath distance) that the radar is looking for. This time interval, also called the radar range bin, is swept sequentially for complete spatial coverage. The architecture may also be described in the language of communication theory 2 . Fig. 5.8 depicts a communication-theoretic description of the RF-multibeam ST-RAKE architecture. While the transmitter and the receiver are co-located for radar, and share most of their resources in the RF-multibeam ST-RAKE architecture, they are represented 2 It should be noted that boldfaced letters are used to signify matrices and column vectors. The superscript H represents the conjugate transpose of a matrix or vector. 189 Figure 5.8: Communication-theoretic description of the RF-multibeam Spatio-Temporal RAKE architecture. While the transmitter and the receiver are typically co-located for radar, and share most of their resources in the RF-multibeam ST-RAKE architecture, they are represented separately in this gure as is typically done in communication sys- tems. separately in Fig. 5.8 as is typically done in communication systems. Assuming N trans- mitting and receiving antennas, the channel matrix H is anNN matrix whose entries represent the channel's transfer function for the corresponding transmitting-receiving an- tenna pair. In communication theory, the environment is typically assumed to be an idealized, rich-scattering environment, and the entries of H are independent, identically- distributed Gaussian random variables [110]. To describe the RF-multibeam ST-RAKE architecture, we follow the representation of [110], where a physical channel model is constructed from its constituent multipaths. Specically, H = L X l=1 l a( R;l )a H ( T;l ); (5.1) where L is the number of multipaths and l is the complex gain associated with the l th multipath. T;l and R;l are the phase progressions associated with the angles of transmission at the transmitter and incidence at the receiver, respectively, for the l th multipath. a() = [1;e j ::e j(N1) ]. The multibeam matrix, M , is an NB matrix given by 190 (M ) p;q =e j(p1) M;q ; (5.2) where B is the number of beams formed by the multibeam matrix and M;q is the phase progression associated with theq th beam. The input X is the vector [x 1 ;x 2 ::::x B ], where x 1 ;x 2 ::::x B are theB orthogonal codes that are sent along the individual beams. Ignoring channel noise, the nal output Y is given by Y = M H HMX = M H H B X m=1 x m a( M;m ) = M H L X l=1 B X m=1 l a( R;l )x m AF v ( T;l M;m ): (Y ) n = L X l=1 B X m=1 l x m AF v ( T;l M;m )AF v ( M;n R;l ): (5.3) AF v () = 1+e j ::e j(N1) is the complex-voltage array factor. The goal of the ST-RAKE radar is to determine the complex multipath gains l . From (5.3), it is easy to see that l is determined by correlating (Y ) n with x m , with n and m chosen such that R;l = M;n and T;l = M;m . The bank of correlators in the ST-RAKE architecture perform these correlations for all m = 1::B and n = 1::B. The architecture is called an RF-multibeam spatio-temporal RAKE because it is inspired by the RAKE receiver for communication in multipath-ridden channels [99]. The original RAKE architecture was proposed for single-antenna systems, and employed \RAKE ngers" only in the temporal domain to coherently combine dierent multipaths. 191 In the transceiver architecture proposed in this chapter, the multiple beams constitute RAKE ngers in the spatial domain, and the correlators that sequentially correlate the incoming signal with delayed versions of the code templates to determine the target's distance can be thought of as RAKE ngers in the temporal domain 3 . While the RF-multibeam spatio-temporal RAKE architecture has been illustrated here in the context of pulse-based radar, it may be extended to continuous-wave (CW) radar systems as well. The main advantages of pulse-based radar systems arise from their time-gated nature. The isolation between the transmit and receive sections is enhanced because of the dierent transmit and receive times. Multipath resolution is eased due to the dierence in arrival times of the LoS and multipath re ections. Finally, the isolated transmit and receive times imply that it is possible for the transmit and receive circuitry to share the same antenna array through T/R switches rather than expensive circulators. As a result, the remainder of this chapter, including the prototype targeting the vehicular- radar application space, will focus on pulse-based radar systems. The concept of a spatio-temporal RAKE has been proposed earlier for CDMA base- station receivers. In [64], the authors propose a 2D RAKE (Fig. 5.9). For each user, the multipaths are coherently combined by the implementation of multiple ngers, each em- ploying beamforming tuned to the direction of arrival of that multipath and time-delayed correlation tuned to the delay of that multipath. When performed across multiple users, each with a unique spreading code, the architecture bears a strong resemblance to the architecture proposed in this chapter. In the 2D RAKE, the settings of the beamformers 3 Indeed, hardware and power resources permitting, multiple correlators for each code and beam can be implemented that simultaneously correlate the received signal with dierent delayed versions of the code template. This would set up multiple simultaneous RAKE ngers in the temporal domain. 192 Figure 5.9: 2D RAKE receiver proposed for CDMA systems [64]. The slice corresponding to the i th user is depicted. N antennas are employed and L i multipaths are resolved for the i th user. and the time delays are determined by a channel-estimation block that determines the time and angle of arrival of each multipath. The radar architecture presented in this chapter, in eect, tries to perform this channel estimation. The 2D RAKE is sometimes also called the beamformer RAKE. Other variants, such as the space-time maximal-ratio- combining RAKE, decoupled space-time RAKE, joint space-time RAKE and space-time eigen RAKE, have also been studied [16]. 5.4 Code Requirements The orthogonal waveforms or codes to be employed on each beam of the RF-multibeam ST-RAKE architecture must satisfy certain criteria. A sharp autocorrelation prole is essential for maximum range resolution. From this point of view, Barker codes are optimal in terms of the peak-to-sidelobe ratio for any set of truncated coding sequences and hence 193 Figure 5.10: (a) Cross-correlation properties of modied bipolar Walsh-Hadamard se- quences of length 16. The diagonal matrix used to modify the Walsh-Hadamard matrix has the following diagonal elements: -1 1 1 1 1 -1 1 -1 -1 -1 -1 1 -1-1 -1 -1. (b) Auto- correlation properties of the modied Walsh-Hadamard sequences. are popular for radar [52]. In addition, the codes on the dierent beams must have low cross correlations for all time shifts to minimize interference between the codes. In practice, additional signal processing may be required on the received and correlated data to account for nite cross correlations. These requirements are quite similar to the requirements on the spreading sequences employed for channel separation in direct sequence CDMA (DS-CDMA) [132]. In syn- chronous DS-CDMA, it is sucient for the cross correlation to be zero for zero time shift. However, in the asynchronous case, such as uplink transmission, the cross correlation must be as low as possible for all time shifts. Several code families have been investi- gated for these applications. In [132], modied Walsh-Hadamard sequences are proposed. These sequences have zero cross correlation for zero time shift, making them suitable for synchronous DS-CDMA. They also exhibit reduced cross-correlation values for non-zero shifts when compared with unmodied Walsh-Hadamard sequences. Fig. 5.10 depicts the 194 cross-correlation and autocorrelation properties of bipolar, modied Walsh-Hadamard se- quences of length 16. The diagonal matrix used to modify the Walsh-Hadamard matrix has the following sequence of diagonal elements: -1 1 1 1 1 -1 1 -1 -1 -1 -1 1 -1-1 -1 -1 [132]. The rows of the resultant modied matrix are used as the code sequences. The ratio of the peak cross-correlation value to the peak autocorrelation value is 0.4375. Other code se- quences, such as M-sequences, Gold codes and Kasami codes, have also been investigated for DS-CDMA. The design of appropriate code families for the RF-multibeam ST-RAKE architecture is a topic that is beyond the scope of this thesis, and is a worthy topic for future research. It is anticipated that the hardware implementation that is discussed later in this chapter will serve as a testbed for experimentation with dierent codes. 5.5 Baseband Implementation - Analog versus Digital Baseband signal processing in radar involves the correlation of the received and down- converted signal with a delayed version of the transmitted baseband template. This correlation must be performed, either sequentially using a single correlator (Fig. 5.11(a) and (b)) or in parallel using multiple correlators (Fig. 5.11(c)) , for dierent delay values to search for targets at dierent distances. For each distance, or range bin, often multiple pulses must be transmitted, received, correlated and accumulated to achieve sucient SNR. Once this data has been collected for dierent range bins, additional signal pro- cessing may also be required, such as background or clutter removal. 195 Figure 5.11: (a) A simplied single-antenna, single-correlator, pulse-based radar with analog baseband processing. (b) Single-antenna, single-correlator, pulse-based radar with digital baseband processing. (c) A single-antenna, pulse-based radar with multiple cor- relators for simultaneous scanning of multiple range bins. Tradeos in digital baseband design have been examined in the context of ultra- wideband impulse systems for other applications in the past [95], [128]. In this section, the problem of partitioning the baseband processing across the analog and digital domains is examined for single-antenna and phased-array radar systems for simplicity. However, the conclusions are applicable to the RF-multibeam ST-RAKE architecture as well. Analog baseband signal processing in radar (Fig. 5.11(a)) involves the use of an analog correlator - essentially a multiplier or mixer followed by an integrator. The resultant integrated signal is then digitized for further radar signal processing. On the other hand, digital baseband processing involves direct digitization of the downconverted signal (Fig. 5.11(b)), and all signal processing is done in the digital domain. 196 Table 5.1: FCC-mandated specications for the vehicular-radar application space [34]. Bandwidth contained between 22 and 29GHz Bandwidth Center frequency > 24.075GHz Signal bandwidth > 20% or 500MHz Signal level Emissions < -41.3dBm EIRP over 1MHz, 1ms average Peak emissions < 0dBm EIRP in 50MHz around peak-emission freq. The advantage of some degree of analog pre-processing is that it alleviates some per- formance requirements of the ADC that follows it, such as speed and/or dynamic range. Digital signal processors are typically more exible and recongurable than their analog counterparts. However, this advantage is not particularly valuable for radar, where the signal processing required is a simple matched lter. To quantify the trade-os between the two approaches, it is necessary to determine the dynamic-range requirement for the vehicular-radar application space, which is targeted by the implementation described later in this chapter. 5.5.1 22-29GHz Commercial Vehicular-Radar Application Space - Dynamic-Range Analysis As was discussed in Chapter 3, the Federal Communications Commission (FCC) has opened up 7GHz of bandwidth from 22 to 29GHz for the deployment of UWB vehicular- radar sensors [34] intended for driver-assistance functions such as blind-spot detection, parking assistance and pre-crash detection. Single-antenna radar sensors for these appli- cations have been developed in SiGe processes [52]. The FCC-mandated specications and application-specic performance requirements are summarized in Tables 5.1 and 5.2. The ranging and target-size specications, in conjunction with the radar equation, determine the dynamic range required for the application. The radar equation enables 197 Table 5.2: Application-specic performance requirements for the vehicular-radar appli- cation space [51]. Range Minimum ranging distance = R min = 15cm Maximum ranging distance = R max = 30m Range Resolution 5cm Target Size Minimum RCS = min = 0.1m 2 (plastic 1/2" pipe) Maximum RCS = min = 100m 2 (automobile) us to compute the power received by the radar for a given transmitted power, target distance, target RCS, frequency of operation and radar antenna gain, and is given by P RX = P TX G 2 2 (4) 3 R 4 : (5.4) R is the distance of the LoS target, is its RCS, is the free-space wavelength correspond- ing to the frequency of operation, G is the radar antenna gain, P TX is the transmitted power in the continuous-wave sense and P RX is the received power. The distance R can vary from 15cm to 30m, and the RCS can vary from 0.1m 2 to 100m 2 . Assuming that the dynamic range is determined by the maximum- and minimum-possible received-signal levels, this results in a dynamic-range requirement of 122dB! In reality, the radar equation is not valid for large objects that are very close to the radar, as it assumes spherical-wave propagation and a target size that is small compared to the target distance. Therefore, a more realistic assumption is that the maximum received signal at the radar is equal to the transmitted power (P TX ) due to complete re ection from a large, nearby target. The minimum received signal is produced by the presence of the smallest object ( min =0.1m 2 ) at the maximum distance (R max =30m), and can be determined to be 9 10 14 P TX assuming =12mm for a center frequency of 25GHz and an antenna gain of 5dBi. This results in a dynamic-range requirement is approximately 130dB. 198 The design of circuits that exhibit such a large dynamic range, whether they are analog or digital in nature, requires a large power consumption. In order to alleviate the dynamic- range requirement on the receiver, a radar that uses a single receiving correlator and sequentially searches dierent range bins using transmitted pulses of dierent amplitudes and dierent receiver front-end gains is preferred (Figs. 5.11(a) and (b) over Fig. 5.11(c)). While the overall scan time is compromised in this approach, the power consumption, and even the energy expended for a complete scan, are signicantly reduced due to the reduced dynamic-range requirement. Once the range bin is xed, the dynamic range is only determined by the maximum and minimum target sizes, and hence is as low as max min =30dB 4 . Table 5.3 derives RF system specications for a 22-29GHz phased-array radar for ve- hicular applications assuming pulsed operation. The signal bandwidth is set by the desired range resolution. The number of elements is determined from the desired beamwidth, which is chosen to distinguish a typical automobile at the maximum ranging distance. Based on the FCC specications for the average- and peak-power levels, the duty cycle and continuous-wave EIRP are determined. The continuous-wave output-power require- ment per PA is relaxed in comparison to the system EIRP due to the presence of multiple elements. In order to determine the worst-case SNR and worst-case scan time, a single- channel noise gure of 8dB is assumed based on the capabilities of current CMOS tech- nology in the 22-29GHz frequency range. The worst-case SNR, achieved for the presence of the smallest target at the maximum distance, is determined to be -31.2dB and derives 4 This implies that 130-30=100dB of PA output-power control and receiver-gain control are required to account for the signal-level dierences across the range bins. 199 Table 5.3: RF performance specications for a phased-array radar for 22-29GHz vehicular applications based on FCC specications assuming pulsed-sinusoid operation. RF Performance Method of Calculation Spec. Bandwidth 310 8 m/s 2Range Resolution (5cm) 3GHz (BW ) Pulse Width 1 BW 333ps (T pulse ) Beamwidth Typical Automobile Dimension (2m) Maximum Range (30m) 180 o 4 o Number of 2 Beamwidth in radians + 1 32 Array Elements (N) Optimal Duty Cycle 10 41:3dBm+10log 10 500dBm 10 0.4% Continuous-Wave -41.3dBm+10log 10 BW 1MHz +10log 10 1 0:4% 17.5dBm TX EIRP (P EIRP ) Antenna Gain Based on typical antennas 5dBi G Continuous-Wave P EIRP -20log 10 N-G -17.6dBm Output Power per PA (P PA ) RX Single-Channel Based on current CMOS technology 8dB Noise Figure (NF ) Worst-case free-space G 2 2 min (4) 3 R 4 max -130dB path loss (P path loss ) Worst-case SNR (P PA +20log 10 N+P path loss ) -31.2dB (SNR min ) (-174dBm+10log 10 BW +NF -10log 10 N) Worst-case scan time 10 jSNR min j+10dB 10 T pulse 1 Duty Cycle(0.4%) 1.1ms (Desired SNR is 10dB) 200 benet from the presence of multiple array elements. In order to improve this SNR to a threshold of +10dB, multiple pulses must be sent, received, correlated and accumulated, which results in a worst-case scan time of approximately 1ms. It should be mentioned that 32 elements are dicult to integrate onto a monolithic CMOS radar chip. It is likely that practical systems will multiple scalable sub-arrays to achieve the desired resolution, with each sub-array integrating 4 or 8 elements onto a single-chip. Under these assumptions, the digital-baseband approach requires an ADC with 30dB of dynamic range and a sampling rate of 6GSa/s. In addition, a digital matched l- ter with the same dynamic range and speed is also required. In the analog-baseband approach, while the analog correlator must demonstrate a dynamic range of 30dB, the speed requirement on the ADC is reduced by a factor equal to the duty cycle. This is because high-speed correlation is performed in the analog domain, and the ADC only needs to sample and digitize the integrated value after each pulse 5 . To determine the power consumption of these two approaches, the following sections quantify the power consumptions of each of these blocks given their performance requirements. 5.5.2 ADC Power Consumption To determine the power consumption of a high-speed ADC with a given sampling rate and a required number of bits, a survey of state-of-the-art high-speed ADCs is useful. Table 5.4 depicts GSa/s ADCs with the highest gures of merit based on a survey recently published by B. Walden [125]. The gure of merit (FOM ADC ) is dened as 5 As was mentioned earlier, multiple pulses are often required to achieve sucient SNR. This accu- mulation can be done either in the digital domain or in the analog domain. If performed in the analog domain, the speed requirement of the ADC would be further reduced by a factor equal to the number of pulses accumulated. 201 Table 5.4: Survey of moderate-dynamic-range ADCs with sampling rates larger than 1 GSa/s (courtesy [125]). ENOB is derived from (5.6). Vendor Tech. f sample n bits SNDR ENOB P ADC FOM ADC (GSa/s) (W) (TSa/J) Nortel 0.13m SiGe 22 5 22.8 3.8 3 0.102 (P. Schvas) Agilent Labs 0.18m CMOS 20 8 29.5 4.9 9 0.067 (Poulton e al.) HP Bipolar Hybrid 4 8 41.5 6.9 39 0.012 (Schiller, Byrne) HP/Rockwell GaAs HBT 4 6 33.1 5.5 5.7 0.032 (Poulton, Wang) Rockwell GaAs HBT 3 8 46 7.7 5.5 0.111 (RAD008) Atmel npn bipolar 2.2 10 48 8 4.2 0.134 (AT84AS008) Atmel npn bipolar 2 10 51 8.5 6.5 0.111 (AT84AS004) Rockwell GaAs HBT 2 8 37 8.5 5 0.029 (RSC-ADC080S) Maxim Bipolar 1.5 8 46.9 7.8 5.25 0.064 (Max 108) Atmel npn bipolar 1.4 10 47.5 7.9 4.6 0.014 (TS83102) Teranetics 0.13m CMOS 1 11 55 9.2 0.25 2.3 (S. Gupta et al.) Rockwell GaAs HBT 1 10 55 9.2 5 0.115 (RAD010) FOM ADC = 2 ENOB f sample P ADC ; (5.5) where f sample is the sampling speed in Hertz and P ADC is the power consumption in watts. The required number of eective ADC bits (ENOB) is determined fromDR, the required dynamic range, using the commonly-used formula ENOB 10log 10 DR 6 : (5.6) 202 It is noteworthy that P ADC = 2 10log 10 DR 6 f sample FOM ADC = p DRf sample FOM ADC : (5.7) In other words, the power consumption of an ADC is proportional to the square root of the required dynamic range. It should be noted that the assumption that the power consumption doubles with every extra bit of precision is only true for ADCs with moderate dynamic range. For ADCs with a dynamic range greater than 75dB, the dynamic range tends to be limited by thermal noise rather than quantization noise, which results in a quadrupling of power for every extra bit [88]. The ADC power consumption then becomes proportional to the dynamic range, rather than to its square root. 5.5.3 Analog Correlator Power Consumption Fig. 5.12 depicts the schematic of an analog correlator. The downconverted received signal is multiplied with the code template in a current-commutating mixer and the resultant signal (which is in the current domain) is dumped onto an integrating capacitor. The integrated voltage is sampled by an ADC after each pulse and a shunt switch resets the correlator in preparation for the next pulse. It should be noted that this schematic assumes that the accumulation of multiple pulses to achieve high SNR is performed in the digital domain. If this accumulation is to be performed in the analog domain to further reduce the ADC's speed requirement, switches may be included in series with the integrating capacitor. The switches can be used to disconnect the capacitor from the active devices in between pulses, so that the capacitor voltage does not decay due to the 203 nite output resistance of the circuit. The shunt switch would then reset the capacitor only after sucient SNR has been achieved in preparation for the next range bin. Figure 5.12: An analog correlator. A useful denition of the dynamic range of the correlator is the ratio of the input- referred -1dB compression point to the input-referred noise level. In order to determine the input-referred -1dB compression point, a\saturation-model" is assumed for the input dierential pair with a linear gain of g m and a dierential threshold voltage of V diff;th (Fig. 5.12) 6 . As was discussed in Section 4.1.1 of Chapter 4, for a saturation block, a sinusoidal dierential input votage of amplitude A produces a dierential output current with a fundamental component given by 6 gm is the transconductance of each device and V diff;th = I bias gm . 204 (I 2 I 1 ) fund = g m A 0 @ 2 sin 1 V diff;th A + 2V diff;th A s 1 V 2 diff;th A 2 1 A : (5.8) This fundamental component is compressed by 1dB for an input amplitude of A 1dB 1:25V diff;th = 1:25 I bias g m : (5.9) It is assumed that compression is dominated by the input swing rather than the swing at the output nodes. To determine the noise performance, assume that the code template that the input is correlated with is a pulse of width T pulse , as shown in Fig. 5.12. During the duration of the pulse, the commutating transistors completely switch resulting in the equivalent circuit depicted on the right in Fig. 5.12. The dierential short-circuit output noise current, obtained by replacing the capacitor with a short circuit, is given by I 2 out;n = I 2 n1;n2 +I 2 dn;n1 +I 2 dn;p2 +I 2 dn;p1 4 = 4kT g d0 f, assuming the pMOS current sources are sized to have an identical g d0 to the input nMOS transistors for simplicity 7 . The nMOS current source does not contribute any noise in dierential mode, and the switching noise of the commutating transistors is ignored under the assumption of hard-switching square- wave input pulses. Then, we have V out;n (t) = 1 C Z t 1 I out;n ()V pulse ()d; (5.10) 7 is the device excess noise factor and g d0 is the channel conductance at zero drain-source bias. 205 where V pulse (t) is the code template with a normalized pulse amplitude of 1. The ADC samples the integrated signal at the end of the pulse (t = T pulse ). In determining the mean-square value of this sample, we have V 2 sample = E V 2 out;n (T pulse ) = E 1 C 2 Z T pulse 1 I out;n (t 1 )V pulse (t 1 )dt 1 Z T pulse 1 I out;n (t 2 )V pulse (t 2 )dt 2 = 1 C 2 E Z T pulse 1 Z T pulse 1 I out;n (t 1 )I out;n (t 2 )V pulse (t 1 )V pulse (t 2 )dt 1 dt 2 = 1 C 2 Z T pulse 1 Z T pulse 1 4kT g d0 (t 1 t 2 )V pulse (t 1 )V pulse (t 2 )dt 1 dt 2 = 4kT g d0 C 2 T pulse : (5.11) To refer this noise to the input, the sampled noise level must be divided by the gain applied to an input pulse, which is nothing but gmTpulse 2C . Therefore, the input-referred noise level becomes V 2 in;n = 16kT g d0 g 2 m 1 T pulse : (5.12) Interestingly, this result indicates that the correlator's noise performance is identical to that of a dierential pair with pMOS current-source loads and 1 T pulse as the noise- equivalent bandwidth. The dynamic range may now be written as DR = A 2 1dB V 2 in;n 1:56I 2 bias T pulse 16kT g d0 0:1I bias V od T pulse kT ; (5.13) as, in general, g d0 is equal to 2I ds V od , where V od is the overdrive voltage (=V gs V th ). 206 Equation (5.13) captures several trade-os in the design of analog signal-processing elements. Firstly, it is clear that to support a larger dynamic range, a linearly-larger power consumption is required. Secondly, as the pulse width decreases, which corresponds to an increase in the signal bandwidth, a larger power consumption is required to maintain the same dynamic range. This is due to the greater amount of noise that is integrated over the larger signal bandwidth. Finally, the overdrive voltageV od can be related to available supply voltage as nV od + Output Swing Budget =V dd ; (5.14) where n is the number of devices that are vertically stacked in the circuit (four for the correlator depicted in Fig. 5.12). As a result, with the reducing supply voltages that result from the scaling of technology to lower process nodes, the overdrive voltages reduce and a larger current consumption is required to maintain the same dynamic range. To verify this theoretical formulation, simulations are performed in SpectreRF using transistors from IBM's 8RF 0.13m CMOS process across dierent bias levels (Fig. 5.13). The device sizes are indicated in Fig. 5.12 forI bias =4.3mA, and the sizes for other current levels are scaled linearly to maintain constant overdrive levels of approximately 200mV for each transistor. A pulse width of 200ps is employed which corresponds to a signal bandwidth of approximately 5GHz. C=1pF, V dd =1.5V and is approximately 2/3 based on the process models. The RMS value of the sampled output noise voltage is determined through root-mean-square-averaging across several transient-noise-simulation runs. A good agreement is seen between theory and simulations. There is a constant multiplicative 207 Figure 5.13: (a) SpectreRF simulations of an analog correlator implemented in IBM's 8RF 0.13m CMOS process. The schematic of the correlator is provided in Fig. 5.12. The pulse width is 200ps andC=1pF. is determined to be 2/3 from the process models. (b) Simulated dynamic range computed as the ratio of the output-referred -1dB compression point to the RMS sampled output noise voltage. dierence of approximately 5dB between the theory and simulations in both the output- referred -1dB compression point and dynamic range, and this is attributed to capacitive parasitics. However, the linear dependence of dynamic range on power consumption is indeed observed. It should be noted that icker noise has been ignored in the presented analysis and simulations. However, it can be a signicant factor that increases the noise level and limits the dynamic range, especially in deep-submicron processes. The incorporation of icker noise into the presented formulation is a topic for future investigation. 5.5.4 Digital Correlator Power Consumption Fig. 5.14 depicts the block diagram of a typical digital correlator, also called a matched lter. A bank of n bits -wide shift registers are used to time-shift the received signal. As is the case with ADCs, n bits is determined from the dynamic-range requirement. The number of shift registers is equal to the code length (2 m ). Each register is then multiplied 208 by the correlator coecients which represent the code sequence. Assuming two-level codes for simplicity, these coecients would be 11...1 or 00...0. Hence, the multipliers can be simply implemented using multiplexors. The various multiplied values are then added using a binary tree of n-bit adders. Figure 5.14: Block diagram of a typical digital correlator. To determine the power consumption of the shift-register portion, the analysis of [48] is followed. It is assumed that each digital gate provides a unit load to its corresponding driver. In each register, on an average, for random data, n bits 2 bits ip their values every clock cycle. The fan out of each bit is 2 because it drives the next register and a load in the correlation network. In addition, the clock ips twice every cycle. Therefore, P shift /f CLK V 2 dd 2 m n bits 2 2 + 2 m n bits 2 /n bits 2 m f CLK V 2 dd : (5.15) 209 The rst term in the equation above represents theCV 2 switching power associated with the n bits 2 bits that ip every clock cycle on an average in each register. The second term represents the switching power associated with the clock. The power consumption in the multipliers is ignored owing to the simplifying assump- tion of two-level codes. In the adder tree, the rst level of adders are 2 m1 in number and n bits -wide. The second-level adders are 2 m2 in number and n bits + 1-wide and so on. Ignoring the increase in adder width and assuming that the power consumption of an n-bit adder is proportional to n, we have P adder /f CLK V 2 dd n bits 2 m1 + 2 m2 :::1 /n bits (2 m 1)f CLK V 2 dd : (5.16) Given these formulations for the power consumptions of the shift-register and adder portions, it becomes possible to dene a normalized Figure of Merit for digital matched lters (FOM corr ). FOM corr = P corr n bits 2 m f CLK V 2 dd L ; (5.17) where P corr is the power dissipation and L is the channel length of the technology em- ployed. L is present because the power dissipation is also proportional to the capacitance associated with each node, which scales down roughly linearly with technology. It is in- teresting to note thatP corr /n bits / 10 6 log 10 DR. In other words, the power dissipation of digital matched lters is proportional to the logarithm of the dynamic-range requirement. 210 Table 5.5: Survey of digital matched-lter designs. The references with an asterisk(*) are designs with I and Q channels. Therefore their power dissipation is halved. Ref. Technology f CLK V dd n bits Code Length P corr FOM corr [48] 2m 25MHz 5V 8 256 1.373 W 5.410 7 [48] 2m 25MHz 5V 8 256 0.753 W 310 7 [80]* 0.8m 50MHz 5V 4 512 0.092 W 4.510 8 [80]* 0.8m 20MHz 2.5V 4 512 0.007 W 3.410 8 [131]* 0.8m 93MHz 5V 4 176 0.138 W 1.110 7 [131]* 0.8m 44MHz 2.6V 4 176 0.030 W 1.810 7 [134] 0.6m 2.5MHz 2V 4 16 0.0016 W 4.210 6 [50] 0.18m 15.6MHz 1.6V 6 128 0.0009W 1.610 7 [113] 0.8m 50MHz 3V 1 128 0.170 W 3.710 6 In order to determine the typical FOM corr of digital matched lters, a survey of matched-lter designs is performed. The results of the survey are depicted in Table 5.5. It should be mentioned that several designs in the survey employ several samples per code bit. This increases the eective code length (depth of the shift register and number of adders). It also increases the clock frequency beyond the code rate. Based on this survey, the best (lowest) FOM corr achieved is 3.410 8 . 5.5.5 Comparison of Analog- and Digital-Baseband Approaches Fig. 5.15 shows a comparison between the power consumptions of the various blocks as a function of the required dynamic range. A bandwidth of 3GHz for vehicular radar sets the sampling rate at 6GSa/s for the ADC to be used in the digital-baseband approach. FOM ADC is assumed to be 2.3TSa/J, the best reported in the survey described earlier. As was mentioned earlier, for high-resolution ADCs, the assumption that an extra bit of resolution doubles the power consumption no longer holds true, since the ADC tends to be limited by thermal noise. Therefore, a second line representing the quadrupling of power for every extra bit in a high-resolution ADC is also included forDR> +75dB. The 211 bandwidth also sets the pulse width at 333ps for the analog correlator. is assumed to be equal to 3 (typical for deep-submicron processes), V dd is set to 1.2V (typical for a 90nm CMOS process) and V od is assumed to be 0.175V, assuming four stacked transistors in an analog correlator and an output swing budget of 0.5V. For the digital matched lter, a code length of 8 is assumed. The clock frequency is 3GHz, V dd is 1.2V and L is set to 80nm (the drawn channel length of a typical 90nm CMOS process). FOM corr is assumed to be 3.410 8 , the best reported in the survey of digital matched lters described earlier. Figure 5.15: Comparison of the power consumptions of a 6GSa/s ADC, an analog cor- relator handling a 333ps pulse with = 3, V od = 0:175V and V dd = 1:2V, and a digital matched lter with a code length of 8, f CLK = 3GHz, L = 80nm and V dd = 1:2V. The gures of merit for the ADC and digital matched lter are obtained from the surveys presented earlier. The power consumption of the analog correlator rises the fastest with the required dynamic range due to their linear relationship. The ADC has a power consumption that is proportional to the square root of the dynamic range, while the digital matched lter exhibits a logarithmic dependence, resulting in a gradual increase in the power 212 consumption. For the digital-baseband approach, it is clear that, for a typical 90nm process, the ADC is the bottleneck in terms of the power consumption when compared to the digital matched lter. Table 5.6: Comparison of the power consumptions of the analog- and digital-baseband approaches for vehicular radar. The bandwidth is assumed to be 3GHz, the duty cycle is 0.4% and the required dynamic range is 30dB.FOM ADC is assumed to be 8.2TSa/J and FOM corr is taken as 3.410 8 . Component Digital Baseband Analog Baseband Comment Power Comment Power ADC 6GSa/s, 5 bits 83.5mW 24MSa/s, 5 bits 0.334mW Analog =3, V dd =1.2V, Correlating N/A N/A V od =0.175V, 2.6W Integrator T pulse =333ps Digital f CLK =3GHz, V dd =1.2V Matched L=80nm, 0.5mW N/A N/A Filter Code Length=8 Total Power 84mW 0.34mW Based on these numbers, Table 5.6 compares the power consumptions of the analog- and digital-baseband approaches. The required dynamic range for vehicular radar is 30dB, as was discussed earlier, and the duty cycle is 0.4%. In the digital-baseband approach, the power consumption is dominated by the high-speed ADC, and is 83.5mW. In the analog-baseband approach, as was discussed earlier, the speed requirement on the ADC is reduced by a factor equal to the duty cycle. Furthermore, a 30dB-dynamic-range analog correlator requires only 2.6W. As a result, the total power consumption is as low as 0.34mW, making the analog-baseband approach the preferred implementation for vehicular radar 8 . 8 For a dynamic-range requirement as low as 30dB, it is possible that stray factors that were not taken into account in the analog-correlator formulation will dominate over the computed power consumption of 2.6W. Such factors include the power of the common-mode feedback circuitry and the power associated with the charging and discharging of the capacitors of the commutating transistors that are being switched hard. Nevertheless, the power consumptions of both the analog and digital correlators are dominated by 213 The digital-baseband approach is power hungry because the high-speed ADC con- tinuously digitizes the received signal at a high speed, even though the radar is only interested in one range bin at any give time. The power consumption of this ADC may also be reduced by a factor equal to the duty cycle through the design of an ADC that exploits \intelligent sampling" only in the window (i.e., range bin) of interest. Such tech- niques that exploit known properties of the system/application must be investigated to achieve high-speed digitization at high dynamic ranges and reasonable power consump- tions. Another application that can benet from such investigations is Software-Dened Radio (SDR). The classical view of SDR involves direct digitization of the received signal after the antenna [12]. To cover the major radio standards upto 5GHz, a 12-bit, 10GSa/s ADC is required [12], which currently consumes a large power of 1.9W based on the survey described earlier. In [12], the authors describe a mixed-signal preconditioning technique that relaxes the dynamic-range requirement of the ADC, resulting in signicant power savings. 5.6 A 4-Channel 24-26GHz RF-Multibeam ST-RAKE Transceiver for Vehicular Radar in 90nm CMOS Based on the RF Multibeam ST-RAKE concept, a 24-26GHz single-chip radar is im- plemented in IBM's 9RF-LP 90nm CMOS process for vehicular-radar applications. A characterization of the process is presented in Appendix A.3. The radar employs a 44 multibeam matrix and hence supports 4 beams. The radar chip occupies an area of their respective ADCs, and the ADC that is required for the analog-baseband design requires signicantly lower power due its alleviated speed requirement. 214 Figure 5.16: Chip microphotograph of the experimental 90nm CMOS 24-26GHz RF- multibeam ST-RAKE radar. 3.44.2mm 2 . The chip microphotograph and block diagram are depicted in Fig. 5.16 and Fig. 5.17 respectively. The RF front end of each channel consists of a LNA and a PA which share an antenna path through a low-loss T/R switch 9 . The T/R switch's interface with the antenna is single-ended to ease the mm-wave chip-antenna transition, but its interface with the PA and LNA is dierential through an on-chip balun. The implemen- tation of the LNAs and PAs as dierential circuits is mainly motivated by the need to reduce substrate coupling between the PA and LNA and between adjacent channels. At 9 The implementation of switches enables the sharing of the antenna because the radar is designed to be half-duplex. In other words, simultaneous transmit and receive capability is not required. As was mentioned before, this is an advantage that pulse-based radars enjoy over continuous-wave radars - the time-gated nature enables sharing of resources and improves isolation between the transmit and receive sections. 215 Figure 5.17: Block diagram of an experimental 90nm CMOS 24-26GHz RF-multibeam ST-RAKE radar. 216 the output of the LNA and the input of the PA, another set of switches are incorporated to allow the PA and the LNA to share the area-hungry mm-wave multibeam matrix for beamforming. The outputs of the multibeam matrix interface with the baseband blocks, which incorporate separate I/Q paths, perform on-chip analog baseband processing and share the multibeam matrix between transmit and receive modes. An on-chip LO is implemented and feeds the baseband blocks. At the time of the writing of this thesis, the measurement of several blocks of the prototype are still ongoing. Measurements have been obtained for the on-chip LO and the 44 multibeam matrix and are presented here. It is anticipated that the measurement of the remaining blocks as well as a system-level demonstration of the chip's ST-RAKE radar functionality will be completed shortly. Figure 5.18: Circuit diagram of the T/R switch. Fig. 5.18 depicts the circuit diagram T/R switch and Fig. 5.19 depicts its close-up microphotograph. At the input is a stacked transformer that converts the single-ended input to a dierential signal. The stacked windings are single-turn spirals with an outer dimension (OD) of 195m and a width (W) of 10m. The top spiral is implemented in the top metal layer (LB), while the lower spiral is implemented in the next two metal layers 217 Figure 5.19: Chip microphotograph of the T/R switch. The coupled CPWs are bent substantially to minimize their area consumption. (M1 2B and M2 2B) which are strapped together. The second spiral has a capacitance shunted across its terminals to resonate out the inductance of the spiral at 25GHz. Once the input is converted to a dierential signal, the T/R switch employs quarter-wavelength (/4) transmission lines to eliminate the series transistor that is required in conventional T/R switch designs. A /4 line with a dierential characteristic impedance close to the required 100 is employed in each branch. When a branch is disabled, the shunt transistors at the end provide a (near) short-circuit to ground. The /4 line transforms the short circuit to an open circuit so that the matching condition for the other branch is undisturbed. The /4 lines are implemented as coupled coplanar waveguides (CPWs) in the LB metal layer with a width (W) of 8m, a spacing to ground (S) of 10m and a dierential spacing (D) of 10m. The ground plane underneath is formed in the two bottom metal layers (M1 and M2). The coupled CPWs are bent to minimize their area consumption (Fig. 5.19). Fig. 5.20(a) depicts the simulated small-signal S-parameters of the switch when port 3 is enabled and port 2 is disabled. The insertion loss (S 31 ) is approximately 3dB, half of 218 Figure 5.20: (a) Simulated small-signal performance of the T/R switch. Port 3 is enabled and port 2 is disabled. (b) Simulated large-signal T/R switch performance. which is contributed by the input balun and half by the switch. The re ection coecients are acceptable over the frequency ranges of interest and the transmission to the disabled port (S 21 ) is approximately -25dB. The large signal performance of the switch at 25GHz is depicted in Fig. 5.20(b). The elimination of the series transistor greatly enhances the switch's power handling capability, and the input-referred -1dB compression point is approximately 19dBm. Fig. 5.21(a) depicts the circuit diagram of LNA and its output switch and Fig. 5.21(b) depicts the chip microphotograph. The LNA is a four-stage design, with the current sharing employed in the rst and second pair of stages. Each stage employs a dierential pair with a dummy pair for unilateralization through C gd -cancellation. The stages are all identical to each other except for the fact that the rst stage has an input matching network and the last stage has an output matching network that are designed to match the ports to 100 . The inductors are implemented as spirals in the LB metal layer with a patterned ground shield formed in M1.The total bias current consumption is 18mA from the supply voltage of 1.2V. Stages 2 and 4 also have pMOS switches at 219 their outputs. These switches reduce the LNA gain during the transmit phase to prevent saturation of the LNA due to the PA's output and also contribute toward stability of the PA-LNA combination. Figure 5.21: (a) Circuit diagram of the four-stage LNA. (b) Chip microphotograph of the LNA. The output side switch consists of series transistor switches, with a dummy set of transistors with inverted connections. These dummy transistors exploit the dierential 220 Figure 5.22: (a) Circuit diagram of the single-stage pseudo-dierential PA. (b) Chip microphotograph of the PA. nature of the circuit to provide feedthrough-capacitance cancellation and essentially en- hance isolation. This too is essential for the stability of the PA-LNA combination in transmit mode. Fig. 5.22(a) depicts the circuit diagram of the PA and its input switch. Fig. 5.22(b) depicts the chip microphotograph. The input switch is identical to the output switch of the LNA. The PA is a single-stage cascoded pseudo-dierential pair that is designed for class A operation. Class A operation is necessitated by the fact that the PA must 221 be linear to support the superposition of the codes being transmitted on the dierent beams. The PA is biased to draw 60mA from the supply using a scaled replica branch that uses an operational amplier-based feedback loop to x the current across process and temparature variations. As is the case in the LNA, there is a shunt pMOS switch at the output of the PA to reduce the gain in receive mode to ensure stability of the LNA-PA combination. The 490m CPS at the input of the PA is necessitated by the layout to compensate for the extra length of the LNA due to its four-stage nature. Figure 5.23: (a) Simulated small-signal S-parameters of the PA-LNA-T/R switch com- bination in receive mode. (b) Simulated large-signal performance of the PA-LNA-T/R switch combination in receive mode. Fig. 5.23 depicts the simulated performance of the T/R switch, LNA and PA com- bination in receive mode. The LNA is expected to exhibit a peak small-signal gain of approximately 32dB at 25GHz and an NF<5.7dB over the 24-26GHz frequency 10 . Fig. 5.23(b) shows the simulated large-signal performance of the LNA at 25GHz. The input- referred -1dB compression point of the LNA is expected to be approximately -35dBm. 10 Based on T/R switch simulations, the contribution of the T/R switch to the NF is approximately 3dB. 222 Figure 5.24: (a) Simulated small-signal gain of the PA-LNA-T/R switch combination in transmit mode. (b) Simulated large-signal performance of the PA-LNA-T/R switch combination in transmit mode. Fig. 5.24 depicts the simulated performance of the T/R switch, LNA and PA com- bination in transmit mode. The PA is expected to exhibit a peak small-signal gain of approximately 11dB at 25GHz. Fig. 5.24(b) shows the large-signal performance of the PA at 25GHz. The PA is expected to achieve an output-referred -1dB compression point of 8dBm and a saturated output power level in excess of 13.5dBm. Several multibeam matrices have been reported in past literature [18], [14], [29]. The Blass matrix [14] (Fig. 5.25(a)) and Chu's architecture [29] (Fig. 5.25(b)) are true- time-delay architectures and hence are suitable for extremely wideband signals. The Blass matrix uses varying lengths of transmission lines to generate delay dierences and employs area-hungry couplers to transfer signals from one transmission-line to another. Chu's architecture reduces the number of delay elements required in comparison to the Blass matrix. In the implementation described in [29], the couplers are replaced with active buers to transfer the signal from one line to another. This further reduces the area requirement but comes at the expense of power consumption and linearity. 223 Figure 5.25: (a) The Blass Matrix. (b) Chu's mulitbeam architecture for the simple case of two antennas. The Butler matrix [18], in the form of a 4-input, 4-output realization, is depicted in Fig. 5.26(a). It employs -3dB quadrature hybrids and xed-length transmission lines to generate the multiple beams. Being a purely passive structure, it is bidirectional in na- ture and highly linear. In view of these advantages, the Butler matrix was chosen for the implementation described in this section. It is, however, not a true-time-delay architec- ture as it maintains prescribed constant phase dierences over frequency at its outputs between the signals incident at the inputs. Hence, it is suitable only for applications 224 Figure 5.26: (a) A 4-input, 4-output Butler matrix. (b) Implemented -3dB quadrature branchline hybrids. where the fractional bandwidth is not too large. However, as was discussed in Chapter 3, for a four-element array in the vehicular-radar frequency range, the lack of true-time delays does not signicantly degrade array performance. Fig. 5.26(b) depicts the implemented -3dB, 90 o couplers, realized as branchline hy- brids. The transmission lines of the branchline hybrids are implemented using coupled coplanar waveguides in LB, with the ground plane implemented in M1 and M2. Fig. 5.27(a) depicts a chip microphotograph of a single hybrid, while Figs. 5.27(b)-(d) sum- marize the simulated performance. Simulations based on foundry models for the coupled CPWs are compared to EM simulations of the hybrid in IE3D. A reasonable agreement is seen in all parameters. Based on the foundry models, the loss from the input port to the through and coupled ports is 4-5dB in the desired frequency range. This implies a dissipative loss of 1-2dB when compared to the ideal hybrid loss of 3dB to each port. The input re ection coecient, isolation to the isolated port and phase dierence between the through and coupled ports are all acceptable based on simulations. 225 Figure 5.27: (a) Chip microphotograph of the implemented -3dB quadrature branchline hybrid. (b) Simulated insertion loss to through and coupled ports. (b) Simulated re ec- tion coecient and isolation to the isolated port. (d) Phase dierence between through and coupled ports. The small-signal S-parameters of the Butler matrix are measured through test SGS pads that are placed in the layout at the four outputs of the Butler matrix. Unfortunately, test pads were not placed at the four inputs due to space constraints. As a result, the inputs of the four T/R switches are probed with the PA-LNA-T/R switch combinations congured to receive mode. Using this probing scheme, the insertion gains and phases over frequency from each input to each output are determined, and this data is used to synthesize normalized UWB array patterns for each beam (Fig. 5.28). The waveform is assumed to be a pulsed sinusoid with 500ps pulse width and 25GHz center frequency. 226 Figure 5.28: Synthesized normalized UWB array patterns of the 44 Butler matrix from measured S-parameter data. The antenna spacing is assumed to be half-wavelength at 25GHz and an energy detector is assumed to gauge the output strength. The array performance is seen to be reasonable and conrms the fact that the lack of true-time-delays does not signicantly degrade performance for the bandwidths and number of array elements of interest. The Butler matrix is area-hungry and represents a poor utilization of the power of CMOS technology, as it does not take advantage of the active devices that can be reliably integrated to reduce the area consumption in any way. A more-compact 4-input, 4-output Butler matrix operating at 24GHz was reported recently [27], and occupies a silicon area of 0.9mm0.46mm while exhibiting a measured minimum insertion loss of 2.25dB. While the bidirectional nature of the architecture does allow the Butler matrix to be shared between transmit and receive modes, thus keeping the overall transceiver area under check, alternate compact multibeam architectures that do not rely on passive elements for delays/phase shifts are a worthy line of research for the future. 227 Figure 5.29: Chip microphotograph and block diagram of each beam's baseband block - transmit mode. The output of each beam is connected to a baseband block, the chip microphotograph and block diagram of which are depicted in Fig. 5.29 for transmit mode. A dierential Wilkinson power splitter/combiner [130] is used to combine the signals from the I and Q sub-blocks. The splitter is constructed using coupled CPW lines with the appropriate characteristic impedance (100 p 2 140 ). Each I/Q sub-block consists of a passive mixer that, in up-conversion mode, is driven by a TX modulator and an LO buer. The passive mixer is chosen for bidirectionality - the mixer, the LO buer driving its LO port and the power splitter/combiner are shared between transmit and receive modes. The TX modulator receives is code data from a shift register - this enables exibility during testing for experimentation with dierent coding schemes. The frequency of the code, which governs the bandwidth of the transmitted signal, is set by the externally provided 228 shift register clock and the other timing signals that control the generation and duration of the code are externally provided as well. Figure 5.30: Chip microphotograph and block diagram of each beam's baseband block - receive mode. The block diagram and chip microphotograph of the baseband block in receive mode are depicted in Fig. 5.30. The RF signal is split by the power splitter to the I and Q sub- blocks, where it is downconverted to baseband by the passive mixer. The downconverted signal in each sub-block is then correlated with each of the four transmitted codes and then integrated using four correlators and integrators. The four correlators receive the template codes from shift registers in a manner similar to the TX modulator for testing exibility. Fig. 5.31(a) shows the schematic diagram of the passive mixer present in each I/Q sub-block. Fig. 5.31(b) shows the simulated large-signal downconversion performance of the mixer. The baseband side of the mixer is terminated to 100 , the LO signal has a 229 Figure 5.31: (a) Schematic diagram of the passive mixer in each baseband I/Q sub-block. (b) Simulated large-signal downconversion performance of the passive mixer. frequency of 25GHz and a dierential peak voltage of 1V, the RF frequency is 26GHz and V bias = 0:5V . The input-referred -1dB compression point is close to -1dBm, and the conversion gain is approximately -8.4dBm. Figure 5.32: Schematic diagram of the 25GHz VCO employed for I/Q LO generation. Fig. 5.32 depicts the schematic diagram of the coupled VCO architecture employed for I/Q LO generation. Each individual VCO is implemented using a cross-coupled nMOS pair and an LC resonant load. The 227pH inductor is implemented as a single-turn spiral 230 inductor in LB with an outer dimension of 145m, a line width of 15m and an M1 slotted ground shield. The Q at 25GHz is 24.6 based on foundry models. Peak Q is achieved at a frequency of 33.5GHz and is equal to 26.1. nMOS varactors are included for frequency tuning, and a bank of calibration varactors are also included to accommodate for process and layout mismatches to ensure good quadrature. A pMOS current source is employed due to its superior icker noise performance when compared to its nMOS counterpart. The two VCOs are coupled to each other to ensure quadrature through the employment of dierential-pair injection transistors of which one pair has an inverted output connection in comparison to the other [107]. Each VCO is also equipped with an output buer that generates sucient output power to distribute the I/Q LO signals to the various baseband blocks. Each VCO, along with its injection transistors, consumes approximately 5.2mA of current, and each output buer consumes 15.4mA. Figure 5.33: Circuit diagram of the LO distribution network. I/Q LO distribution is accomplished in the following manner - the inputs of the I/Q LO buers in each baseband block have a 100 resistor shunted across their inputs to provide a termination for the long 100 coupled CPW lines that connect each LO buer's 231 input to the output of the output buer of the coupled VCO (Fig. 5.33). Therefore, each I/Q output buer of the coupled-VCO pair has four terminated 100 lines in parallel interfacing with it, and hence its output is matched to 25 . Each I/Q LO buer in the baseband blocks consumes 9mA and this, in conjunction with the power generated by the VCO output buers, is sucient to ensure a peak dierential swing in excess of 1V at the various baseband mixers. The power consumption associated with LO distribution is rather large and may be computed to be 215:4mA1:2V+89mA1:2V= 123:4mW. The sources of this power consumption are the 100 termination resistors at the inputs of the I/Q LO buers that dissipate the power generated by the I/Q VCO's output buer and the I/Q LO buers themselves that provide additional voltage gain. An alternate design approach involves the matching of the input impedance of each I/Q passive mixer to 100 . This would potentially eliminate the 100 termination resistors and the I/Q LO buers, as the matching network would provide the required voltage gain. It should be noted that the power associated with LO distribution is further exacer- bated by the long distances (1-3mm) over which the LO signals need to be routed. These long distances result in transmission-line losses that must be overcome by the I/Q VCO's output buers. The challenge of LO distribution is central to multibeam transceivers and power- and area-ecient techniques to accomplish the distribution remain an open topic of research. Fig. 5.34(a) depicts the measured frequency-tuning characteristic of the I/Q VCO when all calibration bits are set to 0/1. The simulated tuning curve when all bits are 0 is also depicted. The frequency error is approximately 1GHz at a control-voltage value 232 Figure 5.34: (a) Measured frequency tuning characteristic of the I/Q VCO. All calibration bits are set to 0/1. The simulated tuning range when all bits are 0 is also depicted. (b) Simulated and measured phase noise performance when the control voltage is set to 1.2V and all calibration bits are set to 0. of 0V, and 1.4GHz at a control-voltage value of 1.2V. It is found that this discrepancy corresponds to an increase in the capacitance of the VCO's tuned loads by approximately 17fF. The simulated and measured phase noise of the VCO for a control-voltage value of 1.2V when all calibration bits are set to 0 are shown in Fig. 5.34(b). The VCO achieves a phase noise performance of -93.7dBc/Hz at a 1MHz oset. Figure 5.35: Simulated I/Q phase dierence as a function of mismatch capacitance. The sensitivity of a coupled I/Q VCO's quadrature phase relationship to process and layout mismatches is an important performance metric. Fig. 5.35 shows the simulated phase dierence across the I and Q outputs as a function of the capacitance mismatch 233 between the two VCOs 11 . The calibration varactors can be used to compensate for upto 15fF of capacitance mismatch. Figure 5.36: (a) Circuit diagram of the TX modulator. (b) Circuit diagram of the analog correlator. Fig. 5.36 illustrates the circuit diagrams of the TX modulator and the analog cor- relator. The TX modulator is a simple hard-switching dierential pair that accepts the rail-to-rail square-wave code from the shift register and produces an output square wave of controllable amplitude. The output amplitude is controlled by setting the bias current. The bias current may be varied in seven linear steps from 1.78mA-10.78mA through the implementation of three controllable binary-weighted current sources in par- allel. This in turn causes the output amplitude of the TX modulator to vary from 90mV to 550mV, which serves to provide approximately 16dB of transmit power control per code. Common-mode feedback is employed to maintain a constant output common-mode 11 An extra mismatch capacitance is added in shunt to one of the VCO cores to perform the simulation. All calibration bits are set to 0. 234 level across the various bias currents. The analog correlator is a doubly-balanced current- commutating mixer with the commutating transistors being driven by the square-wave code sequence provided by the shift registers. Each correlator consumes 530A and em- ploys shunt switches at its output to vary the load resistance and hence the voltage gain from 13dB to 4dB. Figure 5.37: Circuit diagram of the analog integrator. Fig. 5.37 illustrates the circuit diagram of the analog integrator. The design consists of a dierential-pair transconductance cell with an active load and an integrating out- put capacitor. Three levels of nMOSes and pMOSes are stacked to increase the output resistance. This reduces the frequency of the dominant output pole and, as a result, in- creases the hold-time of the integrator. A shunt switch is included along with the output capacitor to reset the integrator's output to zero. Table 5.7 summarizes the simulated performance of the experimental prototype. As was mentioned earlier, the measurement of several blocks of the prototype are still ongo- ing, and will be completed shortly. It should be pointed out that the power consumption 235 Table 5.7: Summary of the simulated performance of the implemented 90nm CMOS 24-26GHz RF-multibeam ST-RAKE radar. Implementation Technology 90nm CMOS Die Area 4.2mm 3.4mm Supply Voltage 1.2V RF-Path Performance PA+T/R switch output-referred CP dB 8dBm PA+T/R switch saturated output power > 13.5dBm LNA+T/R switch NF < 5.7dB over 24-26GHz LO-Path Performance Measured I/Q VCO tuning range 5.6% Measured I/Q VCO phase noise at 1MHz oset -93.7dBc/Hz Array Performance Number of beams 4 Number of antenna channels 4 RF-Path Power Consumption PAs 460mA1.2V=288mW LNAs 418mA1.2V=86.4mW LO-Path Power Consumption I/Q VCO and buers 49.4mW Baseband-Path Power Consumption TX modulators 810.75mA1.2V=103.2mW Analog correlators 320.5mA1.2V=19.2mW Integrators 323.08mA1.2V=118.3mW I/Q local LO buers 89mA1.2V=86.4mW Total Power Consumption 751mW of the radar transceiver can be signicantly reduced by switching o the PA and other transmit components during receive mode, and the LNA and other receive components during transmit mode, through the design of fast-power-on, fast-power-o circuits. 5.7 Topics for Future Research The partitioning of signal processing between the analog and digital domains was inves- tigated in this chapter in the context of radar. The analysis of analog correlators that was presented ignored the eect of icker noise. Flicker noise is a serious concern that 236 exacerbates as CMOS technology scales. Therefore, the incorporation of icker noise into the analog-correlator formulation is an important task for the future. The main obstacle for purely digital signal processing, especially in high-bandwidth, high-dynamic-range applications, is the prohibitively-large power consumption of the high-speed ADC that is required. Therefore, application-specic, power-ecient analog- /mixed-signal processing techniques that can be performed prior to conversion to ease the ADC's performance requirements form an interesting research topic for the future. The design of orthogonal codes to be used on the multiple beams in the RF-Multibeam ST-RAKE transceiver architecture is a topic that is beyond the scope of this thesis. It is expected that the experimental prototype described in this chapter will serve as a testbed for dierent code families, and hence will aid future investigations in this direction. The passive RF-multibeam Butler matrix employed in the experimental prototype, despite oering a linearity advantage, is area-hungry and occupies 1.5mm1.5mm of silicon area. Relying purely on quarter-wavelength transmission lines to achieve the required phase shifts, the passive Butler matrix is a poor candidate for CMOS integration. It does not take advantage of the reliable active devices that the process has to oer to enhance performance. A more CMOS-friendly area-ecient multibeam matrix is a worthy topic for future research, as it would signicantly reduce the area of the prototype, and reduce the cost of the radar for commercialization. The timing signals required to switch between transmit and receive modes and select the desired range bin were not implemented in the prototype described in this chapter. It is expected that they will be generated o-chip for future system-level measurements. However, on-chip implementation of the timing circuitry is a worthy topic for future 237 investigation, as these signals have high speed and low jitter requirements due to the wide bandwidth of operation. Reliability is another key concern for the vehicular-radar application space targeted by the prototype. Radar chips mounted on vehicles will experience signicant temparature variations and severe mechanical disturbances. Circuits must be designed to be robust to these variations. In addition, the packaging techniques employed must be able to meet this burden as well. As was discussed earlier in this chapter, it is likely that 32 array elements will be re- quired to meet the beamwidth requirements of vehicular radar. However, the implemen- tation of 32 channels on a single radar chip is challenging and places a large burden on the packaging technology to provide a symmetric interface to the antenna array. Therefore, it is likely that the beamwidth will be achieved through the combination of single-chip sub-arrays of 4-8 elements each. Therefore, it is desirable to investigate techniques by which the prototype described in this chapter can be used as a sub-array within a larger array. It is likely that such techniques will require the use of true time delays between sub-arrays since the delay-phase approximation begins to fail for vehicular-radar speci- cations when the number of elements exceeds 16, as was seen in Chapter 3. It is also likely that the 32 elements will need to be arranged in a two-dimensional conguration to support three-dimensional beam steering. In vehicular radar, re ections o the ground produce strong multipath signals, and vertical selectivity to isolate ground re ections is desirable. 238 5.8 Summary In this chapter, an RF-Multibeam ST-RAKE transceiver architecture was introduced for radar and imaging applications. The architecture has the ability to isolate not only LoS re ections but multipath re ections as well. The collection of additional multipath- re ection information enhances scene reconstruction, as multipath re ections impinge on the desired object(s) from directions other than the LoS. An experimental prototype, operating in the 24-26GHz frequency range and targetting the commercial vehicular-radar application space, was built to verify the principle of operation of the architecture. The design of orthogonal codes that are central to the operation of the RF-Multibeam ST-RAKE transceiver architecture is a topic that is beyond the scope of this thesis. It is expected that the experimental prototype described in this chapter will serve as a testbed for dierent code families, and hence will aid future investigations in this direction. 239 Chapter 6 Conclusions This thesis presented several new architectures and integrated circuits for the realization of multiple-antenna wireless transceivers on silicon-based processes. Multiple-antenna transceivers will play a key role in the success of emerging millimeter-wave commercial applications such as high-speed wireless communication, automotive radar and millimeter- wave imaging. The architectures and circuits presented in this thesis exploit the benets of silicon integration to ease the area and power requirements of multiple-antenna systems and enhance their functionality. 6.1 Summary Passive elements are critical components in virtually every wireless-transceiver building block. At millimeter-wave frequencies, the design of passive elements is beset with sev- eral challenges, but several opportunities present themselves as well. Distributed passive components, such as transmission lines, become viable design components. This thesis presented a comparative study of dierent on-chip transmission-line structures. A com- plementary, current-sharing oscillator topology was introduced that employs a high-Q 240 coplanar-stripline-based resonator to achieve a low phase-noise performance. A prototype 26GHz oscillator was implemented in a 0.18m CMOS process and achieved a state-of- the-art phase-noise performance of -110dBc/Hz at 1MHz oset. The use of transformers to enhance resonatorQ over resonators based on single spiral inductors was investigated. Through theoretical analysis and experiments on 5GHz integrated-oscillator prototypes, it was determined that transformer-based resonators oer no Q improvement over res- onators based on single spirals when subjected to the same area and eective-inductance constraint. A formulation that captures the impact of passive-element loss on the noise gure (NF ) of low-noise ampliers was also developed. The formulation led to the pro- posal of a new minimum-NF metric,NF min;p , that captures the quality of the active and passive devices available in the process. A 0.13m SiGe E-band low-noise amplier was implemented to support the formulation. Phased arrays are a special class of multiple-antenna systems that employ a linear phase progression across multiple antennas to form an electronically-steerable directional beam. An overview of conventional phased-array architectures was presented. A Variable- Phase Ring Oscillator and Phase-Locked Loop (VPRO-PLL) architecture for integrated phased-array transceivers was then developed. The architecture is essentially a multi- functional nonlinear circuit that exploits the injection-pulling properties of a tuned ring oscillator locked in a PLL to achieve full phased-array functionality. By eliminating sev- eral key phased-array building blocks, such as phase shifters, mixers and power splitters, the architecture reduces the area and power consumption when compared to conven- tional architectures. A theoretical analysis of performance metrics, such as sensitivity, linearity and the performance in the presence of process mismatches, was presented. A 241 highly-integrated, 4-channel, 24GHz, 0.13m CMOS phased-array-transceiver prototype was implemented and veries the principle of operation of the architecture and the the- oretical analyses of performance metrics. A second, 4-channel, UWB, 0.13m CMOS phased-array-transmitter prototype was also implemented. The second prototype also operates in the vicinity of 24GHz and enhances the VPRO-PLL architecture to enable UWB modulation capability. The second prototype also employs a waveform-adaptive, tunable-narrowband design paradigm which allows it to extract UWB behavior from inherently tunable-narrowband building blocks. The VPRO-PLL architecture demon- strates that nonlinear multifunctional circuits uniquely enabled by CMOS integration can be exploited to increase functionality and reduce the area and power consumption when compared with conventional architectures. Multipath interference often limits the performance of wireless-communication sys- tems. However, through the use of multiple-antenna systems, the channel capacity of a multipath-rich environment can be signicantly enhanced. Similarly, in radar applica- tions, multipaths can be harnessed to gather more information about the desired targets. An RF-Multibeam Spatio-Temporal RAKE architecture was introduced that exploits multiple-antenna techniques developed for communication systems in the realm of radar. The architecture uses an RF-multibeam spatial lter in conjunction with orthogonal code signals to isolate Line-of-Sight (LoS) re ections from multipath echos. Multibeam transceivers require a baseband processor for each beam, and as the application bandwidth increases, the power consumption of these baseband processors follows suit. Therefore, the tradeos between analog and digital baseband processing for radar were analyzed. It was determined that, from a power perspective, digital signal processing is limited by the 242 prohibitively-large power consumption of the high-speed ADC that is required. Therefore, some degree of analog baseband processing is preferred to ease the ADC's performance requirements. A RF-Multibeam ST-RAKE prototype, operating in the 24-26GHz range and targeting automotive-radar applications, was implemented in a 90nm CMOS process to validate the principle of operation of the architecture. 6.2 Topics for Future Research The investigations that have formed this thesis have opened up several topics for future research. These topics are listed here brie y. A more detailed description may be found in the individual chapters. In the context of passive components on silicon-based processes, it is hypothesized that there exists a fundamental limit on the achievableQ of a resonator given the process parameters, such as the interconnect stack. The investigation of such a limit would not only be useful as an upper bound on performance, but may shed light on new passive structures that outperform those that are currently used. The degradation of resonator Q due to the loss of the active devices employed in an integrated oscillator is another open problem that is particularly relevant for oscillators that function near thef max of the process technology. The development of a formulation for the loaded Q of a resonator is likely to be dependent on the oscillator topology, and hence may reveal topologies that are suitable for near-f max operation. 243 There are several unsolved problems in the VPRO-PLL phased-array architecture as well. The VPRO is capable of multiple modes of oscillation, and techniques for prefer- ential selection of the desired mode are yet to be determined. The architecture currently supports only linear phase progressions for phased-array operation. Support for arbitary phases in each channel is desirable. Techniques to accomplish this have been proposed but must be investigated in greater depth. The extension of the VPRO-PLL architecture to two-dimensional phased arrays has been proposed as well. The incorporation of I/Q capability in the transceiver and amplitude-modulation capability in the transmitter also remain open for the future. With respect to the RF-Multibeam ST-RAKE transceiver architecture, the design of the orthogonal codes to be used on the multiple beams is a topic that was beyond the scope of this thesis. It is expected that the experimental prototype described in this thesis will serve as a testbed that will aid future investigations in this direction. The analysis of the tradeos between analog and digital signal processing for radar ig- nored the eects of icker noise, which is a serious challenge, especially in deep-submicron CMOS. The incorporation of icker noise into the formulation must be accomplished in the future. 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[133] Tsung-Yu Yang and Hwann-Kaeo Chiou, \A 28 GHz sub-harmonic mixer using LO doubler in 0.18-m CMOS technology," in 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Technical Papers, June 2006, pp. 3754-3757. [134] S.-H. Yen and C.-K. Wang, \A 2 V CMOS programmable pipelined digital dif- ferential matched lter for DS-CDMA system," in Proceedings of the First IEEE Asia-Pacic Conference on ASICs, pp. 403-404, August 1999. [135] R. A. York, \Nonlinear analysis of phase relationships in quasi-optical oscillator arrays," IEEE Transactions on Microwave Theory and Techniques, vol. 41, no. 10, pp. 1799-1809, Oct. 1993. 256 [136] Tiku Yu, G. M. Rebeiz, \A 24 GHz 4-channel phased-array receiver in 0.13 m CMOS," in 2008 IEEE Radio Frequency Integrated Circuits Symposium Digest of Technical Papers, pp. 361-364, June 2008. [137] C. P. Yue and S. S. Wong, \Physical modeling of spiral inductors on silicon," IEEE Transactions on Electron Devices, vol. 47, no. 3, pp. 560-568, March 2000. [138] H. Zarei and D. J. Allstot, \A low-loss phase shifter in 180 nm CMOS for multiple- antenna receivers," in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 392-534, Feb. 2004. 257 Appendix Characterization of Process Technologies Used This appendix contains a characterization of the various process technologies used in this thesis. These characterizations are based on simulations of the models provided in the process design kits. A.1 IBM's 8HP 0.13m SiGe BiCMOS IBM's 8HP technology features SiGe BiCMOS HBT transistors with a minimum drawn channel width of 0.12m. CMOS transistors with a minimum channel length of 0.12m are also available. However, RF layouts and models for these CMOS transistors are not provided. Fig. A.1 depicts the small-signal transconductance and input capacitance looking into the base for HBTs of varying emitter lengths and bias currents. These are determined in simulation by using a current source in the emitter to bias the device and bypassing the current source with a large capacitor. The base is biased at 1V and the collector at 1.8V. The base capacitance is determined from the input impedance looking into the base and therefore includes bothC andC . The simulatedg m requires correction for the emitter 258 Figure A.1: (a)g m for dierent emitter length and bias current values. (b)C b for dierent emitter length and bias current values. Figure A.2: Parasitic emitter, base and collector resistances (r e , r b and r c ) as a function of the emitter length. contact resistance (r e ), which is characterized shortly. Both g m and C b increases almost linearly with current, which is expected for HBT devices. In the case of C b , there is a constant overlap capacitance in addition to the component that is proportional to the bias current. This overlap capacitance is larger for larger emitter lengths. Fig. A.2 depicts the parasitic emitter, base and collector resistances as a function of the emitter length. As the emitter length increases, these parasitic resistances decrease. 259 Figure A.3: (a) f max for dierent emitter length and bias current values. (b) NF min for dierent emitter lengths. The bias current is 3mA for an emitter length of 2.5m, 10mA for 7.5m and 20mA for 15m. These bias currents maximize the f max for each emitter length. Fig. A.3(a) depicts the maximum oscillation frequency, f max , as a function of the emitter length and bias current. For each emitter length, there is a bias current that maximizesf max . It is interesting to note that this bias current is proportional to emitter length. Fig. A.3(b) shows theNF min as a function of emitter length. The bias current in each case is chosen to maximize f max , and is 3mA for an emitter length of 2.5m, 10mA for 7.5m and 20mA for 15m. The metallization stack is depicted in Fig. A.4 and features a 4m-thick upper metal layer for high-quality inductors and transmission lines. Fig. A.5 presents a characteri- zation of a few 8HP CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, AM, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. AsS increases, the inductance per unit length (L) increases due to the increased area between the conductors for magnetic ux linkage. Therefore, Z 0 increases as well. As W increases, the dominant eect is the 260 Figure A.4: Metallization stack of 8HP. Metal layers M1 through MQ are copper. LY and AM are aluminium. increase in the capacitance per unit length of the line (C), which causes a reduction in Z 0 . The wavelength of the transmission line () decreases with an increase in either W orS due to the increase in theLC product. For lines with smallW andS, the losses are mostly caused by the series resistance of the CPS lines. An increase in W improves the Q due to a reduction of the series resistance. An increase in S produces in improvement in theQ due to reduced proximity eects. However, for wider lines, the losses are mostly shunt substrate losses. An increase in either W or S exacerbates these shunt substrate losses and degrades Q. A.2 IBM's 8RF 0.13m CMOS IBM's 8RF technology features CMOS transistors with a minimum drawn channel length of 0.12m. This technology is oered in two avors - LM and DM. While both versions 261 Figure A.5: Characteristics of a few 8HP CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, AM, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. (a) Characteristic impedance (Z 0 ). (b) Q of a quarter-wavelength CPS resonator, computed as 2 . (c) Attenuation constant (). (d) Wavelength (). feature the same active devices, the back end of the line (BEOL) is dierent. DM oers several thick analog metal layers that may be used to realize high-quality inductors and transmission lines (Fig. A.6). Fig. A.7 depicts a DC characterization of a 1000.48m/120n IBM 8RF nFET. V gs and V ds are concurrently swept from 0 to 1.5V. The drain current (I ds ) is plotted versus V ds . The transconductance g m as a function of V gs is also depicted. It can be seen that forV gs >1V,g m no longer increases with an increase inV gs , which is indicative of velocity saturation. The velocity-saturated transconductance per unit gate width, gm;sat W , for this technology is approximately 0.65mS/m. 262 Figure A.6: Metallization stacks for the DM and LM avors of 8RF. All metal layers are copper, except for MA, which is aluminium. Fig. A.8(a) shows the gate resistance (r g ) and capacitance (C g ) of an 8RF nFET as the number of ngers (nf) of the device is increased. The total width is maintained constant at 48m. Fornf > 12,r g no longer improves with an increase in the number of ngers due to the resistance of the horizontal lines that connect the ngers together. C g remains roughly constant with nf and is only dependent on the total width. It should be noted that these graphs are generated by determining the input impedance looking into the gate when the source and drain terminals are at AC ground. Therefore, C g is essentially a sum ofC gs , the gate-source capacitance, andC gd , the gate-drain capacitance. The gate capacitance per unit gate width, Cg W , for this technology is 1.3fF/m. The velocity-saturated transconductance per unit gate capacitance gm;sat Cg for this technology is approximately 0.5mS/fF. This is also equal to the technology's unity current-gain frequency ! T . f T therefore is 79.6GHz. 263 Figure A.7: (a) Drain current versus V ds for a 1000.48m/120n IBM 8RF nFET for dierent V gs values. (b) g m versus V gs for a 1000.48m/120n IBM 8RF nFET for dierent V ds values. Figure A.8: (a) Gate capacitance and gate resistance for dierent number of ngers. The total width is kept constant at 48m. (b) Maximum oscillation frequency (f max ) as function of the device bias current and the device aspect ratio. The total device width is kept constant at 48m. Fig. A.8(b) represents f max as a function of the bias current and the aspect ratio of the device. f max is determined through small-signal S-parameter simulations of the device, and is the frequency at which the Maximum Available Gain (MAG) from the device becomes unity. The total gate width is 48m. The bias current is varied by keeping V ds =1.5V and varying V gs . f max is seen to improve with the bias current and with an increase in the number of ngers due to the reducing gate resistance. 264 Figure A.9: (a) Drain-current thermal noise as a function of the device bias point for a 1000.48m/120n nFET. (b) Device excess noise factor ( ) as a function of V gs for a 1000.48m/120n nFET with V ds =1.2V. A noise characterization of the process is also performed. The noise characterization is restricted to drain-current thermal noise - icker noise is ignored. Fig. A.9(a) shows the drain-current thermal noise PSD of a 1000.48m/120n nFET as V gs and V ds are varied. There is a strong dependence onV gs , while the variation withV ds is weak. Hence, for analysis purposes, a piecewise-linear t with respect to V gs may be employed. The piecewise-linear t is I 2 dn f = 0 A 2 =Hz for V gs < 0:4; = 20 10 22 (V gs 0:4) A 2 =Hz for 0:68>V gs > 0:4; = 12 10 22 (V gs 0:4) + 5:2 10 22 A 2 =Hz for V gs > 0:68: (A.1) 265 Figure A.10: Characteristics of a few 8RF-LM CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, LM, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. (a) Characteristic impedance (Z 0 ). (b)Q of a quarter-wavelength CPS resonator, computed as 2 . (c) Attenuation constant (). (d) Wavelength (). The drain-current thermal noise for devices of other sizes may be obtained by scaling the piecewise-linear formula accordingly. The drain-current thermal noise prole as a function of V gs shows a strong correlation to the g m prole, hinting at a 4kT g m model for its PSD, where is the device excess noise factor. The simulated drain-current thermal noise PSD for V ds =1.2V is divided by 4kTg m to obtain . is typically equal to 2/3 for long-channel devices and is known to increase to 3 for deep-submicron process. Fig. A.9(b) shows the simulated versus V gs based on the 8RF design-kit models. Fig. A.10 presents a characterization of a few CPS structures in the LM metallization stack with dierent widths (W ) and spacings (S). The CPS is formed in the top metal 266 layer, LM, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. The trends are similar to those described for 8HP CPS structures in Appendix A.1. However, the Q values are lower due to the fact that LM is considerably thinner than the 4m-thick top metal layer available in 8HP. There is also unexplained behavior in Z 0 , and Q for the W = 10m, S = 30m CPS. Z 0 and are unusually high, and correspondingly, Q is rather low. A characterization of CPS structures in the DM metallization stack is not provided, as it is quite similar to the 8HP stack. Therefore, CPS performance is expected to be similar as well. A.3 IBM's 9RF-LP 90nm CMOS IBM's 9RF-LP technology features CMOS transistors with a minimum drawn channel length of 0.10m. Fig. A.11 depicts a DC characterization of a 1000.36m/100n IBM 9RF-LP nFET. V gs and V ds are concurrently swept from 0 to 1.2V. The drain current (I ds ) is plotted versusV ds . The transconductanceg m as a function ofV gs is also depicted. The velocity-saturated transconductance per unit gate width, gm;sat W , for this technology is approximately 1mS/m. Fig. A.12(a) shows the gate resistance (r g ) and capacitance (C g ) of a 9RF-LP nFET as the number of ngers (nf) of the device is increased. The total width is maintained constant at 36m. As was the case for 8RF, for nf > 20, r g no longer improves with an increase in the number of ngers. C g shows a signicant variation with nf although the total width is kept constant. This indicates that overlap capacitance is larger contributor to the total capacitance in 9RF-LP than in 8RF. Using a mean value of 40fF from Fig. 267 Figure A.11: (a) Drain current versus V ds for a 1000.36m/100n IBM 9RF-LP nFET for dierent V gs values. (b) g m versus V gs for a 1000.36m/100n IBM 9RF-LP nFET for dierent V ds values. Figure A.12: (a) Gate capacitance and gate resistance for dierent number of ngers. The total width is kept constant at 36m. (b) Maximum oscillation frequency (f max ) as function of the device bias current and the device aspect ratio. The total device width is kept constant at 36m. A.12(a), the gate capacitance per unit gate width, Cg W , is determined to be 1.1fF/m. The velocity-saturated transconductance per unit gate capacitance, gm;sat Cg , for this technology is then 0.9mS/fF. f T therefore is 143.2GHz. Fig. A.12(b) represents f max as a function of the bias current and the aspect ratio of the device. The total gate width is 36m. The bias current is varied by keeping V ds =1.2V and varying V gs . f max is seen to improve with the bias current. With respect to the number of ngers, there seems to be an optimum aspect ratio that maximizesf max . 268 Figure A.13: Minimum noise gure (NF min ) for a 500.72m/100n 9RF-LP nFET for dierent bias currents. V ds =1.2V and V gs is varied to achieve the bias currents. This is likely because a further increase in the number of ngers beyond the optimum point does not improve r g but increases C g due to the increased overlap capacitance. Fig. A.13 depicts the minimum noise gure (NF min ) for a 500.72m/100n 9RF-LP nFET for dierent bias currents. In the 20-30GHz frequency range, NF min is seen to range from 0.35dB to 0.62dB. Fig. A.14 depicts the metallization stack that is available in IBM's 9RF-LP process. Fig. A.15 presents a characterization of a few CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, LB, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. Once again, the trends are similar to those described for 8HP CPS structures in Appendix A.1. TheQ values are lower those achieved in the 8HP metallization stack, and are similar to those obtained in the 8RF-LM stack. There is unexplained behavior in Z 0 , and Q for the W = 10m, S = 30m CPS in 9RF-LP as well. Z 0 and are unusually high, and correspondingly, Q is rather low. 269 Figure A.14: Metallization stack for 9RF-LP. All metal layers are copper. Figure A.15: Characteristics of a few 9RF-LP CPS structures with dierent widths (W ) and spacings (S). The CPS is formed in the top metal layer, LB, and shielding metal strips of width 5m and spacing 5m are included in M1, the rst metal layer. (a) Characteristic impedance (Z 0 ). (b)Q of a quarter-wavelength CPS resonator, computed as 2 . (c) Attenuation constant (). (d) Wavelength (). 270

Abstract (if available)

Abstract This thesis presents unique architectures for the implementation of multiple-antenna systems at millimeter-wave frequencies on silicon-based processes.

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Creator Krishnaswamy, Harish (author)

Core Title Architectures and integrated circuits for RF and mm-wave multiple-antenna systems on silicon

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 11/04/2009

Defense Date 01/26/2009

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag CMOS,millimeter-wave,MIMO,multiple-antenna transceivers,OAI-PMH Harvest,oscillators,phased arrays,RF,silicon,wireless

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Hashemi, Hossein (committee chair), Haas, Stephan (committee member), Levi, Anthony F. J. (committee member), Prata, Aluizio, Jr. (committee member)

Creator Email hk2532@columbia.edu,hkrishna@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-m2164

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