Close
About
FAQ
Home
Collections
Login
USC Login
Register
0
Selected
Invert selection
Deselect all
Deselect all
Click here to refresh results
Click here to refresh results
USC
/
Digital Library
/
University of Southern California Dissertations and Theses
/
Testing for crosstalk- and bridge-induced delay faults
(USC Thesis Other)
Testing for crosstalk- and bridge-induced delay faults
PDF
Download
Share
Open document
Flip pages
Contact Us
Contact Us
Copy asset link
Request this asset
Transcript (if available)
Content
TESTING FOR CROSSTALK- AND BRIDGE-INDUCED DELAY FAULTS by Shahdad Irajpour _____________________________________________________________ A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2007 Copyright 2007 Shahdad Irajpour ii Dedication To my father, mother and brother iii Acknowledgments I would like to thank Professors Sandeep K. Gupta and Melvin A. Breuer for their supervision, guidance and support throughout this endeavor. I would like to thank my dear mom, Shahla Ravanpour, my dear dad, Manouchehr Irajpour, and my dear brother, Shahram Irajpour, for their love and support without which the completion of this work would not have been possible. My parents sacrificed their life to provide me with a comfortable and peaceful living environment and the opportunity to pursue higher education. My brother has always been an impeccable mentor for me throughout my life. His advice has always helped me choose the right path at different stages of my life. Whatever I have achieved, I owe it to my family and I hereby thank them. I would also like to thank those caring friends who nourished me with their love and encouragement in the past six years. You know who you are and I hereby thank you. I wish to thank my colleagues, I-De Huang and Shideh Shahidi, for their friendship and help during our time at USC. I have many pleasant memories with them that I will always cherish. I also wish to thank Liang-Chi Chen for his help during my first two years at USC. I took advice from Professors Massoud Pedram and Alice Parker in various occasions during my education at USC for which I am also very thankful. iv Table of Contents Dedication ii Acknowledgments iii List of Tables viii List of Figures ix Abstract xiii Chapter 1 Introduction 1.1 Delay testing 1.1.1 Gate delay fault 1.1.2 Path delay fault 1.1.2.1 Functional sensitization test for a logical path 1.1.2.2 Robust test for a logical path 1.1.3 Delay testing using tests for logical paths 1.2 Crosstalk-induced delay 1.2.1 Timing verification in the presence of crosstalk 1.2.2 Testing for crosstalk-induced delay faults 1.3 Bridge-induced slow-down 1.4 Technology trends and the purpose of this dissertation 1.5 Review of related work 1.6 Overview of the dissertation Chapter 2 Testing for crosstalk-induced delay faults 2.1 Introduction 2.2 Test generation methodology for crosstalk slow-down targets 2.2.1 Terminology 2.2.2 Surrogate 2.2.3 Top-down overview of testing for crosstalk-induced delay faults 2.2.4 FS-test for a surrogate 2.2.5 Restricted-robust test for a surrogate 2.2.6 Testing for crosstalk-induced delay faults using tests for the corresponding surrogates 2.3 Test pattern generation 2.3.1 Value system 2.3.2 Overview of test generation core 2.4 Experimental results 2.4.1 Run time 2.5 Conclusions 1 3 5 6 9 11 12 13 14 16 17 19 21 23 25 25 27 27 30 34 35 37 39 41 41 42 43 45 45 v Chapter 3 Testing for WRB-induced delay faults 3.1 Introduction 3.2 Test generation methodology for WRB slow-down targets 3.2.1 Terminology 3.2.2 Macro-surrogate 3.2.3 Surrogates corresponding a macro-surrogate 3.2.4 FS-test for a macro-surrogate 3.2.5 Robust-plus test for a macro-surrogate 3.2.6 FS-test and RR-test for a surrogate 3.2.7 Testing for WRB-induced delay faults using tests for the corresponding macro-surrogates 3.2.7.1 Least-restricted test for a macro-surrogate 3.3 Test pattern generation 3.4 Experimental Results 3.5 Conclusions Chapter 4 Testing for crosstalk- and WRB-induced delay faults under constrained gate delay fault assumptions 4.1 Introduction 4.2 Correlated process variations 4.2.1 Comparing delays of surrogates and macro-surrogates with t S or with each other 4.2.2 Non-criticality 4.2.2.1 Crosstalk sites 4.2.2.1.1 Non-critical situations 4.2.2.2 WRB sites 4.2.2.2.1 Non-critical situations 4.2.3 Delay-inferiority; delay-superiority 4.2.3.1 Delay-superior situations for surrogates 4.2.3.2 Delay-superior situations for macro-surrogates 4.2.4 Signals implied at circuit lines 4.2.5 Relaxed tests for surrogates and macro-surrogates 4.2.5.1 R-test 4.2.5.2 Relaxed R-test 4.2.5.3 RR-test 4.2.5.4 Relaxed RR-test 4.2.5.5 R + -test 4.2.5.6 Relaxed R + -test 4.2.6 Relaxed RR- and R + -test generation 4.2.6.1 Simulation 4.2.6.1.1 Simulation under single-uncertain-interval simplification 4.2.6.2 Effects of crosstalk- and WRB-induced delay faults 48 48 50 50 51 52 54 55 56 56 58 60 61 62 64 64 70 71 73 73 75 76 77 79 80 84 85 88 91 93 96 100 106 107 109 110 116 118 vi 4.2.6.3 Checking test requirements 4.2.6.4 Search process 4.3 Single gate delay fault 4.3.1 Delays of surrogates 4.3.2 Surrogate-gate pairs 4.3.3 Comparing delays of surrogates with t S or with each other 4.3.4 Non-criticality 4.3.5 Delay-superiority 4.3.6 Relaxed RR-test for a surrogate-gate pair 4.3.7 Relaxed RR-test generation 4.4 Bounded maximum extra delay 4.5 Implementations 4.5.1 Test generation framework for crosstalk-induced delay faults under the SGDF 4.5.1.1 Flow of test generation framework 4.5.1.2 Experimental results 4.5.1.3 Conclusion, notes and future work 4.5.2 Procedure for generating relaxed R + -tests under the BMD 4.5.2.1 Experimental results 4.5.2.2 Conclusion, notes and future work References Appendices Appendix A: Preliminaries A.1 Pin-to-pin delay model A.1.1 Underlying assumptions A.1.2 Implications A.1.2.1 Intervals at virtual delayed points A.1.2.2 Processing intervals through gates A.2 Signals implied at circuit lines under two-pattern input sequences A.3 CTE of FS-untestable logical paths Appendix B: Delay testing using tests for logical paths Appendix C: Testing for crosstalk-induced delay faults C.1 Crosstalk-induced ∆-delay; crosstalk-induced slow-down; crosstalk-induced speed-up C.2 Proofs for theorems presented in Chapter 2 Appendix D: Testing for WRB-induced delay faults 120 121 121 122 123 126 128 129 131 132 133 135 136 140 144 146 148 153 154 156 161 161 161 161 162 162 164 166 175 180 186 186 193 198 vii D.1 WRB-induced ∆-delay; WRB-induced slow-down; WRB- induced speed-up D.2 Proofs for theorems presented in Chapter 3 Appendix E: Supplementary material related to Chapter 4 E.1 Calculating upper-bound and lower-bound for sd C E.2 Calculating upper-bound and lower-bound for ∆ WRB E.3 Situations where a surrogate-gate pair is delay-superior to another surrogate-gate pair 198 206 214 214 220 223 viii List of Tables Table 2-1. Composite values and the basic values that they contain. Table 2-2. Specifications of the circuits under study. Table 2-3. Coverage. Table 2-4. Run times of RR-test generation for old and new approaches. Table 3-1. Coverage. Table 4-1. S-coverage of the surrogates. Table 4-2. Coverage. 42 43 44 45 62 145 154 ix List of Figures Figure 1-1. Flow charts of design and testing. Figure 1-2. An example used to demonstrate that path delay faults on logical paths might cause timing errors in circuits. (a): The example circuit. (b): Timing error occurs under T 1 . (c): No timing error occurs under T 2 . Figure 1-3. Functional sensitization requirements for a 2-input on- path NAND gate. (a): i has 0-to-1 logical direction, (b): i has 1-to-0 logical direction. Figure 1-4. An FS-test for P R , where P = (a, g 1 , b, g 2 , c, g 3 , d, g 4 , e). Figure 1-5. Robust requirements for a 2-input on-path NAND gate. (a): i has 0-to-1 logical direction, (b): i has 1-to-0 logical direction. Figure 1-6. Crosstalk-induced slow-down. Figure 1-7. Crosstalk-induced speed-up. Figure 1-8. WRB-induced slow-down and speed-up when S x and S y are clean transitions. Figure 2-1. An example illustrating a crosstalk site and three corresponding IX-, IY-, and YO-sub-paths. Figure 2-2. An example illustrating that surrogate delay faults might cause timing errors. (a) The example circuit. (b): If coupling did not exist, no timing error would occur under T 1 . (c): In the presence of the coupling, timing error occurs under T 1 . Figure 2-3. An example demonstrating that an FS-test for a surrogate is not a detecting-test for the surrogate. Figure 2-4. R-robust requirements for a 2-input on-IX-sub-path NAND gate. (a): a has 0-to-1 logical IX-direction, (b): a has 1-to-0 logical IX-direction. Figure 2-5. The general flow of the two approaches used for generating tests for surrogates. 1 8 9 11 11 13 14 18 29 33 37 38 47 x Figure 3-1. An example illustrating a WRB site and three corresponding IX-, IY-, and YO-sub-paths. Figure 4-1. An example. Figure 4-2. S c in five different fabricated copies of the circuit. Figure 4-3. S c in five different fabricated copies of the circuit. Figure 4-4. Illustration of an uncertain interval. Figure 4-5. A rising transition under the MGDF. Figure 4-6. Signals implied at inputs and output of a 2-input on-IY- sub-path NAND gate g with on-sub-path input a, off- sub-path input b and output c. Figure 4-7. Examples of signals at an on-path line under an R-test under a constrained gate delay fault assumption. (a): On-path line has 0-to-1 logical direction. (b): On-path line has 1-to-0 logical direction. Figure 4-8. Robust requirements for an example 2-input on-path NAND gate with on-path input a, off-path input b and output c. (a): a has 0-to-1 logical direction. (b): a has 1-to-0 logical direction. Figure 4-9. Waveforms under (a) T 1 , and (b) T 2 . Figure 4-10. Examples of signals at an on-IX-sub-path line under an RR-test under a constrained gate delay fault assumption. (a): On-sub-path line has 0-to-1 logical IX-direction. (b): On-sub-path line has 1-to-0 logical IX-direction. Figure 4-11. R-robust requirements for an example 2-input on-IX- sub-path NAND gate with on-sub-path input a, off- sub-path input b and output c. (a): a has 0-to-1 logical IX-direction. (b): a has 1-to-0 logical IX-direction. Figure 4-12. Waveforms for an example situation under (a) T 1 , and (b) T 2 . 51 85 86 87 88 88 90 92 92 94 99 99 102 xi Figure 4-13. Waveforms for an example situation under (a) T 1 , and (b) T 2 . Figure 4-14. S a' and S b' . Figure 4-15. The resulting S c . Figure 4-16. S a' and S b' . Figure 4-17. The resulting S c . Figure 4-18. Examples of partially specified signals at circuit inputs. Figure 4-19. An example signal and its representation under the SUI simplification. Figure 4-20. Relaxed r-robust off-sub-path requirement. Figure 4-21. Relaxed r-robust off-sub-path requirement under the SUI simplification. Figure 4-22. Relaxed affecting signal requirement. Figure 4-23. Relaxed affecting signal requirement under the SUI simplification. Figure 4-24. An example demonstrating how the effect of crosstalk-induced delay fault is considered during simulation, under the CPV. Figure 4-25. An example surrogate and the seven corresponding surrogate-gate pairs. Figure 4-26. An example surrogate with on-IX-sub-path gate g. Figure 4-27. Maximum crosstalk-induced slow-down. Figure 4-28. S 1 , S 2 , and g, the location of the gate delay fault. Figure 4-29. Maximum crosstalk-induced slow-down. Figure 4-30. Correspondence of minimum and maximum arrival times with EII and BFI. 108 112 113 114 115 115 116 117 117 118 118 119 124 126 127 127 128 137 xii Figure 4-31. Flow of our test generation framework. Figure 4-32. Gates that belong to each G S i , i = 1, …, or 4, and the status of the surrogate-gate pairs. Figure 4-33. Comparison of the coverage of crosstalk sites under the MGDF and SGDF. Figure 4-34. Arrival times under the BMD in terms of those under the nominal condition. Figure 4-35. AFAS requirements for a 2-input on-IX-sub-path NAND gate. (a): a has 1-to-0 logical IX-direction, (b): a has 0-to-1 logical IX-direction. Figure 4-36. AIAS requirements for a 2-input on-IX-sub-path NAND gate. (a): a has 1-to-0 logical IX-direction, (b): a has 0-to-1 logical IX-direction. 140 141 146 149 151 153 xiii Abstract Process technology advancements are increasing coupling capacitance values and the resulting crosstalk-induced delay. As a result, noise and timing margins are decreasing and circuits’ susceptibility to defects is increasing. The population of defects is also changing and the influence of fluctuations of process parameters during manufacturing is becoming more and more important due to process technology advancements. Due to the above mentioned reasons, crosstalk-induced delay must not only be considered in timing verification but it must also be considered in post-fabrication testing together with realistic populations of manufacturing imperfections and process variations. This dissertation focuses on testing for crosstalk-induced delay faults in the presence of delay faults caused by defects and process variations. Furthermore, with bridges being the predominant type of manufacturing defects in new technologies, this dissertation also focuses on testing for bridge-induced delay faults in the presence of other delay faults. In the presence of delay faults at unknown locations and of unknown sizes, nominal timing information is not valid. We present timing-independent approaches for testing for crosstalk- and bridge-induced delay faults. Using these approaches, under certain circumstances, tests are generated that guarantee testing for crosstalk- or bridge-induced delay faults. No existing approach generates tests that can provide such a guarantee. xiv Certain assumptions about the nature of defects and process variations and the resulting delay faults can be exploited in the test methodology that result in higher coverage of crosstalk or bridge sites and also lower test generation and test application costs. These assumptions and their ramifications are also discussed. 1 Chapter 1 Introduction Figure 1-1 shows simplified flow charts of design and testing for digital sequential circuits. Original specification Design Logic verification Preliminary timing verification Layout design No Yes No Yes Post-layout timing verification Tapeout Logic behavior as desired? Temporal behavior as desired? Temporal behavior as desired? No Yes Tapeout Fabrication Logic testing Logic error observed? Delay testing Timing error observed? Discard Discard Yes Yes No No Send to market Design Testing Figure 1-1. Flow charts of design and testing. A sequential circuit is designed with the objective of having a certain functionality. Logic verification [16] is then undertaken to verify that the designed circuit meets the original specification as far as logic behavior is concerned. If the behavior is not as desired, the design step is revisited. 2 Subsequently, the correct temporal behavior of the designed circuit is also verified. This is done through preliminary timing verification [16][43]. If the behavior is not as desired, it is rectified via redesign. Every fabricated copy of the designed circuit will contain parasitics such as capacitive couplings between patterns of metal, resistances or inductances of patterns of metal, etc. Therefore, after layout, such parasitics are modeled and correctness of the temporal behavior of the designed circuit is re-verified in the presence of parasitics. This is done through post-layout timing verification [43]. If the behavior is not as it is desired, either the layout is modified or redesign is undertaken. When the designed circuit is fabricated, due to defects (physical imperfections in fabricated dies are called manufacturing defects or defects for short) and/or process variations (variations in the manufacturing process), faults might exist in a fabricated circuit [27]. (When an electrical property is different from what is expected, a fault is said to exist.) Faults might cause errors in the circuit [27]. (Behavior at an observable point that is different from what is expected is called an error.) Therefore, before sending any fabricated copy of the circuit to the market, it must be verified that the circuit copy operates error-free. This is done through testing. In the process of testing a fabricated circuit, stimuli, referred to as tests, are applied to the circuit. Under a test, if one or more errors are observed, it is said that the circuit has failed the test. However, if no error is observed, it is said that the circuit has passed the test. If the fabricated circuit fails even one test, it is discarded. However, if the fabricated circuit passes all the tests, it is conjectured that it would operate error-free under all possible stimuli. Whether or not this conjecture is valid depends on the nature 3 of the tests used. Tests must be chosen as stimuli that make any fault that might possibly exist in fabricated circuits cause errors (provided that the fault can actually cause errors). The process of searching for tests is called test generation [27]. In logic testing the circuit is tested for logic errors while in delay testing [27][28] the circuit is tested for timing errors. Delay testing is done after a fabricated circuit passes logic testing. In the rest of this chapter some introductory material about delay testing is presented first. Crosstalk-induced and bridge-induced delay effects and the associated verification and testing problems are discussed next. Technology trends and the purpose of this dissertation are explained and the related previous work is reviewed. Finally, the overview of this dissertation is presented. 1.1 Delay testing In order to facilitate delay testing, it is a common practice to use full enhanced [15] scan [61][17] in sequential circuits. In such circuits, for the purpose of delay testing, only the combinational logic blocks that reside between flip-flops are considered and it is investigated whether such blocks propagate transitions from their inputs to their outputs within a specified amount of time referred to as the sampling time [27][28][15][61][17]. (All through this dissertation, sampling time is denoted by t S .) In this dissertation, we only consider circuits that have full enhanced scan and by “circuit”, we mean a combinational block that resides between flip-flops. 4 Due to defects and/or process variations, delay faults might exist in a fabricated circuit. (When the propagation delay between two nodes in a circuit is different from the expected value, a delay fault is said to exist [27][28].) Most delay faults of interest slow the propagation of transitions. Therefore, a delay test 1 must excite transitions that are delayed by delay faults and propagate the effects to circuit outputs. Hence, a delay test must be a two-pattern sequence <P i , P t > [27][28]. The first pattern, P i , is called the initialization pattern, and the second pattern, P t , is called the test pattern. P i and P t are applied to the circuit at t = t i and t = t t , respectively, where t t > t i [27][28]. It is a common practice to use the slow-fast test application scheme [27][28], where t t – t i is long enough to let the circuit lines reach their steady-state values under P i even in the presence of likely delay faults. For each circuit line l in the circuit, IV(l), initial value at line l, is defined as the steady-state logic value of l under P i . Similarly, FV(l), final value at line l, is defined as the steady-state logic value of l under P t . In this dissertation, we assume that the slow-fast test application scheme is used. In all the future discussions, we consider t t as the time reference, i.e., t t = 0. Under a two-pattern input sequence, if the signal at a circuit output at t = t S is different from its final value, it means that at least one transition does not arrive at the output before t = t S . This is regarded as an error and is referred to as a timing error. 1 In the context of delay testing, tests are referred to as “delay tests”. 5 1.1.1 Gate delay fault Under the pin-to-pin delay model, delay in propagating a rising or a falling transition in the signal implied at an input of a gate to the output of the gate is deemed independent of the signals at other inputs. (Delay also occurs when transitions propagate from the near end of a circuit line to its far end. Delay of a circuit line can be integrated with either the delay of the gate driving the line or with the delays of the gates driven by the line. Therefore, without loss of generality, throughout this dissertation, we assume that circuit lines have no delay.) The pin-to-pin delay model has been extensively used both in simulation and testing. It is known that the pin-to-pin delay model does not capture all the transistor-level details that affect delays. Other delay models have been developed and used [7][8] that capture the dependency of the delay associated with an input of a gate on the signals at other inputs. However, this dissertation assumes the pin-to-pin delay model for two reasons. First, the complexity of more accurate models are deemed excessive for the purpose of simulation and testing. Second, the results obtained from using this model are believed by the industry as providing sufficient accuracy and quality. (Refer to Appendix A, Section A.1 for more details about the pin-to-pin delay model.) A gate delay fault [27][28][23][55] is said to exist on a gate if a rising or a falling pin-to-pin delay of the gate is different from its expected value, referred to as the nominal value, independent of the signals implied at different nodes. Size of the gate delay fault is defined as the difference between the actual delay and its nominal value [27][28][23][55]. 6 1.1.2 Path delay fault A path [27][28] is a sequence of circuit lines and gates from a circuit input to a circuit output. Circuit lines that are on the path are called on-path lines. The first on- path line is called the path input and the last on-path line is called the path output. Gates that are driven by the on-path lines are called on-path gates. An input of an on- path gate that is an on-path line is called the on-path input. An input of an on-path gate that is not an on-path line is called an off-path input. In association with each path P, rising logical path P R and falling logical path P F are respectively defined corresponding to rising transition and falling transition at some on-path line, referred to as the logical path’s direction-reference [28]. Any future reference to a logical path assumes the path input as the direction-reference of the logical path unless otherwise stated. In conjunction with a logical path, an on-path line is said to have even parity if there are even number of inverting on-path gates from the logical path’s direction-reference to the line. Else, it is said to have odd parity. In the case of a rising logical path, on-path lines that have even parity are said to have 0-to-1 (or rising) logical direction and those that have odd parity are said to have 1-to-0 (or falling) logical direction. In the case of a falling logical path the naming is the other way. Under the pin-to-pin delay model, a delay is associated with logical path P R (P F ), denoted by R d P ( F d P ), and is defined as the sum of the delay values along the logical path [28]. In conjunction with a gate whose on-path input has a rising (falling) logical direction, “delay” in the above sum is the rising (falling) pin-to-pin delay of the gate for 7 the on-path input. This applies to all references to the sum of delay values along a logical path in the rest of this dissertation. All the terms defined above can be defined in a similar way in conjunction with a sub-path, a sequence of circuit lines and gates, where the first and last circuit lines are not necessarily a circuit input and a circuit output. Under the multiple gate delay fault (MGDF) assumption, it is assumed that multiple gate delay faults exist in a fabricated circuit at unknown locations and with unknown sizes. Under the MGDF, it is said that a path delay fault exists on a logical path if the delay of the logical path, due to the presence of gate delay faults along the path, is greater than t S [28][33][53][37]. Path delay faults on logical paths might cause timing errors in the circuit. An example is presented below. ___________________________________________________________________ Example 1-1: Consider the example circuit shown in Figure 1-2 (a). Under the pin-to-pin delay model, delay in propagating a rising or falling transition from input l of a gate g to the output of the gate is denoted by X d l g , where X ∈ {R, F} (refer to Appendix A, Section A.1). Suppose in a fabricated copy of the example circuit, 1 R d a g = 5, 2 F d b g = 2 F d f g = 2, 3 R d c g = 3, 4 F d d g = 2, and 5 R d h g = 3. Suppose t S = 11. There is a path delay fault on the rising logical path P R , where P = (a, g 1 , b, g 2 , c, g 3 , d, g 4 , e), because R 24 13 FF RR S d= d d d d 12 t P ab c d gg gg ++ + => . 8 Under the two-pattern input sequence shown in Figure 1-2 (b), T 1 , a timing error occurs at e. It should be noted that a path delay fault on a logical path does not cause a timing error under all stimuli. Under the two-pattern input sequence shown in Figure 1-2 (c), T 2 , no timing error is created. c b a d e g 1 g 2 g 3 g 4 g 5 S1 S1 S1 S1 S0 5 7 10 12 0 c b a d e g 1 g 2 g 3 g 4 g 5 S1 S1 S1 S1 5 5 8 10 0 3 t S t S f f h h 0 0 (b) (c) c b a d e g 1 g 2 g 3 g 4 g 5 f h (a) Figure 1-2. An example used to demonstrate that path delay faults on logical paths might cause timing errors in circuits. (a): The example circuit. (b): Timing error occurs under T 1 . (c): No timing error occurs under T 2 . _______________________________________________________________________________________________________________________________________ 9 1.1.2.1 Functional sensitization test for a logical path In this dissertation we assume that the circuit under test is comprised of primitive gates, i.e., AND, NAND, OR, NOR, and NOT gates. (Any non-primitive gate can be modeled using a number of primitive gates.) For a gate g that is a NAND or an AND gate, controlling value, denoted by cv g , and non-controlling value, denoted by ncv g , are defined as logic-0 and logic-1, respectively. For a gate g that is a NOR or an OR gate, the definition is the other way around. Consider a path P in a circuit. Consider a multiple-input on-path gate g with on-path input i. In association with P R (or P F ), functional sensitization requirements [13][30] for g, under a two-pattern input sequence, are defined as follows. If i has cv g -to-ncv g logical direction, On-path requirement: FV(i) = ncv g , and Off-path requirement: For every off-path input j, FV(j) = ncv g . If i has ncv g -to-cv g logical direction, On-path requirement: FV(i) = cv g , and Off-path requirement: For every off-path input j, S j ≠ Static cv g , where S j denotes the signal at j (refer to Appendix A, Section A.2). For a 2-input on-path NAND gate, the requirements are illustrated in Figure 1-3. Any signal other than static logic-0 (a) (b) i j i j Figure 1-3. Functional sensitization requirements for a 2-input on-path NAND gate. (a): i has 0-to-1 logical direction, (b): i has 1-to-0 logical direction. 10 Considering a logical path, a two-pattern input sequence that, independent of whether gate delay faults exist, satisfies functional sensitization requirements for every multiple-input on-path gate along the path is called a functional sensitization test (FS- test) for the logical path [13][30]. If an FS-test exists for a logical path, the logical path is called FS-testable. Else, it is called FS-untestable. A two-pattern input sequence under which a timing error is created at the output of a logical path when any path delay fault exists on the logical path, while path delay faults might (or might not) exist on other logical paths, is called a detecting-test for the logical path. When a fabricated circuit passes a detecting-test for a logical path, it can be concluded that no path delay fault exists on the logical path. (Note that when a fabricated circuit fails a detecting-test for a logical path, it cannot be concluded that a path delay fault necessarily exists on the logical path since the timing error might have been caused by path delay faults on other logical paths.) Under the MGDF, an FS-test for a logical path is not a detecting-test for the logical path. An example is presented below. ___________________________________________________________________ Example 1-2: Consider the example circuit discussed in Example 1-1. Suppose, whether or not gate delay faults exist, T 2 in Example 1-1 implies signals as shown in Figure 1-4. T 2 is an FS-test for P R . For the fabricated copy of the circuit that was discussed in Example 1-1, as discussed before, T 2 does not cause an error. Therefore, T 2 is not a detecting-test for P R . 11 c b a d e g 1 g 2 g 3 g 4 g 5 S1 S1 S1 S1 f h Figure 1-4. An FS-test for P R , where P = (a, g 1 , b, g 2 , c, g 3 , d, g 4 , e). _______________________________________________________________________________________________________________________________________ 1.1.2.2 Robust test for a logical path Consider a path P in a circuit. Consider a multiple-input on-path gate g with on-path input i. In association with P R (or P F ), robust requirements [53][37][30] for g, under a two-pattern input sequence, are defined as follows. If i has cv g -to-ncv g logical direction, On-path requirement: IV(i) = cv g and FV(i) = ncv g , and Off-path requirement: For every off-path input j, FV(j) = ncv g . If i has ncv g -to-cv g logical direction, On-path requirement: IV(i) = ncv g and FV(i) = cv g , and Off-path requirement: For every off-path input j, S j = Static ncv g . For a 2-input on-path NAND gate, the requirements are illustrated in Figure 1-5. Static logic-1 (a) (b) i j i j Figure 1-5. Robust requirements for a 2-input on-path NAND gate. (a): i has 0-to-1 logical direction, (b): i has 1-to-0 logical direction. Considering a logical path, a two-pattern input sequence that, independent of whether gate delay faults exist, satisfies robust requirements for every multiple-input 12 on-path gate along the path is called a robust test (R-test) for the logical path [53][37][30]. If no R-test exists for a logical path, the logical path is called robustly untestable (R-untestable). Else, it is called robustly testable (R-testable). As can be seen, functional sensitization requirements for a gate are a subset of robust requirements. Therefore, a necessary condition for a logical path to be R-testable is that the logical path is FS-testable. If a logical path is FS-untestable, it cannot be R- testable. Under the MGDF, an R-test for an FS-testable logical path is a detecting-test for the logical path [53][37][30] (refer to Appendix B). 1.1.3 Delay testing using tests for logical paths Under the MGDF, if no path delay fault exists on the logical paths in the circuit, no timing error might occur in the circuit [30] (refer to Appendix B). Furthermore, no timing error is caused even when path delay faults exist on FS-untestable logical paths as long as no path delay fault exists on any FS-testable logical path [13][30] (refer to Appendix A, Section A.3, and also Appendix B). Therefore, delay testing can be carried out by verifying that no path delay fault exists on the FS-testable logical paths in the circuit. As mentioned in Section 1.1.2.2, verifying that no path delay fault exists on an FS-testable logical path is carried out by applying a corresponding R-test [53][37][30]. Therefore, if a circuit passes a test-set that contains an R-test for each FS-testable logical path in the circuit, it is guaranteed that no timing error occurs in the circuit [30] (refer to Appendix B). 13 1.2 Crosstalk-induced delay Consider a capacitive coupling effect between two circuit lines x and y. A transition in S y , the signal implied at y, is delayed (compared to the situation where the coupling effect does not exist) if a transition in the opposite direction occurs in S x within a relatively short time [3][32][9][10]. The capacitive coupling effect also causes the transition in S x to arrive later (compared to the situation where the coupling does not exist). This phenomenon is called crosstalk-induced slow-down or delay. An illustration is shown in Figure 1-6. t y and t x respectively denote the arrival times of the transitions in S y and S x . t x0 and t y0 respectively denote the arrival times if the coupling did not exist. t y – t y0 and t x – t x0 are the magnitudes of crosstalk-induced slow-down at y and x, respectively. c x y t y 0 t y t y0 t x Slow-down at y a b t x 0 t x0 Slow-down at x Skew = t x0 - t y0 Skew = t x0 - t y0 Figure 1-6. Crosstalk-induced slow-down. A transition in S y is sped up (compared to the situation where the coupling effect does not exist) if a transition in the same direction occurs in S x within a relatively short time [3][9][10]. The capacitive coupling effect also causes the transition in S x to arrive earlier (compared to the situation where the coupling does not exist). This phenomenon is called crosstalk-induced speed-up. An illustration is shown in Figure 1-7. t y0 – t y and t x0 – t x are the magnitudes of crosstalk-induced speed-up at y and x, respectively. 14 c x y t y 0 t y t y0 t x Speed-up at y a b t x 0 t x0 Speed-up at x Skew = t x0 - t y0 Skew = t x0 - t y0 Figure 1-7. Crosstalk-induced speed-up. The magnitudes of the crosstalk-induced slow-down or speed-up at y or x depend on the strengths of the gates driving x and y, the amount of loads being driven by x and y, and the coupling capacitance c [9][10]. They also depend on skew, i.e., t x0 – t y0 (refer to Figure 1-6 and Figure 1-7), and are at their maximum values around skew ≈ 0 [9][10]. If the electrical effort 1 associated with the gate driving x is much smaller than that of the gate driving y, the crosstalk-induced slow-down or speed-up at x will be negligible [9][10]. In such a situation, circuit lines y and x are respectively called victim and affecting lines. The affecting and victim lines together with the capacitive coupling effect between them are collectively called a crosstalk site. 1.2.1 Timing verification in the presence of crosstalk As discussed in the beginning of the chapter, after layout design, many parasitics that will exist in a fabricated chip, e.g., capacitive couplings between patterns of metal, inductances of patterns of metal, and so on, are identified and post-layout timing verification verifies correct temporal behavior of the circuit in the presence of such parasitics. Many post-layout timing verification approaches only focus on capacitive coupling and assume that other parasitics either do not exist or the corresponding effects 1 Electrical effort for a gate is defined as the ratio of the capacitance that loads the output of the gate to the capacitance presented by the input terminal of the gate. Electrical effort is also called fan-out by many CMOS designers [59]. 15 are negligible. We make the same assumption as well. Existing approaches are categorized into single- and multiple-crosstalk-site approaches. In single-crosstalk-site approaches, crosstalk sites are considered one at a time [9][10][11][12][52]. Post layout timing verification is done by performing timing verification for the circuit in the presence of each of the sites, independently. Timing verification of the circuit in the presence of a crosstalk site is done by searching for a two-pattern input sequence that creates a timing error in the circuit [9][10][11][12][52]. The two-pattern input sequence must excite a crosstalk-induced delay (slow-down) effect and propagate the delay effect to the outputs and cause at least one of the outputs to be at a value different from the desired value at t = t S [9][10][11][12][52]. In order to excite a crosstalk-induced delay effect, the two-pattern input sequence must invoke opposite-direction transitions at the affecting and victim lines with small skew [9][10][11][12][52]. If the search process fails, i.e., if no such two-pattern input sequence is found, timing verification of the circuit in the presence of the crosstalk site is presumed successful. (Note that incompleteness of search may result in erroneous conclusions.) Else, the circuit has timing errors and thus either the layout must be modified or the circuit must be redesigned (Figure 1-1). In this approach, crosstalk- induced delay effect is treated as a generic delay fault with certain excitation conditions and the search process, in essence, is nothing but a test generator for delay faults. Combined effects of several crosstalk sites might result in erroneous timing behavior of a design. In multiple-crosstalk-site approaches, multiple crosstalk sites are considered at the same time [29][2]. For the purpose of post layout timing verification, the first step is to search for tests that are likely to invoke extensive delays. Test 16 generation problem considering multiple crosstalk sites is a very difficult problem because of the complex logic as well as timing requirements (e.g., at each crosstalk site, opposite direction transitions must be invoked at the affecting and victim lines with small skew). Incorporating timing into test generation process has an extremely high complexity; therefore, in multiple-crosstalk-site approaches either timing is ignored [2] or non-deterministic methods (for example, genetic algorithm based search process [29]) are utilized during test generation. As a result, generated tests are not guaranteed to invoke the maximum delay of the circuit. The next step is to accurately simulate (logic as well as timing) the circuit with the generated tests. If a timing error is observed under any of the generated tests, the circuit has timing errors and thus either the layout must be modified or the circuit must be redesigned (Figure 1-1). Else, timing verification of the circuit in the presence of the crosstalk sites is presumed successful. 1.2.2 Testing for crosstalk-induced delay faults In a fabricated copy of a circuit, it is possible that, due to the presence of defects and process variations, crosstalk-induced delay (slow-down) is greater than that predicted by post-layout timing verification and thus a timing error is created in the circuit. Therefore, crosstalk-induced delay must not only be considered during post-layout timing verification but must also be considered in post-fabrication testing where it is modeled as a delay fault. A test for a crosstalk-induced delay fault must invoke a crosstalk-induced delay (slow-down) effect and propagate the delay effect to circuit outputs. 17 1.3 Bridge-induced slow-down Shorts between circuit nodes are a predominant type of manufacturing defects [48][19][26][22], and shorts between gate outputs, also known as bridges, account for about 90% of shorts [19][26][22][46][47][54]. In general, a bridge is resistive (by resistive, we mean its resistance is not necessarily zero) and its severity is inversely proportional to its resistance. A bridge might cause logic errors [46][47][50][18]. Sometimes, the resistance of a bridge is not low enough to cause logic errors for low speed tests. Such bridges are called weak resistive bridges (WRB). WRBs might affect temporal behavior of the circuits [40][36][25]. Consider a WRB between two circuit lines x and y. A falling transition in S y is delayed (compared to the situation where the WRB does not exist) if S x is at logic-1 during a time interval close to when S y makes the transition [40][36][25]. This phenomenon is called WRB-induced slow-down or delay. The falling transition in S y is sped-up (compared to the situation where the WRB does not exist) if S x is at logic-0 during a time interval close to when S y makes the transition. This phenomenon is called WRB-induced speed-up. WRB-induced slow-down and speed-up also occur in conjunction with a rising transition in S y and also in conjunction with rising or falling transitions in S x . The magnitudes of the WRB-induced speed-up or slow-down at y depend on the strengths of the gates driving x and y, the amount of loads being driven by x and y, and the resistance of the bridge, r b [60]. They also depend on the interval(s) of time when S x is at logic-0 or logic-1. (Similar relations also hold regarding the magnitudes of the WRB-induced speed-up or slow-down at x). For instance, when S x is static logic-1 18 (logic-0), the magnitude of the WRB-induced slow-down applied to a falling (rising) transition in S y is at its maximum possible value. Figure 1-8 shows an illustration for the situation where S x and S y are clean transitions. t y and t x respectively denote the arrival times of the transitions in S y and S x . t x0 and t y0 respectively denote the arrival times if the WRB did not exist. t y – t y0 is referred to as WRB-induced ∆-delay at y. In Figure 1-8 (a), for positive values of skew (i.e., t x0 – t y0 ), we have a case of WRB-induced slow-down and for negative values of skew, we have a case of WRB-induced speed-up. In Figure 1-8 (b), for negative values of skew, we have a case of WRB-induced slow-down and for positive values of skew, we have a case of WRB-induced speed-up. Similar graphs can be shown for WRB- induced ∆-delay at x. r b x y 0 Skew = t x0 - t y0 t y t y t y0 t x a b Slow-down at y Speed-up at y r b x y 0 Skew = t x0 - t y0 t y t y t y0 t x Speed-up at y Slow-down at y a b (a) (b) Figure 1-8. WRB-induced slow-down and speed-up when S x and S y are clean transitions. If the electrical effort associated with the gate driving x is much smaller than that of the gate driving y, the WRB-induced slow-down or speed-up at x will be negligible. In such a situation, circuit lines y and x are respectively called victim and affecting lines. 19 The affecting and victim lines together with the WRB between them are collectively called a WRB site. WRB-induced slow-down behaves like a delay fault in the sense that if the delayed transition propagates to circuit outputs, it may cause timing errors [40][25]. Therefore, testing for WRB-induced delay faults is essential. A test for a WRB-induced delay fault must invoke a WRB-induced slow-down effect and propagate the delay effect to circuit outputs. 1.4 Technology trends and the purpose of this dissertation Process technologies are constantly challenged by demands for higher operating frequencies, improved circuit densities, lower power consumption, and so on [62][5]. The above demands are met by process scaling, architecture changes, circuit optimizations, layout optimizations, and so on. The advantages gained using many of the above methods and approaches are achieved at the cost of increased parasitic effects, such as crosstalk-induced delay, ground bounce, swing on power nets, substrate and thermal noise, and so on [62][5]. For example, through process scaling, the feature size will decrease, the minimum width of an interconnect will decrease and its height- to-width aspect ratio will increase. Furthermore, the minimum separation between interconnects will decrease. These trends result in decrease in self capacitance values but cause increase in coupling capacitance values [62][5]. Increase in coupling capacitance values results in increased crosstalk-induced delay (see Section 1.2). Similarly, demand for improved circuit densities will increase the lengths of interconnects (relative to minimum feature size) and thus will increase self capacitance 20 as well as coupling capacitance values [62][5] and hence will increase crosstalk-induced delay. Ensuring correct operation of digital systems in the presence of parasitic effects is imperative. Process technology advancements are changing the population of physical defects that affect circuit functionality [62]. Tight timing requirements reduce the thresholds and hence increase a circuit’s sensitivity to defects [62]. Changing circuit sensitivities are likely to make defects that were benign in the past become catastrophic in the future [62]. Furthermore, increasing parasitic effects, such as crosstalk induced-delay, decrease noise and timing margins and increase circuit susceptibility to defects [62]. With decreasing geometries, the influence of fluctuations of process parameters during manufacturing on the circuit’s performance is becoming more and more important because process tolerances are not scaling in proportion to geometries [21]. Process variations are also aggravating parasitic effects such as crosstalk-induced delay [4][42]. Furthermore, in today’s design environments, due to high complexity and prohibitive cost and performance considerations, it is impossible to check and fix all possible signal integrity problems during design verification phase. Due to above reasons, crosstalk-induced delay (slow-down) must not only be considered during post-layout timing verification but it must also be considered during post-fabrication testing together with realistic populations of manufacturing imperfections and process variations. The major focus of this dissertation is on developing a test methodology for crosstalk-induced delay faults in the presence of 21 other gate 1 delay faults caused by defects and process variations. A single crosstalk site methodology (refer to Section 1.2.1) will be used. As bridges are the predominant type of manufacturing defects in new technologies [62], this dissertation also focuses on developing a test methodology for WRB-induced delay faults in the presence of other gate delay faults caused by defects and process variations. The methodology will focus on one WRB site at a time. 1.5 Review of related work In [9] and [10] expressions relating the crosstalk-induced delay to circuit parameters, the rise/fall times of the input transitions, and the skew between the transitions are derived. It is also shown that crosstalk effects can be significantly aggravated by variations in the fabrication process. Conditions that must be satisfied by a sequence of patterns used for verification are also provided. In [11] and [12] the problem of generating two-pattern tests for crosstalk-induced delay has been addressed. A mixed-signal test generator has been developed that incorporates classical static values and dynamic signals as well as timing information, such as signal arrival times, rise/fall times, and gate delay. In [52], some shortcomings of the test generation approach presented in [11] and [12] are addressed and solutions are provided. In particular, propagation conditions are relaxed to increase the size of the solution space and the likelihood of finding a test; the relation between arrival time and required time ranges is used to selectively turn off the timing computation procedure which is 1 As mentioned in Section 1.1.1, delays of circuit lines (also referred to as wire delay or interconnect delay in the literature) can be integrated with delays of gates driving or being driven by the circuit lines. Therefore, we only focus on gate delay faults. 22 computationally expensive; a more accurate delay model for gates is used; and more accurate calculation of crosstalk-induced delay at the victim line is incorporated. The approaches in [11], [12] and [52] are based on nominal delay values and thus are suitable for post-layout timing verification and can not be used for post-fabrication testing due to the following two reasons. 1) A test generator that does not consider defects might erroneously report that no timing error occurs in any fabricated copy of the circuit while there exists at least one two-pattern input sequence that creates a timing error in a fabricated copy of the circuit. 2) Due to presence of defects, maximum delay of a fabricated circuit under a test generated by a test generator that does not consider defects might be smaller than that predicted by the test generator. When the fabricated circuit passes the test, it cannot be concluded that no timing error occurs in the circuit. A test other than the one found by the test generator might invoke larger delay and cause a timing error. In [51] and [34] test generation methods based on single precise crosstalk path delay fault (S-PCPDF) model and non-robust and robust propagation conditions are proposed. Tests generated by these approaches do not necessarily invoke the worst-case delay and thus do not guarantee testing of the crosstalk-induced delay effect. Bridge-induced logic fault has been extensively studied in the literature. Many have considered modeling [47][45] and simulation of this fault class [31][50]. Test generation for this fault class has been carried out in [50][38]. In [36], a model for WRB-induced delay fault has been presented. This model ignores the skew between input transitions and hence covers only the worst-case slow-down. As a result, tests 23 generated using this method may not detect the fault. In [39], test conditions for WRB- induced delay faults are identified. Such tests do not necessarily invoke the worst-case delay. Furthermore, no systematic approach for generating such tests has been proposed. 1.6 Overview of the dissertation This dissertation focuses on developing test methodologies for crosstalk- and WRB- induced delay faults in the presence of gate delay faults caused by defects and process variations. In a fabricated circuit, multiple gate delay faults might exist the sizes and locations of which are unknown. For such a circuit, nominal timing information is not valid. In Chapter 2, a timing-independent approach for testing for crosstalk-induced delay faults is presented. In conjunction with each crosstalk site, using this approach, under certain circumstances, tests can be generated that guarantee testing for crosstalk- induced delay faults in the sense that if a fabricated circuit passes such tests, it can be concluded that no timing error occurs in the circuit under any possible two-pattern input sequence. No existing approach generates tests that can provide such a guarantee. In Chapter 3, a timing-independent approach for testing for WRB-induced delay faults is presented. In conjunction with each WRB site, using this approach, under certain circumstances, tests can be generated that guarantee testing for WRB-induced delay faults. No existing approach generates tests that can provide such a guarantee. Experimental results in conjunction with the approach presented in Chapter 2 will show that considerable percentage of crosstalk sites in benchmark circuits are not 24 covered by the approach. Furthermore, for the covered crosstalk sites, cost of test generation and test application might be high. The same is true in conjunction with the approach presented in Chapter 3 and WRB sites. Certain assumptions about the nature of defects and process variations and the resulting gate delay faults can be exploited to obtain higher coverage of crosstalk and WRB sites and lower test generation and test application costs. These assumptions and their ramifications are presented in Chapter 4. Appendices contain complementary materials that are referred to in Chapters 1-4. In particular, proofs for the statements and theorems presented in Chapters 1-4 are available in Appendices. 25 Chapter 2 Testing for crosstalk-induced delay faults 2.1 Introduction Consider a crosstalk site with affecting and victim lines x and y. Under a two-pattern input sequence, crosstalk-induced delay fault C(x, y, R) is said to be induced at y if There exists a falling transition in the signal implied at x, S x , There exists a rising transition in S y the arrival time of which is delayed compared to the situation where the capacitive coupling did not exist, and The magnitude of the crosstalk-induced slow-down is large enough to affect circuit’s temporal behavior. Crosstalk-induced delay fault C(x, y, F) can be defined in a similar way. The effect of the crosstalk-induced delay fault at y might propagate to circuit outputs and cause timing errors. In this chapter, an approach for testing for crosstalk-induced delay faults is presented. We focus on circuits that only have one crosstalk site 1 . Using this approach, under certain circumstances, tests can be generated that guarantee testing for crosstalk- induced delay faults in the sense that if a fabricated circuit passes such tests, it can be concluded that no timing error occurs in the circuit under any possible two-pattern input sequence. No existing approach generates tests that can provide such a guarantee. 1 At a crosstalk site, the crosstalk-induced slow-down or speed-up at the affecting line is negligible (refer to Section 1.2 for the definition of a “crosstalk site”). 26 Our approach assumes the pin-to-pin delay model (refer to Appendix A, Section A.1). Our approach assumes the MGDF, i.e., it is assumed that in addition to the crosstalk site that might cause crosstalk-induced delay faults, multiple gate delay faults might exist in the circuit but we do not know their locations and sizes. Nominal pin-to- pin delay values are thus of no use and only the assumptions underlying the pin-to-pin delay model are utilized (in brief, delay in propagating a transition from an input of the gate to the output of the gate is independent of the signals at other inputs). Our approach assumes that no static logic error occurs in the circuit and no path delay fault exists on any FS-testable logical path that does not pass through the victim line. In other words, the generated tests are used after each fabricated circuit passes logic testing and classical delay testing. Our approach focuses on circuits with crosstalk sites for which the affecting and victim lines are not circuit inputs or outputs and are not in transitive fan-in [27] of each other. During the search for a test that invokes a crosstalk-induced delay fault at a crosstalk site and propagates the delay effect to circuit outputs and thereby causes timing errors, it is not known a priori whether a crosstalk-induced delay fault can actually be invoked at the site. Therefore, the term “crosstalk slow-down target” or “crosstalk delay target” is used in test generation methodology. In conjunction with crosstalk slow-down target C(x, y, R) (or C(x, y, F)), under a two-pattern input sequence, whether or not a crosstalk-induced delay fault is created at y depends on the transitions invoked in S x and S y and their arrival times. The arrival times depend on the delay values along propagation sub-paths from circuit inputs to x and y (refer to 27 Appendix A, Section A.2). If the delayed transition at y is propagated to circuit outputs, the arrival time of such transitions at the outputs depend on the arrival time of the delayed transition at y and the delay values along propagation sub-paths from y to the outputs (refer to Appendix A, Section A.2). In other words, whether or not a two-pattern input sequence is a test for the crosstalk slow-down target depends on the delay values along sub-paths from circuit inputs to y and x and sub-paths from y to circuit outputs. Under the MGDF, delay values along such sub-paths are not known. Therefore, generating tests for crosstalk slow-down targets must be carried out in a timing- independent manner. The organization of the rest of this chapter is as follows. In Section 2.2 the timing- independent test generation methodology for crosstalk slow-down targets that we have developed is presented. We have implemented an automatic test pattern generator (ATPG) that incorporates the developed methodology. This ATPG is presented in Section 2.3. Experimental results are reported in Section 2.4. Section 2.5 summarizes the key conclusions. 2.2 Test generation methodology for crosstalk slow-down targets 2.2.1 Terminology In conjunction with a crosstalk site, sub-paths that start at circuit inputs and end at the affecting line are called IX-sub-paths; sub-paths that start at circuit inputs and end at the victim line are called IY-sub-paths; and sub-paths that start at the victim line and end at circuit outputs are called YO-sub-paths. In the case of an IX-sub-path, on-sub- path lines and on-sub-path gates are called on-IX-sub-path lines and on-IX-sub-path 28 gates, respectively. On-IY- and on-YO-sub-path lines and on-IY- and on-YO-sub-path gates are defined in a similar way. Throughout Section 2.2, we focus on a crosstalk site with affecting and victim lines x and y with n IX-sub-paths, IX 1 , IX 2 , …, IX n , m IY-sub-paths, IY 1 , IY 2 , …, IY m , and p YO-sub-paths, YO 1 , YO 2 , …, YO p . In conjunction with the IX-sub-paths, the terms “logical sub-path”, “parity”, and “logical direction” (refer to Section 1.1.2) are referred to as “logical IX-sub-path”, “IX- parity”, and “logical IX-direction”. In conjunction with the logical IX-sub-paths, the direction-reference (refer to Section 1.1.2) is the affecting line. We use the terms “logical IY-sub-path”, “IY-parity”, and “logical IY-direction” in conjunction with the IY-sub-paths and the terms “logical YO-sub-path”, “YO-parity”, and “logical YO- direction” in conjunction with the YO-sub-paths. In conjunction with the logical IY- sub-paths and the logical YO-sub-paths, the direction-reference is the victim line. A delay is associated with each R IX i ( F IX i ), { 1, ..., } in ∈ , denoted by R IX d i ( F IX d i ), and is defined as the sum of the delay values along the logical IX-sub-path. For sub-path IX 1 = (e, g 5 , h, g 6 , x) in the example shown in Figure 2-1, R 1 IX d and F 1 IX d can be written as R 6 5 1 F R IX dd d eh g g =+ , and F 6 5 1 R F IX dd d eh g g =+ . A delay is associated with each R IY j ( F IY j ), { 1, ..., } jm ∈ , denoted by R IY d j ( F IY d j ), and is defined as the sum of the delay values along the logical IY-sub-path. For the gate that is driving the victim line, the effect of the coupling is ignored. For sub- 29 path IY 1 = (a, g 1 , b, g 2 , y) in the example shown in Figure 2-1, R 1 IY d and F 1 IY d can be written as R 2 1 1 F R IY nc dd d ab g g =+ , and F 2 1 1 R F IY nc dd d ab g g =+ . 2 R nc d b g ( 2 F nc d b g ) represents delay of g 2 in propagating a rising (falling) transition in the signal at b to y if the coupling did not exist (nc: no coupling). (Refer to Appendix A, Section A.1.1 for more details.) A delay is also associated with each R YO k ( F YO k ), { 1, ..., } kp ∈ , denoted by R YO d k ( F YO d k ), and is defined as the sum of the delay values along the logical YO- sub-path. For sub-path YO 1 = (y, g 3 , c, g 4 , d) shown in Figure 2-1, R 1 YO d and F 1 YO d can be written as R 3 4 1 R F YO dd d y c g g =+ , and F 3 4 1 F R YO dd d y c g g =+ . y b a c d g 1 g 2 g 3 g 4 g 6 x g 5 e h IX 1 IY 1 YO 1 Figure 2-1. An example illustrating a crosstalk site and three corresponding IX-, IY-, and YO-sub- paths. A logical IY-sub-path together with a logical YO-sub-path constitute a logical path referred to as a logical IY||YO-path. Direction-reference of this logical path is considered to be the victim line. For example, R IY j together with R YO k is denoted by RR IY || YO jk and is a rising logical path. 30 2.2.2 Surrogate As mentioned earlier, whether or not a two-pattern input sequence is a test for a crosstalk slow-down target depends on the delays of the IX-, IY- and YO-sub-paths. In conjunction with C(x, y, R), n × m × p surrogates are defined as triplets of logical sub- paths FR R (IX , IY , YO ) ij k , i = 1, …, n, j = 1, …, m, and k = 1, …, p. For example, for C(x, y, R) in the example shown in Figure 2-1, FR R 11 1 (IX , IY , YO ) is a surrogate. In conjunction with C(x, y, F), n × m × p surrogates are defined as triplets of logical sub- paths RF F (IX , IY , YO ) ij k , i = 1, …, n, j = 1, …, m, and k = 1, …, p. Surrogates that share a logical IY-sub-path and a logical YO-sub-path are said to belong to the surrogate-set corresponding the associated logical IY||YO-path. For example, surrogates that share R IY j and R YO k , i.e., { } FR R (IX , IY , YO ), 1, ..., ij k in = , are said to belong to the surrogate-set corresponding RR IY || YO jk . Hence, there are m × p surrogate-sets and there are n surrogates in each set. When S x , the signal implied at x, is a clean falling transition, and S y is a clean rising transition, the magnitude of the crosstalk-induced slow-down is represented as a function of the skew between the two transitions, sd C R (skew) 1 (refer to Appendix C for more details). Similarly, the magnitude of the crosstalk-induced slow-down is represented as a function sd C F (skew) when S x and S y are clean rising and falling transitions, respectively. 1 sd: slow-down 31 A delay is associated with each surrogate FR R (IX , IY , YO ) ij k S = , denoted by d S , and is defined as RR FR IY IY IX YO R C d= d (d d ) d jj ik S sd+− + . A delay is also associated with each surrogate RF F (IX , IY , YO ) ij k S = , and is defined as FF RF IY IY IX YO F C d= d (d d ) d jj ik S sd+− + . Under the MGDF, a surrogate delay fault exists on a surrogate if the delay of the surrogate, due to the presence of gate delay faults along the three sub-paths, is greater than t S . Existence of surrogate delay faults on surrogates might cause timing errors in the circuit. An example is presented below. ___________________________________________________________________ Example 2-1: Consider the example circuit shown in Figure 2-2 (a). Suppose in a fabricated copy of the circuit, 1 R d a g = 5, 2 F nc d b g = 2 (delay if coupling did not exist), 3 R d y g = 3, 4 F d c g = 2, 4 F d w g = 2, 5 F d e g = 3, 6 R d h g = 4, 7 F d u g = 5, and 8 R d v g = 5. As shown in the figure, IX 1 = (e, g 5 , h, g 6 , x), IY 1 = (a, g 1 , b, g 2 , y), and YO 1 = (y, g 3 , c, g 4 , d). Let us refer to IY 1 || YO 1 as path P. Suppose that t S = 13. Suppose that R C (0) 2 sd = . If the coupling did not exist, no path delay fault would exist on the logical path P R (direction-reference of P R is y) because, R 2 1 1 F R IY nc d= d d 7 ab g g += , and R 3 4 1 R F YO d= d d 5 y c g g += . 32 Thus RR R 11 IY YO S d= d d = 12 t P +< . As a result, under the two-pattern input sequence shown in Figure 2-2 (b), T 1 , no error would be created at d. However, in the presence of the coupling, a surrogate delay fault exists on the surrogate FR R 11 1 (IX , IY , YO ) S = because F 6 5 1 R F IX d= d d 7 eh g g += , and R F IY IXRR CC (d d ) (0) 2 j i sd sd −= = . Thus RR FR IY IY IX YO R CS d = d (d d ) d 527 14 t jj ik S sd + − + =++ = > . As shown in Figure 2-2 (c), as a result of the surrogate delay fault, a timing error occurs at d under T 1 . 33 y b a c d g 1 g 2 g 3 g 4 g 6 S1 S1 S1 5 9 12 14 0 t S S1 x 7 g 5 e h S1 0 3 IX 1 IY 1 YO 1 (c) S1 S1 S0 y b a c d g 1 g 2 g 3 g 4 g 6 S1 S1 S1 5 7 10 12 0 t S S1 x 7 g 5 e h S1 0 3 IX 1 IY 1 YO 1 (b) S1 S1 S0 g 7 g 8 g 7 g 8 y b a c d g 1 g 2 g 3 g 4 g 6 x g 5 e h IX 1 IY 1 YO 1 (a) g 7 g 8 uv w uv w uv w Figure 2-2. An example illustrating that surrogate delay faults might cause timing errors. (a) The example circuit. (b): If coupling did not exist, no timing error would occur under T 1 . (c): In the presence of the coupling, timing error occurs under T 1 . _______________________________________________________________________________________________________________________________________ 34 2.2.3 Top-down overview of testing for crosstalk-induced delay faults In this section, a top-down overview of our approach for testing for crosstalk- induced delay faults is presented. Details will be presented in Sections 2.2.4-2.2.6 in a bottom-up fashion. We will prove that if no surrogate delay fault exists on any surrogate defined in conjunction with C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. As a result, testing for crosstalk-induced delay faults can be carried out by verifying whether a surrogate delay fault exists on each corresponding surrogate. We will define a restricted-robust test (RR-test) for a surrogate as a two-pattern input sequence that satisfies certain timing-independent requirements in conjunction with the surrogate and will prove that such a test can verify whether there exists any surrogate delay fault on the surrogate. If there is a surrogate delay fault on a surrogate in a fabricated copy of the circuit, under an RR-test for the surrogate, a timing error is created in the circuit. Therefore, if a fabricated copy of the circuit passes an RR-test for a surrogate, it can be concluded that no surrogate delay fault exists on the surrogate in that fabricated copy of the circuit. As a result, a set of RR-tests for all the surrogates defined in conjunction with C(x, y, R) and C(x, y, F) guarantees testing for crosstalk- induced delay faults in any fabricated copy of the circuit. We will also define a functional sensitization test (FS-test) for a surrogate as a two- pattern input sequence that satisfies certain timing-independent requirements in conjunction with the surrogate. If no FS-test exists for a surrogate, the surrogate is referred to as FS-untestable; else, it is referred to as FS-testable. We will also prove that existence of surrogate delay faults on FS-untestable surrogates, as long as no 35 surrogate delay fault exists on the FS-testable surrogates, does not cause any timing error in the circuit either. As a result, a set of RR-tests for FS-testable surrogates guarantees testing for crosstalk-induced delay faults in any fabricated copy of the circuit. 2.2.4 FS-test for a surrogate In association with logical IY- and YO-sub-paths, functional sensitization requirements for multiple-input on-IY-sub-path and on-YO-sub-path gates are defined similar to functional sensitization requirements for on-path gates, as presented in Section 1.1.2.1. Definition: For surrogates that belong to the surrogate-set corresponding a logical IY||YO-path, a two-pattern input sequence that, independent of whether gate delay faults exist, Satisfies functional sensitization requirements for every on-IY-sub-path gate, and Satisfies functional sensitization requirements for every on-YO-sub-path gate is called a functional sensitization test (FS-test). For surrogates that belong to the surrogate-set corresponding a logical IY||YO-path, an FS-test is actually an FS-test for the logical IY||YO-path. If an FS-test exists for such surrogates (in other words, if the logical IY||YO-path is FS-testable), the surrogates in the set are called FS-testable. Else, they are called FS-untestable. A two-pattern input sequence under which a timing error is created at the output of a surrogate when any surrogate delay fault exists on the surrogate while surrogate delay 36 faults might exist on other surrogates is called a detecting-test for the surrogate. When a fabricated circuit passes a detecting-test for a surrogate, it can be concluded that no surrogate delay fault exists on the surrogate. (Note that when a fabricated circuit fails a detecting-test for a surrogate, it cannot be concluded that a surrogate delay fault necessarily exists on the surrogate since the timing error might have been caused by surrogate delay faults on other surrogates.) Under the MGDF, an FS-test for a surrogate is not a detecting-test for the surrogate. An example is presented below. ___________________________________________________________________ Example 2-2: Consider the example circuit discussed in Example 2-1. Suppose, independent of whether gate delay faults exist, a two-pattern input sequence, T 2 , implies signals as shown in Figure 2-3 (a). T 2 is an FS-test for surrogate FR R 11 1 (IX , IY , YO ) S = . For the fabricated copy of the circuit that was discussed in Example 2-1 (where a surrogate delay fault exists on S), as shown Figure 2-3 (b), T 2 does not cause an error. Therefore, T 2 is not a detecting-test for S. 37 y b a c d g 1 g 2 g 3 g 4 g 6 S1 S1 5 9 12 12 0 t S S1 x 7 g 5 e h S1 0 3 IX 1 IY 1 YO 1 S1 0 10 5 g 7 g 8 y b a c d g 1 g 2 g 3 g 4 g 6 S1 S1 S1 x g 5 e h S1 IX 1 IY 1 YO 1 S1 g 7 g 8 (a) (b) uv w uv w Figure 2-3. An example demonstrating that an FS-test for a surrogate is not a detecting-test for the surrogate. _______________________________________________________________________________________________________________________________________ 2.2.5 Restricted-robust test for a surrogate Let us focus on a logical IX-sub-path. Consider a multiple-input on-IX-sub-path gate g with on-sub-path input a. In association with the logical IX-sub-path, restricted- robust (r-robust) requirements for g, under a two-pattern input sequence, are defined as follows. On-sub-path requirement: S a = Clean transition (refer to Appendix A, Section A.2) with the same direction as a’s logical IX-direction, and 38 Off-sub-path requirement: For every off-sub-path input b, S b = Static ncv g . For a 2-input on-IX-sub-path NAND gate, the requirements are illustrated in Figure 2-4. Static logic-1 a b a b cc Static logic-1 (a) (b) Figure 2-4. R-robust requirements for a 2-input on-IX-sub-path NAND gate. (a): a has 0-to-1 logical IX-direction, (b): a has 1-to-0 logical IX-direction. In association with logical IY-sub-paths, r-robust requirements for multiple-input on-IY-sub-path gates are defined in a similar way. Furthermore, in association with logical YO-sub-paths, robust requirements for multiple-input on-YO-sub-path gates are defined similar to robust requirements for on-path gates, as presented in Section 1.1.2.2. Definition: For a surrogate, a two-pattern input sequence that, independent of whether gate delay faults exist, Satisfies r-robust requirements for every on-IX-sub-path gate, Satisfies r-robust requirements for every on-IY-sub-path gate, and Satisfies robust requirements for every on-YO-sub-path gate is called a restricted-robust test (RR-test). If an RR-test exists for a surrogate, the surrogate is called RR-testable. Else, it is called RR-untestable. As can be seen, requirements that a two-pattern input sequence must satisfy in order to be an FS-test for a surrogate are a subset of the requirements that need to be satisfied to make the two-pattern input sequence an RR-test for the 39 surrogate. Therefore, a necessary condition for a surrogate to be RR-testable is that the surrogate is FS-testable. If a surrogate is FS-untestable, it cannot be RR-testable. Theorem 2-1: An RR-test for an FS-testable surrogate is a detecting-test for the surrogate. (Proof is presented in Appendix C, Section C.2.) It should be noted that for a two-pattern input sequence to be an RR-test for a surrogate, no timing requirement needs to be satisfied. In other words, requirements of RR-tests are defined in a timing-independent manner. 2.2.6 Testing for crosstalk-induced delay faults using tests for the corresponding surrogates Under the assumptions made in Section 2.1, in particular, under the MGDF and the pin-to-pin delay model, Theorem 2-2: If no surrogate delay fault exists on the surrogates defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix C, Section C.2.) In the meantime, existence of surrogate delay faults on FS-untestable surrogates, as long as no surrogate delay fault exists on FS-testable surrogates, does not cause any timing error in the circuit either. In other words, 40 Theorem 2-3: If no surrogate delay fault exists on the FS-testable surrogates defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix C, Section C.2.) Corollary 2-1: If all the surrogates defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F) are FS-untestable, no timing error might occur in the circuit. (Such a crosstalk site is called an FS-untestable crosstalk site. A crosstalk site that is not FS-untestable is called FS-testable.) From what stated above, it can be concluded that, in conjunction with a crosstalk site that is not FS-untestable, testing for crosstalk-induced delay faults can be carried out by verifying whether a surrogate delay fault exists on each FS-testable surrogate defined in association with crosstalk targets C(x, y, R) and C(x, y, F). As mentioned in Section 2.2.5, an RR-test for a surrogate can verify whether there exists any surrogate delay fault on the surrogate. Therefore, Theorem 2-4: If a circuit with an FS-testable crosstalk site passes a test-set that contains an RR-test for each FS-testable surrogate defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix C, Section C.2.) 41 A crosstalk site for which such a test-set exists is called an RR-testable crosstalk site. For an RR-testable crosstalk site, such a test-set is guaranteed to test fabricated copies of the circuit for crosstalk-induced delay faults. In conjunction with an RR- testable crosstalk site, the number of invocations of test generator is n × m × p, in the worst case. 2.3 Test pattern generation We have implemented an ATPG for generating tests for surrogates. 2.3.1 Value system Using six basic values [27] namely, static logic-0 (S0), static logic-1 (S1), falling- transition (T0), rising-transition (T1), hazardous logic-0 (H0) and hazardous logic-1 (H1), twenty composite values [27] are identified which provide closure for forward and backward implication procedures [27]. This value system ensures that no information is lost during the implication process. Key details of the procedure used for identifying the composite value set are as follows. 1. Define six composite values each of which contains only one of the basic values. 2. Define “unknown value” as a composite value that contains all the basic values. 3. Considering the currently identified composite values, construct (or reconstruct) tables to be used by forward implication procedure. 4. By applying combinations of the currently identified composite values to the backward implication procedure, identify new composite values that need to be added. (These composite values contain specific combinations of the basic values.) 42 5. By applying combinations of the currently identified composite values to the forward implication procedure, identify other new composite values that need to be added. (These composite values contain some other specific combinations of the basic values.) 6. Repeat steps 3 to 5 until no new values are added. The resulting composite values and the basic values that they contain are shown in Table 2-1. Table 2-1. Composite values and the basic values that they contain. Composite value Basic values contained in the composite value Value 0 {S0} Value 1 {S1} Value 2 {T0} Value 3 {T1} Value 4 {H0} Value 5 {H1} Value 6 {S0, S1, T0, T1, H0, H1} Value 7 {S0, T0, H0} Value 8 {S0, T1, H0} Value 9 {S0, H0} Value 10 { S0, T0, T1, H0, H1} Value 11 {S1, T0, H1} Value 12 {T1, H0} Value 13 {T0, H1} Value 14 {S1, T1, H1} Value 15 {T0, H0} Value 16 {T1, H1} Value 17 {S1, T0, T1, H0, H1} Value 18 {T0, T1, H0, H1} Value 19 {S1, H1} Value 20 {} 2.3.2 Overview of test generation core During initialization [27], depending on whether an RR-test or an FS-test is being sought for a surrogate, appropriate values are injected at on-sub-path lines and off-sub- path inputs of on-sub-path gates corresponding to the surrogate. The ATPG core implements D-algorithm [49] within which forward and backward implication and 43 justification procedures [27] are executed repeatedly until no unjustified line remains in the circuit. In order to save memory space, at each justification step and when storing the state of the test generator in order to deal with a possible backtrack [27], only the values at unjustified lines and circuit’s inputs are stored. When backtrack becomes necessary, these values are injected back into lines and necessary implications are performed to completely restore the values at all lines. 2.4 Experimental results The above ATPG is used to generate tests for the surrogates corresponding to crosstalk slow-down targets in the combinational parts of ISCAS 89 circuits. Table 2-2 presents some details about the circuits under study. Table 2-2. Specifications of the circuits under study. Circuit #of inputs #of outputs #of levels #of paths Total #of crosstalk sites with the specifications stated in Section 2.1 Total #of surrogates associated with the crosstalk sites S298 17 20 14 231 84,006 2,208,024 S349 24 26 29 365 109,718 15,515,240 S420 35 18 43 369 159,214 19,786,974 S444 24 27 18 535 183,876 23,067,606 S510 25 13 17 369 245,930 11,484,106 S820 23 24 12 492 657,714 16,368,208 S1488 14 25 21 962 2,157,036 167,830,524 FS- and RR-tests are sought for the surrogates corresponding each crosstalk site. The results are shown in Table 2-3. “Coverage” represents percentage of FS-testable crosstalk sites that are RR-testable. 44 Table 2-3. Coverage. Circuit Total #of crosstalk sites with the specifications stated in Section 2.1 Total #of FS-untestable crosstalk sites Total #of RR-testable crosstalk sites Coverage S298 84,006 7,253 40,984 53.40% S349 109,718 7,404 24,739 24.18% S420 159,214 18,504 60,287 42.84% S444 183,876 13,529 38,627 22.68% S510 245,930 35,930 37,484 17.85% S820 657,714 105,424 223,746 40.51% S1488 2,157,036 187,902 316,846 16.09% In [24], we have extensively studied and analyzed the results of RR-test generation for surrogates. In particular, distribution of crosstalk sites with regard to the number of / percentage of the corresponding surrogates that are RR-testable, and also distribution of crosstalk sites with regard to the number of / percentage of the corresponding surrogates with large nominal delays that are RR-testable are studied. Furthermore, crosstalk sites are categorized into groups according to the number of / percentage of the corresponding surrogates that are RR-testable. For each of the categories, nominal delay profiles of the surrogates are studied. We performed the above mentioned study to identify trends or relations that possibly exist between the coverage of crosstalk sites and the number of / percentage of the corresponding surrogates and their nominal delays. This study revealed only the obvious trends: The closer the affecting and victim lines are to the outputs, the more is the number surrogates and the larger are the delays of the surrogates and the less is the likelihood of the crosstalk site to be RR-testable. 45 2.4.1 Run time Table 2-4 shows run times in seeking RR-tests for all the surrogates (all the possible pairs of lines were targeted in these results including those that are in transitive fan-in of each other) in different circuits. The number of lines, the number of surrogates, the number of logic levels in the circuit and the topology of the circuit are factors that affect the total run time for test generation. Two different approaches were used for targeting surrogates for test generation. The second approach or the so called “new approach” results in much smaller run times. Figure 2-5 shows the general flows of the two approaches. Table 2-4. Run times of RR-test generation for old and new approaches. Circuit # of inputs # of outputs # of levels # of paths # of surrogates Run time (mins) (old approach) Run time (mins) (new approach ) S298 17 20 14 231 3,295,974 12 8 S349 24 26 29 365 23,438,096 150 56 S420 35 18 43 369 30,809,540 238 100 S444 24 27 18 535 30,634,424 166 64 S510 25 13 17 369 14,879,752 132 72 S820 23 24 12 492 20,428,284 312 192 S1488 14 25 21 962 206,748,592 5796 2796 2.5 Conclusions For the first time, an approach for testing for crosstalk-induced delay faults in the presence of multiple gate delay faults is proposed. The approach is based on generating tests for the corresponding surrogates the requirements of which are completely timing- independent. 46 Experimental results show relatively low coverage of crosstalk sites in benchmark circuits. The reason is that for many surrogates, two-pattern input sequences that satisfy highly restricted requirements of an RR-test do not exist. In other words, many surrogates are RR-untestable. A similar situation occurs in testing for path delay faults, where many of the paths are R-untestable [13][20]. Furthermore, for some of the covered crosstalk sites, costs of test generation and test application is high due to large number of surrogates involved. Certain realistic assumptions about the nature of defects and process variations and the resulting gate delay faults can be made that result in higher coverage of crosstalk sites and lower test generation and test application costs. In Chapter 4, these assumptions and their ramifications are introduced and used. 47 Figure 2-5. The general flow of the two approaches used for generating tests for surrogates. New Approach: For each target, select the IY||YO-paths one by one and perform the following steps. 1. Inject values at on-path and off-path inputs of on-path gates along the path Æ Stop if there is a CONFLICT. (No need to perform value injection, implication, etc. on any sub-path ending at the affecting line.) 2. Perform the necessary implications after the value injections. Æ Stop if there is a CONFLICT. (No need to perform value injection, implication, etc. on any sub-path ending at the affecting line.) 3. Save the status of the circuit (line values and the list of unjustified lines). Select the sub-paths ending at the affecting line one by one and perform the following steps. 4. Restore the status of the circuit (line values and the list of unjustified lines). 5. Inject values at on-sub-path and off-sub-path inputs of on-sub-path gates along the sub-path that ends at the affecting line. Æ Stop if there is a CONFLICT. 6. Perform the necessary implications after the value injections. Æ Stop if there is a CONFLICT. 7. Stop if there remains no unjustified line. Repeat the following step until it stops. 8. Using a search tree, inject a value assignment that may justify an unjustified line and perform the necessary implications afterwards. Æ Backtrack if there is a CONFLICT. Æ Stop if no unjustified line is left. Æ Stop if the entire search tree has been traversed. Old Approach: For each target, select the surrogates one by one and perform the following steps. 1. Inject values at on-sub-path and off-sub-path inputs of on-sub-path gates along the three sub- paths, ending_at_affecting, ending_at_victim, and starting_at_victim. Æ Stop if there is a CONFLICT. 2. Perform the necessary implications after value injection. Æ Stop if there is a CONFLICT. 3. Stop if there remains no unjustified line. Repeat the following step until it stops. 4. Using a search tree, inject a value assignment that may justify an unjustified line and perform the necessary implications afterwards. Æ Backtrack if there is a CONFLICT. Æ Stop if no unjustified line is left. Æ Stop if the entire search tree has been traversed. 48 Chapter 3 Testing for WRB-induced delay faults 3.1 Introduction Consider a WRB site with affecting and victim lines x and y. Under a two-pattern input sequence, WRB-induced delay fault WRB(x, y, R) is said to be induced at y if The signal implied at x, S x , is at logic-0 in some interval of time, There exists a rising transition in S y the arrival time of which is delayed compared to the situation where the WRB did not exist, and The magnitude of the WRB-induced slow-down is large enough to affect circuit’s temporal behavior. WRB-induced delay fault WRB(x, y, F) can be defined in a similar way. The effect of the WRB-induced delay fault at y might propagate to circuit outputs and cause timing errors. It is realistic to assume that only one WRB site might exist in a fabricated circuit because for any process with reasonable yield, it is very unlikely that multiple bridges exist in a fabricated circuit [48][22][46][47][56][57][58]. In this dissertation, we make the same assumption. In this chapter, an approach for testing for WRB-induced delay faults is presented. Using this approach, in conjunction with each suspected WRB site 1 , under certain circumstances, tests can be generated that guarantee testing for WRB- induced delay faults in the sense that if a fabricated circuit passes such tests, it can be 1 At a WRB site, the WRB-induced slow-down or speed-up at the affecting line is negligible (refer to Section 1.3 for the definition of a “WRB site”). 49 concluded that no timing error occurs in the circuit under any possible two-pattern input sequence. No existing approach generates tests that can provide such a guarantee. Our approach makes similar assumptions to those made in Chapter 2 in conjunction with testing for crosstalk-induced delay faults. In particular, the MGDF and the pin-to- pin delay model are assumed 1 . Our approach assumes that no static logic error occurs in the circuit and the suspected bridge sites might only affect temporal behavior of the circuit. It also assumes that no path delay fault exists on the FS-testable logical paths that do not pass through the victim line. In other words, it is assumed that tests generated by our approach are used after each fabricated circuit passes logic testing (including testing for bridge- induced logical faults) and classical delay testing. Our approach focuses on WRB sites for which the affecting and victim lines are not circuit inputs or outputs and are not in transitive fan-in of each other. During the search for a test that invokes a WRB-induced delay fault at a WRB site and propagates the delay effect to circuit outputs and thereby causes timing errors, it is not known a priori whether a WRB-induced delay fault can actually be invoked at the site. Therefore, the term “WRB slow-down target” or “WRB delay target” is used in test generation methodology. In conjunction with WRB slow-down target WRB(x, y, R) (or WRB(x, y, F)), under a two-pattern input sequence, whether or not a WRB-induced delay fault is created at y depends on the signal implied at x, S x , the transition invoked in S y and its arrival time both of which depend on the delay values along propagation 1 In the presence of gate delay faults at unknown locations and with unknown sizes, nominal pin-to-pin delay values are of no use and only the assumptions underlying the pin-to-pin delay model are utilized. 50 sub-paths from circuit inputs to x and y (refer to Appendix A, Section A.2). If the delayed transition at y is propagated to circuit outputs, the arrival time of such transitions at the outputs depend on the arrival time of the delayed transition at y and the delay values along propagation sub-paths from y to the outputs (refer to Appendix A, Section A.2). In other words, whether or not a two-pattern input sequence is a test for the WRB slow-down target depends on the delay values along sub-paths from circuit inputs to y and x and sub-paths from y to circuit outputs. Under the MGDF, delay values along such sub-paths are not known. Therefore, generating tests for WRB slow-down targets must be done in a timing-independent manner. The organization of the rest of this chapter is as follows. In Section 3.2, the timing- independent test generation methodology for WRB slow-down targets that we have developed is presented. The ATPG presented in Section 2.3 has been modified to incorporate the developed methodology (Section 3.3). Experimental results are reported in Section 3.4. Section 3.5 summarizes the key conclusions. 3.2 Test generation methodology for WRB slow-down targets 3.2.1 Terminology In conjunction with a WRB site, the terms IX-, IY-, and YO-sub-path, on-IX-, on- IY-, and on-YO-sub-path line, on-IX-, on-IY-, and on-YO-sub-path gate, logical IX-, IY-, and YO-sub-path, IX-, IY-, and YO-parity, logical IX-, IY-, and YO-direction, delay of a logical IX-, IY-, and YO-sub-path, and logical IY||YO-path are defined similar to the corresponding terms defined in Section 2.2.1 in conjunction with a 51 crosstalk site. An example circuit with a WRB site and three corresponding IX-, IY-, and YO-sub-paths is shown in Figure 3-1. y b a c d g 1 g 2 g 3 g 4 g 6 x g 5 e h IX 1 IY 1 YO 1 Figure 3-1. An example illustrating a WRB site and three corresponding IX-, IY-, and YO-sub- paths. Throughout Section 3.2, we focus on a WRB site with affecting and victim lines x and y with n IX-sub-paths, IX 1 , IX 2 , …, IX n , m IY-sub-paths, IY 1 , IY 2 , …, IY m , and p YO-sub-paths, YO 1 , YO 2 , …, YO p . 3.2.2 Macro-surrogate In conjunction with WRB(x, y, R), m × p macro-surrogates are defined as pairs of logical sub-paths RR (IY , YO ) jk , j = 1, …, m, and k = 1, …, p. For example, for WRB(x, y, R) in the example shown in Figure 3-1, RR 11 (IY , YO ) is a macro-surrogate. In conjunction with WRB(x, y, F), m × p macro-surrogates are defined as pairs of logical sub-paths FF (IY , YO ) jk , j = 1, …, m, and k = 1, …, p. A macro-surrogate is nothing but a logical IY||YO-path (with y as the direction-reference). Ahead, it will become clear why we preferred to use the term macro-surrogate instead. In conjunction with WRB(x, y, R) (in conjunction with a rising transition in S y ), the magnitude of the WRB-induced slow-down is at the maximum possible, denoted by R WRB max-sd (“sd” denotes slow-down), when S x is static logic-0 (refer to Appendix D for more details). Similarly, in conjunction with WRB(x, y, F) (in conjunction with a 52 falling transition in S y ), the magnitude of WRB-induced slow-down is at the maximum possible, denoted by F WRB max-sd , when S x is static logic-1. A delay is associated with each macro-surrogate RR (IY , YO ) jk MS = , denoted by d MS , and is defined as R R IY YO R WRB d= d max- d j k MS sd ++ . A delay is also associated with each macro-surrogate FF (IY , YO ) jk MS = and is defined as F F IY YO F WRB d= d max- d j k MS sd ++ . Under the MGDF, a macro-surrogate delay fault exists on a macro-surrogate if the delay of the macro-surrogate, due to the presence of gate delay faults along the two sub- paths, is greater than t S . Existence of macro-surrogate delay faults on macro-surrogates might cause timing errors in the circuit. 3.2.3 Surrogates corresponding a macro-surrogate For each macro-surrogate RR (IY , YO ) jk , 2 × n surrogates are defined as triplets of logical sub-paths RR R (IX , IY , YO ) ij k and FR R (IX , IY , YO ) ij k , i = 1, …, n. Similarly, for each macro-surrogate FF (IY , YO ) jk , 2 × n surrogates are defined as triplets of logical sub-paths RF F (IX , IY , YO ) ij k and FF F (IX , IY , YO ) ij k , i = 1, …, n. In conjunction with WRB(x, y, R) (in conjunction with a rising transition in S y ), for a situation where S x is a clean rising transition, the WRB-induced ∆-delay (refer to Section 1.3) is represented by a function of the skew between the two transitions, R, R WRB (skew) ∆ (refer to Appendix D for more details). For a situation where S x is a 53 clean falling transition, the WRB-induced ∆-delay is represented by the function R, F WRB (skew) ∆ . Similarly, in conjunction with WRB(x, y, F) (in conjunction with a falling transition in S y ), the WRB-induced ∆-delay is represented by functions F, R WRB (skew) ∆ and F, F WRB (skew) ∆ when S x is a clean rising and a clean falling transition, respectively. (Refer to Appendix D for more details.) A delay is associated with each surrogate RR R (IX , IY , YO ) ij k S = , denoted by d S , and is defined as RR RR IY IY IX YO R, R WRB d= d (d d ) d jj ik S +∆ − + . A delay is also associated with each surrogate FR R (IX , IY , YO ) ij k S = , and is defined as RR FR IY IY IX YO R, F WRB d= d (d d ) d jj ik S +∆ − + . Delays are also associated with surrogates RF F (IX , IY , YO ) ij k S = and FF F (IX , IY , YO ) ij k S = and are defined in a similar way. For each surrogate RR R (IX , IY , YO ) ij k S = corresponding RR (IY , YO ) jk MS = , RR RR IY IY YO YO RR WRB WRB d dmax- d d d max- d jj kk MS S su sd −+ ≤≤ + + , where R WRB max-su denotes the maximum possible magnitude of the WRB-induced speed-up in conjunction with WRB(x, y, R) (“su” denotes speed-up). In conjunction with WRB(x, y, R) (in conjunction with a rising transition in S y ), when S x is static logic- 1, the magnitude of the WRB-induced speed-up is R WRB max-su . (Refer to Appendix D for more details.) Similar inequalities can be written in conjunction with any surrogate corresponding any macro-surrogate. 54 Under the MGDF, a surrogate delay fault exists on a surrogate if the delay of the surrogate, due to the presence of gate delay faults along the three sub-paths, is greater than t S . Existence of surrogate delay faults on surrogates might cause timing errors in the circuit. 3.2.4 FS-test for a macro-surrogate As mentioned before, a macro-surrogate is a logical IY||YO-path. Functional sensitization test (FS-test) for a macro-surrogate is defined as in Section 1.1.2.1. If an FS-test exists for a macro-surrogate, the macro-surrogate is called FS-testable. Else, it is called FS-untestable. A two-pattern input sequence under which a timing error is created at the output of a macro-surrogate when any macro-surrogate delay fault exists on the macro-surrogate while macro-surrogate or surrogate delay faults might exist on other macro-surrogates and surrogates is called a detecting-test for the macro-surrogate. When a fabricated circuit passes a detecting-test for a macro-surrogate, it can be concluded that no macro- surrogate delay fault exists on the macro-surrogate. (Note that when a fabricated circuit fails a detecting-test for a macro-surrogate, it cannot be concluded that a macro- surrogate delay fault necessarily exists on the macro-surrogate since the timing error might have been caused by macro-surrogate or surrogate delay faults on other macro- surrogates or surrogates.) Counterexamples can be used to show that FS-tests for macro-surrogates are not detecting-tests for macro-surrogates. 55 3.2.5 Robust-plus test for a macro-surrogate Definition: For a macro-surrogate RR (IY , YO ) jk , a two-pattern input sequence that is an R-test for RR IY || YO jk and invokes a static logic-0 at x is called a robust-plus test (R + -test). Similarly, for a macro-surrogate FF (IY , YO ) jk , an R + -test is a two-pattern input sequence that is an R-test for FF (IY , YO ) jk and invokes a static logic-1 at x. If an R + -test exists for a macro-surrogate, the macro-surrogate is called R + -testable. Else, it is called R + -untestable. As can be seen, requirements that a two-pattern input sequence must satisfy in order to be an R + -test for a macro-surrogate are a superset of the requirements that need to be satisfied to make the two-pattern input sequence an FS- test for the macro-surrogate. Therefore, a necessary condition for a macro-surrogate to be R + -testable is that the macro-surrogate is FS-testable. If a macro-surrogate is FS- untestable, it cannot be R + -testable. Theorem 3-1: An R + -test for an FS-testable macro-surrogate is a detecting-test for the macro- surrogate. (Proof is presented in Appendix D, Section D.2.) It should be noted that for a two-pattern input sequence to be an R + -test for a macro- surrogate, no timing requirement needs to be satisfied. In other words, requirements of R + -tests are defined in a timing-independent manner. 56 3.2.6 FS-test and RR-test for a surrogate FS-test and RR-test for a surrogate defined in association with a macro-surrogate in conjunction with a WRB target are defined similar to FS-test and RR-test for a surrogate defined in conjunction with a crosstalk target (refer to Section 2.2.4 and 2.2.5). The terms “FS-testable”, “FS-untestable”, “RR-testable”, “RR-untestable”, and “detecting-test” are defined in a similar way. Theorem 3-2: An RR-test for an FS-testable surrogate is a detecting-test for the surrogate. (Proof is presented in Appendix D, Section D.2.) Note that an RR-test for a surrogate defined in association with a macro-surrogate is not a detecting-test for the macro-surrogate (does not necessarily create a timing error if a macro-surrogate delay fault exists on the macro-surrogate). If all the surrogates corresponding a macro-surrogate are RR-testable, a set of RR- tests for all the surrogates is called an RR-test-set for the macro-surrogate. When a fabricated circuit passes an RR-test-set for a macro-surrogate, it can be concluded that no surrogate delay fault exists on the corresponding surrogates but it can not be concluded that no macro-surrogate delay fault exists on the macro-surrogate. 3.2.7 Testing for WRB-induced delay faults using tests for the corresponding macro-surrogates Under the assumptions made in Section 3.1, in particular, under the MGDF and the pin-to-pin delay model, 57 Theorem 3-3: If no macro-surrogate delay fault exists on the macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix D, Section D.2.) In the meantime, existence of macro-surrogate delay faults on FS-untestable macro- surrogates, as long as no macro-surrogate delay fault exists on FS-testable macro- surrogates, does not cause any timing error in the circuit either. In other words, Theorem 3-4: If no macro-surrogate delay fault exists on the FS-testable macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix D, Section D.2.) Corollary 3-1: If all the macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F) are FS-untestable, no timing error might occur in the circuit. (Such a WRB site is called an FS-untestable WRB site. A WRB site that is not FS- untestable is called FS-testable.) From what stated above it can be concluded that, in conjunction with a WRB site that is not FS-untestable, testing for WRB-induced delay faults can be carried out by verifying whether a macro-surrogate delay fault exists on each FS-testable macro- surrogate defined in association with WRB targets WRB(x, y, R) and WRB(x, y, F). As 58 mentioned in Section 3.2.5, an R + -test for a macro-surrogate can verify whether there exists any macro-surrogate delay fault on the macro-surrogate. Therefore, Theorem 3-5: If a circuit with an FS-testable WRB site passes a test-set that contains an R + -test for each FS-testable macro-surrogate defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix D, Section D.2.) A WRB site for which such a test-set exists (in other words, a WRB site for which all the FS-testable macro-surrogates are R + -testable) is called an R + -testable WRB site. For an R + -testable WRB site, such a test-set is guaranteed to test fabricated copies of the circuit for WRB-induced delay faults. In conjunction with an R + -testable WRB site, the number of invocations of test generator is m × p, in the worst case. 3.2.7.1 Least-restricted test for a macro-surrogate In conjunction with a macro-surrogate RR (IY , YO ) jk , the following set of requirements are the least restricted set of requirements for a two-pattern input sequence under which a rising transition might be invoked in S y with WRB-induced slow-down of R WRB max-sd and the rising transition might be propagated to the output of R YO k . S a , where a is the input of R IY j , is a transition that matches a’s logical IY- direction (i.e., if a has rising (falling) logical IY-direction, S a is a rising (falling) transition), In conjunction with every on-IY- or on-YO-sub-path gate g, for every off-path input b, S b ≠ Static cv g , and 59 S x is static logic-0. A two-pattern input sequence that satisfies the above set of requirements is called a least-restricted test (LR-test) for the macro-surrogate. If an LR-test exists for a macro- surrogate, the macro-surrogate is called LR-testable. Else, it is called LR-untestable. Theorem 3-4 states that if no macro-surrogate delay fault exists on the FS-testable macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. Existence of macro- surrogate delay faults on FS-testable LR-untestable macro-surrogates does not cause a timing error either as long as no surrogate delay fault exists on the surrogates corresponding the FS-testable LR-untestable macro-surrogates and no macro-surrogate delay fault exists on the FS-testable LR-testable macro-surrogates. In other words, Theorem 3-6: If no macro-surrogate delay fault exists on the FS-testable LR-testable macro- surrogates and no surrogate delay fault exists on the surrogates corresponding the FS- testable LR-untestable macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix D, Section D.2.) From what stated above it can be concluded that, in conjunction with a WRB site that is not FS-untestable, testing for WRB-induced delay faults can be done by verifying whether a macro-surrogate delay fault exists on each FS-testable LR-testable macro- surrogate and by verifying whether a surrogate delay fault exists on each surrogate corresponding each FS-testable LR-untestable macro-surrogate defined in association with WRB targets WRB(x, y, R) and WRB(x, y, F). As mentioned in Section 3.2.6, 60 verifying whether no surrogate delay fault exists on the surrogates corresponding a macro-surrogate can be done by applying a corresponding RR-test-set. Therefore, Theorem 3-7: If a circuit with an FS-testable WRB site passes a test-set that contains an R + -test for each FS-testable LR-testable macro-surrogate and an RR-test-set for each FS-testable LR-untestable macro-surrogate defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. (Proof is presented in Appendix D, Section D.2.) A WRB site for which such a test-set exists (in other words, a WRB site for which all the FS-testable LR-testable macro-surrogates are R + -testable and all the surrogates corresponding all the FS-testable LR-untestable macro-surrogates are RR-testable) is called an R + -RR-testable WRB site. For an R + -RR-testable WRB site, such a test-set is guaranteed to test fabricated copies of the circuit for WRB-induced delay faults. In conjunction with an R + -RR-testable WRB site, the number of invocations of test generator is n × m × p, in the worst case, and is m × p, in the best case. Note that for an R + -testable WRB site, all the FS-testable macro-surrogates are LR- testable. 3.3 Test pattern generation The ATPG presented in Section 2.3 has been modified to incorporate the proposed test generation methodology for WRB slow-down targets. In conjunction with each WRB site, we pick macro-surrogates one by one. For each picked macro-surrogate, we start by checking whether the macro-surrogate is FS- 61 untestable (this is done by attempting to find an FS-test for the macro-surrogate). If the macro-surrogate is FS-untestable, we ignore the macro-surrogate and pick the next macro-surrogate. Else, we check whether the macro-surrogate is LR-testable (this is done by attempting to find an LR-test for the macro-surrogate). If the macro-surrogate is LR-testable, we attempt to search for an R + -test for the macro-surrogate. If an R + -test is found, we add it to the test-set but if the search fails, the macro-surrogate is presumed R + -untestable and our methodology cannot guarantee testing for WRB-induced delay faults. If the macro-surrogate is LR-untestable, we attempt to search for an RR-test-set for the macro-surrogate. If an RR-test-set is found, we add it to the test-set but if the search fails (because a corresponding surrogate is RR-untestable), our methodology cannot guarantee testing for WRB-induced delay faults. 3.4 Experimental Results The test generation flow presented in Section 3.3 is used to generate tests for WRB sites (with the specifications stated in Section 3.1) in ISCAS 89 benchmark circuits. Results are shown in Table 3-1. The column labeled as “RR only” shows the number of WRB sites for which all the FS-testable macro-surrogates are LR-untestable (for such macro-surrogates, corresponding RR-test-sets are used). The last column shows the total number of WRB sites for which our methodology generates test-sets that are guaranteed to test the fabricated copies of the circuit for WRB-induced delay faults. 62 Table 3-1. Coverage. Coverage R + -RR-testable WRB sites Circuit Total #of WRB sites with the specifications stated in Section 3.1 R + -testable WRB sites RR only Combination of RR and R + Total S349 109,718 61,672 (56.21%) 2,732 (2.49%) 5,014 (4.57%) 69,418 (63.27%) S444 183,876 120,935 (65.77%) 7,649 (4.16%) 9,047 (4.92%) 137,631 (74.85%) S510 245,930 83,911 (34.12%) 10,723 (4.36%) 20,560 (8.36%) 115,194 (46.84%) S641 323,964 210,117 (62.08%) 9,201 (2.84%) 13,736 (4.24%) 224,054 (69.16%) S820 657,714 320,438 (48.72%) 61,628 (9.37%) 52,288 (7.95%) 434,354 (66.04%) As can be seen, coverage is considerably high. It is also important to note that for R + - testable WRB sites (which constitute fairly high percentage of the sites) the number of invocations of test generator is #of IY-sub-paths × #of YO-sub-paths. 3.5 Conclusions For the first time, an approach for testing for WRB-induced delay faults in the presence of multiple gate delay faults is proposed. The approach is based on generating tests for the corresponding macro-surrogates and surrogates, the requirements of which are completely timing-independent. Experimental results show that the proposed approach provides high coverage. The run-time complexity and test-set sizes are also substantially lower than those for crosstalk slow-down. Certain realistic assumptions about the nature of defects and process variations and the resulting gate delay faults can be made that result in higher coverage of WRB sites 63 and also lower test generation and test application costs. In Chapter 4, these assumptions and their ramifications are introduced and used. 64 Chapter 4 Testing for crosstalk- and WRB-induced delay faults under constrained gate delay fault assumptions 4.1 Introduction In Chapter 2 and Chapter 3, under the MGDF, timing-independent approaches for testing for crosstalk- and WRB-induced delay faults were proposed. Experimental results reported in conjunction with these approaches showed that considerable percentage of crosstalk and WRB sites in the experimented benchmark circuits are not covered by the proposed approaches and for some covered sites test generation and test application costs are high. Under the MGDF, it is assumed that multiple gate delay faults might exist in each fabricated circuit but no assumption is made about the locations, sizes, and the multiplicity of gate delay faults Certain realistic assumptions can be made about the nature of defects and process variations and the resulting gate delay faults that might result in higher coverage of crosstalk and WRB sites and also lower test generation and test application costs. For example, it can be assumed that only one defect exists in a combinational block of logic in a fabricated circuit which results in a single gate delay fault. This assumption, referred to as the single gate delay fault assumption (SGDF), is realistic because with reasonable yield values, it is very unlikely that more than one defect exists in a combinational block of logic in a fabricated circuit [56][57][58]. Alternatively, it can be assumed that process variations result in gates that have correlated delay values. This 65 assumption, referred to as the correlated process variations assumption (CPV), is likely to be true in realistic situations [41][44]. It can also be assumed that the accumulation of extra delays along any logical path or sub-path is upper-bounded. This assumption, referred to as the bounded maximum extra delay assumption (BMD), is the basis for all path selection methods which focus on the longer logical paths and ignore the shorter ones during delay test generation [35][6]. These assumptions are referred to as constrained gate delay fault assumptions in general, as opposed to the MGDF that makes no assumptions about the location, size and the multiplicity of gate delay faults in fabricated circuits. (MGDF is a fairly unconstrained assumption.) Under the MGDF, a test-set that contains an RR-test for each FS-testable surrogate defined in association with a crosstalk site is guaranteed to test for crosstalk-induced delay faults (refer to Theorem 2-4). An RR-test for a surrogate makes the circuit fail (creates a timing error in the circuit) if any surrogate delay fault exists on the surrogate. In this chapter, we will show that under constrained gate delay fault assumptions, a test that is not an RR-test for a surrogate or a test-set that does not contain an RR-test for a surrogate might also be guaranteed to make the circuit fail when any surrogate delay fault exists on the surrogate. A test or a test-set that is guaranteed to make the circuit fail when any surrogate delay fault exists on a surrogate is said to S-cover the surrogate. (An RR-test for a surrogate S-covers the surrogate under the MGDF and also under constrained gate delay fault assumptions which are special cases of the MGDF.) When a circuit passes a test or a test-set that S-covers a surrogate, it can be concluded that no surrogate delay fault exists on the surrogate. 66 Consider a crosstalk site with the specifications stated in Section 2.1 with affecting and victim lines x and y. Theorem 4-1: Under a constrained gate delay fault assumption, if a circuit with an FS-testable crosstalk site passes a test-set that S-covers every FS-testable surrogate defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. Proof: When the circuit passes the test-set, it can be concluded that no surrogate delay fault exists on the FS-testable surrogates. Therefore, according to Theorem 2-3, no timing error might occur in the circuit. ■ Using the above theorem might result in higher coverage of crosstalk sites and also lower test generation and test application costs. Examples are given below. ___________________________________________________________________ Example 4-1: Suppose an FS-testable surrogate S 1 defined in association with a crosstalk site is not RR-testable but all other FS-testable surrogates are RR-testable. Under the MGDF, the approach proposed in Chapter 2 does not guarantee testing for crosstalk- induced delay faults. In other words, the site is not identified as covered by the proposed approach. However, this site might be identified as covered under a constrained gate delay fault assumption. Suppose that under a constrained gate delay 67 fault assumption, S 1 is S-covered with an RR-test for surrogate S 2 , T 1 . (Later in the chapter, it will become clear how such a thing is possible.) A test-set including T 1 and RR-tests for all other FS-testable surrogates S-covers all the FS-testable surrogates defined in association with the crosstalk site and thus, according to According to Theorem 4-1, is guaranteed to test for crosstalk-induced delay faults. Therefore, the site is identified as covered (thus higher coverage). _______________________________________________________________________________________________________________________________________ ___________________________________________________________________ Example 4-2: In the case of Example 4-1, suppose S 1 is RR-testable but still is S-covered by T 1 , an RR-test for S 2 . Similar to the situation in Example 4-1, a test-set including T 1 and RR-tests for all other FS-testable surrogates (excluding S 1 ) S-covers all the FS- testable surrogates defined in association with the crosstalk site and thus, according to Theorem 4-1, is guaranteed to test for crosstalk-induced delay faults. This is achieved without expending any effort for generating an RR-test for S 1 (thus lower test generation cost) and no RR-test for S 1 needs to be applied to the circuit during the testing process (thus lower test application cost). _______________________________________________________________________________________________________________________________________ A similar discussion can be presented in conjunction with testing for WRB-induced delay faults. Consider a WRB site with the specifications stated in Section 3.1 with affecting and victim lines x and y. Theorem 4-2: Under a constrained gate delay fault assumption, if a circuit with an FS-testable WRB site passes a test-set that MS-covers each FS-testable LR-testable macro-surrogate and 68 S-covers all the surrogates corresponding each FS-testable LR-untestable macro- surrogate defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. Proof is straight-forward using Theorem 3-6. Similar to the case of the crosstalk site, using the above theorem might result in higher coverage of WRB sites as well as lower test generation and test application costs. In this chapter, in conjunction with each of the three constrained gate delay fault assumptions introduced above, situations under which a test other than an RR-test for a surrogate or a test-set that does not contain an RR-test for a surrogate S-covers the surrogate are investigated. Similarly, situations under which a test other than an R + -test for a macro-surrogate or a test-set that does not contain an R + -test for a macro-surrogate MS-covers the macro-surrogate are investigated. Throughout this chapter, we assume that a crosstalk site or a WRB site (with the specifications stated in Sections 2.1 and 3.1, respectively) with affecting and victim lines x and y, IX-sub-paths, IX 1 , IX 2 , …, IX n , IY-sub-paths, IY 1 , IY 2 , …, IY m , and YO- sub-paths, YO 1 , YO 2 , …, YO p exist in the circuit. In the case of the crosstalk site, it is assumed that the coupling capacitance, c, is known. Furthermore, it is assumed that the functions R C () sd and F C () sd are known. (These two functions are monotonically rising in the skew range of (- ∞, skew 0 R ) and (- ∞, skew 0 F ), respectively, and are monotonically falling in the skew range of [skew 0 R , + ∞) and [skew 0 F , + ∞). Maximum values of the two functions, which happen at skew = skew 0 R and skew = skew 0 F are referred to as R C max-sd and F C max-sd , respectively. For simplicity and without loss of generality, we assume that skew 0 R = 0 and skew 0 F = 0.) 69 In the case of the WRB site, the bridge resistance, b r , is not known. However, it is assumed that min max bbb rrr ≤≤ , where min b r and max b r are known. It is also assumed that the functions R, R WRB (skew, ) b r ∆ , R, F WRB (skew, ) b r ∆ , F, R WRB (skew, ) b r ∆ , and F, F WRB (skew, ) b r ∆ which represent the dependency of the WRB-induced ∆-delay to skew and the bridge resistance (refer to Sections 1.3 and 3.2.3 and also Appendix D) are known. For any fixed value of b r , R, R WRB (skew, ) b r ∆ and F, F WRB (skew, ) b r ∆ are monotonically rising in the skew range of (- ∞, + ∞). The skew value at which the two functions become zero are referred to as R, R 0 skew and F, F 0 skew , respectively. For simplicity and without loss of generality, we assume that R, R 0 skew 0 = and F, F 0 skew 0 = . Similarly, For any fixed value of b r , R, F WRB (skew, ) b r ∆ and F, R WRB (skew, ) b r ∆ are monotonically falling in the skew range of (- ∞, + ∞). The skew value at which the two functions become zero are referred to as R, F 0 skew and F, R 0 skew , respectively. For simplicity and without loss of generality, we assume that R, F 0 skew 0 = and F, R 0 skew 0 = . It is also assumed that the functions R WRB max- ( ) b sd r and F WRB max- ( ) b sd r which represent the dependency of the maximum possible WRB-induced slow-down on the bridge resistance are known. Maximums of R WRB max- ( ) b sd r and F WRB max- ( ) b sd r occur at min bb rr = . Sections 4.2, 4.3, and 4.4 focus on the correlated process variations, single gate delay fault, and bounded maximum extra delay assumptions, respectively. In Section 4.5, the procedures that we have implemented in conjunction with Sections 4.2-4.4 are introduced; experimental results are presented and discussed. 70 4.2 Correlated process variations Under the correlated process variations (CPV) assumption, it is assumed that for an input a of a gate g, RR n d . d aa gg α = , and FF n d . d aa gg β = , where R n d a g and F n d a g are the nominal rising and falling delay values, min max 0 α αα <≤≤ min max (1 ) α α ≤ ≤ , and min max 0 β ββ < ≤≤ min max (1 ) β β ≤≤ . For a logical IX-sub-path R IX i , RR R IX IX IX d ( , ) . r . f ii i αβ α β =+ , where R IX r i is equal to the sum of the nominal rising delay values of the gates along R IX i whose on-sub-path inputs have rising logical IX-directions and R IX f i is equal to the sum of the falling delay values of the gates along R IX i whose on-sub-path inputs have falling logical IX-directions. Similar formulas can be written for F IX i , R IY j , F IY j , R YO k , and F YO k . Organization of this section is as follows. In Section 4.2.1, it is discussed that under the CPV, we might be able to compare delays of surrogates and macro-surrogates with t S or with each other. The fact that we might be able to compare delays of surrogates (macro-surrogates) with t S allows us to filter out some surrogates (macro-surrogates) from the list of the surrogates (macro-surrogates) that need to be S-covered (MS- covered) in conjunction with Theorem 4-1 (Theorem 4-2). Details are presented in Section 4.2.2. The fact that we might be able to compare delays of surrogates (macro- surrogates) with each other allows us to identify situations where a surrogate (macro- 71 surrogate) is S-covered (MS-covered) by an RR-test (R + -test) for another surrogate (macro-surrogate). Details are presented in Section 4.2.3. Under the CPV, we might be able to identify determinate intervals of logic-0 and logic-1 in the signals implied at circuit lines. This might allow us to identify a test that satisfies less restricted requirements than those satisfied by an RR-test for a surrogate (R + -test for a macro-surrogate) as a detecting-test for the surrogate (macro-surrogate) which S-covers (MS-covers) the surrogate (macro-surrogate). We refer to such a test as a relaxed RR-test (relaxed R + -test) for the surrogate (macro-surrogate). Signals implied at circuit lines under the CPV and determinate and uncertain intervals are discussed in Section 4.2.4. Relaxed tests are discussed in Section 4.2.5. Finally the process of generating relaxed tests is discussed in Section 4.2.6. 4.2.1 Comparing delays of surrogates and macro-surrogates with t S or with each other Under the CPV, we might be able to compare delays of surrogates and macro- surrogates with t S or with each other. An example is given below. ___________________________________________________________________ Example 4-3: Consider macro-surrogates RR 1 (IY , YO ) jk MS = and RR 2 (IY , YO ) bc MS = . Delays of MS 1 and MS 2 can be written as R R 1 RR RR IY YO R WRB IY IY YO YO R WRB d ( , , ) d (, ) max- ( ) d (, ) . (r r ) . (f f ) max- ( ), and j k jj kk MS bb b rsdr sd r αβ αβ αβ αβ =+ + = ++ + + RR 2 RR R R IY YO R WRB IY YO IY YO R WRB d ( , , ) d (, ) max- ( ) d (, ) . (r r ) . (f f ) max- ( ). bc bc b c MS bb b rsdr sd r αβ αβ αβ αβ =+ + = ++ + + 72 Maximum value of 1 d(,,) MS b r αβ occurs at max α α = , max β β = , and min bb rr = . Therefore, if 1 max max min S d( , , ) t MS b r αβ < , i.e., if RR RR IY IY YO YO R max max WRB min S . (r r ) . (f f ) max- ( ) t jj kk b sd r αβ ++ + + < , then 1 S d(,,) t MS b r αβ < for all min max (), αααα ≤≤ all min max (), ββββ ≤ ≤ and all b r min max () bbb rrr ≤≤ . Furthermore, suppose R RR R IY IY YO YO rr r r j bc k +> + , and R RR R IY IY YO YO ff f f j bc k +< + . Let us define R RR R R RR R R RR R IY IY YO YO IY IY YO YO 0 IY IY YO YO 0 D d (, ) d (, ) d (, ) d (, ) .(r r ) (r r ) . (f f ) (f f ) j bc k j bc k j bc k αβ αβ αβ αβ α β > < =+ − − = ⎡⎤ ⎢⎥ +− + + ⎢⎥ ⎣⎦ +− + . ⎡ ⎤ ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ Note that 21 Dd ( , , ) d ( , , ) MS MS bb rr αβ αβ =− . Minimum value of D, min-D, occurs at min α α = and max β β = . Therefore, if min-D > 0, or in other words, if 73 R RR R R RR R IY IY YO YO min IY IY YO YO max .(r r ) (r r ) . (f f ) (f f ) 0 j bc k j bc k α β ⎡⎤ +− + + ⎢⎥ ⎣⎦ ⎡⎤ + −+ > ⎢⎥ ⎣⎦ then D > 0 for all min max () αααα ≤ ≤ , all min max () ββββ ≤ ≤ , and all b r min max () bbb rrr ≤≤ . In such a situation, 12 d(,,) d (,,) MS MS bb rr αβ αβ ≤ for all α min max () α αα ≤≤ , all min max () ββββ ≤ ≤ , and all b r min max () bbb rrr ≤≤ . _______________________________________________________________________________________________________________________________________ More details about the situations where delay of a surrogate (a macro-surrogate) is less than t S or delay of another surrogate (macro-surrogate) under the CPV will be presented ahead. Note that under the MGDF, such comparisons cannot be made. 4.2.2 Non-criticality 4.2.2.1 Crosstalk sites As mentioned in Section 4.2.1, under the CPV, we might be able to compare delays of surrogates with t S . Surrogate S is said to be non-critical if S dt S < . Under the CPV, no surrogate delay fault might exist on a non-critical surrogate. In conjunction with Theorem 4-1, such a surrogate can be filtered out from the list of the surrogates that must be S-covered. A surrogate that is not non-critical is said to be potentially-critical. Theorem 4-3: Under the CPV, if a circuit with an FS-testable crosstalk site passes a test-set that S- covers each FS-testable potentially-critical surrogate defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. 74 Proof is straight-forward using Theorem 4-1 and the fact that every other FS-testable surrogate is non-critical and, under the CPV, no surrogate delay fault exists on any one of them. Filtering out non-critical surrogates might result in higher coverage of crosstalk sites and also lower test generation and test application costs. Examples are given below. ___________________________________________________________________ Example 4-4: Suppose no test-set S-covers FS-testable surrogate S 1 defined in association with a crosstalk site but all other FS-testable surrogates are RR-testable and thus are S- covered by their corresponding RR-tests. Under the MGDF, the approach proposed in Chapter 2 does not guarantee testing for crosstalk-induced delay faults. In other words, the site is not identified as covered by the proposed approach. However, this site might be identified as covered under the CPV. Suppose that under the CPV, it can be verified that 1 S dt S < . According to Theorem 4-3, a test-set that contains RR-tests for all other FS-testable surrogates is guaranteed to test for crosstalk- induced delay faults and thus the site is identified as covered (thus higher coverage). _______________________________________________________________________________________________________________________________________ ___________________________________________________________________ Example 4-5: In the case of Example 4-4, suppose S 1 is also RR-testable but, under the CPV, it can be verified that 1 S dt S < . According to Theorem 4-3, a test-set that contains RR-tests for all other FS-testable surrogates is guaranteed to test for crosstalk- induced delay faults and thus the site is identified as covered. No attempt for generating an RR-test for S 1 needs to be made (thus lower test generation cost) and 75 no RR-test for S 1 needs to be applied to the circuit during the testing process (thus lower test application cost). _______________________________________________________________________________________________________________________________________ 4.2.2.1.1 Non-critical situations Let us focus on C(x, y, R). Let us focus on FR R 1 (IX , IY , YO ) ij k S = . Lemma 4-1: Under the CPV, S 1 is non-critical if 1 RR F R IY IY IX 1R max max C YO max max S d( , ) d (,)d(,) d ( , ) t . jj i k Usd α β αβ αβ αβ ⎡⎤ ⎛⎞ +− ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ + < (If the above inequality holds true, 1 S dt S < for all α , min max α αα ≤ ≤ , and all β , min max β ββ ≤≤ .) Proof is straight-forward. In Appendix E, Section E.1, an approach for calculating an upper-bound for R F IY IX R C d ( ,) d ( ,) j i sd αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ is presented where depending on the values of R F IY IX (r r ) j i − and R F IY IX (f f ) j i − being positive or negative, an upper-bound is either calculated as the value of R F IY IX R C d ( ,) d ( ,) j i sd αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ at one of the corner points min min (, ) α β , min max (, ) α β , or max min (, ) α β , 1 All through this dissertation, U[] indicates upper-bound. 76 or as R C max-sd . An example is given below. ___________________________________________________________________ Example 4-6: Suppose R F IY IX rr 0 j i −> and R F IY IX ff 0 j i − > . In such a situation, R F IY IX R C d ( ,) d ( ,) j i Usd αβ αβ ⎡⎤ ⎛⎞ − ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ is calculated as the value of R F IY IX R C d ( ,) d ( ,) j i sd αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ at the corner point min min (, ) α β (refer to Appendix E, Section E.1). Therefore, if RR F R IY IY IX R max max C min min min min YO max max S d( , ) d ( , )d( , ) d ( , ) t , jj i k sd α β αβ αβ αβ ⎛⎞ +− ⎜⎟ ⎝⎠ +< then S 1 is non-critical. _______________________________________________________________________________________________________________________________________ Similar discussion can be presented in conjunction with C(x, y, F). 4.2.2.2 WRB sites As mentioned in Section 4.2.1, under the CPV, we might be able to compare delays of macro-surrogates and surrogates with t S . Macro-surrogate MS 1 is said to be non- critical if 1 S dt MS < . Under the CPV, no macro-surrogate delay fault exists on a non- critical macro-surrogate. If such a macro-surrogate is LR-testable, it can be filtered out from the list of macro-surrogates that must be MS-covered in conjunction with Theorem 4-2; else, it can be filtered out from the list of the macro-surrogates whose surrogates must be S-covered. A macro-surrogate that is not non-critical is said to be potentially- critical. Similarly, surrogate S 1 corresponding an FS-testable LR-untestable macro- surrogate is said to be non-critical if 1 S dt S < . Under the CPV, no surrogate delay fault exists on a non-critical surrogate. Such a surrogate can be filtered out from the list of 77 surrogates that must be S-covered in conjunction with Theorem 4-2. A surrogate that is not non-critical is said to be potentially-critical. Theorem 4-4: Under the CPV, if a circuit with an FS-testable WRB site passes a test-set that MS- covers each FS-testable LR-testable potentially-critical macro-surrogate and S-covers all the potentially-critical surrogates corresponding each FS-testable LR-untestable potentially-critical macro-surrogate defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. Proof is straight-forward using Theorem 4-2 and the fact that under the CPV, no macro- surrogate delay fault exists on non-critical macro-surrogates and no surrogate delay fault exists on non-critical surrogates. Similar to the case of crosstalk sites, filtering out non-critical macro-surrogates and surrogates might result in higher coverage of WRB sites and also lower test generation and test application costs. 4.2.2.2.1 Non-critical situations Let us focus on WRB(x, y, R) and RR 1 (IY , YO ) jk MS = . Lemma 4-2: Under CPV, MS 1 is non-critical if R R IY YO R max max WRB min max max S d( , )max- ( )d ( , )t. j k b sd r αβ αβ ++ < (If the above inequality holds true, 1 S dt MS < for all α , min max α αα ≤≤ , all β , min max β ββ ≤≤ , and all b r, min max bbb rrr ≤ ≤ .) 78 Proof is straight-forward. Now, let us focus on FR R 1 (IX , IY , YO ) ij k S = defined in association with RR (IY , YO ) jk . Lemma 4-3: Under the CPV, S 1 is non-critical if RR F R IY IY IX R, F max max WRB min YO max max S d( , ) d (,)d(,), d ( , ) t . jj i k b Ur α β αβ αβ αβ ⎡⎤ ⎛⎞ +∆ − ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ + < (If the above inequality holds true, 1 S dt S < for all α , min max α αα ≤≤ , all β , min max β ββ ≤≤ , and all b r, min max bbb rrr ≤ ≤ .) Proof is straight-forward. In Appendix E, Section E.2, an approach for calculating an upper-bound for R F IY IX R, F WRB min d(,)d (,), j i b r αβ αβ ⎛⎞ ∆− ⎜⎟ ⎝⎠ is presented where depending on the values of R F IY IX (r r ) j i − and R F IY IX (f f ) j i − being positive or negative, the upper-bound is calculated as the value of R F IY IX R, F WRB min d(,)d (,), j i b r αβ αβ ⎛⎞ ∆− ⎜⎟ ⎝⎠ at one of the corner points min min (, ) α β , min max (, ) α β , max min (, ) α β , or max max (, ) α β . Similar discussion can be presented for surrogate RR R 1 (IX , IY , YO ) ij k S = defined in association with RR (IY , YO ) jk . 79 Similar discussion can be presented in conjunction with WRB(x, y, F). 4.2.3 Delay-inferiority; delay-superiority Under the MGDF, no information is available about the relative delay values of surrogates. However, as mentioned in Section 4.2.1, under the CPV, we might be able to compare delays of surrogates with each other. Surrogate S 1 is said to be delay- inferior to surrogate S 2 if 12 dd SS ≤ . (In such a situation S 2 is said to be delay-superior to S 1 .) Theorem 4-5: If surrogate S 2 is delay-superior to surrogate S 1 and test T S-covers S 2 , then T also S- covers S 1 . Proof: If a surrogate delay fault exists on S 1 , i.e., if 1 S dt S > , there exists a surrogate delay fault on S 2 as well because 12 dd SS ≤ and thus 2 S dt S > . In such a situation, the circuit fails T because T S-covers S 2 . ■ According to what is stated above, if a surrogate S 2 is RR-testable and delay- superior to a surrogate S 1 under the CPV, an RR-test for S 2 (which S-covers S 2 ) S- covers S 1 . In other words, under the CPV, a test that is not an RR-test (and is not a relaxed RR-test, as will be introduced ahead) for a surrogate might also S-cover the surrogate. As mentioned is Section 4.1, this might result in higher coverage of crosstalk sites and also lower test generation and test application costs. 80 Similar discussion can be presented in conjunction with macro-surrogates. 4.2.3.1 Delay-superior situations for surrogates Let us focus on C(x, y, R). Let us focus on two surrogates FR R 1 (IX , IY , YO ) ij k S = and FR R 2 (IX , IY , YO ) ab c S = . Lemma 4-4: Under CPV, S 2 is delay-superior to S 1 if 1 (1) R FFR IY IX IX IY d ( ,) d ( ,) d ( ,) d ( ,) j iab αβαβ αβ αβ −= − , and (2) R RR R IY YO IY YO d ( ,) d ( ,) d ( ,) d ( ,) j kb c αβαβ αβ αβ +≤ + , Or if (3) RR FR IY IY IX YO R C d ( ,) d ( ,) d ( ,) d ( ,) jj ik Usd αβαβ αβ αβ ⎡⎤ ⎛⎞ +− + ≤ ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ RF R R IY IX IY YO 1R C d ( ,) d ( ,) d ( ,) d ( ,) ba b c Lsd αβαβαβ αβ ⎡⎤ ⎛⎞ +− + ⎜⎟ ⎢⎥ ⎝⎠ ⎣⎦ for all α , min max α αα ≤≤ , and all β , min max β ββ ≤ ≤ . (If conditions (1)&(2) or (3) hold true, 12 dd SS ≤ for all α , min max α αα ≤≤ , and all β , min max β ββ ≤≤ .) Proof is straight-forward. Condition (1) stated in the lemma is satisfied for all values of α and β if and only if R FFR IY IX IX IY rr r r j iab −= − and R FFR IY IX IX IY ff f f j iab −= − . 1 All through this dissertation, L[] indicates lower-bound. 81 In order to investigate whether conditions (2) or (3) stated in the lemma are satisfied, the following two lemmas are used. Lemma 4-5: For constant values of K ≥ 0, R 1 , F 1 , R 2 , and F 2 , inequality R 2 . α + F 2 . β + K ≤ R 1 . α + F 1 . β is satisfied for all values of α ( α min ≤ α ≤ α max ) and β ( β min ≤ β ≤ β max ) if (i) R 2 ≤ R 1 , (ii) F 2 ≤ F 1 , and (iii)The inequality is satisfied at the corner point ( α min , β min ), i.e., R 2 . α min + F 2 . β min + K ≤ R 1 . α min + F 1 . β min , Or if (i) R 2 < R 1 , (ii) F 2 > F 1 , and (iii)The inequality is satisfied at the corner point ( α min , β max ), i.e., R 2 . α min + F 2 . β max + K ≤ R 1 . α min + F 1 . β max , Or if (i) R 2 > R 1 , (ii) F 2 < F 1 , and (iii)The inequality is satisfied at the corner point ( α max , β min ), i.e., R 2 . α max + F 2 . β min + K ≤ R 1 . α max + F 1 . β min . Proof is straight-forward. 82 Lemma 4-6: For constant values of K > 0, R 1 , F 1 , R 2 , and F 2 , inequality R 2 . α + F 2 . β ≤ R 1 . α + F 1 . β + K is satisfied for all values of α ( α min ≤ α ≤ α max ) and β ( β min ≤ β ≤ β max ) if (i) R 2 ≤ R 1 , and (ii) F 2 ≤ F 1 , Or if (i) R 2 ≤ R 1 , (ii) F 2 > F 1 , and (iii)The inequality is satisfied at the corner point ( α min , β max ), i.e., R 2 . α min + F 2 . β max ≤ R 1 . α min + F 1 . β max + K, Or if (i) R 2 > R 1 , (ii) F 2 ≤ F 1 , and (iii)The inequality is satisfied at the corner point ( α max , β min ), i.e., R 2 . α max + F 2 . β min ≤ R 1 . α max + F 1 . β min + K, Or if (i) R 2 > R 1 , (ii) F 2 > F 1 , and (iii)The inequality is satisfied at the corner point ( α max , β max ), i.e., R 2 . α max + F 2 . β max ≤ R 1 . α max + F 1 . β max + K. Proof is straight-forward. 83 In order to investigate whether condition (2) stated in the Lemma 4-4 is satisfied for all values of α , min max α αα ≤≤ , and β , min max β ββ ≤ ≤ , Lemma 4-5 is used with the values K = 0, R 1 = RR IY YO rr bc + , F 1 = RR IY YO ff bc + , R 2 = R R IY YO rr j k + , and F 2 = R R IY YO ff j k + . In Appendix E, Section E.1, an approach for calculating a lower-bound for R F IY IX R C d ( ,) d ( ,) j i sd αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ is presented where depending on the values of R F IY IX (r r ) j i − and R F IY IX (f f ) j i − being positive or negative, the lower-bound is calculated as the value of R F IY IX R C d ( ,) d ( ,) j i sd αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ at one of the corner points min max (, ) α β , max min (, ) α β , or max max (, ) α β . In order to investigate whether the condition (3) stated in Lemma 4-4 is satisfied for all values of , α min max , α αα ≤ ≤ and , β min max , β ββ ≤≤ first R F IY IX R C d ( ,) d ( ,) j i Usd αβ αβ ⎡⎤ ⎛⎞ − ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ and FR IX IY R C d(,)d (,) ab Lsd αβ αβ ⎡ ⎤ ⎛⎞ − ⎜⎟ ⎢ ⎥ ⎝⎠ ⎣ ⎦ are replaced with the calculated values and then either Lemma 4-5 or Lemma 4-6 is used. If 84 R F FR IY IX R C IX IY R C d(,)d (,) d ( , ) d ( , ) , j i ab Usd Lsd αβ αβ αβ αβ ⎡⎤ ⎛⎞ −≥ ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎡ ⎤ ⎛⎞ − ⎜⎟ ⎢ ⎥ ⎝⎠ ⎣ ⎦ Lemma 4-5 is used with R F FR IY IX R C IX IY R C K d (, ) d (, ) d ( , ) d ( , ) . j i ab Usd Lsd αβ αβ αβ αβ ⎡⎤ ⎛⎞ =− − ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎡ ⎤ ⎛⎞ − ⎜⎟ ⎢ ⎥ ⎝⎠ ⎣ ⎦ Else, Lemma 4-6 is used with FR R F IX IY R C IY IX R C Kd(,)d(,) d ( , ) d ( , ) . ab j i Lsd Usd αβ αβ αβ αβ ⎡⎤ ⎛⎞ =− − ⎜⎟ ⎢⎥ ⎝⎠ ⎣⎦ ⎡ ⎤ ⎛⎞ − ⎢ ⎥ ⎜⎟ ⎝⎠ ⎣ ⎦ Both lemmas are used with the values R 1 = RR IY YO rr bc + , F 1 = RR IY YO ff bc + , R 2 = R R IY YO rr j k + , and F 2 = R R IY YO ff j k + . Similar discussion can be presented in conjunction with C(x, y, F). Similar discussion can be presented in conjunction with surrogates defined in association with WRB(x, y, R) and WRB(x, y, R). 4.2.3.2 Delay-superior situations for macro-surrogates Let us focus on WRB(x, y, R). Let us focus on RR 1 (IY , YO ) jk MS = and RR 2 (IY , YO ) bc MS = . MS 2 is delay-superior to MS 1 if R RR R IY YO IY YO d ( ,) d ( ,) d ( ,) d ( ,) j kb c αβαβ αβ αβ +≤ + , 85 for all α , min max α αα ≤ ≤ , and β , min max β ββ ≤ ≤ . Investigating whether MS 2 is delay-superior to MS 1 can be done using Lemma 4-5 with the values K = 0, R 1 = RR IY YO rr bc + , F 1 = RR IY YO ff bc + , R 2 = R R IY YO rr j k + , and F 2 = R R IY YO ff j k + . Similar discussion can be presented in conjunction with WRB(x, y, F). 4.2.4 Signals implied at circuit lines Let us focus on the following two examples. ___________________________________________________________________ Example 4-7: Consider a 2-input NAND gate shown in Figure 4-1, where a and b are circuit inputs, under the two-pattern input sequence shown in the figure. Suppose R n d a g = 3, F n d b g = 5. g a c b Figure 4-1. An example. Under the CPV, R d a g = 3 α, F d b g = 5 β. Suppose 0.7 ≤ α ≤ 1.2 and 0.8 ≤ β ≤ 1.3. For five fabricated copies of the circuit with values of α and β shown below, S c is demonstrated in Figure 4-2. Circuit #1: α = 1 and β = 1 86 Circuit #2: α = 0.7 and β = 0.8 Circuit #3: α = 0.7 and β = 1.3 Circuit #4: α = 1.2 and β = 0.8 Circuit #5: α = 1.2 and β = 1.3 35 2.1 6.5 3.6 4 2.1 4 3.6 6.5 S c Circuit #1 Circuit #2 Circuit #3 Circuit #4 Circuit #5 Figure 4-2. S c in five different fabricated copies of the circuit. As can be seen in Figure 4-2, in each of the five fabricated copies of the circuit with specific values of α and β, S c is as follows. S c : Logic-1 in the interval (- ∞, 3 α], logic-0 in the interval [3 α, 5 β], and logic-1 in the interval [5 β, ∞). It can be shown that the above is valid for any fabricated copy of the circuit with values of α and β, where 0.7 ≤ α ≤ 1.2 and 0.8 ≤ β ≤ 1.3. _______________________________________________________________________________________________________________________________________ ___________________________________________________________________ Example 4-8: Consider the same situation discussed in Example 4-7 except that suppose F n d b g , instead of being equal to 5, is equal to 4. For five fabricated copies of the circuit with the same values of α and β as discussed in Example 4-4, S c is demonstrated in Figure 4-3. 87 34 2.1 5.2 2.1 3.2 3.6 5.2 S c Circuit #1 Circuit #2 Circuit #3 Circuit #4 Circuit #5 Figure 4-3. S c in five different fabricated copies of the circuit. As can be seen in Figure 4-3, for Circuit #1, #2, #3, and #5, S c is as follows. S c : Logic-1 in the interval (- ∞, 3 α], logic-0 in the interval [3 α, 4 β], and logic-1 in the interval [4 β, ∞). However, this is not the case for Circuit #4, where S c has no interval of logic-0. It can be verified that in this example situation, for all the fabricated copies of the circuit, S c is logic-1 in the interval (- ∞, 2.1] and the interval [5.2, ∞). _______________________________________________________________________________________________________________________________________ We refer to the intervals of the signals that are common in all the fabricated copies of the circuit as determinate intervals, and refer to the remaining intervals as uncertain intervals. In Example 4-7, the determinate intervals for S c are the logic-1 interval (- ∞, 3 α], the logic-0 interval [3 α, 5 β], and the logic-1 interval [5 β, ∞) and there is no uncertain interval. In Example 4-8, the determinate intervals for S c are the logic-1 interval (-∞, 2.1] and the logic-1 interval [5.2, ∞) and the uncertain interval is the interval [2.1, 5.2]. We only focus on the determinate intervals. It must be noted that the begin- and end-times of the determinate intervals might be constants (e.g. 2.1 or 5.2 in Example 4- 88 8) or functions of α and β (e.g., 3 α, or 5 β in Example 4-7). All through this dissertation, the uncertain intervals are illustrated by gray-shaded regions. For example, in conjunction with Example 4-8, S c is represented as shown in Figure 4-4. S c 2.1 5.2 Figure 4-4. Illustration of an uncertain interval. Note that under the MGDF, we only know the initial and final values of the signal implied at each circuit line. Under the MGDF, the signal implied at each circuit line consists of an uncertain interval, the begin- and end-times of which are not known. For example, when the signal implied at a circuit line l is a rising transition, S l is as shown in Figure 4-5. Unknown Unknown 0 S l Figure 4-5. A rising transition under the MGDF. 4.2.5 Relaxed tests for surrogates and macro-surrogates Under the CPV, a test that satisfies less restricted requirements than those satisfied by an RR-test for a surrogate (R + -test for a macro-surrogate) might be guaranteed to cause a timing error at the output of the surrogate (macro-surrogate) when a surrogate (macro-surrogate) delay fault exists on the surrogate (macro-surrogate) and be a detecting-test for the surrogate (macro-surrogate). We refer to such a test as a relaxed RR-test (relaxed R + -test) for the surrogate (macro-surrogate). A relaxed RR-test (relaxed R + -test) for a surrogate (macro-surrogate) is not an RR-test (R + -test) for the surrogate (macro-surrogate) but S-covers (MS-covers) the surrogate (macro-surrogate). 89 As mentioned in Section 4.1, the fact that a surrogate (macro-surrogate) might be S- covered (MS-covered) by a test that is not an RR-test (R + -test) for the surrogate (macro- surrogate) might result in higher coverage of crosstalk sites (WRB sites) and also lower test generation and test application costs. An example is given below. ___________________________________________________________________ Example 4-9: Consider surrogate FR R 1 (IX , IY , YO ) ij k S = defined in association with C(x, y, R). Assume that under the CPV, a two-pattern input sequence T satisfies r-robust requirements for every on-IX-sub-path gate, satisfies r-robust requirements for every on-IY-sub-path gate except gate g, and satisfies robust requirements for every on-YO-sub-path gate. Suppose g is a 2-input NAND gate with input lines a and b, where a is the on-sub-path input and has 1-to-0 logical IY-direction. Suppose T satisfies r-robust on-sub-path requirement for g but invokes a signal as shown in Figure 4-6 at b' (b' is the virtual delayed point (refer to Appendix A, Section A.1.1) corresponding b 1 ) and thus does not satisfy the r-robust off-sub-path requirement. S b' is at logic-1 (ncv g ) and changes from logic-1 only after S a' stabilizes at logic-0; therefore, the signal implied at the output of g is no different from the signal that would be implied if S b' was a static logic-1 (r-robust off-sub-path requirement). Therefore, under T, the signal implied at the output of R YO k is the same as that implied under an RR-test for the surrogate. As a result, when a surrogate delay fault exists on the surrogate, T, exactly like an RR-test, creates a timing error at the 1 All through this dissertation, a primed circuit line represents the virtual delayed point of the line with the corresponding unprimed name. 90 output of R YO k and thus is a detecting-test for the surrogate. T satisfies a relaxed version of r-robust requirements for g and is a relaxed RR-test for the surrogate. T S-covers the surrogate. S a' S b' S c Figure 4-6. Signals implied at inputs and output of a 2-input on-IY-sub-path NAND gate g with on-sub-path input a, off-sub-path input b and output c. _______________________________________________________________________________________________________________________________________ Before presenting further details about relaxed RR-tests and relaxed R + -tests, since some of the requirements of RR- and R + -tests are the same as those of R-tests for logical paths, we will first focus on R-tests and relaxed R-tests. In Section 4.2.5.1, characteristics of R-tests for logical paths are studied in more detail (than what was presented in Section 1.1.2.2) and then in Section 4.2.5.2, relaxed R-tests are defined. Similarly, in Sections 4.2.5.3 and 4.2.5.5, characteristics of RR- and R + -tests are respectively studied in more detail (than what was presented in Sections 2.2.5 and 3.2.5) and then relaxed RR- and R + -tests are defined in Sections 4.2.5.4 and 4.2.5.6. It must be noted that testing for path delay faults using tests that satisfy a relaxed version of robust requirements, such as non-robust [37][13][20] and FS-tests, has been previously studied in the literature [14]. All such studies have focused on very special cases of relaxation. Besides, they do not consider any gate delay fault model. In other words, using analysis under the nominal defect-free (NDF) assumption, which assumes that no process variations exist and defects do not affect delays of gates, they identify 91 two-pattern input sequences that are more likely to create timing errors when path delay faults exist on logical paths. 4.2.5.1 R-test As mentioned in Section 1.1.2.2, an R-test for a logical path is a two-pattern input sequence that satisfies robust requirements for every multiple-input on-path gate. For a multiple-input on-path gate g with on-path input a, robust requirements are defined as follows. If a has cv g -to-ncv g logical direction, On-path requirement: IV(a) = cv g and FV(a) = ncv g (IV(a) and FV(a) are complements of each other), and Off-path requirement: For every off-path input b, FV(b) = ncv g . If a has ncv g -to-cv g logical direction, On-path requirement: IV(a) = ncv g and FV(a) = cv g (IV(a) and FV(a) are complements of each other), and Off-path requirement: For every off-path input b, S b = Static ncv g . Under an R-test for a logical path, the arrival time of the first transition edge in the signal implied at an on-path line is greater than or equal to the delay of the logical path from its input to the on-path line (refer to Appendix B, Theorem B-3). This transition edge is referred to as the robust logical path delay superior transition edge (RPST). Under a constrained gate delay fault assumption, signals implied at circuit lines include uncertain intervals. Under an R-test for a logical path, in each fabricated circuit, the RPST in the signal implied at each on-path line is somewhere within an uncertain 92 interval which is referred to as the robust logical path delay superior uncertain region (RPSU). Under an R-test for a logical path, in each fabricated circuit, the RPSU in the signal implied at each on-path line is the first uncertain interval. Examples of signals at an on-path line and the corresponding RPSUs and RPSTs are shown in Figure 4-7. In all illustrations in this dissertation, RPSTs are made distinguishable using thick lines to denote the transitions and RPSUs are circled using thick lines. RPSU RPST (a) (b) Figure 4-7. Examples of signals at an on-path line under an R-test under a constrained gate delay fault assumption. (a): On-path line has 0-to-1 logical direction. (b): On-path line has 1-to-0 logical direction. Under a constrained gate delay fault assumption, robust requirements for an example 2-input on-path NAND gate with on-path input a, off-path input b and output c are illustrated in Figure 4-8. S a' S b' S c Or S a' S b' S c (a) (b) Figure 4-8. Robust requirements for an example 2-input on-path NAND gate with on-path input a, off-path input b and output c. (a): a has 0-to-1 logical direction. (b): a has 1-to-0 logical direction. 93 For a multiple-input on-path gate g with output c and on-path input a that has ncv g - to-cv g logical direction, the robust off-path requirement guarantees that the RPST in S c does not get sped up compared to the RPST in S a' (Figure 4-8(b)). We refer to this property as no-speed-up property. It is clear that if a has ncv g -to-cv g logical direction, the RPST in S c cannot get delayed. If a has cv g -to-ncv g logical direction, it is clear that the RPST in S c cannot get sped up and the off-path requirement allows slow-down of the RPST in S c compared to the RPST in S a' (Figure 4-8(a)). 4.2.5.2 Relaxed R-test Under a constrained gate delay fault assumption, a relaxed R-test for a logical path is a two-pattern input sequence that is a detecting-test for the logical path by satisfying a relaxed version of the robust requirements for every multiple-input on-path gate. An example is given below. ___________________________________________________________________ Example 4-10: Consider the situation shown in Figure 4-9 where a has 1-to-0 logical direction. Suppose that under an R-test for the logical path, T 1 , signals are as shown in Figure 4-9(a). Furthermore, suppose that under another two-pattern input sequence, T 2 , the corresponding signals are as shown in Figure 4-9(b). T 2 is not an R-test for the logical path due to the following reasons. - For g 1 , where the on-path input, a, has 1 ncv g -to- 1 cv g logical direction, the off-path requirement is not satisfied because S b' is not at logic-1 ( 1 ncv g ) at all times. 94 - For g 2 , where the on-path input, c, has 2 cv g -to- 2 ncv g logical direction, the on-path requirement is not satisfied because IV(c) is not the complement of FV(c), i.e., IV(c) is not 2 cv g . - For g 3 , where the on-path input, e, has 3 ncv g -to- 3 cv g logical direction, the on-path requirement is not satisfied because IV(e) is not complement of FV(e), i.e., IV(e) is not 3 ncv g . However, as shown in Figure 4-9(b), T 2 , exactly similar to T 1 , is a detecting-test for the logical path. Thus, T 2 is a relaxed R-test for the logical path. b a c g 1 z d e g 2 h g 3 S b' S a' t 1 a' t 2 a' S c S b' S a' S c t S t S (a) S d S d S e S e S h S h S z S z (b) γ Figure 4-9. Waveforms under (a) T 1 , and (b) T 2 . T 1 T 2 95 T 2 satisfies a relaxed version of the robust on-path requirements at c and e. In particular, S c and S e do not have complementary initial and final values. Furthermore, T 2 satisfies a relaxed version of the robust off-path requirement at b. Under T 2 , S a' ’s RPSU propagates to c and is considered as S c ’s RPSU. Since a has 1 ncv g -to- 1 cv g logical direction, this is meant to guarantee the no-speed-up property (refer to Section 4.2.5.1) at g 1 . The requirement that T 2 satisfies at b in this regard is that S b' is at logic-1 in the interval [t 1 a' , t 2 a' ] (Figure 4-9(b)), where interval [t 1 a' , t 2 a' ] is S a' ’s RPSU. Another uncertain interval, circled with thin drawing line, also propagates to c from b' which occurs earlier than the RPSU in S c . (S c ’s RPSU is not the first uncertain interval anymore.) The uncertain interval propagated from b' is such that when the resulting S c propagates down along the path to z, the corresponding uncertain interval always occurs earlier than the RPSU. This is meant to guarantee the no-speed-up property at on-path gates in the fan-out cone of g 1 . The requirement that T 2 satisfies at b in this regard is that S b' is also at logic-1 in the interval [t 1 a' – γ, t 1 a' ] (Figure 4-9(b)). If this requirement is not satisfied, the uncertain interval circled with thin drawing line might get mixed with the RPSU and thus the RPST might get sped up. As a result, a timing error might not be created under the two-pattern input sequence when a path delay fault exists on the logical path. _______________________________________________________________________________________________________________________________________ Example 4-10 gives us clues as how to define relaxed robust requirements by relaxing The on-path requirements, and also 96 The off-path requirement when the on-path input has non-controlling to controlling logical direction (this relaxation must guarantee the no-speed-up property). Details are as follows. For a multiple-input on-path gate g with on-path input a and output c, relaxed robust requirements are defined as follows. If a has cv g -to-ncv g logical direction, On-path requirement: S a contains RPSU and FV(a) = ncv g , and Off-path requirement: For every off-path input b, FV(b) = ncv g . If a has ncv g -to-cv g logical direction, On-path requirement: S a contains RPSU and FV(a) = cv g , and Off-path requirement: For every off-path input b, S b' is at ncv g at least in the interval [t 1 a' – γ g , t 2 a' ], where interval [t 1 a' , t 2 a' ] is S a' ’s RPSU and γ g depends on the delays of on-path segments from c to any on-path line in its fan-out cone. It should be noted that S a' ’s RPSU that propagates to c is considered as S c ’s RPSU and it is not necessarily the first uncertainty region. 4.2.5.3 RR-test As mentioned in Section 2.2.5, an RR-test for a surrogate defined in association with a crosstalk slow-down target is a two-pattern input sequence that Satisfies r-robust requirements for every on-IX-sub-path gate, Satisfies r-robust requirements for every on-IY-sub-path gate, and Satisfies robust requirements for every on-YO-sub-path gate. 97 For a multiple-input on-IX-sub-path gate g with on-sub-path input a, r-robust requirements are defined as follows. On-sub-path requirement: S a = Clean transition with the same direction as a’s logical IX-direction, and Off-sub-path requirement: For every off-sub-path input b, S b = Static ncv g . For a multiple-input on-IY-sub-path gate, r-robust requirements are defined similarly. For a multiple-input on-YO-sub-path gate, robust requirements are defined similar to robust requirements for an on-path gate (refer to Section 1.1.2.2 or 4.2.5.1). Under an RR-test for a surrogate, the arrival time of the transition edge in the signal implied at an on-IX-sub-path line is equal to the delay of the logical IX-sub-path from its input to the on-IX-sub-path line (because for every on-IX-sub-path gate, the signal implied at each off-sub-path input is the static non-controlling value of the gate). This transition edge is referred to as the r-robust logical IX-sub-path delay equivalent transition edge (RR-IX-SPET). Under a constrained gate delay fault assumption, signals implied at circuit lines include uncertain intervals. Under an RR-test for a surrogate, in each fabricated circuit, the RR-IX-SPET in the signal implied at each on- IX-sub-path line is somewhere within an uncertain interval which is referred to as the r- robust logical IX-sub-path delay equivalent uncertain interval (RR-IX-SPEU). Under an RR-test for a logical path, in each fabricated circuit, the RR-IX-SPET in the signal implied at each on-IX-sub-path line is the only uncertain interval. Under an RR-test for a surrogate, the arrival time of the transition edge in the signal implied at an on-IY-sub-path line (other than the victim line) is equal to the delay of the logical IY-sub-path from its input to the on-IY-sub-path line. At the victim line, the 98 arrival time of the transition edge is equal to the delay of the logical IY-sub-path plus the crosstalk-induced slow-down (for example in conjunction with the surrogate FR R (IX , IY , YO ) ij k S = , the crosstalk-induced slow-down is R F IY IX R Cn n (d d ) j i sd − ). This transition edge is referred to as the r-robust logical IY- sub-path delay equivalent transition edge (RR-IY-SPET). Under an RR-test for a surrogate, in each fabricated circuit, the RR-IY-SPET in the signal implied at each on- IY-sub-path line is somewhere within the only uncertain interval which is referred to as the r-robust logical IY-sub-path delay equivalent uncertain interval (RR-IY-SPEU). Furthermore, under an RR-test for a surrogate, the arrival time of the first transition edge in the signal implied at an on-YO-sub-path line (other than the victim line) is greater than or equal to the arrival time of the RR-IY-SPET at the victim line plus the delay of the logical YO-sub-path from the victim line to the on-YO-sub-path line (refer to Appendix B, Theorem B-3). This transition edge is referred to as the robust logical YO-sub-path delay superior transition edge (R-YO-SPST). Under an RR-test for a surrogate, in each fabricated circuit, the R-YO-SPST in the signal implied at each on- YO-sub-path line is somewhere within an uncertain interval which is referred to as the robust logical YO-sub-path delay superior uncertain interval (R-YO-SPSU). Under an RR-test for a surrogate, in each fabricated circuit, the R-YO-SPSU in the signal implied at each on-YO-sub-path line is the first uncertain interval. Examples of signals at an on-IX-sub-path line and the corresponding RR-IX-SPEUs and RR-IX-SPETs are shown in Figure 4-10. In all illustrations in this dissertation, RR- IX-SPETs, RR-IY-SPETs and R-YO-SPSTs are made distinguishable using thick lines 99 to denote the transitions and RR-IX-SPEUs, RR-IY-SPEUs and R-YO-SPSUs are circled using thick lines. RR-IX-SPEU RR-IX-SPET (a) (b) Figure 4-10. Examples of signals at an on-IX-sub-path line under an RR-test under a constrained gate delay fault assumption. (a): On-sub-path line has 0-to-1 logical IX-direction. (b): On-sub-path line has 1-to-0 logical IX-direction. Under a constrained gate delay fault assumption, r-robust requirements for an example 2-input on-IX-sub-path NAND gate with on-sub-path input a, off-sub-path input b and output c are illustrated in Figure 4-11. S a' S b' S c S a' S b' S c (a) (b) Figure 4-11. R-robust requirements for an example 2-input on-IX-sub-path NAND gate with on- sub-path input a, off-sub-path input b and output c. (a): a has 0-to-1 logical IX-direction. (b): a has 1-to-0 logical IX-direction. For a multiple-input on-IX-sub-path gate g with output c and on-sub-path input a that has cv g -to-ncv g logical IX-direction, the r-robust off-sub-path requirement guarantees that the RR-IX-SPET in S c does not get delayed compared to the RR-IX- SPET in S a' (Figure 4-11(a)). We refer to this property as the no-slow-down property. It is clear that if a has cv g -to-ncv g logical IX-direction, the RR-IX-SPET in S c cannot get sped-up. If a has ncv g -to-cv g logical IX-direction, the r-robust off-sub-path requirement 100 guarantees that the RR-IX-SPET in S c does not get sped-up compared to the RR-IX- SPET in S a' (Figure 4-11(b)). We refer to this property as the no-speed-up property. It is clear that if a has ncv g -to-cv g logical IX-direction, the RR-IX-SPET in S c cannot get delayed. The same is true for a multiple-input on-IY-sub-path gate. For a multiple-input on-YO-sub-path gate g with output c and on-sub-path input a that has ncv g -to-cv g logical YO-direction, the robust off-sub-path requirement guarantees the no-speed-up property. If a has cv g -to-ncv g logical YO-direction, the off-sub-path requirement allows slow-down of the R-YO-SPST in S c compared to the R-YO-SPST in S a' . Similar discussion can be presented in conjunction with an RR-test for a surrogate defined in association with a WRB slow-down target. 4.2.5.4 Relaxed RR-test Under a constrained gate delay fault assumption, a relaxed RR-test for a surrogate defined in association with a crosstalk slow-down target is a two-pattern input sequence that is a detecting-test for the surrogate (and thus S-covers the surrogate) by satisfying a relaxed version of the r-robust requirements for every multiple-input on-IX-sub-path and on-IY-sub-path gate and a relaxed version of robust requirements for every multiple-input on-YO-sub-path gate. An example is given below. ___________________________________________________________________ Example 4-11: Consider the situation shown in Figure 4-12. In conjunction with surrogate FR R (IX , IY , YO ) ij k S = defined in association with crosstalk slow-down target C(x, y, R), on-IX-sub-path line a has 1-to-0 logical IX-direction. Suppose that under an RR-test for S, T 1 , signals are as shown in Figure 4-12(a). RR-IY-SPET and RR- 101 IY-SPEU in S y are delayed due to the presence of the coupling capacitance. Furthermore, suppose that under another two-pattern input sequence, T 2 , the corresponding signals are as shown in Figure 4-12(b). T 2 is not an RR-test for S due to the following reasons. - For g 1 , where the on-sub-path input, a, has 1 ncv g -to- 1 cv g logical IX- direction, the off-path requirement is not satisfied because S b' is not at logic- 1 ( 1 ncv g ) at all times. - For g 2 , where the on-sub-path input, c, has 2 cv g -to- 2 ncv g logical IX- direction, The on-path requirement is not satisfied because S c is not a transition; furthermore, The off-path requirement is not satisfied because S d' is not at logic-1 ( 2 ncv g ) at all times. - For g 3 , where the on-sub-path input, e, has 3 ncv g -to- 3 cv g logical IX- direction, the on-path requirement is not satisfied because S e is not a transition. However, as shown in Figure 4-12(b), T 2 , exactly similar to T 1 , is a detecting-test for the surrogate. Thus, T 2 is a relaxed RR-test for the surrogate. 102 b a c g 1 x y z IX i IY j YO k d e g 2 h g 3 S b' S a' t 1 a' S c (a) S b' S a' S c S z S z t S t S Early enough S y If coupling did not exist S d' S e S c' S c' S d' S e S x S x Late enough S y If coupling did not exist S y S y (b) t 2 a' t 1 c' t 2 c' 12 max( , ) ε ε 12 max( , ) ζ ζ Figure 4-12. Waveforms for an example situation under (a) T 1 , and (b) T 2 . T 2 satisfies a relaxed version of the r-robust on-sub-path requirements at c and e. In particular, S c and S e are not clean transitions. Furthermore, T 2 satisfies a relaxed version of the r-robust off-sub-path requirements at b and d. Under T 2 , T 1 T 2 103 S a' ’s RR-IX-SPEU propagates to c and is considered as S c ’s RR-IX-SPEU. Since a has 1 ncv g -to- 1 cv g logical IX-direction, this is meant to guarantee the no-speed-up property (refer to Section 4.2.5.3) at g 1 . The requirement that T 2 satisfies at b' in this regard is that S b' is at logic-1 in the interval [t 1 a' , t 2 a' ] (Figure 4-12(b)), where interval [t 1 a' , t 2 a' ] is S a' ’s RR-IX-SPEU. Another uncertain interval, circled with thin drawing line, also propagates to c from b' which occurs earlier than the RR-IX- SPEU in S c . (S c ’s RR-IX-SPEU is not the first uncertain interval anymore.) The uncertain interval propagated from b' is such that when the resulting S c propagates down along the IX-sub-path to x, the corresponding uncertain interval always occurs earlier than the RR-IX-SPEU. This is meant to guarantee the no-speed-up property at on-IX-sub-path gates in the fan-out cone of g 1 . The requirement that T 2 satisfies at b' in this regard is that S b' is also at logic-1 in the interval [t 1 a' – ε 1 , t 1 a' ] (Figure 4-12(b)). If this requirement is not satisfied, the uncertain interval circled with thin drawing line might get mixed with the RR-IX-SPEU and thus the RR-IX-SPET might get sped up. As a result, S x ’s RR-IX-SPET might get sped up, crosstalk- induced slow-down applied to S y ’s RR-IY-SPET might be smaller than that in Figure 4-12(a), and thus a timing error might not be created under the two-pattern input sequence when a surrogate delay fault exists on the surrogate. Furthermore, under T 2 , the uncertain interval propagated from b' is such that when the resulting S c propagates down along the IX-sub-path to x, the corresponding uncertain interval in S x occurs far earlier than the RR-IY-SPEU in S y and thus the RR-IY-SPET and the RR-IY-SPEU in S y are delayed exactly to the same amount as under T 1 where a single transition occurs in S x . We refer to this 104 property as the single-transition-delay property. The requirement that T 2 satisfies at b' in this regard is that S b' is at logic-1 in the interval [t 1 a' – ε 2 , t 2 a' ] (Figure 4-12(b)). If this requirement is not satisfied, crosstalk-induced slow-down applied to S y ’s RR- IY-SPET might be smaller than that under T 1 and thus a timing error might not be created under T 2 when a surrogate delay fault exists on the surrogate. Similarly, under T 2 , S d' is at logic-1 in the intervals [t 1 c' , t 2 c' ], [t 1 c' , t 1 c' + ζ 1 ], and [t 1 c' , t 1 c' + ζ 2 ] (Figure 4-12(b)), where interval [t 1 c' , t 2 c' ] is S c' ’s RR-IX-SPEU. Since c has 2 cv g -to- 2 ncv g logical IX-direction, these are meant to guarantee the no-slow- down property (refer to Section 4.2.5.3) at g 2 and on-IX-sub-path gates in its fan- out cone as well as the single-transition-delay property. _______________________________________________________________________________________________________________________________________ Example 4-11 gives us clues as how to define relaxed r-robust requirements by relaxing the on-sub-path and off-sub-path requirements. Details are as follows. For a multiple-input on-IX-sub-path gate g with on-sub-path input a and output c, relaxed r-robust requirements are defined as follows. If a has cv g -to-ncv g logical IX-direction, On-sub-path requirement: S a ≠ Static logic-0 or Static logic-1 and contains RR-IX-SPEU, and Off-sub-path requirement: For every off-sub-path input b, S b' is at ncv g at least in the interval [t 1 a' , t 2 a' + ζ g ], where interval [t 1 a' , t 2 a' ] is S a' ’s RR-IX-SPEU. If a has ncv g -to-cv g logical IX-direction, On-sub-path requirement: S a ≠ Static logic-0 or Static logic-1 and contains RR-IX-SPEU, and 105 Off-sub-path requirement: For every off-sub-path input b, S b' is at ncv g at least in the interval [t 1 a' – ε g , t 2 a' ], where interval [t 1 a' , t 2 a' ] is S a' ’s RR-IX-SPEU. ε g and ζ g depend on the delays of on-IX-sub-path segments from c to any on-IX- sub-path line in its fan-out cone, victim line’s RR-IY-SPEU, strengths of the gates driving the affecting and victim lines, strengths of the gates driven by them, and also on the coupling capacitance. ( ε g and ζ g are incorporated in order to guarantee no speed-up and no slow-down properties as well as single-transition-delay property.) It should be noted that S a' ’s RR-IX-SPEU that propagates to c is considered as S c ’s RR-IX-SPEU which might not be the only uncertain interval in S c . For a multiple-input on-IY-sub-path gate g with on-sub-path input a and output c, relaxed r-robust requirements are defined as follows. If a has cv g -to-ncv g logical IY-direction, On-sub-path requirement: FV(a) = ncv g but S a ≠ Static ncv g and contains RR- IY-SPEU, and Off-sub-path requirement: For every off-sub-path input b, S b' is at ncv g at least in the interval [t 1 a' , t 2 a' + θ g ], where interval [t 1 a' , t 2 a' ] is S a' ’s RR-IY-SPEU. If a has ncv g -to-cv g logical IY-direction, On-sub-path requirement: FV(a) = cv g but S a ≠ Static cv g and contains RR- IY-SPEU, and Off-sub-path requirement: For every off-sub-path input b, S b' is at ncv g at least in the interval [t 1 a' – η g , t 2 a' ], where interval [t 1 a' , t 2 a' ] is S a' ’s RR-IY-SPEU. η g and θ g depend on the delays of on-IY-sub-path segments from c to any on-IY- sub-path line in its fan-out cone. ( η g and θ g are incorporated in order to guarantee no speed-up and no slow-down properties.) 106 It should be noted that S a' ’s RR-IY-SPEU that propagates to c is considered as S c ’s RR-IY-SPEU which might not be the only uncertain interval in S c . For a multiple-input on-YO-sub-path gate relaxed robust requirements are defined similar to those defined for an on-path gate (Section 4.2.5.2). Relaxed RR-test for a surrogate defined in association with a WRB slow-down target is defined in a similar way. 4.2.5.5 R + -test As mentioned in Section 3.2.5, an R + -test for macro-surrogate is a two-pattern input sequence that Satisfies robust requirements for every on-IY-sub-path gate, Satisfies robust requirements for every on-YO-sub-path gate, and Satisfies the affecting signal requirement (in conjunction with RR (IY , YO ) jk , affecting signal requirement indicates that S x must be static logic-0, and in conjunction with FF (IY , YO ) jk , it indicates that S x must be static logic-1). For a multiple-input on-IY- or on-YO-sub-path gate, robust requirements are defined similar to robust requirements for an on-path gate (refer to Section 1.1.2.2 or 4.2.5.1). Under an R + -test for a macro-surrogate, the arrival time of the first transition edge in the signal implied at an on-IY-sub-path line (other than the victim line) is greater than or equal to the delay of the logical IY-sub-path from its input to the on-IY-sub-path line (refer to Appendix B, Theorem B-3). At the victim line, the arrival time of the first transition edge is greater than or equal to the delay of the logical IY-sub-path plus the maximum possible WRB-induced slow-down (for example in conjunction with 107 RR (IY , YO ) jk , the maximum possible WRB-induced slow-down is R WRB max-sd ). This transition edge is referred to as the robust logical IY-sub-path delay superior transition edge (R-IY-SPST). Under an R + -test for a macro-surrogate, in each fabricated circuit, the R-IY-SPST in the signal implied at each on-IY-sub-path line is somewhere within an uncertain interval which is referred to as the robust logical IY- sub-path delay superior uncertain interval (R-IY-SPSU). Under an R + -test for a macro-surrogate, in each fabricated circuit, the R-IY-SPSU in the signal implied at each on-IY-sub-path line is the first uncertain interval. Furthermore, under an R + -test for a macro-surrogate, the arrival time of the first transition edge in the signal implied at an on-YO-sub-path line (other than the victim line) is greater than or equal to the arrival time of the R-IY-SPST at the victim line plus the delay of the logical YO-sub-path from the victim line to the on-YO-sub-path line (refer to Appendix B, Theorem B-3). This transition edge is referred to as the robust logical YO-sub-path delay superior transition edge (R-YO-SPST). Under an R + -test for a macro-surrogate, in each fabricated circuit, the R-YO-SPST in the signal implied at each on-YO-sub-path line is somewhere within an uncertain interval which is referred to as the robust logical YO-sub-path delay superior uncertain interval (R-YO-SPSU). Under an R + -test for a macro-surrogate, in each fabricated circuit, the R-YO-SPSU in the signal implied at each on-YO-sub-path line is the first uncertain interval. 4.2.5.6 Relaxed R + -test Under a constrained gate delay fault assumption, a relaxed R + -test for a macro- surrogate is a two-pattern input sequence that is a detecting-test for the macro-surrogate 108 (and thus MS-covers the macro-surrogate) by satisfying a relaxed version of the affecting signal requirement and a relaxed version of the robust requirements for every multiple-input on-IY-sub-path and on-YO-sub-path gate. An example is given below. ___________________________________________________________________ Example 4-12: Consider the situation shown in Figure 4-13. Consider macro-surrogate RR (IY , YO ) jk MS = defined in association with WRB slow-down target WRB(x, y, R). Suppose that under an R + -test for MS, T 1 , signals are as shown in Figure 4-13(a). R-IY-SPST and R-IY-SPSU in S y are delayed due to the presence of the WRB. Furthermore, suppose that under another two-pattern input sequence, T 2 , the corresponding signals are as shown in Figure 4-13(b). T 2 is not an R + -test for MS because S x is not at logic-0 at all times. However, as shown in Figure 4-13(b), T 2 , exactly similar to T 1 , is a detecting-test for the macro-surrogate. Thus, T 2 is a relaxed R + -test for the macro-surrogate. x y z IY j YO k (a) S z S z t S t S S y If coupling did not exist S x S x S y If coupling did not exist S y S y (b) λ µ Figure 4-13. Waveforms for an example situation under (a) T 1 , and (b) T 2 . T 1 T 2 t 1 y t 2 y 109 Under T 2 , S x falls to logic-0 enough earlier than the R-IY-SPSU in S y and does not rise until enough later than it. As a result, the R-IY-SPST and the R-IY-SPSU in S y are delayed exactly to the same amount as under T 1 . The requirement that T 2 satisfies at x in this regard is that S x is at logic-0 in the interval [t 1 y – λ, t 2 y + µ] (Figure 4-13(b)), where interval [t 1 y , t 2 y ] is S y ’s R-IY-SPSU. _______________________________________________________________________________________________________________________________________ Example 4-12 gives us clues as how to define relaxed affecting signal requirement as follows. In conjunction with WRB(x, y, R) (WRB(x, y, F)), S x is at logic-0 (logic-1) at least in the interval [t 1 y – λ, t 2 y + µ], where interval [t 1 y , t 2 y ] is S y ’s R-IY-SPSU. λ and µ depend on the strengths of the gates driving the affecting and victim lines, strengths of the gates driven by them, and the resistance of the bridge. Relaxed robust requirements for a multiple-input on-IY- or on-YO-sub-path gate are defined similar to those defined for an on-path gate (Section 4.2.5.2). 4.2.6 Relaxed RR- and R + -test generation Under constrained gate delay fault assumptions, the process of generating a relaxed RR-test or a relaxed R + -test is the process of searching for a two-pattern input sequence that satisfies certain logic as well as timing requirements. In this process, a search engine and a fault simulation engine work interactively. The fault simulation engine is a simulation engine that considers the effect of the crosstalk- or WRB-induced delay fault (when they are excited) at the victim line. 110 At each step, the search engine identifies a candidate fully specified or partially specified two-pattern input sequence under which the simulation is performed. If the crosstalk- or WRB-induced delay fault is excited, the effect of the fault is considered in the simulation process. After fault simulation is preformed under a candidate two-pattern input sequence, it is checked whether test requirements are satisfied. If the requirements are satisfied, a test has been found. Else, if the whole search space has not been traversed yet and if we are willing to continue the search, another candidate two-pattern input sequence is identified and the cycle is repeated. In Section 4.2.6.1, an overview of the simulation process under any constrained gate delay fault assumption is presented first and then issues related to the simulation process under the CPV are discussed in particular. In Section 4.2.6.2, it is briefly discussed how the effects of crosstalk- or WRB-induced delay faults are considered during the simulation process under the CPV. Section 4.2.6.3 briefly addresses the process of checking the test requirements under the CPV. Finally in Section 4.2.6.4, the search process is briefly discussed. 4.2.6.1 Simulation Under a constrained gate delay fault assumption, simulation is the process of finding the signal implied at each circuit line, i.e., the information about all the determinate intervals of logic-0 or logic-1, under a two-pattern input sequence. Logic levels [27] of gates are first calculated and then simulation is performed level-by-level starting from level-1. At each level, the signal implied at each gate’s output is found using the signals 111 implied at the gate’s inputs. In particular, for each gate, the simulation is done through the following two steps. (I) Finding the signals at virtual delayed points. (II) Using the signals at virtual delayed points together with the Boolean functionality of the gate to find logic-0 and logic-1 intervals at the output of the gate. In step (I), in conjunction with each logic-0 or logic-1 interval in the signal implied at a circuit line a, the corresponding interval in S a' is found as it is explained in Appendix A, Section A.1.2.1. As mentioned in Appendix A, some of the resulting logic-0 or logic-1 intervals might have intersections and must be replaced with the corresponding intersection intervals. In step (II), interval intersection and union operations are used to find logic-0 and logic-1 intervals in the signal implied at a gate’s output using those at the inputs’ virtual delayed points as it is explained in Appendix A, Section A.1.2.2. For example, for a 2-input NAND gate with inputs a and b and output c, if a logic-1 interval in S a' has an intersection with a logic-1 interval in S b' , we consider the intersection interval as a logic-0 interval in S c . Furthermore, in conjunction with any logic-0 interval in S a' or S b' , we consider a logic-1 interval in S c . Among the resulting logic-1 intervals, those that have intersections with each other are replaced with the corresponding union intervals. As mentioned above, the principal operations for performing simulation under constrained gate delay fault assumptions are interval intersection and union. Comparison operations are utilized in interval intersection and union operations. For example two intervals 11 1 I[tb , te ] = and 22 2 I[tb , te ] = have an intersection if 112 max-tb min-te < , where 12 max-tb Max(tb , tb ) = and 12 min-te Min(te , te ). = If 12 tb tb ≤ , 12 2 Max(tb , tb ) tb . = Else ( 12 tb tb > ), 12 1 Max(tb , tb ) tb . = Similarly, if 12 te te , ≤ 12 1 Min(te , te ) te . = Else ( 12 te te > ), 12 2 Min(te , te ) te . = In other words, checking whether two intervals have an intersection (and eventually finding the intersection interval when an intersection exists), is done using comparisons of begin- and end-times of the intervals (for example, 12 tb tb or >< ). The same is true for union operation. Under the CPV, as mentioned before, begin- and end-times of determinate intervals might be constants or functions of parameters α and β (refer to Section 4.2.4). Therefore, under the CPV, the comparison operations are not necessarily simple arithmetic comparisons. An example is given below. ___________________________________________________________________ Example 4-13: Let us investigate how simulation is performed in conjunction with gate g in Example 4-7 (correlated process variations is assumed with N N min max 0.7 1.2 αα α ≤≤ and N N min max 0.8 1.3 ββ β ≤≤ ). S a' and S b' are as shown in Figure 4-14. S a' S b' 3 α 5 β Figure 4-14. S a' and S b' . Logic-0 interval 0 ' I( ,3] a α =−∞ and logic-1 interval 1 ' I[3,) a α = ∞ exist in S a' . Logic-1 interval 1 ' I( ,5] b β =−∞ and logic-0 interval 0 ' I[5,) b β = ∞ exist in S b' . Investigating whether 1 ' I a has an intersection with 1 ' I b is done as follows. max-tb Max(3 , ) α =−∞ . Comparing 3 α with −∞ is not a simple arithmetic comparison: 113 min 3 3 α α >−∞⇒ >−∞ for all α , 0.7 1.2 α ≤ ≤ , max-tb 3 α ⇒= . Furthermore, min-te Min( , 5 ) β =∞ . Comparing ∞ with 5 β is not a simple arithmetic comparison either: max 55 β β ∞> ⇒ ∞ > for all β , 0.8 1.3 β ≤ ≤ , min-te 5 β ⇒= . In order to have an intersection, max-tb must be less than min-te. Comparing max-tb( 3 ) α = with min-te( 5 ) β = is not a simple arithmetic comparison: max min 3 5 3 5 α βαβ <⇒ < for all , α N N min max 0.7 1.2 , α αα ≤ ≤ and all , β N N min max 0.8 1.3 β ββ ≤≤ . Therefore, an intersection exists and the intersection interval is [3 ,5 ] α β . As a result, logic-0 interval 0 I[3,5] c α β = exists in S c . Furthermore, 0 ' I a and 0 ' I b create logic-1 intervals (,3] α − ∞ and [5 , ) β ∞ in S c . It can be shown that max-tb Max( ,5 ) 5 β β =−∞ = , min-te Min(3 , ) 3 α α =∞= for all α , 0.7 1.2 α ≤ ≤ , and all β , 0.8 1.3 β ≤≤ . Since 53 β α > , the two logic-1 intervals (,3] α − ∞ and [5 , ) β ∞ in S c do not have an intersection. Therefore, S c is a follows. S c 3 α 5 β Figure 4-15. The resulting S c . _______________________________________________________________________________________________________________________________________ 114 The fact that comparison operations are not necessarily simple arithmetic operations might add complications to the simulation. An example is given below. ___________________________________________________________________ Example 4-14: Let us investigate how simulation is performed in conjunction with gate g in Example 4-8 (correlated process variations is assumed with N N min max 0.7 1.2 αα α ≤≤ and N N min max 0.8 1.3 ββ β ≤≤ ). S a' and S b' are as shown in Figure 4-16. S a' S b' 3 α 4 β Figure 4-16. S a' and S b' . Logic-0 interval 0 ' I( ,3] a α =−∞ and logic-1 interval 1 ' I[3,) a α = ∞ exist in S a' . Logic-1 interval 1 ' I( ,4] b β =−∞ and logic-0 interval 0 ' I[4,) b β = ∞ exist in S b' . Considering that 0.7 1.2 α ≤ ≤ and 0.8 1.3 β ≤ ≤ , it can be shown that max-tb Max(3 , ) 3 α α =−∞= and min-te Min( , 4 ) 4 β β =∞ = . 34 α β < for all α , 0.7 1.2 α ≤≤ , and all β , 0.8 1.3 β ≤ ≤ . Furthermore, 3 4 α β > for all α , 0.7 1.2 α ≤≤ , and all β , 0.8 1.3 β ≤ ≤ . Therefore, we cannot say that 1 ' I a and 1 ' I b have an intersection, nor can we say that these two intervals are disjoint. We consider no logic-0 interval for S c . Furthermore, 0 ' I a and 0 ' I b create logic-1 intervals ( ,3 ] α − ∞ and [4 , ) β ∞ in S c . In the same way, we cannot say that these two intervals are disjoint, nor can we say that these two intervals do have an intersection. Therefore, we cannot combine the two intervals, nor can we keep them as disjoint intervals. However, we know that in all fabricated copies of the circuit, S a' is at logic-0 in the interval min (,2.1( 3 )] α −∞ = 115 and S b' is at logic-0 in the interval max [5.2( 4 ), ) β = ∞ . As a result S c is at logic-1 during the two intervals (,2.1] − ∞ and [5.2, ) ∞ . Note that these two intervals do not have an intersection. Therefore, we consider logic-1 intervals of (,2.1] −∞ and [5.2, ) ∞ and also an uncertain interval [2.1, 5.2] for S c as shown below. S c 2.1 5.2 Figure 4-17. The resulting S c . _______________________________________________________________________________________________________________________________________ Under the CPV, comparison operations verify the validity of inequalities of types 11 1 2 2 2 R. F. K R . F . K αβαβ ++ < + + , or 11 1 2 2 2 R. F. K R . F . K αβαβ ++ ≥ + + ( 1 R, 1 F, 2 R, 2 F, 1 K , and 2 K are constants.) for all values of α , min max α αα ≤≤ , and β , min max β ββ ≤ ≤ . Such verifications can be carried out using Lemma 4-5 and Lemma 4-6. Under partially specified two-pattern input sequences, uncertain intervals are considered in conjunction with the inputs whose signals are not fully specified and then simulation is carried out in the same way. For example, when only the logic value of circuit input i 1 in the first pattern is set as logic-0, a logic-0 interval (- ∞, 0] and an uncertain interval [0, + ∞) is considered for 1 S i (see Figure 4-18). Similarly, when only the logic value of circuit input i 2 in the second pattern is set as logic-1, an uncertain interval (- ∞, 0] and a logic-1 interval [0, + ∞) is considered for 2 S i (see Figure 4-18). 0 0 1 S i 2 S i Figure 4-18. Examples of partially specified signals at circuit inputs. 116 4.2.6.1.1 Simulation under single-uncertain-interval simplification In order to reduce storage, run-time and computational complexities during simulation, it is a common practice to use the single-uncertain-interval (SUI) simplification. Under this simplification, maximum of one uncertain interval is used in the representation of the signal implied at each circuit line. For example, if the signal implied at a circuit line l is as shown in Figure 4-19 (a), under the SUI implication, the representation that we consider for S l is as shown in Figure 4-19 (b). Only the first interval (- ∞, t 1 ] and the last interval [t 2 , ∞) are considered in the representation of S l under the SUI simplification and the uncertain interval [t 1 , t 2 ], the determinate interval [t 2 , t 3 ], the uncertain interval [t 3 , t 4 ], the determinate interval [t 4 , t 5 ], and the uncertain interval [t 5 , t 6 ] are integrated into one single uncertain interval [t 1 , t 6 ]. t 1 S l S l (a) (b) t 2 t 3 t 4 t 5 t 6 t 1 t 2 Figure 4-19. An example signal and its representation under the SUI simplification. Under the SUI simplification, the signal at each circuit line l under a fully specified two-pattern input sequence is representable using the following four parameters: ■ Initial value of l, IV(l), which determines whether the first interval, referred to as the initial interval, is an interval of logic-0 or logic-1. ■ End-time of the initial interval, referred to as EII. ■ Final value of l, FV(l) which determines whether the last interval, referred to as the final interval, is an interval of logic-0 or logic-1. ■ Begin-time of the final interval, referred to as BFI. t 6 117 Note that for static signals, there is no uncertain interval and the first and the last intervals are the same. Therefore, for such signals, EII = ∞ and BFI = - ∞. Under the SUI simplification, requirements of relaxed tests (Sections 4.2.5.2, 4.2.5.4, and 4.2.5.6) must be defined in conjunction with the above set of parameters. For example, in conjunction with a logical IX-sub-path, for a multiple-input on-IX-sub- path gate g with on-sub-path input a that has ncv g -to-cv g logical IX-direction, the relaxed r-robust off-path requirement was defined in Section 4.2.5.4 as follows. Off-sub-path requirement: For every off-sub-path input b, S b' is at ncv g at least in the interval [t 1 a' – ε g , t 2 a' ], where interval [t 1 a' , t 2 a' ] is S a' ’s RR-IX-SPEU. (When g is a NAND gate, this requirement is as illustrated in Figure 4-20.) S b' S a' t 1 a' t 2 a' ε g Figure 4-20. Relaxed r-robust off-sub-path requirement. Under the SUI simplification, the requirement is defined as follows. Off-sub-path requirement: For every off-sub-path input b, IV(b) = ncv g and EII(b') > BFI(a'). When g is a NAND gate, this requirement is as illustrated in Figure 4-21. EII(a') BFI(a') S a' EII(b') S b' Figure 4-21. Relaxed r-robust off-sub-path requirement under the SUI simplification. 118 As another example let us recall that in conjunction with WRB(x, y, R), relaxed affecting signal requirement was defined in 4.2.5.6 as follow. S x is at logic-0 at least in the interval [t 1 y – λ, t 2 y + µ], where interval [t 1 y , t 2 y ] is S y ’s R-IY-SPSU. (This requirement is illustrated in Figure 4-22.) x y z IY j YO k S y S x λ µ t 1 y t 2 y Figure 4-22. Relaxed affecting signal requirement. Under the SUI simplification, the requirement is defined as follows. FV(x) = logic-0 and BFI(x) < EII(y) – λ (Figure 4-23 (a)), or IV(x) = logic-0 and EII(x) > BFI(y) + µ (Figure 4-23 (b)). EII(y) S y BFI(x) S x BFI(y) S y EII(x) S x (a) (b) µ λ Figure 4-23. Relaxed affecting signal requirement under the SUI simplification. 4.2.6.2 Effects of crosstalk- and WRB-induced delay faults Under the constrained gate delay fault assumptions, during simulation, the effects of crosstalk- or WRB-induced delay faults must be considered whenever they are excited. In conjunction with the CPV, an example is given below. 119 ___________________________________________________________________ Example 4-15: Consider the situation shown in Figure 4-24. If the coupling did not exist, a logic-0 interval 22 2 (,R. F. K] α β −∞ + + and a logic-1 interval 22 2 [R . F . K , ) α β ++ ∞ would exist in S y . If 11 1 R. F. K α β + + and 22 2 R. F. K α β ++ are relatively close to each other, the fault simulation engine must consider the excitation of the crosstalk-induced delay fault. A logic-0 interval 22 2 (,R. F. K], α β ′′ ′ −∞ + + an uncertain interval 22 2 [R . F . K , α β ′′ ′ ++ 22 2 R. F. K ], α β ′′ ′′ ′′ ++ and a logic-1 interval 22 2 [R . F . K , ) α β ′′′′ ′′ + +∞ exist in the resulting S y . x y a b c d S b' S a' S y 22 2 R. F. K α β + + 22 2 R. F. K αβ ′′′′ ′′ ++ 11 1 R. F. K α β + + 22 2 R. F. K αβ ′ ′′ ++ S y 22 2 R. F. K α β + + If coupling did not exist Coupling exists Figure 4-24. An example demonstrating how the effect of crosstalk-induced delay fault is considered during simulation, under the CPV. _______________________________________________________________________________________________________________________________________ During the simulation process determinate intervals of the signal implied at the victim line are first calculated assuming that no coupling exists and then the begin- and 120 end-times of such intervals are modified to take into effect the effect of the crosstalk- or WRB-induced delay faults. New uncertain intervals might also emerge. 4.2.6.3 Checking test requirements After fault simulation is performed under a candidate two-pattern input sequence, it is verified whether test requirements are satisfied. In conjunction with the CPV, an example is given below. ___________________________________________________________________ Example 4-16: Consider a 2-input on-YO-sub-path NAND gate g with on-sub-path input a and off-sub-path input b. Suppose the result of fault simulation tells us that S b' is at logic-1 in the interval 11 12 2 2 [R.F. K,R.F. K] α βα β + ++ + . Suppose a has 1-to-0 logical YO-direction. The off-sub-path requirement for g requires that S b' be at logic-1 in the interval [t 1 a' – γ g , t 2 a' ]. Suppose t 1 a' = 33 3 R. F. K α β + + and t 2 a' = 44 4 R. F. K α β ++ . Checking whether the requirement is satisfied can be done by using comparison operations. In particular, it is verified whether 22 2 4 4 4 R. F. K R . F. K αβαβ ++ ≥ + + , and 11 1 3 3 3 R. F. K R . F. K γ g αβαβ ++ ≤ + + − for all values of α , min max α αα ≤≤ , and β , min max β ββ ≤ ≤ . Such verifications can be carried out using Lemma 4-5 and Lemma 4-6. _______________________________________________________________________________________________________________________________________ In general, under the CPV, the requirements of relaxed RR-, and R + -tests can be checked using comparison operations. Lemma 4-5 and Lemma 4-6 are used in comparison operations. 121 4.2.6.4 Search process Identifying the candidate two-pattern input sequences is the responsibility of the search engine. In searching for candidate two-pattern sequences, the search engine might be implemented with different degrees of intelligence from the least intelligent (selecting patterns randomly) to highly intelligent (using logic and timing implication and justification procedures). More details about alternatives in implementing search processes are beyond the scope of this dissertation. It is believed that the decisions made in intelligent search processes will again be based on comparison operations. In particular, validity of inequalities of the following types 11 1 2 2 2 R. F. K R . F . K αβαβ ++ < + + , or 11 1 2 2 2 R. F. K R . F . K αβαβ ++ ≥ + + ( 1 R, 1 F, 2 R, 2 F, 1 K , and 2 K are constants.) for all values of , α min max , α αα ≤ ≤ and , β min max β ββ ≤ ≤ is verified. As mentioned before, such verifications can be done using Lemma 4-5 and Lemma 4-6. 4.3 Single gate delay fault In this section, we only focus on the case of a crosstalk site. Similar discussions can be presented in conjunction with a WRB site. Under the single gate delay fault (SGDF) assumption, it is assumed that only one defect might exist in each fabricated circuit as a result of which a delay fault exists on the output line of a gate and no process variations exist. 122 4.3.1 Delays of surrogates Suppose gate g is the location of the delay fault. Let δ denote the size of the delay fault. If R IX i passes through g, RR IX IX n dd ii δ = + , where the subscript ‘n’ is used to indicate nominal delay. Else, RR IX IX n dd ii = . The same is true for F IX i , R IY j , F IY j , R YO k , and F YO k . Let us focus on a surrogate FR R (IX , IY , YO ) ij k S = defined in association with C(x, y, R). Nominal delay of S, denoted by n d S , is RR FR IY IY IX YO R nn C n n n dd (d d )d jj ik S sd =+ − + . Delay of S when g is the location of the delay fault is denoted by d | S g . In conjunction with S, the set of all the gates along the corresponding IX-, IY-, and YO- sub-paths is referred to as S’s gate-set and is denoted by G S . When g ∉G S , n d| d SS g = . When g ∈G S , g might be (i) An on-IX-sub-path gate, (ii) An on-IY-sub-path-gate, (iii)An on-IX-sub-path gate as well as an on-IY-sub-path-gate, or (iv) An on-YO-sub-path-gate. g cannot be an on-YO-sub-path gate as well as an on-IX-sub-path gate or an on-YO- sub-path gate as well as an on-IY-sub-path gate, because the affecting and victim lines are not in each other’s transitive fan-in. For each of the cases (i)-(iv) above, d | S g is as follows. Case (i): RR FR IY IY IX YO R nCn n n d(d d)d jj ik sd δ ++− + Case (ii): RR FR IY IY IX YO R nCn n n d(dd )d jj ik sdδδ ++ − − + 123 Case (iii): RR FR IY IY IX YO R nCn n n d(dd)d jj ik sd δ ++ − + Case (iv): RR FR IY IY IX YO R nCn n n d(d d)d jj ik sd δ +− + + Similar discussion can be presented in conjunction with a surrogate defined in association with C(x, y, F). In conjunction with a crosstalk site, under the SGDF, we assume that t S is greater than the maximum nominal delay among all the corresponding FS-testable surrogates (because if this is not the case, a timing error might occur in the circuit even if no gate has a delay fault). 4.3.2 Surrogate-gate pairs Under the SGDF, the existence of a surrogate delay fault on a surrogate is because of the presence of a delay fault on the output line of one gate in the surrogate’s gate-set. Therefore, in conjunction with each surrogate, multiple cases can be considered in each of which a gate in the surrogate’s gate-set has a delay fault on its output line while delays of all other gates are at their nominal values. Each such case is referred to as a surrogate-gate pair. Figure 4-25 shows an example surrogate, S, with two on-IX-sub- path gates, three on-IY-sub-path gates, and two on-YO-sub-path gates. As illustrated in the figure, seven surrogate-gate pairs, (S, g 1 ), (S, g 2 ), …, (S, g 7 ), can be considered. The gate that is circled is the one that has a delay fault. 124 x y S g 7 g 3 g 2 g 1 x x x x y y y y (S, g 1 ) (S, g 2 ) (S, g 3 ) (S, g 7 ) Figure 4-25. An example surrogate and the seven corresponding surrogate-gate pairs. In general, for surrogate S with G S = {g 1 , …, g N S }, N S surrogate-gate pairs (S, g 1 ), …, (S, g N S ) can be considered. A test is said to Sg-cover a surrogate-gate pair (S, g), where g ∈G S , if the circuit fails the test in any situation where as a result of a delay fault on the output line of g a surrogate delay fault exists on the surrogate. A test-set is said to Sg-cover a surrogate- gate pair if at least one test in the set Sg-covers the surrogate-gate pair. It is clear that an RR-test for a surrogate Sg-covers every corresponding surrogate-gate pair. In this section, we will show that under the SGDF, a test that is not an RR-test for a surrogate might also Sg-cover a surrogate-gate pair corresponding the surrogate. 125 Lemma 4-7: Under the SGDF, a surrogate is S-covered by a test-set if all the corresponding surrogate-gate pairs are Sg-covered by the set. Proof is straight-forward. Under the SGDF, a surrogate-gate pair might be Sg-covered by a test that is not an RR-test for the corresponding surrogate. As a result, a surrogate might be S-covered by a test-set that does not contain an RR-test for the surrogate. As mentioned in Section 4.1, this fact might result in higher coverage of crosstalk sites and also lower test generation and test application costs. Organization of the rest of Section 4.3 is as follows. In Section 4.3.3, it is discussed that under the SGDF, in conjunction with a gate as the location of the delay fault, we might be able to compare delays of surrogates with t S or with each other. The fact that we might be able to compare delays of surrogates with t S allows us to filter out some surrogate-gate pairs from the list of the surrogate-gate pairs that need to be Sg-covered in conjunction with Lemma 4-7. More details are presented in 4.3.4. The fact that we might be able to compare delays of two surrogates S 1 and S 2 might allow us to identify (S 1 , g) as being Sg-covered by an RR-test for S 2 or a relaxed RR-test (as will be introduced ahead) for (S 2 , g). More details are presented in Section 4.3.5. Under the SGDF, in conjunction with a gate as the location of the delay fault, we might be able to identify determinate intervals of logic-0 and logic-1 in the signals implied at circuit lines. This might allow us to identify a test that satisfies less restricted requirements than those satisfied by an RR-test for a surrogate as a detecting test for the 126 surrogate-gate pair that Sg-covers the surrogate-gate pair. We refer to such a test as a relaxed RR-test for the surrogate-gate pair. Details are discussed in Section 4.3.6. Finally in Section 4.3.7, the process of generating relaxed RR-tests for surrogate-gate pairs is discussed. 4.3.3 Comparing delays of surrogates with t S or with each other Under the SGDF, in conjunction with a gate as the location of the delay fault, we might be able to compare delays of surrogates with t S or with each other. Examples are given below. ___________________________________________________________________ Example 4-17: Consider surrogate FR R (IX , IY , YO ) ij k S = defined in association with C(x, y, R). Suppose as shown in Figure 4-26, gate g, an on-IX-sub-path gate for S, is where the delay fault exists. Therefore, RR FR IY IY IX YO R nCn n n d| d (d d ) d jj ik S gsd δ =+ +− + . g IX i YO k IY j x y Figure 4-26. An example surrogate with on-IX-sub-path gate g. Suppose R F IY IX nn dd 0 j i −< . In such a situation, as shown in Figure 4-27, maximum possible crosstalk-induced slow-down is R C max-sd and thus maximum of 1 d| S g is R R IY YO R nCn dmax- d j k sd ++ . Therefore, if R R IY YO R nCn S dmax- d t j k sd ++ < , 127 then 1 S d| t S g < for all δ ( δ ≥ 0). Note that only nominal delay terms are used in the above inequality. 0 sd C R R F IY IX nn skew d d j i δ =+− δ = ∞ 0 δ = R C Max max-sd = Figure 4-27. Maximum crosstalk-induced slow-down. _______________________________________________________________________________________________________________________________________ ___________________________________________________________________ Example 4-18: Consider surrogates FR R 1 (IX , IY , YO ) ij k S = and FR R 2 (IX , IY , YO ) ab c S = . Suppose as shown in Figure 4-28, gate g, an on-IX-sub-path gate as well as an on- IY-sub-path gate for S 1 and an on-IY-sub-path gate for S 2 , is where the delay fault exists. Therefore, RR FR 1 IY IY IX YO R nCn n n d| d (d d ) d jj ik S gsd δ =++ − + , and RFR R 2 IY IX IY YO R nCn n n d| d (d d ) d bab c S gsdδδ =++ − −+ . It can be easily shown that if RR FRRR IY IY IX YO IY YO R nCn n n n n d(d d)d d d jj ikbc sd+− + ≤ + , then 12 d| d | SS gg ≤ for all δ ( δ ≥ 0). Again, note that only nominal delay terms are used in the above inequality. g p IX a YO c IY b YO k IX i IY j x y Figure 4-28. S 1 , S 2 , and g, the location of the gate delay fault. _______________________________________________________________________________________________________________________________________ 128 More details about the situations where delay of a surrogate is less than t S or delay of another surrogate under the SGDF will be presented ahead. Note that such comparisons cannot be made under the MGDF where no assumptions are made about the nature of defects and process variations and the resulting gate delay faults. 4.3.4 Non-criticality In conjunction with surrogate FR R (IX , IY , YO ) ij k S = and gate g ∈G S , surrogate- gate pair (S, g) is said to be non-critical if S d| t S g < . Under the SGDF, when (S, g) is non-critical, no surrogate delay fault exists on S when a gate delay fault exists at g. If a surrogate-pair is not non-critical, it is said to be potentially-critical. Since no assumption is made about the size of the delay fault under the SGDF, (S, g) might be non-critical only if g is an on-IX-sub-path gate (Case(i) in Section 4.3.1). In such a case, when R F IY IX nn dd 0 j i −≥ , (S, g) is always non-critical because RR FR IY IY IX YO R nCn n n d| d (d d ) d jj ik S gsd δ =+ +− + , and as shown in Figure 4-29, maximum crosstalk-induced slow-down occurs at 0 δ = and is R F IY IX R Cn n (d d ) j i sd − . In other words, RR FR n IY IY IX YO R nCn n n S d nS d| d (d d ) d d| t. dt jj ik S S S S gsd g ⎫ ≤+ − + ⎪ ⎪ ⇒< ⎬ ⎪ ⎪ < ⎭ 0 sd C R 0 δ = δ = ∞ R F IY IX nn skew d d j i δ =+− R F IY IX R Cn n Max (d d ) j i sd=− Figure 4-29. Maximum crosstalk-induced slow-down. 129 However, when R F IY IX nn dd 0 j i −< , as discussed in Example 4-17, (S, g) is non- critical if R R IY YO R nCn S dmax- d t j k sd ++ < . Identification of (S, g) as non-critical makes it unnecessary for us to ensure its Sg- coverage in conjunction with Lemma 4-7. Theorem 4-6: Under the SGDF, a surrogate is S-covered by a test-set if all the corresponding potentially-critical surrogate-gate pairs are Sg-covered by the set. Proof follows from Lemma 4-7 and the fact that in conjunction with a non-critical surrogate-gate pair (S, g), no surrogate delay fault exists on S when a delay fault exists at g. Similar discussion can be presented in conjunction with surrogate RF F (IX , IY , YO ) ij k . 4.3.5 Delay-superiority In conjunction with surrogates S 1 and S 2 and gate g that belongs to 1 S G as well as to 2 S G , (S 1 , g) is said to be delay-inferior to (S 2 , g) if 12 d| d | SS gg ≤ . (In such a situation (S 2 , g) is said to be delay-superior to (S 1 , g).) In Example 4-18, a situation where a surrogate-gate pair is delay-superior to another surrogate-gate pair was presented. In Appendix E, Section E.3, a complete set of situations where a surrogate-gate pair (S 2 , g) can be shown to be delay-superior to the surrogate-gate pair (S 1 , g) is presented. 130 Theorem 4-7: If (S 2 , g) is delay-superior to (S 1 , g) and a test T Sg-covers (S 2 , g), then T also Sg-covers (S 1 , g). Proof: If a gate delay fault at g causes a surrogate delay fault to exist on S 1 (meaning that 1 S d| t S g > ), a surrogate delay fault also exists on S 2 because 12 2 1 S S d| d | d| t d| t SS S S gg g g ⎫ ≤ ⎪ ⇒> ⎬ > ⎪ ⎭ . Since T Sg-covers (S 2 , g), the circuit fails T. The fact that the circuit fails T indicates that T also Sg-covers (S 1 , g). ■ According to what stated above, if a surrogate S 2 is RR-testable and in conjunction with a gate g that belongs to 1 S G as well as to 2 S G , (S 2 , g) is delay-superior to (S 1 , g) under the SGDF, an RR-test for S 2 (which Sg-covers (S 2 , g)) also Sg-covers (S 1 , g). Furthermore, if a relaxed RR-test for (S 2 , g) (as will be introduced ahead) exists, the test Sg-covers (S 2 , g) and thus Sg-covers (S 1 , g). According to Theorem 4-6, if all the potentially-critical surrogate-gate pairs corresponding a surrogate are Sg-covered, the surrogate is S-covered. As a result, under the SGDF, a surrogate might be S-covered by a test-set that does not contain an RR-test for the surrogate. As mentioned is Section 4.1, this might result in higher coverage of crosstalk sites and also lower test generation and test application costs. 131 4.3.6 Relaxed RR-test for a surrogate-gate pair Similar to the discussion presented in Section 4.2.4 in conjunction with the CPV, it can be shown that under the SGDF, in conjunction with a gate as the location of the delay fault, determinate and uncertain intervals exist in the signals implied at circuit lines. The begin- and end-times of the determinate intervals might be constants or functions of the size of the delay fault, δ . Under the SGDF, in conjunction with a gate g as the location of the delay fault and a surrogate S, where S gG ∈ , a test that satisfies less restricted requirements than those satisfied by an RR-test for S might be guaranteed to cause a timing error at the output of S in any situation where, as a result of a delay fault on the output line of g, a surrogate delay fault exists on S. We refer to such a test as a relaxed RR-test for the surrogate- gate pair (S, g). A relaxed RR-test for a surrogate-gate pair Sg-covers the surrogate- gate pair. Relaxed RR-tests for the surrogate-gate pairs corresponding a surrogate can be used in a test-set that S-covers the surrogate in conjunction with Lemma 4-7 and Theorem 4-1. As mentioned in Section 4.1, the fact that a surrogate might be S-covered by a test-set that does not contain an RR-test for the surrogate might result in higher coverage of crosstalk sites and also lower test generation and test application costs. In Section 4.2.5.4, relaxed RR-tests for surrogates were defined. Although this section was a sub-section of Section 4.2 which focuses on the CPV, the requirements that a test must satisfy to be a relaxed RR-test for a surrogate were defined independent of the specific constrained gate delay fault assumption. Under the SGDF, in conjunction with a gate g as the location of the delay fault and a surrogate S, where S gG ∈ , a relaxed RR-test for (S, g) is defined as a two-pattern input 132 sequence that satisfies the same requirements defined in Section 4.2.5.4. Of course, the implications of these requirements are different in conjunction with the SGDF from those under the CPV. 4.3.7 Relaxed RR-test generation In the process of generating a relaxed RR-test for a surrogate-gate pair (S, g), a delay fault with unknown size δ is considered on the output line of g. Simulation is done as it is explained in Section 4.2.6.1. For a gate that is not in the fan-out cone of g, the begin- and end-times of the intervals in the signals implied at the inputs of the gate are constant values and simple arithmetic comparisons are used to find the intervals at the output of the gate. For g, simulation is first done as if the delay fault does not exist and then δ is added to the begin- and end-times of the intervals. For a gate that is in the fan-out cone of g, begin- and end-times of intervals might be constants or functions of δ. As a result, the comparison operations used in the intersection and union operations during the simulation are not necessarily simple arithmetic comparisons, and complications (similar to those discussed in Example 4-14 in conjunction with the CPV) might be added to the simulation process, the result of which is the emergence of uncertain intervals in the signals implied at circuit lines. During simulation, the effect of crosstalk-induced delay should be considered. Similar to the case of the CPV (refer to Section 4.2.6.2), during this process uncertain intervals might also be added to the signals. Similar to the case of the CPV (refer to Section 4.2.6.3 and Section 4.2.6.4), comparison operations are also used in the process of checking the test requirements as well as in the search process. 133 4.4 Bounded maximum extra delay Under the bounded maximum extra delay (BMD) assumption, it is assumed that the accumulation of extra delays along any logical path or sub-path is upper bounded by a value ∆. Under the BMD, we might be able to compare delays of surrogates and macro- surrogates with t S or with each other. Examples are given below. ___________________________________________________________________ Example 4-19: Consider macro-surrogate RR 1 (IY , YO ) jk MS = defined in association with WRB(x, y, R). We have R R 1 IY YO R WRB dd max- ()d j k MS b sd r =+ + . Therefore, if R R IY YO R nWRBminn S dmax- ( )d t j k b sd r +++∆< , then 1 S dt S < . _______________________________________________________________________________________________________________________________________ ___________________________________________________________________ Example 4-20: Consider surrogates FR R 1 (IX , IY , YO ) ij k S = and FR R 2 (IX , IY , YO ) qj k S = defined in association with C(x, y, R). RR FR 1 IY IY IX YO R C dd (d d )d jj ik S sd =+ − + , and RFR R 2 IY IX IY YO R C dd (d d )d jq j k S sd =+ − + . Suppose R F IY IX nn dd j i >+∆ , FR IX IY nn dd qj >+∆ , and F F IX IX nn dd q i >+∆ . As a result, R F IY IX dd j i > , FR IX IY dd qj > , and F F IX IX dd . q i > In both surrogates skew is guaranteed to be positive. Furthermore, R F IY IX dd j i − is guaranteed to be greater than FR IX IY dd . qj − As the amount of slow-down decreases as the skew becomes more positive, we have 134 RFR F IY IX IY IXRR CC (d d) (d d) jqj i sd sd −< − . As a result, 12 dd SS < . _______________________________________________________________________________________________________________________________________ Similar to the case of the CPV, the fact that we might be able to compare delays of surrogates (macro-surrogates) with t S allows us to filter out some surrogates (macro- surrogates) from the list of the surrogates (macro-surrogates) that need to be S-covered (MS-covered) in conjunction with Theorem 4-1 (Theorem 4-2). (Under the BMD, non- criticality is defined in a similar way.) Furthermore, similar to the case of the CPV, the fact that we might be able to compare delays of surrogates (macro-surrogates) with each other allows us to identify situations where a surrogate (macro-surrogate) is S-covered (MS-covered) by an RR- test (R + -test) for another surrogate (macro-surrogate). (Under the BMD, delay- superiority is defined in a similar way.) Similar to the case of the CPV, we might be able to identify determinate intervals of logic-0 and logic-1 in the signals implied at circuit lines and identify relaxed RR-tests (R + -tests) for surrogates (macro-surrogates) that S-cover (MS-cover) the surrogates (macro-surrogates). Requirements of relaxed tests are the same as those defined in Sections 4.2.5.4 and 4.2.5.6. Similar to the case of the CPV, using non-criticality, delay-superiority and relaxed tests might result in higher coverage of crosstalk and WRB sites and also lower test generation and test application costs. The process of generating relaxed tests can be implemented in a conceptually similar way to how it is done in conjunction with the CPV (refer to Section 4.2.6). 135 4.5 Implementations Previously in this chapter, three constrained gate delay fault assumptions were discussed. It was also discussed how the ramifications of these assumptions might result in higher coverage of crosstalk and WRB sites and also lower test generation and test application costs. In order to achieve these advantages, the following procedures can be utilized. - A procedure for identifying the “non-criticalities” (i.e., checking whether surrogates or macro-surrogates are non-critical under the CPV or BMD, or checking whether surrogate-gate pairs or macro-surrogate-gate pairs are non-critical under the SGDF), - A procedure for identifying the delay-superiority relations (among surrogates or macro-surrogates under the CPV or BMD, or among surrogate-gate pairs or macro- surrogate-gate pairs under the SGDF), and - A procedure that searches for relaxed RR- and R + -tests (for surrogates and macro- surrogates under the CPV or BMD; for surrogate-gate pairs and macro-surrogate- gate pairs under the SGDF). In conjunction with the SGDF, we have implemented a full test generation framework for crosstalk-induced delay faults that incorporates the procedure for generating FS- and RR-tests for surrogates implemented and used in conjunction with the experimental results reported in Chapter 2 as well as all the above type of procedures. Details and the corresponding experimental results are presented in Section 4.5.1. 136 In conjunction with the BMD and WRB targets, we have implemented a procedure for generating relaxed R + -tests for macro-surrogates. Details and the corresponding experimental results are presented in Section 4.5.2. 4.5.1 Test generation framework for crosstalk-induced delay faults under the SGDF The procedure for generating FS- and RR-tests for surrogates implemented and used in conjunction with the experimental results reported in Chapter 2 is incorporated in our test generation framework. We have implemented and incorporated a procedure that identifies the non-critical surrogate-gate pairs. This procedure uses the criteria presented in Section 4.3.4. We have also implemented and incorporated a procedure that identifies the delay-superiority relations among surrogate-gate pairs. This procedure uses the criteria presented in Appendix E, Section E.3. We have also implemented and incorporated a procedure for generating relaxed RR-tests for surrogate-gate pairs. Details of this procedure are as follows. We had previously implemented a logic and timing simulator, LTS, in which the signal implied at each circuit line l is represented with the parameters ▪ Initial value, IV(l), ▪ Final value, FV(l), ▪ Minimum and maximum arrival time for a rising transition in S l (also referred to as minimum and maximum rising arrival time), A R min(l) and A R max(l), and ▪ Minimum and maximum arrival time for a falling transition in S l (also referred to as minimum and maximum falling arrival time), A F min(l) and A F max(l). 137 For each circuit line, LTS calculates the above parameters under fully or partially specified vectors. (Describing the implementation details of LTS is beyond the scope of this dissertation.) In conjunction with a circuit line l, depending on IV(l), A R min(l) or A F min(l) can be considered as l’s EII in the SUI representation of S l (refer to Section 4.2.6.1.1). Similarly, depending on FV(l), A R max(l) or A F max(l) can be considered as l’s BFI in the SUI representation of S l . This is illustrated in Figure 4-30. Therefore, LTS can be used as an SUI simulation tool. EII(l) = A R min(l) BFI(l) = A F max(l) − ∞ ∞ IV(l) = logic-0, FV(l) = logic-0 S l − ∞ ∞ IV(l) = logic-0, FV(l) = logic-1 S l − ∞ ∞ IV(l) = logic-1, FV(l) = logic-0 S l − ∞ ∞ IV(l) = logic-1, FV(l) = logic-1 S l EII(l) = A R min(l) BFI(l) = A R max(l) EII(l) = A F min(l) BFI(l) = A F max(l) EII(l) = A F min(l) BFI(l) = A R max(l) Figure 4-30. Correspondence of minimum and maximum arrival times with EII and BFI. Relaxed r-robust and robust requirements consist of logic as well as timing requirements. Satisfying logic and timing requirements can be done by incorporating timing-oriented implication and justification procedures. Another alternative is to satisfy logic and timing requirements in two phases. Timing-oriented implication and justification procedures are not available to be used in conjunction with this dissertation 138 and implementing them is a subject of our future research studies. Therefore, we use the second alternative. We have modified LTS to consider the effect of the single gate delay fault and also the crosstalk-induced delay at the victim line. The modified LTS is used as an SUI simulation tool. Therefore, we focus on relaxed r-robust and robust requirements under the SUI simplification (Section 4.2.6.1.1). Phase (I): Satisfying the logic requirements. In this phase, the test generation core used in conjunction with generating FS- and RR-tests for surrogates is utilized with the same composite value system (refer to Section 2.3). Composite values that satisfy the logic part of the relaxed requirements under the SUI simplification are identified and are injected at on- and off-sub-path inputs of on-sub-path gates during initialization. For example, in conjunction with an on-IX-sub-path NAND gate, when the on-sub-path input has a falling logical IX-direction, the on-sub-path input is initialized to {T0} and the off-sub-path inputs of the gate are initialized to {S1, T0, H1}. Note that in this case, each basic value contained in the composite value injected at an off-sub-path input must have logic-1 (non-controlling) initial value (refer to Section 4.2.6.1.1). When the on- sub-path input has a rising logical IX-direction, the on-sub-path input is initialized to {T1} and the off-sub-path inputs of the gate are initialized to {S1, T1, H1}. Note that in this case, each basic value contained in the composite value injected at an off-sub-path input must have logic-1 (non-controlling) final value. After initialization is done, logic- only forward and backward implication and justification procedures are invoked until all the circuit lines are justified. 139 Phase (II): Satisfying the timing requirements. After getting to a point where all the circuit lines are justified, we run LTS to calculate the minimum and maximum rising and falling arrival times at each circuit line. At this point, we check whether the timing part of the relaxed requirements under the SUI simplification are satisfied. For example, in conjunction with an on-IX-sub-path NAND gate, when the on-sub-path input has a falling logical IX-direction, the minimum falling arrival time at each off-sub-path input must be greater than the maximum falling arrival time at the on-sub-path input (refer to Section 4.2.6.1.1, Figure 4-21). When the on-sub-path input has a rising logical IX- direction, the maximum rising arrival time at each off-sub-path input must be less than the minimum rising arrival time at the on-sub-path input. If all the timing requirements are satisfied, we have found a test. When the requirements are not satisfied, there might be a possibility that they will be satisfied if the current partially specified two-pattern input sequence is further specified. If there is no such a possibility, we backtrack in the search tree of the ATPG core (we go back to Phase (I)). But if such a possibility exists, we enumerate different ways of fully specifying the two-pattern input sequence. Each time, we use LTS to calculate the new timing parameters and check whether the timing requirements are satisfied. If we come across a situation where the timing requirements are satisfied, we have found a test. We maintain an enumeration count and consider a limit for it. When the limit is reached, we backtrack in the search tree of the ATPG core (we go back to Phase (I)). It must be noted that LTS also gives us some extra information that can be used to refine logic information (such information are not available from a conventional SUI simulation tool). For example, if an {H0} is implied at a circuit line, and we know that 140 the maximum falling arrival time at the line is less than the minimum rising arrival time at the line, we can conclude that the signal at the line is actually a {S0} and not a {H0}. We refer to such refinements as timing-oriented logic refinements. Such refinements have been incorporated in our framework. 4.5.1.1 Flow of test generation framework Flow of our test generation framework is shown in Figure 4-31. Figure 4-31. Flow of our test generation framework. Loop-1. While there exists a surrogate that has not been processed before, pick such a surrogate. - If FS-testability of the surrogate has not been investigated before, Search for an FS-test for the surrogate. If the ATPG returns a CONFLICT, • Mark the surrogate and all other surrogates in the same surrogate-set as FS-untestable. • Continue Loop-1. Else, mark the surrogate and all other surrogates in the same surrogate-set as FS-testable. - Else (i.e., if FS-testability of the surrogate has been investigated before), If the surrogate is FS-untestable, continue Loop-1. - Check the non-criticality of the surrogate-gate pairs that are not Sg-covered. - Check whether all the potentially-critical surrogate-gate pairs are Sg-covered. - If all the potentially-critical surrogate-gate pairs are Sg-coverd, mark the surrogate as S-covered. - Else (i.e., if not all the potentially-critical surrogate-gate pairs are Sg-covered), Search for an RR-test for the surrogate. If an RR-test exists, • Mark the surrogate as S-covered. • Mark all the surrogate-gate pairs are Sg-covered. • In conjunction with each surrogate-gate pair, find all the delay-inferior surrogate-gate pairs and mark them as Sg-covered (only if they have not been identified as non-critical before). Else (i.e., if an RR-test does not exist), • For each corresponding potentially-critical surrogate-gate pair that is not Sg-covered, search for a relaxed RR-test. • If a relaxed RR-test exists, ► Mark the surrogate-gate pair as Sg-covered. ► Find all the delay-inferior surrogate-gate pairs and mark them as Sg-covered (only if they have not been identified as non-critical before). Loop-2. For every FS-testable surrogate that is not S-covered, - Check whether all the potentially-critical surrogate-gate pairs are Sg-covered. - If all the potentially-critical surrogate-gate pairs are Sg-covered, mark the surrogate as S-covered. 141 In conjunction with a surrogate that is found RR-testable, it is more likely to identify many delay-superiority relations if the nominal delay of the surrogate is large. Therefore, as a heuristic, surrogates are processed in the decreasing order of their nominal delays in Loop-1 in Figure 4-31. It is possible that some surrogate-gate pairs corresponding a surrogate are marked as Sg-covered as a result of delay-superiority relations that are identified when an RR-test for a subsequent surrogate is found. Processing surrogates in decreasing order of their nominal delays in Loop-1 reduces this possibility but does not eliminate it. Therefore, Loop-2 in Figure 4-31 goes through all FS-testable surrogates that are still not marked as S-covered and checks whether all the corresponding potentially-critical surrogate-gate pairs are Sg-covered. The steps of our test generation framework are illustrated in the following example. ___________________________________________________________________ Example 4-21: Suppose surrogates S 1 , S 2 , S 3 , and S 4 , are defined in association with a crosstalk slow-down target. Suppose 1 n d S > 2 n d S > 3 n d S > 4 n d S . Suppose gates that belong to each G S i , i = 1, …, or 4, are as shown in Figure 4-32. An entry of the table that corresponds to surrogate S i and gate g j , j = 1, …, or 7, has been shaded if g j ∉G S i . A non-shaded entry of the table that corresponds to surrogate S i and gate g j represents surrogate-gate pair (S i , g j ). g 1 g 2 g 3 g 4 g 5 g 6 g 7 S 1 S 2 1 N 3 S 3 S 4 3 2 1 Figure 4-32. Gates that belong to each G S i , i = 1, …, or 4, and the status of the surrogate-gate pairs. Steps of the test generation framework are as follows. 142 1. Loop-1. Pick S 1 . - Search for an FS-test. Suppose no CONFLICT is returned by the ATPG. Mark S 1 as FS-testable. Suppose S 1 and S 3 belong to the same surrogate-set. Mark S 3 as FS-testable as well. - Check the non-criticality of the surrogate-gate pairs. Suppose no surrogate-gate pair is non-critical. - Search for an RR-test. Suppose the test generation attempt succeeds. Mark (S 1 , g 1 ), (S 1 , g 3 ), (S 1 , g 4 ), (S 1 , g 5 ), and (S 1 , g 6 ) as Sg-covered. Sg-coverage of surrogate-gate pairs by an RR-test for the corresponding surrogate is shown by “ ” in Figure 4-32. Find the delay-inferior surrogate-gate pairs. Suppose the following delay-inferiority relations are identified: (S 2 , g 1 ) is delay-inferior to (S 1 , g 1 ). (S 4 , g 5 ) is delay-inferior to (S 1 , g 5 ). Mark (S 2 , g 1 ) and (S 4 , g 5 ) as Sg-covered. When (S i , g j ) is Sg-covered and is delay-superior to (S x , g j ), Sg-coverage of (S x , g j ) is shown by “ i ” in Figure 4-32. 2. Loop-1. Pick S 2 . - Search for an FS-test. Suppose no CONFLICT is returned by the ATPG. Mark S 2 as FS-testable. Suppose S 2 and S 4 belong to the same surrogate-set. Mark S 4 as FS-testable as well. - Check the non-criticality of the surrogate-gate pairs that are not Sg-covered (i.e., (S 2 , g 2 ), (S 2 , g 4 ), and (S 2 , g 6 )). Suppose (S 2 , g 2 ) is found non-critical. - Mark (S 2 , g 2 ) as non-critical. Non-criticality of a surrogate-gate pair is shown by “ N ” in Figure 4-32. 143 - Not all the potentially-critical surrogate-gate pairs are Sg-covered ((S 2 , g 4 ) and (S 2 , g 6 ) are not Sg-covered). - Search for an RR-test. Suppose the test generation attempt fails. - Search for a relaxed RR-test for (S 2 , g 4 ). Suppose the test generation attempt succeeds. Mark (S 2 , g 4 ) as Sg-covered. Sg-coverage of a surrogate-gate pair by a relaxed RR-test for the surrogate-gate pair is also shown by “ ” in Figure 4-32. Find the delay-inferior surrogate-gate pairs. Suppose the following delay-inferiority relation is identified: (S 4 , g 4 ) is delay-inferior to (S 2 , g 4 ). Mark (S 4 , g 4 ) as Sg-covered. - Search for a relaxed RR-test for (S 2 , g 6 ). Suppose the test generation attempt fails. 3. Loop-1. Pick S 3 . - Check the non-criticality of the surrogate-gate pairs. Suppose no surrogate-gate pair is non-critical. - Search for an RR-test. Suppose the test generation attempt succeeds. Mark (S 3 , g 2 ), (S 3 , g 3 ), (S 3 , g 6 ), and (S 3 , g 7 ) as Sg-covered. Find the delay-inferior surrogate-gate pairs. Suppose the following delay-inferiority relations are identified: (S 4 , g 2 ) is delay-inferior to (S 3 , g 2 ). (S 2 , g 6 ) is delay-inferior to (S 3 , g 6 ). Mark (S 4 , g 2 ) and (S 2 , g 6 ) as Sg-covered. 4. Loop-1. Pick S 4 . - All the potentially-critical surrogate-gate pairs are Sg-covered. Mark the surrogate as S-covered. 5. Loop-2. Pick S 2 . 144 - All the potentially-critical surrogate-gate pairs are Sg-covered, mark the surrogate as S-covered. As can be seen, (S 2 , g 6 ) is marked as Sg-covered as a result of a delay-superiority relation that is identified when an RR-test for a subsequent surrogate, S 3 , is found. Thus, S 2 is marked as S-covered in Loop-2. _______________________________________________________________________________________________________________________________________ It must also be noted that Example 4-21 is an example of a situation where utilizing the concepts discussed in this chapter results in higher coverage of crosstalk sites and also lower test generation and test application costs. In this example, S 2 is RR- untestable; therefore, under the MGDF, the approach proposed in Chapter 2 does not guarantee testing for crosstalk-induced delay faults. In other words, the site is not identified as covered. However, under the SGDF, S 2 is found as S-covered and thus the target is identified as covered. Clearly, this provides higher coverage. Furthermore, an RR-test for S 4 does not need to be added to test-set, since S 4 is also found as S-covered. This provides lower test application cost. Note that this is accomplished without making an RR-test generation attempt for S 4 . This provides lower test generation cost. 4.5.1.2 Experimental results We have used the developed test generation framework in conjunction with the combinational parts of ISCAS 89 benchmark circuits. In each circuit, 1000 random crosstalk sites are considered. The total number of surrogates, number of FS-untestable surrogates and number of surrogates that are S-covered under the MGDF and SGDF are reported in Table 4-1. As can be seen in the table, there is a considerable increase in the S-coverage of the surrogates under the SGDF. In conjunction with the SGDF, two sets 145 of data are reported. In conjunction with the first set, only RR-tests and a combination of non-criticality and delay-superiority are used. In this case, the improvement in the coverage is achieved at no extra (and even reduced) test generation cost. However, relaxed RR-tests are also used in conjunction with the second set of data and the improvement in coverage compared to the previous situation is achieved at some extra test generation and test application costs. Table 4-1. S-coverage of the surrogates. #of S-covered surrogates MGDF SGDF Circuit #of surrogates #of FS-untestable surrogates S-covered using RR-test S-covered using RR-test, a combination of non-criticality and delay-superiority S-covered using RR-test, a combniation of non-criticality, delay-superiority as well as using relaxed RR-tests s820 205,750 4,230 (2.05%) 14,810 (7.35%) 41,230 (20.46%) 63,095 (31.31%) s953 415,974 0 (0.00%) 24,180 (5.81%) 72,924 (17.53%) 111,318 (26.76%) s1196 1,961,936 211,568 (10.78%) 51,040 (2.91%) 181,734 (10.38%) 253,674 (14.49%) s1488 231,802 0 (0.00%) 9,664 (4.16%) 57,640 (24.87%) 72,452 (31.26%) c1355 2,906,796 335,152 (11.53%) 240,190 (9.34%) 723,146 (28.12%) 939,421 (36.53%) c1908 3,460,984 469,308 (13.56%) 242,026 (8.09%) 710,222 (23.74%) 937,889 (31.35%) c2670 4,248,780 600,766 (14.17%) 243,320 (6.67%) 855,092 (23.44%) 1,293,947 (35.47%) For s953, the coverage of crosstalk sites under the MGDF and the SGDF are broken down into categories in Figure 4-33. “A” represents the number of crosstalk sites for which all the FS-testable surrogates are S-covered. These are the crosstalk sites for which we provide guarantee for testing for crosstalk-induced delay faults. As can be seen, under the SGDF, the number of such crosstalk sites is considerably higher than that under the MGDF. “B”, “C”, “D”, “E”, and “F”, respectively represent the number 146 of crosstalk sites for which more than 80%, 60%, 40%, and 20% of the FS-testable surrogates are S-covered and illustrate the trend by which the improved S-coverage of the surrogates affect the coverage of the crosstalk sites. Similar graphs for other circuits reveal similar trends. 0 50 100 150 200 250 300 350 400 450 MGDF SGDF Figure 4-33. Comparison of the coverage of crosstalk sites under the MGDF and SGDF. 4.5.1.3 Conclusion, notes and future work We have developed a test generation framework for crosstalk-induced delay faults under the SGDF. Using this framework, considerably higher coverage of surrogates is achieved compared to the framework discussed in Chapter 2 that assumes MGDF. Using the framework, considerably higher coverage of crosstalk sites is also achieved. As discussed in Section 4.5.1.1, the framework also results in lower test generation and test application costs. Gathering experimental results to demonstrate these advantages is a subject of our future research studies. As the results show, many of the surrogates are still not S-covered and for many of the crosstalk sites still not all the FS-testable surrogates are S-covered. The following must be noted in this regard. AB C D E 147 In this dissertation, we assume the size of the delay fault, δ, to be in the range [0, ∞). As gate delay faults with large sizes are likely to cause the circuit to malfunction under non-delay tests as well as conventional tests for delay faults, when testing for crosstalk- induced delay faults, we need not worry about gate delay faults with large sizes. In other words, assuming δ to belong to the interval [0, δ max ], where δ max is a known value, is realistic. Under such assumption, relatively less restricted conditions need to be satisfied for a surrogate-gate pair to be non-critical. Similarly, less restricted conditions need to be satisfied for a delay-superiority relation to exist between two surrogate-gate pairs. Furthermore, less restricted conditions must be satisfied for a two-pattern input sequence to be a relaxed RR-test for a surrogate-gate pair. As a result, under such assumption, higher S-coverage of surrogates and thus higher coverage of crosstalk sites will be achieved. Incorporating this assumption in our framework is a subject of our future research studies. Our procedure for generating relaxed RR-tests for surrogate-gate pairs uses the SUI simplification. Higher S-coverage of surrogates and thus higher coverage of crosstalk sites will be achieved if this simplification is not used. Furthermore, since timing- oriented implication and justification procedures were not available, we divided the task of satisfying the requirements to two separate tasks of satisfying the logic requirements and the subsequent task of satisfying the timing requirements. As a result, our search process was rather inefficient and many of our relaxed RR-test generation attempts did not succeed because backtrack and enumeration limits were met. By incorporating timing-oriented implication and justification procedures and targeting the logic and timing requirements at the same time, search space will reduce and we will be able to 148 find relaxed RR-tests for a larger population of surrogate-gate pairs. In this way, higher S-coverage of surrogates and thus higher coverage of crosstalk sites will be achieved. It must also be noted that our search for a two-pattern input sequence that satisfies timing requirements after getting to a point where all the lines are logically justified is also somewhat blind. Using heuristics facilitates this search and results in higher S-coverage of surrogates as well. 4.5.2 Procedure for generating relaxed R + -tests under the BMD We have also implemented a procedure for generating relaxed R + -tests under the BMD. The procedure only focuses on relaxation of the affecting signal requirement. We use LTS as an SUI simulation tool and focus on relaxed affecting signal requirement under the SUI simplification (refer to Section 4.2.6.1.1). When running LTS, nominal delay values are assumed for gates. The minimum rising and falling arrival times that are calculated can be used as the minimum rising and falling arrival times under the BMD. However, the maximum rising and falling arrival times under the BMD, are the calculated maximum rising and falling arrival times plus ∆. This is illustrated in Figure 4-34. 149 A R min n (l) A R max n (l) A R max BMD (l) A R min BMD (l) A F min n (l) A F max n (l) A F max BMD (l) A F min BMD (l) A R min n (l) A F max n (l) A F max BMD (l) A R min BMD (l) A F min n (l) A R max n (l) A R max BMD (l) A F min BMD (l) ∆ ∆ ∆ ∆ Figure 4-34. Arrival times under the BMD in terms of those under the nominal condition. Similar to the test generation framework that we have implemented for crosstalk- induced delay faults (Section 4.5.1), we satisfy logic and timing requirements in two subsequent phases. As Figure 4-23 illustrates, we can satisfy the relaxed affecting signal requirement in two alternative ways, alternative-(a) and alternative-(b), corresponding to Figure 4-23 (a) and (b), respectively. We try one alternative and if we do not succeed in finding a test, we try the other one. Details are explained below in conjunction with a macro-surrogate for a WRB slow-down target WRB(x, y, R). For satisfying the logic requirements, the test generation core used in conjunction with generating R + -tests for macro-surrogates is utilized with the same composite value system (refer to Section 3.3). The same composite values are injected at the on-sub-path and off-sub-path inputs of on-IY- and on-YO-sub-path gates during initialization. 150 Alternative-(a), Phase (I): Satisfying the logic requirements. In conjunction with alternative (a), the composite value injected at the affecting line is {S0, T0, H0}. (S0 is also allowed at the affecting line. In other words, the test found by the procedure might be an R + -test for the macro-surrogate. Therefore, this procedure can be used as a unified generator for R + -tests as well as relaxed R + -tests.) In Figure 4-23 (a), it is more likely that the timing requirement is satisfied if BFI(x) (which is equal to A F max BMD (x)) is as small as possible. Therefore, as a heuristic, a short IX-sub-path is targeted and appropriate logic-only auxiliary FV-affecting signal (AFAS) requirements are defined. For an on-IX-sub-path NAND gate g with on-sub-path input a, we define logic-only AFAS requirements as follows. If a has 0-to-1 logical IX-direction, On-sub-path requirement: S a = {S1, T1, H1}, and Off-sub-path requirement: For every off-sub-path input b, S b = {S1}. The requirements are illustrated in Figure 4-35 (b) for a 2-input on-IX-sub-path NAND gate. If the signal implied at b is a {S1}, A F max(c) = A R max(a'). Any signal other than S1 might make A F max(c) to be larger than A R max(a'). We do not allow this because the larger A F max(c), the larger A F max(x) and thus the less likely it is that the timing requirement is satisfied. If a has 1-to-0 logical IX-direction, On-sub-path requirement: S a = {S0, T0, H0}, and Off-sub-path requirement: None. The requirements are illustrated in Figure 4-35 (a) for a 2-input on-IX-sub-path NAND gate. If the signal implied at b is {S1}, A R max(c) = A F max(a'). Any signal 151 other than S1 might make A R max(c) to be smaller than A F max(a'). We allow this because the smaller A R max(c), the smaller A F max(x) and thus the more likely it is that the timing requirement is satisfied. or or or or Any signal S1 Speed-up allowed Slow-down not allowed (a) (b) a b a b cc or S0 or S1 or S1 or S0 Figure 4-35. AFAS requirements for a 2-input on-IX-sub-path NAND gate. (a): a has 1-to-0 logical IX-direction, (b): a has 0-to-1 logical IX-direction. For other types of on-IX-sub-path gates, we define logic-only AFAS requirements in a similar way. After initialization is done, logic-only forward and backward implication and justification procedures are invoked until all the circuit lines are justified. Alternative-(a), Phase (II): Satisfying the timing requirement. After getting to a point where all the circuit lines are justified, we run LTS and then check whether A F max BMD (x) < A R min BMD (y) – λ (refer to Figure 4-23 (a)). When the requirement is satisfied, we have found the test. When the requirement is not satisfied, there might be a possibility that it will be satisfied if the current partially specified two-pattern input sequence is further specified. If there is no such a possibility, we backtrack in the search tree of the ATPG core (We go back to Phase (I)). But if such a possibility exists, we enumerate different ways of fully specifying the two-pattern input sequence. Each time, we use LTS to calculate the new timing parameters and check whether the timing requirement is satisfied. If we come across a situation where the timing requirement is 152 satisfied, we have found a test. We maintain an enumeration count and consider a limit for that. When the limit is reached, we backtrack in the search tree of the ATPG core (we go back to Phase (I)). It must be noted that in Phase (I), whenever we run out of alternatives, we choose the next shortest IX-sub-path and repeat the same steps. Alternative-(b), Phase (I): Satisfying the logic requirements. In conjunction with alternative (b), the composite value injected at the affecting line is {S0, T1, H0}. In Figure 4-23 (b), it is more likely that the timing requirement is satisfied if A R min(x) is as large as possible. Therefore, as a heuristic, a long IX-sub-path is targeted and appropriate logic-only auxiliary IV-affecting signal (AIAS) requirements are defined. For an on-IX-sub-path NAND gate g with on-sub-path input a, we define logic-only AIAS requirements as follows. If a has 0-to-1 logical IX-direction, On-sub-path requirement: S a = {S0, T1, H0}, and Off-sub-path requirement: None. The requirements are illustrated in Figure 4-36 (b) for a 2-input on-IX-sub-path NAND gate. If the signal implied at b is {S1}, A F min(c) = A R min(a'). Any signal other than S1 might make A F min(c) to be larger than A R min(a'). We allow this because the larger A F min(c), the larger A R min(x) and thus the more likely it is that the timing requirement is satisfied. If a has 1-to-0 logical IX-direction, On-sub-path requirement: S a = {S1, T0, H1}, and Off-sub-path requirement: For every off-sub-path input b, S b = {S1}. 153 The requirements are illustrated in Figure 4-36 (a) for a 2-input on-IX-sub-path NAND gate. If the signal implied at b is a {S1}, A R min(c) = A F min(a'). Any signal other than S1 might make A R min(c) to be smaller than A F min(a'). We do not allow this because the smaller A R min(c), the smaller A R min(x) and thus the less likely it is that the timing requirement is satisfied. or or or or Any signal Speed-up not allowed Slow-down allowed S1 (a) (b) a b a b cc or S0 or S1 or S0 or S1 Figure 4-36. AIAS requirements for a 2-input on-IX-sub-path NAND gate. (a): a has 1-to-0 logical IX-direction, (b): a has 0-to-1 logical IX-direction. For other types of on-IX-sub-path gates, we define logic-only AIAS requirements in a similar way. After initialization is done, logic-only forward and backward implication and justification procedures are invoked until all the circuit lines are justified. Alternative-(b), Phase (II): Satisfying the timing requirement. This phase is executed similar to the case of Alternative-(a). The only difference is that the timing requirement that is checked is A R max BMD (y) + µ < A R min BMD (x) (refer to Figure 4-23 (b)) and whenever we run out of alternatives in Phase (I), we choose the next longest IX-sub-path and repeat the same steps. 4.5.2.1 Experimental results We have used the developed procedure for generating R + -tests and relaxed R + -tests for macro-surrogates defined in association with WRB sites in combinational parts of 154 ISCAS 89 benchmark circuits. We applied our procedure to the same WRB sites considered in conjunction with the experimental results reported in Chapter 3. For each macro-surrogate that was found R + -testable there, our new procedure finds an R + -test in the same way. However, for some macro-surrogates that were not R + -testable, our new procedure finds relaxed R + -tests. This results in higher coverage of WRB sites. In Table 4-2, the extra coverage achieved and the new total coverage have been reported. Table 4-2. Coverage. Coverage Circuit Total #of WRB sites with the specifications stated in Section 3.1 Total achieved in Chapter 3 Extra achieved through using relaxed R + -tests New total S349 109,718 69,418 (63.27%) 10,752 (9.80%) 80,170 (73.07%) S444 183,876 137,631 (74.85%) 13,386 (7.28%) 151,017 (82.13%) S510 245,930 115,194 (46.84%) 27,175 (11.05%) 142,369 (57.89%) S641 323,964 224,054 (69.16%) 19,891 (6.14%) 243,945 (75.30%) S820 657,714 434,354 (66.04%) 67,021 (10.19%) 501,375 (76.23%) 4.5.2.2 Conclusion, notes and future work We have developed a procedure for generating R + -tests and relaxed R + -tests for macro-surrogates under the BMD. Using this procedure, considerably higher coverage of macro-surrogates and thus WRB sites is achieved compared to the framework discussed in Chapter 3 that assumes MGDF. Similar to the implemented test generation framework for crosstalk-induced delay faults (Section 4.5.1) simplifications used and separating the task of satisfying logic and 155 timing requirements due to unavailability of timing-oriented implication and justification procedures, limits the extra coverage achieved. Furthermore, we only focused in relaxing the affecting signal requirement. By incorporating a more accurate simulation approach and timing-oriented implication and justification procedures, also by focusing on relaxation of robust requirements along the IY- and YO-sub-paths, and also by using appropriate heuristics, relaxed R + -tests can be found for more of the R + - untestable macro-surrogates and thus higher coverage will be achieved. These are subjects of our future research studies. 156 References [1] M. Abramovici, M. A. Breuer, and A. D. Friedman, “Digital Systems Testing and Testable Design”, IEEE Press, 1990. [2] X. Bai, and S. Dey, A. Krstic, “HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk”, Proc. Int. Test Conf., pp. 112-121, 2003. [3] H. B. Bakoglu, “Circuits, Interconnects, and Packaging for VLSI”, Addison- Wesley, 1990. [4] M. A. Breuer, and S. K. Gupta, “Process Aggravated Noise (PAN): New Validation and Test Problems”, Proc. Int. Test Conf., pp. 914-923, 1996. [5] F. Caignet, S. Delmas-Bendhia, and E. Sicard, “The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology”, Proc. of the IEEE, Volume 89, No. 4, pp. 556-573, Apr. 2001. [6] T. J. Chakraborty and V. D. Agrawal, “Effective Path Selection for Delay Fault Testing of Sequential Circuits,” Proc. Int. Test Conf., pp. 998–1003, 1998. [7] L.-C. Chen, S. K. Gupta, and M. A. Breuer, “A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation”, Proc. Asian Test Symp., pp. 102-107, 2000. [8] ——, “TA-PSV-Timing Analysis for Partially Specified Vectors”, Journal of Electronic Testing: Theory and Applications, pp. 73-88, 2002. [9] W. Y. Chen, S. K. Gupta, and M. A. Breuer, “Analytic Models for Crosstalk Delay and Pulse Analysis for Non-Ideal Inputs”, Proc. Int. Test Conf., pp. 809- 818, 1997. [10] ——, “Analytic Models for Crosstalk Excitation and Propagation in VLSI Circuits”, IEEE Trans. on Computer-Aided Design, Volume 21, Issue 10, pp. 1117-1131, Oct. 2002. [11] ——, “Test Generation for Crosstalk-Induced Delay in Integrated Circuits”, Proc. Int. Test Conf., pp. 191-200, 1999. [12] ——, “Test Generation for Crosstalk-Induced Faults: Framework and Computational Results”, Journal of Electronic Testing: Theory and Applications, pp. 17-28, 2002. 157 [13] K.-T. Cheng, and H.-C. Chen, “Classification and Identification of Nonrobust Untestable Path delay faults”, IEEE Trans. on Computer-Aided Design of Integrated Circuits, Volume 15, Issue 8, pp. 845-853, Aug. 1996. [14] K.-T. Cheng, A. Krstic, and H.-C. Chen, “Generation of High Quality Tests for Robustly Untestable Path Delay Faults”, IEEE Trans. on Computers, Volume 45, No. 12, pp. 1379-1392, Dec. 1996. [15] B. Dervisoglu, and G. Strong, “Design for Testability: Using ScanPath Techniques for Path-Delay Test and Measurement”, Proc. Int. Test Conf., pp. 365- 374, 1991. [16] S. Devadas, A. Ghosh, and K. Keutzer, “Logic Synthesis”, McGraw-Hill, 1994. [17] E.B. Eichelberger, and T. W. Williams, “A logic Design Structure for Design for Testability”, Proc. Design Automation Conf., pp. 462-468, 1977. [18] P. Engelke, I. Polian, M. Renovell, and B. Becker, “Simulating Resistive Bridging and Stuck-at Faults”, Proc. Int. Test Conf., pp. 1051-1059, 2003. [19] F. J. Ferguson, and J. P. Shen, “A CMOS Fault Extractor for Inductive Fault Analysis”, IEEE Transactions on Computer-Aided Design, Volume 7, No. 11, pp. 1181-1194, Nov. 1988. [20] K. Fuchs, F. Fink, and M. H. Schulz, “Dynamite: An Efficient Automatic Test pattern Generation System for Path Delay Faults”, IEEE Trans. on Computer- Aided Design of Integrated Circuits and Systems, Volume 10, Issue 10, pp. 1323- 1335, Oct. 1991. [21] T. Gneiting, and I. P. Jalowiecki, “ Influence of Process Parameter Variations on the Signal Distribution Behavior of Wafer Scale Integration Devices”, IEEE Trans. on Components, Packaging, and Manufacturing Technology – Part B, Volume 17, No. 3, pp. 424-430, Aug. 1995. [22] C. F. Hawkins, J. M. Soden, A. W. Righter, and F. J. Ferguson, “Defect Classes – An Overdue Paradigm for CMOS IC Testing”, Int. Test Conf., pp. 413-425, 1994. [23] E. P. Hsieh, R. A. Rasmussen, L. J. Vidunas, and W. T. Davis, “Delay Test Generation”, Proc. Design Automation Conf., pp. 486-491, 1977. [24] S. Irajpour, S. K. Gupta, and M. A. Breuer, “Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models”, Int. Test Conf., pp. 1024-1033, 2004. 158 [25] S. Irajpour, S. Nazarian, L. Wang, S. K. Gupta, and M. A. Breuer, “Analyzing Crosstalk in the Presence of Weak Bridge Defects”, VLSI Test Symp., 385-392, 2003. [26] A. Jee, and F. J. Ferguson, “Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits”, IEEE VLSI Test Symp., pp. 92-98, 1993. [27] N. K. Jha, and S. K. Gupta, “Testing of Digital Systems”, Cambridge University Press, 2003. [28] A. Krstic, and K.-T. Cheng, “Delay Fault Testing for VLSI Circuits”, Kluwer Academic Publishers, 1998. [29] A. Krstic, J.-J. Liou, and K.-T. Cheng, “Delay Testing Considering Crosstalk- Induced Effects”, Proc. Int. Test Conf., pp. 558-567, 2001. [30] W. K. Lam, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vicentelli, “Delay Fault Coverage, Test Set Size, and Performance Trade-Offs”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 14, Issue 1, pp. 32-44, Jan. 1995. [31] C. Lee, and D. M. H. Walker, “PROBE: A PPSFP Simulator for Resistive Bridging Faults”, Proc. VLSI Test Symp., pp. 105-110, 2000. [32] K. T. Lee, C. Nordquist, and J. A. Abraham, “Test Generation for Crosstalk Effects in VLSI Circuits”, Proc. Int. Symp. on Circuits and Systems, Volume 4, pp. 628-631, May 1996. [33] J. P. Lesser, and J. J. Shedletsky, “An experimental Delay Test Generator for LSI Logic”, IEEE Trans. on Computers, Volume C-29, No. 3, pp. 235-248, Mar. 1980. [34] H. Li, P. Shen, and X. Li, “Robust Test Generation for Precise Crosstalk-Induced Path Delay Faults”, Proc. VLSI Test Symp., 2006. [35] W. N. Li, S. M. Reddy, and S. K. Sahni, “On Path Selection in Combinational Logic Circuits,” IEEE Trans. on Computer-Aided Design, Volume CAD–6, pp. 694–703, Sept. 1987. [36] Z. Li, X. Lu, W. Qiu, W. Shi, and D. M. H. Walker, “A Circuit Level Fault Model for Resistive Bridges”, VLSI Test Symp., 379-384, 2003. [37] C. J. Lin, and S. M. Reddy, “On Delay Fault Testing in Logic Circuits”, IEEE Trans. on Computer-Aided Design, Volume 6, Issue 5, pp. 694-703, Sep. 1987. 159 [38] T. Maeda, and K. Kinoshita, “Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits”, Proc. Int. Test Conf., pp. 510-519, 2000. [39] S. Mandava, S. Chakravarty, S. Kundu, “On Detecting Bridges Causing Timing Failures”, Proc. Int. Conf. on Computer Design, pp. 400-406, 1999. [40] W. Moore, G. Gronthoud, K. Baker, and M. Lousberg, “Delay Fault Testing and Defects in Sub-Micron ICs – Does Critical Resistance Really Mean Anything?” Proc. Int. Test Conf., pp. 95-104, 2000. [41] C. S. Murthy and M. Gall, “Process Variation Effects on Circuit Performance: TCAD Simulation of 256-Mbit Technology”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 16, No. 11, pp. 1383-1389, Nov. 1997. [42] S. Natarajan, M. A. Breuer, and S. K. Gupta, “Process Variations and Their Impact on Circuit Operation”, Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 73-81, 1998. [43] F. Nekoogar, “Timing Verification of Application-Specific Integrated Circuits”, Prentice Hall, 1999. [44] A. K. Pramanick and S. M. Reddy, “On the Fault Coverage of Gate Delay Fault detecting Tests”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 16, No. 1, pp. 78-94, Jan. 1997. [45] M. Renovell, F. Azais, and Y. Bertrand, “Detection of Defects Using Fault Model Oriented Test Sequences”, Journal of Electronic Testing: Theory and Applications, Volume 14, pp. 13-22, 1999. [46] M. Renovell, P. Huc, and Y. Bertrand, “CMOS Bridging Fault Modeling”, VLSI Test Symp., pp. 392-397. [47] M. Renovell, P. Huc, and Y. Bertrand, “The Concept of Resistance Interval: A New Parametric Model for Realistic Resistive Bridging Fault”, VLSI Test Symp., pp. 184-189, 1995. [48] R. Rodriguez-Montanes, E. Bruls, and J. Figueras, “Bridging Defect Resistance Measurements in a CMOS Process”, Proc. Int. Test Conf. , pp. 892-899, 1992. [49] J. P. Roth, W. G. Bouricius, and P. R. Schneider, “Programmed Algorithms to Compute Tests to Detect and Distinguish between Failures in Logic Circuits”, IEEE Trans. on Electronic Computers, Volume EC-16, No. 10, pp. 567-579, Oct. 1967. 160 [50] V. R. Sar-Dessai, and D. M. H. Walker, “Resistive Bridge Fault modeling, Simulation and Test Generation”, Proc. Int. Test Conf., pp. 596-605, 1999. [51] P.-F. Shen, H.-W. Li, Y.-J. Xu, and X.-W. Li, “Non-Robust Test Generation for Crosstalk-Induced Delay Faults”, Proc. Asian Test Symp., pp. 120-125, 2005. [52] A. Sinha, S. K. Gupta, and M. A. Breuer, “An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults”, in Proc. Asian Test Symp., pp. 174- 177, 2003. [53] G. L. Smith, “A Model for Delay Faults Based on Paths”, Proc. Int. Test Conf., pp. 342-349, 1985. [54] J. J. T. Sousa, F. M. Goncalves, and J. P. Teixeria, “IC Defects-Based Testability Analysis”, Proc. Int. Test Conf., pp. 500-509, 1991. [55] T. M. Storey, and J. W. Barry, “Delay Test Simulation”, Proc. Design Automation Conf., pp. 492-494, 1977. [56] C. H. Strapper, J. A. Patrick, and R. J. Rosner, “Yield Model for ASIC and Processor Chips”, Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 136-143, 1993. [57] C. H. Strapper, A. J. Rideout, “On Fractal Yield Models: A statistical Paradox”, Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 83- 87, 1994. [58] C. H. Strapper and R. J. Rosner, “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation”, IEEE trans. on Semiconductor Manufacturing, Volume 8, No. 2, pp. 95-102, May 1995. [59] I. Sutherland, B. Sproull, D. Harris, “Logical Effort – Designing Fast CMOS Circuits”, Morgan Kaufmann Publishers, Inc., 1999. [60] L. Wang, S. K. Gupta, and M. A. Breuer, “Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects Between On-Chip Interconnects”, Proc. Asian Test Symp., pp. 440-447, 2004. [61] M. Williams, and J. Angell, “Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic”, IEEE Trans. on Computers, Volume C-22, Issue 1, pp. 46-60, Jan. 1973. [62] “International Technology Roadmap for Semiconductors, 2005 Edition”, [Online]. Available: http://www.itrs.net. 161 Appendices Appendix A: Preliminaries A.1 Pin-to-pin delay model Different variations of the pin-to-pin delay model have been used in the literature. All through this dissertation, by “pin-to-pin delay model” we mean a specific variation of the model, the underlying assumptions of which are presented in Section A.1.1. The corresponding implications are presented in Section A.1.2. A.1.1 Underlying assumptions It is assumed that delay in propagating a rising or a falling transition in the signal implied at an input of a gate to the output of the gate is independent of the signals at other inputs of the gate. It is assumed that delay phenomenon is transport delay [1] and no inertial delay [1] exists. In other words, each gate is modeled as a zero-delay Boolean function together with delay mechanisms at each input. An example is shown in Figure A-1. For input a of gate g 1 , the pin-to-pin rising and falling delays are denoted by 1 R d a g and 1 F d a g , respectively. For each input of a gate, a virtual delayed point is imagined, e.g., a' in Figure A-1. a b c a' b' Zero delay a b c g 1 Figure A-1. Pin-to-pin delays; virtual delayed points, a' and b'. 1 R d a g 1 F d a g 1 R d b g 1 F d b g 162 When capacitive or resistive coupling 1 exists between the output of gate g 1 and the output of a gate g 2 , delay in propagating a rising transition in the signal at a, S a , to c, as shown in Figure A-2, is 11 RR nc d aa gg +∆ , where 1 R nc d a g represents delay if the coupling did not exist (nc: no coupling) and 1 R a g ∆ represents the change in delay due to the presence of the coupling. Shapes of the signals implied at the inputs of g 2 affect the value of 1 R a g ∆ to a great extent (as will be discussed in more detail in Appendices C and D). In other words, 1 R a g ∆ is not a fixed value. Furthermore, strengths of the gates g 1 and g 2 and the amount of load driven by them are other factors that also determine the value of 1 R a g ∆ . Similar observations hold for delay in propagating a falling transition in S a to c and also delays in propagating rising and falling transitions in S b to c (Figure A-2). a b c a' b' Zero delay a b c g 1 g 2 Capacitive or resistive coupling Figure A-2. Pin-to-pin delays in the presence of coupling. A.1.2 Implications A.1.2.1 Intervals at virtual delayed points Under the pin-to-pin delay model, if the signal at input a of a gate g, S a , is at logic-0 during interval 11 [tb , te ] and if FR 11 tb d te d aa gg +< + , the signal at the 1 Resistive coupling might exist due to a manufacturing defect that manifests itself as a bridge with non- zero resistance. 11 1 RR R nc dd aa a gg g =+∆ 11 1 FF F nc dd aa a g gg =+∆ 11 1 RR R nc dd bb b gg g =+∆ 11 1 FF F nc dd bb b g gg =+∆ 163 corresponding virtual delayed point a', S a' , is at logic-0 during interval FR 11 [tb d , te d ] aa gg ++ . The reason beyond this can be explained as follows: if S a is at logic-1 prior to 1 ttb = , the falling transition at 1 ttb = in S a arrives at F 1 ttb d a g =+ in S a' and thus S a' is at logic-0 starting from F 1 ttb d a g =+ . Moreover, if S a is at logic-1 after 1 tte = , the rising transition at 1 tte = in S a arrives at R 1 tte d a g =+ in S a' and thus the logic-0 interval in S a' ends at R 1 tte d a g =+ . Similarly, if S a is at logic-1 during interval 11 [tb , te ] and if RF 11 tb d te d aa gg +< + , S a' is at logic-1 during interval RF 11 [tb d , te d ] aa gg ++ . An example is shown in Figure A-3. All through this dissertation, a primed circuit line represents the virtual delayed point of the line with the corresponding unprimed name. S a S a' aa' R 1 td a g + 1 t 2 t 3 t F 2 td a g + R 3 td a g + RF d, d aa g g 4 t F 4 td a g + Figure A-3. An example illustrating the relationship between the signal at a circuit line and that at its corresponding virtual delayed point. If S a is at logic-0 during interval 11 [tb , te ] and FR 11 tb d te d aa gg +> + , logic-0 interval 11 [tb , te ] in S a does not cause any logic-0 interval in S a' . The same is true in conjunction with a logic-1 interval. An example is shown in Figure A-4 where logic-0 interval 23 [t , t ] in S a does not cause any logic-0 interval in S a' . Note that in this example, logic-1 intervals 12 [t , t ] and 34 [t , t ] in S a together constitute a long interval 164 RF 14 [t d , t d ] aa gg ++ in S a' which is the union of the two intervals RF 12 [t d , t d ] aa gg ++ and RF 34 [t d , t d ] aa gg ++ caused by the two intervals in S a , individually. S a S a' R 1 td a g + 1 t 2 t 3 t F 2 td a g + R 3 td a g + 4 t F 4 td a g + Figure A-4. An example illustrating that an interval in S a does not create any corresponding interval in S a' . A.1.2.2 Processing intervals through gates Intervals 11 1 I[tb , te ] = and 22 2 I[tb , te ] = have an intersection if max-tb min-te < , where 12 max-tb Max(tb , tb ) = and 12 min-te Min(te , te ) = . Interval [max-tb, min-te] is the intersection interval. Under the pin-to-pin delay model, for a 2-input NAND gate with input lines a and b and output c, a logic-1 interval, I 1 = [tb 1 , te 1 ], in S a' together with a logic-1 interval, I 2 = [tb 2 , te 2 ], in S b' create a logic-0 interval in S c if I 1 and I 2 have an intersection. The resulting logic-0 interval in S c is the intersection interval of I 1 and I 2 . An example is shown in Figure A-5. The above discussion can be extended to NAND gates as well as AND gates (logic-1 intervals at inputs; logic-1 interval at output) with any number of inputs. It can also be extended to NOR gates (logic-0 intervals at inputs; logic-1 interval at output) as well as OR gates (logic-0 intervals at inputs; logic-0 interval at output). 165 S a' t 1 t 2 S b' t 3 t 4 S c t 1 t 2 Figure A-5. Logic-1 intervals in S a' and S b' create a logic-0 interval in S c . Under the pin-to-pin delay model, for a 2-input NAND gate with input lines a and b and output c, logic-0 interval [tb, te] in either S a' or S b' makes S c to be at logic-1 in the interval [tb, te]. Examples are shown in Figure A-6. Note that in Figure A-6 (b), logic-0 intervals 12 [t , t ] and 34 [t , t ] in S a' and S b' have an intersection and thus together constitute a long logic-1 interval 14 [t , t ] in S c which is the union of the two intervals created by the intervals in S a' and S b' , individually. The above discussion can be extended to NAND gates as well as AND gates (logic-0 intervals at inputs; logic-0 interval at output) with any number of inputs. It can also be extended to NOR gates (logic-1 intervals at inputs; logic-0 interval at output) as well as OR gates (logic-1 intervals at inputs; logic-1 interval at output). S a' t 3 t 4 S b' t 1 t 2 S c t 1 t 4 S a' t 3 t 4 S b' t 1 t 2 S c t 1 t 2 t 3 t 4 (a) (b) Figure A-6. Logic-0 intervals in S a' and S b' create logic-1 intervals in S c . 166 A.2 Signals implied at circuit lines under two-pattern input sequences The focus of this dissertation is on delay testing. As mentioned in Section 1.1, a delay test is a two-pattern sequence <P i , P t >. At t = 0, P t is applied to the circuit that has been long stabilized under P i . When such a two-pattern sequence is applied to the circuit, the signal at a circuit input has one of the forms shown in Figure A-7. t = 0 + ∞ −∞ t = 0 +∞ −∞ t = 0 + ∞ − ∞ t = 0 + ∞ −∞ Figure A-7. Signals at circuit inputs under two-pattern input sequences. In the previous section, it was discussed how, under the pin-to-pin delay model, as a result of logic-0 or logic-1 intervals in the signals implied at a gate’s inputs, intervals of logic-0 and logic-1 are implied in the signal at the gate output. In general, it can be shown that the signal implied at any circuit line a under a two-pattern input sequence either is statically at logic-0 or logic-1 or has the general format shown in Figure A-8. As can be seen, the signal implied at the line might contain one or more rising and/or falling transition edges. For a rising transition edge, say R a i (i: an integer), the arrival time is denoted by R A a i . Similarly, for a falling transition edge F a j (j: an integer), the arrival time is denoted by F A a j . R i a F j a t = 0 +∞ −∞ Figure A-8. The general format of a non-static signal at a circuit line a. All through this dissertation, by “signal” at a line we mean the signal implied at the line as a result of a two-pattern input sequence applied to the circuit inputs. 167 When the signal at a circuit line is statically at logic-0, it is said that the signal is a static logic-0. Static logic-1 is defined in a similar way. When the signal at a circuit line has logic-0 initial value and logic-1 final value, it is said that the signal at the line is a rising transition. In such a situation, if there exists only one rising transition edge, the signal is called a clean rising transition. Else it is called a hazardous rising transition. Clean falling transition and hazardous falling transition are defined in a similar way. When the signal at a circuit line has logic-0 initial value as well as logic-0 final value and there exists at least one rising transition edge and one falling transition edge in the signal, it is said that the signal at the line is a hazardous logic-0. A hazardous logic-1 is defined in a similar way. Lemma A-1: Under the pin-to-pin delay model, any transition edge in the signal implied at a gate’s output is the result of the propagation of individual transition edges in the signals at one or more of the gate’s inputs. The arrival time of the transition edge at the output is equal to the sum of the arrival time of one of the involved transition edges at one of the inputs and the corresponding delay value. Proof: Without loss of generality assume the gate, g, to be a 2-input NAND gate with inputs a and b and output c. Under the pin-to-pin delay model, the situations illustrated in Figure A-9 along with their duals (when a and b are interchanged) constitute all possible cases where the output signal might have at least one transition when the non- static signals at a and b are clean rising/falling transitions. In cases (a), (b) and (d), the 168 falling transition edge in S c is the result of the propagation of the rising transition edge in S a and 11 R FR AA d ca a g =+ . In case (c), the falling transition edge in S c is the result of the propagation of the rising transition edge in S b and 11 R FR AA d cb b g =+ . In cases (d) and (f), the rising transition edge in S c is the result of the propagation of the falling transition edge in S b and 11 F RF AA d cb b g =+ . In cases (e) and (g), the rising transition edge in S c is the result of the propagation of the falling transition edge in S a and 11 F RF AA d . ca a g =+ At the boundary between the cases (b) and (c), i.e., when 11 R R RR Ad A d , ab ab g g += + the falling transition edge in S c is the result of the propagation of both the rising transition edge in S a and that in S b and 11 R FR AA d ca a g =+ 1 R R Ad b b g =+ . At the boundary between the cases (f) and (g), i.e., when 1 F F Ad a a g + 1 F F Ad b b g =+ , the rising transition edge in S c is the result of the propagation of both the falling transition edge in S a and that in S b and 11 1 F F RF F AA d A d ca b ab g g =+ = + . Therefore, when the non-static signals at a and b are clean rising/falling transitions, the lemma is true. Now, let us focus on the case where S a is not a clean transition (i.e., where multiple transition edges exist in S a ) and S b is a static logic-1. Let us consider the example situation shown in Figure A-10. 1 R a tends to cause a fall in S c at time 1 R R Ad a a g + . Furthermore, 1 F a tends to cause a rise in S c at time 1 F F Ad . a a g + If 11 RF RF Ad A d aa aa gg +< + , a hazardous logic-1 consisting of a falling transition at time 1 R R Ad a a g + and a rising transition at time 1 F F Ad a a g + occurs at c (Figure A- 10(a)). In such a situation, each transition edge in S c is the result of the propagation of a transition edge in S a and the corresponding arrival time is simply the arrival time of the transition edge at a plus the corresponding delay value ( 11 R FR A=A d ca a g + and 169 11 F RF A=A d ca a g + , respectively). If 11 RF RF Ad A d aa aa gg +> + , the rising transition edge is masked by the falling transition edge due to the delay mechanism at a and no transition occurs in S c (Figure A-10(b)). Under the pin-to-pin delay model, for a general situation with a static logic-1 implied at b, a transition edge in S a might get masked by a time-adjacent opposite-direction transition edge due to the delay mechanism at the gate input. However, if masking does not occur and a transition edge really propagates through the gate, the arrival time of the resulting transition edge at the output is not affected by the other transition edges in S a and is simply the arrival time of that transition edge in S a plus the corresponding delay value. Now, let us focus on the very general situation. Under the pin-to-pin delay model, a rising transition edge in S a that is not masked by a time-adjacent falling transition edge in S a , say R a i (i: an integer), tends to cause a fall in S c at time R R Ad a i a g + . S b might tend to cause a rise or a fall in S c at the same time. When rising transition edge R b j (j: an integer), not masked by a time-adjacent falling transition edge, exists in S b such that R R R R Ad A d b a j i ab g g += + , a falling transition occurs in S c at time R R Ad a i a g + R R Ad b j b g =+ (R b j tends to cause a fall in S c at the same time). When falling transition edge F b k (k: an integer), not masked by a time-adjacent rising transition edge, exists in S b such that F R RF Ad A d ab ik ab g g += + , no transition actually occurs in S c at time R R Ad a i a g + F F Ad b k b g =+ (F b k tends to cause a rise in S c at the same time). In the case where S b does not tend to cause a transition in S c at time R R Ad a i a g + , if S b tends to imply a logic-0 in S c at the time, a falling transition occurs in S c at time R R Ad a i a g + and if S b implies a logic-1 in S c at the time, no transition occurs in S c at 170 time R R Ad a i a g + . Similar discussion can be presented in conjunction with a falling transition edge in S a . The above discussion states that, under the pin-to-pin delay model, any transition edge in S c is the result of the propagation of a transition edge in S a , a transition edge in S b , or individual transition edges in both S a and S b (note: due to the presence of defects and process variations, we do not know which specific one(s)) and the arrival time of the transition edge in S c is equal to arrival time of the responsible transition edge (in S a or in S b or in both) plus the corresponding delay value. This discussion can be easily generalized to any type of gate with any number of inputs and proves the lemma to be true in a general situation. ■ A note in Lemma A-1: When coupling exists between the output of the gate and the output of another gate, Lemma A-1 still holds true but it should be noted that in such a situation, the ‘ ∆’ term exists in the pin-to-pin delay value which depends on the shapes of the signals at the inputs of that other gate (refer to Section A.1.1). 171 Figure A-9. c has at least one transition when the non-static signals at a and b are clean transitions. 172 b a c g S1 S a' S b' S c S a' S b' S c (a) (b) Figure A-10. S a not a clean transition, S b static logic-1. Lemma A-2: Under the pin-to-pin delay model, under any two-pattern input sequence, a transition edge in the signal implied at a circuit line is the result of the propagation of a transition along one or more of the logical sub-paths that start at circuit inputs and end at the line. The arrival time of the transition edge is equal to the delay of each such logical sub-path. Proof: Let us focus on a transition edge in the signal implied at circuit line c. Let us focus on the gate that drives c, g c (if c is a fan-out branch, the gate that drives the stem is considered instead). Under the pin-to-pin delay model, Lemma A-1 introduces individual transition edges in the signals implied at one or more input lines of g c as being responsible for the invocation of the transition edge in S c . Assume that a transition edge in S a , where a is an input of g c , is such a transition edge. Now let us 1 R a 1 F a 1 R R Ad a a g + 1 F F Ad a a g + 1 F F Ad a a g + 11 R FR A=A d ca a g + 11 F RF A=A d ca a g + 11 RF RF Ad A d aa aa g g +< + 11 FR FR Ad A d aa aa g g +< + 1 R R Ad a a g + 173 focus on the gate that drives a, g a (if a is a fan-out branch, the gate that drives the stem is considered instead). Lemma A-1 also introduces individual transition edges in the signals implied at one or more input lines of g a as being responsible for invocation of the transition edge in S a . This backward traversal can be continued until a circuit input is reached. The circuit lines that are traversed constitute a sub-path that starts from a circuit input and ends at line c and the arrival time of the transition edge in S c is equal to the sum of the pin-to-pin delay values all along the sub-path considering the inversion of the gates along the sub-path. In fact, the arrival time of the transition edge in S c is equal to the delay of one of the two corresponding logical sub-paths. It is possible that the transition edge in S c is also the result of the propagation of a transition edge in the signal implied at another input of gate g c , say b. A similar backward traversal can be carried out until a circuit input is reached. The circuit lines that are traversed constitute another sub-path that starts from a circuit input and ends at c and the arrival time of the transition edge in S c is also equal to the delay of one of the two corresponding logical sub-paths. At each gate that is visited during the above mentioned backward traversals, the transition edge at the output might be the result of the propagation of individual transition edges in the signals implied at more than one input. Therefore, in general, the arrival time of the transition edge in S c might be equal to the delay of multiple logical sub-paths that start at circuit inputs and end at c. ■ 174 A note in Lemma A-2: When a coupling exists between a line on the sub-path and another line l in the circuit, Lemma A-2 still holds true but it should be noted that in such a situation, the corresponding delay value in the “sum” depends on the signals implied at the circuit lines that drive l (refer to “A note about Lemma A-1” and also Section A.1.1). Corollary A-1: Under the pin-to-pin delay model for gates, under any two-pattern input sequence, a transition edge in the signal implied at a circuit output is the result of the propagation of a transition along one or more of the logical paths that end at the output. The arrival time of the transition edge is equal to the delay of each such logical path. When, under a two-pattern input sequence, a transition edge in the signal implied at a circuit line l is the result of the propagation of a transition along a logical path that goes through l (and thus its arrival time is equal to the delay of the portion of the logical path from its input to l) the transition edge in S l is called the characteristic transition edge (CTE) of the logical path at l. When a transition edge in the signal implied at a circuit output o is the CTE of a logical path that ends at o, there exists a transition edge in the signal implied at every on-path circuit line that is the CTE of the logical path at that on-path line. The logical path is called a sensitization logical path for the transition edge in S o and it is said that the CTE of the logical path exists along the path. Corollary A-1 can be re-written as follows. 175 Corollary A-1: Under the pin-to-pin delay model for gates, under any two-pattern input sequence, a transition edge in the signal implied at a circuit output is the CTE of one or more of the logical paths that end at the output. A.3 CTE of FS-untestable logical paths Let us focus on a rising logical path, P 1 R . Under a two-pattern input sequence that implies a rising transition at the input of P 1 , an on-path gate is said to satisfy the property-set-I, if – The on-path input of the gate has a ncv-to-cv (i.e., 1-to-0 when the on-path gate is a NAND or an AND gate, or 0-to-1 when the on-path gate is a NOR or an OR gate) logical direction, – The final value of the on-path input is the controlling value of the gate, and – The signal implied at at least one of the off-path inputs of the gate is static controlling value of the gate. Furthermore, under a two-pattern input sequence that implies a rising transition at the input of P 1 , an on-path gate is said to satisfy the property-set-II, if – The on-path input of the gate has a cv-to-ncv (i.e., 0-to-1 when the on-path gate is a NAND or an AND gate, or 1-to-0 when the on-path gate is a NOR or an OR gate) logical direction, – The final value of the on-path input is the non-controlling value of the gate, and – For at least one of the off-path inputs of the gate, the final value is the controlling value of the gate. 176 Let us assume that P 1 R is FS-untestable. Under a two-pattern input sequence that implies a rising transition at the input of P 1 , either there is at least one on-path gate that satisfies the property-set-I, or if this not the case, there is at least one on-path gate that satisfies the property-set-II. In the rest of this section, we focus on a situation where under a two-pattern input sequence that implies a rising transition at the input of P 1 R , the CTE of P 1 R exists along the path. In such a situation, no on-path gate satisfies the property-set-I and at least one on-path gate satisfies the property-set-II. An example circuit with FS-untestable logical path P 1 R is illustrated in Figure A-11 under four different two-pattern input sequences, T 1 , T 2 , T 3 , and T 4 . Under all the four two-pattern input sequences, a rising transition is implied at the input of P 1 and gate g 1 is the last on-path gate that satisfies the property- set-II. It is assumed that for each gate, each input has equal rising and falling delay values that are the same as those of the other input. The signals implied at the on-path lines from the output of g 1 , to the output of P 1 R , o, are analyzed below. 177 (a) Under T 1 a b g 1 i 1 e g 2 o g 3 c d f i 2 CTE of P 1 R at a CTE of P 2 F at b CTE of P 1 R at c i 3 CTE of P 2 F at c CTE of P 1 R at o CTE of P 2 F at o i 4 i 5 i 6 S0 S0 S1 S0 S1 S1 a b g 1 i 1 e g 2 o g 3 c d f i 2 CTE of P 1 R at a CTE of P 2 F at b CTE of P 1 R at c i 3 CTE of P 2 F at c CTE of P 1 R at o i 4 CTE of P 3 R at d i 5 i 6 S1 S0 S0 S1 CTE of P 1 R at e a b g 1 i 1 e g 2 o g 3 c d f i 2 CTE of P 1 R at a CTE of P 2 F at b CTE of P 1 R at c i 3 CTE of P 2 F at c CTE of P 1 R at o CTE of P 4 F at o i 4 CTE of P 3 R at d CTE of P 4 F at d i 5 i 6 S1 CTE of P 1 R at e CTE of P 4 F at e S1 S0 a b g 1 i 1 e g 2 o g 3 c d f i 2 CTE of P 1 R at a CTE of P 2 F at b CTE of P 1 R at c i 3 CTE of P 2 F at c CTE of P 1 R at o CTE of P 5 R at o i 4 CTE of P 5 R at f CTE of P 6 R at f i 5 i 6 S1 S0 S0 CTE of P 1 R at e CTE of P 2 F at e (b) Under T 2 (c) Under T 3 (d) Under T 4 P 1 R P 2 F P 1 R P 2 F P 3 R P 1 R P 2 F P 4 F P 3 R P 1 R P 2 F P 5 R P 6 R Figure A-11. An example circuit with an FS-untestable logical path under four different tests. 178 Under all the four two-pattern input sequences, the CTE of P 1 R exists in the signal implied at the output of g 1 , i.e., S c , because the arrival time of the falling transition edge in S b (which is the CTE of P 2 F at b) is greater than that of the CTE of P 1 R at a. In other words, the existence of the CTE of P 1 R in the signal implied at o, S o , is partly due to P 2 F having a delay greater than that of P 1 R . Under T 2 and T 3 , the CTE of P 1 R exists in S e also because the arrival time of the falling transition edge in S d (which is the CTE of P 3 R at d) is greater than that of the CTE of P 1 R at c. In other words, the existence of the CTE of P 1 R in S o is also due to P 3 R having a delay greater than that of P 1 R . Under T 4 , The CTE of P 1 R exists in S o also because the arrival time of the falling transition edge in S f (which is the CTE of P 5 R at f) is greater than that of the CTE of P 1 R at e. In other words, the existence of the CTE of P 1 R in S o is also due to P 5 R having a delay greater than that of P 1 R . Under all the four two-pattern input sequences, the existence of the CET of P 1 R along the path is due to one or more logical paths having delays greater than that of P 1 R . This can be proven to be true under any two-pattern sequence that implies a rising transition at the input of P 1 and leads to the existence of the CTE of P 1 R in S o . It can be further proven that at least one of the logical paths with greater delay than that of P 1 R which cause the CTE of P 1 R to exist in S o is FS-testable. Theorem A-1: Under a two-pattern input sequence, if the CTE of an FS-untestable logical path exists along the path, there must be an FS-testable logical path in the circuit (that at least shares its output with the FS-untestable logical path) whose delay is greater than that of the FS-untestable logical path. 179 Proof is beyond the scope of this dissertation. In the next section, we use the above result in the context of delay testing. 180 Appendix B: Delay testing using tests for logical paths In Sections 1.1.2.1 and 1.1.2.2, it was mentioned that, under the MGDF, an FS-test for a logical path is not a detecting-test for the logical path while an R-test is a detecting-test for the logical path. Furthermore, in Section 1.1.3, it was mentioned that when no path delay fault exists on FS-testable logical paths, even if path delay faults exist on the FS-untestable logical paths, no timing error might occur in the circuit. It was thus concluded that, under the MGDF, delay testing can be done using a test-set that contains an R-test for each FS-testable logical path. The above statements are referred to in the literature either explicitly or implicitly. For example, [13] states that FS-untestable logical paths can be excluded from the list of logical paths that need to be tested and in [30], FS-untestable logical paths are said to belong to the set of robust dependent logical paths and it has been stated that path delay faults on robust dependent logical paths cannot cause timing errors in the circuit unless a path delay fault exists on some R-testable logical path. In some cases proofs provided for the above statements are wrong. For example, [13] states that the reason why FS- untestable logical paths can be excluded is that such logical paths cannot be sensitized by any two-pattern input sequence in any fabricated copy of the circuit. This is contradicted by the example shown in Figure A-11 where an FS-untestable logical path, P 1 R , is sensitized under a two-pattern input sequence, T 2 . In this section, complete and accurate proofs are provided for all the above statements although for some of the statements, conceptually equivalent proofs are provided in the literature. The main reason why these proofs are included in this 181 dissertation is that testing for crosstalk- and bridge-induced delay faults using tests for surrogates and macro-surrogates (refer to Chapter 2 and Chapter 3) have similarities with delay testing using tests for logical paths and similar concepts are used in proving the corresponding theorems. All through this section, the MGDF and the pin-to-pin model are assumed. Theorem B-1: If no path delay fault exists on the logical paths in a circuit, no timing error might occur in the circuit. Proof: According to Corollary A-1, under a two-pattern input sequence, a transition edge in the signal implied at a circuit output is the CTE of a logical path that ends at the output and the arrival time of the transition edge is equal to the delay of the logical path. If no path delay fault exists on the logical paths in the circuit (i.e., the delay of each logical path is less than t S ), under any two-pattern input sequence, the arrival times of all the transition edges in the signals implied at all the circuit outputs are thus less than t S . In other words, the signals implied at all the circuit outputs stabilize to their final values before t S . Hence, no timing error occurs at any circuit output. ■ Theorem B-2: If no path delay fault exists on the FS-testable logical paths in a circuit, no timing error might occur in the circuit. 182 Proof: Consider a circuit in which no path delay fault exists on the FS-testable logical paths. If no path delay fault exists on the FS-untestable logical paths as well, according to Theorem B-1, no timing error might occur in the circuit. Now consider the more interesting case where a path delay fault exists on at least one of the FS-untestable logical paths. Under a two-pattern input sequence, no late transition edge (i.e. a transition edge whose arrival time is greater than t S ) might exist in the signal implied at any circuit output. If a late transition edge exists in the signal implied at a circuit output o, it must be the CTE of one or more FS-untestable logical paths that have path delay faults on them. (According to Corollary A-1, the transition edge is the CTE of a logical path that ends at o. It cannot be the CTE of an FS-testable logical path since no delay fault exists on such logical paths. Nor can it be the CTE of an FS-untestable logical path that has no path delay fault on it because delays of such logical paths are less than t S .) In such a situation, in conjunction with each FS- untestable logical path that is the sensitization logical path of the transition edge, according to Theorem A-1, there must be an FS-testable logical path whose delay is greater than the delay of the FS-untestable logical path and thus greater than t S . In other words, there must be an FS-testable logical path with a path delay fault on it. This contradicts the assumption that we made about the circuit. Therefore, under a two- pattern input sequence, no late transition edge might exist in the signal implied at any circuit output. In other words, the signals implied at all the circuit outputs stabilize to their final values before t S . Hence, no timing error occurs at any circuit output. What stated above 183 is true under any two-pattern input sequence. Hence, no timing error occurs in the circuit. ■ Theorem B-3: Consider a sub-path SP from circuit line i to circuit line o. Under the MGDF, suppose the first transition edge in the signal implied at i under a two-pattern input sequence is a rising (falling) transition. In conjunction with SP R (SP F ), if the two-pattern sequence satisfies robust requirements for every multiple-input on-sub-path gate 1 , the arrival time of the first transition edge in S o is greater than or equal to the delay of the logical sub-path plus the arrival time of the first transition edge in S i . Proof: Under a two-pattern input sequence that satisfies robust requirements for every multiple-input on-sub-path gate along SP R (SP F ), at each gate whose on-path input has a ncv-to-cv logical direction, the signal implied at the off-path input is the static non- controlling value of the gate. At each such gate, independent of whether gate delay faults exist, the arrival time of the first transition edge in the signal implied at the output is equal to the arrival time of the first transition edge in the signal implied at the on-path input plus the ncv-to-cv delay (i.e., falling delay when the on-path gate is a NAND or an AND gate and rising delay when the on-path gate is a NOR or an OR gate) of the on- path input. Furthermore, at each gate whose on-path input has a cv-to-ncv logical 1 Robust requirements for multiple input on-sub-path gates are defined similar to robust requirements for multiple-input on-path gates. 184 direction, the final value of the signal implied at the off-path input is the non-controlling value of the gate. At each such gate, independent of whether gate delay faults exist, the arrival time of the first transition edge in the signal implied at the output is greater than or equal to the arrival time of the first transition edge in the signal implied at the on- path input plus the cv-to-ncv delay (i.e., rising delay when the on-path gate is a NAND or an AND gate and falling delay when the on-path gate is a NOR or an OR gate) of the on-path input. Therefore, the arrival time of the first transition edge in S o is greater than or equal to the delay of the logical sub-path plus the arrival time of the first transition edge in S i . ■ Corollary B-1: Under an R-test for a logical path, even if path delay faults exist on other logical paths, the arrival time of the first transition edge in the signal implied at the output of the path is greater than or equal to the delay of the logical path. Theorem B-4: An R-test for a logical path is a detecting-test for the logical path. Proof: Let us refer to the output of the path as o. According to Corollary B-1, under an R- test for the logical path, even if path delay faults exist on other logical paths, the arrival time of first transition edge in S o is greater than or equal to the delay of the logical path. Meanwhile, existence of a path delay fault on the logical path means that the delay of 185 the logical path is greater than t S . In such a situation, the first transition in S o occurs after t S and thus S o (t S ) = IV(o) = FV( ) o . Therefore, an R-test for a logical path is a detecting-test for the logical path. ■ Theorem B-5: If a circuit passes a test-set that contains an R-test for each FS-testable logical path in the circuit, no timing error might occur in the circuit. Proof: According to Theorem B-4, an R-test for a logical path is a detecting-test for the logical path which means that when the circuit passes such a test, it can be concluded that no path delay fault exist on the logical path. When the circuit passes a test-set that contains an R-test for each FS-testable logical path in the circuit, it can be concluded that no path delay fault exists on the FS-testable logical paths. Therefore, according to Theorem B-2, no timing error might occur in the circuit. ■ In other words, under the MGDF, delay testing can be carried out using a test-set that contains an R-test for each FS-testable logical path in the circuit. 186 Appendix C: Testing for crosstalk-induced delay faults Throughout this section, it is assumed that a crosstalk site 1 with affecting line x and victim line y exists in the circuit for which x and y are not circuit inputs, circuit outputs, fan-out branches and are not in transitive fan-in of each other. x and y are assumed to not be fan-out branches to simplify the discussions and this assumption does not limit the generality of the argument. It is assumed that x and y are driven by the gates g x and g y , respectively. It is assumed that circuit line i y is an input of g y . Without loss of generality assume that g x and g y are inverting gates. It is assumed that there are n IX- sub-paths, IX 1 , IX 2 , …, and IX n , m IY-sub-paths, IY 1 , IY 2 , …, and IY m , and p YO-sub- paths, YO 1 , YO 2 , …, and YO p . We assume that no path delay fault exists on the FS-testable logical paths that do not pass through the victim line. Throughout this section, the MGDF and the pin-to-pin delay model are assumed. C.1 Crosstalk-induced ∆-delay; crosstalk-induced slow-down; crosstalk- induced speed-up Due to the presence of the capacitive coupling, delay in propagating a rising transition from i y to y is RR nc d yy yy ii gg +∆ , where the first term is the delay if the coupling did not exist (nc: no coupling) and the second term reflects the change in the delay due to the presence of the capacitive coupling (refer to Appendix A, Section A.1.1). A similar formula can be written for the delay in propagating a falling transition. 1 Refer to Section 1.2 for the exact definition of a “crosstalk site”. 187 The change in the delay is referred to as crosstalk-induced ∆-delay. When crosstalk- induced ∆-delay is a positive term it is referred to as crosstalk-induced slow-down or crosstalk-induced delay, and when it is a negative term, it is referred to as crosstalk- induced speed-up (also discussed in Section 1.2). Suppose a falling transition edge in S y , F y β ( β: an integer), is the result of the propagation of a rising transition edge in S i y , R y i α ( α: an integer). If the coupling did not exist, the arrival time of F y β would be R F R nc nc A= A d i y y y y i g β α + . However, in the presence of the coupling, RR F R nc A= A d i y y yy yy ii gg β α ++∆ . Crosstalk-induced ∆-delay, R y y i g ∆ , depends on the shape of the signal implied at x 1 . In particular, if there are φ rising transition edges, 1 R x , 2 R x , …, and R x ϕ , and also ψ falling transition edges, 1 F x , 2 F x , …, and F x ψ in S x , skew values R RF R R nc nc AA A [A d ] i xy x y y y i g ηβ η α −= − + , η = 1, …, and φ, and also skew values R FF F R nc nc AA A [A d ] i xy x y y y i g µβ µ α −= − + , µ = 1, …, and ψ, affect the value of R y y i g ∆ . When S x is a clean rising transition, skew = 11 R F R RR nc nc AA A [A d ] i y xx y y y i g β α −= − + . 1 In Appendix A, Section A.1.1, it was stated that R y y i g ∆ depends on the shape of the signals implied at the inputs of g x . Since all through Appendix C it is assumed that the signal implied at x in the presence of the coupling is the same as that when the coupling does not exist (refer to the definition of “crosstalk site” in Section 1.2), R y y i g ∆ actually depends on the shape of the signal implied at x. 188 In such a situation, the crosstalk-induced ∆-delay, R y y i g ∆ , is a slow-down (also discussed in Section 1.2) and its dependency on skew is represented by the function sd C F (skew) 1 (also discussed in Section 2.2.2). Function sd C F (skew) has a positive value. A similar discussion can be presented for a rising transition edge in S y . Note that in general, functions sd C R () and sd C F () are not the same. Also note that in this dissertation, there are occasions (e.g., when defining delay of a surrogate in Section 2.2.2 and also in what is discussed next) where the values of the functions sd C R (skew) or sd C F (skew) are used with no inference to the actual existence of clean transitions in S x or S y . Theorem C-1: Suppose, under a two-pattern input sequence, rising transition edges 1 R x , 2 R x , …, and R x ϕ exist in S x and falling transition edge F y β ( β: an integer) in S y is the result of the propagation of R y i α ( α: an integer) in S i y through g y . The following inequality holds true. RR R R F Cnc Max (A [A d ]), 1, ..., i x y yy yy ii gg sd η α η ϕ ⎧⎫ ⎪⎪ ∆≤ − + = ⎨⎬ ⎪⎪ ⎩⎭ Proof of the above theorem follows observations similar to the one presented below. Suppose, under a two-pattern input sequence T 1 , S x and S i y are as shown in Figure C-1 (a) and R y i α in S i y propagates through g y and the resulting falling transition edge in S y is F y β . If the capacitive coupling did not exist, the arrival time of this transition edge would be R R nc Ad i y y y i g α + (see S nc y and note that d nc denotes R nc d y y i g in the figure). Due to the presence of the coupling, the arrival time is RR R nc Ad i y yy yy ii gg α ++∆ instead (see S y and note that R y y i g ∆ has been denoted by ∆ in the figure). Now suppose 1 sd: slow-down. 189 that under the two-pattern input sequences T 2 and T 3 , the signals are as shown in Figure C-1 (b) and (c), respectively. Under T 2 , S x is a clean rising transition and the arrival time of the rising transition edge is equal to the arrival time of 1 R x in S x under T 1 . Under T 3 , S x is also a clean rising transition and the arrival time of the rising transition edge is equal to the arrival time of 2 R x in S x under T 1 . In cases (b) and (c), similar to case (a), R y i α in S i y propagates through g y and the resulting falling transition edge in S y is F y β . If the capacitive coupling did not exist, the arrival time of this transition edge would be R R nc Ad i y y y i g α + . Under T 2 , due to the presence of the coupling, the arrival time of F y β , instead of being R R nc Ad i y y y i g α + , is 1 RR RR R F nc C nc Ad (A [A d ]) ii x yy yy yy ii gg sd αα ++ − + . (Note that 1 R R R F Cnc (A [A d ]) i x y y y i g sd α −+ has been denoted by sd 1 in the figure.) Similarly, under T 3 , the arrival time of F y β is 2 RR RR R F nc C nc Ad (A [A d ]) ii x yy yy yy ii gg sd αα ++ − + . (Note that 2 R R R F Cnc (A [A d ]) i x y y y i g sd α −+ has been denoted by sd 2 in the figure). F 1 x (a) (b) (c) S x S y i S y S nc y d nc d nc d nc sd 1 sd 2 R 1 x F 2 x R 2 x R y i α R y i α F y β F y β F y β 1 R A x 2 R A x Arrival time equal to Arrival time equal to R y i α ∆ Figure C-1. Crosstalk-induced ∆-delay under three two-pattern input sequences. Observation: The value of ∆ is less than the maximum of sd 1 and sd 2 . 190 In general ∆ is less than or equal to the maximum of sd 1 , sd 2 , …, and sd φ . In other words, RR R R F Cnc Max (A [A d ]), 1, ..., i x y yy yy ii gg sd η α η ϕ ⎧⎫ ⎪⎪ ∆≤ − + = ⎨⎬ ⎪⎪ ⎩⎭ . Further detail about the proof of Theorem C-1 is beyond the scope of this dissertation. Note that the theorem is also true even when under no two-pattern input sequence a clean rising transition with arrival time equal to R A , {1, ..., } x η η ϕ ∈ can be invoked at x. Similar inequality holds true in conjunction with a rising transition edge in S y . Under a two-pattern input sequence, a transition edge in the signal implied at a circuit output o, say X o γ (X {R, F} ∈ , γ: an integer), is the CTE of one or more logical paths that end at o (Corollary A-1). As mentioned before, such logical paths are called sensitization logical paths for X o γ . If at least one of the sensitization logical paths for X o γ passes through the victim line (i.e., it is a logical IY||YO-path), X o γ is called a crosstalk-affected transition edge. Else, it is called a non-crosstalk-affected transition edge. It must be noted that the delay of a logical IY||YO-path (which is the sum of the delay values along the logical path) is not fixed and depends on crosstalk-induced ∆- delay under the two-pattern input sequence that has been applied to the circuit. If X o γ is a crosstalk-affected transition edge, it is the result of the propagation of a rising or a falling transition edge in S y . Such a transition edge is called the victim-line- ascendant transition edge for X o γ . 191 Theorem C-2: Under a two-pattern input sequence, for crosstalk-affected transition edge X o γ (o: a circuit output, X {R, F} ∈ , γ: an integer) with a sensitization logical path FF IY || YO jk , X A o γ is less than or equal to the maximum delay among the surrogates that belong to the surrogate-set corresponding FF IY || YO jk . Proof: Sub-path IY j goes through g y . Let us refer to other on-IY-sub-path gates along IY j from its input to g y as g 1 , …, g π and refer to the corresponding on-sub-path inputs as l 1 , …, l π , respectively (Figure C-2). Suppose i y is the on-sub-path input of g y . Let us refer to on-YO-sub-path gates along YO k from y to o as g π+1 , …, g ρ (Figure C-2). On-sub- path input of g π+1 is line y. Let us refer to the on-sub-path inputs of g π+2 , …, g ρ as l π+2 , …, l ρ , respectively (Figure C-2). g y x g 1 l 1 i y g π y 1 g π + g ρ l π l ρ o Figure C-2. Logical path IY j F ||YO k F . The victim-line-ascendant transition edge of X o γ is a falling transition edge in S y . This transition edge is the result of the propagation of a rising transition, say R y i α ( α: an integer), in S i y . Arrival time of X o γ is 1 1 1 1 x R x x F X A d ... d d d ... d o y y i l l y l g g g g g ρ π ρ π π γ ρ π + =+ + + + + + , IY j YO k 192 where x v , { 1, ..., , 2, ..., } v ππρ ∈+ , is either ‘R’ or ‘F’. The above equation can be manipulated as 1 1 1 1 x RR x x F X nc A d ... d d d ... d o yy yy ii l l y l g gg g g g ρ π ρ π π γ ρ π + =+ + + +∆ + + + F F R IY YO dd y jy k i g =+∆ + (C-1) If, under the two-pattern input sequence, S x is static, there is no crosstalk-induced ∆- delay. As a result, F F IY X YO Ad d o j k γ =+ . Else if, under the two-pattern input sequence, S x is a clean falling transition, the crosstalk induced ∆-delay is a speed-up and R y y i g ∆ is thus a negative number. As a result, F F IY X YO Ad d o j k γ ≤+ . For both of the above two cases, FF RF IY IY X IX YO F C A d (d d ) d , 1, ..., o jj ik sd i n γ ≤+ − + = X RF F A delay of (IX , IY , YO ), 1, ..., o ij k in γ ⇒≤ = { } X RF F A Max delay of (IX , IY , YO ), 1, ..., o ij k in γ ⇒≤ = Else, there exists at least one rising transition edge in S x . Suppose rising transition edges 1 R x , 2 R x , …, and R x ϕ exist in S x . According to Theorem C-1, RR R R F Cnc Max (A [A d ]), 1, ..., i x y yy yy ii gg sd η α η ϕ ⎧⎫ ⎪⎪ ∆≤ − + = ⎨⎬ ⎪⎪ ⎩⎭ (C-2) R R nc Ad i y y y i g α + is equal to F IY d j . Arrival time of each R , 1, ..., x η η ϕ = is equal to the delay of a rising logical IX-sub-path R IX , where { 1, ..., } n ζ ζ ∈ (refer to Lemma A- 2). Therefore, for an { 1, ..., } η ϕ ∈ , 193 F R R IY RIX RFF Cnc C (A [A d ]) (d d ), where { 1, ..., } i x y y yj i g sd sd n ηζ α ζ −+ = − ∈ . (C-3) From equations (C-2) and (C-3), it can be concluded that F R R IY IX F C Max (d d ), 1, ..., y yj i i g sd i n ⎧⎫ ∆≤ − = ⎨⎬ ⎩⎭ (C-4) From equations (C-1) and (C-4), it can be concluded that FF RF IY IY X IX YO F C A Maxd (d d ) d , 1, ..., o jj ik sd i n γ ⎧⎫ ≤+ − + = ⎨⎬ ⎩⎭ { } X RF F A Max delay of (IX , IY , YO ), 1, ..., o ij k in γ ⇒≤ = Therefore, X A o γ is less than or equal to the maximum delay among the surrogates that belong to the surrogate-set corresponding FF IY || YO jk . ■ The same is also true in conjunction with a crosstalk-affected transition edge X o γ with a sensitization logical path RR (IY || YO ) jk . Corollary C-1: When no surrogate delay fault exists on the surrogates that belong to the surrogate-set corresponding a logical IY||YO-path, under no two-pattern input sequence, the CTE of the logical path can be late (or in other words, under no two-pattern input sequence, delay of the logical IY||YO-path can be greater than t S ). C.2 Proofs for theorems presented in Chapter 2 Theorem 2-1: An RR-test for an FS-testable surrogate is a detecting-test for the surrogate. 194 Proof: Suppose the surrogate is RF F (IX , IY , YO ), ij k S = where { 1, ..., }, in ∈ { 1, ..., } jm ∈ , and { 1, ..., } kp ∈ . Under an RR-test for S, for every on-IX- and on-IY- sub-path gate, the signal implied at each off-sub-path input is the static non-controlling value of the gate; therefore, S x is a clean rising transition and S y is a clean falling transition (S i y is a clean rising transition). Furthermore, R 1 IX R Ad x i = , and 11 1 1 RR FR R R nc C nc AA d (A [A d ]) ii yx yy yy yy ii gg sd =+ + − + . Since 1 R R nc Ad i y y y i g + is equal to F IY d j , FF R 1 IY IY IX F C Ad (d d ) y jj i sd =+ − . Under an RR-test for S, robust requirements are satisfied for all the on-YO-sub-path gates; therefore, according to Theorem B-3, for 1 X o (X {R, F} ∈ ), the first transition edge in the signal implied at the output of YO k , o, FF RF 1 IY IY IX YO X C d(d d)d A o jj ik sd+− + ≤ 1 X dA o S ⇒≤ . A similar conclusion can be made if the surrogate is FR R (IX , IY , YO ) ij k S = . Existence of a surrogate delay fault on S means that S dt S > . In such a situation, under an RR-test for S, the first transition in S o happens after t S and thus S o (t S ) = IV(o) = FV( ) o . Therefore an RR-test for a surrogate is a detecting-test for the surrogate. ■ 195 Theorem 2-2: If no surrogate delay fault exists on the surrogates defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. Proof: When no surrogate delay fault exists on the surrogates, delay of each surrogate RF F (IX , IY , YO ) ij k or FR R (IX , IY , YO ) ij k , where { 1, ..., } in ∈ , { 1, ..., } jm ∈ , and { 1, ..., } kp ∈ is less than t S . Let us focus on a transition edge X o γ (X: ‘R’ or ‘F’, γ: an integer) in the signal implied at a circuit output o, under a two-pattern input sequence. If X o γ is a non- crosstalk-affected transition edge, none of the sensitization logical paths for X o γ pass through the victim line. Suppose logical path P R (or P F ) is such a logical path. X A o γ is equal to R d P (or F d P ). As per our assumption, no path delay fault exists on the logical path, i.e., R d P (or F d P ) < t S ; therefore, X A o γ < t S . If X o γ is crosstalk-affected transition edge, one of the sensitization logical path of X o γ is a logical IY||YO-path. No surrogate delay fault exists on the surrogates that belong to the surrogate-set corresponding such a logical IY||YO-path (because no surrogate delay fault exists on any surrogate in the circuit); therefore, according to Corollary C-1, X o γ cannot be late. Since the above discussion can be made for any transition edge in the signal implied at any circuit output under any two-pattern input sequence, it can be concluded that no transition occurs in the signals implied at circuit outputs after t S and thus the crosstalk site cannot cause any timing error. ■ 196 Theorem 2-3: If no surrogate delay fault exists on the FS-testable surrogates defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. Proof: Consider a circuit in which no surrogate delay fault exists on the FS-testable surrogates. According to Corollary C-1, under any two-pattern input sequence, the CTEs of FS-testable logical IY||YO-paths cannot be late; or in other words, delays of FS-testable logical IY||YO-paths are less than t S . If no surrogate delay fault exists on the FS-untestable surrogates, according to Theorem 2-2, no timing error might occur in the circuit. Suppose a surrogate delay fault exists on at least one of the FS-untestable surrogates. Under a two-pattern input sequence, if a late transition edge exists in the signal implied at a circuit output o, it must be the CTE of one or more FS-untestable logical IY||YO-paths. (According to Corollary A-1, the transition edge is the CTE of a logical path that ends at o. It can not be the CTE of a logical path that does not pass through the victim line because no path delay fault exists on such logical paths. Nor can it be the CTE of an FS-testable logical IY||YO-path.) In such a situation, in conjunction with each FS-untestable logical IY||YO-path that is a sensitization logical path of the transition edge, according to Theorem A-1, there must be an FS-testable logical path whose delay is greater than the delay of the FS-untestable logical IY||YO-path and thus greater than t S . Such FS-testable logical path must be a logical IY||YO-path (because no 197 path delay fault exists on the FS-testable logical paths that do not pass through the victim line). This contradicts the assumption that we made about the circuit. Therefore, under the two-pattern input sequence, no late transition edge might exist in the signal implied at any circuit output. In other words, the signals implied at all the circuit outputs stabilize to their final values before t S . Hence, no timing error occurs at any circuit output. What stated above is true under any two-pattern input sequence. Hence, no timing error occurs in the circuit. ■ Theorem 2-4: If a circuit with an FS-testable crosstalk site passes a test-set that contains an RR-test for each FS-testable surrogate defined in association with crosstalk slow-down targets C(x, y, R) and C(x, y, F), no timing error might occur in the circuit. Proof: According to Theorem 2-1, an RR-test for a surrogate is a detecting-test for the surrogate which means that when the circuit passes such a test, it can be concluded that no surrogate delay fault exist on the surrogate. When the circuit passes a test-set that contains an RR-test for each FS-testable surrogate in the circuit, it can be concluded that no surrogate delay fault exists on the FS-testable surrogates. Therefore, according to Theorem 2-3, no timing error might occur in the circuit. ■ 198 Appendix D: Testing for WRB-induced delay faults Throughout this section, it is assumed that a WRB site 1 with affecting line x and victim line y exists in the circuit for which x and y are not circuit inputs, circuit outputs, fan-out branches and are not in transitive fan-in of each other. x and y are assumed to not be fan-out branches to simplify the discussions and this assumption does not limit the generality of the argument. It is assumed that x and y are driven by the gates g x and g y , respectively. It is assumed that circuit line i y is an input of g y . Without loss of generality assume that g x and g y are inverting gates. It is assumed that there are n IX- sub-paths, IX 1 , IX 2 , …, and IX n , m IY-sub-paths, IY 1 , IY 2 , …, and IY m , and p YO-sub- paths, YO 1 , YO 2 , …, and YO p . We assume that no path delay fault exists on the FS-testable logical paths that do not pass through the victim line. Throughout this section, the MGDF and the pin-to-pin delay model are assumed. D.1 WRB-induced ∆-delay; WRB-induced slow-down; WRB-induced speed- up Due to the presence of the resistive coupling (the WRB), delay in propagating a rising transition from i y to y is RR nc d yy yy ii gg +∆ , where the first term is the delay if the resistive coupling did not exist (nc: no coupling) and the second term reflects the change in the delay due to the presence of the WRB (refer to Appendix A, Section A.1.1). A similar formula can be written for the delay in propagating a falling transition. 1 Refer to Section 1.3 for the exact definition of a “WRB site”. 199 The change in the delay is referred to as WRB-induced ∆-delay. When WRB-induced ∆-delay is a positive term it is referred to as WRB-induced slow-down or WRB-induced delay, and when it is a negative term, it is referred to as WRB-induced speed-up (also discussed in Section 1.3). Suppose a falling transition edge in S y , F y β ( β: an integer), is the result of the propagation of a rising transition edge in S i y , R y i α ( α: an integer). If the WRB did not exist, the arrival time of F y β would be R F R nc nc A= A d i y y y y i g β α + . However, in the presence of the coupling, RR F R nc A= A d i y y yy yy ii gg β α ++∆ . The WRB-induced ∆-delay, R y y i g ∆ , depends on the shape of the signal implied at x 1 . When S x is static logic-1, the WRB-induced ∆-delay is a slow-down and its magnitude is at the maximum possible, denoted by F WRB max-sd (“sd” denotes slow- down). When S x is static logic-0, the WRB-induced ∆-delay is a speed-up and its magnitude is at the maximum possible, denoted by F WRB max-su (“su” denotes speed- up). If S x is not static and there are φ rising transition edges, 1 R x , 2 R x , …, and R x ϕ , and also ψ falling transition edges, 1 F x , 2 F x , …, and F x ψ in S x , skew values R RF R R nc nc AA A [A d ] i xy x y y y i g ηβ η α −= − + , η = 1, …, and φ, and also skew values 1 In Appendix A, Section A.1.1, it was stated that R y y i g ∆ depends on the shape of the signals implied at the inputs of g x . Since all through Appendix D it is assumed that the signal implied at x in the presence of the WRB is the same as that when the WRB does not exist (refer to the definition of “WRB site” in Section 1.3), R y y i g ∆ actually depends on the shape of the signal implied at x. 200 R FF F R nc nc AA A [A d ] i xy x y y y i g µβ µ α −= − + , µ = 1, …, and ψ, affect the value of R y y i g ∆ . When S x is a clean rising transition, skew = 11 R F R RR nc nc AA A [A d ] i y xx y y y i g β α −= − + . In such a situation, the dependency of the WRB-induced ∆-delay on skew is represented by the function F, R WRB (skew) ∆ , where F WRB F, R 0 F, R WRB F, R 0 F WRB max- for a large negative skew, 0 for skew skew , (skew) 0 for skew skew , and max- for a larg sd su >< ∆= <> − e positive skew. ⎧ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎩ (This was partially discussed in Section 1.3 and an illustration was presented in Figure 1-8 (b).) Without loss of generality, we assume that F, R 0 skew 0 = . When S x is a clean falling transition, skew = 11 R F R FF nc nc AA A [A d ] i y xx y y y i g β α −= − + . In such a situation, the dependency of the WRB-induced ∆-delay on skew is represented by the function F, F WRB (skew) ∆ , where F WRB F, F 0 F, F WRB F, F 0 F WRB max- for a large negative skew, 0 for skew skew , (skew) 0 for skew skew , and max- for a larg su sd − << ∆= >> e positive skew. ⎧ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎩ (This was partially discussed in Section 1.3 and an illustration was presented in Figure 1-8 (a).) Without loss of generality, we assume that F, F 0 skew 0 = . The above discussion was presented in conjunction with a falling transition edge in S y . A similar discussion can be presented in conjunction with a rising transition edge in 201 S y . Note that, in a general situation, functions R, R WRB () ∆ , R, F WRB () ∆ , F, R WRB () ∆ , and F, F WRB () ∆ and also values R WRB max-sd , F WRB max-sd , R WRB max-su , and F WRB max-su are not the same. Note that in this dissertation, there are occasions (e.g., when defining delay of a macro-surrogate in Section 3.2.2) where R WRB max-sd and F WRB max-sd are used with no inference to the actual existence of rising or falling transition edges in S y and static logic-0 or static logic-1 at x or y. Furthermore, note that there are occasions (e.g., when defining delay of a surrogate in Section 3.2.3 and also in what is discussed next) where the values of the functions R, R WRB (skew) ∆ , R, F WRB (skew) ∆ , F, R WRB (skew) ∆ , and F, F WRB (skew) ∆ are used with no inference to the actual existence of clean transitions at x or y. Theorem D-1: Suppose, under a two-pattern input sequence, rising transition edges 1 R x , 2 R x , …, and R x ϕ and also falling transition edges 1 F x , 2 F x , …, and F x ψ exist in S x and falling transition edge F y β ( β: an integer) in S y is the result of the propagation of R y i α ( α: an integer) in S i y through g y . The following inequality holds true. R 12 Max(MAX , MAX ) y y i g ∆≤ , where R R R R F, R 1WRB nc F R F, F 2WRB nc MAX Max (A [A d ]), 1, ..., , MAX Max (A [A d ]), 1, ..., . i x y y y i x y y y i i g and g η α µ α ηϕ µψ ⎧⎫ ⎪⎪ =∆ − + = ⎨⎬ ⎪⎪ ⎩⎭ ⎧⎫ ⎪⎪ =∆ − + = ⎨⎬ ⎪⎪ ⎩⎭ Proof of the above theorem follows observations similar to the one presented in conjunction with the proof of Theorem C-1 in association with crosstalk-induced ∆- 202 delay in Appendix C. Further detail about the proof is beyond the scope of this dissertation. Similar inequality holds true in conjunction with a rising transition edge in S y . If at least one of the sensitization logical paths for X o γ , a transition edge in the signal implied at a circuit output o under a two-pattern input sequence (X {R, F} ∈ , γ: an integer), passes through the victim line (in other words, if at least one of the sensitization logical paths is a logical IY||YO-path), X o γ is called a WRB-affected transition edge. Else, it is called a non-WRB-affected transition edge. It must be noted that the delay of a logical IY||YO-path (which is the sum of the delay values along the logical path) is not fixed and depends on the WRB-induced ∆-delay under the two- pattern input sequence that has been applied to the circuit. If X o γ is a WRB-affected transition edge, it is the result of the propagation of a rising or a falling transition edge in S y . Such a transition edge is called the victim-line- ascendant transition edge for X o γ . Theorem D-2: Under a two-pattern input sequence, for WRB-affected transition edge X o γ (o: a circuit output, X {R, F} ∈ , γ: an integer) with a sensitization logical path FF IY || YO jk , – If the two-pattern input sequence implies a static logic-1 at x (case(a)), X A o γ is equal to the delay of the macro-surrogate FF (IY , YO ) jk MS = , – Else (case(b)), X A o γ is less than or equal to the maximum delay among the surrogates that correspond FF (IY , YO ) jk . 203 Proof: Sub-path IY j goes through g y . Let us refer to other on-IY-sub-path gates along IY j from its input to g y as g 1 , …, g π and refer to the corresponding on-sub-path inputs as l 1 , …, l π , respectively (Figure D-1). Suppose i y is the on-sub-path input of g y . Let us refer to on-YO-sub-path gates along YO k from y to o as g π+1 , …, g ρ (Figure D-1). On-sub- path input of g π+1 is line y. Let us refer to the on-sub-path inputs of g π+2 , …, g ρ as l π+2 , …, l ρ , respectively (Figure D-1). g y x g 1 l 1 i y g π y 1 g π + g ρ l π l ρ o Figure D-1. Logical path IY j F ||YO k F . The victim-line-ascendant transition edge of X o γ is a falling transition edge in S y . This transition edge is the result of the propagation of a rising transition, say R y i α ( α: an integer), in S i y . Arrival time of X o γ is 1 1 1 1 x R x x F X A d ... d d d ... d o y y i l l y l g g g g g ρ π ρ π π γ ρ π + =+ + + + + + , where x v , { 1, ..., , 2, ..., } v ππρ ∈+ , is either ‘R’ or ‘F’. The above equation can be manipulated as 1 1 1 1 x RR x x F X nc A d ... d d d ... d o yy yy ii l l y l g gg g g g ρ π ρ π π γ ρ π + =+ + + +∆ + + + F F R IY YO dd y jy k i g =+∆ + (D-1) If, under the two-pattern input sequence, S x is static logic-1, then R F WRB max- y y i g sd ∆= . (D-2) IY j YO k 204 From equations (D-1) and (D-2), F F IY X YO F WRB Ad max- d d o j k MS sd γ =+ + = . Therefore the theorem is true for case (a). Now let us focus on case (b). If, under the two-pattern input sequence, S x is static logic-0, then R F WRB max- y y i g su ∆=− . (D-3) From equations (D-1) and (D-3), F F IY X YO F WRB Ad max- d o j k su γ =− + . (D-4) In the meantime, delay of each surrogate that corresponds FF (IY , YO ) jk is equal to or greater than F F IY YO F WRB dmax- d j k su −+ (refer to Section 3.2.3). As a result, F F IY YO F WRB dmax- d j k su −+ and thus X A o γ is equal to or smaller than the maximum delay among the surrogates that correspond FF (IY , YO ) jk . Now let us focus on the situation where, under the two-pattern input-sequence, S x is not static. Suppose rising transition edges 1 R x , 2 R x , …, and R x ϕ and falling transition edges 1 F x , 2 F x , …, and F x ψ exist in S x . According to Theorem D-1, R 12 Max(MAX , MAX ) y y i g ∆≤ , (D-5) where R R R R F, R 1WRB nc F R F, F 2WRB nc MAX Max (A [A d ]), 1, ..., , and MAX Max (A [A d ]), 1, ..., . i x y y y i x y y y i i g g η α µ α ηϕ µψ ⎧⎫ ⎪⎪ =∆ − + = ⎨⎬ ⎪⎪ ⎩⎭ ⎧⎫ ⎪⎪ =∆ − + = ⎨⎬ ⎪⎪ ⎩⎭ R R nc Ad i y y y i g α + is equal to F IY d. j Arrival time of each R , 1, ..., x η η ϕ = is equal to the delay of a rising logical IX-sub-path R IX , where { 1, ..., } n ζ ζ ∈ (refer to Lemma A- 2). Therefore, for an { 1, ..., } η ϕ ∈ , 205 F R R R R F, R WRB nc IY IX F, R WRB (A [A d ]) (d d ), where { 1, ..., }. i x y y y j i g n η α ζ ζ ∆− + = ∆− ∈ As a result, F R IY IX F, R 1WRB MAX Max (d d ), 1, ..., j i in ⎧⎫ =∆ − = ⎨⎬ ⎩⎭ . (D-6) Furthermore, arrival time of each F , 1, ..., x µ µ ψ = is equal to the delay of a falling logical IX-sub-path F IX , where { 1, ..., } n ξ ξ ∈ . Therefore, for a { 1, ..., } µ ψ ∈ , F F R F R F, F WRB nc IY IX F, F WRB (A [A d ]) (d d ), where { 1, ..., }. i x y y y j i g n µ α ξ ξ ∆− + = ∆− ∈ As a result, F F IY IX F, F 2WRB MAX Max (d d ), 1, ..., j i in ⎧⎫ =∆ − = ⎨⎬ ⎩⎭ . (D-7) From equations (D-1), (D-5), (D-6), and (D-7), it can be concluded that X A o γ is equal to or smaller than the maximum delay among the surrogates that correspond FF (IY , YO ) jk . Therefore, the theorem is also true for case (b). ■ The same is also true in conjunction with a WRB-affected transition edge X o γ with a sensitization logical path RR (IY , YO ) jk . Note that the maximum delay among the surrogates that correspond a macro- surrogate is equal to or less than the delay of the macro-surrogate (refer to Section 3.2.3). Therefore, Corollary D-1: When no macro-surrogate delay fault exists on a macro-surrogate, under no two- pattern input sequence, the CTE of the corresponding logical IY||YO-path can be late 206 (or in other words, under no two-pattern input sequence, delay of the logical IY||YO- path can be greater than t S ). D.2 Proofs for theorems presented in Chapter 3 Theorem 3-1: An R + -test for an FS-testable macro-surrogate is a detecting-test for the macro- surrogate. Proof: Suppose the macro-surrogate is FF (IY , YO ) jk MS = , where { 1, ..., } jm ∈ and { 1, ..., } kp ∈ . Under an R + -test for MS, S x is static logic-1. Furthermore, robust requirements are satisfied for all the on-IY-sub-path gates; therefore, S y is a falling transition (S i y is a rising transition) and according to Theorem B-3, F 1 IY F F WRB dmax- A y j sd +≤ , (D-8) where 1 F y is the first transition edge in S y . Furthermore, under an R + -test for MS, robust requirements are satisfied for all the on-YO-sub-path gates; therefore, according to Theorem B-3, for 1 X o (X {R, F} ∈ ), the first transition edge in the signal implied at the output of YO k , o, F 11 YO FX Ad A yo k +≤ (D-9) From equations (D-8) and (D-9), F F 1 IY YO X F WRB dmax- d A o j k sd ++ ≤ 1 X dA o MS ⇒≤ . A similar conclusion can be made if the macro-surrogate is RR (IY , YO ) jk MS = . 207 Existence of a macro-surrogate delay fault on MS means that S dt MS > . In such a situation, under an R + -test for MS, the first transition in S o happens after t S and thus S o (t S ) = IV(o) = FV( ) o . Therefore an R + -test for a macro-surrogate is a detecting-test for the macro-surrogate. ■ Theorem 3-2: An RR-test for an FS-testable surrogate is a detecting-test for the surrogate. Proof: Suppose the surrogate is RF F (IX , IY , YO ) ij k S = , where { 1, ..., }, in ∈ { 1, ..., } jm ∈ , and { 1, ..., } kp ∈ . Under an RR-test for S, for every on-IX- and on-IY- sub-path gate, the signal implied at each off-sub-path input is the static non-controlling value of the gate; therefore, S x is a clean rising transition and S y is a clean falling transition (S i y is a clean rising transition). Furthermore, R 1 IX R Ad x i = , and 11 1 1 RR FR R R F, R nc WRB nc AA d (A [A d ]) ii yx yy yy yy ii gg =+ +∆ − + . Since 1 R R nc Ad i y y y i g + is equal to F IY d j , FF R 1 IY IY IX F F, R WRB Ad (d d ) y jj i =+∆ − . Under an RR-test for S, robust requirements are satisfied for all the on-YO-sub-path gates; therefore, according to Theorem B-3, for 1 X o (X {R, F} ∈ ), the first transition edge in the signal implied at the output of YO k , o, FF RF 1 IY IY IX YO X F, R WRB d(dd)dA o jj ik +∆ − + ≤ 1 X dA o S ⇒≤ . 208 A similar conclusion can be made if the surrogate is FF F (IX , IY , YO ), ij k RR R (IX , IY , YO ) ij k , or FR R (IX , IY , YO ) ij k . Existence of a surrogate delay fault on S means that S dt S > . In such a situation, under an RR-test for S, the first transition in S o happens after t S and thus S o (t S ) = IV(o) = FV( ) o . Therefore an RR-test for a surrogate is a detecting-test for the surrogate. ■ Theorem 3-3: If no macro-surrogate delay fault exists on the macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. Proof: When no macro-surrogate delay fault exists on the macro-surrogates, delay of each macro-surrogate FF (IY , YO ) jk or RR (IY , YO ), jk where { 1, ..., } jm ∈ and { 1, ..., } kp ∈ is less than t S . Let us focus on a transition edge X o γ (X {R, F} ∈ , γ: an integer) in the signal implied at a circuit output o, under a two-pattern input sequence. If X o γ is a non-WRB- affected transition edge, none of the sensitization logical paths for X o γ go through the victim line. Suppose logical path P R (or P F ) is such a logical path. X A o γ is equal to R d P (or F d P ). No path delay fault exists on the logical path, i.e., R d P (or F d P ) < t S ; therefore, X A o γ < t S . If X o γ is a WRB-affected transition edge, one of the sensitization logical path of X o γ is a logical IY||YO-path. Consider such a logical path. No macro-surrogate delay 209 fault exists on the corresponding macro-surrogate; therefore, according to Corollary D- 1, X o γ cannot be late. Since the above discussion can be made for any transition edge in the signal implied at any circuit output under any two-pattern input sequence, it can be concluded that no transition happens in the signals implied at circuit outputs after t S and thus the WRB site cannot cause any timing error. ■ Theorem 3-4: If no macro-surrogate delay fault exists on the FS-testable macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. Proof: Consider a circuit in which no macro-surrogate delay fault exists on the FS-testable macro-surrogates. According to Corollary D-1, under any two-pattern input sequence, the CTEs of FS-testable logical IY||YO-paths cannot be late; or in other words, delays of FS-testable logical IY||YO-paths are less than t S . If no macro-surrogate delay fault exists on the FS-untestable macro-surrogates, according to Theorem 3-3, no timing error might occur in the circuit. Suppose a macro-surrogate delay fault exists on at least one of the FS-untestable macro-surrogates. Under a two-pattern input sequence, if a late transition edge exists in the signal implied at a circuit output o, it must be the CTE of one or more FS-untestable logical IY||YO-paths. (According to Corollary A-1, the transition edge is the CTE of a 210 logical path that ends at o. It can not be the CTE of logical path that does not pass through the victim line because no path delay fault exists on such logical paths. Nor can it be the CTE of an FS-testable logical IY||YO-path.) In such a situation, in conjunction with each FS-untestable logical IY||YO-path that is a sensitization logical path of the transition edge, according to Theorem A-1, there must be an FS-testable logical path whose delay is greater than the delay of the FS-untestable logical IY||YO-path and thus greater than t S . Such FS-testable logical path must be a logical IY||YO-path (because no path delay fault exists on the FS-testable logical paths that do not pass through the victim line). This contradicts the assumption that we made about the circuit. Therefore, under the two-pattern input sequence, no late transition edge might exist in the signal implied at any circuit output. In other words, the signals implied at all the circuit outputs stabilize to their final values before t S . Hence, no timing error occurs at any circuit output. What stated above is true under any two-pattern input sequence. Hence, no timing error occurs in the circuit. ■ Theorem 3-5: If a circuit with an FS-testable WRB site passes a test-set that contains an R + -test for each FS-testable macro-surrogate defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. Proof: According to Theorem 3-1, an R + -test for a macro-surrogate is a detecting-test for the macro-surrogate which means that when the circuit passes such a test, it can be 211 concluded that no macro-surrogate delay fault exist on the macro-surrogate. When the circuit passes a test-set that contains an R + -test for each FS-testable macro-surrogate in the circuit, it can be concluded that no macro-surrogate delay fault exists on any FS- testable macro-surrogate. Therefore, according to Theorem 3-4, no timing error might occur in the circuit. ■ Theorem 3-6: If no macro-surrogate delay fault exists on the FS-testable LR-testable macro- surrogates and no surrogate delay fault exists on the surrogates corresponding the FS- testable LR-untestable macro-surrogates defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. Proof: Proof uses the following theorem and can be presented similar to the proof of Theorem 3-4. ■ Theorem D-3: When no surrogate delay fault exists on the surrogates corresponding an LR-untestable macro-surrogate, under no two-pattern input sequence, the CTE of the corresponding logical IY||YO path can be late (or in other words, under no two-pattern input sequence, delay of the logical IY||YO-path can be greater than t S ). 212 Proof: Without loss of generality, suppose the macro-surrogate is FF (IY , YO ) jk MS = . Suppose circuit line a is the input of F IY j . Since the macro-surrogate is LR-untestable, under no two-pattern input sequence that invokes a transition that matches a’s logical IY-direction at a and propagates a transition along FF IY || YO jk S x is static logic-1. Therefore, if the CTE of FF IY || YO jk exists in the signal implied at its output under a two-pattern input sequence, it is case (b) in Theorem D-2 and thus the arrival time of the CTE is less than or equal to the maximum delay among the surrogates that correspond MS. Since no surrogate delay fault exists on the surrogates corresponding MS (delay of each corresponding surrogate is less than t S ), under no two-pattern input sequence, the CTE of FF IY || YO jk can be late. ■ Theorem 3-7: If a circuit with an FS-testable WRB site passes a test-set that contains an R + -test for each FS-testable LR-testable macro-surrogate and an RR-test-set for each FS-testable LR-untestable macro-surrogate defined in association with WRB slow-down targets WRB(x, y, R) and WRB(x, y, F), no timing error might occur in the circuit. According to Theorem 3-1, an R + -test for a macro-surrogate is a detecting-test for the macro-surrogate which means that when the circuit passes such a test, it can be concluded that no macro-surrogate delay fault exist on the macro-surrogate. According to Theorem 3-2, an RR-test for a surrogate is a detecting-test for the surrogate which means that when the circuit passes such a test, it can be concluded that no surrogate 213 delay fault exist on the surrogate. When the circuit passes a test-set that contains an R + - test for each FS-testable LR-testable macro-surrogate and an RR-test-set for each FS- testable LR-untestable macro-surrogate, it can be concluded that no macro-surrogate delay fault exists on any FS-testable LR-testable macro-surrogate and no surrogate delay fault exists on any surrogate corresponding any FS-testable LR-untestable macro- surrogate. Therefore, according to Theorem 3-6, no timing error might occur in the circuit. ■ 214 Appendix E: Supplementary material related to Chapter 4 E.1 Calculating upper-bound and lower-bound for R F IY IX R C d ( ,) d ( ,) j i sd αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ As discussed in Section 4.2, FF F IX IX IX d ( , ) . r . f ii i αβ α β =+ , and RR R IY IY IY d ( , ) . r . f jj j αβ α β =+ ; Therefore, RR R FF F IY IY IY IX IX IX d ( , ) d ( , ) . (r r ) . (f f ) jj j ii i αβ αβ α β −= − + − . Let us refer to the maximum and minimum values of R F IY IX d(,)d (,) j i αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ as max-skew and min-skew, respectively. In order to calculate the upper-bound and lower- bound for R F IY IX R C d ( ,) d ( ,) j i sd αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ , different cases must be considered. Case (a): R F IY IX rr 0 j i −≥ , R F IY IX ff 0 j i − ≥ In this situation, max-skew occurs at max max (, ) α β and min-skew occurs at min min (, ) α β . Note that both max-skew ≥ 0 and min-skew ≥ 0. In this case, R C () sd is monotonically falling in the range [min-skew, max-skew] and hence () R F IY IXRR CC d(,)d (,) min-skew j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and () R F IY IXRR CC d(,)d (,) max-skew j i Lsd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ . In other words, 215 R F R F RR FF IY IX R C IY IX R C min min min min IY IY IX IX R Cmin min d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) , j i j i jj ii Usd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ and R F R F RR FF IY IX R C IY IX R C max max max max IY IY IX IX R Cmax max d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) . j i j i jj ii Lsd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ Case (b): R F IY IX rr 0 j i −≥ , R F IY IX ff 0 j i − < In this situation, max-skew occurs at max min (, ) α β and min-skew occurs at min max (, ) α β . Three cases can be imagined. (b-I) min-skew ≥ 0 In this case, R C () sd is monotonically falling in the range [min-skew, max-skew], and hence () R F IY IXRR CC d(,)d (,) min-skew j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and () R F IY IXRR CC d(,)d (,) max-skew j i Lsd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ . In other words, 216 R F R F RR FF IY IX R C IY IX R C min max min max IY IY IX IX R Cmin max d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) , an j i j i jj ii Usd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ d R F R F RR FF IY IX R C IY IX R C max min max min IY IY IX IX R Cmax min d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) . j i j i jj ii Lsd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ (b-II) min-skew < 0, max-skew ≥ 0 In this case, R C () sd is monotonically rising in the range [min-skew, 0) and monotonically falling in the range [0, max-skew] and hence R F IY IXRR CC d(,)d (,) max- j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and () ( ) () R F IY IX R C RR CC d(,)d (,) Min min-skew , max-skew . j i Lsd sd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ In other words, R F R F R F IY IX R C IY IX R C min max min max IY IX R C max min max min R C d(,)d (,) d ( ,)d ( ,), Min d ( ,)d ( ,) Min j i j i j i Lsd sd sd sd αβ αβ αβ αβ αβ αβ α ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ⎛⎞ − ⎜⎟ ⎜⎟ ⎝⎠ ⎜⎟ = ⎜⎟ ⎛⎞ ⎜⎟ − ⎜⎟ ⎜⎟ ⎝⎠ ⎝⎠ RR FF RR FF IY IY IX IX min max IY IY IX IX R Cmax min . (r r ) . (f f ) , . . (r r ) . (f f ) jj ii jj ii sd β αβ ⎛⎞ ⎛⎞ −+ − ⎜⎟ ⎜⎟ ⎝⎠ ⎜⎟ ⎜⎟ ⎛⎞ ⎜⎟ −+ − ⎜⎟ ⎜⎟ ⎝⎠ ⎝⎠ 217 (b-III) max-skew < 0 In this case, R C () sd is monotonically rising in the range [min-skew, max-skew] and hence () R F IY IXRR CC d(,)d (,) max-skew j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and () R F IY IXRR CC d(,)d (,) min-skew j i Lsd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ . In other words, R F R F RR FF IY IX R C IY IX R C max min max min IY IY IX IX R Cmax min d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) , and j i j i jj ii Usd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ R F R F RR FF IY IX R C IY IX R C min max min max IY IY IX IX R Cmin max d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) . j i j i jj ii Lsd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ Case (c): R F IY IX rr 0 j i −< , R F IY IX ff 0 j i − ≥ In this situation, max-skew occurs at min max (, ) α β and min-skew occurs at max min (, ) α β . Three cases can be imagined. (c-I) min-skew ≥ 0 In this case, R C () sd is monotonically falling in the range [min-skew, max-skew] and hence () R F IY IXRR CC d(,)d (,) min-skew j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and 218 () R F IY IXRR CC d(,)d (,) max-skew j i Lsd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ . In other words, R F R F RR FF IY IX R C IY IX R C max min max min IY IY IX IX R Cmax min d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) , and j i j i jj ii Usd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ R F R F RR FF IY IX R C IY IX R C min max min max IY IY IX IX R Cmin max d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) . j i j i jj ii Lsd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ (c-II) min-skew < 0, max-skew ≥ 0 In this case, R C () sd is monotonically rising in the range [min-skew, 0) and monotonically falling in the range [0, max-skew] and hence R F IY IXRR CC d(,)d (,) max- j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and () ( ) () R F IY IX R C RR CC d(,)d (,) Min min-skew , max-skew . j i Lsd sd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ In other words, 219 R F R F R F IY IX R C IY IX R C min max min max IY IX R C max min max min R Cmin d(,)d (,) d ( ,)d ( ,), Min d ( ,)d ( ,) Min j i j i j i Lsd sd sd sd αβ αβ αβ αβ αβ αβ α ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ⎛⎞ − ⎜⎟ ⎜⎟ ⎝⎠ ⎜⎟ = ⎜⎟ ⎛⎞ ⎜⎟ − ⎜⎟ ⎜⎟ ⎝⎠ ⎝⎠ RR FF RR FF IY IY IX IX max IY IY IX IX R Cmax min . (r r ) . (f f ) , . . (r r ) . (f f ) jj ii jj ii sd β αβ ⎛⎞ ⎛⎞ −+ − ⎜⎟ ⎜⎟ ⎝⎠ ⎜⎟ ⎜⎟ ⎛⎞ ⎜⎟ −+ − ⎜⎟ ⎜⎟ ⎝⎠ ⎝⎠ (c-III) max-skew < 0 In this case, R C () sd is monotonically rising in the range [min-skew, max-skew] and hence () R F IY IXRR CC d(,)d (,) max-skew j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and () R F IY IXRR CC d(,)d (,) min-skew j i Lsd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ . In other words, R F R F RR FF IY IX R C IY IX R Cminmax minmax IY IY IX IX R Cmin max d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) , and j i j i jj ii Usd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ R F R F RR FF IY IX R C IY IX R C max min max min IY IY IX IX R Cmax min d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) . j i j i jj ii Lsd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ 220 Case (d): R F IY IX rr 0 j i −< , R F IY IX ff 0 j i − < In this situation, max-skew occurs at min min (, ) α β and min-skew occurs at max max (, ) α β . Note that both max-skew < 0 and min-skew < 0. In this case, R C () sd is monotonically rising in the range [min-skew, max-skew] and hence () R F IY IXRR CC d(,)d (,) max-skew j i Usd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ , and () R F IY IXRR CC d(,)d (,) min-skew j i Lsd sd αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ . In other words, R F R F RR FF IY IX R C IY IX R C min min min min IY IY IX IX R Cmin min d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) , an j i j i jj ii Usd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ d R F R F RR FF IY IX R C IY IX R C max max max max IY IY IX IX R Cmax max d(,)d (,) d ( , ) d ( , ) . (r r ) . (f f ) . j i j i jj ii Lsd sd sd αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ −= ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ −= ⎜⎟ ⎝⎠ ⎛⎞ −+ − ⎜⎟ ⎝⎠ E.2 Calculating upper-bound and lower-bound for R F IY IX R, F WRB min d(,)d (,), j i b r αβ αβ ⎛⎞ ∆− ⎜⎟ ⎝⎠ As discussed in Section 4.2, FF F IX IX IX d ( , ) . r . f ii i αβ α β =+ , and RR R IY IY IY d ( , ) . r . f jj j αβ α β =+ ; Therefore, 221 RR R FF F IY IY IY IX IX IX d ( , ) d ( , ) . (r r ) . (f f ) jj j ii i αβ αβ α β −= − + − . Let us refer to the maximum and minimum values of R F IY IX d(,)d (,) j i αβαβ ⎛⎞ − ⎜⎟ ⎝⎠ as max-skew and min-skew, respectively. In order to calculate the upper-bound and lower- bound for R F IY IX R, F WRB min d(,)d (,), j i b r αβ αβ ⎛⎞ ∆− ⎜⎟ ⎝⎠ , different cases must be considered. Note that () R, F WRB min skew, b r ∆ is a monotonically falling function of skew. Therefore, () R F IY IX R, F WRB min R, F WRB min d(,)d (,), min-skew, , and j i b b Ur r αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ∆ () R F IY IX R, F WRB min R, F WRB min d ( ,) d ( ,), max-skew, . j i b b Lr r αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ∆ Case (a): R F IY IX rr 0 j i −≥ , R F IY IX ff 0 j i − ≥ In this situation, max-skew occurs at max max (, ) α β and min-skew occurs at min min (, ) α β . Therefore, R F R F RR FF IY IX R, F WRB min IY IX R, F WRB min min min min min IY IY IX IX R, F WRB min min min d(,)d (,), d ( , ) d ( , ), . (r r ) . (f f ), , and j i j i jj ii b b b Ur r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ R F R F RR FF IY IX R, F WRB min IY IX R, F WRB max max max max min IY IY IX IX R, F WRB max max min d ( ,) d ( ,), d ( , ) d ( , ), . (r r ) . (f f ), . j i j i jj ii b b b Lr r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ Case (b): R F IY IX rr 0 j i −≥ , R F IY IX ff 0 j i − < 222 In this situation, max-skew occurs at max min (, ) α β and min-skew occurs at min max (, ) α β . Therefore, R F R F RR FF IY IX R, F WRB min IY IX R, F WRB max min max min min IY IY IX IX R, F WRB max min min d(,)d (,), d ( , ) d ( , ), . (r r ) . (f f ), , and j i j i jj ii b b b Ur r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ R F R F RR FF IY IX R, F WRB min IY IX R, F WRB min max min max min IY IY IX IX R, F WRB min max min d(,)d (,), d ( , ) d ( , ), . (r r ) . (f f ), . j i j i jj ii b b b Lr r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ Case (c): R F IY IX rr 0 j i −< , R F IY IX ff 0 j i − ≥ In this situation, max-skew occurs at min max (, ) α β and min-skew occurs at max min (, ) α β . Therefore, R F R F RR FF IY IX R, F WRB min IY IX R, F WRB min max min max min IY IY IX IX R, F WRB min max min d(,)d (,), d ( , ) d ( , ), . (r r ) . (f f ), , and j i j i jj ii b b b Ur r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ R F R F RR FF IY IX R, F WRB min IY IX R, F WRB max min max min min IY IY IX IX R, F WRB max min min d(,)d (,), d ( , ) d ( , ), . (r r ) . (f f ), . j i j i jj ii b b b Lr r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ Case (d): R F IY IX rr 0 j i −< , R F IY IX ff 0 j i − < 223 In this situation, max-skew occurs at min min (, ) α β and min-skew occurs at max max (, ) α β . Therefore, R F R F RR FF IY IX R, F WRB min IY IX R, F WRB min min min min min IY IY IX IX R, F WRB min min min d(,)d (,), d ( , ) d ( , ), . (r r ) . (f f ), , and j i j i jj ii b b b Ur r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ R F R F RR FF IY IX R, F WRB min IY IX R, F WRB max max max max min IY IY IX IX R, F WRB max max min d ( ,) d ( ,), d ( , ) d ( , ), . (r r ) . (f f ), . j i j i jj ii b b b Lr r r αβ αβ αβ αβ αβ ⎡⎤ ⎛⎞ ∆− = ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ⎛⎞ ∆− = ⎜⎟ ⎝⎠ ⎛⎞ ∆−+ − ⎜⎟ ⎝⎠ E.3 Situations where a surrogate-gate pair is delay-superior to another surrogate-gate pair Let us focus on surrogates FR R 1 (IX , IY , YO ) ij k S = and FR R 2 (IX , IY , YO ) ab c S = and gate g, where g belongs to 1 S G as well as to 2 S G . It can be easily shown that in each of the following cases, (S 2 , g) is delay-superior to (S 1 , g). ) g is an on-IY-sub-path gate for S 2 (refer to Figure E-1) IX a YO c IY b x y g Figure E-1. g is an on-IY-sub-path gate for S 2 . ¾ g is an on-IY-sub-path gate for S 1 (refer to Figure E-2) 224 g IX a YO c IY b YO k IX i IY j x y Figure E-2. g is an on-IY-sub-path gate for S 2 . g is an on-IY-sub-path gate for S 1 . • If FR IX IY nn dd 0 ab −< & R F IY IX nn dd 0 j i −< & R FFR IY IX IX IY nn n n dd d d j iab −< − & R RR R IY YO IY YO nn n n dd d d j kb c +≤ + , • Or if FR IX IY nn dd 0 ab −< & R F IY IX nn dd 0 j i −< & R FFR IY IX IX IY nn n n dd d d j iab −≥ − & RR FR RF R R IY IY IX YO R nCn n n IY IX IY YO R nCn n n d(d d)d d (d d ) d , jj ik ba b c sd sd +− + ≤ +− + • Or if FR IX IY nn dd 0 ab −< & R F IY IX nn dd 0 j i −≥ & R RR R IY YO IY YO R nCn n n dmax- d d d j kb c sd ++ ≤ + , • Or if FR IX IY nn dd 0 ab −≥ & R F IY IX nn dd 0 j i −≥ & R FFR IY IX IX IY nn n n dd d d j iab −= − & R RR R IY YO IY YO nn n n dd d d j kb c +≤ + , 225 • Or if FR IX IY nn dd 0 ab −≥ & R F IY IX nn dd 0 j i −≥ & R FFR IY IX IX IY nn n n dd d d j iab −≠− & R RR R IY YO IY YO R nCn n n dmax- d d d j kb c sd ++ ≤ + , • Or if FR IX IY nn dd 0 ab −≥ & R F IY IX nn dd 0 j i −< & RR FR RF R R IY IY IX YO R nCn n n IY IX IY YO R nCn n n d(d d)d d (d d ) d & jj ik ba b c sd sd +− + ≤ +− + R RR R IY YO IY YO nn n n dd d d j kb c +≤ + . ¾ g is an on-IX-sub-path gate as well as an on-IY-sub-path gate for S 1 (refer to Figure E-3) g IX a YO c IY b YO k IX i IY j x y Figure E-3. g is an on-IY-sub-path gate for S 2 . g is an on-IX-sub-path gate as well as an on-IY-sub- path gate for S 1 . • If RR FRRR IY IY IX YO IY YO R nCn n n n n d(d d)d d d jj ikbc sd+− + ≤ + . ) g is an on-IX-sub-path gate as well as an on-IY-sub-path gate for S 2 (refer to Figure E-4) YO c IY b IX a x y g Figure E-4. g is an on-IX-sub-path gate as well as an on-IY-sub-path gate for S 2 . 226 ¾ g is an on-IY-sub-path gate for S 1 (refer to Figure E-5) IX i YO c IY b YO k IX a IY j x y g Figure E-5. g is an on-IX-sub-path gate as well as an on-IY-sub-path gate for S 2 . g is an on-IY-sub- path gate for S 1 . • If R F IY IX nn dd 0 j i −≥ & R R RF R R IY YO R nCn IY IX IY YO R nCn n n dmax- d d (d d ) d , j k ba b c sd sd ++ ≤ +− + • Or if R F IY IX nn dd 0 j i −< & RR FR RF R R IY IY IX YO R nCn n n IY IX IY YO R nCn n n d(d d)d d (d d ) d . jj ik ba b c sd sd +− + ≤ +− + ¾ g is an on-IX-sub-path gate as well as an on-IY-sub-path gate for S 1 (refer to Figure E-6) g IX i YO c IY b YO k IX a IY j x y Figure E-6. g is an on-IX-sub-path gate as well as an on-IY-sub-path gate for S 2 . g is an on-IX-sub- path gate as well as an on-IY-sub-path gate for S 1 . RR FR RF R R IY IY IX YO R nCn n n IY IX IY YO R nCn n n If d (d d ) d d (d d ) d . jj ik ba b c sd sd •+ − + ≤ +− + ) g is an on-YO-sub-path gate for S 2 (refer to Figure E-7) 227 IX i YO k IY j x y g Figure E-7. g is an on-YO-sub-path gate for S 2 . ¾ g is an on-YO-sub-path gate for S 1 (refer to Figure E-8) IX i IY j YO k IX a YO c IY b x y g Figure E-8. g is an on-YO-sub-path gate for S 2 . g is an on-YO-sub-path gate for S 1 . RR FR RF R R IY IY IX YO R nCn n n IY IX IY YO R nCn n n If d (d d ) d d (d d ) d . jj ik ba b c sd sd •+ − + ≤ +− + ) g is an on-IX-sub-path gate for S 2 (refer to Figure E-9) g IX a YO c IY b x y Figure E-9. g is an on-IX-sub-path gate for S 2 . ¾ g is an on-YO-sub-path gate for S 1 (refer to Figure E-10) g IX i IY j YO k IX a YO c IY b x y Figure E-10. g is an on-IX-sub-path gate for S 2 . g is an on-YO-sub-path gate for S 1 . • If R FFR IY IX IX IY nn n n dd d d j iab −= − & R RR R IY YO IY YO nn n n dd d d j kb c +≤ + .
Abstract (if available)
Abstract
Process technology advancements are increasing coupling capacitance values and the resulting crosstalk-induced delay. As a result, noise and timing margins are decreasing and circuits' susceptibility to defects is increasing. The population of defects is also changing and the influence of fluctuations of process parameters during manufacturing is becoming more and more important due to process technology advancements.
Linked assets
University of Southern California Dissertations and Theses
Conceptually similar
PDF
Test generation for capacitance and inductance induced noise on interconnects in VLSI logic
PDF
Timing-oriented approach for delay testing
PDF
Modeling and testing crosstalk faults in arbitrary inter-core interconnects that include tri-state and bi-directional nets
PDF
Accurate and efficient testing of resistive bridging faults
PDF
Timing and power analysis of CMOS logic cells under noisy inputs
PDF
Error-rate testing to improve yield for error tolerant applications
PDF
High level design for yield via redundancy in low yield environments
PDF
Redundancy driven design of logic circuits for yield/area maximization in emerging technologies
PDF
Timing analysis of coupled interconnect and CMOS logic cells in the presence of crosstalk noise
PDF
Structural delay testing of latch-based high-speed circuits with time borrowing
PDF
Static timing analysis of GasP
PDF
Architecture and application of an autonomous robotic software engineering technology testbed (SETT)
PDF
Error tolerance approach for similarity search problems
PDF
Systematic performance and robustness testing of transport protocols with congestion control
PDF
Stochastic dynamic power and thermal management techniques for multicore systems
PDF
Self-assembly for discreet, fault-tolerant, and scalable computation on internet-sized distributed networks
PDF
Microring resonator based filters and modulators: optical coupling control and applications to digital communications
PDF
A variation aware resilient framework for post-silicon delay validation of high performance circuits
PDF
Trustworthiness of integrated circuits: a new testing framework for hardware Trojans
PDF
Defect-tolerance framework for general purpose processors
Asset Metadata
Creator
Irajpour, Shahdad
(author)
Core Title
Testing for crosstalk- and bridge-induced delay faults
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
12/03/2007
Defense Date
10/19/2007
Publisher
University of Southern California
(original),
University of Southern California. Libraries
(digital)
Tag
Bridge,crosstalk,delay fault,OAI-PMH Harvest,TEST
Language
English
Advisor
Gupta, Sandeep K. (
committee chair
), Breuer, Melvin A. (
committee member
), Medvidovic, Nenad (
committee member
)
Creator Email
irajpour@usc.edu
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-m963
Unique identifier
UC1294958
Identifier
etd-Irajpour-20071203 (filename),usctheses-m40 (legacy collection record id),usctheses-c127-488497 (legacy record id),usctheses-m963 (legacy record id)
Legacy Identifier
etd-Irajpour-20071203.pdf
Dmrecord
488497
Document Type
Dissertation
Rights
Irajpour, Shahdad
Type
texts
Source
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Repository Name
Libraries, University of Southern California
Repository Location
Los Angeles, California
Repository Email
cisadmin@lib.usc.edu
Tags
crosstalk
delay fault