Close
About
FAQ
Home
Collections
Login
USC Login
Register
0
Selected
Invert selection
Deselect all
Deselect all
Click here to refresh results
Click here to refresh results
USC
/
Digital Library
/
University of Southern California Dissertations and Theses
/
The selective area growth and coalescence of indium phosphide nanostripe arrays on silicon through MOCVD for NIR monolithic integration
(USC Thesis Other)
The selective area growth and coalescence of indium phosphide nanostripe arrays on silicon through MOCVD for NIR monolithic integration
PDF
Download
Share
Open document
Flip pages
Contact Us
Contact Us
Copy asset link
Request this asset
Transcript (if available)
Content
The Selective Area Growth and
Coalescence of Indium Phosphide
Nanostripe Arrays on Silicon through
MOCVD for NIR Monolithic Integration
By Mitchell Dreiske
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment for the Degree of
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING – ELECTROPHYSICS)
May 2020
ii
ACKNOWLEDGEMENTS
I’d like to thank my advisor, Prof. Daniel Dapkus for guiding me through my work at USC. His
pioneering work with MOCVD was an immeasurable help with my research. His stories from his days at
UIUC, Bell Labs, and Rockwell were both entertaining and enlightening, and moved me in the right
direction in my most difficult times. His standards for how to carry out experiments and how to report
results, beyond what is usually expected, very well-prepared me for work past grad school and I can’t
thank him enough.
I’d also like to thank Chun-yung Chi and Yoshitake Nakajima for training me with the MOCVD system
and much of the processing and characterization equipment in the cleanroom and beyond. With their help,
I learned the deepest intricacies of the InP reactor and the quirks unique to it needed to be taken into
account for growth.
For my qualification exam and PhD defense committees, I’d like to thank Profs Rehan Kapadia, Wei Wu,
Jayakanth Ravichandran, and Han Wang.
I thank Prof Rehan Kapadia and his students, notably Debarghya Sarkar, Jun Tao, and Hyun Uk Chae for
helping me with device work for my InP structures and for helping me with safety considerations during
growth, good luck with your future work with the MOCVD system!
For nanoimprint lithography and high-aspect ratio etching, I’d like to thank Prof Wei Wu, Zerui Liu,
Deming Meng, and Tse-Hsien Ou. Without their exceptionally hard work optimizing the pattern geometry
and etch chemistry for our samples, I’d never achieve the growth quality I did on such large-area patterns.
For my AFM measurements, I thank Prof Mark Thompson, Taylor Hodgkins, Rasha Hamze for helping
train me on their Agilent Picovision system, with which I demonstrated films comparable to or even
superior to some of the smoothest coalesced-nanostripe films without seed layers or CMP ever reported.
For photoluminescence, I’d like to thank Ashkan Seyedi and Yoshi Nakajima again for training me on our
own custom system, and Debarghya Sarkar, Prof Steve Cronin, and Bo Wang for helping me with the
iii
microPL system. Prof Cronin also helped provide valuable input with preparations for EBIC
measurements, which allowed us to demonstrate our coalescence and aspect ratio trapping strategy may
have reduced defect densities in films by nearly two orders of magnitude.
For XRD, immensely vital for the calibration of my lattice-matched InGaAs films grown on InP, I’d like
to thank Prof Jayakanth Ravichandran, Yang Liu, Tom Orvis, and Tom Orvis for helping measure the
XRD of my samples.
For the deposition of low-stress LPCVD silicon nitride, I thank Prof Eun Sok Kim and Yonkui Tang,
without whom I’d again wouldn’t be able to grow some of the smoothest coalesced InP films ever
reported.
For their role in helping me acquire my vital cross-sectional TEM and defect densities of coalesced films
grown on Si, I thank Matt Mecklenberg of USC’s CNI and Noah Bodzin of UCLA. Without your help, I
wouldn’t have been able to show the usefulness of aspect ratio trapping in reducing the defect density in
InP films grown on Si.
I’d also like to thank Donghai Zhu and Alfonso Jimenez for maintaining the numerous equipment in the
cleanroom and throughout the campus vital for our research.
Finally, I’d like to thank my parents, Peter and Tina Dreiske for always being there for me in my hardest
times and for giving me additional advice for my research and life outside the lab.
iv
TABLE OF CONTENTS
Acknowledgements ii
List of Figures vii
Abstract xi
Chapter 1: Introduction 1
1.1: Aspect Ratio Trapping and Coalescence 3
1.2: Outline of Dissertation 8
Chapter 2: Theory of Metalorganic Chemical Vapor Deposition and Selective Area Growth 9
2.1: Overview 9
2.2: Thin Film Growth Physics 10
2.2.1: Thermodynamics of Growth: Compositional Effects 10
2.2.2: Reaction Kinetics 13
2.2.3: Surface Physics 15
2.2.3.1: Adsorption, Migration, and Desorption 15
2.2.3.2: Surface Energy Conditions and Growth Modes 16
2.3: Selective Area Growth 19
2.3.1: Requirements for Selectivity 19
2.3.2: Growth Rate Enhancement 20
2.3.3: Effect of Opening Geometry on Growth Morphology 22
2.3.4: Effect of Growth Conditions on Morphology 28
2.3.5: Enhancement Effect on Composition 31
Chapter 3: Aspect Ratio Trapping and Coalescence 33
3.1: Challenges to Monolithic Integration of Compound Semiconductor Structures on Si 33
3.1.1: Heteroepitaxy and Defect Generation 33
3.1.2: Early Methods of Defect Filtering 37
3.1.3: Proposed Method for Large-area Monolithic Integration with Defect Filtering 38
3.2: Aspect Ratio Trapping 43
3.3: Coalescence and its Applications 47
3.3.1: Coalescence and Defect Generation 47
3.3.2: Current Work with Coalescence 49
Chapter 4: Sample Preparation 51
4.1: Substrate Selection and Antiphase Boundary Elimination 51
4.2: Choice of Pattern 53
4.2.1: EBL-defined Nanostripe Openings 54
v
4.2.2: NIL-defined Nanostripe Openings 57
4.3: Wet Cleaning 67
Chapter 5: Selective Area Growth of Indium Phosphide Nanostripes on Silicon Employing Thin
Masking Layers 69
5.1: Low Temperature Nucleation Layer Formation 71
5.1.1: Temperature Dependence of Nucleation Layer Density 71
5.1.2: Nucleation Layer Damage at Elevated Temperatures 74
5.2: Investigations of Nanostripe Growth Conditions and Mask Geometry through EBL 76
5.2.1: Temperature Variation of Nanostripe Growth on Si 76
5.2.2: Increasing the Thickness of the Nucleation Layer 78
5.2.3: The Role of Opening Depth on Nanostripe Morphology 80
5.2.4: Variation of Mask Pitch 83
5.3: NIL Nanostripe Growth: Large Area SAG 86
5.4: Coalescence and Regrowth 87
5.4.1: Coalescence with EBL Nanostripes 87
5.4.2: Coalescence with NIL Nanostripes 89
5.4.3: Regrowth and Twin-like Crystallite Defect Formation and Suppression 94
5.5: Initial Conclusions for SAG and Coalescence 96
Chapter 6: Optimization and Characterization of Coalesced Nanostripe Morphology Compared to
Thin Films Grown on Si 98
6.1: Nucleation Optimization 98
6.1.1: Pre-nucleation Si Surface Preparation with Hydride Anneals 99
6.1.2: Protection of Nucleation Layer from Thermal Damage with Intermediate-
Temperature Layer Growth 101
6.1.3: Use of GaAs as a Pre-InP Nucleation Seed Layer 103
6.1.4: Optimization of RIE System Cleanliness 106
6.2: Optimization of Aspect Ratio Trapping and Coalescence 110
6.2.1: Nanostripe Orientation 110
6.2.2: Effect of Opening Pitch and Depth on Defect Formation 118
6.3: Use of a Buffer Layer under the Nanostripe Mask 122
6.3.1: EBL with Buffer Layer under Mask 122
6.3.2: Coalescence with a Buffer Layer under the Mask 124
6.3.3: NIL with Buffer Layer under Mask 131
6.4: Determination of the Nature of Surface Features through EBIC 133
vi
6.4.1: EBIC Overview 134
6.4.2: EBIC Results 134
6.5: Conclusions for Coalescence 137
Chapter 7: Fabrication and Characterization of PN Junctions on Coalesced InP Film 140
7.1: PN Junction Design 140
7.1.1: Design of Mesas 140
7.1.2: Design of Contacts 141
7.2: Selectively Grown PN Mesas 143
7.2.1: Morphology of SAG Mesas and Overgrown Edge 143
7.2.2: IV Characteristics of SAG Mesas 145
7.3: Etched Mesas 149
7.3.1: Etch Chemistries 149
7.3.2: IV Characteristics of Etched Mesas 150
7.4: Conclusions for PN Junctions 154
Chapter 8: Future Work 156
8.1: Project Summary 156
8.2: Proposed Work: Growth 158
8.2.1: Reduction of Defect Densities 158
8.2.2: Growth on Exact (100) Si 158
8.3: Proposed Work: PIN Photodiode Fabrication 159
8.3.1: PIN Photodiode Overview 159
8.3.2: Normal-incidence PIN Photodiode Mesas 160
8.3.3: Silicon Photonic Integration 161
List of References 165
vii
TABLE OF FIGURES
Chapter 1:
Figure 1: Schematic of aspect ratio trapping (ART) 3
Figure 2: Schematic of vapor phase diffusion and surface migration during SAG, SEM of SAG
microstripes 4
Figure 3: Schematic of coalescence 5
Figure 4: Schematic of evanescence coupling to a photodiode with ART and coalescence 6
Figure 5: Schematic of butt coupling to a photodiode 7
Chapter 2:
Figure 1: SEM showing the formation of In droplets from too low a V/III ratio 11
Figure 2: 100x OM showing the formation of VLS nanowires from too low a V/III ratio 14
Figure 3: Schematic of the various processes occurring during nucleation 15
Figure 4: Schematic and energy conditions determining the geometry of nuclei 17
Figure 5: Different growth modes possible 18
Figure 6: SEM of microstripes 19
Figure 7: Dependence of growth rate enhancement on mask width and material, schematic of
SAG mechanisms 21
Figure 8: Cross-sectional SEM of [1-10] and [110]-oriented microstripes 24
Figure 9: Schematic of the disappearance of the (100) surface in for [110]-oriented stripes 25
Figure 10: Schematic of the orientational dependence of lateral epitaxial overgrowth 26
Figure 11: Orientational dependence of stripe morphology 27
Figure 12: Schematic of the origin of differing growth rates on [1-10] and [110] step edges 31
Figure 13: Dependence of the composition of InGaAs on growth rate enhancement 32
Chapter 3:
Figure 1: Schematic of a dislocation loop and the difference between edge and screw dislocations 34
Figure 2: Schematic of the formation of a stacking fault on (111) planes 35
Figure 3: Schematics of how defects that penetrate a junction affect device performance 36
Figure 4: Different approaches for selective growth and coalescence of nanostripes to form a
“quasisubstrate” for device integration 40
Figure 5: Additional mask geometries considered in this project 42
Figure 6: Cross-sectional schematic of aspect ratio trapping 43
viii
Figure 7: An unclosed defect loop terminating at the mask sidewalls 44
Figure 8: Process of defect formation from coalescence 47
Chapter 4:
Figure 1: Schematic of a monoatomically-stepped surface, with different bond arrangements
(Type A and Type B) on each step 51
Figure 2: Monoatomically-stepped Si surface after III-V growth 52
Figure 3: Typical EBL pattern used for this project 54
Figure 4: Top-down SEM of underexposed and overexposed/etch-damaged patterns 56
Figure 5: Process to define chromium etch mask for dry-etching 58
Figure 6: Cross-sectional SEM of an ICP-etched thermal oxide mask, with an undercut into the Si
to ensure the oxide was removed within the opening 59
Figure 7: Representative NIL masks patterned by RIE 60
Figure 8: Schematic of the possible mechanism behind the worsening nucleation density 62
Figure 9: Parallel view of a stripe opening, showing a schematic of the possible effect of
contaminants on nucleation density 63
Figure 10: 60-degree angled openings filled in by some contaminant 64
Figure 11: Adapted patterning process if an InP buffer layer is present under the dielectric SAG
mask 66
Chapter 5:
Figure 1: SEM comparison of InP selective growth on InP and Si, without nucleation layer 72
Figure 2: Temperature dependence of nucleation on Si within microstripe openings 73
Figure 3: Comparison under SEM of growth in microstripe openings on Si with and without
nucleation 74
Figure 4: SEM closeup of one of the stripes in Figure 3.b 74
Figure 5: Variation in stripe morphology with growth temperature and orientation 76
Figure 6: Result of increasing nucleation time for stripe morphology 79
Figure 7: Effect of increasing opening depth from 20 to 60 nm 80
Figure 8: Effect of increasing opening depth from 60 to 200 nm 81
Figure 9: Dependence of stripe growth morphology in 200 nm-deep openings on temperature 82
Figure 10: Top-down SEM of stripes grown at 660 °C out of 100 nm-wide openings 200 nm deep
with a 1 µm and 250 nm pitch 84
Figure 11: SEM of nanostripes grown for 200 s at 610 °C with differing pitches 85
ix
Figure 12: Top-down SEM of InP grown in NIL stripe openings, showing the improvement in
growth continuity with increasing nucleation time. 86
Figure 13: Top down SEM showing further improvement in stripe continuity by maintaining
TMIn flow during the temperature ramp between the 400 °C nucleation and 610 °C
stripe growth. 87
Figure 14: SEM of coalescence as a function of temperature, pitch, and orientation for stripes
grown at different temperatures 88
Figure 15: SEM micrographs of two coalesced NIL nanostripe films 90
Figure 16: Top-down SEM and OM of coalesced films with increasing thickness 91
Figure 17: AFM of films in Figure 16 92
Figure 18: Overview of crystallite defects 95
Chapter 6:
Figure 1: Post-hydrogen bake hydride anneal conditions 99
Figure 2: Effect of different hydride anneal conditions on stripe growth continuity 100
Figure 3: AFM of three coalesced films with different initial stripe growth temperatures 102
Figure 4: SEM of films nanostripes grown at different temperatures 103
Figure 5: Effect of introducing a thin GaAs layer prior to InP nucleation 104
Figure 6: Coalesced film quality with and without GaAs seed layer 105
Figure 7: Cross sectional SEM of NIL openings with changing chamber conditions 107
Figure 8: Effect of increasing initial stripe growth time on coalesced film quality 109
Figure 9: Too low a stripe growth rate leads to thermal damage of the nucleation layer 110
Figure 10: AFM of the coalesced films from Figure 8 111
Figure 11: Cross-sectional TEM of two 60°-off-[1-10]-oriented coalesced films 112
Figure 12: Cross-sectional TEM of a coalesced film of [1-10]-oriented stripes 114
Figure 13: Cross-sectional TEM of an InP buffer layer under a SAG mask 115
Figure 14: Surface defects in optimal sample from Figure 6 116
Figure 15: Surface defects in films from Figure 8 117
Figure 16: Surface defects in a [1-10]-oriented coalesced film with no GaAs layer 118
Figure 17: SEM and TEM of a 390 nm-pitch coalesced film 119
Figure 18: SEM and TEM of a thin-mask (150 nm) 121
Figure 19: Improvement of stripe morphology with a buffer layer under the mask 122
x
Figure 20: Nanostripe morphology change with temperature, with buffer layer under mask 123
Figure 21: Dependence of coalescence morphology with array orientation for a 1 µm pitch 125
Figure 22: Cross-sectional TEM for EBL sample with buffer layer under mask, 250 nm pitch 126
Figure 23: Additional TEM and SEM of sample from Figure 22 127
Figure 24: Cross-sectional TEM for EBL sample with buffer layer under mask, 1 µm pitch 129
Figure 25: Additional TEM and SEM of sample from Figure 25 130
Figure 26: 100x optical micrograph of failed NIL-with-buffer layer coalesced film 132
Figure 27: Cross-sectional TEM of sample from Figure 26 133
Figure 28: SEM of [1-10]-oriented coalesced film 135
Figure 29: EBIC of same area as Figure 28, showing surface streaks as defects 136
Figure 30: Top-down SEM of buffer layer grown directly on Si 137
Chapter 7:
Figure 1: Schematics of the two approaches used for PN mesa design: SAG and etching 140
Figure 2: Schematic of the contact design for the mesas 142
Figure 3: Top-down SEM of overgrown edge of SAG mesa 144
Figure 4: Schematic of overgrown edge morphology 145
Figure 5: Schematic of trap-assisted generation and recombination 146
Figure 6: IV characteristics of SAG mesas grown on an InP substrate, InP buffer layer, and
coalesced InP film 147
Figure 7: IV characteristics of etched mesas formed on an InP substrate and a coalesced film 151
Figure 8: Comparison of buffer layer and coalesced film, showing the lack of and presence of
streak defects on them, respectively 153
Chapter 8:
Figure 1: Potential butt-coupled photodiode formed on coalesced film of nanostripes 161
Figure 2: Potential evanescently-coupled photodiode formed on coalesced film 164
xi
ABSTRACT
A dense array of InP nanostripes selectively grown on silicon is coalesced through lateral overgrowth into
a continuous film. This film would serve as a quasi-substrate suitable for the fabrication of an InGaAs
PIN photodiode. High aspect-ratio openings in the mask help filter defects originating from the InP-Si
interface, shielding the coalesced film on top from the effects of the interface below. The quality of this
film is highly dependent on the original stripe morphology, itself dependent on not just growth conditions,
but also: how effective the defect filtering is, the quality of the initial nucleation on Si, and if the growing
material can transition from Volmer-Weber growth to step-flow before emerging from the mask. Unlike
the several-micron-thick buffer layers employed for monolithic integration, the thinner mask and
coalesced film could possibly allow a photodiode fabricated from it to be close enough to an SOI
waveguide for evanescent coupling, not to mention possess superior defect reduction. This epitaxial
approach also avoids the cost and size-availability issues of the III-V wafers needed for efficient bonding
to increasingly large silicon substrates. Through this technique, films with an RMS roughness comparable
to bulk films grown on Si are achieved, with defect densities nearly two orders of magnitude lower.
Strong reverse bias leakage currents of PN diodes grown on these coalesced films show more work is
needed to suppress additional defect generation through the coalescence process.
1
Chapter 1: Introduction
Optoelectronic devices are an important component of today’s technology, forming the backbone of
telecommunications and efficient lighting. While silicon remains the dominant material for electronic
devices, such as CMOS technology, optoelectronic devices, outside of Si solar cells or Ge photodiodes,
are typically constructed from compound semiconductors. With these materials, low-noise, high-
bandwidth devices can be integrated on-chip through Si waveguide optical interconnects [1,2,3]. One
photodiode integrated on Si had a reported bandwidth greater than 140 GHz [2].
However, the III-V materials used for these devices are generally not lattice-matched to silicon, and
efficient monolithic integration of these devices into existing silicon-based environments is difficult due
to the high defect generation at the III-V-Si interface. For InP and related alloys used for NIR
communications (1.3 and 1.55 µm), the lattice mismatch with Si is 8%, and defect densities as high as
10
9
cm
-2
have been reported in bulk InP films grown on Si [4]. For photodetectors, as an example, a high
defect density in the active region of the device would greatly increase the magnitude of the reverse bias
dark current (making low-light detection more difficult) and reduce the responsivity [5]. For LEDs, the
internal quantum efficiency would suffer from increased non-radiative recombination.
For successful monolithic integration, these defects must be prevented from reaching the device layers.
Although wafer bonding (which isn’t monolithic but ignores this issue entirely by growing the device first
on a III-V substrate), has been used successfully to form high-performance III-V-on-Si optoelectronic
devices coupled to Si waveguides, there remains a significant issue with the expense and availability of
larger compound-semiconductor wafers needed to wafer bond efficiently on large silicon wafers [6,7].
Direct growth allows for a much more efficient use of space on the Si substrate, and costly handle wafers
used for the bonding process would not be needed.
In this project, a direct growth technique that filters defects, aspect ratio trapping, is applied to InP
MOCVD on Si to suppress defect propagation into device layers without the need for a thick buffer layer
or SLS structure. InP is grown within parallel stripe openings in a patterned dielectric mask on Si, with
2
the height of the openings greater than the width to block defect propagation out of them. After emerging
from the openings, the InP stripe structures are allowed to overgrow the dielectric mask and merge into a
continuous film, a process termed “coalescence”. Previous attempts at coalescence of InP, to improve the
quality of the coalesced film, have either sacrificed the efficacy of defect filtering by removing the mask
[8,9] or the closeness of the coalesced film to the Si substrate by using a polished InP buffer layer
between the Si and mask [4,10,11]. The goal of this project would be to show that InP coalescence and
successful aspect ratio trapping can be achieved without these handicaps.
Different dielectric mask geometries and their effect on aspect ratio trapping and coalescence are tested,
with the coalesced film morphology and effectiveness of defect filtering characterized through SEM,
AFM, and TEM compared to direct thin film growth on Si. Various InP growth conditions are tested to
optimize coalescence and suppress unwanted additional defect formation from the process.
As a measure of both the material quality and usefulness of the coalesced films for an optoelectronic
device platform, the IV characteristics of PN junction mesas grown on coalesced films as well as on InP
substrates and InP films grown directly on Si with no patterning, are compared.
Without aspect ratio trapping, to suppress defect propagation at all, several micron-thick buffer layers or
strain layer superlattices (SLSs) are generally needed below the device layers. These force defects to
annihilate with each other or engineer the strain to bend defects away from the surface. Defect filtering is
not perfect, however, and devices constructed with these platforms have shown poor performance
compared to wafer bonded devices [7,12,13]. Chemical mechanical polishing (CMP) may be needed to
planarize the buffer layer/SLS surface prior to device growth, which may damage existing structures
present on the sample [10,11,14]. Additionally, too thick a layer separating the silicon substrate from the
device layer would greatly hinder vertical integration with silicon photonics [3]. Through aspect ratio
trapping and coalescence, with device layers possibly within 1 micron or less of the Si surface, vertical
coupling to Si photonic structures in a similar manner so far only achieved through wafer bonding may be
possible [3,7].
3
1.1: Aspect Ratio Trapping and Coalescence
Through “Aspect Ratio Trapping” (ART), selective area growth in high-aspect-ratio mask openings leads
to suppression of defect propagation, shown in Figure 1 [15]. With increasing aspect ratio, the typically
(111)-lying defects that originate from the Si-epitaxial material interface are blocked from propagating
into the upper layers of the grown material by the mask.
Figure 1: Schematic of aspect ratio trapping (ART). (a) if the aspect ratio of the selective opening is too low, defects, the vast
majority of which lie on (111) planes, will not be effectively trapped. (b) a high enough aspect ratio will block the line of sight of
defects generated at the interface. An aspect ratio of at least 1.43 would be needed to block all defects, as the (111) plane is at a
54.7° angle off the (100) surface.
In general, selective area growth (SAG), heteroepitaxial or otherwise, requires careful control of growth
conditions and geometry to ensure proper growth morphology [16]. Growth at low pressures is generally
required to suppress gas-phase reactions that would lead to significant mask deposition. The temperature
and V/III ratio, both of which control surface migration between planes on the growing material, greatly
affects the final morphology of the structure, as well as the degree of mask overgrowth [17]. The
selectivity itself leads a concentration gradient in the vapor phase between the mask and opening,
enhancing the growth rate in the openings. This may alter doping concentration and alloy composition
due to differences in species mobilities, such as for InGaAs. As the concentration gradient is dependent
4
on the mask geometry, compositions can be tailored through control of the enhancement. A schematic of
the mechanism behind selective growth is shown in Figure 2.a [18].
Figure 2: (a) Basic schematic of the vapor phase diffusion and surface migration responsible for the morphological changes of
selectively-grown structures, strongly impacted by growth conditions and pattern geometry. From [18]. (b) An example of a
selectively grown pair of InP microstripes.
If the selective structures are allowed to overgrow the mask (often referred to as lateral epitaxial
overgrowth or LEO) and merge with neighboring structures, a much larger area is available for device
integration than with the structures alone. This process is termed “coalescence” in this dissertation and
elsewhere in literature, and a schematic of a typical cross-section post-coalescence is shown in Figure 3.
Nanostripes—long, trapezoidal mesas with angled {111} sidewalls (an example of such is shown in
Figure 2.b, though on a much larger scale—these would more aptly be called “microstripes”)—are a
commonly-studied structure for this application. For this project they have been chosen due to their
relatively simple shape and single axis of coalescence. Other structures, such as nanopillars (with the
vertical direction as the long direction), would overgrow the mask in multiple directions and many
different coalescence fronts would have to be taken into account. In general, the degree of overgrowth and
nature of coalescence is highly dependent on the morphology of the initial stripes, which is in turn
affected by both the stripe orientation and the growth conditions. Julian et al suggest 60°-off-[1-10] as the
ideal stripe orientation for coalescence [4,19].
(a) (b)
5
Figure 3: A schematic of a cross-section of a coalesced array of InP nanostripes.
Our group has investigated GaAs stripe growth and coalescence without the use of a buffer layer, though
without the use of aspect ratio trapping [20]. J. Z. Li et. al. merged their selectively-grown GaAs
nanostripes, though cross-sectional SEM revealed a rather rough surface [15,21].
For InP, other groups have investigated stripe coalescence on silicon, but with the use of a polished InP
seed layer under the aspect ratio-trapping mask. The Lourdudoss group has studied InP coalescence
extensively and has demonstrated it on a large-scale using nanoimprint lithography [10,11] Although their
process also involves HVPE rather than MOCVD, coalesced films have been reported with RMS
roughnesses as low as 15 nm.
An unfortunate drawback with the use of such buffer layers is that although the defective InP-Si interface
is separated from the coalesced film layer, vertical coupling with any Si photonic structures on the
substrate would also become more challenging.
A typical Si photonic waveguide is roughly 220x500 nm in cross-section and fabricated from a silicon-
on-insulator (SOI) layer, achieved through wafer bonding, leaving a several micron-thick buried oxide
layer in between the waveguide and the Si substrate [3,22,23]. The BOX layer must be thick for good
confinement in the waveguide. With aspect ratio trapping and coalescence, it is possible a “rib waveguide”
structure could be embedded within the dielectric mask to couple to the absorbing InGaAs layer on
6
coalesced InP above it, as shown in the schematic in Figure 4. If a buffer layer, however, were to be used
in between the ART mask and the Si surface, the thickness of the buffer layer would be added to the
distance between the waveguide and the active InGaAs layer. The further a waveguide is from an active
layer it is meant to couple with the less overlap there will be between the field in the two regions and the
coupling will be weaker [3]. Z. Wang et. al. suggest placing the InP buffer layer between the BOX layer
and Si substrate and growing the InP within openings in the BOX layer to address this problem, but even
with CMP of the buffer layer, the SOI fabrication process may become far more difficult [1]. Highly
smooth surfaces are required for direct wafer bonding of the BOX and SOI layers to be successful without
the formation of hydrogen bubbles in between the handle wafer and main wafer [24].
Figure 4: Schematic of a monolithic, evanescently-coupled rib waveguide and pin InP/InGaAs/InP photodiode (waveguide
vertically displaced from the active layer it couples to) combined with aspect ratio trapping and coalescence [3].The InP would
be grown on the SOI layer and be coalesced, with the waveguide within one of the mask sidewalls. An aspect ratio HO/WO
(height/width of opening) greater than at least 1 would be required for effective defect filtering, and the width of the mask must
be greater than the width of the rib waveguide. The waveguide portion of the SOI will be around 500 nm wide, with the height
optimized for best confinement and coupling to the InGaAs layer. The closer the active i-InGaAs layer is to the waveguide, the
stronger the coupling. This approach has been up until now limited to wafer bonding, with the coalesced i-InP and ART mask
replaced by a transparent bonding material such as BCB [2,7].
Coupled light in absorber
Light confined in
waveguide
7
Figure 5: Butt-coupled waveguide and pin photodiode. This has been used in the past to monolithically integrate photodiodes on
Si, but with poorer device performance than wafer-bonded evanescently-coupled devices [7]. Growth on thick buffer layers, not
on coalesced films, was used then. A thin wall of oxide would separate the waveguide and device structure and protect the SOI
waveguide during growth [22,23].The BOX is again several microns thick, while the waveguide is only 200 nm thick, so there is a
strong constraint to how thick the buffer layer be if the i-InGaAs is to be aligned to the waveguide properly.
A waveguide could instead be made in-plane to the III-V active layers on top of the coalesced film such
that the waveguide feeds directly into the active layer, as shown in Figure 5. This “butt-coupling”
approach has been achieved for direct growth without aspect ratio trapping or coalescence on Si for III-V
pin photodiodes, though with poorer device characteristics than wafer-bonded photodiodes due to a lack
of defect filtering [7,12,13,22]. Another drawback of this approach are the significant patterning
challenges that may make aspect ratio trapping difficult to employ with this coupling method. The Si
surface for growth of any buffer layers or the formation of ART masks would be far below the waveguide
due to the BOX layer separating the waveguide typically being several microns thick [23]. Contact
lithography techniques that could make the ART openings, such as nanoimprint lithography, may have
issues producing the pattern with this large height change on the sample surface [10,11]. Additionally,
since for single-mode waveguides, the geometry is small (200x500 nm cross-section), the waveguide
must be carefully aligned to the active layer of the III-V region or else coupling will be poor [2,22].
Light
8
Few groups have reported on InP selective nanostripe growth in conjunction with coalescence without the
use of a buffer layer. Both Q Li et al [8] and Megalini et al [9] demonstrated InP coalescence on patterned
silicon, initially using an SiO
2
mask for ART with the silicon recessed underneath. However, in both
instances the mask was then removed, and the InP stripes were allowed to both overgrow the exposed
silicon and coalesce. No defects in the final coalesced film were attributed to the initial stripes, but the
overgrowth and coalescence process on mismatched silicon generated many defects.
The goal of this project would be to demonstrate coalescence of nanostripes through high-aspect ratio
openings can be achieved without the use of the buffer layer or CMP at any stage and that film
morphology and defect densities are superior to that of thin film buffer layers directly grown on Si.
1.2: Outline of Dissertation
In this dissertation, the selective area growth and coalescence of InP nanostripes on Si through MOCVD
for 1.55 µm optoelectronic integration will be discussed. Chapter 2 will briefly cover the theory of
MOCVD, and give an in-depth discussion of selective area growth. Chapter 3 will explore aspect ratio
trapping and coalescence. Previous work with InP heteroepitaxy on Si will be briefly discussed, and mask
geometries for ART and coalescence are proposed. Chapter 4 will cover our approach to sample
preparation and the unique challenges that arise during such. Chapter 5 will discuss in great detail our
work with the selective area growth and coalescence of InP on Si, with multiple growth conditions and
pattern geometries varied and the morphological changes to stripe and coalesced film morphology
compared. Chapter 6 will explore the optimization of coalescence morphology and defect densities in
comparison direct thin film growth on Si. Chapter 7 will cover the use of these coalesced films for PN
junctions, comparing the device characteristics to those integrated homoepitaxially on InP wafer pieces
and InP buffer layers grown on Si. Finally, Chapter 8 will summarize the work presented in this
dissertation and explore future avenues for this approach at monolithic integration.
9
Chapter 2: Theory of Metalorganic Chemical Vapor Deposition and
Selective Area Growth
2.1: Overview
In this project, metalorganic chemical vapor deposition (MOCVD) was used to selectively grow arrays of
parallel nanostripes, which are subsequently coalesced to form a macroscopic InP surface for potential
optoelectronic device integration.
In MOCVD of compound semiconductors, one or more precursors consist of organic groups bonded to a
metal atom (such as trimethylindium) thermally decompose and combine with the product of another
source, typically a non-metal hydride precursor such as phosphine. The use of these metalorganic
precursors allows for stoichiometric material deposition by exploiting their product’s often much lower
vapor pressure compared to both the reactant and product of the nonmetal source, as long as the more-
volatile source is in excess [25].
MOCVD also allows for specialized deposition technique known as selective area growth (SAG). In SAG,
material is preferentially deposited in an opening in a dielectric mask layer where a semiconductor
surface is exposed. Rather than being etched, complex nanostructures such as dense high-aspect ratio
vertical nanowire arrays or compositionally-varying alloy semiconductor microstripes can be formed on a
single sample [18,26]. An important factor is that the metalorganic precursor is more volatile than its
product, so with careful control of growth conditions, both sources will preferentially react on the
exposed semiconductor surface and preferentially desorb off the dielectric mask.
In contrast, the physical deposition of elemental sources used in molecular beam epitaxy (MBE) does not
have this added reaction component and deposition is not selective due to the poor desorption of the low
vapor pressure element [16]. Metalorganic molecular beam epitaxy (MOMBE) uses metalorganic
precursors within an MBE system, allowing selective growth, but MOCVD remains the dominant method
for SAG.
10
2.2: Thin Film Growth Physics
2.2.1: Thermodynamics of Growth: Compositional Effects
Metalorganic chemical vapor deposition is a complex growth technique, where the morphology,
composition, and uniformity of film or structure can be altered by numerous variables. For instance, the
temperature of the substrate directly impacts the growth rate of the material growing on top of it. For
MOCVD, growth occurs in three general temperature regimes: low, mid, and high [25,27]. At lower
temperatures (generally around or below 400 °C for InP grown using TMIn), the metalorganic precursors
do not decompose as efficiently, and the growth rate increases with temperature. When the temperature is
high enough, around 500–700 °C, enough so that the metalorganic precursor is completely decomposed
on the semiconductor surface, the growth rate becomes independent of temperature and relies solely on
mass transport—that is, the partial pressure of the source for a given reactor pressure and carrier flow. At
too high a temperature, however (700 °C or so for InP), enough thermal energy is present in the growing
material to promote easy desorption of adatoms, and the growth rate begins to decrease as the temperature
increases.
Even for the mass transport-limited case, the partial pressures of the precursors impact growth beyond
simply controlling growth rate. The ratio of the partial pressures of the V and III sources is an important
consideration. Because the V element usually has a higher vapor pressure than the III element, it will
often desorb more easily [27]. Furthermore, the actual concentration of the V and III sources at the
surface of the substrate will be different than that in the gas phase, and at too low a V/III ratio, the lower
vapor-pressure III element may precipitate, as shown in Figure 1 [25]. As such, maintaining an
overpressure of the V-source is vital for MOCVD. Furthermore, because the V-source is in excess, this
leads the growth rate to be determined by the partial pressure of the III-source alone, the limiting reactant,
and the III-source being depleted at the surface from its total decomposition.
11
Figure 1: Formation of In droplets (white droplets in SEM) from the emptying of the TBP source bottle during a growth run. Too
low a V/III ratio allowed the lower-vapor pressure In to precipitate before P could bond to the individual In atoms. The intended
experiment was to form a selectively-grown InP microstripe structure on an InP substrate at 650 °C.
The composition of an alloy grown by MOCVD is also strongly impacted by growth conditions. The
compositions of cation-mixed alloys, such as InGaAs, are generally easy to control. Assuming complete
decomposition of the precursor, the III-source will be depleted at the surface (likely at standard growth
temperatures), and thus the input ratio of the two metalorganic species, say TMIn and TMGa will be the
same as that of the adatoms, In and Ga [25]. Slight variations to this 1:1 correspondence between vapor
phase and solid composition can exist from strain, but in general, this trend holds. At higher temperatures,
in the desorption/thermodynamic regime, the different vapor pressures of the III elements start to become
important and nonlinear incorporation effects may result [25]. This is especially true for InGaN or AlGaN,
which must be grown at relatively high temperatures due to the stability of ammonia.
For mixing on the anion sublattice, however, nonlinear incorporation exists even at standard growth
temperatures. Due to differences in precursor deposition a given growth temperature (as the hydride will
likely not be fully decomposed, unlike the metalorganic source), incorporation of one element may be
12
much less preferable than another. For instance, since phosphine is a far more stable molecule than arsine,
to achieve an equal concentration of As and P in the alloy, a larger amount of phosphine than arsine
would need to be used. As the temperature in the reactor is increased and the phosphine decomposes more
effectively, the amount of phosphine needed would decrease. Meanwhile, if metalorganic V precursors
were used, compositional control would become easier, due to the much easier decomposition of the
source [25].
Quaternary compounds are significantly more complicated than ternaries. Not only does the difference in
the degree of pyrolysis for the hydride sources come into play, but changing the ratio of metallorganic III
precursors will also affect the composition nonlinearly. Although the ratio of III elements is still linearly
dependent on that of ratio of the metallorganic precursors, for InGaAsP, for instance, more As will be
incorporated the more Ga-rich the input is [33]. Lattice matching to InP or GaAs becomes more difficult,
as a result. Furthermore, even the V/III ratio will affect incorporation of the V elements, especially for
lattice-matching. For InGaAsP compositions lattice matched to InP, as the V/III ratio is increased, the
stronger the preference for As incorporation at low phosphine input [28]. With the nonlinear change in
input needed for specific lattice-matched compositions, achieving a desired band-gap can be more
difficult than anticipated.
Finally, nonlinear effects complicate dopant incorporation. First, if the dopant supplied by a hydride
source, the degree of pyrolysis must be taken into account, such as silane or disilane for n-type Si doping
in InP [25]. If the dopant element has a much higher vapor pressure than the element it is meant to
replace, then the incorporation may be actually inversely proportional to temperature, as is the case for
DEZn or DMZn for InP or GaAs [25]. A “distribution coefficient” exists for dopants. There will not be a
1:1 correspondence between dopant source input and composition, for multiple reasons, including that the
dopant atom must replace another with often a very different size or bond strength [29]. Furthermore,
solid solubility limits exist for dopants, and for certain materials, such as InP, it is easier to achieve higher
doping levels for one doping type (n-type at 10
19
) over another (p-type up to mid-10
18
) [29]. Without ion-
13
implantation or depositing a different material on top of the layer, it is more difficult to form a low-
contact resistance Ohmic contact on p-InP than on n-InP as a result [30,31] Finally, some dopants are
“amphoteric” (giving either p- or n-type doping) which must be taken into account when choosing which
dopants to use for a device structure.
2.2.2: Reaction Kinetics
The incorporation of elements in a material is ultimately most strongly impacted by the degree of
decomposition of the precursor. Two main mechanisms of precursor decomposition exist: homogeneous
and heterogeneous reactions. In homogeneous reactions, the precursor molecule pyrolyzes by itself, while
for heterogeneous reactions, the precursor will decompose with the aid of a surface [25].
Taking the reaction of the precursors by themselves, before adding the effect of a surface, must be
considered first. Organometallic precursors, such as TMIn, decompose easily at low temperatures, down
to below 300 °C, due to the weak bonds to the source atom and the organic groups attached to it [25].
Meanwhile hydrides such as AsH
3
and especially PH
3
are more stable, only partly decomposing even at
standard mass-transport limited growth temperatures. Organometallic V-precursors, such as TBAs or TBP
exist, which decompose more readily at lower temperatures as well as ease compositional control
challenges for alloys, but tend to be more expensive [25,32].
The choice of carrier gas plays an important role for this decomposition as well. An inert reactor ambient
will not alter the standard decomposition reaction, but hydrogen will react with the metallorganic
precursor, attacking the organic groups [25]. For TMIn and other methyl-group terminated sources, this
means the formation of methane, instead of the ethane that is formed in a helium ambient [25]. The
removal of these byproducts is an important consideration, as Stringfellow mentions that InP grown via
MOCVD tends to be n-type due to C-incorporation below a 650 °C growth temperature [25]. Conversely,
InGaAs will tend to be p-type from C-incorporation.
14
For heterogeneous reactions, the presence of a surface can weaken the bonds of the precursor and enhance
their decomposition. The nature of the surface will affect how well the precursor will decompose. For
instance, the presence of a GaAs or InP surface for AsH
3
or PH
3
pyrolysis, respectively, greatly improves
the decomposition rate at a given temperature over decomposition on the quartz liner of the reactor [25].
This is because the III and V atoms will form strong chemical bonds with the semiconductor surface,
rather than be weakly bonded to the dielectric. These heterogeneous reactions are vital for low-
temperature growth of InP, allowing nucleation on Si as low as 400 °C. Even with the presence of an InP
surface, less than 10% of the injected PH
3
decomposes, requiring very high input V/III ratios to
compensate–over 1000. If the V/III ratio is too low, not enough phosphorus will be available to prevent In
precipitation and vapor liquid solid (VLS) growth, as shown in Figure 2.
400 °C Nucleation of InP on Si in microstripe openings, importance of V/III ratio
(a) V/III 1786 (b) V/III 397
Figure 2: 100x OM showing degradation in heteroepitaxial growth quality through the reduction of the V/III ratio. (a) InP
nucleation at 400 °C on Si in 10-µm-wide openings in a dielectric mask, V/III ratio 1786. (b) In-precipitation leading to vapor
liquid solid (VLS) nanowire growth by reducing the V/III ratio from increasing the growth rate by a factor of 4.5. Material has
been deposited on the mask as well.
Since the rate of homogeneous, gas-phase reactions increase with temperature, ensuring only the substrate
is heated is vital to suppress them—gas phase reactions would make selective growth difficult due to the
deposition of atomic species on the growth mask [16]. The reactor pressure should be decreased as well to
increase the diffusion length and increase the flow velocity in the chamber, though this has the added
complication of reducing hydride decomposition on the surface due to reducing their time in the “hot zone”
15
on the substrate, being swept away into the exhaust more readily. As the substrate temperature is
increased, more of the surrounding gas will be heated through radiation and convection, and
homogeneous reactions become more likely.
2.2.3: Surface Physics
2.2.3.1: Adsorption, Migration, and Desorption
After the precursors have decomposed into adatoms, the physics of the surface become important. The
adatom may bond with the surface, migrate, or desorb, as shown in Figure 3. The overpressure of the
hydride source, the substrate temperature, and the chemistry of the bonds that form on the surface vs
desorption products all must be taken into account.
Figure 3: Processes that may occur during initial growth. Adatoms arrive on the surface and bond to sites, migrate to a more
preferable site (such as a cluster or at a step edge) or desorb. From [33].
A typical model used to describe adsorption is the Langmuir model [25,34]. Here, the surface is described
as being composed of multiple sites on which a precursor can arrive, react, and leave behind an adatom.
Whether or not the precursor will react depends on if the III or V element is more stable as the precursor
in the vapor phase or bonded to the surface, and this will be influenced by the temperature of the
precursor, as discussed previously [27]. Adatoms may also migrate into and out of these sites, or desorb
off of them, either alone or in clusters.
16
The surface coverage of the sites described by the Langmuir model at low temperatures, where desorption
is minimal, is directly proportional to the input partial pressure, in other words the arrival rate of the
precursor [25,34]. Meanwhile, at higher temperatures (the aforementioned desorption regime), surface
coverage decreases with temperature as the desorption rate increases with temperature. Along with
desorption, adatoms will also migrate, especially if a more preferable site can be found to lower the
surface energy of the configuration, such as a site on a step edge with more available bonds or a growing
cluster [27]. Adatoms may also migrate in response to strain or the presence of defects or contaminants,
which can lead to non-planar growth [33]. Migration is also reliant on thermal energy, increasing with the
rate and length of migration increasing with temperature [25,27].
Desorption follows the general form
, where [A] is the concentration of the
desorbing species on the surface, n is order of desorption (n=1 single atom, with a larger value for
clusters), is attempt frequency,
is heat of desorption (usually the same as adsorption of the same
species) [27]. The V-atoms often desorb as dimers (n=2). For instance, phosphorus will desorb even more
easily than arsenic, as P-P bonds are stronger than As-As bonds. This is especially true for heteroepitaxial
growth of phosphides and arsenides on Si. Although the P-Si bond is stronger than As-Si (296 kJ/mol vs
328 kJ/mol), the P-P bond is even stronger at 489 kJ/mol (160 kJ/mol larger than P-Si) vs As-As’s
382 kJ/mol (only 76 kJ/mol higher than As-Si) [35,36]. This leads to a greater surface coverage of As on
Si compared to P. One surprising result of this is the difficulty of GaP growth in smooth layers with an
abrupt interface on Si [37,38]. Despite being near-lattice-matched with it, without an initial coverage of
As atoms to improve the adsorption and suppress the desorption of P, the GaP will grow somewhat in a
three dimensional mode and will diffuse into the Si [38].
2.2.3.2: Surface Energy Conditions and Growth Modes
Especially for heteroepitaxy, where misfit and thermal strain will impact the initial growth of a layer on
the substate, additional factors must be considered for growth. The interplay between surface
energy/tension of the growth surface (
), that of the growing nuclei (
), and the energy of the interface
17
between them
) determines the shape the nuclei/deposit will take (deposit contact angle ), and
ultimately what “growth mode” the film will grow in [33].
The general expression relating these is
[33]. The contact angle of the deposit, and
thus whether growth occurs in a 2D or 3D mode, will be determined by the interplay of the three energies.
This is demonstrated in Figure 4 below.
Figure 4: Energy conditions (bottom) for whether the growing cluster/nucleus (top schematic) will form in a 3D mode (nonzero
contact angle) or a 2D mode (zero contact angle).
is the surface tension of the substrate,
is the surface tension of the
deposit, and
is the interfacial tension between the deposit and substrate. The interplay between these determines the shape the
deposit will take (deposit contact angle ). From [33].
Figures 5.a-c show the three main modes growth may follow. For homoepitaxy or lattice-matched growth
with a low interfacial energy (the second energy condition in Figure 4), growth will be in a layer-by-layer
mode (also known as Frank-van der Merwe) (Figure 5.b) [25,33]. Here, monolayers will be completed
without too many significant height variations in growth across the surface. If the surface is stepped, and
the spacing between steps is short enough compared to the migration length of adatoms, adatoms may
preferentially bond to step edges instead of on the surface, where more bonds are available [25,27]. This
growth mode is called “step-flow” growth, where the steps will grow laterally. If the spacing is large, then
layer-by-layer growth is more likely. Growth rate, temperature, degree of miscut of a wafer, and if a non-
, Island Growth,
, Layer Growth,
18
planar structure is being grown, among other factors, all play a role in whether the step-flow mode or
layer-by-layer growth occurs [25]. In either case, the flat or stepped surface will be preserved through
these 2D growth modes.
Misfit strain (which isn’t relieved by dislocation generation) will increase the interfacial energy and may
lead to the first energy condition in Figure 4, “Volmer-Weber” or island growth (shown in Figure 5.a)
[20,33]. For the GaP growth on Si discussed previously, the poor surface coverage of P on Si leads the
interfacial energy to also be too large (the Si surface isn’t covered enough by P), and along with the
strong nuclei self-energy, it also forms in the 3D island mode.
If the interfacial energy is not too large initially, layer-by-layer growth may proceed for one or a few
monolayers, but the interfacial energy will steadily increase. Eventually, island growth will begin. This
mode is called “Stransky-Krastinov” growth (Figure 5.c).
Figure 5: The three main growth modes that may arise during growth and how it proceeds for various surface coverages, in
monolayers ML. (a) Island growth. (b) Layer-by-layer growth. (c) Stransky-Krastinov growth. From [20].
Lastly, the 3D growth mode may eventually give way to a 2D mode. After a film has relaxed, due to the
different growth rates between planes, height variations may eventually diminish [19,39]. However, the
initial nucleation density on the surface and how large the height variations are in the growing film will
19
impact how planar the film will become. In some cases, chemical mechanical polishing may be needed
[11,40].
2.3: Selective Area Growth
In selective area growth (SAG), the difference in decomposition of precursors on different surfaces is
exploited to form micro- or even nano-scale structures of many shapes and sizes. These structures are
grown in windows in dielectric masks, which expose the preferable semiconductor growth surface. An
example is shown in Figure 6, where I have grown InP microstripes on (100) InP out of 80 nm-thick,
10 µm-wide windows in a PECVD silicon nitride mask. These stripes take on a trapezoidal mesa cross-
section, formed from the interplay of differing growth rates between the planes and the migration of
adatoms between them. Even alloy or doping composition of layers within such structures may be altered
by taking advantage of differing incorporation rates of species on various crystal planes.
Figure 6: Top-down SEM of pair of InP microstripes (light) grown homoepitaxially out of 10 micron-wide openings 80 nm deep in
a PECVD silicon nitride mask (dark background). The stripes have overgrown the mask partly, which is expected with SAG.
2.3.1: Requirements for Selectivity
The decomposition of hydrides is often greatly enhanced on semiconductor surfaces compared to
dielectric surfaces. The same is also true for metalorganic precursors, such as TMGa on GaAs [25].
However, this selectivity is not perfect, and some growth on the dielectric mask may occur.
Mask
InP
20
To improve selectivity, lower chamber pressures and higher gas velocities are often used, which as
mentioned previously suppresses gas-phase reactions by decreasing the transit time of precursors to the
growth surface [16,17,25]. Otherwise, the elemental species that would form from these homogeneous
reactions would have little-to-no selectivity in their deposition. In our system, a carrier flow of 3.5 sLm
for both the upper and lower manifolds is used, and the reactor pressure is set to 1/10
th
atmosphere, or
76 Torr.
Due to their volatility, for standard growth conditions in MOCVD (low-pressure, mid-temperature
regime), the both the reactant and product of the V-source will easily desorb off the dielectric surface. As
such, selectivity is not dependent on the concentration of the V-source. However, selectivity is affected by
the concentration of the III-source. There are limits to how high the III-partial pressure can be increased
until the growth enters a regime where selectivity is lost and net deposition on the mask occurs [16].
Naturally, increasing the temperature improves selectivity by increasing the desorption rate of the species
on the mask. Increasing the V-overpressure will not alter selectivity.
2.3.2: Growth Rate Enhancement
Selective area growth has added complications besides ensuring growth only occurs on the exposed
semiconductor surface. One of the more interesting effects is growth rate enhancement. As long as
selectivity holds, precursors will not be consumed over the mask surface. Adjacent windows in the mask,
where the III-precursor is depleted, a concentration gradient in the vapor phase develops that, through
diffusion, feeds more precursor to the opening and enhancing the growth rate [16,17,18,41]. This lateral
vapor phase diffusion occurs within the stagnant “boundary layer” above the growth surface, where
precursor motion is dominated by diffusion. Unlike the transport of the sources from the reactor’s
showerhead gas injector, this lateral diffusion is controlled by not only the diffusion coefficient of the
species in the gas phase, but also how rapidly they adsorb onto the growing material [18]. Because these
rates will vary based on the chemistry of the precursor and the semiconductor surface, the growth rate
enhancement will vary between materials. Sang Jun Choi from our group calculated that the average
21
diffusion length of the precursors in the vapor phase for a 2D structure (such as a microstripe opening) is
40 µm for InAs, 65 µm for InP, 160 µm for GaAs, and 300 µm for GaP, as shown in Figure 7.a [18]. The
smaller this length, the larger the enhancement. This simulation was performed for a 50 µm-wide opening
surrounded by varying widths of mask, with the length direction long enough to be ignored. The
simulation agreed with experimental results in the literature and from our group, showing that the
enhancement ratios decrease as R
InAs
>R
InP
>R
GaAs
>R
GaP
. Caneau et. al. suggest that this difference comes
from the differing decomposition rates of TMIn, TMGa, AsH
3
, and PH
3
[42]. Meanwhile, for smaller
openings, such as a circle or square, a 3D simulation had to be employed. The enhancement ratios were
found to change to 25, 35, 70, and 120 µm for InAs, InP, GaAs, and GaP, respectively [18].
Figure 7: (a) Dependence of growth rate enhancement on mask coverage, surrounding a 50 um-wide microstripe opening. Note
the difference in enhancement ratio for different materials, originating from differing decomposition rates of the precursors and
their interactions with one another. Simulation: lines, measurement data: markers. (b) Schematic of the various mechanisms
precursors arrive on a growing selective structure. From [18].
Increasing the mask area between SAG windows locally increases the concentration of precursors in the
vapor phase, increasing the enhancement ratio. The increase generally follows a linear trend, but in
practice, the enhancement ratio for a fixed opening width saturates beyond a certain mask width/opening
separation. Kayser et. al. found for 610 °C growth of InP within an array of 5 µm-wide microstripe
windows with an increasingly wide separation, the enhancement saturated around a separation of 30 µm
(a)
(b)
22
[17]. The enhancement ratio will also be larger for narrower openings, as more precursor is supplied to a
smaller area [41].
Since simulating the exact growth rate enhancement for patterns can be complex, in practice, finding the
real enhancement ratio by comparing the growth rate of an unmasked wafer piece to that within the SAG
window is recommended, especially when layer thickness of a selective structure needs to be precisely
controlled.
Besides vapor-phase diffusion, surface migration from the mask to the window or between facets on the
growing structure are also possible avenues of non-planar growth effects, shown in 7.b. For the former,
however, precursor migration on the mask surface is not a significant source of enhancement [16,18].
Choi added narrow openings to the side of the main SAG microstripe window in his SAG experiments,
which would block surface migration of precursors from the mask to the main window, did not lead to
any noticeable changes in the growth rate enhancement of the material in the main opening. Instead,
precursors desorb off the mask (assuming perfect selectivity), rather than migrate.
The latter migration mechanism, the migration between crystal planes, plays a significant role in growth
morphology and even affects composition of alloys.
2.3.3: Effect of Opening Geometry on Growth Morphology
Selective area growth can often result in highly-nonplanar morphology, depending on window geometry
and the crystal plane of the exposed semiconductor surface. For instance, the two different (111) surfaces
can give greatly different morphologies for nanowire growth. For InP, only the (111)A plane is conducive
for vertical nanowire growth [26].
The crystal planes present on the surface and on the selectively-grown structure are ultimately determined
by the surface energy of the planes compared to others, which is heavily controlled by the dangling bond
density on those planes. How the density of dangling bonds is altered by adsorption will impact the
growth rate on that plane.
23
For InP selective growth on the (100) surface, the dominant crystal planes present (especially for
nano/microstripes) are (111)A, (111)B, (100), (1-10), and (110). The (111)A plane for InP and other
semiconductors tends to be the fastest-growing of the most common growth planes, with a bond density
per unit area of 1.73 [41]. Next comes the (100) plane, with a bond density of 1. Finally, bonding on the
(111)B surface, with a bond density of 0.58. The growth rate on the {110} planes is more strongly
affected by chamber conditions beyond III-mass transport than others, as will be discussed shortly.
The change in dangling bond density on different crystal planes is also important. Not only is the
dangling bond density higher on the (111)A surface, but as Julian et al note, an In atom on that surface
would be bonded to two P atoms, decreasing the number of dangling bonds [19]. Growth on the (111)A
surface for InP is energetically favorable. Meanwhile, on the (111)B surface, the number of dangling
bonds would increase with bonding, making growth on this surface energetically unfavorable.
The orientation of the selective opening on the substrate has one of the strongest impacts on ultimate
growth morphology, as it determines what crystal planes will be present. For nano/microstripe openings,
with one dimension much larger than the other, growth morphology can be described with 2D vertical
cross-sections, such as with the SEM image in Figure 8 below. The orientation of stripe openings is
typically described by the direction of the long-dimension. In Figure 8.a, the stripes are oriented along the
[110]-direction (into the page). The stripes in Figure 8.b are oriented along the [1-10] direction instead.
24
Figure 8: Cross-sectional SEM of pairs of InP microstripes grown homoeptixially out of 10 µm-wide, 80 nm-deep openings in a
PECVD SiNx mask, grown at 660 °C at a V/III ratio of 238. (a) Stripes oriented along the [110] direction (into the page). Note the
edge enhancement, circled in red. (b) Stripes grown along the [1-10] direction, 90° rotated off [110]. Edge enhancement has
been significantly reduced. The edge enhancement occurs over a 1-µm length at the edge of the (100) top surface.
The [110] and [1-10]-directions for microstripes are well-studied, as they correspond to cleavage planes
for zincblende semiconductors, making patterning and cross-sectional studies simpler. Microstripes
generally take on a trapezoidal or triangular cross-section in these directions, and the top (100) surface is
bounded by the (111)B and (111)A sidewalls, respectively. This difference in bounding sidewalls for
these two orientations greatly impacts the morphology of the stripes.
Since adjacent crystal planes will have differing growth rates, if a slow-growth facet, such as the (111)B
plane, is small enough compared to the surface migration length, an adatom may migrate off that plane
and onto a faster-growth plane, further enhancing the growth on the faster-growth plane. For relatively
wide, micron-scale openings, this results in non-planar edge enhancement on the top surface, sometimes
referred to as “bird beaks”. This can clearly be seen in Figure 8.a, with much less-prominent enhancement
for 8.b.
If the openings are too narrow, stripe growth in the [110] direction may lead to a complete disappearance
of the (100) surface, with the two bounding (111)B planes meeting each other or even pinching off into a
triangular cross-section, as demonstrated in Figure 9 [17]. For the growth conditions used in Figure 8,
because the edge enhancement occurs over a 1-µm distance, the (100) surface on the top of the stripe
(a) (b)
Ꙩ [110]
Ꙩ [1-10]
InP substrate
[100] [100]
(111)B
(111)A
25
would disappear for an opening width slightly larger than 2 µm, as the footprint of the stripe is slightly
wider than the top.
Figure 9: Disappearance of top-(100) InP surface of [110]-aligned stripes as the opening width is reduced. (a) Edge-enhanced
mesa-cross-section of a [110]-aligned microstripe. (b) Triangular cross-section where the (100) surface has disappeared. This
triangular cross-section is especially common for sub-micron width openings, which will be used for this project.
If the selective growth within the opening is prolonged, the material will grow on top of the mask in a
process called “lateral epitaxial overgrowth” [18,19]. The degree of overgrowth is dependent on the
bounding sidewall of the growth structure at the edge of the mask, and the growth rate of that facet. Stripe
openings were chosen for this project due to their simpler faceting. With only one sidewall morphology to
consider for a given stripe geometry (though growth conditions may alter the sidewall morphology as will
be mentioned shortly), control of this overgrowth becomes easier as well. It is this mechanism that is the
driving force for coalescence, where two overgrowth fronts from adjacent stripes merge into a continuous
structure. With that in mind, the edge enhancement experienced by stripes along the [110] direction
makes them unsuitable for coalescence, as a flat (100) surface is needed. The slow (111)B growth rate
also leads to a slow overgrowth rate, thus a greater tendency for vertical growth. Any non-uniformities in
height along the length of the stripe could be exaggerated as a result, and a merged film from these stripes
would likely be rougher than that formed from stripes along the [1-10] direction. The differences in
overall stripe morphology for [1-10] and [110]-oriented stripes are demonstrated in Figure 10 below.
(b) Wide opening: Mesa shape
(111)B (111)B (111)B (111)B
(100)
(a) Narrow opening: Triangular shape
26
Figure 10: Schematic of typical cross sectional morphology for homoepitaxial InP selective growth in [1-10] and [110]-oriented
openings.
Finally, for growth in stripe openings oriented off the <110>-directions, stripe morphology becomes
considerably more complex. The sidewall is no longer simply a (111) surface, but is instead a
combination of multiple planes—sometimes forming into higher-order planes, but often possessing a
stepped structure [19,43]. In Figure 11 below, Choi grew stripes in microscale openings oriented along
different directions.
27
Figure 11: Cross-sectional SEM of InP/InGaAsP layered stripes grown in micro-scale angled openings, (a) 0°, (b) 10°, (c) 25°, (d)
45°, (e) 90° off [110]. The darker layers in the stripes are InGaAsP. From [18].
Altering the opening orientation angle of the stripes affects which planes are present, and how strong of
an impact those planes have for the overall sidewall. The stripes start with a trapezoidal cross-section with
noticeable edge enhancement due to their [110]-alignment and (111)B sidewalls [18]. Slightly angling the
stripe direction by 10° (b) adds two additional planes to the sidewall: a predominantly (111)A underside
and a vertical (110) and (1-10)-mixed facet. The top of the sidewall remains predominantly (111)B, but
increasing (111)A and {110} character. Increasing the angle further to 25° (c) leads to a surprising
result—the stripe has taken on a “dovetail” shape, with the predominantly-(111)A underside much larger
than would be expected. As will be discussed in more detail shortly, this dovetail shape originates from
28
growth rate differences between the (110) and (1-10) planes, which depend on growth conditions [19].
Altering the angle will adjust how much of either {110} plane makes up the sidewall. Julian et al
observed a similar stripe morphology for a 30° angle off [110] (or 60° off [1-10]), with the underside
stepped and the top of the sidewall smooth [19]. They also found that this particular stripe morphology
“overgrew” the mask even more easily than the [1-10] direction, since less of the mask surface was
contacted by the InP—the footprint of the stripe is smaller.
At a 45° stripe angle, the sidewalls are {110} in character from the stripe being along a <100> direction,
and although the other side is not shown, due to usually the different growth rates of the planes, that the
stripe may be asymmetric [18]. Finally, at a 90° angle off [110], or in other words, [1-10]-aligned, edge
enhancement is absent, and the sidewall is (111)A in character, with a (111)B underside.
Whether a facet on the sidewall is smooth or stepped is determined by the intersections of planes—the
intersection of the (111)B and (110) plane is energetically favorable (dangling bond number changes by
−2), and thus there is a possibility of a flat higher-order plane forming here, rather than (111)B and (110)
planes alone [19]. For the (111)A and (110) intersection, however, the number of dangling bonds would
increase if bonding occurred there, so it is more energetically favorable for the two planes to be
maintained separately. This gives a stepped surface to the latter plane intersection.
Understanding the sidewall morphology is vital for proper control of coalescence. Unfortunately, these
observed structures are not general for the particular opening orientations they were grown in, and are
strongly impacted by growth conditions.
2.3.4: Effect of Growth Conditions on Morphology
Growth conditions can further affect growth morphology beyond opening geometry alone. As mentioned
previously, migration between crystal planes of differing growth rates can further enhance growth rates.
The migration of adatoms is determined by both the V-precursor overpressure and the temperature.
Increasing the temperature gives an adatom more energy to move between sites more readily by allowing
29
it to break or stretch bonds, and the rate follows an Boltzmann trend,
, with A some rate
constant and
the activation energy of the process [19,25,27]. Increasing the temperature strongly
increases the attempt rate of migration, and thus the average migration length greatly increases.
The effect of V-overpressure is more subtle. At higher V/III ratios, the surface is said to possess more “In-
vacancies” where In adsorption is favorable. In effect, the V-source will “seize” the III-adatom by
bonding the V-element to it, arresting surface migration more strongly the higher the V/III ratio is, and
leave the surface more predominantly covered with the V-species. At high V/III ratios, edge enhancement
for [110]-oriented stripes can be suppressed [17]. What determines whether a V/III ratio is “high” or “low”
depends on the situation, but generally, the existence or suppression of edge enhancement is a good
measure.
Migration is also important for ensuring quality faceting of the selective structure. Kayser et. al. found
that, as the temperature is decreased, and although there is a greater tendency for edge enhancement,
sidewalls become rougher [17].
With off-<110>-angled stripes, the effects of growth conditions become more pronounced. Kayser et. al.
report that for stripes oriented 60° off [1-10], a dovetail shape emerged at lower growth rates (75 mPa
TMIn), while at higher growth rates (150 mPa TMIn), the profile of the stripes took on the more familiar
trapezoidal wedge/mesa shape [17]. With the PH
3
partial pressure held constant at 60 Pa, however, this
change in morphology could actually be due to the change in the V/III ratio. The aforementioned dovetail
shaped Julian et. al. reported disappeared with a reduction in the V/III ratio from 248 to 124 [19].
The effective growth rates of the different surfaces, especially for stripes oriented off the standard <110>
directions, are altered by changes in growth conditions. Asai notes that the growth rates for GaAs in the
[110] and [1-10] directions change with temperature and V-overpressure [44]. Although his model was
used for GaAs, it is also applicable for InP. Asai modeled the growth rates and found a close match to
30
what was experimentally observed for the lateral growth of a round mesa structure formed on a GaAs
wafer.
The change in the growth rates with temperature can be explained with Figure 12 [44]. The As atom at a
[110] step edge is only held to the surface by one bond if the edge Ga atom migrates away. It would then
easily desorb, hindering the overall growth rate in that direction. Meanwhile, an As atom at a step edge in
the [1-10] direction, even after the edge Ga atom migrates, will be held to the surface by two atoms, and
thus the growth rate in that direction is more stable with stable with increasing temperature.
For the effect of V/III ratio, the rate in the [110] direction is faster at higher V/III ratios due to the greater
number of bonds at the step edge for the Ga atom: 3 for the [110] direction instead of 2 for the [1-10]
direction [44]. When the V/III ratio is dropped, however, there is a greater tendency for the As edge atom
in the [110] direction to desorb due to enhanced Ga migration, lowering the growth rate in that direction.
The growth rate in the [1-10] direction, meanwhile, is stable with V/III ratio, again due to the greater
number of bonds holding the As atoms to the surface.
As for the growth rate on the (100) plane, it is not largely affected by changes in temperature or V/III
ratio, even up to 800 °C. The Ga and As atoms both held in a more stable arrangement than on the {110}
step edges, not as strongly affected by migration or desorption.
31
Figure 12: Schematic of growth on (100) GaAs on [110] and [1-10] step edges. The difference in bonding arrangements of the Ga
and As atoms at the step edges affects how the growth rates will change with changing temperature or V/III ratio. The As atom
at the step edge along the [110] direction will only held by one bond (circled in red) if the Ga atom to the right of it migrates
away from the step. Meanwhile, in the [1-10] direction, the As atom at the step edge is held by two bonds (circled in red). From
[44].
2.3.5: Enhancement Effect on Composition
The growth rate enhancement also has an unexpected side-effect for semiconductor alloys: due to the
difference in vapor-phase diffusion lengths from the mask to the growing surface, certain adatoms may
incorporate more readily into a growing alloy than others. As shown in Figure 13, when Choi increased
the growth rate enhancement by increasing the mask width outside an opening leads to an increasing
wavelength in an InGaAsP layer within the InP microstripe, also slightly varying with stripe orientation
due to the different growth rates on the sidewalls [18]. Caenegem et. al. and Caneau et. al. suggest that the
compositions for ternaries and quaternaries varies with the individual enhancement ratios of their
constituent binaries [18,41,42]. For InGaAsP, this would mean an increasing growth rate enhancement
would lead the wavelength to tend toward that of the fastest-incorporating binaries, namely InAs.
Meanwhile, InGaP should tend toward InP with increasing enhancement. The consequence of this effect
is the development of misfit strain in selective structures with alloy materials, which can be exploited to
vary the composition within a single growth run just by altering the pattern geometry.
32
Figure 13: Dependence of the peak wavelength of a (100) InGaAsP layer within an InP microrstripe on growth rate enhancement
from increasing the masked area outside the 15 µm-wide stripe opening. From [18].
33
Chapter 3: Aspect Ratio Trapping and Coalescence
In this chapter, a strategy to address defect generation from heteroepitaxy, aspect ratio trapping, will be
discussed, where the propagation of defects (which typically lie on (111) planes for InP) are blocked by
high aspect-ratio openings in a selective growth mask. Through its use with parallel arrays of nanostripe
openings in a selective mask (with stripe growth discussed in the previous chapter), stripe structures that
emerge from the openings are allowed to laterally overgrow the mask and merge (termed “coalescence”
in this chapter), forming a quasi-substrate for integration of InP-based devices. This technique is not
limited to InP, and may also be applied to GaAs and other materials [20].
3.1: Challenges to Monolithic Integration of Compound Semiconductor
Structures and Devices on Si
3.1.1: Heteroepitaxy and Defect Generation
When a material is heterogeneously grown on a target substrate, the mismatch in the lattice constant and
thermal expansion coefficient will lead to the film and structure being strained. After a certain thickness,
defects will be formed to reduce the strain energy of the epitaxial material. For InP grown on Si, desirable
for 1.55 µm integration of InGaAs or InGaAsP photodetectors or lasers to Si photonic structures, there is
nearly an 8% compressive strain formed from the lattice mismatch, and the relative difference between
thermal expansion coefficients is as high as 77% [4].
Dislocations are one of the most common defects generated from this strain. For zincblende
semiconductors, dislocations will almost always lie on (111) planes, with non (111)-lying defects only
being significant at ultra-low defect densities ~10
2
cm
-2
or lower [45]. These majority of dislocations have
line vectors along <110> directions, and have Burger’s vectors (the direction of their glide) 60° off the
line vector, meaning they are a “mixed” type of dislocation, but closer to edge than screw. A dislocation
loop showing the change in the dislocation line vector l with respect to the Burger’s vector b, depicting
edge, mixed, and screw dislocations on a slip plane, is shown in Figure 1 [46]. When l and b are parallel
or antiparallel, the dislocation is screw-type. When they are 90° off each other, the dislocation is edge-
34
type. Anything in between is mixed-type. Unless they annihilate (dislocations of opposite sign, or rather
their extra half planes are on opposite sides of the slip plane, meeting) or terminate at a free surface, some
other defect, or the exposed surface of the epitaxial layer, the dislocations must form a loop within the
semiconductor material. The line vector will always be tangential to the loop and point either clockwise
or counter clockwise, while the Burger’s vector will always point in one direction.
Figure 1: Dislocation loop on a slip plane, showing the change in the line vector l with respect to the Burger’s vector b, defining
edge, mixed, and screw dislocations. Adapted from [46].
Ꙩ Slip Plane
Edge
Mixed
Screw
35
Figure 2: Schematics of (Left): a perfect dislocation and (Right): a stacking fault for a FCC/zincblende/diamond structure crystal
structure. The three layers are (111) planes, with blue, green, red atoms layers/sites A, B, C, respectively. For this particular
stacking fault, a line of atoms has moved from the C site to the A site. The perfect dislocation has a Burger’s vector b1, which is a
linear combination of the two partials’ Burger’s vectors b2 and b3 [47].The perfect dislocation’s “extra half-plane” is beneath the
missing line of atoms, and all of the red atoms are bonded to one another, even across the gap.
Dislocations in semiconductors may also dissociate into “partial” dislocations, forming a stacking fault.
Here, as shown in Figure 2, the atoms on the surface near the original dislocation shift to an undesirable
position, away from the usual ABCABC stacking of the (111) planes (for zincblende semiconductors), to
a sequence more like ABABCA in this case. The partial dislocations bound the stacking fault and have
two new Burger’s vectors, along b
2
and b
3
= <1-21> directions instead of the original b
1
= <110>, such
that the original is a linear combination of the partial dislocations [47]. While dislocations are considered
one-dimensional “line” defects (based on their cores, where the missing atoms are in Figure 2), stacking
faults are two dimensional due to them being a partial plane of misplaced atoms. A related defect is a
microtwin, where the stacking sequence reverses temporarily, such as the sequence ABCBACBACABC.
Stacking faults and microtwins can interfere with the morphology of a nanostructure by locally
introducing unwanted planes, which could have different growth rates than neighboring non-defective
regions of the structure, leading to a non-uniform shape [48]. Along with dislocations, these may also
locally alter the etch rate of solutions, possibly leading to a non-uniform etch of a film or structure. A
similar effect may occur through mass-transport of adatoms preferentially away from a defect penetrating
the surface at high temperatures [49].
36
Figure 3: (Top) Schematic of an InP PN junction grown directly on Si, with dislocations or other defects (black) penetrating the
depletion region and interface. (Bottom) Trap-assisted generation and recombination compared to standard generation and
recombination. The presence of defects in the depletion region increases the reverse bias leakage current by increasing the n=2
SRH recombination-generation component [5]. In the forward bias, nonradiative recombination (producing a lattice vibration
rather than emitting a photon) from these defects reduces the quantum efficiency of devices such as LEDs.
In general, the defects that form through heteroepitaxy can greatly hinder device performance. For pin
photodiodes, the presence of dislocations or other defects in the absorbing layer can lead to an increase in
the reverse-bias saturation current. In other words the dark current, due to the n=2 term of the IV
characteristics, the Shockley-Read-Hall Recombination-Generation current, increasing from trap-assisted
generation and recombination in the depletion/absorbing region, as demonstrated with the defects in the
schematic in Figure 3 [5,50]. With a larger dark current, slight changes from light absorption will be
37
harder to discern from noise, reducing the sensitivity of the device. For LEDs and similar devices, this
also leads to a reduction in the quantum efficiency due to non-radiative recombination of carriers in the
depletion region.
3.1.2: Early Methods of Defect Filtering
Defects generated through misfit strain can be difficult to suppress. Strain engineering through the use of
buffer layers, strained-layer superlattices, and even quantum dots have been proposed [14,51,52,53,54].
Although they can repel or pin dislocations, quantum dots remain difficult to reliably form with MOCVD,
due to their tendency to coalesce and form further defects, especially at higher strains [53,54]. For buffer
layers, unless they are exceedingly thick (often 10 µm or thicker), they do not effectively reduce defect
densities at all. Studies from other groups and our own studies of InP film growth on Si have shown a
defect density greater than 10
9
cm
-2
form within them [4,14]. The buffer layers also often need to be
annealed, which may be incompatible with optoelectronic integration—possibly damaging pre-existing
devices structures on the sample.
Strained-layer superlattices, which engineer the strain in alternating layers to bend defects to annihilate
each other or not propagate vertically, are far more effective than buffer layers and are generally the most
attractive traditional method for defect mitigation. However thick layers still need to be formed, and
defect filtering still relies on the random chance of defects annihilating with each other [14].
Finally, although many semiconductors, such as Si, GaP, or GaAs, can have dislocation glide and climb
controlled through strain engineering, some materials do not behave in this manner. InP, for instance, has
a very low stacking fault energy—18 mJ/m
2
as opposed to 55, 43, and 45 mJ/m
2
for Si, GaP, and GaAs
respectively [55]. The lower the stacking fault energy, the more likely stacking faults or microtwins are to
form from dislocation dissociation into partials, rather than simple dislocation glide or climb [49,55].
Only GaN or II-VI materials have comparable or lower stacking fault energies. Once the InP layer is
grown, further defect reduction through additional superlattices may not be as effective, especially if the
lattice constant of InP is the target. Lowering the growth rate of InP may help suppress this dissociation,
38
but as strain induces glide and climb in high stacking fault energy materials, any other types of strain,
such as thermal strain, could still lead to stacking fault formation.
3.1.3: Proposed Method for Large-area Monolithic Integration with Defect Filtering
Much work has been done with the selective growth of nanostripes and other structures in high aspect
ratio, defect-filtering openings, and devices such as LEDs and even nanolaser arrays have been
constructed using them [56,57]. However, the merger of these defect-filtered structures into a continuous,
macroscopic film, which gives more freedom for device fabrication, is not as well-studied. Most
published attempts at the coalescence of adjacent InP nanostripes have used a seed layer under the
selective mask of the same material as the coalesced film, as shown in the schematic in Figure 4.a [4,11].
This seed (also referred to as a buffer layer) is first grown on the (typically Si) substrate, and may be
solely InP or may have other layers prior to that to aid in nucleation of the InP or to reduce the strain
experienced by the InP. Chemical mechanical polishing (CMP) may also be employed for the InP top
layer of the seed to improve the surface roughness of the selective mask to avoid creating further
complications to coalescence [40].
To our knowledge, attempts at coalescence of defect-filtered nanostripes without a buffer layer have
resulted in rough surfaces, or have necessitated the removal of the selective mask prior to coalescence, as
shown in the schematic in Figure 4.b [8,21].
A major goal of this project would be to show, through MOCVD, neither a buffer layer under the
selective mask nor CMP at any stage are necessary for coalescence and aspect ratio trapping to give a
similar or even superior surface roughness and defect density to a buffer layer grown on Si alone. To our
knowledge, so far, the use of buffer layers (and their derivatives such as strain layer superlattices) has
been the only widespread method for the monolithic integration of InP-based optoelectronic devices on a
large-area (ie typical photodiode area) film on Si [7,22].
39
Our proposed structures are shown in Figures 4.c and 5, schematics of the coalesced films. In Figure 4.c,
the target structure is shown. InP is grown in selective openings in a dielectric mask and allowed to
emerge and overgrow it to form a continuous film. The openings have an aspect ratio defined by the ratio
of their height H to their width W
O
. The sidewalls—twice the distance a stripe must overgrow to meet
another stripe, have width W
M
. This gives the stripe pattern pitch W
M
+W
O
.
Beyond varying growth conditions, such as growth temperature or the initial growth of other materials at
the bottom of the openings, the geometry of the mask will be altered and its effect on coalesced film
morphology and defect density will be characterized.
Increasing the stripe pitch by increasing the mask sidewall width will reduce the area of the exposed Si
surface (Figure 5.a), potentially reducing the defect density in the coalesced film (as the Si-InP interface
would be smaller). There would also be fewer points of coalescence to deal with, as the merger of
adjacent stripes can form new defects if the stripes meet in a nonuniform fashion [19,58]. However, the
InP would have to overgrow the mask to a further extent, and the interaction of the mask with the
overgrowing material can thermally strain it [59].
40
Figure 4: Different approaches for selective growth and coalescence of nanostripes to form a “quasisubstrate” for device
integration. The green is the mask. (a) Standard method for coalescence: a polished InP (or multi-layer) buffer layer serves as a
seed to aid in growth in openings on top of it. (b) An approach used by the Lau group, which allows for coalescence on exact-
(100) Si, using etched grooves in the Si surface after mask removal [8]. (c) Proposed approach: no buffer layer used under the
mask. The openings are width Wo, the sidewalls width Wm, the pitch defined as Wo+Wm, and the sidewall height (also opening
depth, unless the Si was etched into during patterning) is H.
(a)
(b)
(c)
41
A narrower-sidewall mask (Figure 5.b), one with a shorter height H, would alleviate thermal strain issues
of the mask on the semiconductor, on the basis the volume of it is smaller, but the aspect ratio of the
openings would be reduced without also reducing the opening width. Narrower openings present other
challenges with growth besides fabrication, as nucleation becomes more difficult [39].
Altering the orientation of the stripe openings with respect to the [1-10] direction on the substrate surface
is another consideration (Figure 5.c–d). As discussed in Chapter 2, the planes present on the sidewalls of
the stripes will change with the orientation angle, and around a θ = 60−70° orientation of the stripes off
[1−10], the usual trapezoidal cross-section inverts to form a dovetail shape, which minimizes the contact
of the overgrowing material to the mask as well as minimizes the contact area of merging stripes [18,19].
Lastly, the morphology and defect density of a standard thin film grown on Si, and a coalesced film with
a buffer layer under the mask will be characterized as a comparison to the proposed seedless approach.
42
Figure 5: Additional mask geometries considered in this project. (a) Wide-pitch mask, meant to reduce the number of defects
that escape the openings or form via coalescence by reducing the opening density. (b) Low-thickness mask, meant to address
possible thermal strain-induced defects, though potentially hindering defect filtering. (c) and (d): Top view schematic of [1-10]
and off-[1-10]-aligned openings. Insets: (c) cross-section of a mesa-type stripe grown along a [1-10] direction. (d) Dovetail-type
morphology of a stripe, with an inverted sidewall, grown at an angled-stripe orientation 60-80°-off-[1-10]. From [18].
Dovetail Mesa
(c) (d)
(a)
(b)
43
3.2: Aspect Ratio Trapping
An alternative to the aforementioned approaches of reducing defect density is aspect ratio trapping. J Li et.
al. suggested using selective area growth in high-aspect ratio openings in a dielectric mask to block defect
propagation [21,60]. With this approach, a dielectric SAG mask is patterned on the desired mismatched
substrate (typically Si), but with openings deeper than they are wide (giving a high aspect ratio). Selective
growth on the exposed substrate within the openings proceeds as normal. However, at least for a (100)
substrate, with the high aspect ratio, threading dislocations and related Si interface-generated defects will
have their line of sight out of the selective opening blocked by the mask sidewalls, as shown in Figure 6.
Figure 6: Cross-sectional schematic of aspect ratio trapping in nanostripe openings. This is what might be expected from cross-
sectional TEM of dislocations or stacking faults TD: threading dislocation.
In materials where dislocation glide is favorable, the presence of the dielectric mask may even attract
dislocations to them and filter defects that generate above the Si interface. Behaving like a free surface,
the mask can attract dislocations near it (on the order of 10s of nm, depending on mask thickness) through
an “image force” [61,62]. Here, the alteration of the strain field for a dislocation near a surface can be
simulated by the presence of a parallel and opposite sign virtual dislocation on the other side of the
surface, attracting the dislocations toward it. The mask also induces strain on the semiconductor material,
creating a gliding force which also attracts dislocations, and relieving the thermal strain between the
44
growing semiconductor and the Si below [63,64]. The geometrical filtering, image force, and mask-
induced strain all become more effective with increasing aspect ratio. A more detailed schematic of defect
filtering, along with the termination/annihilation of defects that reach the dielectric sidewall surfaces is
shown in Figure 7 [46]. The misfit strain from the growing semiconductor and the substrate produces a
misfit dislocation MD, which lies on the intersection of a (111) slip plane and the substrate. Threading
dislocations TD (60° mixed-type) propagate on the slip plane above the epitaxial material-substrate
interface but are annihilated by virtual dislocations VD through the image force.
Figure 7: An unclosed defect loop terminating at the mask sidewalls. The termination of threading dislocations TD can be
modeled by adding virtual dislocations VD inside the mask, with an opposite line and Burger’s vector [61,62]. The threading
dislocations are generated from an original misfit dislocation MD (itself formed from the lattice mismatch) that lies at the III/V-
substrate interface. The threading and misfit dislocations lie on a dislocation loop on a (111) A slip plane as shown in Figure 1,
but the loop is incomplete, terminating at the sidewalls. Adapted from [46].
The effectiveness of aspect ratio trapping depends on the geometry of the opening. A deep hole, with both
lateral dimensions narrower than the depth of the opening should theoretically block all defects generated
at the Si-III/V interface. For the more typical <110>-aligned stripe opening, with one lateral direction
45
sometimes millimeters-long, suppression of defect propagation in the long direction may not occur, as
defects would have a line of sight out of the opening. However, because the dislocation line vectors are
not <111>, but rather <110>, Q Li et. al. suggest that, with a high enough aspect ratio, threading
dislocations at least can be completely blocked [65]. Other defects, such as stacking faults or microtwins,
may not be blocked.
With a high-enough aspect ratio, both {111} defect planes could be blocked by the sidewalls. The aspect
ratio required to block both planes is given by , where is the angle between the stripe
orientation and whichever {111} plane is closest to it, that is within . Alternatively, if we
define the stripe misorientation angle to be off the [1-10] direction, then
The value 1.412 comes from , with 54.7° the angle the (111) plane makes with the (100)
surface. This value is also the required aspect ratio to block at least one of the (111) planes for stripes
along one of the <110> directions. For stripes oriented 60° off [1-10], then the necessary aspect ratio is
approximately 1.6 to block both (111) planes.
For blocking stacking faults or other planar defects, however, Junesand et. al. suggest that for stripe
orientation angles off [1-10] less than 45°, stacking faults lying on (111)A slip planes cannot be blocked
[66]. To find the necessary aspect ratio, Eqns 1 and 2 are modified to take account for the new
propagation directions of the partial dislocations bounding the stacking fault or microtwin. To block any
stacking faults, for a stripe orientation angle 60° off [1-10], an aspect ratio of 3.9 is needed, assuming the
Burger’s vectors of the partial dislocations diverge from the Burger’s vector of the original perfect
46
dislocation by 30° (the [1-21] and [21-1] directions, for a perfect dislocation with a [1-10] Burger’s vector,
for instance). The modified required aspect ratio is given in Eqn 3:
Although Junesand et. al. propose that stacking faults propagating in the [1-10] direction do not generate
as often and were not observed, recent TEM studies from our group found stacking faults or microtwins
propagating in both <110> directions, so if this model holds, stacking faults might not be completely
blocked at all, regardless of aspect ratio.
Stacking fault and microtwin generation can be somewhat suppressed with lower growth rates, as G.
Wang et. al. found with InP nanostripe growth on Si [48]. Additionally, they suggest the initial growth of
a material that is more likely to have dislocation glide or one that generates fewer defects at the Si and InP
interfaces (such as an intermediately-strained material like GaAs) may also help avoid these problems
[49].
Lastly, although the thermal strain induced by the mask can aid in defect filtering (for materials where
dislocation glide is favorable), with enough bulk mask present, the thermal strain can generate new
defects. If the mask is too thick, the difference in thermal expansion coefficients between it and the
substrate can lead to cracking [61]. Twins were reported by Orzali et. al. for GaAs SAG on Si in a thermal
SiO
2
mask, despite using a high aspect ratio (>3) and narrow (sub-100 nm-wide) openings [59].
Fortunately, Orzali et al note that a high semiconductor-to-mask volume (that is, a thinner sidewall
compared to the opening width) may suppress defect formation, as the thermal strain would be reduced
[59]. J Li et. al. reported defect-free GaAs stripes grown in high aspect ratio trenches, as the mask
sidewalls were at most one-third the width of the opening [21,60]. Choice of mask material would be also
important, as the thermal expansion coefficients for thermal SiO
2
and PECVD SiO
2
are very different,
3.5E-7 °C
-1
2.6E-6 °C
-1
respectively (deposition temperatures 950-1150 °C and 200 °C respectively) [67].
This is compared to InP’s 4.6E-6 °C
-1
, meaning thermal SiO
2
will induce a larger strain on the InP [68].
47
Although the dislocation attraction effect from thermal strain would also be reduced, for materials such as
InP with a low stacking fault energy, this would not matter, and it may even further suppress stacking
fault generation.
3.3: Coalescence and its Applications
3.3.1: Coalescence and Defect Generation
In concert with aspect ratio trapping, possible defect generation during coalescence also constrains mask
design. Even for InP homoepitaxy, defects may still form depending on how the overgrowth fronts of the
stripes converge. If the fronts are locally concave and each possess a different number of lattice points,
when they meet, one or more dislocations are formed (called “two-zipper” by Yan et. al. in their studies
of MBE and LPE stripe coalescence) [58]. A high density of dislocations forms this way, making the film
unsuitable for devices sensitive to defects. Locally convex fronts, meanwhile, meet at only a single point,
and no such dislocation forms (“one-zipper”). This is shown in Figure 8 below [4,58]. The two-zipper
mode is more likely to occur for larger sidewall areas, so the choice in growth conditions and stripe
orientation, which affects sidewall shape, is vital [19].
Figure 8: Process of defect formation from coalescence. (a) One-zipper coalescence mode, where coalescence occurs at a single
point. No defects are formed. (b) Two-zipper mode, where coalescence occurs at two points, with the number of lattice points m
and n in between on either side of the line of coalescence mismatched. One or more dislocations form after coalescence is
finished, as there will be one or more extra half planes the side with more lattice points. From [58].
(a) (b)
48
Julian et. al. have reported that the 60°-off-[1-10] orientation at higher V/III ratios (>248) minimizes the
occurrence of the aforementioned “two-zipper” coalescence by minimizing the contact area of adjacent
stripes. This is because, rather than the standard mesa present for most orientations and growth conditions,
they form a dovetail shape from the combination of {111} and {110} planes and the intersections
between them that are altered by changing the stripe orientation, the V/III ratio, and temperature [20,58].
An example of the dovetail shape is shown in the inset in Figure 5.d. At low V/III ratios (<124), stripes
oriented 30°-off-[1-10] coalesce in a more superior fashion, as the dovetail shape in the 60° direction is
absent (instead a mesa shape like the inset in 5.c is present). However, the 60° direction was found, with
optimized high V/III ratio and the inverted dovetail shape, to overgrow the mask the furthest without
forming additional defects during coalescence, with stripe pitches as large as 2.5 µm for 800 nm-wide
openings giving continuous coalescence. This is because the footprint of the overgrowth is minimized by
the inverted sidewalls of the dovetail cross-section, preventing the mask from potentially straining the
growing material.
The aforementioned interaction of the mask and overgrowing material is an important consideration for
coalescence—the material may become warped from strain or an attraction to the dielectric as it further
overgrows the mask [69]. Coalescence of two tilted growth fronts may generate additional defects, even
grain boundaries, known as “wingtilt”.
For InP the 60°-off-[1-10]-oriented stripes, with their minimized footprint during overgrowth due to the
dovetail shape, would minimize this wingtilt, as would reducing the separation between openings to
reduce the overgrowth length. Julian did not observe grain boundary formation for this pattern orientation
[4]. Careful choice of masking materials, such as using PECVD- or low-stress LPCVD-grown silicon
nitride for the SAG mask on silicon instead of thermally-grown silicon dioxide, may also help.
49
3.3.2: Current Work with Coalescence
The heteroepitaxial coalescence of selective InP nanostructures has only been studied by a few groups,
and as mentioned previously, most attempts have used polished seed layers under the selective mask. The
Lourdudoss group at KTH Sweden has, through HVPE, grown large-area coalesced films with the initial
nanostripe openings, which were oriented 60°-off-[1-10], patterned via NIL [11]. A polished InP buffer
layer was present under their SiO
2
SAG mask (initially 36 nm RMS roughness, after polishing 1.1 nm
RMS roughness). For coalescence on a Si substrate with an InP buffer layer, the coalesced film roughness
was reported to be 15 nm. For hompepitaxial coalescence (InP substrate underneath SAG mask), the RMS
roughness was 3 nm. Although defect densities were not reported, few if any defects generated from
coalescence were reported, though the group cautions stacking fault propagation out of the openings can
be an issue [66].
The Bowers group at UCSB have also worked on coalescence of InP nanostripes on silicon. As
mentioned earlier, Julian et al found that, due to their dovetail shape, nanostripes grown at a high V/III
ratio along a direction near-60° off [1-10] will overgrow the mask the best out of all orientations,
coalescing with the fewest defects (<1E5 cm
-2
generated defects for homoepitaxial coalescence) [4,19].
Applied to heteroepitaxy, a multi-layer buffer of GaAs and InAlAs was used under the SAG mask. CMP
was also performed of the buffer layer to improve coalescence. Cross-sectional TEM of the coalesced
film revealed no dislocations generated from coalescence within the cross-section.
Finally, the Lau group of Hong Kong University of Science and Technology achieved InP coalescence on
exact (100) Si with initial GaAs nucleation layers, and no buffer layer was used under the selective mask
[8]. However, the openings required for growth on exact (100) wafers needed a <110> orientation, which
may not coalesce as well [4,8,19,39]. To combat this, the selective mask was removed to improve
coalescence as shown in the schematic in Figure 4.b, perhaps at the expense of aspect ratio trapping, as
new defects would likely be formed during InP overgrowth on top of the freshly exposed Si serving as the
50
trench sidewalls. The reported defect density reaching the surface was 2E8 cm
−2
. The group has
successful made working lasers and other devices with this approach with arsenide materials [70].
In all, to our knowledge from literature, work with InP coalescence that both maintains the aspect ratio
trapping and does not use a buffer layer under the mask appears to be limited.
51
Chapter 4: Sample Preparation
4.1: Substrate Selection and Antiphase Boundary Elimination
Indium phosphide wafers were purchased from InPact in France, and were 2”, n-type S-doped, on-axis
(100). These wafers were used for initial tests with our nanostripe patterns to determine suitable growth
conditions for stripe formation and to serve as control samples for compositional studies with InGaAs,
doping and device structure growth.
The silicon wafers used for this project, 2” n-type miscut (100) wafers, were purchased from Virginia
Semiconductor. This miscut, 4° off (100) toward [0-11] was an important property of these wafers: the
(100) Si surface will not be atomically flat. Instead, it is more energetically favorable for the Si surface to
form monoatomic steps, with the 2 1 reconstruction on each step rotated by 90 degrees [71]. This
alternating bond arrangement is shown in Figure 1.
Figure 1: Schematic of a monoatomically-stepped surface, with different bond arrangements (Type A and Type B) on each step.
52
Figure 2: Monoatomically-stepped Si surface after III-V growth. Note that a III-III bond (circled in red) is present along the anti-
phase domain.
The “Type A” surface (also known as a domain or phase) is composed of bonds that are aligned parallel
to the step, while the “Type B” surface has bonds perpendicular to the step [72]. If a compound
semiconductor is grown on such a surface, a deposited layer of the cation or anion element will also be
monoatomically stepped, as shown in Figure 2. Here, the blue atoms are Si, the black are V-atoms, say P,
and the white are III-atoms, say In. The elements will shift between different FCC sublattices in the
zincblende structure between each step, and at each step edge, III-III or V-V bonds will form. These
unwanted bonds will continue up through the growing material and cannot be filtered by aspect ratio
trapping, a defect called an “anti-phase boundary” (APB) [49].
Miscut wafers, when annealed in hydrogen at high temperature, form diatomic steps in multiples of two,
with each step possessing the same configuration [71,72]. The miscut gives a greater tendency for
diatomic steps to form, and with the energy provided with the hydrogen anneal, the Type B surface will
redistribute and merge with a step, leaving only a Type A surface on the entire surface [72]. As a result,
53
no APBs should be generated if a compound semiconductor is grown on top. The anneal also helps
remove residual native oxide from the Si surface [73].
One important consideration is that the single-phase surface will not persist if, after the anneal, the wafer
is cooled to too low a temperature. Poon et. al. suggest that the crossover temperature from single to
double phase at a 3° miscut is 500 K (227 °C) [74]. The substrate needs to be in-situ stabilized with
additional deposition before it can be removed from the reactor chamber. Bringans et. al. show that
exposing the single-phase Si surface to As and then growing GaAs on top of this surface will preserve the
single-phase geometry [75].
For the mechanism of initial nucleation on this single-phase surface, Kroemer proposes that the V-atom,
in his case As, will replace a surface Si atom and two Ga atoms will bond on top of it, stabilizing the
surface [72]. The Ga and As will remain in their proper sublattices.
Without the replacement of the Si atoms with As atoms, a relatively large electric field of 4×10
7
V/cm
would develop due to the difference in the number of valence electrons between Si and As. Growth at
higher temperatures would lead to redistribution of atoms on the surface to minimize this field, including
the formation of anti-site defects (III-III or V-V bonds). This is not observed however. Instead, with the
As atoms replacing the Si, and the two Ga atoms bonded to the As atom, the As and Ga will be bonded to
an equal number of Si atoms, and no electric field will develop.
4.2: Choice of Pattern
Our initial studies with InP selective growth on Si began in an array of pairs of 10 µm-wide stripe
openings 5 µm apart with a 95 µm pitch, with a PECVD silicon nitride mask thickness of 20 nm. These
openings were defined by photolithography and etched by RIE. This pattern was primarily used to
investigate the need for low-temperature nucleation and the sensitivity of the initial nucleation layer to
higher temperatures in subsequent portions of the growths. These nucleation studies will be expanded
upon in more detail in Chapter 5.
54
The main patterns used for this project were electron beam lithography (EBL)-defined and nanoimprint
lithography (NIL)-defined arrays of stripe openings with various geometries.
4.2.1: EBL-defined Nanostripe Openings
For the first half of our project, EBL was used to define a variety of pattern geometries simultaneously on
a single sample. As shown in Figure 3, eight groupings were arranged in a 2×2 mm
2
matrix. Each
grouping contained nine 100×100 µm
2
sub-arrays of stripe openings, each of which tested a particular
geometry: a constant orientation with varying opening width (increasing dosage), or a constant opening
width with a varying orientation. The stripe openings themselves were 100 µm long and each array was
separated from one another by 1 µm of mask.
Openings aligned 30 and 60° off [1-10] were given special consideration as Julian et al had noted
coalescence morphology near those directions improved, depending on the V/III ratio used for growth
[19].
Five hundred nanometer-pitch stripes were initially tested but were later excluded in lieu of a greater
emphasis on stripe orientation. As will be discussed in more detail in Chapter 5, the 250 nm-pitch were
Figure 2: Typical EBL pattern used for this project. Angles in text
boxes are the orientation of the openings with respect to [1-10].
Geometries tested:
Pitch: 250, 500, 1000 nm
Orientation: [1-10], [110], and
orientations in between
Opening width: limited by dosage and
harder to control, ranged from 80-200 nm
Opening depth (mask thickness): 20, 80,
200 nm
55
superior for coalescence, while the 1000 nm-pitch allowed for a much easier study of stripe morphology
without neighboring stripes interfering with one another’s growth prematurely.
Surrounding each group of arrays was a 30 µm-wide square strip of open mask, serving as a sink for
excess precursors that might otherwise lead to possible deposition on the mask in between the patterns
[16]. The remaining features were used for alignment and for identification of the substrate orientation.
The openings in the 20 and 80 nm-thick PECVD nitride masks were patterned using reactive ion etching
(RIE) with polymethyl methylacrylate (PMMA) as an etch mask, but the resist proved too insensitive and
too easily damaged by the RIE to allow patterning anything much deeper. For 200 nm-deep openings, we
used a recently-invented resist by AllResist in Germany, CSAR 62. The CSAR 62 resist, although also
easily damaged by RIE, was sensitive enough to allow a thicker film to be spun that would survive long
enough to allow etching of 200 nm-deep openings as narrow as 100 nm wide. Furthermore, the write time
was decreased in half, from 10–14 hours for 13 samples to 5–7 hours.
For RIE etching, a flow rate of 45 sccm of CF
4
, at a chamber pressure of 50 mTorr and a microwave
power of 100 W was used. Although the etch rate of SiN
x
with CF
4
is rapid, it is a rather isotropic etch
which can lead to tapered sidewalls [76]. Arrays with openings that were too wide (approaching 200 nm
or so for a 250 nm pitch), leaving too thin a sidewall in between, were damaged as a result of this isotropy.
The other factor limiting patterning was exposure. Continuous openings narrower than 100 nm were
difficult to reproduce, as the resist routinely not achieve the dosage necessary to develop properly. The
end result of this underexposure were parallel lines of holes, as seen in Figure 4.a.
Overexposure was not an issue for wider pitches, but openings with a 250 nm pitch were affected. The so-
called proximity effect with EBL, where the electron beam exposure overlaps between neighboring
features, leads to an enhanced exposure [77]. Too much resist is removed, and the opening array is not
formed properly, as seen in Figure 4.b.
56
Figure 3: Top-down SEM of underexposed and overexposed/etch-damaged patterns. (a) If the EBL dosage is too low, the resist
will not be chemically altered enough, and the resulting openings will be segmented. (b) Too wide an opening relative to the
pitch combined with too isotropic an etch can lead to pattern damage. Even if the etch is anisotropic, if the features to be etched
are too close together, the electron beam exposure between these features will overlap and the pattern will be overexposed.
After development, the pattern will be damaged.
Overetching into the silicon was required to ensure the Si was exposed. Judging the required etch time for
the openings based on the bulk etch rate of the PECVD nitride was in general not possible, due to a
nonlinear variation in the etch rate [78]. Much like MOCVD, there is a selectivity to the etching and
depletion of the ions locally leads to a decrease in the etch rate on dense, deep, and narrow openings
relative to an isolated opening. Although not feasible for EBL samples, for later NIL patterns, we checked
the pattern cross-section after etching and before mask removal to ensure the SiN
x
had been removed. For
the EBL samples, the patterns were too small to easily cleave across. Therefore, the success of the SiN
x
removal was tested by using one sacrificial sample to ensure selective growth. The resist mask was left on
the rest of the batch to allow for continued etching if the first attempt did not completely remove the SiN
x
.
Only stripe growth and coalescence were tested with these EBL-patterned samples. After the nanostripes
grown out of the arrays are coalesced, the resulting pad would still likely experience some growth rate
enhancement due to their small size. This enhancement could result in different-than-expected
compositions for alloy growth and doping [79]. This could possibly be exploited in future work to test a
variety of alloy compositions on a single sample, but for the remainder of our project we focused on
larger-area NIL-defined patterns.
(a) (b)
57
4.2.2: NIL-defined Nanostripe Openings
For larger-area patterns much larger than 10,000 µm
2
, EBL would be too slow and too costly a technique,
and increasing the writefield size to prevent stitching errors may have led to worsening resolution. We
collaborated with Zerui Liu and Tse-Hsien Ou from Professor Wei Wu’s group to form large, 3.5×3.5 cm
arrays of 100 nm-wide, 250 nm-pitch stripe openings. Unlike EBL, only one orientation can be tested per
wafer. The orientations tested were [1-10]-aligned openings and openings oriented 60° off [1-10].
For the mask, thermal silicon dioxide and Si-rich LPCVD silicon nitride were used, the latter chosen for
its insensitivity to hydrofluoric acid (allowing a longer oxide strip time) and to prevent thermal strain
from cracking the films. With thermal oxide, the desired mask thickness was 200 nm, though it would
vary due to limitations with temperature control on the oxidation furnace. LPCVD nitride masks 300 nm-
thick were deposited by Yongkui Tang in Professor Eun Sok Kim’s group.
For etching, instead of PMMA or CSAR62, chromium was used as a hardmask. The process to define this
hardmask is shown in Figure 5 below:
58
Figure 4: Process to define chromium etch mask for dry-etching. Blue: Si, Green: dielectric mask. Red: resist, Gray: chromium.
After deposition of the dielectric mask (a), resist is spun onto the wafer (b), which is then patterned with
nanoimprint lithography and development (c). A layer of chromium 60 nm thick is then deposited onto
the surface (d), then the remaining resist with chromium on top is removed through lift off (e). Where the
resist was initially removed through NIL and development is where the chromium hardmask is now
(a)
(b)
(c)
(d)
(e)
59
present, defining the general width of the mask sidewalls for the nanostripe growth openings protected
during etching.
For etching, initially, the cleanroom’s Oxford inductively coupled plasma (ICP) etching tool was used,
leaving tapered sidewalls behind. Higher aspect ratios were not possible as the etch damaged the mask, as
seen in Figure 6.
Figure 6: Cross-sectional SEM of an ICP-etched thermal oxide mask, with an undercut into the Si to ensure the oxide was
removed. This geometry representative of what was used during the initial studies with NIL patterning, and the ICP, being more
isotropic than RIE, gave tapered sidewalls and a relatively low aspect ratio.
For the majority of the project, a combination of 30 sccm CHF
3
and 2 sccm O
2
were used in the
cleanroom’s Oxford RIE. The RIE could give a much more anisotropic etch, allowing for deeper
openings with a higher aspect ratio, and was in general a cleaner system. A representative cross section
patterned by RIE is shown in Figure 7.a. This particular batch had a pattern oriented 60°-off-[1-10], but
the pattern would be the same regardless of orientation.
SiO
2
Si
60
Figure 7: Representative NIL masks patterned by the RIE system. The masks here were 300 nm-thick LPCVD silicon nitride
overetched into the silicon substrate. The pattern orientation here is 60 degrees off [1-10], but these shapes are general
regardless of orientation. Both SEM images are taken before chromium hardmask removal. (a) With the RIE, the etch is far more
anisotropic, giving deeper, higher-aspect ratio openings. However, accompanying this was an increased level of residual RIE
passivation, as well as contamination from the chamber itself, so reproducibility of continuous and selective stripe growth
became more difficult. (b) Increasing the O
2
content in the etch leads to improved reproducible selective growth, at the cost of
sidewall geometry.
Reproducible, selective and continuous growth was found to be difficult with these high aspect ratio
openings with vertical sidewalls, however. Increasing the O
2
content in the etch from 2 to 8 sccm was
found to be necessary to ensure reproducibility. The resulting structure is the undercut sidewall seen in
Figure 7.b.
One especially difficult source of contamination to deal is passivation residues from the CHF
3
:O
2
etch
process itself. The F:C ratio of the etch gas mixture is an important consideration for etch rate, anisotropy,
and especially this passivation. CF
4
is a highly isotropic etch because little to no fluorocarbon passivation
is deposited on the sidewalls [76]. Meanwhile, CHF
3
has a lower F:C ratio and thus more fluorocarbon
residue is deposited, but this leads to a more anisotropic etch with a lower and more controllable etch rate,
important for forming deep, high aspect ratio openings. A dirty chamber could also artificially increase
the carbon content in the system, leading to a lower-than-desired F:C ratio, and thus, a greater amount of
fluoropolymer will form. This residue is hydrophobic and can affect the efficacy of subsequent wet-etch
treatments.
(a) (b)
61
The fluoropolymer could also outgas during growth, by interfering with precursor transport by creating a
pressure gradient inside the openings, as shown in the schematic in Figure 8.
Outgassing could also possibly interfere with precursor decomposition on the Si surface itself by leading
to contaminants occupying sites on the Si surface and not desorbing fast enough for a good surface
coverage of phosphorus [25]. The more sites that are occupied, the greater the tendency for precursor
migration and possibly desorption. Non-uniform contamination would then lead to non-uniform
nucleation, where adatoms would aggregate in cleaner regions in the openings. This behavior is shown in
Figure 9.
Since O
2
reduces the carbon content in the gas mixture by producing CO
2
, increasing the amount of O
2
during the etch suppresses the formation of this fluoropolymer in a more controllable manner than using
the highly isotropic CF
4
as the main etch.
62
Figure 8: Schematic of the possible mechanism behind the worsening nucleation density. (a) Mass transport to the Si surface is
only affected by the geometry of the pattern, and growth rate enhancements, as mentioned in Chapter 2, would lead to an
increased growth rate compared to a bare substrate [16]. Growth is dominated by mass transport and/or kinetics [25]. (b) If a
high vapor-pressure contaminant is present in the openings (shown in black), such as hydrocarbon residues from RIE, they can
outgas during growth, and locally, this would lead to higher-pressure pockets relative to the chamber (shown in gray) existing
inside the openings. Since precursor flux to the Si surface occurs through diffusion, this pressure gradient would lead to a
reduced growth rate and from nucleation, a less-dense layer. Further contamination on the Si surface could lead to an even
smaller effective growth rate by interfering with precursor decomposition.
Si substrate
SAG mask
Precursor transport at 76 Torr
Si substrate
SAG mask
Precursor transport at 76 Torr
Outgassing of
contaminants and
pressure gradient
Reduced
precursor flux
(a)
(b)
63
Figure 9: Parallel view of a stripe opening, showing a schematic of the possible effect of contaminants on nucleation density. (a)
Ignoring the effects of strain, precursors are transported to the Si surface (blue arrows), decompose and react, forming a
generally uniform and dense layer (orange). Strain would lead to more 3D growth, as mentioned in Chapter 2, but with proper
growth conditions, the nucleation layer would be continuous. (b) Contaminants (black), perhaps outgassed from the sidewalls,
occupy sites on the Si surface and prevent precursor decomposition there. Precursors then migrate to cleaner regions (if they do
not desorb first) and decompose there, resulting in more non-uniform growth, and in the case of nucleation, a less dense
nucleation layer. Resulting bulk growth will be non-uniform as well.
At one point, we considered using O
2
plasma cleans to remove the residue, and this did in the past help
recover selective growth after several failed batches, but in the end, this only led to a worsening of sample
contamination, or worse, redeposition from the chamber. Figure 10 shows a cross-section of similar
openings as Figure 6.a, using the same etch recipe, but with an hour of O
2
cleaning after the etch. The
openings have been filled in by some material, which must have come from RIE chamber.
Si substrate
Precursor transport at 76 Torr
Precursor transport at 76 Torr
Si substrate
Poor nucleation
density
High nucleation
density
(a)
(b)
64
Figure 10: 60-degree angled openings filled in by some contaminant. The openings should be deep and not tapered, like the
cross-section in Figure 5. This level of contamination led us to abandoning the O
2
clean, which did help occasionally in the past,
but is too risky a treatment to be worth it.
After etching, cross-sectional SEM is taken of the mask to ensure the mask has been removed and the Si
is exposed (judged from overetch into the Si). Once this is confirmed, the chromium hardmask is then
removed, and the openings are then etched in CF
4
for three minutes to help remove any lingering
passivation residue and, for the samples with the sidewall undercut, to remove the “overhang” of the mask
above the undercut.
If an InP buffer layer were to be used under the selective area growth mask, complications arise with the
trench patterning process. First, neither LPCVD silicon nitride nor dry-furnace thermal oxide can be
deposited or grown on the InP due to the material’s incompatibility with high, 800+ °C temperatures (the
phosphorus readily desorbs leaving an indium-rich layer which then melts). PECVD silicon dioxide or
silicon nitride, deposited at a 350 °C, would be needed.
Second, the chromium hardmask, while inert to the RIE etch chemistry (allowing high-aspect ratio
openings to be formed in the dielectric mask), is also inert to or only weakly attacked by most etchants
65
and requires a special cerium and perchloric acid-based solution to remove it [14]. The perchloric acid
unfortunately attacks InP and other compound semiconductors. The Loududoss group had investigated
NIL patterning of dielectric masks with an InP buffer layer between the mask and Si, but instead of Cr,
they used Al as the etch mask [9]. Aluminum is unfortunately attacked in by the fluorine chemistry of the
RIE etch, so thicker layers would have to be deposited, and the aspect ratio of the openings could be
limited [80]. The chamber would also be contaminated by the etched aluminum.
A solution, then, is to deliberately underetch the PECVD dielectric mask to leave behind a thin layer
above the InP, protecting it from the chromium etchant. The chromium etch mask is then removed, and
the batch is etched under RIE again. Because the mask thickness will be reduced, and because the etch
rates in the openings will be lower than for the bulk material, care must be taken to leave behind just
enough dielectric on the InP to be visible under SEM while also minimizing the thinning of the pattern
[78]. Too thin a residual layer may also result in patches of exposed InP, which would then lead to
significant pattern damage if there were enough of them. The recipe may be more sensitive to etch rate
variations with too thin a layer. Increasing the pattern thickness could compensate for this thinning as
well. A schematic of the altered patterning process is shown below in Figure 11.
Lastly, because the RIE does not etch InP as readily as Si, determining if the residual dielectric layer at
the bottom of the trenches has been fully removed via cross-sectional SEM may not be possible, and a
dummy growth run may be necessary, unless an etch chemistry is used that attacks the InP as well, such
as the inclusion of argon.
66
Figure 11: Adapted patterning process if an InP buffer layer is present under the dielectric SAG mask (in this case PECVD silicon
nitride). (a) Nanoimprint lithography, chrome deposition, and liftoff are performed as usual. (b) The silicon nitride is deliberately
underetched to leave a protective layer on top of the InP. (c) The chromium is removed without damaging the InP buffer layer.
(d) The SAG mask is etched further to expose the InP. Hatched green and white: Silicon nitride that was removed through this
second etch. The sidewalls will etch faster than the material at the bottom of the openings due to the microloading effect [78].
The material left behind at the bottom of the openings prior to the second etch must be optimized to reduce the amount of
thinning of the mask while ensuring the process is reproducible and uniform across the whole pattern.
(a)
(b)
(c)
(d)
67
4.3: Wet Cleaning
One of the most important considerations of sample preparation is maintaining sample cleanliness.
Contamination can severely hinder uniform nucleation by reducing the number of available sites on a
growth surface on which precursors decompose and adsorb [25]. A hydrophobic surface could lead to a
non-uniform removal of native oxide on the growth surface, also impacting nucleation. Finally,
contaminants can undesirably incorporate into a material, acting as unwanted dopants, form deep-level
states, or even lead to an increased defect density. To have a reliable, reproducible process that forms
quality material, cleaning processes must be included during sample preparation.
Because they oxidize when exposed to air, the Si and InP wafers need their native oxide stripped prior to
growth. In addition to a high temperature H
2
anneal, a wet etch is required. For InP, a one minute
treatment in dilute solution of 1:5 H
2
SO
4
:H
2
O was used instead, followed by a quick dip in DI and then
methanol [81]. This process is mentioned in the literature to leave the surface passivated with sulfur
atoms and is stable for hours. Piranha solution was used initially instead, but it was found to etch the InP
along with the oxide.
For Si, prior to even the deposition of the growth mask, the wafers are first cleaned in the SC-1 solution
of the RCA clean (5:1:1 H
2
O:NH
4
OH:H
2
O
2
at 70 °C for 10 minutes) to remove organic residue. After
mask patterning, the Si native oxide is stripped with 6:1 BOE. The BOE chosen contains a surfactant,
which our group has used for many years, as it helps improve the wetting of the BOE to the Si, especially
in small and deep openings [82]. For the thermal oxide mask, 3−15 seconds were used for the oxide strip,
while the LPCVD nitride could use longer times, as it was resistant to the etchant. For the thermal oxide
mask, this had the side effect of widening the openings to approximately 150 nm, and reducing the
thickness of the mask by approximately 25 nm.
Another issue that arose was the longevity of a batch and possible contamination during etching. Even if
the wafer was thoroughly cleaned and is covered with a mask promptly afterward, after etching, the Si
layer will be exposed. Small batches introduce more issues from variability with pattern etching, but
68
larger batches can result in samples sitting out too long and eventually becoming contaminated by
outgassing from the container they are stored in or even the air itself. The RIE itself can potentially
introduce contaminants as well.
It was for these reasons we included a second SC-1 clean after pattern etching, to improve batch longevity
and to improve the robustness of our process to variations in equipment cleanliness. Because the SC-1
treatment oxidizes the Si surface, a longer BOE etch was needed—one–two minutes was found to be
required—but only LPCVD nitride could survive such a long treatment [80]. Longer treatments lead to
delamination of the mask.
After wet treatments, the samples are promptly loaded into the reactor (within a minute or two) and kept
under hydrogen as the growth run begins. After about 15 minutes of reactor pump downs and carrier gas
flow increases, the reactor temperature was increased to 920 °C for a 5-minute hydrogen anneal.
69
Chapter 5: Selective Area Growth of Indium Phosphide Nanostripes
on Silicon Employing Thin Masking Layers
In this chapter, the initial growth conditions and pattern geometry for selective area growth of InP on
silicon through MOCVD is investigated. Patterns generated via e-beam lithography (EBL) and
nanoimprint lithography (NIL) are used, along with photolithography for the initial studies of low-
temperature nucleation. Owing to the flexibility in patterning, through EBL, stripe pitch (center-to-center
separation) and orientation (relative to the [1-10] direction) were varied simultaneously across the same
mask pattern. For pitch, 250, 500, and 1000 nm were employed. For orientation, [1-10], [110] and stripe
directions in 5 or 10° increments in between were patterned. The standard stripe width was 150 nm. With
NIL, we were limited to a single array orientation and pitch per sample batch, so EBL was used for the
initial studies to determine the optimal mask geometry. Preparation of these EBL and NIL patterns is
discussed in Chapter 4. Photolithography was performed with AZ 5214-E resist and a Karl Suss MJB3
mask aligner, defining multiple pairs of parallel openings 10 µm wide, 80 nm deep, with the stripes in
each pair separated by 5 µm of silicon nitride mask. The pairs themselves had a 95 µm pitch.
For the growth conditions explored, first, the temperature used for nucleation of InP is varied, showing
the need for initial growth at a lower temperature to form a continuous InP layer within the selective
openings. Anneals of the nucleation layer are performed with various conditions to explore how the
morphology changes at the higher temperatures used for stripe growth.
For stripe growth, the initial nucleation time and stripe growth temperature are varied to find the optimal
conditions to give the largest (100) top stripe surface while maintaining regular faceting of the stripes.
Mask geometry is altered to determine its effect on stripe morphology: stripe pitch (center-to-center
separation), stripe orientation (relative to the [1-10] direction), and opening depth are all adjusted.
Lateral epitaxial overgrowth and the subsequent coalescence are explored for various mask geometries,
with the optimal geometry applied to larger-area arrays (>1 mm
2
in area) patterned through NIL. These
large area coalesced films are characterized through SEM and AFM.
70
Surface irregularities in the form of trapezoidal crystallites embedded within the film, composed primarily
of (111) planes, are discovered in some coalesced films. These are attributed to twin propagation to the
surface. A means to suppress their formation is found through separating bulk growth of coalesced films
from the initial nucleation and coalescence growth run.
The typical growth conditions used for selective area heteroepitaxy on Si involve an elevated-temperature
heat treatment in hydrogen to remove residual native oxide and to form an antiphase-domain-free material
(detailed in Chapter 4), a low-temperature InP nucleation step, and stripe growth at a temperature around
600 °C. For stripe coalescence, the stripe growth step is prolonged beyond the typical 150-200 s to at least
300-500 s, where the stripes completely merge. Following coalescence, especially for our larger-area
nanoimprint pattern, the growth rate is doubled for the remainder of the run owing to the decrease in
growth rate enhancement from the decreasing masked area. Higher growth rates also allow a more
efficient use of phosphine, and, according to G Wang et. al., suppress thermal etching, where material
moves out of the way of defects reaching the surface to form small sub-micron wide pits [47]. This
process flow is shown in Table 1 below. Unless otherwise stated, these conditions are what were used for
stripe growth and coalescence.
Step
TMIn
partial
pressure
(mTorr)
TMIn
flow rate
(sccm)
PH
3
partial
pressure
(mTorr)
PH
3
flow
rate
(sccm)
V/III
ratio
Temperature
(°C)
Time (s)
Hydrogen
bake
0 0 0 0 N/A 920 300
InP nuc 1.82 40 3257 300 1786 400 75 –600
Temp
ramp*
0
1.82
0
40
3257 300
N/A
1786
400 –610 120
Stripe
growth†
8.21 180 1954 180 238 610 Varies
Bulk
growth††
8.21-
16.42
180-360 1954 180 119-238 610 Varies
Cooldown 0 0 1954 180 0 610 –300 200
Table 1: Initial standard growth conditions used for heteroepitaxy.
* Top: EBL-sample and original NIL growth condition, Bottom: optimized NIL-sample growth condition
† Standard stripe growth condition for selective area growth, 0.1818 nm/s without taking enhancement into account
†† Standard bulk film growth condition, the higher partial pressure of 16.42 mTorr, corresponding to a 0.3636 nm/s was used for
bulk growth on large-area patterns post-coalescence.
71
Later refinements to these conditions—such as nucleating first with GaAs, adding additional stripe
growth steps, or performing bulk growth in a separate regrowth run—are detailed throughout this
dissertation.
5.1: Low Temperature Nucleation Layer Formation
5.1.1: Temperature Dependence of Nucleation Layer Density
Owing to the large lattice and thermal mismatch between InP and Si (8% and 77%, respectively), InP will
nucleate in a three-dimensional growth mode, and numerous defects (above 10
9
cm
-2
) will form at the
interface [4,33,83]. Furthermore, owing to the difficulty for phosphorus to form a stable monolayer on the
Si surface (compared to arsenic), and the large migration of adatoms on the surface, relatively large
islands will form instead of a continuous layer [37,38]. When these large islands merge, even more
defects may be formed, such as stacking faults.
In Figure 1 direct, SEM micrographs of InP grown directly on (a) InP and (b) Si wafers at 660 °C for
800 s growth in 80 nm-deep, 10 µm-wide pairs of microstripe openings are shown. The standard TMIn
and PH
3
input conditions of 8.21/1954 mTorr (V/III ratio 238) were used. The InP growth density on Si is
dramatically lower, to the point where no continuous growth structure has formed.
To combat this sparse growth, an initial low temperature nucleation layer is often formed prior to bulk
film growth [4,83]. InP was grown at a low growth rate for 300 s at 600 °C, 550 °C, 450 °C, 400 °C, and
375 °C. The growth results are shown in Figure 2. Growth lower than 400 °C led to vapor-liquid-solid
(VLS) growth (Figure 2.e), where In began precipitating, and the absorption of phosphine created
nanowire-like features. The actual growth rate was approximately 0.5 nm/s. Selective growth on the
patterned wafer leads to a growth rate enhancement of more than 10x.
72
800 s of 660 °C InP growth, standard stripe growth rate
(a) Growth on InP (b) Growth on Si
Figure 1: SEM comparison of InP selective growth on InP and Si, with the same paired-microstripe mask pattern. The openings
are 10 µm-wide, separated by 5 µm, and the pairs of stripes separated by 70 µm. (a) Growth on InP in the [110]-direction. Note
the triangular ridges at the edge of the stripes from migration of adatoms away from the slow-growing (111)B sidewalls.
Growth is in general quite smooth and sidewalls are well-defined. (b) same growth conditions, but with a Si substrate. Growth is
discontinuous and chaotic.
As the temperature decreases, so does the migration and desorption of adatoms on the surface, and the
surface coverage increases [16,17,25,34]. The nucleation layer will become denser as the individual
islands become smaller in diameter. Similar results, where too high a growth temperature led to
discontinuous growth, were observed by Yamamoto et. al. [84].
To compensate for the low-decomposition rate of phosphine, a high input partial pressure of phosphine
relative to TMIn is used. If the V/III ratio is too low, indium precipitates will form, as the effective V/III
ratio at the surface would be even lower [25,84]. This may lead to vapor-liquid-solid (VLS) growth, as
observed in Figure 2.e.
In Figure 3, the 400 °C nucleation step is added to the stripe growth conditions used for the growth in
Figure 1, and the continuity dramatically improved.
73
300 s InP nucleation on Si at progressively lower temperatures
(a) 600 °C nucleation (b) 550 °C nucleation
(c) 450 °C nucleation (d) 400 °C nucleation—roughly 150 nm thick
(e) 375 °C nucleation
Figure 2: Temperature dependence of nucleation on Si within microstripe openings shown via SEM, showing the increase in layer
density and the decrease in island diameter as the temperature decreases. (a) and (b), 600 and 550 °C, growth is sparse and
consists of multi-micron-wide crystallites. (c) and (d) 450 and 400 °C, growth becomes dramatically more uniform, and the
average island size decreases greatly. At 400 °C, the layer is continuous, and the nuclei are approximately 20 –50 nm wide. (e)
decreasing the temperature by on 25 °C further results in VLS growth, the phosphine decomposition is too poor for effective
nucleation, despite the nuclei appearing even smaller.
74
800 s of stripe growth at 660 °C, with and without a nucleation layer
(a) No nucleation layer (b) With nucleation layer
Figure 3: Comparison under SEM of growth in microstripe openings on Si with and without the nucleation layer, showing a
dramatic improvement in growth continuity. The growth on the mask away from the stripes can be reduced by increasing the
pattern density on the surface, leaving less exposed mask available for this to occur.
5.1.2: Nucleation Layer Damage at Elevated Temperatures
Although growth density dramatically improves with the use of a low-temperature nucleation layer, the
grown InP still had deep pits in the surface, seen in Figure 4.
Figure 4: SEM closeup of one of the stripes in Figure 3.b. Although the stripe is mostly continuous, there are quite a few deep pits
in the surface.
75
To further improve stripe morphology, I noted that from the literature, annealing the nucleation layer at
the bulk growth temperature (around 600 °C) had been observed to planarize the layer through mass
transport of the grown material, leading to smoother overall bulk growth [83,84]. This mass transport
technique, where the InP is controllably decomposed, allowing surface adatoms to redistribute into a more
energetically favorable positions, has been used in early studies with MOCVD and LPE (liquid phase
epitaxy) of InP to smooth out sharp corners in trenches and fill in gaps between adjacent growth
structures, used in fabrication of buried heterostructures [85,86,87]. In earlier work from our own group,
thermal anneals of regrowth structures successfully planarized them, reducing the prominence of humps
and valleys near the structures [18].
However, all these anneals did for our samples was damage the InP nucleation layer, with worsening
damage the lower the phosphine overpressure was or the higher the temperature. Material redistributed
too strongly, especially when the migration of adatoms is made easier (lower phosphine
overpressure/higher temperature), and instead of the nucleation layer planarizing, it instead forms large
clumps/crystallites. Thinner layers are more strongly damaged. InP was also found to be redeposited on
the mask owing to desorption of material from the nucleation layer.
The decomposition occurs from the breaking of the In-P bond and desorption of phosphorus, which is
thus affected by the anneal’s temperature, which planes are exposed (as that affects the number of bonds a
particular P or In atom is held to the surface with), and the overpressure of phosphine [44,88].
From here on, the phosphine flow rate was held at 300 sccm until high-temperature stripe growth began.
In the next section, various growth conditions were tested, and from them, it was clear that the nucleation
layer/initial layers of bulk InP could be damaged even during the main stripe growth step. However, the
damage was not to the extent as an anneal, as would be expected: with TMIn flowing, there was a net
adsorption of new material on top the nucleation layer instead of solely desorption and redeposition of
pre-existing material.
76
5.2: Investigations of Nanostripe Growth Conditions and Mask Geometry
through EBL
After the initial nucleation studies, we employed EBL to create the masks for selective growth, allow us
to determine the effect of mask geometry on growth morphology all on one sample. Our studies varied
stripe growth temperature, nucleation layer thickness, and opening depth (mask thickness) to determine
the optimum geometry and growth conditions for nanostripe growth. Our initial mask was 20 nm-thick
PECVD silicon nitride, so the aspect ratio was below 1.
5.2.1: Temperature Variation of Nanostripe Growth on Si
(a) Temperature Dependence of stripe morphology. 100 nm-wide openings, 500 nm-wide pitch
560 °C 610 °C 660 °C 710 °C
[110]
[1-10]
(b) Temperature dependence of stripe morphology. 100 nm-wide openings, 250 nm-wide pitch
560 °C 610 °C 660 °C 710 °C
[110]
[1-10]
Figure 5: Variation in stripe growth morphology with growth temperature and orientation shown via SEM. (a) 500 nm pitch,
(b) 250 nm pitch.
77
In Figure 5, the stripe growth temperature is varied from 560–710 °C. On each of the four samples, the
morphology of InP grown in stripe openings 100 nm-wide with a 250 nm and 500 nm pitch, aligned with
the [110] and [1-10] directions is investigated.
Figure 5.a shows the results of stripe growth in 100 nm-wide openings with a 500 nm pitch at a varying
growth temperature. For all samples, 75 seconds of 400 °C nucleation was used. Following this, the
stripes were grown for 200 seconds, save for the sample at 560 °C, which used 100 seconds to suppress
overgrowth.
Growth at 610 °C gave the largest (100) surface for individual stripes, roughly over 90% of the scanned
area in the SEM micrograph. This (100) surface vital for the formation of a smooth surface post-
coalescence. In fact the stripes had already begin to coalesce for [1-10]-oriented stripes due to the fast
lateral growth rate of the (111)A sidewall.
Higher growth temperatures damage the nucleation layer more easily. The [110] direction led to
discontinuous growth occurring at a lower temperature than the [1-10] direction, agreeing with Asai’s
observation that the [110] step edges decompose more easily owing to fewer bonds holding the V-atoms
in place at the step edge in that direction [44]. Furthermore, more chaotic growth occurs as adatom
mobility between planes enhances the growth rate differences between them, and any irregularities from
defects or strain in the stripe profile may be exaggerated. This is seen even for the [1-10]-oriented stripes
grown at 660 °C. Too low a temperature, on the other hand (560 °C) seems to not give the adatoms
enough mobility to for the stripes to form faceted sidewalls [89]. Additionally, the (100) top surface is not
as well-formed.
In Figure 5.b, the stripes have already begun or have even completed their coalescence, owing to the
narrower 250 nm pitch and thus a shorter distance needed for coalescence. Only the stripes along the
[1−10] direction grown at 610 °C coalesced with minimal void formation. At 560 °C, the growth time
was shorter so the voids would likely fill in, but owing to the rougher (100) surface, the coalesced film
78
quality would be poorer. At 660 °C, the (100) surface is not prominent owing to enhanced mobility (with
stripes more easily forming a triangular cross-section), and coalescence was chaotic. This chaotic
coalescence extends to 710 °C. Although the 610 °C coalesced film lacked noticeable voids, owing to the
very low aspect ratio of 0.2, aspect ratio trapping of dislocations would not occur here and the defect
density would be high. If the fill factor of the trenches underneath the opening reduced the film’s defect
density by reducing the contact area of the InP on Si, the defect density would only be reduced by 60%
from the bulk >10
9
cm
-2
. A thicker mask would be needed.
5.2.2: Increasing the Thickness of the Nucleation Layer
The nucleation time was increased to 150 s help protect the layer upon heating. In Figure 6.a, it can be
clearly seen that the stripes oriented in the [110] direction show more continuous and regular growth than
the stripes which were initially nucleated on the Si surface for only 75 s. From our earlier findings with
nucleation layer anneals, a nucleation layer is much more easily damaged if it is too thin. Despite the
growth rate enhancement that occurs during selective growth, a thicker layer is still required. The stripes
still have numerous height and width variations. Furthermore, as seen in Figure 6.b, multiple triangular
notches can be observed intersecting the stripes at an angle, undoubtedly lying on (111) planes. Surface
TEM or some other characterization technique with a good-enough resolution would be needed to
determine their nature and see whether or not they are evidence of defect propagation out of the selective
openings.
Based on these observations described above, nucleation layer growth for 150 s was used for all
subsequent growth studies using thin masks and EBL.
79
(a) Increasing nucleation time, 660 °C, 200 s stripe growth
75 s 150 s
[110]
[1-10]
Figure 6: (a) Result of increasing the nucleation time shown via SEM. Stripe growth continuity has greatly improved. (b) Detail of
the bottom right image in (a), where multiple triangular notches (examples of which are circled) can be seen intersecting the
stripes at an angle. These appear to lie on (111) planes and may be from planar defects.
(b)
80
5.2.3: The Role of Opening Depth on Nanostripe Morphology
Increasing the mask thickness to at least above 160 nm is vital for ensuring aspect ratio trapping occurs
for 100 nm-wide openings. If the aspect ratio is less than 1.43 (tan(54.7°), as the (111) plane on which
most defects lie is ~54.7° off the (100) surface), dislocations generated at the InP-Si interface will not be
effectively trapped. For stacking faults, this rises to 1.6, and the required value becomes even larger if the
orientation is off one of the <110> directions [66]. Beyond defect filtering, increasing the mask thickness
also improves the quality of the stripes that emerge from the openings, as shown in Figures 7 and 8 below.
Increasing the opening depth from 20 to 60 nm had a negligible effect on stripe morphology, and the
notches (possibly planar defects) are still ubiquitous.
EBL-patterned PECVD nitride mask, 500 nm pitch, thickness variation, 660 °C, 200 s growth
20 nm-thick mask, “5155” 60 nm-thick mask, “5158-2”
[110]
[1-10]
Figure 7: Top-down SEM of nanostripes grown in 100 nm wide openings 20 and 60 nm deep with a 500 nm pitch. There is not
much difference in the stripe morphology. For stripes along the [1-10] direction, the (100) surface is not present.
81
EBL-patterned PECVD nitride mask, 1-µm pitch, thickness variation, 660 °C, 200 s growth
60 nm thick mask, “5158-2” 200 nm thick mask, “5195-2”
[110]
[1-10]
Figure 8: Dependence of stripe morphology on opening depth shown via SEM. The pitch has been increased to 1 µm to isolate
the stripes from one another. At a 60 nm opening depth/mask thickness, the stripes have emerged in a nonuniform fashion, with
some height variations, but more notably, a continued lack of a (100) surface, even for the [1-10] direction. Increasing the depth
to 200 nm results in far more uniform, trapezoidal cross-section stripes forming, with (111)-dominant sidewalls and a consistent
width. The (100) surface is also more prominent as well, at least for the stripes grown in the [1-10] direction.
Merckling et. al. note that, if the nucleation density was initially poor, the nuclei/islands will be delayed
in their merger into a continuous layer, and growth will persist in a three-dimensional mode [39]. If the
openings are too shallow, this will likely occur even if the nucleation density was high, as not enough
growth would have taken place to transition to a two-dimensional mode to begin with. This is well-
demonstrated by the nanostripes in Figure 8—the stripes grown in 60 nm-deep openings did not have
enough time to transition to a two-dimensional growth mode before emerging from the opening.
Although stripe morphology has improved moving to a 200 nm opening depth, notches can still be seen
periodically. They are, however far fewer in number than for the 20 and 60 nm-deep openings, one or
82
fewer per micron, rather than one or more per 100 nm. Using deeper openings may allow stacking faults
to annihilate by giving them a greater length to propagate and potentially cross paths.
In Figure 9, I compare the effect of growth temperature again, now with the thicker mask. As expected,
the stripes grown at 610 °C for sample 5198 show a much more prominent (100) top surface, but the
sidewall is also not as well-defined. As discussed earlier in this chapter, enhanced migration improves the
faceting of stripe growth, but at the expense of the (100) surface [17,89].
EBL-patterned PECVD nitride mask, 1-µm pitch, 200 nm-depth, temperature variation
660 °C, 200 s, “5195-2” 610 °C, 200 s “5198”
[110]
[1-10]
Figure 9: SEM of nanostripes separated by 1 µm grown for 200 s at different temperatures. The [1-10]-aligned stripes have a
larger (100) top surface, which is vital for coalescence. Meanwhile, reducing the stripe temperature to 610 °C has improved
overgrowth and has increased the size of the (100) top surface, but at the expense of the faceting quality of the sidewall.
Although there would be fewer height variations after coalescence or fewer gaps owing to the superior overgrowth at this lower
temperature, the rougher sidewall may lead to more defects forming.
83
5.2.4: Variation of Mask Pitch
The one-micron pitch allowed us to study the morphologies of individual stripes without having them
coalesce, however, coalescence is more uniform and tends to form fewer defects (at least in theory) with
narrower pitches, according to Julian et. al. [19]. Our group had also found that narrower pitches
improved the continuity of coalesced films of GaAs nanostripes on (100) Si [20].
On every EBL-patterned sample, nanostripe opening arrays with a 250 nm-pitch were included in order to
test coalescence. In Figures 10 and 11, I compare the effect of pitch on stripe morphology for stripes
grown at 660 and 610 °C, respectively, out of 200 nm deep openings. These arrays were from the same
samples studied in Figure 10, numbered 5195-2 and 5198. The stripes grown in the narrower-pitch array
tended to have a poorer morphology than those grown in the wider pitch array for the same growth time.
Two important considerations are 1) the fill factor of the pattern is four times larger for the 250 nm-pitch
arrays, increasing the available volume for InP to be grown in, and 2) the selective growth rate
enhancement is also lower. All SEM images in Figures 10 and 11 were taken at the same magnification,
and it is clear that the 1 µm-pitch nanostripes are far wider than the 250 nm-pitch stripes—they’re at a
later stage of growth.
84
EBL-patterned PECVD nitride mask, pitch variation, 660 °C, 200 s growth
1 µm pitch 250 nm pitch
[110]
[1-10]
Figure 10: Top-down SEM of stripes grown at 660 °C out of 100 nm-wide openings 200 nm deep with a 1 µm and 250 nm pitch.
Although the stripe shape is maintained at the narrower pitch for [110]-aligned stripes, the [1-10]-aligned stripes have begun
coalescing —and not simultaneously along the stripe length. This may lead to height variations or defect formation.
85
EBL-patterned PECVD nitride mask, pitch variation, 610 °C, 200 s growth
1 µm pitch 250 nm pitch
[110]
[1-10]
Figure 11: SEM of nanostripes grown for 200 s at 610 °C, in 100 nm-wide openings 200 nm deep. At 610 °C, stripe formation in
narrower-pitch openings is more regular compared to Figure 10, and chaotic coalescence for stripes along the [1-10] is
suppressed to some extent. However, height variations in the stripes are still present —not enough growth occurred for
individual stripes to let them transition to a 2D growth mode before they began coalescing, let alone leaving the opening, unlike
the stripes grown in openings with a 1 µm pitch.
Owing to their faster lateral overgrowth, the [1-10]-oriented nanostripes had already begun to coalesce as
well, but not in a uniform manner. Although Julian et. al. and Chi and found that narrower pitches gave
superior coalescence owing to less interaction of the overgrown material with the mask and the smaller
area of the sidewall, if the initial nucleation was poor, the stripes will not have enough time to transition
to a 2D growth mode before they coalesce, let alone before the material breaches the opening and begins
to overgrow the mask [19,20,39]. Growth at lower temperatures helps suppress this chaotic coalescence to
some extent by reducing height variations from adatom migration off the sidewalls to the (100) top
surface.
86
5.3: NIL Nanostripe Growth: Large Area SAG
With the large-area nanoimprint pattern, 150 nm-wide openings post-BOE treatment, and the 250 nm
pitch, about 50–70% of a sample’s surface was exposed semiconductor, and the growth rate enhancement
would be lower than that of the EBL nanostripe arrays [16,17]. The nucleation layer would be thinner for
the same 150 s growth condition used previously and thus be more easily damaged. As a result, to
compensate for the reduced growth rate, the growth times are increased to achieve comparable growth
thicknesses as were used when sparser stripe patterns are used. However, as seen in Figure 12, the InP
was still somewhat discontinuous even after the increase in the nucleation time. This suggests that the
nucleation layer was still likely being damaged. To compensate further for the decreased growth rate
enhancement, and to conserve phosphine, rather than further increase the nucleation time, the 40 sccm
TMIn flow was kept on during the 120 s temperature ramp to 610 °C. In Figure 13, stripe growth was
lengthened in duration to 150 s, and without this TMIn flow, the stripes were still discontinuous, with an
average segment length of 500–700 nm. With the additional TMIn flow, however, the stripes became
continuous, save for a rare void. The morphology was not as ideal as would be desired at this point, but as
will be shown in section 5.4, they were sufficient for coalescence.
Increased nucleation time, 50 s stripe growth at standard growth rate
150 s nucleation 300 s nucleation
Figure 12: Top-down SEM of InP grown in NIL stripe openings, showing the improvement in growth continuity with increasing
nucleation time.
Stripe
Mask
87
Effect of continuing TMIn flow during temperature ramp, 610 °C, 300 s nucleation,
150 s growth at standard growth rate
(a) Without TMIn flowing during ramp (b) With TMIn flowing during ramp
Figure 13: Top down SEM showing further improvement in stripe continuity by maintaining TMIn flow during the temperature
ramp between the 400 °C nucleation and 610 °C stripe growth.
5.4: Coalescence and Regrowth
5.4.1: Coalescence with EBL Nanostripes
Coalescence was first studied with EBL openings 80 nm deep, where multiple mask geometries could be
investigated owing to the flexibility of the patterning technique. After 150 s of nucleation, standard stripe
growth was prolonged to 900 s to coalescence the stripes. In Figure 14, the effect of opening pitch,
orientation, and growth temperature on coalescence morphololgy are demonstrated. As expected from
earlier results, stripes grown at 610 °C along the [1-10] direction with a 250 nm-pitch gave the smoothest
films, as judged by SEM examination.
Even for stripes oriented along the [1-10]-direction, coalescence at 660 °C, meanwhile, leads to void
formation in the film. This is likely in part caused by a more poorly-defined (100) surface for stripes
grown at that temperature.
88
(a) Coalescence, 660 °C, 900 s
1 µm pitch 500 nm pitch 250 nm pitch
[110]
[1-10]
(b) Coalescence, 610 °C, 900 s
1 µm pitch 500 nm pitch 250 nm pitch
[110]
[1-10]
Figure 14: SEM of coalescence as a function of temperature, pitch, and orientation for stripes grown at (a) 660 °C and (b) 610 °C
within openings in an EBL-patterned mask. As the pitch is decreased, the stripes merge more uniformly, with fewer voids or
height variations forming. Agreeing with Figures 5, 9, and 11, stripes grown along the [1-10] direction at a lower temperature
form the smoothest film.
89
5.4.2: Coalescence with NIL Nanostripes
The 610 °C growth condition used for EBL was adapted for coalescence of nanostripes grown out of
large-area NIL-patterned arrays. With the reduced mask area, selectivity would be easier to control during
initial stripe growth, and after coalescence, the mask is covered, leaving behind a large-area film.
Compositional control of alloy layers grown on top of the InP post-coalescence would also be simpler
owing to the lack of selective effects.
Because growth rate enhancement would vanish after coalescence for these NIL samples, I doubled the
growth rate to approximately 0.3636 nm/s. Too low a film growth rate had been found by G Wang et. al.
to lead to the development of pits in the surface of the films, through a process known as “thermal etching”
[47]. In this process, film material redistributes away from defects to lower the surface energy, forming
pits or similar features. If the growth rate is reduced, adatoms on the surface will migrate a greater
distance before newly-arriving adatoms bond to them and arrest their migration. Increasing the growth
temperature would have a similar effect owing to the increased adatom mobility. This development of pits
is observed in Figure 15. A coalesced film approximately 400 nm thick was grown at 610 °C and
appeared relatively smooth, aside for superficial streaking and surface rippling. However, when the final
150 s of bulk film growth was performed at 660 °C, the streaks became more pronounced, indicating
stronger thermal damage.
90
Coalesced NIL nanostripe film morphology dependence on growth temperature of film alone
610 °C, 300 s post-coalescence film growth 610 °C 150 s followed by 660 °C 150 s film growth
Figure 15: SEM micrographs of two coalesced NIL nanostripe films. Both were grown to approximately a 400 nm thickness, but
one (right) had the final 150 s of post-coalescence film growth (out of a total 300 s) occur at 660 °C. Although present
superficially for the all-610 °C-film growth sample (left), parallel streaks were observed in the 660 °C sample, evidence of
thermal etching and possibly the presence of defects.
In Figures 16 and 17, I show the effect of increasing growth thickness on surface quality and RMS
roughness, as judged via SEM, OM, and AFM. There was an initial 200 nm of growth (the stripes
coalesced into a film together after 300 s of growth-rate-enhanced stripe growth and lateral overgrowth),
followed by 200, 400, and 800 nm of bulk film growth at the doubled growth rate.
Increasing the coalesced film thickness from 400 to 600 nm did not affect the surface morphology too
strongly, with the RMS roughness essentially unchanged. Increasing the film thickness further to
1000 nm, however, leads to a reduction in RMS roughness to 17.9 nm.
91
NIL coalescence 610 °C, varying film thickness
400 nm thick
600 nm thick
1000 nm thick
Figure 16: Top down SEM (left) and 100x OM (right) of coalesced films of increasing thickness. Note the streaks in the SEM
images, which are never closer than 250 nm, and the hillocks in the OM (harder to see under SEM).
92
AFM of films in Figure 16
400 nm thick
600 nm thick
1000 nm thick
Figure 17: AFM scan and data for the three films in Figure 20, showing an eventual improvement in roughness at an 800 nm film
thickness. The AFM scan parameters are: Sq, RMS roughness; Ssk, skewness; Sku, kurtosis; Sp, max peak height measured with
respect to average height on surface; Sv, min peak height with respect to average height; Sz, roughly the difference between Sp
and Sv; Sa, average roughness; and Sdar, area of scan.
93
The films have a rough, rippled surface of hillocks roughly 2–5 µm across and at most roughly 100 nm
tall. These are most likely formed by the initial height variations of the stripes resulting in a spatial
variation of the coalescence across the sample. These height variations, as observed in Figure 13.b, are
themselves the result of a non-uniform nucleation density and growth in a 3D mode from the lattice
mismatch between InP and Si [39]. There is no correspondence between hillock location and stripe
orientation.
However, as shown in Figures 15, 16, and 17, parallel streaks along the [1-10]-direction are present on the
surface of the films, and are never spaced closer than the stripe pitch apart. Some streaks are possibly
formed from portions of the stripes where coalescence was delayed, forming a pit in the coalesced film.
Since (111)B surfaces would likely form and overgrow slowly, coalescence would still occur mostly
laterally along the [1-10] direction through (111)A planes. Incomplete coalescence was observed for
wider-pitch arrays in Figure 14.
These streaks may also be evidence that coalescence-related defects have formed. Yan et. al. note that a
mismatch in the number of lattice points between two growth fronts converging between two points
(which bound a void) will lead to dislocation formation when the void is filled in [58]. This “two-zipper”
mode is more likely to occur for stripes with a large sidewall area or ones with many height variations.
The more preferable “one-zipper” mode, where coalescence occurs at a single point, does not form extra
defects, and is more likely when the sidewall area is minimized. Julian et. al. note this occurs for stripes
with an orientation closer to 60°-off-[110], with a high V/III ratio [4,19]. Beyond improving coalescence
through optimizing the stripe direction, to reduce this streaking and the surface roughness, nucleation
would need to be improved. This would perhaps be achieved through the initial growth of a layer that
improves the initial P adsorption, such as GaAs as suggested by Wang et. al. [47]. Increasing trench depth
even further could also help counteract the effects of poor nucleation, as demonstrated in Figure 8 [39].
94
5.4.3: Regrowth and Twin-like Crystallite Defect Formation and Suppression
A complication with the growth of these coalesced films was the appearance of bulk, twin-like defects
embedded in the films after extended growth periods. As shown in Figure 18, they take on a trapezoidal
appearance and are aligned with one of the <110> directions, dependent on the orientation of the openings.
In Figure 18.b, two coalesced EBL arrays, the crystallites switch orientation when the (111) slip plane
that the unblocked planar defects would lie on (line of sight out of the openings) switches. For openings
nearer to the [1-10] direction, (111)B-lying planar defects are unblocked, while for openings nearer to the
[110] direction, (111)A-lying planar defects are unblocked. In Figure 18.c, a schematic of their proposed
formation is shown. Stacking faults or microtwins, perhaps related to the notches seen in Figures 6-8,
escape the openings and form into these crystallites if given enough time to grow. In Figure 18.a, splitting
the run in two, with the initial nucleation and stripe growth separated from the majority of the bulk
growth, seems to arrest either the propagation of these planar defects or prevents them from becoming
enlarged defects that break up the film. When growth is segmented into multiple runs, the layer cools to
ambient temperature and is then reheated during the next run, possibly acting as somewhat of a weak
“thermal cycling” or anneal of the layer, which has been used in the past to suppress defect propagation
[51,52].
This growth segmentation is not perfect, and the crystallites were also observed to appear more often
when the initial Si surface was contaminated, which would worsen nucleation density and thus increase
the chance for defect formation at the surface [37,38,39,47]. In Figure 18.b, crystallites still formed over
the entire surface of the coalesced films with EBL samples, even with splitting the run into multiple steps,
but the particular batch was not as clean as the NIL samples. Because stacking faults and microtwins are
generated by the dissociation of dislocations, poor coalescence may increase the chance for crystallite
formation as well.
95
(a) 610 °C NIL coalescence, 1400 nm of film growth, 100x OM
Growth separated into two runs: 600 s then
2700 s of bulk film growth
Single, prolonged run with 3300 s of bulk film
growth
(b) Crystallite formation on coalesced EBL stripe array, 250 nm-pitch, 610 °C
(representative of entire coalesced EBL array)
30° off [1-10] 60° off [1-10]
(c) Schematic of crystallite and originating, unhindered, [1-10]-propagating stacking fault (SF)
Figure 18: Overview of (a) crystallite formation hindered and unhindered by splitting the growth run in two (NIL samples), (b)
the dependence of crystallite orientation on stripe direction (EBL samples), and (c) the geometry of the crystallites, with the red
plane the (111) slip plane a planar defect such as a stacking fault or microtwin may lie on. Note the same notched appearance of
the crystallite as what was observed in stripes earlier in this chapter in Figures 6-8.
Stripe ornt
[1-10]
[110]
30° 60°
[1-10]
[110]
Stripe ornt
Crystallite ornt Crystallite ornt
10 µm
[110]
[1-10]
96
From this point onwards, bulk growth was separated into multiple runs to suppress this crystallite
formation, which could impact device growth by creating a large short in a junction or interfering with
contact deposition on the top surface. These crystallites are an example of the challenges faced with
reproducibility of growth morphology, which is addressed in the next chapter, where growth conditions
and sample geometry are optimized to ensure it.
5.5: Initial Conclusions for SAG and Coalescence
Initial variations of growth conditions and sample geometry revealed to us a good starting point for
coalescence. Low temperature nucleation is vital for the formation of continuous nanostripes. Growth of
the nanostripes at 610 °C was found to give the best compromise between (100) top surface formation and
sidewall crystallinity. Too low a temperature and the stripes are not well-faceted, but too high a
temperature and the stripes become discontinuous from nucleation layer thermal damage. As expected,
[1-10]-aligned nanostripes possess a larger (100) surface than [110]-aligned ones. Increasing the opening
depth from below 100 nm to 200 nm greatly improved the morphology of the stripe sidewalls, with fewer
breaks in the sidewall morphology observed.
For coalescence, the shorter the pitch, the more uniform coalescence will be across the nanostripe array
and fewer voids of delayed coalescence will form. Too high a temperature will also lead to non-uniform
coalescence. [1-10]-aligned nanostripes, owing to their faster lateral growth rate, merge much better than
[110]-oriented nanostripes.
With NIL, large-area coalesced films were achieved, in some instances with RMS roughnesses lower than
20 nm. However, along <110> directions, streaks and occasionally trapezoidal, twin-like crystallites were
observed in the films. Though possibly evidence of defect propagation to the surface, the streaks were
small, <1 µm long and <100 nm wide. The crystallites, on the other hand, were several microns long and
were comprised mostly of (111) planes. Halting bulk film growth, allowing the samples to cool, and
resuming growth in a separate run was found to suppress their formation. Further refinements to film
morphology were needed, including further optimizing opening orientation and nucleation. The defect
97
densities of these films and the nature of those defects—whether they are primarily from poor aspect ratio
trapping or from coalescence—will be determined through TEM and EBIC in the next chapter.
98
Chapter 6: Optimization and Characterization of Coalesced
Nanostripe Morphology Compared to Thin Films Grown on Si
Although coalescence of nanostripes into a continuous film was achieved, the surface remained rather
rough, with height variations greater than 100 nm observed, despite a <20 nm RMS roughness. The
morphology outlined in Chapter 5 also proved challenging to reproduce beyond this. The crystallite
defects embedded in the surface of the films, although suppressed by splitting the growth into several runs,
would still appear if the nucleation was poor. Initial stripe morphology would also suffer, with more
height variations appearing and even a loss of stripe continuity.
In this chapter, methods to both optimize coalesced film morphology and to ensure reproducibility are
explored. Further improvements to the nucleation layer’s density beyond simple increases in the
nucleation time (as judged by improvements to stripe morphology) and making the layer more robust
against processing variations (such as contamination from RIE) is detailed and briefly compared to what
has been achieved elsewhere.
Then, additional alterations to the mask geometry are all compared with AFM and TEM, notably
changing the stripe opening orientation to improve coalescence and investigating if adjusting the pitch
and mask thickness, by affecting the thermal strain encountered by the InP, impacts defect generation
from coalescence. The use of an InP buffer layer under both EBL and NIL-patterned masks is studied as a
means to further improve coalescence morphology.
Finally, EBIC is used to determine the nature of surface defects observed in coalesced and bulk films
grown on Si.
6.1: Nucleation Optimization
One of the first changes to improve nucleation reproducibility was to shift to a LPCVD silicon nitride
mask that was resistance to the BOE used for the pre-growth oxide strip. Longer etch times could then be
used, allowing more time for the acid to penetrate deeper, higher-aspect ratio openings without damaging
99
the mask. Furthermore, the samples could now be cleaned with the RCA treatment before growth,
improving the longevity of prepared samples. The treatment forms a thin oxide layer on silicon, but with
an inert mask, whatever oxide is present can be safely removed [80].
The mask depth was then increased to 300 nm, allowing higher-aspect ratio openings to be formed.
6.1.1: Pre-nucleation Surface Preparation with Hydride Anneals
To improve nucleation density and its reproducibility, pre-nucleation exposures of the Si surface with
flows of phosphine and arsine immediately after the 920 °C hydrogen anneal were tested. These exposure
conditions are given in Figure 1.
Figure 1: Post-hydrogen bake hydride anneal conditions. After the five-minute bake at 920 °C, 100 sccm of phosphine or arsine is
introduced. The chamber temperature is maintained for an additional 60 s, then ramped down to 400 °C for eventual nucleation.
The hydride source is maintained once that temperature is reached until nucleation begins or if a higher flow rate needs to be
used for nucleation.
0 200 400 600 800 1000 1200
0
200
400
600
800
1000
Temperature ( C)
0 200 400 600 800 1000 1200
0
20
40
60
80
100
Hydride flow rate (sccm)
100
G Wang et al noted that annealing with a TBAs or arsine ambient leads to the formation of a stable As
monolayer on the Si surface, unlike TBP or phosphine, which does not leave a stable P monolayer [49].
Without a stable V-monolayer, InP nucleation density will be poorer. Likewise, Kohama et al report
improved GaP film quality grown on Si with an arsine pre-exposure [37,38]. As mentioned previously in
this dissertation, P does not easily form a stable monolayer on Si. Phosphine decompose far less readily
than arsine [25]. Additionally, the P-P bond strength is much stronger than the P-Si bond strength relative
to As-As over As-Si [35,36]. As such, phosphorus may more readily desorb from the surface as dimers
than will arsenic.
NIL Nanostripe growth with different nucleation conditions, 500 s, 610 °C, V/III 238
(a) 5285-2, phosphine anneal (b) 5287, arsine anneal
(c) 5288, no hydride anneal, 600 s
nucleation
(d) 5289, phosphine anneal, 300 s
nucleation
Figure 2: Effect of different anneal conditions on stripe growth continuity. (a) 60 s of phosphine at 920 °C, (b) 60 s of arsine at
the same temperature, (c) no hydride anneal, (d) 60 s phosphine anneal followed by shortened InP nucleation.
101
However, as shown in Figure 2, little to no difference was observed in the InP nucleation density with
pre-exposure in phosphine (with 2.a and without phosphine 2.c). Furthermore, the arsine anneal actually
worsened the nucleation quality, leading to discontinuous stripes (2.b).
In 2.d, halving the nucleation time was found to also lead to worsening nucleation, with occasional stripe
discontinuities appearing that aren’t present in 2.a, confirming the need for a prolonged nucleation step as
addressed in Chapter 5.
6.1.2: Protection of Nucleation Layer from Thermal Damage with Intermediate-Temperature
Layer Growth
Some improvement to reproducibility with stripe continuity was achieved by forming an intermediate-
temperature layer on top of the nucleation layer, then continuing with standard stripe growth.
As explored with the nucleation layer anneal and initial stripe growth temperature variation studies in
Chapter 5, the nucleation layer can be easily damaged when exposed to elevated temperatures, with
enhanced P desorption and In migration causing the layer to coarsen. In Figures 3 and 4, AFM and SEM
of three coalesced films with the initial stripe growth temperature conditions varied are shown. 500 s of
stripe growth was used to allow the stripes to begin to emerge from the openings, but not coalesce. After
these varied stripe growth temperatures, an additional 500 s of stripe growth at 610 °C occurred to
coalesce the stripes, followed by 1200 s of bulk film growth at 0.3636 nm/s.
These varied stripe growth conditions were: (a) 500 s of stripe growth at 610 °C, (b) 500 s of growth at
560 °C, and (c) 250 s of growth at 560 °C followed by another 250 s of growth at 610 °C. There is
marginal improvement in the coalesced film roughness when the stripe growth occurs at two temperatures.
However, the film is significantly roughened, indicating poor initial stripe quality, when all of the initial
500 s of stripe growth occurs at 560 °C. This is despite coalescence and film growth occurring at the ideal
610 °C later. Although desorption of the nucleation layer is less likely at lower temperatures, stripe
crystallinity suffers due to suppressed adatom surface migration, agreeing with the findings in Chapter 5
[16,17,89].
102
Effect of initial stripe growth temperature on coalesced film quality
610 °C
560 °C
560 and 610 °C
Figure 3: AFM of three coalesced films with different stripe growth temperature conditions: (top) stripes grown completely at
610 °C, (middle) stripes grown completely at 560 °C, and (bottom) stripes grown initially at 560 °C, then at 610 °C. The stripes
were all coalesced and regrown to 1.5 µm at 610 °C. Stripe growth initially at 560 °C marginally improves ultimate film
morphology, but it must be followed by stripe growth at 610 °C, otherwise coalescence morphology will suffer due to poorer
faceting of the stripes when grown at lower temperatures.
103
Stripe growth in 60°-off-[1-10]-oriented openings, 300 s, varying temperature
560 °C 610 °C
Figure 4: Top-down SEM of stripes grown at 560 °C and 610 °C. All though the morphology seems more chaotic, the growth at
560 °C more effectively fills the opening with fewer height variations. The nucleation layer is likely protected from thermal
damage by growing this intermediate layer prior to 610 °C stripe growth. However, if too much growth occurs at a lower
temperature, the stripes will not have well-defined sidewalls and coalescence morphology will be poor.
6.1.3: Use of GaAs as Pre-InP Nucleation Seed Layer
The most significant improvement to nucleation quality and reproducibility at large was achieved by
using GaAs as a <12 nm seed layer prior to InP nucleation. Rather than forming a single monolayer of As,
deposition of GaAs more reliably prepared the surface for denser InP nucleation by ensuring a continuous,
As-terminated surface was present. GaAs nucleation has helped overcome the extreme sensitivity of the
InP growth to the slightest processing-related contamination [49]. Figure 5 shows the effect of the
inclusion of this GaAs layer on stripe morphology for a 60°-off-[1-10] orientation. The (100) surface
became much more prominent and height variations were strongly suppressed. The sidewalls, rather than
possessing an inverted dovetail shape as expected from Julian et al’s studies with stripes in this direction
have a stepped morphology [4]. After coalescence of these stripes, the rest of the film was grown in 2200
s at 0.3636 nm/s.
Mask
Stripe
104
InP growth in angled openings (from same batch, etched at the same time)
No GaAs nucleation layer, 5312 With GaAs nucleation layer, 5314
Figure 5: Effect of introducing a thin GaAs layer prior to InP nucleation shown through top-down SEM. The voids and numerous
height variations in the stripes were eliminated, and a predominantly-(100) surface was formed. Steps were formed on the stripe
sidewalls, seemingly following the <110> directions.
105
Coalescence of the previous angled nanostripes
Without GaAs nucleation layer,
RMS roughness 46.95 nm
With GaAs nucleation layer,
RMS roughness 12.2 nm, 5314-2
Figure 6: Effect of the introduction of a GaAs pre-layer on coalesced film morphology. These samples are the same as in Figure 3,
except the stripes have been coalesced into films. As seen with the stripes, morphology has enormously improved, reducing the
surface RMS roughness by almost a factor of 4 down to 12.2 nm.
106
In Figure 6, the result of coalescence and bulk growth of the stripes with and without the GaAs pre-layer
is shown. Without the pre-layer, the RMS roughness was relatively large compared to previous films
detailed in the previous chapter at 46.95 nm, with significant height variations in the film. With the pre-
layer, the roughness improved by nearly a factor of four, down to 12.2 nm. The latter film is still
somewhat rippled, as observed in the films in Chapter 5, but is still smoother than any film grown prior.
6.1.4: Optimization of RIE System Cleanliness
With the use of the GaAs nucleation layer, selective, reproducibility of continuous stripe growth was
ensured. However, the low surface roughness of the coalesced film for sample 5314-2 proved more
challenging to reproduce in subsequent attempts. This was attributed to drifting chamber conditions in the
RIE system leading to substantial fluoropolymer residues coating the sidewalls of the samples [76].
Although the sidewall passivation is vital for high-aspect ratio etching, ensuring anisotropy, it needed to
be removed at the end of etching, as it would outgas during nucleation and interfere both with precursor
transport into the openings as well as block sites for adsorption [35].
Non-uniform contamination would then lead to non-uniform nucleation, where precursors would
aggregate in cleaner regions in the openings. Increasing the precursor flux or growth time would be two
possible solutions, but if the contamination is non-uniform across the length of the opening, as it very
likely would be, this would lead to exaggerated growth height differences.
The drifting chamber conditions were attributed to a degraded platen introducing excess carbon into the
etch, which would increase the formation of fluoropolymer residues. Oxygen would counteract this effect
and lead to undercut openings [76]. This increase in chamber carbon was confirmed when etch profile,
shown in Figure 7.a was compared to earlier samples from months prior which gave undercut openings
(7.b).
107
Figure 7: (a) cross section of NIL openings. The expected cross section is shown in (b), but that wasn’t observed. (b) used the
same etch recipe and the same mask thickness though was patterned months prior.
To combat this, the O
2
content in the etch recipe was increased, forming undercut openings. The new etch
recipe resulted in undercut sidewalls for our mask, increasing the opening volume. This led to a
significant delay in the emergence and coalescence of stripes, requiring a change in the growth conditions.
The nucleation time was doubled. The second stripe growth step at 610 °C had to be prolonged from 300s
to 1800s to ensure coalescence was finished before proceeding with the bulk growth step. In Figure 8
below, the coalesced film continuity improves with increasing stripe growth time preceding the bulk
growth step. As this was not observed with previous samples, this also shows that too high of a growth
(b)
(a)
108
rate prior to the completion of coalescence will significantly delay planarization. At higher growth rates,
individual adatoms would not migrate as far on the surface of the stripes since new material would
quickly be deposited, and voids would be less likely to be filled in and may persist longer than usual.
Step
TMIn
partial
pressure
TMGa
partial
pressure
PH3
partial
pressure
AsH3
partial
pressure
V/III
ratio
Temperature
(°C)
Time (s)
Hydrogen
bake
0 0 0 0 N/A 920 300
Pre-
Anneal
0 0 1086 N/A 920 60
GaAs nuc 0 1.087 0 1086 100 400 180
InP nuc 1.81 0 3257 0 1786 400 300
Temp
ramp 1
1.81 0 3257 0 1786 400-560 120
Stripe
growth 1
7.51 0 1954 0 260 560 300
Temp
ramp 2
0 0 1954 0 N/A 560-610 80
Stripe
growth 2
7.51 0 1954 0 260 610 300+
Regrowth (40 °C TMIn bath temperature)
Bulk
Growth 1
12.8 0 1953 0 153 610 500
Bulk
Growth 2
25.6 0 1954 0 76 610 2200
Cooldown 0 0 1954 0 N/A 610-300 200
Table 1: Current parameters used for stripe growth and coalescence.
109
Stripes after coalescence and regrowth, each with increasing stripe growth time, 2700 s of bulk
growth after
5320-2: 600 s total stripe growth, [1-10], 2.5kx 60 degrees-off [1-10], 2.5kx
5321-2: 2100 s total stripe growth, [1-10], 7kx 60 degrees-off [1-10], 7kx
Figure 8: Effect of increasing initial stripe growth time on ultimate coalesced film quality. Films of coalesced stripes both [1-10]-
aligned and 60°-off-[1-10] are shown. Table 1 gives the growth conditions—the only variation is the second stripe growth step at
610 °C, 300 s in the top row and 1800 s in the bottom row. Following this, bulk growth of approximately 900 nm was performed.
Meanwhile, lowering the stripe growth rate significantly, such that the rate is unchanged after InP
nucleation, leads to worsening stripe morphology, as shown in Figure 9. Significant height variations are
observed, indicating the nucleation layer had been damaged. As discussed in Chapter 5, exposing the
nucleation layer to the higher temperatures used for stripe growth will lead to a redistribution of material.
Too slow a growth rate will expose too thin a layer to the elevated temperatures for too long a time.
110
Figure 9: SEM of nanostripes grown at 4.5x lower the normal rate, matching that of initial nucleation. Significant height
variations are observed, despite the use of a GaAs nucleation layer.
6.2: Optimization of Aspect Ratio Trapping and Coalescence
6.2.1: Nanostripe Orientation
To give a quantitative measure for the usefulness of coalesced films over buffer layers, cross-sectional
TEM was employed to verify whether aspect ratio trapping was successful in reducing the defect density.
First, AFM of the two films from Figure 8, 5321-3, are shown below in Figure 10. These two films used a
prolonged stripe step, as mentioned above, to compensate for the larger opening volumes from the
intentional RIE undercut. There is a clear improvement in the RMS roughness when 60°-off-[1-10]-
angled stripes are used for coalescence as opposed to [1-10]-aligned stripes, as expected from the findings
of Julian et. al. [4,19]. The roughness isn’t quite as good as what was observed for the first attempt at
111
GaAs nucleation 5314-2, but the film was still specular and lacked the twin-like crystallite defects
outlined in Chapter 5 that had hindered film growth prior to the use of the GaAs pre-layer.
AFM surface morphology, stripe direction dependence
5321-3: bulk growth to 1 µm
[1-10], 38.5 nm roughness 60 degrees-off-[1-10], 30.1 nm roughness
Figure 10: AFM of coalesced stripes shown under SEM in Figure 8. The RMS roughness for coalesced films of angled stripes is
noticeably lower than that for [1-10]-aligned stripes.
A qualitative measure of defect formation for these two samples, along with the previous 60°-aligned
coalesced film sample in section 6.1, 5314-2, were acquired via TEM and shown in Figures 11 and 12.
The number and location/origin of the defects are tabulated in Table 2. Three quantities are defined here:
emerging defects, coalescence-related defects, and defects that penetrate the surface. The emerging
defects are the ones that escape the openings. Coalescence-related defects are defined here as defects
emerging from the top of the sidewalls. And the surface-reaching defects are defects counted near the
surface. These latter defects may emerge from a location in the sample that was not in the cross-section,
especially for the 60°-off-[1-10]-oriented samples where the defects do not lie parallel within the plane of
the cross-section, and as such are counted separately from the emerging defects.
Defects emerging from the openings and reaching the surface are separately numbered. Voids, if present,
are numbered V#.
112
Figure 11: Cross-sectional TEM of 60°-off-[1-10]-oriented coalesced stripes
5314-2, 60 degree
5321-3, 60 degree (damaged by FIB)
Closeup of 5314-2 Closeup of 5321-2, 60 degree
113
For sample 5314-2, a few voids are present above the sidewalls, but since these are not observed in the
second 60°-off-[1-10]-oriented sample, these are not taken to be representative of this geometry, and
coalescence-related defects overall not observed outside of those voids. Some defects do escape the
openings, and there are a substantial number of defects reaching the surface, 9 in total within the 7 µm
cross-section of 5314-2.
For the final sample with openings oriented along the [1-10]-direction, defect formation has increased
dramatically. Although not as immediately evident in the lower-magnification image, the four higher
magnification images shown in Figure 12 reveal substantial coalescence-related defect formation, 9 in
total are observed for the whole cross section. Additionally, a significant number of defects, 15, are
observed escaping the openings, with a line of sight directly parallel to them. It is clear that orienting the
stripe openings near 60°-off-[1-10] is vital to suppress coalescence-related defect formation.
Number of defects and their location observed for 7 µm-wide, <100 nm thick TEM cross-sections
Sample Emerging Coalescence Surface Notes
5314-2 9 None* 9
*Voids present
5321-3, 60° 6
None 2 in 3 µm
Top FIB damage
5321-3, [1-10] 15
9
2-3
Coalescence-related defects
shown in next two figures
Table 2: Tabulated numbers of observed defects and their origin.
Another noticeable feature of these defects is a great majority clearly being either stacking faults or twins.
They are perfectly straight, lying on the (111) planes, and when viewed along the 60°-off-[1-10] cross
sections, are two-dimensional. Meanwhile, dislocations would be curved under TEM due to glide and
climb [66]. Some stacking faults appear to penetrate “through” the mask, but as Junesand et. al. note, this
is from stacking faults in neighboring openings joining together into a single defect once one of them
escapes its opening. They maintain that stacking faults that propagate closer to parallel than perpendicular
to the opening orientation cannot be blocked through aspect ratio trapping.
114
Figure 12: Closeup of Coalescence related defects “C#” in 5321-3, [1-10]
(a)
(b)
(c) (d)
(a) (b)
(c) (d)
115
Figure 13: TEM of an InP buffer layer grown directly on Si, showing significant defect propagation. The buffer layer was used for
later stripe growth through a dielectric mask patterned on top of the buffer layer, with void formation (white triangles) from a
sub-optimal InP native oxide clean, before an optimized etch was finalized.
As a comparison, as shown in the TEM image of Figure 13, an InP buffer layer grown directly on Si and
subsequently used as a seed layer for stripe growth was found to possess a substantial number of defects
on a much narrower lengthscale than the other samples. Without the presence of the mask above the
buffer layer in this particular sample, none of the defects would be filtered through aspect ratio trapping.
A very rough estimate of the defect density by counting the linear density of defects reaching near the top
of the buffer layer and squaring that value gives 2E9 cm
-2
, a typical value for direct epitaxial layer on
silicon [4,19]. Some dislocations are also observed, marked D#. This means of extrapolating the defect
density would be highly inaccurate for coalesced films, since the openings are oriented along a specific
direction and the cross section would not be symmetric with 90° rotation.
D1
D2
D3
116
With aspect ratio trapping, this high defect density is suppressed, not only by geometrical blocking of
defects originating from the Si surface, but also by reducing the footprint of the Si-InP interface, in turn
reducing the density of defects generated.
An additional feature was observed in coalesced films, but not buffer layers grown directly on Si. Like
with the first coalesced NIL films studied in Chapter 5, streaks aligned with the <110> directions are
observed in the film surface. Most streaks seem aligned with whatever <110> direction is closest to the
stripe direction. They do not disappear with additional growth. As a result, much like the crystallite
defects observed in Chapter 5, these streaks are believed to be planar defects, possibly associated with
coalescence. First, Figure 14 shows the surface of film 5214-2, possessing moderate streaking and a few
voids in the surface, with a total streak density of around 1.96E7 cm
-2
.
Figure 14: Surface of sample 5314-2, showing streak defects and small gaps in growth. Examples of streaks are circled in red.
Next, in Figure 15, the other two films which were characterized via TEM in Figures 11 and 12 (the two
films grown in run 5321-3) are shown. Although SEM again shows a rougher surface, the streak density
for the film with the 60°-off-[1-10] stripe orientation changed little over 5314-2, remaining around
1.9E7 cm
-2
. However, the streak density for the film with the [1-10] stripe orientation was increased to
117
3.06E7 cm
-2
. Coalescence-related defect generation has not been completely suppressed in coalesced
angled stripe films, but it is reduced over films with an initial [1-10] stripe orientation. This agrees with
the findings from TEM, where numerous coalescence-related defects were observed forming for the latter
mask geometry.
Figure 15: SEM of surfaces of the two coalesced film samples grown in run 5323-3 and characterized via TEM above in Figure 11.
(top) 60°-off-[1-10] stripe orientation. (bottom) [1-10] stripe orientation. Streaks are circled in red, with some appearing to be
needle-like crystallites embedded in the surface.
60°-off-[1-10]
[1-10]
118
Compare these films with the smoother but unoptimized coalesced film 5258, which used no GaAs
nucleation layer in Figure 16. The streak density has increased dramatically, to over 1E8 cm
-2
.
Figure 16: Streak defects in a coalesced film of [1-10] nanostripes, without a GaAs nucleation layer. The streak density has
increased substantially to over 1E8 cm
-2
, and the streaks are longer on average, from less than 1 µm in length for the previous
three samples to 1-2 µm in length here.
For a quantitative measure of defect densities and to determine the nature of the streak defects, EBIC was
taken of several films and is discussed at the end of the chapter.
6.2.2: Effect of Opening Pitch and Depth on Defect Formation
Aspect ratio trapping is not perfect, and some defects will invariably escape. New defects can also be
produced through coalescence. One possible method to counter these effects is to reduce the opening
density, which should reduce the total number of defects that escape in a given cross-sectional length as
well as reduce the number of coalescence-related defects simply by having fewer sites for those to occur.
The pitch was increased from 250 nm to 390 nm, though in the patterning process (due to NIL mask
availability), the openings became wider, now 200 nm wide. SEM of the top surface of the coalesced film
along with a TEM cross-section is shown in Figure 17.
119
Figure 17: (top) SEM of the wider-pitch sample showing more prominent needle crystallites within the streaks. (bottom) TEM of
the same sample. A coalescence-related defect was observed here, underlined in red. Dark-field was used in an attempt to
improve the image quality, the particular cross-section gave issues with imaging.
Although TEM was not as illuminating for the wider-pitch sample besides the presence of a coalescence-
related defect, the streak density had increased to 5.06E7 cm
-2
. Additionally, the needle-like crystallites,
120
possibly twins, embedded within the streaks seem more well-defined for this sample. AFM of these
needles in a separate sample confirmed that they are facets of an embedded structure within a larger
groove/streak.
If given a longer time to grow, these needles may eventually form into the larger trapezoidal crystallites
observed in some films in Chapter 5. A wider pitch may lead to worsening coalescence morphology
through greater height variations. Since the stripes would have to overgrow the mask further before
coalescence, they would also grow larger vertically, which would likely exaggerate height variations
present in them. Additionally, with larger stripe sidewalls as a result of the greater vertical growth, there
is an increased chance of “two-zipper” coalescence, and enhanced defect generation [4,19,58]. If the
streaks are the result of aggregated coalescence-related defects combining into larger twins or stacking
faults, then the more prominent streaks and their associated needle-like crystallites shown in Figure 17
would indicate a greater defect density.
The thermal strain expected to be produced by the mask in the InP can possibly produce additional
defects [59]. One avenue to address this is to reduce the volume of the dielectric to suppress thermal
strain by using a thinner mask. However, aspect ratio trapping may suffer. In Figure 18, top-surface SEM
and cross-sectional TEM of a sample with a 150 nm-thick mask is shown.
Unfortunately, more defects were observed escaping the openings owing to poorer aspect ratio trapping,
correlating with an increase in the streak density to nearly 8.7E7 cm
-2
. However, the needle-like
crystallites were less prominent. With TEM, clear defect propagation out of the openings is observed. A
coalescence-related defect propagating from the top of the mask was also observed.
121
Figure 18: (top) SEM of the surface of a film with a thinner mask. The streak density has increased to nearly 9E7 cm
-2
, but the
needle-like crystallites observed in Figure 17 are not as prevalent. (bottom) TEM of the same sample, showing clear defect
propagation out of the opening as well as a coalescence-related defect. Two of the four openings were damaged via FIB.
With thinner masks and wider pitches generating a greater streak density and promoting coalescence-
related defect formation, the optimal geometry discovered so far for coalescence remains a mask with
openings 300 nm deep, 150 nm wide with a 250 nm pitch, and aligned 60°-off-[1-10].
122
6.3: Use of a Buffer Layer under the Nanostripe Mask
6.3.1: EBL with Buffer Layer under Mask
To compare the morphology of the coalesced films grown directly on Si to the standard, ART-on-buffer layer
approach used in literature, we formed coalesced films for both EBL and NIL-patterned samples with a
500 nm-thick InP buffer layer under the mask [4,10,11].
EBL patterning of such samples presented no additional challenges besides reproducing smooth (sub-30 nm
RMS roughness) buffer layer morphology, as at that point GaAs was not used as the initial nucleation layer.
660 °C Standard condition growth
InP homoepitaxy, 20 nm mask
Heteroepitaxy no buffer layer,
200 nm mask
Heteroepitaxy with buffer
layer, 200 nm mask
[110]
[1-10]
L5114 L5195-2 L5206
Figure 19: Stripe growth on various templates in the [1-10] and [110] directions, at 660 °C for 200 s. Stripe growth in the [110]
direction shows a clear improvement when using a buffer layer, reproducing the morphology of homoepitaxial stripes. The
streaks/kinks in the stripes observed for the no-buffer 5195-2 (which as discussed in Chapter 5 are believed to be unblocked
stacking faults altering the sidewall morphology) are not observed in 5206. Meanwhile, stripe morphology is poor for the [1-10]
direction, even for the homoepitaxial sample.
123
1 µm pitch, 150 nm-wide openings
610 °C 660 °C
[110]
[1-10]
L5208 L5205
Figure 20: Improvement in [1-10] stripe morphology, with a buffer layer under the mask, following a reduction in stripe growth
temperature. The sidewalls of stripes grown along the [1-10] direction are better formed, but still possess the streaks/kinks
observed in the no-buffer sample 5195-2 in Figure 19. However, the (100) surface is now prominent.
In Figure 19, the morphology of stripes grown at 660 °C in the [110] orientation enormously improved
over growth without a buffer layer, reproducing the morphology of stripes grown selectively on an InP
substrate. The morphology in the [1-10] direction showed little improvement, though improved when the
temperature was decreased to 610 °C, as shown in Figure 20. The (100) surface is now prominent, vital
for coalescence. Meanwhile, stripes in the [110] direction have become highly chaotic, no longer
possessing the triangular cross-section observed at 660 °C. This change in morphology with temperature
may be related to both defect propagation out of the openings and adatom migration between planes. The
well-defined facets of [110]-oriented stripes rely on migration of adatoms off the (111)B sidewalls and
onto the (100) top surface. Eventually, the slow-growing (111)B sidewalls are all that remains as the
(100) plane disappears [12,16,17]. With a decreasing temperature, migration is suppressed, and more
growth occurs on the (111)B planes. Higher-order planes with possibly much different growth rates than
the surrounding (111)B plane which may be introduced through defects could be exaggerated as a result
from a lack of migration away from them.
124
Meanwhile, for [1-10]-oriented stripes, their (111)A sidewall is fast-growing. At higher temperatures,
migration away from the plane enhances (100) and perhaps other defect-related plane growth. However,
there would still not be enough growth on the (100) surface to cause it to disappear like for the [110]-
aligned stripes.
6.3.2: Coalescence with a Buffer Layer under the Mask
With the buffer layer under the mask, stripe morphology dramatically improved. This in turn allowed
more subtle changes to coalescence morphology with small adjustments to stripe orientation to be
observed. Little change in morphology with stripe orientation was observed for a 250 nm pitch and the
films were continuous.
In Figures 21, top down SEM of nine coalesced arrays of stripes with a 1 µm pitch is presented. The
opening orientation varied by 10° between each of the 9 arrays, with the exception of the inclusion of a
film of coalesced stripes oriented 45°-off-[1-10].
125
1 µm pitch, ~150 nm-wide stripes, angular dependence of morphology
10 degrees 20 degrees 30 degrees
40 degrees 45 degrees 50 degrees
60 degrees 70 degrees 80 degrees
Figure 21: Dependence of surface morphology for 1 µm pitch coalesced stripes with varying orientation as gauged through SEM.
Only stripes near 60-70°-off-[1-10] coalesced in a continuous manner, while for the rest of the orientations, numerous voids
were present where coalescence lagged.
Coalescence over a 1 µm pitch shows a strong dependence in morphology on orientation, with pits from
incomplete coalescence (and aligned with the stripe direction, unlike the streaks in Figures 14-18). As
expected from the findings of Julian et. al., and consistent with my findings presented earlier in this
chapter, films with am originating stripe orientation 60-70°-off-[1-10] have the smoothest surface with
minimal pitting [4,19]. Meanwhile, other orientations, especially stripes very near [110], show pits almost
on the order of 1/µm. Attempts at coalescence at such a large pitch without a buffer layer under the mask
were unsuccessful.
[1-10]
126
Cross-sectional TEM of arrays 60°-off-[1-10] with a 250 nm and 1 µm pitch was acquired to gauge the
effectiveness of defect filtering and the suppression of coalescence-related defect generation with the
buffer layer present.
Figure 22: Cross-sectional TEM of the 60°-off-[1-10] oriented stripe array with a buffer layer under the mask, possessing a
250 nm pitch. Defect filtering is far more effective now that the defective interface is separated from the top of the openings by
an additional 500 nm. At least one defect, outlined in red, was observed escaping, but otherwise, aspect ratio rapping is far
superior to the samples that did not possess a buffer layer under the mask.
Si substrate, polished by FIB
Si substrate, unpolished
127
Figure 23: (Top) SEM of the surface of the film in Figure 22. Virtually no streak defects are observed, only superficial pitting at
4.17E7 cm
-2
. (bottom) Closeup of part of the cross-section in Figure 22. On the left, a defect can be seen emerging from the top
of the mask, indicative of coalescence-related defect formation. Few defects are observed escaping the openings otherwise.
128
Cross-sectional TEM of the 250 nm-array is shown in Figures 22 and 23. Although few if any defects are
observed escaping the openings since the defective InP-Si interface has been placed far away from the
openings, more coalescence-related defects are observed than for the bufferless approach in 5314-2. This
is possibly due to the sidewalls not being level. There is a very slight roughness to the buffer layer that the
sidewalls pick up here (measured on subsequent films to be around 10 nm RMS). If adjacent stripes have
a vertical separation from this roughness, not just horizontal, it is possible the “two-zipper” mode outlined
in Chapter 3 may occur [4,19,58]. Thus, there is a greater chance for defect generation. This would be
avoided with CMP, however, a much thicker buffer layer would first have to be grown, and this merely
removes an issue the buffer layer itself caused.
That being said, the presence of the buffer layer has, at least relative to the cross-section viewed, made
defect filtering nearly perfect. The “untrappable” stacking faults propagating too close to the direction of
the openings Junesand et. al. caution about are not observed [66]. This isn’t just because defects would
first have to enter the openings from underneath because of the buffer layer—Junesand et. al’s
coalescence studies with hydride vapor phase epitaxy used a buffer layer as well. With only a geometric
model of defect trapping provided instead of simulation, it is possible this is an inaccurate hypothesis.
With off-<110>-orientations for openings, it may be possible to trap both dislocations and planar defects
effectively, regardless of the propagation direction of the defect. More TEM cross-sections of this
particular array, as well as that of new arrays like it, would need to be taken to verify this.
Since this is a matter of simply the InP-Si interface being much deeper in the structure than usual,
replacing the buffer layer with an equivalent additional depth to the selective openings should give the
same effect. At the same time, the mask will be flatter since it wouldn’t be formed on a heteroepitaxial
film but rather the Si substrate. Coalescence related defect-generation may be further reduced. Superficial
surface pitting was observed for this array with a density of 4.17E7 cm
-2
, but the streaks seen in previous
NIL samples were not present. Like the streaks, these pinholes may also be from defect propagation to the
129
surface of the coalesced films, and if so, they would most likely be from stacking faults or twins, being
the dominant defect-type observed under TEM.
Figures 24 and 25 show cross-sectional TEM of the 1 µm pitch array.
Figure 24: Cross-sectional TEM of the 60°-off-[1-10] array in Figure 21, 1 µm pitch. With coalescence successful over such a wide
pitch, defect filtering became more effective, with fewer openings available for propagation into the coalesced film from the Si-
InP interface. A few coalescence-related defects were observed, but overall the coalesced film seems less defective than the
array with the 250 nm pitch. Two voids are observed on top of the mask with a triangular cross-section.
130
Figure 25: (top) Surface SEM of the film from Figure 24. Streaks with a density of 7E7 cm
-2
are observed. (bottom) Closeup of the
void and a coalescence-related defect observed in Figure 24. With the void roughly triangular in appearance, the stripes likely
possessed the desirable inverted dovetail morphology prior to coalescence, undoubtedly responsible for the superior continuity
over the other orientations explored in Figure 21.
131
With the pitch increase, unexpectedly, the number of coalescence-related defects seems to have been
reduced dramatically. This is despite large semi-triangular voids being present on some of the sidewalls
due to the inverted shape of the coalescence front (dovetail-type following the convention used in
Chapter 2). Unlike other stripes grown along this orientation which possessed a standard mesa shape with
upwards-facing sidewalls, the dovetail shape is ideal, which allows greater lateral overgrowth while
maintaining a smaller footprint, and also minimizes the contact area of coalescence, reducing the
probability of coalescence-related defect formation through the “two-zipper” coalescence mode [4,19,58].
Defect filtering is still highly effective. In this case, the defect density may have been reduced simply
from there being fewer openings for defects to emerge from as well as fewer points of coalescence. The
effect of the buffer layer also relieving the strain of the InP prior to growth seems to have also helped with
the coalescence: attempts at continuous coalescence over such a large pitch without a buffer layer in past
experiments were unsuccessful.
However, streaks are now observed at this pitch, with a density of 7E7 cm
-2
. As a result, although the
defect density appears lower in the cross-section, coalescence-related defect generation may in fact be
higher than for the 250 nm pitch. In a separate sample, these streak defects were confirmed to be regions
of strong recombination, undoubtedly from planar defects, via EBIC in section 6.5. Pinhole-type surface
defects were also confirmed to be regions of recombination, but not nearly as strongly recombining as the
streaks.
6.3.3: NIL with Buffer Layer under Mask
Patterning NIL openings with a buffer layer under the mask proved challenging. First, the etchant used to
remove the Cr hardmask, CR-7 was found to etch the underlying InP buffer layer, delaminating the entire
pattern. To counter act this, the silicon nitride mask (this time PECVD nitride as the LPCVD nitride is
deposited at too high a temperature for InP) was deliberately underetched to leave a protective layer on
top of the buffer layer during Cr removal, which is then etched away by further RIE. This unfortunately
132
etches the sidewalls, but careful control of the protective layer thickness and moving to a larger mask
thickness of 400 nm allowed a mask with aspect ratio trapping still possible to occur.
There was a second problem with this approach, however. Even though the RMS roughness of recent
buffer layers have been measured to be consistently 10–15 nm, there is still a wavy surface much like the
coalesced film shown for 5314-2. This results in a little-to-no consistent contact with a hard NIL UV
mask, and microscale gaps in the pattern with even a soft PDMS mold, where the valleys in the wavy
surface are present. This leads to problems with coalescence, as openings or sidewalls can be too large in
areas.
In Figure 26 below, 100x OM of a coalesced film using one of these poorly-patterned samples is shown.
Coalescence hasn’t completely finished, due to the small brown pits in the surrounding reflective film, but
much larger, greenish diagonal streaks are observed. This is the color of the underlying PECVD nitride
mask where the PDMS mold likely did not contact the surface. Eventually, these streaks would be filled
in if additional growth was performed, but these regions would likely be highly defective.
Figure 26: 100X OM of a coalesced NIL nanostripe film on a buffer layer. The poor mask definition led to significant gaps in the
film where coalescence lagged.
After many attempts, a batch with an intact pattern was produced, but this procedure is not reproducible.
The Lourdudoss group used Al as their hardmask, which can be etched with BOE, and their buffer layer
was polished through CMP, which would eliminate contact problems in NIL [10,11,80]. It is highly likely
133
CMP is needed for this procedure to be reliable, a technique outside the scope of USC’s facilities at the
moment.
Figure 27: Cross-sectional SEM of a coalesced NIL nanostripe film on a buffer layer. The poorly-defined mask has led to
significant coalescence-related defect generation, with at least 8 found in the cross-section, making NIL with a buffer layer
impractical without CMP of the buffer layer. Defect filtering was somewhat successful, with only one found emerging out of the
buffer layer and out of the opening (E1). However, the poor resolution from FIB issues with this particular sample may be hiding
additional defect propagation out of the openings.
TEM in Figure 27 revealed that numerous defects were generated by the poorly-defined NIL mask. The
nature of the lithography makes this type of sample far more sensitive to the surface roughness of the
initial buffer layer. Without CMP, use of NIL with a buffer layer under the mask is highly impractical.
6.4: Determination of the Nature of Surface Features through EBIC
Cross-sectional TEM alone is a highly-inaccurate measure of defect densities due to the small data size.
Surface-TEM could be performed and may most-reliably give this information, but sample preparation is
difficult, likely requiring manual polishing. Although exact defect densities were not obtained, the streaks
134
and pinholes observed in the preceding sections were confirmed to be regions of recombination, and thus
from defects.
6.4.1: EBIC Overview
In EBIC, the primary electrons from an SEM scatter within the film they enter and create electron-hole
pairs in a depletion layer within a junction, which are then collected by a picoammeter [90]. Since the
electron beam is scanned across the surface of the sample, regions exposed by the beam which result in
greater or poorer carrier collection create a contrast map correlating with the SEM image. Since defects
create localized trap states, recombination of carriers generated by the electron beam, rather than
collection by the picoammeter, is likely [5]. As a result, defect densities, or at least identifying regions of
recombination, can be ascertained, as long as the resolution is good enough.
For our samples, a 500 nm-thick p-InP layer was grown on top of multiple samples. Following this, small
square pads of Cr/Au 10/20 nm were deposited to form Shottky barriers, with a barrier height of
approximately 60-70 nm [5,91]. The Cr was used as an adhesion layer. Ohmic contacts were formed with
In dots soldered on a hotplate to the InP surface.
6.4.2: EBIC Results
EBIC revealed that the pinholes and streaks observed in the films are indeed regions of strong
recombination. The pinholes streaks and pinholes are typically 100 nm wide or less, with the streaks
many hundreds of nanometers long. These features do not disappear with additional growth and are thus
not thought to be simply areas of incomplete growth or coalescence.
135
5196, the 1000 nm-thick coalesced [1-10]-aligned stripe film from Chapter 5 (though with 500 nm of p-
InP on top of it here) is analyzed in Figure 28. Here, numerous streak defects are present in addition to
pinholes. Two streaks are circled in red.
Figure 30: SEM of 5196, a coalesced [1-10]-oriented film to be compared with EBIC. Examples of streaks are circled.
136
Figure 29: EBIC of 5196. Although the resolution of some of the pinhole defects are lost within the regions of recombination,
streaks give a stronger contrast, indicating they are likely from defect propagation to the surface, and lead to more severe
recombination than pinholes. The circled streaks correspond to the same locations in Figure 28.
There is correlation between the darker regions in the EBIC map in Figure 29 and the location of surface
defects seen under SEM in Figure 28. Forty-four streaks within the 293.5 µm
2
image area are observed,
each approximately 1 µm long, giving a density of 1.53E7 cm
-2
. One hundred nineteen pinhole defects are
observed within the same area, a density of 4.16E7 cm
-2
. The total defect density in the analyzed area is
5.7E7 cm
-2
, over twice that of the 60°-oriented coalesced film sample investigated in previous sections.
This again demonstrates the latter being the optimal stripe orientation.
Since a planar defect, such as a stacking fault or twin, would introduce a greater density of trap states than
a dislocation due to a larger local disruption of the lattice, the stronger recombination from these streaks
as opposed to pinholes suggests they are where planar defects intersect the surface.
137
Additionally, the streak defects may have been generated from coalescence as they far less prominent, if
not observed at all in films directly grown on Si, as shown in Figure 30.
Figure 30: Buffer layer grown directly on Si showing few, if any streaks. This indicates streak generation is likely tied primarily to
coalescence and/or defects escaping from openings reaching the surface.
As mentioned previously, they occur for samples with sub-optimal mask geometry or poorer nucleation,
where multiple regions of “two-zipper” coalescence occur and likely aggregate into a larger defect [58].
Since dislocations were likely not imaged through this technique and yet were observed in buffer layers
under TEM, the pinholes and streaks are likely planar defects that have affected the surface morphology.
With TEM of the coalesced films showing primarily planar defects reaching the surface, EBIC gives a
reasonable measure for their defect filtering ability.
6.5: Conclusions for Coalescence
Through the coalescence of selectively-grown InP nanostripes on Si, a macroscopic film (>1 mm
2
) was
obtained which boasted a similar RMS roughness as direct film growth on Si. No buffer layer was used
under the mask, nor was CMP at any step. The only use of a seed layer for these samples was a
138
selectively-grown GaAs pre-layer prior to InP nucleation within the mask window. This layer ensures the
general reproducibility of continuous nucleation layer and subsequent stripe growth.
With TEM, aspect ratio trapping was confirmed to be more effective for stripes oriented 60°-off-[1-10]
compared to [1-10]-aligned stripes. Coalescence is improved for the former mask geometry as well, with
fewer defects observed generated through the process.
EBIC confirmed that pinholes and streak defects especially observed on the surface of the films are
regions of strong recombination. The streak defects are only observed for coalesced films and are always
aligned with the <110> directions. These defects are attributed to the propagation of stacking faults or
twins to the surface, either formed through coalescence or from defects that escaped the selective
openings. A higher–resolution defect imaging method would be needed to discern smaller defects such as
individual dislocations.
The pinhole and streak densities increase if the stripe orientation is moved away from the optimal 60°-off-
[1-10], if the mask were made thinner, or if the pitch is increased, as coalescence morphology becomes
poorer.
In all, a near-factor of 100 decrease in the defect density for coalesced films was observed with optimized
mask geometry—roughly 2E7 cm
-2
defects observed on the surface of the optimized 60°-off-[1-10]-
oriented nanostripe film compared to the 2E9 cm
-2
for buffer layers. However, coalescence-related defect
generation remains a significant issue, along with imperfect defect filtering, creating streak defects on the
surface.
The use of a buffer layer is impractical with NIL. Without CMP, the buffer layer is too rough for the
technique, as the height variations translate to regions of missing pattern on the mask.
With a buffer layer under an EBL mask, at a 250 nm stripe pitch, virtually no streaks were observed,
though a pinhole density of 4.17E7 cm
-2
was present. Although streaks were generated for a 1 µm pitch,
139
continuous coalescence achieved. This may allow easier photonic integration, silicon or otherwise. If the
buffer layer is again replaced with the same thickness of mask, the pitch would be wide enough for a Si
waveguide to be embedded within each sidewall [3]. A complication with using a thick mask to replace
the buffer layer, combined with the wide pitch, is the effect of thermal strain, as the mask volume would
increase significantly.
The application of the coalesced 60°-off-[1-10] films compared to bulk thin films on Si or InP substrates
for PN mesa diodes, the first step for PIN photodiode fabrication, is explored in the next chapter.
140
Chapter 7: Fabrication and Characterization of PN Junctions on
Coalesced InP films
In this chapter, the IV characteristics of PN junctions fabricated on InP substrates and on coalesced films
are compared to give a practical measure for the viability of coalesced films for device applications. The
junctions are formed into square and rectangular mesas 300–500 µm on a side, fabricated through
selective growth and etching. These two different fabrication approaches are compared, with selective
growth leading to an unexpectedly large reverse bias leakage current.
7.1: PN Junction Design
7.1.1: Design of Mesas
The initial mesa design consists of two 1.5-2 µm layers of n- and p-InP, with the p-layer on top. Since the
Si-InP interface is highly defective, and because the Si substrate is not doped heavily enough to allow
Ohmic contacts to be easily fabricated on the back surface, a transverse junction design as shown in
Figure 1 below was employed [92].
Figure 1: The two approaches for mesa formation used in this experiment. (top) selectively grown mesa. (bottom) etched mesa.
n-contact
p-contact
SAG p-InGaAsP
SAG p-InP
SAG n-InP
LEO InP/InGaAsP
SiN
x
mask
p-contact
Etched p-InGaAsP
n-contact
Etched p-InP
Etched n-InP
141
Due the longer lifetime of minority carriers, n-InP was chosen as the base layer as the n-layer’s
quasineutral region length is over two orders of magnitude longer than the p-layer’s due to the transverse
design of the diode. P-InP alone, however, is not as effectively doped due to limits in Zn solubility, and as
a result, the layer together with its contact can be much more resistive, and Ohmic nature of contacts is
harder to ensure [30,31]. To resolve this issue, a 300 nm-thick heavily Zn-doped (expected carrier
concentration >10
19
cm
-3
) p-InGaAsP top layer was grown on top of the p-InP. The InGaAsP had a -0.5%
strain, with a lattice constant of 5.88-5.89 Å. The intended lattice-matched composition was
In
.82
Ga
.18
As
.39
P
.61
, which would give a bandgap around 1.085 eV.
The first fabrication method employs selective area growth to avoid having to etch down to the n-layer to
form the n-contact, while the second uses wet or dry-etching.
7.1.2: Design of Contacts
Four mesa sizes were fabricated: 300×300, 400×400, 500×500, and 300×700 µm
2
; “small”, “mid”,
“large”, and “RT” as the labels, respectively. Surrounding each mesa, with a 50 µm separation from the
mesa, was an n-contact shaped into a ring with a width of 200 µm, with a 500 µm-wide pad connected to
it for probing.
For the p-contacts, pads with a slightly smaller area than the mesa were created, with a 25 µm spacing
between the mesa edge and the contact edge. Each mesa was spaced 1.5 mm from one another in the
horizontal direction and 2 mm in the vertical direction, as the ring contacts are wider in the latter direction.
The mesas were rotated 60° from the <110> directions to minimize edge enhancement forming a “lip”
that could lead to challenges with photolithography [18]. The contact design is outlined in Figure 2.
142
Figure 2: Contact design for mesas. (Left): n-InP ring contact and p-InP/p-InGaAsP contact geometry. M: mesa, PC: p-contact,
NC: n-contact. (Right): geometry for “RT” rectangular mesa.
For n-InP Ohmic contacts, AuGe/Ni/Au 100/30/50 nm was used [93]. Two adjacent ring contacts on n-
InP, were found to give a resistance of 7 Ohm before annealing and 5 Ohm after annealing. The 30 nm of
Ni helps prevent the AuGe layer from balling up during annealing, and previous work in our group had
found that a roughly 1:3 ratio of Ni:AuGe thicknesses is needed for this effect to hold [93,94].
Initially, 200 nm was used for the thickness of the top Au layer, but this led to issues with liftoff where
the metal on the resist connected to the metal in the opening, requiring sonication to finish liftoff and
often damaged the contacts. Reducing the top layer thickness to 50 nm resolved this problem.
The first p-type contacts used Ti/Au/Zn/Au 5/20/40/200 nm to replicate the more ideal AuZn alloy—
which could not be deposited at USC, but the adhesion was poor [31,93]. Additionally, the resistance of
the contacts and layer together, measured through a test sample using adjacent rings on a p-InP film, was
high—around 800 Ohm—even after annealing. The final design used Ti/Pt/Au 30/50/100 nm contacts on
p-InGaAsP.
143
For annealing, both n- and p-contacts were annealed in an RTA furnace simultaneously at 440 °C for 20 s
in H
2
. Clauson and Leistiko had tested a range of anneal temperatures for the same n-InP contacts and
found that 440 °C gave a minimum contact resistance [95].
For p-InGaAsP, the same annealing conditions were used. A Katz had found that annealing at 450 °C for
30 s gave the optimum contact resistance but this is not the optimum for the n-contacts, so 440 °C was
used [31].
7.2: Selectively Grown PN Mesas
7.2.1: Morphology of SAG Mesas and Overgrown Edge
First, mesas grown selectively out of openings in an 80 nm-thick silicon nitride mask were investigated.
Due to selectivity, there was a growth rate enhancement of roughly 3x, requiring a reduction in the
growth times from the originally expected 800 nm/2200 s.
The morphology of the mesas, which overgrew the mask approximately 10 µm, is shown in Figure 3. The
cross-hatched top InGaAsP surface of the films was similar to what was observed on planar samples. This
would be expected for the large sample area, but the overgrown edges have an unexpected morphology.
Not only is there edge enhancement, but an additional top (100) surface formed at the edge.
The sidewall for the InP control sample is stepped rather than possessing a single, flat facet, but is
reasonably consistent in geometry with no significant height variations. Also labeled are four planes of
note that are identified with the immediate vicinity of the mesa edge: 1, the lowest portion of the sidewall,
2, a possible raised (100) portion of the edge, 3, a facet joining portion 2 to the bulk, and 4, the bulk (100)
surface of the mesa. A schematic of the cross section of the sidewall is shown in Figure 4.
144
Figure 3: SEM of the sidewall of a SAG mesa grown homoepitaxially on an InP substrate. The white numbers identify planes
marked in the schematic in Figure 4. Note the extensive break in otherwise smooth (though cross-hatched from defects in the
InGaAsP top layer) marked by the red line, where numerous defects are likely present that penetrate into the depletion layer.
Another anomalous feature, marked by the red line, was observed under SEM. There is a break in the
flatness of the film with a rather rough morphology that marks where the sidewall begins, which is likely
caused from a substantial defect density that may even penetrate the depletion layer. This line also does
not correspond with the edge of the opening, it simply where the edge enhancement on the mesa top
surface begins. This overgrown edge of the mesa will be shown to be responsible for an anomalously
large reverse bias leakage current in the next sections.
3 (defective region)
2 (overgrown edge, (100)
1 (edge sidewall)
4 (bulk of mesa, (100)
SAG mask
145
Figure 4: Schematic cross-section of the edge of a typical SAG mesa, numbered to correspond to the SEM image in Figure 3. 1 is
the sidewall that rises from the mask, and is a stepped combination of {111} and {110} planes. 2 is (100), with cross-hatching
from the mismatch of p-InGaAsP to the p-InP below it. 3 is another stepped {111}+{110} facet. Where 3 meets the mesa proper is
a break in film morphology that may penetrate deep into the depletion region and does not correspond to the location of edge
of the opening in the SAG mask. Finally 4 is the (100) surface of the bulk of the mesa. The entire surface is covered in InGaAsP,
aside for the exposed SAG mask.
7.2.2: IV Characteristics of SAG Mesas
The IV characteristics of SAG-pn mesas for three different sample types were acquired. These samples
were mesas grown on: InP substrates, InP thin films (a “buffer layer”) on Si, and coalesced InP films of
60°-off-[1-10]-aligned stripes on Si. As mentioned earlier, these were “Large” 500x500 µm
2
, “Mid”
400x400 µm
2
, “Small” 300x300 µm
2
, and “RT” (rectangular) 300x700 µm
2
mesas. IV curves of the
“Large” mesas is shown in Figure 6 for bias voltage in V and current in A. Little change in the IV
characteristics were observed between different mesa sizes, so the rest are excluded.
To further compare the junctions, the ideality factor n, the ratio between the current in the forward and
reverse biases, and the inverse slope of the curve (resistance) at -2 and 2 volts are tabulated. The ideality
factor n in the denominator of the exponential component of the diode equation terms
gives a measure for the dominant contribution of the current, whether it follows ideal diode behavior or is
dominated by Shockley-Read-Hall (SRH) trap-assisted generation and recombination [5,96]. For the latter,
defect states within the bandgap, as shown in the schematic in Figure 5, allow for additional generation
and recombination of carriers that form within the depletion region of the junction beyond simple band-
to-band generation and recombination or from the absorption/emission of light.
4
3
2
1
SAG Mask
146
Figure 5: Standard band-band generation and recombination compared to trap assisted generation and recombination. The
latter gives a lower barrier height for the transition due the presence of a trap state within the bandgap, formed from a defect.
At low forward bias, n=2 behavior will dominate for a few tenths of a volt, but for good diodes, standard
n=1 behavior should take hold up until series resistance effects occur above 1 V. Both n=1 and n=2 terms
will be present for a real diode, as given in the equation below, and in the reverse bias, the current will
have a small dependence with reverse bias from the increasing depletion width
[5,96].
For trap-assisted generation-recombination, the lifetime is inversely proportional to the density of states
of traps [97]. Since this trap density of states would increase with increasing defect density, the n=2 term
(itself inversely proportional to will generally increase in magnitude the higher the defect density is.
The ideality factors in real diodes may not be exactly 1 or 2, but whichever it is closest gives a good
measure for the behavior. To find it, take the inverse slope of the curve in forward bias, with a natural-log
scale for current, and the factor divided out.
n=2,
SRH generation-recombination
n=1,
Ideal diode
147
Mesa
substrate
Forward/Reverse
current ratio at
2/-2 V
Dominant
ideality factor
before series
resistance
Forward
resistance
at 2 V
(Ohm)
Reverse
resistance
at -2 V
(Ohm)
Coalesced -22.42 2.91 11.98 160.39
Buffer -210.65 3.02 17.46 2260.01
InP control -130.81 2.21 10.68 1015.03
Figure 6: IV characteristics for “Large” 500x500 µm
2
mesas. A large reverse bias current is present which does not saturate. The
mesa on the coalesced film sample has the most severe leakage, with the lowest reverse bias resistance. The other samples
show similar IV characteristics, even having similar series resistances.
-0.01
0.01
0.03
0.05
0.07
0.09
0.11
-2 -1 0 1 2
Current (A)
Bias (V)
IV of SAG Mesas
Large 60 1
Large Buffer 1
Large InP 2
Coalesced
Buffer layer
InP control
1E-09
1E-08
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
-2 -1 0 1 2
Large 60 1
Large Buffer 1
Large InP 2
Coalesced
Buffer layer
InP control
148
The most noticeable feature of the IV characteristics of all mesas is the anomalously-large reverse bias
leakage current. The magnitude of the current continues to increase with increasing reverse bias beyond
−2 V and does not saturate to a dependence on reverse bias. The reverse bias current expected for
the InP control mesas from simulation should be well below 1 nA, even when taking SRH generation and
recombination into effect with the lifetimes expected for our doping levels (from literature, ~157 ns and
<1 ns for holes and electrons, respectively) [98]. With the magnitude of the n=2 component of the current
in the reverse bias proportional to the trap density of states, high defect densities within the mesas are
responsible for this behavior.
The coalesced InP films show the most severe reverse bias leakage, with consistently the lowest forward-
to-reverse-bias ratio and a current magnitude at -2 V of nearly 4 mA. Meanwhile, the reverse bias current
for the InP controls do not increase in magnitude as rapidly. The mesas should have a very low defect
density <10
3
cm
-2
, being grown on an InP substrate. But even for them, a very large leakage current is
observed. However, the overgrown edge is likely highly defective and acting as a region of strong,
localized trap-assisted generation and recombination. As will be discussed in the next section, etching the
mesas rather than growing them selectively eliminated this behavior for mesas, at least on InP substrates,
lending strong evidence of the overgrown edge is responsible.
It is possible there is even premature breakdown at the edge before it occurs in the bulk of the mesa.
Proper breakdown is expected to be around -5 V for our doping levels but we did not observe this for our
SAG mesas (breakdown was observed between -4 and -5 V for etched InP control mesas, however) [68].
Essentially, the overgrown edge acts as a short. With increasing reverse bias and trap-assisted generation,
increasingly more current passes through it than the bulk of the mesa.
Despite buffer layers having defect densities over 6 orders of magnitude higher than InP substrates, mesas
formed on them show a similar reverse bias characteristic to those on InP substrates. Both the InP
substrate and buffer mesas have a current magnitude at -2 V between 0.1 and 1 mA, averaging around
0.5 mA or almost an order of magnitude lower than the coalesced film. Similarly, the resistance measured
149
in the reverse bias at -2 V is over 5x larger for the InP control and buffer mesas over coalesced film mesa.
This implies that the coalesced films somehow are leakier than the other two sample types, even though
the buffer layer has a defect density nearly two orders of magnitude larger.
For the forward bias, the current for all samples converges at 2 V to around 100 mA, indicating a similar
series resistance around 10-15 Ohm. With ideality factors >2, SRH recombination and generation through
defects dominates [5,96]. The turn on voltages were also found to be lower than ideal, with the current
increasing sharply at 0.5-0.6 V rather than the expected 0.8-0.9 V expected through modeling.
Since the true effects of the difference in defect densities between InP control samples and the coalesced
films were obscured, fabrication of the mesas through an alternate method, etching, was employed
7.3: Etched Mesas
7.3.1: Etch Chemistries
To avoid the edge effects that were observed when pn junctions are grown selectively, “planar” junctions
were fabricated in which the pn junctions were grown over the entire surface of the sample in a single run.
Etched mesas were then prepared by etching away the p-contact and p-InP layers to expose the underlying
n-layer and ohmic contacts were applied to the n- and p- layers.
Initially, dry etching in a chlorine chemistry gave poor selectivity to the dielectric mask on top of the
mesas meant to protect them from etching, so a wet etch treatment was employed.
A 30 °C, 3:1:1 H
2
SO
4
:H
2
O
2
:H
2
O treatment was found to etch the InGaAsP layer cleanly and selectively to
the InP layer with 5 minutes enough to strip it [99]. HCl etching of InP proved more challenging to
control, with the concentration of HCl:H
2
O and temperature strongly affecting the etch rate. Ultimately,
35 °C 1:1.25 found to etch homoepitaxially-grown InP at 240 nm/min. Unfortunately, the etching was not
planar, instead working through defects, which led to roughening of the surface, so a back contact had to
be made instead of the ring-shaped top contact to the n-InP layer.
150
There was an extreme enhancement of the etch rate for the heteroepitaxial samples, which were severely
roughened. An InP film grown directly on Si etched over 1.4 µm in just 1 minute, and a coalesced film
etched around 500 nm in the same time, significantly roughening the surface to varying by hundreds of
nanometers across a profilometry scan length of 200 µm. This etch rate dependent on the defect density
agrees with the findings regarding defect densities in the previous chapter, where fewer dislocations were
found in coalesced films compared to bulk films directly grown on Si. Slowing down the etch rate
through dilution with water did not substantially suppress the roughening.
With our available etchants not reliable for mesa formation, especially for coalesced film samples, dry
etching with a thick photoresist mask on top of the mesas was employed. At a 95 W RF bias, 0 W ICP
power, 75 °C substrate temperature, and 6, 6, 2, 8 sccm of BCl
3
, Cl
2
, H
2
, and Ar respectively, an InP etch
rate of 23-25 nm/min was obtained. In five 11.4-minute segments, a total of 57 minutes of etching
exposed the n-layer, etching 100 nm of the layer away. After photoresist and nitride hardmask removal,
both n- and p- top contacts were made; the n-layer surface was not roughened as substantially as the dilute
HCl etch of the InP homoepitaxial control.
7.3.2: IV Characteristics of Etched Mesas
The IV characteristics of the etched mesas are shown in Figure 7. The same tabulated data is collected:
ideality factor, resistance at -2 and 2 V, and the forward/reverse ratio. Just mesas on coalesced films and
InP wafer control samples were tested here. Due to limitations in which coalesced mesas were available
for testing, mid-sized (400x400 µm) mesas were characterized instead of the large 500x500 µm mesas
presented in the SAG section. In general, this only affects the series resistance, causing it to increase
somewhat. The series resistance of the InP control sample may have also negatively affected by how the
n-contact was probed. Since the wet-etch left behind a rough n-layer, the n-contact was made instead to
the back side of the n-InP substrate and the diode was probed vertically.
151
Mesa
substrate
Forward/Reverse
current ratio at
2/-2 V
Dominant ideality
factor before
series resistance
Forward
resistance at
2 V
(Ohm)
Reverse
resistance
at -2 V
(Ohm)
Coalesced -3.600 2.85 18.51 44.00
InP control -1.53E6 2.14 83.30 1.22E8
Figure 7.a: IV characteristics of etched mid-sized mesas. The reverse bias characteristics of the InP control mesas have improved
enormously over their SAG counterparts. Meanwhile, the coalesced film mesa shows no improvement.
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
-2 -1 0 1 2
Current (A)
Bias (V)
IV of etched mesas
Mid 2 60 Etched 1
Mid 1 InP Etched 1
InP control
1E-13
1E-12
1E-11
1E-10
1E-09
1E-08
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
-2 -1 0 1 2
Mid 2 60 Etched 1
Mid 1 InP Etched 1
Coalesced
Coalesced
InP control
152
Figure 7.b: Reverse bias characteristics of an etched InP control mesa. Breakdown is observed to occur around -4 to -5 V,
agreeing with literature for our doping levels [68]. This was not observed in our studies of SAG mesas, possibly indicating
premature breakdown occurred non-uniformly within them through the overgrown edges.
It was found that for the etched mesas on InP substrates, the reverse bias leakage was reduced
substantially, lending strong evidence that the overgrown regions of the SAG mesas is responsible for the
anomalously high reverse bias currents.
Although the reverse bias still increases, the magnitude of the reverse bias current at -2 V was nearly four
orders of magnitude lower than for the SAG mesas on InP wafers. The Forward/Reverse bias ratio of the
current at 2 and -2 V increased significantly, to over 1 million (from a few hundred for the SAG samples),
with a reverse bias resistance of 122 MOhm. The ideality factor is also closer to 2 than before. Ideal diode
n=1 behavior is still not observed, which could be from surface recombination contributing n=2 behavior,
as the sidewalls of the mesa were not passivated [5,96].
Furthermore, the “knee” or turn-on voltage has shifted closer to the ideal 0.8-0.9 V. This also implies that
the lower-than-expected turn-on voltage in the forward bias for SAG samples was due to the defective
edge as well. Lastly, breakdown is observed to occur around -4 to -5 V in Figure 7.b, consistent with
when it should occur for the expected doping level of the layers [68]. This was not observed for SAG
-1.60E-06
-1.40E-06
-1.20E-06
-1.00E-06
-8.00E-07
-6.00E-07
-4.00E-07
-2.00E-07
0.00E+00
-5 -4 -3 -2 -1 0
Current (A)
Bias (V)
Etched InP control reverse bias IV
153
mesas when the bias was extended to -4 to -5 V, possibly indicating that premature breakdown occurred
in the overgrown SAG edge.
Meanwhile, the Mid-sized mesa for the etched coalesced sample still shows a high leakage current and a
turn-on voltage around 0.5-0.6 V like for the SAG mesa of the same size on coalesced InP. There is no
overgrown edge, but the strong leakage characteristic and high ideality factor remain.
With SAG mesas on buffer layers showing superior IV characteristics superior to the coalesced film
mesas (regardless of fabrication type) and similar characteristics to SAG mesas on InP substrates, this
leakage must be caused by something other than absolute defect density. Coalesced films possess defect
densities, when optimized, nearly two orders of magnitude lower than buffer layers. As discussed in
Chapter 6, prior to InGaAsP layer growth, streak defects aligned with one of the <110> directions are
observed for the coalesced films but not for buffer layers or InP homoepitaxial films on InP wafers. This
indicates they were generated either through coalescence or through defects that escaped the openings
Comparison of heteroepitaxial film surfaces with pinhole and streak defects
500 nm-thick buffer layer, 15kx 1.5 µm-thick coalesced film, 60°-off-[1-10]
opening orientation, 20kx
Figure 8: Comparison of two InP films grown on Si, one directly on the substrate and the other a coalesced film. Streak like
defects are observed only for the coalesced film, while pinholes are present for both.
This is demonstrated through the SEM micrographs in Figure 8. Although pinhole defects were also
observed in both buffer layers and coalesced films, EBIC revealed they are not as strongly-recombining
as the streaks. With the streaks 0.5-1 µm long on average, and their density of at least 2E7 cm
-2
, the total
154
length of all streaks on a coalesced film mesa is, on average, 2.5-5E4 µm, comparable to the ~2E4 µm
mesa perimeter for the large 500x500 µm
2
SAG mesas. The streaks, collectively, are likely acting in the
same manner as the overgrown edge for SAG mesas and thus coalescence-related defect generation must
be suppressed, along with improving aspect ratio trapping. Although pinholes were present, the streaks
were not observed for 60°-off-[1-10] coalesced films formed on top of a buffer layer, though only for a
250 nm pitch.
Whether or not mesas formed on buffer layers would still show the high leakage currents after switching
to an etched-mesa fabrication method was not determined. However, with the reverse bias current for
buffer layer SAG lower than that for SAG mesas on coalesced films, and the lack of streak defects on the
surface, it is expected some improvement would be observed, though not to the same degree as the InP
substrate mesas.
7.4: Conclusions for PN Junctions
Selectively grown pn mesas on InP substrates, coalesced InP films, and InP buffer layers on Si show an
anomalously large reverse bias leakage current, which is attributed to a defective overgrown edge on top
of the SAG mask. The coalesced InP film mesas show the most severe leakage, with the InP substrate and
buffer layer mesas possessing less severe leakage. The proposed cause is SRH Generation or possibly
premature breakdown through a high density of trap states occurring alongside current crowding through
these more conductive defective regions, making this effect inhomogenous across the mesa and dependent
on reverse bias voltage.
Etching the mesas instead was found to greatly improve the reverse bias characteristic, with >100 MOhm
resistance observed at -2 V for one InP homoepitaxial mesa. Breakdown was observed at -4 to -5 V,
consistent with the expected doping levels of the layers in the mesa [68].
The coalesced film mesas, even after changing fabrication methods, still possess a highly leaky reverse
bias current. These mesas, unlike ones formed on InP substrates or InP buffer layers on Si, show streak
155
defects aligned with the <110> directions, attributed through EBIC and TEM to be large twins or stacking
faults that may have been generated by poor coalescence. With a comparable collective length of these
streaks to the SAG mesa perimeter, these defects would act in a similar manner to the overgrown edges,
allowing for strong generation and recombination to occur.
To suppress this anomalous leakage behavior, more effective aspect ratio trapping is required. The use of
a buffer layer under the nanostripe mask—or more preferably a greater opening depth—that separates the
InP-Si interface from the mouth of the mask opening, would help trap more defects, also making them
less likely to interfere with coalescence. Furthermore, deeper openings would also allow height variations
from the initial 3D growth mode to be lessened in severity, improving coalescence and suppressing
coalescence-related defect generation.
156
Chapter 8: Future Work
8.1: Project Summary
In this project, the formation of single crystal films of InP on Si was investigated to enable the monolithic
integration of these materials. Owing to the large lattice and thermal expansion mismatch between these
materials direct epitaxial growth of InP has not resulted in the formation of high-quality materials. As a
result, this study has investigated the selective area growth and coalescence of InP epiaxial deposits in
nanoscale openings in dielectric masks on Si. By using high aspect ratio nanoscale openings in the
masking film, defects formed owing to lattice mismatch can be effectively terminated in the nanoscale
deposits which are then allowed to merge to form continuous film with lower defect density than is
possible without the masking and selective growth. Many aspects of the mask materials and openings as
well as the growth process play a role to in the effectiveness of this approach. Many of these influences
have been studied in this dissertation and the characteristics of the resultant film have been carefully
measured.
For nanostripe growth and coalescence, first, a high-temperature sample anneal in hydrogen was
performed to clean the Si surface and to suppress antiphase boundary formation. Low-temperature
nucleation at 400 °C after the hydrogen anneal was required to form a continuous layer for InP nanostripe
growth. The use of a GaAs pre-layer before InP nucleation further improved nucleation density and
ensured reproducibility of continuous nanostripe growth. The growth temperature is then increased for
stripe growth, where the InP emerges from the selective openings, overgrows the mask, and eventually
merges into a continuous film. Stripe morphology and coalescence were optimal at a 610 °C growth
temperature after nucleation.
Multiple mask geometries were tested, with stripe arrays oriented 60°-off-[1-10] forming the fewest
coalescence-related defects, and even forming a continuous layer over a 1 µm dielectric mask for a
sample that employed an InP buffer layer under the selective mask. A coalesced film with a roughness of
157
12.2 nm over a macroscopic area (> 1 mm
2
) was formed through coalescence without the use of a buffer
layer under the mask or CMP.
Defect densities were found to be reduced, relative to bulk films grown on InP, by nearly two orders of
magnitude in optimized coalesced films. However, these densities remained above 1E7 cm
-2
, and through
TEM, SEM, and EBIC, many defects observed reaching the surface of the films were discovered to be
generated through coalescence of the deposits over the mask, despite the defect filtering from aspect ratio
trapping being successful.
More work is needed to reduce these defect densities over bare InP thin films grown directly on Si. EBIC
confirmed pinhole and especially streak defects observed through SEM are regions of strong
recombination. A stronger method of characterization is needed to determine exact defect densities, such
as surface TEM.
PN junction mesas were formed on top of coalesced films and were compared to junctions grown on InP
wafers and InP buffer layers. Selectively growing the mesas led to the creation of a highly defective
overgrown edge, producing a highly leaky reverse bias characteristic. At a reverse bias of -2 V, the
current magnitude was over 0.1 mA for all samples. Etching the mesas instead gave homoepitaxial PN
mesas with a reverse bias resistance of over 100 MOhm in one instance and a current magnitude at -2 V
of less than 10 nA. But PN junctions formed on coalesced films still gave devices with high reverse bias
currents, with a magnitude above 1 mA and continued to show higher ideality factors under forward bias
than junctions formed on InP substrates. It is believed highly localized regions of high trap state densities
formed by the streak defects, generated by coalescence or by poor aspect ratio trapping of defects formed
at the Si-InP interface, are responsible for the poor performance of PN mesas formed on coalesced films.
To improve the reverse bias characteristics, the defect density must be reduced significantly for
coalescence to be practical.
158
8.2: Proposed Work: Growth
8.2.1: Reduction of Defect Densities
The primary application of coalesced InP is to serve as a platform for alloy materials latticed-matched to
it that could be used for optoelectronic device fabrication. InGaAsP could be used to form 1.3 and
1.55 µm laser diodes, and InGaAs could be used as a detector for those wavelengths. In Chapter 7, PN
junction mesas were fabricated on various substrates, including coalesced films, but before a PIN
photodiode can be made, the defect densities in the films must be improved. Coalesced films still possess
defect densities at least >1E7 cm
-2
. Most of these defects seem to be coalescence-related, but some defects
are from the Si-InP interface as well. Increasing the opening depth significantly, from the current aspect
ratios of 2-3 to a more desirable 7-10 should greatly improve stripe morphology and suppress coalescence
related defect formation as a result [4,39]. Not only would defect filtering be superior, the InP would have
more time to relax prior to emergence from the openings, and height variations would be less prominent.
Coalescence of nanostripes grown out of EBL openings with a buffer layer under the mask proved the
most successful in suppressing surface streak defects, but defect densities in the 1E7 cm
-2
were still
observed.
8.2.2: Growth on Exact (100) Si
Growth of InP on exact (100) Si would allow integration on a more widely-used platform than our miscut
wafers. However, since the (100) surface is only monoatomically stepped, a large collection of antisite
defects in a III-V epitaxial layer on the Si would form, creating a planar, (100)-propagating defect at each
step edge known as an anti-phase boundary (APB) unblockable by aspect ratio trapping [71,72]. The use
of miscut wafers annealed hydrogen allows the formation of biatomically-stepped surface, suppressing
APB generation. One recent method to suppress APBs formation on on-axis Si was explored by
Merckling et. al. They demonstrated the growth of InP nanostripes without APBs through the use of
anisotropically etched V-groove trenches of (111) planes in silicon, at the bottom of high-aspect ratio
mask windows [39]. The emerging nanostripes using the V-groove approach had little-to-no variation in
cross section and were used to fabricate arrays of NIR nanolasers [57]. One major complication is that V-
159
grooves require very specific planes (the (111) planes) to be present to inhibit APB formation, and off-
angled stripes might not possess them. Anti-phase domains may still form as a result. However, <110>-
oriented stripes, as demonstrated by Julian et. al., are not ideal for coalescence, so there may be a tradeoff
between wafer orientation and coalescence quality [4,19].
8.3: Proposed Work: PIN Photodiode Fabrication
8.3.1: PIN Photodiode Overview
The coalesced ART approach could be applied to the fabrication of many devices, from transistors to
lasers. With lattice-matched InGaAs grown on the InP, one clear application is photodetection. There are
numerous structures that can be implemented for photodetection, from photoconductors to APDs. For
InGaAs, a common approach is to use a PIN junction with the i-layer as the absorbing region [12,100].
For a photodiode, a pn junction would need to have one or both of the layers be absorbing. The issue here
is that when a photon is converted into an e-h pair anywhere outside of the space charge region, one of
them would be a minority carrier and might not be collected [12]. By introducing a neutral intrinsic region
in between the p and n regions, the space charge region is effectively widened, and by engineering the
depth of this layer to account for the absorption length of the light, many more carriers will be collected
as they are far less likely to recombine. Key figures of merit describing detector performance are
described below:
Bandwidth (measured in Hz) is related to the speed of the device and is inversely proportional to device
resistance and capacitance (and thus transit time of carriers). Increasing device area will increase the
number of photons collected, but will also increase capacitance. A thicker absorbing region, which also
increases sensitivity, will also increase the transit time of the device and thus lower the speed. Dark
Current is the current measured in the reverse bias without exposure to light. The larger the magnitude
this current, such as from thermalization of carriers for narrow-bandgap materials or trap-assisted
generation from defects, the more difficult it is to discern a weak signal from light. Finally, responsivity
is directly proportional to quantum efficiency and for PIN phododiodes is typically measured in A/W,
160
peaking at specific wavelengths. The greater the quantum efficiency, the larger the current gained from
the input power and thus the easier weaker signals can be detected. The responsivity is also proportional
to transit time, so unfortunately, high-responsivity photodetectors tend to be slow, and vice versa [100].
Typical industry-standard InGaAs PIN phododiode parameters are: responsivity 0.85–0.95 A/W between
1.3 and 1.55 µm photon wavelength, dark current increasing from 10
-11
A to >10
-9
A as reverse bias
increased from 0 to 40 V, and bandwidths of 3.3-10 GHz for a 100 µm
2
area [100]. A high-speed
InGaAs/InP PIN photodiode for 1.3–1.5 µm wavelengths was reported with a bandwidth of 90 GHz with
a responsivity of 0.53 A/W [2]. Another photodiode, evanescently coupled to a Si waveguide (though
wafer bonded) had a bandwidth as high as 33 GHz, with a dark current of 1.6 nA at just -4 V reverse bias
[7].
8.3.2: Normal-incidence PIN Photodiode Mesas
The mesa structure developed in Chapter 7 can be used, with modification, for an InP/InGaAs/InP PIN
photodiode. First, to give a larger operating range for reverse bias, the doping levels of the n and p layers
in an InP PN or PIN structure must be optimized to prevent too early a breakdown, which occurred for
our PN mesas between -4 and -5 V. If the n- or p-InP layers are too highlty-doped, the breakdown voltage
could limit the operation range of the device [5].
The InGaAs growth conditions must be optimized as well to ensure lattice-matching. With latticed-
matched InGaAs, an InP/InGaAs/InP normal-incidence photodiode mesa can be fabricated. To absorb
enough of the normally-incident light, the i-InGaAs would be made at least two absorption lengths thick,
or approximately 3.2 µm [101]. The top p+ layer would be InGaAsP, with a bandgap chosen to not absorb
the 1.55 µm light. The contact on the InGaAsP must be optimally designed to uniformly bias the device
while not obstructing the light.
Various figures of merit outlined in section 8.3.1 would be tested to compare the devices to other
monolithic integration attempts in literature, and to wafer-bonded detectors.
161
8.3.3: Silicon Photonic Integration
Figure 1: Potential butt-coupled PD using ART. The white arrow is the direction of light propagation, showing that the InGaAs
layer thickness plays less a role in absorption.
For a PIN photodiodes on coalesced InP, there are two main methods of fabrication beyond normal
incidence: butt-coupling and evanescent coupling, which involve coupling to Si photonics. Normal
incidence PDs would be the easiest to fabricate and would simply involve adapting the etched PN mesa
design in Chapter 7. Here, light illuminates the top surface of the PD and is absorbed by the i-layer below.
They often possess very high quantum efficiencies and coupling efficiencies, but photonic integration
with structures on the substrate may not be possible [23]. Furthermore, the responsivity-speed tradeoff is
a significant detriment. The waveguide approaches in this case are more desirable—a significant benefit
is that they can decouple responsivity from the transit time-limited bandwidth, depending on design [2].
With butt-coupling (Figure 1), light is guided and illuminates the side of the absorbing region. Because
light absorption is perpendicular to carrier transport, responsivity and bandwidth can both be high without
tradeoff. In essence, the length of the i-layer, rather than its thickness, is used for absorption, which
improves responsivity. Meanwhile the capacitance of the photodiode, and thus the bandwidth, is
controlled by the photodiode area. Since the butt-coupled photodiode does not need to be as long as a
normal-incidence photodiode to absorb light effectively, the device area can be made much smaller and
the capacitance is reduced, increasing the bandwidth.
Coupling efficiency is generally very high [13]. Unlike evanescently-coupled WGs, monolithic
integration of III-V PDs through this technique has been achieved with buffer layers [7,22]. One
p-InP
i-InGaAs
n-InP
LEO-InP
Light
162
downside to butt-coupling that due to the smaller device area (as light is absorbed over a smaller lateral
length), the carrier distribution along the optical path is non-uniform, and as a result, butt-coupling is
generally unsuitable for high-power applications [2].
Monolithically-integrated InGaAs/InP butt-coupled PDs have been reported to suffer high dark currents
and low bandwidth (as high as 400 µA for only 15 GHz) [2]. The ultra-high bandwidths together with a
large responsivity achieved through Ge butt-coupled PDs on Si—over 50 GHz, with a 0.8 A/W
responsivity and 4 µA dark current—have not been reproduced with III-V butt-coupled PDs [7,22]. Since
both dark current and responsivity can be negatively affected by the presence of defects, it is possible
dislocations or other defects have not been adequately suppressed by the buffer layer and are penetrating
into the active regions [12]. With ART instead of a buffer layer, it is possible that higher both higher
bandwidths and responsivities could be achieved with this method. Furthermore, since the defect filtering
would occur over a smaller distance than, say, an SLS structure, there would be more freedom with
structure design, and alignment to the WG may be easier [14]. Finally, if a Ge layer is deposited on the Si
substrate surface during the SOI process, multistep formation and native oxide removal can be achieved at
a much lower temperature than for Si (possibly below 700 °C as reported by Wang), and as a result, no
prolonged high temperature anneals would be necessary through the entire growth process [49]. The Ge
would have to be kept thin, as it can absorb the 1.55 µm light, though if spaced far enough away from the
i-layer, it wouldn’t be much of an issue.
Unfortunately, the device would be most complicated of the three to implement, especially when taking
ART into account. Performance is highly sensitive to the alignment of the waveguide to the absorbing
region [2]. Another significant issue is possible difficulty in lithography of the ART mask below the SOI
level. The Si substrate is separated from the SOI layer typically by 3 µm of oxide, and so the ART layer,
deposited on the substrate, would be at a significant depth as well. Contact-based lithography such as NIL
might not be possible.
163
Evanescent coupling (Figure 2), with its vertical layout, would be easier to implement than butt-coupling,
as lithography would be easier. This method works through coupling the tails of the electromagnetic
fields leaking out of the waveguide to a nearby absorbing region. Larger device areas are possible than for
butt-coupling, and as such this structure is more suitable for high-power applications [22]. High
bandwidths and low dark currents are harder to achieve, however, and the responsivity-transit time
tradeoff may be somewhat more prominent. Furthermore, they require the waveguide to be close to the
active region, and the size of the waveguide and active region must be engineered to improve uniformity
and speed across the device [3]. Bandwidth issues have been addressed through using modifications of
this vertically-coupled structure (some of which move away from the PIN design), such as the
unitraveling carrier waveguide [22].
This approach has, to my knowledge, not been achieved for InGaAs PDs without waferbonding. A buffer
layer approach, as explained previously, would separate the active region too much from the waveguide,
and since InP has a similar refractive index as Si, confinement (which relies on total internal reflection)
would suffer and so would coupling. The ART mask and coalesced InP may still be too large a distance
for coupling, however. To improve coupling, the waveguides could be placed inside the mask, as shown
in the cross-section for a hypothetical device, though this would mean the mask sidewall (and therefore
pitch) would have to be larger so the waveguide could fit inside, and likely also to preserve confinement.
Fortunately, Si single mode WGs for 1.55 µm propagation are only 200 500 nm or so in cross section, so
not too large of a mask sidewall or too deep a trench is needed [3]. Improvement in coalescence over a
wider pitch would be necessary, though. Finally, as this would be a “rib waveguide” approach, the main
SOI layer would have to be kept thin. Optical simulations would be needed to find the best method of
vertically coupling the waveguide the absorbing region above the mask, how to optimize the waveguide
geometry, and whether this “mask-buried rib waveguide” approach would work.
A more pressing issue is that both the LEO and n-InP regions must be thin to ensure proper coupling to
the active region. Because the SiO
2
that would surround the WG must be small to allow for adequate
164
SAG and coalescence, there will likely be poor confinement vertically, and for too thick of an n-layer, too
much of the light may leak out where the WG first meets the PD, ruining uniformity. A similar effect
occurs if the active region is too thick: the light is absorbed over too short of a lateral distance, and
uniformity of coupling and speed suffers greatly [3]. The i-layer must be kept thinner than the absorption
length. However, thinning the n-layer will make charge collection more difficult, as the InP-Si interface
below it must be avoided. Another issue is that the mask sidewall would be wider than the openings, and
if thermal mismatch does lead to defect generation as Orzali et. al. note, this could be disastrous to device
performance [59]. Finally, the SOI layer, which the InP would be grown on, may not be as high quality as
the Si substrate underneath due to the fabrication process (which involves waferbonding), so nucleation
could suffer. However, working epitaxial, evanescently-coupled Ge PDs on SOI have been demonstrated,
so it is possible InP could be selectively grown on top a Ge layer on the SOI in a similar manner detailed
by Wang et. al. [7,49,3]. Lastly, the defects formed through coalescence still need to be suppressed with
improved mask geometry. The inclusion of an i-layer and not doping the full n and p layers as highly,
only near the contacts, may help prevent the highly non-linear reverse bias behavior from occurring, but a
high dark current from a greatly increased n=2 component would limit practical application [5].
Figure 2: Potential epitaxially-grown, evanescently-coupled photodiode. The waveguides would be embedded in the stripes as a
“rib waveguide array”. The WGs place constraints on mask geometry. The lateral view shows the process of light absorption:
unlike butt-coupling, light is absorbed vertically, so the thickness of the InGaAs layer is important for speed. The active area
though is larger, meaning more light can be absorbed, and the device is well-suited for high-power applications.
Light
165
LIST OF REFERENCES
[1] Z. Wang et. al., Mater. Sci. Eng. B 177 1551 (2012)
[2] A. Beling and J. Campbell in: Advances in Photodetectors and Optical receivers (Optical Fiber
Telecommunications VI A, 2013) Chapter 3
[3] D. Ahn, L. C. Kimerling, and J. Michel, J. Lightwave Tech. 28 23 (2010)
[4] N. Julian et. al., J. Cryst. Growth 402 234 (2014)
[5] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3
rd
ed (Wiley, New Jersey, 2007)
[6] Y. Geng et. al., IEEE J Sel. Top. Quantum Electron. 20 6 (2014)
[7] A. W. Poon et. al., Proc. of SPIE 8628 (2013)
[8] Q. Li et. al., J. Cryst. Growth 405 81 (2014)
[9] L. Megalini et. al., J. Electron. Mater. 47 2 (2018)
[10] W. Metaferia et. al., Phys. Status Solidi C 9 7 (2012)
[11] H. Kataria et al, ECS Trans. 64 6 (2014)
[12] A. Joshi and G. H. Olson in: Handbook of Optics 2
nd
ed (Optical Society of America, 1995)
Chapter 16
[13] M. Piels and J. E. Bowers in: “Photodetectors” (Elsevier, 2016) Chapter 1
[14] K. Samonji et. al., Appl. Phys. Lett. 69 100 (1996)
[15] J. Z. Li et al, Appl. Phys. Lett. 91 021114 (2007)
[16] O. Kayser, J. Cryst. Growth 107 989 (1991)
[17] O. Kayser et. al., J. Cryst. Growth 112 111 (1991)
[18] S. J. Choi, Ph.D. Dissertation, University of Southern California (2004)
[19] N. Julian et. al., J. Electron. Mater. 41 5 (2012)
[20] C. Y. Chi, Ph.D. Dissertation, University of Southern California (2015)
[21] J. Z. Li et. al., J. Appl. Phys. 103 (2008)
[22] A. Beling and J. Campbell, IEEE J Quantum Electron. 51 11 (2013)
[23] J. E. Bowers and Y. G. Wey in: Handbook of Optics 2
nd
ed (Optical Society of America, 1995)
Chapter 17
[24] Y. Gao et. al., IEEE Pho. Tech. Lett, 24 4 (2012)
[25] G. Stringfellow, Organometallic Vapor Phase Epitaxy, Theory and Practice 2
nd
ed. (Academic Press,
London, 1999)
[26] H. J. Chu, Ph.D. Dissertation, University of Southern California (2010)
166
[27] A. Rockett, The Materials Science of Semiconductors 1
st
ed. (Springer, New York, 2008)
[28] A. Koukitu and H. Seki, J. Cryst. Growth 76 (1986)
[29] C. C. Hsu, Y. R. M. Cohen, G. B. Stringfellow, J. Cryst. Growth 74 (1986)
[30] E. K. Byrne in: Indium Phosphide and Related materials: Processing, Technology and Devices
(Artech House, Boston, 1992) 155
[31] A Katz in: Indium Phosphide and Related materials: Processing, Technology and Devices (Artech
House, Boston, 1992) 307
[32] M. Czub and W. Strupinski, Acta Phys Pol. A 88 4 (1995)
[33] K Reichelt, Vacuum 38 12 (1988)
[34] I. Langmuir, J. Am. Chem. Soc. 40 9 (1918)
[35] K. Yuan et. al., AIP Adv. 8 (2014)
[36] M. Winter, WebElements, webelements.com
[37] Y. Kohama et. al., Appl. Phys. Lett. 53 862 (1988)
[38] Y. Kohama, Y. Kadota, and Y. Ohmachi, Jpn. J. Appl. Phys. 29 2 (1990)
[39] C. Merckling et al, J. Appl. Phys. 115 (2014)
[40] C. Junesand et. al., J Electron. Mater. 41 9 (2012)
[41] T. V. Caenegem, I. Moerman, and P. Demeester, Prof Cryst. Growth Char. 35 2 (1997)
[42] C. Caneau et. al., J. Cryst. Growth 124 (1992)
[43] Y. T. Sun et. al., J. Cryst. Growth 225 (2001)
[44] H. Asai, J. Cryst. Growth 80 (1987)
[45] G. Müller et. al., Phys. Stat. Sol. (a) 202 15 (2005)
[46] Wikipedia, Dislocation Loop, https://commons.wikimedia.org/wiki/File:Dislocation_loop.png
Wikimedia Commons (2009)
[47] D. Hull and D. J. Bacon, Introduction to Dislocations, 5th ed (Elsevier, 2011)
[48] G. Wang et. al., J. Cryst. Growth 315 (2011)
[49] G. Wang et. al., J. Electrochem. Soc. 157 11 (2010)
[50] Y. Wei et. al., Microelectron. Int. 29 3 (2012)
[51] M. Sugo and M. Yamaguchi, Appl. Phys. Lett. 54 1754 (1989)
[52] M. Sugo et. al., J. Appl. Phys. 68 540 (1990)
[53] S. Chen et. al., Nature Phot. 10 (2016)
[54] D. L. Huffaker and S. Birudavolu, Proc. SPIE 49999 (2003)
167
[55] S. Takeuchi and K. Suzuki, Phys. Stat. Sol. (a) 171 99 (1999)
[56] Y. Nakajima, Ph.D. Dissertation, University of Southern California (2016)
[57] Z. Wang et. al., Nature Phot. 9 837 (2015)
[58] Z. Yan et. al., J. Cryst. Growth 212 1 (2000)
[59] T. Orzali et. al., J. Appl. Phys. 118 (2015)
[60] J. Z. Li et. al., Appl. Phys. Lett. 91 (2007)
[61] F. Olsson et. al., J. Appl. Phys. 104 093112 (2008)
[62] E. M. Rehder et. al., J. Appl. Phys. 94 7892 (2003)
[63] Y. T. Sun, K. Baskar, and S. Lourdudoss, J. Appl. Phys. 94 4 (2003)
[64] M. Yamaguchi et. al., Appl. Phys. Lett. 56 27 (1990)
[65] Q. Li and K. M. Lau, Prog. Cryst Growth Char. Mater 63 4 (2017)
[66] C. Junesand et. al., Opt. Mater. Exp., 3 11 (2013)
[67] F. Maseeh, S. M. Gelston, S. D. Senturia, VLSI Pub. 89 (1989)
[68] Ioffe Institute, Thermal Properties of Indium Phosphide
http://www.ioffe.ru/SVA/NSM/Semicond/InP/thermal.html,
[69] Z. R. Zytkiewicz et al, J. Appl. Phys. 101 (2005)
[70] Y. Wan et. al., Appl. Phys. Lett. 108 (2016)
[71] K. Sakamoto et. al., J. Electrochem. Soc. 136 9 (1989)
[72] H. Kroemer, J. Cryst. Growth 81 193 (1987)
[73] T. Yamazaki et. al., J. Electrochem. Soc. 139 4 (1992)
[74] T. W. Poon et. al., Phys. Rev. Lett. 65 17 (1990)
[75] R. D. Bringans, D. K. Biegelsen, and L. E. Swartz, Phys. Rev. B 44 7 (1991)
[76] C. L. Timmons, Ph.D. Dissertation, Georgia Institute of Technology, (2004)
[77] M. A. McCord and M. J. Rooks in: SPIE Handbook of Microlithography, Micromachining, and
Microfabrication (SPIE, 1997)
[78] C. Hedlund, H. O. Blom, and S. Berg, J. Vac. Sci. Tecnol A 12 4 (1994)
[79] Y. D. Galeuchet, P. Roentgen, and V. Graf, J. Appl. Phys 68 2 (1990)
[80] K. R. Williams, K. Gupta, and M. Wasilik, J. Microelectromech. S 12 6 (2003)
[81] O. Pluchery, Y. J. Chabal, and R. L. Opila, J. Appl. Phys. 94 2707 (2003)
[82] H. Kikuyama et. al., IEEE Trans. Semicon. Mfc. 3 3 (1990)
[83] D. S. Wuu, R. H. Horng, and M. K. Lee, J. Appl. Phys., 68 7 1990
168
[84] A. Yamamoto, N. Uchida, and M. Yamaguchi, J. Cryst. Growth 96 369 (1989)
[85] K. Hansen et al, Jpn. J. Appl. Phys. 32 (1993)
[86] T. R. Chen et. al., J. Appl. Phys. 54 2407 (1983)
[87] C. Blaauw et. al., J. Cryst. Growth 77 326 (1986)
[88] S. N. G. Chu, C. M. Jodlauk, and W. D. Johnston, Jr, J. Electrochem. Soc. 130 12 (1983)
[89] C. Merckling et. al., J. Appl. Phys. 114 (2013)
[90] Electron beam-induced current, Wikipedia https://en.wikipedia.org/wiki/Electron_beam-
induced_current
[91] P. D. Dapkus and C. H. Henry, J. Appl. Phys. 47 4061 (1976)
[92] H. C. Card, IEEE Trans. Electron Dev. 23 6 (1976)
[93] A. G. Baca et. al., Thin Sol. Films 308 599 (1997)
[94] C. K. Lin, Ph.D. Dissertation, University of Southern California (1999)
[95] T. Clausen and O. Leistiko, Microelectron. Eng. 18 (1992)
[96] B. V. Zeghbroeck, Principles of Semiconductor Devices, http://ece-www.colorado.edu/~bart/book,
University of Colorado (2011)
[97] S. Steingrube et. al., J. Appl. Phys. 110 (2011)
[98] P. Jenkins et. al., IEEE Photovolt. Spec. Conf - 1991 (1991)
[99] A. R. Clawson, Mater. Sci. Eng. 31 (2001)
[100] P. R. Norton in: Handbook of Optics, 2
nd
edition (Optical Society of America, 1995) Chapter 15
[101] Mikhail Polyanskiy, Refractive Index Database,
https://refractiveindex.info/?shelf=other&book=GaAs-InAs&page=Adachi (2019)
Abstract (if available)
Abstract
A dense array of InP nanostripes selectively grown on silicon is coalesced through lateral overgrowth into a continuous film. This film would serve as a quasi-substrate suitable for the fabrication of an InGaAs PIN photodiode. High aspect-ratio openings in the mask help filter defects originating from the InP-Si interface, shielding the coalesced film on top from the effects of the interface below. The quality of this film is highly dependent on the original stripe morphology, itself dependent on not just growth conditions, but also: how effective the defect filtering is, the quality of the initial nucleation on Si, and if the growing material can transition from Volmer-Weber growth to step-flow before emerging from the mask. Unlike the several-micron-thick buffer layers employed for monolithic integration, the thinner mask and coalesced film could possibly allow a photodiode fabricated from it to be close enough to an SOI waveguide for evanescent coupling, not to mention possess superior defect reduction. This epitaxial approach also avoids the cost and size-availability issues of the III-V wafers needed for efficient bonding to increasingly large silicon substrates. Through this technique, films with an RMS roughness comparable to bulk films grown on Si are achieved, with defect densities nearly two orders of magnitude lower. Strong reverse bias leakage currents of PN diodes grown on these coalesced films show more work is needed to suppress additional defect generation through the coalescence process.
Linked assets
University of Southern California Dissertations and Theses
Conceptually similar
PDF
Building blocks for 3D integrated circuits: single crystal compound semiconductor growth and device fabrication on amorphous substrates
PDF
The growth and characterization of III-V semiconductor nanowire arrays by nanoscale selective area metalorganic chemical vapor deposition
PDF
Integrating material growth and device physics: building blocks for cost effective emerging electronics and photonics devices
PDF
One-dimensional nanomaterials for electronic and sensing applications
PDF
Fabrication, deposition, and characterization of size-selected metal nanoclusters with a magnetron sputtering gas aggregation source
PDF
Phase change heterostructures for electronic and photonic applications
Asset Metadata
Creator
Dreiske, Mitchell Curtis
(author)
Core Title
The selective area growth and coalescence of indium phosphide nanostripe arrays on silicon through MOCVD for NIR monolithic integration
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
02/25/2020
Defense Date
12/16/2019
Publisher
University of Southern California
(original),
University of Southern California. Libraries
(digital)
Tag
1.55 micron,aspect ratio trapping,coalescence,compound semiconductor,CTE,defect,defect elimination,defect filtering,defect mitigation,diode,dislocation,dislocation annihilation,EBIC,electron beam induced current,epitaxial lateral overgrowth,epitaxy,growth on silicon,heteroepitaxial growth,heteroepitaxy,III-V,indium gallium arsenide,indium phosphide,InGaAs,InP,lateral epitaxial overgrowth,lattice matching,lattice mismatch,lithography,metalorganic,metalorganic chemical vapor deposition,metalorganic vapor phase epitaxy,microtwin,misfit strain,MOCVD,monolithic integration,Moore's Law,MOVPE,nanograting,nanoimprint lithography,nanolithography,nanopatterning,nanostripe,nanostructure,nanotechnology,NIR,nucleation,OAI-PMH Harvest,OMCVD,OMVPE,optical interconnect,organometallic,organometallic chemical vapor deposition,organometallic vapor phase epitaxy,photodetector,photodiode,PIN,PIN junction,PIN photodiode,PN,pn junction,selective area epitaxy,selective area growth,semiconductor,semiconductor growth,Si,silicon,silicon photonic integration,silicon photonics,stacking fault,strain,thermal mismatch,thermal strain,thin film,V-III
Language
English
Contributor
Electronically uploaded by the author
(provenance)
Advisor
Dapkus, Paul Daniel (
committee chair
), Kapadia, Rehan (
committee member
), Ravichandran, Jayakanth (
committee member
), Wang, Han (
committee member
)
Creator Email
dreiske@usc.edu,mitchelldreiske@yahoo.com
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-c89-274046
Unique identifier
UC11673602
Identifier
etd-DreiskeMit-8208.pdf (filename),usctheses-c89-274046 (legacy record id)
Legacy Identifier
etd-DreiskeMit-8208.pdf
Dmrecord
274046
Document Type
Dissertation
Rights
Dreiske, Mitchell Curtis
Type
texts
Source
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Access Conditions
The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...
Repository Name
University of Southern California Digital Library
Repository Location
USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA
Tags
1.55 micron
aspect ratio trapping
coalescence
compound semiconductor
CTE
defect
defect elimination
defect filtering
defect mitigation
diode
dislocation
dislocation annihilation
EBIC
electron beam induced current
epitaxial lateral overgrowth
epitaxy
growth on silicon
heteroepitaxial growth
heteroepitaxy
III-V
indium gallium arsenide
indium phosphide
InGaAs
InP
lateral epitaxial overgrowth
lattice matching
lattice mismatch
metalorganic
metalorganic chemical vapor deposition
metalorganic vapor phase epitaxy
microtwin
misfit strain
MOCVD
monolithic integration
Moore's Law
MOVPE
nanograting
nanoimprint lithography
nanolithography
nanopatterning
nanostripe
nanostructure
nanotechnology
NIR
nucleation
OMCVD
OMVPE
optical interconnect
organometallic
organometallic chemical vapor deposition
organometallic vapor phase epitaxy
photodetector
photodiode
PIN
PIN junction
PIN photodiode
PN
pn junction
selective area epitaxy
selective area growth
semiconductor
semiconductor growth
Si
silicon
silicon photonic integration
silicon photonics
stacking fault
strain
thermal mismatch
thermal strain
thin film
V-III