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Nonuniform sampling and digital signal processing for analog-to-digital conversion
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Nonuniform sampling and digital signal processing for analog-to-digital conversion
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NONUNIFORM SAMPLING AND DIGITAL SIGNAL PROCESSING FOR ANALOG-TO-DIGITAL CONVERSION by Tzu-Fan Wu A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL AND COMPUTER ENGINEERING) December 2019 ©2019 Tzu-Fan Wu All Rights Reserved To my dear mother and father To my beloved wife In loving memory of my grandmother Abstract A low-power, wide-bandwidth, and high-resolution analog-to-digital converter (ADC) is one of the critical building blocks in the design of a wireless receiver. However, quantization noise fundamentally limits the performance of ADCs. For this reason, continuous-time delta-sigma modulators (CT DSM) with high-order noise shaping have become a popular choice. However, the demand for a wider bandwidth increases the sampling rate, which requires high-speed and highly linear analog building blocks. Therefore, in this work, we investigate a new ADC architecture that uses nonuniform sampling (NUS) and digital signal processing (DSP) to avoid the aforementioned problems. The main challenge associated with quantization noise is that it is aliased by a fixed sampling rate. To overcome this limitation, this work proposes the application of nonuniform sampling to the input signal with inherent amplitude quantization, followed by another time quantization at the sampling instant. The key aspect is that the quantization noise is aliased at the frequency of the inverse of the time quantization resolution instead of the sampling rate. The quantization noise can be pushed to a higher frequency and removed by using the proposed nonuniform DSP. Moreover, the nonuniform DSP converts the nonuniform samples to a uniform output data stream, which can seamlessly interact with the existing synchronous DSP. The proposed NUS ADC architecture is implemented in four different prototypes. To prove the concept, nonuniform sampling is first implemented by using a voltage-domain level-crossing quantizer in a flash architecture, in which a dedicated comparator is connected to each reference quantization level. To reduce the number of comparators and the nonuniform sampling rate, a two-stage subranging-based NUS ADC is implemented in the second prototype with a timeout mechanism to adjust the sampling rate by filtering sampling events. To further improve the dynamic range and reduce the implementation cost, a first-order noise-shaping NUS ADC is implemented in the third prototype, which utilizes a voltage-controlled oscillator (VCO) as an integrator and a phase-domain level-crossing quantizer. The phase-domain comparison naturally eliminates the need for any voltage-domain comparator or reference voltage generation, resulting in a mostly digital implementation. A VCO-based NUS ADC that integrates both an NUS modulator and an on-chip nonuniform DSP, including calibration of the VCO linearity, is demonstrated in the fourth prototype. This implementation achieves a competitive dynamic range and power/area efficiency compared to state-of-the-art high-order CT DSM ADCs, in addition to offering the advantages of an open-loop architecture, a mostly digital design, and lower supply voltage. i Table of Contents List of Figures vi List of Tables xvii Acknowledgements xviii Chapter 1 Introduction 1 1.1 Area of focus ..................................................................................................1 1.2 Primary contributions .....................................................................................3 1.3 Thesis overview ..............................................................................................4 Chapter 2 Nonuniform Sampling ADC Architecture 6 2.1 Quantization noise modeling ..........................................................................8 2.1.1 Amplitude quantization noise characteristics ...................................10 2.1.2 Approximated amplitude quantization noise model .........................16 2.1.3 SQNR due to amplitude quantization ...............................................18 2.1.4 Time quantization noise modeling ...................................................24 2.1.5 Comparison with uniform sampling scheme ....................................31 ii 2.2 Design considerations and limitations ..........................................................32 2.3 Nonuniform digital signal processor ............................................................34 2.3.1 High-level concept and algorithm of nonuniform DSP....................35 2.3.2 Alias-free property validation ..........................................................43 2.3.3 Relaxed analog anti-aliasing filter requirements ..............................44 2.3.4 Reconfigurable signal reconstruction ...............................................45 2.3.5 Filter response reconfigurability ......................................................49 2.3.6 One embodiment of the nonuniform DSP ........................................52 Chapter 3 Nonuniform Sampling ADC Implementation 54 3.1 Modeling circuit non-ideality .......................................................................54 3.1.1 Variation of comparator propagation delay......................................55 3.1.2 Offset of comparator and reference voltage .....................................60 3.1.3 Noise in time quantizer and voltage quantizer .................................61 3.2 Flash-based NUS ADC ................................................................................65 3.2.1 Architecture ......................................................................................65 3.2.2 Reference generator and comparator ................................................66 3.2.3 Offset calibration ..............................................................................69 3.2.4 Pulse generator .................................................................................71 iii 3.2.5 Pulse combiner and level encoder ....................................................72 3.2.6 Time quantizer ..................................................................................75 3.2.7 Design tradeoffs ...............................................................................77 3.2.8 Measurement results .........................................................................80 3.3 Subranging-based NUS ADC .......................................................................87 3.3.1 Compared to flash-based NUS ADC ...............................................87 3.3.2 Time-domain view of subranging-based nonuniform sampling ...........................................................................................89 3.3.3 Architecture ......................................................................................90 3.3.4 Circuit implementation .....................................................................92 3.3.5 Measurement results .........................................................................97 3.3.6 Conclusion ......................................................................................103 Chapter 4 VCO-Based Nonuniform Sampling ADC 104 4.1 Review of nonuniform sampling ADC ......................................................104 4.2 Noise-shaping nonuniform sampling ADC ................................................106 4.2.1 VCO-based integrator and amplitude quantizer .............................107 4.2.2 Phase-domain level crossing ..........................................................108 4.2.3 Signal flow and nonuniform DSP computation .............................111 iv 4.3 Analysis of quantization error ....................................................................115 4.4 Comparison with uniformly sampled open-loop VCO-based ADC ..........120 4.5 Prototype of VCO-based NUS ADC with 200-MHz bandwidth and 60-dB dynamic range .................................................................................121 4.5.1 Voltage-controlled ring oscillator ..................................................123 4.5.2 Time quantizer ................................................................................125 4.5.3 Nonuniform bit storage ..................................................................129 4.5.4 Linearity calibration .......................................................................132 4.5.5 Example of nonuniform DSP implementation ...............................138 4.5.6 Measurement results .......................................................................140 4.6 Comparison of VCO-based NUS ADC with uniformly sampled continuous-time delta-sigma ADC .............................................................148 4.7 Prototype of VCO-based NUS ADC with 40-MHz bandwidth and 78-dB dynamic range .................................................................................149 4.7.1 Architecture ....................................................................................149 4.7.2 Implementation of NUS modulator ................................................151 4.7.3 Interface between NUS modulator and NU DSP ...........................152 4.7.4 Two-point phase error compensation .............................................153 v 4.7.5 Implementation of NU DSP ...........................................................156 4.7.6 Measurement Results .....................................................................160 Chapter 5 Conclusions and Suggestions for Future Work 166 5.1 Conclusions ................................................................................................166 5.2 Suggestions for future work .......................................................................167 5.2.1 VCO-based multi-stage noise-shaping NUS ADC ........................167 5.2.2 Nonuniform sampling for RF-to-digital direct conversion ............168 Bibliography 170 vi List of Figures Figure 2.1: (a) Uniformly sampled Nyquist-rate ADC and (b) proposed nonuniform sampling ADC................................................................................................. 7 Figure 2.2: Model of additive amplitude and time quantization noise in the proposed ADC. ................................................................................................................... 8 Figure 2.3: Input sinusoid of time period T (dotted line) and its reconstruction (solid line) from points generated by the level-crossing quantizer, along (a) comparator thresholds versus (b) half LSB shifted from comparator thresholds. Quantization error versus input signal using (c) comparator thresholds versus (d) half LSB shifted from comparator thresholds. .................................................................... 9 Figure 2.4: Power spectral density of quantization noise for sinusoidal input passed through a 4-bit level-crossing quantizer shown here on a logarithmic frequency scale.................................................................................................................. 12 Figure 2.5: SFDR versus number of bits when using different interpolation techniques. ........................................................................................................................ 13 vii Figure 2.6: Comparison of (a) Ŝ AQ (f) with S AQ (f) by using a linear frequency scale and (b) P ̂ AQ (f) with P AQ (f) by using a logarithmic frequency scale. ................................. 15 Figure 2.7: Comparison of NUS ADC SQNR AQ with corrected AQ SQNR and conventional ADC SQNR as c varies for 4-, 6-, and 10-bit quantizers, whose h p values are denoted as h p4 , h p6 , and h p10 , respectively. ....................................................... 22 Figure 2.8: Variation of the SQNR of a 6-bit quantizer with c TQ for different values of c. ........................................................................................................................ 25 Figure 2.9: Comparison of SQNR with the real SQNR for the 4-, 6-, and 8-bit quantizers, as time quantizer accuracy c TQ varies, with c fixed at 3.2. ............................. 26 Figure 2.10: Modeling Ŝ AQ (f) of (2.8) as a decreasing exponential. ................................. 27 Figure 2.11: SQNR improvement between the proposed NUS ADC with time quantizer accuracy of c TQ ∼ 9900 and different uniform oversampling ADCs but the same average sampling rate. ....................................................................................... 29 Figure 2.12: (a) Conventional digital FIR filter. (b) Proposed DAAF in the NU DSP. .................................................................................................................................. 34 Figure 2.13: Time-domain view of nonuniform output samples. ..................................... 37 viii Figure 2.14: Filter response of (a) conventional digital FIR filter and (b) proposed DAAF with an input of band-limited white noise up to 2F rs and filter corner at 0.25F rs . .............................................................................................................................. 41 Figure 2.15: Power spectrum of (a) analog input and (b) resampled output with and without the proposed DAAF. ..................................................................................... 43 Figure 2.16: (a) Spectrum of the analog input where two blockers are located at 0.55F rs and 0.98F rs , and the band-limited signal is located between 0.6F rs and 0.9F rs . (b) and (c) Blockers attenuated by an 11th-order Butterworth band-pass filter and subsampled by an ideal uniformly sampled ADC. (d) Reconstructed signal before processing using the proposed digital AA filter. (e) Subsampled and filtered output. ................................................................................................................... 48 Figure 2.17: Subsampling for a sinusoid input at 0.75F rs . (a) Uniform sampling ADC. (b) Proposed NUS ADC architecture with ZOH interpolation, Hann windowed, and ND set to 32. ............................................................................................ 50 Figure 2.18: Implementation of proposed nonuniform DSP. ........................................... 52 Figure 3.1: Model of non-idealities in the front end of NUS ADC. ................................. 55 Figure 3.2: Time-domain waveform within the comparator model using a ramp input. ................................................................................................................................. 56 ix Figure 3.3: (a) Delay variation and (b) degradation on distortions of various f comp , where spline interpolation is applied as a reference reconstruction algorithm. ................ 58 Figure 3.4: Voltage error introduced by the delay variation with different input slopes................................................................................................................................. 59 Figure 3.5: Errors introduced by the offset voltage in the voltage quantizer. .................. 60 Figure 3.6: SNR of a 20-MHz sinusoidal input over different jitter values. .................... 62 Figure 3.7: Concept of generating and processing level-crossing events. ........................ 63 Figure 3.8: Block diagram of the proposed flash-based NUS ADC. ................................ 64 Figure 3.9: Comparator implementation. .......................................................................... 66 Figure 3.10: Measured (a) comparator offset and (b) combined pulse using a 20-KHz ramp signal. (c) Measured output spectrum reconstructed using spline interpolation. ..................................................................................................................... 68 Figure 3.11: Pulse generator with tunable pulse width. .................................................... 70 Figure 3.12: Delay-balanced pulse combiner and level encoder. ..................................... 71 Figure 3.13: (a) Conventional CMOS OR gate. (b) Delay-balanced OR gate. ................ 72 Figure 3.14: Block diagram of the time quantizer including fine quantization and coarse quantization............................................................................................................ 73 x Figure 3.15: Current-starved inverter with tunable delay used in the ring oscillator. ........................................................................................................................................... 74 Figure 3.16: Passive phase interpolation by cross-coupled resistors. ............................... 74 Figure 3.17: Sense-amplifier-based flip-flop with pre-amplifier. ..................................... 75 Figure 3.18: Chip micrograph. .......................................................................................... 78 Figure 3.19: Measurement setup. ...................................................................................... 79 Figure 3.20: (a) Input amplitude and (b) measured and theoretical SFDR (entire spectrum) over different frequencies with single sinusoidal input. .................................. 80 Figure 3.21: Measured and calculated SNR (within 20-MHz bandwidth around the input frequency) (a) over different frequencies with single sinusoidal input and (b) over different input amplitudes with 1-MHz input............................................... 81 Figure 3.22: Measured and theoretical spectra of two tones at 15 and 19 MHz using (a) ZOH and (b) spline interpolation. ...................................................................... 82 Figure 3.23: Measured DNL and INL of the time quantizer. ........................................... 83 Figure 3.24: Measured blocker tests with NU DSP. (a) Low-pass. (b) Band-pass........... 84 Figure 3.25: Measured 64-QAM signal with 30-dB higher blocker presented at 43 MHz. (a) Before NU DSP. (b) Constellation after NU DSP. ........................................... 84 xi Figure 3.26: Proposed subranging-based NUS ADC versus flash-based NUS ADC. ........................................................................................................................................... 87 Figure 3.27: Block diagram of the proposed subranging-based NUS ADC. .................... 89 Figure 3.28: Circuit implementation of critical building blocks....................................... 92 Figure 3.29: Proposed alternating reference level switching scheme. .............................. 93 Figure 3.30: Implementation of continuous-time comparators. ........................................ 94 Figure 3.31: Spectra measured using flash-based and subranging-based architectures. ..................................................................................................................... 96 Figure 3.32: Measured SFDR and F s,avg with different T out settings (F in = 1 MHz). ........ 98 Figure 3.33: Measured SFDR, SNDR, and η NUS for different input frequencies. ............ 99 Figure 3.34: Measured spectra with a blocker 73 dB higher than the desired signal. ......................................................................................................................................... 101 Figure 3.35: Chip micrograph. ........................................................................................ 101 Figure 4.1: Architecture of the conventional NUS ADC. ............................................... 105 Figure 4.2: Phase-domain level crossing with a sinusoidal input. .................................. 108 Figure 4.3: (a) Time-domain waveform of the voltage-domain level crossing. (b) Time-domain waveform of the phase-domain level crossing when using a multi-stage VCRO. ......................................................................................................... 109 xii Figure 4.4: Signal flow of NS-NUS ADC with the phase-domain level crossing. ......... 111 Figure 4.5: Proposed VCO-based NS-NUS ADC architecture. ..................................... 112 Figure 4.6: (a) the combined phase and time quantization shown in Figure 4.4 is separated into phase quantization and time quantization. (b) Nonuniform ZOH is moved to precede the time quantization. The time quantization is modeled as a uniform sampler clocked at the effective sampling rate of F s,eff = 1/T Q and is followed by uniform ZOH with a period of T Q . (c) Differentiation and uniform ZOH are moved to precede the sampler. (d) VCO, phase quantization, nonuniform ZOH, and differentiation are combined into a PFM. ...................................................... 114 Figure 4.7: SQNR at the proposed NS-NUS ADC output calculated from (4.6), numerical simulation, and [41] over different input frequencies with the full-scale input A in K VCO = 0.7F FR .................................................................................................... 119 Figure 4.8: Block diagram and implementation of the proposed VCO-based NS-NUS ADC. ................................................................................................................ 121 Figure 4.9: Schematic diagram of VCRO and buffer. .................................................... 122 Figure 4.10: Schematic diagram of the reference time regenerator in the time quantizer. ......................................................................................................................... 126 xiii Figure 4.11: System-level simulation of SNDR for different values of jitter in the reference time.................................................................................................................. 127 Figure 4.12: System-level simulation of SNDR for the reference time mismatch. ........ 128 Figure 4.13: Implementation of nonuniform bit storage. ................................................ 129 Figure 4.14: Schematic diagram of the initial phase detector. ........................................ 131 Figure 4.15: (a) Plots of the desired F VCO and Δt versus the input amplitude. (b) Plot of the measured Δt versus the input amplitude, and the relationship between Δt ideal and Δt meas . .............................................................................................................. 132 Figure 4.16: (a) Accumulated phase error within Δt meas . (b) Approximated accumulated phase error within Δt meas . ........................................................................... 134 Figure 4.17: Phase error compensation. (a) Phase domain (after ZOH). (b) Voltage domain (after differentiation). ........................................................................... 135 Figure 4.18: Numerically simulated third-order harmonic with and without calibration over different input frequencies. ................................................................... 137 Figure 4.19: Representative design example of the linearity correction and the NU DSP, including the reconstruction filter. ......................................................................... 137 Figure 4.20: Chip micrograph in 65-nm CMOS. ............................................................ 140 Figure 4.21: Spectrum measured with sinusoidal input at 65 MHz. ............................... 141 xiv Figure 4.22: Plots of measured SNR and SNDR versus input frequency. ...................... 142 Figure 4.23: Plots of measured SNR and SNDR versus input amplitude (F in = 65 MHz). .............................................................................................................................. 142 Figure 4.24: Plot of measured THD versus chip temperature (F in = 5 MHz). ................ 143 Figure 4.25: Plots of measured SDR and SNDR versus VCO supply voltage (F in = 5 MHz). ........................................................................................................................... 144 Figure 4.26: Measured spectrum with inputs at 173.2 MHz and 184.9 MHz. ................ 144 Figure 4.27: (a) Architecture of conventional high-dynamic-range continuous-time delta-sigma modulator ADC. (b) Architecture of proposed VCO-based noise-shaping NUS ADC architecture, including nonuniform sampling modulator and NU DSP................................................................................... 147 Figure 4.28: Implementation of the nonuniform sampling modulator, and the interface between the nonuniform and uniform clock domains. ..................................... 151 Figure 4.29: Phase-domain level crossing with single amplitude quantization level. ......................................................................................................................................... 151 Figure 4.30: Characterization of the voltage-to-frequency relationship of VCO, and the time-domain relationship between ∆t measured and ∆t ideal . ..................................... 153 xv Figure 4.31: Proposed two-point phase error compensation for VCO linearity calibration. ...................................................................................................................... 154 Figure 4.32: Implementation of the proposed two-point phase error compensation scheme............................................................................................................................. 155 Figure 4.33: Behavioral simulation of the proposed two-point phase error compensation scheme. .................................................................................................... 155 Figure 4.34: Time-domain waveform of the calibrated signal (V out,q,calib ) at the NU DSP input. ....................................................................................................................... 156 Figure 4.35: The implementation of a digital AA filter in the NU DSP, including decimation and two-point phase error compensation. .................................................... 157 Figure 4.36: Chip micrograph. ........................................................................................ 158 Figure 4.37: Measurement setup. .................................................................................... 159 Figure 4.38: Measured spectra at NU DSP output for F in of 2.64 MHz and 12.41 MHz. ............................................................................................................................... 160 Figure 4.39: Measured SNDR versus input amplitude for F in of 2.64 MHz with 40-MHz BW.................................................................................................................... 160 Figure 4.40: Measured output spectrum in two-tone test. .............................................. 161 xvi Figure 4.41: Plots of measured SNDR and DR versus different input frequencies at NU DSP output. .......................................................................................................... 161 Figure 4.42: Plot of measured SNDR versus different chip temperatures at NU DSP output (F in = 2.64 MHz), where the ADC is characterized at 45°C. ...................... 161 Figure 4.43: Simulated and measured frequency responses of the digital AA filter in the NU DSP. ............................................................................................................... 163 Figure 4.44: Measured spectra at the input and output of the NU DSP. ......................... 163 xvii List of Tables Table 3.1: Comparison with ADCs utilizing nonuniform samples................................... 85 Table 3.2: Comparison of proposed subranging-based NUS ADC with ADCs utilizing nonuniform samples. ........................................................................................ 102 Table 4.1: Summary and comparison of performance of the proposed architecture with prior implementations. ............................................................................................ 146 Table 4.2: Performance summary and comparison of the proposed architecture with state-of-the-art CT DSM ADCs. ............................................................................. 164 xviii Acknowledgements I would like to thank my advisor Prof. Mike Shuo-Wei Chen for guiding my research, for his invaluable lessons in intuitive thinking and clear writing, and for his patience. I am grateful for his contagious excitement about novel ideas and circuits. I thank the National Science Foundation, Defense Advanced Research Projects Agency, and Google, LLC, for funding the entire research work. I also take this opportunity to thank the members of my doctoral qualifying and defense examination committee, namely Prof. Hossein Hashemi, Prof. Keith Michael Chugg, Prof. Antonio Ortega, Prof. Ellis Fan-Chuin Meng, and Prof. Nick Graham for their interest in, time spent on, and feedback about my research. I especially thank Mr. Mark Rich who supported our vision in the early stages of this project and engaged in technical discussions along with Brian Kaczynski, Michael Mack, and MeeLan Lee during the Google R2 Program. I am grateful to all my colleagues who are or have been in my group, especially Dr. Cheng-Ru Ho, Dr. Jaewon Nam, Dr. Shiyu Su, Aoyang Zhang, and Mohsen Hassanpourghadi for their help and technical discussions. I also thank all the other students, namely Ce Yang, Qiaochu Zhang, Juzheng Liu, Rezwan A Rasul, Mostafa xix Ayesh, Soumya Mahapatra, and Baishakhi Rani Biswas for their friendship and for making the lab an amusing place to be. I thank both Dr. Praveen Kumar Sharma and Sourya Dey, as well as many people from Prof. Hashemi’s group, namely Dr. Sungwon Chung, Dr. Run Chen, Dr. Sushil Subramanian, Masashi Yamagata, Pingyue Song, Aria Samiei, and Samer Idres for their many helpful discussions and hands-on assistance. I also thank Prof. Fon-Che Liu, who is also my cousin-uncle, Prof. Shen-Iuan Liu, and Prof. Liang-Hung Lu from National Taiwan University for encouraging me to pursue a doctorate after I worked in the industry for four years. Words are inadequate to express my gratitude toward my parents. I thank my mother Li-Jung Liu and my father Wen-Yuan Wu for their endless love and physical, spiritual, emotional, and financial support and for always giving me (and my brother) the best. An accomplishment of this nature would not have been possible without their love, advice, and encouragement. They have given me the foundations and the freedom to undertake many adventures, and they believe everything will somehow turn out right. They also believed me every time I said I will graduate “next year.” I also thank my brother Tzu-Cheng for always being there for me and for loving me. My wife Yao-Han Yang has worked in so many ways to support me and our family. I am deeply grateful for her love, tolerance of irregular daily schedules, caring for our child, xx and being the hand to hold throughout my life. My child Vincent has shown me the joy of learning, exploration, and accomplishment, especially by waking me up early every morning. I dedicate my thesis to my parents who have given me (and my brother) everything; to my wife for the promise of our future of always being together; and in memory of my grandmother who took care of me in all possible ways in my childhood. 1 Chapter 1 Introduction 1.1 Area of focus Digital signal processors (DSPs 1 ) are an integral part of various systems used in a variety of applications because they offer the benefits of wide programmability and noise immunity. An analog-to-digital converter (ADC) serves as the bridge between the analog and digital worlds. It approximates an input signal by quantizing its amplitude to a finite range of discrete values. Traditionally, ADCs uniformly sample an analog signal at a fixed clock frequency. This is the main reason for the synchronous operation of digital circuits, and it facilitates sampling circuit implementation and digital sample reconstruction. However, the negative consequence of uniform sampling is spectral aliasing, which translates any input signal from integer multiples of the sampling frequency down to the baseband and, thus, degrades the signal-to-noise ratio (SNR). In 1 “DSP” in this thesis is used as an acronym for both “digital signal processing” and “digital signal processor”. 2 addition, approximation of the input signal amplitude introduces the amplitude quantization error, which fundamentally limits the lower bound of SNR in an ADC. The scaling of complementary metal–oxide–semiconductor (CMOS) technology has led to exponential growth in the performance of digital circuits and the intrinsic speed of devices, but it has increased the difficulty of analog circuit design. For example, it has reduced the voltage headroom and gain. These limitations are especially challenging from the viewpoint of designing high-dynamic-range ADCs and have encouraged researchers to rethink ADC architecture and its associated computations, which will prevail in future technology trends. Based on these observations, the research objective of this thesis is to employ multidisciplinary approaches that leverage algorithmic, architectural. and circuit-level innovations to devise a new route for performing analog-to-digital conversion and digital anti-aliasing (AA) filtering in a completely nonuniform fashion to substantially reduce the implementation complexity and improve the dynamic range and power/area efficiency, in addition to relaxing the requirements of analog AA filters. 3 1.2 Primary contributions This work explores a new area that combines the unique properties of nonuniform sampling (NUS) and nonuniform discrete-time DSP, which cannot be achieved by employing conventional uniform sampling. Specifically, a new class of NUS ADC architectures is proposed to nonuniformly sample analog input signals, followed by a novel nonuniform DSP to post-process the resultant irregular samples. The proposed architecture evolves not only the new ADC design concept but also the manner in which computations should be performed at the system level. In the proposed architecture, voltage-domain nonuniform sampling reacts spontaneously with input signal activities, which increases the overall system agility and ensures that the input signal is alias-free. This creates a new route to perform AA filtering in the digital domain, which is more reconfigurable and suited for technology scaling. With an analog-equivalent digital computation, the proposed architecture can considerably relax the requirements of analog AA filters. Moreover, because the amplitude quantization noise in the proposed architecture is not aliased by the sampling rate, it can be pushed to a higher frequency, and the out-of-band noise can be filtered using nonuniform signal processing techniques. This improves the dynamic range of the proposed ADC compared to that of conventional 4 uniformly sampled ADCs. Finally, a novel ADC design paradigm in which nonuniform sampling is performed in the phase domain together with time quantization results in a mostly digital implementation, which is better suited for scaling with future technology. 1.3 Thesis overview This thesis is divided into two main parts. The first half focuses on the voltage-domain NUS ADC architectures in Chapter 2 and Chapter 3, and the second half focuses on the phase-domain NUS ADC in Chapter 4. In both sections, we will summarize previous works in the area, analyze and discuss the various problems that must be addressed to achieve high resolution, and present prototype implementations along with measurement results. Chapter 5 concludes the thesis with a few general remarks and suggestions for future work. The first half of the thesis begins with Chapter 2, which provides a background of uniform sampling ADCs and introduces the proposed NUS ADC architecture. The proposed architecture is described, and a theoretical analysis of voltage and time quantization noise is performed to determine the SNR bounds. The filter algorithm is derived, and numerical simulation results are presented to prove the concept. In Chapter 3, we demonstrate two different implementations of the voltage-domain NUS ADC, namely 5 the flash-based and subranging-based architectures. The implementation details of several key building blocks are elaborated, and circuit non-ideality analysis is performed. In the second half of the thesis in Chapter 4, the proposed voltage-controlled oscillator (VCO)-based NUS ADC architecture with phase-domain level crossing is presented. An analysis of the quantization error and the details of the circuit implementations are provided. Two different methods for calibrating the VCO nonlinearity are proposed, and our implementation of the nonuniform DSP with the embedded calibration engine is described. 6 Chapter 2 Nonuniform Sampling ADC Architecture The conventional uniform sampling Nyquist-rate ADC architecture is shown in Figure 2.1(a). An analog AA filter is typically required before uniform sampling to attenuate any unwanted out-of-band signal. In addition, the amplitude quantization noise will be folded without any filtering, resulting in the well-known quantization noise power, LSB 2 /12, where LSB is the least significant bit. The proposed NUS ADC architecture [1], in which the conventional sequence of ADC blocks is swapped, is shown in Figure 2.1(b). The amplitude quantizer is moved to the very first block, and the time information of the sampling instants is subsequently quantized and recorded, where Q[·] represents the time quantization process. Both amplitude and time information are utilized in the nonuniform digital signal processor (NU DSP), which performs AA filtering but in the digital domain. Therefore, it can relax the analog AA filter, as will be discussed in Section 2.3.3. The amplitude quantization noise depicted in Figure 2.1(b) represents the interpolation error generated by a signal reconstruction method, e.g., zero-order hold (ZOH), in the digital 7 (a) (b) Figure 2.1: (a) Uniformly sampled Nyquist-rate ADC and (b) proposed nonuniform sampling ADC. AA filter (DAAF), and there exists a tradeoff between the complexity of the reconstruction method and the number of levels in the amplitude quantizer. The time quantization noise, which can be ascribed to the finite time resolution, can induce an aliasing effect on the amplitude quantization noise. However, the technology scaling generally can improve the time accuracy. Finally, the proposed NU DSP will output uniform samples that can seamlessly interact with existing synchronous DSPs. Therefore, f s 2 F Amplitude Quantization Noise f Signal Synchronous DSP Analog Input Amplitude Quantization Fs Uniform Sampling Analog AA Filter Conventional Nyquist-Rate ADC f x(t) NAQ-bit f Amplitude & Time Quantization Noise f Signal s 2 F Nonuniform DSP Synchronous DSP Proposed Nonuniform Sampling ADC x(tk) Q[tk] f f Analog Input Analog AA Filter (relaxed) x(t) Amplitude & Time Quantization NAQ-bit 8 Figure 2.2: Model of additive amplitude and time quantization noise in the proposed ADC. at the top level, the proposed NUS ADC architecture appears a uniformly sampled ADC, even though it internally performs processing in a nonuniform domain. 2.1 Quantization noise modeling The amplitude quantizer can be implemented using an N AQ -bit level-crossing quantizer, where 2 N AQ − 1 comparator thresholds or detection levels divide the full-scale input range from −A to +A into 2 N AQ equally spaced intervals. Whenever a band-limited input signal crosses any of these predefined thresholds, nonuniform samples are generated and their amplitude information is recorded, that is, sampling and amplitude quantization are performed simultaneously. If the average sampling rate of nonuniform sampling satisfies the Nyquist rate, aliasing can be prevented and perfect reconstruction facilitated [2], [3]. In a practical case, a level density may always be found that guarantees this average sampling rate for a signal with an adequate level-crossing rate. A relationship between level density and the average sampling rate was discussed in the Analog Input NU DSP Amplitude Quantization AQ Time Quantization TQ 9 (a) (b) (c) (d) Figure 2.3: Input sinusoid of time period T (dotted line) and its reconstruction (solid line) from points generated by the level-crossing quantizer, along (a) comparator thresholds versus (b) half LSB shifted from comparator thresholds. Quantization error versus input signal using (c) comparator thresholds versus (d) half LSB shifted from comparator thresholds. literature [4]. However, the computational complexity of this error-free reconstruction algorithm is high. Therefore, for ease of implementation, the performance of the proposed NUS ADC is analyzed using the simplest reconstruction algorithm, i.e., ZOH, -A/4 Amplitude T/2 T/4 Time 0 A/4 A/2 3A/4 A -A/4 Amplitude T/2 T/4 Time 0 A/4 A/2 3A/4 A Error (LSB) 0 A/2 A -A/2 -A Input Signal (Amplitude) -1 -0.5 0 0.5 1 Error (LSB) 0 A/2 A -A/2 -A Input Signal (Amplitude) -1 -0.5 0 0.5 1 10 which provides a lower performance bound and better understanding of the limitations of this ADC architecture. As shown in Figure 2.2, to model the errors in the NUS ADC architecture, they are separated into an additive amplitude quantization noise (AQ) given signal reconstruction algorithm of ZOH interpolation, and time quantization noise (TQ). Thus, the quality of the reconstructed NUS ADC outputs can be characterized by both amplitude and time quantization noise to better understand the signal-to-quantization-noise ratio (SQNR) bounds of the NUS ADC architecture. Modeling of amplitude quantization noise due to the ZOH interpolator in the proposed NU DSP is first discussed, and its SQNR is derived in approximate forms. The time quantization effects are examined later. 2.1.1 Amplitude quantization noise characteristics In terms of signal reconstruction, ZOH uses horizontal reconstruction levels and can be done using two different methods shown in Figure 2.3. The difference between them is a half LSB shift in the reconstruction levels. Studies [5] [6] [7] have used the actual 2 N AQ − 1 detection levels as the reconstruction levels [Figure 2.3(a)], which increases the quantization error [Figure 2.3(c)]. Therefore, the DAAF in the proposed NU DSP uses reconstruction levels shifted a half LSB upward and downward from the detection levels [Figure 2.3(b)], which ensures there exist 2 N AQ reconstruction levels. This limits the 11 quantization error to half LSB for the entire input signal range [Figure 2.3(d)]. Notably, the implementation requirement is the same in both cases because both cases use N AQ bits and 2 N AQ − 1 comparators. The amplitude quantization noise aq(x) is defined as the amplitude difference between the input signal x and the ZOH-reconstructed signal. The value of LSB is assumed to be normalized to one, such that the full-scale amplitude A = 2 N AQ−1 . From the sawtooth profile illustrated in Figure 2.3(d), the amplitude quantization noise can be decomposed into a Fourier series of x. Upon analyzing the sinusoidal input case in which x(t) = Asin(ω 0 t), aq(x) becomes [8] [9] 1 1 0 sin ( ) sin((2 (2 ( )) ( () ) ) 1) k m m kx t aq x t k aq t A m t π π ω ∞ = ∞ = ≡−= −− = ∑ ∑ (2.1) where 21 1 2 (2 ) mm k A J kA k π π ∞ − = = ∑ (2.2) and J 2m−1 (·) is the Bessel function of the first kind of order 2m − 1, as obtained from the Jacobi–Anger expansion in (2.1). Equation (2.1) shows that the quantization noise is the sum of all odd harmonics of the input signal frequency, including the fundamental. 12 Figure 2.4: Power spectral density of quantization noise for sinusoidal input passed through a 4-bit level-crossing quantizer shown here on a logarithmic frequency scale. Therefore, aq(t) is periodic, and its period is equal to that of the input sinusoid, which is 1/f 0 or 2π/ω 0 . aq(t) can now be expressed as a Fourier series in time to analyze the spectral distribution of energy 0 () ju t u u aq t C e ω ∞ = −∞ = ∑ (2.3) -40 -35 -30 -25 -20 0 Harmonic Number ( ) ff 47 95 1 3 5 7 hp 3hp 2hp -20 -25 -30 -35 -40 AQ Quantization Noise PSD ( ) (dB/Hz) Sf 13 Figure 2.5: SFDR versus number of bits when using different interpolation techniques. where 1 , when is odd. 0 , when is even. (2 ) π π ∞ = = = ∑ u k u u j Cu u J kA k u (2.4) This value of C u and the fact that |C u | = |C −u | are used to obtain the single-sided power spectral density (PSD) of the amplitude quantization noise as 20 30 40 50 60 70 80 ZOH 1st order 2nd order 2 3 4 5 6 7 8 Number of Bits SFDR (dB) 80 70 60 50 40 30 20 ZOH 1 st order 2 nd order 14 2 AQ 0 2 1,3,5,... 1 (2 ) 2 ( ) ( ) u uk J kA S f f uf k π δ π ∞ ∞ = = = − ∑∑ (2.5) where δ denotes the Dirac delta function. The value 2πA = 2 N AQ π is of considerable interest. It is referred to as h p and its corresponding frequency 2πAf 0 is referred to as f p . Figure 2.4 shows a plot of S AQ (f) versus. harmonic number f/f 0 for a 4-bit quantizer (h p = 50) obtained by setting the upper limits of 100 and 100h p (i.e., 5000) for the summations over k and u, respectively. The terms beyond these values in (2.5) are negligible relative to the other terms. The following inferences can be made from (2.5) and Figure 2.4. First, the Dirac delta function confirms that the amplitude quantization noise aq(t) consists of discrete tones at the input frequency f 0 and its odd harmonics only, as predicted using the time-domain expression in (2.1). Notably, the noise tone at f 0 will only cause slight changes in the signal amplitude and phase. It will not be considered noise in the context of SQNR. Therefore, the analysis will consider noise content at frequencies starting from 3f 0 . Second, J u (x) reaches its global maximum (which is the first local maximum) for u ≈ 0.95x [10]. This explains the notable characteristic of “high-frequency energy maxima” that occurs at harmonic numbers close to integer multiples of h p , as shown in Figure 2.4. Moreover, Figure 2.4 confirms that maximum noise energy is present at the kth harmonic, 15 (a) (b) Figure 2.6: Comparison of (a) Ŝ AQ (f) with S AQ (f) by using a linear frequency scale and (b) P ̂ AQ (f) with P AQ (f) by using a logarithmic frequency scale. where k is the closest odd integer to 0.95h p , which determines the spurious-free dynamic range (SFDR) of the NU ADC. In addition to ZOH, other advanced techniques, such as first-order (linear) and second-order polynomial interpolation, can be employed to reconstruct a signal from its nonuniform samples. These techniques can be analyzed theoretically by using approaches analogous to the one used in the ZOH case. Numerical simulations of SFDR by using higher-order interpolators were performed with different numbers of amplitude quantizer 0 hp 2hp 4hp 3hp -10 -20 -30 -40 -50 -60 0 Harmonic Number ( ) ff Noise PSD (dB/Hz) 3 hp 2hp 4hp 3hp 0 -10 -20 -30 0 Harmonic Number ( ) ff Noise PSD (dB/Hz) 16 bits, as shown in Figure 2.5. As expected, SFDR improved with increasing order, which spurred us to explore higher-order interpolators combined with the proposed DAAF algorithm, which is elaborated in Section 2.3.4. 2.1.2 Approximated amplitude quantization noise model Equation (2.1) indicates that the quantization noise waveform aq(t) is essentially phase-modulated by the input x(t). In general, the PSD S C (ω) of a signal c(t) being phase-modulated by p(t), that is, c(t) = A c sin[ω c t + αp(t)], can be approximated as [11] 2 C () 2 cc c A S gg π ω ω ω ω ω αα α − −− = + (2.6) where α is a constant, and ġ(·) denotes the derivative of the distribution function of p(t). If p(t) is a sinusoid with amplitude A p and frequency ω p , ġ becomes [5] 2 1 () . 1 pp pp gz z A A ωπ ω = − (2.7) 17 By using (2.1), an approximated simplified formula can be derived, Ŝ AQ (f), for S AQ (f) by making these replacements: c(t) with aq(t), p(t) with x(t) = Asin(ω 0 t), A c with −1/(πk), α with 2πk, and ω c with zero. Then 0 0 1 2 AQ 33 1 11 ˆ ( ) 1 . 22 k f Sf Af k Af k ππ − ∞ = = − ∑ (2.8) Equation (2.8) presents a simplified function of the quantization noise with double side band, which consists of a series of decaying segments, where the kth segment is defined as the frequency range from (k − 1)f p to kf p . Figure 2.6(a) depicts a comparison of Ŝ AQ (f) with S AQ (f), and Figure 2.6 (b) shows the corresponding noise power profiles P AQ (f) and P ̂ AQ (f) obtained by integrating S AQ (f) and Ŝ AQ (f), respectively, from 0 to f. Equation (2.8) is continuous in terms of frequency over every segment, as opposed to the discrete tones obtained using (2.5). Moreover, the singularities of (2.8) at f = kf p lead to overestimation of the high-frequency energy maxima of (2.5). These effects combine to make P ̂ AQ (f) larger than P AQ (f), and the maximum error between P ̂ AQ (f) and P AQ (f) is approximately 7 dB at h p , after which it remains constant as the noise tones beyond the first segment decay and, compared to the first segment, contribute little to the overall noise power. 18 Notably, when applying a low-pass DAAF, the quantization noise in the low-frequency region is the main object of interest, where P ̂ AQ (f) is a fairly accurate model of P AQ (f). Equation (2.6) was derived by approximating a Taylor series by using its first term. A more accurate approximation can be made by involving the 4th derivatives of ġ with respect to ω [11]. However, the increment in accuracy is small, and the resulting expression is quite complex. Therefore, the use of (2.8) to approximate the amplitude quantization noise is more practical. 2.1.3 SQNR due to amplitude quantization In this section, the SQNR of the proposed NUS ADC is derived based on the amplitude quantization noise models derived thus far. Time quantization effects are ignored here, but they are addressed in Section 2.1.4. It is known that in uniform sampling ADCs, the sampling frequency F s is typically selected to be greater than 2f 0 to satisfy the Nyquist rate, and the frequency band of interest ranges from DC to F s /2. Given that the high-frequency amplitude quantization noise aliases back to the band of interest and makes the noise appear white, the well-known formula SQNR = 6.02N AQ + 1.76 can be derived. Because of the absence of aliasing in the NUS ADC, the PSD of the amplitude quantization noise is the same as that derived using (2.5), starting from the tone at 3f 0 . The PSD must be integrated within the band of interest, that is, from DC to f c , 19 which is the cutoff frequency of the low-pass DAAF. By defining normalized filter bandwidth c = f c /f 0 and using A = 2 N AQ−1 as before, the total noise power P AQ in the passband can be computed as follows: c 2 AQ AQ 2 3,5,7,... 1 0 (2 ) 2 ( ) . f n c u uk Jk P S f df k π π ∞ = = = = ∑∑ ∫ (2.9) Signal power P SIG is given as A 2 /2 = 2 2N AQ−3 . Then, the exact value of the SQNR (in dB) due to amplitude quantization can be computed numerically as a function of N AQ and c as ( ) AQ AQ 1 2 0 AQ 3 SQNR 10log 2 . N P − = (2.10) Notably, because the noise energy is considered starting from 3f 0 , SQNR AQ is infinite when c < 3. This is a direct consequence of the alias-free property of the proposed NUS ADC, which assumes a zero time-quantization step. Although (2.10) gives the exact value of SQNR AQ , a simpler formula is desirable. This can be obtained by replacing P AQ with P ̂ AQ in (2.10), where P ̂ AQ is the total passband noise power obtained by integrating the approximated PSD, Ŝ AQ (f), of (2.8). First, a relationship is established between the discrete tones of S AQ (f) and the continuous form of 20 Ŝ AQ (f). Because the tones in S AQ (f) are spaced 2f 0 apart, each tone can be considered to represent the frequency band from −f 0 to +f 0 in its tone frequency. In other words, the tone at f 0 in S AQ (f) represents the range from DC to 2f 0 in Ŝ AQ (f), tone at 3f 0 in S AQ (f) represents the range from 2f 0 to 4f 0 in Ŝ AQ (f), and so on. Because the first noise tone of S AQ (f) at f 0 is not considered, the integration of Ŝ AQ (f) should start from 2f 0 , and it is expressed as follows: c 0 c 0 AQ 3 AQ 0 2 3 1 0 2 2 11 ˆ . 1 ˆ 2 2 ( ) π π ∞ = = − = ∫ ∑ ∫ f k f f f P df Af k f Af k df Sf (2.11) Then AQ SQNR can be calculated as 10log 10 (2 2N AQ−3 /P ̂ AQ ). However, as depicted in Figure 2.6(b), P ̂ AQ overestimates P AQ and, therefore, AQ SQNR is lower than the real SQNR AQ obtained using (2.10). An empirical correction factor will be introduced later to account for this approximation error. With the low-pass DAAF, the limiting value of the summation over k is k s , such that 2πA(k s − 1) < c < 2πAk s . The term k = k s can be expressed as 21 0 0 c c s 1 2 AQ 3 3 22 s s s s 22 ss s 00 0 2 2 1 ˆ 1 arcsin 22 2 arcsin arcsin . 2 2 2 2 k f f f f ff P df Af k Af k k Af k c k Ak Ak π π ππ ππ π − = − = = − ∫ (2.12) While integrating for the values of k < k s , the frequency band under consideration is the kth segment, which ends at kf p = 2πkAf 0 . Thus, for the terms in which k < k s , 0 AQ 22 2 22 0 2 1 ˆ arcsin arcsin . 2 22 22 k p f kf f P k Af k k k Ak π π ππ π = = − (2.13) The total noise power P ̂ AQ can be now computed from (2.12) and (2.13) as s ss AQ AQ 1 1 2 22 2 2 11 ss ˆ ˆ 11 2 1 arcsin arcsin . 22 22 k k k kk kk PP c k k Ak k Ak π π ππ π = − = = = =+− ∑ ∑∑ (2.14) For most practical applications, the filter bandwidth of interest is small, that is, c << h p , which implies that k s = 1. By writing A = 2 N AQ−1 , (2.14) can be reduced to 22 Figure 2.7: Comparison of NUS ADC SQNR AQ with corrected AQ SQNR and conventional ADC SQNR as c varies for 4-, 6-, and 10-bit quantizers, whose h p values are denoted as h p4 , h p6 , and h p10 , respectively. AQ AQ AQ 2 ˆ arcsin arcsin . 22 22 NN c P π ππ = − (2.15) AQ SQNR can now be computed as 10log 10 (2 2N AQ−3 /P ̂ AQ ). Because both c and 2 are considerably smaller than h p , the arcsin(·) and log 10 (·) functions can be approximated by using their Taylor series as 3 20 50 (hp4) 10 100 400 (hp7) 1000 3200 (hp10) c (Normalized Filter Bandwidth) 100 90 80 70 60 50 40 30 SQNR (dB) NAQ = 4 NAQ = 7 NAQ = 10 Actual SQNRAQ of (3.10) Approximate SQNRAQ of (3.18) Conventional Nyquist ADC 23 ( ) 2 1 arcsin 1 6 x x x ≈+ (2.16a) ( ) 10 10 log 1 log 0.43 . xx e x +≈ ≈ (2.16b) The final expression of AQ SQNR then becomes ( ) AQ 2 AQ AQ 0.07 SQNR 9.03 2.87 10log( 2) 2 4 . 4 = + − −− + + N N c c c (2.17) Notably, (2.17) is valid only for c > 3, as explained earlier. Numerical simulations show that (2.17) closely resembles (2.10) when c is small; however, the error between the two equations, defined as SQNR AQ − AQ SQNR , increases as c increases because of the low accuracy of the approximations of (2.16a) and (3.16b). In fact, the error reaches a maximum at c = h p because P ̂ AQ (f) is larger than P AQ (f), as explained in Section 2.1.2. Given that h p increases as N AQ increases, the rate of increase in error with c decreases at larger values of N AQ . On the basis of these observations and the results of numerical simulations, an empirical correction factor is incorporated to adjust the coefficient of the term −log(c − 2) in (2.17). The coefficient is lower than 10 for low values of N AQ , and it asymptotically approaches 10 as N AQ increases, exhibiting exponential behavior. The objective is to achieve an accurate approximation of AQ SQNR that is good for the entire 24 range of 3 ≤ c ≤ h p . By using curve-fitting techniques, we incorporate the adjusted coefficient of −log(c − 2) into (2.18) to obtain ( ) ( ) AQ AQ 2 AQ AQ 0.07 SQNR 9.03 2.87 10 12 1.35 log( 2) 2 4 . 4 − = + − −⋅ −− + + N N N c c c (2.18) The curve-fitting techniques used herein were optimized for the more practical cases, in which the bandwidth of the low-pass filter is low, that is, c is low, and N AQ is small in low-complexity implementations. Therefore, SQNR approximation in those regimes is superior, as illustrated in Figure 2.7. The figure also shows that the SQNR of the proposed NUS ADC is significantly superior to the SQNR of conventional uniform sampling Nyquist ADCs. Further comparison with uniform sampling ADCs is given in Section 2.1.5. 2.1.4 Time quantization noise modeling The quantization noise models discussed thus far are based only on amplitude quantization. Therefore, the derived equations for SQNR AQ assume that the time information of a sample can be known with infinite precision. In reality, the time quantizer has a resolution T Q that causes the amplitude quantization noise to fold in the 25 Figure 2.8: Variation of the SQNR of a 6-bit quantizer with c TQ for different values of c. frequency spectrum in the form of time quantization noise. The single-sided PSD of the time quantization noise is ( ) QQ AQ 1 ( ) TT m S f S f mf ∞ = = + ∑ (2.19) where f TQ = 1/T Q . The double-sided filter passband covers the frequencies from −f c to +f c . The noise power folding back into this passband from the mth shifted copy of the noise 40 50 60 70 80 200 400 600 800 1000 1200 1400 1600 1800 = QQ 0 Time Quantizer Accuracy ( ) TT c ff SQNR (dB) c = 2 c = 3.2 c = 7.2 26 Figure 2.9: Comparison of SQNR with the real SQNR for the 4-, 6-, and 8-bit quantizers, as time quantizer accuracy c TQ varies, with c fixed at 3.2. can be determined by integrating S AQ (f) over the interval (mf TQ − f c ) to (mf TQ + f c ). Then, the total noise power P Q becomes c Q c Q Q AQ TQ AQ AQ 1 ( ) T T mf f m mf f P P P P S f df + ∞ = − = + = + ∑ ∫ (2.20) 200 400 600 800 1000 1200 1400 1600 1800 = QQ 0 Time Quantizer Accuracy ( ) TT c ff 2000 25 35 25 45 55 65 75 SQNR (dB) Real SQNR of (3.21) Approximate SQNR derived from (3.23) n = 8 n = 6 n = 4 27 Figure 2.10: Modeling Ŝ AQ (f) of (2.8) as a decreasing exponential. from which the final value of SQNR can be calculated as AQ 23 SIG 10 10 QQ 2 SQNR 10log ( ) 10log ( ) − = = N P PP . (2.21) Figure 2.8 shows the variation of SQNR with c TQ = f TQ /f 0 under different normalized filter bandwidths c, which better shows the time-quantization effects. When c < 3, P AQ is zero, and only P TQ is present, which consistently decreases as c TQ increases because of a 0 Harmonic ( ) ff 0 50 100 150 200 -25 -30 -35 -40 -45 -50 -55 -60 Quantization Noise PSD (dB/Hz) Approximate PSD of (3.8) Uniform Distribution Model Exponential Curve-fit Model 28 reduction in noise folding. This leads to a continuous increase in SQNR. When c > 3, P AQ is not zero, and it dominates over P TQ for large values of c TQ , where a negligible amount of noise folds back. This causes SQNR saturation, as shown in Figure 2.8 for the 6-bit case. The limit of the summation over m in (2.20) is set to 10, beyond which any changes are negligible. When c TQ ≈ kh p , where k is an integer, shifted copies of the high-frequency noise maxima close to integer multiples of h p will fall inside the filter passband. This effect is more pronounced for low values of k, such as 1, 2, and 3. A similar phenomenon can be observed when h p ≈ kc TQ as a shifted copy of the first noise maximum at h p fold backs to the passband. These effects degrade the SQNR, as shown by the downward spikes at kh p and h p /k in Figure 2.8 and Figure 2.9, respectively. Equation (2.20) is not suitable for manual calculations, even if P AQ and S AQ (f) are replaced with their approximations, P ̂ AQ and Ŝ AQ (f), respectively. A practical way to compute the summed integral of (2.20) is by modeling Ŝ AQ (f) as a decreasing exponential of the form af −b because it comprises an infinite number of decaying segments. To achieve this, the area under the curve for each segment is found and modeled using a constant value equal to its area divided by f p . This approach preserves the noise power of each segment. Because the initial segments contribute greater amounts of passband noise, we calculated a and b by taking the first two segments and finding the points of 29 Figure 2.11: SQNR improvement between the proposed NUS ADC with time quantizer accuracy of c TQ ∼ 9900 and different uniform oversampling ADCs but the same average sampling rate. intersection of the constant value with the actual Ŝ AQ (f) curve. Suitable approximations were made, as f c << f TQ to finally obtain b ≈ 2 and a ≈ 0.1f p . The entire process is depicted in Figure 2.10, and it yielded 0 AQ 22 0.1 0.63 ˆ ˆ ( ) p f Af Sf ff = = . (2.22) Notably, the correction to ignore the noise tone at f 0 was not applied because it had little effect on this approximation. By replacing S AQ (f) and P AQ in (2.20) with their approximations from (2.22) and (2.14), respectively, we get 2 5 6 7 8 4 3 Amplitude Quantizer Bits 90 80 70 60 50 40 20 30 10 0 SQNR Improvement (dB) Uniform Oversampling ADC 4-bit 1 st -order ΔΣ ADC 1-bit 4 th -order ΔΣ ADC 4-bit 4 th -order ΔΣ ADC 30 Q Q AQ 22 1 1.26 1 ˆ ˆ m T Ac PP cm ∞ = = + ∑ (2.23) where P ̂ AQ can be easily calculated using (2.15) instead of (2.14) for the typical case of f c << f p . Finally, the approximated SQNR can be computed as SQNR = 10log 10 (2 2N AQ−3 /P ̂ Q ). Figure 2.9 compares SQNR with the real SQNR given by (2.21) as c TQ varies for several typical values of N AQ and c = 3.2. The comparison highlights the general good agreement between the approximated SQNR and the real SQNR for typical values of c TQ . However, when c TQ is considerably smaller than h p (empirically estimated as c TQ < h p /2), a large portion of the first noise PSD segment (≤ h p ) is aliased back to itself, resulting in inaccurate SQNR approximation. This can be ascribed to the fact that at higher values of N AQ , greater numbers of nonuniformly sampled points are generated, and the time intervals between these points are reduced. In such cases, SQNR should be determined based on the numerical simulations instead of using the analytical expression for computing SQNR . Therefore, the SQNR plots in Figure 2.9 start from h p /2. 31 2.1.5 Comparison with uniform sampling scheme As the proposed NUS ADC architecture nonuniformly samples an analog input based on level-crossing events, its instantaneous sampling rate varies with the characteristics of the input signal, for example, amplitude and frequency, and the number of levels in the quantizer. For example, the average sampling rate of a full-swing sinusoidal input with a 3-bit amplitude quantizer is seven times the Nyquist sampling rate. This ratio is defined as the average oversampling ratio (OSR avg ). Then, the SQNR of the proposed NUS ADC is compared with that of the conventional uniform sampling ADCs that generate the same average sampling rate. To provide a more comprehensive comparison, conventional oversampling ADCs are considered with and without noise shaping. A numerical simulation with a range of amplitude quantizer bits and fixed time quantization accuracy is performed for the NUS ADC by using ZOH interpolation. The SQNR improvement, computed from DC to the 2nd Nyquist zone (twice the input frequency), over different uniform oversampling ADCs is plotted in Figure 2.11. It shows that the improvement is greater when the number of amplitude quantizer bits is lower. Compared to higher-order delta-sigma ADCs, the SQNR improvement is weaker when the number of amplitude quantizer bits is higher. Note that both the proposed NUS ADC and the delta-sigma ADCs incur an underlying implementation overhead in the regime of higher bit-number amplitude quantizers. For example, a higher average sampling rate requires higher levels 32 of asynchronous data capture in case of the proposed NUS ADC. By contrast, in case of the delta-sigma ADCs, it demands operational amplifiers with gain-bandwidth products a few times higher than the sampling rate for achieving proper output settling. As a result, for a more practical hardware implementation of the proposed NUS ADC, the region of interest lies in the lower bit-number amplitude quantizer regime, for example, the silicon prototype in [12] uses only a 4-bit amplitude quantizer. In addition, a uniform sampling ADC constantly performs sampling at the maximal rate, regardless of the input characteristics, thereby providing less flexibility, while the proposed NUS ADC can automatically adjust its instantaneous sampling rate according to the input signal characteristics. In the case of a uniform sampling ADC, it is challenging to vary the sampling clock frequency based on the input signal characteristics in real time. 2.2 Design considerations and limitations While the focus of this chapter is to explore the theoretical bounds of the proposed NUS ADC architecture, a few practical design considerations and examples, as discussed in [12] and [13] are summarized here for completeness. First, in a representative embodiment, the number of comparators increases exponentially as the number of 33 amplitude quantizer bits increases (similar to the conventional flash ADC architectures), and the accuracy of the amplitude quantization levels can be limited by manufacturing variability. Therefore, in applications requiring high dynamic range, a comparator offset calibration technique can be applied [12]. Additionally, the heightened amplitude quantization levels shorten the time between nonuniform samples, that is, they increase the maximum instantaneous sampling rate. Parallel processing on these nonuniform samples for each amplitude level can be executed to achieve high throughput [14], and in this case, the instantaneous sampling rate can be as high as 45 GS/s. Nevertheless, these factors impose an upper limit of amplitude quantizer resolution in practical implementations. By contrast, time quantization resolution should scale with the maximum input frequency for a given reconstruction fidelity. For a given accuracy of time quantization, it imposes an upper limit on the signal bandwidth. In addition, aside from the quantization noise, which is defined by the time quantizer resolution, the precision of time measurement depends on several other factors, such as clock jitter and differential nonlinearity (DNL) of the quantizer. Note that technology scaling generally improves time accuracy. Using the current state-of-the-art hardware, 450-fs time quantization [15] has already been demonstrated. The achievable signal bandwidth and resolution are expected to improve as technology advances thanks to increasing device intrinsic speeds. 34 (a) (b) Figure 2.12: (a) Conventional digital FIR filter. (b) Proposed DAAF in the NU DSP. 2.3 Nonuniform digital signal processor The proposed NU DSP simultaneously performs several important functions, including a) digital AA filtering, b) conversion of input nonuniform samples to output uniform samples, and c) decimation to a uniform resampling rate. The unique feature of x[k] x(t) s[n] Conventional Digital FIR Filter c0 c1 cN-1 cN y[k] t x[k] s rs F F M = f Signal Noise ( ) X f 1 τ 1 τ − Filter Response Ω () Y Ω π - π ω () S ω Noise Folding τ τ τ s F x(tk) x(t) s[n] Proposed Digital AA Filter cN cN-1 c1 c0 y(t) t x(tk) rs rs 1 F T = f Signal Noise ( ) X f π - π ω () S ω Noise Folding Filter Response ( ) Yf N τ 1 N τ − 1 τ f s,avg F 35 alias-free nonuniform sampling and the emulation of an analog filter response in the DAAF enable the NU DSP to perform AA filtering on the input signal in the digital domain. Moreover, the same DAAF can be used to remove quantization noise and improve SQNR compared to that achieved by conventional uniform sampling ADCs, as shown in Figure 2.11. In this section, the filter algorithm is derived assuming ZOH interpolation for the input signal and the derived algorithm is extended to higher-order interpolations and various filter responses. 2.3.1 High-level concept and algorithm of nonuniform DSP Figure 2.12 shows a comparison of the conventional digital FIR filter with the proposed DAAF, which performs AA filtering and converts nonuniform samples to uniform samples with a fixed resampling rate F rs . A decimator is placed at the output of the conventional FIR filter to achieve the same output resampling rate, that is, a decimation factor of M = F s /F rs . For simplicity, the effect of quantization noise is excluded here. The analog input is composed of the desired signal component (white triangle) and the band-limited noise (shaded box). In case of the conventional digital FIR filter shown in Figure 2.12(a), the fixed sampling rate F s and tap delay (τ = 1/F s ) cause spectrum aliasing and noise folding. However, the proposed DAAF shown in Figure 2.12(b) leverages alias-free nonuniform sampling and constructs a time-varying, 36 signal-dependent FIR filter whose tap delay matches the time gap of nonuniform samples. Thus, the filter response does not repeat at integer multiples of 2π, that is, F s,avg . The following annotations are used for deriving the filter algorithm: the analog input signal to be filtered is given in the time domain and denoted by x(t). The desired filter transfer function is H(ω) in the frequency domain, and its impulse response is h(t). The continuous-time analog filtering process can be represented mathematically as the convolution of x(t) with h(t) ( ) ( ) ( ) τ ττ ∞ −∞ = − ∫ y t x ht d (2.24) where 1 () ( ) 2 ω ωω π ∞ −∞ = ∫ j t ht H e d . (2.25) Although h(t) can be any arbitrary impulse response designed to achieve any desired attenuation profile, an ideal brick-wall low-pass filter with the corner frequency ω c = 2πf c is considered here as a representative case. Therefore, the time domain impulse response is the normalized sinc function 37 Figure 2.13: Time-domain view of nonuniform output samples. ( ) cc sinc ωω ππ = ht t . (2.26) The convolution in (2.24) can be rewritten as the sum of integral sections from t k to t k+1 as ( ) ( ) ( ) 1 cc 1 sinc ωω τ τ τ ππ + ∞ = = − ∑ ∫ k k t k t yt x t d (2.27) where t k is the instant of time corresponding to the kth level-crossing point, as shown in Figure 2.13. According to the results of ZOH reconstruction, the amplitude quantizer output has discrete amplitudes, and it remains constant between level-crossing points. Therefore, the tk 2, kn t − ∆ (x'k-1, tk-1) rs ( 1) nT − rs nT Trs rs ( 1) nT + (x'k, tk) 1, kn t − ∆ , kn t ∆ 1, kn t + ∆ (Nonuniform Samples) (Uniform Resampled Instant) (x'k+1, tk+1) 38 amplitude of x(τ) in each interval from t k to t k+1 is a constant value x k , which contains a half LSB shifted from x' k and can be separated from the convolution integral. The variable is changed to reference all t k values to t by setting t' = τ − t, Δt k = t k − t, and Δt k+1 = t k+1 − t, resulting in ( ) 1 cc 1 sinc ωω ππ + ∆ ∆ ∞ = ′′ = ∫ ∑ k k t k k t y x t dt t . (2.28) In a real implementation, the filter duration should be finite in time to prevent the filter from using an infinite number of nonuniform samples, that is, the filter should be restricted to the set t k ∀ k : |Δt k | ≤ t d . Thus, the time duration of the filter is set to 2t d . To achieve sharper rolloff and superior stopband attenuation, the impulse response h(t) is multiplied with a nonrectangular windowing function w(t). By using the Hann window centered at t = 0, we get ( ) d 1 1 cos 2 π = + t w t t . (2.29) 39 Upon including w(t) in the convolution integral, (2.28) can be rewritten as ( ) 1 cc d d sinc 1 cos 2 . : k k t k k t k t y x t dt t kt t t ωω π ππ + ∆ ∆ ′ ′′ = + ∀ ∆≤ ∫ ∑ (2.30) According to (2.30), the sinc and cosine functions are completely decoupled from the input, and the integral can be evaluated and represented using the sine-integral function Si(x), which is defined as ( ) 0 sin Si = ∫ x t x dt t . (2.31) 40 On integrating (2.30) and applying limits, we get ( ) ( ) ( ) { c1 c c 1c dd c 1c dd Si Si 4 2 Si Si Si Si k kk k kk kk x yt t t tt tt t t t t ωω π ππ ωω π π ωω + + + = ∆ − ∆ + + ∆ − + ∆ −∆ − −∆ + ∑ d : . k kt t ∆ ∀≤ (2.32) Although the computations utilize nonuniform samples, the proposed filter algorithm is only evaluated at the uniformly resampled time instants to ensure that it can be processed using a synchronous DSP. The resampled output after filtering can be computed as ( ) rs , d [] : = = ∆ ⋅∀ ≤ ∑ kk k k n sn y n x g k t Tt (2.33) where , rs ∆= − k n k t t nT . (2.34) 41 (a) (b) Figure 2.14: Filter response of (a) conventional digital FIR filter and (b) proposed DAAF with an input of band-limited white noise up to 2F rs and filter corner at 0.25F rs . g k is obtained by dividing the term inside the curly brackets in (2.32) with 4π, where n is a positive integer, and T rs is the inverse of the resampling frequency F rs . Equation (2.33) can be viewed as a time-varying, signal-dependent FIR filter, where the tap delays and weights change dynamically as functions of nonuniform time instants relative to the resampling time nT rs . This is the key to alias-free operation. With infinite time quantization accuracy and time duration of the filter, (2.28) becomes equivalent to (2.24), Normalized Frequency ( ) π 2 1 0 3 4 20 0 -20 -40 -60 -80 -100 Magnitude (dB) ND = 8 (Rect. window) ND = 16 (Rect. window) ND = 16 (Hann window) 20 0 -20 -40 -60 -80 -100 Magnitude (dB) -120 Normalized Frequency ( ) π 2 1 0 3 4 0.5 1.5 2.5 3.5 ND = 8 (Rect. Window) ND = 16 (Hann Window) ND = 16 (Rect. Window) 42 except that x(τ) is replaced with a ZOH representation of the input. Therefore, the filter output s[n] is equivalent to the sampled output of the continuous-time convolution between the input signal and the analog filter response. To validate the frequency response of the proposed AA filter, band-limited white noise with frequency up to 2F rs and peak lower than full scale is used as the test input signal, and an 8-bit ideal nonuniform sampling ADC is simulated with a very fine time quantization step, such that T Q << T rs . The corner frequency of the low-pass filter is set to 0.25F rs , and simulation results are shown in Figure 2.14. To illustrate the effect of finite time duration of the filter, t d is normalized to π/ω c and quantified as d c d c ND 2 π ω = = t ft . (2.35) The term ND denotes the number of zero crossings of the sinc impulse response, and it is a measure of filter sharpness. Higher ND values lead to narrower transition bands. The windowed filter responses obtained by utilizing a Hann window are shown in Figure 2.14 as representative examples, where the input is band-limited white noise up to 0.5F rs and the filter corner is at 0.25F rs with ND set to 16. Depending on the specifications, suitable 43 (a) (b) Figure 2.15: Power spectrum of (a) analog input and (b) resampled output with and without the proposed DAAF. time duration of the filter and window function can be selected to obtain a desired filter response. This proves the flexibility of the proposed filter algorithm. 2.3.2 Alias-free property validation A unique property of the proposed filter algorithm is that it attenuates any out-of-band signal before it folds into the Nyquist band due to uniform resampling, that is, analog input Normalized Frequency ( ) π 0.8 0.4 0 1.2 2 0 -50 -100 -150 Amplitude (dB) 1.6 Analog Input w/o filter with filter Normalized Frequency ( ) π 0.8 0.4 0 1.2 2 0 -50 -100 -150 Amplitude (dB) 1.6 with Filter without Filter 44 AA filtering takes place. To validate this alias-free property, a blocker test is performed in the simulation, in which a modulated input signal and an unwanted blocker are employed. The filter response is configured with a large t d and Hann window to minimize the effect of finite time duration, and a high time accuracy is set to reduce time quantization noise. The simulation setup is the same as the one in Figure 2.14, except that the band-limited white noise is now located in the first Nyquist zone along with a 60-dB-higher blocker at 0.625F rs . The overall signal amplitude is adjusted to be within the full scale of the NUS ADC to avoid any amplitude clipping, that is, ideal automatic gain control (AGC) is assumed. The final resampled outputs with and without the proposed AA filter are compared, and their power spectra are plotted in Figure 2.15. Both the blocker and the amplitude quantization noise can be attenuated significantly by using the proposed filter algorithm before they are aliased. 2.3.3 Relaxed analog anti-aliasing filter requirements In addition to the reconfigurability and the advantages of technology scaling, the possibility of using a DAAF relaxes the analog AA filter requirements. For example, when a large out-of-band blocker is present near the pass band, a conventional Nyquist-rate ADC requires an analog AA filter to attenuate the blocker to be lower than the desired signal for maintaining the required SNR after uniform sampling, that is, 45 spectral aliasing. Additionally, the filtered signal is typically amplified using a programmable gain amplifier (PGA) to utilize the full dynamic range of the ADC, that is, the input-referred noise is suppressed. These requirements can be relaxed in the NUS ADC architecture because of its alias-free sampling and digital AA filtering. For instance, considering a voltage-domain amplitude quantizer has a full-scale input of 1 V, an input-referred thermal noise of 1 mV RMS , and a timing jitter of 1 ps, there exists a desired signal with 20-MHz bandwidth when using a 50-dB-higher blocker at 80 MHz. A conventional Nyquist-rate ADC can achieve an SNR of 40 dB, but it demands 90-dB attenuation on the blocker with a 50-dB PGA gain. However, the proposed NUS ADC with 15 quantization levels requires only 20-dB attenuation on the blocker with a 20-dB PGA gain to suppress the input-referred noise. This can reduce the costs of analog AA filters and PGAs. 2.3.4 Reconfigurable signal reconstruction Thus far, ZOH has been assumed as the interpolation method for signal reconstruction. The amplitude quantization noise due to deviation of the term x(τ) in (2.24) generates harmonic tones, as discussed in Section 2.1.1. With relaxed signal reconstruction requirements, ZOH is a reasonable choice for minimizing computation. In addition, the amplitude quantizer can be reconfigured into fewer levels to not only 46 minimize the implementation cost but also reduce the number of nonuniform samples for reducing the digital signal post-processing load. With more stringent signal reconstruction requirements, it is possible to reduce the amplitude quantization noise by using higher-order interpolations combined with the proposed filter algorithm to enhance the quality of the reconstructed signal, as illustrated in Figure 2.5. The only overhead is calculation of the coefficients of the interpolation function of each section when a new level-crossing sample is generated. The output is evaluated at the resampled instants by using the existing nonuniform samples. In the following derivations, a generic second-order piecewise polynomial is used as an example to approximate the input signal x(t) between adjacent nonuniform samples. Therefore, the input signal can be written as () () = ∑ k k xt x t (2.36) and each function x k (t) is a piecewise polynomial defined in [t k , t k+1 ], where k = 0, 1, 2,… For a second-order polynomial, 2 ()= ++ k k k k x t a t bt c (2.37) 47 where a k , b k , and c k are the coefficients defined in [t k , t k+1 ] and can be calculated using existing numerical approaches, such as Lagrange interpolation. Therefore, (2.30) can be modified as ( ) ( ) ( ) ( ) 1 cc 2 d d sinc 1 cos . : k k k k k t k t k t y tt tt t dt t k ta tt bc ωω π ππ + ∆ ∆ ′ ′′ ′ ′ = ++ + ∀ ++ ∆≤ ∑ ∫ (2.38) After some algebraic manipulation, the resampled output s[n] can be expressed as r, d s [] ( : ) n n n k n s n y nT A B t k C t ∀ = = ∆ ≤ + + (2.39) which is a combination of the three terms obtained by integrating t' 2 , t', and the constant term in (2.38), and it involves the sine and cosine functions in addition to Si. When a k = b k = 0, the equation reduces to the ZOH case, where A n = B n = 0, and C n is equal to the right-hand side of (2.33). Similarly, first-order interpolation can be applied when a k = 0. Different embedded interpolation options provide another degree of freedom to the proposed filter algorithm. 48 (a) (b) (c) (d) (e) Figure 2.16: (a) Spectrum of the analog input where two blockers are located at 0.55F rs and 0.98F rs , and the band-limited signal is located between 0.6F rs and 0.9F rs . (b) and (c) Blockers attenuated by an 11th-order Butterworth band-pass filter and subsampled by an ideal uniformly sampled ADC. (d) Reconstructed signal before processing using the proposed digital AA filter. (e) Subsampled and filtered output. Normalized Frequency ( ) π 0.8 0.4 0 1.2 2 0 -50 -100 -150 Amplitude (dB) 1.6 50 Normalized Frequency ( ) π 2 -50 -100 -150 Amplitude (dB) 1.6 0 1.2 0.8 0.4 0 Analog Filter Normalized Frequency ( ) π 2 -50 -100 -150 Amplitude (dB) 1.6 0 1.2 0.8 0.4 0 Normalized Frequency ( ) π 2 -50 -100 -150 Amplitude (dB) 1.6 0 1.2 0.8 0.4 0 Normalized Frequency ( ) π 2 -50 -100 -150 Amplitude (dB) 1.6 0 1.2 0.8 0.4 0 49 2.3.5 Filter response reconfigurability Thus far, the derivations have focused on the low-pass filter response. However, they can be extended to other responses, such as band-pass filtering, because of digital reconfigurability. This is especially useful for subsampling applications [16], [17]. Conventionally, to perform subsampling, an ADC relies on an analog band-pass filter centered at the carrier frequency with a sharp frequency response or samples at rates higher than the Nyquist rate to avoid any undesirable out-of-band components from being aliased on top of the desired signals. This design constraint limits the practicability of subsampling with uniform sampling. Benefiting from the alias-free property of nonuniform sampling, the proposed DAAF can remove any out-of-band componentsbefore subsampling. In addition to undesired signals presented to the ADC, the proposed AA filter can relax the noise requirements of the amplitude quantizer by using subsampling and improve the value of SNR. However, when a baseband signal of one-sided bandwidth B is located at a center frequency f 0 , because the average sampling rate is proportional to B + f 0 , an increased average sampling rate will increase design costs, as described in Section 2.2. Therefore, the upper limit of the passband signal frequency for subsampling should be bound, similarly to signal bandwidth considerations. 50 (a) (b) Figure 2.17: Subsampling for a sinusoid input at 0.75F rs . (a) Uniform sampling ADC. (b) Proposed NUS ADC architecture with ZOH interpolation, Hann windowed, and ND set to 32. Considering an ideal brick-wall band-pass filter with corner frequencies at ω H and ω L , the output S BPF [n] can be given as CH CL BPF LP LP [] [] [] ωω ωω = = = − s n sn sn (2.40) where S LP [n] denotes the low-pass filter output obtained using (2.39) with the desired interpolation order. To validate the response of band-pass filter, an NUS ADC with a band-limited signal along with two adjacent 60-dB-higher blockers is simulated, and the Normalized Frequency ( ) π 2 -20 -40 -60 Amplitude (dB) 1.6 0 1.2 0.8 0.4 0 -80 -100 Normalized Frequency ( ) π 2 -20 -40 -60 Amplitude (dB) 1.6 0 1.2 0.8 0.4 0 -80 -100 51 subsampled output spectrum is shown in Figure 2.16. The proposed filter with ZOH and ND = 16 yields an attenuation of more than 60 dB on blockers, which would require an 11th-order Butterworth band-pass filter when implemented using the conventional analog approach. The ND values can be adjusted flexibly depending on the requirements to obtain the equivalent 3rd-order and 20th-order Butterworth band-pass filters for ND equal to 4 and 32, respectively. As an illustration of relaxation of the noise requirements of the amplitude quantizer, we examine an NUS ADC case by using an 8-bit amplitude quantizer to subsample a sinusoidal input at 0.75F rs without any amplitude clipping in the presence of additive white Gaussian noise (AWGN). This additive noise can be caused by the intrinsic circuit noise of the amplitude quantizer implementation. With noise characterized by a standard deviation of 0.85 LSB referred at the input, the uniform sampling ADC achieves an SNR of 40 dB after subsampling owing to aliasing of the out-of-band noise, as shown in Figure 2.17(a). When the proposed NUS ADC architecture with the digital AA band-pass filter is utilized (corners at 0.5F rs and F rs ), out-of-band noise is filtered because the average sampling rate is higher than F rs , resulting in an SNR improvement of 29 dB, as shown in Figure 2.17(b). 52 Figure 2.18: Implementation of proposed nonuniform DSP. 2.3.6 One embodiment of the nonuniform DSP Figure 2.18 shows a possible hardware implementation of the proposed NU DSP algorithm using ZOH. A first-in-first-out (FIFO) buffer can be used to store the incoming nonuniform samples, and the final filter output rate can only satisfy the Nyquist rate, that is, twice the signal bandwidth. Furthermore, the desired filter responses evaluated at y, such as sine-integral, can be pre-calculated and stored in lookup tables to reduce the computation cost in real time. Because y is bounded between 0 and t d , the size of the lookup table can be optimized for specific values of ω c and ND. For each filter output Nonuniform Sampling + Amplitude / Time Quantization xk tk, tk+1 ..., tk, tk+1, ... FIFO ..., xk, xk+1, ... nTrs Si(y) Lookup Table Adder Register Frs Filter Output s[n] Nonuniform DSP 53 time instant nT rs , Δt k , and Δt k+1 are computed for all nonuniform samples within the filter duration of nT rs − t d to nT rs + t d . These values are plugged into the filter response values read from the lookup tables. The values are subtracted and multiplied with the incoming nonuniform samples x k and a final accumulator computes the filter output at a rate of F rs . 54 Chapter 3 Nonuniform Sampling ADC Implementation 3.1 Modeling circuit non-ideality To prove the proposed concept, an NUS ADC prototype using a 15-level flash-based voltage-domain amplitude quantizer and a 9-ps time quantizer is implemented with 65-nm CMOS technology [18]. The circuit non-ideality modeling of quantizers in the proposed NUS ADC is depicted in Figure 3.1. The propagation delay variation [13], [19], [20], [21] of the voltage quantizer, which is composed of multiple multi-stage continuous-time comparators connected to different threshold voltages, is derived as a function of the input slope at the level crossing and various other circuit parameters. Ideally, the voltage and time quantizers should generate V in (t k ) and Q[t k ], respectively, where t k is the ideal time instant for level crossing. However, a signal-dependent propagation delay (t pd ) is added to t k , and it can result in the generation of harmonics, 55 Figure 3.1: Model of non-idealities in the front end of NUS ADC. especially during level-crossing quantization [13]. Additionally, the impact of comparator offset, which can lead to distortions in the reconstructed signal, is analyzed. For the time quantizer, SNR degradation due to jitter (t j ) of the time quantizer is considered and added to the time instant at the voltage quantizer output (t VQ ). Finally, the analysis can be extended to model the effect of the noise originating from the voltage quantizer. 3.1.1 Variation of comparator propagation delay For a full-scale single sinusoidal input A FS ·sinω in t, the maximum delay variation can be calculated at the central and topmost quantization levels with the maximum and minimum input slopes, respectively. The comparator model presented in [19] is used herein for delay variation analysis, as illustrated in Figure 3.1. The sinusoidal input is approximated to a ramp with the slope S in , which is the input slope at the threshold Vin(t) Vin(tk) G Vamp Gain Stage Amplitude- Limiting Circuit Vin Vth Vlimit R C Vout NU DSP Voltage Quantizer VQ pd k t tt = + Time Quantizer j t Timing Jitter VQ t Q[·] TQ t TQ Q[ ] t TQ Q[ ] t Bandwidth- Limiting Circuit Multi-stage Comparator 56 Figure 3.2: Time-domain waveform within the comparator model using a ramp input. voltage (V th ). The voltage difference between the input and threshold voltages V in,diff = (V in − V th ), as illustrated in Figure 3.2, is first amplified, that is, V amp = GV in,diff , and then passed on to an amplitude-limiting circuit with output swing from −A max to A max . The last stage is a bandwidth-limiting circuit with the time constant RC = 1/2πf comp , where f comp denotes the comparator bandwidth. Assuming A FS = A max for simplicity, the propagation delay of a single comparator from V in to V out can be obtained by Laplace transformation of a ramp signal applied to the RC network. As shown in the time-domain waveform in Figure 3.2, t 2 is the time at which V limit reaches A max , and t 3 is the time at which V out 0 Vin,diff max A − max A Vamp Vlimit t t0 t1 t2 t3 tpd GSin Vout V 57 reaches zero. Therefore, the propagation delay is defined as the difference between the input and output zero-crossing time instants, that is, t 3 – t 1 . The propagation delay can be derived for the following two cases: max comp in 2 2 max comp max comp pd 3 2 comp in in 22 1 ln ln 1 for 2 π π π π − = + − −≥ Af GS A f A f t e tt f GS GS (3.1) max comp pd in 2 pd 3 2 comp 1 1 for 2 π π −+ =−< A ft GS t e tt f . (3.2) In this flash-based NUS ADC, the comparator is designed with a multi-stage topology to achieve a wide bandwidth and high gain with lower implementation cost [22]. The total propagation delay of a K-stage comparator can be calculated as t pd,tot = pd, 1 = ∑ K i i t , where t pd,i is the single-stage propagation delay of the ith stage. t pd,i can be obtained using either (3.1) or (3.2) by replacing f comp with the bandwidth of the ith stage f comp,i and keeping S in as the input slope in the first stage but replacing G with the accumulated gain acc, 1 = = ∏ i im m GG , where G m is the gain of the mth stage. In this prototype, multiple comparators connected to different threshold voltages are utilized, and their outputs are eventually be converted to a single-ended output. The triggering threshold mismatch of the following single-ended stage between different 58 (a) (b) Figure 3.3: (a) Delay variation and (b) degradation on distortions of various f comp , where spline interpolation is applied as a reference reconstruction algorithm. comparators can introduce an extra delay variation. According to a Monte Carlo analysis, an overall gain of >45 dB is needed to ensure a sufficiently sharp single-ended transition single-tone two-tone 200 400 600 800 1000 1200 Comparator Bandwidth (MHz) 700 600 500 400 300 200 100 0 Delay Variation (ps) single-tone two-tone single-tone two-tone 200 400 600 800 1000 1200 Comparator Bandwidth (MHz) 14 12 10 8 6 4 2 0 Degradation (dB) single-tone two-tone 59 Figure 3.4: Voltage error introduced by the delay variation with different input slopes. edge to ensure that the extra delay variation is negligible compared to the delay variation generated by the comparator. Considering a four-stage comparator whose overall gain is evenly distributed across each of the stages with the same bandwidth, Figure 3.3 shows the delay variation and degradation on distortions over different bandwidths for a 15-level voltage quantizer with an input of 20 MHz full-scale single tone or two equal amplitude tones located around 20 MHz with 1-MHz spacing. The presentation of multiple frequencies at the input can generate a larger delay variation because of the wider range of the input slope, but a smaller input slope at level crossing can tolerate more delay variation. This is illustrated in Figure 3.4, where δt pd1 and δt pd2 represent the delay deviation from a nominal delay value t pd0 . This delay variation effect can be approximated as an error voltage given as the product of the input slope and the time deviation. Therefore, given a certain error voltage bound V e , more delay variation (δt pd2 > δt pd1 ) can be tolerated when the input slope at the level-crossing point is smaller. Based pd1 t δ Ve pd2 t δ pd0 t 60 Figure 3.5: Errors introduced by the offset voltage in the voltage quantizer. on the above analyses, a four-stage comparator is designed for this prototype, where the gain and bandwidth of each stage are >12 dB and 1 GHz, respectively, which ensure that the degradation on distortions is less than 3 dB. 3.1.2 Offset of comparator and reference voltage The offset voltage (V off ) of the comparator and the reference voltage generator changes the threshold of the corresponding voltage quantization level, and this change effectively causes a timing error δt off in the time instant of level crossing. Assuming an offset occurs only at the center level, δt off can be approximated as V off /A FS ω in for a sinusoidal input A FS ·sinω in t. Considering the ZOH reconstruction method, this δt off -induced error e off (t) is modeled as a superposition of two pulse trains e(t) and e(t + 0.5/F in + δt off ), where e(t) is a square wave with a period of 1/F in , as shown in Figure 3.5. Vth Vth + Voff e(t) off t δ FS 2 1 A N − + 0 FS in sin At ω off in 0.5 () et t f δ + + 61 Because e off (t) is repetitive, it can be expressed as the following Fourier series expansion: ( ) ( ) ( ) ( ) off off FS off in in off 1 FS 2 () ( 1) 4 1 sin cos 1 cos ( 1) 2 k k V e t N A kV kt k t t N kA π ω ωδ π ∞ = − = + − +− + + ∑ (3.3) where N is the number of levels in the voltage quantizer. Notably, V off introduces harmonic distortions. The above derivation can be extended to multiple threshold voltages with offset, and the errors can be combined by superposition. Based on this analysis, the maximum offset voltage should be less than 1.3 mV to achieve SFDR higher than 65 dB in the prototype. This is accomplished by employing the offset calibration scheme elaborated in Section 3.2.3. 3.1.3 Noise in time quantizer and voltage quantizer The noise of a time quantizer can be modeled as timing jitter [23]. To calculate the effect of timing jitter [t j ∼ N(0, j t σ )], t j is multiplied by the input slope at the level-crossing point, that is, the induced voltage error, which is similar to jitter analysis of sampling clocks in conventional ADCs [24]. However, the varying sampling rate of the NUS ADC causes the noise spectrum to spread from DC to half of the average sampling 62 Figure 3.6: SNR of a 20-MHz sinusoidal input over different jitter values. rate. Considering a sinusoidal input of A·sinω in t, the average sampling rate F s,avg is pF in , where p is the number of nonuniform samples generated in each cycle, and it is proportional to A. The OSR avg can be represented as F s,avg /2F BW , where F BW is the desired bandwidth. Assuming that the noise spectrum is white with a DAAF applied to attenuate out-of-band noise higher than F BW , there is an additional processing gain of G DAAF = max(OSR avg , 1) = max(pf in /2F BW , 1). Therefore, the SNR over F BW can be derived as follows: 15 75 70 65 60 SNRjitter (dB) j Jitter, (ps) t σ 14 13 12 11 10 9 8 7 6 5 63 Figure 3.7: Concept of generating and processing level-crossing events. ( ) j 2 DAAF FS jitter 10 1 22 0 1 2 2 SNR 10log for 1 1 σ − = ⋅ = > + ∑ p tk k A G A A N S p (3.4) where S k is the input slope at the kth nonuniform sample. Because an automatic gain control loop is typically applied to the system, A > 2A FS /(N + 1) is always satisfied. Considering a 15-level voltage quantizer with a 20-MHz input, the SNR jitter over the 20-MHz bandwidth is plotted for different jitter values with a full-scale input shown in Figure 3.6. Practically, if the noise spectrum is not white, the analysis can be extended to a colored noise spectrum by reducing G DAAF in (3.4). Similarly, this analysis can be Analog Input Level<N-1> Level<N-2> Level<N-3> pulse<N-1> pulse<N-2> pulse<N-3> pulse_combined time instant tk-1 x(tk) x(tk+1) tk tk+1 level N-1 N-2 N-3 tk+2 x(tk+2) 64 Figure 3.8: Block diagram of the proposed flash-based NUS ADC. applied to the effect of noise from the voltage quantizer by replacing the denominator in (3.4) with an equivalent input-referred noise power 2 DAAF VQ 10 2 n,VQ 1 2 SNR 10log ⋅ = A G V . (3.5) With a 20-MHz input and 20-MHz bandwidth, an overall SNR of 65 dB can be achieved when the input-referred noise of the voltage quantizer and jitter of the time quantizer are 700 μV RMS and 9 ps, respectively. Analog Input Pulse Combiner & Level Encoder Time Quantizer Vref+ Vref- 15-Level Voltage Quantizer { } , ( ), k xt ⋅⋅⋅ ⋅⋅⋅ pulse_combined 4 [ ] { } ,Q , k t ⋅⋅⋅ ⋅⋅⋅ comparator pulse<0> pulse<14> level<14> level<0> pulse generator 13 65 3.2 Flash-based NUS ADC 3.2.1 Architecture Figure 3.7 shows the high-level time-domain concept of the flash-based NUS ADC implementation. As mentioned in Chapter 2, two essential elements of the input signal—level and time—are required for signal processing in the NU DSP. Whenever an analog input signal crosses certain pre-defined quantization levels, it triggers a pulse to indicate an NUS event. Pulses from different levels are combined before they are recorded by a shared time quantizer to minimize hardware complexity. A simplified block diagram of the front end of the proposed flash-based NUS ADC is shown in Figure 3.8. The voltage quantizer developed in a previous work [25] is composed of two comparators, but it keeps switching the reference voltage to track the input signal. However, the settling time, including the feedback loop delay, must be shorter than the minimum time spacing between two adjacent sampling events, and this requirement becomes a bottleneck when the signal bandwidths are wider. To maximize bandwidth, a parallel bank of comparators with fixed reference voltages is implemented. Assuming t diff,min is the minimum time spacing between two adjacent pulses at which the time quantizer can function properly, and N is the number of levels, the maximum input frequency F in,max of a full-scale single tone can be determined as F in,max ≤ 66 Figure 3.9: Comparator implementation. [2πt diff,min sin −1 (2/(N + 1))] −1 . In the case of this prototype, when t diff,min = 500 ps and N = 15, F in,max is 40 MHz. The comparator outputs are followed by pulse generators that convert the level-crossing events into nonuniform pulses. The pulse combiner then combines all the pulses, and the level encoder indicates the level that is being crossed by the analog input. Finally, the combined pulse triggers the time quantizer and the time instant of each rising edge is recorded. 3.2.2 Reference generator and comparator The reference generator and comparators are fully differential but are depicted with the single-ended configuration for simplicity. The reference generator consists of two Bandwidth Control Hysteresis refn on1 inp inn refp op1 op1 on1 outn2 outp2 5-bit Current DAC 5-bit Current DAC outn2 outp2 out_p out_n Vb Vb 200 uA 200 uA 16 0.06 1.5 K Ω 200 uA 4 0.06 100 uA 2 0.06 First Stage Second Stage Third and Fourth Stages 67 matched poly-resistor ladders placed in parallel but along opposite directions to minimize and balance the routings to the comparators at the cost of doubling the power consumption. The positive and negative reference voltages are 1 V and 0.4 V, respectively, resulting in a maximum amplitude of 0.6 V for the differential input. The matching requirements are relaxed by applying the offset calibration scheme described in Section 3.2.3, and the peak mismatch between the two ladders is designed to be 0.5% based on the results of a Monte Carlo simulation. The four-stage comparator is shown in Figure 3.9. Considering the instant of level crossing in the first stage, except in case of the middle comparator, where all inputs are at the same voltage, the differential output voltage can exhibit dependence on different operating conditions, and this can cause a reference-level-dependent delay variation in addition to the slope-dependent delay variation discussed in Section 3.1.1. To minimize this effect, inp and refp are connected to one of the differential pairs, while inn and refn are connected to the other differential pair. In this manner, the differential input voltages of both differential pairs become zero upon level crossing, and the differential pairs operate in the most linear region of the transfer function. As a result, the comparator delay variation among different reference levels is minimized, which has been confirmed in this study by conducting SPICE simulations. Additionally, the gain of the first stage can attenuate the kickback noise before the noise being coupled to the reference 68 (a) (b) (c) Figure 3.10: Measured (a) comparator offset and (b) combined pulse using a 20-KHz ramp signal. (c) Measured output spectrum reconstructed using spline interpolation. 25 mV -15 -10 -5 0 5 10 15 20 25 0.5 mV -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Before Offset Calibration Offset (%LSB) Offset (%LSB) Comparator # 0 1 2 3 4 5 6 7 8 9 121314 1011 After Offset Calibration Comparator # 0 1 2 3 4 5 6 7 8 9 121314 1011 0 25 50 -0.6 0 0.6 Amplitude (V) 0 25 50 0 0.5 1 Amplitude (V) 0 25 50 0 0.5 1 Time (us) Amplitude (V) 20 KHz Ramp Input Signal Before Calibration After Calibration pulse_combined pulse_combined 10 6 10 7 10 8 10 9 -120 -100 -80 -60 -40 -20 0 Frequency (Hz) Amplitude (dBFS) 10 6 10 7 10 8 10 9 -120 -100 -80 -60 -40 -20 0 Frequency (Hz) Amplitude (dBFS) ~20 dB Before Offset Calibration After Offset Calibration 69 generator, and hysteresis is applied to reduce unexpected multiple crossing events at the same reference level due to circuit noise. The offset calibration scheme is applied to the outputs of the second stage by including 5-bit current-steering DACs at the positive and negative nodes. The third and fourth stages provide extra gain, which sharpens the signal transition edge. According to the SPICE simulation results, each stage achieves a bandwidth of more than 1 GHz, and the overall gain is approximately 45 dB with input-referred noise <600 μV RMS . To confine the delay variation within specifications, numerous SPICE simulations are performed using different process corners, supply voltages, and temperatures (PVT) by maintaining some tunability in the tail current, load resistors, and transistors. 3.2.3 Offset calibration The offset from both the reference generator and the comparators can be calibrated simultaneously by receiving a known signal and calculating the difference between the measured time codes and the expected time instants of crossing. The measured time codes are averaged over multiple cycles to mitigate the effect of noise. Then, a binary search can be conducted to suitably adjust the current DACs in the comparators to compensate the offset. To minimize the delay variation due to different input slopes, a ramp can be applied during the calibration stage, and its amplitude can be overdriven to 70 Figure 3.11: Pulse generator with tunable pulse width. be greater than the full scale to reduce the effect of overdrive voltage in the comparator. After calibration, the offset voltage can be confined within 0.5 mV, resulting in the generation of more uniformly spaced pulses and a 20-dB improvement in SFDR shown in Figure 3.10. Moreover, the ADC can be calibrated using a low-frequency sinusoid wave, for example, 1 MHz, which would yield similar results because the delay variation is negligible. Although this calibration scheme is executed in the foreground, the results of a Monte Carlo simulation indicate that the offset voltage due to temperature drift is 11 μV/°C after the initial calibration process, which is tolerable given the target specification. When tighter offset control is required, the comparator can be recalibrated whenever in IN REF D Pulse Generator B A CML XOR Gate A A B B B out Pulse Combiner Level Encoder A B pulse pulse D REF IN pulse width ~ 300 ps to 400 ps 100 uA 71 Figure 3.12: Delay-balanced pulse combiner and level encoder. the absence of a signal-crossing event or an auxiliary comparator may be used to bring one of the comparators offline for calibration. 3.2.4 Pulse generator The pulse generator shown in Figure 3.11 contains an exclusive-OR gate and a delay cell, and it employs the differential current-mode logic (CML) to minimize the propagation delay and delay variation. The pulse width is set between 300 and 400 ps to satisfy the minimum time spacing requirement between two adjacent pulses ( ∼500 ps), pulse<0> P<13> pulse<1> pulse<2> pulse<14> 0 1 2 3 4 5 6 7 8 9 10 11 13 12 Level Encoder L<14:0> 4 pulse_combined P<10> P<11> P<13> L<13> S R Q Delay-Balanced OR L<13> Delay-Balanced Pulse Combiner { } , ( ), k xt ⋅⋅⋅ ⋅⋅⋅ 14 72 (a) (b) Figure 3.13: (a) Conventional CMOS OR gate. (b) Delay-balanced OR gate. and it can be controlled using the delay cell [14], which is tunable in this implementation for prototyping purposes. 3.2.5 Pulse combiner and level encoder In addition to minimizing the delay variation in voltage quantization, it is important to match the propagation delay of each path in the pulse combiner all the way to the time quantizer input. Figure 3.12 shows 15 identical sub-modules formed by combining two A B B A out Q A B Q d,HL,A t d,HL,B t d,HL,A d,HL,B tt > Cp CQ B B B A A Replica A B Q d,HL,A t d,HL,B t d,HL,A d,HL,B tt = Q CQ Cp Cp A out 73 Figure 3.14: Block diagram of the time quantizer including fine quantization and coarse quantization. pulses from adjacent comparators and pre-encoding the level information to indicate the origin of each pulse. A tree structure is utilized to match all the routing parasitics and guarantee that each path passes through the same number of submodules. A delay-balanced OR gate is compared in Figure 3.13 with the conventional CMOS logic. Because the rising edge of the pulse contains information about the sampling time instant, the propagation delay from either of the input ports to the high-to-low transition at the Q port must be matched. In the conventional CMOS design, the high-to-low Elmore delay t d,HL can be written as t d,HL,A = R N C Q + (R N + R P )C p and t d,HL,B = R N C Q , where C Q and C p are the total parasitic capacitances at the internal nodes, and R N and R P are the effective turn-ON resistances of NMOS and PMOS, respectively. To equalize two different delays t d,HL,B = t d,HL,A = R N C Q + (R N + R P )C p , a replica of the pull-up circuit is added to match the CML Buffer External Clock pulse_combined 8-bit Counter 8 t<13:0> Sense-Amplifier-Based Flip-Flops 7-Stage Cross-Coupled Ring Oscillator Encoder 13 [ ] { } ,Q , k t ⋅⋅⋅ ⋅⋅⋅ Fine Coarse 74 Figure 3.15: Current-starved inverter with tunable delay used in the ring oscillator. Figure 3.16: Passive phase interpolation by cross-coupled resistors. load of the pull-down network. The results of the post-layout simulation indicate that the delay difference can be limited to <1 ps with negligible performance degradation. outn inp 50 uA 10 0.28 9 0.06 9 0.06 10 0.28 2 0.28 2 0.28 2 0.28 A1 B1 A2 B2 A3 B3 C1 C2 C3 A1 C1 B2 C2 A3 D D pulse_combined Sense-Amplifier-Based Flip-Flops pulse_combined t<13:9> 10000 11100 11110 t<9> Q D D D D Q Q 75 Figure 3.17: Sense-amplifier-based flip-flop with pre-amplifier. 3.2.6 Time quantizer The time quantizer is implemented using a time-to-digital converter (TDC) which can be divided into coarse quantization and fine quantization modules [26] shown in Figure 3.14. The coarse time quantization is composed of an 8-bit counter consisting of a 3-bit straight ring counter clocked at the ring oscillator frequency (>4 GHz) and a 5-bit synchronous counter that operates eight times more slowly. The fine time quantization is achieved by latching the internal states of the ring oscillator with the combined pulse. The ring oscillator contains seven pseudo-differential current-starved inverter stages (Figure 3.15), and it naturally provides 14 sub-phases within one oscillation period. The delay of each inverter sets the duration between the sub-phases and, therefore, defines the basic resolution of time quantization [27]. To increase the resolution of time quantization, D a a D pulse_combined a a b b Q b b Pre-amplifier Sense-Amplifier SR Latch 76 passive interpolation [28], [29] is applied by employing cross-coupled resistor ladders (Figure 3.16) between the inverter stages, which doubles the TDC resolution and mitigates the mismatch effects. Moreover, the oscillation frequency of this prototype can be adjusted from 2 to 4.2 GHz to characterize the effects of various time resolutions. In addition, a sense-amplifier-based flip-flop [30] is used in the fine time quantization (Figure 3.17) to achieve superior sensitivity and higher speed (up to 2 GHz). An additional pre-amplifier stage sharpens the waveforms from the passive phase interpolator and reduces the kickback noise from the subsequent stages. Finally, an encoder with bubble correction logic combines both coarse and fine time codes and produces a final 13-bit output. When the signal activity is low, two consecutive time codes may be recorded with multiple wraparounds in between because of the finite number of bits in the counter. Therefore, an extra overflow bit to indicate counter saturation is implemented and captured by another counter in the NU DSP to properly unwrap the time codes. However, to avoid the time interval between samples that out of range because the frequency or amplitude of the input signal is too low, a new sample with a code of the same level as that of the previous sample can be generated without a level-crossing event. This can be achieved either by forcing a pulse event to the pulse combiner or by inserting a new sample in the asynchronous FIFO queue. In this prototype, the full time-scale is designed to be sufficiently large so as to cover our test cases. 77 Because it is difficult to achieve a well-defined oscillation frequency (time resolution) with a free-running ring oscillator over PVT, injection-locking is performed to synchronize the frequency and phase with those of the injected clock source in the steady state. In addition, injection locking can suppress the phase noise accumulated in the delay elements, which can reduce jitter. For achieving adequate coupling strength from the external clock source, which is proportional to the injection-locking bandwidth, a CML clock buffer with coupling strength that can be adjusted by tuning the current bias is utilized. 3.2.7 Design tradeoffs Considering different design spaces in terms of signal bandwidth, resolution, and power and area consumption, there are several design tradeoffs in the proposed architecture. As mentioned in Section 3.2.1, by eliminating the need to switch the reference voltage in the level-crossing quantizer, the signal bandwidth of the proposed flash-based architecture can be extended to more than tens of KHz [25]. In addition, the building blocks implemented in this prototype are intended for proof of concept and can be further optimized. For example, one may apply calibration techniques to address the signal-dependent delay variation because dependence of the delay on the signal slope or reference level can be learned and compensated in the time code. The literature indicates 78 Figure 3.18: Chip micrograph. that it is feasible to learn the signal slope [31], [32], [33]. Consequently, the desired comparator bandwidth and gain can be reduced to achieve a more power- or area-efficient design. For the time quantizer, because the time resolution is overdesigned for characterizing different noise sources, a coarser time resolution can be used to lower the oscillation frequency, which would also reduce power consumption proportionally. Moreover, it is possible to further increase the signal bandwidth in the flash-based NUS ADC. For instance, the pulses from the various comparators can trigger the time TDC CML Output Buffers SPI Voltage Quantizer 1.0 mm 1.5 mm 79 Figure 3.19: Measurement setup. quantizer separately (bypassing the pulse combiner) to increase the NUS throughput without reducing the input amplitude. Another possible design choice is to use fewer levels in the voltage quantizer to achieve a tradeoff between the signal bandwidth and the resolution while reducing power and area consumption. In an extreme case where only two quantization levels are deployed using the same building blocks as those implemented in this prototype, the power and area consumption can be reduced by 70% with the resolution of 4 bits and the signal bandwidth of hundreds of MHz. Note that the building blocks can be redesigned accordingly because of the reduced resolution. For example, the class-A continuous-time comparators can be replaced with the class-B inverter-based comparators [14], without static power consumption, which will also relax the demands on the time quantizer. In summary, a wide design space can be explored by using the proposed flash-based NUS ADC architecture while reaping the benefits afforded by a flexible NU DSP. TDC Test Chip Keysight 16962A Logic Analyzer Memory NU DSP 1 7 12 CLK CML Buffer Level 4 13 Time Pulse Pulse Combiner Level Encoder Voltage Quantizer Buffer 4 GHz Vref+ Vref- Input Filter Output 80 (a) (b) Figure 3.20: (a) Input amplitude and (b) measured and theoretical SFDR (entire spectrum) over different frequencies with single sinusoidal input. 3.2.8 Measurement results The proof-of-concept prototype was fabricated using 65-nm CMOS technology on a core area of 0.3 mm 2 (Figure 3.18). The core area included the reference generator, comparators, pulse generator or combiner, level encoder, and time quantizer. Figure 3.19 shows the measurement setup, in which an external clock is employed for injection locking, and voltage and time codes are recorded on local memory by using a logic analyzer. To characterize the front end of the NUS ADC, the DAAF was configured to perform only interpolation without filtering, that is, an all-pass filter response, with a 12-bit output for achieving a negligible finite word-length effect. SFDR was measured from the output interpolated using two representative reconstruction methods, ZOH and spline interpolation using Neville’s algorithm, the area and power consumption of which Input Frequency (MHz) Amplitude (dBFS) -15 -10 -5 0 5 100 10 1 Input Frequency (MHz) SFDR (dB) 10 30 40 60 70 100 10 1 20 50 SFDR_ZOH (measured) SFDR_ZOH (theoretical) SFDR_spline (theoretical) SFDR_spline (measured) 81 (a) (b) Figure 3.21: Measured and calculated SNR (within 20-MHz bandwidth around the input frequency) (a) over different frequencies with single sinusoidal input and (b) over different input amplitudes with 1-MHz input. are 0.002 mm 2 & 0.3 mW and 0.11 mm 2 & 5.7 mW, respectively. The input swing is reduced when the frequency is higher than 20 MHz [Figure 3.20(a)] to ensure adequate time spacing between nonuniform samples due to the bandwidth limitation imposed by the PCB parasitics and the data acquisition equipment. Figure 3.20(b) shows the measured and theoretical (without circuit non-idealities) SFDR over the entire spectrum for a single sinusoidal input. The degradation of SFDR results mainly from the delay variation that can be ascribed to finite comparator gain and bandwidth. As shown in Figure 3.21(a), the SNR (excluding the harmonics from the interpolation error) with injection-locking enabled (with an external clock) and disabled (without an external clock) is measured from the output reconstructed at the TDC resolution and is calculated within Input Frequency (MHz) SNR (dB) 30 40 50 60 70 100 10 1 Injection-Locking Enable Calculated Injection-Locking Disable Input Amplitude (mV) SFDR (dB) 30 40 60 600 75 50 SFDR_ZOH (measured) SFDR_ZOH (theoretical) SFDR_spline (theoretical) SFDR_spline (measured) 525 450 375 300 225 150 Calculated Measured 82 (a) (b) Figure 3.22: Measured and theoretical spectra of two tones at 15 and 19 MHz using (a) ZOH and (b) spline interpolation. the 20-MHz bandwidth around the input frequency as a reference study. The measured RMS values of jitter, including those of the on-chip drivers and the time quantizer, are 7 and 25 ps (integrated phase noise from frequency offset of 10 kHz to 20 MHz at 4 GHz) with injection-locking enabled and disabled, respectively. At low input frequencies, the noise is dominated by the voltage quantizer, which is around 900 μV RMS as calculated using (3.5), but the timing jitter starts degrading the SNR as the input frequency increases. The calculated SNR shown in Figure 3.21(a) is computed using (3.4) and (3.5) by assuming input-referred noise of the voltage quantizer as 900 μV RMS and jitter of the time quantizer as 7 ps. The difference between the calculated and measured results at higher input frequencies can be ascribed to the kickback noise from the comparators and the 10 10 10 10 10 10 10 10 10 10 Theoretical Measured 10 -1 10 0 10 1 10 2 10 3 Frequency (MHz) 10 -1 10 0 10 1 10 2 10 3 Frequency (MHz) 0 Amplitude (dBFS) -20 -40 -60 -80 -100 0 Amplitude (dBFS) -20 -40 -60 -80 -100 -120 -120 Theoretical Measured 10 -1 10 0 10 1 10 2 10 3 Frequency (MHz) 10 -1 10 0 10 1 10 2 10 3 Frequency (MHz) 0 Amplitude (dBFS) -20 -40 -60 -80 -100 0 Amplitude (dBFS) -20 -40 -60 -80 -100 -120 -120 Theoretical Measured 83 Figure 3.23: Measured DNL and INL of the time quantizer. colored noise in the time quantizer. In addition, the supply noise and ground bounce also play a role in the pulse combiner because of the single-end implementation. The measured and calculated SNR values for different input amplitudes are illustrated in Figure 3.21(b) for an input of 1 MHz. In Figure 3.22, when two tones of equal amplitude at 15 and 19 MHz are injected, the measured output spectra compared to the theoretical ones (without circuit non-idealities) exhibit <2dB degradation in distortion, which can primarily be ascribed to the variation in comparator propagation delay. 27 24 21 18 15 12 9 6 3 0 -0.5 0 0.5 TDC Code DNL (LSB) 27 24 21 18 15 12 9 6 3 0 TDC Code -0.5 0 0.5 INL (LSB) 84 (a) (b) Figure 3.24: Measured blocker tests with NU DSP. (a) Low-pass. (b) Band-pass. (a) (b) Figure 3.25: Measured 64-QAM signal with 30-dB higher blocker presented at 43 MHz. (a) Before NU DSP. (b) Constellation after NU DSP. The linearity of the time quantizer can be characterized by disconnecting the pulses combined by the pulse combiner and applying an external clock at a reference frequency of 300 MHz. By analyzing the code density statistic, the measured DNL and integral Before Filter After Filter Signal Blocker > 80 dB attnuation Frequency (MHz) 1 10 -120 -100 -40 -20 0 20 Amplitude (dBFS) -140 -80 -60 Frequency (MHz) 1 10 -120 -100 -40 -20 0 20 Amplitude (dBFS) -140 -80 -60 Before Filter After Filter Signal Blocker Blocker Digital AA filter response (to be applied) Signal Frequency (MHz) 0 -120 -100 -40 -20 0 Amplitude (dBFS) -80 -60 10 20 30 40 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 I -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 Q EVM = -28 dB -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 I Q -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 85 This Work b [25] c [34] d [14] e Alias-free Sampling Yes Yes No Yes Alias-free Filtering Yes No No No Uniform Digital Output Yes No Yes No Supply Voltage 1.0 V 1.0 V 1.0 V 1.2 V # of Levels 15-level 256-level Signal- Dependent 8-level Implementation Differential Single-ended Single-ended Single-ended SFDR 56 dB (F in = 19 MHz) ~ 60 dB (F in = 0.2 KHz) 53 dB (F in = 290 KHz) 23.5 dB (1-tap) 31.5 dB (6-tap) (F in = 1 GHz) SNDR 59.9 dB (F in = 19 MHz) (F BW = 20 MHz) 47 dB (F in = 0.2 KHz) 62 dB (F in = 4 KHz) (F BW = 10 KHz) 49 dB (F in = 290 KHz) (F BW = 300 KHz) 20.3 dB (1-tap) 25.3 dB (6-tap) (F in = 1 GHz) (F BW = 2.4 GHz) Power a 30 mW 1.23 mW 14 μW 5 mW a Power dissipation during signal processing is excluded. b Because of alias-free sampling, SFDR is calculated across the entire spectrum without applying post-filtering on the spline-interpolated output. The alias-free filtering assumes that the finite resolution of the time quantizer is considerably smaller than the period of the input signal, which introduces a negligible aliasing effect. c It is an ADC/DSP/DAC system in which nonuniform samples at the ADC output are interpolated using ZOH. d Nonuniform samples at the ADC output are interpolated using an iterative algorithm [2]. e It is an ADC/DSP/DAC system in which nonuniform samples at the ADC output are interpolated using ZOH. Post-filtering is applied to the interpolated output, and SFDR and SNDR are calculated from 0.8 GHz and 3.2 GHz, excluding half-harmonics (F in /2). Table 3.1: Comparison with ADCs utilizing nonuniform samples. 86 nonlinearity (INL) of the TDC are shown in Figure 3.23, where the maximum DNL and INL are 0.41 and 0.43 LSB, respectively. Blocker tests are performed, including DAAF, by utilizing ZOH. Figure 3.24 shows both low-pass filtering and band-pass filtering, where a blocker is injected at 5 MHz, which is 40 dB higher than the desired signal at 4 MHz. In Figure 3.25, a 30-dB-higher single sinusoidal blocker is injected at 43 MHz with a 64-quadrature amplitude modulation (QAM) signal; the error vector magnitude (EVM) shows −28 dB at the output of the NU DSP. The measured peak power, including those of the reference generator (1.1 mW), comparators (12 mW), pulse generators (1.7 mW), pulse combiner or level encoder (1.2 mW), fine and coarse time quantizers (4.8 mW and 3.2 mW, respectively), and clock buffer (1.6 mW), is 30 mW when a full-scale 19-MHz signal and a 4-GHz external clock are injected. Table 3.1 compares this proof-of-concept prototype with various ADCs that utilize nonuniform samples. The proposed ADC architecture achieves alias-free NUS, DAAF, and uniform digital output simultaneously, which is compatible with the existing synchronous DSP. 87 Figure 3.26: Proposed subranging-based NUS ADC versus flash-based NUS ADC. 3.3 Subranging-based NUS ADC 3.3.1 Compared to flash-based NUS ADC When a higher amplitude resolution is demanded with the same signal reconstruction method, the flash-based NUS ADC requires an increasing number of amplitude reference levels N flash , that is, comparators. Furthermore, F s,avg increases proportionally with N flash because finer amplitude reference levels trigger higher numbers of signal-crossing eventcoarse eventfine Tout Reffine Refcoarse eventcombined Flash-based eventcombined (xk, tk) Tout Tout Subranging-based x(t) 88 activities. In many cases, it is not desirable to couple F s,avg with the amplitude quantization resolution because doing so can increase the area and power consumption of both analog and digital circuitry unnecessarily, resulting in an inefficient implementation for higher resolutions. To alleviate the limitations of the flash-based architecture, we propose a two-stage subranging-based NUS ADC that 1) preserves the alias-free sampling property; 2) uses the same number of comparators but increases the effective amplitude quantization resolution or reduces the required number of comparators but maintains the same effective quantization resolution; and 3) further reduces F s,avg with minimum impact on the quality of the reconstructed signal. To achieve these goals, we divide the comparators into coarse and fine stages, controlled by the proposed switching scheme, where the amplitude reference levels of the fine stage (Ref fine ) are continuously switched between coarse amplitude reference levels (Ref coarse ) according to the input signal. This not only avoids the need to use a dedicated comparator for each Ref fine but also preserves the alias-free sampling property. Even so, F s,avg increases as the number of amplitude reference levels increases. Therefore, we propose a timeout mechanism for sampling event filtering. In other words, we can arbitrarily adjust F s,avg based on need by decoupling it from the amplitude quantization resolution. 89 Figure 3.27: Block diagram of the proposed subranging-based NUS ADC. 3.3.2 Time-domain view of subranging-based nonuniform sampling The time-domain view of the proposed subranging-based NUS ADC with the timeout mechanism is shown in Figure 3.26. If a flash-based NUS ADC is used, one comparator is required for each amplitude reference level, resulting in the use of N flash comparators in the amplitude quantizer. To reduce the total number of comparators, we switch Ref fine between Ref coarse , which results in N coarse + N fine < N flsah , where N coarse is the number of Ref coarse , and N fine is the number of Ref fine between Ref coarse . Unlike a conventional Level Encoder { } ,, k x ⋅⋅ ⋅ ⋅ Ref+ Ref- M U X 3 Ref+ Ref- Input Event Filter Collision-Free Pulse Combiner Time-out Controller Time Quantizer 15 4 { } , , k t ⋅⋅ ⋅ ⋅ 1 st Stage (Coarse) 2 nd Stage (Fine) eventcoarse eventfine winTO eventcombined 15 × 3 3 even channel odd channel 15 × 90 subranging ADC, where a finer amplitude quantization resolution is applied to the same sampled input, the proposed nonuniform sampling and quantization scheme generates additional samples from Ref fine . This fundamentally different operation preserves the alias-free sampling property. Notably, because the extra nonuniform samples may not effectively improve the quality of signal reconstruction, especially when the input signal changes rapidly [31] [35] [36], that is, in the high slew rate region, we propose a timeout mechanism that allows the generation of new samples only after a certain timeout duration T out , as shown in Figure 3.26. Each new level-crossing event reinitiates the timeout mechanism immediately. Thus, it filters out more nonuniform samples when the input slew rate is higher, and vice versa, resulting in a more efficient distribution of the nonuniform samples. Additionally, by adjusting the value of T out , one can control the F s,avg of this subranging-based NUS, regardless of the number of Ref fine . Consequently, one can adjust the overall amplitude quantization resolution and F s,avg independently, which is not feasible with flash-based NUS ADCs. 3.3.3 Architecture Figure 3.27 shows a simplified block diagram of the proposed ADC. The input signal is compared continuously in two stages: the first stage is composed of 15 continuous-time comparators connected with fixed Ref coarse . The second stage consists of two banks of 91 three comparators (an even and an odd channel) connected to alternating Ref fine . The proposed ADC can thus track the input signal even when the signal direction changes immediately after the level-crossing event. Compared to a flash-based NUS ADC with the same amplitude quantization resolution, the proposed subranging-based architecture uses only 21 comparators instead of 63, which amounts to a hardware cost reduction of more than 60%. After the level-crossing events, that is, transitions at the comparator outputs, are generated, they are processed by the event filter. An active-low mask-out window win TO is used to determine whether the events should be removed or converted into pulses (event coarse and event fine ). To match the propagation delay between two stages, the event filters inserted in the first stage are replicas of the ones in the second stage, albeit with the event-filtering function disabled. Owing to the asynchronous operation between first and second stages, pulses can be corrupted in the pulse-combining process. For example, if an OR gate is used to combine the pulses, adjacent pulses that are too close to each other will be merged into a wider pulse or will generate glitches, which may affect the operation of the time quantizer [18]. Therefore, a collision-free pulse combiner is proposed to guarantee a properly combined pulse train. Next, the level encoder uses 15 separated pulses from the first stage to determine which Ref coarse the input signal has just crossed. Therefore, it can switch Ref fine 92 Figure 3.28: Circuit implementation of critical building blocks. correctly even when any pulse is removed by the pulse combiner. Finally, the time quantizer provides quantized time information at the rising edge of each pulse with a resolution of <9 ps. 3.3.4 Circuit implementation The implementations of several key building blocks are depicted in Figure 3.28. The event filter consists of two D flip-flops (DFFs) to detect the transitions generated at the eventfine winTO : collision avoidance Input Ref winTO tunable delay eventcoarse Tout compout Tout R D Q R D Q Event Filter Counter reset eventcoarse overflow 10 R D Q Time-out Controller eventfine R D Q R D Q eventcombined : event removed Collision-Free Pulse Combiner eventcombined compout Comparator D D D D D D Tout (programmable) 93 Figure 3.29: Proposed alternating reference level switching scheme. comparator output whenever the input crosses the voltage reference level. The timeout controller is composed mainly of a counter, which asserts win TO until it reaches the preprogrammed threshold T out . T out ranges between 0.5 ns and 500 ns, and it is determined by the targeted F s,avg and the characteristics of the input, for example, signal bandwidth. When win TO is high, the transition at the DFF input will assert Q at the output to reset the counter and win TO for filtering the subsequent transitions. After the tunable delay D, Q will be reset, which will yield a pulse of width D and enable the counter to resume (0.4 V) Ref - Ref_coarse Ref_fine (even) Ref_coarse Ref_fine (odd) Ref_coarse Ref_coarse Ref_fine (even) (1 V) Ref + Ref_fine (odd) Fine Stage (odd) Fine Stage (even) Decoder 16 Level code (coarse) Thick-oxide device Ref_coarse time Ref_fine (odd) Ref_fine (odd) Ref_fine (even) Ref_fine (even) Tout Switching of fine reference levels Tout Ref_coarse Ref_coarse Ref_coarse 4 Ref_coarse 94 Figure 3.30: Implementation of continuous-time comparators. counting. In addition to performing event filtering, the event filter can prevent pulses from being closer than 2D, thus alleviating the problem of proximity among multiple pulses due to comparator noise, which can cause a malfunction in the time quantizer D can be determined based on the design of time quantizer, and it is ∼250 ps for this prototype. Finally, the collision-free pulse combiner contains a cross-coupled reset path. When a pulse is detected from either the first or second stage, the collision-free pulse combiner will block the subsequent incoming pulses if they are too close together, which would make them prone to collisions or glitches. Whenever the input crosses a new Ref coarse , Ref fine are switched accordingly. However, the input signal may change its direction immediately and cross the same Ref coarse again. This can impose a stringent settling requirement on Ref fine . Therefore, we propose an inp inn refn refp on op on op 1 st stage of comparator outp outn Vb Vb GND GND VDD (1 V) VDD GND GND 2 nd - 4 th stages of comparator Differential-to- single-ended amplifier outp outn out VDD GND 95 alternating switching scheme, as illustrated in Figure 3.29. The even and odd channels are responsible for monitoring level-crossing events from different intervals between Ref coarse . However, only the channel, which is farther from the input signal, is switched at each level-crossing event. Ref fine are determined from the resistor ladder and multiplexed using an array of thick-oxide devices to minimize the input-dependent leakage current. Because the comparators in the first stage are connected to fixed voltage reference levels, the overall ADC throughput is not limited by the settling of the fine voltage reference levels. The comparator implementation (Figure 3.30) consists of multistage preamps, followed by a differential-to-single-end converter. Because of finite gain and bandwidth, the comparator can generate an input-slew-rate-dependent propagation delay, which can cause distortion at the output. To minimize this effect, the comparators are designed with overall gain of more than 60 dB and bandwidth of 1 GHz for each stage according to the analysis in [18]. To relax the matching requirements between comparators, the offset calibration routine is accomplished in two steps with a low-frequency input. The first step is executed in the analog domain, where the coarse time codes from the time quantizer [18] are captured. A binary search algorithm then properly adjusts the built-in binary-weighted offset compensation current cells (V b in Figure 3.30) to confine the offset voltage within 1.3 mV. This guarantees that the comparators are triggered monotonically, which is required for the timeout mechanism. The second step is executed 96 Figure 3.31: Spectra measured using flash-based and subranging-based architectures. in the digital domain, where we exploit the fine time quantization resolution and a priori information about the input slope to compute the errors between the measured and ideal time codes. These errors are subsequently used to calculate the residual offset voltages, which can be compensated during signal reconstruction to achieve accuracy levels higher than 13 bits. Finally, this prototype can potentially allow for more power savings because the comparators can be powered off individually during idle time, for example, during timeout duration. Each comparator consumes 800 μA and 10 μA during power-on and power-off, respectively. 10 -1 10 0 10 1 10 2 -120 -100 -80 -60 -40 -20 0 100 0.1 -120 -100 -80 -60 -40 -20 0 Amplitude (dBFS) 10 1 Frequency (MHz) Flash-Based (Nflash = 18) 62 dB fs,avg = 36 MS/s 10 -1 10 0 10 1 10 2 -120 -100 -80 -60 -40 -20 0 100 0.1 -120 -100 -80 -60 -40 -20 0 Amplitude (dBFS) 10 1 Frequency (MHz) Subranging-Based (Ncoarse = 15, Nfine = 3) > 77 dB fs,avg = 36 MS/s 97 3.3.5 Measurement results In this prototype, the subranging-based architecture can also be configured into an 18-level flash-based architecture for comparison. The spectra measured using the flash-based and subranging-based configurations are illustrated in Figure 3.31. For reference, the ADC outputs are reconstructed with spline interpolation. The timeout mechanism of the subranging architecture is programmed to have the same F s,avg instead of its maximum F s,avg of 126 MS/s without any event filtering for facilitating a fair comparison. The numerical simulation shows that the achievable SFDR should be more than 90 dB without circuit non-idealities. However, because of the limited number of samples available during data acquisition through the logic analyzer, the measured SFDR is bounded by the noise floor. Nevertheless, it shows >15 dB improvement with a 1 MHz sinusoidal input. Here, we define the following figure of merit to evaluate the efficiency of NUS: eq s,avg NUS s,norm s,norm BW , where 2 NF F FF η≡≡ (3.6) where N eq is the equivalent number of voltage quantization levels when a flash-based NUS ADC is used that yields the same SFDR as the targeted NUS ADC given the same 98 Figure 3.32: Measured SFDR and F s,avg with different T out settings (F in = 1 MHz). input signal and reconstruction method. We normalize F s,avg with twice the signal bandwidth (F BW ), that is, the Nyquist rate, because the number of nonuniform samples increases proportionally with F in . By normalizing F s,avg , we can ensure a fair comparison of the efficiency of NUS with different F BW . Finally, a larger value of η NUS indicates a lower F s,norm , which means fewer samples are needed for the same SFDR or a higher SFDR value can be achieved with the same F s,norm . In other words, a higher η NUS 0 50 150 100 200 250 300 55 60 65 70 75 80 Flash-Based Subranging-Based Timeout Setting (Tout / 500 ps) 50 SFDR (dB) 0 50 150 100 200 250 300 Timeout Setting (Tout / 500 ps) 70 80 90 100 110 120 60 50 40 20 30 Flash-Based Subranging-Based Fs,avg (MS/s) 99 Figure 3.33: Measured SFDR, SNDR, and η NUS for different input frequencies. 0 2 60 65 70 75 80 85 Flash-Based Subranging-Based 55 SFDR (dB) 4 6 8 10 12 14 16 18 20 Input Frequency (MHz) 0 2 55 60 65 70 Flash-Based Subranging-Based 50 SNDR (dB) 4 6 8 10 12 14 16 18 20 Input Frequency (MHz) 0 2 10 100 Flash-Based Subranging-Based 1 4 6 8 10 12 14 16 18 20 Input Frequency (MHz) ηNUS 100 indicates higher efficiency of the NUS ADC architecture. Given the same F s,norm , the proof-of-concept prototype achieves N eq > 38 with N coarse + N fine = 18, which translates into a more than 2× higher η NUS compared to that of the flash-based NUS ADC, where N eq = N flash = 18. Figure 3.32 shows the measured SFDR and F s,avg with different timeout settings. The figure indicates that the subranging architecture maintains its improved SFDR even when F s,avg is lower than that of the flash-based architecture, which proves the effectiveness of the timeout mechanism. When T out is small, SFDR is limited by the noise floor. However, SFDR starts degrading whenever the amplitude quantization noise, that is, the interpolation error during signal reconstruction, plays a role. Until T out is adequately large to filter all the level-crossing events generated in the fine stage, the subranging-based architecture acts as a 15-level flash architecture with SFDR of approximately 60 dB. The measured dynamic performances for different input frequencies are shown in Figure 3.33. SFDR is calculated from the entire spectrum up to half of (TDC resolution) −1 . At low input frequencies, SFDR is bounded by the noise floor because of measurement limitations, but it improves as the input frequency increases. This is because F s,avg is proportional to the input frequency, which spreads the noise over a wider bandwidth, resulting in a lower noise floor [18]. Moreover, it explains the peak SNDR at the input frequency of 15 MHz. However, at higher input frequencies, SFDR decreases because of 101 Figure 3.34: Measured spectra with a blocker 73 dB higher than the desired signal. Figure 3.35: Chip micrograph. comparator delay variation. We observe that η NUS is higher than that of the 18-level flash-based configuration for input frequencies covering the entire bandwidth, which proves the superiority of the subranging architecture. 1 1 10 100 100 0.1 -120 -100 -80 -60 -40 -20 0 Amplitude (dBFS) 10 1 Frequency (MHz) Flash-Based (Nflash = 18) 100 0.1 -120 -100 -80 -60 -40 -20 0 Amplitude (dBFS) 10 1 Frequency (MHz) Subranging-Based (Ncoarse = 15, Nfine = 3) 1 1 10 100 SFDR improved > 13 dB Blocker Signal Blocker Signal TDC Pulse Combiner 1 st Stage (Coarse) Output Buffer 2 nd Stage (Fine) SPI 2.12 mm 1.72 mm 102 This Work [18] [31] [37] Bandwidth 20 MHz 20 MHz 20 KHz 40 MHz NUS η a 100 (adjustable) 50 (fixed) ~10 (adaptive) 50 (fixed) Power 28 mW 30 mW 9 μW 36 μW SFDR 80 dB (F in = 5 MHz) 70 dB (F in = 19 MHz) 58 dB (F in = 5 MHz) 56 dB (F in = 19 MHz) 58.3 dB (F in = 1 KHz) – SNDR 59 dB (F in = 490 KHz) 65.1 dB (F in = 19 MHz) 54 dB (F in = 490 KHz) 59.9 dB (F in = 19 MHz) 47 dB (F in = 100 Hz) 54 dB (F in = 20 KHz) 32 dB (F in = 10 MHz) a Considering the case of F in ≈ 0.05F BW . Table 3.2: Comparison of proposed subranging-based NUS ADC with ADCs utilizing nonuniform samples. In Figure 3.34, a blocker 73 dB higher than the desired signal at 1 MHz is injected at 490 KHz to confirm that the NUS ADC can detect a weak signal in the presence of a considerably stronger signal. The third harmonic of the blocker limits the measured SFDR and the subranging-based architecture shows >13 dB improvement in SFDR compared to that of the flash-based architecture. The chip consumes an active area of 0.7 mm 2 and peak power of 28 mW, while the voltage and time quantizer consume 20 mW and 8 mW, respectively. A micrograph of the chip is presented in Figure 3.35. Table 3.2 summarizes a comparison of this prototype with ADCs utilizing nonuniform sampling. It 103 achieves the highest SFDR and SNDR, along with the highest η NUS , among all the ADCs compared here. 3.3.6 Conclusion We proposed and implemented a two-stage subranging-based NUS ADC architecture that: 1) preserves the alias-free sampling property; 2) reduces the required number of comparators compared to that in the flash-based architecture given a certain voltage quantization resolution; and 3) adjusts the average sampling rate by using the built-in timeout mechanism. The proposed NUS ADC architecture is more flexible, which allows designers to freely choose the desired resolution and average sampling rate independently based on their specific needs. 104 Chapter 4 VCO-Based Nonuniform Sampling ADC 4.1 Review of nonuniform sampling ADC An NUS ADC with an NU DSP is shown schematically in Figure 4.1. The amplitude of the input signal is first nonuniformly sampled by level-crossing quantization. Then, the time instants of the level-crossing events are quantized with time resolution of T Q to generate nonuniform samples [x in (t k ), Q[t k ]]. The following NU DSP [1] first interpolates between samples to reconstruct a CT signal x out (t), which is composed of the input signal, as well as amplitude and time quantization errors. With technology scaling, the application of a finer time resolution can reduce the effect of spectral aliasing on the time quantization. Thus, the amplitude quantization error can be attenuated by means of analog-equivalent filtering during signal reconstruction. Finally, the filtered output y(t) is sampled by an embedded uniform sampler operating at the resampling rate F rs , which only needs to satisfy the Nyquist rate of the desired signal bandwidth F BW to generate the 105 Figure 4.1: Architecture of the conventional NUS ADC. final discrete-time digital output y[n]. This NUS ADC architecture exhibits an improved SQNR compared to conventional Nyquist-rate ADCs with the same number of amplitude quantization levels. In addition, on the top level, it appears as a uniformly sampled ADC that can interact seamlessly with the existing synchronous DSP. A conventional method for implementing amplitude quantization involves using the voltage-domain level crossing, which can be achieved by using a bank of CT comparators and a reference-voltage generator [18] [38] [14]. Comparator non-idealities, for instance, Amp. & Time Quantization Interpolation (e.g. ZOH) Reconstruction (filtering) xin(t) xout(t) xin(tk) Q[tk] H(f) f rs rs 1 F T = y(t) y[n] Nonuniform DSP f ω Y(ω) Y(f ) 0.5Frs f Xout(f ) Quant. Error FBW Xin(f ) Signal f (xin(tk),Q[tk]) t t t n 106 offset, finite gain, and finite bandwidth, can generate input-dependent propagation delay, which can cause distortions at the ADC outputs and, thus, limit performance [18] [13]. In addition, the noise at the comparator input may trigger multiple unexpected level crossings, requiring removal of these events [38] or the introduction of hysteresis in the comparator [18]. When the input amplitude is smaller, the level crossing quantizer will generate fewer samples and increase the amplitude quantization error. This can be solved by adding dithering to the input signal [39], but doing so requires additional hardware. 4.2 Noise-shaping nonuniform sampling ADC To further improve the SNR, we can add an integrator in front of the level-crossing quantizer, followed by a differentiator to shape the quantization error [37]. However, the input voltage of the quantizer can be overloaded in doing so, which imposes a limitation on this architecture. Thus, we employ a different approach to integrate the input signal and achieve level-crossing quantization in the phase domain [40]. With the noise shaping and phase-domain level crossing, the performance of the proposed noise-shaping NUS (NS-NUS) ADC architecture improves, and the implementation costs of both the analog and digital circuitries decrease. 107 4.2.1 VCO-based integrator and amplitude quantizer Instead of a voltage-domain integrator, voltage-controlled oscillators (VCOs) have been widely used in conventional uniform sampling ADCs as integrators or quantizers. This method has been demonstrated with the open-loop architecture [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] and inside the delta–sigma modulator (DSM) [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69]. In addition, VCO can be utilized for CT data conversion [40] [70] [71] [72] through the phase-domain level crossing [40], followed by CT DSP [73] for signal reconstruction. In [74] [75], we proposed the use of VCO in the NUS ADC architecture, which performs integration and level crossing in the phase domain. The phase-domain comparison naturally eliminates the need for any voltage-domain comparator or reference voltage generation. Thus, it can substantially increase the signal bandwidth and reduce the implementation costs on both analog and digital circuitries compared to those of the existing voltage-domain NUS ADCs [18] [38]. In addition, SQNR can be improved by leveraging the noise shaping and inherent dithering through the free-running oscillation of the VCO. Notably, in the voltage-domain level-crossing quantization, because the average sampling rate F s,avg is adapted to the input signal, the proposed flash-based and subranging-based NUS ADCs can potentially achieve alias-free input sampling. However, because F s,avg in the proposed architecture is determined by the number of 108 Figure 4.2: Phase-domain level crossing with a sinusoidal input. phase-quantization levels within every 2π and the free-running frequency of oscillator, the input alias-free bandwidth is fixed. Therefore, there is a design tradeoff between these two NUS ADC architectures. 4.2.2 Phase-domain level crossing The idea of using a VCO in an ADC was introduced in [76] and [77]. Based on the oscillator output, the input signal is integrated and presented in phase, which automatically wraps an interval of 2π without saturating the following circuits. Motivated by this unique property, we employ a VCO instead of a voltage-domain integrator in the NUS ADC architecture to overcome voltage overload. Because the integrated input signal at the VCO output is presented in phase, the conventional voltage-domain level crossing should migrate to the phase-domain level crossing, as illustrated in Figure 4.2. The VCO Vin(t ) t t 2π 4π 6π 8π t 2π 0 10π in () t Φ in,wrap () t Φ 2 N π 109 (a) (b) Figure 4.3: (a) Time-domain waveform of the voltage-domain level crossing. (b) Time-domain waveform of the phase-domain level crossing when using a multi-stage VCRO. first integrates and converts the voltage input V in (t) into the phase Φ in (t). Because of the free-running oscillation frequency F FR , the phase will continue to increase and wrap within 2π. By monitoring the zero-crossing events at the VCO output, we can naturally obtain a phase-domain level crossing at π and 2π with no saturation. If a finer phase-quantization level is required, we can design a multi-phase VCO, for example, a multi-stage voltage-controlled RO (VCRO) that outputs phase-domain level crossings at intervals of 2π/N by monitoring the zero-crossing events at all internal nodes, where N is the number of phase-quantization levels within the interval 2π. Notably, the average Vref,N Vref,1 Vin Vout,N Vout,1 Vref,1 Vref,2 Vin Vout,1 Vout,2 Vout,1 Vout,2 2π/N Vout,1 Vout,2 Vout,N/2 Vin in Φ 110 sampling rate F s,avg can be approximated as NF FR if the free-running oscillation frequency is considerably higher than the input signal frequency. To explain the concept of phase-domain level crossing, we first review the time-domain waveform of level crossing in the voltage domain, as illustrated in Figure 4.3(a). The comparator toggles the output whenever the input crosses its reference voltage. These transitions preserve the time instants of level crossings and can be used to trigger the time quantizer. Equivalently, the phase-domain level crossing generates these transitions when Φ in (t) crosses every 2π/N. Therefore, the internal nodes of a multi-phase VCO exhibit the same behavior as that of the comparator outputs, as shown in Figure 4.3(b), where the phase difference between two adjacent nodes is 2π/N. This suggests that the phase comparison is automatically built-in and does not require a CT comparator or reference generator, which saves a significant amount of power and area compared to the voltage-domain level crossing. In addition, it prevents unexpected toggling from the noise and solves the problem of small-input amplitude by leveraging an inherent sawtooth dither signal in the phase. in,dither in FR VCO in 0 () () 2 2 () Φ Φ π π = + ∫ t t t F t K V t dt (4.1) 111 Figure 4.4: Signal flow of NS-NUS ADC with the phase-domain level crossing. where K VCO denotes the VCO gain. Because the phase is not overloaded at the quantizer input, amplitude control of the dither signal [39] is not required. The subsequent differentiator, which is used to remove the integration on the input, also converts the dither signal to DC, which can then be removed by the differential architecture. 4.2.3 Signal flow and nonuniform DSP computation Figure 4.4 shows the signal flow of the proposed NS-NUS ADC architecture with the phase-domain level crossing. Because integration occurs before the quantizer, differentiation is added afterward. ZOH interpolation is employed because of its simplicity. This operation interpolates nonuniform samples into a staircase waveform with a constant step size ΔΦ = 2π/N. After differentiation, where the scaling factor of Vin(t) Q[tk] rs rs 1 FT = y[n] t y[n] Vout(t) t Vin(t) t d dt Φ ZOH VCO n Q[tk] Q[tk] A Trs Vout(t) Phase & Time Quantization H(f) in () k t Φ ZOH () t Φ in () k t Φ Δ Φ 112 Figure 4.5: Proposed VCO-based NS-NUS ADC architecture. 1/2πK VCO is embedded, the signal transforms into an impulse train with a constant amplitude A = ΔΦ/2πK VCO at Q[t k ] and with a value of 0 between nonuniform samples. This signal is further filtered to remove the quantization error and perform uniformly sampling with the resampling rate of F rs . The only required information about the impulse train is quantized time information because A is a constant, predefined design parameter. Because Q[t k ] is already available at the quantizer output, ZOH and the differentiation operation can be merged into a single block that performs zero padding between nonuniform samples. Thus, we can further simplify this architecture, resulting in the final proposed architecture shown in Figure 4.5 without the need for Φ in (t k ). Considering the actual implementation of the NU DSP shown in Figure 4.1, the interpolation, reconstruction, and resampling operations can be integrated into a single equation y[n] = x out (t) ∗ h(t), where t = nT rs [1], x out (t) is the interpolation output, h(t) is Vin(t) Q[tk] rs rs 1 FT = y[n] Zero Padding VCO Vout(t) Nonuniform DSP Phase & Time Quantization H(f) in () k t Φ 113 the desired impulse response of the reconstruction filter, and T rs is the period of the resampling clock. In [18], y[n] is calculated as 1 Q[ ] out rs Q[ ] [] ( ) ( ) + = ⋅− ∑ ∫ k k t k k t y n x t h nT t dt (4.2) assuming ZOH interpolation. Although the integration operation can be precomputed, it requires multiplication, which increases the implementation complexity. In the proposed architecture, because of the unique properties of the impulse train (constant amplitude and zeros between nonuniform samples), the computation can be simplified to only the summation rs [ ] ( Q[ ]) = − ∑ k k y n A h nT t . (4.3) The simplified NU DSP can reduce the complexity of the digital circuitry compared to that of the circuitry in the voltage-domain NUS ADC architecture. A representative design example is discussed in Section 4.5.5. 114 (a) (b) (c) (d) Figure 4.6: (a) the combined phase and time quantization shown in Figure 4.4 is separated into phase quantization and time quantization. (b) Nonuniform ZOH is moved to precede the time quantization. The time quantization is modeled as a uniform sampler clocked at the effective sampling rate of F s,eff = 1/T Q and is followed by uniform ZOH with a period of T Q . (c) Differentiation and uniform ZOH are moved to precede the sampler. (d) VCO, phase quantization, nonuniform ZOH, and differentiation are combined into a PFM. ZOH Time Quant. Q[ ] k t out () Vt (nonuniform) k t Phase Quant. VCO in () Vt d dt Φ in () t Φ in () k t Φ in () k t Φ ZOH () t Φ ZOH (nonuniform) ZOH (uniform) s,eff F out () Vt k t Phase Quant. VCO in () Vt d dt Φ in () t Φ in () k t Φ ZOH () t Φ ZOH (nonuniform) s,eff F Zero Padding out () Vt k t Phase Quant. VCO in () Vt HZOH(s) d dt Φ in () t Φ in () k t Φ HZOH(s) s,eff F Zero Padding out () Vt Pulse Frequency Modulation in () Vt PFM () Vt NS () Vt 115 4.3 Analysis of quantization error The quantization error of the voltage-domain NUS ADC was analyzed in [1]. However, in the architecture proposed in the present study, we apply integration before amplitude quantization with the additional dithering signal. Therefore, the results in [1] cannot be applied directly. In this section, we show that the quantization error of the proposed architecture is equivalent to that of a uniformly sampled VCO-based ADC sampled at the effective sampling rate, which is 1/T Q . Thus, quantization error analysis based on pulse-frequency modulation (PFM) [71] [78] [79] [80] can be applied to estimate the performance of the proposed architecture. However, it is noteworthy that although the quantization error remains the same, the actual output data rate, that is, the input sampling rate, can be decoupled from the effective sampling rate in the proposed architecture. We first separate the combined phase and time quantization in Figure 4.4 into two blocks, as shown in Figure 4.6(a). Because phase quantization is achieved by means of the level-crossing quantization, the nonuniform sample [Φ in (t k ), t k ] contains information about the phase amplitude and time instant of the level-crossing event without introducing any quantization error. After quantizing t k into a finite time grid Q[t k ], ZOH interpolation is applied between nonuniform samples to reconstruct a CT signal Φ ZOH (t), 116 which introduces the interpolation error, that is, the amplitude quantization error. The final differentiation removes the integration on the input signal and recovers the desired information. Instead of performing the ZOH on time-quantized nonuniform samples [Φ in (t k ), Q[t k ]], the signal flow in Figure 4.6(a) is modified by first applying ZOH directly to [Φ in (t k ), t k ], as shown in Figure 4.6(b). To obtain the same output at Φ ZOH (t), the time quantization can be modeled as a uniform sampler clocked at the effective sampling rate of F s,eff = 1/T Q , followed by a ZOH operation, which holds the uniformly sampled values with period T Q to generate the CT waveform. We can further move the differentiation and the uniform ZOH with fixed period T Q to precede the sampler. Then, the differentiation output is convolved with an impulse response that is the same as output of uniform ZOH, which is a rectangular function with fixed width T Q and can be represented with the Laplace domain representation [81] H ZOH (s) = (1 − e −sT Q )/s, as shown in Figure 4.6(c). H ZOH (s) denotes a low-pass filter with notches at multiple integers of F s,eff . In addition, the conversion of discrete time to CT is achieved by means of zero padding after the sampler. In the proposed architecture, the amplitude quantization error is first-order shaped and aliased at integer multiples of the effective sampling rate. In the following discussion, the aliased amplitude quantization error is termed the time quantization error [1]. In the conventional VCO-based ADC, the notches of the inherent input anti-aliasing 117 filter are at integer multiples of the actual sampling rate. However, in the proposed architecture, the notches are at integer multiples of the effective sampling rate. Thus, there is a design tradeoff when considering the unwanted out-of-band input signals. Figure 4.6(c) indicates that the VCO, phase quantization, nonuniform ZOH, and differentiation can be merged together to act the same as PFM. The output of the PFM will be fed to H ZOH (s), as shown in Figure 4.6(d). The details of the PFM operation have been comprehensively analyzed and generalized in [71] [78] [79] [80], and further discussion on this topic is outside of the scope of this dissertation. To analyze the upper performance bound of the proposed architecture, which contains only the quantization error, we consider a simple case of a sinusoidal input signal V in (t) = A in cos(2πF in t). The amplitude quantization error represented in the voltage domain at the PFM output before being aliased and shaped by H ZOH (s) can be written as ( ) ( ) ( ) in VCO sb in Q,PFM 1 sb sb (, ) 1 ( ) (, ) (, ) VCO n qn qNA K f q n J Fq V f N f f qn f f qn K δδ ∞∞ = = −∞ ⋅ ≈ ⋅ + + − ∑∑ (4.4) where f sb (q, n) = qF s,avg + nF in , and J n (z) is the Bessel function of the first kind, of order n. It is scaled with the number of quantization levels in the oscillator, as we expected. By contrast, the desired signal can be derived as 118 ( ) ( ) ( ) in sig,PFM in in ( ) 2 δδ ≈⋅ + + − A V f f F fF . (4.5) To compare the time quantization errors aliased from ±rF s,eff , where r is a positive integer, the SQNR r at the proposed NS-NUS ADC output can be defined as max min 2 in VCO ZOH in 10 2 in VCO sb in 1 ZOH sb (2 ) 2 SQNR =10log (, ) ( 2 ( , )) r n n q nn NA K H jF qNA K f q n J F q H j f qn π π ∞ = = ⋅ ⋅ ⋅ ∑∑ (4.6) where n min = ceil[(rF s,eff − F BW − qF s,avg )/F in ], and n max = floor[(rF s,eff + F BW − qF s,avg )/F in ]. SQNR 0 is then referred to the amplitude quantitation error originally located within F BW before aliasing. We can further define A in K VCO = αF FR , which gives NA in K VCO ≈ αF s,avg . In this prototype, to avoid overloading of the oscillator due to severe nonlinearity, α max is set to approximately 0.7. As discussed in [71], (4.6) exhibits nonmonotonic behavior in terms of A in K VCO , F in , F BW , and F FR . Thus, we use the following parameters in this prototype as a case study: N = 4, T Q = 6 ps, F FR = 1 GHz, and F BW = 200 MHz. Considering the case of full-scale input, where A in K VCO = α max F FR = 0.7F FR , (4.6) is calculated over different input frequencies below F BW and plotted in 119 Figure 4.7: SQNR at the proposed NS-NUS ADC output calculated from (4.6), numerical simulation, and [41] over different input frequencies with the full-scale input A in K VCO = 0.7F FR . Figure 4.7. For this specific case, SQNR tot , which includes all quantization errors, is dominated primarily by the time quantization error in the proposed architecture. Thus, a smaller T Q , that is, a higher F s,eff , is desirable. Because the choice of T Q in the proposed architecture is decoupled from the actual output data rate determined by F FR and N, another degree of freedom is available in the design. To verify the equivalence of Figure 4.6(a) with Figure 4.6(d) in terms of the quantization error, the model schematized in Figure 4.6(a) is numerically simulated with the same parameters as those used to calculate (4.6). The difference between the simulated SQNR and SQNR tot is less than 1.5 dB in this case study, which indicates that the PFM operation can be applied to estimate the performance of the proposed architecture. Notably, because the proposed architecture leverages a fine T Q , that is, F s,eff is considerably higher than F s,avg , the assumption of Input Frequency (MHz) 20 0 45 (dB) 40 60 80 100 120 55 60 65 70 75 80 50 SQNR4 SQNR3 SQNR2 SQNR1 SQNRtot SQNR (sim.) SQNR ([41]) 140 160 180 200 120 white noise on the quantization error [41] cannot be applied because doing so would result in a deviation of more than 17 dB, as shown in Figure 4.7. Considering another case in which the input is a DC voltage A DC , the VCO will oscillate at a constant frequency F FR + A DC K VCO and generate spurious tones at integer multiples of N(F FR + A DC K VCO ). After time quantization, these tones can be aliased back to the desired signal band. These tones are similar to the spurious tones that exist in the conventional first-order VCO-based ADCs for DC or low-amplitude input signals [42]. 4.4 Comparison with uniformly sampled open-loop VCO-based ADC Uniformly oversampled open-loop VCO-based ADCs typically require a higher oversampling ratio (OSR) (> 32) or a higher amplitude quantizer resolution (> 4 bit) because the quantization errors are only first-order shaped and then aliased at the oversampling rate on the input signal, which is equal to the actual output data rate. However, in the ADC architecture proposed herein, the quantization errors are aliased at a considerably higher frequency (called the effective sampling rate F s,eff in the context of this thesis) than the actual output data rate (equal to F s,avg ). The effective sampling rate is determined as 1/T Q , where T Q is the time quantizer resolution. As a result, a higher F s,eff 121 Figure 4.8: Block diagram and implementation of the proposed VCO-based NS-NUS ADC. can be achieved by employing a finer time-quantizer resolution without increasing the actual output data rate. The quantization errors are shaped to a considerably higher frequency (0.5F s,eff ), which allows the digital anti-aliasing filter [1] to remove the out-of-band quantization errors before they are aliased at the final decimation. In this case, given the same output data rate, the proposed architecture can potentially achieve a wider signal bandwidth and fewer amplitude quantization levels. 4.5 Prototype of VCO-based NUS ADC with 200-MHz bandwidth and 60-dB dynamic range Figure 4.8 shows a block diagram of the proposed VCO-based NS-NUS ADC architecture depicted in Figure 4.5. Voltage-to-phase conversion, including phase Nonuniform Bit Storage & Linearity Calibration 4 Vinn VCRO & Buffer Vinp 4 18 18 6 SAFF*18 2 φ 0~17 φ 0~17 φ 0 φ 0 counter 6 6 6 encoder 8 8 8 8 Frs = Fclk/8 Q[tk,2 π] Q[tk,0.5 π] Q[tk, π] Q[tk,1.5 π] 4 4 TQ Time Quantizer φ 0 φ 0 Reference 4 Nonuniform Bit Storage & Nonlinearity Estimation ÷ 8 encoder Q Q Q Q D D Q D D Q D D Q D D Q D D D2S D2S: Differential to Single-ended Buffer Positive Path Negative Path 18 18 ππ π π 0.5 1.5 2 ,, , V VV V Fine Coarse φ 0 φ 1 φ 0 Fclk TQ = Fclk -1 /36 Nonuniform DSP & Nonlinearity Correction on-chip off-chip 122 Figure 4.9: Schematic diagram of VCRO and buffer. quantization, is achieved by first feeding the differential input signal into two pseudo-differential multi-phase VCOs. Their outputs are buffered and sent to the time quantizer. The time quantizer records and digitizes the time instants of the nonuniformly occurring transitions at the VCO outputs to generate Q[t k ], as shown in Figure 4.5. Before the NU DSP, these quantized nonuniform samples are processed using fully synthesized nonuniform bit storage, which first buffers the nonuniform samples from the average output data rate ( ∼4 GS/s) to the resampling rate ( ∼580 MS/s) and then combines and Vin dummy dummy outp inn π 0.5 V π 2 V inp op inn op outn outp Buffer π V π 1.5 V inp outn on inp on Delay Cell 123 sorts them chronologically from four different input paths. Linearity calibration is separated into on-chip nonlinearity estimation and off-chip nonlinearity correction embedded in the NU DSP. Several key building blocks and a representative implementation of the NU DSP, including the proposed nonlinearity correction, are elaborated in this section. 4.5.1 Voltage-controlled ring oscillator The multi-phase VCO implemented using a four-stage VCRO is shown in Figure 4.9. It is composed mainly of pseudo-differential current-starved delay cells. There are four outputs, namely, V 0.5π , V π , V 1.5π , and V 2π , and their rising edges represent the phase-domain level crossings. To reduce flicker noise, a PMOS (W/L = 64 μm/0.48 μm) is selected as the input device. The free-running oscillation frequency can be set properly during calibration by configuring V inp = V inn = V incm and adjusting V incm according to the value of F FR calculated from the quantized time information. Notably, it is possible for the calibration to operate in the background by monitoring the average sampling rate. The buffers connected to the internal nodes of the VCRO shown in Figure 4.9 are used to prevent the large kickback noise of the flip-flops from corrupting the transition edges, that is, level-crossing events. In addition, these buffers convert the differential outputs of the VCRO to single-ended outputs, thus simplifying the design of the time 124 quantizer. Any input-dependent propagation delay added to the time instants of the level crossings will generate distortions in the reconstructed output and should therefore be considered in the design phase. In the first buffering stage, a tail current is included to suppress any input common-mode-dependent propagation delay. Because the zero crossing of a single-ended output is more vulnerable to the logic threshold level than the differential output at the input of the following building blocks, an extra delay variation is introduced on different signal paths. To mitigate this issue, the transition edges are sharpened by the buffers, which are designed to provide adequate gain. Buffer offset has an effect similar to that of a mismatch between VCO delay cells, which introduces errors at the time instants of level-crossing events. A Monte Carlo simulation is performed during the design phase to ensure that this error is negligible compared to the quantization error. Because of the mismatch on the tuning curve between the two oscillators, the pseudo-differential configuration can only reduce the even-order harmonics without complete nullification. The results of a Monte Carlo simulation indicate that with the use of properly sized transistors and carefully laid out VCROs, the even-order harmonics are lower than −75 dBc for the full-scale single sinusoidal input. Compared to the odd-order harmonics, degradation due to mismatch is negligible in this prototype. With supply voltages of 1.05 V and V incm = 0.55 V, the oscillator runs at F FR of 1 GHz and K VCO of 4.8 125 GHz/V. Considering the single-ended full-scale input of A FS = 0.15 V, the oscillators are designed to have an SNR of more than 70 dB over the 200-MHz bandwidth. Without any calibration, the third-order harmonic (HD3) at the oscillator outputs ranges from −40 dBc to −45 dBc for an input amplitude close to the full scale, which can limit the performance of the entire ADC. Thus, a linearity calibration, described in Section 4.5.4, is proposed to compensate for the errors in the phase domain. In addition, the performance degradations due to temperature and supply voltage variations are discussed in Section 4.5.6. 4.5.2 Time quantizer The time quantizer shown in Figure 4.8 contains two-stage time-strobing circuits and a reference time generator. Quantization at the time instants of the level-crossing events is achieved by strobing the reference time ( 0-17 0-17 and φφ ) by using the nonuniform rising edges of the VCRO outputs. Voltage swing is reduced to lower the power consumption of the buffers at the reference time generator outputs. Thus, to achieve superior sensitivity, sense-amplifier-based flip-flops (SAFF) with preamplifiers are used in the first stage of the time-strobing circuit. Because of the finite word length in digital outputs, the time code will continue to wrap. To properly unwrap the strobed time information, we ensure that there is at least one nonuniform sample before every wraparound. Considering the extreme case in which a dc input is applied, resulting in the minimum VCO oscillation 126 Figure 4.10: Schematic diagram of the reference time regenerator in the time quantizer. frequency (F VCO,min = F FR − A FS K VCO ), the word length of each time code can be determined as NT Q > log 2 (1/F vco,min NT Q ). Thus, for a targeted time resolution of 6 ps, NT Q = 8 is selected for this prototype. The implementation of a shared reference time generator between the positive and negative paths is shown in Figure 4.10. It consists primarily of a six-stage pseudo-differential RO with current-starved inverters. To mitigate the mismatch between φ ′ 12 φ 17 φ 0 φ 0 Resistive Phase Interpolation clock source Vbp Vbn inp outn CML buffer replica φ ′ 0 φ ′ 0 φ ′ 3 φ ′ 3 φ ′ 6 φ ′ 6 φ ′ 9 φ ′ 9 φ ′ 15 φ ′ 15 φ ′ 12 φ 17 Injection Locking Fclk 127 Figure 4.11: System-level simulation of SNDR for different values of jitter in the reference time. stages, cross-coupled resistors are utilized [18]. The time resolution is increased by 3× with the use of passive phase interpolation with resistors [28]. Thus, with a T Q of 6 ps and a total of 36 phases within one clock cycle, the expected oscillation frequency is 4.63 GHz. However, a free-running RO can yield excessive jitter and frequency drift over time, inducing slow variations in T Q . During time strobing, the jitter in the reference time can disturb the ideal Q[t k ]. This shifts each impulse at the ADC output earlier or later, thus leading to the introduction of additional errors. Therefore, to achieve a well-defined T Q and reduce jitter, the oscillator is injection-locked by using a low-noise clock source (F clk ). Assuming the application of a clock source operating at 4.63 GHz with a root mean square (RMS) jitter of less than 1 ps, the jitter of the reference time exhibits a standard deviation of less than 600 fs, according to the results of a transient noise analysis f in = 5 MHz f in = 15 MHz f in = 65 MHz f in = 125 MHz f in = 185 MHz f in = 200 MHz 0 0.02 0.04 0.06 0.08 0.1 0.12 SNDR (dB) 65 63 64 65.5 64.5 63.5 Fin=5MHz Fin=15MHz Fin=65MHz Fin=125MHz Fin=185MHz Fin=200MHz σ jQ (normalized to ) tT 128 Figure 4.12: System-level simulation of SNDR for the reference time mismatch. simulation. To demonstrate the impact of jitter on the performance of the proposed architecture, we use the same design parameters as those used in Section 4.3 with A in = − 0.5 dBFS and perform a system-level simulation with different values of jitter in the reference time. Figure 4.11 shows the average SNDR computed from 20 simulations, including the errors caused by quantization and jitter. Compared to the simulated SNDR of the conventional first-order noise-shaped VCO-based ADC with the same quantization errors, the SNDR of the proposed architecture is approximately 1.5 dB higher for F in = 200 MHz and j t σ = 600 fs. In addition, to mitigate the DNL in the clock-injected node, replicas of current-starved inverters are placed at the last stage of the clock buffers to match the voltage swing at the internal nodes. Figure 4.12 shows the average SNDR for a 0 SNDR (dB) 63 65 61 59 0.05 0.1 0.15 0.2 0.25 0.3 σ DNL Q (normalized to ) T 129 Figure 4.13: Implementation of nonuniform bit storage. sweep of the standard deviation of the DNL ( DNL σ ) in the reference time with F in = 65 MHz and A in = −0.5 dBFS. Each point corresponds to the average of more than 10 simulations. A Monte Carlo simulation performed using this prototype yielded a DNL σ value less than 0.06T Q . 4.5.3 Nonuniform bit storage Figure 4.13 shows the implementation of the nonuniform bit storage, which serves as the interface with the NU DSP. The nonuniform samples at the time quantizer outputs Q[t k,0.5π ], Q[t k,π ], Q[t k,1.5π ], and Q[t k,2π ] are first buffered by four parallel event-driven first-in first-out (FIFO) units. Each FIFO unit contains two banks of flip-flops. The first bank (marked in red) is clocked by the phase-crossing event from the individual VCRO D Q D Q D Q Initial Phase Detector Gray Counter (0 to 2) 1-to-3 DEMUX 8 D Q Frs (resampling clock) 2 D Q 2 D Q D Q D Q 2 8 8 8 4 NNUS Σ 32 32 32 reset ϕinit 2 Event-Driven FIFO Nonuniform Sample Combine & Sort Q[tk] (phase-crossing event from VCRO) π 0.5 V π 2 V π ,2 Q[ ] k t π ,0.5 Q[ ] k t π NUS,0.5 N 130 output; the second bank (marked in blue) is clocked by the resampling rate F rs , which is also the clock frequency of the following NU DSP. Parallelization of the input data is achieved using a counter and a demultiplexer. Because the instantaneous output data rate of the time quantizer varies with the VCRO oscillation frequency F VCO , the number of nonuniform samples within each resampling period (T rs = 1/F rs ) is not constant. To calculate the required depth of each FIFO unit, we first define N NUS,i [n] as the number of nonuniform samples between (n − 1)T rs and nT rs , where n is an integer, and i is 0.5π, π, 1.5π, and 2π. The depth of each FIFO unit should be greater than the maximum possible value of N NUS,i , where VCO,max FR FS VCO NUS, rs rs ( )( ) i F F A K N floor floor FF + ≤= . (4.7) To calculate N NUS,i [n], which is the difference between the counter values at two consecutive resampling instants, the counter output is sampled using flip-flops clocked at F rs . Because this process crosses two different clock domains, a Gray code counter is used to mitigate the resulting metastability. In addition, 2 NUS NUS, 0.5 [] [] i i Nn N n π π = = ∑ represents the total number of nonuniform samples between (n − 1)T rs and nT rs . Because the phases are crossed sequentially, we can properly combine and sort the nonuniform 131 Figure 4.14: Schematic diagram of the initial phase detector. samples chronologically by using N NUS [n] and Φ start [n], where Φ start [n] denotes the location of the first phase between (n − 1)T rs and nT rs . To find Φ start [n], the location of the first phase after releasing the reset during power up Φ init is detected by the initial phase detector, as shown in Figure 4.14. The pulse generator converts the rising edges of the VCRO outputs into pulses. After releasing the reset, whenever a pulse enters one of the four channels, its SR latch output is set and maintained in the “high” state. All four SR latches are subsequently disabled by forcing the input of “S” to 0. Then, Φ start [n] can be calculated as 1 init NUS 1 [] n p Np Φ − = + ∑ . Finally, the quantized time information Q[t k ] is processed by the linearity calibration and the NU DSP discussed in Sections 4.5.4 and Section 4.5.5, respectively. S R π 0.5 V Q PG Encoder 2 PG: Pulse Generator reset π 2 V SR Latch D Q R delay Φ init 132 (a) (b) Figure 4.15: (a) Plots of the desired F VCO and Δt versus the input amplitude. (b) Plot of the measured Δt versus the input amplitude, and the relationship between Δt ideal and Δt meas . 4.5.4 Linearity calibration Ideally, the VCO should convert the input voltage to frequency linearly by using a constant K VCO . However, the nonlinear characteristics of transistors can generate distortions at the ADC output, thus limiting the SNDR. To mitigate this problem, we propose a calibration scheme by utilizing quantized time information to compensate for errors in the phase domain. The quantized time difference between adjacent phase crossings with a spacing of 2π/N is defined as Δt. Then, Δt meas and Δt ideal denote Δt with and without nonlinearities, respectively. The calibration procedure can be divided into four steps. The first step involves building the desired linear transfer function between Δt and the input amplitude V in . To this end, we first measure the K VCO of VCRO around V in = V incm by using the F VCO calculated from 1/(N ∙ Δt). When Δt is measured using the time quantizer, the values of FVCO Vin KVCO FVCO,ideal ∆t Vin ∆tideal Vincm Vincm Vin ∆tideal Vincm ∆t ∆tideal ∆tmeas ∆tmeas 133 multiple cycles are captured and averaged to reduce the time quantization error. Then, an ideal oscillation frequency F VCO,ideal for a different V in can be obtained by linear extrapolation, and Δt ideal can be determined as 1/(N ∙ F VCO,ideal ), as shown in Figure 4.15(a). The second step involves characterizing the actual VCRO oscillation frequency F VCO,meas , that is, measuring Δt meas over the entire input range by sweeping the amplitude of the dc input or by using a low-frequency sinusoidal wave, for instance, F in << F BW . With Δt meas and Δt ideal versus V in , the relationship between Δt meas and Δt ideal can be characterized as shown in Figure 4.15(b). The process of nonlinearity estimation, including the utilization of N NUS and Q[t k ] at the nonuniform bit storage output to calculate Δt, averaging Δt over 62K samples, and estimating K VCO , is implemented on-chip. As shown in (4.1), the accumulated phase is the integration of F VCO over time. Because the actual oscillation frequency deviates from the ideal frequency, the accumulated phase is incorrect. Therefore, to achieve the linearity calibration, we estimate and compensate for this phase error. To reduce the overhead on the calibration, instead of compensating for the phase error continuously between Q[t k ] and Q[t k+1 ], we only estimate the total error within Δt and place it between two adjacent nonuniform samples for improving the approximation of the continuous phase error. Because Δt meas denotes the time difference between two phase crossings spaced by 2π/N, the 134 (a) (b) Figure 4.16: (a) Accumulated phase error within Δt meas . (b) Approximated accumulated phase error within Δt meas . accumulated phase within Δt meas is precisely 2π/N, as indicated by the dashed area in Figure 4.16(a). The excess or deficient accumulated phase is indicated by the dotted area. The third step in the calibration involves estimating this phase error, ΔΦ err . Practically, the input is not constant. As a result, F VCO varies within Δt meas , as shown in Figure 4.16(a). However, because the average sampling rate is considerably higher than the input frequency, we assume, for simplicity, that the variation of F VCO within Δt meas is negligible. Thus, we can approximate ΔΦ err as a rectangle, as shown in Figure 4.16(b), which can be calculated as FVCO t ∆tmeas π 2 N Φ err Δ FVCO,ideal FVCO,meas FVCO t ∆tmeas π 2 N Φ err Δ FVCO,ideal FVCO,meas 135 (a) (b) Figure 4.17: Phase error compensation. (a) Phase domain (after ZOH). (b) Voltage domain (after differentiation). VCO,ideal VCO,meas err VCO,meas meas ideal ideal 2 Δ () Δ Δ 2 . Δ FF NF t t Nt π Φ π − ≈ × − = × (4.8) After the phase error is computed, the fourth and final step involves compensating for this error and restoring linearity. To better illustrate the concept, ZOH and differentiation t Φ ZOH () t Q[tk] Q[tk+1] t Φ err Δ () t + + 1 Q[ ] Q[ ] 2 kk tt Φ err, Δ k t Φ ZOH,calib () t Q[tk] Q[tk+1] π 2 N t out () Vt Q[tk] Q[tk+1] t ∆ err () Vt + + 1 Q[ ] Q[ ] 2 kk tt t out,calib () V t Q[tk] Q[tk+1] π π VCO 2 2 N K Φ π err, VCO Δ 2 k K 136 are separated into two steps, but they are merged in the actual implementation. The time-domain waveforms at ZOH and the differentiation outputs are shown in Figure 4.17(a) and (b), respectively. Before compensation, the output phase increases by 2π/N at each level-crossing instant, which results in the formation of an impulse at the differentiation output. After compensating for the error between nonuniform samples, the calibrated phase at the ZOH output can be expressed as follows: 1 ZOH,calib ZOH err, 1 Q[ ] Q[ ] () () Δ () 2 k k k k tt t t ut ΦΦ Φ ∞ + = + =+− ∑ (4.9) where ΔΦ err,k denotes the ΔΦ err between Q[t k ] and Q[t k+1 ], and u(t) denotes the unit step function. In the actual implementation, we have to add another impulse train with an amplitude proportional to ΔΦ err . To simplify the implementation of the nonlinearity correction and the subsequent NU DSP, the error can be compensated for after filtering and decimation, as described in Section 4.5.5. Because ΔΦ err depends only on Δt meas , which is quantized and bounded between (4F VCO,max T Q ) −1 and (4F VCO,min T Q ) −1 , it can be precomputed and stored in a lookup table (LUT) as a function of Δt meas to reduce the required real-time computation. A numerical simulation is performed using N = 4, T Q = 6 ps, F FR = 1 GHz, K VCO = 4.8 GHz/V, and A in = 0.15 V. Nonlinearities are introduced in 137 Figure 4.18: Numerically simulated third-order harmonic with and without calibration over different input frequencies. Figure 4.19: Representative design example of the linearity correction and the NU DSP, including the reconstruction filter. the model, and the resulting third-order harmonics with and without calibration are shown in Figure 4.18. Because of the assumption of a constant F VCO within Δt in the Frequency (MHz) 0 -80 HD3 (dBc) 20 40 60 80 -70 -60 -50 -40 100 120 140 160 180 200 w/o calibration w/ calibration Nonuniform Bit Storage & Nonlinearity Estimation * Q[tk], ... * ∆tk, ... nTrs * For all samples between nTrs - td and nTrs + td y[n] AVG LUT x Σ Σ yerr[n] ycalib[n] Nonlinearity Correction hn,k = A ∙h(nTrs - Q[tk]) LUT 0.5(hn,k + hn,k+1) ΦΦ err, , Δ Δ nk 138 approximation, the quality of the calibration results deteriorates as the input frequency increases, but they remain within the design specifications of this prototype. 4.5.5 Example of nonuniform DSP implementation Figure 4.19 shows a representative design example of the NU DSP and the nonlinearity correction. The uncalibrated V out (t) and the error ΔV err (t) shown in Figure 4.17(b) are denoted by y[n] and y err [n] after filtering and decimation, respectively. The calculations of y[n] and y err [n] are separated and summed later to simplify the implementation. Following (4.3), we first calculate nT rs − Q[t k ] for all nonuniform samples within the filter duration (t d ) [41], where t d is determined by the desired filter frequency response. For the same SQNR, if we use a finer T Q to reduce F s,avg , that is, F FR or N, the requirement on the decimation filter becomes more stringent in terms of increased stopband attenuation. In other words, it offloads the analog complexity to the digital domain and is therefore expected to benefit from the technology scaling. After nT rs − Q[t k ] is calculated, h n,k = A · h(nT rs − Q[t k ]) is read from the preprogrammed LUT in real time, where A = ΔΦ/(2πK VCO ) and ΔΦ = 2π/N. All readout values are then summed up to generate the uncalibrated y[n]. In the nonlinearity correction, y err [n] can be calculated as 139 err, , 1 err rs VCO 1 rs , ,1 err, , err, , Q[ ] Q[ ] [] ( ) 22 Q[ ] Q[ ] () 2 . 2 Δ Δ Δ Δ Δ nk nk k k k k nk k k nk nk k tt y n h nT K tt A h nT hh Φ Φ Φ Φ π Φ + + + + = − + = ⋅− + ≈ ∑ ∑ ∑ (4.10) An approximation is applied to reduce the memory cost with negligible performance degradation. In addition, ΔΦ err,n,k /ΔΦ is read from another LUT in real time by using Δt k calculated from the nonlinearity estimation. For this prototype, the reconstruction filter is designed with a corner frequency at 200 MHz, and the entire NU DSP operates at the resampling rate (F rs ∼ 580 MS/s), which is F clk /8, as shown previously in Figure 4.8. To ensure that the degradation of SNR and SNDR due to aliased out-of-band components remains less than 1 dB after decimation, t d is designed to be equal to T rs , and the average number of nonuniform samples at each resampling instant is approximately 14. The NU DSP, including the nonlinearity correction, has been synthesized using a 65-nm CMOS digital standard cell library, and the overall SNR/SNDR degradation is less than 1.5 dB considering the finite-word length effect. After place-and-route, the estimated cost is 25 mW and 0.104 mm 2 , where the computations of y[n] and y err [n] consume 11 mW and 0.036 mm 2 and 14 mW and 0.068 140 Figure 4.20: Chip micrograph in 65-nm CMOS. mm 2 , respectively. Thus, the complete signal processing operation consumes 30 mW and 0.114 mm 2 , including the on-chip nonuniform bit storage (5 mW and 0.01 mm 2 ). 4.5.6 Measurement results A photograph of the ADC chip fabricated using a standard 65-nm CMOS process is shown in Figure 4.20. The VCO and the time quantizer occupy an active area of 0.13 mm 2 , and the fully synthesized digital block contains the nonuniform bit storage, nonlinearity estimator, and SRAM of 53 KB. The SRAM is used to store the output of the nonuniform bit storage to avoid the need to drive a high-speed output data bus. During measurement, F FR and K VCO are first characterized by sweeping the dc input, and a VCO 390 um 333 um Time Quantizer Bit Storage (w/ SRAM) & Nonlinearity Estimation 141 Figure 4.21: Spectrum measured with sinusoidal input at 65 MHz. 1-MHz sinusoidal input is applied to characterize the nonlinearity and generate the LUT for the calibration. Then, the LUT is fixed, that is, it is not regenerated for different inputs. To evaluate ADC performance before filtering and decimation, V out (t) and V out,calib (t), shown in Figure 4.17(b), are plotted at an effective sampling rate of 1/T Q . The noise and distortions are calculated within the 200-MHz bandwidth, which cannot be filtered afterward. 524288-point FFT SNDR w/o calibration w/ calibration SNR THD 44.7 dB 59.6 dB -44.9 dBc -100 -80 -60 -40 -20 0 10 -1 10 0 10 1 10 2 10 3 10 4 -120 60.1 dB 58.5 dB -63.6 dBc w/ calibration w/o calibration 10 -2 dBFS Frequency (MHz) 10 5 142 Figure 4.22: Plots of measured SNR and SNDR versus input frequency. Figure 4.23: Plots of measured SNR and SNDR versus input amplitude (F in = 65 MHz). Figure 4.21 shows the measured spectrum of a sinusoidal input at 65 MHz with amplitude of −0.5 dBFS. After linearity calibration, we obtain an SNR of 60.1 dB and an SNDR of 58.5 dB, demonstrating an improvement of more than 18 dB in terms of the total harmonic distortion (THD). Plots of the measured SNR and SNDR versus different input frequencies are shown in Figure 4.22, where the worst-case SNDR is obtained with 5 10 100 50 55 70 SNDR SNR 60 65 50 Input Frequency (MHz) dB -70 -60 -50 -40 -30 -20 -80 -10 0 20 40 60 0 -20 Dynamic Range = 62 dB Input Amplitude (dBFS) dB SNDR SNR 143 Figure 4.24: Plot of measured THD versus chip temperature (F in = 5 MHz). a 65-MHz input when HD3 is within the 200-MHz bandwidth. Figure 4.23 shows plots of the measured SNR and SNDR versus the input amplitude with a 65-MHz input; a dynamic range (DR) of 62 dB is achieved, and this range is limited by the VCO phase noise, including the effects of the supply noise and circuit noise, quantization error, and circuit noise of the time quantizer. To validate the effectiveness of the linearity calibration at different temperatures, we initially calibrate the ADC at 45 °C and then vary the chip temperature. As shown in Figure 4.24, the in-band THD, referred to as the signal power, exhibits a degradation of less than 2 dB when the chip temperature is varied from 15 °C to 85 °C. In addition, the VCO supply voltage critically influences the ADC performance. To examine the voltage effects, the ADC is first characterized at a VCO supply voltage of 1 V, and the input common-mode voltage is set to have a free-running oscillation frequency of approximately 1 GHz. When the VCO supply voltage changes, 10 -68 -67 20 30 40 50 60 70 -69 dBc Chip Temperature (°C) 80 90 144 Figure 4.25: Plots of measured SDR and SNDR versus VCO supply voltage (F in = 5 MHz). Figure 4.26: Measured spectrum with inputs at 173.2 MHz and 184.9 MHz. 0.8 0.9 1.0 1.1 50 VCO Supply Voltage (V) 1.2 55 60 65 70 75 dB SDR SNDR -100 -80 -60 -40 -20 0 100 200 250 300 -120 70 dBFS Frequency (MHz) 350 150 400 w/ calibration w/o calibration 524288-point FFT IM3 @ 161.5 MHz w/o cal. w/ cal. -55.01 dBc -51.99 dBc < -85 dBc -61.75 dBc -62.76 dBc < -85 dBc IM3 @ 196.6 MHz IM2 @ 11.7 MHz 145 the input common-mode voltage is adjusted to have a similar free-running oscillation frequency. As expected, the best signal-to-distortion ratio (SDR) and SNDR are obtained under the initial calibrated condition, that is, supply voltage of 1 V, as shown in Figure 4.25. As the supply voltage decreases, the degradation becomes more prominent because the input signal amplitude decreases accordingly. Another reason is that the VCRO tuning curve deviates more from the initial calibrated condition. The measured IM2 and IM3 distortions are −85 dBc and −62 dBc, respectively, with two −8.5-dBFS tones at 173.2 and 184.9 MHz, as shown in Figure 4.26. Table 4.1 summarizes the performance of the proposed architecture and compares it with the performance of state-of-the-art NUS ADCs and uniform sampling first-order noise-shaped VCO-based ADCs (BW > 3 MHz). The proposed chip consumes a total of 19.7 mW, including VCO (5.4 mW at 1.05 V), reference time generator (RO: 5.3 mW at 1.05 V; others: 5 mW at 0.95 V), and the time-strobing circuits (4 mW at 0.95 V). Compared to the voltage-domain level-crossing NUS ADCs at the same technology node [18] [38], the architecture proposed herein improves the bandwidth and power efficiency. Because the frequencies, where the quantization errors are aliased and the oversampling rate on the input signal, are independent, the proposed architecture uses fewer quantization levels for the same signal bandwidth compared to the uniformly sampled 146 Architecture Ref. Quant. Levels Tech (nm) Area (mm 2 ) Power (mW) F s (MHz) F BW (MHz) SNDR (dB) SNR (dB) DR (dB) FoM1 (fJ/step) FoM2 (dB) Calib. Uniformly Sampled VCO-Based ADC (F BW > 3 MHz) [41] 64 130 0.078 12.6 500 10 57.7 63.1 - 101.0 >152.1 excl. [42] 30 65 0.075 17 1152 18 67 70 67 d 258.1 157.2 incl. 9 72 76 72 d 290.3 159.2 [43] 64 65 0.02 11.4 300 30 64 - - 146.7 >158.2 excl. 0.009 5.7 300 30 52 - - 292.1 >149.2 [44] 32 130 0.12 14.3 600 20 52.5 55.1 - 1037.6 >146.6 excl. [45] a 28 65 0.075 39 2400 37.5 70 71 73 e 201.2 162.8 incl. 26 1920 30 70 71 72 e 167.7 162.6 17.5 1600 25 70 71 72 e 135.4 163.5 11.5 1300 20.3 69 70 71 e 123 163.5 [46] 32 90 0.16 4.1 640 5 73 75.4 77 d 112.3 167.9 incl. [53] 31+14 180 0.4 5 35 3.5 70 - - 276.4 >158.5 excl. 4.1 8.4 1.1 75.7 77 - 374.1 >161.3 [49] 15 65 0.026 3.3 205 25.62 50.3 52.8 - 240.8 >151.7 excl. [51] 15+15 40 0.017 2.57 1600 40 59.5 60.7 - 41.6 >162.6 - [52] 4+33 65 0.62 8.2 1000 50 60.6 - - 93.7 >158.5 incl. 30 65 - - 94.0 >160.6 20 68 - - 99.9 >161.9 [70] 1 40 0.08 3.5 1000 20 53 - - 239.7 >150.5 - NUS ADC [18] 15 65 0.3 30 570 c 20 59.9 59.9 - 928.5 >148.1 excl. [38] 18 65 0.7 28 606 c 20 65.1 66.8 - 476.2 >155.3 excl. NS-NUS ADC This Work 4 65 0.13 19.7 4000 c 200 58.5 60.1 62 d 71.6 162.1 excl. This Work b 4 65 0.244 49.7 4000 c 200 57 58.7 60 d 214.8 156 incl. FoM1 = Power/(2*F BW *2 (SNDR-1.76)/6.02 ), FoM2 = DR + 10*log 10 (F BW /Power) a Decimation filter is included. b Including the estimated power and area of reconstruction filter, as well as the linearity calibration performed using the design example in Section 4.5.5. c Refers to F s,avg on the input signal, that is, the actual output data rate, instead of F s,eff on the quantization error. d Calculated from input amplitude of peak SNDR. e Calculated from input amplitude of peak SNR. Table 4.1: Summary and comparison of performance of the proposed architecture with prior implementations. 147 (a) (b) Figure 4.27: (a) Architecture of conventional high-dynamic-range continuous-time delta-sigma modulator ADC. (b) Architecture of proposed VCO-based noise-shaping NUS ADC architecture, including nonuniform sampling modulator and NU DSP. first-order noise-shaping VCO-based ADCs thanks to the nonuniform reconstruction filter. The performance and implementation cost after including the overhead in the DAC ê M s F ω FBW Quant. Noise DAC ∫ ∫ s 0.5F DAC ELD Analog Modulator 40-80dB/dec Continuous-Time Delta-Sigma Modulator Image @ Fs ω rs 0.5F = s rs F F M Digital Signal Processor Amplifier Multi-Bit DAC (Linearization, Higher VDD) FBW ω |H( ω)| s F Uniform Samples ω Q 0.5 T FBW s,avg 0.5F ∫ Vin(t) Phase-Domain Level Crossing d dt Φ ZOH VCO Time-to-Digital Converter (TQ) Q[ ] k t s,avg F Nonuniform DSP Nonuniform a Uniform VCO () Vt Shaped to >> Fs,avg 20dB/dec Nonuniform Sampling Modulator Image @ 1/TQ out () Vt Vin(t) Quant. Noise TDC Mostly Digital ê M ω rs 0.5F ω FBW |H(ω)| Q 0.5 T = s,avg rs F F M Nonuniform Samples Φ in () t Analog Modulator Digital Signal Processor 148 linearity calibration and the reconstruction filter are summarized in Table 4.1 for reference. Note that whenever the required signal bandwidth is narrower, the figure of merit (FoM) of the proposed architecture is expected to improve because of the extra degrees of design freedom among N, F s,avg , T Q , and the reconstruction filter. Because of the mostly digital architecture and time-based nature of the proposed NS-NUS ADC, we expect that its performance, for example, bandwidth, resolution, and FOM, can be improved by using more advanced technology nodes. 4.6 Comparison of VCO-based NUS ADC with uni- formly sampled continuous-time delta-sigma ADC A low-power, wide-bandwidth, and high-dynamic-range ADC is one of the critical building blocks in the design of a wireless receiver. For this reason, the continuous-time delta-sigma modulator (CT DSM) ADC has become a popular choice, and its conventional architecture is illustrated in Figure 4.27(a). The demand for a wider bandwidth increases the sampling rate F s , which requires the use of a high-speed loop filter, quantizer, feedback DAC, and excess loop delay compensation (ELDC) [62]. By reducing the oversampling ratio, one can relax these requirements, but doing so results in the formation of a greater number of amplitude quantization levels and high-order noise 149 shaping. The feedback DAC often becomes a design challenge because its distortions degrade ADC performance and can require linearization and higher supply voltage [82] [83] [84] [85]. By contrast, the proposed NS-NUS ADC architecture shown in Figure 4.27(b) avoids these issues by leveraging the unique property of nonuniform sampling, where spectral aliasing on the quantization noise is independent of the actual average sampling rate F s,avg . Thus, the quantization noise can be shaped to a frequency considerably higher than F s,avg and subsequently filtered by the NU DSP. To achieve a SNDR similar to that of CT DSM ADCs, the proposed architecture only requires first-order noise shaping, which facilitates the use of an open-loop architecture without stability and ELD issues. The NUS modulator has a mostly digital architecture without amplifiers, reference voltage generator, and DACs, and this architecture is suitable for technology scaling. 4.7 Prototype of VCO-based NUS ADC with 40-MHz bandwidth and 78-dB dynamic range 4.7.1 Architecture In the NUS modulator shown in Figure 4.27(b), sampling is performed using a phase-domain level-crossing quantizer [75], which first converts the input amplitude 150 from voltage to phase with inherent integration. The input signal is reconstructed by applying ZOH between nonuniform samples followed by differentiation to remove the integration effect. Thus, the quantization noise is alias-free and is first-order shaped. It conceptually generates a CT impulse train V out (t), in which the Dirac delta function appears at every level-crossing instant t k . The overall operation can be accomplished using a single VCO and monitoring its nonuniform transitions at the output, where F s,avg is approximately equal to the free-running oscillation frequency F VCO,FR . Instead of performing analog computation on the impulse train [73], a TDC is utilized to digitize t k with a resolution of T Q to yield Q[t k ] and V out,q (t). Although this process introduces aliasing on the quantization noise at the frequency of 1/T Q , this frequency can be considerably higher than F s,avg by benefitting from a fine T Q , which can be ascribed to technology scaling. In other words, different from the CT DSM, in the proposed architecture, quantization noise can be shaped to a considerably higher frequency without generating excessive samples. The NU DSP simultaneously performs several important functions, including a) anti-aliasing filtering, b) conversion of input nonuniform samples to output uniform samples, c) decimation to a uniform resampling rate F rs , and d) VCO linearity calibration through two-point phase error compensation. Note that the images of filter response are repeated at intervals of 1/T Q instead of F s,avg in the conventional digital decimation filter. 151 Figure 4.28: Implementation of the nonuniform sampling modulator, and the interface between the nonuniform and uniform clock domains. Figure 4.29: Phase-domain level crossing with single amplitude quantization level. 4.7.2 Implementation of NUS modulator Figure 4.28 shows a simplified block diagram of the NS-NUS ADC and the implementation of the NUS modulator. An analog input is first fed into the VCO Nonuniform DSP Data Rearrangement Event-Driven FIFO D Q 16 Encoder 9 D Q 4 Q[ ] k t MOD-12 Counter rs CLK = rs ref 12 FF 4 ref CLK 16 Coarse Pulse Generator NU CLK Metastability Detection TDC 9 9 NNUS 9 9 x 8 8 16 x 8 Vin s,avg VCO,FR FF ≈ Nonuniform Clock Domain Uniform Clock Domain PFD CP x8 DLL VCO Vin VVCO VVCO Fine tk t VVCO(t) 2π out () Vt Φ in () t 152 implemented using a pseudo-differential ring oscillator. As illustrated in Figure 4.29, the NUS modulator utilizes a single amplitude quantization level in the phase domain to generate nonuniform samples, while avoiding mismatches between levels, and simplifies TDC design. The TDC consists of a bank of registers that latch the output phases of a delay-locked loop (DLL) and a counter to perform fine and coarse time quantization, respectively. The DLL contains eight delay stages, which generate 16 phases and are further resistively interpolated by 2X. F rs is designed to be F ref /12 based on the desired anti-aliasing filter response. 4.7.3 Interface between NUS modulator and NU DSP As shown in Figure 4.28, an event-driven FIFO buffers the nonuniform samples with a depth of eight words to avoid overflow when the VCO oscillates at its maximum frequency. This provides a proper interface between nonuniform and uniform clock domains. N NUS denotes the actual number of nonuniform samples within each T rs . Similar to the metastability issue in conventional clock domain crossings, any potential metastability indicates that the value of the present nonuniform sample may require more time to resolve. Thus, it is processed and rearranged in the next resampling cycle to facilitate proper NU DSP operation. 153 Figure 4.30: Characterization of the voltage-to-frequency relationship of VCO, and the time-domain relationship between ∆t measured and ∆t ideal . 4.7.4 Two-point phase error compensation A two-point phase error compensation technique is proposed to mitigate the VCO nonlinearity. As shown in Figure 4.30, the first step is characterizing the voltage-to-frequency relationship of VCO, and this can be achieved by injecting DC voltages and measuring the VCO oscillation frequency by averaging the quantized time spacing between level-crossing events. In addition, a sinusoidal wave can be applied to characterize the VCO nonlinearity. Thereafter, by taking the inverse of the measured and ideal VCO frequencies, we can find the time-domain relationship between ∆t measured and ∆t ideal , which are the quantized time differences between adjacent level crossings with and without nonlinearity, respectively. As discussed in Section 4.5.4, the accumulated phase error, ∆Φ e , due to VCO nonlinearity can approximated between level crossings as ∆ measured,k t in V ∆ ideal t ∆ measured t ∆ ideal,k t incm V VCO F ideal measured VCO,measured F VCO,ideal F − ∆= 1 VCO tF 154 Figure 4.31: Proposed two-point phase error compensation for VCO linearity calibration. measured, ideal, e, ideal, Δ Δ Δ 2 Δ kk k k t t t Φπ − ≈ (4.11) where measured, 1 Q[ ] Q[ ] . kk k t tt + ∆ = − Different from the linearity calibration proposed in Section 4.5.4, which compensates for the phase error at the additional midpoint, this two-phase error compensation scheme splits ∆Φ e equally at two adjacent nonuniform FVCO t +1 Q[ ] k t −1 Q[ ] k t Q[ ] k t π 2 t −1 Q[ ] k t +1 Q[ ] k t Q[ ] k t out,q,calib V 2 π Φ − e, 1 Δ k 2 π Φ e, Δ k t −1 Q[ ] k t +1 Q[ ] k t Q[ ] k t out,q V t −1 Q[ ] k t Q[ ] k t Φ − e, 1 0.5 Δ k Φ − e, 1 0.5 Δ k t Q[ ] k t Φ e, 0.5 Δ k +1 Q[ ] k t Φ e, 0.5 Δ k FVCO,ideal FVCO,measured out,q,calib,k V π 2 π 2 Uncalibrated Signal (@ NU DSP Input) Φ − e, 1 Split Δ k Φ e, Split Δ k Calibrated Signal 155 Figure 4.32: Implementation of the proposed two-point phase error compensation scheme. Figure 4.33: Behavioral simulation of the proposed two-point phase error compensation scheme. sample points and sums it with the uncalibrated signal, V out,q (t), at the NUS DSP input (Figure 4.31). Because ∆Φ e is treated as a part of the existing nonuniform samples, it reduces the computational cost by nearly 2X. In the implementation illustrated in Figure 4.32, the sum of π and split ∆Φ e are stored in LUTs with the readout value based on ∆t measured . To validate the proposed calibration, a behavioral simulation is performed, as shown in Figure 4.33. The simulation results indicate that when F s,avg /F in decreases, the distortion is suppressed to a lesser extent. This is because the variation of VCO πΦ += e, measured, 0.5 Δ LUT( Δ ) kk t 1 Q[ ] k t + Q[ ] k t LUT LUT πΦ − + e, 1 0.5 Δ k 1 Q[ ] k t − πΦ + e, 0.5 Δ k out,q,calib,k V measured, Δ k t − measured, 1 Δ k t Fs,avg/Fin 0 HD3 (dBc) -110 -90 -70 -50 -30 500 400 300 200 100 After Calibration Before Calibration 600 156 Figure 4.34: Time-domain waveform of the calibrated signal (V out,q,calib ) at the NU DSP input. oscillation frequency between adjacent nonuniform samples increases. Thus, the error originating from the approximation in (4.11) increases and degrades the calibration effectiveness. 4.7.5 Implementation of NU DSP After the amplitude of the CT impulse train (V out,q ) is calibrated (V out,q,calib ), it is sent to the NU DSP, in which the quantized time Q[t k ] of level crossing and calibrated amplitude V out,q,calib,k are utilized to perform digital AA filtering. To compute the filtered and decimated output out[n], we first calculate the time difference between the k th nonuniform sample and the n th resampling point, which is denoted ∆t k,n in Figure 4.34. rs nT rs CLK rs ( +1) nT t ∆ , kn t td +1 Q[ ] k t td −1 Q[ ] k t − ∆ 1, kn t rs ( -1) n T Q[ ] k t −2 Q[ ] k t out,q,calib V out,q,calib,k V 157 Figure 4.35: The implementation of a digital AA filter in the NU DSP, including decimation and two-point phase error compensation. By modifying (4.3) with the calibrated amplitude, the algorithm of NUS DSP can be written as out,q,calib, , , out[ ] , : ) ( k k n k n d k n V ht k t t = ⋅∆ ∀≤ ∆ ∑ . (4.12) The algorithm computes the convolution between the calibrated NUS modulator output V out,q,calib (t) and the desired AA filter response h(t) at a uniform resampling clock rate NNUS Clock Gating rs CLK ,1 () kn ht + ∆ z 0 z -1 z -2 z -3 ,2 () kn ht − ∆ ,1 () kn ht − ∆ , () kn ht ∆ + out[ ] n Two-Point Phase Error Compensation + … 1 Q[ ], Q[ ], kk tt 12 12 12 12 12 15 out,q,calib,k V LUT x8 x8 x8 x8 x8 NNUS = 1 ~ 8 8 158 Figure 4.36: Chip micrograph. 1/T rs . Because of the pseudo-differential architecture, the two NUS modulators have individual NU DSPs, and their outputs are subtracted to generate the final output. The implementation of a single NU DSP is shown in Figure 4.35, including the two-point phase error compensation scheme. To compute the n th output sample, the algorithm requires sums up and multiplies the corresponding filter response h( ∆t k,n ) with all the nonuniform samples within the filter duration, which is set to 4T rs in this prototype. Distributed memory-based computing is used in this work, where h(t) is first divided into four equal sections, that is, partial filter responses, and stored in four SRAM banks. Each SRAM bank consists of eight identical units to accommodate the maximal number of nonuniform samples within one T rs . The clocks driving the SRAM units can be gated VCO TDC 100um 230um Nonuniform DSP & Output Data Storage Nonuniform DSP & Output Data Storage 159 Figure 4.37: Measurement setup. based on N NUS for reducing power consumption. In addition, the address encoder of the SRAM and the TDC coding scheme are judiciously designed to further reduce the cost of computing ∆t k,n . Finally, the outputs of each of the SRAM banks are delayed by different cycles for proper code alignment. Linear Regulator Signal Source Agilent 8644B Bandpass Filter PCB Linear Regulator Balun Vinp Vinn CLKref Clock Source Agilent 8665B 5 Logic Analyzer Agilent 16962A Vin Buffer DUT NUS Modulator NU DSP Q[tk] CLKrs Data Storage Balun Bandpass Filter Voltage Translator 0.9V Pattern Generator Agilent 16720A to LUTs & SPI (Chip on Board) CLKref Pattern Generator Logic Analyzer Pattern Generator Logic Analyzer KEITHLEY 2604B SourceMeter Vin Signal Generator (Agilent 8644B) Power Supply Signal Generator (Agilent 8665B) Pattern Generator & Logic Analyzer 160 Figure 4.38: Measured spectra at NU DSP output for F in of 2.64 MHz and 12.41 MHz. Figure 4.39: Measured SNDR versus input amplitude for F in of 2.64 MHz with 40-MHz BW. 4.7.6 Measurement Results The chip micrograph is shown in Figure 4.36. The NUS modulators occupy 0.023 mm 2 , and the measurement setup is demonstrated in Figure 4.37. For a signal bandwidth 0.1 1 -120 Frequency (MHz) Magnitude (dBFS) -100 -80 -60 -40 -20 0 10 100 Frs = 416.67 MHz, 2048-point FFT 57.6dB 0.1 1 -120 Frequency (MHz) Magnitude (dBFS) -100 -80 -60 -40 -20 0 10 100 Frs = 416.67 MHz, 2048-point FFT 42.5dB SNDR OFF HD3 38.3dB -38.3dBc ON 76.2dB -95.9dBc φ ∆ e Two-point compensation SNDR OFF HD3 38.7dB -38.7dBc ON 75.2dB -81.2dBc φ ∆ e Two-point compensation -90 -10 0 10 20 30 40 50 60 70 80 -80 -70 -60 -50 -40 -30 -20 -10 0 Dynamic Range = 78.0 dB SNDR Input Amplitude (dBFS) (dB) 0 -1 -2 -3 -6 -5 -4 80 70 75 161 Figure 4.40: Measured output spectrum in two-tone test. Figure 4.41: Plots of measured SNDR and DR versus different input frequencies at NU DSP output. Figure 4.42: Plot of measured SNDR versus different chip temperatures at NU DSP output (F in = 2.64 MHz), where the ADC is characterized at 45°C. 0 30 -120 Frequency (MHz) Magnitude (dBFS) -100 -80 -60 -40 -20 0 Frs = 416.67 MHz, 2048-point FFT F1 = -6.5 dBFS @ 34.0 MHz F2 = -6.5 dBFS @ 36.8 MHz 50 70 80 IM3 < -81.2 dBc 60 40 20 10 Φ e Two-point Δ compensation: OFF Φ e Two-point Δ compensation: ON 0 5 15 74 Input Frequency (MHz) (dB) 76 80 25 35 40 SNDR DR 78 30 20 10 BW = 40 MHz 15 30 70 Chip Temperature (°C) (dB) 74 80 60 75 SNDR 45 BW = 40 MHz 72 76 78 162 of 40 MHz, F s,avg , T Q , and the cutoff frequency of the digital AA filter are set to 2.0 GHz, 6.25 ps, and F rs /4, respectively. Figure 4.38 shows the measured spectra at the NU DSP output with for input frequencies of 2.64 MHz and 12.41 MHz; the peak SNDR after calibration is 76.2 dB. A plot of the measured SNDR versus input amplitude is shown in Figure 4.39, and it indicates that the dynamic range is 78 dB. The two-tone test is performed with input frequencies of 34 MHz and 36.8 MHz, and the resulting output spectrum is shown in Figure 4.40. After calibration, the third-order intermodulation (IM3) distortions are at least lower than -81.2 dBc, which are overwhelmed by the noise floor due to the limited number of data points stored in the on-chip memory for plotting the spectrum. Figure 4.41 shows plots of the DR and SNDR over different input frequencies. The worst DR and SNDR occur when the input frequency is around one-third of the signal bandwidth, where the performance is limited by the in-band HD3. The performance over different chip temperatures are measured and shown in Figure 4.42. VCO nonlinearity is initially characterized at 45°C without recharacterization as the temperature varies. However, the input common voltage of the VCOs is adjusted to maintain the free-running oscillation frequency, that is, F s,avg , at approximately 2 GHz to maintain the SQNR and minimize deviation of the VCO characteristics between the initially characterized condition and the ones after temperature variation. When the chip temperature varies from 15°C to 75°C, the maximum degradation in SNDR is 163 Figure 4.43: Simulated and measured frequency responses of the digital AA filter in the NU DSP. Figure 4.44: Measured spectra at the input and output of the NU DSP. approximately 4 dB, which can be ascribed to the higher noise level at higher temperatures and deterioration in HD3 owing to inaccurate VCO characteristics in the linearity calibration. Measured Frequency Response Simulated Frequency Response 10 0 10 1 10 2 -120 -100 -80 -60 -40 -20 0 10 3 10 4 Magnitude (dB) 10 0 10 1 10 2 -120 -100 -80 -60 -40 -20 0 10 3 10 4 Magnitude (dBFS) Frequency (MHz) Measured NU DSP Input (Vout,q(t) in Fig. 5.31) Measured NU DSP Output ( out[n] in Fig. 5.35) 164 This Work [86] [85] [67] [84] [62] [83] [82] Arch. NS-NUS ADC CT DSM ADC Process (nm) 28 28 28 65 28 16 65 28 Area † (mm 2 ) 0.023 0.085 0.019 0.35 0.25 0.217 0.16 0.34 NTF Order 1 st 4 th 4 th 4 th 4 th 4 th 4 th 4 th Need OTA NO YES YES YES YES YES YES YES Supply (V) 1.1 0.9 1.2 0.95 1.5 1.2 1.5 1.1 - 1.5 1.16 1.5 1.35 1.0 1.8 1.2 1.5 1.3 1.2 F S (MHz) 1500^ 2000^ 1200 2000 1500 2000 2150 900 1800 F BW (MHz) 25 40 50 100 50 50 125 45 50 DR * (dB) 79.5 78.0 78.4 76.3 73.1 82.2 74.8 79 82 SNDR (dB) 77.8 76.2 76.6 72.6 73.5 79.8 71.9 75.3 74.6 Power † (mW) 10.9 17.5 29.2 16.3 51.8 64.3 54 24.7 78 FoM W (fJ/step) 34.4 41.5 52.8 23.4 134.0 80.5 67.2 57.7 177.7 FoM S,SNDR (dB) 171.4 169.8 168.9 170.5 163.3 168.7 165.5 167.9 162.7 FoM S,DR (dB) 173.1 171.6 170.7 174.2 162.9 171.1 168.4 171.6 170.1 FoM W = P/(2*F BW *2 (SNDR-1.76)/6.02 ); FoM S,SNDR = SNDR + 10*log 10 (F BW /P); FoM S,DR = DR + 10*log 10 (F BW /P) † Analog modulator without digital signal processor ^ Average sampling rate * Calculated from the input amplitude of peak SNDR Table 4.2: Performance summary and comparison of the proposed architecture with state-of-the-art CT DSM ADCs. 165 For the measurements, the implemented AA filter is programmed to have a filter response equivalent to that of a 1536 th -order Hann window FIR filter clocked at 1/T Q = 160 GHz. To validate the filter response, a single sinusoidal wave of different frequencies is applied, and the amplitude of the fundamental tone is measured at the NU DSP output. The input frequency is swept up to approximately 500 MHz because of the limited bandwidth of the input balun. The measured and simulated filter responses are plotted in Figure 4.43, and the difference between them is less than 0.5 dB. To verify the NU DSP, Figure 4.44 demonstrates the measured spectra at the input and output of the NU DSP, which confirm the functions of anti-aliasing filtering, decimation, and phase error compensation. The NUS modulators consume 17.5 mW, where VCO and TDC operate at 1.2 V and 0.95 V, respectively. The NU DSP consumes 38 mW at 0.85 V with a core area of 0.3 mm 2 , including the interface and the two-point phase error compensation. The signal bandwidth of the proposed architecture can be reconfigured by adjusting F s,avg and T Q . As an example, a signal bandwidth of 25 MHz is measured at F s,avg = 1.5 GHz, T Q = 7.8 ps, and F in = 3.1 MHz. Table 4.2 summarizes the performance of the proposed architecture and compares it with the performance of state-of-the-art CT DSM ADCs. The comparison results indicate that the proposed architecture has a comparable FoM with a lower supply voltage. 166 Chapter 5 Conclusions and Suggestions for Future Work 5.1 Conclusions An NUS ADC architecture with an embedded nonuniform DSP has been proposed to utilize both amplitude and time quantization; this architecture seamlessly interfaces with existing synchronous DSPs. In applications in which the signal frequency, bandwidth, or activity may vary over time or with operating conditions, the proposed flash-based and subranging-based NUS ADCs can provide high levels of agility in terms of an adaptable sampling rate based on the incoming signal and a reconfigurable digital AA filter response. This relaxes the analog AA filter because of the nearly analog-equivalent frequency response. Compared with the uniformly sampled ADC, where both the input signal and quantization noise are aliased at a uniform sampling rate, the amplitude quantization noise in the proposed architecture is aliased at the frequency of the inverse 167 of the time quantization resolution instead of the input sampling rate. The quantization noise can be pushed to a higher frequency and removed by using the proposed nonuniform DSP. A noise-shaping NUS ADC architecture that utilizes a VCO as an integrator, followed by phase-domain level crossing, has been proposed. The absence of continuous-time voltage comparators and a reference voltage generator widens the bandwidth and increases the power and area efficiencies of the proposed NUS ADC compared to those of existing NUS ADCs. Because of the mostly digital architecture, the proposed VCO-based NUS ADC is suited for technology scaling. Essentially, the proposed NUS ADC architecture provides a flexible route for performing analog-to-digital conversion and filtering, in addition to providing different approaches for designing ADCs. 5.2 Suggestions for future work 5.2.1 VCO-based multi-stage noise-shaping NUS ADC As mentioned in Section 2.1.4, the time quantization can alias the amplitude quantization errors and degrade the in-band SNDR. Therefore, to mitigate the performance degradation caused by the increase in signal bandwidth, a finer time 168 resolution should be utilized. An alternative approach without increasing the time resolution involves employing a higher-order noise-transfer function, which demands that the VCO-based NUS ADC be placed in a higher-order DSM. However, such an implementation can lead to stability problems and complicate the design, as mentioned in Section 4.6. Therefore, to maintain the open-loop architecture while increasing the order of noise shaping, a multi-stage noise-shaping (MASH) architecture is proposed for the VCO-based NUS ADC. To realize this architecture, the extra phase errors attributable to time quantization in the first stage of the proposed VCO-based NUS ADC are extracted as pulses. Then, this pulsed signal is used to modulate the second stage, which is implemented using a VCO-based NUS ADC as well. As a consequence, this VCO-based MASH NUS ADC can potentially achieve a wider signal bandwidth by means of high-order noise shaping without sacrificing the stability and the mostly digital nature of the implementation. In addition, because the amplitude of a pulse has only two levels, it can desensitize the nonlinearity of the VCO in the second stage. 5.2.2 Nonuniform sampling for RF-to-digital direct conversion As is known, uniform sampling leads to frequency aliasing at integer multiples of the sampling frequency, denoted as N∙F s , where N is the subsampling ratio, and F s is the uniform sampling rate. Therefore, if the desired input signal is present at any of those 169 frequencies, for example, k∙F s , where k is an integer, we can apply a band-pass filter to the desired signal to perform AA filtering and simply sample the signal at F s without the need for a mixer. However, the requirement for an analog band-pass AA filter becomes more stringent at larger subsampling ratios. Therefore, a nonuniform subsampling scheme is introduced to relax the AA filtering requirement. The idea is to perturb the original uniform sampling instants by using a periodically random sequence, that is, dithering. The theory behind this is that the dithering essentially performs phase modulation on the uniform sampling delta function. When the dithering period is an integer multiple of 1/(k∙F s ), the frequency contents at DC and the integer multiples of k∙F s are summed constructively; for other frequencies, they are summed destructively. Thus, only the signal components at integer multiplies of k∙F s will be aliased to DC, and the other frequency aliases will transform into the form of the noise. Because the spacing between the frequencies aliased back to DC is k∙F s , which is k times larger than that in the case in which a uniform clock rate of F s is used, the requirements of the band-pass AA filter can be relaxed to a greater extent. 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Abstract (if available)
Abstract
A low-power, wide-bandwidth, and high-resolution analog-to-digital converter (ADC) is one of the critical building blocks in the design of a wireless receiver. However, quantization noise fundamentally limits the performance of ADCs. For this reason, continuous-time delta-sigma modulators (CT DSM) with high-order noise shaping have become a popular choice. However, the demand for a wider bandwidth increases the sampling rate, which requires high-speed and highly linear analog building blocks. Therefore, in this work, we investigate a new ADC architecture that uses nonuniform sampling (NUS) and digital signal processing (DSP) to avoid the aforementioned problems. ❧ The main challenge associated with quantization noise is that it is aliased by a fixed sampling rate. To overcome this limitation, this work proposes the application of nonuniform sampling to the input signal with inherent amplitude quantization, followed by another time quantization at the sampling instant. The key aspect is that the quantization noise is aliased at the frequency of the inverse of the time quantization resolution instead of the sampling rate. The quantization noise can be pushed to a higher frequency and removed by using the proposed nonuniform DSP. Moreover, the nonuniform DSP converts the nonuniform samples to a uniform output data stream, which can seamlessly interact with the existing synchronous DSP. ❧ The proposed NUS ADC architecture is implemented in four different prototypes. To prove the concept, nonuniform sampling is first implemented by using a voltage-domain level-crossing quantizer in a flash architecture, in which a dedicated comparator is connected to each reference quantization level. To reduce the number of comparators and the nonuniform sampling rate, a two-stage subranging-based NUS ADC is implemented in the second prototype with a timeout mechanism to adjust the sampling rate by filtering sampling events. To further improve the dynamic range and reduce the implementation cost, a first-order noise-shaping NUS ADC is implemented in the third prototype, which utilizes a voltage-controlled oscillator (VCO) as an integrator and a phase-domain level-crossing quantizer. The phase-domain comparison naturally eliminates the need for any voltage-domain comparator or reference voltage generation, resulting in a mostly digital implementation. A VCO-based NUS ADC that integrates both an NUS modulator and an on-chip nonuniform DSP, including calibration of the VCO linearity, is demonstrated in the fourth prototype. This implementation achieves a competitive dynamic range and power/area efficiency compared to state-of-the-art high-order CT DSM ADCs, in addition to offering the advantages of an open-loop architecture, a mostly digital design, and lower supply voltage.
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Asset Metadata
Creator
Wu, Tzu-Fan
(author)
Core Title
Nonuniform sampling and digital signal processing for analog-to-digital conversion
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
12/05/2019
Defense Date
10/24/2019
Publisher
University of Southern California
(original),
University of Southern California. Libraries
(digital)
Tag
ADC,analog-to-digital converter,calibration,delta-sigma modulator,digital signal processing,event-driven,level-crossing,noise-shaping,nonuniform sampling,OAI-PMH Harvest,voltage-controlled oscillator
Language
English
Contributor
Electronically uploaded by the author
(provenance)
Advisor
Chen, Shuo-Wei (
committee chair
), Graham, Nick (
committee member
), Hashemi, Hossein (
committee member
)
Creator Email
tfwu0103@gmail.com,tzufanwu@usc.edu
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-c89-244217
Unique identifier
UC11673467
Identifier
etd-WuTzuFan-8006.pdf (filename),usctheses-c89-244217 (legacy record id)
Legacy Identifier
etd-WuTzuFan-8006.pdf
Dmrecord
244217
Document Type
Dissertation
Rights
Wu, Tzu-Fan
Type
texts
Source
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Access Conditions
The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...
Repository Name
University of Southern California Digital Library
Repository Location
USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA
Tags
ADC
analog-to-digital converter
calibration
delta-sigma modulator
digital signal processing
event-driven
level-crossing
noise-shaping
nonuniform sampling
voltage-controlled oscillator