University of Southern California Dissertations and Theses

Building blocks for 3D integrated circuits: single crystal compound semiconductor growth and device fabrication on amorphous substrates

(USC Thesis Other)

Building blocks for 3D integrated circuits: single crystal compound semiconductor growth and device fabrication on amorphous substrates

PDF

Download a page range

Download transcript

Copy asset link

Request this asset

Transcript (if available)

Content

Building Blocks for 3D Integrated Circuits:
Single Crystal Compound Semiconductor Growth
and Device Fabrication on Amorphous Substrates

by

Debarghya Sarkar

A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(Electrical Engineering)

May 2020

Copyright 2020 Debarghya Sarkar

To all of material and abstract consciousness
that have shaped me until today
iii

Acknowledgments
It was late August in 2014, when I started my Ph.D. program at USC. Five and half years
since then (at the time of writing this dissertation), with over 2500 emails and numerous Slack
messages, and uncounted hours of working together in the lab ranging from building custom pieces
of equipment to performing experiments or brainstorming ideas, I have been extremely privileged
to have shared a very close and unique relationship with Professor Rehan Kapadia. Being a first
generation Ph.D. student (I was a week late to claim myself to be the first student!), I have seen
first-hand, the extreme hard work of my advisor in his initial years as a faculty member, and have
directly and indirectly been inspired by that. I would forever cherish those days when he has played
the role of a senior grad student, post-doc and professor – all together – when he literally held our
hands and taught us the fine details of every aspect of research while inspiring us of being able to
visualize the bigger picture and gradually pushing us towards being independent researchers.
Dotted with multitude of embarrassingly stupid mistakes all throughout the years including some
that resulted in very trying situations, I’ve amazingly found a very gentle supportive person in him
during these times. My biggest critic during these years, one who knows my biggest weaknesses
inside-out and have helped me identify and address them, I’ll be forever grateful to Professor
Kapadia for what I’ve received from him. In many ways, he has gone much beyond what I would
expect from a research advisor, and has helped me progress. Not just conducting research, but the
art of communicating the results well – through writing and through oral presentations – I would
always appreciate his efforts to try to make me a holistic research personality. Ranging from
collaborating with several groups, to encouraging me to attend multiple conferences for presenting
my research and building my professional network, my advisor has taken utmost care to help me
gain visibility in the research community. And I can go on and on, but it would possibly still not
be sufficient to describe his contributions to turn me from an ugly duckling to a swan. I don’t think
I have given enough justice to his efforts in making me a beautiful one, but I’ll continue to strive
to be one, some day. Thank you very much, Professor.
In addition to Professor Kapadia, there were several other professors who also played different
significant roles in my Ph.D. career, and I would like to acknowledge them next.
I’ll be forever indebted to Professor Michelle Povinelli, for her instrumental role in having me
selected as a Ph.D. student with incoming fellowship at USC. I literally owe my very Ph.D.
opportunity at USC, to her. Professor Jayakanth Ravichandran is someone whom I shared a very
cordial relationship with. After my direct advisor, he was the one who seemed to always
understand me very well, and I am fortunate to having been able to discuss many of my
professional (and personal) issues with him on multiple occasions. A stalwart for his research
contributions for over five decades, and yet a very nice and caring personality, and still so eager
to learn new things and simultaneously share his immense knowledge to mentor our collaboration
iv

– is how I would remember Professor Paul Daniel Dapkus. A big thanks to Professor Steve Cronin
for allowing us to use his photoluminescence setup throughout my Ph.D. That tool definitely had
a huge impact on my Ph.D. progress.
Special thanks to Professor Arka Majumdar (at University of Washington) and Professor Megan
McCain (from USC Biomedical Engineering) for the collaborations I was a part of, and for the
mentorship I’ve received from them at different stages.
Professor Wei Wu, whose always-cheerful greeting would necessarily make me smile even on the
most troubled days; Professor Han Wang, whose lab equipment I’ve also used at times; Professor
Willie Ng and Dr. William Schroeder, whom I learnt quite a bit of optical components handling
from, in my initial days; Professor Anupam Madhukar, who with his scrutinous queries would
encourage me to think more deeply about my research and will always serve an inspiration for me
in the way I may teach in future; Professor Anthony Levi, Professor Aluizio Prata, Professor
Armand Tanguay, whose courses have helped me create a strong foundation to build my scientific
understanding and critical analysis; and many others whom I’ve received mentorship on multiple
occasions – Professor Andrea Armani, Professor Constantine Sideris, Professor Hossein Hashemi,
Professor Bhaskar Krishnamachari – and the list goes on.
A good majority of my time was spent in the USC cleanroom: thanks to Dr. Donghai Zhu and
Alfonso Jimenez for their efforts in keeping everything running. Special thanks to Megan Utley.
The ability to use the JPL MDL cleanroom was an absolute boon. I would appreciate Dr. Frank
Greer’s efforts for having me get access to a whole spectrum of tools there, and also introducing
me to a number of brilliant scientists who work there from whom I’ve also learnt a lot.
Next, I would like to acknowledge the incredible peers I had in our research group and those I had
collaborated with, at USC and beyond. When I compile a research presentation or a paper, or this
dissertation for that matter, I’m constantly reminded of their immense contribution in what I would
present as my research results. And it’s completely out of my imagination how things might have
been, if any of them weren’t there. Their collective contribution towards this dissertation is
possibly way more than my own.
My earliest co-worker and partner in crime, Jubin Hazra, who introduced me to Professor Kapadia.
It was from him that I learnt photolithography and metal evaporation, and general cleanroom use,
as well as electronic device simulations. One of my earliest collaborators (from Professor
Ravichandran’s lab) and a very dear friend and someone I learnt a lot of theoretical and
experimental aspects of materials science from – Dr. Shanyuan Niu – he’s the one who helped me
perfect my SEM skills, helped me understand the functioning and analysis of an XRD, and
indirectly helped me mold my ways to be a better researcher. I had one of the most productive
research comradeship with Wei Wang – the three papers I could write with her close contribution
essentially created the basis of my Ph.D. work. I have always been inspired to make myself more
organized and focused on work at hand, from Dr. Fatemeh Rezaeifar; and to be more professional,
v

from Dr. Qingfeng Lin. Jun Tao and Hyun Uk Chae are two of my close junior colleagues who
have been very instrumental in the latter part of my Ph.D., and with whom I hope to publish a few
more papers in the very near future. Several of my other junior colleagues have been very helpful
in contributing to much of the heavy-lifting in different aspects of the workflow, and thereby
allowing us to make progress as a team. Of them, Sizhe Weng, Yunpeng Xu, Dingzhu Yang,
Chenhao Ren, Shreyas Naik, and Bamdad Mesri deserve special mention. Another person whom
I’ve worked less on research but have talked the most on non-research stuff with (particularly on
sociopolitical matters) is Ragib Ahsan. I continue to be inspired by his scientific mind during
research group meetings, and our few scientific discussions in the office. A big thanks to Dr.
Mitchell Dreiske for being a very helpful peer in several of the academic courses we took together,
as well as for teaching me the details of the MOCVD reactor. Matthew Yeung and Louis
Blankemeier are two of the most amazing undergrads I’ve had the opportunity to work with, during
their times at USC and beyond.
I also owe my appreciation to Dr. Matthew Mecklenburg and Arashdeep Singh Thind (from Prof.
Rohan Mishra’s group at WUSTL) for their excellent STEM characterization of my samples, and
to Dr. Andrew Clough for his thorough XPS analysis of my samples.
And of course, there are many more whom I may regard as my cleanroom buddies – Dr. Dongseok
Kang (who taught me many useful cleanroom tricks), Huandong Chen, Yongkui Tang, Lurui Zhao;
peers from Professor Cronin’s lab which used to be my second most visited places after our own
– Dr. Rohan Dhall, Dr. Haotian Shi, Dr. Bingya Hou, Dr. Nirakar Poudel, and so on; peers from
Professor Ravichandran’s lab – Mythili Surendran, Yang Liu, Thomas Orvis, Boyang Zhao; peers
from Professor Madhukar’s lab – Swarnabha Chattaraj and Lucas Jordao; peers from Professor
Wang’s lab – Huan Zhao and Xiaodong Yan; all of whom I have a very cordial relationship with.
I would also like to appreciate the help from our department’s research administrators who play
an immensely important role in keeping our research run smoothly – Kim Reid, Susan Zarate,
Esrath Rumki, Diana Vuong, Jennifer Ramos, Sunny Bhalla, Kalief Washington, and Birgitte Hunt
– I’ve worked with all of them at different times. Also thanks to Diane Demetras, Tracy Charles,
Jennifer Gerson, and Kate Tegmeyer: all of whom have helped me through my Ph.D. as they help
many others. Special shout-out to Cathy Huang and Ben Paul.
A very brief but vivid thanks to all my high school and undergraduate teachers and friends (many
of whom are also currently pursuing or already finished their Ph.D.) – I’m blessed to have you in
my network, and am constantly inspired by your achievements.
Finally, I would like to express my heartiest gratitude to my roots in India – my parents Debjani
Sarkar and Basudeb Sarkar, my brother Deep Sarkar, my grandparents, my aunts, uncles and
cousins, and everyone else who had helped me in reaching here, and who were constantly with me
in their mind, spirit and prayers throughout my Ph.D. journey.
vi

Abstract
Building Blocks for 3D Integrated Circuits: Single Crystal Compound Semiconductor Growth
and Device Fabrication on Amorphous Substrates
by
Debarghya Sarkar
Committee: Prof. Rehan Kapadia (Chair), Prof. Michelle Povinelli,
Prof. Jayakanth Ravichandran, Prof. Han Wang

Over the past five decades, the world has made rapid technological progress supported by
the advancement in solid-state electronics and photonics. Referred to as the Moore’s Law, the
fundamental mechanism for making a better microprocessor chip has been the reduction of
footprint of individual operational units (field effect transistors), thus increasing the chip
functionality and performance by increasing planar density. However, there is an impending
problem. Improving integrated circuits by device miniaturization is coming to an end, since device
miniaturization is reaching its fundamental physical limit. A potential novel approach for
continued improvement is a three dimensional (3D) multifunctional integrated circuit. However,
there are several challenges associated with fabricating a 3D IC, and this dissertation is aimed at
experimentally establishing the viability of potential solutions to some of the fundamental
problems. Those are: (i) the ability to integrate single crystal semiconductors on an amorphous
buffer, (ii) at a temperature below 400
0
C so that underlying active layers are not affected, and (iii)
to be able to fabricate high-performance devices out of them.
A recently introduced non-epitaxial growth technique called thin film – vapor liquid solid growth
that showed the ability to grow large area grain size (10-100 m) polycrystalline film on metal
foils, has been adopted as the primary material growth method. It has been first generalized to be
integrable on any substrate including amorphous and crystalline dielectrics (i.e. not just limited to
metals), and its geometrical constraints from a thermodynamic perspective are established. This
has allowed for a wide variety of compound semiconductor materials (III-Vs and IV-Vs) to be able
to be grown as templates upto tens of micron in lateral dimension on a wide variety of
technologically relevant substrates. Extensive photoluminescence measurements and analyses
have been performed, which indicate excellent optoelectronic performance comparable to that of
commercial single crystal InP wafer. Temperature dependent photoluminescence, Hall mobility,
and electron back-scatter diffraction studies demonstrate the ability to grow high quality single
crystal III-Vs below 400
0
C on amorphous substrates including on flexible substrates such as
polyimide. Room temperature Hall mobility reaching 6000 cm
2
/V-s for InAs grown at 300
0
C on
HfO2, and contact-resistance limited FET mobility of 500 cm
2
/V-s for InP grown on SiO2, have
been shown: one of the highest values so far for any material family directly grown on an
amorphous dielectric. A scalable platform for obtaining artificial synapses has been demonstrated
by modulation of oxide-semiconductor interface trap occupancy in InP nanowire FETs. Finally,
selective growth of MOCVD epitaxial layers on these single crystal templates have been briefly
studied as precedents to obtain ultra-high performance devices on the back-end of CMOS chips.
vii

Table of Contents
Acknowledgments……………………………………………………………….. iii
Abstract…………………………………………………………………………... vi
1. A Brief Summary of my Research…………………………………………….1
1.1. 3D Integrated Circuits: Why? What? How?.........................................................................1
1.2. Epitaxial lift-off and transfer………………………………………………………………3
1.3. Direct non-epitaxial growth?................................................................................................4
1.4. Thin Film – Vapor Liquid Solid Growth…………………………………………………..4
1.5. Templated Liquid Phase (TLP) growth…………………………………………………….5
1.6. InP Channel MOSFET Characteristics…………………………………………………...12
1.7. Artificial Synaptic Device………………………………………………………………..13
1.8. Novelty in Device Fabrication……………………………………………………………15
1.9. InP-Si3N4 Hybrid Ring Resonator………………………………………………………..16
1.10. Optoelectronic Characteristics…………………………………………………………...16
1.11. Low Temperature Templated Liquid Phase (LT-TLP) InP Growth……………………..18
1.12. LT-TLP InAs Hall Mobility……………………………………………………………...21
1.13. Comparison of Electron Mobility………………………………………………………...22
1.14. Epitaxial Growth Process Integration on Non-epitaxial Substrates……………………...22
1.15. Conclusion………………………………………………………………………………. 23

2. Confined Liquid Phase Growth of Crystalline Compound Semiconductors
on Any Substrate…………………………………………………………….24
2.1. Template aspect ratio dependent wetting propensity…………………………………….24
2.2. Thermodynamics of confined liquid templates…………………………………………..26
2.3. Templated liquid phase growth…………………………………………………………..29
2.4. Far from equilibrium ternary material growth……………………………………………32
2.5. Growth of single-crystalline materials without an established single crystal substrate….33
2.6. Lateral heterojunction of distinct crystal structures………………………………………37

3. Optoelectronic Properties of Templated Liquid Phase Grown Indium
Phosphide……………………………………………………………………41
3.1. Steady State Photoluminescence Characteristics………………………………………..41
3.2. Urbach Parameter………………………………………………………………………..43
3.3. Photoluminescence Efficiency and quasi-Fermi Level Splitting………………………..44
3.4. Temperature Dependent Growth Quality Optimization…………………………………46
3.5. Buffer Insensitive Optoelectronic Quality……………………………………………….46
viii

4. III-V Nanostripe Devices……………………………………………………49
4.1. Templated Liquid Phase Growth of Device Structures…………………………………..49
4.2. TLP III-V Device Fabrication……………………………………………………………51
4.3. InP FET Characteristics…………………………………………………………………..52
4.4. InP and InAs Hall Mobilities……………………………………………………………..53

5. Mimicking Biological Synaptic Functionality with an Indium Phosphide
Synaptic Device on Silicon for Scalable Neuromorphic Computing……...56
5.1. Introduction……………...……………………………………………………………….56
5.2. Biological Synapse……………………………………………………………………….57
5.3. InP-Al2O3 Artificial Synaptic Device…………………………………………………….58
5.4. Spike Amplitude Dependent Plasticity…………………………………………………...59
5.5. Metaplasticity…………………………………………………………………………….61
5.6. Spike Number Dependent Plasticity……………………………………………………...63
5.7. Spike Timing Dependent Plasticity………………………………………………………65

6. Epitaxial Growth Process Integration on Non-epitaxial Substrate……….68

7. 300
o
C Growth of Single Crystal InP and InAs for

CMOS Back-end-of-line
Devices……………………………………………………………………….71
7.1. Overview of LT-TLP Growth Process…………………………………………………..71
7.2. Single Crystallinity of LT-TLP InP……………………………………………………..74
7.3. Optoelectronic Quality Optimization of LT-TLP InP…………………………………...74
7.4. LT-InP Nanoribbon FET Fabrication and Device Characteristics………………………76
7.5. LT-InAs Hall Mobility…………………………………………………………………..78
7.6. Conclusion……………………………………………………………………………….79
References………………………………………………………………………...80
1

Chapter 1
A Brief Summary of my Research
My Ph.D. research has been centered on materials and device innovation as potential
candidates for future three dimensional integrated circuits (3D ICs). This chapter of my
dissertation highlights the main research results in a comprehensive but relatively high-level
narrative. Following chapters build on the highlights mentioned here, and give an in-depth fine-
detailed-technical description of the experiments and their outcomes.
1.1 3D Integrated Circuits: Why? What? How?
Let us start with the question: why do we need 3D integrated circuits?
Over the past five decades, the world has witnessed rapid technological growth driven by
progress in computational ability. This increase in the operational bandwidth has been engineered
by integrating a higher number of operational units per unit area of the microprocessor chip by
reducing the size of each operational unit, called Field Effect Transistor devices (FETs). Famously
referred to as the Moore’s Law,
1
this trend of making a better microprocessor chip by incorporating
larger number of FETs, has been successfully followed for multiple consecutive generations of
chip design (Figure 1.1). However, there is an impending problem. Improving integrated circuits
by device miniaturization is coming to an end, since device miniaturization is reaching its
fundamental physical limit.

A potential novel approach for continued improvement is a three
dimensional (3D) multifunctional integrated circuit.

Figure 1.1: Historical trend of increasing device density and reducing device dimension. Data
from en.wikipedia.org/wiki/Moore%27s_law and …/Transistor_count
2

What can be a zeroth order description of of a 3D IC architecture?
A representative cartoon of a 3D multifunctional integrated circuit is shown in Figure 1.2.
Essentially, there would be multiple functional circuits for logic, communication, and memory
operations stacked on top of each other in the same chip. One may think of it as a vertically stacked
motherboard with different circuits performing modular functions (logic, memory, etc.) in the
same chip, instead of different modular chips performing their functions and communicating
across the present-day motherboard. It is important to have 3D to get higher density of integration
(versus state-of-the-art 2D integration). And it is important to integrate multiple materials to
achieve multiple functionalities, since each material is ideally suited for unique applications.
Silicon has been the backbone material for the semiconductor industry all along due to early
advantages in manufacturing processes. But it is far from being the ideal semiconductor material
considering performance of devices. Compound semiconductors are a general class of materials
that have electronic and optoelectronic properties far superseding that of silicon, but have not quite
found their way into mainstream electronic devices because of economic disadvantage in
traditional growth processes and difficulty in efficient integration.

Figure 1.2: Schematic representation of a potential 3D IC stack.
3

So how can we fabricate such a structure?
There are several challenges associated with fabricating a 3D IC so that no commercial 3D IC
exists today despite this idea being there for literally decades. This dissertation is aimed at solving
some of the most fundamental problems to help pave the way forward. Those are:
(i) we need to integrate single crystal semiconductors on an amorphous buffer,
(ii) at a temperature below 400
0
C so that underlying active layers are not affected, and
(iii) we should be able to fabricate high-performance devices out of them.
1.2 Epitaxial lift-off and transfer
The most widely used approach towards that currently followed, is some variant of this
method called epitaxial growth and transfer.
2
In this case, semiconductor layers are epitaxially
grown on lattice matched substrates, and through multiple steps, transferred to the host substrate
on which devices are fabricated (Figure 1.3). This is successfully followed in many academic
setups and in some commercial applications, but there are also some well-known important
drawbacks: the process is expensive, is not scalable over large areas required for industrial
production, and has access to limited materials stemming from lattice matching and suitable
release-process constraints.

Figure 1.3: Integration of high performance devices by epitaxial lift-off and transfer.
Reproduced with permission from [2]. Copyright 2010, Springer Nature.
4

1.3 Direct non-epitaxial growth?
Alternatively, can we directly grow single crystal materials on amorphous materials
instead? The traditional methods for semiconductor growth such as metal-organic chemical vapor
deposition (MOCVD) and molecular beam epitaxy (MBE) would give single-crystalline growth
only when grown on single-crystal substrates. On the other hand, these methods would give a poly-
crystalline material (Figure 1.4) when grown on a buffer layer which is inherently amorphous.
3

Poly-crystalline materials would give device performance that are orders of magnitude lower than
that of their single-crystalline counterparts. This is the most important roadblock that has prevented
efficient integration of multifunctional high-performance devices in the past.

1.4 Thin Film – Vapor Liquid Solid growth
On the other hand, a novel growth technique was recently developed, called thin film
vapor-liquid-solid,
4, 5
where it was shown that large area single crystal indium phosphide (InP)
with grain size of the order of 100 m to 1 mm can be grown on refractory metal foils (Figure 1.5).
This was the first step towards growth of crystalline compound semiconductor film on a non-
epitaxial substrate.

Figure 1.4: Polycrystalline InP by MOCVD directly on amorphous Mo foil. Reproduced with
permission from [3]. Copyright 2012, American Institute of Physics.

Figure 1.5: Ultra-large-grain size polycrystalline InP by TF-VLS directly on amorphous Mo
foil. Reproduced with permission from [4]. Copyright 2013, Springer Nature.
5

How is it done? Well, as represented in Figure 1.6 (a), indium (In) is first deposited on
molybdenum (Mo) foil, and capped with silicon dioxide (SiO 2). This is then taken to the furnace
and heated to a growth temperature of 450-800
0
C, where In is molten. Phosphorus (P) is
introduced in the vapor phase which percolates through the SiO 2 capping layer, and gradually
saturates liquid In. As it gets slightly supersaturated, InP is precipitated. Now, once the first InP
nucleus forms, a depletion region of P is created around it driven by the high diffusivity of P in
liquid In, such that the concentration of P in that region is always below the solubility of P in liquid
In, and no InP is nucleated in this region. The second InP nucleus forms a distance away from the
first, of the order of 100 m to 1 mm, determined by the P flux and the initial In thickness.
The plot in Figure 1.6 (b) is an experimental verification of this model, where it is seen that the
nucleation density reduces with lower P flux, thereby giving rise to larger grain sizes. This work
was pioneered by Kapadia et. al. at UC Berkeley.

1.5 Templated Liquid Phase (TLP) growth
Then it was proposed that if we pattern the indium so that the lateral dimension is less than
a typical depletion length, each pattern will form only a single crystal.
6

1.5.1 Single Crystal Compound Semiconductor mesas on Diverse Substrates
Building on that, my research efforts first demonstrated growth of single crystal compound
semiconductor mesas on diverse substrates.
7

Figure 1.6: (a) Schematic of controlled grain size in TF-VLS growth. (b) Experimental
verification of nucleation model. Reproduced with permission from [4]. Copyright 2013,
Springer Nature.
6

Schematically shown in Figures 1.7 (a-d), we start with patterns of In capped with SiO 2 on a
substrate. This is then taken to the growth furnace and heated to the growth temperature in presence
of phosphine (PH3). The PH3 flux is controlled to ensure single nucleation in each pattern, which
with time, gradually grows as a single crystal to achieve single crystal InP in each pattern. Figures
1.7 (e-h) are a sequence of SEM images of InP nucleating in a pool of In, gradually growing as a
single crystal until the entire pattern is transformed to InP, so that the entire pattern is a single InP
crystal (which in this case, is 6 m diameter). Although InP is used to describe this process, it may
be noted that it’s not just InP that can be grown by this process. In fact we have grown many
different materials, and on a wide variety of substrates, as shown in Table 1.1.

Figure 1.7: (a) Schematic of TLP growth of InP on any substrate. (b) Representative SEM of
InP nucleating and growing in a pool of indium. Reproduced with permission from [7].
Copyright 2018, American Chemical Society.

Table 1.1: Different materials grown by TLP method on different substrates.
7

As representative examples, Figures 1.8 (a-c) are some experimental results, showing growth of
different stoichiometries of indium gallium phosphide, different stoichiometries of tin phosphide,
as well as an atomically sharp lateral heterojunction between InP and Sn 4P3.
Also, Figures 1.9 (a-c) are transmission electron microscope images showing InP grown on
crystalline Gd2O3, amorphous TiO2, and 2D graphene.

Figure 1.8: (a) In-Ga-P, (b) Sn-P, (c) InP-Sn 4P3 lateral heterojunction grown by TLP method.
Reproduced with permission from [7]. Copyright 2018, American Chemical Society.

Figure 1.9: InP grown on (a) crystalline Gd2O3, (b) amorphous TiO2, (c) 2D graphene.
Reproduced with permission from [7] (Copyright 2018, American Chemical Society) and [9]
(Copyright 2018, American Vacuum Society)
8

1.5.3 Large Area (>100 m) Single Crystal
Moving forward, we worked on expanding the area of the crystal, e.g. the mesas in Figure
1.10 (a) are over 100 m in length and 5 m in width. As evident by electron backscatter diffraction
(EBSD) inverse pole figure imaging in Figure 1.10 (b) (i-vi), each mesa is represented by a single
color, and is therefore a single crystal.

1.5.4 Crystal Quality Analysis of TLP InP
Figure 1.11 is a collage of representative (scanning) transmission electron microscopy
(S)TEM images of TLP InP. Figure 1.11 (a) shows InP growing directly on graphene transferred
on SiO2. The selective area electron diffraction (SAED) in Figure 1.11 (b) and the high resolution
TEM in Figure 1.11 (c) indicate the high crystalline quality of the grown films. However, it may
also be noted that given the stacking fault energy for III-Vs is low, these grown films often have
multiple stacking faults as shown in Figure 1.11 (d) and twinning present within the crystals as in
Figure 1.11 (e).

Figure 1.10: (a) InP growing as a single crystal in a Hall element structure, (b) single
crystallinity indicated by EBSD.
9

1.5.4 Surface roughness of TLP materials
As seen in Figure 1.12, the typical surface roughness of the grown films can be controlled
to within 1-2 nm RMS roughness. This is mainly determined by the initial indium film roughness,
which is controlled by evaporating indium at relatively low rates and with the samples connected
to a liquid nitrogen cooled stage to reduce surface mobility of incident In atoms.

Figure 1.11: (a) STEM image of InP on graphene transferred to SiO 2, (b) SAED and (c)
STEM image of InP on TiO2, (d) Stacking faults in InP on Gd2O3, (e) Twinning in InP on
HfO2.

Figure 1.12: AFM map of representative TLP InP surface.
10

1.5.5 Dewetting of Liquid Indium on Diverse Substrates
Before we go forward, it may be better to take a step back and recognize that the translation
from growth on metals to growth on dielectrics is actually non-trivial. Compared to this flat film
of InP on Mo (Figure 1.13 (a)), when similarly tried to be grown on SiO 2 (Figure 1.13 (b)), it
doesn’t stay flat. When patterned on molybdenum oxide (MoO x), it stays as intended (Figure 1.13
(c)), but forms holes when done on dielectric surfaces (Figure 1.13 (d)). The reason is that most
substrates are “indium-phobic” causing In to dewet when it’s molten.

To understand this better, we worked on a thermodynamic model, where we calculated the Gibbs
free energy of formation of two different structures: one wetting i.e. without void (Figure 1.14 (a)),
and one dewetting, i.e. with void (Figure 1.14 (b)). When we subtract one from the other, we get
the Gibbs free energy of formation of the void, and plot it as a function of void radius (r) for
different template radii (RT). As can be seen here (Figure 1.14 (c)), that for a given initial thickness
of In (h), there is finite probability of void formation, and a thermodynamically stable size of voids.
On the other hand, no stable void formation would occur for templates below a certain size for the
given indium thickness. In other words, liquid templates would always wet a given substrate once
they are above a critical aspect ratio.

Figure 1.13: Representative InP growth on different substrates before wetting control.
11

This is supported by experimental verification where we patterned In in multiple sizes on the same
chip, and heated them in vacuum above the melting point. It is observed (Figure 1.15) that below
a certain radius, patterns stay intact, whereas above it, voids are formed. And as predicted, the size
of the voids increase with increasing template radius.

Figure 1.14: Thermodynamic modeling of constrained wetting. Reproduced with permission
from [7] (Copyright 2018, American Chemical Society).

Figure 1.15: Experimental verification of size controlled wetting. Reproduced with
permission from [7] (Copyright 2018, American Chemical Society).
12

1.6 InP Channel MOSFET Characteristics
Moving forward, we tried to establish a scalable platform of InP microstripe FETs directly
grown on SiO2 with a very thin wetting layer of MoOx, and all devices on a chip being batch
fabricated simultaneously. After much optimization, reasonably uniform FET device performance
could be obtained as can be seen in a representative section of devices on a specific chip (Figure
1.16). These are fully-depleted junctionless long-channel devices, of 50 um channel length, 2um
width, and 100nm thick.
These devices showed reasonably high effective mobility of upto 500 cm
2
/V-s. It may be
noted that this mobility is limited by non-ohmic contacts at the source-drain, and charge traps at
the oxide-semiconductor interface. This is evident by the significant OFF-state current difference
between lower and higher source-drain voltages (Figure 1.17 (b)), as well as the increasing field-
effect mobility with increasing gate voltage (Figure 1.17 (d)). It may be noted however, that the
effective mobility stays approximately the same in the linear region of FET operation, and reduces
with higher gate overdrive due to surface roughness and interface scattering (Figure 1.17 (c)).

Figure 1.16: Fairly uniform characteristics of FET fabricated by batch processing on a chip.
Reproduced with permission from [8] (Copyright 2018, American Chemical Society).

13

1.7 Artificial Synaptic Device
While existence of traps was a hindrance to get higher mobility of the FETs, we utilized
these traps demonstrate artificial synaptic behavior through the FETs. Briefly, a biological synapse
(Figure 1.18 (a)) is the connection between two neurons, and the signal transduced to the post-
synaptic neuron is a time-domain convolution of the action potential from the pre-synaptic neuron
with the synaptic weight or synaptic strength.
Post Synaptic Current (𝑡) = 𝑤 ∗ 𝑓(𝐴𝑐𝑡𝑖𝑜𝑛 𝑃𝑜𝑡𝑒𝑛𝑡𝑖𝑎𝑙)
Also, the synaptic strength is itself dynamic, and is an evolutionary function of its present strength
and the activity of the surrounding neurons.
∆𝑤 (𝑡) = 𝑓 (𝑤 , 𝜃 )
Analogously, the MOS structure in the FET is the artificial synapse. The gate receives signal from
the pre-synaptic neuron, and a corresponding current is sent to the post-synaptic neuron by the
drain (Figure 1.18 (b)). The channel conductance is interpreted as the synaptic weight which
determines the current flowing to the post-synaptic neuron. And the conductance itself is dynamic,
where the gate pulse causes charging and discharging of oxide trap, changing the channel
electrostatics, thereby changing threshold voltage.

Figure 1.17: (a) Output characteristics, (b) Transfer characteristics, (c) Effective mobility, (d)
Field Effect Mobility of a representative device.
14

A number of synaptic learning mechanisms were demonstrated: spike amplitude dependent
plasticity, metaplasticity, spike number dependent plasticity, and spike timing dependent
plasticity, as shown in Figures 1.19 (a-d).
8

Figure 1.18: (a) Schematic of biological synapse, (b) Schematic of artificial synapse.
Reproduced with permission from [8] (Copyright 2018, American Chemical Society).

Figure 1.19: Different synaptic learning mechanisms mimicked by artificial synapse.
Reproduced with permission from [8] (Copyright 2018, American Chemical Society).
15

1.8 Novelty in Device Fabrication
Before moving forward, we may take a look at a small innovation done in the device
fabrication process that’s specific to the TLP geometry, and actually turns out that has more far-
reaching positive consequences than initially anticipated. The white regions seen along the sides
of the intended TLP structure in Figure 1.20 (a-b), are called “side-growths”, and they occur due
to vapor-phase reaction between some of the indium atoms that escape through the sides, and the
P in the environment. For device measurement to not be affected by extraneous carrier transport
properties including surface roughness scattering, these side-growths should ideally be gotten rid
of. It has been shown previously that side capping the structure would reduce the side-growth, but
that process is not fool-proof, and also it’s difficult to effectively cap everywhere particularly for
structures which have openings on all sides.
So, the approach we took was a post-growth self-aligned selective etch. It may be realized that the
side-growth is not capped, while the SiO2 keeps the TLP region fully capped. Therefore, we used
the chemically selective BCl3-Cl2 etch to remove the side-growths, while keeping the TLP
structure intact (Figure 1.20 (c-d)). Then the capping layer was removed by etching in fluorine
based wet or dry etch (Figure 1.20 (e-f)), and contacts were made to the structure (Figure 1.20 (g-
h)).

Figure 1.20: Device fabrication steps showing self-aligned side-etch and top cap etch.
16

1.9 InP-Si3N4 Hybrid Ring Resonator
Another benefit of developing the selective side-growth trim-etch, was the realization of a
coupled InP-Si3N4 ring resonator structure. As can be seen in the SEM images Figures 1.21 (a-d),
InP was grown selectively on Si3N4 ring resonator conformally all along the ring. This was done
by first fabricating the Si 3N4 ring, then doing another photolithography step to expose an aligned
ring on top of it, followed by deposition of In and SiO 2, lifted off, and then transforming the In to
InP. However, the presence of side-growth (as highlighted in Figure 1.21 (b)), would act as antenna
radiating out, and the ring resonance would be lost (Figure 1.21 (e)). Upon doing the self-aligned
side-etch, cavity-coupled photoluminescence was obtained at room temperature (Figure 1.21 (f)).

1.10 Optoelectronic Characteristics
Speaking of photoluminescence, here we get back to describing the intrinsic properties of
the grown materials, specifically photoluminescence. Figure 1.22 shows a set of curves depicting
representative PL characteristics of TLP InP, and is compared with that of commercial single-
crystal InP wafer (black curve in each plot). As can be seen here, they have similar linewidth
(Figure 1.22 (a)) , indicating similar optoelectronic quality. A more sensitive probe of the material
quality is the subband-gap absorption or Urbach tail, which is heavily influenced by disorder in
the semiconductor. Sharper band tails are indicative of higher electronic quality and are defined
by a smaller inverse slope in units of meV/decade. As seen here, both the wafer and the grown

Figure 1.21: SEM of InP on Si3N4 ring (a-b) without side-etch, (c-d) with side-etch, (e)
photoluminescence with no cavity coupling, (f) cavity coupled photoluminescence.
17

film have similar inverse slopes, indicating similar order of defects in the crystal (Figure 1.22 (b)).
The most sensitive probe is quantitative photoluminescence, which shows that the efficiency of
the films is within an order of magnitude of the InP wafer. If we translate this to device terms, that
would mean a reduction in maximum open circuit voltage in both cases, by about 45 mV (Figure
1.22 (c)).

And these properties are fairly uniform irrespective of the substrate the material is grown
upon, which is a very unique and important aspect of this growth method (Figure 1.23).
9

Figure 1.22: (a) SSPL spectrum, (b) Urbach tail, (c) quantitative PL efficiency of TLP InP
compared with InP wafer. Reproduced with permission from [7] (Copyright 2018, American
Chemical Society).

Figure 1.23: InP SSPL spectra on different substrates. Reproduced with permission from [7]
(Copyright 2018, American Chemical Society).
18

But the properties do depend significantly on the growth temperature, as shown in Figure
1.24. An optimal temperature which is also slightly substrate dependent, is seen in the range 550-
650
0
C.

Now, all of these results are in the higher temperature regime. But if we remember the premise of
this dissertation, we should ideally be able to do the integration at a temperature below 400
0
C. So
how would the characteristics be, if we reduce the growth temperature?
1.11 Low Temperature Templated Liquid Phase (LT-TLP) InP Growth
It turns out, that as we reduce the temperature, the quality actually degrades until in the
small growth window of 280-330
0
C, where it dramatically improves (Figure 1.25 (a-c)). The
reason for this behavior is not exactly understood, but it is hypothesized that this may be related

Figure 1.24: InP SSPL spectral analysis from growths at different temperatures. Reproduced
with permission from [9] (Copyright 2018, American Vacuum Society).
19

to different modes of reaction that are dominant between In and PH 3 or different P species (like in
tetramer/hexamer form). Figure 1.25 (d) shows a representative photoluminescence spectrum of
InP grown at an optimal temperature of 300
0
C.

Figure 1.26 shows representative images of single crystal growth in different geometries and on
different substrates at optimal temperature of 300
0
C. 1 m wide and 10 m long stripes of InP
growing as a single crystal on HfO2. These are 10 m diameter InP circles growing on polyimide.
Being able to reduce the growth temperature, allows us to grow these materials also on flexible
substrates.

Figure 1.25: InP SSPL spectral analysis from growths at different temperatures including
below 400
0
C.

Figure 1.26: Single crystal LT InP growth on different substrates.
20

EBSD inverse pole figure images show in Figure 1.27 that individual stripes are single crystals
(after correcting for existence of twins). And this also shows a small statistic of the different kinds
of crystal faces that occur in this growth process.

1.11.1 CMOS BEOL Compatible InP FET
Fabricating FET from these grown stripes, we have devices having high ON-OFF ratios of
10
4
, and ON current of 1 A/ m (Figure 1.28).

Figure 1.27: EBSD Kikuchi patterns and inverse pole figures showing single crystal LT-InP.

Figure 1.28: BEOL compatible InP FET characteristics.
21

1.11.2 Back-gated phototransistor
Being able to grow at low temperatures also allowed us to do back-gated phototransistor.
Under broadband illumination, it showed a peak responsivity of 20 A/W, with an average of 13
A/W in the ON state (Figure 1.29).

1.12 LT-TLP InAs Hall Mobility
Next, we turned to making InAs at low temperatures, and as can be seen in Figure 1.30 (a),
it gives very high mobility of about 6000 cm
2
/V-s at room temperature, and a fairly constant sheet
carrier density of 1.5e13 cm
-2
(Figure 1.30 (b)). Translated to a volume density, this would give
5e17 cm
-3
. However, as evident from the independence of temperature, this behavior is a direct
indication of the surface Fermi level pinning above the conduction band minimum, leading to a
formation of accumulation layer of high charge density near the surface.

Figure 1.29: BEOL compatible InP back-gated photo-FET characteristics.

Figure 1.30: (a) Electron mobility, (b) Sheet carrier density of LT-InAs.
22

1.13 Comparison of Electron Mobility
Figure 1.31 is a compilation of best electron mobilities of different materials directly grown
on an amorphous substrate. As can be seen, in comparison to all different families of materials
including 2D materials, transparent conductive oxides/nitrides, polycrystalline III-Vs, solid phase
crystallized Si, etc., TLP III-Vs have the best reported electron mobilities, with InAs being over 2
orders of magnitude higher than the usual rest.

1.14 Epitaxial Growth Process Integration on Non-epitaxial Substrate
Having looked at the intrinsic crystal properties of the TLP grown materials, here we finally
take a peek at some of our efforts in using these single crystal mesas as the seed layers for further
growth by traditional epitaxial methods like MOCVD. Being successful in being able to do so,
would allow us to leverage the vast advancement and high-performance devices developed over
the last several decades, to be translated on orders of magnitude cheaper substrates, and potentially
also back-end of CMOS.
Figures 1.32 (a-b) show representative TLP mesas, and Figures 1.32 (c-d) are that of mesas after
MOCVD growth. From the uniformly faceted texture that comes up, it is further obvious that the
underlying TLP mesa is indeed single crystal. Also, this is selective so that there isn’t growth in
the surrounding dielectric substrate. The microscale roughness that is seen, arises from different
rates of growth of the adjacent nuclei.

Figure 1.31: Comparison of electron mobility for different material families directly grown
on amorphous dielectrics.
23

Although the previous figure highlighted only the final steps of the process, it is important to talk
about the full process too, where the side-etching once again plays an important role. Specifically,
we start with growing by TLP method, etch the sides selectively, then etch the capping layer, and
finally perform the MOCVD growth (Figure 1.31).
Because if we don’t do the side etch, then MOCVD would nucleate from those as well, giving rise
to uncontrollable morphology and unpredictable final structure (Figure 1.32).
Figures 1.33 (a-b) are images of some partially optimized growth conditions to give InP MOCVD
growth on an InP TLP stripe, and Figures 1.33 (c-d) are that of MOCVD InGaAs growth on an
InP TLP circle.
1.15 Conclusion
Taking all of these together: growth of single crystal materials and at low thermal budget,
growth of multiple materials and in selective geometry, and demonstrating competitive electronic
and optoelectronic device performance, my dissertation aims to establish the important
fundamental steps to realizing 3D multifunctional integrated circuits in future.
The following chapters deliberate in depth, the summarized view given in this chapter.

Figure 1.32: Representative SEM of selective MOCVD growth on TLP seeds.
24

Chapter 2
Confined Liquid Phase Growth of Crystalline Compound
Semiconductor on Any Substrate
The information in this chapter is largely based on the peer-reviewed paper.
7

2.1 Template aspect ratio dependent wetting propensity
The critical aspect forming the basis of progression for any work described in this
dissertation, is a better understanding for microscale template wetting. Here, we first
experimentally study the behavior of circular indium templates on an oxide surface (representative
image shown in Figure 2.1 (a)) as they are heated to 250
o
C in vacuum (Tmelt=157
o
C) and then
cooled to room temperature. Figure 2.1 (b) shows the result for 400 nm thick indium templates
with an SiOx capping layer on a Gd2O3 substrate.

Figure 2.1: Optical microscope images of indium templates on Gd 2O3 (a) after cryo-
evaporation, and (b) after heating to 250
o
C and cooling back. Reproduced with permission
from [7]. Copyright 2018, American Chemical Society.
25

Two behaviors were observed. First, below a critical template radius, there was no observable
dewetting, while above the radius, nearly all templates dewetted. Second, for the templates which
dewetted, there is a stable void size in the dewetted films.

Figure 2.2 (a) shows the wetting fraction, defined as 1 −
(i.e. unity wetting fraction
indicates no void), for a 400 nm thick indium template as a function of template radius. For
templates with radius less than 6 m, no stable void can form, and thus no dewetting occurs. Larger
templates support a stable void, and thus the wetting fraction falls below 1. Figure 2.2 (b) shows
the same behavior with tin. We have developed a thermodynamic model (described in more detail
in section 2.2) that can explain these results, and can also predict both observed behaviors. The
model developed here shows excellent agreement with experimental data.

Notably, a similar dewetting experiment on MoO x gives unity wetting fraction irrespective of the
template radius, shown in Figure 2.3, thus further validating the experimental procedure and the
theoretical model.

Figure 2.2: (a) Experimental wetting fraction of indium templates of varying radius on
different substrates and supported by the thermodynamic model prediction. (b) Experimental
wetting fraction of tin templates of varying radius on different substrates and supported by
the thermodynamic model prediction. Reproduced with permission from [7]. Copyright 2018,
American Chemical Society.
26

2.2 Thermodynamics of confined liquid templates

The solid to liquid phase transition alters the free surface energies associated with the metal at its
interface with the bottom substrate, top capping layer, and the surrounding medium. As a result,
the liquid metal has a natural tendency to reshape to a geometry that minimizes the energy. It was
experimentally found that the liquid tends to dewet for certain template geometries, thus reducing
its contact area with the underlying substrate and capping layer, and increasing the area with the
surrounding medium.
To theoretically simulate this behavior, we model the structure as a metal cylinder of radius 𝑅
and height ℎ with the capping SiO2 layer on top, and the substrate on the bottom (Figure 2.4 (a)).

Figure 2.3: Wetting fraction of indium templates showing no dewetting of indium on MoO x.
Reproduced with permission from [7]. Copyright 2018, American Chemical Society.
27

The schematic for a dewetted template with void radius 𝑟 , and dewetted template height ℎ
is
shown in Figure 2.4 (b).

From mass conservation, the total volume of the metal with or without the void should be the same.
This yields the following geometric relationship between the initial height of the template, ℎ, and
the height of the dewetted template, ℎ
:
ℎ
= ℎ 𝑅 𝑅 − 𝑟
where it is assumed that, even after formation of the void, the height of the metal is even across
the contact surface (i.e., the geometry resembles a “hollow” cylinder). Note that the assumption of
a cylindrical geometry for the void does not cause much loss of generality since the surface area
thus created, and not the actual shape, is the important factor for energetic considerations.
Next, we define the following surface energies at the interfaces between the liquid metal, the top
capping layer, the bottom substrate, and the surrounding vapor: 𝜎 : surface energy between top
capping layer material and liquid metal; 𝜎 : surface energy between bottom substrate material and
liquid metal; 𝜎 : surface energy between liquid metal and vapor; 𝜎 : surface energy between top
capping layer material and vapor; 𝜎 : surface energy between bottom substrate material and
vapor.

Figure 2.4: Schematic of a metal template on substrate with capping layer (a) as-deposited
before annealing, (b) with void formation due to annealing. (c) Calculated free energy of
formation for a void of radius 𝑟 in different microscale liquid templates of radii 𝑅 . (d)
Wetting phase diagram showing traditional wetting (surface energy), constrained wetting
(geometry driven), and dewetting regimes. Color bar: wetting fraction. Reproduced with
permission from [7]. Copyright 2018, American Chemical Society.
28

Thus, the total surface free energy without the void can be estimated as
𝐹 = 𝜋𝑅 (𝜎 + 𝜎 )
( )
+ 2𝜋𝑅 ℎ𝜎 ( )
.
Term (𝑎 ) represents the energetic contribution from the liquid metal-top capping layer and liquid
metal-bottom substrate interfaces, which have area 𝜋𝑅 and surface energies 𝜎 and 𝜎 ,
respectively. Term (𝑏 ) represents the contribution from the liquid metal-peripheral vapor
interface, which has area 2𝜋𝑅 ℎ and surface energy 𝜎 .
Similarly, the total surface free energy with the void can be estimated by
𝐹 = 𝜋 𝑅 − 𝑟 (𝜎 + 𝜎 )
( )
+ 2𝜋 (𝑅 + 𝑟 )ℎ 𝑅 𝑅 − 𝑟 𝜎 ( )
+ 𝜋𝑟 (𝜎 + 𝜎 )
( )
.
As before, term (a) represents energetic contributions from the interfaces between the liquid metal
and the top and bottom substrates, which now have area 𝜋 (𝑅 − 𝑟 ). Term (b) represents the
combined contribution from the liquid metal-vapor interface at the external cylinder with surface
area 2𝜋𝑅 ℎ
and the internal cylinder with surface area 2𝜋𝑟 ℎ
. The new term (c) represents
contributions from the interfaces between the vapor and top capping layer and the bottom substrate
in the void, which have area 𝜋𝑟 and surface energies 𝜎 and 𝜎 , respectively.
We calculate the total surface free energy of the structure with (𝐹 ) and without the void
(𝐹 ). The difference of these two energies ∆𝐹 (= 𝐹 − 𝐹 ) indicates which
of the two orientations is more stable. For ∆𝐹 < 0, dewetting is energetically favorable while, for
∆𝐹 > 0, wetting is favorable.
The difference in free energy between the two geometries is:
∆𝐹 = 𝐹
− 𝐹
= 𝜋𝑟 (𝜎 − 𝜎 + 𝜎 − 𝜎 ) + 2𝜋 ℎ 𝑅 𝑅 − 𝑟 𝜎 − 2𝜋𝑅 ℎ𝜎
= 𝜋𝑟 (𝜎 − 𝜎 + 𝜎 − 𝜎 ) + 2𝜋𝑅 ℎ 𝑟 𝑅 − 𝑟 𝜎
Figure 2.4 (c) shows ∆𝐹 for 400 nm thick In on a Gd2O3

surface, and an SiO2 capping layer with
differing template radii, 𝑅 . Importantly, we see that the behavior of the free energy curves predicts
that below a critical template radius, void formation in the film is energetically unfavorable (∆𝐹 >0
for all 𝑟 ), and that above the critical radius, there exists a minimum in the free energy (
∆ = 0),
indicating a thermodynamically favorable void size.
Normalizing and defining ∆𝐹 ′ =
∆ and 𝑟 =
, and noting that cos 𝜃 =

and cos 𝜃 =
, where 𝜃 is the contact angle between the liquid metal and the top capping
material, and 𝜃 is the contact angle between the liquid metal and the bottom substrate, we have:
∆𝐹 ′ =
1
2
𝑟 𝑅 ℎ
(cos 𝜃 + cos 𝜃 ) +
𝑟 1 − 𝑟
From this equation for change in free energy, we can derive the following conclusions:
29

1. ∆𝐹 ′ > 0 ∀ cos 𝜃 + cos 𝜃 > 0
2. For cos 𝜃 + cos 𝜃 < 0, and a given template aspect ratio , the stable void radius
would be for the case
∆ = 0, which yields
𝑟 (1 − 𝑟 )
= −
1
𝑅 ℎ
(cos 𝜃 + cos 𝜃 )

This equation can be numerically solved to find the critical aspect ratio (𝑅 ℎ ⁄ )
below which
we do not get a valid 𝑟 solution for (cos 𝜃 + cos 𝜃 ) < 0. For (𝑅 /ℎ) < (𝑅 ℎ ⁄ )
, no stable
void exists. Above this critical aspect ratio, we get an asymptotically increasing 𝑟 solution, which
implies that a stable void exists, and the void radius increases with (𝑅 /ℎ).
Figure 2.4 (d) shows a “wetting phase diagram”, with the horizontal axis corresponding to the
template aspect ratio (𝑅 ℎ ⁄ ), and the vertical axis corresponding to the sum of the contact
angles, cos 𝜃 + cos 𝜃 (=
+
), where 𝜃 is the contact angle between the liquid
metal and the capping material, and 𝜃 is the contact angle between the liquid metal and the
substrate. When this sum is greater than 0, the surface energies of the template prevent the
formation of a stable void, independent of the template geometry. When this sum is less than zero,
the liquid wets the template only when it is below some critical aspect ratio, .

The surface energy values used for model computations are
10, 11
:
𝜎 = 0.8 J/m
2
(SiO2)
𝜎 = 0.68 J/m
2
(SiO2)
𝜎 = 0.023 J/m
2
(Gd2O3)
𝜎 = 0.5 J/m
2
(Gd2O3)
𝜎 = 0.6 J/m
2
(In), 0.7 J/m
2
(Sn)

2.3 Templated liquid phase growth
Therefore, nearly independent of surface energy, it is possible to find dimensions which
enable wetting of the template, and thus allows us to carry out confined templated liquid phase
(TLP) growth on any thermally stable substrate. This allows us to predict and design templates
that will enable liquid phase wetting on a substrate of choice with knowledge of only the surface
energy values. With this, we then show that InP, GaP, InAs, InGaP, SnP, and Sn 4P3 crystals can
be grown directly on SiO2, Si3N4, TiO2, Al2O3, Gd2O3, SrTiO3, and graphene. The variety of
materials and substrates illustrate this approach is truly general. Figure 2.5 shows a schematic of
the TLP process.

30

Indium (99.99995%) and/or tin (99.9999%) and/or gallium (99.99995%) was thermally
evaporated on the lithographically patterned samples mounted on a cryo-cooled (liquid nitrogen)
stage using an alumina covered tungsten boat at rates of 4-5 Å/sec. The thickness of evaporated
metal was varied between 400-800 nm as required by the lateral mesa dimension and substrate
based on the thermodynamically controlled geometric wetting model. A capping layer of 180-200
nm SiO2 was electron-beam evaporated using SiO2 pellets (99.99% pure, Kurt J Lesker). This was
followed by standard photoresist lift-off procedure in acetone, resulting in templates of
metal/capping layer stacks on substrate.
TLP growth was done in a single-zone hot-wall tube furnace (Lindberg Blue) under furnace
temperature ranging between 450 to 650
0
C (specific temperatures are mentioned in the main text
for individual material systems). 100% PH3 (99.9995%, Matheson) was used as the P precursor,
diluted u with 99.999% H 2 to achieve the desired PH3 partial pressure. The PH3 flux was controlled
to ensure nucleation of a single compound semiconductor crystal in each liquid metal template.
This occurs by obtaining a phosphorus depletion region around the initial nucleation region which
prevents the surrounding liquid melt from being supersaturated with P, and thus no further stable
nucleation occurs in that region. This allows the initial nucleus to grow out into a single crystal,
consuming the entire metal template.
Figures 2.6 (a-d) are scanning electron microscope (SEM) images of TLP growth of InP in
an indium template at various stages of growth, starting with a single nucleus of the
thermodynamically favorable hexagonal faceted shape for a (111)-oriented crystal, and ending
with the circular template geometry.

Figure 2.5: Schematic of the TLP growth process. Reproduced with permission from [7].
Copyright 2018, American Chemical Society.
31

To understand the nature of the interface between the single crystal templates and the
substrate, as well as the structural quality of the materials, we have carried out transmission

Figure 2.6: SEM image of InP growing in an indium template on a Gd 2O3 substrate.
Reproduced with permission from [7]. Copyright 2018, American Chemical Society.

Figure 2.7: TEM image of InP grown on (a) Si/crystalline Gd 2O3, (b) Si/SiO2/TiO2. (c)
HRTEM image of InP grown on graphene transferred to an Si/SiO 2 wafer. (d) Selected area
electron diffraction pattern of InP grown on graphene transferred to an Si/SiO 2 wafer. (e)
Scanning transmission electron microscope image of InP grown on TiO 2. Reproduced with
permission from [7]. Copyright 2018, American Chemical Society.
32

electron microscopy (TEM) imaging of InP/Gd 2O3/Si, InP/Graphene/SiO2/Si, and InP/TiO2/
SiO2/Si. Figures 2.7 (a) and (b) show TEM images of InP grown on a Si/Gd 2O3 and Si/SiO2/ TiO2
substrate, respectively. Figures 2.7 (c) shows a TEM image of InP/Graphene/SiO 2/Si, where the
lattice planes of InP are clearly visible. This indicates both the crystalline nature of the InP and the
clean interface with the amorphous substrate. The electron diffraction pattern of the crystal along
the [112] zone axis is shown in Figure 2.7 (d). Finally, we show a scanning transmission electron
microscope (STEM) image of InP crystals grown on a TiO 2 substrate, with the atomic resolution
showing the excellent crystalline quality of materials grown via this approach (Figure 2.7 (e)).

2.4 Far from equilibrium ternary material growth
A key advantage of III-V material systems is the tunability of the bandgap via alloying of
multiple group III or group V elements. Unlike binary line compounds such as InP or GaP, alloys
have a wide range of stable stoichiometries; therefore, ensuring uniform alloy composition during
growth is a challenge. For TLP growth of an In x-Ga1-x-P alloy, the approach would be to evaporate
In and Ga as the template with the desired atomic ratio, and then carry out the growth. With a near
equilibrium liquid phase growth approach, however, uniform material can only be achieved if the
solid which precipitates out has the same In/Ga ratio as the liquid. But in general, the solid will
not have the same In/Ga ratio as the liquid, and thus we would not expect to be able to create
uniform materials. Thus, the composition of the liquid would continuously change throughout the
growth process, resulting in significant lateral grading of the solid composition and bandgap. This
would be observable as a large spread in the peak position of the photoluminescence.
12

To explore this, circular InxGa1-x templates with x=1, 0.9, 0.7, and 0 were fabricated, and
then grown under a phosphine/hydrogen ambient at temperatures varying from 550
o
C - 750
o
C.
After growth, the results were interrogated through microphotoluminescence, with a spot diameter
of 1 m. Figure 2.8 (a) shows photoluminescence of the InxGa1-xP grown by tuning the In/Ga ratio
in the template
13
. In Figure 2.8 (b) we show how the Raman spectra of the grown material shift as
a function of In/Ga ratio. The TO and LO peaks of InP shift as Ga is added
14
, and at higher Ga
fractions (x=0.7), we see the emergence of a third, broader GaP-like LO peak, induced by alloy
disorder.
33

While the micro PL shows that tuning the composition of the liquid metal clearly changes the
bandgap of the grown material, it is necessary to identify the spread in bandgap to quantify the
results of the growth. By taking multiple PL spectra across a grown chip and extracting the peak
energy, the spread in bandgap is determined. In0.9Ga0.1P was grown at temperatures ranging from
550
o
C to 750
o
C, with Figure 2.8 (c) showing the peak position with error bars representing the
distribution, and Figure 2.8 (d) shows the standard deviation of the peak position. A minimum in
the standard deviation of the material is observed for a growth temperature of 645
o
C of 16 meV,
which is significantly lower than expected. Thus, the uniformity of this material is expected to be
driven by growth at a high rate, pushing it far from equilibrium and removing the expected
constraint due to near equilibrium growth. The experimental trend is consistent with this
hypothesis. At lower temperatures, the growth rate is limited by the precursor cracking and mass
transport to the substrate, while at higher temperatures the growth rate is reduced due to an increase
in re-evaporation of the phosphorus from the liquid templates, reducing the supersaturation and
the driving force for growth. While InxGa1-xP is demonstrated here, a clear route is presented
towards far-from equilibrium growth of uniform ternary alloys with this growth technique.
2.5 Growth of single-crystalline materials without an established single
crystal substrate
Unlike III-V semiconductors explored here, many novel materials do not have well-
established epitaxial substrates, limiting the ability to grow thin-film geometry single crystalline
materials. One example of this is tin phosphide, a promising emerging layered material system

Figure 2.8: (a) PL spectra, and (b) Raman spectra of InGaP with varying Ga fractions. (c)
Extracted bandgap and dispersion in observed bandgap across grown In 0.9Ga0.1P as a function
of temperature. (d) Variance of bandgap across growths as a function of temperature.
Reproduced with permission from [7]. Copyright 2018, American Chemical Society.
34

with multiple stable phases
15, 16
, each with dramatically different properties and crystal structures.
Rhombohedral Sn4P3
17
and hexagonal SnP
18, 19
have been recently demonstrated as ultra-high
capacity anode materials for sodium and lithium ion batteries, respectively. However, due to the
lack of an available epitaxial template for tin phosphide, the demonstrations have been limited to
powders, nanoparticles, and small bulk crystals
16-21
. By removing the need for an epitaxial
template, TLP enables us to grow phase pure, templated crystalline Sn 4P3 and SnP on a
silicon/SiO2 handle wafer. Growth is carried out by first depositing tin into circular arrays with a
SiOx capping layer, directly on the Si/SiO2 or Mo substrate, and then following the TLP growth
process to get tin phosphide. Figure 2.9 (a) shows an SEM image of tin phosphide templates grown
on an Si/SiO2 substrate and the corresponding EDS images showing tin (Figure 2.9 (b)),
phosphorus (Figure 2.9 (c)) and Si (Figure 2.9 (d)).

The atomic structures of rhombohedral Sn 4P3
22
and hexagonal SnP
23
are schematically
shown in Figures 2.10 (a) and (b), respectively. Both phases exhibit a layered structure with
alternating planes of P and Sn atoms along the c-axis, with Sn 4P3 exhibiting 7 alternating planes
per layer, and SnP exhibiting 3.

Figure 2.9: (a) Top-view SEM of crystalline Sn xPy arrays grown on SiO2. Corresponding
EDS images showing (b) Sn, (c) P, (d) Si. Reproduced with permission from [7]. Copyright
2018, American Chemical Society.
35

Figures 2.11 (a) and (b) show Raman spectra of Sn4P3 and SnP, respectively. Due to the
dramatically different crystal structures, these materials have distinct Raman spectra, allowing us
to identify the phase we have grown. When grown at 450
o
C, 100% of the Raman spectra match
that shown in Figure 2.11 (a), while at 550
o
C, 100% match the spectra shown in Figure 2.11 (b).
For growth temperatures within that range, both Raman spectra are observed, indicating that a
combination of phases are present.

Figure 2.10: Crystal structures of tin phosphide (a) rhombohedral Sn 4P3 grown at 450
o
C, (b)
hexagonal SnP grown at 550
o
C. Reproduced with permission from [7]. Copyright 2018,
American Chemical Society.
36

X-ray photoelectron spectroscopy (XPS) was also used to then identify the valence states of the
Sn and P atoms in both phases. Figure 2.11 (c) shows the XPS spectra of tin (3d) in Sn 4P3,
illustrating presence of only Sn
4+
(487.6 eV). On the other hand, Figure 2.11 (e) shows that in SnP,
a mix of Sn
4+
(487.6 eV) and Sn
0
(485.3 eV) valences occur. Figures 2.11 (d) and (f) show that
both stoichiometries show the expected doublet phosphide P
3-
(2p) peak (129.5 eV, 130.5 eV), and
a phosphate PO
x-
peak (134 eV). The intensity of the phosphate peak was found to be higher on
samples with longer exposure to ambient air after growth, and is expected due to surface oxides (a
similar phosphate PO
x-
peak was also found to be present on InP wafer, thus confirming this
hypothesis, not shown here). The X-ray diffraction (XRD) spectra of the two phases are shown in
Figures 2.12 (a) and (b) respectively.

Figure 2.11: Raman spectra of (a) Sn4P3, and (b) SnP. XPS spectra of (c,e) Sn4P3, and (d,f)
SnP. Reproduced with permission from [7]. Copyright 2018, American Chemical Society.
37

2.6 Lateral heterojunction of distinct crystal structures

It was also demonstrated that this approach enables high-quality hetero-interfaces
between non-epitaxial crystalline materials, which is not possible with vapor phase epitaxy
techniques. To achieve this, we heat an array of indium and tin mesas to 550
o
C and then introduce
phosphine. At these temperatures, the two metals will fully mix before introduction of PH 3.
However, indium phosphide and tin phosphide do not form any stable ternary compound
24
, as the
crystal structures are vastly dissimilar, thus both indium phosphide and tin phosphide grow from
a single In/Sn melt. Figure 2.13 (a) shows an SEM image of the InP-Sn 4P3 crystals grown on
Si/SiO2 with a layer of ALD TiO2. Figure 2.13 (b) shows a TEM image of the InP-Sn 4P3 interface
on the TiO2 surface. Four EDS elemental maps of Figure 2.13 (b) allow us to investigate materials
and interface properties: In (Figure 2.13 (c)), P (Figure 2.13 (d)), Sn (Figure 2.13 (e)), and Ti
(Figure 2.13 (f)). In Figure 2.13 (c), we observe a clear interface between the InP, Sn 4P3, and
underlying TiO2, and Figure 2.13 (d) shows P observed uniformly across both InP and Sn 4P3. Due
to the solubility of Sn in InP, we observe a background concentration of Sn doping in the InP

Figure 2.12: XRD spectra of (a) Sn4P3, and (b) SnP. Reproduced with permission from [7].
Copyright 2018, American Chemical Society.
38

(Figure 2.13 (e)). The underlying TiO2 substrate (Figure 2.13 (f)) shows no In, P, or Sn
incorporation due to the thermal stability at the growth temperatures.

Remarkably, high-resolution TEM imaging (Figure 2.14 (a)) shows that this approach
enables us to create lateral atomically-sharp crystalline heterostructures from materials with
completely dissimilar crystal structures. To gain an atomic scale understanding of the interface,
we have indexed the TEM images of the InP and Sn 4P3 to determine the orientation of both crystals
at the interface. It is found that Sn4P3 (001) planes are growing on top of an InP (111) termination.
From this, we have built a ball-and-stick chemical model of the InP (Figure 2.14 (b)) and Sn 4P3
(Figure 2.14 (c)) showing the {111}InP|{001}Sn 4P3 || <110>InP|<120>Sn4P3 interfacial
relationship.

Figure 2.13: (a) SEM image of an InP/Sn 4P3 lateral heterojunction, (b) TEM image of the
heterojunction and TiO2 substrate, (c-f) EDS maps of In, P, Sn, and Ti, showing the
heterojunction on the substrate clearly. Reproduced with permission from [7]. Copyright
2018, American Chemical Society.
39

At these growth conditions, InP nucleates and grows first, incorporating Sn, and leaving behind a
melt of Sn, after which Sn4P3 nucleates and grows. This can be predicted from the metal-rich
liquidus curves of the In-P and Sn-P binary phase diagrams. At 550
o
C, the solubility of P in liquid
indium is <0.2%
25
, while the solubility of P in Sn is >10%
15
. Thus, as the concentration of P
increases in the uniform Sn/In melt, the Gibbs free energy for InP precipitation will cause
nucleation of the InP first. After this, the surface of the growing InP crystal will act as a sink for P
atoms, depleting the entire template, suppressing further nucleation of InP and Sn 4P3. After the
InP crystal has consumed the excess In, the melt is expected to be entirely Sn with In impurities,

Figure 2.14: (a) High resolution TEM image of the interface, showing nearly atomically sharp
interface. Atomic scale model of (b) InP [110] with {111} termination and (c) Sn 4P3 [120]
with {100} termination at the interface. Reproduced with permission from [7]. Copyright
2018, American Chemical Society.
40

and the phosphorus concentration will continue to rise. Finally, the Sn 4P3 will nucleate and grow
in the template, creating a lateral heterostructure as shown here. As this requires the two materials
to have crystal structures so vastly dissimilar that the formation of any alloys is precluded, the set
of high-quality material interfaces that can be formed with this approach is orthogonal to standard
vapor-phase growth approaches.

41

Chapter 3
Optoelectronic Properties of Templated Liquid Phase Grown
Indium Phosphide

The information in this chapter is largely based on the peer-reviewed papers.
7,9

3.1 Steady State Photoluminescence Characteristics
We study the optoelectronic quality of indium phosphide grown on various substrates.
While the crystallinity is easily observable from direct inspection, such as TEM or visual
observation of the crystal geometry while growing, understanding the quality of this material
requires more sensitive probes. Steady-state photoluminescence curves of the TLP InP on Gd 2O3
and a commercially purchased InP wafer are shown in Figure 3.1 (a).

Figure 3.1: (a) Photoluminescence spectra of a commercial InP wafer and the USC InP. (b)
Sub-bandgap density of states spectra. (c) Quantitative photoluminescence of USC InP and
InP wafer. Reproduced with permission from [7]. Copyright 2018, American Chemical
Society.
42

Figure 3.2: PL of TLP InP grown on a, single crystal strontium titanate (SrTiO 3), b, thermally
grown SiO2, c, PECVD Si3N4, d, ALD Al2O3, e, ALD TiO2, f, graphene transferred to
Si/SiO2 handle wafer. Reproduced with permission from [7]. Copyright 2018, American
Chemical Society.
43

3.2 Urbach parameter

A more sensitive probe of the material quality is the sub-bandgap absorption or band-tail
26
,
which is heavily influenced by disorder in the semiconductor. Sharper band-tails are indicative of
higher electronic quality, and are defined by a smaller inverse slope in units of meV/decade. Here,
the TLP InP, exhibits a band tail slope of 17.18 meV/decade with E 0=7.16 meV, while the InP
wafer exhibits a slightly higher 17.38 meV/decade with E 0=7.34 meV (Figure 3.1 (b)). The method
for estimation of the Urbach parameter is discussed in the following subsection.

3.2.1 Estimation of Urbach parameter

The van Roosbroeck-Schockley equation relates the optical emission rate per unit energy
𝑅 (ℎ𝑣 ) to the absorption coefficient 𝛼 (ℎ𝑣 ) as
27

𝑅 (ℎ𝑣 ) = 𝛼 (ℎ𝑣 )
⁄

Table 3.1: Comparison of photoluminescence spectral metrics of InP grown on different
substrates with InP wafer. Reproduced with permission from [7]. Copyright 2018, American
Chemical Society.
Substrate Peak position
(eV)
FWHM
(eV)
Gd
2
O
3
1.349 ± 0.0012 0.048 ± 0.0021
SrTiO
3
1.348 ± 0.0016 0.048 ± 0.0020
SiO
2
1.348 ± 0.0016 0.055 ± 0.0026
TiO
2
1.346 ± 0.0035 0.050 ± 0.0025
Al
2
O
3
1.339 ± 0.0021 0.048 ± 0.0029
Si
3
N
4
1.343 ± 0.0027 0.056 ± 0.0033
Graphene 1.338 ± 0.0035 0.047 ± 0.0028
Reference InP 1.346 ± 0.0001 0.048 ± 0.0001
44

where 𝑅 (ℎ𝑣 ) is the emission intensity, 𝜈 is frequency, ℎ is Planck’s constant, 𝑐 is the speed of
light in vacuum, 𝑘 is Boltzmann’s constant, 𝑇 is absolute temperature.
Energies for which absorption coefficient is small, such as in the bandgap, the (external)
photoluminescence spectrum 𝑃 (ℎ𝜈 ) may be approximated to be of similar shape to that of the
emission spectrum, irrespective of the thickness of the sample. Thus, the van Roosbroeck-
Shockley equation may be represented as
28

𝛼 (ℎ𝜈 ) ∝ 𝑃 (ℎ𝜈 )
⁄
( )

As first pointed out by Franz Urbach, the absorption coefficient in the bandgap scales
exponentially with energy
26
, so that it can be fitted with an equation of the form
𝛼 (ℎ𝜈 ) = 𝛼 𝑒 ( ) ⁄

where 𝛼 and 𝐸 are fitting parameters, and 𝐸 is a reference energy. The term 𝐸 is referred to
as Urbach parameter, and is indicative of the sharpness of the exponentially decreasing absorption
in the bandgap.
Though it is not well understood, it is thought that the absorption in the bandgap is related
to bandgap states arising from intrinsic and extrinsic crystal defects, and thus a lower value of
Urbach parameter is a measure of lesser defect density in the material.

3.3 Photoluminescence Efficiency and quasi-Fermi-level Splitting

The most sensitive probe of optoelectronic quality, however, is the photoluminescence
efficiency, defined as
, and enables us to extract the electron and hole quasi-Fermi
level splitting in a material. Figure 3.1 (c) shows the photoluminescence efficiency and quasi-
Fermi level splitting (∆𝐸 ) versus incident power for TLP and commercial InP (the methods for
measuring and calculating the same are discussed in the following subsections). ∆𝐸 is defined as
the difference between the electron and hole quasi-Fermi level under illumination. The dashed line
indicates ∆𝐸 for the ideal case, where only radiative emission processes exist, and every absorbed
photon is reemitted as photoluminescence. Critically, within the range of measured photon fluxes,
the difference in ∆𝐸 between the grown InP and wafer is ~45 meV. Compared to the theoretical
limit, the InP wafer exhibits ∆𝐸 ~150 meV lower while the TLP InP exhibits ~195 meV less than
the theoretical limit. Thus, we show this approach enables the growth of excellent quality materials
with spectral characteristics, sub-bandgap absorption, and luminescence intensity nearly identical
to single crystalline wafers.

3.3.1 Measurement of External Luminescence Efficiency

A broadband light source with calibrated relative intensity variation was used to obtain the
system response function, 𝜂 . A wavelength calibrated power meter Thorlabs PM100D was used
45

to measure the incident laser powers and calculate the excitation photon flux, 𝑅 (number of
photons/area/sec). The reference InP wafer photoluminescence with known quantum efficiency (at
a given incident power) was thereby used to calibrate the instrument counts to external photon
emission flux 𝑅 (number of photons/area/sec).
The external luminescence efficiency of the grown InP was thus calculated from the measured
photoluminescence as
𝜂 =
𝑅 𝑅
where 𝑅 is the photoluminescence flux and 𝑅 is the incident photon flux.

3.3.2 Calculation of Quasi Fermi Level Splitting
The quasi-Fermi level splitting is calculated as
29
:
Δ𝐸 = 𝑘𝑇 ln ∫ ∫ ∫ ( , ) ( ) ( ) ∅
+ 𝑘𝑇 ln(𝜂 ),
where 𝜂 is the photoluminescence external quantum efficiency, and 𝑎 (𝐸 , 𝜃 ) is the effective
absorbance of the incident flux by the semiconductor, given as
𝑎 (𝐸 , 𝜃 ) = 𝔸 (𝐸 ) × 𝕋 (𝜃 )
The energy-dispersive absorptance 𝔸 (𝐸 ) of the semiconductor of thickness 𝐿 is
𝔸 (𝐸 ) = 1 − 𝑒 ( )
with the absorption coefficient
𝛼 (𝐸 ) = 10
𝑐𝑚 𝑓𝑜𝑟 𝐸 ≥ 𝐸 10
∗ 𝑒 𝑐𝑚 𝑓𝑜𝑟 𝐸 ≤ 𝐸
where 𝐸 is the photon energy, 𝐸 is the band-gap energy, 𝐸 is the Urbach parameter.
It may be noted that the absorptance thus calculated, assumes a perfect reflector at the bottom of
the InP, which may not be true in these substrates.
𝕋 (𝜃 ) is the transmittance of the semiconductor-air interface calculated from Fresnel equations.
𝑏 (𝐸 ) is the blackbody spectrum at temperature 𝑇 given by
𝑏 (𝐸 ) =
2𝑛 ℎ
𝑐 𝐸 1
𝑒⁄
− 1

where 𝑛 is the refractive index of free space, ℎ is Planck’s constant, 𝑐 is the speed of light in
vacuum, 𝑘 is Boltzmann’s constant, and 𝑇 is temperature (here taken to be 300 K).
𝑅 is the absorbed photon flux calculated as
𝑅 = 𝑎 (𝐸 , 𝜃 ) × 𝑅
with 𝐸 being the laser excitation energy, 𝜃 = 0 for normal incidence of the excitation.

46

3.4 Temperature Dependent Growth Quality Optimization
We explored the growth condition optimization of optoelectronic properties of TLP InP
grown on crystalline and amorphous insulators on silicon, with a commercial single crystalline
wafer as the reference. Photoluminescence spectra from materials grown at different temperatures
were analyzed to extract peak position, full width at half maximum (FWHM), and Urbach
parameter as metrics for optoelectronic quality comparison. Nominally the peak luminescence
occurs at the bandgap energy of the semiconductor. But the peak position may blue shift (called
Burstein-Moss shift) because of doping of the semiconductor leading to an effective shift in the
energy level with available states
30, 31
. A red shift in the peak position may be caused by presence
of charge traps in the bandgap with long lifetime. An average of 20 data samples obtained from
growths done over a range of PH3 partial pressure were used to build the statistics for each growth
temperature of 450
0
C, 540
0
C, 650
0
C, and 750
0
C. Probability density distributions of peak
position for different growth temperatures are plotted in Figure 3.3 (a) and fitted with skewed
Gaussian functions. The quartile distribution of the peak position variation with growth
temperature is shown in Figure 3.3 (b). It is observed that a growth temperature of 650
0
C gives
the narrowest dispersion around the median peak position very close to that of the single crystal
wafer. Similar statistical analysis for FWHM and Urbach parameter were also performed and are
shown in Figures 3.3 (c-e). For a clear visual comparison, the respective parametric values for the
reference InP are also plotted in the corresponding quartile plots. Based on the holistic statistical
analysis of the optoelectronic parameters, 650
0
C appears to be an overall optimal growth
temperature for vapor-liquid-solid InP templated films grown on Gd 2O3. Similar statistical
analyses were also carried out on InP grown on other substrates, specifically graphene transferred
on silicon dioxide (SiO2) as shown in Figure 3.4 (a-c), silicon nitride (Si 3N4) shown in Figure 3.4
(d-f), and titanium dioxide (TiO2) as shown in Figure 3.4 (g-i). In general, very narrow dispersion
of the optoelectronic metrics namely peak position, FWHM, and Urbach parameter was observed
for each substrate.
3.5 Buffer Insensitive Optoelectronic Quality
It is important to observe that TLP InP of optoelectronic quality comparable to a single
crystal InP wafer can be obtained in a growth temperature window of about 100
0
C between 540
0
C
and 650
0
C, independent of the chemical composition and microstructure of the substrate being
used, qualitatively shown in Figure 3.2. By performing detailed optoelectronic characterization,
we find that the quality of the grown material not only closely matches commercial single
crystalline InP wafers but is also highly insensitive to the buffer layer used. Given that this material
was grown in a simple quartz tube furnace with no regard to controlling gas flow, this is important
evidence pointing to the potentially improved scalability of this approach as compared to standard
vapor-solid approaches that require complex gas flow control to achieve material uniformity across
wafers. Brief statistics of the quality metrics is given in Table 3.1.

47

Figure 3.3: Optoelectronic quality control through growth process optimization. Probability
density distributions of (a) peak position, (c) FWHM, (e) Urbach parameter of InP templates
grown on crystalline Gd2O3 film on Si at 450, 540, 650, and 750
0
C. Box-and-whisker
quartile plots of (b) peak position, (d) FWHM, (f) Urbach parameter of InP grown on
crystalline Gd2O3 film on Si at 450, 540, 650, and 750
0
C. Data of about 20 measurements
are analyzed at each temperature. Reproduced with permission from [9]. Copyright 2018,
American Vacuum Society.
48

Figure 3.4: Quartile plots for peak position, FWHM, and Urbach parameter for InP templates
grown on (a)–(c) graphene, (d)–(f) Si3N4, and (g)–(i) TiO2 on Si/SiO2 handle wafer.
Reproduced with permission from [9]. Copyright 2018, American Vacuum Society.
49

Chapter 4
III-V Nanostripe Devices

While photoluminescence gives a sense of the optoelectronic quality of the grown material, a
suitable measure of the electronic quality would be given by FET characteristics and the derived parameters
such as effective mobility. The information in this chapter is largely based on the peer-reviewed
paper
8
as well as one submitted for peer review.

4.1 Templated Liquid Phase Growth of Device Structures

Si/SiO2 substrate was thoroughly cleaned with acetone, isopropyl alcohol and deionized
water, and blow-dried with dry nitrogen. FET channel templates were photolithographically
patterned on the substrate.
4-6 nm MoOx followed by 100 nm Indium (99.99995%) was thermally evaporated using alumina
covered tungsten boats, on the patterned samples connected to a cryo-cooled (liquid nitrogen)
stage. 100 nm SiO2 was electron-beam evaporated using SiO2 pellets (99.99%), as the capping
layer. FET templates of MoOx/In/SiO2 were then obtained using standard lift-off procedure,
schematically shown in Figure 4.1 (a-b).

TLP growth of InP was done in a single-zone hot-wall tube furnace at furnace temperatures in the
range 550-575
0
C. 99.9999% PH3, diluted ex-situ with 99.999% H2 to achieve the desired PH3

Figure 4.1: Schematic of templated liquid phase growth of crystalline InP nanowire arrays on
Si/SiO2 and subsequent fabrication of nanowire FETs. Reproduced with permission from [7].
Copyright 2018, American Chemical Society.
50

partial pressure, was used as the P precursor. At the growth temperature, the indium nanowires
turn to liquid but maintain their geometry due to the capping layer. In the presence of phosphine
and hydrogen, InP precipitates out of the In liquid, leading to an array of InP nanowires directly
grown on an Si/SiO2 substrate, as shown in Figure 4.1 (c).
Figures 4.2 (a) (i) through (v) are grayscale optical microscope images of different stages of TLP
InP growing in the Hall-bar geometry of length 100 m, width 5 m, and thickness 225 nm. Indium
(In) capped by silicon dioxide (SiO2) mesas in the shape of a bridge-type Hall specimen are first
obtained by lithography, evaporation and liftoff on thermal SiO 2 on Si carrier wafer, with 5 nm
molybdenum oxide (MoOx) as a thin interposing buffer layer. This is introduced to a single-zone
tube furnace, and heated to the growth temperature, when indium melts but retains the geometry
as-deposited. Group V precursor (phosphorus or arsenic) is then introduced in the respective
hydride gas phase (phosphine or arsine) diluted with hydrogen, and the flow rates are optimally
controlled to obtain slightly positive supersaturation, for the III-V material to precipitate as a single
nucleus in each mesa. Once the first nucleation event happens in a single connected pool of indium,
the balance between the rate of growth at that temperature and rate of nucleation determined by
group V flux and diffusion of the group V species in liquid group III metal, leads to the growth of
the first nucleation, and prevents another nucleation in the same mesa. Thus, with time, the entire
group III metal mesa is transformed to a III-V semiconductor mesa, retaining the same geometry
as patterned. Figure 4.2 (a) (i) is a representative mesa after 2 min of growth, where a small
nucleation event is seen, and with time the nucleus grows, until it fully grows the pattern as in
Figure 4.2 (a) (v).
Microstructural crystallographic orientation of individual Hall elements was obtained by electron
backscatter diffraction (EBSD) analysis. Figures 4.2 (b) (i) through (vi) are EBSD maps of

Figure 4.2: (a) (i)-(vi) Representative grayscale optical microscope (OM) images of different
stages of growth of single crystal TLP InP in a Hall element geometry. (b) (i) – (vi) Electron
backscatter diffraction (EBSD) maps of individual Hall elements indicating single
crystallinity.
51

different devices. It is seen that each device gives a single out-of-plane crystal orientation
(represented by a single color). Each device being represented by a single out-of-plane crystal
orientation gives direct experimental proof of them being individually of a single out-of-plane
crystal orientation.
4.2 TLP III-V Device Fabrication

The capping SiO2 layer on TLP grown InP FET channels was etched in 1:10 hydrofluoric
acid (HF, 48-50%) dissolved in water. Source-drain pads were then patterned using
photolithography. 6 nm Ge, 20 nm Au, and 80 nm Ni were electron-beam evaporated, followed by
lift-off. A 380
o
C rapid thermal annealing (RTA) was done to reduce contact resistance by Ge
alloying with InP at the source-drain contact regions. 60 nm of Al 2O3 was then deposited using
atomic layer deposition (ALD) as the gate dielectric. After that, gate electrodes were patterned
using photolithography, followed by 80 nm Ni electron-beam evaporation and lift-off. Source-
drain contact vias were then opened by photolithography and etching the Al 2O3 on the contact
pads. The device arrays on Si/SiO2 are thus fabricated, as shown schematically in Figure 4.1 (d).

Some specific details in the fabrication of the devices are shown by representative scanning
electron microscope (SEM) images in Figures 4.3 (a) through (g). Figure 4.3 (a) is an as-grown
device pattern, and Figure 4.3 (b) is a higher magnification image of the same showing extraneous
vapor-phase III-V growth nucleating along the sides of the SiO 2 capped TLP III-V mesa. These
“side-growths” may be considered as growth artifacts, and would adversely affect charge transport
by surface roughness scattering. Using a self-aligned etch process where the SiO 2 cap acts as an
etch mask, the vapor-phase InP is selectively etched using BCl 3-Cl2 plasma etching. SEM images
of a device after side-growth etching are shown in Figures 4.3 (c) and (d). The top oxide cap is
then etched away using either dilute hydrofluoric acid (50% HF:H 2O::1:10) or CHF3-Ar plasma to
yield the III-V Hall element on the SiO2 substrate, as represented in Figures 4.3 (e) and (f).

Figure 4.3: (a – b) Scanning electron microscope (SEM) image of as-grown pattern, (c – d)
SEM of pattern after selective side-growth etch, (e – f) SEM of pattern after top oxide cap
etch, (g) SEM of pattern after device fabrication, (h) Schematic of complete device.
52

Electrodes are then defined on the Hall bridge arms, using photolithography, metal evaporation
(Ni/Au) and liftoff, and annealed at 300
0
C to improve contact resistance. Figure 4.3 (g) is a
representative SEM image of a fully fabricated Hall element, while Figure 4.3 (h) is a schematic
representation of the device indicating the current injection and voltage measuring paths.
4.3 InP FET Characteristics

The output characteristics of a representative 2 × 4 array of devices are shown in Figure
4.4 (a-h), with an average extracted effective mobility of ~200 cm
2
/V-s at 3 V gate voltage
overdrive with peak effective mobilities of ~500 cm
2
/V-s. This is more than 10x higher than most
CNT network devices, which exhibit peak mobilities of ~5-20 cm
2
/V-s.
32, 33
The top row of devices
all have channel length of L=10 m, while the bottom row all have channel lengths of L=25 m.
Critically, we demonstrate the ability to deterministically place and grow devices on an amorphous
substrate with high device yield.

It may be noted that this mobility is limited by non-ohmic contacts at the source-drain, and charge
traps at the oxide-semiconductor interface. This is evident by the significant OFF-state current
difference between lower and higher source-drain voltages (Figure 4.5 (b)), as well as the
increasing field-effect mobility with increasing gate voltage (Figure 4.5 (d)). It may be noted
however, that the effective mobility stays approximately the same in the linear region of FET
operation, and reduces with higher gate overdrive due to surface roughness and interface scattering
(Figure 4.5 (c)).

Figure 4.4: Output characteristics of an array of transistors (a-d) of length 10 m, and (e-h) of
length 25 m, at Vgs=0,1,2,3 V. Reproduced with permission from [7]. Copyright 2018,
American Chemical Society.
53

4.4 InP and InAs Hall Mobilities

The electron mobility of the InAs and InP templated films was extracted from Hall effect over a
wide range of temperatures, from 2 to 300 K measurement using Physical Property Measurement
System (PPMS). The magnetic flux density was swept in logarithmic steps from 4 mT through
256 mT for positive and negative polarities. Injection current was set at 10 𝜇 A. The Hall effect
voltage was collected across the two voltage pads using lock-in amplifier to minimize
background noises signal. Substrate temperature was swept from 2 K to 400 K.
Raw data was symmetrized with the equation:
𝑉 =
1
2
(𝑉 − 𝑉 )
VH is the Hall effect voltage, Vpositive B and Vnegative B are the measured voltage under same
external magnetic field magnitude in opposite directions. The symmetrization treatment is a

Figure 4.5: (a) Output characteristics, (b) Transfer characteristics, (c) Effective mobility, (d)
Field Effect Mobility of a representative device.
54

common method for analyzing Hall effect measurement data to minimize the offset voltage
generated by geometrical imperfections of the Hall-effect structure, such as inhomogeneities of
material or mechanical distortions.
The current sensitivity SI of a Hall sensor biased with current I is given by:
𝑆 =
1
𝐼 𝑑𝑉 𝑑𝐵
Resistivity measurements were carried out by Van der Pauw technique. Two characteristic
resistances RA and RB were measured, and sheet resistance R s was achieved by solving Van der
Pauw equation:
𝑒 / + 𝑒 / = 1
Sheet resistance ns and mobility  can be calculated by the following equations:
𝑛 =
𝐼 ∙ 𝐵 𝑞 |𝑉 |

𝜇 =
|𝑉 |
𝑅 ∙ 𝐼 ∙ 𝐵 =
1
𝑞𝑛 𝑅
The mobility of a representative InAs Hall element is shown in Figures 4.6 (a). A peak
mobility of 5200 cm
2
/V-s is measured at 100 K, and the room temperature mobility is 3200 cm
2
/V-
s. The median mobility data points are fitted by a theoretically modeled curve considering ionized
impurity and phonon scattering as the primary modes of mobility limitation to obtain the
normalized lineshape. This is then scaled down to match the actual measured mobility values,
where this reduction factor is ascribed to surface roughness, interface traps, and twinning.
55

The sheet resistance and the sheet charge density are shown in Figure 4.6 (b). The shape of
the sheet resistance of InAs is also observed in epitaxial InAs by MBE in earlier reports. The
almost constant value of sheet charge density in InAs is ascribed to the presence of a surface
accumulation layer due to pinning of surface Fermi level above the conduction band.
TLP InP Hall mobility has been limited to about 200 cm
2
/V-s at room temperature (Figure
4.7 (a)), which is again ascribed to the non-optimized contact resistance as can be seen from the
temperature dependent sheet resistance measurement (Figure 4.7 (b)), where the resistance rises
with reduction in temperature, as may be expected in a Schottky contact.

Figure 4.6: (a) Mobility, (b) Sheet carrier density and sheet resistance of TLP InAs.

Figure 4.7: (a) Mobility, (b) Sheet carrier density and sheet resistance of TLP InP.
56

Chapter 5
Mimicking Biological Synaptic Functionality with an Indium
Phosphide Synaptic Device on Silicon for Scalable
Neuromorphic Computing
The information in this chapter is largely based on the peer-reviewed paper.
8

5.1 Introduction

The Arithmetic/Logic Unit (ALU) in any modern day Central Processing Unit (CPU) is
the fundamental building block responsible for accurate computation and logic operations. While
the requirement of accuracy and precision in computation is necessary for many applications, a
dramatic increase in the need to extract general relations from large sets of high-dimensional data
has driven the use of machine learning and multi-dimensional optimization algorithms in fields
such as computer vision, voice recognition, natural language processing, and autonomous systems.
To obtain useful results from these approaches, it is typically necessary to train the algorithms on
large clusters with large amounts of data, requiring hours, or even days for commercially relevant
applications. However, in this respect, the human brain supersedes any supercomputer, being six
to nine orders of magnitude more power efficient than today’s digital logic computers for these
types of applications. A unique feature of the human brain is the closely intertwined nature of the
memory and logic units which enables this efficient computing, unlike today’s computers where
the CPU and memory units though themselves being sufficiently fast, are largely restricted by data
transport among them, commonly referred to as the von Neumann architecture bottleneck. To this
end, researchers have started developing computing architectures that mimic the functioning of the
brain, referred to as neuromorphic computing. Neuromorphic computation is a leading candidate
for efficient, fault-tolerant processing of large-scale data, as well as real-time sensing and
transduction of complex multivariate systems and networks such as self-driving vehicles or
Internet of Things applications. While the exact functioning of the brain is an area of active
neuroscientific research, to a good approximation, it may be said that the neurons act as the logic
units operating in a three-dimensional multi-connected network supported by their end connections
called synapses, acting as the memory units.
34-37

Neural networks have been long studied and implemented in software
38
, and some
prototypes of hardware neuromorphic systems have already been built using existing CMOS
technology
39-45
. Neuronal spiking
46-48
and synaptic behavior
49-53
have been emulated using CMOS
based circuits containing 6 to 12 transistors depending on the specific functionality and robustness
of the design. But an omnipresent usage would require hardware implementation with reduced
footprint and energy consumption, and increased parallelism and interconnections, by several
orders of magnitude
37
. Architectures based on single device and novel materials to act as individual
57

units of the neuromorphic computing block are therefore heavily studied
34-36
. While there have
been fewer reports of neuronal behavior from single device
54, 55
, emulation of synaptic activity
from single device has been widely demonstrated, pioneered by Diorio et. al. in 1996 based on
hot-electron injection and electron tunneling in a floating-gate Si MOS transistor
56
. Memristor-
based synaptic devices from phase-change materials
57
, ferroelectricity
58, 59
, ferromagnetism
55
, and
nanoionics
60-73
have been demonstrated. Time dependent threshold voltage shift arising from
charging and discharging of traps in the semiconductor
74
, at the insulator-semiconductor
interface
75, 76
, or ion migration in the gate dielectric
77
in MOSFETs has more recently been utilized
for synaptic emulation.
However, due to the fundamental limitations on the growth of high-quality crystalline
material on amorphous materials, current 3-D approaches often use low-mobility solution
deposited materials, nanocrystalline channels, or physical transfer processes that are not scalable.
Here, we demonstrate a scalable, back-end compatible, artificial synapse with a crystalline Indium
phosphide (InP) channel grown directly on Si/SiO2 wafer with templated liquid phase growth
4-6,
78
. We show these synaptic devices emulate a range of behaviors such as elasticity, short-term and
long-term plasticity, metaplasticity, and spike timing dependent plasticity.

5.2 Biological Synapse

A synapse
79
is a 20-40 nm junction between two neurons (schematically shown in Figure
5.1 (a)) which aids in the communication of signals between neurons. These connections are not
hard-coded but evolve over time, and are plastic, depending on the activity of the connecting
neurons. Based on the nature of pre- and post-synaptic activity, the synaptic weight may remain
unchanged (elasticity), increase (potentiation), or decrease (depression). The change in the
synaptic connectivity (also called synaptic plasticity) is regarded as a key ingredient in learning
and memory. Synaptic plasticity leads to future data processing along the same pathway to be
accordingly affected: a potentiated synapse would enable better transduction of information from
pre-synaptic action potentials, and a depressed synapse would lead to a constrained transduction
of information. The difference in post synaptic current (PSC) determines the synaptic weight
change that occurred owing to the coupling neuronal activity. The synaptic weight change is also
time dependent, with a gradual decay over time. Based on the lifetime of the plasticity, two
categories of plasticity are defined: short-term plasticity and long-term plasticity. While the exact
times scales defining each is not precisely defined, short-term plasticity often refers to behavior
on the milliseconds to seconds time frame, while long-term plasticity refers to behavior on the
time frame of seconds to years.

58

5.3 InP-Al2O3 Artificial Synaptic Device
The device architecture used in this work to emulate the synaptic behavior, is schematically
shown in Figure 5.2. The device is a top-gated 100 nm thick InP nanowire transistor fabricated on
Si/SiO2 wafer with 60 nm Al2O3 as the gate dielectric. The Al2O3-InP stack may be regarded as
the synapse connecting the cell membrane of the pre-synaptic neuron (gate electrode) to the cell
membrane of the post-synaptic neuron (drain electrode).
Pre-synaptic action potentials are applied as pulses to the gate electrode, which leads to a post-
synaptic current (PSC) in the drain electrode based on the strength of the synapse. The synaptic
strength is the conductance of the semiconductor channel. Application of a voltage pulse on the
gate leads to charging or discharging of traps in the oxide or at the oxide/semiconductor interface
76
.
This in turn changes the electrostatics of the channel and leads to a shift in the threshold voltage,
so that the drain current (PSC) at the same constant gate voltage before and after the gate voltage
pulse, may be different. The magnitude of the hysteresis depends on the pulse amplitude and width.
The amplitude determines the electric field within the oxide, and the population of charge carriers
in the semiconductor, with higher amplitudes accessing higher energy traps. The pulse width
determines the length of time under which the oxide is under tension, changing the number of traps

Figure 5.1: Schematic of a biological synapse showing communication of signal between
neurons by release of neurotransmitters from the pre-synaptic neuron causing diffusion of
Na
+
ions into the post-synaptic neuron. Reproduced with permission from [7]. Copyright
2018, American Chemical Society.
59

that are charged or discharged. The synaptic strength evolves as a function of the nature of the
pulse and the strength of the synapse before the application of the pulse.

5.4 Spike Amplitude Dependent Plasticity
The effect of amplitude of gate pulse in changing the electrostatics of the channel and thus
the behavior of the artificial synapse, is shown in Figure 5.3. We interpret the amplitude of gate
pulses to be proportional to the probability of exocytosis for neurotransmitter release
76
. Thus, a
higher amplitude pulse signifies higher probability of release of neurotransmitters than that of a
lower amplitude pulse. Physically, a higher gate voltage pulse causes higher energy traps to be
accessed. Figures 5.3 (a) and (b) show the transfer characteristics of the synaptic device for
different peak gate voltages (5 V and 0.7 V respectively), starting from 0 V. It is found that a peak

Figure 5.2: Schematic of the indium phosphide channel field effect transistor on silicon as the
synaptic device, where a voltage spike in the pre-synaptic neuron terminal (gate) results in a
change in the current in the post-synaptic terminal (drain) based on the synaptic dynamics
(oxide-semiconductor charge traps). Reproduced with permission from [7]. Copyright 2018,
American Chemical Society.
60

gate voltage of +5 V increases the threshold voltage, lowering Ids (Figure 3 (a)), while a peak gate
voltage of -5 V decreases the threshold voltage, increasing Ids. From this, we show that positive
gate voltage pulses lead to depression, a reduction in the PSC, while negative voltage pulses lead
to potentiation. However, as shown in Figure 5.3 (b), it is seen that a peak voltage of +0.7 V has
nearly no effect on the PSC, leading to elastic behavior of the synapses, where a pulse is passed
however no synaptic weight change occurs. To show the dynamics of the synapse, representative
post-synaptic current (PSC) curves are plotted in Figure 5.3 (c). The current for 𝑡 < 0 is the PSC
before arrival of the spikes, for 𝑡 > 0 is the PSC after arrival of the spikes, and the dotted line
indicates the time of spike arrival. Here, we use a rectangular pulse train of 40 pulses of width 500
s, and 50% duty cycle with 0 V baseline. The three behaviors were obtained by the application
of pulses with varying amplitudes. A pulse amplitude of 0.1 V results in elasticity, -5 V gives
potentiation and +5 V gives depression. We also plot the synaptic weight change for different peak
pre-synaptic potentials in Figure 5.3 (d). We define the short-term plasticity (STP) as the difference
between the average PSC over the first 1 s after pulse, and that before pulse, normalized to the
PSC before pulse. The long-term plasticity (LTP) is defined as the difference between the
normalized average PSC between 10 s and 40 s after pulse, and that before pulse. The magnitude
of plasticity increases with increasing voltage amplitude, and can be modeled with exponential
functions of the form,
∆𝑤 = 𝐴 ∗ 𝑒
where 𝑉 is the peak gate voltage, and 𝑉 is the activation voltage for the traps. The physical
implication of a non-zero plasticity is that a future signal would be transduced with the modified
weight of the synapse. This leads to selectivity of pathways for transduction of a signal to converge
to an optimal solution in a neural network.
61

5.5 Metaplasticity
It may be noted that the synaptic weight change at time t is actually a function of the
synaptic weight at t and the neuronal activity at that time
80
. Mathematically, it may be represented
as
∆𝑤 = 𝑓 (𝑤 , 𝜃 ),
where 𝑤 is the synaptic weight and 𝜃 is the neuronal activity at time 𝑡 .

Figure 5.3: (a) Hysteretic transfer characteristics showing depression for +5 V and
potentiation for -5 V. (b) Hysteretic transfer characteristics showing elasticity for +0.7 V and
potentiation for -0.7 V. (c) Transient post-synaptic current before and after application of pre-
synaptic pulse leading to elasticity (0.1 V), potentiation (-5V), and depression (+5V). (d)
Short-term and long-term synaptic weight change for different values of pre-synaptic voltage
pulse. (All curves reported with Vds = 3 V). Reproduced with permission from [7]. Copyright
2018, American Chemical Society.
62

Thus, for the same neuronal activity, the synaptic weight change would depend on the initial
condition of the synapse. In other words, for the same gate voltage pulse(s), the change in the drain
current (arising from the change in the electrostatics of the channel) would depend on the initial
electrostatic condition of the channel and the threshold voltage of the device
70, 72
. This
phenomenon is referred to as metaplasticity and is one of the most important characteristics of
biological synapses. It allows a highly non-linear optimization of the synaptic weight based on the
sequence of signals it transduces, to in turn give rise to an optimal selectivity of the signals being
transduced. Metaplasticity of our synaptic device was emulated by applying the same gate voltage
pulse but preceded by different “priming” gate voltage pulses to emulate prior brain activity. The
gate voltage pulse trains consisted of 10 pulses of 5 ms width and 6 ms period. As a demonstration,
we chose +2.5 V pulse as a depressing priming pulse, and -2.5 V pulse as a potentiating priming
pulse. The PSC plots for two representative potentiating and depressing cases are depicted in
Figures 5.4 (a) and (b). The same -4.5 V pulse train gives a significantly higher relative change of
PSC when it follows depressing priming, than when it succeeds a potentiating priming. Similarly,
a depressing priming allows a less depression for a +4.5 V pulse train than a potentiating priming.
Figure 5.4 (c) shows the short-term synaptic weight change extracted from the PSCs for gate
voltages ranging between -5 V to +5 V, for three different initial conditions of no priming,
depressing priming, and potentiating priming. It is observed that a reduction in potentiation weight
change occurs for an initially potentiated synapse, while an increased potentiation occurs for an
initially depressed synapse. Similarly, an initially depressed synapse leads to having less
depression than an initially potentiated synapse. As may be realized, the unique feedback
mechanism embedded in metaplasticity allows the synapse to optimally tune its weight such that
it regressively stays within bounds instead of diverging towards either extreme.
63

5.6 Spike Number Dependent Plasticity
For the same initial state of the synapse, the synaptic weight change is also dependent on
the number of neurotransmitters being transmitted simultaneously
76
. The number of
neurotransmitters is in turn, dependent on the number of action potentials that have reached the
pre-synaptic terminal in quick succession (each action potential typically releasing same number
of neurotransmitters). To emulate the pulse number dependent plasticity of synapses, we excite the
synaptic device with +5 V peak (for depression) or -5 V peak (for potentiation) and 0 V baseline
pulse trains of 5 ms width and 5.5 ms period, consisting of varying number of pulses, the results
of which are shown in Figure 5.5. Some representative potentiation and depression curves (for
pulse trains consisting of 1, 20, and 100 pulses) are plotted in Figure 5.5 (a). A general trend of
increased potentiation or depression is observed as we increase the number of incident action
potentials. The PSC in each case was fitted with a double exponential function
62
given by:
𝑃𝑆𝐶 = 𝐼 + 0.5 ∗ (𝐼 − 𝐼 ) ∗ (𝑒 / + 𝑒 / )
The PSC approaches the steady state value 𝐼 from 𝐼 at a rate given by the double exponentials:
one of them is used to fit the very fast decay right after the pulse, while the other gives the relatively
slower decay rate until the PSC virtually reaches the steady-state value. The PSC decay time
constant (inverse of the slower decay rate), referred to in the graph as the synaptic relaxation time

Figure 5.4: Synaptic metaplasticity. (a) Increased potentiation of synapse succeeding a
depressing priming compared to potentiating priming. (b) Increased depression of synapse
succeeding a potentiating priming compared to depressing priming. (c) Short-term synaptic
weight change for different values of pre-synaptic voltage pulse without priming, and with
depressing and potentiating priming. (All curves reported with V ds = 3 V). Reproduced with
permission from [7]. Copyright 2018, American Chemical Society.
64

constant, is plotted in Figure 5.5 (b). It is also seen that the relaxation rate initially decreases and
gradually saturates with increase in the number of action potentials stimulating the synapse.

Figure 5.5 (c) and (d) respectively show the long-term and short-term synaptic weight change,
where the weight change definitions have been as done earlier. As expected, a gradual increase in
the plasticity of the synapse is observed with increasing number of action potentials, as more
number of traps are populated, until gradually all or most of the traps that can be affected by the
pulse amplitude, are influenced, so that the plasticity gradually saturates. The same reasoning may
be applied for the trend observed for the relaxation rate as well. Considering that faster traps are
populated earlier than slower traps, with increasing number of pulses we gradually excite higher
number of slower traps, increasing the decay time constant.

Figure 5.5: Spike Number Dependent Plasticity. (a) Transient post-synaptic current before
and after application of pre-synaptic pulse for varying pulse number, n AP=1, 20, 100. (b)
Variation of short-term synaptic relaxation time constant with different number of action
potentials. (c) Long-term, and (d) short-term synaptic weight change for different number of
potentiating and depressing action potentials. (All curves reported with V ds = 3 V).
Reproduced with permission from [7]. Copyright 2018, American Chemical Society.
65

5.6 Spike Timing Dependent Plasticity
Once an action potential is generated in the post-synaptic neuron, it travels down the length
of the axon. However, a fraction of this signal is reflected and impinges on the output terminal of
the synapse, potentially changing the synaptic strength. Synaptic modification arising from the
correlated activity of the pre-synaptic and post-synaptic neuron was first introduced by Hebb
81
in
1949, and later refined by other researchers such as Bienenstock-Cooper-Munro
82
in 1982. One of
the most well-known versions of Hebbian (or BCM) learning is spike timing dependent plasticity
(STDP), some of the first demonstrations of which were in classic neuroscience experiments such
as by Markram et. al.
83
, Bi and Poo
84
, and modeled by van Rossum et. al.
85
. STDP has been
emulated by the neuromorphic device community over the years, mostly based on memristor
technology. However, STDP in MOSFET based synapses has not clearly been demonstrated using
solely time-correlated activity of the pre- and post-synaptic neuron. Instead, due to the nature of
the pulse waveforms used and the behavior of MOSFETs, it is necessary to use differing pulses
for depression and potentiation, which would require external circuitry to enable learning.
While many different STDP behaviors exist, a commonly implemented STDP behavior is the
potentiation of the synapse when the post-synaptic action potential succeeds the reflected pre-
synaptic action potential, and depression when the reflected post-synaptic action potential precedes
the pre-synaptic action potential. The highest magnitude of potentiation and depression occurs for
the shortest time gap ( t) between the pre- and post-synaptic action potentials, and the synapse
tends to stay elastic for increasing time spacing between the pre- and post-synaptic action
potentials. Such an asymmetric and time-correlated behavior may well be reasoned based on
causality principles. Here we utilize engineering of hysteresis in a family of transfer characteristics
to demonstrate STDP in our synaptic device. The pre-synaptic action potential is designed as a
pulse that goes from 0 to +2.75 V to -5 V to 0 V with a total width of 10 ms. The reflected post-
synaptic action potential is designed as a pulse with a baseline of 1.5 V, ramping up to 2.1 V in
100 ms, ramping down to 0.9 V in 20 ms, and again ramping up to 1.5 V in 100 ms. The peak
values of the pre-synaptic potential were chosen such that it results in elasticity at the 1.5 V
baseline post-synaptic potential (Figure 5.6 (b)), which is the boundary condition for high | t|. For
post-synaptic potentials less than 1.5 V, the same pre-synaptic pulse gives depression, with
increasing plasticity for lower potentials (representative hysteresis shown in Figure 5.6 (a)). For
post-synaptic potentials greater than 1.5 V, the pre-synaptic pulse gives potentiation, with
increasing plasticity for higher potentials (representative hysteresis shown in Figure 5.6 (c)).

66

This effect has been utilized to accordingly design the shape of the post-synaptic potential. The
ramp times have been chosen to closely match that found in STDP of typical synapses. The upper
panel of Figure 5.7 (a) shows the waveform simulating the reflected post-synaptic action potential,
while the lower panel depicts the pre-synaptic pulse. The relative positioning of the two pulses can
be directly interpreted as positive and negative t as has been shown in Figure 5.7 (a). The long-
term synaptic weight change for different t was calculated, and has been plotted in Figure 5.7 (b).
It is seen that as expected from the waveform design, we get maximum potentiation (depression)
for the minimum positive (negative) t, which gradually decays down to give elasticity for longer
time intervals. It may also be noted that other different STDP behaviors such as those demonstrated
by Kuzum et al.
57
, may also be easily reproduced in our synaptic device by only changing the post-
synaptic potentials, for the same pre-synaptic potential as used here.

Figure 5.6: Hysteresis engineering in a family of transfer characteristics for V gs= 0 to +5V to
-1 V to 0 V showing (a) depression for V ds=0.1 V, (b) elasticity for Vds=1.5 V, (c)
potentiation for Vds=3 V. Reproduced with permission from [7]. Copyright 2018, American
Chemical Society.
67

Figure 5.7: Spike Timing Dependent Plasticity. (a) Waveforms representing back-reflected
post-synaptic action potential (upper row) and pre-synaptic action potential (lower row) for
pre-synaptic action potential preceding (left column) and succeeding (right column) the
reflected post-synaptic action potential. (b) Long-term synaptic weight change for different
values of time offset between the pre- and post-synaptic action potentials. Reproduced with
permission from [7]. Copyright 2018, American Chemical Society.
68

Chapter 6
Epitaxial Growth Process Integration on Non-epitaxial
Substrate
Having looked at the intrinsic crystal properties of the TLP grown materials, here we take
a peek at some of our efforts in using these single crystal mesas as the seed layers for further
growth by traditional epitaxial methods like MOCVD. Being successful in being able to do so,
would allow us to leverage the vast advancement and high-performance devices developed over
the last several decades, to be translated on orders of magnitude cheaper substrates, and potentially
also back-end of CMOS.
Figures 6.1 (a-b) show representative TLP mesas, and Figures 6.1 (c-d) are that of mesas after
MOCVD growth. From the uniformly faceted texture that comes up, it is further obvious that the
underlying TLP mesa is indeed single crystal. Also, this is selective so that there isn’t growth in
the surrounding dielectric substrate. The microscale roughness that is seen, arises from different
rates of growth of the adjacent nuclei.

Although the previous figure highlighted only the final steps of the process, it is important to talk
about the full process too, where the side-etching once again plays an important role. Specifically,
we start with growing by TLP method, etch the sides selectively, then etch the capping layer, and
finally perform the MOCVD growth (Figure 6.2).

Figure 6.1: Representative SEM of selective MOCVD growth on TLP seeds.
69

Because if we don’t do the side etch, then MOCVD would nucleate from those as well, giving rise
to uncontrollable morphology and unpredictable final structure (Figure 6.3).

Figures 6.4 (a-b) are images of some partially optimized growth conditions to give InP MOCVD
growth on an InP TLP stripe, and Figures 6.4 (c-d) are that of MOCVD InGaAs growth on an
InP TLP circle.

Figure 6.2: SEM images depicting complete sequence of integrating epitaxially grown
materials (MOCVD growth) on amorphous substrate.

Figure 6.3: SEM images showing uncontrollable morphological growth due to presence of
side-growth.
70

Figure 6.4: SEM images showing MOCVD growth (a-b) InP on InP and (c-d) InGaAs on InP
TLP mesas.
71

Chapter 7
300
o
C Growth of Single Crystal InP for

CMOS Back-end-of-
line Devices
The information in this chapter has been submitted for a peer-reviewed publication.
The previous works of TLP have mainly focused on high processing temperatures, with a
typical optimal region of operation being around 550
0
C. Here, we explore the possibility of
extending the TLP growth to lower temperatures, specifically below 400
0
C to test the viability of
potential back-end-of-line (BEOL) integration. We present a reactor configuration for obtaining
low temperature – templated liquid phase (LT-TLP) grown compound semiconductor films, and
establish an optimal temperature scheme to obtain high optoelectronic quality semiconductor
growth by scanning through growth conditions. Electron backscatter diffraction (EBSD) patterns
corroborate our claims of obtaining single crystal templates in the micron scale at these low
temperatures. Using the LT-TLP approach, we directly grow an InP nanoribbon on HfO 2 at 300
0
C, and fabricate a long channel field effect transistor with all associated device fabrication steps
within a thermal budget of 300
0
C.

7.1 Overview of LT-TLP growth process

The low temperature – templated liquid phase (LT-TLP) growth for InP is
schematically illustrated in Figure 7.1 (a). The substrate is an amorphous dielectric layer: thermal
SiO2 on a Si carrier wafer, or atomic layer deposited HfO 2, ZrO2 or Al2O3 on top of the thermal
SiO2. Substrates are cleaned with acetone, isopropyl alcohol and deionized water, blow-dried with
dry nitrogen, and thereafter an O2 plasma ashing was performed. Desired templates are then
patterned by photolithography or electron-beam lithography, depending on the intended areal
dimension. Samples are mounted on a cryo-cooled (liquid nitrogen) stage, and indium
(99.99995%) is thermally evaporated using an alumina covered tungsten boat at rates of 0.5 – 1
Å/sec. The areal dimension of the patterns range from 100 nm to 10 m (in one direction). The
thickness of evaporated indium varied between 75 to 750 nm as required by the lateral mesa
dimension and substrate based on the thermodynamically controlled geometric wetting model. A
capping layer of 120-300 nm SiO2 is evaporated by electron-beam using SiO2 pellets (99.99%
pure, Kurt J Lesker or 99.999% pure, LTS Research Laboratories). Lift-off procedure in suitable
resist stripper, resulted in templates of In/SiO2 on the substrate. 1 cm squared chips of these In-
SiO2 mesas on the substrate are introduced to a CVD furnace and heated to the growth temperature
(optimal window of 280-320
0
C). Phosphorus is introduced in the gas phase through phosphine
pre-cracked at a higher pyrolysis temperature (600-700
0
C). 100% PH3 (99.9995%, Matheson) was
used as the P precursor, diluted with 99.999% H2 to achieve the desired PH3 partial pressure. The
phosphorus flux is controlled such that there is just enough supersaturation for InP to precipitate
72

as a single nucleus in each template, and grow with time as a single crystal. Thus, elemental In
transforms to InP in the same geometry as the original In template. Figures 7.1 (b) (i) through (vi)
are grayscale optical microscope images representing different stages of LT-TLP InP growth in a
stripe geometry of dimensions 1 m x 10 m. Figure 7.1 (b) (vii) is the same InP stripe as in Figure
7.1 (b) (vi), after selective etching of the vapor-phase InP side growth and top cap etch, keeping
the LT-TLP InP intact. Figures 7.1 (c) (i) through (vi) are optical microscope images representing
different stages on LT-TLP InP growth in a 10 m diameter circle.

Figure 7.1: Overview of LT-TLP growth of crystalline compound semiconductors. (a)
Schematic of the LT-TLP growth process. (b) (i)-(vi) Representative grayscale optical
microscope (OM) images of different stages of growth of single crystal LT-TLP InP in a 1
m x 10 m stripe. (b) (vii) Representative grayscale OM image of LT-TLP InP stripe after
side and top cap etching. (c) (i)-(vi) Representative optical microscope (OM) images of
different stages of growth of single crystal LT-TLP InP in a 10 m diameter circle.
73

Figure 7.2 shows InAs grown by the LT-TLP process, with similar procedure but with
arsine as the precursor.

Differences in reactor configuration for high temperature and low temperature TLP
growths are schematically shown in Figure 7.3. High temperature TLP was typically done in a
single-zone hot-wall tube furnace (Lindberg Blue) under furnace temperature ranging between 450
to 650
0
C (optimal temperatures ~550
0
C), as depicted in Figure 7.3 (a). Figure 7.3 (b) shows the
configuration for LT-TLP growth. It was typically done in a dual-zone hot-wall tube furnace (MTI
Corporation), with the two zones independently operated at two different temperatures. The first
zone was used as a cracking furnace with temperatures 600-800
0
C (optimal temperature ~700
0
C),
while the second zone was used as the growth zone with temperatures 200-400
0
C (optimal
temperature ~300
0
C).

Figure 7.3: Schematic of reactor configuration for (a) high temperature, and (b) low
temperature TLP.

Figure 7.2: Representative images of LT-TLP grown InAs stripes.
74

7.2 Single Crystallinity of LT-TLP InP

Electron backscatter diffraction (EBSD) was performed on individual LT-TLP InP stripes
to get the microstructural crystallographic orientation. Grayscale optical microscope image of a
representative 10 m long and 1 m wide InP stripe is shown in Figure 7.4 (a). Kikuchi patterns
were obtained from different positions along the stripe, some representatives of which are shown
in Figure 7.4 (a) (i) through (iv). Similar Kikuchi patterns from different locations indicate that the
entire stripe is indeed a single crystal. Figure 7.4 (b) is an EBSD map of eight of these stripes. A
single color in each stripe representing the out-of-plane crystal orientation further corroborates the
single crystallinity of each stripe, while the array shows a representative distribution of the
orientations that occur by this method.

7.3 Optoelectronic Quality Optimization of LT-TLP InP

Low temperature – templated liquid phase (LT-TLP) growth of InP was carried out at
different growth temperatures, and characterized by micro-photoluminescence. Representative
photoluminescence spectra of InP grown at 300
0
C,

350
0
C and 500
0
C are shown in Figure 7.5 (a)
through (c), and compared with that of a commercial single crystal InP wafer used as a reference.
Normalized intensity curves are plotted in the main panel of each, while the log-scale plot
comparing the actual intensities under similar excitation conditions are shown in the inset. It may
be observed that the peak position for LT-TLP InP at 350
0
C is significantly blue-shifted, and the
FWHM and Urbach parameters are also much higher. This unintentional “doping-like” behavior

Figure 7.4: Single crystallinity of LT-TLP InP. (a) Grayscale OM image of an LT-TLP InP
stripe, and (a) (i)-(iv) Representative EBSD Kikuchi patterns from different regions of the
same stripe indicating single crystallinity across entire stripe. (b) EBSD orientation map of
eight different LT-TLP InP stripes.
75

most likely arises from point defects acting as donor states to the conduction band. The defect
density at 550
0
C is arguably comparable to that of the commercial wafer, indicated by similar
FWHM and Urbach parameters. The peak position, full width at half maximum, and Urbach
parameter of the 300
0
C InP are similar to that of the wafer, indicating excellent optoelectronic
quality and comparable defect density at the optimal LT-TLP growth conditions. Notably, the
external quantum efficiency is of the same order of magnitude of the InP wafer, and may be further
improved by post-growth passivation and smoothening of the surface.

The optimization of LT-TLP growth conditions was carried out by extracting photoluminescence
parameters, such as peak position, full width at half maximum (FWHM), and Urbach parameter
from a statistical set of measurements of the samples grown at different temperatures (200 – 400
0
C), and comparing those from single crystal InP wafer as a reference. These are plotted in Figure
7.6 (a) through (d) along with our previously published data from growths at higher temperatures
9
.
The optoelectronic quality decreases with decreasing temperature until 350
0
C. However, below
that, the quality dramatically improves, and an optimal growth temperature window exists in 280-
320
0
C. In this region, the mean values of the photoluminescence parameters are closest to that of
the reference wafer, and the spread of values (for example indicated by standard deviation of the
FWHM in Figure 7.6 (d)) is also the minimum. It would be interesting to understand the reason
behind this behavior, and the present hypothesis is that it is linked to the differences in reaction
mechanisms between the decomposition products of phosphine with indium at the different growth
temperatures.

Figure 7.5: Representative photoluminescence spectra of TLP InP grown at (d) 300
0
C, (e)
350
0
C, and (f) 550
0
C, compared with that of commercial InP wafer. [Main panel:
Normalized intensity curves. Inset: Log-scale plot comparing the actual intensities under
similar excitation conditions.]
76

7.4 InP Nanoribbon FET Fabrication and Device Characteristics

Using standard microfabrication techniques, these single crystal stripes were used to
fabricate field effect transistors (FET) also within a maximum processing temperature of 300
0
C.
Source and drain electrodes are patterned using photolithography, and 100nm Ni/5nm Au are
evaporated by electron-beam with planetary rotation to efficiently contact the InP sides. After
liftoff, the chip is annealed in vacuum at 300
0
C for 45 min. 60nm Al2O3 is then blanket deposited
by ALD at a deposition temperature of 200
0
C. Gate electrode is defined on top, using
photolithography, metal evaporation and liftoff. Vias are opened on the source-drain electrodes by
selectively etching the Al 2O3. Highlighted steps of this procedure are shown in Figure 7.7.

Figure 7.6: LT-TLP InP growth condition optimization by photoluminescence
characterization. Box-and-whisker plot of (a) Peak position, (b) Full width at half maximum
(FWHM), and (c) Urbach parameter of TLP InP grown at different temperatures. (d)
Standard deviation of FWHM TLP InP grown at different temperatures. [Data at
temperatures 450
0
C, 540
0
C, 650
0
C, and 750
0
C reprinted with permission from [9].
Copyright 2018, American Vacuum Society]
77

It may be highlighted that utilizing the deterministic nature of the TLP growth process to obtain
single crystal mesas in the geometry and location determined by lithography, batch processing of
FET can be done, so that an array of devices can be fabricated simultaneously on the same chip.
Figure 7.8 (a) shows a single fully fabricated device, while Figure 7.8 (b) is the zoomed in view
of the active region. The output and transfer characteristics of a representative LT-TLP InP FET
are plotted in Figure 7.8 (c) and (d) respectively. The on-state saturation current is 1 A/ m,
fundamentally limited by Schottky barrier at the source-drain contacts, and not by the intrinsic
material quality. This is evident by the output curves which show a linear increase with gate
voltage followed by saturation and not a square law, indicating significant series resistance. Also,
the transfer curves show a noticeable offset in the sub-threshold state between that at low and at
high drain voltages. Importantly, an ON-OFF ratio of 4 orders of magnitude with off-state
saturation current of 100 pA/ m is observed, indicating good material quality despite a metal
semiconductor Schottky drain junction. The subthreshold slope is 200 mV/dec, which could be
improved in the future by using thinner gate dielectrics and surface treatments.

Figure 7.7: Schematic of BEOL compatible LT-TLP InP nanoribbon FET fabrication.
78

7.5 LT-TLP InAs Hall Mobility

As can be seen in Figure 7.9 (a), LT-TLP InAs gives very high mobility of about 6000
cm
2
/V-s at room temperature, and a fairly constant sheet carrier density of 1.5e13 cm
-2
(Figure 7.9
(b)). Translated to a volume density, this would give 5e17 cm
-3
. However, as evident from the
independence of temperature, this behavior is a direct indication of the surface Fermi level pinning
above the conduction band minimum, leading to a formation of accumulation layer of high charge
density near the surface.

Figure 7.8: CMOS BEOL compatible FET fabrication. (a) SEM of a single device. (c) High
magnification SEM of the active region of a device. (d) Output, and (e) Transfer
characteristics of an LT-TLP InP FET.
79

7.6 Conclusion

Single crystal compound semiconductor mesas are grown directly on amorphous substrates
at temperatures below 400
0
C, using the technique introduced here as low temperature – templated
liquid phase (LT-TLP) growth. An optimal growth condition giving high-quality optoelectronic
properties with external quantum efficiency comparable to that of commercial InP wafer, was
obtained by thorough characterization and analysis of the growths done at different temperatures.
Finally, device performance of an LT-TLP InP FET is presented, having switching ratio over 10
4

and low off-state current, indicating good material quality. In summary, this letter establishes the
groundwork for a potential CMOS back-end-of-line integrable electronic and optoelectronic
device fabrication by direct growth of single crystals at deterministic location and geometry on
interlayer dielectrics.

Figure 7.9: (a) Electron mobility, (b) Sheet carrier density of LT-InAs.
80

References
1. Moore, G. E. IEEE solid-state circuits society newsletter 2006, 11, (3), 33-35.
2. Ko, H.; Takei, K.; Kapadia, R.; Chuang, S.; Fang, H.; Leu, P. W.; Ganapathi, K.; Plis, E.;
Kim, H. S.; Chen, S.-Y.; Madsen, M.; Ford, A. C.; Chueh, Y.-L.; Krishna, S.; Salahuddin, S.;
Javey, A. Nature 2010, 468, (7321), 286-289.
3. Zheng, M.; Yu, Z.; Joon Seok, T.; Chen, Y.-Z.; Kapadia, R.; Takei, K.; Aloni, S.; Ager, J.
W.; Wu, M.; Chueh, Y.-L. Journal of Applied Physics 2012, 111, (12), 123112.
4. Kapadia, R.; Yu, Z.; Wang, H.-H. H.; Zheng, M.; Battaglia, C.; Hettick, M.; Kiriya, D.;
Takei, K.; Lobaccaro, P.; Beeman, J. W. Scientific reports 2013, 3, srep02275.
5. Kapadia, R.; Yu, Z.; Hettick, M.; Xu, J.; Zheng, M. S.; Chen, C.-Y.; Balan, A. D.;
Chrzan, D. C.; Javey, A. Chemistry of Materials 2014, 26, (3), 1340-1344.
6. Chen, K.; Kapadia, R.; Harker, A.; Desai, S.; Kang, J. S.; Chuang, S.; Tosun, M.; Sutter-
Fella, C. M.; Tsang, M.; Zeng, Y. Nature communications 2016, 7, 10502.
7. Sarkar, D.; Wang, W.; Mecklenburg, M.; Clough, A. J.; Yeung, M.; Ren, C.; Lin, Q.;
Blankemeier, L.; Niu, S.; Zhao, H. ACS nano 2018.
8. Sarkar, D.; Tao, J.; Wang, W.; Lin, Q.; Yeung, M.; Ren, C.; Kapadia, R. ACS Nano 2018,
12, (2), 1656-1663.
9. Sarkar, D.; Wang, W.; Lin, Q.; Tao, J.; Mecklenburg, M.; Ravichandran, J.; Kapadia, R.
Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials,
Processing, Measurement, and Phenomena 2018, 36, (3), 031204.
10. Tyson, W. R.; Miller, W. A. Surface Science 1977, 62, (1), 267-276.
11. Yu, H. K.; Lee, J.-L. Scientific reports 2014, 4.
12. Kato, T.; Matsumoto, T.; Ogura, H. Japanese journal of applied physics 1990, 29, (6A),
L856.
13. Hakki, B. W.; Jayaraman, A.; Kim, C. K. Journal of Applied Physics 1970, 41, (13),
5291-5296.
14. Kato, T.; Matsumoto, T.; Ishida, T. Japanese journal of applied physics 1988, 27, (6R),
983.
15. Ritscher, A.; Schmetterer, C.; Ipser, H. Monatshefte für Chemie-Chemical Monthly 2012,
143, (12), 1593-1602.
16. Tallapally, V.; Esteves, R. J. A.; Nahar, L.; Arachchige, I. U. Chemistry of Materials
2016, 28, (15), 5406-5414.
17. Lan, D.; Wang, W.; Shi, L.; Huang, Y.; Hu, L.; Li, Q. Journal of Materials Chemistry A
2017, 5, (12), 5791-5796.
18. Kim, Y.; Hwang, H.; Yoon, C. S.; Kim, M. G.; Cho, J. Advanced Materials 2007, 19, (1),
92-96.
19. Aso, K.; Kitaura, H.; Hayashi, A.; Tatsumisago, M. Journal of the Ceramic Society of
Japan 2010, 118, (1379), 620-622.
81

20. Zaikina, J. V.; Kovnir, K. A.; Sobolev, A. N.; Presniakov, I. A.; Kytin, V. G.;
Kulbachinskii, V. A.; Olenev, A. V.; Lebedev, O. I.; Tendeloo, G. V.; Dikarev, E. V. Chemistry
of Materials 2008, 20, (7), 2476-2483.
21. Ganesan, R.; Richter, K. W.; Schmetterer, C.; Effenberger, H.; Ipser, H. Chemistry of
Materials 2009, 21, (18), 4108-4110.
22. Olofsson, O. Acta Chem Scand 1970, 24, (4), 1153-1162.
23. Gullman, J. Journal of solid state chemistry 1990, 87, (1), 202-207.
24. In-P-Sn Vertical Section of Ternary Phase Diagram: Datasheet from "PAULING FILE
Multinaries Edition – 2012" in SpringerMaterials (http://materials.springer.com/isp/phase-
diagram/docs/c_1401076), Springer-Verlag Berlin Heidelberg & Material Phases Data System
(MPDS), Switzerland & National Institute for Materials Science (NIMS), Japan.
25. Panish, M. B. Journal of Crystal Growth 1974, 27, 6-20.
26. Urbach, F. Physical Review 1953, 92, (5), 1324.
27. Van Roosbroeck, W.; Shockley, W. Physical Review 1954, 94, (6), 1558.
28. Kost, A.; Lee, H. C.; Zou, Y.; Dapkus, P. D.; Garmire, E. Applied physics letters 1989,
54, (14), 1356-1358.
29. Miller, O. D.; Yablonovitch, E.; Kurtz, S. R. IEEE Journal of Photovoltaics 2012, 2, (3),
303-311.
30. Bennett, B. R.; Soref, R. A.; Del Alamo, J. A. IEEE Journal of Quantum Electronics
1990, 26, (1), 113-122.
31. Liu, C.; Dai, L.; You, L. P.; Xu, W. J.; Qin, G. G. Nanotechnology 2008, 19, (46),
465203.
32. Cao, C.; Andrews, J. B.; Kumar, A.; Franklin, A. D. ACS nano 2016, 10, (5), 5221-5229.
33. Chen, K.; Gao, W.; Emaminejad, S.; Kiriya, D.; Ota, H.; Nyein, H. Y. Y.; Takei, K.;
Javey, A. Advanced Materials 2016, 28, (22), 4397-4414.
34. Kuzum, D.; Yu, S.; Wong, H. S. P. Nanotechnology 2013, 24, (38), 382001.
35. Jeong, D. S.; Kim, I.; Ziegler, M.; Kohlstedt, H. RSC Advances 2013, 3, (10), 3169-3183.
36. Suri, M., Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices.
Springer: 2017.
37. Schuller, I. K.; Stevens, R. report of a roundtable convened to consider neuromorphic
computing basic research needs 2015.
38. Demuth, H. B.; Beale, M. H.; De Jess, O.; Hagan, M. T., Neural network design. Martin
Hagan: 2014.
39. Mead, C. Proceedings of the IEEE 1990, 78, (10), 1629-1636.
40. Mead, C.; Ismail, M., Analog VLSI implementation of neural systems. Springer Science &
Business Media: 2012.
41. Merolla, P. A.; Arthur, J. V.; Alvarez-Icaza, R.; Cassidy, A. S.; Sawada, J.; Akopyan, F.;
Jackson, B. L.; Imam, N.; Guo, C.; Nakamura, Y.; Brezzo, B.; Vo, I.; Esser, S. K.; Appuswamy,
R.; Taba, B.; Amir, A.; Flickner, M. D.; Risk, W. P.; Manohar, R.; Modha, D. S. Science 2014,
345, (6197), 668-673.
82

42. Hsu, J. IEEE spectrum 2014, 51, (10), 17-19.
43. Furber, S. B.; Galluppi, F.; Temple, S.; Plana, L. A. Proceedings of the IEEE 2014, 102,
(5), 652-665.
44. Benjamin, B. V.; Gao, P.; McQuinn, E.; Choudhary, S.; Chandrasekaran, A. R.; Bussat,
J.-M.; Alvarez-Icaza, R.; Arthur, J. V.; Merolla, P. A.; Boahen, K. Proceedings of the IEEE
2014, 102, (5), 699-716.
45. Furber, S. Journal of neural engineering 2016, 13, (5), 051001.
46. Farquhar, E.; Hasler, P. IEEE Transactions on Circuits and Systems I: Regular Papers
2005, 52, (3), 477-488.
47. Rangan, V.; Ghosh, A.; Aparin, V.; Cauwenberghs, G. In A subthreshold aVLSI
implementation of the Izhikevich simple neuron model, 2010, IEEE: pp 4164-4167.
48. Indiveri, G.; Linares-Barranco, B.; Hamilton, T. J.; Van Schaik, A.; Etienne-Cummings,
R.; Delbruck, T.; Liu, S.-C.; Dudek, P.; Häfliger, P.; Renaud, S. Frontiers in neuroscience 2011,
5.
49. Chicca, E.; Indiveri, G.; Douglas, R. In An adaptive silicon synapse, 2003, IEEE: pp I-I.
50. Bartolozzi, C.; Indiveri, G. Neural computation 2007, 19, (10), 2581-2603.
51. Friesz, A. K.; Parker, A. C.; Zhou, C.; Ryu, K.; Sanders, J. M.; Wong, H. S. P.; Deng, J.
In A biomimetic carbon nanotube synapse circuit, 2007, p 29.
52. Arthur, J. V.; Boahen, K. In Learning in silicon: Timing is everything, 2006, pp 75-82.
53. Azghadi, M. R.; Iannella, N.; Al-Sarawi, S. F.; Indiveri, G.; Abbott, D. Proceedings of
the IEEE 2014, 102, (5), 717-737.
54. Pickett, M. D.; Medeiros-Ribeiro, G.; Williams, R. S. Nature materials 2013, 12, (2),
114-117.
55. Krzysteczko, P.; Münchenberger, J.; Schäfers, M.; Reiss, G.; Thomas, A. Advanced
Materials 2012, 24, (6), 762-766.
56. Diorio, C.; Hasler, P.; Minch, A.; Mead, C. A. IEEE transactions on Electron Devices
1996, 43, (11), 1972-1980.
57. Kuzum, D.; Jeyasingh, R. G. D.; Lee, B.; Wong, H. S. P. Nano letters 2011, 12, (5),
2179-2186.
58. Chanthbouala, A.; Garcia, V.; Cherifi, R. O.; Bouzehouane, K.; Fusil, S.; Moya, X.;
Xavier, S.; Yamada, H.; Deranlot, C.; Mathur, N. D. Nature materials 2012, 11, (10), 860-864.
59. Zuo, F.; Panda, P.; Kotiuga, M.; Li, J.; Kang, M.; Mazzoli, C.; Zhou, H.; Barbour, A.;
Wilkins, S.; Narayanan, B. Nature Communications 2017, 8, (1), 240.
60. Chang, T.; Jo, S.-H.; Lu, W. ACS nano 2011, 5, (9), 7669-7676.
61. Ohno, T.; Hasegawa, T.; Tsuruoka, T.; Terabe, K.; Gimzewski, J. K.; Aono, M. Nature
materials 2011, 10, (8), 591-595.
62. Wang, Z. Q.; Xu, H. Y.; Li, X. H.; Yu, H.; Liu, Y. C.; Zhu, X. J. Advanced Functional
Materials 2012, 22, (13), 2759-2765.
83

63. Mayr, C.; Staerke, P.; Partzsch, J.; Cederstroem, L.; Schüffny, R.; Shuai, Y.; Du, N.;
Schmidt, H. In Waveform driven plasticity in BiFeO3 memristive devices: model and
implementation, 2012, pp 1700-1708.
64. Subramaniam, A.; Cantley, K. D.; Bersuker, G.; Gilmer, D. C.; Vogel, E. M. IEEE
Transactions on Nanotechnology 2013, 12, (3), 450-459.
65. Williamson, A.; Schumann, L.; Hiller, L.; Klefenz, F.; Hoerselmann, I.; Husar, P.;
Schober, A. Nanoscale 2013, 5, (16), 7297-7303.
66. Ambrogio, S.; Balatti, S.; Nardi, F.; Facchinetti, S.; Ielmini, D. Nanotechnology 2013, 24,
(38), 384012.
67. Shi, J.; Ha, S. D.; Zhou, Y.; Schoofs, F.; Ramanathan, S. Nature communications 2013,
4, 2676.
68. Du, C.; Ma, W.; Chang, T.; Sheridan, P.; Lu, W. D. Advanced Functional Materials
2015, 25, (27), 4290-4299.
69. Kim, S.; Du, C.; Sheridan, P.; Ma, W.; Choi, S.; Lu, W. D. Nano letters 2015, 15, (3),
2203-2211.
70. Tan, Z. H.; Yang, R.; Terabe, K.; Yin, X. B.; Zhang, X. D.; Guo, X. Advanced Materials
2016, 28, (2), 377-384.
71. Wang, Z.; Joshi, S.; Savel’ev, S. E.; Jiang, H.; Midya, R.; Lin, P.; Hu, M.; Ge, N.;
Strachan, J. P.; Li, Z. Nature materials 2017, 16, (1), 101-108.
72. Zhu, X.; Du, C.; Jeong, Y.; Lu, W. D. Nanoscale 2017, 9, (1), 45-51.
73. La Barbera, S.; Vuillaume, D.; Alibart, F. ACS nano 2015, 9, (1), 941-949.
74. Alibart, F.; Pleutin, S.; Guérin, D.; Novembre, C.; Lenfant, S.; Lmimouni, K.; Gamrat,
C.; Vuillaume, D. Advanced Functional Materials 2010, 20, (2), 330-337.
75. Tian, H.; Guo, Q.; Xie, Y.; Zhao, H.; Li, C.; Cha, J. J.; Xia, F.; Wang, H. Advanced
Materials 2016, 28, (25), 4991-4997.
76. Arnold, A. J.; Razavieh, A.; Nasr, J. R.; Schulman, D. S.; Eichfeld, C. M.; Das, S. ACS
nano 2017, 11, (3), 3110-3118.
77. Xu, W.; Min, S.-Y.; Hwang, H.; Lee, T.-W. Science advances 2016, 2, (6), e1501326.
78. Lin, Q.; Sarkar, D.; Lin, Y.; Yeung, M.; Blankemeier, L.; Hazra, J.; Wang, W.; Niu, S.;
Ravichandran, J.; Fan, Z.; Kapadia, R. ACS Nano 2017, 11, (5), 5113-5119.
79. Purves, D. E.; Augustine, G. J.; Fitzpatrick, D. E.; Katz, L. C., Neuroscience. Sinauer
Associates: 1997.
80. Striedter, G. F., Neurobiology: A Functional Approach. Oxford University Press: 2015.
81. Hebb, D. O., The organization of behavior: A neuropsychological approach. John Wiley
& Sons: 1949.
82. Bienenstock, E. L.; Cooper, L. N.; Munro, P. W. Journal of Neuroscience 1982, 2, (1),
32-48.
83. Markram, H.; Lübke, J.; Frotscher, M.; Sakmann, B. Science 1997, 275, (5297), 213-215.
84. Bi, G.-q.; Poo, M.-m. Journal of neuroscience 1998, 18, (24), 10464-10472.
84

85. Van Rossum, M. C. W.; Bi, G. Q.; Turrigiano, G. G. Journal of neuroscience 2000, 20,
(23), 8812-8821.

Abstract (if available)

Abstract Over the past five decades, the world has made rapid technological progress supported by the advancement in solid-state electronics and photonics. Referred to as the Moore’s Law, the fundamental mechanism for making a better microprocessor chip has been the reduction of footprint of individual operational units (field effect transistors), thus increasing the chip functionality and performance by increasing planar density. However, there is an impending problem. Improving integrated circuits by device miniaturization is coming to an end, since device miniaturization is reaching its fundamental physical limit. A potential novel approach for continued improvement is a three dimensional (3D) multifunctional integrated circuit. However, there are several challenges associated with fabricating a 3D IC, and this dissertation is aimed at experimentally establishing the viability of potential solutions to some of the fundamental problems. Those are: (i) the ability to integrate single crystal semiconductors on an amorphous buffer, (ii) at a temperature below 400 ℃ so that underlying active layers are not affected, and (iii) to be able to fabricate high-performance devices out of them. ❧ A recently introduced non-epitaxial growth technique called thin film—vapor liquid solid growth that showed the ability to grow large area grain size (10-100 μm) polycrystalline film on metal foils, has been adopted as the primary material growth method. It has been first generalized to be integrable on any substrate including amorphous and crystalline dielectrics (i.e. not just limited to metals), and its geometrical constraints from a thermodynamic perspective are established. This has allowed for a wide variety of compound semiconductor materials (III-Vs and IV-Vs) to be able to be grown as templates up to tens of micron in lateral dimension on a wide variety of technologically relevant substrates. Extensive photoluminescence measurements and analyses have been performed, which indicate excellent optoelectronic performance comparable to that of commercial single crystal InP wafer. Temperature dependent photoluminescence, Hall mobility, and electron back-scatter diffraction studies demonstrate the ability to grow high quality single crystal III-Vs below 400 ℃ on amorphous substrates including on flexible substrates such as polyimide. Room temperature Hall mobility reaching 6000 cm²/V-s for InAs grown at 300 ℃ on HfO₂, and contact-resistance limited FET mobility of 500 cm²/V-s for InP grown on SiO₂, have been shown: one of the highest values so far for any material family directly grown on an amorphous dielectric. A scalable platform for obtaining artificial synapses has been demonstrated by modulation of oxide-semiconductor interface trap occupancy in InP nanowire FETs. Finally, selective growth of MOCVD epitaxial layers on these single crystal templates have been briefly studied as precedents to obtain ultra-high performance devices on the back-end of CMOS chips.

Linked assets

University of Southern California Dissertations and Theses

Conceptually similar

PDF

III-V semiconductor heterogeneous integration platform and devices for neuromorphic computing

PDF

The selective area growth and coalescence of indium phosphide nanostripe arrays on silicon through MOCVD for NIR monolithic integration

PDF

Integrating material growth and device physics: building blocks for cost effective emerging electronics and photonics devices

PDF

Perovskite chalcogenides: emerging semiconductors for visible to infrared optoelectronics

PDF

Integrated photonics assisted electron emission devices

PDF

Printed electronics based on carbon nanotubes and two-dimensional transition metal dichalcogenides

Asset Metadata

Creator Sarkar, Debarghya (author)

Core Title Building blocks for 3D integrated circuits: single crystal compound semiconductor growth and device fabrication on amorphous substrates

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 02/27/2020

Defense Date 02/18/2020

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag 3D integration,artificial synaptic device,compound semiconductor,high mobility,III-V,InAs,InP,liquid phase,low temperature growth,MOCVD,OAI-PMH Harvest,thin body FET,thin film

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Kapadia, Rehan (committee chair), Povinelli, Michelle (committee member), Ravichandran, Jayakanth (committee member), Wang, Han (committee member)

Creator Email debarghyasarkar.ds@gmail.com,dsarkar@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c89-275497

Unique identifier UC11673064

Identifier etd-SarkarDeba-8217.pdf (filename),usctheses-c89-275497 (legacy record id)

Legacy Identifier etd-SarkarDeba-8217.pdf

Dmrecord 275497

Document Type Dissertation

Rights Sarkar, Debarghya

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA