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Printed electronics based on carbon nanotubes and two-dimensional transition metal dichalcogenides

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Printed electronics based on carbon nanotubes and two-dimensional transition metal dichalcogenides

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Content PRINTED ELECTRONICS BASED ON CARBON NANOTUBES AND TWO-DIMENSIONAL TRANSITION METAL DICHALCOGENIDES Copy right 2020 By FanqiWu A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (MATERIALS SCIENCE) May 2020 FanqiWu Dedication This dissertation is dedicated to my beloved family. Acknowledgements I have never imagined that I would gam such a wonderful and precious experience when I first joined University of Southern California (USC) as a Ph.D. student in 2014. During the past five and half years, I felt so lucky to meet so many kind and brilliant people who helped me, encouraged me and inspired me not only in my research but also in my personal life. Without their support, it would be impossible for me to accomplish this dissertation. First of all, I would like to express my sincere appreciation to my Ph.D. advisor, Prof. Chongwu Zhou, for his valuable guidance and endless support during my PhD study. My vision and knowledge have been greatly broadened by working with him. His passion and dedication to research have always been inspiring me to explore in my research field and grow to be a professional experimentalist, an enthusiastic researcher, and an independent thinker. Meanwhile, I would like to thank my dissertation committee members, Prof. Wei Wu and Prof. Jayakanth Ravichandran, for their valuable suggestions and comments for my dissertation. Besides, I also want to thank Prof. Edward Goo and Prof. Aiichiro Nakano for serving on my Ph.D. qualifying exam committee. Additionally, I would like to thank all my former and current group members and friends: Pattaramon Vuttipittayamongkol, Dr. Xuan Cao, Dr. Bilu Liu, Dr. Jia Liu, Dr. Qingzhou Liu, Dr. Gang Liu, Dr. Hui Gui, Dr. Yihang Liu, Dr. Haitian Chen, Dr. ii Luyao Zhang, Dr. Xiaoli Wang, Dr. Ahmad Abbas, Dr. Mingyuan Ge, Dr. Xin Fang, Dr. Yuchi Che, Dr. Noppadol Aroonyadet, Dr. Maoqing Yao, Dr. Jiepeng Rong, Dr. Yu Cao, Dr. Yuqiang Ma, Dr. Sen Cong, Dr. Liang Chen, Dr. Chenfei Shen, Dr. Anyi Zhang, Nai-Yun Shih, Christian Lau, Dr. Tianchi Chen, Zhen Li, Mingrui Chen, Zhiyuan Zhao, Dingzhou Cui, Dr. Bingya Hou, Dr. Haotian Shi, and Dr. Jihan Chen. Thank all of you for your help and support for me during the past years. I can't imagine my PhD journey without sharing my ups and downs with you. Needless to say that I would never be able to achieve the accomplishments without your encouragement and inspiration. Finally but most importantly, I want to thank my parents, my husband, Dr. Liang Chen, and my little daughter for their endless love, support and encouragement. It is your love and support that made me fearless to explore my research field and all the possibilities of myself. Thank you for making me a better me. iii Table of Contents Dedication ........................................................................................................................... .i Acknowledgements ............................................................................................................ ii List of Figures .................................................................................................................... vi List of Tables ...................................................................................................................... vi Abstract ............................................................................................................................ xvi Chapter 1: Introduction ....................................................................................................... 1 1.1 Introduction to Carbon Nanotubes ............................................................................. 1 1.2 Structure of Carbon Nanotubes ................................................................................. 2 1.3 Printed Electronics Based on SWCNTs .................................................................... .4 1.4 Introduction to Two-Dimensional Transition Metal Dichalcogenides ....................... 9 1.5 Printed Electronics Based on 2D TMDCs ............................................................... 10 Chapter 2: Threshold Voltage Tuning and Printed Complementary Transistors and Inverters Based on Thin Films of Carbon Nanotubes and Indium Zinc Oxide ................. 13 2.1 Introduction ............................................................................................................. 13 2.2 Experimental Methods ............................................................................................. 15 2.3 Results and Discussion ............................................................................................ 17 2.4 Conclusions ............................................................................................................. 31 Chapter 3: Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length ................................................. 33 3.1 Introduction ............................................................................................................. 33 3.2 Experimental Methods ............................................................................................. 35 3.3 Results and Discussion ............................................................................................ 37 3.4 Conclusion ............................................................... ................................................ 52 Chapter 4: High-Performance Sub-Micron Channel WSe2 Field-Effect Transistors Prepared Using A Flood-Dike Printing Method .............................................. 54 4.1 Introduction ............................................................................................................. 54 4.2 Experimental Methods ............................................................................................. 56 4.3 Results and Discussion ............................................................................................ 58 4.4 Conclusion ............................................................................................................... 92 Chapter 5: Conclusions and Future Directions .................................................................. 93 iv 5.1 Conclusions ............................................................................................................. 93 5.2 Future Directions on Printed CNT Electronics ........................................................ 95 Bibliography ····················································································································lOO V List of Figures Figure 1.1 Excellent properties of carbon nanotubes and their potential applications . ................................................................................................................................. 1 Figure 1.2 Structure of SWCNTs. (a) Chirality map of SWCNTs where key parameters such as base vectors, chiral vector, chiral index, chiral angle, and diameter, are shown. (b, c) Atomic structure of (6,5) and (9,1) SWCNT, respectively . ................................................................................................................................. 4 Figure 1.3 Carbon nanotube applications m nanoelectronics and macroelectronics . ................................................................................................................................. 6 Figure 1.4 Recent progress in CNT printed electronics. ( a) Schematic diagram showing the process of fully ink-jet printed SWCNT TFTs, including: 1. printing first silver electrodes; 2. printing SWCNT network; 3. printing second layer of silver electrodes; 4. printing ionic gel as dielectric material. 14 (b) Schematic diagram of screen printer and an optical image of screen printed SWCNT TFT array on a PET substrate. 15 (c) Schematic diagram outlining gravure printing process of SWCNT TFTs and images of printed TFT and nanotube network on a PET substrate. 29 (d) Schematic diagram of flexographic printing and an optical image of flexographic printed CNT TFT electronics on a PET substrate. 38 ................................................................................................................................. 9 Figure 1.5 Periodic table showing elemental combinations ofTMDCs . ............................................................................................................................... 10 Figure 1.6 Recent progress in the field of printed electronics based on 2D TMDCs. (a) Inkjet printing of MoS2. 73 (b) Electrical properties of synthesized large-area MoS2 field-effect transistors fabricated with inkjet-printed contacts. 72 (c) Liquid-exfoliated TMDC nanosheet inks for all-printed FETs. 74 (d) 2D crystal inks for all-printed photodetectors and memory devices. 76 ............................................................................................................................... 12 Figure 2.1 Schematic diagrams of the printed complementary inverter fabrication process, optical and SEM images of printed back-gated CNT and IZO TFTs. Schematic diagrams demonstrate the printed complementary inverter fabrication process, including (a) printing ofIZO precursor solution as the active material for n-type transistor and (b) printing of 98% semiconducting enriched SWCNT solution as the active material for p-type transistor. (c) An optical image of a printed CNT TFT (before annealing). ( d) An SEM image of the CNT network in the channel region. ( e) An optical image of a printed IZO vi TFT (after annealing). (f) An SEM image of a printed back-gated IZO TFT. ............................................................................................................................... 18 Figure 2.2 Characterization of printed back-gated p-type CNT TFTs and n-type IZO TFTs. (a) Jo-Vo characteristics of a representative CNT TFT (L = 100 µm , W = 500 µm). (b) Io-Va characteristics (black for linear scale; blue for logarithm scale) and gm- Va characteristics (red) of the same CNT TFT measured at Vo = 1 V. ( c) Statistical analysis of the Vih distribution of 20 CNT TFTs. ( d) Jo-Vo characteristics of a representative IZO TFT (L = 100 µm, W = l 00 µm). ( e) Io Va characteristics (black for linear scale; blue for log scale) and gm-Va characteristics (red) of the same IZO TFT measured at Vo= 1 V. (f) Statistical analysis of Vih distribution of 20 IZO TFTs . ............................................................................................................................... 20 Figure 2.3 Histograms of normalized on-current, current on/off ratio, and field effect mobility of 20 CNT TFTs with Ti/ Au S/D metal contacts and 20 CNT TFTs with Ti/Pd metal contacts. (a) Histogram of normalized on-current measured from 20 CNT devices with Ti/ Au S/D metal contacts. (b) Histogram of field-effect mobility of the 20 CNT devices showing the average mobility of 2.35 cm 2 /(V ·s), with 8 of the devices showing mobility between 2 and 3 cm 2 /(V ·s). (c) Histogram of current on/off ratio of the same 20 CNT devices, with 16 of the devices showing on/off ratios between 1 x 10 5 and 1 x 10 7 . ( d) Histogram of normalized on-current of 20 CNT devices with Ti/Pd S/D metal contacts. ( e) Histogram of field-effect mobility measured from the same 20 CNT TFTs showing the average mobility of 1.17 cm 2 /(V·s), with 10 of the devices showing mobility between 1.0 and 1.5 cm 2 /(V·s). (f) Histogram of current on/off ratio of the same 20 CNT TFTs, with nine of the devices showing on/off ratios between 1 x 10 5 and 1 x 10 7 . ............................................................................................................................... 21 Figure 2.4 Histograms of normalized on-current, current on/off ratio, and field effect mobility of20 IZO TFTs. (a) Histogram of normalized on-current of 20 IZO TFTs. (b) Histogram of current on/off ratio measured for the same 20 IZO devices, with 12 of the devices showing on/off ratios between 1 x 10 5 and 1 x 10 7 . ( c) Histogram of field-effect mobility of the 20 IZO devices showing the average mobility of 5.86 cm 2 /(V·s), with 9 of the 20 devices showing mobility between 4 and 8 cm 2 /(V·s) . ............................................................................................................................... 22 Figure 2.5 Characterization of printed CNT TFT with Ti/Pd (1 nm/50 nm) as S/D electrodes. (a) Jo-Vo characteristics of a representative CNT TFT (L = 100 µm, W = 500 µm). (b) Io-VG characteristics of the same CNT device. (c) Statistical analysis of Vih distribution of 20 printed CNT TFTs with Ti/Pd as S/D electrodes . ............................................................................................................................... 25 vii Figure 2.6 Characterization of printed IZO TFTs with various In:Zn ratio. (a) ID-Va characteristics of IZO TFTs with different In:Zn ratios including In:Zn = 1: 1 (blue), In:Zn = 2: 1 (red) and In:Zn = 3: 1 (black), measured at VD= 1 V. (b) ID-VD characteristics of a representative IZO TFT (L = 100 µm, W = 100 µm) with In:Zn = 1: 1. ( c) Io-Va characteristics of the same IZO TFT with In:Zn = 1: 1. ( d) ID-VD characteristics of a representative IZO TFT (L = 100 µm, W = 10 µm) with In:Zn = 3:1. (e) ID-Va characteristics of the same IZO TFT with In:Zn = 3:1. ............................................................................................................................... 28 Figure 2. 7 Characterization of a printed complementary inverter based on p type CNT TFT and n-type IZO TFT. (a) Vour-VIN characteristics of one representative inverter measured under Voo = 4 V (black), 5 V (red), 6 V (green), 7 V (dark blue), 8 V (light blue), respectively. (b) Switching current (Jo-VIN) curves of the same complementary inverter with VDD = 4 V (black), 5 V (red), 6 V (green), 7 V (dark blue), 8 V (light blue), respectively. (c) Gains of the same complementary inverter with VDD = 4 V (black), 5 V (red), 6 V (green), 7 V ( dark blue), 8 V (light blue), respectively . ............................................................................................................................... 30 Figure 3 .1 SEM image of the highly uniform printed carbon nanotube network. ............................................................................................................................... 39 Figure 3 .2 Top-contact self-aligned printed ultrashort channel CNT thin film transistors. (a-d) Schematic diagrams showing the fabrication process of a top contact self-aligned printed ultrashort channel nanotube transistor. (a) Schematic diagram showing the ink-jet printing process of the first electrode on top of the pre-printed nanotube network. (b) Schematic diagram showing the surface functionalization of the electrodes with a self-assembled monolayer. (c) Schematic diagram showing the self-aligned ink-jet printing process of the second electrode on the SAM-decorated surface of the first electrode before dewetting. (d) Schematic diagram showing the ink-jet printing of ion gel dielectric. ( e) Optical microscope image showing two printed electrodes defined by top-contact self-aligned printing technique and the ultrashort channel formed between these two electrodes. (f) AFM and SEM images showing an ultrashort channel of 400 nm with nanotubes between two printed electrodes formed by self-aligned printing . ............................................................................................................................... 40 Figure 3.3 (a) Optical microscope image showing the dewetting of the second electrode from the first electrode surface about 5 minutes after printing. The color contrast on the first electrode may come from solvent residue after the dewetting of the second electrode. (b) Optical microscope image showing the trace of solvent was removed after sintering due to solvent evaporation . ............................................................................................................................... 41 viii Figure 3.4 Electrical characterization of fully-printed ultrashort channel CNT TFTs on willow glass. (a) Transfer characteristics (Io-Vo) of a representative ultrashort channel nanotube TFT (L=400 run, W=40 µm) , measured at different Vos, from -0.1 V to -0.5 V with a step of -0.1 V. (b) Transfer characteristics measured under Vos=-0.1 V showing a current on/off ratio of ~lx10 5 . The inset of this figure exhibits the gate leakage current as a function ofV oat Vos=-0.1 V. ( c) Output characteristic (Io-Vo) of the same device measured at different Vo (from 0.5 V to -2 V with -0.5 V steps). (d) Comparison of channel length and on-state current density of printed CNT TFTs between this work, and other work. ............................................................................................................................... 42 Figure 3.5 Capacitance-voltage characteristic for the printed ultrashort channel CNT TFT, measured at a frequency of 100 Hz . ............................................................................................................................... 44 Figure 3.6 Output characteristic of the top-contact self-aligned printed ultrashort channel CNT TFT in linear region . ............................................................................................................................... 44 Figure 3. 7 Statistical data of channel length measurements on printed ultrashort channel devices. (a) SEM image of printed ultrashort channel with 15 evenly spaced channel length measurements along the channel's x axis. (b) Plot of channel length measurements from (a). (c) Combined histogram of channel length measurements from 9 printed ultrashort channel devices. ( d) Combined plot of channel length measurements from 9 printed ultrashort channel devices . ............................................................................................................................... 45 Figure 3.8 Statistics analysis of 30 CNT TFTs with L=496 run printed with top contact self-aligned printing technique. (a) On-state current density distributions of 30 TFTs measured at Vo=-1.5V and Vos=-0.1 V. (b) Field-effect mobility distributions of 30 TFTs extracted from transfer characteristics measured at Vos=-0.lV. (c) Threshold voltage distributions of 30 TFTs. (d) Current on/off ratio distributions of 30 TFTs measured at Vos=-0.1 V. ............................................................................................................................... 48 Figure 3.9 Optical images showing the printed CNT TFTs with different channel lengths, 40 µm , 120 µm and 150 µm . ............................................................................................................................... 48 Figure 3 .10 Electrical characterization of printed CNT TFTs with different channel lengths. (a) Transfer characteristics ofrepresentative printed CNT TFTs with channel lengths of 496 run (violet), 40 µm (red), 120 µm (green), and 150 µm (blue). (b) Statistical study of 45 printed CNT TFTs showing on-state current density as a function of channel length. ( c) Statistical study of 45 printed CNT TFTs showing width-normalized total resistance as a function of channel length. ix ............................................................................................................................... 49 Figure 4.1 "Flood-dike" self-aligned printing of short channel FETs based on CVD WSe2. (a) Schematic diagram showing a single monolayer triangle-shape WSe2 flake transferred on Si/Si 02. (b-d) Schematic diagrams showing the three steps of the "flood-dike" self-aligned printing method, including (b) printing of the first gold electrode, ( c) functionalizing the surface of the first electrode with SAM, and ( d) printing of the second gold electrode close to the first one. ( e) Zoomed-in schematic diagram showing the gold ink of the second electrode flooding towards the first electrode right after landing on the WSe2 surface. (f) Zoomed-in schematic diagram showing the gold ink gets stopped by the SAM "flood-dike", forming a short channel in sub-micron scale . ............................................................................................................................... 59 Figure 4.2 XPS studies of CVD monolayer WSe2. (a) XPS spectrum of a W 4f core level of CVD monolayer WSe2 on Si/SiO2 before air annealing. The blue solid line represents the experimental data. The orange dashed lines are Lorentzian fits for the peaks of WSe2. (b) XPS spectrum of a W 4f core level of CVD monolayer WSe2 on Si/SiO2 after annealing in air at 220 °C for 2h. The black solid line represents the experimental data. The dashed lines in orange and green represent Lorentzian fits for the peaks ofWSe2 and WOx, respectively . ............................................................................................................................... 60 Figure 4.3 EDX mapping of Au and S on the surface of the printed gold electrode and SiO2 substrate after SAM treatment. The mapping area is shown in (a) . ............................................................................................................................... 60 Figure 4.4 Representative optical images of water drops on (a) Au surface, (b) SAM-treated Au surface, (c) WSe2 surface, (d) WSe2 surface after SAM treatment, (e) SiO2 surface, and (f) SiO2 surface after SAM treatment. ............................................................................................................................... 62 Figure 4.5 Representative optical images of gold ink drops on (a) WSe2 surface, (b) SiO2 surface, (c) fresh Au surface, and (d) SAM-treated Au surface . ............................................................................................................................... 62 Figure 4.6 Representative optical image of xylene drop on WSe2 surface . ............................................................................................................................... 63 Figure 4.7 (a-d) Images and characterizations of CVD monolayer WSe2. (a) Optical microscope image showing a typical triangle-shape monolayer WSe2 flake transferred to Si/Si 02. This particular flake is ~ 187 µm. (b) AFM image of the WSe2 flake in (a) along with the cross-section height profile of the white dash line. The thickness of this flake is measured to be ~0.8 nm corresponding to a mono layer TMDC. ( c) Raman spectrum of a typical transferred WSe2 flake showing the two characteristic peaks of E2g1 mode and Alg mode. ( d) PL spectrum of the same WSe2 flake in (c) showing a strong PL peak at ~752 nm, X confirmed the mono layer status. ( e) Optical microscope image of a sub-micron channel defined by the "flood-dike" printing approach. (f) AFM and SEM (inset) images showing a clearly-defined gap measured to be~ 750 nm . ............................................................................................................................... 64 Figure 4.8 Optical microscope images showing three typical printed WSe2 FETs with sub-micron channel lengths, fabricated using the "flood-dike" printing method . ............................................................................................................................... 66 Figure 4.9 SEM image showing a typical sub-micron channel formed by "flood dike" printing method . ............................................................................................................................... 66 Figure 4.10 Representative zoomed out optical microscope image showing two printed sub-micron channel FETs on a single WSe2 flake . ............................................................................................................................... 67 Figure 4.11 Electrical characteristics of the printed ultra-short channel WSe2 FET with a back-gate device structure. (a) Transfer characteristics (Jo-Vo) of a typical WSe2 FET (L = 750 nm, W = 30 µm) measured under different Vos from -0.5 V to -2.0 V in a step of -0.5 V. The inset shows the AFM image of the channel, measured to be 750 nm. (b) The same transfer characteristics plotted in a logarithmic scale showing an Ion! loff ratio of 1x10 5 . ( c, d) Output characteristics (Jo-Vos) of the same device measured under different Vo from 0 V to -100 V in a step of -10 V, with ( c) showing the low Vos region and ( d) showing the high Vos region, respectively . ............................................................................................................................... 69 Figure 4.12 (a) Logarithm and (b) linear scale of the Io-Va characteristics of a representative WSe2 FET measured using DC method under Vos = -2 V and different integration time of 0.64 ms, 20 ms and 100 ms. ( c) Logarithm and ( d) linear scale of the Jo-Vo characteristics of the same WSe2 FET measured by pulse 1-V method, with different pulse period (tperioct) varying from 10- 2 s to 1 s under a constant pulse width (ton) of 10- 3 s. The base of Vo was set to be O V and Vos was -2 V. (e) Comparison of hysteresis (t::.V) between the forward and backward sweeps for the transfer characteristics of the WSe2 FET, measured by the conditions in (a-d). The hysteresis was extracted based on the pink dashed line in (a) and (c), where -Jo= 1 nA. (f) Trap density (ntrap) of the device under different measurement conditions, estimated using ntrap = Cox x !::. V / e , where Cox= 1.21xl0- 8 F/cm 2 for 285 nm SiO2 . ............................................................................................................................... 70 Figure 4.13 ( a-c) Statistic Analysis of 24 sub-micron WSe2 FE Ts printed using the three-step "flood-dike" printing method. (a) Histogram showing the on-state current densities (Jon/W) distribution measured at Vos= -2 V and Vo= -100 V. (b) Histogram showing the on/off current ratio (Jonlloff) distribution, extracted xi at Vos = -2 V. (c) Histogram showing the field-effect mobility distribution extracted from Io-Vo curves measured at Vos= -2 V. (d) Comparison study of on-state current density and on/off current ratio between this work and previously reported printed TMDC works . ............................................................................................................................... 72 Figure 4.14 Transfer characteristics of the LED-driving WSe2 FET, measured under different Vos, from -0.5 V to -2.0 Vin -0.5 V steps . ............................................................................................................................... 77 Figure 4.15 (a) Energy band diagram of DHNR LED and a schematic of a DHNR. (b) Schematic diagram showing the structure of the DHNR-LED. (c) Current-voltage characteristics of the DHNR-LED . ............................................................................................................................... 78 Figure 4.16 Current-voltage characteristics of the inorganic LED . ............................................................................................................................... 79 Figure 4.17 (a) Schematic diagrams showing the cross-section view of the OLED structure. The OLED used in this study is a 4,4'-bis[N-(l-naphthyl)-N phenylamino ]bi phenyl (NPD)/tris(8-hydroxyquinoline )aluminum (Alq3) green light OLED with aluminum (Al) as the cathode and indium tin oxide (ITO) as the anode. (b) Current-voltage characteristics of the OLED . ............................................................................................................................... 80 Figure 4.18 Printed back-gated sub-micron WSe2 FET for QDLED, inorganic LED and OLED control. (a, b) Electrical characteristics of the printed WSe2 FET connected to an external QDLED with the circuit diagram shown in the inset. (a) lQoLED-Vo family curves measured under different Voo from 1.5 V to 4.0 V in a step of 0.5 V. (b) lQoLE o-Voo family curves measured under Vo from 0 V to -100 V in a step of -10 V. ( c) Optical images demonstrating the light intensity modulation of QDLED by tuning Vo at Voo = 4 V. ( d, e) Electrical characteristics of the printed WSe2 FET connected to an external inorganic LED with the circuit diagram shown in the inset. ( d) hED-Vo family curves measured under Voo from 1.5 V to 3.0 Vin a step of 0.5 V. (e) hED-Voo family curves measured under Vo from O V to -100 Vin a step of -10 V. (f) Optical images showing the light intensity modulation of inorganic LED by tuning Vo at Voo = 2 V. (g, h) Electrical characteristics of the printed WSe2 FET connected to an external OLED with the circuit diagram shown in the inset. (g) Io1Eo-Vo family curves measured under Voo from 5 V to 10 V in a step of 1 V. (h) Io1Eo-Voo family curves measured under Vo from O V to -100 V in a step of -10 V. (i) Optical images showing the light intensity modulation of OLED by tuning Vo at Voo = 8 V. ............................................................................................................................... 81 Figure 4.19 (a) Schematic diagrams of CVD setups for triangle-shaped WSe2 growth and hexagram-shaped WSe2 growth. For hexagram-shaped growth, the xii substrate is enclosed in a special inner tube with a small opening facing the upstream supplies. (b )( c) optical microscope images showing the as-grown WSe2 flakes with triangular shapes (b) and hexagram shapes ( c ). The lateral size of an individual WSe2 flake is ~ 10 µm for triangular-shaped samples and ~20 µm for hexagram-shaped samples. (d) AFM image of a hexagram-shaped WSe2 flake along with the cross-section height profile of the white dash line. The height of the sample is measured to be ~0.8 nm corresponding to a mono layer TMDC. ( e) Raman spectrum of the as-grown CVD WSe2 showing the two characteristic peaks of E2g1 mode and Alg mode. (f) PL spectrum of the CVD WSe2 sample showing a strong PL peak at ~ 770 nm, confirmed the monolayer status . ............................................................................................................................... 84 Figure 4.20 (a) Io-VG transfer curve of a representative printed sub-micron WSe2 FET, measured at a negative Vos of -2V. The inset shows the optical image of the device. (b) The transfer curve plotted in a logarithmic scale showing an Ion! fo ff ratio of 10 5 . The inset shows the SEM image of the device. ( c) A family of Jo- Vos output curves of the printed devices showing the existence of Schottky barrier. ( d) Jo-Vos output curves in the low-bias region . ............................................................................................................................... 87 Figure 4.21 Optical microscope images of additional sub-micron channel devices prepared using "flood-dike" printing method. These devices were printed on monolayer WSe2 flakes directly synthesized on Si/SiO2 . ............................................................................................................................... 87 Figure 4.22 Statistic studies of the performance of printed ultra-short channel devices on CVD monolayer WSe2 flakes synthesized on Si/SiO2. (a) Ion/W distribution of 14 printed sub-micron monolayer WSe2 FETs, measured under VG = -100 V and VDS = -2 V. (b) Ion/Ioff ratio distribution of the devices printed on monolayer WSe2. (c) Field-effect mobility distribution of the printed devices on monolayer WSe2, extracted under VDS = -2 V. ............................................................................................................................... 88 Figure 4.23 Printed ultra-short channel devices based on few-layer CVD WSe2. (a) Io-VG transfer curve measured at a Vos of -2 V. (b) Io-VG transfer curve at a negative Vos of -2 V in a logarithmic scale. A clear p-type behavior can be observed for few-layer WSe2 samples. Compared to monolayer WSe2 devices, few-layer WSe2 devices show higher on-current but lower Ionlloffratio. (c)(d) A family of Jo-Vos output curves measured at different VG . A clear Schottky behavior can be observed from the output curves . ............................................................................................................................... 89 Figure 4.24 Printed back-gated sub-micron WSe2 FET for inorganic LED and OLED control. ( a, b) Electrical characteristics of printed WSe2 FET connected to an external inorganic LED with the circuit diagram shown in the inset. (a) xiii lLED-VG curve measured under VoD of5 V. (b) lLED-VDD family curves measured under VG from -40 V to -100 V in a step of -10 V. ( c) Optical images demonstrating the light intensity modulation of LED by tuning VG at Voo = 5 V. ( d, e) Electrical characteristics of printed WSe2 FET connected to an external OLED. (d) loLEo-VG family curves measured under VDD from O V to 10 Vin a step of 2 V. ( e) loLEo-V DD family curves measured under VG from O V to -100 Vin a step of -20 V. (f) Optical images showing the light intensity modulation of OLED by tuning VG at VDD = 8 V. ............................................................................................................................... 90 Figure 5 .1 (a) Schematic diagrams showing a screen printing system. (b) Equivalent circuit diagram of a single pixel in the thin-film transistor (TFT) array with the sensor acting as a variable resistor in series with the single-wall carbon nanotube (SWCNT) TFT. (c) Cross-section schematic diagram of a pressure sensor cell. ( d) A photograph of a screen-printed flexible sensor array with SWCNT active-matrix backplane . ............................................................................................................................... 97 Figure 5.2 AMOLED using SWCNT TFTs. (a) Optical image of an AMO LED substrate containing 7 AMO LED elements, each with 20x25 pixels. (b) Photograph showing the pixels on an integrated AMOLED. (c) Characteristics of the OLED controlled by a single pixel circuit. (d) Plot of the current through the OLED (/OLEO; red line) and OLED light intensity (green line) versus VDATA with VDD = 8 V. 112 ............................................................................................................................... 99 xiv List of Tables Table 3 .1 Comparison of on-state current density for printed CNT TFTs. ~ .......... .46 Table 4 .1 Comparison of the device performances for printed 2D TMDC FE Ts .. 7 5 xv Abstract Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed electronics due to their excellent electrical performance and intrinsic printability with solution-based deposition. Compared to traditional micro fabrication, printing technology offers a scalable and cost-effective way to fabricate electrical devices by eliminating multi-stage lithography patterning and high vacuum environment. Besides that, printing technology allows carbon nanotubes to be deposited at room temperature through a solution-based process, so devices can be printed on any kinds of substrates, including flexible and stretchable substrates. Thus, printing technology is very promising for making large-scale low-cost flexible electronics. This dissertation discusses about the development of two novel platforms for printed carbon nanotube electronics. The first platform is inkjet printing of p-type carbon nanotube (CNT) and n-type indium zinc oxide (IZO) for complementary integrated circuits. Carbon nanotube transistors are usually p-type in air due to the adsorption of oxygen. Achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging to make reliable n-type CNT transistors. Metal oxides have been reported to be good candidates for n-type channel materials. In this study, indium zinc oxide was selected as our n-type channel material. In order for complementary circuits to work correctly, both types xvi of transistors need to operate in enhancement mode. To achieve this, the threshold voltages of both types of transistors were carefully tuned, by engineering the work function of metal contacts for CNT transistors and adjusting In to Zn molar ratio for IZO transistors. With the optimum recipe, IZO and CNT thin films were printed sequentially on the same substrate to construct a complementary inverter. The printed inverter worked correctly with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work shows the promise of using inkjet printing for the hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits. The second platform is a top-contact self-aligned printing approach for submicron channel carbon nanotube thin-film transistors. Limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 µm) and consequently low current-drive capabilities (<0.2 µA/µm). With top-contact self aligned printing approach, the transistor channel length has been successfully downscaled to submicron scale, leading to a dramatically enhanced on-state current density of ~4.5 µA/µm . These advantageous features of our printed ultrashort channel transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics. xvii Furthermore, part of this dissertation presents the development of a novel printing platform for high-performance submicron-channel two-dimensional (2D) transition metal dichalcogenide (TMDC) field-effect transistors (FETs ). 2D TMDCs have been drawing great attention because they are atomically thin, intrinsically flexible, and they have good electrical properties. 2D TMDCs are ideal materials for flexible electronics. Printing technology has potential to offer a cost effective and scalable way to fabricate electronic devices based on 2D TMDCs. However, limited by the registration accuracy and resolution of printing, the previously reported printed TMDC FETs have relatively long channel lengths (13-200 µm) , thus suffering low current-driving capabilities (:S0.02 µA/µm). In this dissertation, I developed a "flood-dike" self-aligned printing technique that allows the formation of source/drain metal contacts on TMDC materials with submicron channel lengths in a reliable way. With this printing technique, we have successfully downscaled the channel length to ~750 nm and achieved enhanced on-state current density of ~0.64 µA/µm (average) and high on/off current ratio of ~3 x 10 5 (average). Furthermore, with our high-performance printed WSe2 FETs, driving capabilities for quantum-dot light-emitting diodes (LEDs), inorganic LEDs, and organic LEDs have been demonstrated, which reveals the potential of using printed TMDC electronics for display backplane applications. This dissertation is structured as follows. Chapter 1 gives a brief introduction to carbon nanotubes, two-dimensional transition metal dichalcogenides, and printed xviii electronics, which serves as the background knowledge for the following chapters of this dissertation. Chapter 2 presents the development of inkjet-printed complementary transistors and circuits based on p-type carbon nanotubes and n- type indium zinc oxide. After that, Chapter 3 talks about the development of top contact self-aligned printing method for submicron channel carbon nanotube thin film transistors. Following that, Chapter 4 discusses about the development of "flood-dike" self-aligned printing approach for submicron channel 2D TMDC FETs. Finally, Chapter 5 presents the conclusions and points out future directions. xix Chapter 1: Introduction 1.1 Introduction to Carbon Nanotubes Since Sumio Ijima first reported the discovery of carbon nanotubes (CNTs) in 1991 in Japan, 1 tremendous research efforts have been devoted into the field of CNTs in the aspects of both fundamental science and technological applications. Over the past years, CNTs have become one of the most explored one-dimensional nanomaterials. Nanoelectronics & Macroelectronics Power Transmission Lines Electronic ,. - ,. Figure 1.1 Excellent properties of carbon nanotubes and their potential applications. CNTs have superior mechanical, electronic, chemical, optical, and thermal properties, so they are promising for a wide variety of potential applications, including nanoelectronics, macroelectronics, optoelectronics, power transmission lines, heat sink, mass sensor, CNT 1 filter, chemical sensor, biological imaging, etc. (Figure 1.1). 2 Regarding to the electronic property, CNTs can be either metallic or semiconducting depending on its geometry. 3 On one hand, semiconducting CNTs can achieve ballistic transport due to the large mean free path in the scale of hundreds of nanometers. 4 Extremely high field-effect carrier mobility has been observed in semiconducting CNTs, experimentally measured to be over 100,000 cm 2 /V s, which exceeds the mobility of silicon. 5 • 6 On the other hand, metallic CNTs have much larger current-carrying capability (over 10 10 A/cm 2 ) than copper and they are free of electromigration due to the strong C-C bonding, making metallic CNTs ideal material for interconnects. 1.2 Structure of Carbon Nanotubes CNTs are seamless, hollow cylinders made of carbon atoms, formed by rolling up graphene sheets with honeycomb structure (Figure 1.2a). 3 The number of graphene layers being rolled up determines the wall number of CNTs, classifying CNTs to single-walled carbon nanotubes (SWCNTs) and multi-walled carbon nanotubes (MWCNTs). For SWCNTs, depending on the way the graphene sheet is rolled up, the resulting SWCNT can have very different structures, i. e., atom arrangements in the three dimensions. As is shown in Figure 1.2a, the unit base vectors of the hexagonal graphene lattice are: ll1 = a( v'3, 0) a,= a('7,;) 2 , where a= 0.142 nm which is the bond length of C-C bond. The chiral vector of SWCNTs is defined as: Ch = na1 + ma2 The pair of integers (n,m) indicates the structure of SWCNTs, which is defined as chirality, or chiral index. The angle between the chiral vector and base vector a1 is defined as chiral angle 8: e = tan- 1 [-./?,m] m+2n The diameter of carbon nanotube is defined as: ../?,a.---- d = ---J n 2 + mn + m 2 1[ Depending on the chiral angle of SWCNTs, they can be classified into the following three types. When 8 = 0°, the nanotube is defined as zigzag nanotube. When 8 = 30°, the nanotube is defined as armchair nanotube. When 0° < 8 < 30°, the nanotube is defined as chiral nanotube. The structure of a SWCNT can be described by its chirality (n,m) or, equivalently, diameter (d) and chiral angle (8). Figure 1.2b and 1.2c show the atomic structure of (6,5) and (9,1) SWCNT, respectively. It is well-known that electronic band structures and many properties of SWCNTs are determined by their chiralities. For example, about one-third of SWCNTs are metals (when n - m = 3q, where q is an integer), while the rest of the two- thirds are semiconductors (when n - m -::/::- 3q). Equally noticeable is that for semiconducting SWCNTs, their band gaps are inversely proportional to tube diameters. 3 Therefore, the structure and property of SWCNTs, including diameter, chirality, and electronic property, have to be well controlled for various applications of nanotubes. Figure 1.2 Structure of SWCNTs. (a) Chirality map of SWCNTs where key parameters such as base vectors, chiral vector, chiral index, chiral angle, and diameter, are shown. (b, c) Atomic structure of (6,5) and (9,1) SWCNT, respectively. 1.3 Printed Electronics Based on SWCNTs Due to the excellent electronic properties of SWCNTs, great research interest has been drawn to the CNT electronics field over the past few decades. The research efforts can be classified into two different directions. One is nanoelectronics and the other one is macroelectronics (Figure 1.3). CNT nanoelectronics field focuses on scaling down the transistor dimensions and improving the individual transistor performance, aiming for 4 replacing silicon for the future generation of electronic devices. A lot of progress has been made in this field, including ballistic field-effect transistors, 4 ' 7 radio frequency transistors, 8 - 11 and integrated circuits, 12 etc. On the other hand, macroelectronics field focuses on the development oflarge-area pixel-based highly-uniform thin-film transistors, which can work as "switch" for light-emitting diodes (LEDs) or sensors aiming for consumer electronics (Figure 1.3). 13 - 15 For macroelectronics, the devices need to cover a large area (> 1 m 2 ). In contrary to nanoelectronics, it doesn't require a high integration density of transistors. As a result, the transistor dimensions don't have to be downscaled to nanometer scale, as long as the performance of the devices satisfies the need for driving LEDs or sensors. Actually, for macroelectronics, transistors usually have large channel lengths of 1-100 µm. The main applications of macroelectronics include flexible electronics, display electronics, and printed electronics (Figure 1.3). In this dissertation, I mainly focus on the application of carbon nanotubes in printed electronics direction. 5 CPU Memory Touch Screen Flexible Electronics , Scale down Improve Large-area "Switch" for transistor transistor pixel-based LEDs or dimension performance uniform TFTs ' (l RF Electronics Neuromorphic Display Electronics Printed Electroncis Figure 1.3 Carbon nanotube applications in nanoelectronics and macroelectronics. Printed electronics is a set of printing methods utilized to fabricate electrical devices on various substrates. Functional materials, including metals, semiconductors and insulators can be formulated into inks with properties suitable for printing. Then the inks can be directly printed onto any substrate, including flexible and stretchable substrates. With proper curing, functional patterns can be generated. Compared to conventional fabrication methods, printing has many advantages. First of all, printing is an additive patterning process, which eliminates the need for multistage thin film deposition, lithography patterning, and etching processes commonly required for a subtractive patterning process. Thus, the amount of functional materials used can be reduced and the time of fabrication can be shortened. Besides that, printing can be done in ambient environment with high throughput and scalability. In this way, device fabrication is not 6 limited to wafer scale or batch processing. Furthermore, printing technology allows the functional materials to be deposited at moderate temperature through a solution-based process. 16 , 17 As a result, the devices can be easily made on flexible and stretchable substrates, including polyethylene terephthalate (PET), polyethylene naphthalate (PEN), styrene-ethylene-butylene-styrene (SEBS), etc. Printing technology has emerged as a promising approach to realize large-area cost-effective flexible and stretchable electronics. SWCNTs, which are intrinsically printable at room temperature, show its great advantages over amorphous silicon and polysilicon for printed electronics. 14 , 18 Compared to other printable organic materials, SWCNTs have much higher mobility and better stability in ambient 1 5 , 19 , 20 Thanks to the great progress made in SWCNT separation,3, 21 • 22 high-purity semiconducting-enriched SWCNT solution has been realized, which leads to feasibility of printing high-performance SWCNT thin-film transistors (TFTs) for macro and display electronic applications. 14 , 15 , 23 - 27 To realize fully printed high-performance SWCNT TFTs, selection of materials for electrodes and gate dielectrics is critical. In terms of electrodes, silver and gold based nanoparticle inks are the most widely used because of their high conductivity and the formation of Ohmic contact between electrodes and SWCNTs. 23 , 28 , 29 Although nanomaterials such as metallic SWCNTs have been used as electrodes, 30 the performance was rather moderate and therefore hard to be applied for macro and display electronics. For printing gate dielectrics, mixtures composed of high-K metal oxide nanoparticles and organic binders are commonly used to achieve relatively high capacitance, 15 , 29 which can 7 reduce the operation voltage of printed TFTs. Another group of dielectric materials is electrolyte, which have been reported by Frisbie and Hersam's groups. 26 • 31 The most important advantage of employing electrolyte as the gate dielectric is the high capacitance regardless of its rather large physical thickness. As a result, the performance of such printed electrolyte-gated SWCNT TFT is superior in terms of on-state current density, current on off ratio and low operation voltage. 32 Multiple printing technologies reported for fabricating SWCNT TFTs can be mainly divided into two groups. 15 The first one is of high registration accuracy represented by aerosol-jet printing and inkjet printing. The second one is of high scalability and throughput represented by gravure printing and flexographic printing. On one hand, for printing SWCNTs as channel materials, ink-jet and aerosol-jet printing are the main-stream technologies using relatively low-viscosity inks to pattern an ultrathin and uniform film. On the other hand, ink-jet printing, aerosol-jet printing, screen printing, gravure printing and flexographic printing have all been employed for patterning gate dielectric and electrodes to achieve fully-printed SWCNT TFTs. Up until now, the fully-printed high performance SWCNT TFT has been used for macro, display, and sensor electronics. Our group made great efforts to develop fully printed SWCNT TFTs for OLED driving using ink-jet printing (Figure 1.4a) and screen printing (Figure 1 .4b ). 14 • 15 Javey and Cho' s groups pioneered in gravure printed SWCNT electronics (Figure 1.4c), realizing D flip-flop, 33 full adder, 34 and fully printed backplane for electronic skin. 35 Hersam' s group reported high performance printed ring oscillators using aerosol-jet printing. 24 • 36 • 37 Ohno's group made 8 great efforts on developing fully flexographic printed SWCNT TFTs with CVD grown nanotubes (Figure 1.4d). 38 Overall, such cost-effective and solution-based printing technologies have been attracting more and more research interest and are promising for practical applications. C d ,. "-' Jj JJ #-, .. j - • ." J1 •• "'\'--~ ... ', Figure 1.4 Recent progress in CNT printed electronics. (a) Schematic diagram showing the process of fully ink-jet printed SWCNT TFTs, including: 1. printing first silver electrodes; 2. printing SWCNT network; 3. printing second layer of silver electrodes; 4. printing ionic gel as dielectric material. 14 (b) Schematic diagram of screen printer and an optical image of screen printed SWCNT TFT array on a PET substrate. 15 ( c) Schematic diagram outlining gravure printing process of SWCNT TFTs and images of printed TFT and nanotube network on a PET substrate. 29 ( d) Schematic diagram of flexographic printing and an optical image of flexographic printed CNT TFT electronics on a PET substrate. 38 1.4 Introduction to Two-Dimensional Transition Metal Dichalcogenides Transition metal dichalcogenides (TMDCs) which are two-dimensional (2D) layered materials generally have a formula of MX2, where M stands for a transition metal and X 9 stands for a chalcogen (Figure 1.5). 39 - 41 Depending on the composition, the TMDCs can span from superconductors to semiconductors and even insulators 39 · 42 · 43 Meanwhile, other factors including thickness, defects, and strain can also affect their physical properties such as band gap and field-effect mobility. 44 - 48 Among the large family of TMDCs, MoS2 and WSe2 are the two most widely studied species with interesting semiconducting features. 49 - 51 In particular, mono layer WSe2 which possesses a direct band gap and ambipolar transport behavior, 52 · 53 has been demonstrated as a good candidate for optoelectronics, 54 - 57 spintronics, 58 and valleytronics. 51 · 59 At the same time, this TMDC material is also suitable for other electronic applications such as chemical sensing and flexible electronics because of the 2D layered nature. 60 - 63 MX 2 M = Transi tion metal Li Be X = Chal cogen B C N 0 F Ne Na Mg 3 4 5 6 7 8 9 10 11 12 Al Si p s Cl Ar K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr Rb Sr y Zr Nb M o Tc Ru Rh Pd Ag Cd In Sn Sb Te X e Cs Ba La-Lu Hf Ta w Re Os Ir Pt Au Hg Tl Pb B i Po At Rn Fr Ra Ac-Lr Rf Db Sg Bh Hs Mt Os Rg Cn Uut Fl Uup Lv Uus Uuo Figure 1.5 Periodic table showing elemental combinations of TMDCs. 1.5 Printed Electronics Based on 2D TMDCs The current semiconductor manufacturing relies heavily on sophisticated fabrication processes such as lithography, vacuum deposition, etc., which may be prohibitively costly and time-consuming to adapt to TMDC-based devices. Fortunately, printing technology 10 designed for solution-based low-temperature processing can eliminate the needs for high cost lithography and vacuum systems. 64 Up to now, printing approaches have been reported for a number of devices including field-effect transistors (FETs), logic gates, and solar cells using CNTs, 14 , 15 , 23 , 26 , 27 , 29 , 65 metal oxides, 24 , 27 , 66 organic films, 67 , 68 or inorganic nanoparticles, 69 which demonstrate the great potential of using printing technology for low cost and large-scale electronic applications. 22 , 35 , 70 Recently, significant progress has been made in printed electronics based on 2D TMDCs. 71 - 75 In 2014, Li et al. demonstrated fully inkjet-printed M0S2 FETs by printing M0S2 liquid dispersions on top of printed silver contacts (Figure 1.6a). 73 Later on, Kim et al. reported chemical vapor deposition (CVD) synthesized monolayer M0S2 FETs with inkjet-printed silver contacts (Figure 1.6b ). 72 Recently, a family ofliquid-exfoliated TMDC nanosheet inks have been utilized for all-printed FETs by Kelly et al. 74 (Figure 1.6c), all printed photodetectors and memory devices by McManus et al. (Figure 1.6d), 76 respectively. To sum up, printing technology emerges as a promising platform to offer a cost-effective and scalable approach to fabricate electronic devices based on 2D TMDCs. 11 a C A ~1 ~ - s • Graphene ----g d b d Figure 1.6 Recent progress in the field of printed electronics based on 2D TMDCs. (a) Inkjet printing of MoS2. 73 (b) Electrical properties of synthesized large-area MoS2 field effect transistors fabricated with inkjet-printed contacts. 72 ( c) Liquid-exfoliated TMDC nanosheet inks for all-printed FETs. 74 (d) 2D crystal inks for all-printed photodetectors and memory devices. 76 12 Chapter 2: Threshold Voltage Tuning and Printed Complementary Transistors and Inverters Based on Thin Films of Carbon Nanotubes and Indium Zinc Oxide 2.1 Introduction In the past decades, single-wall carbon nanotube (SWCNT) thin-film transistors (TFTs) have been extensively studied as a potential replacement of amorphous silicon TFTs due to their superior electrical performance in terms of field-effect mobility, on/off current ratio (Jonlloff), small operation voltage and high-speed operation. 4 ' 14 , 77 • 78 As-synthesized carbon nanotubes (CNTs) have capabilities of being either semiconducting or metallic depending on chirality, 79 and there have been a number of efforts to selectively eliminate metallic ones in order to increase Ion/ loff of CNT TFTs. Various approaches have been developed to remove metallic nanotubes from existing nanotube devices. 80 - 84 However, these methods cannot be easily scaled up and/or can degrade device performance or even severely damage devices. An important alternative is exploiting separated semiconducting CNT solutions, which are commercially available, by means of deposition techniques such as printing, 14 , 85 spin coating, 86 , 87 incubation, 78 , 88 , 89 or drop casting. 90 In particular, printing has the advantage of allowing deposition of CNTs at room temperature, which makes device and circuit fabrication on flexible substrates possible. In addition, there is no photolithography process involved during the printing process, and hence it can reduce the cost of fabrication. 13 While p-channel TFTs have been demonstrated with SWCNTs as active channel materials, 91 , 92 metal oxide semiconductors are good candidates for n-channel transistors. These two kinds of semiconductors have noticeable advantages over traditional amorphous silicon and organic semiconductors, such as relatively high carrier mobility, high stability under ambient conditions, low manufacturing cost, high transparency, and room temperature fabrication compatibility. 93 Indeed, there have been many reports, especially for metal oxides such as indium zinc oxide (IZO), 94 - 98 zinc oxide, 99 , 100 and indium gallium zinc oxide. 101 Due to the ease of precursor preparation, most studies of these materials have employed sputtering 94 , 100 and spin coating 95 , 96 , 99 , 101 techniques rather than solution processed inkjet printing technique. 97 , 98 However, the latter is more desirable since it offers scalability and cost efficiency with patterning, because there is no clean-room process required. Combining p-type and n-type transistors to construct complementary logic circuits is preferred for the reason that they have low static power consumption, full voltage swings, and large noise margins. 102 , 103 With these advantages, manufacturing of both p-type and n type transistors on the same substrate giving an integrated complementary circuit is desired. Nevertheless, an inexpensive, uncomplicated process is a challenge. The inkjet printing technique is a good candidate, as it allows fabrication of TFTs without the involvement of masks or photolithography processes, which also results in reduced fabrication time. Thus, using inkjet printing is very effective as a low-cost technology to print both enhancement mode p-type and n-type semiconductors for complementary transistors and circuits. The 14 first part of my research focused on inkjet-printed complementary transistors and inverters comprising p-type CNT and n-type IZO semiconductors, and threshold voltage (Vih) tuning of both p-type and n-type transistors. We have compared Ti/ Au and Ti/Pd as source/drain (S/D) electrodes for p-type TFTs, and it was clearly demonstrated that Ti/ Au metal contacts offered enhancement-mode operation with Vih < 0. In addition, the effects of varying In:Zn ratios (1:1 , 2:1 and 3:1) of the IZO precursor solution were studied. The optimized In:Zn ratio was found to be 2: 1, as devices with this ratio exhibited relatively high on-state current (Jon) and enhancement-mode operation (Vih > 0). Last but not least, we have achieved the printing of a complementary inverter with an output swing of 99 .6% of the supply voltage (Voo) and voltage gain of 16.9, made up of an enhancement-mode CNT transistor (p-type) and an enhancement-mode IZO transistor (n-type) on the same substrate. 2.2 Experimental Methods IZO precursor solution preparation Indium(III) nitrate hydrate (ln(NO3)3 ·xH2O) and zmc acetate dihydrate (Zn(CH3COO)2"2H2O) were dissolved in 2-methoxyethanol as precursors of indium oxide and zinc oxide with a concentration of 0.6 and 0.3 M, respectively. These two solutions were stirred with a speed of 3,500 rpm at 50 ° C for 1 h and then mixed to obtain In:Zn ratios of 1: 1, 2: 1, and 3: 1. During the mixing process, ethanolamine (EA) was added to the mixture as a stabilizer to improve the uniformity and viscosity of the solution to meet the inkjet printing requirements. The volume concentration of the stabilizer added was found 15 to be optimized at 32%. Lastly, the final solution was stirred at 50 °Cat 3,500 rpm for 1 h and then aged overnight. IZO TFT printing First, 1 nm/50 nm Ti/Au S/D electrodes were patterned onto a Si/SiO2 (50 nm) wafer by a photolithography process. Next, the well-sonicated IZO precursor solution was printed onto the channel region as the active material of n-type transistors via a GIX Microplotter Desktop (Sonoplot Inc.), followed by air annealing at 500 ° C for 1 hour. CNT TFT printing First, a Si/SiO2 (50 nm) substrate was immersed into diluted aminopropyltriethoxysilane (APTES) solution (APTES/isopropanol alcohol (IPA)= 1/10) for 10 min, in order to form an amine-terminated monolayer on top of the substrate and improve the adhesion between CNTs and the substrates. Then, the substrate was rinsed with IPA and blown dry with N2. After that, a density gradient ultracentrifugation (DGU) separated 98% semiconducting-enriched SWCNT solution (IsoNanotubes-S_DGU, 1.0 mg in 100 mL of aqueous solution, Nanointegris Inc.) was printed in the channel region as the active material of p-type transistors via the inkjet printer. After printing, the samples were left in air for 30 min and then baked at 80 ° C for 20 min to remove the solvent. Finally, they were aged overnight to improve the adhesion between CNTs and the substrate before being rinsed with deionized (DI) water to remove surfactant residue from the CNT film. 16 2.3 Results and Discussion Figure 2. la and 2.1 b show schematic diagrams of the inkjet-printed integrated complementary inverter fabrication process. Figure 2.la shows the printing process of a back-gated IZO TFT as the n-type transistor of the inverter. Briefly, the IZO precursor solution was printed on a Si/SiO2 (50 nm SiO2) substrate with pre-photolithography pattemed Ti/ Au (1 nm/50 nm) S/D electrodes. Post-printing annealing was performed in order to convert the printed precursor film into IZO, which acts as the active material in then-type transistor. Similarly, Figure 2.1 b shows the printing process of an SWCNT TFT. A 98% semiconducting-enriched SWCNT solution was printed as the active material for the p-type transistor of the inverter. Before the printing of CNT, the Si/SiO2 substrate was functionalized with APTES to improve the adhesion between SWCNT and the Si/SiO2 substrate, following our previously published recipes. 14 • 78 • 88 • 89 Immediately after printing, the CNT film was inspected with an optical microscope to check the quality of the film. Figure 2.1 c shows that the CNT film of the CNT TFT before annealing has good uniformity and no cracks. Then, a field emission scanning electron microscope (FESEM) was utilized to examine the uniformity and density of the CNT networks in the channel region of the TFT. From the FESEM image in Figure 2.1 d the density of CNT networks is approximately 26-35 tubes/µm 2 , which is a viable density for TFT applications according to our previously published work. 14 , 88 Figure. 2.1 e illustrates an optical image of a printed IZO TFT after annealing. It is evident that the IZO layer has good shape and uniformity. This well-controlled printing 17 process was realized by optimizing the amount of EA added in the precursor ink to achieve the desired viscosity for inkjet printing. The FESEM image of an IZO TFT (Figure 2.1 f) shows the uniformity of the IZO film after air annealing at 500 ° C for one hour. a C e Print 120 film ____,______. 120 solution / Ti/Au ·SJD - 100 µm ,/ Ti/Au S/D - 100 µm Print CNT film b .-------.CNT solution d------------- CNT Network - 2µm f Figure 2.1 Schematic diagrams of the printed complementary inverter fabrication process, optical and SEM images of printed back-gated CNT and IZO TFTs. Schematic diagrams demonstrate the printed complementary inverter fabrication process, including (a) printing ofIZO precursor solution as the active material for n-type transistor and (b) printing of 98% semiconducting-enriched SWCNT solution as the active material for p-type transistor. (c) An optical image of a printed CNT TFT (before annealing). ( d) An SEM image of the CNT 18 network in the channel region. ( e) An optical image of a printed IZO TFT ( after annealing). (t) An SEM image of a printed back-gated IZO TFT. Electrical measurements were carried out for the inkjet-printed back-gated CNT TFTs. We found that most of the printed CNT devices exhibited Ion in the range between 0.8 and 9.5 µA with gate bias (VG) of -10 V and drain voltage (Vo) of 1 V. The devices possess Ionlioff ratios of 10 4 -10 6 with mobilities of 1-5 cm 2 /(V·s) and Vih of -1.0 - -3.0 V. These features are comparable with those demonstrated in our previous publications on printed CNT TFTs. 14 Histograms of normalized on-current (/on x LIW), current on/off ratio (Joni Ioff) and field-effect mobility of 20 CNT TFTs are shown in Figure 2.3a-c respectively. The electrical characteristics of one representative CNT device with channel length (L) of 100 µm and channel width (W) of 500 µmare presented in Figure 2.2a and 2.2b. As shown in Figure 2.2a, the output (Io-Vo) characteristics of the representative CNT device exhibited a saturation behavior as Vo became more negative. Figure 2.2b shows the transfer (Io-Vo) characteristics of the same device. The black curve represents the Io-Va characteristics on a linear scale. From this plot, one can see that Ion is 5 .2 µA when VG is -10 V and Vo is 1 V. In addition, one can find Vih to be around -1.4 V. The Io-VG characteristics on a logarithmic scale (the blue curve in Figure 2.2b) indicate that Ionliorr is 1 x 10 6 . The transconductance-gate voltage (gm-VG) characteristics are also plotted in Figure 2.2b in red, where the peak gm and the mobility of this CNT device were extracted to be 1.5 µS and 4.38 cm 2 /(V·s), respectively, based on the parallel plate model. Statistical Vih analysis 19 was carried out for 20 printed CNT devices. As shown in Figure 2.2c, most devices show Vth between -1.0 and -3.0 V, which indicates that most CNT devices were operating in enhancement mode (Vth<0). a b C CNTTFT VG from -5V to 5V -16 -1 i-12 e 5 -8 u C · e -4 C 0 5 1 4 ... C 3 e ... ::s 2 u C . i! C 0 -5 -10 ~ Cl) Cl J9 0 > 'ti 0 .J:. Ul e .J:. t-- 3 2 1 0 -1 -2 -3 -4 - • • -4 -3 -2 -1 0 Drain Voltage (V) 10 .. v 05 =1 v 10-" 10·' ~ ... 10_, Pl 10-9 8 10·" - ~ 10-11 0 -5 0 5 10·" 10 Gate Voltage (V) •• • • - . • - • • • •• • •• • " 5 o 2 4 6 8 101214161820 Index of Devices 1.6 1.41 1.2 Cl) ,., 1.0 i 0.8 o ::s 0.6 "g 0.4 0 ,., 0.2 Ul C 0.0 ~ -0.2 d e _ 16 1 c 12 ~ 8 8 C -~ 4 C 0 i: 3 c 2 ~ ::s u C 1 - ~ C 0 0 -5 IZOTFT VG from 10Vto-5V in -1.5 v step 2 3 Drain Voltage (V) v 05 = 1 v 0 5 Gate Voltage (V) 4 5 10·' 10-" ~ 10· 1 ~ 10 .. a C 10-9 -~ C 10· 10 10· 11 10 f _ 3.------------, 2:. .. 8, 2 ~ g 1 ------- .... - -" -- .. -- .. - 'tl .. .. .. .. .. :g o ... .. ;...._ .. ....z....,.___ ..., - ""' .. ___ ....; .. ....; " - ,,, ~ -1 t-- · 2 0 2 4 6 8 101214161820 Index of Devices 0.6 (ii 0.5 .c\, a, 0.4 g 0.3 ~ ::s 0.2 'g 0 0.1 ~ C 0.0 f! t-- -0.1 Figure 2.2 Characterization of printed back-gated p-type CNT TFTs and n-type IZO TFTs. (a) Io-Vo characteristics of a representative CNT TFT (L = 100 µm, W= 500 µm). (b) Io Va characteristics (black for linear scale; blue for logarithm scale) and gm- Va characteristics (red) of the same CNT TFT measured at Vo= l V. (c) Statistical analysis of the Vth distribution of 20 CNT TFTs. ( d) Io-Vo characteristics of a representative IZO TFT (L = 20 100 µm, W= 100 µm). (e) ID-VG characteristics (black for linear scale; blue for log scale) and gm-VG characteristics (red) of the same IZO TFT measured at VD= 1 V. (f) Statistical analysis of Vih distribution of 20 IZO TFTs. a 8--------- ~ 6 ·;; ., 04 0 l;; ~2 ::, z CNT TFTs with Ti/Au S/D o...._....___. _ _.___..._..__, 0.0 0.2 0.4 0.6 0.8 1 0 :L/W (µA) 1.0 1.2 d 8 f/1 ~ 6 - ~ 04 0 ... ., ~2 ::, z 0 0.0 0.2 CNT TFTs with Ti/Pd S/D ~ - 0.4 0.6 1 0 ;uw (.uAl 0.8 1.0 b 10.-----------, ~ 8 " ·;; ~ 6 0 ~ 4 § 2 z C 12.----------, ,,, 10 ., I 8 0 6 l;; 4 .0 § 2 z 0 0---~2--3--4--s 01-~2-~3-~4-~s-6-~7 Mobility (cm 2 N's) log 10 (1 0 /l 0 11 ) Figure 2.3 Histograms of normalized on-current, current on/off ratio, and field-effect mobility of 20 CNT TFTs with Ti/ Au SID metal contacts and 20 CNT TFTs with Ti/Pd metal contacts. (a) Histogram of normalized on-current measured from 20 CNT devices with Ti/ Au SID metal contacts. (b) Histogram of field-effect mobility of the 20 CNT devices showing the average mobility of 2.35 cm 2 /(V ·s), with 8 of the devices showing mobility between 2 and 3 cm 2 /(V·s). (c) Histogram of current on/off ratio of the same 20 CNT devices, with 16 of the devices showing on/off ratios between 1 x 10 5 and 1 x 10 7 . ( d) Histogram of normalized on-current of 20 CNT devices with Ti/Pd SID metal contacts. ( e) Histogram of field-effect mobility measured from the same 20 CNT TFTs showing the average mobility of 1.17 cm 2 /(V ·s), with 10 of the devices showing mobility between 1.0 and 1.5 cm 2 /(V·s). (f) Histogram of current on/off ratio of the same 20 CNT TFTs, with nine of the devices showing on/off ratios between 1 x 10 5 and 1 x 10 7 . 21 (a) 10 IZO FTs (J) 8 <1J (.) ·;; 4.) 6 "O ._ 0 4 .... 4.) ..0 E ::I 2 ;z 0 0.0 0.5 1.0 1.5 2.0 2.5 Io n x l/W (µA ) (b) 1 0 <I) 8 4.) .::! > cu 6 "O ._ 0 4 .... cu .i::, E 2 ::I ;z 0 I 2 3 4 5 6 7 logw (Jo,/ fotV (c) 1 0 <I) Cl) 8 .2 > Cl) 6 "O .... 0 ,.__ 4 4.) .i::, E 2 ::I 0 0 4 8 12 16 Mobility (cm 2 /(V• )) Figure 2.4 Histograms of normalized on-current, current on/off ratio, and field-effect mobility of 20 IZO TFTs. (a) Histogram of normalized on-current of 20 IZO TFTs. (b) Histogram of current on/off ratio measured for the same 20 IZO devices, with 12 of the devices showing on/off ratios between 1 x 10 5 and 1 x 10 7 . ( c) Histogram of field-effect mobility of the 20 IZO devices showing the average mobility of 5.86 cm 2 /(V·s), with 9 of the 20 devices showing mobility between 4 and 8 cm 2 /(V·s). The electrical performance of the printed IZO TFTs was also studied. It is found that most IZO TFTs showed Ion of 0.6-5.2 µA for a Vo of 10 V and Vo of 1 V, Ionlloff of 10 4 - 22 106, mobility of 1.0-14.1 cm 2 /(V·s) and Vih of 0-1 V, which are comparable with those in the literature for printed IZO TFTs. 97 • 98 Figure 2.4 shows the histograms of normalized on current (Figure 2.4a), current on/off ratio (Figure 2.4b) and field-effect mobility (Figure 2.4c) of 20 IZO devices. Figure 2.2d shows the lo-Vo family curves of one representative IZO device with L = l 00 µm and W = l 00 µm. In Figure 2.2d, one can observe a saturation behavior as Vo becomes more positive. Figure 2.2e exhibits the transfer characteristics of the same IZO device on both linear (black curve) and logarithmic (blue curve) scales, and the plot of gm versus Vo (red curve), from which one can extract values for this IZO device of Ion of 3.3 µA, Vih of0.2 V, IonlioffOf lxl0 5 , peak gm of0.5 µSand mobility of 7.36 cm 2 /(V·s). The Vih values ofIZO TFTs were also collected and studied. The statistical results based on 20 inkjet-printed back-gated IZO TFTs shown in Figure 2.2f indicate that most IZO devices had Vih between O and 1.0 V, and were operating in enhancement mode (Vih > 0). The outstanding benefits of a complementary circuit make it the preferred choice over many other configurations for the inverters presented in this work. We emphasize that it is significant to make sure that both p-type and n-type composites are operating in enhancement modes. Therefore, a study on the Vih tuning of both types of transistors was conducted. Here we demonstrate first the effects of different metal electrodes on Vih of the p-type devices. Besides the Ti/Au details given previously, Ti/Pd (1 nm/50 nm) was also used to fabricate S/D electrodes of printed CNT TFTs. The majority of CNT devices with these Ti/Pd electrodes show I on of 0.5-9 µA,lo n lioff Of 10 3 -106, mobility of 0.50-2.39 cm 2 /(V ·s), 23 and Vih of 1.0-3.0 V. Histograms of normalized on-current, current on/off ratio and field effect mobility of 20 CNT devices are exhibited in Figure 2.3d-f. The normalized on current and current on/off ratio, and mobility of these 20 CNT devices with Ti/Pd SID contacts are comparable with ones with Ti/ Au. The electrical characteristics of one of these devices (L = 100 µm , W = 500 µm) are shown in Figure 2.5a and 2.5b. The Io-Vo family curves in Figure 2.5a demonstrate a saturation behavior as Vo becomes more negative while the Io-Vo family characteristics in Figure 2.5b were investigated under Vo swept from 1 to 0.2 V in -0.2 V steps. In Figure 2.5b, Ion is apparently 2.45 µA when Vo is -10 V and Vo is 1 V, Vih is 1.2 V, and Ion! IofI is 1 x 10 5 . The maximum gm of this device was found to be 0.32 µS; subsequently, the mobility was calculated to be 1.38 cm 2 /(V·s). In addition, Figure 2.5c shows the statistics obtained from the Vih of 20 CNT TFTs with Ti/Pd as S/D metal contacts. Most of the devices have Vih of 1-3 V, indicating that the majority were operating in depletion mode (Vih > 0), unlike those with Ti/Au metal contacts (shown in Figure 2.2c ). It is concluded that Ti/Pd electrodes caused a right shift of the Vih of CNT TFTs relatively to that of Ti/ Au electrodes. The reasons why the TFTs with Ti/Pd electrodes exhibit more positive Vih are: the conduction of holes between the electrode and the CNT channel is dictated by the alignment between the Fermi energy level of the metal and the valence band of the CNT. The work function of Pd is around 5 .1 e V, which is similar to the work function of CNT, and hence enables lower energy barrier between the metal electrode and the CNT. This results in a lower energy being required to lower the barrier for carrier conduction, and hence shifts the Vih to the right. 104 Therefore, Ti/Au SID contacts are 24 preferred in this work because CNT TFTs with Ti/ Au metal contacts showed more negative Vih, which ensured the preferred enhancement-mode (Vih < 0) p-type CNT TFTs for application in complementary circuits. a -6 -5 < ..;; -4 .... C ~ -3 ::I (.) -2 C ~ -1 ~5 -4 CNT TFT with Ti/Pd SID VG from -5 Vto 5 V -3 -2 -1 Drain Voltage (V) 0 b 3.0r------------. C 12.5 :;:- 2.0 C e 1 ... . 5 ::I (.) C 1.0 .E C 0.5 0 ·~10 ~ (I) C) cu - 0 > "C 0 ..c 1/) (I) .. ..c I- 4 3 2 1 0 -1 -2 -3 • • • Vos from 1 V to 0.2 V -5 0 5 10 Gate Voltage (V) & .... • • • • • • • & • .... • • • • • -4 0 2 4 6 8 1 0 12 141618 20 Index of Devices Figure 2.5 Characterization of printed CNT TFT with Ti/Pd (1 nm/50 nm) as S/D electrodes. (a) Jo-Vo characteristics of a representative CNT TFT (L = 100 µm, W = 500 25 µm). (b) ID-Vo characteristics of the same CNT device. (c) Statistical analysis of Vih distribution of 20 printed CNT TFTs with Ti/Pd as S/D electrodes. Likewise, the relationship between Vih of the n-type device with In-to-Zn molar ratio, which also affects the Ionliotr and mobility of the devices, was investigated. Figure 2.6a shows the transfer characteristics of the printed IZO devices with In:Zn ratios of 1: 1, 2: 1 and 3: 1 represented by blue, red and black curves, respectively. Higher In:Zn ratios result in higher mobility and Ion, lower Io n lio tr and Vih apparently shifting to the left, which are consistent with previously published work. 97 As the amount of In was increased two and three fold, the carrier mobility rose dramatically from 1.11 to 7.36 cm 2 /(V ·s) and to as high as 31.74 cm 2 /(V·s) while Ion (at Vos= 1 V and Vo = 10 V) increased correspondingly from 0.49 to 3.3 and 4.1 µA. Our devices with In:Zn = 1: 1 and 2: 1 had about the same values of Ion! Io ff on average because Iotr also increased along with Io n- However, when the In:Zn ratio was increased to 3: 1, Iotr increased much faster than Ion, resulting in poor Ion! Iotr- As in Figure 2.6a, values of Ion/Ioff Ofthe 1 :1 and 2:1 devices are about the same, ~ 10 5 , whereas that of the 3: 1 device drops abruptly to as low as 4. Moreover, the first two show positive Vih while the latter apparently has negative Vih, which indicates it is operating in depletion mode (Vih < 0). It can be concluded that IZO TFTs with In:Zn = 1:1 resulted in poor Ion while those with 3: 1 had unacceptable Ion! Io ff and depletion-mode operation ( Vih < 0). Therefore, it is clear that an In:Zn ratio of 2: 1 offered the best overall performance, with the combination of desirable Ion, mobility, Ion! Io ff and Vih. The IZO TFT with In:Zn = 2: 1 shown in Figure 2.2 has been discussed in the previous section of this paper. For 26 comparison, Figure 2.6b and 2.6c show lo-Vo and Io-VG curves for a representative IZO device (L = 100 µm , W = l 00 µm) with In:Zn = 1: 1; this device shows Ion of 0.49 µA, Vih of 1 V, Ionlioff Of 10 5 and carrier mobility of 1.11 cm 2 /(V ·s). Figure 2.6d and 2.6e reveal that the IZO device with In:Zn = 3: 1 cannot be fully depleted even at VG= -15 V. As is evident from their high drain currents at relatively high negative VG, most of the IZO devices with In:Zn = 3: 1 operated in depletion mode ( Vih < 0). According to previous studies, 97 , 105 this phenomenon arises because, among the oxides of In, Ga and Zn, indium oxide has the highest mobility and the largest carrier concentration. With such high carrier concentration, it is challenging to bring down Ioff so as to improve the poor Ion! Ioff. 27 b d a 4 Vos= 1 v ~ ~3 ... C: I!! 52 (.) C: -~ 1 C 0 -4 -2 0 2 4 6 8 10 Gate Voltage (V) 3.0 ln/Zn=1/1 12.5 .,. VG from 10 V to -5 V e! 2.0 in -1.5 V steps 8 1.5 ·; 1.0 0 0.5 0 · 0 o 1 2 3 4 Drain Voltage (V) 20 ln/Zn=3/1 i 15 VG from 10 V to -15 V ... C: in -2.5 V steps I!! 10 ... ::::i (.) C: . E 5 C 8.o 0.5 1.0 1.5 Drain Voltage (V) 5 2.0 C 0.6.....-----------, ln/Zn=1/1 i 0.5 ;; 0.4 Vos from 1 V to 0.2 V C: a, in -0.2 V steps I: 0.3 ::::i (.) c: 0.2 "i! C 0.1 0 -~5 o 5 Gate Voltage (V) e 4 ln/Zn=3/1 ~ Vos from 1 v to 0.2 v ~ 3 ... in -0.2 V steps C: I!! ... 2 ::::i (.) C: "{! 1 C ~15 -10 -5 0 Gate Voltage (V) 10 5 10 Figure 2.6 Characterization of printed IZO TFTs with various In:Zn ratio. ( a) Jo-Vo characteristics of IZO TFTs with different In:Zn ratios including In:Zn = 1: 1 (blue), In:Zn = 2: 1 (red) and In:Zn = 3: 1 (black), measured at Vo= 1 V. (b) Jo-Vo characteristics of a representative IZO TFT (L = 100 µm, W = 100 µm) with In:Zn = 1:1. (c) Io-Va characteristics of the same IZO TFT with In:Zn = 1: 1. ( d) Jo-Vo characteristics of a representative IZO TFT (L = 100 µm, W = 10 µm) with In:Zn = 3: 1. ( e) Io-Va characteristics of the same IZO TFT with In:Zn = 3: 1. 28 The capability of printing both CNT TFTs and IZO TFTs with desirable mobility, controlled Vth and good IonliofI enables us to construct high-quality complementary digital circuits through the inkjet printing approach. As demonstrated, a printed complementary inverter was achieved based on thin films of CNT and IZO. The electrodes were Ti/Au (1 nm/50 nm) patterned by a photolithography process. The In:Zn ratio in the IZO precursor ink was selected to be 2: 1, in accordance with the conclusion discussed above. Information about the static performance of the complementary circuit can be acquired from its voltage transfer (Voui-Vin) curves. In Figure 2.7a, the voltage transfer characteristics of one typical complementary inverter are illustrated at various Voo ranging from 4 to 8 V in 1 V steps. Ideally, the output voltage switches from the "l" state (8 V) to the "0" state (0 V) in response to an input signal that is swept from the "0" state (0 V) towards the "1" state (8 V) and vice versa. As shown in Fig. 2.7a, our inverter operates correctly. Its output levels are very close to the corresponding Voo and the low output levels are approximately 0. Considering Voo = 8 Vas an example, the output swing reaches 7.97 V (99.6% of Voo), which is much higher than the values for several previously published CNT-based inverters. 7 • 31 • 33 • 106 - 108 Ideally, one transistor of the complementary inverter is always off; however, during the switching state there will be a moment where both pull-up and pull- down circuits are on. As a result, there is a direct current flow from Voo to ground causing a power dissipation called dynamic short-circuit power. This power dissipation is directly proportional to Iomax, which is the peak value of the drain current of the Io-Vin curve. The Io-Vin characteristic of the inverter displayed in Fig. 2.7b is as expected. When the inverter 29 is operating in close proximity to either "O " or " 1" states, its Io is near zero, indicating infinitesimal power loss during this period. When switching, Io dramatically rises and reaches a maximum before attenuating to nearly zero. The voltage gain of the same inverter measured at different Voo ranging from 4 to 8 Vin 1 V steps is shown in Fig. 2.7c. At Voo = 8 V, the inverter manifested a sharp tum at the switching threshold, where the gain is 16.9. a Si=,,,..=--------, 7 6 - 5 2:. 4 5 3 > 2 1 Voo Vin -c~Vout Voo -4V - SV GND - 6V - 7V - sv 1 2 3 4 5 6 7 8 Vjn(V) b 2.0---------..... j 1.s c ~ 1.0 ::I (.) - ~ 0.5 ... C Voo -4V - sv - 6V - 7V - sv 0 · 0 o 1 2 3 4 5 6 7 8 Vjn(V) C 20..----------..... Voo -4V - sv - 6V - 7V - sv 0 o 1 2 3 4 5 6 7 8 Vin<V> Figure 2. 7 Characterization of a printed complementary inverter based on p-type CNT TFT and n-type IZO TFT. (a) Vour-VIN characteristics of one representative inverter measured under Voo = 4 V (black), 5 V (red), 6 V (green), 7 V (dark blue), 8 V (light blue), 30 respectively. (b) Switching current (ID-VIN) curves of the same complementary inverter with Voo = 4 V (black), 5 V (red), 6 V (green), 7 V ( dark blue), 8 V (light blue), respectively. (c) Gains of the same complementary inverter with VDD= 4 V (black), 5 V (red), 6 V (green), 7 V ( dark blue), 8 V (light blue), respectively. 2.4 Conclusions We have demonstrated desirable inkjet-printed complementary transistors and inverters based on CNT and IZO TFTs operated in enhancement mode. The CNT TFTs exhibited highest Ion of 9.5 µA, lonlio ff of 10 4 -10 6 and maximum mobility of 5 cm 2 /(V·s), and the IZO TFTs attained a highest Ion of 5 .2 µA, Ion! Io ff of 10 4 -10 6 and mobility as high as 14.1 cm 2 /(V ·s). In addition, experiments on alternative Ti/Pd electrodes showed that Ti/Pd metal contacts shifted the Vih of CNT TFTs to the positive side compared to devices with Ti/ Au metal contacts. Therefore, the Ti/ Au electrodes were preferred for this work since they enabled the CNT devices to operate in enhancement mode. Moreover, IZO TFTs with various In:Zn ratios, namely 1:1, 2:1 and 3:1, were investigated, and the ratio of 2:1 gave the optimum combination of Ion, lonlloff, mobility and enhancement-mode operation (Vih > 0). It is therefore the optimized composition of the IZO precursor solution. Finally, a complementary inverter was fabricated by sequentially printing IZO and CNT solutions as the active materials onto the same Si/SiO2 substrate with pre-patterned Ti/ Au electrodes. A maximum output swing of 99.6% of VDD and voltage gain of 16.9 (with VDo = 8 V) of the inverter were achieved. These results demonstrate that CNT and IZO are outstanding materials for p-type and n-type transistors, while inkjet printing technology allows the two 31 types of materials to be patterned on the same substrate to form a complementary circuit through a simple, reproducible and low cost approach. Our work has paved the way for future research where printed complementary circuits with more sophisticated logic and even superior performance can be expected. 32 Chapter 3: Top-Contact Self-Aligned Printing for High Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length 3.1 Introduction Semiconducting single-wall carbon nanotubes (CNTs) have been drawing growing attention in developing fully printed thin-film transistors (TFTs) due to their outstanding electrical and mechanical properties, solution-based low-temperature deposition process, and stability against oxygen and moisture. 12 • 64 • 78 • 109 - 111 Main-stream printing technologies such as ink-jet printing, 14 • 23 aerosol-jet printing, 24 • 26 • 31 screen printing, 15 • 65 gravure printing, 29 • 35 and flexographic printing 38 have been used for fabricating carbon nanotube thin-film transistors, which have great potential for applications in display electronics and sensing systems. 22 • 35 • 65 • 112 • 113 Those methods eliminate the need for high-vacuum environment and multi-stage patterning process, thus paving a way for scalable manufacturing of large-area, low-cost, and flexible electronics. Although previously reported fully-printed CNT TFTs 14 • 15 • 29 • 35 , 65 , 113 , 114 show satisfactory performance in terms of mobility and current on/off ratio, the channel lengths of such devices are rather large (>20 µm) due to the limitation of printing resolution and registration accuracy. Consequently, the on-state current densities of fully printed CNT TFTs in those papers are very low (in the scale of between 10- 1 µA/µm and 10- 5 µA/µm). 33 For example, our group published screen-printed CNT TFTs with 105 µm channel length and current density of ~ 10- 4 µA/µm. 15 , 65 Javey and Cho reported gravure-printed CNT TFTs with 85 µm channel length and current density of ~1.4x10- 4 µA/µm. 29 , 35 Ink-jet and aerosol-jet printed CNT TFTs with ion-gel gating have also been reported with 25-100 µm channel length and improved current density of~ 10- 1 -10- 3 µA/µm. 14 , 30 , 113 - 115 For one of the most significant applications, current driving for organic light emitting diodes, low on state current density of driving TFTs is disadvantageous since large channel width is needed to achieve desirable brightness of the integrated light-emitting devices, resulting in a low aspect ratio. Also, such long-channel TFTs are with low speed and high operation voltage, which may limit their applications such as radio-frequency transistors. 67 Overall, downscaling of fully printed CNT TFTs is necessary to further improve the performance and widen the potential applications for scalable manufacturing of large-area and low-cost CNT electronics. Previously, Sirringhaus's group pioneered a back-contact self-aligned printing (SAP) method to develop ultrashort-channel organic transistors. 67 , 116 However, due to the vulnerability of organic materials at high temperature required by sintering gold ink, the organic TFTs were configured by having the organic semiconductor layer on top of the printed electrodes, thus forming back contacts to the channel. This introduced a self assembled monolayer (SAM) between the semiconductor and metal contacts. As a result, the contact resistance may increase remarkably. In addition, as the channel length is downscaled to sub-micron scale, a small effective thickness of dielectric layer is required to have strong gating on the short-channel devices. 34 Here we report a facile and highly reliable top-contact self-aligned printing strategy to fabricate fully ink-jet printed, ultrashort-channel (sub-micron), and lateral-gate CNT TFTs on willow glass. In this study, we first printed the carbon nanotube network and then printed the electrodes to form top contacts with a sub-micron channel in between. Therefore, the gold electrodes were printed and sintered on the semiconducting CNT network and directly formed good Ohmic contacts, eliminating the SAM which may cause large contact resistance. 67 Furthermore, a high capacitance ion-gel material 117 has been employed as the dielectric material with an effective thickness of sub-nanometer scale provided by electrical double layer. 32 Thus we have further improved the on-state current density and lowered the operation voltage of our devices with the enhanced gating. The as-printed short-channel CNT TFTs show excellent performance with superior average on-state current density ( 4.5 µA/µm) at low operation voltage of gate voltage (Va)= -1.5 V and source-drain voltage (Vos)= -0.1 V, outstanding mobility (15.03 cm 2 v- 1 s- 1 ), and high current on/off ratio ( ~ 10 5 ). Compared with previously reported fully-printed CNT TFTs, we dramatically downscaled the channel length from tens of micrometers to sub-micron and realized the great improvement in current density by orders of magnitude. We believe the advantageous performance will be highly desirable for future large-area high-definition printed displays, electronic skins, radio frequency applications, and sensing systems. 3.2 Experimental Methods Printing of Lateral Gate Electrodes 35 Willow glass with a thickness of 200 µm was used as the substrate. Before printing, acetone sonication and isopropyl alcohol (IPA) rinsing were performed as surface cleaning steps. Gold nanoparticle ink (UTDAu40IJ, UT Dots, Inc.), with 40% gold nanoparticles dispersed in a hydrocarbon solvent, was printed using a SonoPlot printer (Microplotter Desktop, SonoPlot, Inc.) with a 50 µm glass nozzle. After printing, the printed gold ink was sintered in air at 250 °C for 1 h. Printing of CNT Channels A semiconducting-enriched SWCNT solution (IsoSol-SlO0, Nanointegris, Inc.) was defined in the channel region with a SonoPlot printer, followed by baking in air at 200 °C for 1 h. The quality of the printed CNT random network was examined using a field emission scanning electron microscope (Hitachi S4800). Printing of First Contact Electrodes The first gold contact electrodes were printed on top of the printed CNT film using the same printing conditions as the gate electrode, followed by a 1 h sintering at 220 °C in air. A slightly reduced sintering temperature was used to avoid damaging the printed CNTs. Self-Aligned Printing of Second Contact Electrodes First of all, the surface of the printed gold electrodes was modified with a SAM, 1H,1H,2H,2H-perfluorodecanethiol (PFDT) (97%, Sigma-Aldrich). Specifically, the sample was immersed in an IPA-diluted PFDT solution with a dilution ratio of 1:10 and was treated for 18 h, followed by IPA rinsing and nitrogen blow-drying. After the surface functionalization, xylene-diluted gold nanoparticle ink (gold ink:xylene=l :2) was printed 36 on the PFDT-treated surface of the first gold electrodes with a slight overlap. After the gold ink landed on the SAM-modified first electrode surface, it eventually dewet from the surface under repulsion force. After 5 min of slow drying in air, a sub-micron gap between the two electrodes was observed under an optical microscope. Then the printed second electrodes were sintered on a hot plate at 220 °C for 1 h. Optical microscope, AFM, and SEM were used to characterize the channel length. Printing of Ion-Gel Gate Dielectric Ion-gel ink was formulated by mixing a biblock copolymer of poly(styrene-block methyl methacrylate) (Sigma-Aldrich), an ionic liquid of 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide (EMD Chemicals), and n-butyl acetate (Sigma-Aldrich) in a ratio of2:9:90 in weight. SonoPlot printer with a nozzle of 70 µm was used to drop the ion gel on the device region covering the channel and the lateral gate. 3.3 Results and Discussion Ultrashort channel CNT TFTs are printed on flexible willow glass with lateral-gate device architecture and ion gel as the gate dielectric. In principle, any substrates which can go through the sintering temperature (~250 °C) for gold (to be discussed below) can be used, such as Si/SiO2, glass, polyimide, etc. Specifically, here we chose willow glass as our substrate for demonstration. As the first step, gold nanoparticle ink was printed as the lateral gate electrode, followed by sintering at 250 °C for one hour. As the second step, semiconducting-enriched single-wall CNT solution was printed and defined in the channel 37 region. The printed nanotube film was then annealed in air at 200 °C to let the solvent evaporate. As previously reported, 118 annealing at 400 °C in vacuum can remove the excess polymer. However, this temperature may be too high for some potential substrates such as polyethylene terephthalate (PET), and therefore is not used here. The quality of the printed nanotube film was then inspected using field-emission scanning electron microscopy (FESEM), and the SEM image (Figure 3.1) shows the highly-uniform clean nanotube random network. As the third step, the first gold electrode was printed to form a contact with the nanotube network (Figure 3.2a). After sintering in air for one hour, self-assembled monolayer (1H,1H,2H,2H-perfluorodecanethiol (PFDT)) functionalization was performed to modify the surface of the printed gold electrodes to be hydrophobic (Figure 3.2b). Right after the treatment, the second gold electrode was initially printed in a partially overlapping fashion with the first electrode (Figure 3 .2c ). The gold ink landing on the surface of the SAM-decorated first electrode was repelled by the hydrophobic surface, and a sub-micron gap between the first electrode and the second electrode usually formed about five minutes after the printing and when the solvent was drying. 116 , 119 We have observed that with 5- min slow drying in air after printing, the contact line of the second electrode, which initially overlapped slightly with the first electrode, has retracted from the surface of the first electrode, leaving a color contrast at the location where the second electrode has dewet from (Figure 3.3). The color contrast observed here may come from some residue of the ink solvent after the ink dewet. The sample was then sintered at 220 °C in air for one hour, which worked to remove surfactants from the printed gold particles and made the printed 38 gold electrodes highly conductive. After sintering, the color contrast observed in Figure 3.3a has disappeared completely (Figure 3.3b) due to solvent evaporation. The optical microscope image (Figure 3.2e) shows a sub-micron channel defined by the top-contact self-aligned printing, which was further characterized using atomic force microscopy (AFM) and FESEM. Figure 3.2f shows a well-defined channel of 400 nm with carbon nanotube random network within the channel. The fabrication process of the device completed with the printing of ion gel 117 as the gate dielectric (Figure 3 .2d). Once the ion gel droplet landed on the device, it spread out and formed a thin layer covering the channel region as well as the lateral gate. Thanks to the electrolytic gating nature of the ion gel, 117 lateral-gate device architecture can be used, which simplifies the printing process. Figure 3.1 SEM image of the highly uniform printed carbon nanotube network. 39 Printed Au lateral gate SAM Willo ~ s ..,,r '\ \ SAM functionalization Printed CNT network Ion gel Source & drain C Ion gel printing e Figure 3.2 Top-contact self-aligned printed ultrashort channel CNT thin film transistors. ( a-d) Schematic diagrams showing the fabrication process of a top-contact self-aligned printed ultrashort channel nanotube transistor. (a) Schematic diagram showing the ink-jet printing process of the first electrode on top of the pre-printed nanotube network. (b) Schematic diagram showing the surface functionalization of the electrodes with a self assembled monolayer. (c) Schematic diagram showing the self-aligned ink-jet printing process of the second electrode on the SAM-decorated surface of the first electrode before dewetting. (d) Schematic diagram showing the ink-jet printing of ion gel dielectric. (e) Optical microscope image showing two printed electrodes defined by top-contact self aligned printing technique and the ultrashort channel formed between these two electrodes. 40 (f) AFM and SEM images showing an ultrashort channel of 400 nm with nanotubes between two printed electrodes formed by self-aligned printing. (a} 5 min First Electrode (b} Sintered First Electrode Second Electrode 20µm Figure 3.3 (a) Optical microscope image showing the dewetting of the second electrode from the first electrode surface about 5 minutes after printing. The color contrast on the first electrode may come from solvent residue after the dewetting of the second electrode. (b) Optical microscope image showing the trace of solvent was removed after sintering due to solvent evaporation. The electrical performance of the fully printed ultrashort channel CNT TFTs was studied and shown in Figure 3.4. The transfer characteristics of a representative CNT TFT with channel length (L) = 400 nm and channel width (W) = 40 µm, measured under different drain voltages (Vos) from -0.1 V to -0.5 V in a step of -0.1 V, are presented in Figure 3 .4a, showing a typical p-type transistor behavior. Figure 3.4b exhibits the transfer curve of the representative device in logarithm scale under Vos= -0.1 V, clearly showing a high current on/off ratio of ~ 1x10 5 . The threshold voltage of this TFT is ~ -0.2 V. Due to the high capacitance of the ion gel gate dielectric, which is measured to be ~ 1.5 µF /cm 2 at 100 Hz (Figure 3.5), the transistor can be operated with a gate voltage (Va) ofless than -1.5 V and 41 achieve a high on-state current density of 5.68 µA/µm at Vos= -0.1 V. The average current density is 4.5 µA/µm , measured over 30 devices at Va= -1.5V and Vos= -0.1 V. The field effect mobility of this transistor is estimated to be 12.12 cm 2 v- 1 s- 1 , calculated with the standard linear regime relation, Iv =µCi: ( (Vcs - Vth)Vvs - Vis). Moreover, the gate leakage current as a function of gate voltage at Vos= -0.1 V is shown in the inset of Figure 3.4b, indicating a small gate leakage current ( <10 nA) for ion-gel gate dielectric. The output characteristics of the same device (Figure 3 .4c) show a typical current saturation for p-type (hole) transport due to the pinch-off effect. The linear region of the output curve (Figure 3.6) indicates Ohmic contacts were formed between the printed gold electrodes and the printed nanotube network. a o -150 i -300 C -450 -600 -750 - V 03 = -0.1 V - V05 =-0.2 V - V05 =-0.3V - V 05 =-0.4 V - V05 =-0.5 V -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 ?0.001 _c -0.002 -0.8 VG (V) VG -0.5 V - av - -0.5 - -1.0 - -1 .5 - -2 V 0.0 b 1000 100 _ 10 1 1 - _ '""E 10. 00 -0.01 -1.5 -1.0 -0.5Jt(Jr5 1.0 1.5 - 0 0.1 0.01 1E-3 -1 .5 -1.0 -0.5 0.0 0.5 1.0 1.5 d 10 ® VG (V) \ --- ~ 0.1 E ,✓ • ..... .,, This work 1 , -2- 0.01 <I'. 2,1E-3 ~~ 1E-4 _ o 1E-S I \ I .. \ \ .. \ \ I Other / \ I ✓ ' � • • I works ,_ 1 ' ~..:.-~/ 1 10 100 1000 Channel Length (µm) Figure 3.4 Electrical characterization of fully-printed ultrashort channel CNT TFTs on willow glass. (a) Transfer characteristics (Io-Va) of a representative ultrashort channel nanotube TFT (L=400 nm, W=40 µm) , measured at different Vos, from -0.1 V to -0.5 V 42 with a step of -0.1 V. (b) Transfer characteristics measured under VDs=-0.1 V showing a current on/off ratio of~ 1x10 5 . The inset of this figure exhibits the gate leakage current as a function of Vo at Vos=-0.1 V. ( c) Output characteristic (fo-V D) of the same device measured at different Va (from 0.5 V to -2 V with -0.5 V steps). (d) Comparison of channel length and on-state current density of printed CNT TFTs between this work, and other work. Our fully-printed ultra-short channel CNT TFTs demonstrate a great success in downscaling the channel length of printed nanotube transistors from tens of micrometers to sub-micron. In consideration of the solution based printing technique, we note that there is variation in the channel length within a single device and among different devices. We performed channel-length measurements of 9 devices with 15 different locations in each as shown in Figure 3.7a. The results show the channel length of self-aligned printed CNT TFTs is 496 ± 82 nm (Figure 3.7c, 3.7d). Our sub-micron nanotube TFTs show excellent electrical performance in terms of high on-state current density, low-voltage drive, outstanding on/off ratio and good mobility. Especially, our printed ultrashort channel TFTs show a dramatically improved on-state current density of 4.5 µA/µm at Vos= -0.1 V and Va = -1.5 V, which is several orders of magnitude higher than other printed CNT TFTs. Figure 3.4d clearly shows the comparison of channel length and the on-state current density for printed CNT TFTs between this work and other previous reported work. 14 , 15 , 27 - 3 o , 33 , 35 , 65 , 85 , 113 , 114 , 120 , 121 From Figure 3.4d, we can observe that our printed CNT TFTs have the shortest channel length and the highest on-state current density at a low drain voltage of - 0.1 V and a small gate voltage of -l .5V. Detailed comparison of all the representative printed CNT TFTs reported so far has been presented in Table 3 .1, including the printing 43 method, gate dielectric material, metal contact, on-state current density, etc. Based on Table 3 .1 , we can also conclude that our fully printed CNT TFTs have the smallest channel length and the best on-state current density. The ultrashort channel length may enable scaling up the number of transistors per unit area, which may be promising for applications such as printed CNT TFT active backplanes for high resolution sensing, display, etc. Moreover, the high current density at low-voltage operations makes these printed CNT TFTs good candidates for display applications and low-power-consumption portable electronics. _ 1.6 "'e (.) ii: 1.4 2: ~ 1.2 C: "' - -~ 1.0 Q. "' Frequency= 100 Hz ·, .. .. .. • • • • • 0 o.s---...... --...... --...... -- -2 ~ 0 1 2 Voltage (V) Figure 3.5 Capacitance-voltage characteristic for the printed ultrashort channel CNT TFT, measured at a frequency of 100 Hz. 2.0x10-s $ 0 -0.004 -0.002 0.000 vos M VG -0.5 - o - -0.5 - -1 .0 - -1.5 - -2 0.002 0.004 Figure 3.6 Output characteristic of the top-contact self-aligned printed ultrashort channel CNT TFT in linear region. 44 a b 700 ~ 600 E -S 500 .c g' 400 Q) -' <ii 300 C C "' 200 .c () 100 0 0 500 1000 1500 2000 2500 3000 x (nm) d 1000 C rn 30 900 c Device Q) E 800 Number E -S 700 ~ .c ;jl 20 0) 600 "' C Q) Q) -' 500 2 0 <ii 400 C a3 10 C "' 300 .0 .c E () 200 :::, z 100 0 400 600 800 0 500 1000 1500 2000 2500 3000 Channel Length (nm) x (nm) Figure 3. 7 Statistical data of channel length measurements on printed ultrashort channel devices. ( a) SEM image of printed ultrashort channel with 15 evenly spaced channel length measurements along the channel's x axis. (b) Plot of channel length measurements from (a). (c) Combined histogram of channel length measurements from 9 printed ultrashort channel devices. ( d) Combined plot of channel length measurements from 9 printed ultrashort channel devices. 45 Table 3.1 Comparison of on-state current density for printed CNT TFTs.~ Reference L Method Dielectric Electrode VG Vos Ion/W Year (µm) (V) (V) (µA/µm) This work 0.496 Ink-jet Ion Gel Au -1.5 -0.1 4.5 2016 Ref 85 100 Ink-jet Ion Gel Ag -1 0.1 0.075 2008 Ref 14 75 Ink-jet Ion Gel Ag 1 0.5 0.002 2011 (PEI/LiClO4) Ref 121 150 Gravure BTO Ag -1.5 -0.1 0.000013 2011 +Ink-jet Ref 30 200 Ink-jet Ion Gel Metallic -1.5 -0.1 0.003 2013 CNTs Ref 122 85 Gravure BTO+PMMA Ag -1.5 -0.1 0.00014 2013 Ref 15 105 Screen BTO Ag -1.5 -0.1 0.0001 2014 Ref 13 100 Gravure BTO Ag -1.5 -0.1 0.000016 2015 Ref 123 25 Aerosol Ion Gel Au/PEDOT -1.5 -0.1 0.18 2016 Ref 28 100 Aerosol SiO2 Ag (double -1.5 -0.1 0.00094 2016 layer) Ref 28 100 Aerosol SiO2 Metallic -1.5 -0.1 0.0014 2016 CNT Ref 28 100 Aerosol SiO2 Au -1.5 -0.1 0.0016 2016 Ref 120 350 Ink-jet Polymer Ag -1.5 -0.1 0.000015 2016 (PV3D3) Ref 124 105 Screen BTO Ag -1.5 -0.1 0.0001 2016 Ref 12s 150 Ink-jet BTO/PDMS Unsorted -1.5 -0.1 0.000064 2016 CNTs ~If values were not provided in the manuscripts explicitly, they were estimated from the I- V curves presented in the manuscripts. On-state current density of this work are the average value of 30 printed ultrashort channel CNT TFTs. In order to assess the uniformity of the fully-printed ultrashort channel CNT TFTs, 30 transistors with channel length of ~496 nm have been printed and the electrical performance has been tested. Statistics studies on the key device parameters, including the on-state current density, field-effect mobility, threshold voltage, and the current on/off ratio, of the 30 printed transistors have been conducted and presented in Figure 3.8. Judging from 46 the on-state current density distributions of the 30 printed CNT TFTs (Figure 3.8a), these devices show good uniformity with on-state current density of 4.5±2.5 µA/µm at Vos= - 0.1 V and Va = -1.5 V. We note that while the variation in channel length affects the variation in the on-current, it does not fully account for the on-current variation, as the variation in the CNT density can be another important factor. Field-effect charge carrier mobilities of the 30 printed TFTs are extracted from the transfer curves measured at Vos = -0.1 V. The statistic distributions of mobilities are shown in Figure 3.8b, illustrating uniform mobility with an average value of 15.03 cm 2 v- 1 s- 1 . Moreover, the transistors have threshold voltages of -0.45±0.22 V (Figure 3.8c). Furthermore, Figure 3.8d shows the distribution of current on/off ratios, with log1o(Ionllotr) of 4.81±0.56, which is comparable with previously published ion-gel-gated CNT TFT work. 26 The semiconducting-nanotube ink was purchased from Nanointegris Inc. with ultra-high purity of >99.99%, which is believed to be the reason of the observed high on/off ratio greater than 10 4 • As a result, even if 1 out of 10000 nanotubes is metallic, we should be able to obtain high on/off ratio. Overall, printing of ultrashort channel CNT TFTs with self-aligned printing approach is highly reliable and reproducible, and all of the printed sub-micron nanotube TFTs show highly uniform electrical performance. 47 a 18 b 8 16 lon/W 7 mobility 14 4.5±2.5 µA/µm 15.03±9.16 cm 2 V- 1 s- 1 6 $ 12 $ 5 C 10 C :I :I 4 0 8 0 (.) (.) 3 6 4 2 2 2 4 6 8 10 12 14 0 0 3 6 9 12 15 18 21 24 27 I on/W (µA/µm) Mobility (cm2v- 1 s- 1 ) C 18 d 20 16 V,h 18 Log,o(Io.florrl -0.45±0.22 V 4.81±0.56 14 16 12 14 II) 10 II) 12 - - C: C: 10 ::I 8 ::I 8 0 0 (J 6 (J 6 4 4 2 2 0 0 -1 .0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 2 3 4 5 6 7 v,h (V) log1o(l • .flo11) Figure 3.8 Statistics analysis of 30 CNT TFTs with L=496 nm printed with top-contact self-aligned printing technique. (a) On-state current density distributions of 30 TFTs measured at Va=-1.5V and Vos=-0.1 V. (b) Field-effect mobility distributions of 30 TFTs extracted from transfer characteristics measured at Vos=-0 .1 V. ( c) Threshold voltage distributions of 30 TFTs. ( d) Current on/off ratio distributions of 30 TFTs measured at Vos=-0.lV. 50 µm Figure 3.9 Optical images showing the printed CNT TFTs with different channel lengths, 40 µm , 120 µm and 150 µm. 48 a 10~-----------~ - 0.496µm 1 - 40µm - 120µm - 150µm 1E-5 1E-6 -1.5 -1 .0 -0.5 0.0 0.5 1.0 1.5 VG (V) b 10 f - E 1 ::i. --- t <( ::i. ._., ~c: 0.1 a 0 2 0 50 100 150 Chanel Length (µm) C 2.0 1.8 1.6 1.4 E 1.2 :,, a 1.0 e, s 0.8 ri:: 0.6 0.4 0.2 0.0 50 100 150 Channel Length (µm) Figure 3.10 Electrical characterization of printed CNT TFTs with different channel lengths. (a) Transfer characteristics of representative printed CNT TFTs with channel lengths of 496 nm (violet), 40 µm (red), 120 µm (green), and 150 µm (blue). (b) Statistical study of 45 printed CNT TFTs showing on-state current density as a function of channel length. ( c) Statistical study of 45 printed CNT TFTs showing width-normalized total resistance as a function of channel length. 49 In order to fully reveal the benefits of channel length downscaling, systematic comparison has been carried out between the printed CNT TFTs with 496 nm channel length and TFTs with channel lengths of 40, 120, and 150 µm (Figure 3 .9). A control group of 15 CNT TFTs have been printed with channel lengths of 40, 120, and 150 µm , following the same printing procedure as short channel devices. All of the printed TFTs with long channel lengths were electrically tested with exactly the same measurement parameters of the short channel devices, and the comparison has been made and presented in Figure 3 .1 Oa and 3 .1 Ob. Transfer characteristics of four representative CNT TFTs, with channel lengths of 496 nm, 40 µm, 120 µm, and 150 µm , are shown in Figure 3.10a, indicating a much higher on-state current density for the 496-nm CNT transistor compared to transistors with longer channel lengths. Figure 3.10b further shows the on-state current density of these printed transistors as a function of the channel length, exhibiting a decreasing trend of the on-state current density as the channel length increases. Moreover, the width-normalized total resistance (R • W) of CNT TFTs as a function of channel length is exhibited in Figure 3 .1 Oc. As channel length scales from 496 nm to 40, 120 and 150 µm, the R • W increases by a factor of 10, 34 and 50, respectively. When the channel length of transistors is downscaled to sub-micrometer scale, contact resistance becomes a critical factor limiting the current density, due to which the benefits of channel-length downscaling is partially lost. To study the contact resistance between the printed gold contacts and the printed nanotube film, transmission line method (TLM) was used to extract the contact resistance of the printed CNT TFTs with channel lengths from 400 nm to 150 µm. A TLM plot is 50 constructed and shown in Figure 3 .1 0c, exhibiting the total resistance of CNT TFTs as a function of channel length. The total resistance of CNT TFTs can be viewed as the sum of channel resistance and contact resistance. Thus, the contact resistance can be extracted using the TLM plot from the interception of linear fit and the resistance axis. This method yields a contact resistance of 12.5 ± 3.4 kQ·µm, which is comparable with previously reported values. 28 Overall, the printed ultrashort channel CNT TFTs show remarkably high on-state current density at low-voltage operation, which makes it promising for low-power consumption displays and portable electronics. By now, we have talked about the printing of CNT TFTs with sub-micron channel length using a top-contact self-aligned printing strategy. For future work, tunable channel length and channel width may be highly desirable for wide applications. The channel length of TFTs defined by the self-aligned printing technique is mainly determined by the repulsion force between the metal nanoparticle ink and the SAM-modified first electrode. Many factors can be adjusted to tune the channel length. First of all, by choosing different thiol-based self-assembled monolayers, the surface hydrophobicity of the first electrode can be altered and different channel lengths can be achieved. Second, the concentration of the self-assembled monolayer and the functionalization time may affect the hydrophobicity of the electrode surface and yield different channel lengths. Moreover, the viscosity of the metal nanoparticle ink can also be tuned to achieve the desirable channel length. The channel width of the printed TFTs is basically controlled by the printing process, which can be varied in a range from 20 µm to 1000 µm. In addition, many different kinds of ion 51 gels 32 have been reported so far, and can be used as the gate dielectric in replacement of the ion gel we used in this paper for the self-aligned printed transistors. Furthermore, the dielectric materials for the top-contact self-aligned printed TFTs are not limited to ion gel. Indeed, the top-contact self-aligned printing technique is compatible with various state-of the-art dielectric deposition technologies. Many dielectric materials can be deposited as the gate dielectric layer. For example, a thin layer ( ~ 20 nm) of atomic layer deposition ( ALD )- deposited aluminum oxide can be a great alterative dielectric material for the self-aligned printed TFTs. Last but not least, the top-contact self-aligned printing technique is not limited to CNT TFTs. Instead, a wide range of channel materials, such as two-dimensional transition metal dichalcogenide monolayers, organic materials (which can be stable up to 200-280 °C), etc., are compatible with this printing strategy and are worth of exploration. 3.4 Conclusion In conclusion, we have successfully downscaled the channel length of fully-printed CNT TFTs to sub-micron with a top-contact self-aligned printing technique, which bypassed the resolution limit of ink-jet printing technology. In addition, high-capacitance ion gel has been printed as the gate dielectric to further promote the on-state current density at low-voltage operation. Notably, the fully-printed sub-micron CNT TFTs exhibit superior electrical performance, with an outstanding average on-state current density of 4.5 µA/µm at Vo= -1.5 V and Vos= -0.1 V, large average carrier mobility of 15.03 cm 2 v- 1 s- 1 , and high 52 current on/off ratio of ~lx10 5 . Especially, our printed ultrashort channel CNT TFTs demonstrate a huge improvement in terms of on-state current density, which is several orders of magnitude higher than previously reported printed CNT TFTs. 14 , 15 , 27 - 3 o , 33 , 35 , 65 , 85 , 113 , 114 • 120 The successful channel-length downscaling and on-state current improvement make printed ultrashort-channel CNT TFTs a capable candidate as a low-cost, high- definition solution for display electronics, sensing systems, electronic skins, etc. 53 Chapter 4: High-Performance Sub-Micron Channel WSe2 Field-Effect Transistors Prepared Using A Flood-Dike Printing Method 4.1 Introduction Printing technology has potential to offer a cost-effective and scalable way to fabricate electronic devices based on two-dimensional (2D) transition metal dichalcogenides (TMDCs). However, previously reported printed 2D TMDC devices usually have rather long channel lengths in the scale of 13 µm - 200 µm, mainly limited by the resolution and the registration accuracy of the printing instrument. A large channel length would compromise the device performance, especially the on-state current density, resulting in a relatively low current-drive capacity (:S 0.02 µA/µm). A major reason is that, within such a long channel length, there exists a large number of either flake-to-flake junctions (for liquid-exfoliated TMDC nanosheet networks) or grain boundaries (for continuous TMDC films). Therefore, downscaling of the transistor channel length is desired to improve the device performance and enable potential applications. Previously, Sirringhaus et al. reported a back-contact self-aligned printing method for sub-micrometer FETs with organic materials as the channel materials, 67 • 116 while we reported a top-contact self-aligned printing method for sub-micrometer FETs with CNTs as the channel materials. 126 The traditional self-aligned printing method works in an 54 "overlap-dewet" fashion, meaning that the second metal electrode is intentionally printed to partially overlap with the self-assembled monolayer (SAM)-coated first electrode and then slowly dewets from the first electrode, yielding a sub-micrometer gap. 67 · 116 , 126 However, we have found that this traditional self-aligned printing strategy is not suitable when applied to 2D TMDCs due to the extraordinary wetting properties of the gold ink on the TMDC surface. Specifically, during the printing of the second electrode, the gold ink wets the surface of the TMDC flake so well that it affects the dewetting process of the second electrode, leaving a significant amount of short circuits. Hence, a modified self- aligned printing strategy needs to be developed for 2D TMDC materials. Here, we report a three-step "flood-dike" self-aligned printing method which can reliably produce sub-micrometer channels on 2D TMDC flakes. In this study, we chose CVD-synthesized monolayer WSe2 as the channel materials for demonstration. This printing strategy is highly compatible with other CVD-synthesized, mechanically exfoliated and liquid exfoliated 2D TMDC materials. As the first step, gold nanoparticle ink is printed on the WSe2 flake to form the first contact electrode. As the second step, a hydrophobic thiol SAM of 1H,1H,2H,2H-perfluorodecanethiol (PFDT) is utilized to modify the surface of the gold electrode by lowering the surface tension, making the surface highly hydrophobic. 67 · 119 The formation of SAM layer on the gold electrode surface is facilitated by the formation of Au-S covalent bonds between the thiol SAM and gold, 127 while the thiol SAM does not assemble on the pristine WSe2 surface or the bare Si/Si02 surface. 119 As the last step, gold ink is printed close to the first electrode with a certain 55 distance. Due to the good wettability of the gold ink on the WSe2 surface, the ink will "flood" towards the first electrode and then be stopped by the hydrophobic SAM coating on the first electrode, ending up drying in close proximity, but not electrical connected, with the first electrode. With this "flood-dike" self-aligned printing method, we have successfully formed gold contacts on WSe2 flakes with ~ 750 nm channel lengths with ~90% yield. The as-printed WSe2 FETs show dramatically improved on-state current densities of ~ 0.64 µA/µm (average), high on/off current ratios of ~ 3x10 5 (average), and good field effect mobilities of ~ 1.0 cm 2 /Vs (average). Compared to previously reported printed 2D TMDC FETs, we have successfully downscaled the channel length to sub-micrometer scale and promoted the on-state current density by several orders of magnitude. Furthermore, with these superior printed WSe2 transistors, we have successfully demonstrated the driving capabilities for quantum dot (QD) light emitting diodes (LEDs), inorganic LEDs, and organic LEDs. Overall, our work offers a lithography-free low-cost platform to produce high-performance 2D TMDC electronics and may enable display backplane, sensing and many other potential applications. 4.2 Experimental Methods Ultrafast CVD Growth and Transfer of High-Quality Monolayer WSe2 on Au Foils We grew high-quality monolayer WSe2 on Au foils by ambient-pressure CVD, as reported previously. 128 A piece of polycrystalline Au foil (99.95 wt %, Alfa Aesar) was well treated with fine polishing and annealing at 1040 °C for over 10 h to reduce its surface 56 roughness before the first use. Then, it was placed in a small quartz boat together with 100 mg of WO3 powder (99.998 wt%, Alfa Aesar) upstream and loaded at the central zone of a horizontal CVD furnace equipped with a I-inch-diameter quartz tube. Another small quartz boat that contains 1000 mg of Se pellets (99.99 wt%, Sigma-Aldrich) was placed upstream at the low-temperature zone of the furnace. The Au substrate was first heated to 800-950 °C in an Ar atmosphere (100 seem) and then annealed for 2 min to remove the organics absorbed on its surface. Then we introduced a small flow rate of H2 (0.5 seem) to initiate WSe2 growth. After 1 min, we rapidly stopped the growth by quickly moving the two boats to the low-temperature zone. For structural characterization and device fabrication, the electrochemical bubbling method 128 - 130 was used to transfer monolayer WSe2 from Au foils onto Si substrates with a 285 nm SiO2 dielectric. Materials Characterization Raman and PL measurements were performed with a 561 nm laser (Renishaw Raman system). AFM (Digital Instrument, DI 3100) was conducted to inspect the thickness of the as-grown WSe2 samples. AFM and SEM (Hitachi S4800 with an electron accelerating voltage of 1 kV) were used to inspect the channel length of the printed WSe2 FETs. Three-Step "Flood-Dike" Printing Method The first Au electrodes were printed onto the CVD WSe2 flakes using an inkjet printer (Mi crop lotter Desktop, SonoPlot, Inc.) followed by sintering at 220 °C for 1 h to remove the solvent in the Au inks (UTDAu40IJ, UT Dots, Inc.). Then, the sample was immersed in a solution consisting of PFDT (97%, Sigma-Aldrich) and isopropyl alcohol (IPA) in a 57 volume ratio of 1: 10 for 18 h. During this functionalization step, PFDT molecules will be selectively deposited on the surface of the first printed electrodes, forming a self-assembled monolayer. This selective deposition of PFDT on the Au surface was facilitated by forming Au-S covalent bonds between Au and thiol. 127 After functionalization, the sample was gently rinsed with IP A and blown dry with N2 gas. In the last step, a xylene-diluted gold ink (gold ink:xylene = 1 :2) was used to print the second electrodes close to the previous electrodes. A clear screening effect of the ink flow can be observed. The sample was sintered at 220 °C for another 1 h to remove the solvent in the second electrodes. 4.3 Results and Discussion Sub-micrometer WSe2 FETs were printed on Si/SiO2 (285 nm oxide) substrate with back-gate device structure. To start, high-quality monolayer WSe2 flakes were synthesized using an ultrafast catalytic growth method on reusable gold foils, 128 and then were transferred onto Si/SiO2 (Figure 4. la) by a nondestructive electrochemical bubbling method 128 - 130 to initiate the three-step "flood-dike" self-aligned printing process. As the first step, gold nanoparticle ink was printed with an inkjet printer on the WSe2 flake to form top contact (Figure 4.1 b ), followed by sintering in air at 220 °C for one hour to remove the solvent. We used X-ray photoelectron spectroscopy (XPS) to examine WSe2 after the annealing step and the XPS data (Figure 4.2) indicated slight oxidation of WSe2, which is qualitatively consistent with our previous observation. 131 As the second step, a thiol-based perfluorinated SAM (1H,1H,2H,2H-perfluorodecanethiol (PFDT)) was used to 58 functionalize the surface of the first electrode to make it repulsive to gold ink (Figure 4.lc). Lastly, the second electrode was printed close to the edge of the first electrode with a certain distance (Figure 4.ld, 4.le). After the fresh gold ink contacted the surface of CVD WSe2, it spread on the flake and flooded towards the edge of the first electrode (Figure 4.le), due to the good wetting property between the gold ink and the WSe2 flake. The SAM coating on the first electrode served as a "flood-dike" and blocked the ink flow of the second electrode from touching the first gold electrode, yielding a sub-micrometer channel in between (Figure 4. lf). The sample was then sintered in air at 220 °C for one hour to conclude the printing process. a CVD C e -- -- ----- ---- -- -- -- Printing of 1 st Au Electrode ~ " Flood-Dike" Printing of 2"' Au E lectroj e b ---------- / / / Sub-Micron Channel f / ,- ✓---~S~ AM~--------; Figure 4.1 "Flood-dike" self-aligned printing of short channel FETs based on CVD WSe2. (a) Schematic diagram showing a single monolayer triangle-shape WSe2 flake transferred on Si/Si02. (b-d) Schematic diagrams showing the three steps of the "flood-dike" self- 59 aligned printing method, including (b) printing of the first gold electrode, ( c) functionalizing the surface of the first electrode with SAM, and ( d) printing of the second gold electrode close to the first one. (e) Zoomed-in schematic diagram showing the gold ink of the second electrode flooding towards the first electrode right after landing on the WSe2 surface. (f) Zoomed-in schematic diagram showing the gold ink gets stopped by the SAM "flood-dike", forming a short channel in sub-micron scale. a As-grown b 220 °C 4f7/2 WSe 2 WSe 2 - - ::::i 4f7/2 ::::i 4f5/2 ~ ~ >, >, wox - - "iii "iii 4f7/2 C: C: (I) (I) - - C: C: 40 38 36 34 32 30 40 38 36 34 32 30 Binding Energy (eV) Binding Energy (eV) Figure 4.2 XPS studies of CVD monolayer WSe2. (a) XPS spectrum of a W 4f core level of CVD monolayer WSe2 on Si/SiO2 before air annealing. The blue solid line represents the experimental data. The orange dashed lines are Lorentzian fits for the peaks of WSe2. (b) XPS spectrum of a W 4f core level of CVD monolayer WSe2 on Si/SiO2 after annealing in air at 220 °C for 2h. The black solid line represents the experimental data. The dashed lines in orange and green represent Lorentzian fits for the peaks of WSe2 and WOx, respectively. a Figure 4.3 EDX mapping of Au and Son the surface of the printed gold electrode and SiO2 substrate after SAM treatment. The mapping area is shown in (a). We used both energy-dispersive X-ray (EDX) and contact angle measurement using 60 water droplet to confirm the selective formation of the SAM on the surface of the first gold electrode (Figure 4.3 and 4.4). In addition, we have studied the wetting between the gold ink and WSe2 surface, SiO2 surface, fresh gold surface, and SAM-treated gold surface via contact angle measurements (Figure 4.5). The good wettability of the gold ink on the WSe2 surface was verified by contact angle measurement of a sessile gold ink drop on the WSe2 surface, showing a static contact angle of 4.8° (Figure 4.5a). Specifically, the gold ink used in our study was gold nanoparticle solution with a weight concentration of 40% (purchased from UTDots). For the self-aligned printing of the second electrode, we diluted the gold ink with xylene with a volume ratio of 1 :2. We believe the good wettability of the gold ink on the WSe2 surface can be attributed to the non-polar nature of xylene used to dilute the gold ink and the dispersive nature of WSe2 surface, 132 as evidenced by the rather small contact angle of ~6.6° of a xylene drop on the WSe2 surface (Figure 4.6). 61 a DI water on Au C DI water on WSe 2 e DI water on SiO 2 7 4 . 7 ° b DI water on SAM-Au 96.1 ° d 29.2 ° f DI water on WSe 2 after SAM treatment DI water on SiO 2 after SAM treatment 116.7° 95.8 ° 29.0 ° Figure 4.4 Representative optical images of water drops on (a) Au surface, (b) SAM treated Au surface, ( c) WSe2 surface, ( d) WSe2 surface after SAM treatment, ( e) Si02 surface, and (t) Si02 surface after SAM treatment. a Au ink on WSe 2 4.8 ° b Au ink on SiO 2 12.4 ° - -----~--- C Au ink on Au 3.9 ° d Au ink on SAM-Au 70.60 ° Figure 4.5 Representative optical images of gold ink drops on (a) WSe2 surface, (b) Si02 surface, ( c) fresh Au surface, and ( d) SAM-treated Au surface. 62 Xylene on WSe 2 6.6° Figure 4.6 Representative optical image of xylene drop on WSe2 surface. High-quality monolayer WSe2 was synthesized with a recently reported CVD-based ultrafast growth method on gold foils. 128 The ultrafast growth rate (~26 µm/s) and the reusability of the gold foil allow a cost-effective and energy-saving way to produce large size WSe2 within a minute. After growth, a nondestructive electrochemical bubbling method 128 - 130 was adopted to transfer the as-synthesized monolayer WSe2 flakes to Si/Si 02. Figure 4.7a shows the optical microscope image of a typical transferred triangular WSe2 flake on Si/SiO2. This particular flake has a lateral size of 187 µm. Atomic force microscopy (AFM) inspection was performed on this WSe2 flake as shown in Figure 4.7b. The cross-section height profile along the white dashed line presents a clear step with a height of ~0.8 nm which is close to the thickness of a monolayer WSe2. The wrinkles on the WSe2 flakes were formed during the CVD synthesis mainly due to the thermal coefficient mismatch between gold and WSe2. 128 Raman and photoluminescence (PL) spectra were further conducted to verify the properties of the CVD-grown WSe2. Figure 4.7c is a Raman spectrum measured with an incident laser of 561 nm, where both in-plane E}g and out-plane A 1 g characteristic peaks can be clearly observed. Meanwhile, no Raman peak for B}g mode was found, indicating the monolayer status of the CVD-grown 63 WSe2 samples. In addition, the monolayer feature was further confirmed by PL measurements where a sharp PL emission peak appeared at ~ 752 nm, corresponding to the direct band gap transition of monolayer WSe2 (Figure 4.7d). a C 200 e Monolayer A,, B' r 250 300 350 400 Raman Shift (cm·') Printed 2 nd Au Electrode - ' Printed 1 st Au Electrode ' ' ' ' ' ' ' 450 ' ' ' ' ' b d f ' ' 650 ' ' 700 750 800 Wavelength (nm) 850 Figure 4.7 (a-d) Images and characterizations of CVD monolayer WSe2. (a) Optical microscope image showing a typical triangle-shape monolayer WSe2 flake transferred to 64 Si/SiO2. This particular flake is~ 187 µm. (b) AFM image of the WSe2 flake in (a) along with the cross-section height profile of the white dash line. The thickness of this flake is measured to be ~0.8 nm corresponding to a monolayer TMDC. (c) Raman spectrum of a typical transferred WSe2 flake showing the two characteristic peaks of E} 9 mode and A 19 mode. (d) PL spectrum of the same WSe2 flake in (c) showing a strong PL peak at ~752 nm, confirmed the monolayer status. ( e) Optical microscope image of a sub-micron channel defined by the "flood-dike" printing approach. (t) AFM and SEM (inset) images showing a clearly-defined gap measured to be~ 750 nm. After the three-step "flood-dike" printing process, the as-formed ultra-short channels were first examined using optical microscopy. Figure 4.7e shows a representative optical microscope image of an ultra-short channel defined by the "flood-dike" printing method (more images are shown in Figure 4.8 and Figure 4.9). From this image, a clean gap can be seen between the two printed gold electrodes. A representative low-magnification optical microscope image can be found in the Figure 4.10. AFM was used to further characterize the channel area to get an accurate estimation of the channel length. Based on the AFM characterization of 24 devices, the channel lengths fell in the range of 500 nm - 750 nm with little device-to-device variations. Figure 4.7f shows the AFM image of the channel region of the device shown in Figure 4.7e, with a measured channel length of~ 750 nm. SEM characterization (inset of Figure 4. 7t) of the same device confirmed the channel length to be~ 750 nm. 65 a 2 nd Au Electrode 1 st Au Electrode b 2 nd Au Electrode C l5 1 Au Electrode Figure 4.8 Optical microscope images showing three typical printed WSe2 FETs with sub micron channel lengths, fabricated using the "flood-dike" printing method. Figure 4.9 SEM image showing a typical sub-micron channel formed by "flood-dike" printing method. 66 2 nd Au Electrode 1 st Au Electrod 2 nd Au E1ectrode • Figure 4.10 Representative zoomed out optical microscope image showing two printed sub-micron channel FETs on a single WSe2 flake. The electrical performance study of the printed ultra-short channel back-gated WSe2 FETs was conducted and presented in Figure 4.11. All the transfer and output characteristics of the WSe2 FETs were carried out in an ambient condition. Figure 4. lla shows the transfer characteristics (Jo-VG) of a representative WSe2 FET, with a channel length (L) of 750 nm (measured by AFM, as shown in the inset of Figure 4.1 la) and a channel width (W) of 30 µm, under different drain voltages (Vos) from -0.5 V to -2.0 Vin a step of -0.5 V. A clear unipolar p-type behavior was observed from the transfer characteristics, consistent with previously reported CVD-WSe2 FETs with transferred gold contacts. 128 The success in channel length downscaling allows the printed WSe2 FET to achieve a high on-state current density (/on/W) of 0.78 µA/µm at VG= -100 V and Vos= -2 V. The same transfer characteristics were also plotted in a logarithmic scale to extract on/off 67 current ratio (/onlloff) (Figure 4.11 b ). Figure 4.11 b clearly shows that the printed ultra-short channel WSe2 FET has a high IonlloffOf ~ lxl0 5 at Vos= -2 V. The effective mobility (µeff) under Vos= -2.0 V was extracted with a value of 1.19 cm 2 Ns which is comparable with the previously reported values for CVD mono layer TMDCs; 52 · 72 • 75 however this value is lower than the reported values (100-150 cm 2 Ns) for the same kind of WSe2 with transferred electrodes. 128 The reason could be the transferred electrode method minimizes the damage on WSe2 during the device fabrication process, while our printed devices may have more defects because of the multiple-step treatment process. In addition, the molecular residue from surfactants used in the gold ink may contaminate the Au/WSe2 interface, which will decrease the mobility as well. We believe this mobility still has significant room for further improvement by optimizing the device fabrication parameters and finding better ways to engineer or treat the gold ink. Output characteristics (Jo-Vos) under small Vos bias (Figure 4.11 c) are very linear, suggesting Ohmic contacts between the gold electrode and WSe2. When large Vos bias was applied, a clear current saturation can be observed due to the pinch-off effect (Figure 4.11 d), which is typical for p-type (hole) transport. 68 b 1E-4 a 0 qr Vos 1E-5 -4 - --0.S V Vos -•- -1 .0 V 1E-6 -8 -•--0.5 V . : • -•- -1.5 V -•- -1 .0 V • , 1E-7 ... -•- -2.0 V ? -•- -1 .S V 1 -12 •~ : -•- -20 V ~ - 1E-8 !~ 0 0 -16 I ' - ~ 1E-9 ~ -20 I l 1E-10 -24 1E-11 -100 -50 0 50 100 -100 -50 0 50 100 VG (V) VG(V) C d 0 •=•=•=•=•=•=•=•~ ~=•=•=• = • = • • ·· •~• '~ 8 :=:=:=:=:=:=:===:_ · ::::::::==~!~- ~ - ~ ... •-•-•-•-•-•-•-·-~ -· ?.: 4 -10 - -- - -- - · - · -·-·:: .. _ ......... .,,..✓• ........ .... . ~ ~ ......... -• ,,.•.,, ---·- ........ • 2; 0 2; -· ,,•\ 0 !- ! --=l= e ~ 0 .... . ........... •,,,..,,,.• ::::::::::;::::::=~ · -20 ........... ,,,..,,. V 0 from 0 V to -100 V -- ~= ........ ....... -4 .- in -10 V steps .- :1/" .- .- .- -8 -30 -2 -1 0 2 -10 -8 -6 -4 -2 0 Vos (V) Vos (V) Figure 4.11 Electrical characteristics of the printed ultra-short channel WSe2 FET with a back-gate device structure. (a) Transfer characteristics (Jo-Va) of a typical WSe2 FET (l = 750 run, W = 30 µm) measured under different Vos from -0.5 V to -2.0 Vin a step of -0.5 V. The inset shows the AFM image of the channel, measured to be 750 run. (b) The same transfer characteristics plotted in a logarithmic scale showing an Ion! lofI ratio of 1x10 5 . ( c, d) Output characteristics (Jo-Vos) of the same device measured under different Va from 0 V to -100 V in a step of -10 V, with ( c) showing the low Vos region and ( d) showing the high Vos region, respectively. 69 a C e 1E-3------------- 1E-4 1E-5 1E-6 V 05 =-2V DC Integration time -•-0.64 ms -•- 20 ms -•- 100 ms 1E-12+---r-~--.-----~----,--~-r-~--,--+ 1E-3 1E-4 1E-5 1E-6 <( 1E-7 0 1E-8 ' 1E-9 1E-10 1E-11 1E-12 100 90 80 ~ 70 (JJ 60 'iii ~ 50 Q) u:i 40 >, I 30 20 10 -100 -50 Pulse VG V =OV base V 05 =-2V 50 100 tperiod ( S) -•-10"' - • - 10"' -•- 1 to, = 10-3 s -100 -50 0 50 100 VG(V) Long Medium Short Pulse Pulse Pulse 100ms 20 ms 0.64 ms period period period 10ms 100 ms 1 s b d f 40 30 45 40 35 30 25 ~ 20 3 0 15 ' 10 5 0 -5 8x10 12 7x10 12 6x10 12 c-:iE sx10,2 .3,4x10 12 Q. i" C-3x10 12 2x10 12 1x10 12 DC t-..... \\ ' · .... -100 -100 • Long 100 ms • ,. \, "Forward \ . \ . \ .' -50 v:(V) Pulse V G V = OV base V D$ = -2 V fotward -50 0 VG(V) • • • Medium Short Pulse 20 ms 0.64 ms period 10ms 50 Integration time -•-0.64 ms -•- 20 ms -•- 100ms V 05 =-2V 100 tperiod (S) -·-10"' -·- 10"' -·- 1 to, = 10- 3 s 50 100 • • Pulse Pulse period period 100 ms 1 $ Figure 4.12 (a) Logarithm and (b) linear scale of the ID-Va characteristics of a representative WSe2 FET measured using DC method under VDs = -2 V and different integration time of 0.64 ms, 20 ms and 100 ms. ( c) Logarithm and ( d) linear scale of the ID-Va characteristics of the same WSe2 FET measured by pulse I-V method, with different pulse period (tpe riod) varying from 10- 2 s to 1 s under a constant pulse width (ton) of 10- 3 s. The base of Va was set to be 0 V and VDs was -2 V. (e) Comparison of hysteresis (~V) between the forward and backward sweeps for the transfer characteristics of the WSe2 FET, measured by the conditions in (a-d). The hysteresis was extracted based on the pink dashed line in (a) and (c), where -ID= 1 nA. (f) Trap density (ntrap) of the device under different 70 measurement conditions, estimated using ntrap = Cox X LlV /e, where Cox= 1.21x10- 8 F/cm 2 for 285 nm SiO2. Study of the hysteresis of the transfer characteristics of the printed WSe2 FET can be found in Figure 4.12. Figure 4.12a and 4.12b show the double-sweep transfer characteristics of the representative WSe2 FET shown in Figure 4.11, plotted in both logarithm scale (Figure 4.12a) and linear scale (Figure 4.12b ), measured under varying integration time of 0.64 ms, 20 ms and 100 ms, from which the hysteresis can be clearly observed. We believe the hysteresis originates from the absorption of moisture on the WSe2 surface or the charge trapping at the WSe2/SiO2 interface. 133 - 135 By decreasing the integration time, less hysteresis was observed (Figure 4.12a, 4.12b, and 4.12e ), because shorter integration time reduces the measuring time and thus reduces the Va stress. The hysteresis can be further reduced using pulse 1-V measurement method, as shown in Figure 4.12c-e, because the trapped charges caused by Va stress when Va pulse was on can be detrapped when Va pulse was off, which resulted in less charge traps (Figure 4.12f) and less hysteresis. At constant Va pulse width (ton) of 1 ms, by increasing the pulse period (tperioct), the off time when Va= Vsase = 0 V can be increased, so the trapped charges can have longer time to be detrapped, which reduces the hysteresis of the WSe2 FET (Figure 4.12c-f). 71 a 8 6 Cf) c 4 ::::, 0 u 2 0 - Average l 0 nfW ~o.64 µA/µm - - f-- I I I 1h ~O ~4 ~8 1.2 1B 20 1 0 /W (µA/µm) C 6.....-----------~ 5 4 2 C 3 :::; 0 (.) 2 0 Average Mobility ~ 1.009 cm 2 /Vs 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Mobility (cm 2 Ns) b 12.....---------------. Average l 0 nfl 0 ff 10 ~ 3x1QS 8 .l!l C 6 ::::, 0 (.) 4 2 d 0.8 0.6 E :::t ~ 0.4 :::t - s 0.2 --- C: _o 0.0 100 2 3 4 5 6 7 log10< 1 o/ 1 orr) .... Kelly, 2017, L = 120 µm ... Kelly, 2017, L = 200 µm @ Kim, 2016, L = 100 µm Kim , 2017, L = 100 r,m / • Li, 2014, L = 13 µm This work * This work, L = 750 nm Lithography-patterned Au contacts ~ • ... 10' 102 103 10• 10' l 00 /l 0 ff Ratio 106 Figure 4.13 ( a-c) Statistic Analysis of 24 sub-micron WSe2 FETs printed using the three step "flood-dike" printing method. (a) Histogram showing the on-state current densities (JonlW) distribution measured at Vos= -2 V and Vo= -100 V. (b) Histogram showing the on/off current ratio (Jonllorr) distribution, extracted at Vos= -2 V. (c) Histogram showing the field-effect mobility distribution extracted from lo-Vo curves measured at Vos= -2 V. ( d) Comparison study of on-state current density and on/off current ratio between this work and previously reported printed TMDC works. In order to assess the reliability and uniformity of the "flood-dike" printing method, 24 back-gated FETs have been printed on Si/SiO2 based on ultrafast-CVD mono layer WSe2 and their electrical characteristics have been tested. Key device parameters, such as lonl W, Ion! lofI, and µ eff, were extracted from the transfer characteristics and systematic statistics 72 analysis was carried out, as shown in Figure 4.13. Figure 4.13a shows the distribution of on-state current density for these 24 devices measured at Vos= -2 V and VG= -100 V. The on-state current densities fell in the range of 0.07-1.86 µA/µm with an average value of 0.64 µA/µm. The distribution of the on/off current ratio (Figure 4.13b) shows good uniformity with an average value of 3x 10 5 . Furthermore, the distribution of the field-effect mobilities of these devices is presented in Figure 4.13c, with an average mobility of 1.0 cm 2 Ns and the highest mobility reaching 3.6 cm 2 Ns, which is much higher than the values for TMDC nanosheet networks 73 • 74 and comparable to the previously reported CVD TMDC with printed contacts. 72 Regarding the device-to-device variations in the on-state current density and mobility, we believe an important factor can be the material quality variation from location to location, and from flake to flake. This degree of device-to-device variation is actually comparable to the variations observed in other WSe2 FETs with fabricated metal contacts. 131 • 136 Besides this factor, we believe other factors, such as wrinkles on the WSe2 flakes, contact resistance variation and channel length variation may also contribute to the device-to-device variations. To fully reveal the advantages of using "flood-dike" printing strategy for printed TMDC electronics, a comparison of the on-state current density and on/off current ratio was carried out (as shown in Figure 4.13d), between this work and previously reported printed TMDC works. 72 - 75 Benefiting from the successful downscaling of the transistor channel length, our printed monolayer WSe2 possesses a significantly enhanced on-state current density of 0.64 µA/µm (average), which is much higher than previously reported 73 values (Figure 4.13d). At the same time, the printed sub-micrometer WSe2 FETs have the highest on/off current ratio of 3x 10 5 (average). 72 - 75 We note that previously reported printed 2D TMDC works and this work have used different TMDC species (e.g. M0S2, WSe2, etc.), different material preparation methods (e.g. liquid exfoliation and CVD), different dielectric materials (e.g. Si 02, poly( 4-vinylphenol), ionic liquid and boron nitride/ionic liquid), different contacts (e.g. printed Au, printed Ag, printed poly(3,4- ethylenedioxythiophene) polystyrenesulfonate, printed graphene nanosheet network and fabricated Au), different device structures (e.g. top-gate, back-gate), and different measurement conditions (e.g. different Vos, VG ). The data points presented in Figure 4.13d were extracted from the electrical characteristics measured at comparable gate voltages and drain voltages. Specifically, the magenta-color data point represents IonlW of 6xl 0- 7 µA/µm and Ionllo tr of 3 at VG= -30 V and Vos= 1 V, for back-gated FETs with printed M0S2 ink as channel, printed Ag contacts, and 300 nm SiO2 as dielectric. 73 The light-green data point shows IonlW of 0.003 µA/µm and Ionllo tr of 22 at VG= -2.5 V and Vos = 1 V, for printed WSe2 nanosheet network FETs with printed graphene network electrodes and boron nitride/ionic liquid hybrid dielectric. 74 The dark-green data point represents IonlW of 0.09 µA/µm and Ionll otr of 100 for printed WSe2 nanosheet network FETs with lithography patterned Au contacts and ionic liquid as the dielectric. 74 The on-state current density of these solution-processed TMDC network devices is mainly limited by massive flake-to flake junctions existing in a long channel with channel length in a scale of 13-200 µm. Moreover, the dark-blue data point shows IonlW of 0.02 µA/µm and Ionlio ff of over 10 4 74 measured at Vos = 2V and Va = 20 V for CVD monolayer M0S2 FETs with printed Ag contacts and 270 nm SiO2 gate dielectric. 72 Last but not least, the light-blue data point represents Ion!Wof 0.0005 µA/µm and IonlloffOf 10 3 measured at Vos= 1 V and Va= 80 V for CVD monolayer M0S2 FETs with printed poly(3,4-ethylenedioxythiophene) polystyrenesulfonate (PEDOT:PSS) contacts and poly( 4-vinylphenol) (PVP) gate dielectric. 75 With CVD-synthesized continuous M0S2 film, a significant amount of grain boundaries can exist within a channel of 100 µm, which would consequently compromise the on-state current density. 72 , 75 Detailed comparison between this work and other reported works can be found in Table 4.1. To sum up, the CVD monolayer WSe2 sub-micrometer FETs fabricated using the "flood-dike" printing method show clear advantages in terms of high current-driving capacity and good on/off ratio, offering a great platform for making high-performance TMDC macroelectronics aiming for potential display backplane and sensing applications. Table 4.1 Comparison of the device performances for printed 2D TMDC FETs Reference Channel Contacts Dielectric L Vos VG lonlW 1 0.llorr µ ,rr Year (µm) (V) (V) (µA/µm) (cm 2 /Vs) This work CVO Printed Au SiO2 0.75 -2 -100 0.64 300000 1.00 2017 WSe, (285 nm) Kelly eta/., MoS, Fabricated Ionic 120 I 2 0.22 100 0.15 2017 Science ink Au liquid Kelly etaL, ws, Fabricated Ionic 120 I -2 0.19 600 0.22 2017 Science ink Au liquid Kelly eta/., WSe, Fabricated Ionic 120 I -2.5 0.09 100 0.08-0.22 2017 Science ink Au liquid Kelly et al, WSe, Printed BN/ionic 200 I -2.5 0.003 22 0.08-0.22 2017 Science I ink I graphene I liquid I I I I I I I 75 networks I I I Kim et al., CVD Printed Ag SiO, 100 2 20 0.02 > 10000 18 2016 ACS Nano MoS, (270 nm) Kim etal., CVD Printed Printed 100 1 80 0.0005 1000 0.27 2017 ACS Nano MoS, PEDOT:PSS pyp Li et al., MoS 2 Printed Ag SiO2 13 1 -30 0.0000006 3 - 2014 Advanced ink (300 nm) Functional Materials On the basis of the enhanced current-driving capacity, high on/off current ratio, and decent mobility of the printed ultra-short channel monolayer WSe2 FETs, we further explored their applications in display backplane electronics. As a proof of concept, we connected a typical printed WSe2 FET (L = 750 nm, W=l42 µm) to an external quantum dot-based double heterojunction nanorod LED (QDLED), inorganic LED and organic LED (OLED), respectively, to demonstrate the LED modulation capability of our printed WSe2 device. The transfer characteristics of this particular WSe2 FET can be found in Figure 4.14. The schematic diagrams of the testing circuit are shown in the insets of Figure 4.18. Firstly, when the printed FET was connected to an external QDLED (the energy band diagram and structure shown in Figure 4.15), the current flowing through the QDLED (JQDLED) was measured as a function of Va at VDD from 1.5 V to 4 Vin 0.5 V steps (Figure 4.18a). As VDD = 4 V, lQDLE D was as high as 240 µA at Va = -100 V, and as low as 3 nA at Va = 100 V, corresponding to a modulation of lQDLED of 8x10 4 . A family of lQDLED-VDo curves at different Va from O V to -100 Vin -10 V steps (Figure 4.18b) show a good diode behavior with a clean cutoff region and triode region at different Va, which suggests a good control 76 over the QDLED. From Figure 4.18b, the cutoff voltage of Voo is~ 1.7 V, in accordance with the tum-on voltage of the QDLED (1-V characteristics of the QDLED shown in Figure 4.15c ). 137 Figure 4.18c shows a series of photographs of the QDLED taken under different Vo when Voo was fixed at 4 V, illustrating the light intensity modulation. The QDLED was the brightest when Vo = -l 00 V (1 st image in Figure 4.18c) and got gradually dimmed with increasing Vo (2 nd -5 th image in Figure 4.18c). Eventually, the QDLED was completely turned off when Vo= - 20 V (6 th image in Figure 4.18c). 0 -40 • ••• - ••• <( ••• -80 • !II :::l ·• .. . . --- .. . . 0 • • I -120 I • I -•--0.5V - - -1.0V • I - - -1.5V • -160 I • - - -2.0V -100 -50 0 50 100 VG(V) Figure 4.14 Transfer characteristics of the LED-driving WSe2 FET, measured under different Vos, from -0.5 V to -2.0 V in -0.5 V steps. 77 a b C 0.010..----------~ 0.008 ?0006 c ~ 0.004 ::J () 0.002 0.000 . . . ~ 4 ~ 0 2 4 6 Voltage (V) Figure 4.15 (a) Energy band diagram of DHNR LED and a schematic of a DHNR. (b) Schematic diagram showing the structure of the DHNR-LED. (c) Current-voltage characteristics of the DHNR-LED. Similarly, a commercial inorganic LED was externally connected to this printed FET to demonstrate the switching capability for traditional inorganic LEDs. The current-voltage characteristics of the inorganic LED can be found in Figure 4.16. A family of lLEo-Vo curves under different Voo from 1.5 V to 3.0 V in 0.5 V steps are shown in Figure 4.18d. A closer inspection of Figure 4.18d indicates that at Voo = 2 V, the LED current is ~ 83 µA when Vo = -100 V, which offered enough brightness for LED (1 st image in Figure 4.18f), and the current fell below 1 nA when Vo 2': 60 V, corresponding to a modulation of hED of 8.3x10 4 . Figure 4.18e shows the hED-Voo family curves under Vo from O V to -100 V in -10 V steps, from which a typical diode behavior can be observed with a cutoff Voo of~ 1.5 V, suggesting a good switching capability over inorganic LED. Images of the LED shown in Figure 4.18f show that the LED emission light faded with increased Vo, and got fully turned off at Vo~ -30 V. Moreover, current-driving functionality of the printed WSe2 FET over OLED (structure and electrical characteristics shown in Figure 4.17) was also demonstrated in Figure 4.18g- 4.18i. Based on the loLEo-Vo family 78 curves shown in Figure 4.18g, when Voo = 8 V and Va = -100 V, loLE D reached 25 µA, supplying enough current to the OLED, which needs ~ 1 µA to emit observable light. 14 • 15 The loLED is ~ 1 nA when Va = 60 V. This corresponds to a modulation of loLED of2.5x10 4 . A good diode behavior can also be observed from the loLED-Voo family curves under different Va (Figure 4.18h), showing a cutoff voltage of Voo = 3.5 V which matches the threshold voltage of OLED. 14 Figure 4.18i shows the OLED light modulation by tuning Va at a fixed Voo of 8 V, corresponding to the dark blue curve in Figure 4.18g. When Va was -100 V, the OLED was very bright (1 st image in Figure 4.18i). The light intensity decreased with Vo increasing (2 nd to 5 th image in Figure 4.18i). The OLED was eventually turned off at Va= -30 V (6 th image in Figure 4.18i). Overall, we have successfully demonstrated the good control capability of the printed ultra-short channel WSe2 FET over three different LEDs, including QDLED, inorganic LED and organic LED, which lays a good foundation for using printed TMDC electronics for more complicated display control circuits and other potential applications. 0.08 ,-..0.06 ~ c o.o4 ~ .... 8 0.02 0.00 ;" ;" . I . I l J J ,l " .. 0.0 Q5 1.0 1.5 20 2.5 Voltage (V) Figure 4.16 Current-voltage characteristics of the inorganic LED. 79 a b -Al - 1 nm LiF - 50 nmAlq 3 - 50nm NPD -ITO 3.0 2.5 ~ ,S 2.0 c 1.s ~ 1.0 :::, (.) 0.5 0.0 . I 0 2 4 6 8 Voltage (V) Figure 4.17 (a) Schematic diagrams showing the cross-section view of the O LED structure. The OLED used in this study is a 4,4'-bis[N-(l-naphthyl)-N-phenylamino]biphenyl (NPD)/tris(8-hydroxyquinoline)aluminum (Alq3) green light OLED with aluminum (Al) as the cathode and indium tin oxide (ITO) as the anode. (b) Current-voltage characteristics of the OLED. 80 a 240 180 ~ :::t 120 0 w ...J 0 _o 60 0 C d 300 ~ 200 ~ 0 w 100 ...J 0 f g 60 50 40 1 30 0 w 20 ...J 0 10 0 b 200 Voo J 150 v , ~i V 00 from1 .5 V to4 V '-.. ~ 100 ~ in 0.5 V steps = '- 0 w ...J 0 50 _ o -100 -50 0 50 100 VG(V) a e Voo J v , ~i = "-.."- -4 -2 V 0 from o V to-100 V in -10 V steps v,h of QDLED - 2 4 V00 = 4 V v ,~t Voo J 200 Voo • J J VG-----j i 150 V0 -----j h " ~ ., . V00 from1 .5 V to3.0 '-,. i in 0.5 V steps = '- =, 1 00 1 '-,."- v from o V to -100 V J_: • ~ -=- G 1 , ,; -100 -50 V oo 0 w ...J 50 0 h 40 -3 -2 V oo in -10 V steps , J !l l ~ , -1 0 1 VDD (V) 2 3 V00 = 2 V J V o7 ~ V 00 from 5 V to 10 V 1 '\, J 30 V o----j ~ in 1V steps = "- -100 -50 0 50 100 VG (V) i _ 20 0 w ...J _o 10 0 a - -10 1 '\,'- V 0 from0 V to-100 V = in -10 V steps -5 0 VDD (V) 5 10 Figure 4.18 Printed back-gated sub-micron WSe2 FET for QDLED, inorganic LED and OLED control. ( a, b) Electrical characteristics of the printed WSe2 FET connected to an 81 external QDLED with the circuit diagram shown in the inset. (a) lQDLEo-Vo family curves measured under different Voo from 1.5 V to 4.0 Vin a step of 0.5 V. (b) lQDLED-Voo family curves measured under Va from O V to -100 V in a step of -10 V. ( c) Optical images demonstrating the light intensity modulation of QDLED by tuning Va at Voo = 4 V. (d, e) Electrical characteristics of the printed WSe2 FET connected to an external inorganic LED with the circuit diagram shown in the inset. ( d) l LEo-Va family curves measured under Voo from 1.5 V to 3.0 Vin a step of0.5 V. (e) h Eo-Voo family curves measured under Va from 0 V to -100 Vin a step of -10 V. (f) Optical images showing the light intensity modulation of inorganic LED by tuning Va at Voo = 2 V. (g, h) Electrical characteristics of the printed WSe2 FET connected to an external OLED with the circuit diagram shown in the inset. (g) loLEo-Vo family curves measured under Voo from 5 V to 10 Vin a step of 1 V. (h) loLED Voo family curves measured under Va from O V to -100 V in a step of -10 V. (i) Optical images showing the light intensity modulation of OLED by tuning Va at Voo = 8 V. It is worth mentioning that the "flood-dike" printing strategy is not limited to the specific type of CVD WSe2 used in this work. Indeed, it can serve as a general printing strategy to produce high-performance ultra-short channel TMDC devices. This printing method is highly compatible with various CVD-grown TMDC flakes, liquid-exfoliated TMDC inks, continuous TMDC film, etc. By scaling down the channel length to sub- micrometer scale, the on-state current density can be enhanced significantly by minimizing the number of flake-to-flake junctions or grain boundaries within the channel. We have applied this self-aligned printing approach to mono layer WSe2 flakes directly synthesized on Si/SiO2 substrates using a "traditional" CVD method 5 2 , 138 , 139 (as compared to the ultrafast CVD method 128 ). In this study, we used WSe2 powder and Se powder as 82 precursors instead of a combination of WO3 and Se powders. We found that this PVD-like approach gave us a better uniformity and controllability than the common CVD methods using metal oxides and selenium. We have successfully achieved two kinds of WSe2 samples with either triangular shape or hexagram shape by using two different sets of CVD setups as schematically illustrated in Figure 4.19a. Specifically, we added a specially designed inner tube for the hexagram-shape WSe2 growth, where the inner tube has two openings with the small one facing the upstream and the large one facing the downstream. We discovered that an inner tube with such a structure can greatly facilitate the hexagram shaped growth. Figure 4.19b and 4.19c are two representative optical microscopic images of the as-grown triangle-shaped and hexagram-shaped WSe2 flakes. The lateral size of an individual flake is around 10 µm for triangle-shaped samples and 20 µm for hexagram shaped samples, respectively. According to previous studies, a possible reason for the hexagram-shaped growth may be due to the unique local environment created by the special inner tube with a reduced reactant concentrations and a quasi-static reactant distribution. First, the small front window facing the upstream will significantly reduce the amount of reactants that were introduced into the inner tube, therefore reducing the density of nucleation sites. This is clearly evidenced in Figure 4.19b and Figure 4.19c. Then, the reduced nucleation sites would result in less active growth edges compare to the normal triangle-shaped growth with massive growth edges. At last, the reduced number of growth edges along with the quasi-static environment ensure a continuous and sufficient reactant supply to all growth edges, resulting in a uniform growth rate on all directions. 140 Similar 83 work has been reported in CVD graphene growth where six-lobe graphene flowers were synthesized using a gas trap setup. 141 AFM inspection was performed on the hexagram- shaped WSe2 flakes as shown in Figure 4.19d. The cross-section height profile along the white dashed line presents a clear step with a height of ~0.8 nm which is close to the thickness of a monolayer WSe2. Raman and photoluminescence spectra were further conducted to verify the properties of the CVD-grown WSe2. Figure 4.19e is a Raman spectrum taken under a 561 nm incident laser, where both in-plane E:J,g and out-plane A 1 g characteristic peaks can be clearly observed. Meanwhile, no Raman peak for Big mode was found, indicating the monolayer status of the CVD-grown WSe2 samples. In addition, the monolayer feature was further confirmed by PL measurements where a sharp PL emission peak appeared at ~ 770 nm, corresponding to the direct bandgap transition of monolayer WSe2 (Figure 4.19f). a d ::i E1..,...., ~ 2g z. ·;;; C 2 C C ro E ro a:: 200 250 300 350 400 450 Raman Shift (cm· 1 ) ::J ~ z, 'iii C 2 C ...J c.. C 10 µm 680 720 760 800 840 Wavelength (nm) Figure 4.19 (a) Schematic diagrams of CVD setups for triangle-shaped WSe2 growth and hexagram-shaped WSe2 growth. For hexagram-shaped growth, the substrate is enclosed in 84 a special inner tube with a small opening facing the upstream supplies. (b )( c) optical microscope images showing the as-grown WSe2 flakes with triangular shapes (b) and hexagram shapes ( c ). The lateral size of an individual WSe2 flake is ~ 10 µm for triangular shaped samples and~ 20 µm for hexagram-shaped samples. ( d) AFM image of a hexagram shaped WSe2 flake along with the cross-section height profile of the white dash line. The height of the sample is measured to be ~0.8 nm corresponding to a monolayer TMDC. (e) Raman spectrum of the as-grown CVD WSe2 showing the two characteristic peaks of E:J,g mode and A 1 g mode. (t) PL spectrum of the CVD WSe2 sample showing a strong PL peak at~ 770 nm, confirmed the mono layer status. A low-pressure CVD setup was used to synthesize monolayer WSe2 samples. Specifically, a ceramic boat with 2 mg WSe2 powders (Alfar Aesar, 99.8%) was firstly placed in the middle of a one-inch quartz tube with another ceramic boat containing 10 mg Se powders (Sigma Aldrich, 99%) sitting at the upstream. The Si/SiO2 substrate was placed at the downstream about 15 cm away from the WSe2 powder. Then the furnace will be pumped down to ~900 mTorr with 80 seem Ar flow mixed with 10 seem H2 flow. Once the pressure read-out was stable, the system was ramped up to 1000 °C in 20 minutes and kept for 15 minutes for growth. After completion, the furnace was cooled down naturally under the atmosphere of Ar gas. For the hexagram-shaped WSe2 growth, a small inner tube was used to first encapsulate the Si/SiO2 substrate. The rest were similar to normal CVD growth. Figure 4.20 presents the electrical properties of the printed ultra-short channel FETs based on the monolayer WSe2 synthesized using the "traditional" CVD method (as compared to the ultrafast CVD growth). The measurements were conducted under ambient 85 condition with a back-gated structure. Figure 4.20a shows the transfer characteristics of a typical printed device on mono layer WSe2 with a channel length of ~0.75 µm and a channel width of ~8 µm. The device was measured at a negative Vos of -2 V (Figure 4.20a). A strong unipolar p-type behavior was observed. The inset of Figure 4.20a shows the optical microscope image of this device (images of more devices shown in Figure 4.21 ). Figure 4.20b shows the transfer curve plotted in logarithmic scale with an Ionlloffratio of 10 5 . The inset of Figure 4.20b shows the SEM image of this device. The field-effect mobility (µeff) was also calculated with a value of0.85 cm 2 N·s which is comparable to the reported value for CVD monolayer WSe2. 52 Figure 4.20c shows a family of output curves (Jo-Vos) at various Vo from -100 V to -50 V. The non-linear behavior indicates the existence of Schottky barriers. Figure 4.20d is the output curve in the low Vos bias region. 86 a 0 b 101 10° - -1 -- 10-1 <( 110- 2 :::l -- - _o -2 _010-3 I VDS = -2 V 10-4 -3 10-5 -100 -50 0 50 100 -100 -50 0 50 100 VG (V) VG (V) c15 d 4 10 5 2 -- -- ~ 0 ~ :::t :::t 0 -- -5 -- Cl Cl -10 VG -2 VG - -100V - -90V - -100V - -90V -15 -80V - -70V -S0V - -70V - -60V - -50V -4 - -60V - -S0V -20 -10 -5 0 5 10 -2 -1 0 1 2 Vos(V) Vos(V) Figure 4.20 (a) Io-Va transfer curve of a representative printed sub-micron WSe2 FET, measured at a negative Vos of-2V. The inset shows the optical image of the device. (b) The transfer curve plotted in a logarithmic scale showing an Ion! Iotr ratio of 10 5 . The inset shows the SEM image of the device. ( c) A family of Io-Vos output curves of the printed devices showing the existence of Schottky barrier. ( d) Io-Vos output curves in the low-bias region. Figure 4.21 Optical microscope images of additional sub-micron channel devices prepared using "flood-dike" printing method. These devices were printed on mono layer WSe2 flakes directly synthesized on Si/SiO2. 87 a 10 bs C Average I 0,/W 7 Average 1 0 ,/1 0 • ratio 10 Average mobility ~ 0.27 µA/µm 6 ~1 .6 X 10 5 ~1 .53 cm 2 N s .l!l 6 2 "' 6 C C 4 c :::, 4 :, :::, 0 0 0 4 (.) (.) (.) 0.00 0.25 0.50 0.75 1.00 1.25 0 0 1 2 3 4 5 6 7 2 4 5 6 1 0,/W (µA/µm) Log ,o(l 0,/l 0 ff) Mobility (cm 2 /Vs) Figure 4.22 Statistic studies of the performance of printed ultra-short channel devices on CVD monolayer WSe2 flakes synthesized on Si/SiO2. (a) Ion/W distribution of 14 printed sub-micron monolayer WSe2 FETs, measured under VG= -100 V and VDS = -2 V. (b) Ion/Ioff ratio distribution of the devices printed on monolayer WSe2. (c) Field-effect mobility distribution of the printed devices on monolayer WSe2, extracted under VDS = - 2 V. A systematic statistic study was performed on 14 printed monolayer WSe2 devices to verify the reliability and reproducibility of the three-step printing process. All the devices achieved through this SAM-assisted printing technique possess an ultra-short channel of less than one micrometer while still sustain a high Ionlloff ratio of ~ 1.6 x 10 5 (average) as shown in Figure 4.22b. The distribution of the on-state current densities over these 14 devices is shown in Figure 4.22a, with an average on-state current density of 0.27 µA/µm. Figure 4.22c presents the distribution of µe ff with an average mobility of 1.53 cm 2 /Vs, which is within the range of reported values of as-grown CVD monolayer TMDCs with a back-gated structure. 52 , 72 The results of the printed ultra-short channel FETs on few-layer WSe2 are presented in Figure 4.23 with a higher on-sate current density of 3. 70 µA/µm, a reduced Ionlloff ratio of 10 3 and an increased µe ff of 10.4 cm 2 /Vs, compared to printed monolayer WSe2 FETs. 88 a 0 -10 - <( 2:-20 0 -30 -100 -50 0 50 100 VG (V) c 100---------~ v. - -1oo v 50 = ::~ - -70 V i O 0 - -60 V - -so v -50 -10 -5 0 5 10 Vos(V) b 1 E-5 ~1E-6 0 1 E-7 -100 -50 vi (V)5o 100 d 50 - i 0 - 0 v, - -1oov - -90V - -80V - -70V -50 - -GOV - -50V - -40V -3 -2 -1 0 2 3 Vos(V) Figure 4.23 Printed ultra-short channel devices based on few-layer CVD WSe2. (a) Io-VG transfer curve measured at a Vos of -2 V. (b) Io-Va transfer curve at a negative Vos of -2 V in a logarithmic scale. A clear p-type behavior can be observed for few-layer WSe2 samples. Compared to monolayer WSe2 devices, few-layer WSe2 devices show higher on-current but lower Ion! IofI ratio. ( c )( d) A family of Io-Vos output curves measured at different VG. A clear Schottky behavior can be observed from the output curves. A representative printed sub-micron WSe2 FET (using WSe2 synthesized by "traditional" CVD method) was connected with an external inorganic LED to demonstrate its controllability over inorganic LED (Figure 4.24a-c ). Figure 4.24a plots the current through the LED as a function of VG measured under Voo of 5 V. Figure 4.24b shows the current through the LED as a function of Voo under Vo from -40 V to -100 Vin -10 V steps. Figure 4.24c shows a series of photographs of the LED taken under different VG when Voo was fixed at 5 V, illustrating the light intensity modulation. Similarly, this device was 89 connected with an external OLED to demonstrate its controllability over OLED (Figure 4.24d-f). Figure 4.24d plots the current through the OLED as a function of Vo measured under different Voo from O V to 10 Vin 1 V steps. Figure 4.24e plots the current through the OLED as a function of Voo under different Vo from O V to -100 Vin -20 V steps. Figure 4.24f shows a series of photographs of the OLED taken under different Vo at a fixed Voo of 8 V to demonstrate the light intensity modulation. a 6----------~ b 4 ·100 .50 0 50 100 v. (VJ C d e -100 -50 0 50 100 v. (V) f 8,------,,.,...------------, V.,_ ___ ~ ' - ·100V - •90V 6 I =- .aov - - 1ov I= !~~ - .50v1 ·1 0 2 3 4 5 6 7 VooM G 1 -ov- - zov 1 - -40V - ~ov 4 - .aov - - 1oov -10 -5 0 5 Yoo M V 00 = 8 V Vo -it 10 Figure 4.24 Printed back-gated sub-micron WSe2 FET for inorganic LED and OLED control. ( a, b) Electrical characteristics of printed WSe2 FET connected to an external 90 inorganic LED with the circuit diagram shown in the inset. (a) ILED-Vo curve measured under V DD of 5 V. (b) ILE D-V DD family curves measured under Vo from -40 V to -100 V in a step of -10 V. ( c) Optical images demonstrating the light intensity modulation of LED by tuning Vo at V DD = 5 V. ( d, e) Electrical characteristics of printed WSe2 FET connected to an external OLED. (d) loLED-V o family curves measured under VDD from O V to 10 Vin a step of 2 V. ( e) loLED-V DD family curves measured under Vo from O V to -100 V in a step of -20 V. (f) Optical images showing the light intensity modulation of OLED by tuning Vo at VDD = 8 V. Besides TMDC materials, we believe this printing strategy has the potential to be used for creating sub-micrometer channels on 2D and layered transition metal oxides (TMOs), 142 such as 2D MoO3, Ga2O3, ImO3, ZnO, etc, aiming for high-performance printed devices. Moreover, it is worth mentioning that this printing strategy is not limited to the specific gold ink used in our study. We believe any metal nanoparticle ink that can wet TMDC surface should be able to work with this method. For example, the silver ink used in Ref 72 , which was reported to wet M0S2 well, should be able to work. Furthermore, the substrate of the "flood-dike" printing approach is not limited to Si/Si 02, it can be easily adapted on flexible or transparent substrates by using a top-gate device structure or electrolyte gate, aiming for wearable and display electronics. 91 4.4 Conclusion In summary, we have successfully demonstrated a "flood-dike" self-aligned printing strategy which offers a lithography-free way to form metal contacts on 2D TMDC materials with sub-micrometer channel length resolution. The use of thiol SAM allows the modification of the surface tension of the first gold electrode to make it more repulsive to the following gold ink, while the surface properties of WSe2 and SiO2 remain untouched by the SAM. The contrast in the wetting angles of the gold ink on the SAM-treated Au and the WSe2 surface enables the gold ink to spread on the WSe2 surface but be stopped by the SAM coating, thus creating a sub-micrometer channel in a self-aligned manner. By adopting this printing technique, we managed to downscale the transistor channel length of the printed WSe2 FET to sub-micrometer scale and achieve an enhanced on-state current density of 0.64 µA/µm while maintaining a high on/off current ratio of 3xl 0 5 . The superior performance of the printed WSe2 FE Ts allows good controllability over QDLED, inorganic LED and OLED. This ultra-short channel printing technique may enable future development of low-cost and high-performance electronics based on 2D TMDCs. 92 Chapter 5: Conclusions and Future Directions 5.1 Conclusions In conclusion, this dissertation presented the development of novel platforms for printed electronics based on carbon nanotubes and two-dimensional transition metal dichalcogenides. This dissertation mainly focused on tackling two main challenges in the printed electronics field. One challenge is how to make printed complementary logic circuits. The other challenge is how to scale down the channel lengths of printed transistors aiming for better performance. Complementary logic circuit is highly desirable due to its full voltage swings, low static power consumption, and large noise margins. However, achieving printed complementary logic circuits solely based on CNTs is difficult because it is still challenging to make n-type CNT transistors in a reliable way. On the other hand, metal oxides have been reported as good channel material for n-type transistors. Therefore, we developed an ink-jet printing platform for hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits. Threshold voltages of our p-type and n-type transistors were carefully tuned to ensure enhancement-mode operation for both types of transistors. By printing thin film of CNT as p-type channel and printing thin film of IZO as n-type channel, a complementary inverter has been achieved with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work demonstrates that CNT and IZO are excellent channel materials for p-type and n-type transistors, while inkjet 93 printing offers a simple, reproducible and cost-effective way for construction of complementary logic circuits with these two types of materials. This work has paved the way for future printed complementary circuits with more sophisticated logic and even better performance. Limited by the resolution and registration accuracy of the current printing instruments, previously reported printed transistors based on CNTs and 2D TMDCs have channel lengths in the range of 13-200 µm. For CNT transistors, there exist a large number of nanotube-to-nanotube junctions, which degrades the transistor performance. For 2D TMDC transistors, within such a long channel, there can be numerous grain boundaries or flake-to-flake junctions, limiting the on-state current density of the TMDC transistors. Downscaling of the transistor channel length to submicron scale is highly desired. To tackle this main challenge, two novel self-aligned printing techniques have been developed to achieve submicron critical dimension for printed CNT and 2D TMDC electronics, respectively. With top-contact self-aligned printing approach, CNT TFTs with channel lengths of 500 nm have been achieved, which showed a dramatically enhanced on-state current density compared to previously reported printed CNT TFTs. On the other hand, "flood-dike" self-aligned printing reliably yields high-performance 2D TMDC FETs with 750 nm channel length and superior current-driving capabilities and on/off current ratios. The self-aligned printing approaches built a promising platform to enhance the device performance of printed CNT and TMDC transistors by downscaling the channel length to submicron scale. The printed submicron transistors are promising for future printed high- 94 definition display electronics, sensmg systems, low-power consumer electronics, and large-scale integrated circuits. 5.2 Future Directions on Printed CNT Electronics Printed CNT Electronics for Artificial Skin Fabrication of large-area flexible and stretchable devices and sensor systems allows for the conformal coverage on non-planar surfaces, which may realize many new functionalities, such as user-interactive interfaces, robotic interfaces, wearable body monitors, smart wallpapers, etc. However, most of the applications require a large area of coverage, which is beyond the size limit of traditional fabrication batch processing. Printing technology is a cost-effective and scalable technology with high throughput and is highly compatible with low-temperature processing, which provides an important way in mass production oflarge-area flexible electronics at extremely low cost. Semiconducting single-wall carbon nanotubes (SWCNTs) are very promising materials in printed electronics due to their excellent mechanical and electrical property, outstanding printability, and great potential for flexible and stretchable electronics. The first part of my future work is to develop printed and wearable electronics and sensors based on SWCNTs, which will pave the way for conformal lamination on human skin or robots for spatial and temporal mapping of stimuli, such as pressure, strain, temperature, etc. In order to achieve the goal mentioned above, this proposed study will focus on the 95 following technical approaches. (1) We will design, fabricate and study SWCNT thin-film transistors (TFTs) as active-matrix backplanes on flexible and stretchable substrates using low-cost multiple-step screen printing techniques (Figure 5.la). We will carry out fundamental studies on device physics, including carrier scattering at nanotube-nanotube junctions, contact resistance, nanotube/dielectric interfaces, etc. (2) We will develop pressure, strain and temperature sensor inks which can be directly printed and act as resistors with variable resistance upon stimuli. We will design polymer composites with nanomaterials (i.e. multi-wall carbon nanotubes, graphene nanoplatelets, nickle nanoparticles, etc.) as conductive fillers in polymer matrix. Experiments will be carried out to study the relationship between the sensor's sensitivity, loading of nanomaterials in polymer matrix and morphology. (3) Integration of SWCNT TFT active matrix with pressure/strain/thermal sensors by directly printing active sensing materials in series with SWCNT TFTs (Figure 5.lb and 5.lc). This part of my future work will build a scalable cost-effective technology platform to fabricate environmental-friendly, large-area, lightweight, flexible/stretchable electronics and sensors which can enable a wide range of new functionalities, such as electronic skins, user-interactive surfaces, robotic interfaces, smart clothes, smart wallpapers, etc. 96 a b V ,~? ~CNT f ~nsor Ground Source PET Figure 5.1 (a) Schematic diagrams showing a screen printing system. (b) Equivalent circuit diagram of a single pixel in the thin-film transistor (TFT) array with the sensor acting as a variable resistor in series with the single-wall carbon nanotube (SWCNT) TFT. (c) Cross section schematic diagram of a pressure sensor cell. ( d) A photograph of a screen-printed flexible sensor array with SWCNT active-matrix backplane. Printed CNT Electronics for Flexible Display Separated semiconducting-enriched SWCNT thin films possess great potential for TFTs and active-matrix backplanes for display electronics, due to their high semiconducting purity, high mobility, and room-temperature processing compatibility. As early as 2009, Wang et al. made the first conceptual demonstration of an organic light- emitting diode (OLED) control circuit with a nanotube TFT, with the output light intensity exceeding 104, which paves the way for using nanotube TFTs for display electronics. 78 Active-matrix organic light-emitting diode (AMOLED) display exhibits great potential as a competitive candidate for next-generation display technologies due to its high light efficiency, light weight, high flexibility, and low-temperature processing compatibility. Later, Zhang et al. further successfully demonstrated monolithically integrated AMOLED display elements, consisting of 500 pixels driven by 1000 nanotube TFTs. 112 The optical 97 image of an AMO LED substrate containing 7 AMO LED elements, each with 20 x 25 pixels, is shown in Figure 5.2a. Figure 5.2b is a photograph showing the pixels on an integrated AMO LED. The electrical characteristics of the OLED controlled by a single pixel circuit is shown in Figure 5.2c. Figure 5.2d shows the plot of the current through the OLED (IOLED; red line) and OLED light intensity (green line) versus VDATA with VDD = 8 V. This approach may serve as a critical foundation for using separated CNT thin-film transistors for display applications in the future. Later on, inkjet-printed 14 and screen-printed 15 OLED control circuits were demonstrated, showing a low-cost approach to realize OLED driving capability. However, in previous works, the OLED control circuits were connected to the OLEDs externally for the demonstration. Besides, the OLEDs were fabricated by vacuum evaporation, which is not scalable and rather expensive. In my future research, I plan to develop functional inks for printable OLEDs, which can be directly printed on arbitrary substrates. Then I plan to integrate our printed and flexible CNT TFT active matrix backplane with printed OLEDs on the same chip using screen printing or ink-jet printing methods. The anticipated outcome of my future study will be a fully printed, flexible, large-scale and low-cost flexible active matrix OLED display. 98 a b 40 d 80 10~ C 35 VoATA from -5 V to 5 V V00=SV with a step of 1 V 70 10~ '"e 30 ~t - 60 10· 1 ~ ~ 25 ~ 50 ~ .al, 20 ~~ data 10~ ~ " ~40 10~ ~ "J 15 data loLED -~ 30 ., _o 10 [_]! 10- 10 E 20 5 10 10- 11 t -Von 10· 12 :J 0 0 -8 ~ -4 -2 0 -5.0 -2.5 0.0 2.5 5.0 -V� D (V) VDATA (V) Figure 5.2 AMOLED using SWCNT TFTs. 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Abstract (if available)

Abstract Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed electronics due to their excellent electrical performance and intrinsic printability with solution-based deposition. Compared to traditional micro-fabrication, printing technology offers a scalable and cost-effective way to fabricate electrical devices by eliminating multi-stage lithography patterning and high-vacuum environment. Besides that, printing technology allows carbon nanotubes to be deposited at room temperature through a solution-based process, so devices can be printed on any kinds of substrates, including flexible and stretchable substrates. Thus, printing technology is very promising for making large-scale low-cost flexible electronics. ❧ This dissertation discusses about the development of two novel platforms for printed carbon nanotube electronics. The first platform is inkjet printing of p-type carbon nanotube (CNT) and n-type indium zinc oxide (IZO) for complementary integrated circuits. Carbon nanotube transistors are usually p-type in air due to the adsorption of oxygen. Achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging to make reliable n-type CNT transistors. Metal oxides have been reported to be good candidates for n-type channel materials. In this study, indium zinc oxide was selected as our n-type channel material. In order for complementary circuits to work correctly, both types of transistors need to operate in enhancement mode. To achieve this, the threshold voltages of both types of transistors were carefully tuned, by engineering the work function of metal contacts for CNT transistors and adjusting In to Zn molar ratio for IZO transistors. With the optimum recipe, IZO and CNT thin films were printed sequentially on the same substrate to construct a complementary inverter. The printed inverter worked correctly with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work shows the promise of using inkjet printing for the hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits. ❧ The second platform is a top-contact self-aligned printing approach for submicron channel carbon nanotube thin-film transistors. Limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). With top-contact self-aligned printing approach, the transistor channel length has been successfully downscaled to submicron scale, leading to a dramatically enhanced on-state current density of ∼4.5 μA/μm. These advantageous features of our printed ultrashort channel transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics. ❧ Furthermore, part of this dissertation presents the development of a novel printing platform for high-performance submicron-channel two-dimensional (2D) transition metal dichalcogenide (TMDC) field-effect transistors (FETs). 2D TMDCs have been drawing great attention because they are atomically thin, intrinsically flexible, and they have good electrical properties. 2D TMDCs are ideal materials for flexible electronics. Printing technology has potential to offer a cost-effective and scalable way to fabricate electronic devices based on 2D TMDCs. However, limited by the registration accuracy and resolution of printing, the previously reported printed TMDC FETs have relatively long channel lengths (13−200 μm), thus suffering low current-driving capabilities (≤0.02 μA/μm). In this dissertation, I developed a “flood−dike” self-aligned printing technique that allows the formation of source/drain metal contacts on TMDC materials with submicron channel lengths in a reliable way. With this printing technique, we have successfully downscaled the channel length to ∼750 nm and achieved enhanced on-state current density of ∼0.64 μA/μm (average) and high on/off current ratio of ∼3 × 10⁵ (average). Furthermore, with our high-performance printed WSe₂ FETs, driving capabilities for quantum-dot light-emitting diodes (LEDs), inorganic LEDs, and organic LEDs have been demonstrated, which reveals the potential of using printed TMDC electronics for display backplane applications. ❧ This dissertation is structured as follows. Chapter 1 gives a brief introduction to carbon nanotubes, two-dimensional transition metal dichalcogenides, and printed electronics, which serves as the background knowledge for the following chapters of this dissertation. Chapter 2 presents the development of inkjet-printed complementary transistors and circuits based on p-type carbon nanotubes and n-type indium zinc oxide. After that, Chapter 3 talks about the development of top-contact self-aligned printing method for submicron channel carbon nanotube thin-film transistors. Following that, Chapter 4 discusses about the development of “flood-dike” self-aligned printing approach for submicron channel 2D TMDC FETs. Finally, Chapter 5 presents the conclusions and points out future directions.

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Asset Metadata

Creator Wu, Fanqi (author)

Core Title Printed electronics based on carbon nanotubes and two-dimensional transition metal dichalcogenides

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Materials Science

Publication Date 01/13/2020

Defense Date 11/19/2019

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag carbon nanotubes,OAI-PMH Harvest,printed electronics,thin-film transistors,transition metal dichalcogenides

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Zhou, Chongwu (committee chair), Ravichandran, Jayakanth (committee member), Wu, Wei (committee member)

Creator Email fanqiwu@gmail.com,fanqiwu@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c89-260288

Unique identifier UC11674741

Identifier etd-WuFanqi-8118.pdf (filename),usctheses-c89-260288 (legacy record id)

Legacy Identifier etd-WuFanqi-8118.pdf

Dmrecord 260288

Document Type Dissertation

Rights Wu, Fanqi

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA