Close
About
FAQ
Home
Collections
Login
USC Login
Register
0
Selected
Invert selection
Deselect all
Deselect all
Click here to refresh results
Click here to refresh results
USC
/
Digital Library
/
University of Southern California Dissertations and Theses
/
Digital to radio frequency conversion techniques
(USC Thesis Other)
Digital to radio frequency conversion techniques
PDF
Download
Share
Open document
Flip pages
Contact Us
Contact Us
Copy asset link
Request this asset
Transcript (if available)
Content
DIGITAL TO RADIO FREQUENCY CONVERSION
TECHNIQUES
by
Shiyu Su
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulllment of the Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2019
Copyright 2020 Shiyu Su
Abstract
Digital-to-radio frequency (RF) converters with a high dynamic range are key build-
ing blocks for all-digital communication systems. For a conventional digital-to-
analog converter (DAC), high speed and high dynamic range typically trade o
each other. The main emphasis of this thesis is on techniques that enhance the
signal bandwidth and dynamic range of DAC conversion.
In the rst part of the dissertation, a hybrid DAC architecture is introduced,
which achieves both high speed and high linearity. It takes and combines the best
of conventional Nyquist and delta{sigma DAC. This architecture benets from the
delta{sigma modulator (DSM) in two main aspects: (1) the DSM reduces analog
complexity and leads to a mostly digital design that is highly
exible and favors
CMOS technology scaling, and (2) the high-resolution property of the DSM en-
ables advanced digital pre-distortion (DPD) techniques for high-linearity DAC de-
sign. Based on the hybrid architecture, bandwidth extension techniques, including
unrolled pipeline DSM, DSM-assisted in-band noise cancellation, and successive
pipeline bandpass DSM, are proposed and used to overcome the bandwidth limit
of the hybrid DAC. To maintain the DAC dynamic range over a wide frequency
ii
range, a means of linearizing the DAC based on the DSM is presented. Three
prototype DACs with a resolution of 12{16 bits and a sampling rate of 1{12 GS/s
are implemented to prove the eectiveness of the hybrid DAC architecture and the
techniques developed based on this architecture.
In the second part of the dissertation, a direct-digital radio frequency modulator
(DDRM) based on the hybrid DAC and a time-approximation lter (TAF) is dis-
cussed, focusing on enhancing the system dynamic range via noise and spur ltering
instead of improving the intrinsic linearity of the DAC. The TAF essentially embeds
a nite impulse response (FIR) lter in the upconversion of the DDRM via digitally
modulating the local oscillator (LO) signal, which makes it highly recongurable
with a minimum implementation overhead. As both the hybrid DAC and TAF
are highly
exible, they are combined to create in-band and/or out-of-band (OOB)
spectral notches to support dierent communication scenarios. With TAF, an ex-
perimental prototype DDRM achieves -158 dBc/Hz noise spectral density (NSD) at
100 MHz oset from a 2.4 GHz carrier and -43 dB error vector magnitude (EVM) at
1024 quadrature amplitude modulation (QAM). Without using a surface acoustic
wave (SAW) lter, an extension prototype combines a bandpass hybrid DAC and
a tri-level TAF and achieves -169 dBc/Hz NSD at 68 MHz oset from a 2.2 GHz
carrier, which pushes the envelope of digital transmitters with an output power of
more than 15 dBm below the mask requirement of frequency division duplexing
(FDD) applications.
iii
Dedication
To my parents and grandmother.
iv
Acknowledgements
With utmost gratitude, I wish to acknowledge the company of my friends and
family during my Ph.D. journey. This dissertation would not have been completed,
or even started, without their support.
First and foremost, I would like to acknowledge the support, guidance, enthu-
siasm, and expertise of Professor Mike Chen. I joined his group in the second year
of my master program with almost no circuit background. He was so patient in
letting me gradually catch up and worked hard with me to make all the projects
successful. In the early years, he probably spent more time with the students, in-
cluding me, than with his family. He not only taught me how to tackle research
problems but also the philosophies of handling things that he inherited from his
former advisor and with his own understanding. I would not have gone this far and
probably would not have tried going further without his encouragement.
Professor Hossein Hashemi was generous with his knowledge and ideas, and he
was always willing to spend time with students for technical discussions and to
write recommendation letters for us. He also deserves much credit for teaching the
v
analog and radio frequency classes at USC, from which all the circuit students on
PHE fourth and fth
oors beneted greatly.
I was really fortunate to join USC at the time that Professor Mike Chen and
Professor Hossein Hashemi were trying hard to build the top circuit group in the
eld. As a result, increasing numbers of talented people joined and contributed to
the group, making USC a great place for graduate students to pursue their dreams.
Many thanks are also due to my other qualifying exam and dissertation commit-
tee| Professor Keith Chugg, Professor Dina El-Damak, Professor Nicholas Gra-
ham, and Professor Jayakanth Ravichandran|for all the excellent questions, sug-
gestions, and invaluable time. I would also like to thank Professor Sandeep Gupta,
Professor Dina El-Damak, and Professor Manual Monge for organizing the MHI
scholar event, where I learnt how to eectively communicate with scholars from
various elds.
A lot of people was joking when I rst join USC that Ph.D. students in circuit
groups here don't have \a life." I somehow felt this way during tapeout periods,
but now I could not agree with that. When I look back, I realize that there were
so many wonderful colleagues and friends along with me, making these few years
at USC the best period of my life. I must gratefully acknowledge their company.
First, I would like to thank my seniors, David Chiong, Dylan Hand, Tu-I Tsai,
Praveen Sharma, Jaewon Nam, and Cheng-Ru Ho (Soar). I had no overlap with
David and only worked with Dylan for a few months, but they really spent an
vi
enormous amount of time and eort on building the lab facilities at the early stages,
from which all our group members have continued to benet greatly, including
purchasing servers and equipment, installing software, and building up our group
wiki. Tu-I was the rst senior that I worked with. Without his generous help and
previous research, I probably would have spent a few more years getting my rst
work done. Praveen is the guy who will always stop his own work and help you
whenever you ask. He gave me the most IT and tool support that I was really not
good at. Jaewon, Soar, and I had our own sleeping bags at the lab, and we suered
(40%) and enjoyed (60%) the process of delivering tapeouts in a crazy schedule (of
course crazy research ideas are the prerequisites). Soar deserves my special thanks
as a classmate for two years, a roommate for four years, and a labmate for six years.
Having Soar to take classes, play games, and discuss technical and non-technical
things with truly enriched my Ph.D. life.
I would also like to thank my other lab mates, Tzu-Fan Wu, Aoyang Zhang,
Mohsen Hassanpourghadi, Rezwan A Rasul, Ce Yang, Mostafa Ayesh, Qiaochu
Zhang, Juzheng Liu, Soumya Mahapatra, and Baishakhi Rani Biswas. I would like
to extend special thanks to Aoyang and Tzu-Fan for hanging out with me and for
being good listeners to my complaints and to Qiaochu and Juzheng for our regular
\military-standard training" at the Lyon Center (a gym at USC).
Thanks are also due to colleagues from Professor Hashemi's and Professor El-
Damak's groups. They are Run Chen, SungWon Chung, Pingyue Song, Alireza
vii
Imani, Kunal Datta, Sushil Subramanian, Masashi Yamagata, Samer Idres, Aria
Samiei, and Yuke Zhang. Run was an ideal model for many of us in many aspects
when we rst joined the group. I beneted greatly from my interactions with him
at USC and after he graduated. I also thank Pingyue and his wife for taking care
of my cats when I was out of town and SungWon for technical discussions on the
testing of my rst transmitter chip and great suggestions for my career.
Finally, although I have done this many times at important stages of my life, I
must once again extend my heartfelt gratitude to my family. This thesis is dedicated
to my dad Weicheng Su, who has been excellent role model for me; my mom
Yun Yi, who unconditionally provided her wholehearted support to me; and my
grandmother Hexiu Chen, who brought me up, took care of me, and protected me
when I was a child.
ii
Table of Contents
Abstract ii
Dedication iv
Acknowledgements v
List Of Tables vii
List Of Figures viii
Chapter 1: Introduction 1
1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 2: Direct-Digital RF Conversion 4
2.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Challenges and Solutions . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3: Hybrid DAC Architecture 10
3.1 Overview of DAC Architectures . . . . . . . . . . . . . . . . . . . . 10
3.2 Hybrid DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Segmentation Ratio Tradeos . . . . . . . . . . . . . . . . . . . . . 13
3.3.1 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 4: DSM-Assisted Digital Pre-distortion 19
4.1 Existing Techniques and Limitations . . . . . . . . . . . . . . . . . 19
4.2 DSM-Assisted Pre-distortion . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Pulsed Error Pre-distortion . . . . . . . . . . . . . . . . . . . . . . 23
4.3.1 Amplitude and Timing-error Mechanisms in DAC . . . . . . 23
4.3.2 The Concept of Pulsed-Error Pre-distortion . . . . . . . . . 27
4.3.3 Quantization of Error Pulses . . . . . . . . . . . . . . . . . . 28
4.3.4 Phase Alignment of Error Pulses . . . . . . . . . . . . . . . 31
iii
4.3.5 Numerical Simulation . . . . . . . . . . . . . . . . . . . . . . 36
4.4 Inverse-Sinc Pre-distortion . . . . . . . . . . . . . . . . . . . . . . . 37
4.4.1 Overview of Existing DPD Techniques . . . . . . . . . . . . 37
4.4.2 Inverse-Sinc Shaped Digital Pre-distortion . . . . . . . . . . 38
Chapter 5: High-Speed Delta-Sigma Modulator 42
5.1 Unrolled Pipeline Delta-Sigma Modulator . . . . . . . . . . . . . . 42
5.1.1 Unrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1.2 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.3 Multi-Bit MASH . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 In-Band Noise Cancellation . . . . . . . . . . . . . . . . . . . . . . 48
5.2.1 Conventional Noise Cancellation . . . . . . . . . . . . . . . . 50
5.2.2 DSM-Assisted In-Band Noise Cancellation . . . . . . . . . . 51
5.3 Successive Pipelined Bandpass DSM . . . . . . . . . . . . . . . . . 54
5.3.1 Overview of Bandpass DSM . . . . . . . . . . . . . . . . . . 55
5.3.2 Successive DSM with Tunable Passband . . . . . . . . . . . 56
Chapter 6: Prototype DACs 61
6.1 A 12-bit 1-GS/s Dual-Rate Hybrid DAC . . . . . . . . . . . . . . . 61
6.1.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . 61
6.1.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . 62
6.1.2.1 Data Serializer . . . . . . . . . . . . . . . . . . . . 62
6.1.2.2 CML Latch Driver . . . . . . . . . . . . . . . . . . 64
6.1.2.3 Clock Generator . . . . . . . . . . . . . . . . . . . 64
6.1.2.4 Current-Steering Cell . . . . . . . . . . . . . . . . . 65
6.1.2.5 Digital Core . . . . . . . . . . . . . . . . . . . . . . 67
6.1.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 68
6.1.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2 A 12-bit 2-GS/s Dual-Rate Hybrid DAC . . . . . . . . . . . . . . . 75
6.2.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . 75
6.2.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . 76
6.2.2.1 Pulsed-Error Pre-distortion Logic . . . . . . . . . . 76
6.2.2.2 CML Latch and Drivers . . . . . . . . . . . . . . . 78
6.2.2.3 Current-Steering Cells . . . . . . . . . . . . . . . . 79
6.2.2.4 Error Measurement . . . . . . . . . . . . . . . . . . 81
6.2.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 83
6.2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3 A 16-bit 12-GS/s Single/Dual-Rate Hybrid DAC . . . . . . . . . . . 92
6.3.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . 92
6.3.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . 94
6.3.2.1 Tunable Bandpass DSM with Digital Chopper . . . 94
6.3.2.2 Current-Steering Cells . . . . . . . . . . . . . . . . 97
6.3.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 98
iv
6.3.3.1 Measurement Setup . . . . . . . . . . . . . . . . . 99
6.3.3.2 Static Performance . . . . . . . . . . . . . . . . . . 100
6.3.3.3 Dynamic Performance . . . . . . . . . . . . . . . . 102
6.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Chapter 7: Direct-Digital RF Modulator 108
7.1 Radio Revolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2 Power-Ecient DDRMs . . . . . . . . . . . . . . . . . . . . . . . . 110
7.2.1 Conventional DDRM . . . . . . . . . . . . . . . . . . . . . . 110
7.2.2 DDRM with Lowpass Hybrid DAC and TAF . . . . . . . . . 111
7.2.3 DDRM with Bandpass Hybrid DAC and Tri-Level TAF . . . 114
Chapter 8: Time-Approximation Filter 118
8.1 Reconstruction Filters . . . . . . . . . . . . . . . . . . . . . . . . . 118
8.2 Time-Approximation Filter . . . . . . . . . . . . . . . . . . . . . . . 121
8.2.1 Baseband Time-Approximation Filter . . . . . . . . . . . . . 121
8.2.2 Time-Interleaving Structure . . . . . . . . . . . . . . . . . . 125
8.2.3 RF Time-Approximation Filter . . . . . . . . . . . . . . . . 125
8.3 Tri-Level Time-Approximation Filter . . . . . . . . . . . . . . . . . 127
Chapter 9: Prototype DDRMs 130
9.1 A 1-5GHz DDRM with TAF . . . . . . . . . . . . . . . . . . . . . . 130
9.1.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . 130
9.1.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . 131
9.1.2.1 Hybrid DAC . . . . . . . . . . . . . . . . . . . . . 131
9.1.2.2 LO Generator . . . . . . . . . . . . . . . . . . . . . 132
9.1.2.3 Clock Generator . . . . . . . . . . . . . . . . . . . 133
9.1.2.4 Mixing Latch . . . . . . . . . . . . . . . . . . . . . 134
9.1.2.5 Output Driver . . . . . . . . . . . . . . . . . . . . 136
9.1.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 137
9.1.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.2 A 1-6GHz DDRM with Tri-Level TAF . . . . . . . . . . . . . . . . 147
9.2.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . 148
9.2.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . 148
9.2.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 154
9.2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Chapter 10:Conclusion and Future Directions 163
10.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
10.2.1 High-Speed and High-Resolution ADCs . . . . . . . . . . . . 164
10.2.2 Low-Power and Low-Jitter PLLs . . . . . . . . . . . . . . . 166
10.2.3 Software-Dened Radio . . . . . . . . . . . . . . . . . . . . . 166
v
10.2.4 Analog/Mixed-Signal Design Automation . . . . . . . . . . . 167
Appendix A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
A.1 Quantization Error of the Two-Stage DSM . . . . . . . . . . . . . . 180
vi
List Of Tables
5.1 Summary of Bandpass DSM . . . . . . . . . . . . . . . . . . . . . . 55
6.1 Performance comnparison with state-of-the-art CMOS DACs . . . . 90
6.2 Performance comnparison with state-of-the-art CMOS DACs . . . . 106
9.1 General performance summary . . . . . . . . . . . . . . . . . . . . . 146
9.2 Dynamic performance comparison . . . . . . . . . . . . . . . . . . . 146
9.3 Performance summary . . . . . . . . . . . . . . . . . . . . . . . . . 161
vii
List Of Figures
2.1 Heterodyne transceiver versus soft-ware dened radio . . . . . . . . 5
2.2 Input and output of a binary DAC . . . . . . . . . . . . . . . . . . 6
2.3 Schematic of a Current DAC . . . . . . . . . . . . . . . . . . . . . 7
2.4 Transmitter output spectrum with DAC non-linearity . . . . . . . 7
3.1 Proposed design objective versus conventional DAC architectures . 11
3.2 Behavior model of dual-rate hybrid DAC architecture . . . . . . . 11
3.3 SFDR performance comparison of the Nyquist DAC and dual-rate
hybrid DAC under LSB current-steering cell mismatches . . . . . . 16
3.4 Tradeo of SFDR and bandwidth as a function of segmentation ratio 17
4.1 Proposed delta-sigma assisted pre-distortion . . . . . . . . . . . . . 21
4.2 SFDR performance comparison with and without delta-sigma as-
sisted pre-distortion under MSB current-steering cell mismatches . 22
4.3 Current-steering DAC error mechanisms . . . . . . . . . . . . . . . 24
4.4 Error-correction scheme . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5 Superposition of DAC error pulses . . . . . . . . . . . . . . . . . . 26
4.6 DAC linearity degradation due to static and dynamic errors . . . . 26
viii
4.7 Analog compensation in Nyquist DAC versus digital pre-distortion
techniques in hybrid DAC . . . . . . . . . . . . . . . . . . . . . . . 28
4.8 Amplitude and timing resolution requirement based on SFDR spec-
ication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.9 Approximation model of timing error . . . . . . . . . . . . . . . . . 29
4.10 Proposed double-side timing-error approximation . . . . . . . . . . 32
4.11 Spectrum of error approximation with sinusoidal input signal . . . 35
4.12 Simulated DAC output spectrum with/without pulsed timing-error
pre-distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.13 Comparison of actual and approximation error pulses . . . . . . . . 37
4.14 Actual and approximated timing errors . . . . . . . . . . . . . . . 39
4.15 Simplied block diagram of the proposed inverse-sinc-shaped DPD
module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.16 Spectrum comparison for dierent timing error DPD schemes . . . 41
5.1 Implementation of rst-order DSM unrolling (2X case) . . . . . . . 43
5.2 Implementation of rst-order DSM unrolling (2X case) . . . . . . . 45
5.3 Implementation of the proposed unrolled pipeline 1-1-1 MASH (8X
case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.4 Block diagram of the multi-bit 1-1-1 MASH . . . . . . . . . . . . . 48
5.5 Spectrum comparison with and without bandwidth extension . . . 49
5.6 Traditional DSM noise-cancellation scheme . . . . . . . . . . . . . 49
5.7 Proposed DSM-assisted in-band noise-cancellation scheme . . . . . 50
5.8 Model of hybrid DAC with DSM-assisted in-band noise cancellation 51
5.9 Eective number of bits versus LPF bandwidth . . . . . . . . . . . 53
ix
5.10 3-bit pipelined successive DSM . . . . . . . . . . . . . . . . . . . . 57
5.11 Block diagram of single-stage and successive DSMs . . . . . . . . . 58
5.12 13-bit input/4-bit output single-stage DSM . . . . . . . . . . . . . 59
5.13 13-bit input/4-bit output successive DSM . . . . . . . . . . . . . . 59
5.14 PSD of DSM quantization noise; a =0:5 . . . . . . . . . . . . . . 60
6.1 Proposed dual-rate hybrid DAC architecture with a split Nyquist
(MSB) and delta-sigma (LSB) path . . . . . . . . . . . . . . . . . . 62
6.2 Block diagram of an 8-to-1 data serializer . . . . . . . . . . . . . . 63
6.3 Timing diagram of the clock and data within a data serializer . . . 63
6.4 Block diagram of a clock generator . . . . . . . . . . . . . . . . . . 65
6.5 Schematic of a phase rotator . . . . . . . . . . . . . . . . . . . . . 66
6.6 Schematic of current-steering cells . . . . . . . . . . . . . . . . . . 66
6.7 Micrograph of the test chip in a 65 nm CMOS technology . . . . . 68
6.8 MSB current-steering cell mismatches . . . . . . . . . . . . . . . . 69
6.9 Measured spectra with (a)f
in
= 7 MHz within DC-500 MHz, (b)f
in
= 7 MHz within zoomed-in band of interest, and (c)f
in
= 494.7 MHz 70
6.10 Measured spectra with (a) before and (b) after applying the delta-
sigma assisted pre-distortion . . . . . . . . . . . . . . . . . . . . . 71
6.11 Measured spectra with (a) before and (b) after applying the DWA 71
6.12 SFDR performance versus signal frequency . . . . . . . . . . . . . 72
6.13 NSD versus signal frequency . . . . . . . . . . . . . . . . . . . . . 73
6.14 System-level block diagram of the proposed hybrid DAC . . . . . . 75
6.15 Implementation of pulsed-error generator . . . . . . . . . . . . . . 77
x
6.16 Timing diagram of pulsed-error pre-distortion . . . . . . . . . . . . 78
6.17 CML latches and drivers . . . . . . . . . . . . . . . . . . . . . . . . 79
6.18 Biasing circuits of dual-rate hybrid DAC . . . . . . . . . . . . . . . 80
6.19 Comparison of conventional and proposed DAC on SFDR vs. XLSB
mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.20 Similated NSD at 60 MHz output frequency vs. XLSB mismatch, 0
dBm, full-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.21 DAC error measurement . . . . . . . . . . . . . . . . . . . . . . . . 82
6.22 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.23 Measured amplitude and timing errors . . . . . . . . . . . . . . . . 85
6.24 Spectrum snapshot with and without pre-distortion whenf
sig
= 7.88
MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.25 Spectrum snapshot with and without pre-distortion whenf
sig
= 949
MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.26 NSD comparison with and without proposed in-band noise cancella-
tion, 3 dBm, full-scale . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.27 SFDR versus signal frequency, 3 dBm, full-scale . . . . . . . . . . . 87
6.28 SFDR performance compared with state-of-the-art CMOS DACs, 3
dBm, full-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.29 IM3 perfromance compared with state-of-the-art CMOS DACs, 3
dBm, full-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.30 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.31 Implementation of a second-order three-stage successive pipelined
DSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.32 3-bit DSM: (1) Without pipelining; (b) With pipelining . . . . . . 94
xi
6.33 DSM with choppers . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.34 Spectrum of an eight-way TI DSM . . . . . . . . . . . . . . . . . . 96
6.35 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.36 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.37 Measured errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.38 Measured single-tone spectrum with F
sig
= 3 GHz at F
s
= 9GS/s . 102
6.39 Measured two-tone spectrum with F
sig
= 3 GHz at F
s
= 9GS/s . . 102
6.40 Measured SFDR, 3 dBm, full scale . . . . . . . . . . . . . . . . . . 103
6.41 Measured SFDR and IM3 versus other high-speed CMOS DACs, 3
dBm, full scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.42 Measured SFDR in hybrid mode, 3 dBm, full scale . . . . . . . . . 104
6.43 Measured NSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.1 Radio revolution trend (digital versus analog) . . . . . . . . . . . . 109
7.2 Heterodyne versus software-dened transmitters . . . . . . . . . . . 109
7.3 Conventional DAC-based DDRM . . . . . . . . . . . . . . . . . . . 110
7.4 DDRM with a lowpass hybrid DAC . . . . . . . . . . . . . . . . . 111
7.5 Conventional DDRM versus proposed DDRM with TAF . . . . . . 112
7.6 DDRM with bandpass hybrid DAC and tri-level TAF . . . . . . . 114
7.7 Bandpass hybrid DAC . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.8 Tir-level TAF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.9 Combined noise transfer functions with dierent DSM and TAF con-
gurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
xii
8.1 Summary of DAC reconstruction lters . . . . . . . . . . . . . . . 120
8.2 Zero-order-hold reconstruction lter . . . . . . . . . . . . . . . . . 121
8.3 Generic FIR reconstruction lter . . . . . . . . . . . . . . . . . . . 122
8.4 Generation of time-approximation lter response . . . . . . . . . . 122
8.5 Time-approximation reconstruction lter . . . . . . . . . . . . . . . 123
8.6 Long versus short impulse responses . . . . . . . . . . . . . . . . . 124
8.7 Timing diagram of an eight-way interleaved return-zero DAC . . . 124
8.8 Timing diagram of an eight-way interleaved non-return-zero DAC
with TAF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.9 Upconversion via a mixer . . . . . . . . . . . . . . . . . . . . . . . 126
8.10 Combining baseband TAF pattern with a uniform LO in digital do-
main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.11 Tri-level time-approximation lter . . . . . . . . . . . . . . . . . . 128
8.12 Tri-level TAF response generation . . . . . . . . . . . . . . . . . . 128
9.1 System block diagram of the proposed DDRM . . . . . . . . . . . . 131
9.2 Hybrid DAC Structure . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.3 High-speed serializer-based LO modulator . . . . . . . . . . . . . . 132
9.4 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.5 Master-slave latches . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.6 Mixing latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7 Class-A current-steering driver and
oor planing . . . . . . . . . . 135
9.8 Eight-way time-interleaved quadrature structure . . . . . . . . . . 136
xiii
9.9 Chip micrograph and performance summary . . . . . . . . . . . . . 137
9.10 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.11 Measured DDRM output power . . . . . . . . . . . . . . . . . . . . 139
9.12 Spectra of single-/two-tone signal in baseband mode . . . . . . . . 140
9.13 Measured IM3 versus signal frequency . . . . . . . . . . . . . . . . 141
9.14 Spectra of a 20-MHz 256 QAM and a 10-MHz 1024 QAM signals at
2.4 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.15 Constellations of the QAM signals at 2.4 GHz . . . . . . . . . . . . 142
9.16 Constellations of the QAM signals at 4.4 GHz . . . . . . . . . . . . 143
9.17 Impulse responses of the FIR lters . . . . . . . . . . . . . . . . . 144
9.18 Measured NSD with dierent lter and DSM congurations . . . . 144
9.19 NSD performance comparison with state-of-the-art transmitters . . 145
9.20 System block diagram of proposed DDRM . . . . . . . . . . . . . . 149
9.21 Implementation of sub-channel DAC . . . . . . . . . . . . . . . . . 150
9.22 Current-steering cell . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.23 Error-feedback bandpass DSM . . . . . . . . . . . . . . . . . . . . 152
9.24 DSM congurations . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.25 Implementation of high-speed bandpass DSM . . . . . . . . . . . . 153
9.26 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.27 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . 155
9.28 P
sat
versus F
LO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
xiv
9.29 Measured spectrum and constellation of a 20-MHz 256 QAM signal
at 2.2 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.30 Measured NSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.31 Measured ACLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9.32 Measured ACLR1 over carrier frequencies . . . . . . . . . . . . . . 160
9.33 Measured spectra before and after channel gain calibration . . . . . 160
10.1 Summary of ADC architectures . . . . . . . . . . . . . . . . . . . . 164
10.2 Flash, Delta-Sigma, SAR and Pipeline ADCs . . . . . . . . . . . . 165
10.3 DTC-assisted high performance TDC for all-digital PLL . . . . . . 166
10.4 Heterodyne transceiver versus software-dened radio . . . . . . . . 167
10.5 Analog/mixed-signal design automation tool . . . . . . . . . . . . . 168
xv
Chapter 1
Introduction
1.1 Motivations
The demand for spectrum access has increased since the inception of smartphones.
Traditionally, the integration of multiple transmitters has been required to cover
such a wide band and to support multiple standards. As digital operations have
become faster and more cost eective, it has become possible to move analog opera-
tions into the digital domain. This has invoked the concept of the software-dened
radio, which is mostly digital and highly
exible. In this type of system, a high-
performance digital-to-analog converter (DAC) that is able to convert digital bits
to a radio frequency (RF) signal is key. Additionally, since many emerging wire-
less systems aim for high spectral eciency, it requires a DAC with a good in-band
spurious-free dynamic range (SFDR) and a low noise spectral density (NSD), which
is challenging with current CMOS technology. Therefore, it motivates us to explore
1
a suitable DAC architecture to synthesize a high-delity signal over a wide fre-
quency band.
1.2 Organization
This dissertation consists of ten chapters. Following the introduction, the concept
of direct-digital RF conversion will be discussed in Chapter 2, including background
introduction, challenges, previous research, and a brief highlight of proposed solu-
tions. Chapter 3 introduces and provides a detailed analysis of the hybrid DAC
architecture. Circuit design tradeos are discussed to better explain the pros and
cons of this architecture. Taking the advantages provided by the delta{sigma mod-
ulator (DSM) in a hybrid DAC, a set of DSM-assisted digital pre-distortion (DPD)
techniques that address both static and dynamic DAC errors are presented after
a review of existing solutions and their limitations. Chapter 5 describes the de-
sign techniques of a high-speed DSM, which is the key functional block of a hybrid
DAC, and the main limitations on the operating speed of the hybrid DAC, given
the current CMOS technology. After the discussions on proposed techniques, im-
plementation and measurement results of three prototype DACs will be presented
in Chapter 6, including a 12-bit 1-GS/s dual-rate hybrid DAC, a 12-bit 2-GS/s
dual-rate hybrid DAC, and a 16-bit 12-GS/s single/dual-rate hybrid DAC.
Chapter 7 introduces the direct-digital RF modulator (DDRM) as one of the
important contributors to current radio revolution and describes how the hybrid
2
DAC architecture and techniques based on this architecture can be applied to
and improve the performance of a DDRM. In addition, a highly
exible time-
approximation lter (TAF) that enables a surface acoustic wave (SAW)-less all-
digital transmitter is also brie
y introduced and elaborated in Chapter 8. The
analysis of TAF starts with a review of existing reconstruction lters, which is
followed by mathematical modeling and numerical simulations. Enhanced TAF
techniques are presented in steps. Similarly, the implementation and testing of two
DDRM prototypes based on a hybrid DAC structure and TAF are elaborated in
Chapter 9. Finally, Chapter 10 summarizes the above-mentioned techniques and
discusses future research directions.
3
Chapter 2
Direct-Digital RF Conversion
2.1 Basic Concepts
High-speed, high-linearity, digital-to-analog converters (DAC) are in demand for
many modern electronic systems, including instrumentation applications, radar,
and cable television systems. A wideband linear DAC also enables direct RF syn-
thesis, whereby most signal processing can be implemented in the digital domain
and then directly converted into wideband analog signals. As an example, as shown
in Fig. 2.1, a conventional heterodyne transmitter includes a digital signal process-
ing (DSP) unit, DAC, lters, mixer, variable gain ampliers, power amplier (PA),
and multiples of these building blocks for supporting multi-band and standard com-
munications. An alternative solution is to move the upconversion, gain control, and
band selection modules to the digital domain, which requires a high-performance
DAC that covers all the signal bands with a suciently linear operation, leading to
a highly
exible system with signicant cost reduction. As technology scaling , DSP
4
RF
High-speed clock
DAC
I
Q
DSP
Digital Analog
Analog Digital
DSP
PA
0
o
90
o LO
DAC
DAC
x N
I
Q
voltage
Time
1 0 1 0 0 1 1 …
0 1 0 1 1 0 0 …
0 0 1 1 1 0 1 …
1 1 1 0 0 1 0 …
RF Output
RF
Figure 2.1: Heterodyne transceiver versus soft-ware dened radio
capacity is dramatically enhanced due to higher integration density, faster transis-
tor speed, and lower power dissipation, which makes this kind of digitally-intensive
architecture increasingly attractive.
A DAC generally reconstructs an analog signal that is continuous in both time
and amplitude from a sequence of digital data, as shown in Fig. 2.2. According to
the Nyquist sampling theory, an ideal signal, with a bandwidth equal to or less than
half of the sampling frequency, is encoded in a discrete time sequence. In reality, the
DAC is not linear and will introduce distortion to the reconstructed analog signal
during conversion. The distortion typically leads to harmonic or inter-modulation
tones that will degrade the spectrum purity, i.e., dynamic range.
5
DAC
1 0 1 0 0 1 1 …
0 1 0 1 1 0 0 …
0 0 1 1 1 0 1 …
Digital Analog
0
1
2
time time
{
0
,
1
,
2
, … ,
}
Distorted
Signal
Ideal
Signal
N-Bit Digital Input
0 0 1 1 1 01 …
Figure 2.2: Input and output of a binary DAC
There are dierent types of DAC, including the resistor DAC, the capacitor
DAC, the current DAC, and combinations of them. Among them, the current DAC
presented in Fig. 2.3 is widely used in high-speed applications. Binary weighting
is achieved via sizing the current sources. Digital signals control the switches to
turn on or o the current source to perform 1-bit multiplications. The nal current
summation is undertaken by simply connecting the current sources to each other,
and the net current then
ows through a load to generate an analog voltage output.
There are many circuit non-idealities that cause DAC non-linearity, such as process
mismatches, timing skew, gradient eect, and nite output impedance. When we
observe the DAC output waveform, most of the non-idealities result in two types
of errors. Deviation from the ideal amplitude level is dened as an amplitude error
in this thesis, and deviation at the transition edges is dened as a timing error.
The solution that we proposed to compensate for these errors will be elaborated in
Chapter 4.
6
Amplitude
Error
DAC
output
( + + +… +
) ∙
Timing
Error
Figure 2.3: Schematic of a Current DAC
Signal
Noise
Spur
Frequency
Magnitude
Mask
Signal Bandwidth
Dynamic
Range
Figure 2.4: Transmitter output spectrum with DAC non-linearity
2.2 Challenges and Solutions
Figure 2.4 presents the output spectrum of a modulated signal that is generated by
a non-linear DAC. The spurs and adjacent channel leakage caused by the above-
mentioned non-idealities dene the dynamic range of the DAC. As signal bandwidth
increases, DAC non-linearity usually becomes worse due to limited transition time
and circuit parasitic.
Typically, high performance wideband DACs exploit a compound semiconductor
or bipolar CMOS (BiCMOS) process due to their superior device characteristics;
however, they incur higher costs [1], [2]. The objective here is to explore an ecient
7
DAC architecture using a standard digital CMOS process and push the envelope of
achievable linearity and data rate. Consequently, the proposed hybrid DAC archi-
tecture facilitates system-on-chip (SOC) integration and reduces implementation
costs compared to compound and BiCMOS devices.
One challenge of the proposed architecture is that, given the current CMOS
technology, it is very hard for the DSM to operate beyond 1 GHz. Based on this
issue, a means of accelerating the DSM operation speed are proposed and presented
in Chapter 5.
The other major challenge is to achieve a high dynamic range for a wideband
DAC. To minimize the process variation eect, each DAC element must be sized
suciently large for tolerance. However, large-size transistors result in large out-
put parasitic, which signicantly degrades DAC linearity as the signal frequency
increases. The proposed hybrid DAC architecture breaks the limit of this trade-
o and partially solves the issue. In addition, DSM-assisted DPD techniques are
proposed to tackle the remaining part of the issue for better linearity over a wide
frequency range. There is a more detailed discussion of this in Chapter 6.
To some extent, the eort to improve the intrinsic linearity of the DAC increases
exponentially due to the sophisticated digital signal processing and the limitation
of the CMOS process. Although the hybrid architecture has been proven to be ef-
fective in terms of both speed and linearity, the dynamic range it can provide is still
8
not sucient to meet the extremely stringent requirements of frequency division du-
plexing (FDD) systems. An o-chip SAW lter is typically needed, which occupies
a very large area, particularly when multi-band and multi-standard applications are
needed. A TAF embedded in the upconversion process of a transmitter is proposed
to achieve a low out-of-band (OOB) noise level that is sucient to support most
wireless applications. More detail regarding the design and implementation of TAF
is given in Chapter 8.
9
Chapter 3
Hybrid DAC Architecture
3.1 Overview of DAC Architectures
Figure 3.1 shows conventional DAC architectures over dierent sampling rates and
achievable spurious free dynamic range (SFDR). Nyquist current steering DACs [3]-
[11] are typically adopted to achieve>GHz bandwidth with limited linearity due to
the non-idealities of large-scale current steering cell arrays such as manufacturing-
induced random and systematic variations. On the other hand, delta-sigma DACs
allow higher linearity [12], [13], [14], but the oversampling ratio requirement limits
their usage in wideband applications. Moreover, to deliver the same output power as
the Nyquist DAC, the current cells used in a delta-sigma DAC should steer a larger
amount of current, causing undesired eects such as larger total quantization noise
and higher sensitivity to clock jitter. To break the limitations of the aforementioned
DAC architectures, we propose a dual-rate hybrid DAC architecture that leads to
minimal analog complexity and maximizes the linearity and bandwidth at the same
10
Figure 3.1: Proposed design objective versus conventional DAC architectures
Figure 3.2: Behavior model of dual-rate hybrid DAC architecture
time [20], [21]. The digital pre-distortion scheme is exploited to further optimize
the proposed architecture. Ecient digital signal processing (DSP) implementation
architecture is also explored to facilitate high-speed operation with standard digital
electronic design automation (EDA) design
ow.
3.2 Hybrid DAC
The key idea of a dual-rate hybrid DAC architecture is to divide the input digital
code into two paths: the upper path takes a certain number of most signicant
11
bits (MSBs) and operates at the Nyquist rate, while the lower path takes the re-
maining least signicant bits (LSBs) and operates at some oversampling rate via
a delta-sigma modulator (DSM), as shown in Fig. 3.2. In the time-domain view,
it essentially modulates the high-speed dithering signal on top of the Nyquist non-
return-to-zero waveform [15]. Since the DSM in the lower path further compresses
the bit width, the overall DAC current cells are reduced compared to a conven-
tional Nyquist DAC. The reduced bit width together with DSM dithering reduces
the impact of analog circuit non-idealities and yields a more compact layout for
the sensitive signal path. This is crucial to improve the DAC linearity perfor-
mance, particularly at high frequency. Moreover, since the input can be divided
into two paths with dierent weighting, i.e., segmentation ratio, there is a tradeo
between the achievable bandwidth and linearity. Generally speaking, the key de-
sign objective is to distribute most of the signal energy via the MSB path, while
ne accuracy is obtained via the LSB dithering path. This combination allows
the proposed DAC architecture to potentially achieve high output power, speed,
and linearity simultaneously, beyond the limitations of conventional Nyquist and
delta-sigma oversampling DAC architectures.
Since the DAC input is divided, it is important for the design to guarantee that
the two paths go through the same transfer function. Figure 3.2 shows the behavior
model of the dual-rate hybrid DAC. The MSB path maintains the same Nyquist rate
as input, i.e.,f
s
, while the LSB path exploits a zero-order-hold (ZOH) interpolator
12
that up-converts the sampling rate to f
os
. Therefore, the transfer function of both
paths can be described as follows:
Y
MSB
(f) =e
jf=fs
sinc(f=f
s
)
+1
X
n=1
X
MSB
(fnf
s
) (3.1)
Y
LSB
(f) =
"
e
jf=fs
sin(f=f
s
)
e
jf=fos
sin(f=f
os
)
f
s
+1
X
n=1
X
LSB
(fnf
s
)
+E
shaped
(f)
i
e
jf=fos
sin(f=f
os
)
f
=e
jf=fs
sinc(f=f
s
)
+1
X
n=1
X
LSB
(fnf
s
)
+e
jf=fos
sinc(f=f
os
)
E
shaped
(f)
f
os
(3.2)
The above equations conrm that, as required, the signal transfer function in
both paths is identical without any mismatch. Meanwhile, the DSM quantization
errorE
shaped
in the LSB path is modulated by a sinc function with nulls at integer
multiples of f
os
.
3.3 Segmentation Ratio Tradeos
For the N-bit dual-rate hybrid DAC, one can vary the energy weighting between
MSB and LSB paths, which tradeos the bandwidth and linearity. We dene the
segmentation ratio r as the portion of the total signal energy in the MSB path. For
example, if M out of N bits are chosen for the MSB path, r can be expressed as:
(2
N
2
NM
)=(2
N
1). If M = N, it becomes a pure Nyquist DAC, i.e. r = 1.
13
The fact that r is close to 1 except for very small M values shows an important
characteristic of the proposed hybrid DAC concept. For suitable values of M, only
a small portion of signal energy is allocated in the oversampled DSM path while
most of the signal energy is still delivered to the DAC output by MSB current
steering cells toggling at the Nyquist rate.
3.3.1 Bandwidth
First, we derive the bandwidth tradeos with the segmentation ratior. Bandwidth
is dened as the band with a noise spectral density that is below that of an N-bit
Nyquist DAC. In the case of the k
th
order DSM with a (1z
1
)
k
noise transfer
function, the in-band noise
oor suppression should satisfy the following equation:
20log
10
2sin
f
f
os
k
6(NM); 8f BW (3.3)
whereM is the number of MSB bits and BW is the bandwidth. By substituting M
with the segmentation ratio, BW can be derived from (3.3) as:
BW
f
os
sin
1
(
10
3log
2[
2
N
r(2
N
1)
]
10k
)
(3.4)
According to the above equation, increasing r or k results in a wider bandwidth.
14
3.3.2 Linearity
Next, we examine the DAC linearity tradeos with the segmentation ratio. There
are two key mechanisms that result in better SFDR when the segmentation ratio is
reduced. One is the compact analog layout, while the other is the DSM dithering
in the LSB path. As a result of the dual-rate hybrid DAC architecture, the total
number of current steering cells can be reduced. Specically, for the segmentation
ratio of r, the total number of current steering cells can be expressed as 2
N
=[2
N
r(2
N
1)], assuming the MSB path is thermometer coded with 1-bit DSM output
in the LSB path. Given a certain matching accuracy, the layout area increases
proportionally with the number of current cells. It is well known that there is a
gradient correlation between the mismatch error and spatial position [8], [9] due to
the manufacturing process, i.e., a larger physical spacing results in a worse mismatch
expected between two elements with an identical layout. Moreover, the compact
layout also results in less skewing for clock distribution, interconnect parasitics,
and IR drops in supplies due to shorter physical wire routings. As a result, the
reduced non-idealities lead to better linearity by minimizing static and dynamic
errors. This is particularly important for achieving high SFDR at a high frequency
as dynamic error compensation is generally less eective than that of static error.
The second mechanism is that DSM dithering helps to mitigate the non-idealities of
current steering cells, such as the mismatch associated with each current cell. For
a conventional Nyquist DAC with binary weighted elements, each current branch is
15
Figure 3.3: SFDR performance comparison of the Nyquist DAC and dual-rate
hybrid DAC under LSB current-steering cell mismatches
selected by a periodic pattern in the case of sinusoidal input. Therefore, the errors
associated with each current cell appear as some periodic pattern and result in
harmonic distortions. Since DSM dithers the input pattern and results in a noise-
like output bit stream, the error pattern is eectively randomized and hence the
harmonic tones are whitened without using dynamic element matching techniques,
such as those described in [16].
To validate the linearity improvement due to DSM dithering, MATLAB simu-
lations were performed to compare the proposed hybrid and conventional Nyquist
DACs, where mismatches are introduced only in the LSB current cells since mis-
matches of the MSB ones cannot be alleviated by DSM dithering. Instead, MSB
16
Figure 3.4: Tradeo of SFDR and bandwidth as a function of segmentation ratio
mismatches will be addressed by the proposed pre-distortion technique in Chap-
ter 4. Figure 3.3 shows that larger mismatch error deviation leads to more SFDR
improvement.Furthermore, when the segmentation ratio is reduced, more signal en-
ergy will be dithered by the DSM, and this results in better SFDR improvement
over the Nyquist band.
In conclusion, Figure 3.4 summarizes the general tradeo of SFDR and band-
width as a function of the segmentation ratio for the dual-rate hybrid DAC ar-
chitecture. The design region is bounded by the target bandwidth and SFDR, as
indicated by the shaded area. Within the region, other design considerations, such
as digital circuit complexity and speed/power tradeo, can be explored. In our
rst 12-bit, dual-rate, hybrid DAC prototype, we target the 500 MHz bandwidth
17
and >80dB SFDR in the design phase. Given the Monte-Carlo SPICE simulation
results as well as the acceptable digital DSM complexity, a 4-8 segmentation (M =
4 bits in the Nyquist path) was chosen as an optimal case, i.e., a segmentation ratio
of 0.9377. It is also noteworthy that a dual-rate hybrid DAC reduces out-of-band
noise in comparison with pure a delta-sigma DAC since signicantly less signal en-
ergy is distributed to the DSM path. In conjunction with proper DSM topology,
the hybrid DAC can further suppress the noise
oor, which will be discussed in
Chapter 5. Additionally, since the number of LSB current cells are compressed by
the DSM, it further reduces the overall area occupied by the current cell array. The
compactness of the current cell array relaxes the clock/signal routing constraints
and minimizes the spatial variation.
18
Chapter 4
DSM-Assisted Digital Pre-distortion
4.1 Existing Techniques and Limitations
There are many possible circuit non-idealities that degrade the linearity of a DAC.
In this dissertation, we focus more on resolving both the static amplitude er-
ror and dynamic timing errors owing to the mismatches between DAC current
cells. A few existing techniques have been reported to resolve either static er-
rors [3], [24], [26], [27] or dynamic errors [6], [7], [28]. Randomization techniques,
such as DEM in [16], [19] or DWA in [29], [30], [31] can help mitigate both static
and dynamic errors but at the cost of increased noise
oor. Without degrading
noise performance, a dynamic-mismatch mapping (DMM) scheme in [11] lever-
ages the orthogonality nature of errors and proposes an eective way of detecting
and calibrating both static amplitude and dynamic timing errors through sorting
and optimizing the switching sequence of the current-steering cells. A 3D sort-
and-combine (3D-SC) technique in [23] further extends DMM by combining some
19
thermometer-coded current-steering cells into binary units. Compared to DMM, 3D
error vectors are further minimized via combining, and this incurs more area reduc-
tion for the same yield requirement according to [24]. However, the performance of
DMM and 3D-SC is highly dependent on error patterns, and they cannot be imple-
mented together with randomization techniques for further linearity improvement.
Instead, we propose a more generic solution in [32] called pulsed-error pre-distortion
(PEPD), to tackle both amplitude and timing errors together without penalty on
noise performance, PEPD is independent of error patterns and exploits the full
advantage of the dual-rate hybrid DAC architecture. For better explain the PEPD
scheme, we will rst discuss the general concept of DSM-assisted pre-distortion and
use static error compensation as an example.
4.2 DSM-Assisted Pre-distortion
In the Chapter 3, we focused on the non-idealities in the LSB path and how the
hybrid architecture constraint is relaxed compared to conventional Nyquist DACs.
However, SFDR degradation due to current mismatches in the MSB path still
exists and is not better than the conventional Nyquist DACs. Therefore, the delta-
sigma assisted pre-distortion scheme is proposed to take advantage of the hybrid
architecture and completely compensate for MSB mismatch errors in the digital
domain.
20
Thermometer
Decoder
x1
B
0
x2 x4 x8 x8
B
1
B
3
U
0
U
13
Digital Input
8-to-1 Serializer Delay Equalizer
LSB
-
+
MSB
U
14
U14
U13
U12
U1
U0
x8
DWA
x8 x8
B
2
U
12
LSB MSB
LSB bits
Interpolator
input
8 bits
10 bits
13 bits
Interpolator
Mismatch
code
Figure 4.1: Proposed delta-sigma assisted pre-distortion
Since the dynamic performance of the DAC degrades with increasing parasitic
capacitance of the current cells due to the reduced output impedance at high fre-
quency [6], current cell transistors should be designed with a smaller geometry.
However, from a matching perspective, larger transistors are preferred for better
matching. To resolve this dilemma, the conventional approach is to design smaller
sized current sources with poor matching and then compensate the mismatch er-
ror with additional ne-resolution current cells [2], [3]. The increased number of
current cells, parasitics, and their associated errors still limit the obtainable DAC
SFDR.
Given the dual-rate hybrid DAC architecture, we propose to use the DSM in
the LSB path to compensate for the mismatch errors of the MSB path; we refer to
this as delta-sigma assisted pre-distortion scheme. Since the DSM provides a \ne"
calibration DAC due to the nature of oversampling and noise shaping, the mismatch
errors of the MSB path can be compensated through the DSM path without using
21
Figure 4.2: SFDR performance comparison with and without delta-sigma assisted
pre-distortion under MSB current-steering cell mismatches
any additional current cell. As shown in Fig. 4.1, the current mismatch errors
of MSB branches are measured o-chip and stored in the on-chip memory. Based
on specic MSB branches that are going to be \turned on," corresponding errors
will be read from the on-chip memory and subtracted from the oversampling DSM
path. Eectively, there is no current error for those turned-on MSB branches.
Moreover, this pre-distortion technique can be used in conjunction with a data-
weighted averaging (DWA) algorithm to further randomize other dynamic errors,
such as time skews. The aggregated mismatch error is computed based on the
selected current cells and subtracted at the DSM input by appending extra LSB
bits, i.e., a \ne" calibration DAC. The implementation overhead of increasing the
digital word length is minimal.
22
A numerical simulation shows that SFDR degradation due to mismatch is sub-
stantially mitigated by applying the proposed technique, as illustrated in Fig. 4.2.
As a result, the greatly relaxed matching requirement allows the current cells in
the MSB path to utilize smaller transistors, which are preferred for achieving high
SFDR at high frequency.
4.3 Pulsed Error Pre-distortion
This section rst reviews DAC error mechanisms and describes the proposed PEPD,
which calibrates both amplitude and timing errors in a unied platform. This
involves measuring the errors and subtracting them from the digital domain via
the ne amplitude and time-resolution path of the dual-rate hybrid DAC structure.
4.3.1 Amplitude and Timing-error Mechanisms in DAC
In a current-steering DAC design, amplitude errors are mainly caused by current
mismatches between the current-steering cells (CSCs), which directly contribute
to the DNL of the DAC. Those static amplitude errors typically dominate overall
linearity at lower output frequencies. As the frequencies become higher, the unequal
toggling time instants between CSCs begin to increasingly degrade DAC linearity,
which we will refer to as \timing errors" in the context of this dissertation.
To better explain the error mechanism of current-steering DAC, we use an ex-
ample with two unitary CSCs. As shown in Fig. 4.3, one current cell (annotated
23
∆
∆
∆
2
∆
∆
∆
2
∆
+1
DAC
output
+1
+1
-1
-1 -1
Ref.
DUT
w/ Duty-cycle skew (∆
)
w/ delay skew (∆
)
Ref. Current pulse
w/ amp. Mismatch (∆)
1
2
3
4
Amp. error
Delay error
Duty-cycle error
Ideal output
1 2
1 3
1 4
CS cell
∆
Timing Error
Figure 4.3: Current-steering DAC error mechanisms
REF) provides a reference current pulsei
1
, while the other current cell (DUT) gen-
erates a current pulsei
2
. Ideally, thei
1
andi
2
pulses should match exactly, both in
amplitude and time, for a perfectly matched DAC. Due to manufacturing variabil-
ities (such as lithography gradient eects and dopant
uctuations), the tail-current
source of the REF and DUT cells will most likely conduct dierent currents, thus
resulting in dierent pulse amplitudes. The amplitude error is then dened as the
dierence between the i
1
and i
2
pulses under this condition; it appears as an error
pulse with the same duration as the DAC input sampling period. In addition, the
clock skews (t
skew
) and the delay variation along the signal path (
13
) can
cause the i
1
and i
2
pulses to arrive at the DAC output with dierent time delays.
24
DAC
input
Implemented
in digital
Distorted
output
Calibrated
output
in out
Errors
- Errors
Ideal pulse
Figure 4.4: Error-correction scheme
This delay error dened as the dierence in i
1
and i
2
appears as two short pulses
with the same duration of delay dierence and constant magnitude, but in opposite
polarity. Similarly, the oset voltage variation (V
os;13
) along the signal paths
can cause the duty cycle of the i
1
and i
2
pulses to vary. This variance leads to
duty-cycle error, which appears as two short pulses with the same magnitude and
polarity. This research focuses on these three kinds of error mechanisms, which are
orthogonal to one another. (Note that we refer to the delay and duty-cycle errors
as \timing errors" in the context of this dissertation.) Finally, by toggling the two
current cells in the opposite polarities, we can individually measure those errors.
25
Amplitude
Error
DAC
Output
+
+
+ …
Timing
Error
Amp. err1
Delay err1
Duty-c. err1
Amp. err2
Delay err2
Duty-c. err2
Total
Errors
Figure 4.5: Superposition of DAC error pulses
SFDR[dBc]
I
Static Errors
Dynamic Errors
Sample rate/Signal frequency
II
Figure 4.6: DAC linearity degradation due to static and dynamic errors
26
4.3.2 The Concept of Pulsed-Error Pre-distortion
Assuming that the aforementioned three error pulses are rst measured for a par-
ticular CSC, the basic concept of PEPD is to subtract those error pulses anywhere
from the signal path such that the output will be restored to a perfect current pulse
without any error as shown in Fig. 4.4. Since the nal DAC output is the super-
position of all CSCs (with the polarity depending on the input code), the three
pulse errors from each cell can be separately programmed and summed based on
their digital control codes as shown in Fig. 4.5. The aggregated errors can then
be subtracted from the signal path. Figure 4.6 qualitatively shows a generic DAC
linearity tradeo with sampling frequency or signal frequency, where region I and
II are limited by static and dynamic errors [11], respectively. The objective of ap-
plying the PEPD is that amplitude-error subtraction will improve lower-frequency
linearity, while the timing-error subtraction improves higher-frequency linearity.
To apply the PEPD concept in a Nyquist DAC, additional ne analog CSCs are
typically used and are controlled by the measured error pulses as shown in Fig. 4.7.
This step will not only increase the analog design's complexity and constraints, but
will also add extra parasitics at the DAC output, which inevitably degrade high-
frequency performance. Instead, we propose leveraging the oversampling path of
the hybrid DAC and digitally subtracting the measured error pulses at the DSM
input. Extra CSCs can be thus avoided. More importantly, the oversampling path
naturally provides accurate amplitude resolution via DSM, as well as ne time
27
DAC
input
Digital Pre-distortion for Hybrid DAC
DAC
output
DAC with
Errors
MSB
LSB
Analog Compensation for Nyquist DAC
DAC
output
DAC with
Errors
DAC
input
Amp. err
Delay err
Duty-c. err
Measured
errors
Cal. DAC
Digital Digital Analog Analog
Figure 4.7: Analog compensation in Nyquist DAC versus digital pre-distortion
techniques in hybrid DAC
resolution since the sample rate is higher. These are critical properties for eective
PEPD. Note that, since the proposed PEPD compensates the error in the digital
domain, it requires additional dynamic range at the DSM input. Therefore, we
add three redundant code levels at the DSM input to accommodate the expected
amplitude and timing errors.
4.3.3 Quantization of Error Pulses
In reality, error pulses should be quantized both in amplitude and time to be im-
plemented. The quantization resolution aects the pulsed-error cancellation's ac-
curacy, and hence overall linearity. As an example shown in Fig. 4.8, we perform
numerical simulations for a target SFDR of 80 dBc at 1 GHz frequency and de-
termine that the amplitude and time resolution should be <1 A and <100 fs.
28
Amplitude resolution: <1uA Timing resolution: <1ps
Signal bandwidth[Hz]
SFDR
Target
Different
Timing
Errors(s)
Current mismatch[%]
SFDR
Target
Figure 4.8: Amplitude and timing resolution requirement based on SFDR speci-
cation
time time
Frequency Frequency
0
0
time
Frequency
0
y
Figure 4.9: Approximation model of timing error
29
While the required amplitude resolution is achievable via the DSM path of the hy-
brid DAC, the<100 fs time accuracy is hardly achievable, as it requires a>10 THz
clock to generate the compensation signal. We thus relax the time-accuracy require-
ment by joint design between the amplitude and time duration of the timing-error
pulses (TEPs). To see how time resolution trades o with approximation accu-
racy, we approximate the TEPs as a weighted impulse train that convolves with a
short-duration pulse; the weights correspond to the aggregate timing errors from all
current cells, while time spacing between impulses corresponds to the DAC sample
rate. In the frequency domain, it is essentially a Fourier-transformed impulse train
multiplied with a Sinc function, as shown in Fig. 4.9. Assuming the duration of
the actual error pulse is T
1
, and T
2
is the approximated error-pulse duration, the
output response in the frequency domain in these two cases can be expressed as
Y
1
(f) =e
jfT
1
T
1
I
sinc(fT
1
)X(f) (4.1)
Y
2
(f) =e
jfT
2
T
2
I
sinc(fT
2
)X(f) (4.2)
whereI
is the output current of each current cell. To make a good approximation
at least for low frequencies, the goal is to match the DC gain between (4.1) and
30
(4.2). The approximated error pulse should thus be adjusted by a modication
factor and can be expressed as follows:
=
T
1
sinc(fT
1
)e
jfT
1
T
2
sinc(fT
2
)e
jfT
2
f=0
=
T
1
T
2
(4.3)
Note that nulls are still created by the Sinc function at integer multiples of 1/(pulse
duration). Although we can match the low-frequency response via (4.3), a good
match in high frequencies still relies on a shorterT
2
. The advantage of using a hybrid
DAC is that the oversampling path clocks at a higher rate (in this case 8 GHz). We
can thus take advantage of this fast-sampling path and approximate the error pulses
with a reasonably shortT
2
, such that the Sinc response at 1-GHz Nyquist frequency
yields <2 dB dierence. The amplitude modication factor in (4.3) also suggests
that a ner amplitude resolution is required, which can be naturally provided via
the DSM of the oversampling path. In other words, the pulsed error approximation
is much more feasible with the hybrid DAC architecture compared to a Nyquist
DAC.
4.3.4 Phase Alignment of Error Pulses
In addition to match the magnitudes of error pulses, the phase alignment of those
error pulses is also crucial. Figure 4.10 shows two possible ways to use wider
pulses to approximate short TEPs in the hybrid DAC architecture. The single-
side approximation fully uses the ne time resolution but it incurs phase deviation
31
clk (8G)
delay
Error
duty-cycle
Error
Single-side Approximation Double-side Approximation
∆
≈
=500ps
=125ps
=500ps
250ps
∆
≈ ∙
=
)
1
<2ps
Area1
Area2
Figure 4.10: Proposed double-side timing-error approximation
32
and eventually results in an incomplete cancellation. If we assume T
1
is much less
than the 500-ps Nyquist sampling period, both the phase term e
jfT
1
and gain
term sinc(fT
1
) are close to unity. This assumption is validated via Monte-Carlo
simulation, where the TEP is bounded by 2 ps. With the condition described in
(4.3), the inaccuracy of approximation can be derived by taking the dierence of
(4.1) and (4.2)
!
err
=T
1
I
X(f)
1e
jfT
2
sinc(fT
2
)
(4.4)
If we assume the attenuation due to sinc(fT
2
) is ignorable within the Nyquist band
as ner time resolution is provided by the oversampling path, (4.4) can be re-written
as
!
err
=T
1
I
X(f)
p
2 [1 cos(fT
2
)] (4.5)
Figure 4.10 also shows the comparison of single-side and double-side approximations
to timing errors. Single-side approximation is able to leverage a 125-ps time grid
provided by the 8-GHz clock; the worst-casej
!
err
j can be 8 dB lower than (or 40%
of) the actual timing error according to (4.5). On the other hand, since the phase
of the approximated pulse is closely aligned to the actual TEP with the double-side
approximation, the phase term in (4.4) is essentially removed, leading to
!
err
=T
1
I
X(f) [1 sinc(fT
2
)] (4.6)
33
Despite the pulse duration being doubled to 250 ps in this case, the approximated
pulse magnitude only diers by<1 dB at the Nyquist frequency according to (4.6).
Therefore, the double-side approximation still presents a much better accuracy
compared to the single-side one. Note that, given the DSM's nite word length (12
bit) and (4.3), the pulse-amplitude scaling accuracy corresponds to 60 fs resolution
of timing-error approximation, i.e., 250 ps=2
12
. This is sucient to meet the SFDR
requirement for our prototypes, which will be elaborated in Chapter 6. Should
more stringent specications on timing-error approximation be required, one can
increase the bit width of the DSM modulator, but the tradeo will be digital circuit
complexity and power consumption.
In reality, there are also timing errors associated with the DSM-controlled cur-
rent cells, i.e., the LSB path, that may cause a slight phase deviation of the proposed
double-side approximation and lead to some inaccuracy of error approximation. Ac-
cording to the Monte Carlo simulation, the timing errors within the LSB path is
expected to be much less than 1 ps due to the compact layout; therefore, these
errors can only cause <0.3% approximation error according to (4.5), which causes
negligible eect on the error calibration. Additionally, the delta-sigma modulation
of the LSB path also helps randomize the timing error within the LSB path. As a
result, the impact of the timing error in the LSB path is ignorable.
34
Power Spectrum [dBr]
DAC
With Errors
Digital Sine
wave(2GS/s)
Ideal output
+
Actual Error
Appx. Error
Error Pulse
Quantizer
0 0.2 0.4 0.6 0.8 1
-165
-140
-115
-90
-75
Frequency [GHz]
Actual Error Appx. Error
<3dB
Figure 4.11: Spectrum of error approximation with sinusoidal input signal
-50
-25
0.25
LPF Bandwidth [GHz]
Power Spectrum [dBr]
0 0.5 0.75 1
0
-75
-100
-125
Pre-distortion off
Pre-distortion on
Figure 4.12: Simulated DAC output spectrum with/without pulsed timing-error
pre-distortion
35
4.3.5 Numerical Simulation
To observe the eectiveness of the proposed error-pulse approximation, we build a
dual-rate hybrid DAC behavior model with amplitude and timing errors to allow
for comparison between actual errors and approximated errors. In this case, a
sinusoidal wave is injected as the test signal; the frequency spectrum of the error
pulses is then overlaid in the same plot as shown in Fig. 4.11. We nd that
the spectrum of actual and approximated error matches well at low frequencies
and deviates <3 dB within 95% of the Nyquist band (DC to 1 GHz for a 2GS/s
hybrid DAC with DSM operating at 8GS/s), which is slightly worse than what the
sinc response predicted via (4.1) and (4.2), mainly due to the nite word-length
eect of DSM and dierent sinc rollo of actual and approximated errors. Note
that, in reality, the rising and falling edge of the error pulses may not be symmetric.
According to our behavioral simulation, this impact is negligible in comparison with
the pulse-quantization eects. We thus assume that all of the TEPs are symmetric
to the center of each sampling instance in this work. To validate the complete PEPD
scheme, we perform numerical Monte-Carlo simulations on the entire hybrid DAC
behavioral model, where both delay and duty-cycle errors are randomly introduced
to the MSB CSCs with standard deviation of 1 ps. We nd that SFDR improves
over 17 dB after subtracting the approximated time-error pulses as shown in Fig.
4.12; we observe similar results for the amplitude-error cases [21].
36
Figure 4.13: Comparison of actual and approximation error pulses
4.4 Inverse-Sinc Pre-distortion
This section focuses on a DPD scheme that is used to compensate timing errors of a
DAC with more than GHz bandwidth, which is a extension of PEPD. Similarly, pros
and cons of previous research on timing error calibration will be brie
y reviewed,
including those of PEPD.
4.4.1 Overview of Existing DPD Techniques
At high signal frequencies, the DAC linearity is mainly limited by the dynamic
errors. Signal-dependent output impedance and timing errors of current-steering
cells are the two main error sources. Analog technique [6] has been used to alleviate
the eect of signal-dependent output impedance. Any mismatch along the data
path between DAC elements causes timing errors. Digital calibration techniques
are typically applied for high-speed, high-performance DAC designs.
As described in [11], [23], [40], dierent error mechanisms require dierent cali-
bration methods; dierentiating the various error mechanisms in the measurement
is necessary prior to digital calibration. There are two main approaches to error
37
calibration. One is dynamic mismatch mapping (DMM), which changes the switch-
ing sequence of the DAC cells based on the measured errors [11], [23]. The other
approach [2] directly compensates the timing errors by approximating a duty-cycle
error with its mean value over a period and a delay error with an anti-symmetric
lter.
As a more general technique, the pulsed error pre-distortion approximates tim-
ing errors by treating them as short timing pulses for both delay and duty-cycle
variations. The error calibration technique is applied to hybrid DAC architec-
ture [20], [21]. It leverages the ne time resolution of the DSM path for timing
error approximation, and it is eective over the signal band of interest. However,
as shown in Fig. 4.13, the approximated error pulse is no longer accurate when the
frequency is close to F
s
=2, which necessitates a dierent DPD technique.
4.4.2 Inverse-Sinc Shaped Digital Pre-distortion
Without loss of generality, timing errors can be modeled as a sequence of short
pulses created during input signal transitions, as depicted in Fig. 4.14. In the
frequency domain, these errors appear at harmonic frequencies of the input signal.
Assuming the amplitude resolution is accurate enough to make sure the integrated
energy of each approximated error pulse (e.g. wide pulses 167 ps) equals that
of the actual error pulse (e.g. short pulse <1 ps), the error energy prole of the
short timing pulses is the same as that of the wide timing pulses. This is the case
38
Figure 4.14: Actual and approximated timing errors
except for when being shaped by the sinc function due to pulse width dierence. To
compensate for the discrepancy caused by sinc attenuation, a digital inverse-sinc
lter is proposed to provide gain at high frequencies for the approximated errors
(Fig. 4.14). It convolves the original approximated error pulses with the impulse
response of inverse-sinc lter.
Fig. 4.15 shows the block diagram of the proposed DPD module. The errors
are rst measured and stored on-chip. Then, the approximated error pulses are
generated based on the input signal pattern, shaped by the inversed-sinc lter, and
summed with the input signal at the DSM input. Since the error energy is much
less than the signal energy, the gain of the inverse-sinc lter will not saturate the
input of DSM; thus, no extra DAC cells are needed.
39
1
in[11:0]
out[11:0]
n = 17 FIR-iSinc
Measured
Timing Errors
15
Digital
Input
12b
12b
To
DSM
15Branches
B2T
15b
4b
12b
MSB LSB
16b
13b
Figure 4.15: Simplied block diagram of the proposed inverse-sinc-shaped DPD
module
In the prototype (Chapter 6), a 16th-order 7-taps inverse-sinc lter was used to
achieve sucient error approximation over>80% of the Nyquist band with tolerable
implementation overhead. The coecients of the lter were designed to be among
f0:125;0:5; 0; 2g, which can be implemented by shifting the digital bits without
using a real digital multiplier.
Fig. 4.16 shows the simulated output spectrum of a nonlinear DAC with only
timing errors. The timing errors of each MSB DAC element are randomly generated
with a standard deviation of 1 ps. For a 1.49-GHz input signal, the proposed
inverse-Sinc shaped DPD yields more improvement on SFDR than the pulsed error
pre-distortion at high frequencies. For an input signal with a frequency close to the
Nyquist (5.9 GHz), the harmonics at higher Nyquist bands will be modulated by the
inverse-sinc lter before being aliased back into the rst Nyquist band. Thus, the
40
-40
Mag. [dBFS]
0
-70
-110
PEPD ISS DPD No DPD
0
-40
Mag. [dBFS]
-70
-110
Signal Frequency, F
sig
[GHz]
1.5 3 4.5 6
F
s
= 12 GHz
F
sig
= 1.49 GHz
F
s
=12 GHz
F
sig
=5.9 GHz
2
nd
Harmonic
2
nd
Harmonic
0
Figure 4.16: Spectrum comparison for dierent timing error DPD schemes
inverse-sinc shaped DPD is able to suppress the second harmonic at relatively low
frequency (Fig. 4.16); the pulsed error pre-distortion has almost no improvement.
41
Chapter 5
High-Speed Delta-Sigma Modulator
5.1 Unrolled Pipeline Delta-Sigma Modulator
In our design, the target clock rate of the DSM is >8 GHz, it is not possible to
meet the timing constraint with standard digital design
ow in 65 nm CMOS, which
allows only four FO4 inverter delays per clock cycle. In order to relax the timing
constraint such that the digital core can be synthesized, placed and routed auto-
matically by EDA tools, the DSM architecture was further unrolled and pipelined
to allow a slower clock rate.
5.1.1 Unrolling
Conventionally, the DSP unrolling technique is used to relax the clock period by
leveraging parallel computations given the same throughput. Alternatively, the
pipelining technique is commonly used to reduce the logic depth between the
42
250ps
e[n-3]
x[n-2]
x[n-1]
x[n-1]
x[n]
e[n-2]
y[n]
y[n-1]
x[n]
e[n]
y[n]
x[n-1]
e[n-1]
y[n-1]
k+1
k
1
k
k
n]
−
2X unrolled 1
st
order DSM
n]
k
k+1 1
k k
−
−
k
−
−
125ps
250ps
Figure 5.1: Implementation of rst-order DSM unrolling (2X case)
latches. Both techniques, used individually or jointly, can relax the timing con-
straint of a required computation. Generally speaking, the DSP architectures with-
out feedback loops are more straightforward to unroll and pipeline. It is also pos-
sible to unroll and pipeline the DSP architecture with a feedback loop, which does
not involve nonlinear computation, such as an innite impulse response lter [17].
However, in the case of error-feedback DSM architecture, the feedback loops
involve nonlinear computation, i.e., truncation of the DSM output, which makes
it dicult to unroll with conventional methods. To resolve this issue, the DSM
truncated output is calculated in two steps in this design. First, the feedback error
of the DSM is calculated via its previous sample and the current input sample.
Next, the nal output is computed by summing the feedback error and delayed
input samples.
43
To better explain the proposed unrolling technique, a simplied example 2X
unrolled rst-order DSM is used. For the rst-order DSM operation, the pre-
quantized output y[n] is computed according to (5.1), where x[n] is the input and
e[n 1] is the feedback error with one cycle delay. The feedback error is equal the
dierence between the nal DSM output, i.e., MSBfy[n]g, and y[n], as shown in
(5.2). It is referred to as the LSBfg operation in the context of this paper, since it
is essentially the LSB part of y[n],
y[n] =x[n] +e[n 1] (5.1)
e[n] = LSBfy[n]g =y[n] MSBfy[n]g (5.2)
We then express e[n 1] as (5.3) and substitute it with (5.1). The 2X unrolled
DSM operations are derived as (5.4) and (5.5). Therefore, y[n] andy[n 1] can be
computed simultaneously with 2X relaxed timing, as shown in Fig. 5.1.
e[n 1] = LSBfy[n 1]g
= LSBfx[n 1] +e[n 2]g
(5.3)
y[n] =x[n] + LSBfx[n 1] +e[n 2]g (5.4)
y[n 1] =x[n 1] + LSBfx[n 2] +e[n 3]g (5.5)
44
Figure 5.2: Implementation of rst-order DSM unrolling (2X case)
5.1.2 Pipelining
Since the unrolling operation introduces an additional summation inside the LSBfg
operation, further pipelining of the unrolled DSM is desirable to further relax the
timing constraint. However, x[n] and x[n 1] in (5.4) cannot be individually
pipelined and pre-computed in advance due to the nonlinear LSBfg operation.
Therefore, we derive two-step computation paths to calculate the LSB part of y[n]
rst, followed by the MSB part. First, we take the LSBfg operation on both sides
of (5.4), which yields:
LSBfy[n]g = LSBfx[n] + LSBfx[n 1] +e[n 2]gg
= LSBfx[n] +x[n 1]g + LSBfe[n 2]g
(5.6)
Sincex[n] andx[n 1] are both inside the LSBfg operation, they can be pipelined
45
easily and summed with the previous feedback error, as shown in Fig. 5.2. Next,
the MSB part ofy[n] can be computed by pipelining the delayed result from (5.6),
i.e., LSBfy[n 2]g, and summed with the delayed and current input samples as
MSBfy[n]g = MSBfx[n] + LSBfx[n 1] + LSBfy[n 2]ggg (5.7)
By applying this method, the critical path contains simply one adder in this proto-
type. Extending from the aforementioned method, the DSM can be unrolled into
m sub-channels in conjunction with internal pipelining to achieve the target clock
rate. Each DSM sub-channel utilizes the current and previous samples of the input
and intermediate signals, as indicated by (5.8)
y[n] =x[n] + LSB
(
m1
X
i=1
x[ni]
!
+e[nm]
)
(5.8)
As a result, the unrolled and pipelined DSM architecture can be computed in
parallel using only 1/m
th
of the target clock rate. For simplicity, a 1-1-1 MASH
structure is chosen and unrolled by 8X in order to operate the sub-channels at
a 1-GHz clock rate, i.e., m=8. Since the 1-1-1 MASH structure contains three
independently operated stages without inter-stage feedback loops, each stage can be
unrolled and pipelined individually, as shown in Fig. 5.3. Each stage is composed of
eight sub-channels, and the feedback error from each sub-channel of stage i, e
i
[n],
is passed on to the corresponding sub-channel of the next stage. Moreover, the
46
1GS/s
8 channels
4-bit output
12b
Serial
to
Parallel
1
st
Stage 2
nd
Stage 3
rd
Stage
Delay Equalizer
−
8X
Unrolled
1
st
order
DSM
8X
Unrolled
1
st
order
DSM
8X
Unrolled
1
st
order
DSM
−
−
−
−
−
−
Pipelined Digital Filter
Figure 5.3: Implementation of the proposed unrolled pipeline 1-1-1 MASH (8X
case)
output of each stage should be equalized precisely in terms of latency and sent to
digital lter banks, i.e.,H(z) in Fig. 5.4. Note that the digital lter is also unrolled
into eight sub-channels to interface with the 1-1-1 MASH DSM.
5.1.3 Multi-Bit MASH
In the prototype DAC, a multi-bit MASH architecture with a redundancy region is
used for the DSM. Unlike stages one and two, which have only 1-bit output, stage
three of the MASH structure generates 4-bit output, resulting in less quantization
noise and hence extending the bandwidth, as shown in Fig. 5.4. The alternative is
to increase the order of the DSM; however, this requires larger current steering cells,
causing elevated out-of-band noise power, inter-symbol interference and increased
modulator complexity. Lastly, the intrinsic operation of this multi-bit MASH ar-
chitecture exercises 13 levels instead of 16. Three redundant levels, i.e., the shadow
region in Fig. 5.4, are reserved for the additional dynamic range required by the
47
1
st
order
DSM
1
st
order
DSM
1
st
order
DSM
+
12b
12b
1b
1b
4b
1-1-1 MASH
4b
12b
x1 x2 x4 x8
13
levels
Digital
Filter
Figure 5.4: Block diagram of the multi-bit 1-1-1 MASH
proposed pre-distortion scheme. They should accommodate the maximal mismatch
of the MSB current steering cells.
5.2 In-Band Noise Cancellation
In Chapter 3, we derive the signal bandwidth of a dual-rate hybrid DAC. To scale
this DAC architecture for wider bandwidth, we must ensure that the DSM quan-
tization noise does not violate the in-band noise-
oor requirement as shown in
Fig. 5.5. To achieve this, we can either increase the sampling rate/order of DSM
or insert zeros in the DSM transfer function, which will signicantly increase the
implementation cost. Instead, we explore quantization noise cancellation without
changing DSM in this work to incur minimal overhead.
48
Mag.
Frequency
Mag.
Frequency 0.5G 1G
0.5G 1G
Noise floor
requirement
Noise floor
requirement
DSM Noise
Signals
Figure 5.5: Spectrum comparison with and without bandwidth extension
PSD PSD
Freq.
Freq.
Freq.
time
mag
PSD
<16 levels
Unit CS
Unit CS
PSD PSD
Freq.
Freq.
Freq.
PSD
No
noise
time
mag
4096 levels
1. Complete noise cancellation
4 12
−
Digital
Analog
12
2. In-band noise cancellation
4 12
−
4
12
FIR LPF
Digital
Analog
Figure 5.6: Traditional DSM noise-cancellation scheme
49
FIR LPF
1G
1
st
ord.
Digital Analog
−
DAC
output
PSD
Freq.
PSD
Freq.
PSD
Freq.
mag
Time
mag
Time
mag
Time
PSD
Freq.
1G
1G
DSM noise Extracted noise Bit compression
2 12
Figure 5.7: Proposed DSM-assisted in-band noise-cancellation scheme
5.2.1 Conventional Noise Cancellation
Figure 5.6 shows the block diagram of several existing noise-cancellation approaches.
For complete noise cancellation, DSM quantization noise can rst be extracted
and then subtracted at the output. But the extracted noise contains both in-
band and out-of-band spectral content, which implies signicant noise energy|and
hence too many CSCs are required. The second approach is in-band noise cancella-
tion [33], [34]. Instead of all the delta-sigma truncation noise, only the noise within
the band of interest is selected via FIR low-pass lter (LPF). As a consequence,
less noise energy remains, which then reduces the number of CSCs.
50
−
−
−
−
−
Split MSB and LSB
DSM1
DSM2
Y
−
−
−
−
Frequency
amplitude
Noise floor
M N
V
P
Figure 5.8: Model of hybrid DAC with DSM-assisted in-band noise cancellation
5.2.2 DSM-Assisted In-Band Noise Cancellation
For less analog complexity and better DAC linearity, we aim to further minimize
the number of CSCs required for noise cancellation. The DSM quantization noise
is rst processed by the FIR LPF and then a rst-order DSM to further reduce the
bit width and provide noise shaping as shown in Fig. 5.7. After the cancellation at
node D, it is important to ensure that the noise
oor within the band of interest
still meets the specication which is a 12-bit noise spectral density. To analyze the
noise level and calculate the required bit width, we provide an analytical model of
the dual-rate hybrid DAC with the proposed noise cancellation as shown in Fig.
51
5.8. In this model, the truncation errors are treated as uniformly distributed noise.
In the Z domain, DAC output can be expressed as
Y (z) =X(z) +e
N
+e
trunc1
(1z
1
)
k
[1H
LPF
(z)] +e
trunc2
(1z
1
) (5.9)
where X and Y are the DAC input and output, e
N
is the quantization noise of
the N-bit input signal, e
trunc1
and e
trunc2
are the truncation noise of the k
th
and
rst-order DSM, and H
LPF
is the LPF lter response. Assuming M bits in the
MSB path, V bits at the DSM1 output, and is the LSB of the DAC input, the
power-spectral density of e
trunc1
can be expressed as
PSD e
trunc1
=
2
NMV+1
p
6f
s dsm
(5.10)
where f
s dsm
is the clock rate of DSM. Next, we derive the LPF output bits as a
function of the LPF bandwidth, which is equal to the targeted DAC bandwidth,
B. Since e
trunc1
is a noise-like signal, we then approximate LPF output as a ran-
dom variable with uniform distribution bounded within +A
LPF
=2 andA
LPF
=2.
Assuming that LPF is an ideal brickwall lter, we can integrate PSD e
trunc1
over
bandwidth B and equate it with the power of the approximated random variable
as
A
2
LPF
12
=
Z
B
B
(
PSD e
trunc1
2sin
f
f
s dsm
k
)
2
df (5.11)
52
1
LPF Bandwidth [GHz]
Required Number of Bits
0.5 1.5 2 2.5 3 3.5 4
0
2
4
6
8
Theoretical
256-tap FIR LPF
5-tap FIR LPF
N=12
M=4
V=4
k=3
Figure 5.9: Eective number of bits versus LPF bandwidth
Therefore, by substituting (5.10) in (5.11), the signal range (A
LPF
) at the LPF
output can be derived as
A
LPF
= 2
NMV+k+2
s
1
f
s dsm
Z
B
0
sin
2k
f
f
s dsm
df (5.12)
Figure 5.9 shows the required number of bits at the LPF output as a function of
its bandwidth, assuming a 256-tap FIR lter is used. This shows a good match
between the numerical simulation and the analytical result via (5.12). If the order
of the LPF is reduced, however, the required number of bits is expected to increase
because of the lower amount of ltering involved. In this work, a 5-tap FIR lter
is implemented with 1-GHz LPF bandwidth, which leads to 4-bit output swing.
Finally, we solve the required number of bits at the output of the rst-order DSM,
53
which is denoted as P bits. Similarly to e
trunc1
, the power density of e
trunc2
can be
derived as
PSD e
trunc2
=
A
LPF
2
(P1)
p
6f
s dsm
(5.13)
Since the shaped noise fromPSD e
trunc2
should be lower than the 12-bit noise
oor
within the DAC bandwidth, we simply consider the PSD e
trunc2
at the band edge
to be the worst case as
PSD e
trunc2
2sin
B
f
s dsm
=e
N
=
p
6f
s
(5.14)
where f
s
is the Nyquist sampling rate. By substituting (5.13) in (5.14), we can
solve the required bit width at the DSM2 output as
P = log
2
"
4A
LPF
s
f
s
f
s dsm
sin
B
f
s dsm
#
(5.15)
In out second prototype DAC, we reduceP to eective 1.6 bits with 5-tap FIR LPF
for 1-GHz bandwidth using the proposed noise-cancellation scheme for minimal
analog overhead.
5.3 Successive Pipelined Bandpass DSM
This section rst provides a brief overview of bandpass DSM architectures and
high-speed DSM design techniques. To alleviate existing techniques' constraints,
54
Table 5.1: Summary of Bandpass DSM
we introduce a successive pipelined DSM structure for speed enhancement and
validate their functionality via theoretical analysis and numerical simulations.
5.3.1 Overview of Bandpass DSM
Table 5.1 shows three possible approaches to implementing a bandpass DSM. Here,
we use rst-order NTF as examples for simplicity. The rst approach is adding a
mixer after a lowpass DSM so that the notch of the original NTF will be moved to
the desirable carrier frequency [42], [43], [44]. However, the LO frequency cannot be
arbitrarily chosen to avoid aliasing noise from folding into the signal bands [43]. The
operation speed of this modulation is close to that of a lowpass DSM [21], [45], [46].
The second approach uses an error feedback (EF) DSM topology, in which changing
the polarity of the feedback error or inserting a one-unit delay in the feedback path
will result in a specic NTF with passbands at F
dsm
=2 or F
dsm
=4, respectively,
where F
dsm
is the DSM clock rate. The third approach is implementing DSM with
a bandpass NTF that can potentially tune the zero location to any frequency within
the Nyquist band without mixing assuming that a has innite bits. There is no
55
aliasing noise due to digital mixing. Compared to the above approaches, it is the
most
exible. However, extra multiplication and summation in the NTF limit the
operation speed. To achieve maximal
exibility, we chose the third approach and
proposed a successive implementation to enhance its speed.
5.3.2 Successive DSM with Tunable Passband
The typical approach to enhancing the speed of a lowpass DSM is unrolling and/or
pipelining [21], [44][49]. However, unrolling a bandpass DSM with NTF shown
in Table I results in the growth of a critical path. Additionally, the conventional
pipelining techniques cannot be applied to this bandpass DSM. Based on these
limitations, we propose a general solution for implementing a high-speed bandpass
DSM that is also applicable to a lowpass DSM. The idea of the proposed successive
DSM topology is to gradually compress the input bits via several cascaded DSM
stages. This can be implemented by passing only a certain LSB section of the input
code to the following-stage DSM. It allows relaxed arithmetic computation inside
each stage and straightforward pipelining between stages.
A simple design example of 3-bit EF DSM with relative bit weighting is illus-
trated in Fig. 5.10 for clarity. We chose an EF DSM structure due to its simplicity
and the fact that STF remains independent of H(z), allowing more
exible tuning
of the NTF. In this example, only the very LSB of each stage's input is sent to a
single-bit DSM. The output of the single-bit DSM is the over
ow bit of the input
56
Figure 5.10: 3-bit pipelined successive DSM
adder, while the LSB bit is a quantization error used for feedback. The feedback
lter H(z) consists of adder, multipliers, programmable coecients, and delay ele-
ments. By using successive DSM, it allows single-bit arithmetic operations instead
of 3-bit ones, leading to a reduced critical path in each stage. The output of single-
bit DSM is summed with the remaining MSB bits at the stage boundary. This
adder can be pipelined as it is outside the DSM feedback loop, further enhanc-
ing the operation speed. Through these pipelined stages, the 3-bit input signal is
compressed successively and reduced to single-bit output.
To validate that the proposed successive DSM topology is equivalent to the con-
ventional single-stage DSM, we will analyze and compare the quantization noise of
the DSM in both cases for the same number of output bits. The quantization noise
was assumed to be uniformly distributed within [0, ], where is the resolution of
the quantizer. The total integrated quantization noise of the conventional DSM is
57
Single-Stage DSM
Successive DSM
Figure 5.11: Block diagram of single-stage and successive DSMs
equal to the quantization noise added at the last stage of the successive DSM (due
to the same ). If the quantization noise added at each stage of successive DSM
is independent, the total quantization noise of a successive DSM would be higher
than a conventional DSM. Fortunately, it can be shown that the added noise at
each stage of a successive DSM is correlated with each other and their sum equals
the added noise of a single-stage DSM.
Here, a second order lowpass successive DSM is modeled and shown to be equiv-
alent to its single-stage counterparts. Fig. 5.11 shows the block diagrams of a
conventional single-stage DSM and a two-stage successive DSM as a case study.
Derivations for successive DSM with more stages can be extended from the two-
stage case by substitutions. To formulate the problem, the minimum level spacing
(resolution) of the quantizer at stage 1 and stage 2 are denoted as
1
and
2
.
The input x[n] is an N-bit digital signal with the LSB weighting normalized to
1. Operation MSB
i
fg presents the quantization with a resolution of
i
; LSB
i
fg
58
13/4
DSM
4b 13b
13b
H(z)
4b
10b
Figure 5.12: 13-bit input/4-bit output single-stage DSM
13/10
DSM
10b 13b
10/7
DSM
7b
7/4
DSM
4b
2
3
Figure 5.13: 13-bit input/4-bit output successive DSM
presents the corresponding quantization errors within the range of [0,
i
), where i
is the stage number. From (A.6) and (A.8) in the Appendix, the total quantization
noise of the successive DSM can be derived as
e
1
[n] +e
2
[n] =LSB
2
(
n
X
m=1
m
X
k=1
x[k]
)
(5.16)
According to (A.6), the quantization noise of the single-stage DSM that is given by
e[n] =LSB
2
fy
0
[n]g =LSB
2
(
n
X
m=1
m
X
k=1
x[k]
)
(5.17)
The above equations validate the equivalence of a successive DSM and conventional
single-stage DSM based on low-order lowpass noise shaping.
59
0
NSD [dBc/Hz]
Signal Frequency, F
sig
[GHz]
0.1
-100
-120
0.2 0.3 0.4 0.5 0.6 0.7 0.8
-140
-160
-180
-200
Single [a=-0.5]
Succ. [a=-0.5]
Single [a=0.5]
Succ. [a=0.5]
Order =2
RBW =1Hz
F
dsm
=1.5GHz
Res. =16bit
Figure 5.14: PSD of DSM quantization noise; a =0:5
In the prototype DAC, we use programmable second and third order bandpass
DSMs with 13-bit input and 4-bit output (Fig. 5.12). To support high-speed op-
eration, the actual DSM implementation was pipelined into three successive stages
with each stage reducing the signal bit width by three (Fig. 5.13). Here, we ex-
press the quantization error added at the i
t
h stage as E
i
and the quantization
error in a single-stage bandpass DSM as E. For the bandpass DSM with NTF of
(1 +az
1
+z
2
)
2
, there is no clean analytical derivation. We performed numerical
simulations and conrmed that e[n] =
P
3
i=1
e
i
[n] for an integer a, where e[n] and
e
i
[n] are the discrete-time domain counterparts of E and E
i
. In the case that a is
not an integer number, the discrete-time waveforms of
P
3
i=1
e
i
[n] and e[n] are not
perfectly matched; nevertheless, the NSD and the integrated quantization noise
power over the Nyquist band of the two bandpass DSM structures are still closely
matched, as shown in Fig. 5.14.
60
Chapter 6
Prototype DACs
6.1 A 12-bit 1-GS/s Dual-Rate Hybrid DAC
6.1.1 System Block Diagram
Figure 6.1 shows the simplied block diagram of the dual-rate hybrid DAC pro-
totype targeting at 12-bit resolution with highest possible linearity. Given the
tradeos discussed in Chapter 3, the 1-GS/s 12-bit input digital code is split into
4-bit MSBs and 8-bit LSBs, which are upsampled to 8 GHz via the ZOH interpola-
tor. The 4-bit MSBs are rst converted to a 15-bit thermometer code and fed into
a DWA module to further improve the linearity. The LSB path exploits an 8-GHz
third-order DSM, which reduces the word length to 4 bits without degrading the
in-band noise
oor. The implementation of the DSM requires unrolling and pipelin-
ing. Next, a multi-phase multiplexer (MUX) array serializes the parallel outputs
from the unrolled DSM, and a replica MUX is inserted in the MSB path to exactly
61
MSB 4b
12b
Pre-distortion
LSB 8b
15b
15b
Digital
Input
Thermometer
Decoder
4b
8GS/s
Analog
Digital
DWA DAC
+
MUX
&
Latch
Array
15b
1GS/s
4b
8 Channels
ZOH
Interpolator
13b
DAC
Figure 6.1: Proposed dual-rate hybrid DAC architecture with a split Nyquist (MSB)
and delta-sigma (LSB) path
match the delay in the LSB path. The MUX outputs are retimed by the current
mode logic (CML) latches and control an array of current steering cells, which will
be described in next section. Finally, the delta-sigma assisted pre-distortion tech-
nique described is implemented on-chip to take the DWA output and compute the
required error compensation code in real time.
6.1.2 Circuit Implementation
6.1.2.1 Data Serializer
A three-stage MUX array driven by multi-rate multi-phase clocks is used to serialize
8X unrolled subchannel outputs into a single 8-GHz data stream, as shown in Fig.
6.2. To ensure 8-GHz data serialization in the nal stage and reduce its supply
noise sensitivity, the CML MUX is utilized for its dierential operation and smaller
voltage swing compared to the CMOS MUX used in the prior stages.
62
2-1MUX 2-1MUX 2-1MUX 2-1MUX
2-1MUX 2-1MUX
8X unrolled pipelined 1-1-1 MASH
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
LSB Current Steering Cells
2-to-1 CML MUX Latch
CML Latch
Each data line present a 4 -b bus
Figure 6.2: Block diagram of an 8-to-1 data serializer
8
Figure 6.3: Timing diagram of the clock and data within a data serializer
63
Figure 6.3 shows the timing diagram of various internal signals and clocks in the
MUX array. Note that a phase-alignment algorithm is used for the 8-GHz clock to
align its rising edge with the 90
phase of the 4-GHz data pattern. This is to ensure
maximal margin for the setup and hold time requirement of the 8-GHz CML latch.
6.1.2.2 CML Latch Driver
To interface with the current steering cells, the CML latch and drivers are imple-
mented instead of CMOS logic due to their higher operational speed and robust-
ness over supply noise. Additionally, the lower swing dierential signals allow the
transistors in current steering cells to operate in the deep saturation region when
turned on. This leads to a higher output impedance and hence better DAC lin-
earity. Shown in Fig. 6.2, a master-slave latch architecture is adopted to reduce
the signal feedthrough and other data-dependent errors [7], [10]. A CML driver is
inserted after the CML latch to derive a proper driving waveform in terms of com-
mon mode voltage and slew rate. Moreover, since the power supply of the CML
driver is shared with that of the current steering cells, it avoids the data-dependent
noise coupling from the digital circuitry and prevents SFDR degradations.
6.1.2.3 Clock Generator
A clock generator is used to generate all the required clock frequencies and phases
to support the data serializer. As shown in Fig. 6.4, an external 8-GHz clock source
is utilized and a mix of CML/CMOS dividers [18] is used throughout the chain.
64
Figure 6.4: Block diagram of a clock generator
Additionally, phase rotators and bang-bang detectors are implemented to ensure
proper data-clock alignment [5]. The schematic of the CML phase rotator with
programmable logic is shown in Fig. 6.5. A 7-bit phase tuning code,C
1
-C
7
, steers
the current between the two 90
oset clock phases to achieve phase rotation with
500 fs resolution. However, when the phase interpolation is between 270
and 360
,
an unwanted pulse exists that false triggers the following CMOS divider, as shown
in Fig. 6.4. Therefore, a pulse-masking block is utilized to generate an enable signal
based on the rising edge of the rotator output and to remove the undesirable pulse.
6.1.2.4 Current-Steering Cell
The schematic of a current steering cell is shown in Fig. 6.6. It is a commonly
used current switching pair with an output cascode stage using thick-oxide NMOS
transistors. The cascode devices help increase the output impedance and protect the
65
7
7
4
4
4
4
4
4
4
4
]
[
]
[1]
[1]
CML MUX
CML MUX
Figure 6.5: Schematic of a phase rotator
Figure 6.6: Schematic of current-steering cells
66
core switching devices since the DAC output load is connected to 2.5-V supply for
larger output swing. Owing to the delta-sigma assisted pre-distortion scheme, the
current branches in the MSB path were intentionally designed with smaller device
dimensions such that only 8-bit matching accuracy is required. In this design, the
entire current steering cell array occupies just 250 30 m
2
, which is crucial to
minimize the internal parasitics and routing skews.
6.1.2.5 Digital Core
The digital core, including direct digital frequency synthesis (DDFS), thermometer
encoder, DWA, pre-distortion logic and DSM, is fully synthesized and automatically
laid out by the standard digital design
ow. It occupies 540 540 m
2
of silicon
area with a total of 162 K digital gates clocked at 1 GHz. Nearly 25% of the
area is occupied by DDFS and other debugging logic, which are used only for
testing purposes. Since cross-talk between digital and analog circuits can cause
severe SFDR degradation, special attention has been paid to noise isolation. In
particular, the digital switching noise of the multiplexer array in the data serializer
should be fully isolated from the CML latch. A careful layout, such as minimizing
the overlapped area of digital wires and the latch supply stripes, yields SFDR
improvement of almost 10 dB according to the post-layout simulation.
67
Digital Core
1.27mm
1.53mm
CS
Latch
Clock
MUX
Technology
(CMOS)
65nm
Supply (V)
Analog: 1/2.5
Digital: 1
(mA) 16-20
Power(mW)
430 (40%
analog, 40%
digital, 20%
interface)
Active area
(
2
)
Analog:0.25
Digital:0.3
Figure 6.7: Micrograph of the test chip in a 65 nm CMOS technology
6.1.3 Measurement Results
Figure 6.7 shows the micrograph of the test chip with total area of 1.94 mm
2
in
the 65 nm CMOS technology. The silicon prototype is wire bonded in a QFN 64-
pin package and attached to the PCB via a twist-lock socket. A 12-bit 1 GS/s
CORDIC-based DDFS with a 24-bit frequency control word is implemented on-
chip to synthesize high-quality digital sinusoids for DAC testing over the 500-MHz
frequency band. An 8-GHz clock is generated by the Agilent E8251A and converted
from single-ended to dierential signals via a wideband 180
hybrid before sending
to the board. The DAC output is dierentially loaded with 50-ohm resistors on the
PCB board, and a discrete balun is used to convert the dierential output signal
to single ended for the spectrum measurement.
In Fig. 6.8, the DC characteristic of the MSB current steering cells is measured
via an 8.5-digit digital multimeter o-chip. The current magnitude dierences,
68
-0.10%
-0.05%
0.00%
0.05%
0.10%
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSB Mismatches
Percentage
Figure 6.8: MSB current-steering cell mismatches
when normalized to the nominal value, show less than 0.09% variation across the
15 branches, which have better matching than what is expected from the SPICE
simulations. Note that the distortion due to this current mismatch will be alleviated
via the proposed delta-sigma assisted pre-distortion scheme.
Figure 6.9(a) shows the spectrum of the DAC output with a sine wave frequency
of 7 MHz. Only second- and third-harmonic tones are observable from DC to the
Nyquist band. A zoomed-in frequency band of interest is shown in Fig. 6.9(b),
where SFDR is measured to be 91 dB with the RF attenuation mode enabled in the
spectrum analyzer. Measured SFDRs at other unspecied frequencies are recorded
under a similar zoomed-in setup. Figure 6.9(c) shows the DAC output spectrum
from DC to the Nyquist frequency forf
in
=494.7 MHz, and SFDR measures 76 dB.
To study the eectiveness of delta-sigma assisted pre-distortion, SFDR is mea-
sured before and after pre-distortion with DWA disabled. As an example shown in
Fig. 6.10, applying the pre-distortion scheme improves HD2 by 14 dB and HD3 by
9 dB without raising the noise
oor. In general, we observe SFDR improvement
69
2
nd
3
rd
(a) (b)
(c)
Figure 6.9: Measured spectra with (a) f
in
= 7 MHz within DC-500 MHz, (b) f
in
= 7 MHz within zoomed-in band of interest, and (c) f
in
= 494.7 MHz
70
(a) (b)
Figure 6.10: Measured spectra with (a) before and (b) after applying the delta-
sigma assisted pre-distortion
(a) (b)
Figure 6.11: Measured spectra with (a) before and (b) after applying the DWA
71
This work: 12-bit Hybrid DAC
@ 8GS/s
JSSC2014(W. Lin)
@1.6GS/s
JSSC2011(W. Tseng)
@1.25GS/s
JSSC2009(C. Lin)
@1.6GS/s
ISSCC2012(G. Engel)
@3GS/s
ISSCC2005(K. Doris)
@500MS/s
JSSC2009(C. Lin)
@2.9GS/s
Figure 6.12: SFDR performance versus signal frequency
in the range of 9-14 dB for frequencies < 50 MHz but there is no obvious SFDR
improvement for frequency close to Nyquist since SFDR degradation at high fre-
quency is more constrained by dynamic errors instead of static current mismatches.
On the other hand, Fig. 6.11 studies SFDR improvement solely by DWA with the
pre-distortion scheme disabled. It shows improvement of 12 dB as it randomizes
the mismatches associated with the MSB current steering cells. Similar to applying
the pre-distortion scheme, SFDR improvement due to DWA decreases as frequency
increases. Specically, SFDR improvement reduces to 2-4 dB for a frequency close
to Nyquist.
The measured SFDR performance with both delta-sigma assisted pre-distortion
and DWA enabled is plotted and compared with state-of-the-art high-speed (>
GS/s) DACs in Fig. 6.12. The SFDR value ranges from 76 dB at the Nyquist
frequency up to 91 dB at the low input frequency. This proof-of-concept prototype
72
Nyquist rate: 1 GS/s
Oversampling rate: 8 GS/s
Figure 6.13: NSD versus signal frequency
achieves better SFDR performance than previously published state-of-the-art high-
speed CMOS DACs [3], [4], [6], [7], [19]. Note that SFDR maintains above an 85-dB
value with input frequencies up to 50 MHz and above 77 dB within the 420-MHz
band. As the input frequency increases, SFDR degrades, which is most likely due
to uncompensated dynamic errors, such as time skews and nite output impedance,
of the current steering cells at high frequency [11].
The noise spectrum density (NSD) of the DAC output was also measured for
both in-band and out-of-band with a 65 MHz, -5 dBm testing signal and enabling
the pre-amplication option of the spectrum analyzer. The in-band phase noise
oor achieves -162 dBc/Hz, which is equivalent to 12 bits. The noise
oor starts
to increase beyond 500 MHz due to the noise shaping of the delta sigma opera-
tion. NSD reaches a peak value of -121 dBc/Hz at 2.5 GHz and starts to roll o,
which matches the behavioral simulations. The NSD measurement over frequency
73
is shown in Fig. 6.13. The output RC ltering due to resistor load and the parasitic
of the pads and PCB traces helps to attenuate the out-of-band noise beyond 2.5
GHz.
In terms of implementation cost, the DAC prototype occupies a total active area
of 0.55 mm
2
, including 0.25 mm
2
from digital and 0.303 mm
2
from analog sections.
The total power consumption of the entire chip, including the DDFS, is 430 mW,
while analog, digital, and clock generator supply consume 163 mW, 165 mW, and
104 mW, respectively.
6.1.4 Conclusion
A dual-rate hybrid DAC architecture is used to achieve high linearity and high-
speed operation. This architecture minimizes the analog complexity and favors
future technology scaling. To further minimize the area, a delta-sigma assisted pre-
distortion scheme is proposed to relax current matching requirements. Unrolled and
pipelined DSM is used to allow high-speed operation. The proof-of-concept silicon
prototype achieves higher SFDR compared to published state-of-the-art high-speed
CMOS DACs and is expected to improve further in more advanced technology
nodes.
74
Figure 6.14: System-level block diagram of the proposed hybrid DAC
6.2 A 12-bit 2-GS/s Dual-Rate Hybrid DAC
6.2.1 System Block Diagram
Figure 6.14 shows the system-level implementation of the silicon prototype. 12-
bit 2 GS/s testing signals, including single and double tones, are generated via
on-chip CORDIC-based Direct Digital Frequency Synthesizers (DDFSs). Due to
the speed limitation of the digital logic in 65nm CMOS, the 4-bit MSB signal
is deserialized into two 1 GS/s channels with a selectable DEM/DWA module.
There are a few reasons for implementing DEM/DWA module in this prototype.
First, it allows us to compare the performance of the conventional randomization
techniques versus the proposed PEPD scheme. Second, the possibility of combining
75
the DEM/DWA with PEPD scheme helps compensate the potential errors that may
be not associated with timing or amplitude errors of the current cells. Lastly, since
the prototype performs one-time foreground calibration, this combined approach
provides more robustness in case that the timing and amplitude errors change
dramatically over time, for example, aging eects.
For the 8-bit LSB path, the signal is rst upsampled by 4X and then deserialized
into eight channels, each subtracted from the PEPD codes. As a result, the following
DSM and FIR LPF are unrolled by 8X and pipelined so that each channel can
operate with a 1-GHz clock rate. (The details of unrolled DSM are reported in [21].)
Before controlling the CSCs, the digital bits are serialized and re-timed with CML
latches. For proper operation of high-speed serialization, dierent clock frequencies
(including 1, 2, 4, and 8 GHz), with proper phases, are required. Those clocks are
divided from an external 8-GHz clock source; the phase alignments are guaranteed
by phase detectors and rotators.
6.2.2 Circuit Implementation
6.2.2.1 Pulsed-Error Pre-distortion Logic
Figure 6.15 shows the block diagram of the PEPD logic. First, we store DWA (or
DEM) output bits in shift registers (the adjacent samples are needed for timing-
error approximation). The amplitude-error pulse is generated by a multiply-and-
add (MA) operation based on amplitude-error LUT and the current MSB sample.
76
LSB2
MSB2
Channel 1
MSB1 DWA/
DEM
Therm.
Decoder
M0..14[n+1] M0..14[n] M0..14[n-1]
Code 0
Code 14
M0[n]
M14[n]
Amplitude
Error LUT
Mult_Add
Code 0
Code 14
M0..14[n-1]
M0..14[n]
M0..14[n+1]
To MUX
Mult_Add
Code 0
Code 14
Delay
Error LUT
+
+
+
+
ګ ں ګ ں LSB1
Delay
Equalizer
P1
P2
P3
P4
Pulse
combiner
Duty-cycle
Error LUT
1G
Channel 2
Current
Sample
Previous
Sample
Next
Sample
To DFFs
Figure 6.15: Implementation of pulsed-error generator
The delay-error and duty-cycle-error pulses utilize multiple MA operations based
on previous (M
0::14
[n 1]), current (M
0::14
[n]), and next (M
0::14
[n + 1]) MSB sam-
ples, along with delay-error LUT and duty-cycle LUT. The error pulses are then
combined and summed to the corresponding LSB channels for error pre-distortion.
Figure 6.16 demonstrates a time-domain view of error-pulse generation for a
specic current cell. This plot divides the time of a Nyquist sampling period (500
ps) into four zones (P1{P4). The amplitude error is duplicated over P1{P4 of the
current sample; the delay error is replicated at P1 of the current sample and P4
of the previous sample, together with the negative replicas for P4 (current sample)
and P1 (next sample). A similar strategy is used for creating duty-cycle error
77
M0..14[n-1] M0..14[n] M0..14[n+1]
Current
Sample
Previous
Sample
Next
Sample
P1 P2 P3 P4
Amplitude
Error
Delay Error
Duty-cycle
Error
Total
Errors
MSB data
Time
Figure 6.16: Timing diagram of pulsed-error pre-distortion
pulse. This method of error-pulse approximation exactly matches the description
in Chapter 5.
6.2.2.2 CML Latch and Drivers
Figure 6.17 shows the schematic of the slave stage of the CML latch and drivers,
including the clock buer. CML latches and drivers are used for high-speed oper-
ation and rejection of the common-mode noise. In general, faster data transition
at the latch output leads to better DAC linearity, because it is less sensitive to the
oset voltage of the CSC and results in smaller duty-cycle errors as shown in Fig.
19. Generating faster transition edges implies more current consumption at the
CML driver due to higher tail current and lower load resistance. As a result of the
78
Slave latch Driver
Clock buffer
Figure 6.17: CML latches and drivers
proposed PEPD technique, the driving strength of the CML driver can be relaxed
for a given SFDR target.
6.2.2.3 Current-Steering Cells
Figure 6.18 shows the tail-current sources of the CSCs and part of their biasing
circuits. The binary-weighted LSB current cells are controlled by the oversampling
path of the hybrid DAC and perform PEPD. They are thus suciently large to
achieve 12-b accuracy. The unitary MSB cells can be designed with smaller sizes,
due to the PEPD, and this results in fewer parasitics and a more compact layout,
which then leads to better dynamic performance (particularly at high frequencies).
The extra two current-steering cells (annotated XLSB) are only used for DSM noise
79
XLSB LSB
MSB
Global Bias of tail
current devices
4 8
8 8 8 8 8 8
From o -chip
Figure 6.18: Biasing circuits of dual-rate hybrid DAC
SFDR [dB]
XLSB Mismatch [%]
This DAC Conventional DAC
100
95
90
3
1.5 4.5 0 5
Figure 6.19: Comparison of conventional and proposed DAC on SFDR vs. XLSB
mismatch
80
NSD [dBc/Hz]
XLSB Mismatch [%]
-162
3
1 5 0 8 2
4 6 7
-161.5
-161
-160.5
-160
-159.5
Figure 6.20: Similated NSD at 60 MHz output frequency vs. XLSB mismatch, 0
dBm, full-scale
cancellation. Since this noise-cancellation path only carries DSM noise information,
the mismatch of those XLSB cells causes less impact on overall DAC linearity.
According to Monte-Carlo simulations, the XLSB mismatch causes much less SFDR
degradation compared with conventional Nyquist DAC, as shown in Fig. 6.19.
Intuitively, in conventional DACs, equally weighted CSCs carry comparatively more
input signal information, and hence the SFDR is more sensitive to current-cell
mismatches. Figure 6.20 shows the simulated DAC noise spectral density (NSD)
at 60-MHz output frequency versus XLSB mismatch. Around 1.5-dB degradation
is observed with 8% standard deviation on XLSB CSCs.
6.2.2.4 Error Measurement
A vital part of the PEPD is the measurement of the amplitude and timing errors.
According to SPICE simulation, the amplitude error variation over temperature
(-25 to 105
C) and supply voltage ( 10%) is much less than 1 LSB of the digital
81
Figure 6.21: DAC error measurement
pre-distortion code. For timing errors, as long as the relative timing errors between
CSCs track suciently well with temperature and supply voltage, the pre-distortion
can still function well. In our prototype, a one-time foreground error measurement
after the chip fabrication is used, but the errors can be measured multiple times if
necessary, for example, in the case when the error may vary over circuit aging. This
may involve some on-chip measurement circuitry [11] and a redundant current cell
for background error measurement. It is noteworthy that the SPICE simulation
shows that SFDR and NSD vary by less than 2 dB and 0.5 dB respectively when
the temperature changes from -25 to 105
C after the one-time calibration at room
temperature.
There are two challenges in error measurement in general. First, the
icker
noise will degrade the precision of static-amplitude error measurement. We thus
intentionally toggle the current cells to translate the amplitude errors into higher
82
frequencies to mitigate
icker-noise eects. The second challenge is in dierenti-
ating error sources and measuring them separately. In this case, we exploit the
orthogonalities of the dierent errors. By toggling the two selected cells (REF and
DUT) in opposite polarities, the amplitude, delay, and duty-cycle errors at the
DAC output yield dierent time-domain waveforms and hence the corresponding
frequency-domain proles as shown in Fig. 6.21. Duty-cycle errors are easier to
dierentiate since they appear as even harmonics of the toggling frequency, while
both of the other two errors appear as odd harmonics. Since the amplitude error
dominates when the toggling frequency is low, the amplitude error is rst measured
with low toggling frequency. The delay error can then be measured at higher tog-
gling frequencies with the amplitude error pre-distortion turned on. To measure
the errors in the Lab, DAC outputs are connected to a spectrum analyzer for error
tones detection. Optimal error codes are determined corresponding to the lowest
error energy through a binary search algorithm. This procedure is repeated for
every CSC in the MSB path and is always referenced to a xed pre-selected CSC.
Should on-chip error measurement be desirable, on-chip mixing and ADC can be
used to measure the errors [11].
6.2.3 Measurement Results
The silicon test chip implemented in 65nm CMOS is packaged in QFN, and the
DAC output is dierentially loaded with a 50-ohm resistor while delivering an
83
1.99mm
1.66mm
Figure 6.22: Chip micrograph
output current of 16 mA. The total area occupies 3.3 mm
2
(with an active area
of 0.57 mm
2
); it consumes 681 mW of power; 462 mW of this is consumed by
digital circuits (including calibration and noise-cancellation logics, DSM, DDFSs,
and other testing logics), while 219 mW is consumed by analog (including high-
speed latches and CSCs). The chip micrograph shown in Fig. 6.22 indicates that
most of the area is occupied by digital circuitry, due to the nature of hybrid DAC
architecture.
Figure 6.23 shows the measured DAC errors. The rst gure on top shows
the amplitude errors of the corresponding 15 MSB cells before and after applying
amplitude pre-distortion with an accuracy of200 nA. The plots in the middle
and bottom gures are delay and duty-cycle errors, respectively, where the eective
calibration resolution is60 fs for both cases. Figure 6.24 shows the DAC output
84
Figure 6.23: Measured amplitude and timing errors
Improve
Without Pre-distortion With Pre-distortion
Figure 6.24: Spectrum snapshot with and without pre-distortion when f
sig
= 7.88
MHz
85
Improve 6.87dB
Without Pre-distortion With Pre-distortion
Figure 6.25: Spectrum snapshot with and without pre-distortion when f
sig
= 949
MHz
spectrum snapshot with 7.88 MHz input frequency before and after PEPD. The
SFDR is improved by 15 dB via pre-distortion and achieves 98 dBc. Figure 6.25
shows the spectrum snapshot with input frequency close to Nyquist at 949 MHz.
Before the pre-distortion, SFDR measures 68 dBc and is limited by the 2
nd
and 3
rd
harmonics. With pulsed timing-error pre-distortion, it is improved by 6 dB to the
level of 74 dBc. In both Fig. 6.24 and 6.25, the DWA is turned on and DEM is o
during the measurement.
Figure 6.26 shows the in-band noise-spectrum density versus signal frequency
when the DAC output is a full-swing 1-MHz/960-MHz sinusoid. Without the pro-
posed DSM noise cancellation, delta-sigma-modulator truncation noise rises at 500
MHz. With the noise cancellation enabled, the noise
oor is suppressed and remains
at within the band of interest. 7-dBc/Hz peak improvement in NSD is achieved
at 900 MHz.
86
Cancellation off (
= )
Simulation Results
-151
-153
-155
-157
-159
NSD [dBc/Hz]
300 800 400 500 600 700 900
Frequency [MHz]
-161
-149
Cancellation on(
= )
Cancellation on(
=
)
Cancellation off(
=
)
Figure 6.26: NSD comparison with and without proposed in-band noise cancella-
tion, 3 dBm, full-scale
95
85
90
80
75
70
65
60
0 200 400 600 800 1000
Signal Frequency,F
sig
[MHz]
SFDR [dBc]
DWA and Pre-distortion on
DWA on only
DEM on only
DWA/DEM/Pre-distortion off
Pre-distortion on only
Figure 6.27: SFDR versus signal frequency, 3 dBm, full-scale
87
This work
12b @ 2GS/s
12b@500MS/s
14b@4.6GS/s
12b@1.25GS/s
12b@1.6GS/s
16b@3.2GS/s
14b@3GS/s
12b@2.9GS/s
and 1.6GS/s
Signal Frequency, F
sig
[MHz]
SFDR [dBc]
0 200 400 600 800 1000
90
80
70
60
50
Figure 6.28: SFDR performance compared with state-of-the-art CMOS DACs, 3
dBm, full-scale
Since we have implemented both DEM and DWA modules in the MSB path
of the hybrid DAC, the SFDR measurements with dierent modes are plotted in
Fig. 6.27. We observe that DWA or DEM generally improves SFDR by 5{8 dB
over the entire Nyquist band. Based on DWA, the proposed pre-distortion scheme
further improves SFDR by 15 dB at low frequencies and by 6 dB around Nyquist
frequencies. Figure 6.28 shows the measured SFDR performance versus output
frequency in comparison with the state-of-the-art high-speed CMOS DACs. It
achieves 98 dBc peak SFDR at low frequency and maintains it above 80 dBc for
most of the frequency points up to 500 MHz. From 500 MHz to close to Nyquist
frequency, SFDR is generally around 75 dBc, with the worst case (74.4 dBc) found
at 949 MHz. It achieves the record SFDR performance among the state-of-the-art
techniques, given the same output frequencies.
88
-105
-100
-95
-90
-85
IM3 [dBc]
-80
-75
800 400 600 200 0 1000
Signal Frequency,F
sig
[MHz]
This work,
−
This work,
−
-70
[4] 16b@3.2GS/s
[21] 14b@4.6GS/s
Figure 6.29: IM3 perfromance compared with state-of-the-art CMOS DACs, 3 dBm,
full-scale
89
Table 6.1: Performance comnparison with state-of-the-art CMOS DACs
This
Work
Su
JSSC’15
Vel
ISSCC’14
Tseng
JSSC’11
Lin
JSSC’09
Doris
ISSCC’05
Lin
JSSC’14
McMahill
JSSC’14
Engel
ISSCC’12
Technology[CMOS] 65nm 65nm 65nm 90nm 65nm 0.18um 40nm 0.18um 0.18um
Architecture Hybrid Hybrid Nyquist Nyquist Nyquist Nyquist Nyquist Nyquist Nyquist
Resolution[bit] 12 12 16 12 12 12 12 14 14
Supply[V] 1/2.5 1/2.5 1.2/3.3 1.2/2.5 1/2.5 1.8 1.2 1.8/3.3 1.8/3
GHz] 2/8 1/8 3.2 1.25 1.6 2.9 0.5 1.6 4.6 3
mA] 16 16/20 20 16 50 15 16 80 20
Worst SFDR < 100MHz[ dBc] 81 80.5 78 73 71 71 62 70.3 74 76
SFDR @ 950MHz[dBc] 74.4 N/A N/A N/A N/A N/A N/A N/A 65 61
Peak SFDR < 950MHz[dBc ] 98 91 84 76 73 74 80 74 79.5 84
Worst IM3 < 950MHz[dBc] -80 N/A -68 N/A -61 -51 N/A N/A -74 -64
Peak IM3 < 950MHz[dBc] -101 N/A -89 N/A -78 -78 N/A N/A -97 -68
Active Area[
2
] 0.57 0.55 N/A 0.825 0.31 1.13 0.016 5.2 4
Figure 6.29 shows the results of the two-tone test: the IM3 is measured from
-80 to -101 dBc over the 1 GHz band and remains <-85 dBc within DC to the 300
MHz band. It mostly follows the trend of SFDR measurement over output fre-
quency. IM3 reaches a peak of -101 dBc at low frequencies and drops as frequency
rises. Over the Nyquist band, it remains below -80 dBc, which is also a notable
performance among the state-of-the-art high-speed CMOS DACs that report IM3.
It is worth mentioning that the aforementioned linearity and noise
oor measure-
ment does not change noticeably over 10% variation of the CSCs' supply voltage.
Table 6.1 summarizes the measured performance compared to other relevant prior
techniques. Compared with the previous dual-rate hybrid DAC, this work achieves
double the bandwidth (from 500 MHz to 1 GHz), which conrms the eectiveness
90
of the proposed cancellation and pre-distortion scheme. Note that the rst two
columns use dual-rate hybrid DAC architecture; they both achieve better linear-
ity compared to conventional Nyquist DACs, which conrms the potential of this
architecture in the high-speed and high-linearity regime.
6.2.4 Conclusion
The dual-rate hybrid DAC architecture takes the advantages of Nyquist and delta-
sigma DAC to minimize analog complexity and to leverage high-speed digital pro-
cessing. Based on the hybrid structure, an in-band noise-cancellation scheme is pro-
posed to widen the DAC bandwidth with reasonable implementation overhead. By
exploiting the ner voltage and time resolution of the oversampling path, a PEPD
scheme is proposed to calibrate the DAC timing errors for better high-frequency
performance. As a result of the proposed techniques and hybrid architecture, the
SFDR and IM3 of our silicon prototype compared favorably with the state of the
art. Through the analysis, simulation, and measurement results, this work aims to
enable new opportunities in the high-speed high-linearity regime for future DAC
design.
91
I- I+
ISS DPD
800mV
1V
MUX & Latches
Pipelined
Successive
2
nd
/3
rd
Order
BP-DSM
8 Channels
1X
15b
MSB
2X
4X
8X
8X
4b
LSB
8X
Single/Dual-rate Control
(LSB/MSB rate: 1/2/4/8)
16x
DDSs
+ 7]
[ + 1]
[]
B2T
Delay
Equ.
8 Channels
Measured
Errors
8x15 buses
MSBs
(4b)
LSBs
(12b)
(13b)
10x15
buses
(16b)
DWA
M1
M2
M3 M4
M5 M6
M7
M8
Vb2 Vb2
Vb1
Figure 6.30: System block diagram
6.3 A 16-bit 12-GS/s Single/Dual-Rate Hybrid
DAC
6.3.1 System Block Diagram
Figure 6.30 shows the system block diagram of the silicon prototype. The input
signals were generated on-chip via 16 DDFSs for a single/two-tone test, followed by
a single/dual-rate control block that splits the data into MSB and LSB paths. The
data rate ratio between the two paths was recongurable from 1 to 8. The MSB
path was converted into a thermometer code and randomized by the DWA block for
spurious tone reduction. The output of the DWA determined the error correction
pattern for inverse-Sinc shaped DPD on the corresponding current-steering cells.
The eight-way time-interleaved (TI) DSM was used in the LSB path. Since the DSM
was pipelined, delay equalization was applied in the MSB path to align the data
92
4b
3b
DSM
3b
10b
4b
10b
3b
7b
4b 3b 4b
7b 4b
3b
DSM
3b
DSM
13b
B
C
D
E
F
G A
DSM
IN
DSM
OUT
Pipelined
Adder
B D E F A G C
Bits shrinking
1x
4096x
8x
64x
8x
4096x
64x
4096x
512x
4096x
512x
4096x
64x
512x
13b
4b
2x
4x
8x
16x 16x 16x
64x
512x 512x 512x
32x 32x 32x
64x
128x 128x
256x 256x
128x
256x
128x
256x
2048x
1024x
2048x
1024x
2048x
1024x
2048x
1024x
2048x
1024x
Figure 6.31: Implementation of a second-order three-stage successive pipelined
DSM
phase. All the above circuit blocks were clocked at 1.5 GHz and were synthesized
through digital design
ow. A customized MUX with a multi-phase and multi-
frequency clock serialized the eight-channel 1.5-GS/s digital streams to a single-
channel 12-GS/s high-speed data stream for both MSB and LSB paths. A 12-
GHz clock was generated o-chip and buered via an on-chip CML buer and
dividers to generate all the necessary clock phases and frequencies. All the digital
bits were retimed by CML latches prior to the current steering cells. To achieve
precise retiming, the phase rotator for each clock had a tuning resolution of0.3
ps through current interpolation [21]. In the following subsections, we will examine
several critical building blocks.
93
Figure 6.32: 3-bit DSM: (1) Without pipelining; (b) With pipelining
6.3.2 Circuit Implementation
6.3.2.1 Tunable Bandpass DSM with Digital Chopper
Figure 6.31 shows the implementation of the proposed pipelined DSM. Each stage
consists of a 3-bit DSM and a pipelined adder. Four over
ow bits are generated
at the output of each DSM due to its OOB gain. To avoid bit growth at the nal
output of DSM, a multibit quantizer was used at the nal stage with smaller total
quantization errors. Additionally, the DSM was recongured to third order when
the conjugate zeros of NTF overlapped with each other to avoid excessive OOB
gain.
94
Figure 6.33: DSM with choppers
The 3-bit DSM used the EF structure with a 2
nd
-order NTF. By changing the
coecient a
1
, a
2
, and a
3
(Fig. 6.32), the location of zeros of NTF can be varied
along the unit circle for a tunable passband. The critical path of the conventional
EF DSM includes a tunable gain block and three adders (Fig. 6.32(a)). Due to the
all-pass property of STF in an EF structure, part of the delay cells in the feedback
path can be moved to the feedforward path for pipelining without changing the
NTF of the modulator (Fig. 6.32(b)).
After the adders are pipelined, the tunable gain block becomes the main speed
and area bottleneck, especially as the selectable channels increase. The tunable
gain block is a multiplier with selectable coecients for dierent channels. Here,
95
Ch16
Ch13
Ch1
0
= 1 = 0 = 1 = 0
Magnitude
Band B Band C Band D Band A
F
dsm
DC
0.5F
s
0.5F
dsm
0.75F
dsm
0.25F
dsm
Ch2
Ch3
Ch5
Ch6
Ch7
Ch8
Ch9
Ch10
Ch11
Ch12
Ch14
Ch15
Chopping mode
Channel 2&15
Channel 7&10
Frequency
F
dsm
@
1.5GS/s
F
s
@
12GS/s
Ch4
Figure 6.34: Spectrum of an eight-way TI DSM
there are eight channels from DC to F
dsm
/2, where Fdsm is the clock rate of DSM.
For high-speed operation, the products of input and the eight coecients are pre-
computed simultaneously and then selected by an 8-to-1 MUX. To reduce the crit-
ical path, we leveraged the symmetric property of the DSM. Digital choppers were
inserted at both the input and output of the pipelined DSM to toggle the polarity
of the input and output signals. These choppers can be simply implemented with
MUXs or XOR gates, and they will not aect the critical path of the modulator as
they are outside the DSM loop. The chopping rate was set to F
dsm
/2 so the shaped
noise before and after chopping would be symmetric around F
dsm
/4. Figure 6.33
shows the spectrum along the signal path under various settings. In the chopping
mode (S=0), the input signal was chopped twice while the DSM quantization noise
was only chopped once. Thus, we could use the same value of the lter coecients
to create another passband via spectral images, resulting in halved pre-computation
and MUX size.
96
To support the DC-6 GHz signal band, the DSM should operate at 12 GS/s,
which necessitates an eight-way TI DSM structure as depicted in Fig. 6.30. Since
the data rate is eight times the DSM clock rate, it creates four duplicated spectrums
within the Nyquist band annotated as bands A-D in Fig. 6.34. With four dierent
sets of lter coecients and a digital chopper, each band is divided into 16 channels
and each channel corresponds to a notch frequency of the NTF. As a result, there
are 64 available passband channels from DC to 6-GHz Nyquist frequency. Due
to the symmetric property, some of the channels are available simultaneously. As
shown in Fig. 6.34, when channel 7 and 10 are selected with notch frequencies of
f
7
andf
10
, the corresponding channels in band B, C and D centered at f
7
+nF
dsm
and f
10
+nF
dsm
can also be used, where n = 1, 2 and 3. Therefore, this DAC
conditionally supports carrier aggregation.
6.3.2.2 Current-Steering Cells
In the hybrid DAC structure, the MSB current sources were designed with rela-
tively small geometry to maintain high linearity at high frequencies (at the cost
of worse matching). Theoretically, the size of transistors can be reduced for those
MSB current sources as long as the current mismatches are within the calibration
margin. Meanwhile, the size of LSB current sources is determined by the required
accuracy in order to calibrate the MSB current sources. A common centroid layout
arrangement was applied for the LSB current sources with balanced supply and
97
ground routing. The current matching between MSB and LSB cells was done via
analog current tuning before inverse-Sinc shaped DPD is applied. It dramatically
reduces the magnitude of correction signal for the amplitude error, leaving more
margins for inverse-Sinc shaped DPD without increasing the number of LSB cells.
The schematic of a current steering cell is shown in Fig. 6.30. A cascode
transistor (M2) was used to enhance the output impedance of the tail current
source (M1) and isolate the large parasitic capacitance of the tail transistor to
the common source node. Minimum-length transistors were used for the current
switching pair (M3 and M4) for high-speed operation at the cost of a relatively large
mismatch. This mismatch of the current switching pair can be alleviated by the
fast data transition due to the small switch size. The proposed DPD can mitigate
the duty-cycle error due to the current switching pair mismatch [40]. Lastly, 2.5-V
thick-oxide transistors (M5 and M6) were inserted above the current switching pair
to further boost the output impedance of the current steering cell and protect the
core devices from voltage stress.
6.3.3 Measurement Results
The DAC prototype was fabricated in a 65nm CMOS process with a core area of
1.71 mm
2
. Fig. 6.35 shows the chip micrograph. The current steering (CS) array
occupies a relatively small area, while digital circuits occupy >88% of the total
98
Figure 6.35: Chip micrograph
core area. About 46% of digital circuits are used for testing. The mostly digital
architecture is highly
exible and benets from advanced technology nodes.
6.3.3.1 Measurement Setup
Figure 6.36 shows the measurement setup. The test chip is wire bonded in a stan-
dard QFN package. The dierential DAC outputs are open-drain and terminated
with a dierential 50-ohm on-board resistor. An Agilent E4440A spectrum analyzer
was used to monitor the single-ended output spectrum after a wideband balun for
single/two-tone tests and DAC error measurements. The 12 GHz clock was syn-
thesized by an Agilent E8251A signal generator, passing through the AC-coupling
capacitors and biased to the reference voltage on the PCB. All silicon measurements
were performed under room temperature.
99
Figure 6.36: Measurement setup
6.3.3.2 Static Performance
We measured the static performance of the DAC and used it for various DPD, as
described in [40]. The static amplitude errors were measured in the foreground
with two current cells toggling at opposite polarity, causing spurious tones. At low
toggling frequency, the spur was dominated by the amplitude error. By turning
on the amplitude-error DPD and sweeping the error code, quantized amplitude
error of DUT current branch could be found when the spurious tone reached its
minimum. After the amplitude error was compensated, duty-cycle and delay errors
were measured in a similar way except for the dierent spurious tone frequency (Fig.
6.37). The quantized timing errors were recorded until the corresponding spurious
tones could not be reduced. The inverse-Sinc shaped DPD had to be turned on
when measuring timing errors; otherwise, the measured errors would be inaccurate
due to the Sinc roll o of approximated error pulses.
100
1 1
1
0
0 0
Ref.
S1
S2
DUT
ISS
DPD
S1 S2
LSBs
4b
Load
-70
-80
-90
-100
-110
-120
-130
-140
0 1 2 3 4 5 6 7 8 9 10
-70
-80
-90
-100
-110
-120
-60
-50
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
-70
-80
-90
-100
-110
-120
-60
-50
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Pre-distortion off Pre-distortion on
PSD [dBm/Hz] PSD [dBm/Hz] PSD [dBm/Hz]
Frequency [MHz]
Frequency [GHz]
Frequency [GHz]
Res BW 16Hz
Res BW 10kHz
Res BW 10kHz
Amp. Error Pre-dist.
Amp. and delay
Error Pre-dist.
Amp. and Duty -cycle
Error Pre-dist.
-70
-80
-90
-100
-110
-120
-60
-50
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
PSD [dBm/Hz]
Frequency [GHz]
Amp. , delay and Duty -
cycle Error Pre-dist.
F
m
1.125MHz
F
m
1.125GHz
F
m
1.125GHz
Res BW 10kHz
F
m
1.125GHz
Pre-distortion off Pre-distortion on
Current Variation[%] Delay Error [ps]
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
Duty-Cycle Error [ps]
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
MSB Branches Number
MSB Branches Number
MSB Branches Number
Accuracy: 250 nA
Accuracy: 40 fs
Accuracy: 40 fs
1/F
m
DAC
output
Figure 6.37: Measured errors
101
Improve 11.4dB
DPD OFF
DPD ON
Figure 6.38: Measured single-tone spectrum with F
sig
= 3 GHz at F
s
= 9GS/s
DPD OFF
Improve
7.5dB
DPD ON
Figure 6.39: Measured two-tone spectrum with F
sig
= 3 GHz at F
s
= 9GS/s
6.3.3.3 Dynamic Performance
Figure 6.38 shows the DAC output spectrum with a 3 GHz input frequency before
and after DPD with a sample rate of 9 GS/s. The SFDR was improved by more
than 11 dB and achieved 66 dBc after DPD. In the two-tone test, IM3 was improved
by 7.5 dB and achieved 77 dB after DPD (Fig. 6.39).
102
Signal Frequency, F
sig
[GHz]
40
0 1 2 3 4
45
50
55
60
65
70
75
80
85
SFDR [dBc]
5 6
With DPD and DWA [9GS/s]
Without DPD and DWA [9GS/s]
With DPD and DWA [12GS/s]
Without DPD and DWA [12GS/s]
Figure 6.40: Measured SFDR, 3 dBm, full scale
Figure 6.40 shows the SFDR in dierent signal frequencies and operation modes.
The DWA and DPD improved SFDR by >18 dB at a low frequency, maintaining
the improvement of 59 dB when the signal frequency was close to the Nyquist.
Figure 6.41 shows the SFDR and IM3 performance plot compared with the
state-of-the-art, high-speed CMOS DACs. The SFDR remained above 65 dBc up
to 3 GHz at 9 GS/s and above 60 dBc up to 4 GHz at 12 GS/s. The IM3 was
measured from -85 to -67 dBc over the Nyquist band at 12 GS/s and from -87 to
-70 dBc over the DC-3 GHz band at 9 GS/s.
Figure 6.42 shows the SFDR performance versus the signal frequency when the
DAC is operating in the dual-rate hybrid mode. Dierent curves correspond to
dierent LSB and MSB data rate congurations. Generally, the slower the MSB
data rate, the better the SFDR performance.
103
Signal Frequency, F
sig
[GHz]
85
1 2 3 4 0 1 2 3 4 6 0
SFDR [dBc]
80
75
70
65
60
55
50
45
Signal Frequency, F
sig
[GHz]
IM3 [dBc]
-100
-90
-80
-70
-60
-50
-40
This work [16b 9GS/s]
This work [16b 12GS/s]
2
1
−
2
[16b 9GS/s]
2
2
−
1
[16b 9GS/s]
2
1
−
2
[16b 12GS/s]
2
2
−
1
[16b 12GS/s]
5 6
ISSCC 2017
14b6.8 GS/s
VLSI2016
14b8.9 GS/s
VLSI 2014
9b11 GS/s
ISSCC2017
14b6.8 GS/s
VLSI 2016
14b 8.9GS/s
VLSI2014
9b 11GS/s
VLSI2013
13b9GS/s
5
Figure 6.41: Measured SFDR and IM3 versus other high-speed CMOS DACs, 3
dBm, full scale
Signal Frequency, F
sig
[GHz]
0 0.5 1.5 2.5 3.5 4.5 1 2 3 4
60
SFDR [dBc]
65
70
75
80
85
90
LSB/MSB rate = 8 [9/1.125GS/s]
LSB/MSB rate = 2 [9/4.5GS/s]
LSB/MSB rate = 4 [9/2.25GS/s]
Figure 6.42: Measured SFDR in hybrid mode, 3 dBm, full scale
104
0
-125
NSD
[dBm/Hz]
NSD
[dBm/Hz]
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25
Signal Frequency, F
sig
[GHz]
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
2.25
-135
-145
-155
-165
-175
-125
-135
-145
-155
-165
-175
Ch. 1/16
Ch. 2/15
Ch. 3/14
Ch. 4/13
Ch. 5/12
Ch. 6/11
Ch. 7/10
Ch. 8/9
Chopping
mode (S=1)
Normal
mode (S=0)
RBW1Hz
RBW1Hz
Figure 6.43: Measured NSD
For the achieved noise
oor, Fig. 6.43 shows the measured NSD over dierent
passband settings with and without the chopping mode. The lowest in-band NSD
was measured around -170 dBm/Hz when the DAC output is a full-swing 1-MHz
sinusoid wave. To decouple the close-in phase noise of the clock source from the
DAC noise, the NSD is measured with more than 20 MHz oset from the 1-MHz
fundamental tone. Depends on dierent NSD requirements, the DAC supports
dierent signal bandwidth. As depicted in Fig. 6.43, -165-dBm/Hz NSD denes
an instantaneous bandwidth from 80 to 400 MHz while -155-dBm/Hz NSD has an
instantaneous bandwidth from 200 to 600 MHz. Thanks to the hybrid structure, the
OOB NSD measures below -130 dBm/Hz over the Nyquist band, which means that
the corresponding instantaneous bandwidth can be as high as 6 GHz for signals
require -130 dBm/Hz NSD. Table 6.2 compares our work with state-of-the-arts
high-speed CMOS DACs. In the single-rate mode, the DAC achieved a peak SFDR
105
Table 6.2: Performance comnparison with state-of-the-art CMOS DACs
This Work
Lin
ISSCC’18
Erdmann
ISSCC’17
Ravinuthula
VLSI’16
Olieman
VLSI’15
Xiao
VLSI’13
Technology 65nm 16nm 16nm 40nm 28nm 28nm
Resolution [bit] 16 16 12 14 9 13
Architecture Single-rate DSM Dual-rate (LSB/MSB rate >1) Nyquist Mixing Nyquist TI Nyquist
Fs [GHz] 12 9 9/4.5 9/2.25 9/1.125 6 6.8 8.9 11 9
Nyquist Bandwidth [GHz] 6 4.5 2.25 1.125 0.50625 3 3.4 4.45 5.5 4.5
Worst SFDR < 3GHz [dBc] 60 65 66
(1)
67
(1)
67
(1)
67 63 50 53 N/A
Worst SFDR < 4GHz [dBc] 59 56 64
(1)
66
(1)
70
(1)
67 59
(1)
50 52 N/A
Best SFDR < 6GHz [dBc] 76 82 82
(1)
83
(1)
88
(1)
88 84
(1)
71 64 N/A
Worst IM3 < 6GHz [-dBc] 67 67 71
(1)
77
(1)
77
(1)
72 66
(1)
66 52 44
Best IM3 < 6GHz [-dBc] 85 87 89
(1)
93
(1)
94
(1)
92 88
(1)
93 69 75
Power [mW]
Analog 250 240 230 230 230
350 330 1200 110 360
Digital 1510
(2)
960
(2)
910
(2)
870
(2)
850
(2)
Active Area [mm
2
]
Analog 0.1
0.52 0.855 N/A 0.04 1.16
Digital 1.61
(2)
(1)SFDR and IM3 are measured in higher Nyquist bands (i.e.2
nd
– 8
th
).
(2)Themeasured power and area include 16 16b DDSs operating at 1.125/1.5GHz
of 76 dBc at 12 GS/s and 82 dBc at 9 GS/s and a peak IM3 of -85 dBc at 12 GS/s
and -87 dBc at 9 GS/s, maintaining below -67 dBc IM3 up to Nyquist. In the
dual-rate modes, the prototype achieved a peak IM3 of -94 dBc and maintained
below -77 dBc up to Nyquist.
6.3.4 Conclusion
For this prototype, we demonstrate a highly
exible DAC that explores the poten-
tials of the hybrid structure in a high-speed (> GS/s) DAC design by overcoming
the OSR limitation of the conventional lowpass hybrid DACs via a tunable bandpass
DSM. A successive pipelining technique with time-interleaved structure was used to
implement a high-speed bandpass DSM. The equivalence of the successive DSM and
the conventional single-stage DSM was shown through mathematic derivations and
numerical simulations. Based on the hybrid architecture, an inverse-Sinc shaped
106
DPD scheme was used to enhance the DAC linearity over a wide signal band; this
was done by leveraging the high accuracy provided by the DSM. Lastly, the tech-
nology scaling should benet this digitally-intensive DAC architecture.
107
Chapter 7
Direct-Digital RF Modulator
7.1 Radio Revolution
To meet the growing demands of mobile access, increasing bandwidth, spectrum
eciency, and
exibility have always been the driving forces behind the wireless
revolution. CMOS technology scaling is the main driver of this process by providing
high-speed and low-cost devices, which favor more digitally-intensive design, as
shown in Fig. 7.1.
Beneting from the advances in technology and architecture, software-dened
radio (SDR) is proposed to support multi-standard and multi-band transmission
due to its high bandwidth and recongurability. Figure 7.2 depicts a conventional
analog-intensive heterodyne transmitter and a software-dened transmitter. The
heterodyne transmitter lacks
exibility due to the massive analog blocks. To sup-
port multi-band operation, the system becomes very inecient in terms of both
exibility and cost, as multiple transmitters are required. Ideally, a software-dened
108
Functionality
Single-band Radio
Multi-band
Radio Array
SDR
Implementation Digital Analog
Figure 7.1: Radio revolution trend (digital versus analog)
RF
High-speed clock
DAC
I
Q
DSP
Digital Analog
Digital Analog
PA
0
o
90
o
I
Q
LO
DAC
DAC
Digital
Analog
Heterodyne Transmitter Software-Defined Transmitter
Figure 7.2: Heterodyne versus software-dened transmitters
transmitter is essentially a super DAC that can convert the digital signal into RF
in one step with sucient output power and meanwhile meets all the specications.
However, this is not practical given the current technology. In addition, covering
signal bands from baseband to RF with a single wideband DAC is not as power
ecient as a heterodyne transmitter.
109
PA
0
o
90
o
I
Q
LO
Noise
Signal
Optional
DAC
BP Filter
Figure 7.3: Conventional DAC-based DDRM
7.2 Power-Ecient DDRMs
7.2.1 Conventional DDRM
To optimize the tradeos between the all-digital software-dened transmitter and
the analog-intensive heterodyne transmitter, an RF-DAC-based DDRM architec-
ture has been investigated with the upconversion function embedded in the DAC
via digital mixing, as shown in Fig. 7.3. There are two main advantages of moving
analog functions, such as upconversion and gain control, into the digital domain:
(1) digital operation provides power-ecient design with a small area and high re-
congurability, and (2) merging the functions of the DAC and mixer avoids linearity
degradation due to current-to-voltage and voltage-to-current conversions between
the two blocks, which is believed to be one of the dominant sources of distortion.
Depending on the target requirement, the nal PA stage is optional in the design.
For low-power modulators, a current-steering RF DAC is sucient to deliver the
110
PA
0
o
90
o
I
Q
LO
Noise
Signal
Optional
BP Filter
Lowpass Hybrid Delta-Sigma DAC
LSB
MSB
Din
B2T
16b 4b
12b
15b
4b
UDAC
BDAC
Out
DAC
ΔΣ
Figure 7.4: DDRM with a lowpass hybrid DAC
required output power. For more aggressive output power, power DACs with a
voltage-/current-mode class D/E/F type or combinations of these types of driver
are used with superior power eciency. Pre-distortions are typically used in these
power DACs due to the nonlinear operation of the switching drivers, i.e., the ef-
ciency trades o the linearity, which makes them less attractive for applications
that target high spectrum eciency.
7.2.2 DDRM with Lowpass Hybrid DAC and TAF
To further reduce the analog complexity of the system while achieving high in-
band resolution, we proposed the use of a hybrid DAC structure for the mostly
digital DDRM, as shown in Fig. 7.4. The 12-bit least signicant bit (LSB) data
is compressed to 4 bits via a third-order lowpass DSM. Compared to conventional
heterodyne transmitters, one of the most challenging aspects of a DDRM is to
suppress the unwanted noise and spurious tones that are upconverted to the carrier
frequency band due to the lack of baseband reconstruction ltering between the
111
PA
0
o
90
o
I
Q
LO
Conventional DDRM
LO
0
o
90
o
I
Q
Mod. LO
PA
Relaxed
Proposed DDRM w/ Time-Approx. Filter
Mod. LO
Lowpass
Response
BP Filter
Optional
DAC
ΔΣ
DAC
ΔΣ
Noise
Signal
Figure 7.5: Conventional DDRM versus proposed DDRM with TAF
DAC and the mixer. The situation becomes worse when hybrid DAC is used due
to the shaped DSM noise. A bandpass reconstruction lter in the RF domain
is typically required to ensure a low OOB noise
oor that meets emission mask
requirements; meanwhile, the lter should be highly recongurable with nearly
at
passband and sucient stopband attenuation for wideband communications. In
the case of FDD systems, additional frequency notches at the receiver band may be
needed to further suppress transmitter leakage to avoid desensitizing the receiver
when the transmitter and receiver are working concurrently. This tough noise
requirement makes the lter design very stringent within a reasonable power and
area budget. Additionally, the frequency response and attenuation requirements of
the lter can vary depending on communication standards, making it dicult to
be fully integrated.
To relax the lter requirement, a bandpass DSM is used to create spectral
notches for suppressing OOB noise with a limited in-band dynamic range. A
112
mixed-signal nite impulse response (FIR) lter technique has recently been ap-
plied in DDRM for OOB noise ltering by delaying and summing weighted replicas
of the input signal in the RF domain; this achieves deeper noise attenuation than
a conventional digital FIR lter given the same DAC element mismatches. As tap
weighting of the FIR lter is stored in the amplitude domain, i.e., the size of a
current source or a capacitor, both the accuracy and the recongurability of the
lter are limited.
To overcome the above limitations, we propose an embedded reconstruction
lter during the upconversion process of the DDRM to relax the remaining ltering
requirements in the RF domain, as shown in Fig. 7.5. We approximate the target
lter's impulse response via the time-domain local oscillator (LO) waveform (i.e., a
modulated LO rather than a periodic pulse train), which will eectively change the
DAC reconstruction waveform to achieve ltering. This TAF incurs a low overhead
due to minimal changes in the LO path and can be easily recongured due to the
mostly-digital operation. A time-interleaved (TI) structure is used for the DAC
implementation to deliver high output power without extra PA and meanwhile
enhance the performance of the TAF. To maintain a highly linear operation for
high spectrum eciency, i.e., 1024 quadrature amplitude modulation (QAM), we
used current-steering cells as the DAC elements and nal output drivers. Since a
hybrid DAC is applied to the DDRM architecture, TAF will help to attenuate the
OOB quantization noise introduced by the DSM.
113
PA
DAC
Mod. LO
LOi
LOq
0
o
90
o
BBi
BBq
Relaxed
Filter
RFi
RFq
RFout
Figure 7.6: DDRM with bandpass hybrid DAC and tri-level TAF
7.2.3 DDRM with Bandpass Hybrid DAC and Tri-Level
TAF
While a TAF provides certain recongurability in lter response, the time resolu-
tion requirement of the modulated LO waveform increases with the approximation
accuracy of the target lter response and likely demands a higher system clock rate.
To achieve greater
exibility with a minimal implementation design overhead, we
propose an enhanced DDRM architecture capable of a high in-band dynamic range
and/or a low OOB noise
oor at the desired frequencies. The DDRM involves
two key techniques: 1) a hybrid DAC with a recongurable dual-band DSM that
can create in-band and/or OOB spectral notches to support various communica-
tion scenarios and 2) a tunable tri-level TAF that further suppresses OOB noise
to achieve higher recongurability and stopband attenuation than existing TAFs
without increasing time resolution.
114
LSB
MSB
Din B2T UDAC
BDAC
Out
DAC
Noise
Signal
Noise
Signal
DSM
Quantization
Error
Figure 7.7: Bandpass hybrid DAC
Figure 7.6 shows the proposed DDRM architecture comprising the hybrid DAC
and tri-level TAF. The DDRM is implemented in a quadrature structure that
mainly consists of an I DAC and a Q DAC. Each DAC integrates the function-
ality of a baseband DAC, a mixer, a PA, and a recongurable bandpass lter. In
contrast to the two-level TAF, the tri-level TAF modulates the LO signal not only
on the pulse width but also the amplitude to achieve higher
exibility and stop-
band attenuation. A time-interleaving DAC structure is used to enhance output
power to the level that the PA can be signicantly relaxed or even replaced.
As shown in Fig. 7.7, the hybrid DAC uses a bandpass DSM to compress the
LSB input code, resulting in relaxed analog complexity and better linearity. The
hybrid DAC can be congured for various operation scenarios by manipulating the
noise transfer function (NTF) of the DSM, e.g., inserting notches at DC and/or
OOB.
Subsequently, the tri-level TAF further suppresses the OOB noise in four main
steps: 1) generating TAF responses (TAF H, TAF L) for the duration of the target
115
0.5x
TAF_L
Uniform LO
TAF_H
0.5x
DAC Array
ZOH
RFi/RFq
Tri-Level
TAF Gen.
BBi
/BBq
Cyclic Modulator
Digital
Mod. LO
Figure 7.8: Tir-level TAF
FIR (Fig. 7.8), 2) repeating TAF H, TAF L via a cyclic modulator, 3) multiplying
it with the uniform LO waveform, and 4) digitally mixing the baseband input
with the modulated LO waveform. Note that the entire tri-level TAF operation is
implemented in the digital domain, which makes the system highly recongurable.
Co-designing the DSM's NTF and the tri-level TAF provides maximal
exibility
in supporting a variety of communication scenarios, including creating a low in-
band and/or OOB noise
oor at multiple frequencies, as required by TDD, FDD,
andcarrier aggregation. Two representative cases using lowpass and bandpass DSM
NTFs with dierent tri-level TAF responses are presented in Fig. 7.9. For case 1,
the lowpass DSM supports high in-band resolution, while the OOB shaped DSM
noise will be ltered by the tri-level TAF. For case 2, both the bandpass DSM and
the tri-level TAF aim to suppress noise at the specic band of interest to meet
the stringent noise requirements of applications such as FDD. In this mode, the
116
Figure 7.9: Combined noise transfer functions with dierent DSM and TAF con-
gurations
in-band accuracy will not be as high as the lowpass DSM case. More details on
output reconstruction lters will be elaborated in following chapter.
117
Chapter 8
Time-Approximation Filter
Output ltering is one of the dominant factors that limits the applications of a
DDRM from many perspectives, such as OOB rejection, recongurability, and cost.
Most of these concerns are technology related; therefore, a scheme that benets the
advanced technology is always the most attractive one. In this chapter, we rst
review the existing lter techniques that are used in transmitters and then give an
introduction and analysis of the proposed TAF technique.
8.1 Reconstruction Filters
Analog lters are widely used in conventional heterodyne transmitters. The cost
and
exibility of analog lters are not scaling together with the technology, mak-
ing them less attractive to system-on-chip designs, and they are becoming one of
the bottlenecks of DDRM. With the advancement of high-performance DAC tech-
niques, a DDRM based on digital lters, i.e., interpolators, followed by a wideband
118
high-precision DAC becomes a competitive candidate with maximum relaxation of
the reconstruction lter; the use of the reconstruction lter can even be avoided
and simply relying on the selection capability of the output matching network, if
the DAC rate is suciently high. The accuracy requirement of the DAC is very
stringent for this type of architecture, and mismatches between DAC elements will
dramatically degrade the lter performance, particularly for high-speed designs.
Sophisticated DPD or dynamic element matching (DEM) are typically needed to
deal with element mismatches. A semi-digital FIR lter technique is proposed as a
baseband lter; this achieves deep OOB noise suppression via precisely controlling
the tap weighting of the FIR lter in the analog domain, while the delay of the signal
replicas is done in the digital domain. Recently, this mixed-domain FIR technique
has been widely used in DDRM for RF ltering by leveraging the higher Nyquist
zones of the discrete-time FIR lter. As mentioned in Chapter 7, the mixed-domain
FIR lter lacks recongurability, as each copy of the hardware is xed to present a
specic tap of the FIR lter, and the weighting of the tap is stored in the ampli-
tude domain with limited tuning range and precision. We propose a more digital
technique, i.e., TAF, with high recongurability and accuracy, which dramatically
increases the dynamic range of the high-speed digital-to-analog conversion.
The digital-to-analog conversion process consists of two steps: (1) computing
the weighted bitwise sum of the input digital signal in the discrete-time domain
(
P
x
d
[n]) and (2) converting the discrete-time signal into continuous time via the
119
time
ZOH
time
MRZ/Mixing
RZ NRZ
TI < T
s
time
Sine Shape
MRZ
Mixing
time
Arbitrary Shape
time
Sinc Shape
T
s
x
d
[n] y
h
(t)
ℎ()
x
d
[n]
δ(t − nT
s
)
x
()
ℎ(t)
y
h
(t)
DT
CT
Figure 8.1: Summary of DAC reconstruction lters
convolution of a reconstruction waveform (h(t)), typically a zero-order-hold (ZOH),
as shown in Fig. 8.1. Non-return-zero (NRZ) is one of the most commonly used
reconstruction lters among the ZOH, which holds the data for the whole sampling
period, i.e. T
s
. Each channel of a TI structure holds the data for longer than one
sampling period, which leads to a lower lter corner. However, the data duration
of a return-zero (RZ) reconstruction waveform is less than one sampling period,
which pushes the lter corner to a higher frequency with less signal attenuation
in the second Nyquist zone. Similarly, mixing and multiple-return-zero (MRZ)
reconstructions manipulate the signal gain in higher Nyquist zones to make the use
of these zones worthwhile. Reference [42] proposes a sine shape reconstruction lter
by using a sinusoidal LO signal. Note that all of the above-mentioned reconstruction
lters only provide rst-order ltering, which is typically not sucient for noise
rejection. In addition, they lack
exibility. Ideally, a sinc shape lter provides
perfect reconstruction. However, the impulse response of the sinc shape lter is
120
time time
Freq.
0 0
Freq.
time
0
Freq.
Signal
Noise
Sinc
Figure 8.2: Zero-order-hold reconstruction lter
innite, which is not possible to implement. Our goal here is to nd a reconstruction
waveform that is implementable, low cost, highly recongurable, and with high
stop-band attenuation. The impulse response of this target lter can be arbitrary
so long as it ts the sampling period.
8.2 Time-Approximation Filter
8.2.1 Baseband Time-Approximation Filter
Figure 8.2 shows the operation of a DAC with a ZOH reconstruction lter. In the
time domain, the DAC output is the convolution of the discrete time data and a
brick wall with a duration of one sampling period. This reconstruction method
creates a low-pass sinc lter response in the frequency domain that provides very
limited noise suppression. For some wideband applications, the non-
at response
in-band will even degrade system performance.
121
LP FIR
time time
Freq.
0 0
Freq.
time
0
Freq.
Signal
Noise
Figure 8.3: Generic FIR reconstruction lter
time time time
5 taps (DT) 5 taps (CT ZOH) 5 taps (TAF)
Digital Comparator
time
Sawtooth
time
PWM output
time
PAM
Signal
E.g.
Figure 8.4: Generation of time-approximation lter response
The most straightforward way to achieve better control of both in-band
atness
and OOB attenuation is to replace the ZOH waveform with the impulse response of
a generic FIR lter, as shown in Fig. 8.3. In the frequency domain, we essentially
swap the sinc lter with a higher order lowpass FIR lter. To implement this
reconstruction lter, each element of the DAC must be another high-accuracy DAC
that is capable of synthesizing this analog impulse response, i.e., continuous in
amplitude. In addition, if we want to make the reconstruction lter recongurable,
the diculty will dramatically increase.
122
LP FIR
time time
Freq.
0 0
Freq.
time
0
Freq.
Signal
Noise
Figure 8.5: Time-approximation reconstruction lter
We hence propose to approximate the pulse-amplitude modulated (PAM) FIR
impulse response with a digital-like pulse-width modulated (PWM) waveform. This
way, no extra hardware is needed compared to the conventional DAC element, as
a single switch is enough to synthesize the PWM waveform. Figure 8.4 shows an
example of how a 5-tap TAF response is generated. The original discrete time
impulse response of the target lter is rst calculated as the reference. Then it is
converted to continuous time via ZOH and nally compared to a sawtooth signal to
generate the time-approximated output. The corresponding DAC operation with
the time-approximation reconstruction lter is depicted in Fig. 8.5. Theoretically,
the TAF can perfectly approximate the target FIR lter, if innite ne time res-
olution is available. More design details and tradeo will be discussed in Chapter
9.
123
LPF(t)
time
LPF
(t)
0
Frequency
Magnitude
LPF(f)
LPF
(f)
Lower Corner
Larger
Attenuation
Lower
Peak
Longer Response
Figure 8.6: Long versus short impulse responses
Freq. 0 0
Freq.
0
Freq.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D
out
(Ch1)
D
out
(Ch2)
D
out
(Ch3)
D
out
(Ch4)
D
out
(Ch5)
D
out
(Ch6)
D
out
(Ch7)
D
out
(Ch8)
1/F
s
Sinc
Reconstruction Waveform
Figure 8.7: Timing diagram of an eight-way interleaved return-zero DAC
1
2
3
4
5
6
7
8
9
10
11
Freq. 0 0
Freq.
0
Freq.
FIR
D
out
(Ch1)
D
out
(Ch2)
D
out
(Ch3)
D
out
(Ch4)
D
out
(Ch5)
D
out
(Ch6)
D
out
(Ch7)
D
out
(Ch8)
8/F
s
Figure 8.8: Timing diagram of an eight-way interleaved non-return-zero DAC with
TAF
124
8.2.2 Time-Interleaving Structure
A long impulse response allows a lter with high stopband attenuation and low
corner frequency without sacricing lter sharpness, as shown in Fig. 8.6. To
achieve impulse responses longer than one sampling period, time interleaving is
necessary. Figure 8.7 demonstrates the timing diagram of a conventional eight-way
interleaved return-zero DAC. For long impulse response, the input data of each
time-interleaved channel is held for 8/F
s
, where F
s
is the data rate.
First, the slow data rate for each channel relaxes the timing constraint for the
digital circuitry. Second, since each DAC channel can hold the data sample for a
longer period, it provides higher output power, relaxing the gain requirement of
the following PA. Finally, given the time resolution for modulating the LO, the
TI architecture can approximate various lter impulse responses within 8/F
s
. For
example, a notch can be created at a specic frequency oset to reduce transmitter
(TX) leakage around that band.
8.2.3 RF Time-Approximation Filter
The nal goal is to synthesize a bandpass lter centered at the LO frequency. Con-
ventionally, this can be achieved by chopping the modulated data with a uniform
LO signal, as depicted in Fig. 8.9. To reduce the number of blocks along the signal
path, we combine the baseband TAF pattern generation and the upconversion into
125
Baseband
RF
LPF(t) LO
Discrete
DC
f
DC
f Fc
f
DC
f
DC Fc
Figure 8.9: Upconversion via a mixer
Baseband
LO
Discrete
LPF(t)
RF
DC
f
BPF(t)
DC
f
Fc
f
DC
f
DC Fc
f Fc DC
Digital Domain
Figure 8.10: Combining baseband TAF pattern with a uniform LO in digital domain
126
one step, as shown in Fig. 8.10. Note that this combined LO modulation is all
done in the digital domain, which is highly recongurable.
The time resolution of the LO modulation is constrained to the carrier frequency
for low-overhead implementation, which allows a simple gating operation on top of
the original LO. This gating operation requires a time-window pattern to determine
whether a particular LO cycle should be preserved or gated o. The time-window
pattern can be precomputed and programmed in on-chip memory. The multi-phase
clock signals then multiplex the stored time-window pattern into a single-bit data
stream, which gates the LO signal to generate a modulated LO signal.
8.3 Tri-Level Time-Approximation Filter
The tri-level TAF response generation is shown in Fig. 8.11. A general FIR lter's
impulse response magnitude is continuous, implying that ne amplitude quantiza-
tion is needed for its accurate approximation. This would require a large DAC array,
since each quantization level corresponds to one DAC element. TAF response can
be created by comparing the polarity of the FIR and a triangle waveform, requiring
only a single DAC element. However, due to the nite time resolution available in
any realistic implementation, TAF response must be quantized into a nite grid,
and this limits TAF performance through approximation inaccuracy in terms of the
achievable tuning range/resolution and stop-band attenuation.
127
Conventional FIR
N
Levels
xN
1
N
x
Target FIR
Proposed Tri-Level TAF
0.5x
x2
Resolution
Matching
TAF_H
TAF_L
1
0
1
0
1
0
0.5
0.5
3
Levels
TQ
TQ
TQ = Time
Quantizer
TAF_H’
TAF_L’
Time-Approximation Filter (TAF)
2
Levels
1x
Matching
X Resolution
Target
FIR
1
0
1
0
TQ
Resolution
X Matching
Figure 8.11: Tri-level time-approximation lter
Frequency Responses
Magnitude [dB]
0
-60
-20
-40
DC 0.5F
s
Frequency Mismatch
Stopband
Attenuation
Tri-Level TAF TAF Target FIR
Time Domain View of Tri-Level TAF Generation
Full Scale
Quantized
to time grid
FIR
Response
TAF_H’
TAF_H
TAF_L’
TAF_L
Tri-Level
TAF Res.
Time
0
Figure 8.12: Tri-level TAF response generation
128
To alleviate this limitation, we propose a tri-level TAF using two comparators
between the target FIR and level-shifted triangle waveforms. We then snap the
comparator outputs into nite time grids and generate TAF H/TAF L, creating the
tri-level impulse response shown in Fig. 8.12. Compared to a standard TAF using
the same grids, the tri-level TAF shows much improved approximation accuracy,
leading to better stop-band attenuation for some lter congurations. This also
allows better alignment of frequency notches from the tri-level TAF to the DSM
NTF, resulting in superior OOB noise suppression.
129
Chapter 9
Prototype DDRMs
9.1 A 1-5GHz DDRM with TAF
9.1.1 System Block Diagram
Figure 9.1 presents a block diagram of the proposed DDRM architecture. To derive
time-approximation ltering, the modulated LO waveform is created by repetitively
gating the periodic LO with a specic time-window pattern to determine whether
a particular LO cycle should be preserved or gated o. The time-window pattern
is stored in on-chip memory and selected by clocks divided from LO with proper
phases to generate the modulated LO, and this modulated LO is used to upconvert
the baseband signal, similar to a conventional mixing DAC, while simultaneously
achieving ltering. The input I/Q baseband signal is upsampled and interpolated
o chip. The test data stream is then programmed in on-chip static random access
memory (SRAM) and read by the DAC. Two DAC modes are implemented in this
130
Fs 0
o
90
o
Mod. LO
I
Q
ΔΣ
ΔΣ
Interp.
Interp.
G
LO
Stored
Time Window
Pattern
PLL
SRAM
&
Control
N FIR
DIV
16b
16b
RF
Out
M-Phase Clocks
Serializer
I
BB
Q
BB
FLO=1-5GHz
(2-10GHz)
THIS CHIP
64x
Figure 9.1: System block diagram of the proposed DDRM
prototype: a 7-bit Nyquist mode and a hybrid mode for achieving a low in-band
noise
oor via delta{sigma modulation of the input LSBs [20], [21]. For wideband
operation and a low OOB noise
oor, the DAC operates in the Nyquist mode. In
hybrid mode, the DAC takes up to a 16-bit digital input and compresses this into a
7-bit output. The high input dynamic range allows a high-order modulation scheme
in the DDRM, which is at the cost of a high OOB noise
oor. Fortunately, the
proposed TAF suppresses OOB DSM noise in this TX mode.
9.1.2 Circuit Implementation
9.1.2.1 Hybrid DAC
Figure 9.2 shows the hybrid DAC structure we used in this prototype. The 16-
bit digital input data is split into 4-bit most signicant bits (MSB) and 12-bit
LSB. The 4-bit MSB is converted to thermometer-coded 15-bit data and used to
131
LSB
MSB
Din
B2T
16b 4b
12b
15b
4b
UDAC
BDAC
Out
Figure 9.2: Hybrid DAC Structure
2:1
2:1
2:1
2:1
2:1
64
Mod.
LO
LO
LO/2
LO/4
LO/8
LO/16
LO/32
LO/64
2:1
2:1
2:1
2:1
2 2 2 2 2 2
CMOS
Divider
Clock Generator
32 16 8 4 2 1
DFF
64xDFFs
Figure 9.3: High-speed serializer-based LO modulator
control a unary current-steering DAC array. Simultaneously, the 12-bit LSB is
compressed to 4 bits by a third-order lowpass DSM and used to control a binary
current-steering DAC array. The nal output is combined via current summation.
The DSM is an unrolled 1-1-1 multistage noise shaping (MASH) architecture for
high-speed operation.
9.1.2.2 LO Generator
The LO modulation for TAF is achieved by a high-speed serializer, as shown in
Fig. 9.3. This mainly consists of memory cells, i.e., D-type
ip-
ops (DFF), 2-
to-1 multiplexers (MUX), and a mixing lath. The 64 DFFs are used to store the
TAF response patterns and are programmable. The stored pattern is read out in
132
clk
CML
÷ 2
clkb
Phase
Rotator
Phase
Rotator
Phase
Rotator
CMOS
to
CML
CMOS
to
CML
CMOS
÷ 2
CMOS
÷ 2
CMOS
÷ 2
d_i
d_ib
d_q
d_qb
LO (I channel)
LO/2
LO/4
LO/8
CMOS
to
CML
CMOS
÷ 2
CMOS
÷ 2
CMOS
÷ 2
CMOS
÷ 2
LO/16 LO/32
LO/64
LO (Q channel)
CML
Buf
reset
d
db
CML
Latch
CML
Latch
reset
d db
Tunable
Fixed
Figure 9.4: Clock generator
sequence via an array of 2-to-1 MUXs that are controlled by multi-frequency and
multi-phase clocks. These clocks are divided from the uniform LO signal and trim
to proper phases via the clock generator. Finally, the mixing latch clocked by the
LO signal is used to synchronize and chop the TAF pattern to create the modulated
LO.
9.1.2.3 Clock Generator
The clock generator that is used to create multi-frequency multi-phase clocks is
shown in Fig. 9.4. The input clock (1{11 GHz) is sent from o chip, buered by a
CML driver, and divided into four dierent phases via a current-mode logic (CML)
divider. The four-phase clocks are then used to interpolate a ner clock phase for
serializer clock trimming and I/Q timing alignment. After the phase interpolator,
or phase rotator, the CML signals are amplied to rail-to-tail CMOS signals then
133
Mixing Latch Mod.
LO
Digital
Data
clk
out
in
clk
clk
clk
out
Current
Cell
Current
Out
clk
out
clk
clk
clk
out
in
in
vdd
gnd
S2D
Figure 9.5: Master-slave latches
further divided down by a group of CMOS dividers. For clocks slower than LO/4,
we xed the phases to save power from the phase rotators.
9.1.2.4 Mixing Latch
Data synchronization is achieved by a three-stage latch chain to minimize the input
data dependency. The rst two latches, shown in Fig. 9.5, form a master{slave DFF
that converts the single-end digital input data to dierential and stores it in the
rst half of the modulated LO period for the mixing latch [39]. The mixing latch
applied prior to the DAC element is controlled by the modulated LO for both
data synchronization and frequency upconversion. Multiple operation modes of the
mixing latch are used to experiment with dierent output power levels for chip
characterization purposes, as shown in Fig. 9.6.
134
clk
out in
in
dc
SRZ
dc
SMIX
clk
clk
clk
clk
clk
clk
clk
out
clk
isup
to5.2GHz
Mode
1
2
3
Function
Latch
Latch+AND
Latch+XOR
Figure 9.6: Mixing latch
DMM
LO Modulator DMM
LSB0(1x)
LSB1(2x)
LSB2(4x)
MSB1(8x)
MSB12(8x)
MSB14(8x)
LSB3(8x)
MSB0(8x)
Mixing Latches
Mixing Latches
Mixing Latches
DMM
0V
1V
V
b3
I
N
I
P
CMOS
Drivers
V
b2
V
b1
D
Db
I
out
Mixing Latch Array
D
in
LO
Figure 9.7: Class-A current-steering driver and
oor planing
135
Figure 9.8: Eight-way time-interleaved quadrature structure
9.1.2.5 Output Driver
The class-A type current-steering cell driver is used for its high intrinsic linearity
and wideband property (Fig. 9.7). Two cascode devices are inserted at the output
to increase the DAC output impedance and protect the core switching devices, as
the DAC output load is connected to the 2.5 V supply for a larger output swing.
The binary-weighted LSB current cells are controlled by the oversampling path of
the hybrid DAC for a compact analog design. Sucient dummy cells are placed on
the two sides of the current-steering cell for better matching. Each mixing latch is
well aligned with the corresponding current-steering cell for minimal timing skew.
A replica of the mixing latch is used as the last stage of the LO modulator.
For an eight-way interleaved quadrature structure, the current array is copied
16 times, as shown in Fig. 9.8. Data and clocks for I and Q DACs are routed
from the center and distributed to each channel in a balanced three-dimensional
136
Figure 9.9: Chip micrograph and performance summary
tree structure for tolerable skew. Each channel is laid out close to its subsequent
channels to minimize spurs due to channel mismatches.
9.1.3 Measurement Results
The silicon prototype is fabricated in 65nm CMOS technology with total area of
6.25 mm
2
. Fig. 9.9 shows the die micrograph.
The prototype chip is directly bonded to the printed circuit board (PCB) for
less bond-wire inductance. The measurement setup is shown in Fig. 9.10. All the
power supplies are generated by LDOs on a voltage board. Similarly, bias currents
for current-steering cells and the clock generator are provided by a current board
through wires. The 1{11 GHz clock is synthesized with a E8251A signal genera-
tor, converted from single-end to dierential clocks via an LTCC packed wideband
balun, and sent to the chip. All of the digital controlling signals are generated
137
Figure 9.10: Measurement setup
138
XOR Digital Mixing
AND Digital Mixing
Frequency [GHz]
Peak Pout [dBm]
0.5
-5
1.5 2.5 3.5 4.5 5.5
0
5
10
15
20
25
Figure 9.11: Measured DDRM output power
from an on-chip serial peripheral interface (SPI) module, which communicates with
the laptop via a USBee module. To support a long test pattern length, an Agilent
16902A pattern generation module is used for SRAM writing and sequential control.
The dierential I/Q output is open drain and terminated with a 50-ohm load (i.e.,
the equipment) via power combiners, which include surface mounted RF chokes,
baluns, and a discrete hybrid. A power spectrum analyzer is used to monitor the
RF output spectrum and perform single-tone/two-tone/adjacent channel leakage
ratio (ACLR) tests, while an error vector magnitude (EVM) test is undertaken via
a wideband oscilloscope and vector signal analysis tool.
When XOR digital mixing is performed, the peak output power of the DDRM
is measured from 23 to 0 dBm via a continuous wave (CW) test over a wide carrier
frequency range of 0.9 to 5.2 GHz. Peak output power for the AND digital mix-
ing mode is measured for comparison, as depicted in Fig. 9.11. The power drop
139
Fs = 625MHz
Fsig = 15MHz
Effective FLO = 5GHz
Image
HD2=-60dBc
HD3=-72dBc
Figure 9.12: Spectra of single-/two-tone signal in baseband mode
is mainly due to impedance mismatch over frequency, which can be resolved via
impedance tuning [55].
Before testing modulated signals at RF, the mixing latch is recongured into
a conventional latch to characterize the time-interleaved DACs. Figure 9.12 shows
the single-/two-tone spectra of the I/Q DAC at baseband at 625 MS/s, which
corresponds to a 5 GHz eective LO, i.e., the clock of the latch is a 5-GHz LO
signal divided from a 10-GHz external clock, and it is further divided down for data
clocking. The SFDR is limited by the residue image due to the mismatches between
the time-interleaved channels. The intermodulation distortion (IM3) measures -64.5
dB with 68-MHz signal frequency.
The measured IM3 over various signal frequencies and the corresponding signal
power at 625 MS/s are illustrated in Fig. 9.13. The rst notch of the sinc locates
at 1/8
th
of F
s
due to the NRZ time-interleaved structure, and, hence, the wide-
band signal will be distorted at the band edges more severely than an RZ case.
140
150 50
IM3 [-dBc]
50
60
70
80
90
100
Signal Frequency [MHz]
100 200 250 300 350 0
Signal Power [dBm]
-80
-60
20
0
-20
-40
IM3 @ 2F
1
-F
2
IM3 @ 2F
2
-F
1
P
out
@ 2F
1
P
out
@ 2F
2
Figure 9.13: Measured IM3 versus signal frequency
Fortunately, this in-band
uctuation is highly predictable and can be considered
as a linear error, so either an inverse-sinc predistortion from the transmitter or an
adaptive equalizer from the receiver can correct it back to meet the target accuracy.
Figure 9.14 shows the far-out/close-in spectra of a 20-MHz 256-QAM and a 10-
MHz 1024-QAM. Figure 9.15 shows the constellation from the 256 and 1024-QAM
modulated signals at 2.4 GHz. Due to the limited size of on-chip SRAM, more
than one capture of data is performed to construct the constellations. The EVM
measures -42 and -43 dB.
To validate the wideband operation, Fig. 9.16 shows the measured constellations
of a 40-MHz and a 20-MHz 64-QAM signal at 4.4 GHz. The EVM measures -30 dB
and -34 dB. All of the measurement data is collected without applying any DPD.
The DDRM intrinsically achieves high linearity via current-steering operation. The
141
Image Replica
256 QAM
Hybrid Mode
BW 20MHz
FLO 2.4GHz
EVM -42dB
0
-10
-20
-30
-40
-50
-2.37 -2.4[G] [dB]
With no DPD.
1024QAM
Hybrid Mode
BW 10MHz
FLO 2.4GHz
EVM -43dB
0
-10
-20
-30
-40
-50
-2.37
-2.4[G] [dB]
TI Channel
Mismatch
With no DPD.
Figure 9.14: Spectra of a 20-MHz 256 QAM and a 10-MHz 1024 QAM signals at
2.4 GHz
I-Q
200m
/div
-0.8
0.8
0.8 0
0
Rng=505mV
I-Q
200m
/div
-0.8
0.8
0.8 0
0
Rng=400mV
Figure 9.15: Constellations of the QAM signals at 2.4 GHz
142
EVM -35dB
BW 40MHz
64 QAM
F
LO
4.4GHz
EVM -36dB
BW 20MHz
F
LO
4.4GHz
64 QAM
Rng 128 mV
1.5
I-Q
300
m
/div
-1.5
-2.36678201 2.366782007
20
%
LinMag
2
%
/div
Start 0 sym Stop 419 sym
Rng 128 mV
20
%
LinMag
2
%
/div
Start 0 sym Stop 419 sym
Rng 128 mV
0
%
0
%
Rng 128 mV
1.5
I-Q
300
m
/div
-1.5
-2.36678201 2.366782007
Figure 9.16: Constellations of the QAM signals at 4.4 GHz
performance sensitive circuits, such as the mixing latch and current-steering cells,
are optimized at around 2.4 GHz by design, which is proved from the measurement
results.
Various lter responses are set to compare the eectiveness of the TAF (Fig.
9.17). The measured Nyquist-mode NSD at 2.4 GHz is plotted in Fig. 9.18. Com-
pared to a conventional RZ-TI DDRM, the proposed TAF achieves 25{35 dB noise
rejection over the Nyquist band (using a low-pass lter LPF1/LPF2 conguration);
it also recongures into a lter that enhances the rejection of a specic band (LPF3).
The maximum stopband rejection measures over 50 dB at a 100 MHz oset from
the carrier frequency. To conrm lter
exibility, the LPF4 lter conguration is
measured, moving the notched stopband by 20 MHz from LPF3. The measured
143
RZ
LPF1
LPF2
LPF3
One Period of Mod. LO Pattern (8/F
s
)
Figure 9.17: Impulse responses of the FIR lters
Figure 9.18: Measured NSD with dierent lter and DSM congurations
144
0 5 10 15 20
-110
-120
-130
-140
-150
-160
-170
RX. Band NSD at
100MHz offset [dBc/Hz]
Average Pout [dBm]
Better
performance
Digital Tx
Analog Tx
FDD
requirement
This work
Figure 9.19: NSD performance comparison with state-of-the-art transmitters
NSD in the hybrid DAC mode shows a low in-band noise
oor as the DAC reso-
lution is increased from 7 to 16 bits, while the OOB noise is suppressed to < -123
dBc/Hz due to the TAF.
Compared to state-of-the-art transmitters, including the high-power PAs and
low-power modulators, as shown in Fig. 9.19, this prototype achieves high linear-
ity at higher output power and a low OOB noise
oor at the notch frequency of
the TAF, which pushes the envelope of the current architectures and potentially
facilitates FDD operation.
Table 9.1 summarizes the performance of this work and compares it with several
state-of-the-art digital DDRMs. It shows that this work operates over a wide LO
range with outstanding peak power and system eciency among the medium/low
output power, high-linearity wideband DDRMs. Table 9.2 summarizes the dynamic
performance of this work. It achieves high linearity in terms of EVM and ACLR.
Compared with the high-power PAs, this work trades o the eciency with linearity,
145
Table 9.1: General performance summary
Specifications This work
B. Mohr
RFIC 2014
P. Filho
ISSCC 2016
M. Mehrpoo
JSSC 2018
Architecture Digital IQ Digital IQ Digital IQ Digital IQ
Reconstruction Filter Time-Approx. FIR Sinc Sinc
2
Sinc
1-3
Process [nm] 65 65 28 40
Supply [V] 1/2.5 1.2/2.5 0.9/1.1 1.1/2
Resolution [bits] 7-16 10 12 9
F
LO
Range [GHz] 0.9-5.2 2-2.6 0.9/2.4 0.9-3.1
Fs Range [MS/s] 112-625 860 500 250-750
Peak Psat [dBm] 23 @ 1GHz 11.9 3.5 9.2
Peak
[%] 15 @ 1GHz 6.8 1.8
*
7
* 7dB power backoff.
Table 9.2: Dynamic performance comparison
Specifications This work
B. Mohr
RFIC 2014
P. Filho
ISSCC 2016
M. Mehrpoo
JSSC 2018
F
LO
[GHz] 2.4 4.4 2 2.4 3
Bandwidth [MHz] 10/20 20/40 20 20 57
EVM [dB] -43/-42 -36/-35 -31 -36 -30
ACLR1 [dB] -44.3/-42 -39/-37.6 -33.5 -47 -44
ACLR2 [dB] -54.8/-55.3 -52.5/-53.5 N/A -59 N/A
Noise Floor [dBc/Hz]
-158
@100MHz
N/A N/A
-159
@45MHz
N/A
Peak OOB
Rejection
[dB]
>50dB
@100MHz
N/A N/A N/A N/A
Modulation 1024/256 QAM 64 QAM LTE Multi-tone 64 QAM
N/A – Not available.
146
and it achieves record NSD performance via TAF. As a mostly digital technique,
the application of TAF is not limited by the type of output driver; it can potentially
be used in high-eciency PAs, such as class D, E, and F PAs, to simultaneously
achieve high power, high eciency, and low OOB noise.
9.1.4 Conclusion
This prototype demonstrates a highly
exible 1{5 GHz DDRM that achieves <
-158 dBc/Hz NSD at 100 MHz, oset from a 2.4 GHz carrier by applying the
proposed TAF technique, which approximates a FIR lter impulse response in time.
The prototype incurs a low overhead due to minimal changes in the LO pathway.
Because the time-window pattern is implemented in the digital domain, it has high
exibility in terms of approximating dierent FIR lter impulse responses, which
potentially facilitates FDD operation. An eight-way time-interleaved structure is
implemented to further increase the output power and to achieve high-order TAF
responses. The silicon prototype achieves a 23 dBm peak power at 0.9 GHz and a
-43 dB EVM of a 10-MHz 1024-QAM signal at 2.4 GHz.
9.2 A 1-6GHz DDRM with Tri-Level TAF
In this prototype, a recongurable bandpass DSM is used in the hybrid DAC struc-
ture to support both a high in-band accuracy and a low OOB noise level. In
addition, tri-level TAF is used to further suppress OOB noise without increasing
147
the system clock rate. A proof-of-concept prototype in 65 nm CMOS achieves -40
dB EVM and -169 dBc/Hz NSD at 68 MHz oset using a 17.4-dBm 256-QAM
signal at 2.2 GHz carrier.
9.2.1 System Block Diagram
Figure 9.20 presents the system block diagram of the proposed DDRM. DDRM
test vectors are stored in an on-chip SRAM, and the quadrature data (Di and Dq)
read from the SRAM can either be processed by the hybrid DAC logic or directly
passed to the output current steering cells. An eight-way time-interleaved DAC
structure for the I/Q channel is used for two purposes: rst, to enhance the output
power, and, second, to eectively generate ner time resolution and longer duration
for the tri-level TAF impulse response. For DDRM output, an on-chip wideband
quadrature power combiner is used to sum the I/Q power, converting the dierential
signals to single-ended and terminating the nal output signal to a 50-ohm load.
9.2.2 Circuit Implementation
The implementation of a sub-channel DAC is shown in Fig. 9.21, including the tri-
level TAF generator. The DAC array consists of 15 thermometer-coded 32x MSB
branches, 3 thermometer-coded 8x branches, and 4 LSB branches to accommodate
design tradeos. The LSB branches are controlled by the DSM output signal,
148
50Ω
VDD
Q3 Q6
Q2 Q7
Q4 Q5
Q1 Q8
I6 I3
I7 I2
I5 I4
I8 I1
SPI
Q Ch.
I Ch.
128b
clki/8 clkq/8
SRAMs
8-stage Counter
Latches CNT
ΔΣ
8
B2T
DEM
MSB
LSB
Latches CNT
ΔΣ
8
B2T
DEM
MSB
LSB
Hybrid
DAC
Modulator
Analog
Digital
Bypass
Cap
Digital Data
Di Dq
VDD
Bypass DSM
CLK
Gen.
Figure 9.20: System block diagram of proposed DDRM
149
lob
lo
64b 64b
1x 2x 4x 8x 8x 8x 8x 32x 32x
Mixing Latch Array
64:1 64:1
128b
lo
lob
TAF_H,TAF_L
(From SPI)
clk
Counter
Digital Data
Cyclic
Modulator
3lvl-TAF
Mixing Latch
Current Array
Mod. LO
Figure 9.21: Implementation of sub-channel DAC
150
V
b2
V
b1
0.5x 0.5x
0.5x
V
b3
0.5x 0.5x
0.5x
0.5x
0.5x 0.5x
0.5x 0.5x
0.5x
V
b3
V
b2
V
b1
outb
out
D1 D1b D2 D2b
Figure 9.22: Current-steering cell
which requires high precision. For better matching, these current branches are
sized suciently large and carefully laid out.
A digital-to-time converter with a tuning resolution of around 60 fs aligns the
skews between the time-interleaved DACs, and, to support the tri-level TAF, each
current steering cell is split into two equally weighted paths controlled by D1/D1b
and D2/D2b, as shown in Fig. 9.22. These control codes are generated by the
mixing latch array, which performs input data latching and mixing with the corre-
sponding modulated LO (Fig. 9.21). The TAF H and TAF L responses are stored
in SPI and periodically read out by a 64:1 MUX via a wrap-around counter acting
as a cyclic modulator. It then multiplies with the uniform LO (lo and lob) via
another mixing latch, and a modulated LO is generated. Here, we used the same
mixing latch structure as the DDRM prototype discussed in the previous section.
151
Bits
Compress
4096x
1x(LSB)
512x 512x
4096x
Din Dout
13b
H(z)
4b
9b
Din Dout
Figure 9.23: Error-feedback bandpass DSM
1 zero
1 zero
2 zeros
0
DC F
s
/2
Mag.
DC F
s
/2
Mag.
Tunable
Signal
DC
F
s
/2
Mag.
DC
F
s
/2
Mag.
Two bands
0
2 zeros
1/2/3
zeros
0
1 zero
1 zero
1 zero
0
1 zero
Split notches
1
st
-3
rd
Order LP 2
nd
Order BP
Dual Band: LP/BP Dual Band: Split Notches
Figure 9.24: DSM congurations
152
a
3
Z
-1
a
2
a
3
a
4 Channel 1
Channel 2
e[n-8]
Dout[n] Din[n]
e[n-1]
e[n-2]
e[n-3]
e[n-4]
Dout[n-1]
e[n-9]
e[n]
e[n-1]
Channel 8
a
4 e[n-5]
Dout[n-7]
e[n-15]
e[n-7]
e[n-4]
Tunable Eight-Way Unrolled BP DSM
s[n] MSB{s[n]}
LSB{s[n]}
45-to-1 MUX
Band Sel.
out
in
1,5
1,6
1,1
1,3
1,4
1,2
Tunable High-Speed
Multiplier
a
1
Stored Coefficients
@ Fs>1GHz
Feedback
Errors
Figure 9.25: Implementation of high-speed bandpass DSM
Figure 9.23 presents the proposed bandpass DSM in the LSB path of the hybrid
DAC. The DSM takes the 12-bit LSB from the 18-bit input signal and reserves one
more bit for calibration margin and then truncates the signal to 4 bits to reduce
analog complexity. Multi-mode operation is achieved by reconguring the DSM
NTF, as shown in Fig. 9.24. The NTF can have two tunable complex zeros at
the same location or one tunable complex zero with a real zero at DC or Nyquist
frequency. The DSM can also be tuned from rst to third order to trade o the
in-band and OOB noise performance.
To achieve over a 1 GS/s eective rate, we use an eight-way unrolled DSM, with
each channel operating at 125 MS/s, as shown in Fig. 9.25. For a high-speed tun-
able gain stage with a wide tuning range (i.e., 45 congurations in this prototype),
a MUX-based multiplier is used with minimized critical path. In addition, the mul-
tiplications are performed by shifting and summation for simplicity and shortened
critical paths.
153
Figure 9.26: Chip micrograph
9.2.3 Measurement Results
Figure 9.26 shows the chip micrograph fabricated in 65 nm CMOS with a total
area of 8.68 mm
2
. The measurement setup is presented in Fig. 9.27. The die is
directly attached to the PCB board via chip-on-board bonding to reduce the clock
and data trace for wideband operation. A clock of up to 12 GHz is generated by a
E8251A signal generator, converted from single-end to dierential, and then sent to
the chip. SPI is controlled by a USBee pattern generator, while a 16902A pattern
generation module with sucient memory is used for SRAM data write-in. The
RF output switches between the E4440A spectrum analyzer and the MSOV084A
mixed-signal oscilloscope for noise measurement and demodulation, respectively.
154
Figure 9.27: Measurement setup
155
0
5
10
15
20
25
0.5 1 1.5 2 2.5 3 3.5
3dB
1.6 GHz
F
LO
[GHz]
P
sat
[dBm]
Figure 9.28: P
sat
versus F
LO
Normalized Q
Normalized I
EVM -40dB 256 QAM
2.14 2.18 2.22 2.26
-50
-40
-30
-20
-10
0
BW 20MHz
Frequency [GHz]
Spectrum [dBr]
Figure 9.29: Measured spectrum and constellation of a 20-MHz 256 QAM signal at
2.2 GHz
Figure 9.28 shows the peak output power of DDRM over LO frequencies. Thanks
to the time-interleaved structure, the prototype achieves 22 dBm peak power and
11.7% peak system eciency at 2.2 GHz. A wideband on-chip power combiner
is used in this design with an output 3-dB bandwidth more than 1.6 GHz. A
multi-band power combiner can also be applied here for wider signal bandwidth.
156
Figure 9.30: Measured NSD
157
Figure 9.29 shows the measured spectrum and constellation of a 17.4-dBm 20-
MHz 256-QAM signal at 2.2 GHz. EVM measures -40dB. Measured NSD is shown
in Fig. 9.30. With a 2-MHz 256-QAM signal, the DSM is congured at third-
order lowpass for high in-band resolution, and the tri-level TAF is congured for
optimal OOB noise suppression (case 1). The OOB NSD measures less than -150
dBc/Hz over the Nyquist band. To achieve a lower noise
oor at a specic band,
we recongure the DSM's NTF to bandpass and tune the notches of DSM and
tri-level TAF to the same band of interest. As a result, the NSD measures -169
dBc/Hz at 68 MHz oset (case 2, 3 MHz bandwidth) without a SAW lter. The
ne-tuning resolution of the proposed tri-level TAF allows the lter notch to shift
with a frequency step of 3 MHz (cases 3{6). The tunable DSM and tri-level TAF
enable a lower OOB noise
oor than published transmitters with a comparable
output power and noise
oor, as shown in Fig. 9.30.
Figure 9.31 shows the measured ACLR over average output power with 10-MHz
and 20-MHz 256-QAM signals at 2.2 GHz and shows two representative spectra at
peak average power. Figure 9.32 shows the measured ACLR1 over various carrier
frequencies from 1 to 6 GHz and shows the spectrum snapshot at around 2.2 GHz.
The DAC image is below -45 dBr referring to signal power. Figure 9.33 presents the
measured gain mismatch errors of each time-interleaved channel, and the spectra of
a 10-MHz and a 20-MHz 256-QAM signals with and without channel gain mismatch
calibration. The raw mismatch errors are measured by sequentially toggling the
158
-45.07
dBm
0.52
dBm
-45.20
dBm
-54.76
dBm
-54.14
dBm
Average Power [dBm]
ACLR [dBc]
Average Power [dBm]
ACLR [dBc]
Signal Bandwidth = 10MHz Signal Bandwidth = 20MHz
0 5 10 15 20
-80
-70
-60
-50
-40
-30
-20
-10
0 5 10 15 20
-80
-70
-60
-50
-40
-30
-20
-10
ACLR1
ACLR2
ACLR1
ACLR2
Figure 9.31: Measured ACLR
159
-60
-55
-50
-45
-40
1 2 3 4 5 6
Carrier Frequency [GHz]
ACLR1 [dBc]
1.8 2 2.2 2.4 2.6
-50
-40
-30
-20
-10
0
Frequency [GHz]
Spectrum [dBr]
BW 10MHz
Span 1GHz
DAC
Image
Figure 9.32: Measured ACLR1 over carrier frequencies
w/ Channel Gain Mismatch Calibration
w/o Channel Gain Mismatch Calibration
2.17 2.18 2.19 2.20
2.17 2.18 2.19 2.20
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
-60
-70
Spectrum [dBr] Spectrum [dBr]
Frequency [GHz]
Frequency [GHz]
Signal BW
10MHz
Signal BW
20MHz
1 2 3 4 5 6 7 8
-10
-5
0
5
10
1 2 3 4 5 6 7 8
-10
-5
0
5
10
Deviation [%] Deviation [%]
Channel Number
Channel Number
Measured Channel Gain Mismatch Errors
I DAC
Q DAC
Figure 9.33: Measured spectra before and after channel gain calibration
160
Table 9.3: Performance summary
Specifications This work
Tang
ISSCC’19
Liu
ISSCC’18
Roverato
ISSCC’17
Fulde
ISSCC’17
Bhagavatula
ISSCC’17
Filho
ISSCC’16
Giannini
ISSCC’11
Boos
ISSCC’11
Pozsgay
ISSCC’08
Architecture
Digital
IQ
Analog
IQ
Analog
IQ
Digital
IQ
Digital
Polar
Analog
IQ
Digital
IQ
Analog
IQ
Digital
Polar
Digital
IQ
Matching Network On-chip On-chip On-chip On-chip On-chip On-chip Off-chip On-chip On-chip Off-chip
Process [nm] 65 28 14 28 28 14 28 40 N/A 65
Active
Area
[mm
2
] 2.4 8.3
(a)
1 0.82 1.3 1.1 0.22 0.98 2 0.35
Supply [V] 1/2.5 1.2/1.8 N/A 0.9/1.5 1/1.1/1.3 1/1.8 0.9/1.1 1.1/2.5 1.2/2.5 1.2
Resolution [bits] 9-18 N/A N/A 10 15 N/A 12 N/A 14 11
Fs Range [MS/s] 125-750 N/A N/A 850-900 700-2800 N/A 500 N/A >1000 1350
(a) It Includes two transmitters for carrier aggregation;
(b) Measured with a 2-MHz 256 -QAM signal and the DSM set to bandpass mode;
(c) Measured with P
out
= 0 dBm;
(d) Measured with a 10 -MHz 500-MS/s CW;
(e) Measured with P
out
=-4 dBm.
SC – Single Carrier
F
LO
[GHz] 2.2 2.59 2.53 0.9 2.54 0.79 2.4 1.85 0.9 2.5
P
out
[dBm] 17.4 6.3 3.1 3 6 4.9 -3.5 2.6 6 2.6
[%] 4.5 2.7 1.8 1.3 2.9 2.6 1.8 1.4 3.4 0.72
Bandwidth [MHz] 10 20 20 20 20 40 20 20 20 5 17
EVM [dB] -41 -40 -40 N/A N/A -28.9 -32 -36 -31.7 -28 -32.4
ACLR1 [dB] -46 -45 -45 -44.7 -61 -41.9 -42 -47 -38.4 -50 -42.8
ACLR2 [dB] -55 -51 N/A N/A N/A -52.9 N/A -59 -59 N/A -46.2
Noise
Floor
[dBc/Hz]
-169
(b)
@68MHz
-158.9
@80MHz
-157.8
@80MHz
-158
@30MHz
-152
@120MHz
-155
(c)
@31MHz
-159
(d)
@45MHz
-162.5
@80MHz
-160
@45MHz
-145
(e)
@500MHz
OOB Noise
Suppression
Scheme
Noise Shaping +
Tri-level TAF
Analog
Filter
Analog
Filter
Noise
Shaping
Sinc
Analog
Filter
Sinc
2
Analog
Filter
Sinc
2-tap
FIR
Modulation
SC
256 QAM
LTE
QPSK
LTE
/
LTE
/
2xLTE20
64 QAM
LTE
/
Multi-tone
64 QAM
LTE
/
WCDMA
/
OFDM
64 QAM
N/A – Not available
= P
out
/P
DC
channel that is under measuring and the reference channel with opposite polarity
while other channels are xed to be static. Then the mismatch errors used for
calibration are calculated by referring to the mean value of the error. Thanks to
the high-resolution DSM used in the hybrid DAC, the gain calibration can be very
precise.
Chip performance is summarized in Table 9.3 and compared to state-of-the-art
high-performance quadrature transmitters of both digital and analog architectures.
The proposed noise shaping and tri-level TAF eectively achieved a record OOB
161
noise
oor at 68 MHz oset from the carrier frequency without using analog lters.
Since the class-A driver (current-steering cell) is used as the DAC element, the
DDRM achieves good linearity in terms of ACLR and EVM, even without applying
DPD.
9.2.4 Conclusion
This DDRM incorporates the hybrid DAC architecture using a recongurable dual-
band DSM, which can create in-band and/or OOB spectral notches to support
various communication scenarios. In addition, it applies the proposed tri-level TAF
concept, allowing highly
exible OOB noise suppression simply via LO waveform
modulation. The SAW-less DDRM prototype achieves -40 dB with a 17.4 dBm
20-MHz 256-QAM signal at 2.2 GHz and -169 dBc/Hz OOB NSD at 68 MHz oset
from the carrier frequency. The techniques proposed in this work are not limited
to a specic standard. They are generic techniques that can be applied to various
circuit typologies and architectures.
162
Chapter 10
Conclusion and Future Directions
10.1 Conclusion
To achieve wideband, high-dynamic-range digital-to-RF conversion for next gen-
eration wireless communication, a high-speed hybrid DAC structure and a set of
linearization techniques are proposed. Three prototype DACs are implemented to
prove the eectiveness of the proposed architecture and techniques. The extension
work applies the hybrid DAC architecture in a DDRM to contribute to the radio
revolution from a system level. A TAF is proposed in this DDRM to lter the
DSM OOB noise and/or to achieve high system dynamic range via suppressing the
noise at a specic band of interest. Two prototype DDRMS are implemented, for
which record noise performance is measured thanks to the proposed hybrid DAC
architecture and TAF.
163
2
4
6
8
10
12
14
16
18
20
22
24
1k 10k 100k 1M 10M 100M 1G 10G
Delta-Sigma
SAR
Pipeline
Async.
Time
Inter.
Flash
Sampling Rate
ADC Resolution
Figure 10.1: Summary of ADC architectures
10.2 Future Directions
10.2.1 High-Speed and High-Resolution ADCs
Relevant explorations of high-performance analog-to-digital converters (ADC) is
one possible future direction for increasing the impact of all of the aforementioned
DAC techniques. ADC is the counterpart of DAC on the receiver side, which plays
an important role in both wireless and wireline communication. An ADC archi-
tecture survey is shown in Fig. 10.1 in the dimension of sampling rate and resolu-
tion [56]. Among these, the four mainstream architectures are
ash, delta{sigma,
SAR, and pipeline ADC. Flash ADC can operate fast but with limited resolution.
Pipeline and SAR are power-ecient architectures with medium speed and medium
164
DAC
Decoder
Vin
CLK
Decoder
CLK
Vref
Vin
ADC DAC
S/H
Stage 1 Stage 2 Stage N
Res.
Amp.
Flash ADC
SAR ADC Pipeline ADC
Sigma-Delta ADC
Vin
DAC
1/S 1/S
DAC
Figure 10.2: Flash, Delta-Sigma, SAR and Pipeline ADCs
resolution. Delta{sigma ADC can achieve high resolution but with a limited sam-
pling rate due to the oversampling ratio requirement.
Block diagrams of the four ADC architectures are shown in Fig. 10.2. Other
than
ash ADC, all of the high-precision power-ecient ADC architectures require
very high-performance DACs, as highlighted. When the target resolution or speed
increases to specic points, the DAC becomes the bottleneck of the ADC. Over the
past decade, quite a few of the bench-marking successive-approximation-register
(SAR) and delta{sigma ADCs have been the result of innovative DAC ideas. There-
fore, the DAC techniques that we have developed so far will potentially help with
breakthroughs in ADC performance.
165
TDC
DAC
Digital Loop
Filter
VCO
FCW
Σ
TDC
DAC
Digital Loop
Filter
VCO
FCW
Σ
DTC
Time to digital
converter
High-precision
time to digital
converter
Conventional Digital PLL DTC-Assisted Digital PLL
out out
Figure 10.3: DTC-assisted high performance TDC for all-digital PLL
10.2.2 Low-Power and Low-Jitter PLLs
Phase-locked loop (PLL) can also potentially benet from DAC techniques. As
shown in Fig. 10.3, the performance of a conventional digital PLL is limited by
the time-to-digital converter (TDC) resolution and dynamic range. To design a
TDC with a resolution less than 1 ps and a simultaneously large full-scale range is
very challenging with CMOS technology [57], [58]. To relax the TDC or eectively
increase the TDC resolution, a digital-to-time converter (DTC) is proposed to assist
the TDC design [59]. This way, both the eective TDC resolution and the full-scale
range can be improved. The DTC here is essentially a DAC that converts the digital
signal to an analog delay.
10.2.3 Software-Dened Radio
Figure 10.4 presents the complete block diagram of the conventional heterodyne
transceiver and the software dened radio, including both transmitter and receiver.
166
Heterodyne Transceiver Software-Defined Radio
RF
Fast clock
DAC
DSP
I
Q
PA
0
o
90
o LO
DAC
DAC
x N
DSP
I
Q
LNA
0
o
90
o LO
ADC
ADC
x N
RF
ADC
Transmitter
Receiver
Digital
Digital
Key blocks: 1. DAC
2. ADC
3. PLL
Figure 10.4: Heterodyne transceiver versus software-dened radio
The SDR involves a mostly digital design, which consists of three main analog
blocks, ADC for data acquisition, DAC for signal synthesis, and PLL for clock
generation. As SDR was foreseen a long time ago, much eort has been made to
improve the performance of ADC, DAC, and PLL along with technology scaling.
In the near future, technology scaling will slow down and may even stop at some
point. We believe that architecture-level innovations will be the main driver for
the next generation of communication systems. As mentioned above, advanced
DAC architectures/techniques and DAC-assisted ADC/PLL designs could be key
enablers for software-dened radio.
10.2.4 Analog/Mixed-Signal Design Automation
The automation of analog mixed signal schematic generation has remained a chal-
lenge for many years. Our approach is inspired by and is a generalization of earlier
167
Biased random
design parameters
in search space
Metrics
Finer sweep in Metrics
Selection
Filter2
Preparation Work (Part of Module library)
Human in Loop
User Intent
Designer
Knowledge
Specifications
Module Metrics
Constraints
Priorities
(Area/Power)
Designer
Knowledge
Spice
Training dataset
Train the regression model
Final
Netlist
Parameter Candidates
Final Netlist
Generation
Module Library
Generation
Exploration using
Regression Model
Selection
Filter1
Designer’s
Priority
No Human in Loop
No Human in Loop
Database
Sorting
and /or
Local
Optimization
Spice
IP
Validation
Spice
Figure 10.5: Analog/mixed-signal design automation tool
eorts that used very specic searches to discover new behavior. For example, [60],
starting with the observation that most analog circuits use a small number of tran-
sistors, a numerical study of all possible congurations of a two-transistor circuit
was initiated. In our view, a key aspect of this previous successful work is its
narrow focus. Our approach also minimizes searches by maximizing the use of dig-
ital synthesis, utilizing knowledge of known-good circuit designs, and limiting the
exploration of the parameter space around these point solutions.
Figure 10.5 shows a block diagram of the proposed automated analog and mixed
signal (AMS) circuit generator
ow. It consists of three major steps. The rst step
is to prepare the parameterized module library. This step consists of breaking a
known-good design (KGD) into smaller independent modules, which serve as build-
ing blocks for a parameterized library. We then explore the relationship between
design parameters and the performance metrics of the module. Conventional AMS
168
design requires a thorough design exploration through a combination of designers'
knowledge and intensive SPICE simulations, which is typically a time-consuming
process. In our design
ow, we explore the possibility of deriving a suciently ac-
curate regression model for all of the modules, leading to an expedited parameter
search process, as the computational requirement for using the regression model is
signicantly less in comparison to SPICE simulation.
Once the module library is created and user intention is well captured at the
module level, the appropriate modules for each block are selected using a selection
lter. We use a Python script to read the module library and search for modules
matching the metrics decomposed in the previous step. Through this process, a
few candidates that meet the constraints are selected. They are further validated
through SPICE simulation. If the performance is accurate enough and meets the
target specication, the best candidate is chosen for generating the nal netlist.
Otherwise, a local optimization routine can be applied to ne tune the parameter
around the selected candidate.
It is worth exploring more algorithms on this analog/mixed-signal automation
tool, and the tool signicantly reduces the design cost and time for the system
designer. More importantly, it may change the way in which people design analog
circuits. Designers can be released from repetitive simulations for optimization and
focus more on the innovative elements.
169
References
[1] B. Oyama et al., \InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog
Converter With > 70-dB SFDR", IEEE J. Solid-State Circuits, vol. 48, no. 10,
pp. 2265-2272, Oct. 2013.
[2] F. Van de Sande et al., \A 7.2 GSa/s, 14 bit or 12 GSa/s, 12 bit signal generator
on a chip in a 165 GHz fT BiCMOS process," IEEE J. Solid-State Circuits, vol.
47, no. 4, pp. 1003-1012, Apr. 2012.
[3] W. H. Tseng et al., "A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70
dB SFDR up to 500 MHz," IEEE J. Solid-State Circuits, vol. 46, no. 12, pp.
2845-2856, Dec. 2011.
[4] G. Engel et al., \A 14b 3/6GHz current-steering RF DAC in 0.18um CMOS with
66dB ACLR at 2.9GHz," ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2012.
[5] J. Savoj et al., "A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Con-
verter for Backplane Communications," IEEE J. Solid-State Circuits, vol. 43,
no. 5, pp. 1207-1216, May 2008.
170
[6] C-H. Lin et al., \A 12 bit 2.9GS/s DAC with IM3 < -60dBc Beyond 1GHz
in 65nm CMOS", IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285-3293,
Dec. 2009.
[7] K. Doris et al., \A 12b 500MS/s DAC with > 70dB SFDR up to 120MHz in
0.18um CMOS," ISSCC Dig. Tech. Papers, pp. 116-117, Feb. 2005.
[8] G.A.M. Van Der Plas et al., \A 14-bit intrinsic accuracyQ
2
random walk CMOS
DAC," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.
[9] J. Bastos et al., \A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J.
Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1999.
[10] D. A. Mercer, \Low-power approaches to high-speed current-steering digital-
to-analog converters in 0.18-m CMOS," IEEE J. Solid-State Circuits, vol. 42,
no. 8, pp. 1688-1698, Dec. 2007.
[11] Y. Tang et al., \A 14 bit 200 MS/s DAC with SFDR >78 dBc, IM3 < -83
dBc and NSD < -163 dBm/Hz Across the Whole Nyquist Band Enabled by
dynamic-mismatch mapping," IEEE J. Solid-State Circuits, vol. 46, no. 6, pp.
1371-1381, Dec. 2011.
[12] L. Ribo et al., \Digital approaches to ISI-mitigation in high-resolution over-
sampled multi-level D/A converters," IEEE J. Solid-State Circuits, vol. 46, no.
12, pp. 2892-2903, Dec. 2008.
171
[13] R. Adams et al., \A 113-dB SNR oversampling DAC with segmented noise-
shaped scrambling,"IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1871-1878,
Dec. 1998.
[14] K. Nguyen et al., \A 108dB SNR, 1.1mW oversampling audio DAC with a
three-level DEM technique," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.
2592-2600, Dec. 2008.
[15] BURR-BROWN Corporation, PCM67/69A datasheet.
[16] K. L. Chan et al., \Dynamic Element Matching to Prevent Nonlinear Distor-
tion From Pulse-Shape Mismatches in High-Resolution DACs," IEEE J. Solid-
State Circuits, vol. 43, no. 9, pp. 2067-2078, Sept. 2008
[17] K. K. Parhi, \Pipelined and Parallel Recursive and Adaptive Filters," in VLSI
DigitalSignalProcessingSystems: DesignandImplementation, 1st ed. NJ: John
Wiley & Sons, 1999, ch. 10, sec. 5, pp. 339-344.
[18] U. Singh et al., \Dynamics of high-frequency CMOS dividers," Proc. ISCAS,
vol.5. pp. 421-424, 2002
[19] W. Lin et al., \A 12-bit 40 nm DAC Achieving SFDR> 70 dB at 1.6 GS/s and
IMD < {61dB at 2.8 GS/s With DEMDRZ Technique," IEEE J. Solid-State
Circuits, vol.49, no.3, pp.708-717, Mar. 2014
172
[20] S. Su et al., "A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma
modulator achieving >75dB SFDR over 500MHz in 65nm CMOS", in Proc.
Symp. VLSI Circuits, pp.1-2, June 2014
[21] S. Su et al., \A 12 bit 1GS/s dual-rate hybrid DAC with an 8GS/s unrolled
pipeline delta-sigma modulator achieving > 75 dB SFDR over the Nyquist
band," IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 896{907, Apr. 2015.
[22] K. Doris et al., \D/A conversion: Amplitude and time error mapping optimiza-
tion," in Proc. 8th IEEE Int. Conf. Electronics, Circuits and Systems (ICECS
2001), 2001, vol. 2, pp. 863{866.
[23] H. van de Vel et al., \A 240mW 16b 3.2GS/s DAC in 65nm CMOS with
<-80dBc IM3 up to 600MHz", International Solid-State Circuit Conference
(ISSCC) 2014, pp. 206-207
[24] T. Zeng et al., \New Calibration Technique for Current-Steering DACs", Proc.
IEEE ISCAS, pp. 573-576, May 2010.
[25] E. Olieman et al., "An Interleaved Full Nyquist High-Speed DAC Technique,"
IEEE J. Solid-State Circuits, vol. 50, no. 3, pp. 704-713, March 2015.
[26] T. Chen et al., \A 14-bit 200-MHz current-steering DAC with switching-
sequence post-adjustment calibration," IEEE J. Solid-State Circuits, vol. 42,
no. 11, pp. 2386{2394, Nov. 2007.
173
[27] Y. Cong et al., \A 1.5-V 14-bit 100-MS/s self-calibrated DAC," IEEE J. Solid-
State Circuits, vol. 38, no. 12, pp. 2051{2060, Dec. 2003.
[28] A. R. Bugeja et al., "A 14-b, 100-MS/s CMOS DAC designed for spectral
performance," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1719-1732, Dec
1999.
[29] T. Shui et al., "Mismatch shaping for a current-mode multibit delta-sigma
DAC," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 331-338, Mar 1999.
[30] R. Baird et al., \Linearity enhancement of multibit A/D and D/A con-
verters using data weighted averaging," IEEE Trans. Circuits Syst. II, Analog
Digit. Signal Process., vol. 42, no. 12, pp. 753{762, Dec. 1995.
[31] D. Barkin et al., \A CMOS Oversampling Bandpass Cascaded D/A Converter
With Digital FIR and Current-Mode Semi-Digital Filtering," IEEE J. Solid-
State Circuits, vol. 39, pp. 585-593, Apr. 2004.
[32] S. Su et al., \A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error
pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to
1GHz in 65nm CMOS," ISSCC Dig. Tech. Papers , Feb. 2016, pp. 456{457.
[33] T. Matsuura et al., \A high eciency transmitter with a delta-sigma modulator
and a noise cancellation circuit," Proc. Eur. Conf. Wirel. Technol., 2004.
174
[34] A. Ghosh et al., "A novel quantization noise-cancellation scheme in wideband
D/A converters," 2011 IEEE 54th International Midwest Symposium on Cir-
cuits and Systems (MWSCAS), 2011, pp. 1-4.
[35] D.R. McMahill et al., "A 160 Channel QAM Modulator With 4.6 Gsps 14 Bit
DAC," IEEE J. Solid-State Circuits, vol.49, no.12, pp.2878,2890, Dec. 2014
[36] J. Xiao et al., "A 13-Bit 9GS/s RF DAC-based broadband transmitter in 28nm
CMOS", in Proc. Symp. VLSI Circuits, pp.C262-C263, 12-14 June 2013
[37] V. Ravinuthula et al., \A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving
> 71dBc LTE ACPR at 2.9GHz," 2016 IEEE Symposium on VLSI Circuits
(VLSI-Circuits), Honolulu, Jun. 2016.
[38] E. Bechthum et al., \A wideband RF mixing-DAC achieving IMD < -82 dBc
up to 1.9 GHz," IEEE J. Solid-State Circuits, vol. 51, no. 6, pp. 1374{1384,
Jun. 2016.
[39] C. Erdmann et al., \A 330mW 14b 6.8GS/s Dual-Mode RF DAC in 16nm
FinFET Achieving -70.8dBc ACPR in a 20MHz Channel at 5.2GHz," in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 280{281, Feb.
2017.
175
[40] S. Su et al., \A 12-Bit 2GS/s Dual-Rate Hybrid DAC With Pulsed-Error Pre-
distortion and In-band Noise Cancellation Achieving >74dBc SFDR and <-
80dBc IM3 up to 1GHz in 65nm CMOS," IEEE J. Solid-State Circuits, vol. 51,
no. 12, pp. 2963-2978, Dec. 2016.
[41] S. Su et al., \A 16b 12GS/s single/dual-rate DAC with successive bandpass
delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable
passbands," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Pa-
pers, Feb. 2018, pp. 362{364.
[42] S. Luschas et al., \Radio frequency digital-to-analog converter,"IEEE J. Solid-
State Circuits, vol. 39, no. 9, pp. 1462{1467, Sep. 2004.
[43] A. Jerng et al., \A wideband digital-RF modulator for high data rate
transmitters," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1710{1722, Aug.
2007.
[44] A. Frappe et al., \An alldigital RF signal generator using high-speed mod-
ulators,"IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2722{2732, Oct. 2009.
[45] P. Madoglio et al., \A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, modulator
based on standard cell design with time-interleaving," IEEE J. Solid-State Cir-
cuits, vol. 45, no. 7, pp. 1410{1420, Jul. 2010.
176
[46] A. Bhide et al., \An 11 GS/s 1.1 GHz bandwidth interleaved DAC for 60
GHz radio in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 50, no. 10, pp.
2306{2318, Oct. 2015.
[47] A. Pozsgay et al., \A fully digital 65 nm CMOS transmitter for the 2.4-to2.7
GHz WiFi/WiMAX bands using 5.4 GHz RF DACs," in IEEE Int. Solid-
State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 3{7, 2008, pp. 360{619.
[48] J. J. McCue et al., \A time-interleaved multimode RF-DAC for direct digital-
to-RF synthesis," IEEE J. Solid-State Circuits, vol. 51, no. 5, pp. 1109{1124,
May 2016.
[49] P. Seddighrad et al., \A 3.6 GHz, 16 mW DAC for a 802.11n/802.16e
transmitter with 30 dB digital power control in 90 nm CMOS," in Proc. 34th
Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 15{19, 2008, pp. 202{205.
[50] C.-H. Lin et al., \A 16b 6GS/s Nyuist DAC with IMD< -90dBc up to 1.9GHz
in 16nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, Feb. 2018, pp. 360-362.
[51] M. Mehrpoo et al., \A Wideband Linear I/Q-Interleaving DDRM", IEEE J.
Solid-State Circuits, vol. 53, no. 5, pp. 1361-1373, May 2018.
[52] E. Roverato et al., \All-digital RF transmitter in 28nm CMOS with pro-
grammable RX band noise shaping," ISSCC Dig. Tech. Papers, pp. 222{223,
Feb. 2017.
177
[53] M. Fulde et al., \A Digital Multimode Polar Transmitter Supporting 40MHz
LTE Carrier Aggregation in 28nm CMOS," ISSCC Dig. Tech. Papers, pp.
218{219, Feb. 2017.
[54] P. E. P. Filho et al., \0.22mm2 CMOS Resistive Charge-Based Direct-Launch
Digital Transmitter with -159dBc/Hz Out-of-Band Noise," ISSCC Dig. Tech.
Papers, pp. 250{251, Feb. 2016.
[55] W. M. Gabor et al., "A 21-dBm I /Q Digital Transmitter Using Stacked Output
Stage in 28-nm Bulk CMOS Technology," IEEE Trans. Microw. Theory Techn.,
vol. 65, no. 11, pp. 4744-4757, Nov. 2017.
[56] M. S.-W. Chen et al., \A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-
m CMOS," IEEE J. Solid-State Circuits, pp. 2669-2680, Dec. 2006.
[57] C.-M. Hsu et al., \A Low-Noise, Wide-BW 3.6GHz Digital Fractional-
N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and
Quantization Noise Cancellation," ISSCC Dig. Tech. Papers, pp. 340-341, Feb.
2008.
[58] M. Lee et al., \A Low-Noise Wideband Digital Phase-Locked Loop Based on
a Coarse{Fine Time-to-Digital Converter With Subpicosecond Resolution,"
IEEE J. Solid-State Circuits, pp. 2808-2816, Sep. 2009.
178
[59] V. K. Chillara et al., \An 860W 2.1-to-2.7GHz All-Digital PLL-Based Fre-
quency Modulator with a DTC-Assisted Snapshot TDC for WPAN (Bluetooth
Smart and ZigBee) Applications," ISSCC Dig. Tech. Papers, pp. 172-173, Feb.
2014.
[60] F. Bruccoleri et al., \Noise cancelling in wideband CMOS LNAs," ISSCC Dig.
Tech. Papers, Feb. 2002.
179
Appendix A
A.1 Quantization Error of the Two-Stage DSM
From Fig. 4, the following operators are dened as:
LSB
i
fvg =vmod
i
(A.1)
MSB
i
fvg =v LSB
i
fvg (A.2)
where v is a positive integer number2 [0; 2
N
1). The output of the rst-stage
DSM is given by:
MSB
1
fy[n]g =x[n] LSB
1
fy[n 2]g + 2LSB
1
fy[n 1]g LSB
1
fy[n]g (A.3)
180
Sum A.3 from k = 1 to m, and assume the initial state of integrator has all the
nodes equal to 0 (i.e., y[n] = 0, for all n 0); we have:
m
X
k=1
MSB
1
fy[k]g =
m
X
k=1
x[k] LSB
1
fy[m]g + LSB
1
fy[m 1]g (A.4)
Then, repeat the summation process on the equation from m = 1 to n; we have:
n
X
m=1
m
X
k=1
MSB
1
fy[k]g =
n
X
m=1
m
X
k=1
x[k] LSB
1
fy[n]g (A.5)
Taking the LSB
1
fg on both sides of A.5, the explicit expression for quantization
noise of rst-stage DSM e
1
[n] in terms of input signal x[n] can be given by:
e
1
[n] =LSB
1
fy[n]g =LSB
1
(
n
X
m=1
m
X
k=1
x[k]
)
(A.6)
as
LSB
1
(
n
X
m=1
m
X
k=1
MSB
1
fy[k]g
)
= 0 (A.7)
According to A.5 and A.6, the quantization noise of the second stage e
2
[n] is given
by:
e
2
[n] =LSB
2
fz[n]g =LSB
2
(
n
X
m=1
m
X
k=1
MSB
1
fy[k]g
)
=LSB
2
(
n
X
m=1
m
X
k=1
x[k] LSB
1
(
n
X
m=1
m
X
k=1
x[k]
)) (A.8)
181
Since
2
= 2
i
1
as shown in Fig. 4, LSB
1
v will never be larger than LSB
2
v. A
property of LSB
2
can be obtained as:
LSB
2
fv LSB
1
fvgg = LSB
2
fvg LSB
1
fvg (A.9)
Hence,
e
2
[n] = LSB
1
(
n
X
m=1
m
X
k=1
x[k]
)
LSB
2
(
n
X
m=1
m
X
k=1
x[k]
)
(A.10)
182
Abstract (if available)
Abstract
Digital-to-radio frequency (RF) converters with a high dynamic range are key building blocks for all-digital communication systems. For a conventional digital-to-analog converter (DAC), high speed and high dynamic range typically trade off each other. The main emphasis of this thesis is on techniques that enhance the signal bandwidth and dynamic range of DAC conversion. ❧ In the first part of the dissertation, a hybrid DAC architecture is introduced, which achieves both high speed and high linearity. It takes and combines the best of conventional Nyquist and delta–sigma DAC. This architecture benefits from the delta–sigma modulator (DSM) in two main aspects: (1) the DSM reduces analog complexity and leads to a mostly digital design that is highly flexible and favors CMOS technology scaling, and (2) the high-resolution property of the DSM enables advanced digital pre-distortion (DPD) techniques for high-linearity DAC design. Based on the hybrid architecture, bandwidth extension techniques, including unrolled pipeline DSM, DSM-assisted in-band noise cancellation, and successive pipeline bandpass DSM, are proposed and used to overcome the bandwidth limit of the hybrid DAC. To maintain the DAC dynamic range over a wide frequency range, a means of linearizing the DAC based on the DSM is presented. Three prototype DACs with a resolution of 12–16 bits and a sampling rate of 1–12 GS/s are implemented to prove the effectiveness of the hybrid DAC architecture and the techniques developed based on this architecture. ❧ In the second part of the dissertation, a direct-digital radio frequency modulator (DDRM) based on the hybrid DAC and a time-approximation filter (TAF) is discussed, focusing on enhancing the system dynamic range via noise and spur filtering instead of improving the intrinsic linearity of the DAC. The TAF essentially embeds a finite impulse response (FIR) filter in the upconversion of the DDRM via digitally modulating the local oscillator (LO) signal, which makes it highly reconfigurable with a minimum implementation overhead. As both the hybrid DAC and TAF are highly flexible, they are combined to create in-band and/or out-of-band (OOB) spectral notches to support different communication scenarios. With TAF, an experimental prototype DDRM achieves -158 dBc/Hz noise spectral density (NSD) at 100 MHz offset from a 2.4 GHz carrier and -43 dB error vector magnitude (EVM) at 1024 quadrature amplitude modulation (QAM). Without using a surface acoustic wave (SAW) filter, an extension prototype combines a bandpass hybrid DAC and a tri-level TAF and achieves -169 dBc/Hz NSD at 68 MHz offset from a 2.2 GHz carrier, which pushes the envelope of digital transmitters with an output power of more than 15 dBm below the mask requirement of frequency division duplexing (FDD) applications.
Linked assets
University of Southern California Dissertations and Theses
Conceptually similar
PDF
Nonuniform sampling and digital signal processing for analog-to-digital conversion
PDF
Mixed-signal integrated circuits for interference tolerance in wireless receivers and fast frequency hopping
PDF
Wideband low phase-noise RF and mm-wave frequency generation
PDF
A generic spur and interference mitigation platform for next generation digital phase-locked loops
PDF
High power, highly efficient millimeter-wave switching power amplifiers for watt-level high-speed silicon transmitters
PDF
Calibration of digital-to-analog converters in highly-integrated RF transceivers using machine learning
PDF
RF and mm-wave blocker-tolerant reconfigurable receiver front-ends
PDF
Functional connectivity analysis and network identification in the human brain
PDF
Silicon-based wideband & mm-wave power amplifier architectures and implementations
Asset Metadata
Creator
Su, Shiyu
(author)
Core Title
Digital to radio frequency conversion techniques
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
06/10/2020
Defense Date
10/15/2019
Publisher
University of Southern California
(original),
University of Southern California. Libraries
(digital)
Tag
5G,amplitude error,bandpass DSM,calibration,carrier aggregation,data converter,delta-sigma modulator (DSM),digital pre-distortion,digital-to-analog converter,direct-digital RF modulator,electronic design automation (EDA),frequency division duplexing,high-resolution,high-speed,hybrid,noise cancellation,NSD,OAI-PMH Harvest,pipelining,pulse-amplitude modulation (PAM),pulse-position modulation (PPM),pulse-width modulation (PWM),radio frequency (RF),SFDR,time interleaving,time-approximation filter,timing error,unrolling,wireless transmitter
Language
English
Contributor
Electronically uploaded by the author
(provenance)
Advisor
Chen, Mike Shuo-Wei (
committee chair
), Chugg, Keith (
committee member
), El-Damak, Dina (
committee member
), Graham, Nicholas (
committee member
), Hashemi, Hossein (
committee member
)
Creator Email
shiyusu@usc.edu
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-c89-250961
Unique identifier
UC11674776
Identifier
etd-SuShiyu-8053.pdf (filename),usctheses-c89-250961 (legacy record id)
Legacy Identifier
etd-SuShiyu-8053.pdf
Dmrecord
250961
Document Type
Dissertation
Rights
Su, Shiyu
Type
texts
Source
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Access Conditions
The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...
Repository Name
University of Southern California Digital Library
Repository Location
USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA
Tags
5G
amplitude error
bandpass DSM
calibration
carrier aggregation
data converter
delta-sigma modulator (DSM)
digital pre-distortion
digital-to-analog converter
direct-digital RF modulator
electronic design automation (EDA)
frequency division duplexing
high-resolution
high-speed
hybrid
noise cancellation
NSD
pipelining
pulse-amplitude modulation (PAM)
pulse-position modulation (PPM)
pulse-width modulation (PWM)
radio frequency (RF)
SFDR
time interleaving
time-approximation filter
timing error
unrolling
wireless transmitter