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GaN power devices with innovative structures and great performance

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GaN power devices with innovative structures and great performance

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Content GaN Power Devices with Innovative Structures and Great Performance
by
Zhonghao Du
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2023
Copyright 2023 Zhonghao Du

Dedication
To my wife, my family and everyone.
ii

Acknowledgements
Big thanks to everyone, especially to my supervisor Dr.Wang and those who helped me in my research
career and daily life.
iii

Table of Contents
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Band Structures and stability of III-V nitrides . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 The synthesis and implantation of GaN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 GaN power electronics and 2DEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 2: p-GaN/2DEG junction diodes and tri-gate HEMT . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Regrowth and fabrication of p-GaN/2DEG junction . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Mg pre-flow to enhance the incorporation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Comparison of large-area and multi-finger p-GaN/2DEG junction . . . . . . . . . . . . . . 13
2.4 AlGaN/GaN high electron mobility transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 The structure and preparation of JHMET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Transfer characteristics of tri-gate JHEMTs and MISHEMTs . . . . . . . . . . . . . . . . . . 21
Chapter 3: Multi-channel monolithic-cascode HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 Reduced Surface Field (RESURF) technique for power devices . . . . . . . . . . . . . . . . . 26
3.2 Multi-channel monolithic-cascode HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Device simulation and characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 4: First observation of 2DHG and 2DEG coexistence in multichannel AlGaN/GaN
superlattice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 2DEG and 2DHG in AlGaN/GaN heterostructure . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 Five-channel AlGaN/GaN heterostructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 Undoped and n-doped AlGaN/GaN multichannel with RESURF p-GaN . . . . . . . . . . . 43
4.4 C-V measurements under different temperature and frequency . . . . . . . . . . . . . . . . 46
4.5 Conclusions and future plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 5: Thick buried p-GaN activation and applications . . . . . . . . . . . . . . . . . . . . . . 54
5.1 Thick buried p-GaN activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2 Activated acceptor distribution and modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3 Spatial-temporal distribution of activation ratio . . . . . . . . . . . . . . . . . . . . . . . . 58
iv

Chapter 6: Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
v

List of Figures
1.1 The atomic structure and band structures of III-V nitrides . . . . . . . . . . . . . . . . . . . 2
1.2 GaN power electronics and 2DEG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Entire range of power applications that can be addressed with GaN . . . . . . . . . . . . . 8
2.1 Schematics fo lateral p-GaN/2DEG junction . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 SEM top view and cross view of multifinger lateral p-GaN/2DEG junction . . . . . . . . . . 11
2.3 I-V characteristics of quasi-vertical p-n diodes and SIMS . . . . . . . . . . . . . . . . . . . 12
2.4 I-V charateristics of p-GaN/2DEG p-n junction diodes fabricated with two masks . . . . . . 14
2.5 TCAD simulation of E-field and hole/electron concentrations . . . . . . . . . . . . . . . . . 15
2.6 Methods to realize E-Mode HEMTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 Schematics and SEM of tri-gate JHEMTs and MISHEMT . . . . . . . . . . . . . . . . . . . . 19
2.8 Band diagram and transfer measurements of NiO/2DEG diode . . . . . . . . . . . . . . . . 20
2.9 Transfer characteristics of tri-gate JHEMTs and MISHEMTs . . . . . . . . . . . . . . . . . . 21
2.10 Off-state I–V characteristics of JHEMTs and MISHEMTs . . . . . . . . . . . . . . . . . . . . 23
2.11 TCAD simulated distribution of conduction band energy at the two cross sections . . . . . 24
3.1 RESURF technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Schematic layout of a vertical superjunction trench MOSFET . . . . . . . . . . . . . . . . . 28
3.3 Schematics and parameters of MC2
-HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Main steps in device fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
vi

3.5 Top-view SEM and RESURF p-GaN thinning process . . . . . . . . . . . . . . . . . . . . . . 30
3.6 TCAD simulated potential distribution in MC2
-HEMT . . . . . . . . . . . . . . . . . . . . 31
3.7 Transfer characteristics of E-mode and D-mode MC2
-HEMT . . . . . . . . . . . . . . . . . 32
3.8 Benchmark of E-mode GaN MC2
-HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1 Polarization in GaN/AlGaN/GaN sandwich structure . . . . . . . . . . . . . . . . . . . . . 35
4.2 2DEG in AlGaN/GaN/AlN sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 Movements of electrons and holes in Hall measurement . . . . . . . . . . . . . . . . . . . . 37
4.4 Top view and schematics of multichannel heterostructure . . . . . . . . . . . . . . . . . . . 39
4.5 C-V measurement setup and connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.6 Metal-Semiconductor quasi capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.7 C-V at room temperature under different frequency without p-GaN top layer . . . . . . . . 41
4.8 Frozen states within the band gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.9 Schematic and TEM of AlGaN/GaN multichannel with p-GaN top layer . . . . . . . . . . . 44
4.10 Simulated multichannel band diagram and detailed TEM . . . . . . . . . . . . . . . . . . . 45
4.11 Schematic of n-doped multichannel heterostructure . . . . . . . . . . . . . . . . . . . . . . 46
4.12 XRD and Reciprocal Space Map comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.13 Band diagram comparison and simulated carrier concentration under different n-doping
level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.14 C-V profiles in doped and undoped structure from 0V to -30V . . . . . . . . . . . . . . . . 48
4.15 Simulated carrier distributions of electrons and holes under different reverse bias . . . . . 49
4.16 Measured C-V in doped and undoped structure under different temperature and frequency
from -3V to -10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.17 Measured C-V in doped and undoped structure under different temperature and frequency
from -18V to -27V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.18 Larger sample C-V profiles in doped and undoped structure from 0V to -30V . . . . . . . . 51
4.19 Simulated carrier distributions of electrons and holes under V = -140V . . . . . . . . . . . 52
vii

4.20 Reverse recovery test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1 Multiepitaxy and trench filling process flow . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2 Schematic of the epitaxial structure and SIMS . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3 Two process flows of the sidewall and surface activations . . . . . . . . . . . . . . . . . . . 57
5.4 KPFM for sidewall activated p-GaN and accpetor profile . . . . . . . . . . . . . . . . . . . . 58
5.5 Modeled activation ratio versus time in the sidewall-activated p-GaN . . . . . . . . . . . . 59
viii

Abstract
III/V group semiconductors are rejuvenating recently, attracting more attention due to the maturing commercialization of Gallium nitride (GaN). With wide band gap, high carrier mobility and great thermal
stability, GaN devices have applications not only in optoelectronics, but also in power devices and next
generation integrated circuits (ICs). Nowadays, emerging demands for electric vehicles and energy conservation outline the bright future of GaN high power devices.
In 1980s and 1990s, Hiroshi Amano, et al. developed the p-type GaN based blue light-emitting diodes
(LEDs) and were awarded the 2014 Nobel Prize in Physics. Since then, academia and industry shifted their
focus from the optoelectronics in quantum wells to aluminum gallium nitride/gallium nitride (AlGaN/GaN)
2-dimensional electron gas (2DEG), hoping to integrate Ga on Silicon (Si) substrate and apply it with lower
on-resistance (Ron) and higher breakdown voltage (BV). As the lattice mismatch between Si and GaN was
solved by a buffer layer, the selective-area regrowth of p-GaN is still challenging and more innovative
device structures are to be exploited to improve the performance.
Our group, collaborating with others, fabricate a lateral p-GaN/2DEG junction diode to characterize
the regrown quality and transfer characteristics of the sidewall p-n junction under different Magnesium
(Mg) pre-flow conditions. The planar junction offers a significant improvement by adding a Mg pre-flow
before the regrowth to better diffuse Mg atoms beyond the regrowth interface. A 45s Mg pre-flow gives
the best BV. Large-area and trench filling multi-finger p-GaN/2DEG junction diodes are compared and
excellent rectifying behavior with an on/off ratio of over 5 × 107
in both devices are shown. A BV over
ix

100V is demonstrated, where the peak electric field is estimated to be at least 2.5 MV/cm at the sidewall
junction. The results suggest that p-GaN trench-filling regrowth is a viable approach for selective-area
p-type doping in GaN power devices and also support unconventional GaN devices based on p-GaN/2DEG
junctions.
By combining the p-GaN/2DEG junction conception and FinFETs fabrication, we proposed a tri-gate
GaN junction high-electron-mobility transistor (JHEMT), where a p-type nickel oxide (NiO) wraps around
AlGaN/GaN fins. Such tri-gate JHEMT provides a great subthreshold slope (SS) of 63±2mV /decade with
an on-off current ratio of 108
. The depletion region formed by p-type NiO/2DEG junction exhibits a positive threshold voltage (Vth) in addition with a BV > 1500V. Besides, instead of a single AlGaN/GaN channel,
a 5-channel AlGaN/GaN structure was applied to further improve the specifications for power devices. We
design a multi-channel monolithic-cascode HEMT (MC2
-HEMT), integrating an enhancement-mode (Emode) low-voltage (LV) HEMT and a depletion-mode (D-mode) high-voltage (HV) HEMT together. By
doing so, 2DEG density is significantly promoted and the in-series cascode guarantee our MC2
-HEMT is
normally turned off, which subsequently suppress the Ron. Our devices show a BV higher than 10kV as
well as a low specific Ron of 40mΩ·cm2
.
Although the multichannel structure is already widely applied, there are few experimental reports
of the characterizations and physics at the AlGaN/GaN interface, especially for the existence of 2D hole
gas (2DHG). Due to the lattice mismatch between AlGaN and GaN as well Ga-face orientation, spontaneous and piezoelectric polarization effect will induce 2DEG and 2DHG concurrently. However, 2DHG
is more diluted and has a much smaller mobility, making it difficult to detect the existence of 2DHG. We
fabricate two types of multichannel AlGaN/GaN heterostructures, one with unintentionally doped (UID)
AlGaN and another with Si-doped AlGaN. Capacitance-Voltage (C-V) measurement is also performed under different temperatures and frequency. By comparing these two different types of heterostrcutures,
we clearly manifest the 2DHG at the AlGaN/GaN interface since the presence of 2DHG would increase
x

the vertical capacitance level. An extra small stage is observed by high-resolution sampling unit in the
UID heterostructure, indicating the presence of 2DHG. TCAD is used to simulate the carrier concentration
distributed along the depth and confirm the existence of both 2DEG and 2DHG. This work differentiates
the stage caused by 2DHG and peaks induced by surface states. We also discuss the influence of 2DHG
presence on power devices and how to improve their performance.
We investigate the activation mechanism for buried p-GaN by Kelvin probe force microscopy (KPFM)
mapping and C-V characteristics. KPFM profile shows that dopants are activated more near the sidewall.
Spatial carrier distribution is modeled as a function of annealing time.
In conclusion, our work demonstrates GaN power devices as a promising candidate with recordbreaking performance. We investigate the carrier concentration profile in multichannel AlGaN/GaN heterostructures as well as the activation mechanism for buried p-GaN. All these findings solidify GaN’s
unique role in the application of high power management and ICs.
xi

Chapter 1
Introduction
Gallium nitride, a wdie band gap (WBG) semiconductor with 3.4eV, enables high frequency and high power
devices in today’s green energy orientated world. The compound has a Wurtzite crystal structure and
provides an outstanding performance under extreme condition[1, 2]. The large direct band gap of GaN,
along with other III-V nitrides such as aluminium nitride (AlN) and indium nitride (InN), bases the optical
applications of LEDs and lasers in the red, blue and even ultraviolet wavelength[3, 4]. The invention of blue
LEDs was awarded the 2014 Nobel Prize in Physics, which was marked as the peak of researches on these
III-V nitrides and their alloys by engineering quantum well structures[5–7]. The cheap and bright blue
LED made a hit once it was manufactured and replaced the incandescent light bulbs with longer lifetime
and less power consumption.
As the lattice mismatch is overcome by the buffer layer and wafer-scale GaN-on-Si technology is developed, scientists are trying to utilize the thermal stability and high electric field endurance of GaN to
fabricate high power devices[8–13]. In 1993, the first metal semiconductor field effect transistor (MESFET)
based on GaN was produced[14]. Then more and more vertical as well lateral power devices are investigated, among which heterojunction AlGaN/GaN HEMT are the most fascinating one. P-type GaN is also
synthesized by Mg doping[15]. All these previous works above pave the way for GaN to become a charming semiconductor with high power endurance, high frequency switching and low power consumption[16,
1

Figure 1.1: Atomic structure and band structure of III-V nitrides. (a) Wurtzite hexagonal unit cell of III-V
nitrides. The a and c lattice constants are indicated, together with the c-axis direction and the basal c-plane.
(b) Band structure for GaN in the wurtzite structure. (c) Band gap (left) and corresponding wavelength
(right) as a function of lattice constants for wurtzite III-nitrides (yellow symbols) and classical zincblende
III-V semiconductors (blue symbols). The dots indicate a direct band gap semiconductor while the circles
indicate an indirect band gap. Copyright from 2015 EPFL Scientific Publications and 1994 American Physical Society.
17]. While in the future, the revenue of GaN power devices is expected to grow exponentially as 5G and
electric vehicles (EVs) couldn’t be put too much emphasis on[18].
1.1 Band Structures and stability of III-V nitrides
III-V nitrides usually have the wurtzite (hexagonal) structures under ambient conditions, which offer a
excellent robustness against high temperature and high pressure (Figure 1.1(a))[19]. Figure 1.1(b) shows
the calculated band structure of GaN in the wurtzite structure[20]. The calculations were made by the
linear muffin-tin-orbital (LMTO) method in conjunction with the local density approximation (LDA) to
the density-functional theory. As shown in Figure 1.1(b), the calculated GaN band gap between the valence band and conductive band at Γ (Γv−c = 2.64eV ) is smaller than the experimental measured value
(3.4eV)[21, 22]. The reason is that the calculations were performed under the ideal condition, where the
2

c/a ratio and the internal bond-length parameter u were taken ideally without any external potential adjustment. Wurtzite GaN, AlN and InN have a direct band gap of 3.4eV, 6.2eV and 1.9eV determined by the
measurements of absorption edge position, larger than gallium arsenide’s (GaAs) band gap of 1.42eV (Figure 1.1(c)). Benefiting from the direct band gap, III-V nitrides have a better efficiency in photon-electron
conversion and are widely used in the optoelectronic device application. By engineering heterostructures
and quantum wells with III-V nitrides, scientists utilize these alloys to fabricate emitters, lasers and photodetectors that range in broad wavelengths[23]. Meanwhile, WBG and special band structure in these
materials present a high critical electric field as well as a high mobility. The critical electric field for breakdown in GaN is estimated to be 3.3 MV/cm, comparing to 0.2 MV/cm in Si and 0.4 MV/cm in GaAs. A 1300
cm2/V ·s mobility of GaN is high enough to be a substitute of Si[24].
Another attractive properties of III-V nitrides are the thermal conductivity and thermal stability. A
253 ± 8.8W/mK thermal conductivity of GaN at room temperature is comparable to high-temperature
famed silicon carbide (SiC). Over 1200 °C annealing is a common process in the GaN synthesis and implantation and would not degrade the surface. Such thermal robustness is the critical factor for GaN power
devices[25].
1.2 The synthesis and implantation of GaN
The synthesis of GaN is always challenging and have went through a long journey. Bulk GaN crystal
growth requires a high temperature and high pressure solution[26, 27]. Therefore, GaN grown on a foreign
substrate is expected by the scientists to lower down the extreme requirements. Sapphire and SiC are the
desirable candidate substrates for the epitaxy of GaN. In 1969, H. P. Maruska and J. J. Tietjen prepared
GaN by hydride vapor phase epitaxy (HVPE)[22]. And later, the chemical reaction of Ga and hydrogen
chloride (HCl) to form GaCl and ammonia was involved in the process HPVE in 1971[28]. However, the
huge lattice mismatch hinders the quality of GaN layer and generates considerable amount of defects. The
3

breakthrough occurred in 1980s when an AlN buffer layer was applied first over the substrate and then
GaN was grown on this buffer layer with high quality and smooth surface by Molecular-beam epitaxy
(MBE) and metalorganic vapor phase epitaxy (MOVPE)[29–31]. And recently, metal organic chemical
vapor deposition (MOCVD) is a more economic way to synthesis GaN films[32]. Trimethylgallium (TMGa)
as Ga source and NH3 gas as N source are supplied to the chamber, followed by a high temperature, which
evolved as a leading technique to produce GaN films. With the maturation of GaN growth and the use of
buffer layer, more efforts are devoted to integrating GaN with Si since Ga-on-Si have unrivalled advantages
in high voltage classes over 600V and in commercial cost-effectiveness. Although still in the early stage,
wafer-scale Ga-on-Si fabrication is promising and perspective for a expanding market[33].
Another important task for the application of GaN is to realize p-type GaN growth. As it is quite easy
and efficient to n-dope GaN by incorporating Si or other group-VI elements during the synthesis, high ntype doping can be easily achieved[34]. However, there used to be a theory that self-compensation would
make it impossible to grow p-type GaN because the same number of intrinsic donors such as nitrogen
vacancies would be generated to compensate for the doped acceptors[35]. Typical Group-II metal elements
such as Zinc (Zn) and Mg are supposed to substitute Ga atoms as acceptors. But the ionization of Mg
is hard to realize in the room temperature, which retards the activation of p-type GaN. It is found that
hydrogen (H) plays a crucial role in passivating Mg acceptors. During the implantation process, a Mg-H
complex is formed and it would reduce the hole concentration by almost an order of magnitude[36]. Noble
Laureates Isamu Akasaki, Hiroshi Amano and Shuji Nakamura found that the low-energy electron beam
could damage the bond of Mg-H complex and thermal annealing above 700°C could also dehydrogenate pdoped GaN to increase hole carrier concentration significantly to 3×1017cm−2
and decrease the resistivity
by 6 orders[37, 38]. Such achievements made a huge impact on the applications of GaN power devices,
LEDs and photodetectors based on GaN p-n junctions[39, 40].
4

Selective area p-GaN regrowth is the next problem that the academia try to solve. Lateral epitaxial
overgrowth (LEO) technique was employed by H. Marchand to grow GaN on a certain etched area[41]. A
layer of amorphous SiO2 or Si3N4 mask would be first deposited by plasma-enhanced chemical vapor
deposition (PECVD) over the underlying GaN film. And then a selective area of mask would be etched
through, followed by GaN regrowth. The regrown second layer of GaN could only be deposited on the
etched selective area since there is no "seed" over the other parts of the mask[42–44]. Thermal annealing
to activate hole carriers is still required and could get a high quality regrown layer with low density of
defects. Despite the high-concentration acceptors and a succint process of p-GaN activation, impurities
and etch damages involved by the etch, PECVD and regrowth would import challenges for forming a high
quality junctions at the trench bottoms and sidewalls. This is what my work focuses and will be elaborated
later.
1.3 GaN power electronics and 2DEG
It is by standing upon the shoulders of giants that we witnessed the enormous development of GaN synthesis and applications over the last several decades. Si-based electronics have been providing solutions for
power devices, like MOSFETs, IGBTs, SJTs, BJTs and thyristors. However, GaN-based devices with higher
critical electric field (Ec) and lower specific Ron are being more and more emphasized on as promising
candidates in high power devices beyond Si roadmap.
Vertical GaN devices could increase the blocking voltage by increasing the thickness of the drift region without sacrificing device’s lateral sizing. Therefore, vertical GaN-based power devices with simple
structures and manufacturability are able to reach BV over 1kV easily and have high-speed switching. First
vertical GaN p-n junction diode, whose BV > 1kV and Ron ∼ 1.2mΩ·cm2
, was reported in 2010 and new
records are continuously presented over 2kV and then 4kV(Figure 1.2(a))[45–48]. For those p-n junction
diodes, a 2−6µm thickness N − doped GaN drift layer (typically ND ≈ 1×1016cm−3
) is homoepitaxially
5

Figure 1.2: (a) Schematic cross-sectional view of the vertical GaN p-n diode on bulk GaN. (b) Schematic
diagram of GaN-based current aperture vertical electron transistor (CAVET). (c) Conduction band structure of a modulation-doped structure. (d) Contours of constant Baliga figure-of-merit (BFOM) for various
conventional, WBG and UWBG semiconductors, drawn on a log-log specific on-resistance versus breakdown voltage plot. Copyright from 2013 IEEE, 2004 American Institute of Physics, 2000 Elsevier Science
and 2017 WILEY.
grown on the free-standing GaN substrate. Another much thinner Mg-doped p-GaN layer, usually below
1µm, is subsequently deposited on the drift layer. The low-doped n-GaN drift layer with large thickness
could not only better manage high reverse voltage evenly along the vertical dimension, but could suppress
the peak electric field at the p-n interface as well. Metal anodes and cathodes are both Ohmic contacts.
Instead of employing Ohmic electrodes, vertical Schottky barrier diodes (SBDs) apply a Schottky electrode
on the drift region to rectify the current and don’t have a p-GaN layer. Low Ron and high BV are also
reported in SBDs[49]. Another main vertical GaN device is current aperture vertical electron transistor
(CAVET)(Figure 1.2(b))[50]. The 2DEG at the AlGaN/GaN heterointerface is the source of electron carriers
(the formation of 2DEG will be introduced later in this sector) and a narrow aperture that is filled with conducting material is sandwiched by insulating layer. The 2DEG will flow through the aperture to the drain
6

and controlled by a Schottky gate, located right above the aperture. CAVETs also demonstrate great performance but they are normally-on devices with negative Vth due to the existence of 2DEG[51]. There are
ample amounts of vertical GaN-based devices, like vertical FinFETs, double-diffused MOS (DMOS) and et
al[52]. All these vertical devices show great performance on Baliga’s figure of merit (F OM = BV 2/Ron).
Furthermore, the gradual advancement of GaN epitaxy on foreign substrate could greatly trim the cost and
enable wafer-scale processing while maintaining the performance of vertical GaN-based devices[53].
Given the mentioned benefits from vertical power devices, lateral electronics are yet overshadowed as
their compatibility with mostly lateral Si-based ICs and performance records being pushed by the whole
circle. 2DEG at the AlGaN/GaN interface is the fundamental to lateral GaN-based devices with high electron mobility. As mentioned above, a triangle quantum well is formed due to the band structure discontinuity at the interface between the large band gap AlGaN and the smaller band gap GaN (Figure 1.2(c))[24].
Electrons diffusing from AlGaN will move freely in this two-dimensional quantum well and thus have a low
sheet resistance (Rsh). This 2DEG will be further enhanced by piezoelectric and spontaneous polarization
effects in AlGaN/GaN heterostructures[54]. The 2DEG is located at the Ga-faced interface where AlGaN is
deposited over GaN, while the 2DEG is also located at the N-faced interface where GaN is grown on top of
AlGaN, indicating a spontaneous polarization (PSP ). The lattice mismatch between AlxGa1−xN and GaN
causes the tensile strain and results in the piezoelectric polarization (PP E). Hall-effect measurements and
C-V profiling clearly manifest that spontaneous and piezoelectric polarization of the GaN channel and the
AlGaN barrier play an important role in the formation of 2DEG. This PP E in addition with PSP equals to
the net total polarization (P(x)):
P(x) = Psp + Ppz = [(14.1x + 4.9x
2
) × 10−6 − (0.3 × 10−6
)x]C/cm2
,
7

Figure 1.3: An overview of power applications that can be addressed with GaN. Copyright from 2013 IOP
Publishing Ltd.
where x is the Al-content mole fraction in the AlxGa1−xN alloy. And the sheet carrier concentration of the 2DEG is increased from 6 × 1012cm−2
to 2 × 1013cm−2
if the Al-content is increased from
x = 0.15 to 0.31 in the alloy. The electron mobility over 2000 cm2/V ·s provides low Ron and high frequency operation in radio frequency (RF) devices. My research mainly focuses on the lateral GaN power
electronics exploiting 2DEG, trying to design, fabricate, characterize and analyze brand new power devices
with innovative structures (Figure 1.2(d))[55].
Today, human beings gradually realize that the only way to be entitled to a sustainable development
is to have environmental friendly world. Green power and electricity outweigh any other issues. The
commercialization of the low-cost GaN-based electronics with high working voltages and low dissipation
will power the large-scale applications of EV as well as ultra-high-voltage electricity transmission in the
electricity grids. The micron sized GaN power devices have the potential to leverage a new era (Figure
1.3)[56].
8

Chapter 2
p-GaN/2DEG junction diodes and tri-gate HEMT
Since the advances in the p-GaN doping and activation, devices with p-type GaN are emerging and greatly
expand the applications of GaN power electronics by forming p-n heterostructures[57, 58]. However, most
patterned p-GaN areas in those works are following the grow-and-etch principle while selective p-GaN
regrowth technique is required for high quality lateral p-n junctions in building blocks for high-voltage
Si and SiC power devices (Figure 2.1(a))[59, 60]. As mentioned above, the impurity incorporation and
etch damage at the regrowth interfaces jeopardize the quality of p-n junctions at the trench bottoms and
sidewalls. Although Liu et al. used p-GaN regrowth layer on mesa structures to characterize the Mgdoped concentration at the side wall, there is still the lack of a method to directly characterize the sidewall
junction performances after a selective area GaN regrowth[61]. In this work, we propose to fabricate a pGaN/2DEG junction diode to measure the current-conduction and voltage-blocking characteristics of the
regrown sidewall p-n junction. Unlike previous work which has revealed interesting physical properties
of 2D in-plane p-n diodes formed between the 2DHG and 2DEG, the new 3D/2D p-n junction in our work
demonstrates a different method to deplete a region and to gate control the drift 2DEG layer in transistors
(I will discuss this potential in the following chapter)[62–64].
9

Figure 2.1: Schematics of the (a)selective-area p-GaN trench-filling regrowth desired in GaN power devices
and (b) proposed p-GaN/2DEG junction diodes in this work. 3D schematics of (c) large-area and (d) multifinger p-GaN/2DEG junction diodes fabricated in this work.
2.1 Regrowth and fabrication of p-GaN/2DEG junction
As shown in Figure 2.1(b), a 4µm buffer layer is grown on a 6-inch Si (111) substrate, followed by an i-GaN
layer and a 22.1nm Al0.24Ga0.76N layer to form the 2DEG. Then a 3.3nm GaN cap layer and a 10.3nm in situ
SiNx dielectric layer are epitaxially deposited subsequently. All layers are grown by MOCVD. The 2DEG
density and Rsh are 7 × 1012cm−2
and 490Ω/sq. Two p-GaN/2DEG junction diodes are fabricated in this
work with different geometries for p-GaN trenches. The diode shown in Figure 2.1(c) has a rectangular
trench with a relatively large area of 25 × 100µm2
. The diode shown in Figure 2.1(d) has multi-finger
trenches with both the finger width and finger spacing of 1µm. This multi-finger diode is used to evaluate
the regrown p-GaN in narrow trenches. Any narrow trench without activated p-doping would result in
low forward current and premature punch-through breakdown.
The whole fabrication process is described below. Two dielectric masks are used and compared for
p-GaN regrowth, one purely of a in situ SiNx layer and another one of a 30nm PECVD SiO2 deposited on
10

Figure 2.2: (a) Top-view and (b) cross-sectional SEM images of the fabricated multi-finger diodes.
top of SiNx. Nickel (Ni) metal is patterned on dielectrics as the hard mask, followed by 400nm GaN etch in
an ICP-RIE system to form the trenches. The next step is to remove Ni by wet etch and a treatment in 5%
tetramethylammonium hydroxide (TMAH) for 20min at 70°C to remove the surface etch damage at the
GaN trench sidewalls and around the trench corners[65]. The samples are then loaded into the MOCVD
chamber for p-GaN regrowth. Mg-concentration in GaN is controlled by the flow rate of biscyclopentadienyl magnesium (Cp2Mg) as the Mg gas source and usually Cp2Mg gas is served synchronously with Ga
source gas [39, 66].
2.2 Mg pre-flow to enhance the incorporation
Here, we try to enhance the Mg incorporation at the start of p-GaN growth by supplying Mg pre-flow
(Cp2Mg) before switching on the Ga source (TMGa). Four regrowth processes with no Mg pre-flow and
three Mg pre-flow times (0s, 35s, 45s and 55s) are performed and high temperature activation at 950°C
in pure N2 is done. The top-view and cross-sectional scanning electron microscopy (SEM) images of the
regrown p-GaN are shown in Figures 2.2(a) and 2.2(b). The p-GaN regrowth using both SiNx and SiO2
masks shows a full-coalesced void-free filling in the trenches of different sizes. After the p-GaN regrowth,
11

Figure 2.3: (a) Schematic of the quasi-vertical p-n diodes fabricated on the GaN-on-sapphire control samples. (b) Typical forward and reverse I–V characteristics of the p-n diodes fabricated on the samples without
and with 30 s, 45 s, and 55 s Mg pre-flow. (c) SIMS profile of [Mg] and [Si] near the regrown junction in
the samples with and without 45 s Mg pre-flow. (d) SIMS profile of [H], [O], [C], [Si], and [Mg] near the
regrown junction in the samples with 45 s Mg pre-flow.
the samples were soaked in 5% TMAH at 70°C for 3h to planarize the overgrown p-GaN and to removed
the local super-elevations near the edges of dielectric masks[67, 68]. The following device fabrication steps
include the mesa etch and the formation of Ohmic contacts. A Pd/Ni/Au metal stack is used to form the
anode on p-GaN and a Ti/Al/Ni/Au stack for the cathode on AlGaN/GaN[69, 70].
We use control samples on sapphire substrates to monitor the p-GaN regrowth quality and characterize the transport properties as well as the impurity concentration. Control samples are loaded into the
MOCVD chamber together with the large-area and multi-finger samples during each p-GaN growth. These
control samples are placed in air for days before regrowth to simulate the introduction of interfacial impurities during the sample transfer that has been widely reported[40, 71]. Quasi-vertical GaN p-n diodes are
fabricated as the control sample with a mesa depth of 500nm (Figure 2.3(a)). The Hall measurements reveal the hole concentration and mobility of the regrown p-GaN to be ∼ 4 × 1017cm−3
and ∼ 10cm2/V ·s,
12

respectively. Faint blue light emission is observed under the forward bias, which indicates the high quality
of the regrown planar p-n junctions. Figure 2.3(b) shows the I-V curves of the quasi-vertical p-n diodes
with different pre-Mg flow times under forward bias and reverse bias. The devices with pre-Mg flow show
higher forward turn-on voltage (Von) and lower reverse leakage current compared to the device without
pre-Mg flow, suggesting an improved junction quality. The sample with 45s Mg pre-flow demonstrates the
best I-V characteristics, featured by a over 200V BV and 2V Von. This sample also has a ∼ 1.3 extracted ideality factor (η), indicating a combination of the ideal diffusion current (η ∼ 1) and the Shockley–Read–Hall
(SRH) dominant recombination currents in the space-charge region (η ∼ 2)[72, 73]. This is consistent with
the reported η in regrown planar p-n diodes and GaN p-n diodes on foreign substrates[74].
Figures 2.3(c) and 2.3(d) show the concentrations of [Mg], [Si], [H], [O] and [C] in the regrown p-n
structures with 45s and without Mg pre-flow, measured by secondary ion mass spectrometry (SIMS). A
[Si] concentration spike up to 1018cm−3
at the interface is often owing to the contamination during the
device transfer. Mg pre-flow nearly expand 30nm diffusion depth beyond the regrowth interface and also
increase the [Mg] concentration. In Figure 2.3(d), [Mg] is significantly higher than [H] across the whole
p-n junction, indicating a successful activation of Mg-dopant and a breakdown of the Mg-H complex.
With the 45s Mg pre-flow, our work demonstrated the highest ratio between [Mg] and the peak impurity
concentration at the regrowth interface[40, 71]. This Mg diffusion effect can explain the improved p-n
diode performance in the samples with Mg pre-flow compared to the one without.
2.3 Comparison of large-area and multi-finger p-GaN/2DEG junction
The best regrowth condition with 45s Mg pre-flow is then used for selective-area p-GaN regrowth in AlGaN/GaN. First, diodes fabricated with the PECVD SiO2 mask and the in situ SiNx mask are characterised
and compared (Figure 2.4(a) and (b)). The current density in both diodes is normalized with respect to the
cathode width. The diode with SiNx mask has a higher ideality factor, a lower Von and higher leakage
13

Figure 2.4: (a) Forward and (b) reverse I–V characteristics of the large-area p-GaN/2DEG p-n junction
diodes fabricated with the SiO2 and SiNx masks. (c) Forward I–V characteristics, ideality factor, and (d)
reverse I–V characteristics of the large- area and multi-finger diodes fabricated with the SiO2 mask. Over
10 reverse I–V curves are plotted for each type of device to show the statistical significance.
current under the reverse bias, which are often attributed to the impurity or defects at the regrowth interface[71]. As [Si] is the main impurity at the regrowth interface, these results suggest a much stronger
decomposition of the SiNx mask compared to the SiO2 during the p-GaN regrowth.
Figures 2.4(c) and (d) show the I–V characteristics of the large-area and multi-finger (1µm trench) pGaN/2DEG junction diodes fabricated with SiO2 mask. Both devices show an excellent rectifying behavior
with an on/off ratio of over 5 × 107
. In Figure 2.4(c), multi-finger diode demonstrates a higher forward
current density as well as a larger Von, which could be all explained by a larger junction density in the
multi-finger diode. The deep-level donor-like traps related to the impurities and defects at the regrown
junction will result in a fixed positive charges and consequently will lower the turn-on voltage of the multifinger diode. As calculated in the inset of Figure 2.4(c), both types of devices’ ideality factors are around
1.3–1.5 when the forward bias is small. This behavior is similar to that of planar regrown junctions and
14

Figure 2.5: Simulated distribution of the E-field and hole/electron concentrations in the p-GaN/2DEG junction region with NA = 1018cm−3
.
indicates a combination of diffusion current and SRH recombination current[72]. As shown in Fig. 2.4(d),
the large-area and multi-finger device show a destructive BV of ∼ 120V and ∼ 80V respectively, with a
leakage current of ∼ 10−2A/mm before BV. Before the breakdown, both types of devices behave similarly
and have almost the same leakage current density. This suggests that the 1µm trenches in multi-finger
devices are not fully depleted across the reverse biases up to the device breakdown.
We also simulate the distribution of carriers and electrical field at -100V based on the TCAD models calibrated with HEMTs (Figure 2.5)[75]. As the sidewall [Mg] is difficult to characterize experimentally, we simulate several values ranging from 1017cm−3
to 1019cm−3
for the average ionized acceptor
concentrations (NA ≈ [Mg] − [H]) at the sidewall. The peak junction E-field reaches 3.5MV/cm when
NA = 1018cm−3
. We estimate the sidewall average NA to be at least 1017cm−3
. Otherwise, the 1µm
15

trench will be fully depleted in multi-finger diodes at low reverse biases based on our simulation of multifinger diodes. This suggests that our regrown p-GaN sidewall p-n junction can at least sustain a high
E-field over 2.5MV/cm.
In summary, this work demonstrates the lateral p-GaN/2DEG junction diodes by selective-area p-GaN
regrowth in AlGaN/GaN trenches with different fabrication process and different shapes. A 45s Mg preflow improves the junction characteristics most as a record high ratio between [Mg] and the maximum
impurity spike is achieved at the planar regrown interface. Excellent rectifying behavior is demonstrated
in large-area and multi-finger p-GaN/2DEG junction diodes, suggesting good sidewall junction quality and
the p-type doping into 1µm trenches. Over 100V BV and at least 2.5MV/cm peak junction E-field enable
great potential for selective-area p-GaN trench-filling regrowth for the applications of GaN power devices.
I will introduce another JHEMT device based on this p-type/2DEG junction in the next section.
2.4 AlGaN/GaN high electron mobility transistor
The AlGaN/GaN HEMT is gaining increased adoption in RF and power applications, owing to the high critical field of 3.3 MV/cm and the high electron mobility in 2DEG of 2000 cm2/V ·s. As 2DEG channel is formed
and usually could not be pinched off by the gate, initial research have focused on the depletion-mode (Dmode) devices that are naturally offered in conventional Ga-face C-plane epitaxial wafers and D-mode
transistors are normally-on devices with a negative Vth[76]. However, normally-off enhancement-mode
(E-mode) HEMTs and metal- insulator-semiconductor HEMTs (MISHEMTs) are superior in the applications of RF/microwave circuits and power devices for its elimination of negative-polarity power supply
and power switches[77–79].
There are several methods, to name a few, tuning the negative Vth to the positive one. Fluorine plasma
ion implantation is one way to passivate the positive charges at the interface of semiconductors and dielectric layers (Figure 2.6(a))[80]. The plasma-treated structure has its 2DEG channel’s conduction-band
16

Need Enabling Feature Performance Advantage
High Power/Unit Width Wide Bandgap, High Field Compact, Ease of Matching
High Voltage Operation High Breakdown Field Eliminate/Reduce Step Down
High Linearity
High Frequency
HEMT Topology
High Electron Velocity
Optimum Band Allocation
Bandwidth u-Wave/mm-Wave
High Efficiency High Operating Voltage Power Saving, Reduced Cooling
Low Noise
High Temperature Operation
High Gain, High Velocity,
Wide Band Gap
High Dynamic Range Receivers
Rugged, Reliable, Reduced Cooling
Thermal Management SiC Substrate High Power Devices with Reduced
Cooling Needs
Technology Leverage Direct Band Gap:
Enable for Lighting
Driving Force for Technology:
Low Cost
Table 2.1: Competitive Advantages of GaN Devices. Copyright from IEEE.
Figure 2.6: (a) Schematic of the fabricated E-mode MOS-HEMT by fluorine plasma treatment. (b) Gaterecessed E-Mode HEMT with interrupted 2DEG under the gate due to a thinned AlGaN barrier. (c)
Schematic cross-sectional structure of p-GaN gate HEMTs. Copyright from 2013 AIP Publishing LLC,
2009 The Japan Society of Applied Physics and 2013 IEEE.
minimum above Fermi level and causes an upward bending of the conduction band indicating a completely
depleted channel and E-mode operation[81]. Recessed gate technology also provides a way to interrupt
the 2DEG channel under the gate area and could only be turned on when Vth > 0 (Figure 2.6(b))[82–84].
RIE-ICP etching will reduce the thickness of AlGaN layer and thus gate-recessed devices require more
electrons induced by the positive gate voltage[85, 86]. Another way to achieve an E-mode device would
be using p-type GaN cap layer on top of the AlGaN/GaN heterostructure to perform band engineering and
suppress the zero-bias 2DEG (Figure 2.6(c)). The p-GaN cap layer lifts the Fermi level and totally depletes
the 2DEG if there is no positive gate voltage applied[87–90]. All these three methods mentioned above
17

(fluorine plasma treatment, gate recess structure and p-GaN gate) realize the E-mode HEMTs fabrication
and commercialize E-mode electronics with great performance.
While commercial three-dimensional (3D) FinFET/tri-gate technology has already been widely used in
advanced ICs in TSMC and Samsung, such structure has just recently implemented in GaN HEMTs[91, 92].
The GaN FinFETs and tri-gate HEMTs enabled a superior on-off current ratio, SS, linearity, and transconductance (gm)[52, 93, 94]. Despite these early demonstrations, tri-gate HEMTs still face several challenges
in realizing E-mode operation. Specifically, E-mode in high-voltage transistors requires not only a positive
Vth but also the capability to block high drain voltage at zero gate bias (VG)[95]. The high 2DEG density
typically necessitates a fin width below 30nm for full 2DEG depletion and it often induces drain-inducedbarrier-lowing (DIBL)[96, 97].
In this section, we propose a significantly distinct tri-gate device concept, JHEMT. While all existing
GaN FinFETs and tri-gate HEMTs employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack,
the tri-gate JHEMT relies on the p–n junction wrapping around the AlGaN/GaN fin (Figure 2.7(a)).
2.5 The structure and preparation of JHMET
The p–n junction can offer stronger depletion than the MIS structure owing to a larger built-in potential
(Vbi) and the obviation of voltage drop in the insulating dielectrics, thereby making it easier to realize the
E-mode operation, suppress the DIBL, and prevent the punch- through. It also eliminates the MIS inversion
charges at the fin sidewalls and trench bottoms, thereby reducing the gate charge and the parasitic conduction along the sidewall channels[98]. Compared to the planar p-gate HEMT, such as the gate injection
transistor (GIT), the tri-gate JHEMT offers stronger depletion and gate control over channel electrostatics. While p-GaN is a natural p-type material for the proposed tri-gate JHEMT, sub-micron selective-area
p-type doping is still not viable in GaN. As an alternative, we demonstrate a GaN tri-gate JHEMT using
NiO, a p-type oxide that possesses a high hole concentration and can form high-quality heterojunctions on
18

Figure 2.7: (a) Schematic of the tri-gate GaN MISHEMT and tri-gate GaN JHEMT. (b) SEM image of the
fins before and after the NiO sputtering. (c) I–V curve between two Hall Ni pads on p-NiO, showing a good
Ohmic contact.
AlGaN/GaN, with a relatively large Vbi (1–1.5 eV). In addition, NiO can be sputtered at room temperature,
which simplifies the junction tri-gate fabrication.
The epitaxial structure consists of 10nm in situ SiNx, 3nm GaN, 22 nm Al0.25Ga0.75N, 420nm iGaN, and a buffer layer, all grown on a 6-inch Si substrate by MOCVD. The 2DEG density and Rsh are
8.5 × 1012cm−2
and 480Ω/sq, respectively. As shown in Figure 2.7(a), the tri-gate GaN MISHEMTs and
JHEMTs are fabricated on the same wafer with the fin width (WF in) ranging from 40nm to 120nm. A
relatively large fin spacing (SF in) of 150nm is chosen to allow the fabrication of tri-gate JHEMTs with
different NiO thicknesses, which is critical toward understanding the physics of tri-gate JHEMTs. The fin
length (LF in) varies from 200nm to 1µm and the gate length (LG) is fixed at 2µm. The gate-to-source
distance (LGS) is 2µm, and the gate-to-drain distance (LGS) varies from 6µm to 21µm.
A self-aligned process is used to lift off the NiO and gate metal in the same lithography step[99]. NiO
is deposited in a magnetron sputtering system using a NiO target. Figure 2.7(b) shows the SEM images of
19

Figure 2.8: (a) Band diagram of the NiO/GaN/AlGaN/GaN structure. (b) Schematic and (c) I–V characteristics of the fabricated NiO/2DEG junction diode.
the GaN fins before and after NiO sputtering, verifying the conformal NiO coverage. Three samples with
planar NiO thicknesses of 50nm, 100nm, and 150nm are fabricated. The sidewall sputtering rate is found
to be ∼1/3 of the planar rate. In the 50nm and 100nm samples, NiO fills the inter-fin trenches to the levels
below the 2DEG; in the 150nm sample, NiO fully fills the trenches. A Ni/Au stack is used for the gate,
which forms an Ohmic contact to NiO. Figure 2.7(c) shows the Hall measurements for the Ni pads on NiO
using the van der Pauw method. A hole concentration and mobility of 5 × 1019cm−3
and 0.7cm2/V ·s
are extracted for the sputtered p-NiO, respectively. For the tri-gate MISHEMTs, 15nm Al2O3 is deposited
by atomic layer deposition at 275 °C as the gate dielectric and the same Ni/Au is used for the gate metal.
PECVD SiNx is deposited for the passivation of both tri-gate JHEMTs and tri-gate MISHEMTs.
Figure 2.8(a) shows the simulated band diagram of the NiO/GaN/AlGaN/GaN stack using the material
properties of sputtered NiO, which predicts a Vbi value of 1.2–1.3 eV between 2DEG and p-NiO[100]. To
measure the Vbi value experimentally, a NiO/2DEG p–n junction diode is fabricated, where the sputtered pNiO forms contact with 2DEG at a mesa sidewall (Figure 2.8(b)). Figure 2.8(c) shows the I–V characteristics
of this NiO/2DEG diode. The current starts to increase at ∼1.3V , which verifies the simulated Vbi.
20

Figure 2.9: Transfer characteristics of (a) tri-gate JHEMTs with various NiO thicknesses, (b) tri-gate
JHEMTs (solid lines) and tri-gate MISHEMTs (dashed lines) with 60 nm WFin (ID in black, IG in blue,
and gm in red), and (c) the two types of tri-gate devices with different WF in values. (d) Output characteristics of 60nm tri-gate JHEMTs (solid lines) and 40nm tri-gate MISHEMTs (dashed lines).
2.6 Transfer characteristics of tri-gate JHEMTs and MISHEMTs
Figure 2.9(a) shows the transfer characteristics (VDS = 0.25V , linear region) of the tri-gate JHEMTs with
planar NiO thicknesses of 50nm, 100nm, and 150nm. The current density of all transistors in this work is
normalized by the total gate width (50µm). Due to a smaller sidewall sputtering rate, the 50nm-NiO trigate JHEMT has thin (<16 nm) and even incomplete sidewall coverage, leading to higher leakage current
and higher SS. When NiO is thicker and the sidewall is completely covered, the junction depletion occurs
due to the high hole concentration in NiO, leading to a Vth value that is independent of the NiO thickness.
This is validated by the almost identical transfer characteristics of the tri-gate JHEMTs with 100nm and
150nm NiO (Figure 2.9(a)). Note that this behavior is different from the tri-gate MISHEMT, wherein Vth
strongly depends on the thickness and capacitance of the insulating dielectrics. This difference reflects the
inherent benefits of the junction gate in eliminating the voltage drop in the gate dielectric. The tri-gate
JHEMTs with 100nm and 150nm NiO show a minimum SS of 63±2mV /decade with an on-off current ratio
21

of ∼ 108
. For clarity, the devices discussed through the remainder of this work all have a NiO thickness of
100nm.
Figure 2.9(b) shows the double-sweep transfer characteristics (VDS = 5V , saturation region) of the
tri-gate JHEMTs and MISHEMTs with 60nm WF in. The tri-gate JHEMT has a Vth value of 0.45V and
a hysteresis below 0.1 V, while the tri-gate MISHEMTs show a negative Vth and ∼ 0.6V hysteresis. The
close-to-60mV/decade SS and small hysteresis in tri-gate JHEMTs suggest a very small interface state (Dit)
in the NiO-based junction gate, whereas the larger SS (minimum 70 ± 5mV /decade) and hysteresis in the
tri-gate MISHEMTs suggest a higher Dit on the interface of Al2O3/GaN. The gate leakage current (IG)in
tri-gate JHEMTs is very low at VG < 1V and starts to increase when VG exceeds the Vbi value between
NiO and 2DEG.
Figure 2.9(c) shows the WF in-dependent transfer characteristics of the tri-gate MISHEMT and JHEMT,
where Vth increases with a decreased WF in in both types of devices. Tri-gate JHEMTs show a 1–1.5V
higher Vth than the tri-gate MISHEMTs with the same WF in, validating the stronger 2DEG depletion in
the junction tri-gate. The tri-gate MISHEMT starts to see a positive Vth at 40nm WF in, while the tri-gate
JHEMT does at 60nm WF in. The 40nm tri-gate JHEMT shows a Vth value of 1.1 V. Vth in future tri-gate
JHEMTs can be further increased by either using the p–n junctions with higher Vbi or the barrier structures
allowing more pronounced strain relaxation in narrow fins. Figure 2.9(d) shows the output characteristics
of the 60nm tri-gate JHEMTs and 40nm tri-gate MISHEMTs at a similar Vth value. The higher current
density in the tri-gate JHEMT is mainly due to the larger gate area available for current conduction, i.e.,
filling factor (FF) = WF in/(WF in + SF in). The FF is 0.28 for 60nm tri-gate JHEMTs and 0.21 for 40nm
tri-gate MISHEMTs. The E-mode 60nm tri-gate JHEMT shows Ron of 9.42Ω·mm.
The leakage and BV in high-voltage FinFETs are usually determined by both the E-field management
and the potential barrier in the fin (ΨF in). When ΨF in is high, the drain leakage current is low and the BV
is E-field limited; otherwise, punch-through will occur due to DIBL. ΨF in in a fin gate generally decreases
22

Figure 2.10: Off-state I–V characteristics of (a) 60nm tri-gate JHEMTs with various LGD values at 0V VG,
(b) 40nm tri-gate MISHEMTs with various LGD values at 0V VG (ID in blue solid lines and IG in blue
dashed lines) and -2V VG (ID in black solid lines and IG in red dashed lines), as well as (c) 60nm tri-gate
JHEMTs and (d) 40nm tri-gate MISHEMTs with various LF in values at 0V VG (ID in solid lines and IG in
dashed lines).
with increased WF in, reduced LF in, and more positive VG[95]. Figure 2.10(a) shows the off-state I–V
characteristics of the 60nm tri-gate JHEMT with various LGD values. The ID value is ∼ 107A/mm and
BV scales with LGD at zero VG, suggesting a high ΨF in up to >2000V VD. Figure 2.10(b) shows the offstate I–V characteristics of the 40nm tri-gate MISHEMTs at VG values of 0V and -2V. At a VG = −2V ,
their leakage and BV are similar to those of the 60nm tri-gate JHEMTs. However, at zero VG, the leakage
current increases by at least 103
-fold and the BV is significantly compromised, due to punch-through.
This suggests an intrinsically lower ΨF in in the MIS tri-gate as compared to the junction tri-gate. Figures
2.10(c) and 2.10(d) show the off-state I–V characteristics of the 60nm tri-gate JHEMTs and 40nm tri-gate
MISHEMTs with various LF in values at zero VG. The 60nm tri-gate JHEMT maintains low leakage current
and >2000V BV when LF in is reduced to 200nm. In contrast, the tri-gate 40nm MISHEMT shows punchthrough at 200nm and 500nm LF in and can only realize the high BV with 1µm LF in. These results suggest
23

Figure 2.11: (a) Illustration of the positions of the side-view and top-view cross sections. Simulated distribution of conduction band energy at the two cross sections in (b) 40nm tri-gate MISHEMTs and (c) 60nm
tri-gate JHEMTs with 500nm LF in at VG = 0V and VDS = 1000V .
the gate scaling capability of tri-gate JHEMTs, which would bring performance advancement in all power,
RF, and digital HEMTs.
To further understand the leakage current in tri-gate HEMTs, physics-based 3D device TCAD simulation is performed in Silvaco Atlas, based on similar models previously developed for GaN FinFETs[95].
The 2DEG density in miniaturized fins is determined via calibration using experimental I–V characteristics. As illustrated in Figure 2.11(a), the simulated conduction band energy is extracted at a side-view fin
cross section and a top-view cross section on the 2DEG plane for 40nm tri-gate MISHEMTs (Figure 2.11(b))
and 60nm tri-gate JHEMTs (Figure 2.11(c)) with 500nm LF in, at both 0V VG and 1000V VDS. The lowest
ΨF in in the tri-gate fin channel is found to be at the 2DEG in the middle of the fin. ΨF in is below 0.1eV
in the 40nm tri-gate MISHEMTs, but above 0.55eV in the 60nm tri-gate JHEMTs. This explains the higher
leakage current and punch-through observed in the 40nm tri-gate MISHEMTs at zero VG.
24

In summary, we propose the tri-gate GaN JHEMT concept, which differs from all existing tri-gate GaN
MISHEMTs, and demonstrate it using a p-type NiO and Ohmic gate contact. The tri-gate GaN JHEMTs
show a nearly 60mV/decade SS and minimal hysteresis, suggesting low Dit. They exhibit higher Vth than
tri-gate GaN MISHEMTs, achieve the E-mode operation without additional gate recess and demonstrate
over 2kV BV at zero VG and scaled LF in, which all illustrate the stronger electrostatic control in the
junction tri-gate compared to the MIS tri-gate. These results show the great potential of tri-gate GaN
JHEMTs for both high-voltage power and low-voltage power/digital applications.
25

Chapter 3
Multi-channel monolithic-cascode HEMT
Power device design aims at concurrent realization of lower Ron and high BV. By stacking multiple 2DEG
channels, the 2DEG density can be increased proportionally, therefore reducing the wafer Rsh and device Ron. AlGaN/GaN multi-channel epitaxy has been initially demonstrated around the 2010s by MBE.
However, MBE is usually not suitable for large-diameter, high-volume wafer production. Recently, 4-inch
multi-channel wafers have become available by MOCVD on various substrates including Si, SiC, sapphire
and GaN. The 4-inch, 5-channel, GaN-on-sapphire wafer produced by Enkris Semiconductor Inc. possesses
a 2DEG density of 3.7 × 1013cm−2
, a 2DEG mobility of 1475 cm2/V ·s, and a Rsh of 110Ω/sq, with the
Rsh being over 3-fold lower than the usual value of a single-channel wafer.
3.1 Reduced Surface Field (RESURF) technique for power devices
The trade-off between BV and Ron is the most challenging part in power devices. In our multi-channel
monolithic-cascode HEMT (MC2
-HEMT), a p-GaN cap layer is served as the RESURF structure to balance
the net electrons in AlGaN/GaN multichannel. This p-type layer extends the depletion region almost to the
drain so that it will increase the resistance along the drift channel when the HEMT is off and will also enable
us to raise the doping level in the drift channel. Such technique is widely used in power devices to manage
the E-field and lower down the Ron[101, 102]. Figure 3.1(a) shows a typical diode for high voltages applied
26

Figure 3.1: (a) Lateral RESURF structure at full depletion in a diode. (b) Electrical field comparison at the
surface. (c) Double RESURF MOSFET. Copyright from 2004 iTUm and 2017 IEEE.
by RESURF structure[103]. The full depletion takes the voltage and the E-field is distributed laterally more
evenly (Figure 3.1(b)). The double RESURF in Figure 3.1(c) induces another thin p-doped region (often
termed as p-top), which is more highly doped than the n-drift region and creates an extra depletion region
emerging from the surface[104]. This, in turn, allows a higher carrier concentration in the drift channel,
leading to a lower Ron without compromising the blocking capability of the device. These designs are the
stepping stones towards superjunction power devices.
T. Fujihira first proposed the theory of semiconductor superjunction devices and in the late 1990s,
CoolMOS was introduced as a candidate to break the original Si limitation (Figure 3.2(a))[105–108]. PN stripes could incredibly improve Ron when the net donors and acceptors are well balanced since the
resistance in the drift channel (Rdrif t) dominates Ron when the drain bias is high. There are several
structures designed with p-n superjunctions realizing record-breaking performance in Si-based devices
(Figure 3.2 (b) and (c))[104].
27

Figure 3.2: (a) CoolMOS structure using a planar gate. 3-D schematic layout of a vertical superjunction
trenchMOSFET where the superjunction stripes are (b) parallel and (c) orthogonal to the trench gate.
Copyright from 2017 IEEE.
In this chapter, I will introduce the application of a MC2
-HEMT and our ongoing work on the buried
p-GaN activation towards GaN superjunction as well as the characterization of multi-channel AlGaN/GaN
interface.
3.2 Multi-channel monolithic-cascode HEMT
The multi-channel structure can effectively reduce Ron and could be a game changer for lateral highvoltage GaN devices. Whereas it is very difficult to design multi-channel HEMTs, as their planar gate is in
deep D-mode. This work proposes a new design to realize the E-mode in high-voltage (HV) multi-channel
HEMTs by combining a low-voltage (LV) E-mode HEMT and a HV planar multi-channel HEMT in the
cascode connection. The LV HEMT is integrated monolithically by using one channel in the multi-channel
wafer. This design enables the first demonstration of E-mode GaN HEMTs up to > 10kV. A low specific Ron
of 40mΩ·cm2
is demonstrated in 10kV device, setting a new record in Baliga’s FOM for medium-voltage
transistors.
28

Figure 3.3: (a) 3-D schematic of the AlGaN/GaN MC2
-HEMT fabricated in this work. The SiNx passivation layer is partially removed to show the internal structure. (b) Equivalent circuit model and (c) top-view
schematic of the MC2
-HEMT, showing the cascode consiguration in which the gate of the multi-channel
HEMT (MC-HEMT) is connected to the source. (d) The list of key geometric parameters (illustrated in (c))
and their values. The smallest feature is 2µm; no sub-µm lithography is needed.
Figure 3.3 shows the schematics, equivalent circuit, and key geometries of our MC2
-HEMT. shows the
schematics, equivalent circuit, and key geometries of our MC2
-HEMT. In a 5-channel AlGaN/GaN wafer,
the 5th 2DEG channel is used for making the LV E-mode HEMT with gate recess. A plurality of Ohmic vias
function as the effective drain for the single-channel LV-HEMT and the source for the multichannel HVHEMT. The HV-HEMT gate is connected to the LV-HEMT source, forming a cascode. In the HV-HEMT, a
p-GaN cap layer balances the net donors in the multi-channel and thus functions as a RESUFR structure,
similar to that described in [109]. The BV of the LV-HEMT (≈ 200V ) is designed to be higher than the
magnitude of the multichannel HEMT’s VT H (V MC
T H ≈ −100V ). The smallest geometric feature is 2µm.
This MC2 − HEMT is different from commercial cascode GaN HEMTs, in which the LV device is a Si
MOSFET in a separate chip, or the all-GaN cascode reported in [110], in which the HV-HEMT is on a single
channel. The wafer consists of 20nm p
+-GaN, 350nm p-GaN ([Mg] ≈ 4 × 1018cm−3
), five Al0.25Ga0.75N
(23nm)/ GaN (100 nm) hetero-channels, and a buffer layer, all continuously grown on a 4-inch sapphire
substrate by MOCVD. Hall measurements reveal a Rsh of 178Ω/sq, a 2DEG mobility of 2010cm2/V · s,
and a total 2DEG density of 1.75 × 1013cm−2
.
Figure 3.4 shows the main fabrication steps. Patterned dry etches were first performed for p-GaN
and four AlGaN/GaN channels using Cl2/BCl3 gases. A Cl2/Ar/O2 etch followed, which has a ≈ 20
selectivity for GaN over AlGaN and allows etch-stop at the 5th channel. The Rsh of the exposed 5th
29

Figure 3.4: Schematic illustration of the main steps in device fabrication. The self-aligned Ohmic process
for the vias and drain contact is similar to that in [99].
Figure 3.5: a Top-view SEM image of the fabricated GaN RESURF MC2 − HEMT and the enlarged
image of the source-to-multi-channel-HEMT region. b . Illustrations of charges and capacitance before
and after reaching the critical p-GaN thickness (TO) for charge balance condition, suggesting a drop in
C-V characteristics at the critical condition. c Experimental C-V curves of the test structure with a step
thinning in p-GaN, revealing TO ≈ 80nm
channel was measured to be 567Ω/sq. Three types of LV-HEMTs were fabricated: the D-mode MOSHEMT and Schottky-gate HEMT (Sch-HEMT), and E-mode MOS-HEMT. The E-mode device was made by
an a BCl3 etch for 18 ∼ 19nm AlGaN under gate. A high-k HfO2 was deposited as the gate dielectric
by atomic layer deposition. Ohmic contacts were then formed on the 5th channel as the source, in the
5-channel vias, and over p-GaN and 5-channels as the drain. A self-aligned process was used for the latter
two processes[99]. The p-GaN RESURF was made by a gradual etch to reach the charge balance condition.
A portion of p-GaN close to the drain was completely removed to avoid the p-GaN punch through. Finally,
Ni/Au gates were formed on single- and multi-channel HEMTs, followed by PECVD SiNx passivation.
Figure 3.5(a) shows the top-view SEM images of the fabricated device, showing the accurate etch controls in the single- to five-channel transition region, RESURF, and 5-channel p-gate region. Figure 3.5(b)
30

Figure 3.6: Simulated (a) potential contours, (b) potential distribution along a cutline in the 5
th 2DEG
channel, and (c) E-field contours when the MC2
-HEMT is blocking 10kV, showing the voltage drop in the
LV-HEMT clamped at ∼ 140V .
and (c) shows the RESURF p-GaN thinning process witnessed by C-V measurements of a test structure.
When the acceptors in p-GaN balance total donors in the multi-channel, a capacitance drop is shown. The
critical p-GaN thickness was identified as ∼80nm.
3.3 Device simulation and characterization
3-D TCAD simulations in Silvaco Atlas were used to verify the device working principles. At gate bias
VGS > Vth, Ohmic vias allow current flows from the single channel into 5 channels. In the OFF state (VGS
< Vth), when the VDS is large, the HV HEMT starts to be depleted and the device gate is shielded from
high VDS and E-field (Figure 3.6(a)-(c)). The RESURF in HV-HEMT spreads the E-field, allowing a BV
scaling with the multi-channel gate-drain distance (LMC
GD ). The E-field distribution is well balanced with
the peak E-fields located in the RESURF and drain side. The E-field in the gate region is very low. The gate
is completely shielded from high VDS and E-field.
Figure 3.7(a) and (b) show the transfer and output characteristics of the D-mode and E-mode 10kV
MC2
-HEMT with LMC
GD = 103µm, respectively, one with a Sch-HEMT and the other with a recess MOSHEMT as the LV HEMT. The two types of MC2
-HEMT show Vth of -3.5V and +1.5V extracted at 1 mA/mm.
Only a very small hysteresis was observed. The D- and E-mode 10kV MC2
-HEMT show over 300mA/mm
31

Figure 3.7: (a) Transfer characteristics of E-mode and D-mode MC2
-HEMT with LMC
GD = 103µm. The
D-mode device has a Shocttky gate and E-mode device a MOS gate. Vth = 1.5V in the E-mode device. (b)
Output characteristics of E-mode and D-mode MC2
-HEMT with LMC
GD = 103µm. The E-mode device
show a very slightly lower Ron as compared to the D-mode device. ID exceeds 300mA/mm. (c) OFF-state
I-V curves of E-mode MC2
-HEMTs with LMC
GD of 28, 53, 78 and 103µm, showing BV of 3.45, 6.58, 8.86 and
> 10kV. The 103µm device was tested to 10kV (our setup limit) without breakdown. IG does not increase
at breakdown (gate does not break).
ID, and their Ron is almost identical, suggesting a small gated-channel resistance in the LV recess MOSHEMT using the high-k gate dielectric. Figure 3.7(c) shows OFF-state I-V curves of E-mode MC2
-HEMT
with LMC
GD = 28, 53, 78, 103µm measured at zero VG, revealing a ∼ µA/mm drain leakage current and
BV of 3.5, 6.6, 8.9 and >10kV, respectively. The p-GaN RESURF design enables an average lateral E-field
(EAV E = BV /LMC
GD ) of 1.24 MV/cm. The 103µmLMC
GD device was repeatedly measured to 10kV (our test
limit) without breakdown, and its BV was estimated to be 10.7kV. The gate does not break at BV (IG does
not increase), verifying the low E-field at the device gate.
Figure 3.8 benchmarks the specific Ron vs. BV of our 3.45 ∼ 10kV E-mode GaN MC2
-HEMT and the
reported GaN, SiC and ultra-wide-bandgap (UWBG) FETs with similar BV[111–114]. Our MC2
-HEMT
is the only WBG/UWBG E-mode power FET in the 3 ∼ 10kV range in addition to SiC MOSFETs. The
Ron vs. BV performance of our 6.5kV+ GaN MC2
-HEMT exceeds the SiC 1-D unipolar limit, rendering
32

Figure 3.8: Specific Ron vs. BV benchmark of E-mode GaN MC2
-HEMT and the state-of-the-art 3 ∼ 10kV
GaN HEMTs, SiC MOSFETs, and AlGaN HEMTs
a record Baliga’s FOM of 2.84GW/cm2
. Our 10kV GaN MC2
-HEMT has a 2.5-fold lower specific Ron as
compared to 10kV SiC MOSFETs.
In summary, we present a new device concept, the RESURF MC2
-HEMT, which can concurrently exploit the low Rsh of multi-channel materials, realize the robust E-mode gate control without the need for
sub-micron lithography, and shield the gate region from high E-field. We experimentally demonstrated
E- mode 3.45 ∼ 10kV GaN RESURF MC2
-HEMTs, and their FOMs set a new record in all 6.5kV+ power
transistors. Our results show the great potential of GaN MC2
-HEMTs for medium-voltage power electronics. In addition, the MC2
-HEMT concept is applicable to other WBG/UWBG materials as a platform
design for multi-channel high power devices.
33

Chapter 4
First observation of 2DHG and 2DEG coexistence in multichannel
AlGaN/GaN superlattice
4.1 2DEG and 2DHG in AlGaN/GaN heterostructure
As mentioned in the Introduction, 2DEG is generated by the piezoelectric and spontaneous polarization
and is confined in the triangle quantum well at the AlGaN/GaN interface. For an intrinsic AlGaN/GaN heterostructure, the existence of 2DEG is always accompanied by the 2DHG because of the charge neutrality.
In most samples, MOCVD grown GaN is a Ga-faced material ([0001] direction) and 2DEG is located at
the interface where AlGaN is grown on top of GaN. However, for N-faced GaN ([000¯1] direction), 2DEG
is located at the interface where GaN is grown on top of AlGaN. This material direction effect obviously
points to the spontaneous polarization (PSP ). As for the piezoelectric polarization, the lattice constants
of AlN and GaN are a = 3.110Å and a = 3.190Å respectively[115]. Therefore, in a typical Ga-faced
GaN/AlGaN/GaN heterostructure, PSP is pointing downwards and tensile strain in AlGaN would also
contribute the piezoelectric polarization (PP E) in the same direction (Figure 4.1)[54].
The polarization induced charge density could be calculated by the gradient of polarization in space:
ρP = ∇P
34

Figure 4.1: Polarization induced sheet charge density and directions of the spontaneous and piezoelectric
polarization in Ga-face strained GaN/AlGaN/GaN heterostructures. This sample is Ga-face. Total polarization P) is pointing down, leaving a −σ on the top and a +σ on the bottom.
.
The pointing down PP E and PSP induce positive sheet charge density +σ at the bottom AlGaN/GaN
interface, which in turn free electrons will tend to compensate the polarization induced charge and will
form 2DEG in the AlGaN/GaN band offset. Since AlGaN is unintentionally doped, there should be 2DHG at
the top AlGaN/GaN interface to compensate the negative sheet charge density −σ. This is the theoretical
basis for 2DHG existence and many researchers endeavoured to detect and characterize 2DHG experimentally[116–118]. S. Acar et al. fabricated a Al0.25Ga0.75N/GaN/AlN sample on sapphire (Al2O3) substrate
by MOCVD (Figure 4.2(a)). All layers are nominally undoped. GaN and AlN have a huge bandgap offset
(3.4eV for GaN and 6.2eV for AlN), leading to a conduction band quantum well below the Fermi level at
the Al0.25Ga0.75N/GaN interface and a valence band quantum well above the Fermi level at the GaN/AlN
interface (Figure 4.2(b).
35

Figure 4.2: (a) Layer structure and (b) simulated band diagram in the case of zero bias for the
Al0.25Ga0.75N/GaN/AlN heterostructures.
2DEG and 2DHG are confined in such quantum wells and are enhanced by the polarization induced
carriers. Hall measurements are performed to characterize Hall coefficient (RH) and Hall effect conductivity (σ). Current density is calculated as below:
J⃗ = σE⃗
⇒




Jx
Jy




=




σxx σxy
σyx σyy








Ex
Ey




. As electrons and holes are both existing in the sample, current density in y-direction is:
Jy = Jh + Je = epVhy + enVey
, where p and n are the hole and electron density, Vhy and Vey are the velocity along the y-direction for
electrons and holes. When the magnetic field (Bz) is applied, electrons and holes are manipulated not only
36

Figure 4.3: Lorentz forces on electrons and holes under Hall measurement. Bz is perpendicular outside.Ex
and Ey result in two directions of current density Jx and Jy.
by the electric field force but Lorentz force as well. Forces over electrons and holes are decomposed as
Figure 4.3 shown:
Fhy = eEy − eVhxBz
−Fey = eEy + eVexBz.
We could easily get the following equation:
eEy(nµe + pµh)
2 = BzJx(pµ2
h − eµ2
e
)
,
37

where p and n are the hole and electron density, µe and µh are the mobility of electrons and holes. By
combining this equation and the current density matrix above, σxx(B) and σxy(B) are derived as below:
σxx(B) = Σk
nkeµk
1 + µ
2
kB2
σxy(B) = Σk
Sknkeµ2
kB
1 + µ
2
kB2
, where Sk = 1 for holes and Sk = −1 for electrons. Improved quantitative mobility spectrum analysis
(iQMSA) utilizes the equations above to deduce mobility, conductivity and sheet charge density in Hall
measurements[119]. Step variation of Bz and temperature T would enable the linear regression and determine types of carriers as well as their mobility and density. Several groups performed iQMSA technique to
extract individual carrier mobility and density[120–122]. Besides, Xing & Jena’s group reported the 2DHG
solely at the UID GaN/AlN interface without any 2DEG[123].
4.2 Five-channel AlGaN/GaN heterostructure
Despite all these reports on 2DHG existence in AlGaN/GaN interfaces, most of them fabricate an AlGaN/GaN/AlN sandwich heterostructure and there is no investigation on multichannel structures. In our
MC2
-HEMT, a p-GaN RESURF layer is deposited over the AlGaN/GaN multichannel. It is crucial for us
to determine whether 2DHG coexists together with 2DEG in our system as the detection of 2DHG could
help us better manage the charge balance and improve the dynamic performance of this MC2
-HEMT.
However, the density and mobility of 2DHG are very small at room temperature, compared with
2DEG[124]. 2DHG could be shrouded and even iQMSA is not capable of accurately determining the quantity of 2DHG, especially in the multichannel system. R. Lingaparthi et al. ruled out the possible formation
of 2DHG in their 5-channel AlGaN/GaN heterostructure[125]. At the beginning, we synthesized the same
structure (Figure 4.4). A 1.2 µm buffer layer was grown epitaxially over the 650µm sapphire substrate film.
38

Figure 4.4: (a) Top view and (b) cross section schematic of multichannel heterostructure. Cathode is a
circular ring around the anode. 2DHG is on the top of Al0.28Ga0.72N layer and 2DEG is at the bottom.
Figure 4.5: C-V measurement setup. SMU and CMU are integrated together to obtain the capacitance as a
static bias is applied on the force tip. The Guard Switch Unit (GSWU) is clipped on the guard axis in the
triaxial cable to accurately calibrate the capacitance.
Then the Al0.28Ga0.72N(25nm)/GaN(100nm) barrier channel was deposited by MOCVD, repeating for 5
periods. A very thin AlN layer (1nm) was inserted between Al0.28Ga0.72N and GaN to avoid interface
alloy scattering effects and to improve the lateral mobility of the 2DHG [126]. A cathode ring is etched
first and filled by metals (Ti/Al/Ni/Au). Anode pad is deposited over the film(Ni/Au). All the electrodes
are Ohmic contact.
C-V measurements are performed by Keysight B1500A Semiconductor Device Parameter Analyzer with
Capacitance Measurement Unit (CMU) (Figure 4.5). A small AC voltage (30mV) with certain frequency is
39

Figure 4.6: Schematic of Metal-Semiconductor diode capacitance. We assume a p-doped semiconductor
and the width of free holes is W. And the quantity of free charge is QS. Hole density produced by p-type
dopant is NA. The cross section area of the semiconductor is A.
applied across our 5-channel AlGaN/GaN heterostructure so as to obtain the quasi-capacitor’s impedance
(Z =
V
I
). Meanwhile, a static voltage is also applied by the two probes for investigating the charge
depletion under different bias condition. The analyzer would automatically calculate the phase difference
between voltage and current and return the imaginary part of the total impedance. Under the reverse
bias, both 2DHG (if exists) and 2DEG will be depleted under reverse bias, where C-V reflects the charge
Q inside the heterostructure. A simple Metal-Semiconductor diode model could be used to overview the
carrier distribution profile (Figure 4.6).
Because we assume this semiconductor is p-doped material, we could ignore the intrinsic electrons
and holes as well as the dopant induced electrons. QS could be integrated as:
QS = qA Z W
0
(p − n + N
+
D − N
−
A
) ≈ −qA Z W
0
NA
C =
dQ
dV = qA d
dV Z W
0
NAdW = qANA(W)
dW
dV
The equation for a general capacitor is:
C =
ϵA
d
40

Figure 4.7: C-V measurements of five-channel AlGaN/GaN heterostructures without p-GaN top layer at
room temperature under (a) f=3kHz and (b) f= 1MHz.
, where ϵ is the dielectric permittivity. Here the distance d between the plates could be viewed as W. So
dW
dV is rewritten below:
dW
dV = −
ϵAdC
C2dV
⇒ NA(W) = 2
qA2ϵd(1/C2)/dV
.
The condition in 5-channel AlGaN/GaN sample is definitely much more complex but equations above
clearly suggest that C-V measurement is able to reflect the carrier distribution profile along the z-axis.
We sweep the reverse bias from 0V to -60V on the anode under different AC frequency (Figure 4.7). In
Figure 4.7(a), there are five ledge-like steps in the C-V profile when reverse bias is increasing negatively,
referring to five AlGaN/GaN barrier channels. Besides, sharp peaks and bumps could also be observed
under f=3kHz. For higher frequency, those peaks and measured capacitance are lowered down in Figure
4.7(b).
GaN has a wide band gap (3.4eV), where many surface states are located between the conduction band
and valence band. These states will trap carriers and keep them trapped even when the Fermi level is far
41

Figure 4.8: Estimated ranges for electron emission from interface states at the GaN MOS interface at room
temperature.
higher than these trapping states. According to Shockley–Read–Hall (SRH) statistics, the time constant τ
of electron emission from the surface states to the conduction band is given as follow:
τ =
1
vT HσT HNC
exp
ET
kT
, where vT H is the electron thermal velocity, σT H is the capture cross-section of the surface states, NC
is the density of states at the conduction band edge and ET is the energy from the surface states to the
conduction band. Generally speaking, if energy levels of surface states below the conduction band edge is
larger than 0.7eV, we call those states "frozen states", meaning that they will not respond to the AC signal
(Figure 4.8)[127].
Difference of C-V profiles between Figure 4.6(a) and Figure 4.6(b) could be well explained by the frozen
surface states. At high AC frequency, the deeper trapping states are frozen and holding carriers while the
states respond accordingly at lower frequency, contributing additional peaks and bumps to the measured
capacitance.
In order to eliminate the effect from surface states and keep the consistency, an extra p-GaN is deposited
over the original 5 channel AlGaN/GaN heterostructure. This is exactly the same structure we used in our
42

MC2
-HEMTs. We would like to confirm our hypothesis that 2DEG and 2DHG coexist in the multichannel.
Beyond that, if existing, how the 2DHG effects power devices perform statically and dynamically is also
the prime problem we are trying to figure out.
4.3 Undoped and n-doped AlGaN/GaN multichannel with RESURF pGaN
We fabricated a five-channel AlGaN/GaN diode with p-GaN over it (Figure 4.9(a)). A 1.2µm GaN buffer
layer is deposited over the saphhire substrate and is followed by the AlGaN/GaN heterostructure. 100nm
GaN is epitaxially grown by MOCVD without any intentionally doping and 25nm AlGaN alloy is grown
by adjusting the percentages of Ga-atom gas flow and Al-atom gas flow. Here, 28% Al content and 72%
Ga content composite the Al0.28Ga0.72N alloy. An 1nm-thick AlN layer is additionally inserted between
Al0.28Ga0.72N and GaN to optimize the interface quality and enhance the carrier mobility. After that,
p-GaN is also synthesized by MOCVD, with a Mg preflow. Total 420nm Mg-doped p-GaN is synthesized, including 400nm p-GaN with dopant level 4 × 1018cm−3
and 20nm p
++-GaN with dopant level
2×1019cm−3
. High temperature is required for activating these p-typed GaN as I describe in the previous
chapter. All the wafers are purchased from Enkris Semiconductor Inc and all the fabrication parameters I mentioned above are examined by Enkris Semiconductor. The sheet resistance for these wafers is
around 100 Ohm/square, indicating great carrier mobility. Oxford Instruments PlasmaPro ICP/RIE is used
to etch the p-GaN layer first and then etch Al0.28Ga0.72N/GaN multichannel. The etching is carefully
proceeded by the mix of chlorine (Cl2) and boron trichloride (BCl3) plasma. Many parameters are taken
into consideration for controlling the etch rate, including gas flow rate, RF power, ICP power and holder
temperature[128]. Roughly etched surface and defects will cause superfluous surface states and hurt the
consistence of samples we fabricate as well as the device performance[129–131]. High selectivity between
43

Figure 4.9: Cross section (a) schematic and (b) TEM of AlGaN/GaN multichannel heterostructure with
p-GaN top layer.
AlGaN and GaN provides accurate ethcing depth and great sidewall quality[132]. Ni/Au are deposited for
the anode while Ti/Al/Ni/Au metals are deposited for the cathode to form Ohmic contacts. There is a small
spacing between the anode and the cathode preventing the circuit short. TEM in Figure 4.9(b) confirms
the high material qualify of this five-channel heterostructure.
Just as the band diagram in Figure 4.2(b), repeated Al0.28Ga0.72N/GaN multichannel forms quantum
wells in the conduction band and valence band. Meanwhile, piezoelectric polarization and spontaneous
polarization induce negative sheet carrier and positive sheet carrier at the top and bottom interface of
Al0.28Ga0.72N layer, respectively. Such polarization will, in turn, enhance the formation of 2DHG and
2DEG that are located in the quantum wells. Band diagram is simulated by using Silvaco (Figure 4.10). The
concentrations of 2DEG and 2DHG in each channel are also calculated. The concentration of 2DHG in the
first channel is 2 × 1020cm−3
, higher than the rest of channels (1 × 1020cm−3
). 2DEG’s concentration
distribution is on the contrary to what 2DHG dose. The last channel’s 2DEG concentration is 2×1020cm−3
but it is 1 × 1020cm−3
in the first four channels. Total net carriers is always zero absolutely since AlGaN
and GaN are both unintentionally doped.
To further validate our hypothesis of the 2DHG and 2DEG coexistence in the multichannel, the AlGaN
layer is delta-doped by Silicon and keep all the other designs the same as a comparison (Figure 4.11). XRD
44

Figure 4.10: Left: Simulated carrier type, band diagram and carrier density distribution along the sample
depth. The black left-orientated arrow represents the negative polarization-induced sheet carrier (σ−),
which is corresponding to the blue right-orientated arrow for 2DHG. The black right-orientated arrow
represents the positive polarization-induced sheet carrier (σ+), which is corresponding to the red leftorientated arrow for 2DEG. We could clearly see the distorted quantum well in the conduction band EC
(red) and in the valence band EV (blue). Fermi level is labeled as the dotted black line. Simulated carrier density distribution well matches the location of 2DHG and 2DEG. Peaks are only positioning at the
GaN/AlGaN interface or AlGaN/GaN interface. Right: Detailed TEM zoom in. Slim dark layer is the unintentionally doped AlGaN (i-AlGaN), sandwiched by the thicker gray GaN layer (i-GaN).
2θ-ω curves are measured at the [002] direction for both undoped and doped samples (Figure 4.12(a)). The
normalized curves align well to each other. GaN peaks are at around 34.5° and AlN peaks are at around
36°, suggesting that doped sample is grown as good as the undoped one. Satellite peaks in the mid of
GaN and AlN are the consequences of the periodical superlattice in our five channel[133]. Figure 4.12(b)
is the reciprocal space mapping of the asymmetric [105] reflections measured by the High-resolution XRD
(HRXRD). AlGaN peak and GaN peak are aligned along the Qx axis. As there is huge lattice mismatch
between the AlGaN and GaN layers, such alignment clearly demonstrates that AlGaN is tensile strained
to GaN layer. Mixed Pendellosung fringes from the AlGaN-GaN Superlattice is observed in both undoped
and doped RSM, which shows sharp interfaces between AlGaN and GaN[125]. A distinctive fringe type
pattern of AlGaN diffraction spot is a result of the superposition of superlattice diffraction and AlGaN
diffraction. These XRD measurements affirm the Silicon doping doesn’t change the heterostructure at all
but only makes changes to the doping level of AlGaN barrier.
45

Figure 4.11: Schematic of multichannel n − Al0.28Ga0.72N/GaN heterostructure.
Figure 4.12: (a) X-ray diffraction (XRD) 2θ-ω curves of undoped and doped multichannel nAl0.28Ga0.72N/GaN heterostructures at the [002] direction. Peaks for GaN [002] and AlN[002] are labeled. Satellite peaks between the GaN and AlN are for AlGaN. (b) Reciprocal space mapping (RSM) of the
doped and undoped multichannels. Patterns are also labeled for all three materials.
4.4 C-V measurements under different temperature and frequency
One method to detect the existence of 2DHG in the undoped multichannel structure is the CapacitanceVoltage (C-V) measurement.
If we use TCAD to simulate the band diagram for the doped structure and compare it to the undoped
condition. In Figure 4.13(a), both undoped and doped condition are simulated. Fermi level in n-doped
AlGaN is lifted, destroying the quantum well in valence band at the GaN/AlGaN interface. Comparing the
undoped band diagram (black line), the doped band diagram (red line) doesn’t have the triangle valence
46

Figure 4.13: (a) Simulated carrier type, band diagram and carrier density distribution along the sample
depth. Red line and black line in the band diagram represent the doped condition and undoped condition, respectively. For carrier type, the black left-orientated arrow is the negative polarization-induced
sheet carrier (σ−), which is corresponding to the blue right-orientated arrow for 2DHG. The black rightorientated arrow is the positive polarization-induced sheet carrier (σ+), which is corresponding to the red
left-orientated arrow for 2DEG. (b) Simulated carrier density with different Si-dopant level. Electron is in
red while hole is in blue.
band distortion above the Fermi level. That means no 2DHG could be restricted in the quantum well and
almost move freely. We also simulate the concentration of electrons and holes under different doping level
(Figure 4.13(b)). As the doping level increases gradually, the 2DEG is enhanced as there is more electrons
brought by the Si dopant. Reversely, the 2DHG is hampered and when the concentration of Si dopant
reaches 5 × 1012cm−2
, almost all the 2DHG is emliminated.
B1500A high-resolution CMU is used to perform the C-V measurement and in order to get high resolution, the maximum voltage we applied is limited to -30V. In Figure 4.14(a), we could observe two clear
capacitance dropping off at VBias = −3V and VBias = −15V , which refer to the depletion of 2DEG in the
first and second AlGaN/GaN channel correspondingly. If we zoom in the C-V profiles at the blue region in
Figure 4.14(a), differences between the undoped profile and doped profile are demonstrated. The overall
capacitance value of the doped structure (Red line in Figure 4.14(b)) is larger than the undoped one (Black
line) when VBias from -3V to -10V. Moreover, another interesting distinction is that a minor ledge in the
undoped profile is spotted after the depletion of the first 2DEG channel. Thus we infer that the absence
47

Figure 4.14: (a) Experimental C-V profiles of the undoped multichannel structure (Black line) and the doped
multichannel structure (Red line). Bias voltage sweeps from 0V to -30V. (b) Zoom in data for VBias = −3V
to −10V . Surface trapping states induced peaks and 2DHG induced ledge are also indicated in figure. (c)
Simulated band diagram under VBias = 0V, −10V, −20V . External electric field is pointing leftwards, as
negative bias voltage is applied on the left anode electrode. 2DHG is moving towards the anode and 2DEG
in each AlGaN/GaN channel is moving independently towards the cathode.
of such minor ledge in the doped structure is due to the existence of 2DHG in our undoped multichannel
AlGaN/GaN heterostructure. Qualitatively speaking, when the negative bias applied on the anode is gradually increasing, band energy will be dragged upwards just like the simulated diagrams shown in Figure
4.14(c). And the external E-field is pointing from the cathode to the anode. Holes are drifting to the anode
while electrons are collected by the cathode. It is easier for electrons to be depleted as the cathode contacts
every 2DEG channel in our design but for holes, it has to overcome the p-GaN region to reach the anode.
This is the reason why holes are depleted after the depletion of 2DEG is finished. As for the small and
sharp peaks occurred in both structures, we conclude them as the trapping states induced charges. I will
explain it later.
Our TCAD simulations support the 2DHG existence. As shown in Figure 4.15(a) and (b), when VBias =
−4V , most 2DEG in the first channel is already depleted, contributing to the major capacitance drop-off.
48

Figure 4.15: Simulated carrier distributions of electrons and holes under (a) (b) VBias = −4V and (c) (d)
VBias = −15V .
However, 2DHG will not be completely drained out. Instead, 2DHG in the second channel is lifted to the
anode, reducing the depletion width and resulting the capacitance increase for the minor ledge I described
previously. When VBias = −15V at the second stage, simulation provides similar results (Figure 4.15(c)
and (d)). At the second dropping edge, 2DEG in the second channel is depleted while 2DHG is slightly
lifted up. We think that depletion width reduction at the second dropping edge is not enough to cause
another observable minor ledge there. So only one minor ledge could be measured by C-V sweeping.
To further prove our conclusion about 2DHG existence and surface states. We measure the C-V under different temperature (from 293K to 78K). In Figure 4.16(a), 2DHG-induced ledge doesn’t shrink when
the temperature is decreasing. This phenomenon perfectly manifests the quantum behavior of the 2DHG.
Peaks induced by surface trapping states, however, become smaller and sharper. Under low temperature,
less trapping states could gain enough energy to be unfrozen. In the doped multichannel heterostructure
(Figure 4.16(c), no 2DHG ledge presents and peaks induced by surface trapping states fade likewise during
the cooling down. Frequency dependence of capacitance for undoped and doped multichannel overwhelmingly confirms our statements that peaks mentioned above are from the surface trapping states. In Figure
4.16(b) and (d), when the voltage is swept from -3V to -10V, trapping state peak gradually fades away if
49

Figure 4.16: Experimental C-V measurements in undoped structure for (a) different temperatures and (b)
different frequency at VBias = −3V to −10V . C-V measurements in doped structure for (c) different
temperatures and (d) different frequency at VBias = −3V to −10V .
Figure 4.17: Experimental C-V measurements in undoped structure for (a) different temperatures and (b)
different frequency at VBias = −18V to −27V . C-V measurements in doped structure for (c) different
temperatures and (d) different frequency at VBias = −18V to −27V .
50

Figure 4.18: (a) Larger sample experimental C-V profiles of the undoped multichannel structure (Black
line) and the doped multichannel structure (Red line). Bias voltage sweeps from 0V to -30V. Zoom in data
for (b) VBias = −3V to −9V and (c) VBias = −18V to −27V .
AC small signal alternates faster (3kHz to 300kHz). This is because the trapping states couldn’t respond
simultaneously and act like "frozen" states. Whereas, 2DHG is able to move friction-less in the quantum
well and isn’t affected by the external AC signal frequency.
For VBias = −18V to −27V at the second dropping edge, C-V profiles under different temperatures
and different frequencies in undoped and doped structure follow the same behaviors as they do at the first
dropping edge. In Figure 4.17(a) and (c), as the temperature is decreasing, trapping state induced peaks
gradually shrink. The trapping state induced peaks in the doped structure are wider and larger than those
in the undoped structure. This is because that the Si delta doping brings more defects at the AlGaN/GaN
interface, which is already confirmed in our XRD and RSM measurements (Figure 4.12). Interestingly, in
Figure 4.17(a), when the temperature reaches T=78K low, a small peak as well as a bump in the capacitance
rises up. We think this is contributed to the 2DHG rejuvenation at the low temperature. But further
investigations are required for explaining this. Figure 4.17(b) and (d) also suggest these peaks are from the
surface trapping states as they aren’t able to react when the AC frequency is high.
All the phenomena above could be repeated in other samples with different sizes (Figure 4.18). We
also used B1505A Keysight analyzer for the whole voltage range sweeping, where reverse bias is swept
51

from 0 to -140V at the anode (Figure 4.19). A clear five dropping stages is observed, referring to the five
AlGaN/GaN 2DEG channels in our design. When the bias voltage reaches -140V, almost all the 2DEG and
2DHG are drained. The TCAD simulation indicates such depletion at VBias = −140V
Figure 4.19: Simulated carrier distributions of (a) electrons and (b) holes under VBias = −140V . (c)
Experimental C-V profiles of the undoped multichannel structure (Black line) and the doped multichannel
structure (Red line). Bias voltage sweeps from 0V to -140V.
Figure 4.20: Photograph of the surge current test setup and its circuit diagram.
52

4.5 Conclusions and future plan
Sections above describe and explain the coexistence of 2DEG and 2DHG in our multichannel AlGaN/GaN
heterostructures. We detected and characterized the coexistence of 2DEG and 2DHG for the first time in
the multichannel AlGaN/GaN heterostructure. A minor ledge after the 2DEG depletion is observed in the
undoped strcture. Such ledge will not disappear under different temperatures and different frequencies,
unlike the surface trapping states induced peaks. TCAD simulations also validate our hypothesis as 2DHG
is lifted when the voltage on the anode is negative. As for the future plan, the Multichannel structure is
already exploited for the static power devices. However, the dynamic performance of this multichannel
is still lacking of investigation and we wonder how the presence of 2DHG will influence power devices’
dynamic behavior. GaN HEMT is widely used in the DC-AC or AC-DC conversion and requires outstanding turn-on and turn-off speed. In the future, a surge current test setup will be used to characterize the
robustness and reverse recovery performances of this heterostructure (Figure 4.20)[134]. A voltage pulse
will be triggered and current versus time will be monitored.
53

Chapter 5
Thick buried p-GaN activation and applications
5.1 Thick buried p-GaN activation
There are two ways of fabricating the p-n stripes in the superjunction. One is multiepitaxy and the other is
trench filling. While multiepitaxy uses subsequent expitaxy-and-implantation method to grow and dope
the layer one by one, the trench filling aims at etching-and-regrowth technique (Figure 5.1)[104]. The
advantage of multiepitaxy method is that it could control the doping level at different depth accurately but
it also requires complex fabrication process. The advantage of the trench technology lies in the smooth
shape of the p-n junction[135, 136].
However, when things go to the GaN, we face new challenges as the Mg-doped p-GaN is hard to be
fully activated especially when the p-GaN is buried and there is still few investigations on the sidewall
properties on the p-n interface.
The activation of these buried p-GaN layers usually relies on the lateral hydrogen diffusion through
the etched mesa sidewalls, which is known to induce non-uniform acceptor distributions. The acceptor
profile, electric field (E-field) blocking capability, and leakage current mechanisms of the sidewall activated
p-GaN layer have not been fully understood yet. We want to address these knowledge gaps by fabricating
vertical GaN p-n diodes with a thick (4µm) p-GaN. In this sector, I will describe the work we have done
and the future plan on this topic. Two activation schemes are performed to allow the hydrogen diffusion
54

Figure 5.1: (a) Typical multiepitaxy process flow. (b) Typical trench and side-wall epiprocess flow. Copyright from 2017 IEEE.
through sidewalls and the top surface, respectively. For the sidewall activation, an analytical model is
developed to depict the spatial distribution of the activated acceptor and the temporal evolution of this
distribution with the increased annealing time.
This work probes the dopant profile and electrical characteristics of a sidewall-activated buried pGaN layer, by characterizing vertical GaN p-n diodes comprising it. The surface potential mapping by the
Kelvin probe force microscopy (KPFM) is used to confirm the partial activation. The epitaxial structure
consists of a 20 nm p
+-GaN layer ([Mg]: 1 × 1020cm−3
), a 4.3µm p-GaN layer ([Mg]: 3 × 1019cm−3
) and
a 200nm n-GaN layer ([Si]: 6 × 1018cm−3
) grown on GaN substrates by MOCVD (Figure 5.2(a)). On top
of some samples, a 300nm n-GaN layer ([Si]: 5 × 1018cm−3
) was regrown in MOCVD, which prevents the
55

Figure 5.2: (a) Schematic of the epitaxial structure. (b) SIMS data of [Mg], [H], [Si] and [C] concentrations
in the n-p-n structure after the regrowth of the n-GaN cap layer.
[H] diffusion through top surfaces. Figure 5.2(b) shows the concentrations of [Mg], [H], [Si] and [C] in a
sample with the n-GaN cap measured by SIMS. A high [H] concentration of ∼ 1019cm−3
is exhibited in
the p-GaN layer after the n-GaN regrowth.
Figure 5.3 shows the major fabrication steps of vertical GaN p-n diodes. After the wafer cleaning
(Figure 5.3(a)) and n-GaN regrowth (Figure 5.3(b)), a 5µm deep mesa etch is performed, followed by a
rinse in 5% TMAH to remove the etch damages. The activation annealing is at 800°C in N2
for 0.5-1 hours
(Figure 5.3(c)). Then the n-GaN cap layer is etched (Figure 5.3(d)), followed by the formation of the anode
by Pd/Ni/Au with a 600°C annealing in N2
. The cathode is formed by Ti/Al/Ni/Au (Figure 5.3(e)). A control
diode is fabricated without n-GaN caps during the p-GaN activation, allowing the via-surface [H] release
and thus a full activation (Figure 5.3(f)). Another control diode without p-GaN activation is also fabricated.
The radii of all three types of diodes range from 5µm to 100µm.
5.2 Activated acceptor distribution and modeling
The activated acceptor (NA) profile in the sidewall-activated p-GaN is first probed by KPFM, which enables nanometer-scale mapping of surface potentials[137]. Figure 5.4(a) and (b) show the p-GaN surface
56

Figure 5.3: Major fabrication steps of the vertical p-n diodes (a)-(e) with sidewall activation (blue arrow)
and (f) with surface and sidewall activations (red arrow).
morphology and potential, respectively, after the sidewall activation for 0.5 hours. The surface potential
increases from the diode edge towards the center without correlations to morphology features, suggesting
a non-uniform NA distribution. The NA distribution, NA(x), can be derived by:
NA(x) = niexp(
Ei(x) − EF
kT )(1 + 4e
EA(NA)−EF
kT )
, where ni
is the intrinsic carrier concentration, Ei(x) is the local intrinsic energy level, T is the temperature, k is the Boltzmann constant, and EA is the activation energy of [Mg] in GaN. The Ei(x) variation
can be represented by the relative change in the surface potential. Note that EA also depends on NA[138].
Based on the fitted EA ∼ NA relation and KPFM data, the NA(x) profile is numerically solved as shown
in Figure 5.4(c), revealing a significantly lower NA beyond a distance of 5µm from the sidewall (the concentration of the effective, ionized [Mg] is about 1019cm−3
).
57

Figure 5.4: (a) Surface morphology and (b) potential on the p-GaN surface. (c) Extracted surface potential
and calculated NA along a cutline in (b).
5.3 Spatial-temporal distribution of activation ratio
To quantify the spatial profile of activation ratio (η, the ratio between the activated NA and the effective [Mg] concentration) as a function of annealing time t, a [H] diffusion model is established. The [H]
concentration can be depicted by a generic diffusion equation in the cylindrical coordinate:
D
1
r
∂
∂r (r
∂[H]
∂r ) = ∂[H]
∂t
, where r is the radial distance. A boundary condition in the center that describes the zero [H] concentration gradient, another one depicting the sidewall diffusion barrier, and an initial condition can be written
as:
∂[H]
∂r |r=0,t = 0
d
dt(
[H]r=R,t=0
[H]r=R,t
= A
[H]r,t=0 = 1019cm−3
58

Figure 5.5: (a) Modeled η in a sidewall-activated p-GaN with R=10 µm for the activation time t up to 1
hour. (b) Cutlines for η v.s. r at t of 0.5 and 1 hours. (c) Cutlines for η v.s. r at the device edge and center.
Modeled spatial-temporal distribution of η for sidewall-activated p-GaN with R of (d) 0.1 mm and (e) 1
mm. The activation boundary contour is also marked in (e). (f) Nex
A
and Nmodel
A
of the sidewall activated
p-GaN with various R.
, where D is the [H] diffusion coefficient and A is a constant related to the sidewall surface barrier for [H]
absorption[139]. The model calibration (will be detailed soon) produces a D of 0.9 × 10−10cm2
s
−1
and
an A of 1.3 × 10−3
s
−1
for our samples.
Figure 5.5(a) shows the modeled η as a function of r and t in a sidewall-activated p-GaN region with
R=10µm. The two cutlines in Figure 5.5(b) show the spatial distribution of η after 0.5 and 1 hours annealing.
After 1 hour annealing, η is close to 100% near the edge and around 50% in the center. Another two cutlines
in Figure 5.5(c) show the temporal evolution of η at the edge and center. The activation first occurs at the
edge and saturates early there and the activation in the center shows an initial delay and ramps up later.
Figure 5.5(d) and (e) show the modeled spatial-temporal distribution of η for two larger p-GaN regions
with a R of 0.1 and 1 mm. A 100-hour annealing is predicted to fully activate the former p-GaN, while
a 1000-hour annealing is still insufficient for the latter p-GaN. As shown in Figure 5.5(c), for large R, the
contour of activation boundary in the cylindrical coordinate roughly follows a t ∝ d
2
relation, where d
59

is the radial distance to the sidewall. This suggests a fast increase in t for the full sidewall activation of a
larger p-GaN area.
In summary, this work unveils the NA profile, E-field distribution, and leakage mechanisms of a thick
buried p-GaN activated through the etched sidewalls. Our model reveals the spatial NA distribution as a
function of annealing time. We will use the selective growth technique to fabricate the p-n trenches to
see whether it could have a great interface quality and whether we could apply this buried activation to
achieve the GaN-based superjunction power devices with new records.
60

Chapter 6
Conclusions
GaN power devices are on a swift path to be greatly commercialized and optimized. Our work on the lateral
p-GaN/2DEG junction offers insights of the selective p-GaN regrowth and a better fabrication process of
Mg-doped GaN. And we utilize such p-type/2DEG junction as well as the FinFET concept to design the
tri-gate GaN junction HEMT. P-type NiO contributes to a perfect depletion in the trench gates, which in
turn obtain a lateral JHEMT with over 2kV BV. Then we demonstrated multichannel HEMT to further
improve our devices’ performance by lowering down the Ron. The brilliant application of p-GaN layer
as RESURF layer balances the net donors in the multichannel. This MC2
-HEMT shows a 1.5V Vth, a
40mΩ·cm2
specific Ron and a >10kV BV. We firstly confirmed the coexistence of 2DHG and 2DEG in the
multichannel AlGaN/GaN heterostructure. We compared the undoped multichannel with the n-doped one
and C-V measurements clearly indicate the presence of 2DHG at the top interface of AlGaN barrier. We
keep pushing to the limits of GaN power devices by exploiting superjunctions. Buried p-GaN activation
and interface characteristics are the key factors to realize the p-n stripes in GaN. Our current efforts are
devoted into characterizing and modeling the sidewall activation in the regrown p-GaN. I believe our
research will promote GaN power devices as a promising candidate with record-breaking performance in
the application of high voltage management and ICs. The story is continuing.
61

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71

Abstract (if available)

Abstract III/V group semiconductors are rejuvenating recently, attracting more attention due to the maturing commercialization of Gallium nitride (GaN). With wide band gap, high carrier mobility and great thermal stability, GaN devices have applications not only in optoelectronics, but also in power devices and next generation integrated circuits (ICs). Nowadays, emerging demands for electric vehicles and energy conservation outline the bright future of GaN high power devices.

In 1980s and 1990s, Hiroshi Amano, et al. developed the p-type GaN based blue light-emitting diodes (LEDs) and were awarded the 2014 Nobel Prize in Physics. Since then, academia and industry shifted their focus from the optoelectronics in quantum wells to aluminum gallium nitride/gallium nitride (AlGaN/GaN) 2-dimensional electron gas (2DEG), hoping to integrate Ga on Silicon (Si) substrate and apply it with lower on-resistance (Ron) and higher breakdown voltage (BV). As the lattice mismatch between Si and GaN was solved by a buffer layer, the selective-area regrowth of p-GaN is still challenging and more innovative device structures are to be exploited to improve the performance.

Our group, collaborating with others, fabricate a lateral p-GaN/2DEG junction diode to characterize the regrown quality and transfer characteristics of the sidewall p-n junction under different Magnesium (Mg) pre-flow conditions. The planar junction offers a significant improvement by adding a Mg pre-flow before the regrowth to better diffuse Mg atoms beyond the regrowth interface. A 45s Mg pre-flow gives the best BV. Large-area and trench filling multi-finger p-GaN/2DEG junction diodes are compared and excellent rectifying behavior with an on/off ratio of over 5 × 10^7 in both devices are shown. A BV over 100V is demonstrated, where the peak electric field is estimated to be at least 2.5 MV/cm at the sidewall junction. The results suggest that p-GaN trench-filling regrowth is a viable approach for selective-area p-type doping in GaN power devices and also support unconventional GaN devices based on p-GaN/2DEG junctions.

By combining the p-GaN/2DEG junction conception and FinFETs fabrication, we proposed a tri-gate GaN junction high-electron-mobility transistor (JHEMT), where a p-type nickel oxide (NiO) wraps around AlGaN/GaN fins. Such tri-gate JHEMT provides a great subthreshold slope (SS) of 63±2mV /decade with an on-off current ratio of 10^8. The depletion region formed by p-type NiO/2DEG junction exhibits a positive threshold voltage (Vth) in addition with a BV > 1500V. Besides, instead of a single AlGaN/GaN channel, a 5-channel AlGaN/GaN structure was applied to further improve the specifications for power devices. We design a multi-channel monolithic-cascode HEMT (MC2-HEMT), integrating an enhancement-mode (E-mode) low-voltage (LV) HEMT and a depletion-mode (D-mode) high-voltage (HV) HEMT together. By doing so, 2DEG density is significantly promoted and the in-series cascode guarantee our MC2-HEMT is normally turned off, which subsequently suppress the Ron. Our devices show a BV higher than 10kV as well as a low specific Ron of 40mΩ·cm^2.

Although the multichannel structure is already widely applied, there are few experimental reports of the characterizations and physics at the AlGaN/GaN interface, especially for the existence of 2D hole gas (2DHG). Due to the lattice mismatch between AlGaN and GaN as well Ga-face orientation, spontaneous and piezoelectric polarization effect will induce 2DEG and 2DHG concurrently. However, 2DHG is more diluted and has a much smaller mobility, making it difficult to detect the existence of 2DHG. We fabricate two types of multichannel AlGaN/GaN heterostructures, one with unintentionally doped (UID) AlGaN and another with Si-doped AlGaN.
Capacitance-Voltage (C-V) measurement is also performed under different temperatures and frequency. By comparing these two different types of heterostructures, we clearly manifest the 2DHG at the AlGaN/GaN interface since the presence of 2DHG would increase the vertical capacitance level. An extra small stage is observed by high-resolution sampling unit in the UID heterostructure, indicating the presence of 2DHG. TCAD is used to simulate the carrier concentration distributed along the depth and confirm the existence of both 2DEG and 2DHG. This work differentiates the stage caused by 2DHG and peaks induced by surface states. We also discuss the influence of 2DHG presence on power devices and how to improve their performance.

We investigate the activation mechanism for buried p-GaN by Kelvin probe force microscopy (KPFM) mapping and C-V characteristics. KPFM profile shows that dopants are activated more near the sidewall. Spatial carrier distribution is modeled as a function of annealing time.

In conclusion, our work demonstrates GaN power devices as a promising candidate with record-breaking performance. We investigate the carrier concentration profile in multichannel AlGaN/GaN heterostructures as well as the activation mechanism for buried p-GaN. All these findings solidify GaN’s unique role in the application of high power management and ICs.

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University of Southern California Dissertations and Theses

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Asset Metadata

Creator Du, Zhonghao (author)

Core Title GaN power devices with innovative structures and great performance

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Degree Conferral Date 2023-12

Publication Date 11/22/2024

Defense Date 09/05/2023

Publisher Los Angeles, California (original), University of Southern California (original), University of Southern California. Libraries (digital)

Tag GaN,III-V materials,OAI-PMH Harvest,power devices,semiconductors

Format theses (aat)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Wang, Han (committee chair), Shao, Yu-Tsun (committee member), Wu, Wei (committee member)

Creator Email zhonghad@usc.edu,zhonghaodu@outlook.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-oUC113778513

Unique identifier UC113778513

Identifier etd-DuZhonghao-12492.pdf (filename)

Legacy Identifier etd-DuZhonghao-12492

Document Type Dissertation

Format theses (aat)

Rights Du, Zhonghao

Internet Media Type application/pdf

Type texts

Source 20231129-usctheses-batch-1109 (batch), University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

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