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Van der Waals material electronic devices for memory and computing
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Content
Van der Waals material electronic devices for memory and computing
by
Hung-Yu Chen
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
August 2023
Copyright 2023 Hung-Yu Chen
Acknowledgements
First and foremost I am extremely grateful to my supervisors, Prof. Han Wang for their invaluable
advice, continuous support, and patience during my PhD study. His immense knowledge and plentiful
experience have encouraged me in all the time of my academic research and daily life. I would like to
express my sincere gratitude to my labmates, especially Dr. Jiangbin Wu for their invaluable assistance
during the experiments, provision of materials for lectures, and imparting their extensive knowledge and
skills. I am also grateful to my colleagues from other groups for their valuable contributions to my research
and insightful suggestions. Additionally, I would like to extend my heartfelt appreciation to my supportive
friends who have been with me throughout my academic journey. Lastly, I am deeply grateful to my family,
particularly my husband, whose unwavering support has been my pillar of strength throughout my pursuit
of this degree.
ii
TableofContents
Acknowledgements ii
ListofFigures iv
Abstract vi
Chapter1: Introduction 1
1.1 Van Der Waals material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Background for ferroelectric based memory . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 The mechanism of FTJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Ferroelectric tunnel junction and its electroresistance . . . . . . . . . . . . . . . . . 5
1.3.2 Transport mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Ferroelectric polarization controlled resistive switching . . . . . . . . . . . . . . . . . . . 7
1.5 Copper indium thiophosphate (CuInP
2
S
6
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter2: Hightunnelingelectroresistanceinferroelectrictunnelingjunction 11
2.1 The vdW FTJ structure and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Origin of the ultra-high TER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Non-equilibrium Green’s function (NEGF) . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Origin of the giant TER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Giant modulation of the barrier height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 Switching time, endurance, and data retention . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter3: Low-ResistanceP-TypeContactsto2Dtransistor 30
3.1 Contact resistance for p-type TMD transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 Ab initio DFT Simulations of WSe2 P-Type Contacts . . . . . . . . . . . . . . . . . . . . . . 34
3.3 Computational Screening of P-Type Contact Materials . . . . . . . . . . . . . . . . . . . . . 36
3.4 Multiscale Simulation and Device Performance Projection . . . . . . . . . . . . . . . . . . 38
Chapter4: Conclusions 41
Bibliography 43
iii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ListofFigures
1.1 Schematic representation of the potential profile in a M1-FE-M2 junction . . . . . . . . . . 5
1.2 Three possible transport mechanism with ultrathin ferroelectrics. . . . . . . . . . . . . . . 6
1.3 Crystal structure of CIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Thermal evolution of the different copper site occupancies and the corresponding
probability density contour in CIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 The vdW ferroelectric tunneling junction device structure . . . . . . . . . . . . . . . . . . 12
2.2 Material properties of vdW ferroelectric tunneling junction device . . . . . . . . . . . . . . 13
2.3 The ferroelectric polarization in CIPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Electrical characteristics of the vdW FTJ with semi-metallic graphene contact. . . . . . . . 14
2.5 The capacitance model for electrostatic calculation. . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Origin of the giant TER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7 Band structure of bulk CIPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8 Origin of the giant TER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.9 Effect of the graphene semi-metallic contact on the vdW FTJ characteristics. . . . . . . . . 25
2.10 Performance of the vdW FTJ as memory devices. . . . . . . . . . . . . . . . . . . . . . . . . 28
2.11 The optical microscope image of 5× 7 array with 35 FTJ devices. . . . . . . . . . . . . . . 29
3.1 Schematic of a monolayer WSe2 nanosheet transistor. . . . . . . . . . . . . . . . . . . . . . 31
3.2 Strategies for p-type WSe2 contact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3 Interface charge density and electrostatic potential profiles. . . . . . . . . . . . . . . . . . . 35
iv
3.4 Band structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5 Conduction bands and valence bands for TMDC, bulk semimetal, and vdW materials. . . . 36
3.6 Multiple physical parameters from DFT simulations. . . . . . . . . . . . . . . . . . . . . . . 37
3.7 Multiple physical parameters from DFT simulations. . . . . . . . . . . . . . . . . . . . . . . 37
3.8 Schemetic of the model at the contact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9 Device electrical performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 I-V transport of simulated devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
v
Abstract
This work focuses on two significant breakthroughs in the field of memory and computing technolo-
gies. Firstly, a ferroelectric van der Waals (vdW) heterojunction based on layered CIPS (copper indium
thiophosphate selenide) demonstrates a remarkable giant barrier height modulation and record-high tun-
nel electroresistance. The polarization in CIPS enables a substantial Fermi-level shift of 1 eV at the interface
to provide the giant barrier height modulation. This devices demonstrates excellent reliability tests includ-
ing retention, endurance, switching time, and uniformity for 5x7 array with 35 devices. This FTJ shows
immense potential for high-performance memory and computing applications. Secondly, computational
screening and design techniques are employed to identify low-resistance p-type contacts to 2D semicon-
ductors, specifically WSe2. Van der Waals metallic contacts and bulk semimetallic contacts are found to be
promising strategies for achieving Schottky-barrier-free and low-contact-resistance p-type contacts. The
simulations reveal reduced metal-induced gap states, negligible Schottky barrier height, and impressively
small contact resistance. This breakthrough not only enhances our fundamental understanding of p-type
contacts but also provides a practical pathway for incorporating 2D channel materials in advanced logic
technology. Therefore, these advancements contribute to the future development of high-performance
memory and computing devices. The ferroelectric vdW heterojunction offers a revolutionary approach
with significant barrier height modulation, while the design of low-resistance p-type contacts addresses a
critical challenge in the industry. These findings pave the way for the utilization of novel materials and
interfaces in shaping the future of memory and computing technologies.
vi
Chapter1
Introduction
Recent developments in memory and computing technologies have experienced remarkable break-
throughs, driven by innovative materials and design strategies. Two remarkable projects have emerged,
showcasing their potential to revolutionize these fields and open new avenues for high-performance de-
vices. The first project introduces a novel ferroelectric van der Waals (vdW) heterojunction, while the
second project addresses the critical challenge of low-resistance p-type contacts to two-dimensional (2D)
semiconductors. Both endeavors exhibit a positive attitude and a promising tone, highlighting their con-
tributions to the future of memory and computing.
In the quest for improved memory and computing devices, the ferroelectric vdW heterojunction based
on layered CIPS (Copper Indium Phosphorus Sulfide) emerges as a game-changing innovation. Unlike
previous studies limited by small barrier height modulation, this project demonstrates an extraordinary
barrier height modulation of 1 eV due to the asymmetry of the junction. The reversal of the ferroelectric
polarization field in CIPS triggers a substantial Fermi-level shift of 1 eV at the interface between CIPS
and monolayer graphene. This remarkable achievement, accompanied by impressive performance metrics
in terms of retention, endurance, switching time, and uniformity, positions the ferroelectric vdW hetero-
junction as a potential candidate for high-performance ferroelectric and multiferroic materials in memory
1
and computing applications. With its ability to modulate barrier heights to such a significant extent, this
project holds tremendous promise for shaping the future of memory and computing devices.
Concurrently, the pursuit of low-resistance p-type contacts to 2D semiconductors has been a critical
challenge in advancing advanced logic technology. In response, the second project employs computa-
tional screening and design strategies to identify realistic pathways for achieving Schottky-barrier-free
and low-contact-resistance p-type contacts to 2D semiconductors, specifically focusing on WSe2. The
investigation introduces two groundbreaking contact strategies: van der Waals metallic contacts, exem-
plified by 1H-NbS2, and bulk semimetallic contacts, represented by Co3Sn2S2. These strategies offer a
practical solution to the long-standing challenge, as simulations demonstrate reduced metal-induced gap
states, negligible Schottky barrier height, and impressively small contact resistance. Furthermore, the de-
velopment of Co3Sn2S2 as a new semimetal contact material adds weight to the potential of this approach.
By addressing the limitations of p-type contacts, this project significantly contributes to the future devel-
opment of high-performance memory and computing devices based on 2D semiconductors.
In conclusion, these two projects present a positive outlook and a promising tone for the future of
memory and computing. The ferroelectric vdW heterojunction project introduces a revolutionary struc-
ture capable of high giant barrier height modulation, while the low-resistance p-type contacts project
tackles a critical challenge in the industry. These breakthroughs hold the potential to enhance device per-
formance, functionality, and reliability, paving the way for transformative advancements in memory and
computing technologies. The convergence of innovative materials, computational design strategies, and
impressive performance metrics sets the stage for a new era of memory and computing devices poised to
redefine the boundaries of technological possibilities.
2
1.1 VanDerWaalsmaterial
Advancements in memory and computing technologies have seen significant breakthroughs, driven
by innovative materials and design strategies. The emergence of van der Waals (vdW) materials has par-
ticularly captured attention, offering immense potential to revolutionize electronic devices and unlock
high-performance functionality.
Van der Waals materials possess unique characteristics that make them highly attractive for elec-
tronic applications. Their atomically thin layers can be easily stacked and combined with other materials,
providing precise control over interface properties. This control enables tailored device architectures and
enhanced performance by manipulating electronic, optical, and mechanical properties.
The weak interlayer coupling in vdW materials preserves the intrinsic properties of each layer, re-
ducing undesirable effects such as carrier scattering and energy dissipation. This inherent decoupling
improves device efficiency and reduces power consumption.
Furthermore, van der Waals materials exhibit exceptional mechanical flexibility and resilience, allow-
ing them to withstand bending and stretching without compromising electronic properties. This flexibility
opens doors for the development of flexible and wearable electronic devices that conform to various shapes
and surfaces.
The extensive library of vdW materials with diverse electronic characteristics enables customization
and optimization of device properties. By selectively combining these materials, researchers can tailor
bandgap, carrier mobility, and other parameters to meet specific application requirements. This versatility
enables the design of high-performance transistors, sensors, memory devices, and other components with
improved speed, lower power consumption, and enhanced functionalities.
In conclusion, van der Waals materials represent a paradigm shift in electronic device design. Their
atomically thin layers, decoupled interlayer interactions, mechanical flexibility, and diverse material li-
brary provide unprecedented opportunities for achieving high-performance electronic devices. Harnessing
3
the potential of these materials promises to unlock new frontiers in memory and computing technologies,
driving advancements in device performance, energy efficiency, and functionality across a wide range of
applications.
1.2 Backgroundforferroelectricbasedmemory
Computer memory which is nonvolatile and allows to store the information even when power off
plays more and more important roles in the modern computing. One of the promising candidates for
next-generation computer memory is the ferroelectric based memory. It retains the information by its
ferroelectric polarization with the advantages of fast write speed, write/read cycle endurance, and low-
power consumption. The basic structure of these ferroelectric based memory is the thin ferroelectric
material film sandwiched by two electrodes. Thereby, the polarization of the ferroelectric could be switched
by the external field on the electrodes. One of the applications is ferroelectric random access memories
(FeRAMs). Though this structure of ferroelectric based memory is simple, the development is hindered due
to the capacitive readout which limits the scalability of gigabit densities[1, 2]. Moreover, the destructive
readout causes the problem of power consumption. For another application, ferroelectric diodes, it is the
non-destructive readout[3]. It controls the current through the thick ferroelectric film inside by modifying
the ferroelectric polarization at the ferroelectric/electrode interface. However, the lower current caused
by the large thickness of the ferroelectric film becomes the challenges for miniaturing the memory device.
After shrinking down the thickness of ferroelectric film to several nanometers, the electronic conduction
is increased with quantum-mechanical tunneling through the ferroelectric barrier. The devices with this
mechanism is called ferroelectric tunnel junction (FTJ).
In this introduction, we will simply introduce the working mechanism behind FTJ ,its development
and copper indium thiophosphate (CuInP
2
S
6
).
4
1.3 ThemechanismofFTJ
Figure 1.1: Schematic representation of the potential profile in a M1-FE-M2 junction. The polarization
pointing to the right (a) and pointing to left (b), assuming that M1 has higher efficiency. The dash lines
show the average potential seen by transport electrons tunneling across the ferroelectric barrier. TheE
F
represents the Fermi energy.
1.3.1 Ferroelectrictunneljunctionanditselectroresistance
A simple model for an ultrathin ferroelectric film sandwiched between two different metal electrodes
(M1 and M2) is adopted to explain the electroresistance effect in ferroelectric tunnel junction[4]. The
asymmetric screening effect from the polarization results in the different potential profiles which lead to
the different average barrier height and current level. In the figure 1.1 , the band schematic of ferroelectric
tunnel barriers is illustrated for elaborating the mechanism[1]. The electrons near the interface screen
the polarization which cause the potential change. For the sandwiched ultrathin ferroelectric film with
two different electrodes, the potential profile changes are different by the strength of the screen. Here, we
assume initial potential barrier is rectangular with identical barrier heights for both left and right as well
5
as the left electrode with metal1 (M1) having higher screen efficiency. In the left figure (low barrier height),
the polarization points to right on metal2 (M2). It causes additional electrostatic potential at the interface of
M2 and ferroelectric film which the polarization point to, and vice versa. Due to higher screen efficiency of
M1, it brings about less potential profile change comparing to the right electrode(M2). Hence, the average
barrier height is lower. On the other hand, in the other orientation of polarization, the additional potential
is on the opposite side. With the same asymmetric screen effect on M1 and M2, the different variation of
the potential on M1 and M2 gives rise to large average barrier height. This is the main mechanism for
FTJ. Because the screening length can be significantly different by optimized electrodes, the polarization
reversal in the ferroelectric barrier provides the potential to yield few orders change of resistance leading
to the existence of stably resistive states.
1.3.2 Transportmechanisms
Figure 1.2: (a) Band diagram with three possible transport mechanisms: direct tunneling (DT), Fowler-
Nordheim tuneeling (FNT), and thermionic emission (TI). (b) Transport characteristic of current densities,
J versus voltage, V
DC
for three transport mechanisms: (DT), (FNT), and (TI) through a 3.2 nm thickness
ferroelectric.
6
Though the direct tunneling mechanism is discussed above as the main mechanism, not all the ultra-
thin ferroelectric film devices deal with direct tunneling. D. Pantel and M. Alexe proposed three possible
transport mechanisms: direct tunneling (DT), Fowler-Nordheim tunneling (FNT) and thermionic emis-
sion (TI) [5]. To differentiate its transport mechanism, it can be identified by voltage and temperature
dependencies of the current. For thermionic emission, its current has strong temperature dependence.
Nevertheless, the tunneling including direct tunneling and Fowler-Nordheim tunneling is dependent on
voltage without temperature dependence[6]. When the film thickness is thin at large voltage operation,
the barrier becomes triangle and it is in the Fowler-Nordheim tunneling regime as figure 1.2.
1.4 Ferroelectricpolarizationcontrolledresistiveswitching
The initial concept of FTJ was proposed in 1971 by Esaki [7]. It got more attention after theoretical
prediction of its hysteretic current to voltage curve and tunneling electroresistance[4, 8]. However, it is a
challenge to experimentally demonstrate ferroelectricity on ultrathin ferroelectric film which is compati-
ble with quantum mechanical tunneling. Later, it was found that high-quality epitaxial films should grow
on suitable substrates to keep ferroelectric properties at even nanoscale thickness[9]. In the early 2000s,
several reports showed the ultrathin ferroelectric films with good quality in the experiment. For example,
J. Rodriguez Contreras et. al firstly demonstrated a FTJ with TER=4 with ultrathin films of PbZr
0.5
Ti
0.48
O
3
sandwiched between SrRuO
3
and Pt fabricated on SrTiO
3
substrate at 4.2 K and 300 K in 2003 [10]. Later,
V.Garcia et al. presented resistive readout of the polarization state with conductive-tip atomic force mi-
croscopy (C-AFM) and TER=750 at 3nm ferroelectric film of BaTiO
3
[11].
After decades studying, solid-state FTJ with different ferrorelectric film such as PbZr
0.5
Ti
0.48
O
3
,
BaTiO
3
, BiFeO
3
, HfO
2
, and PbZr
0.2
Ti
0.8
O
3
have been demonstrated. There are several performance met-
rics such as TER(On/Off ratio), write energies, data retention, scalability, endurance, and CMOS technology
compatibility for considering a promising candidate for new-generation non-volatile memories. For these
7
FTJs as non-volatile memories, it generally can be divided into two types of ferroelectric materials: ABO-
type perovskites such as BaTiO
3
and PbZr
0.2
Ti
0.8
O
3
, and binary oxides such as HfO
2
and Hf
0.5
Zr
0.5
O
2
(HZO). For ABO-type perovskite FTJs, by combining the additional semiconducting layer in a complex
structure, the TER can still only reach around 10
6
[12, 13]. Besides, ABO-type FJTs should be grown on
perovskite substrate which limits its compatibility with the existing electronic technology i.e. CMOS tech-
nology. Although for HfO
2
and HZO based FTJs, they are compatible with the electronics fabrication, the
TERs in these FTJs are below 100 due to the limitations of the traditional FTJ modulation mechanism and
the intrinsic material properties[14, 15].
Figure 1.3: Crystal structure of CIPS from (a) b axis, (b) layer normal , and (c) from a axis. (d) The side view
of two layer of CIPS with the vdW gap
1.5 Copperindiumthiophosphate(CuInP
2
S
6
)
Besides the traditional ABO-type perosvskite and binary type, it was found that the ferroelectric
property appears in the two-dimensional (2D) van der Waals (vdW) materials recently such as α -In
2
Se
3
and CuInP
2
S
6
(CIPS). Below the Curie temperature (T
c
), the polarization can be switched by an external
8
field. Among them, CIPS is one of the most representative and potential materials because its transition
temperature is above the room temperature which is potential for electronics applications and CIPS is
compatible with existing industrial fabrication process. Its polarization is out-of-plane polarization. Also,
it belongs to the family of transition metal thio/selenophosphates (TPS). For TPS, its metal cations are
embedded in the lattice frame work of thioplsphate (P
2
S
6
)
4− or selenophosphate (P
2
Se
6
)
4− anions. Their
chemical formulas can be written as[16]:
M
4+
[P
2
X
6
]
4− , [M
2+
]
2
[P
2
X
6
]
4− , orM
1+
M
3+
[P
2
X
6
]
4− whereX=SorSe
Hence, for CIPS, its M
1+
and M
3+
are Cu
I
and In
III
, respectively. In the ABC close-packed stacking of
sulfur framework, the metal cations(Cu and In), and the P-P pairs fill the octahedral voids as the figure
1.3. In figure 1.3 (b), it shows that the Cu and In will form the triangular pattern with P-P pair in the
layer. Also, the bulk is vertically stacked and the week interaction with vdW interaction is shown in figure
1.3 (c-d). Because Cu and P-P pair change their site from one layer to the other layer, it consists of two
adjacent layers in a complete unit cell as shown in figure 1.3 (d) [17].
The out-of-plane polarization originates from the movement of the spatial instability of the Cu
I
cation.
Generally, the Cu
I
prefers to stay in the lower coordination instead of the center of the S octahedron.
Maisonneuve et al. revealed the thermal evolution of the Cu
I
cation in the sublattice [18]. For two Cu
I
sites, Cu
Iu
means the shift upward form the middle of the layer; similarly, Cu
Id
means the shift downward
from the middle of the layer. As shown in figure 1.4 [18], the Cu
Iu
is 100% at 153K. It implies that the
Cu
Iu
is fully filled and this site is the ground state of the CIPS ferroelectric phase at low temperature
(153K). When the temperature increases from 153K to 305K, the occupancy of Cu
Iu
slightly decreases from
100% to 85%. Besides, the Cu
Id
is gradually occupied from 298K. Above the T
c
(315K), the occupancy
of Cu
Iu
and Cu
Id
become the same. Hence, below the T
c
, the displacive instability of Cu
I
results in the
9
Figure 1.4: Thermal evolution of the different copper site occupancies and the corresponding probability
density contour in CIPS. The different probability density of Cu1, Cu2, and Cu3 in temperature of 153K,
243K, 298K, 305K, 318K, 353K.
ferroelectricity. Moreover, in order to retain the stability, In
III
cation in the adjacent S octahedron should
displace in opposite direction of Cu
I
, so it results in a second sublattice.
10
Chapter2
Hightunnelingelectroresistanceinferroelectrictunnelingjunction
In this work, we propose a ferroelectric vdW heterojunction. The layered CIPS is adopted as the fer-
roelectric barrier in FTJs sandwiched between the electrode of Chromium (Cr) and monolayer graphene
(1LG). Comparing to the previous studies based on barium titanate or hafnium dioxide which is limited
to their small barrier height modulation around 0.1 eV, the FTJs in this work demonstrated large barrier
height modulation of 1 eV due to its asymmetric junction. Also, the giant TER 10
7
is exhibited in this
work. To study the origin of this large barrier height modulation, the Fermi-level shift of graphene is dis-
cussed. It implies that reversal of the ferroelectric polarization field in CIPS results in a Fermi-level shift of
1 eV in interface of 1LG and CIPS due to the low density of states in graphene near its Dirac point and its
small quantum capacitance. Furthermore, performance metrics such as the retention, endurance, switch-
ing time, and uniformity show that this CIPS based FTJ has good reliability. This semimetal-ferroelectric
vdW structure provides a new prototype for high giant barrier height modulation in FTJ devices. It is a po-
tential candidate for high-performance ferroelectric and multiferroic materials for memory and computing
applications.
11
2.1 ThevdWFTJstructureandelectricalcharacteristics
Figure 2.1: vdW ferroelectric tunneling junction device structure (a) The schematic of the
Cr/CIPS/Graphene FTJ on the SiO
2
/Si substrate. The G represents graphene. (b) The optical microscope
image of vdW structure Cr/CIPS/Graphene. The graphene, CIPS, Chromium, and gold are labeled. The
scale bar is 2µ m.
The schematic diagram of vdW FTJ and the optical image are shown in figure 2.1 (a) and (b), respec-
tively. The layered CIPS which Raman spectrum is shown in figure 2.2 (a) inside the hetrojunction is used
as the ferroelectric tunneling barrier for FTJ [19, 20]. The Cr and graphene are utilized as the asymmetric
electrodes as shown in figure 2.1 (a). The material compositions in Cr/CIPS/grahphene heterojunction are
further examined by the transmission electron microcopy (TEM) and electron energy loss spectroscopy
(EELS) images in figure 2.2v(b).
12
Figure 2.2: Material properties of vdW ferroelectric tunneling junction device (a) Raman spectrum of the
CIPS sample. (b) High resolution transmission electron microscopy (TEM) and electron energy loss spec-
troscopy (EELS) images of a typical vdW FTJ. The layered structure and the material compositions are
clearly identified. The scale bar is 4 µ m.
To characterize the ferroelectric properties in the CIPS film, the piezoelectric force microscopy (PFM)
measurement and capacitance versus voltage (C-V) measurement under the same circumstance of 20 nm
thickness CIPS and 300 kHz frequency at room temperature are employed and the results are represented in
figure 2.3. In figure 2.3 (a), both amplitude and phase in the PFM measurement demonstrate the hysteresis
loops which proves the existence of the ferroelectricity in CIPS. In figure 2.3 (b), C-V measurement shows
a typical butterfly shape with coercive field about 0.14 V/nm, which is consistent to the result of PFM on
figure 2.3 (a). Hence, the ferroelectricity of the CIPS at room temperature is verified by the result of PFM
and C-V measurement. Also, the remnant polarization (P
r
) of this CIPS sample is obtained as∼ 8µ C/cm
2
by integrating the C-V characteristics.
13
Figure 2.3: The ferroelectric polarization in CIPS. (a) The out-of-plane amplitude and phase measurements
obtained by piezoelectric force microscopy (PFM) on an Au/CIPS/Cr test structure. (b) The capacitance-
electric field characteristics obtained using capacitance-voltage (C-V) measurement on an Au/CIPS/Cr test
structure. The CIPS sample is 20 nm thick in both (a) and (b). Both measurements in (a) and (b) were
carried out at 300 kHz at room temperature.
Figure 2.4: Electrical characteristics of the vdW FTJ with semi-metallic graphene contact. (a) The resistance
v.s. pulse-voltage loop measured by applying the voltage pulse train as shown in the inset. (b) The current-
voltage characteristics of the vdW FTJ with 4 nm CIPS and monolayer graphene contact showing TER
above 107 between the on and off states. The dashed lines show the NEGF simulation results of the device
characteristics, which is consistent with the experimental measurements.
14
The electrical characteristics of a typical Cr/CIPS/graphene vdW FTJ with a 4nm thick CIPS layer
and monolayer graphene as one side of electrodes is shown in figure 2.4. In figure 2.4 (a), The tunneling
resistance of FTJ is swept and plotted of the corresponding switching voltage pulse. The applied voltage
pulses to change the ferroelectric polarization within the CIPS layer shows in the inset of figure 2.4 (a)
from 0 V to 4.5 V, 4.5 V to 0 V, 0 V to -5.5 V, and finally back to 0 V. The corresponding tunneling resistance
changes of FTJ and the hysteresis loops move counterclockwise which is indicated by the light blue arrow
with a 0.4 V read voltage pulse. A large TER above10
7
can be obtained from these high and low resistance
states in this Cr/CIPS/graphene structure. The current versus voltage characteristics of the FTJ device with
a 4nm CIPS is shown in 2.4 (b). The high resistance state from the lower OFF current and low resistance
state from higher ON current are separately set by the voltage pulse of 4.5 V and -5.5 V which is consistent
with resistance-pulse voltage loop result. After setting each state(ON/OFF), to avoid flipping the direction
of the ferroelectric polarization in the CIPS during the measure, the voltage just sweeps within a relatively
small range, i.e., from -1 to 1 V. From 2.4 (b), the lower OFF current showed in blue is ultralow around
10
− 11
A; however, the ON current showed in red is sufficiently high ( 10
− 5
) in this heterostructure. Hence,
the corresponding TER form ON/OFF states achieves seven orders of magnitude. This colossal TER is the
highest among all FTJs that have been demonstrated across different ferroelectric material systems.
15
2.2 Originoftheultra-highTER
To understand the results we got in section 2.1, quantum transport simulations based on the non-
equilibrium Green’s function (NEGF) formalism were performed. The details will be imply introduced in
section 2.2.1.
2.2.1 Non-equilibriumGreen’sfunction(NEGF)
The electrical characteristics of the FTJ is simulated using the NEGF formalism with the effective mass
approximation. For simplicity, ballistic transport is assumed due to the small tunneling barrier thickness.
The retarded Green’s function at energyI can be expressed as,
G(E)=[(E+i0
+
)I− H− Σ g
− Σ m
]
− 1
(2.1)
whereΣ g
andΣ m
are the graphene contact and metal contact self-energies, respectively, and the Hamilto-
nian matrixH is obtained by discretizing
ˆ
H =− (ℏ
2
/2m
∗ )∇
2
+E
c
(⃗ r) . Herem
∗ is the effective mass, and
E
c
(⃗ r)is the conduction band edge in the CIPS ferroelectric layer, which can be obtained by solving an elec-
trostatic capacitance model with the polarization charge as described later. The effective mass m
∗ along
the vertical direction of CIPS is assumed to be 1.3m
0
where m
0
is the free electron mass, and the thick-
ness of the CIPS ferroelectric layer is 4 nm. The current can be computed by using the Landauer-Büttiker
formula,
I =
2q
h
Z
dE[f
g
(E)− f
m
(E)]T
r
(E), (2.2)
whereq is the elementary electron charge, h is the Planck constant,f
g
andf
m
are the graphene contact
and metal contact Fermi-Dirac distribution functions, respectively. The transmission can be expressed as,
T
r
(E)=Trace(GΓ g
G
+
Γ m
), (2.3)
16
whereΓ g,m
=i(Σ
g,m
− Σ +
g,m
).
To obtain the band profile, an electrostatic model needs to treat the following effects: (i) polarization
charge of the ferroelectric layer, (ii) charging of the graphene contact layer, (iii) Thomas-Fermi screening
of the metal contact. The conduction band edge in CIPS can be expressed as E
c
(x) = E
c0
(x)− qV(x),
whereE
c0
(x) is the conduction band edge atV(x)=0, andV(x) is the electrostatic potential. In the CIPS
layer, bothE
c0
(x) andV(x) are linearly dependent on the positionx, defined along the vertical direction,
and the values at the interfaces are sufficient to determine E
c0
(x) and V(x) in CIPS. The E
c0
(x) value
at the graphene/CIPS interface is determined by the difference between graphene and CIPS affinities, and
the value at the metal/CIPS interface is determined by the difference between the metal work function and
CIPS affinity.
To calculate V(x) a capacitor model as shown in figure 2.5, is constructed. The metal and CIPS
electrostatic capacitance values areC
m
= ϵ 0
/a
0
and C
FE
= ϵ 0
ϵ r,CIPS
/d
CIPS
, where ϵ 0
is the vacuum
dielectric constant,a
0
≈ 2 nm is the screening length of the metal contact,ϵ r,CIPS
is the relative dielectric
constant of the CIPS layer, andd
CIPS
is the CIPS layer thickness. The CIPS layer thicknessd
CIPS
is 4 nm
with the ferroelectric polarizationP
r
≈ 8µC/cm
2
.
The nonlinear capacitance of the graphene layer is due to its quantum (or density-of-states (DOS))
capacitance, which relates the capacitor chargeQ
gr
its voltage dropV
gr
through integration over density
of states,
Q
gr
=q
Z
qVgr
0
D(E)dE, (2.4)
whereD(E) the graphene density of states, which is approximately linearly dependent on energyE. De-
generate carrier statistics is used here for simplicity, which is a good approximation because the magnitude
of V
gr
is typically larger than the thermal voltage. The ferroelectric polarization is treated as the nodal
charge on the nodes n1 and n2 in the capacitance model as shown in figure 2.5. It is noted that due to
the low DOS of graphene layer near its Dirac point and small quantum capacitance, the voltage at node
17
n
2
can be modulated significantly, which influences the barrier height at the graphene/CIPS interface, as
schematically shown in figure 2.6.
Figure 2.5: The capacitance model for electrostatic calculation.V
a
is the applied voltage on the C
r
contact,
and C
m
, C
FE
, and C
g
are the capacitance of metal, CIPS, and graphene layer, respectively.
18
2.2.2 OriginofthegiantTER
Figure 2.6: (a) The band diagram for both the on and off states of the vdW FTJ operation. The built-in
polarization field in the CIPS is shown with cyan arrows, and the tunneling current is indicated by the
pink arrows. (b) I-V characteristics of both the on and off states at temperatures of 240 K, 190 K, 130 K and
80 K. The experiment data is shown in solid lines and the NEGF simulation results are shown in dashed
lines. The on state currents at the four different temperatures are shown in linear scale in the inset.
The simulation I-V characteristics result of NEGF are shown by the dashed lines in 2.6 (b) which is
consistent with the experimental result. Hence, the simulation result of the FTJ device implies that the
large TER ratio can be attributed to the efficient modulation of the Fermi level in the graphene contact by
the ferroelectric polarization field, and large effective mass in the vertical direction of the van der Waals
CIPS layer. Comparing to a metal or heavily doped semiconductor contact, a monolayer graphene contact
has a low quantum capacitance near its Dirac point resulting in the highly efficient modulation of the
barrier height. Therefore, by adopting the asymmetric contacts with monolayer graphene on one side
and metal on the other side as the schematic in the figure 2.1 (a), it can lead to a large modulation of the
average barrier height when the ferroelectric polarization inside CIPS is switched. Actually, the influence
of the polarization to the tunneling current is exponential. The band diagram of on and off states are
schematically shown in figure 2.6 (a). The build-in polarization within the CIPS tunneling barrier induces
charges at both interfaces: graphene-CIPS and Cr-CIPS. For the on state (the left figure of figure 2.6 (a)),
19
the induced charges on the graphene by the polarization dopes graphene from relatively intrinsic to n-
type. It leads to the Fermi level shift from relatively intrinsic to well above Dirac point as shown in left
side of figure2.6 (a). The increasing Fermi level decreases the average barrier height, resulting in higher
probability for the electrons to tunnel through the CIPS. As a result, the tunneling current is larger which
provides the on state. On the other hand, when the polarization of FTJ is on the reverse direction as shown
in the right figure of the figure 2.6, the positive charges are induced and dopes the graphene from relatively
intrinsic to p-type. It causes the Fermi-level of graphene to decrease from relatively intrinsic to well below
the Dirac point resulting in the the increase of average barrier height in the figure 2.6 (a). The higher
average barrier height hinders the tunneling current in the tunneling barrier leading to the significantly
low current on off state ( 10
− 12
A). The shift of graphene Fermi level for both on and off state due to the
opposite orientations of polarization gives rise to the colossal TER we presented in section 2.1.
Furthermore, a large effective mass in the vertical direction of the layered CIPS material due to weak
vdW bonding can increase the TER ratio exponentially as the discussion in section 2.2.1. According to the
first principle calculation, the out-of-plane effective mass of CIPS ( 1.3 m
0
, wherem
0
is the free electron
mass) is about 3 times of that in the in-plane crystal direction as shown in figure 2.7 which is similar to
the case in other vdW layered materials, such as black phosphorus[21] and MoS
2
[22]. Thus, the unique
properties of both the two-dimensional graphene and CIPS materials, therefore, are crucial for achieving
the high TER ratio.
There are three possible transport mechanisms in ultra-thin FTJs: Fowler–Nordheim (FN) tunneling,
direct tunneling, and thermionic emission as we mentioned in section 1.3.2. The FN tunneling usually dom-
inates at large voltage, which is not observed here in figure 2.4 and figure 2.6 (b). Hence, the mechanisms
could be either direct tunneling or thermionic emission. The main difference between direct tunneling
and thermionic emission is the temperature dependency. To verify the transport mechanism within this
FTJ device, the temperature dependent current to voltage (I-V) measurement is conducted in the figure
20
2.6 (b). It is apparent that the there is almost no temperature dependence of current for both on state and
off state within a large range from temperature 80 K to 240 K. The NEGF simulation results, as shown
by the dashed lines in figure 2.6 (b), also indicate weak temperature dependence, in agreement with the
experimental data. Therefore, it confirms that the dominated transport mechanism here is the direct tun-
neling, because as a thermally activated process, the thermionic emission mechanism should have strong
temperature dependence in the I-V characteristics.
21
Figure 2.7: Band structure of bulk CIPS. The inset gives the high symmetry path of the first Brillouin zone.
The effective mass of electron and hole along the out-of-plane direction ( Γ -Z) and in-plane direction (Γ -Y)
are labeled.
2.3 Giantmodulationofthebarrierheight
To confirm the giant modulation of the barrier height and the Fermi-level shift we discussed in pre-
vious section, Raman spectroscopy measurement and the Kelvin probe force microscopy (KPFM) is per-
formed. First, the result of Fermi level shift in the graphene contact by Raman spectroscopy measurement
illustrated in the figure 2.8 (a). The both G mode and 2D mode of the monolayer graphene under the CIPS
material have the shifts of 12.4 and 18.9 cm
− 1
comparing to only the monolayer graphene, respectively.
These shifts are attributed to the changes of the Fermi level of monolayer graphene due to the ferroelec-
tric polarization of CIPS. Another possible external perturbation that could result in the similar shifts is
the compression strain [23]; however, it’s precluded in this heterosturcture by thermal annealing prior
22
Figure 2.8: (a) Top panel: Raman spectra of bare monolayer graphene (1LG, blue) and 1LG under CIPS
(yellow) in the wavelength range of the G and 2D modes under the excitation of 532 nm light. The dashed
lines are guide to the eyes. Bottom panel: The corresponding Raman frequency mappings showing the shift
in the G (left bottom) and 2D (right bottom) modes of 1LG and nearby 1LG+CIPS. (b) The surface potential
images of the 1LG stacked on top of CIPS/Au after the ferroelectric polarization in the CIPS layer is set to
be pointing downwards (n-type doping in graphene, left top) and upwards (p-type doping in graphene, left
bottom). The scale bar is 10µ m. The line plots of the surface potential along the corresponding cut-lines
in the left panel are shown in the right panel for the two cases.
to the measurenment which can relax the strain [24]. Besides, the shifts in the Fermi level (∆ E
f
) of the
monolayer graphene can be quantified by the equation[23, 25, 26]:
|(∆ E
f
)|≈ ∆ ω(G)/21≈ 0.5eV where∆ ω(G)istheshiftintheGmodepeak (2.5)
Besides the shifts on the G mode and 2D mode, the shift of Fermi level also presents the decrease of the
intensity ratio between the 2D mode and G mode (I(2D)/I(G)) which is also illustrated in the figure 2.8 (a).
This further confirms the doping effect on the monolayer graphene[27]. This high doping level is primarily
due to the built-in electric field in the CIPS layer acting on the monolayer graphene rather than from the
charge transfer between the monolayer and CIPS, which even if present can only cause very small doping
effect in 2D heterostructures[28]. Because the Raman peak shift resulting from the doping effect can be
distinguished between electron or hole doping, the∆ E
f
can be either positive or negative depending on
whether the Fermi level shifts above or below the Dirac point (n-type or p-type doping)[26]. Therefore,
23
according to the equation 2.5, the total Fermi level shift for on and off states based on the estimation of
|∆ E
f
|≈ 0.5 eV will be 2 |∆ E
f
|≈ 1 eV.
To further verify the Fermi level shift in graphene due to the ferroelectric polarization within CIPS,
the second method, KPFM measurement is used to probe the change in the surface potential, i.e. change
in the Fermi level. After the monolayer graphene is stacked on the CIPS and gold surface, the polarization
direction of the CIPS layer is switched to get two different states in the figure 2.8 (b). The polarization in the
CIPS layer is deterministically switched by the conductive tip in the atomic force microscopy (AFM) system
to change the doping type in the monolayer graphene. The surface potential of the monolayer graphene
on two different states are quite different. For the p-type doped monolayer graphene, the surface potential
is 0.1 eV higher than the reference gold surface; however, for the n-type doped monolayer graphene, the
surface potential is 1.1 eV higher than the same reference gold surface. Hence, it shows that the change
in the Fermi level for p-type and n-type in the monolayer graphene is about 1 eV. This KPFM provides the
directly evidence of the large modulation of 1eV due to the ferroelectric polarization which is consistent
to the result of the Raman spectroscopy measurement. This large Fermi level shift can be originated from
the properties of graphene: the small density of states and low quantum capacitance in graphene near
the Dirac point. In addition, the numerical simulation result from NEFG of the FTJ device indicates that
theP
r
of 8µ C/cm
2
is sufficient for Fermi level shift of 1eV. The better coupling observed here compared
to ABO-type ferroelectrics couple with graphen [29, 30] is reasonable due to the all-vdW nature of the
graphene/CIPS interface, which is expected to have minimal dangling bonds, surface reconstruction and
defect-mediated interfacial charges.
24
Figure 2.9: Effect of the graphene semi-metallic contact on the vdW FTJ characteristics. The current-
voltage characteristics of both the on and off states for the (a) bilayer graphene/CIPS/Cr and (b) Au/CIPS/Cr
FTJ heterostructures, respectively. These heterostructures are fabricated side-by-side on the same CIPS
sheet. The dashed lines outline the underlying bilayer graphene (purple) and Au (orange) bottom contacts
of the two heterostructures in the inset of (a). The top electrode is Cr in both devices. (c) The I-V charac-
teristics of three vdW FTJs with different graphene bottom contact thicknesses. (d) The dependence of the
TER on the thickness (in terms of the number of graphene atomic layers) of the graphene bottom contact.
The dash-dotted line is guide to the eyes.
To further verify the effect of the Fermi level shift in graphene on the TER, we fabricated both thin
graphene (bilayer) and metal (Au) bottom contacts side-by-side under the same CIPS sample with 4 nm
thickness. The two test structure for comparison share a common top metal electrode by Cr as illustrated
in the inset of the figure 2.9 (a). The current to voltage for these two test structures: graphene/CIPS/Cr
and Au/CIPS/Cr are plotted as figure 2.9 (a) and (b), respectively. The off state tunneling currents in both
structures are in similar level around pA. Nevertheless, the on current is notably different. The on current
25
of graphene/CIPS/Cr is about fewµ A. In contrast, the on of Au/CIPS/Cr is about few hundred pA, which
is about 4 orders of magnitude lower than the one with graphene as the electrode contact. Hence, the
structure of graphene/CIPS/Cr with graphene contact leads to much higher TER (∼ 10
6
) comparing to the
Au/CIPS/Cr structure without graphene contact(∼ 50). In figure 2.9 (c) and (d), the dependence between the
TER and graphene contact thickness is demonstrated. As the thickness of the graphene bottom contact is
increased from monolayer up to 21 layers in the vdW FTJs with the same CIPS thickness, the TER severely
decreases. Since the the increasing screening effect leads to smaller Fermi level shift while increasing
graphene contact thickness. Hence, it further verifies that the colossal TER is due to the large Fermi level
shift in the monolayer graphene contact.
2.4 Switchingtime,endurance,anddataretention
Figure 2.10 (a) shows the resistances of a graphene/CIPS/Cr vdW FTJ as a function of the switching
pulse width for both the write (off to on state) and erase (on to off state) operations. The write and erase
voltages used are -5.5 V and 4.5 V, respectively. Both the write and erase time are in the range of 10-50µ s,
which is at the similar level as other FTJs reported in the literature with comparable device size[31, 32].
The measured switching time is most likely limited by the parasitic impedance in the device due to the
relative large device size (2µ m× 2µ m). There is potential for further improving the switching speed of
these devices by scaling down the device size. Figure 2.10 (b) characterizes the data retention of this CIPS
vdW FTJ measured at room temperature. The resistance values of the device is measured by first setting
the device to the on (off) state and then read with 0.4 V bias. The TER of the device remains well above
10
7
after more than 8 hours, showing robust data retention performance. Figure 2.10(b) also shows the
extrapolation of the data retention based on the experimental results, and the 1-year and 10-years marks
are indicated on the time axis, revealing the great potential of the device for achieving long data retention
time. Figure 2.10 (c) shows the endurance measurement on this vdW FTJ over 5000 cycles. Within each
26
cycle, the FTJ is set to the on state by a -5.5 V pulse (10 ms) and read at a bias of 0.4 V, then set to the off state
using a 4.5 V pulse (10 ms) and read at a bias of 0.4 V. The TER remains well above 106 after 5000 cycles.
The extrapolation based on the experimental data indicates that that the TER can potentially remain above
10
6
up to 1 million cycles. To characterize the device uniformity and potential scalability, a 5× 7 vdW
FTJ array is fabricated with graphene contact (see figure 2.11 for the array image). The resistances of the
on and off states of these 35 FTJs and the corresponding TERs are shown in figure 2.10 d, showing good
device uniformity.
In summary, this vdW heterostructure (graphene/CIPS/Cr) enabling giant barrier height modulation
presents a new approach for achieving ultrahigh TER in FJT devices. Unlike the ABO-type perovskite FTJ
where the TER is enhanced due to the tunneling barrier width modulation by the ferroelectric polarization
field in the semiconducting contact, this vdW FTJ with ultra-thin CIPS and graphene contact relies on the
giant ferroelectric modulation of the tunneling barrier height to achieve record TER above10
7
. The close
to 1 eV synergistic Fermi level shift in graphene contact coupled with the switching of the ferroelectric
polarization in CIPS is further enhanced by the high carrier effective mass along the out-of-plane crystal
direction of CIPS. Furthermore, this ultrahigh TER is achieved in thin CIPS tunneling barrier∼ 4 nm thick,
which is favorable for low power device operation. This novel device mechanism capable of obtaining giant
barrier height modulation in tunneling junctions offers a new pathway towards realizing high performance
ferroelectric and multiferroic memory and computing technologies.
27
Figure 2.10: Performance of the vdW FTJ as memory devices. (a) Switch time of the FTJ from off state to on
state (write, orange line and square) and from on state to off state (erase, purple line and dots). The write
voltage is -5.5 V and the erase voltage is 4.5 V. (b) The retention property of the on (red circle) and off (blue
square) states. The dashed lines show the extrapolation of the data retention performance based on the
experimental results, and the 1-year and 10-years marks are indicated on the time axis. (c) The endurance
characteristic of the device. Experimental measurements were obtained for 5000 switching cycles. The
dashed lines show the extrapolation up to 1 million cycles. (d) The measured on state (yellow bars) and off
state (blue bars) resistances, and the TER (red bars) for 35 FTJ devices from a 5× 7 array.
28
Figure 2.11: The optical microscope image of 5× 7 array with 35 FTJ devices.
Table 2.1: Benchmark of the vdW FTJ memory cell with other memory technologies. The M in MFM and
MFS stands for the metal electrode, and the S in MFS stands for the semiconductor electrode. * represents
the simulation with 50 nm wide junction. Data from: [33, 40, 41, 42, 43, 44, 45, 46, 47, 34, 35, 36, 37, 38, 39]
29
Chapter3
Low-ResistanceP-TypeContactsto2Dtransistor
The rapid progress in the field of logic devices utilizing 2D semiconductors like MoS2, WS2, and
WSe2 has generated significant interest and anticipation due to their potential for practical applications.
However, the challenge of establishing low-resistance p-type contacts to these 2-D semiconductors remains
a critical issue. To address this challenge, it is crucial to identify high-work function metallic materials
that minimize the introduction of metal-induced gap states (MIGSs) at the metal/semiconductor interface.
In this study, we conducted systematic computational screening, employing ab initio density functional
theory and quantum device simulations, to identify novel metallic materials and their heterojunctions with
monolayer WSe2. Our analysis identifies two promising contact strategies: van der Waals (vdW) metallic
contact and bulk semimetallic contact. These strategies offer solutions for achieving Schottky-barrier-free
and low-contact-resistance p-type contacts for WSe2 p-type field-effect transistors (pFETs). Based on our
screening criteria, we identified several potential p-type contact materials, such as 1H-NbS2, 1H-TaS2, and
1T-TiS2 in the vdW metal category, and Co3Sn2S2 and TaP in the bulk semimetal category. Simulations
using these new p-type contact materials indicate reduced MIGS, minimal Fermi-level pinning effects,
negligible Schottky barrier height, and small contact resistance (reaching as low as 20Ω · µm ).
30
3.1 Contactresistanceforp-typeTMDtransistor
Two-dimensional (2D) semiconducting transition-metal dichalcogenides (TMDs) like MoS2, WS2, and
WSe2 have emerged as promising channel materials for advanced logic technology nodes. One significant
advantage of these materials is their ability to be thinned down to the monolayer limit (sub 1 nm) with-
out compromising carrier mobility, thereby enabling the scaling down of field-effect transistors (FETs)
to the sub-10-nm regime [48, 49, 50, 51] (figure 3.1). A recent theoretical investigation has demonstrated
that nanosheet (NS) FETs utilizing 2D semiconductors exhibit excellent current delivery capabilities, meet-
ing the requirements of the International Roadmap for Devices and Systems (IRDS) technology roadmap.
Moreover, these devices exhibit superior gate length scaling capabilities compared to Si NS FETs [52].
Significant advancements in wafer-scale material growth and transfer [53, 54, 55, 56], gate-stack process
development [57, 58, 59, 60], foundry-style process establishment [61, 62], and integrated circuit demon-
strations [63, 64] have progressively addressed the major technological challenges, propelling 2D semi-
conductor technology closer to practical production.
Figure 3.1: Schematic of a monolayer WSe2 nanosheet transistor. Finding a barrierless p-type contact is
the goal of this project
31
However, achieving low-resistance contacts for 2D semiconductor field-effect transistors (FETs) is a
significant challenge, serving as a crucial obstacle that hampers their practical applications. A contributing
factor to this challenge is the presence of metal-induced gap states (MIGSs), which have been observed at
the interfaces between metals and semiconductors, including 2D semiconductors. Metal-induced gap states
(MIGSs) emerge as the primary factor contributing to the Fermi-level pinning mechanism, resulting in the
formation of significant Schottky barriers and high contact resistance at metal/semiconductor interfaces.
[65]. Previous research has demonstrated that low density-of-states (DOS) semimetals, such as Bi and Sb,
can mitigate the MIGS issue for 2-D transition-metal dichalcogenides (TMDs), resulting in remarkable n-
type FET (nFET) performance [54, 66, 67, 68, 69, 70]. However, due to their relatively low work functions
(WFs), these semimetals may not be suitable as metallic contacts for p-type field-effect transistors (pFETs).
This is because the low work function results in a significant energy mismatch between the semimetal’s
work function and the hole affinities of 2D transition metal dichalcogenides (TMDs).
To achieve barrier-free p-type contacts, an essential approach is to identify high-WF metallic materials
that exhibit reduced or eliminated MIGS. In this study, we present systematic computational screening and
multiscale simulation results focusing on novel high-WF metallic materials and their interfaces with 2D
semiconducting TMDs. Specifically, we select monolayer WSe2 (referred to as WSe2 for simplicity) on the
semiconductor side due to its lower hole affinity (4.9 eV). Based on our theoretical analysis, we propose
two p-type contacting strategies that offer reduced MIGS and negligible Schottky barriers for WSe2.
The first strategy involves high-WF van der Waals (vdW) metal contacts. The weak vdW interac-
tions between vdW metals and 2-D semiconductors result in minimal perturbation of the electronic states
within the 2D semiconductors. Consequently, this leads to close-to-zero MIGS and a minimal Fermi-level
pinning effect. The second strategy revolves around high-WF bulk semimetal contacts. The relatively
low DOS around the charge neutrality point of bulk semimetals effectively suppresses electron state hy-
bridization at these energy levels, resulting in smaller MIGS and Fermi-level-pinning-free contacts with
32
2-D semiconductors. Through first-principles calculations and in-depth analysis, we observe that the vdW
and semimetallic contact strategies exhibit weaker electron rehybridization and lower MIGS density at the
metal/semiconductor interface, consequently leading to a much weaker Fermi-level pinning effect com-
pared to conventional metals.
Our investigations identify promising high-WF contact materials, including 1H-NbS2, 1T-TiSe2, and
1T-TiS2 in the vdW metal category, as well as Co3Sn2S2 and TaP in the bulk semimetal category. Further-
more, we assess their contact resistance and evaluate device performance when in contact with monolayer
WSe2, utilizing a multiscale simulation framework.
33
3.2 AbinitioDFTSimulationsofWSe2P-TypeContacts
As discussed in the previous chapter, we will now present two strategies to mitigate the effects of
MIGSs, along with one traditional counterpart. Hence, our investigation involves three categories of metal-
lic materials as p-type contacts to WSe2 shown in figure 3.2): (1) Strategy I explores 2D van der Waals (vdW)
metallic materials, including 1T-TiS2, 1H-NbS2, 1T-NbS2, and 1T’-WTe2; (2) Strategy II investigates bulk
topological semimetals such as Co3Sn2S2, TaP, and LaBi; and (3) a control group comprising conventional
metals like Pt, Pd, Au, Ag, and Al. According to our density functional theory (DFT) simulations, both
high-WF vdW metallic materials (Strategy I) and high-WF bulk semimetals (Strategy II) exhibit promising
potential as p-type contacts for WSe2. In this context, we present specific examples (figure 3.3) including
1H-NbS2 (Strategy I, WF = 6.11 eV), Co3Sn2S2 (Strategy II, WF = 5.32 eV), and Pt (conventional, WF = 5.7
eV). Due to the weak vdW coupling at the interface between WSe2 and the vdW contact (1H-NbS2), as
well as the low density of states (DOS) around the Fermi level of the bulk semimetal contact (Co3Sn2S2),
the interactions between WSe2 and these two contact materials are significantly weaker compared to con-
ventional metals. This results in smaller metal-induced gap states (MIGS) and a reduced pinning effect
(figure 3.4). Complete elimination of the p-type Schottky barrier height (pSBH) is achievable if the metal’s
WF is higher than the hole affinity of WSe2 (4.9 eV). The color-coded band structures (figure 3.4a and 3.4b)
vividly demonstrate the substantial reduction in electronic band rehybridizations for 1H-NbS2/WSe2 and
Co3Sn2S2/WSe2 heterojunctions, with Fermi levels around the valence band maximum (VBM), indicating
the elimination of pSBH. In contrast, the band structure of a high-WF conventional metal contact, such as
Pt/WSe2, exhibits pronounced MIGS, resulting in significant Fermi level pinning and a large pSBH (figure
3.4c).
34
Figure 3.2: Strategies for p-type WSe2 contact: 2D vdW materials, 3D bulk semimetals, and conventional
3D metals. The side view of atomistic structures and the differential charge density of heterojunctions are
shown (yellow: positive, blue: negative). 3D semimetals have low MIGS due to low DOS at Fermi level
Figure 3.3: Cross-sectional view of simulated interface charge density and electrostatic potential profiles
of heterostructures: (a) 1H-NbS2 with 1H- WSe2 (b) Sulfur-terminated Co3Sn2S2 with 1H-WSe2 (c) Pt(111)
with 1H-WSe2, each representing the 3 contact cases: 2D vdW materials, 3D bulk semimetal and 3D con-
ventional metals, respectively.
Figure 3.4: Supercell band structure of heterostructures, VBM(green circle), CBM(brown circle), Fermi
levels are located at 0 eV. (a) 1H-NbS2 with 1H-WSe2 (b) Sulfur-terminated Co3Sn2S2 with 1H-WSe2 (c)
Pt(111) with 1H-WSe2. The curves are color coded acording to the origins of the states: red color for WSe2
and grey color for the contact materials 1H-NbS2, Co3Sn2S2 and Pt
35
3.3 ComputationalScreeningofP-TypeContactMaterials
We perform WF calculations for various van der Waals (vdW) and bulk semimetal contact materi-
als (figure 3.5). WFs higher than 4.9 eV are deemed suitable for p-type contacts with WSe2, while WFs
higher than 5.8 eV are favorable for WS2 and MoS2. For vdW metallic materials, only single WFs are
recorded, whereas some bulk semimetals exhibit multiple WFs corresponding to different surface termi-
nations. For instance, in our DFT simulations, we select the sulfur-terminated surface with a WF of 5.3 eV
to achieve a favorable surface contact between the topological semimetal Co3Sn2S2 and WSe2. Another
example involves TaP, where the tantalum-terminated surface (TaP(Ta)) exhibits a lower WF compared to
the phosphorus-terminated surface (TaP(P)).
Figure 3.5: Calculated CBMs and VBMs for TMDs and WFs of bulk semimetals and multilayer 2D vdW
materials. Some semimetals have different surface terminations: Co3Sn2S2 has 4 surfaces: 5.8eV and 5.32eV
for sulfur-termination, 4.63 eV for Co3Sn termination and 4.27 eV for Co termination. For TaP, NbP, TaAs
and TaP, surfaces of non-metal elements have higher work functions and surfaces of metal elements have
lower work functions. S-terminated Co3Sn2S2 (5.32 eV), P-terminated TaP (5.4 eV), 1T-NbS2, 1T-TiS2 and
1H-NbS2 are used in subsequent study to construct metal/WSe2 contact heterostructures.
We analyze multiple physical parameters extracted from DFT simulations at the contact interfaces,
providing a fundamental understanding of the proposed contact strategies. In figure 3.6a, we compare the
WFs of WSe2 after contact with different metallic materials of varying WFs. High-WF vdW and semimetal
contacts induce significant Fermi level shifts, aligning the WFs of the heterojunctions closer to the orig-
inal WFs of the metallic materials, which are also close to the valence band maximum (VBM) of WSe2.
Conversely, the WFs of conventional metals have less impact, resulting in final WFs that are farther from
36
Figure 3.6: (a) WF of WSe2 after contact, (b) interlayer distance, and (c) interlayer dipole (ID) density
versus pristine metal WF. VBM of WSe2 is marked in gray. AA, AB mean stacking of vdW metal/WSe2
heterostructures. Labels for (b, c), figure 3.7, and figure 3.10 follow the same as (a). Red dotted line in (a)
corresponds to the same WF of WSe2 after contact as the WF of pristine metal.
Figure 3.7: (a) Binding energy, (b) total MIGS states per unit cell, and (c) pSBH (left axis) and nSBH (right
axis) of heterojunctions versus pristine metal WF. For (c), experimental results from [71] are marked as
crosses showing remarkable agreement with simulation results. The dashed lines with slopes of 0.5 and
0.05 correspond to vdW and semimetalic contacts with weak pinning, and conventional metal with strong
pinning in (c).
the VBM. We examine interlayer distances, ID densities, and Eb (binding energy) to characterize interface
interactions (figure 3.6b, 3.6c, and figure 3.7a). All computed high-WF vdW and semimetal contacts exhibit
interlayer distances smaller than 3 Angstroms (Å), ID densities closer to zero, and Eb values smaller than 50
meV/Å, while the opposite trends are observed for conventional metal contacts. Furthermore, we observe
a significant reduction in MIGS for high-WF vdW and semimetal contacts, as indicated by the total MIGS
states in figure 3.7b. It is worth noting that the lower-WF termination (TaP(Ta) as an example) leads to
stronger interface interactions and higher total MIGS compared to the higher WF terminations (TaP(P)).
37
This can be attributed to larger electron orbital overlaps of different chemical elements or increased den-
sity of states (DOS) at the VBM of WSe2. Additionally, different stacking orders (AA and AB) between
the vdW contact and WSe2 have minimal impact on interface interaction strengths and final band align-
ments. Finally, figure 3.7c summarizes the extracted pSBH and nSBH, with pinning factors (slope of each
material group) of approximately 0.5 for both vdW and semimetallic contact strategies. These values are
much larger than those of conventional metal contacts (∼ 0.05), indicating a significantly reduced Fermi
level pinning effect. Experimental results from literature [71] are included, demonstrating good agreement
with simulations. All simulated high-WF vdW materials and bulk semimetals exhibit negligible pSBHs, in-
cluding 1H-NbS2, 1T-NbS2, and 1T-TiS2 in the vdW material category, as well as Co3Sn2S2 and TaP(P) in
the bulk semimetal category.
3.4 MultiscaleSimulationandDevicePerformanceProjection
We have developed a multiscale simulation framework to evaluate the resistance-capacitance (RC)
characteristics and device performance of the proposed p-type contact strategies. Three key components
are considered at the contact: the tunneling resistivity around the metal-WSe2 interface (t), the sheet
resistance of WSe2 at the contact (RSHC), and the lateral Schottky barrier (SB) resistance, if present (figure
3.8). In figure 3.9a, we present the simulated RC values and transfer length (LT) for the high-WF vdW and
semimetal materials. Depending on the quality of WSe2 when in contact with these metals, RC values in
the range of 20-100Ω · µ m and LT values between 3-13 nm can be achieved. To illustrate the dependence on
material quality, we plot RC versus WSe2 mobility in figure 3.9b. It demonstrates that RC can be reduced
to approximately 20 Ω · m, approaching the quantum limit. As a reference, the best reported p-type RC
value from experiments is around 0.95 kΩ · µ m [72].
Furthermore, we simulate the current-voltage (I-V) characteristics of a double-gated WSe2 pFET (p-
type field-effect transistor) with Co3Sn2S2 contacts (53 Ω · µ m), 3 nm thick HfO2 gate dielectrics, and gate
38
lengths (L) ranging from 10-30 nm (figure 3.10). The projected on-state current is approximately 2 mA/ µ m
at VDS = -0.5V.
Figure 3.8: Schemetic of the model at the contact.
Figure 3.9: (a) RC (left) and LT (right) versus pristine metal WF. Two cases of WSe2 mobilities of 10
cm
2
V
− 1
S
− 1
and 80 cm
2
V
− 1
S
− 1
(linked by dotted line) under the contact are simulated. RC for 1T-NbS2
has no mobility dependence, because it is limited by RSB in figure 3.8. (b) RC versus WSe2 mobility under
the contact. Best experiment [72], theoretical limit, and RC for Si are also marked.
39
Figure 3.10: Simulated transfer characteristic of different gate lengths, L, and VDS = -0.5 V. (b) Simulated
output characteristics at L=20 nm for Co3Sn2S2/WSe2 FET.
40
Chapter4
Conclusions
In conclusion, these two projects represent significant advancements in the field of memory and com-
puting, offering promising prospects for future applications.
The ferroelectric van der Waals (vdW) heterojunction based on layered CIPS presents a breakthrough
in achieving high giant barrier height modulation in FTJ devices. With a substantial barrier height modu-
lation of 1 eV, far exceeding previous studies, this novel structure showcases its potential to revolutionize
memory and computing technologies. The asymmetric junction and the ferroelectric polarization field
reversal in CIPS enable a remarkable Fermi-level shift of 1 eV at the interface with monolayer graphene.
This achievement, coupled with the demonstrated reliability in terms of retention, endurance, switching
time, and uniformity, paves the way for the development of high-performance ferroelectric and multi-
ferroic materials in memory and computing applications. The impressive performance metrics and the
ability to modulate the barrier height to such a significant extent highlight the immense potential of this
semimetal-ferroelectric vdW heterojunction in shaping the future of memory and computing devices.
Simultaneously, the computational screening and design of low-resistance p-type contacts to 2D
semiconductors, specifically WSe2, provide a crucial breakthrough in advancing memory and computing
41
technologies. The identification of van der Waals metallic contacts (e.g., 1H-NbS2) and bulk semimetal-
lic contacts (e.g., Co3Sn2S2) as promising strategies for achieving Schottky-barrier-free and low-contact-
resistance p-type contacts offers a groundbreaking solution to a critical challenge in the industry. The
simulations demonstrate reduced metal-induced gap states, negligible Schottky barrier height, and im-
pressively small contact resistance of approximately 20 Ω µm . These findings not only provide valuable
insights into the fundamental understanding of p-type contacts but also offer a practical pathway towards
the industrial application of 2D channel materials in advanced logic technology. The development of
Co3Sn2S2 as a new semimetal contact material further solidifies the potential of this approach. By ad-
dressing the low-resistance p-type contact challenge, this project significantly contributes to the future
development of high-performance memory and computing devices based on 2D semiconductors.
Overall, these two projects exemplify the positive attitude and promising tone in advancing memory
and computing technologies. The ferroelectric vdW heterojunction and the low-resistance p-type contacts
offer exciting possibilities for achieving higher performance, improved functionality, and enhanced relia-
bility in future memory and computing applications. These breakthroughs mark important milestones in
the pursuit of more efficient and powerful devices, paving the way for a transformative impact on the field
of memory and computing.
42
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Abstract (if available)
Abstract
This work focuses on two significant breakthroughs in the field of memory and computing technologies. Firstly, a ferroelectric van der Waals (vdW) heterojunction based on layered CIPS (copper indium thiophosphate selenide) demonstrates a remarkable giant barrier height modulation and record-high tunnel electroresistance. The polarization in CIPS enables a substantial Fermi-level shift of 1 eV at the interface to provide the giant barrier height modulation. This devices demonstrates excellent reliability tests including retention, endurance, switching time, and uniformity for 5x7 array with 35 devices. This FTJ shows immense potential for high-performance memory and computing applications. Secondly, computational screening and design techniques are employed to identify low-resistance p-type contacts to 2D semiconductors, specifically WSe2. Van der Waals metallic contacts and bulk semimetallic contacts are found to be promising strategies for achieving Schottky-barrier-free and low-contact-resistance p-type contacts. The simulations reveal reduced metal-induced gap states, negligible Schottky barrier height, and impressively small contact resistance. This breakthrough not only enhances our fundamental understanding of p-type contacts but also provides a practical pathway for incorporating 2D channel materials in advanced logic technology. Therefore, these advancements contribute to the future development of high-performance memory and computing devices. The ferroelectric vdW heterojunction offers a revolutionary approach with significant barrier height modulation, while the design of low-resistance p-type contacts addresses a critical challenge in the industry. These findings pave the way for the utilization of novel materials and interfaces in shaping the future of memory and computing technologies.
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Chen, Hung-Yu
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Van der Waals material electronic devices for memory and computing
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2023-08
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