Close
About
FAQ
Home
Collections
Login
USC Login
Register
0
Selected
Invert selection
Deselect all
Deselect all
Click here to refresh results
Click here to refresh results
USC
/
Digital Library
/
University of Southern California Dissertations and Theses
/
Silicon photonics integrated circuits for analog and digital optical signal processing
(USC Thesis Other)
Silicon photonics integrated circuits for analog and digital optical signal processing
PDF
Download
Share
Open document
Flip pages
Contact Us
Contact Us
Copy asset link
Request this asset
Transcript (if available)
Content
SILICON PHOTONICS INTEGRATED CIRCUITS FOR ANALOG AND DIGITAL OPTICAL SIGNAL PROCESSING by Samer Sayed Bahr Idres A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2024 Copyright 2024 Samer Idres ii Dedication To my parents for their unconditional love, support, and guidance. iii Acknowledgements "He who does not thank people, does not thank Allah (God)," Prophet Muhammad, peace and blessings be upon him. I want to express my heartfelt thanks to my advisor, Prof. Hossein Hashemi, for his invaluable guidance and support throughout my research journey. His consistent feedback, encouragement, and expertise allowed me to explore and succeed in a research topic that was entirely new to me when I began. I am truly grateful to have had him as my mentor. I would like to express my gratitude to the rest of my dissertation and qualifying exam committee, Prof. Alan Willner, Prof. Jayakanth Ravichandran, Prof. Jonathan Habif, and Prof. Michelle Povinelli, for their guidance and support. I appreciate their invaluable contributions to my academic progress and their feedback, which has enriched my work. I am grateful for the time and effort they dedicated. I would like to thank the many group members that I have come across throughout my journey, Dr. Alireza Imani, Dr. Kunal Datta, Dr. Hooman Abediasl, Dr. Sushil Subramanian, Dr. Pingyue Song, Dr. Aria Samiei, Dr. Masashi Yamagata, Dr. Keisuke Kondo, Dr. Masayuki Okano, Vinay Chenna, Yongwei Ni, Thilina Ambagahawaththa and Farshad Serat Nahaei. Thank you for your valuable feedback and research discussions, as well as for being an essential part of this journey. I extend my sincere thanks to Dr. SungWon Chung and Makoto Nakai for sharing their knowledge and experience with me at the start of my research. I appreciate your insights and support throughout the process. I would also like to thank Dr. Shiyu Su, Dr. Aoyang Zhang, Dr. Cheng- iv Ru Ho, Dr. Jaewon Nam, Dr. Mohsen Hassanpourghadi, Dr. Qiaochu Zhang, Dr. Juzheng Liu, Dr. Ce Yang, Dr. Rezwan Rasul, Mostafa Ayesh, Michella Rustom, and Kazem Bakian. I will always cherish your support, encouragement, and friendship. I would like to thank the many ECE staff members for their help and support. Special thanks to Diane Demetras, Jenny Lin, Kim Reid, and Sunny Bhalla. Finally, and most importantly, I would like to thank my parents and siblings for their unwavering love and support. I am truly grateful for the endless encouragement they have provided. My parent’s hard work and countless sacrifices have been instrumental in my success and have opened many doors of opportunity for me. I would also like to thank the rest of my family and friends for their encouragement, which has meant a lot to me throughout this journey. Special thanks to Amr Ibrahim and Mohamed Ibrahim for being true friends and for their invaluable help throughout my journey. Your support, the good times we shared, and your friendship have made a significant difference. v Table of Contents Dedication................................................................................................................................. ii Acknowledgements..................................................................................................................iii List of Tables .......................................................................................................................... vii List of Figures........................................................................................................................viii Abstract.................................................................................................................................. xvi Chapter 1 Introduction .............................................................................................................. 1 1.1 Motivation and Applications........................................................................................... 1 1.2 Integrated Silicon Photonics............................................................................................ 7 1.3 Thesis Outline ................................................................................................................. 9 Chapter 2 Low-Loss Tunable True Time Optical Delay Line................................................ 10 2.1 Low-Loss Optical Delay Line ....................................................................................... 11 2.1.1 Design and Implementation.................................................................................... 11 2.1.2 Measurement Results.............................................................................................. 16 2.2 Variable Binary-Coded Delay Line............................................................................... 17 2.2.1 Design and Implementation.................................................................................... 17 2.2.2 Measurement Results.............................................................................................. 19 2.3 Application Example: Self-interference Canceller........................................................ 22 2.3.1 Experimental Setup ................................................................................................ 23 2.3.2 Measurement Results.............................................................................................. 24 2.3.3 Linear Optical Modulator....................................................................................... 26 vi Chapter 3 Optically Biased and Controlled Signal Processing............................................... 30 3.1 All-Optical remote biasing and controlling concept ..................................................... 31 3.2 Building Blocks............................................................................................................. 32 3.2.1 Wavelength Demultiplexer..................................................................................... 32 3.2.2 Optical Power to Voltage Converter ...................................................................... 35 3.3 All-Optical Signal Processing Demonstration .............................................................. 39 3.3.1 Amplitude Modulator............................................................................................. 39 3.3.2 Two-Tap Sequence Detector.................................................................................. 43 Chapter 4 Universal Optical Input-Optical Output Logic Gates ............................................ 53 4.1 All-optical Switch Implementation ............................................................................... 55 4.2 Zero-bias Low Speed Logic Gate.................................................................................. 56 4.2.1 Concept and Building Blocks................................................................................. 57 4.2.2 Implementation and Fabrication............................................................................. 67 4.2.3 Measurement Results.............................................................................................. 70 4.2.4 Logic Gate Cascadabilty......................................................................................... 78 4.3 Biased High Speed Logic Gate ..................................................................................... 82 4.3.1 Concept and Building Blocks................................................................................. 82 4.3.2 Implementation and Fabrication............................................................................. 85 4.3.3 Simulation Results.................................................................................................. 86 4.4 Logic Circuits Examples............................................................................................... 91 4.4.1 Full Adder............................................................................................................... 91 4.4.2 Pattern Detector...................................................................................................... 95 Chapter 5 Conclusion and Future Work ................................................................................. 97 References............................................................................................................................. 101 vii List of Tables Table 4. 1 Microring Modulator Measured Characteristics.......................................................... 79 Table 4. 2 Simulated bandwidth of the high-speed logic gate for different R values................... 89 viii List of Figures Figure 1. 1 Optical vs Electrical communication links................................................................... 2 Figure 1. 2 Total global traffic and electricity usage of data centers per year................................ 3 Figure 1. 3 The network architecture of the data centers. (a) current implementation, (b) future proposal........................................................................................................................................... 4 Figure 1. 4 Block diagram of (a) electronic switch (b) optical switch. .......................................... 6 Figure 1. 5 The objective of the work presented in this thesis. ...................................................... 7 Figure 1. 6 The layers cross-section of the used silicon photonic technology. .............................. 8 Figure 2. 1 Optical spiral true time delay line. ............................................................................. 10 Figure 2. 2 Refractive index of silicon waveguide versus the waveguide width, showing the different optical modes and the region of single-mode and multi-mode widths. ......................... 12 Figure 2. 3 Proposed geometry of the low-loss silicon photonics delay line showing the dimensions. ................................................................................................................................... 13 Figure 2. 4 Symmetric waveguides coupling................................................................................ 13 Figure 2. 5 The mode simulation of Lπ versus the gap between two symmetric 3 µm waveguides. ....................................................................................................................................................... 14 Figure 2. 6 Low-loss taper implementation. (a) Detailed geometry of the single mode to multimode waveguide taper along with the FDTD loss simulation results. (b) FDTD simulated loss of linear and parabolic tapers for different lengths................................................................ 15 Figure 2. 7 Low-loss U-turn bend implementation. (a)Detailed geometry of the 180° clothoid bend along with the FDTD loss simulation results. (b) FDTD simulated loss of circular and euler 180° bends for different diameter. ....................................................................................... 15 Figure 2. 8 Chip micrograph of the fabricated delay line with a zoom-in to the 180° clothoid bend............................................................................................................................................... 16 ix Figure 2. 9 Measured loss of the delay line across four different chips using the cut-back technique showing direct loss of three different delay lines lengths (0.3 m, 0.6 m, 0.9 m) in addition to the estimated loss of the straight multimode wide waveguide per unit length and delay.............................................................................................................................................. 17 Figure 2. 10 Schematic Diagram of the proposed variable switched optical delay line, showing the number of waveguides (N) and delay (τ) of each delay line section and the low loss optical switch layout design...................................................................................................................... 18 Figure 2. 11 The proposed geometrically-optimized, heat-reuse optical switch .......................... 18 Figure 2. 12 Microphotograph of the fabricated structure showing the location of each delay line section. ................................................................................................................................... 19 Figure 2. 13 The heat-reuse optical switch measurement results showing the output power at the bar and the cross ports versus the heater power...................................................................... 20 Figure 2. 14 Switched optical delay measurements. (c) The group delay measurements of the proposed structure versus the frequency of the modulated RF signals around the optical carrier, showing the minimum and maximum delays and all the coarse tuning 4 MSBs (DL1-DL4) configurations’ delays (d) The measured relative group delays of the fine tuning 3 LSBs (DL5- DL7) configurations...................................................................................................................... 21 Figure 2. 15 Optical 8-bit switchable delay line time domain measurements using 8 GHz bandwidth UWB modulated signal, showing the delay values of the 8 delay line sections......... 21 Figure 2. 16 Proposed continuously tuned delay line ................................................................... 22 Figure 2. 17 RF self-interference cancellation concept. ............................................................... 23 Figure 2. 18 Experimental setup testbench diagram of the self-interference cancellation measurements................................................................................................................................ 24 Figure 2. 19 Receiver output RF voltage (VRF-op) time response of 8 GHz bandwidth (1-9 GHz) UWB transmitted signal with and without the self-interference cancellation. ............................. 25 Figure 2. 20 Receiver output RF voltage (VRF-op) spectrum response of 8 GHz bandwidth (1-9 GHz) UWB transmitted signal with and without the self-interference cancellation. ................... 25 Figure 2. 21 Schematic diagram of the single side band optical modulator showing the required phase relations at each point and the optical harmonics spectrum at the main nodes. ................. 27 Figure 2. 22 Microphotograph of the fabricated single side-band modulator, showing the location of the building blocks and the major dimensions. .......................................................... 27 Figure 2. 23 Optical linearity measurement results showing the output power vs input power response and the measured optical loss of the modulator............................................................. 28 x Figure 2. 24 Test setup schematic diagram showing the fiber array coupling and the RF signals connecting to the chip (DUT), the power harmonics spectrum at the main points are also shown. ....................................................................................................................................................... 29 Figure 2. 25 The output power spectrum of the best measured single sideband and carrier rejection operation for (a) 100 MHz and (b) 1 GHZ modulation RF signals, showing both right and left side-band cases. ............................................................................................................... 29 Figure 3. 1 Conceptual diagram of the all-optical signal processor. ............................................ 31 Figure 3. 2 Wavelength demultiplexer fabricated designs and measurement results. (a) Schematic diagram of the series coupled ring resonator-based wavelength demultiplexer showing the main design specs. (b) Micrograph of the fabricated 3-channel wavelength demultiplexer. ............................................................................................................................... 33 Figure 3. 3 Measured transfer function of three different coupled ring resonators wavelength demultiplexer designs with different number of channels (Nch), 3-channel, 5-channel, and 7- channel. ......................................................................................................................................... 34 Figure 3. 4 Monte-Carlo simulations of coupled ring resonator and single ring resonator, (a) and (b), respectively...................................................................................................................... 35 Figure 3. 5 Measured transfer function of three different single ring resonators wavelength demultiplexer designs with different number of channels (Nch), 3-channel, 5-channel, and 7- channel. ......................................................................................................................................... 35 Figure 3. 6 Photodiode modes of operation showing the I-V diode characteristics, circuit implementation, and input optical power to output voltage transfer function.............................. 36 Figure 3. 7 Optical power to voltage converter fabricated designs based on series stacked photovoltaic photodiodes. (a) schematic diagram, (b) chip micrograph of 16 stacked photodiodes, with a zoomed-in micrograph of 4 photodiodes...................................................... 37 Figure 3. 8 Measured current voltage characteristic of the stacked Si-Ge photodiodes for different numbers of series photodiodes: 1, 2, 4, 8, and 16. ......................................................... 38 Figure 3. 9 Measured open-circuit output voltage versus input optical power for different numbers of series photodiodes (Npd): 1, 2, 4, 8, and 16................................................................ 38 Figure 3. 10 Optically-controlled amplitude modulator: (a) schematic diagram, (b) fabricated device micrograph......................................................................................................................... 40 Figure 3. 11 Optically-controlled amplitude modulator measurements showing the output power versus the input optical control powers that control the two arms of the amplitude modulator MZI.............................................................................................................................. 41 Figure 3. 12 Schematic diagram of electrically-controlled optical switch. .................................. 42 xi Figure 3. 13 Electrically-controlled optical switch measurements showing the output power versus the input electrical control voltages that control the two arms of the optical switch MZI: (a) VC1 (upper arm), (b) VC2 (lower arm). .................................................................................... 42 Figure 3. 14 Conceptual diagram of the two-tap sequence detector showing the dynamic response for an OOK input data.................................................................................................... 44 Figure 3. 15 Optically-controlled two-tap sequence detector: (a) schematic diagram, (b) fabricated device micrograph........................................................................................................ 45 Figure 3. 16 VNA frequency sweep measurements of the optically-controlled two-tap sequence detector showing the optical transmission for different values of the optical control signal that feeds the amplitude modulator...................................................................................................... 46 Figure 3. 17 Optically-controlled two-tap sequence detector dynamic measurements for OOK input modulated signal. PRBS OOK signal is the input to the correlator (in Red), the optical output of the modulator (in Blue) for three different cases of optical power ratios at the end of the asymmetric MZI branches (three amplitude modulator settings). Top: the power ratio is the same (|EA|=|EB|), middle: the power in the non-delayed arm is larger (|EA|<EB|), and bottom: the power in the delayed arm is larger (|EA|>EB|). This is shown for two cases when the phase difference in the optical fields at the point Ea and EB are in phase and out of phase, (a) and (b) respectively. .................................................................................................................................. 48 Figure 3. 18 Optically-controlled two-tap sequence detector dynamic measurements for PAM3 input modulated signal. PRBS signal is the input to the correlator (in Red), the output of the modulator (in Blue) for the same optical power ratios at the end of the asymmetric MZI branches (one amplitude modulator setting), the power ratio is the same (|EA|=|EB|). These results are when the optical fields at the point EA and EB are in phase. ....................................... 49 Figure 3. 19 Optically-controlled two-tap sequence detector dynamic measurements for PAM4 input modulated signal. PRBS signal is the input to the correlator (in Red), the output of the modulator (in Blue) for the same optical power ratios at the end of the asymmetric MZI branches (one amplitude modulator setting), the power ratio is the same (|EA|=|EB|). These results are when the optical fields at the point EA and EB are in phase. ....................................... 50 Figure 3. 20 Two-tap correlator schematic with the different power consumption portions. ...... 51 Figure 3. 21 Two-tap sequence detector power consumption for different optical to voltage converter sizes in the case of targeted output power of 0.1 mW. ................................................. 51 Figure 3. 22 Two-tap sequence detector power consumption for different optical to voltage converter sizes in the case of driving a optical to voltage converter for π phase shift. ................ 52 Figure 4. 1 NOT logic gate block diagram and transfer function: (a) Electrical implementation, (b) optical implementation............................................................................................................ 55 xii Figure 4. 2 Microring modulator based all-optical switch: (a) schematic diagram, (b) microring transmission as function of the input power, (c) the switch nonlinear transfer function for inverting and non-inverting cases. ................................................................................................ 56 Figure 4. 3 Conceptual diagram of the all-optical zero-biased logic gate with optical input combining. .................................................................................................................................... 57 Figure 4. 4 Conceptual diagram of the all-optical zero-biased logic gate with coherent in-phase or uncorrelated optical input combining. (a) schematic diagram of the logic gate showing the main building blocks with the optical inputs combine in the optical domain. (b) Resonant wavelength shift of the micro-ring resonator as a function of combined power level input to the photovoltaic photodiode................................................................................................................ 59 Figure 4. 5 Logic operation of optical gate with coherent in-phase or uncorrelated optical input combining (a) Operational principle of the OR gate for different input combinations. (b) Operational principle of the NOR gate for different input combinations..................................... 59 Figure 4. 6 The combiner output power for one and two input optical data cases. In case of the two operands, the output power is shown for three different cases: the 2 input lasers carriers are uncorrelated, correlated and in phase, and lastly correlated and out of phase.............................. 60 Figure 4. 7 Conceptual diagram of the all-optical zero-biased logic gate with one operand (in case of optical combining). (a) schematic diagram of the logic gate showing the main building blocks. (b) Resonant wavelength shift of the micro-ring resonator as a function of power level input to the photovoltaic photodiode. ........................................................................................... 61 Figure 4. 8 Logic operation of optical gate with one operand (in case of optical combining). (a) Operational principle of the Buffer gate for different input combinations. (b) Operational principle of the NOT gate for different input combinations......................................................... 61 Figure 4. 9 Conceptual diagram of the all-optical zero-biased logic gate with coherent out-ofphase input combining. (a) schematic diagram of the logic gate showing the main building blocks with the optical inputs combine coherently in the optical domain with 180º phase shift. (b) Resonant wavelength shift of the micro-ring resonator as a function of combined power level input to the photovoltaic photodiode.................................................................................... 63 Figure 4. 10 Logic operation of optical gate with with coherent out-of-phase input combining. (a) Operational principle of the XOR gate for different input combinations. (b) Operational principle of the XNOR gate for different input combinations...................................................... 64 Figure 4. 11 Conceptual diagram of the all-optical zero-biased logic gate with electrical input combining. (a) schematic diagram of the logic gate showing the main building blocks with the optical inputs combine in the electrical domain. (b) Resonant wavelength shift of the microring resonator as a function of power level of each input operand............................................... 64 xiii Figure 4. 12 Logic operation of optical gate with electrical input combining. (a) Operational principle of the OR gate for different input combinations. (b) Operational principle of the XNOR gate for different input combinations. (c) Operational principle of the NAND gate for different input combinations......................................................................................................... 64 Figure 4. 13 Conceptual diagram of the all-optical zero-biased logic gate with one operand (in case of electrical combining). (a) schematic diagram of the logic gate showing the main building blocks. (b) Resonant wavelength shift of the micro-ring resonator as a function of power level input to the photovoltaic photodiode. ........................................................................................... 65 Figure 4. 14 Logic operation of optical gate with one operand (in case of optical combining). (a) Operational principle of the Buffer gate for different input combinations. (b) Operational principle of the NOT gate for different input combinations......................................................... 65 Figure 4. 15 Ring modulator resonance shift in case of optical input combining for different input cases (a) one operand, (b) two uncorrelated operands, (c) two correlated (in-phase) operands, (d) two correlated (out-of-phase) operands. ................................................................. 66 Figure 4. 16 Ring modulator resonance shift in case of electrical input combining for different input cases (a) one operand, (b) two operands.............................................................................. 66 Figure 4. 17 Optical-input optical-output zero-biased logic gate with optical input combining. (a) Schematic diagram of proposed design showing the building blocks and the input-output ports. (b) Micrograph of the fabricated logic gate with ring modulator length of 250 µm showing the main building devices and the area size.................................................................................. 68 Figure 4. 18 Schematic diagram of an alternative design of the logic gate with electrical logic operands combining...................................................................................................................... 70 Figure 4. 19 Optical power to voltage characterization. Measured open-circuit output voltage versus input static logic optical power ( or ) for different input logic configurations (00, 01,10, and 11) for two configurations: (a) optical combining and 16 stacked photodiodes, (b) electrical combining using 2 series sets of 8 stacked photodiodes. ........................................ 72 Figure 4. 20 Optical-optical logic gate static measurements. Measured wavelength transmission of the optical logic gate for different input logic cases (with high logic optical power =0.1mW) in case of: (a) two operands, (b) one operand......................................................... 73 Figure 4. 21 Optical-optical logic gate dynamic measurements for 10 Mbps OOK input modulated signal. PRBS OOK signal is the input to the logic gate and (in Red), and the optical output of the logic gate (in Blue) showing the operation of OR and NOR in case of two operands and NOT and Buffer in case of one operand in (a) and (b), respectively...................... 76 Figure 4. 22 Photodiode and ring modulator circuit model for speed measurements. ................. 76 xiv Figure 4. 23 Optical logic gate speed measurements. Measured transient response with input square wave 2 MHz logic input signal () for different optical carrier high level power of both the monitor signal (monitor the input power to the optical power to voltage converter) in green (top) and the logic gate output signal in blue (bottom) for the microring design with =250μm........................................................................................... 77 Figure 4. 24 The measured rise time and fall time (10%-90%) of the logic gate output for different logic input power (top), and the corresponding -3dB bandwidth values (bottom) for different designs........................................................................................................... 77 Figure 4. 25 Optical logic gate cascadability. (a) Measured optical logic gate transfer function (output transmission Pout/Psup versus the input logic power PA) for three different ring modulator geometries. (b) Total optical power needed for one optical logic gate versus the input logic power PA. ............................................................................................................................. 80 Figure 4. 26 Optical logic gate cascadability with fanout. (a) Conceptual diagram of an optical logic gate driving F similar optical logic gates. (d) The minimum total power consumption of an optical logic gate versus different values of fanout (F)............................................................ 81 Figure 4. 27 Conceptual diagram of the optical operands high speed logic gate. ........................ 83 Figure 4. 28 Resonant wavelength shift of the micro-ring resonator of the high speed optical logic gate as a function of power level of each input operand...................................................... 84 Figure 4. 29 Logic operation of high speed optical gate. (a) Operational principle of the OR gate for different input combinations. (b) Operational principle of the XNOR gate for different input combinations. (c) Operational principle of the NAND gate for different input combinations................................................................................................................................. 84 Figure 4. 30 Conceptual diagram of the optical operands high speed logic gate with one operand (a) schematic diagram of the logic gate showing the main building blocks. (b) Resonant wavelength shift of the micro-ring resonator as a function of power level input to the photoconductive photodiode......................................................................................................... 84 Figure 4. 31 Logic operation of the high speed optical gate with one operand. (a) Operational principle of the Buffer gate for different input combinations. (b) Operational principle of the NOT gate for different input combinations. ................................................................................. 85 Figure 4. 32 Ring modulator resonance shift of the high-speed logic gate for different input cases (a) two operands, (b) onw operands. ................................................................................... 85 Figure 4. 33 Schematic diagram of the proposed high speed optical logic gate........................... 86 Figure 4. 34 Circuit model of the high-speed optical logic gate................................................... 87 Figure 4. 35 The modulating voltage Vm versus the photodiode current representing the input logic power.................................................................................................................................... 87 xv Figure 4. 36 The high-speed logic gate simulated AC response................................................... 88 Figure 4. 37 OOK PRBS transit simulation of the high-speed logic gate. ................................... 89 Figure 4. 38 High-speed logic gate energy per bit versus the microring modulator transmission. ....................................................................................................................................................... 90 Figure 4. 39 High-speed logic gate energy per bit versus the microring modulator length. ........ 91 Figure 4. 40 Full adder gate-level implementation: (a) NOR-only, (b) XOR and NAND. .......... 92 Figure 4. 41 Full adder implementation using the high-speed optical logic gate......................... 93 Figure 4. 42 N-bit data parallel addition....................................................................................... 93 Figure 4. 43 N-bit data serial addition .......................................................................................... 94 Figure 4. 44 Serial Full adder implementation using the high-speed optical logic gate............... 94 Figure 4. 45 Serial full adder behavioral simulation..................................................................... 94 Figure 4. 46 Optical pattern detector implementation .................................................................. 95 Figure 4. 47 Optical pattern detector output power as function of x bit similarity between the input data and the target pattern.................................................................................................... 96 xvi Abstract Optical signal processing can play an important role in numerous optical systems broadly used in today’s world, such as optical interconnects and networking, optical computing and machine learning, RF over fiber, lidar, etc. While these systems contain and transmit the data in the optical format, the information processing occurs primarily using CMOS circuits in the electrical domain, which necessitates power-hungry and latency-inducing opto-electric-opto conversion. Performing appropriate signal processing on the optically modulated information signal may reduce the power consumption and latency across the system while bolstering security and high-speed data rate. Silicon photonics integrated silicon (Si PIC), along with the advances in materials and devices, are the key enabling technologies growing the optical signal processing practical utilization. This thesis features different integrated optical signal processing circuits and systems in both the analog and digital domains. True time delay lines are key enablers in analog optical signal processing; therefore, a low-loss variable delay line, leveraging wide straight waveguides and compact bends, is implemented. Targeting optical signal processing occurs at remote nodes with hard access to reliable electrical supply and control signals. An all-optical remotely controlled and biased signal processing system, utilizing WDM laser-delivered bias and control signals, is proposed. Two examples are employed to demonstrate this system: an amplitude modulator and a two-tap sequence detector. Universal optical input – optical output cascadable logic gates are also reported, facilitating digital optical signal processing. These proposed optical processing systems xvii and circuits are fabricated in a commercial silicon photonics process and experimentally demonstrated. Key words: Silicon photonics integrated circuit, Analog optical signal processing, Digital optical signal processing, Optical true time delay line, RF self-interference canceller, All-optical signal processing, Optically controlled signal processing, Optical switching, Optical sequence detection, Optical logic gates, optical logic circuits, Optical full adder. 1 Chapter 1 Introduction 1.1 Motivation and Applications The modern world is highly dependent on internet connectivity, making high-speed data communication essential for our everyday lives. Given this need for fast and high-traffic data links, optical communication systems have become crucial in today's data communication industry, especially for long-distance connections. Fiber optic transmission offers many benefits over copper-based links, including lower signal loss, higher bandwidth, lower costs, greater resistance to electromagnetic interference, lighter weight, and enhanced security against eavesdropping. Optical fiber communication now dominates long-distance data transmission, such as metropolitan networks and long-haul connections, as well as most rack-to-rack communication in data centers [1-4]. On the other hand, electrical interconnects continue to be prevalent for shorter distances, like board-to-board and chip-to-chip communication, as illustrated in Fig. 1.1. The bandwidth provided by electrical interconnects is struggling to keep up with the increasing data demands, which are nearly doubling every year. While adding more I/O pins can boost data rates, this also leads to larger package sizes and fails to address high power consumption. To meet the rapidly growing need for higher data rates, optical links are expected to take over even shorter-range connections[5-7]. Integrating optical I/O into server packages using silicon photonics brings 2 numerous benefits within a smaller form factor, including increased bandwidth, reduced power consumption, and fewer I/O pins [8]. Silicon photonics integration is poised to reshape data center architectures, offering a path to greater efficiency and performance. Metro and Long-Haul 0.1-100 km Rack to Rack 1-100 m Board to Board 10-100 cm Package to Package 1-10 cm Optical Copper Time Figure 1. 1 Optical vs Electrical communication links. The global data center traffic has been growing at an annual rate of around 25% in recent years [9-13], as indicated in Figure 1.2, primarily driven by the surge in online activities such as streaming media, remote learning, surveillance data, connected sensors, social media, online collaboration, virtual reality, and online gaming. However, with the anticipated explosion in artificial intelligence (AI) and machine learning applications, this growth rate is expected to soar to about 80% per year in the coming years. As also shown in Figure 1.2, data centers consumed approximately 500 TWh of electricity in 2021, with electricity usage expected to increase dramatically in the future as it follows the traffic growth trend. This ongoing and projected rise in data center traffic and energy consumption underscores the critical need for high-performance and energy-efficient networking and data transfer within data centers. Achieving these efficiencies is becoming increasingly crucial to support the growing demands for data processing and communication while addressing the environmental and operational impacts of energy consumption. 3 Figure 1. 2 Total global traffic and electricity usage of data centers per year. To reduce power consumption in data communication, optical links can be used to handle highdata-rate long and medium-range links, as mentioned earlier. This is one aspect of power reduction. Another critical factor is reducing power consumption in network switches, which play a key role in data centers by managing packet switching or routing. This operation involves directing data from the source to its intended destination. Current data center network infrastructure relies heavily on electronic packet switches, which are power-intensive. These electronic switches are cascaded because of their limited bandwidth and radix (Fig. 1.3), leading to high latency and high-power consumption due to optical-electro-optical conversion, memory storage, and buffering [14,15]. Electronic switches in data centers are often fixed in terms of data rate, packet length, and topology, providing little reconfigurability. Generally, communication between the rack and the top-of-the-rack (TOR) electronic switch is achieved via Ethernet interfaces using 4-channel 25 Gbps On-Off Keying (OOK) Serializer/De-serializer (SerDes) high-speed electrical links. However, as traffic increases, higher-order modulation and greater data rates are required. The 4 latest developments use 100 Gbps SerDes interfaces with PAM-4 modulation, capable of reaching 400 Gbps [16-18]. In contrast, higher-level network switches typically use optical fiber and can support higher data rates through multiplexing. Current electronic switches use optical-electricaloptical conversion, with input packets converted from optical to electrical upon entering the switch and converted back to optical upon exiting after processing (Fig. 1.3). This process, repeated across each network switch, contributes to high power consumption and latency. The challenge of increasing performance with SerDes IP has led to a saturation point, complicating the support of higher data rates with electronic switches. This is why there's growing interest in developing alloptical switch fabrics to replace electronic switches in data centers, allowing data to remain in the optical domain throughout the network, including packet switches. Internet Core Switches Aggregate Switches Edge Switches Servers Internet Optical Switching Network Electrical Link Optical Link (a) (b) Figure 1. 3 The network architecture of the data centers. (a) current implementation, (b) future proposal. Optical switch fabrics can provide significant benefits, such as reducing electricity usage, increasing speed, and lowering latency. These fabrics can replace high-traffic electronic switches, while low-traffic edge switches can remain electronic (Fig. 1.3). This transition to optical switches can lead to cost savings, improved network scalability, and greater capacity. The future of data 5 center network architecture lies in reconfigurable optical switch fabrics, providing a more efficient and adaptable infrastructure for high data rate and high traffic scenarios [15,19]. Figure 1.4 illustrates the key components of both electronic switches currently used in data centers and the envisioned all-optical switch. In electronic switches, a SerDes ASIC is employed for optical-electrical-optical (O-E-O) conversion, a necessary step in the switching process. However, for edge switches utilizing electrical links, O-E-O conversion is unnecessary. Data packets typically comprise two parts: the header containing destination addresses and start-offrame information, and the payload, which contains user data. In packet switching, the first step involves extracting and interpreting the header information. Electronic switches typically employ a store-and-forward method, where payload data is temporarily stored in memory, then retrieved and sent to the designated output in a clocked manner under the control of a dedicated unit processing the header information. Finally, the frame is reconstructed by combining the header with the payload. Conversely, in an ideal optical switch, all switching processes occur in the optical domain (Fig. 1.4). However, optical systems lack high-speed data storage capabilities, necessitating the use of a switching matrix to direct packets to their designated outputs. A major challenge in realizing such optical switches is the absence of optical logic or control units capable of managing the switching matrix, as well as unresolved issues regarding header extraction in the optical domain. Consequently, the full implementation of all-optical switches remains unrealized, with electronic switches continuing to dominate the data interface networking market. Historically, the consensus has been that optics are better suited for data transmission, while electronics excel in data manipulation and storage. This fundamental distinction has shaped the current landscape, with electronic switches fulfilling critical roles in data center operations. 6 In this thesis, all-optical devices are proposed that are capable of implementing optical switches. The work involves creating a low-loss delay line that can serve as an optical buffer, which provides temporary storage for optical signals. Additionally, an all-optical sequence detector is designed with the ability to recognize packet headers, and an optical logic gate is developed that can be used to build an optical control unit. These innovations aim to overcome the limitations of existing optical switching technology by enabling complete optical processing without relying on optical-electrical-optical (O-E-O) conversion. With these components, it is possible to create an all-optical switch capable of managing data packet routing in the optical domain, addressing the key challenges of traditional electronic switches, such as high-power consumption and limited scalability. E/OO/E E/OE/O ASIC Switch Frame and Header Editing Frame and Header Reading SerDes Frame and Header Reading Shared Memory and Buffer Frame and Header Editing SerDes Control Unit Input Output Optical Switching Network Control Unit Header Extraction and Reading Splitter Optical Delay Input Output Optical Switch Electronic Switch (a) (b) Figure 1. 4 Block diagram of (a) electronic switch (b) optical switch. In conclusion, optical signal processing can play a significant role in various optical systems commonly used today, including optical interconnects and networking, optical computing and machine learning, radio frequency (RF) over fiber, lidar, and other applications. Although these systems store and transmit data in an optical format, the actual information processing is primarily 7 done using CMOS circuits in the electrical domain. This reliance on electrical processing necessitates opto-electric-opto (O-E-O) conversions, which consume considerable power and add latency. By performing signal processing directly on optically modulated information signals (Fig. 1.5), these drawbacks can be mitigated. This approach can reduce overall power consumption, minimize latency, and potentially enhance security, as it minimizes the conversion between optical and electrical formats. Furthermore, processing data in the optical domain may facilitate higherspeed data rates, making these systems more efficient and responsive to the growing demands of modern technology environments. This shift toward optical signal processing could transform the architecture of various optical systems, promoting more energy-efficient and high-speed solutions for a range of applications. Optical Input O/E Electronics Signal Processing E/O Optical Output All-Optical Signal Processing Optical Output Optical Input Figure 1. 5 The objective of the work presented in this thesis. 1.2 Integrated Silicon Photonics Photonic integrated circuits (PIC) use semiconductor technology to integrate multiple photonic components onto a single chip. It provides a much more compact solution than fiber based or freespace bulky optic systems and circuits [20,21]. The main advantage of PIC is that it can drastically decrease the power consumption, coupling loss, size, and costs of the optical systems. Also, it is 8 more suitable for high-volume manufacturing, and improved reliability. PIC has been used in different applications like communication, sensing, and imaging [22,23]. Integrated silicon photonics leverages the well-established silicon platform used in the electronics industry, allowing for cheap, scalable, and efficient photonic devices that can be used for various applications [24,25]. The main advantage of integrated silicon photonics over the other PIC technologies is that it can be easily integrated with the electronic circuits on the same chip, facilitating hybrid systems with optical and electronic functionalities. Overall, integrated silicon photonics represents a significant advancement in combining photonic and electronic technologies, with wide-ranging applications in telecommunications, data centers, computing, sensing, and beyond. It provides a path toward more efficient, scalable, and flexible solutions in various fields. The proposed circuits and systems in this thesis are implemented using a commercial photonics silicon-on-insulator (SOI) photonics technology. The used process is Tower Semiconductor (PH18MA), featuring a silicon thickness of 220 nm on top of a 3µm buried silicon oxide layer. The cross-section and the main layers of this process are shown in Fig. 1.6. TiN Resistor Nitride WG Silicon Oxide P-type Silicon Substrate Strip WG Ridge WG Si Si Ge M1 M2 M3 Figure 1. 6 The layers cross-section of the used silicon photonic technology. 9 1.3 Thesis Outline The thesis consists of five chapters, including chapter one as introduction, and the rest is organized as the following. In chapter two, a low-loss tunable optical delay line is proposed and used to implement a RF self-interference canceller as an application example. Chapter three show a demonstration of the optically biased and controlled signal processing concept, with two examples: amplitude modulation and sequence detection. In chapter 4, universal all-optical logic gates are proposed and used to implement an optical dull adder and pattern detector as digital circuits examples. Finally, chapter five summarize the work in the thesis and shows the possible future improvements and research directions. 10 Chapter 2 Low-Loss Tunable True Time Optical Delay Line Low-loss waveguides are key enablers in photonic integrated circuits and systems including those for communications, computation, sensing, and microwave signal processing [26-28]. The loss is particularly important in signal processing applications where a large delay is needed. In this case, waveguides with larger core size may be used to enhance the confinement and reduce the interaction of the optical field with the sidewall roughness to reduce loss. Such waveguides naturally support multiple propagating modes. This leads to large losses at any discontinuity in the waveguide geometry including waveguide bends. Therefore, most of the existing large delay lines use spiral structures (Fig. 2.1) with very large bends (few mm) to solve this issue [28-31]. The main drawback of this approach is the inability to realize large delay lines in a compact formfactor. In this chapter, we use tapered waveguides to connect the low-loss multi-mode wide-core straights waveguides to single-mode compact waveguide bends that leverage geometrically optimized Euler shapes to reduce their loss [32]. Figure 2. 1 Optical spiral true time delay line. 11 Variable delay line is a key enabler in many RF photonic applications such as microwave filtering, correlators, and self-interference cancelations [31,33]. In this chapter, we demonstrate a switched delay line structure leveraging the aforementioned low-loss compact delay lines and 2x2 Mach-Zehnder Interferometer (MZI) switches. Also, the proposed variable delay line is used in a RF self-interference cancellation experiment. 2.1 Low-Loss Optical Delay Line The proposed low loss true time delay structure is presented in this section. This design is used as a unit cell in the binary switched variable delay line, as shown in the next section. 2.1.1 Design and Implementation There are two types of waveguide designs based on the width and the supported electromagnetic modes: single-mode (small core width) waveguide and multi-mode (wide width) waveguide. Figure 2.2 shows the targeted width of the two types of waveguides. Single-mode waveguide has high surface roughness loss due to low confinement in a small core size and low mode conversion loss at discontinuities & bends; hence, it is more suitable for short-length and compact bends, not long straight waveguides. On the other hand, multi-mode waveguide has low surface roughness loss due to high confinement in a large core size and high mode conversion loss at discontinuities & bends; thus, it is suitable for long straight waveguides and not bends. As shown in Fig. 2.2, the width of 0.7 µm has the largest difference in effective refractive index between the fundamental mode and the other high-order modes; that is why it is selected for the single mode waveguides bends. A width of 3 µm is sufficient for high-field confinement operation. 12 Silicon = 1.550 µm 0.22 µm W 0.7 Multi-mode WG Single-mode WG Figure 2. 2 Refractive index of silicon waveguide versus the waveguide width, showing the different optical modes and the region of single-mode and multi-mode widths. This work realizes low-loss optical delay lines that are laid out in a meandered way with three enabling features (Fig. 2.3). The 4.5-mm-long straight regions of the structure are realized as 3- µm-wide multimode waveguides (MM-WG), spaced with 5 µm pitch. The length of this straight waveguide is limited by the available die size (5 mm x 5 mm). The lower limit for the spacing between the adjacent waveguides is determined by the power coupling and the loss of the tighter U-turn bend. In our implementation, the latter is the limiting factor as the power coupling between two wide-core waveguides with high confinement is very small (less than 30 dB based on the evenodd mode simulation across 4.5 mm). From the symmetric waveguide coupling (Fig. 2.4) equation [34], for total coupling length of 5 mm and coupling less than -30 dB, the required Lπ should be larger than 25 cm. The mode simulation of Lπ verus the gap between two 3 µm waveguides is 13 shown in Fig. 2.5. The minimum gap needed to achieve Lπ =25 cm is 0.5 µm; this makes the waveguide pitch is 3.5 µm. To add some margin, we chose a gap of 2 um, which is 5 um center to center pitch. SM-WG Bend Taper MM Straight WG 0.1 mm 0.1 mm L= 4.5mm 5 mm Figure 2. 3 Proposed geometry of the low-loss silicon photonics delay line showing the dimensions. Si Waveguide W =3 µm g W =3 µm Symmetric Waveguides Pi Pc L =5 mm Si Waveguide Figure 2. 4 Symmetric waveguides coupling. 14 Minimum Pitch= 3.5 µm FDE Mode Simulations 250 mm Figure 2. 5 The mode simulation of Lπ versus the gap between two symmetric 3 µm waveguides. At the two ends of the straight region, 0.1-mm-long waveguide tapers are used to narrow the waveguide width to 0.7 µm to obtain a single-mode waveguide (SM-WG). A parabolic shape taper, as shown in Fig. 2.6(a), has been used to obtain a smaller loss compared to the regular linear shape tapers [35,36]. Figure 2.6(b) compared the simulated loss of the linear and the parabolic taper for different lengths. The waveguide U-turns that connect two adjacent straight waveguides with 5 µm spacing use such 0.7 µm single-mode waveguide regions with an Euler geometry [37,38] to lower the loss. Euler bends has lower loss compared to circular bends, as shown in Fig. 2.7(b). To reduce the loss, we use two smoothly changing (7o ) bends leading to a 5-µm-radius 180o bend. The detailed geometry is shown in Fig. 2.7(a). The total traveling length of the U-turn bend is 64 µm and the total loss is 0.0045 dB. The U-turn section is wider than the waveguide pitch, thus an interleaved layout is used as shown in Fig. 2.3. The number of sections of the proposed structure can be adjusted to realize various delay values. The proposed delay line structure was fabricated using PH18MA Tower Semiconductor Silicon Photonics (SiP) process. 15 3 µm 0.7 µm 100 µm y W(y) W(y)=0.7+0.00023(100-y)2 Loss=0.013dB 0.013 dB (a) (b) Figure 2. 6 Low-loss taper implementation. (a) Detailed geometry of the single mode to multimode waveguide taper along with the FDTD loss simulation results. (b) FDTD simulated loss of linear and parabolic tapers for different lengths. Euler Bend q=180O L=22.8 µm Euler Bend q=7O L=20.6 µm 5 µm 31.7 µm 10 µm Total Length=64 µm Loss=0.00045dB 0.7 µm 0.0035 dB (a) (b) Figure 2. 7 Low-loss U-turn bend implementation. (a)Detailed geometry of the 180° clothoid bend along with the FDTD loss simulation results. (b) FDTD simulated loss of circular and euler 180° bends for different diameter. 16 Figure 2. 8 Chip micrograph of the fabricated delay line with a zoom-in to the 180° clothoid bend. 2.1.2 Measurement Results A cut-back method was intended to measure the loss of the delay line and the U-turn bends. Three different structures were designed with different total straight MM-WG lengths (0.3 m, 0.6 m, and 0.9 m), by changing only the length of the straight MM-WG and keep the same number of bends (585). MZI can’t be used to characterize the loss of such a long device, as it will cause a very short free spectral range (FSR), making it very hard to measure the peak to null ratio of the MZI output. Figure 2.9, shows the measured optical loss values with respect to a reference structure (two grating couplers connect back-to-back). A reference test structure consists of direct connect grating couplers was used to de-embed the coupling and the fiber array loss. From the slope we can get the loss of the MM-WG to be 3.3 dB/m or with respect to the introduced delay it is equivalent to 0.25 dB/ns. From the zero-length structure we can get the loss of the bends, it is equal to 0.048 dB per U-turn (two tapers and one 180o bend). Given the maximum die size (5 mm), we need around 19 bends to implement 1 ns of delay corresponding to 0.91 dB of loss. The total loss after adding the 1 ns MM-WG length (0.25 dB) is around 1.16 dB. This number can be reduced accordingly be using larger die sizes to reduce the number of the U-turns bends or by further improving the design of the U-turn bends. The proposed delay line design is very area efficient, per unit delay it consumes 0.5 mm2 /ns. 17 LossWG dB/m dB/ns LossBend+Taper dB Figure 2. 9 Measured loss of the delay line across four different chips using the cut-back technique showing direct loss of three different delay lines lengths (0.3 m, 0.6 m, 0.9 m) in addition to the estimated loss of the straight multimode wide waveguide per unit length and delay. 2.2 Variable Binary-Coded Delay Line We used the same technology TowerJazz (PH18MA) to experimentally demonstrate a digital variable delay line system using the delay line structures that is described in the previous section. 2.2.1 Design and Implementation The structure, shown in Fig. 2a, consists of eight cascaded parallel paths one has delay line structure and one with zero (neglected) delay, separated by 2x2 MZI optical switches. By configuring each optical switch Bar and Cross setting we can control the total delay of the whole structure. The eight delay lines have delays values follows a binary pattern of 3.2 ns, 1.6 ns, 0.8 ns, 0.4 ns, 0.2 ns, 0.1 ns, 0.05, and 0.025 ns. The binary pattern is achieved by halving the number 18 (N) of the straight waveguides (L= 4.5 mm) used in the following delay line section except for the three least significant bits (LSBs) where the length of the straight waveguide is halved while using the same number of waveguides (N=2). The corresponding loss of each delay line section is 3.83 dB, 1.89 dB, 0.92 dB, 0.44 dB, 0.2 dB, 0.08 dB, 0.06, and 0.04 dB, respectively. G C VC1 VC2 N= 16 t= 0.8 ns N= 32 t = 1.6 ns N= 64 t= 3.2 ns VC3 VC4 N= 8 t= 0.4 ns VC5 Optical Switch Delay Line DL1 DL2 DL3 DL4 N= 2 t = 0.1 ns N= 4 t= 0.2 ns VC6 VC7 N= 2 t = 0.05 ns VC8 DL5 DL6 DL7 N= 2 t = 0.025 ns VC9 DL8 Figure 2. 10 Schematic Diagram of the proposed variable switched optical delay line, showing the number of waveguides (N) and delay (τ) of each delay line section and the low loss optical switch layout design. The optical switch layout is also shown in Fig. 2.11. For the phase shifter element, we used a geometrically-optimized, heat-reuse, thermo-optic phase modulator structure (design B in [39]) to achieve low power consumption and low loss [39,40]. Multiple sections of a meandered waveguide are judiciously placed under a single heater to reuse the heat and reduce the power consumption. Low-loss optical Euler bends are used to connect the adjacent waveguides. One phase shifter is used to introduce the required phase difference between the two arms and the other one is just dummy connected to equalize the loss between the two paths. The measured Pπ and loss of the phase shifter are 2.5 mW and 1 dB, respectively. A microphotograph image of the fabricated system is shown in Fig. 2.12, showing a total area of 5 mm x 1 mm. In B C Figure 2. 11 The proposed geometrically-optimized, heat-reuse optical switch 19 Delay Lines I/O GC 1 mm 5 mm 1 2 345678 Ref. GC Figure 2. 12 Microphotograph of the fabricated structure showing the location of each delay line section. 2.2.2 Measurement Results The performance of the optical switch is measured first, as shown in Fig. 2.13. As expected from the phase shifter performance, the measured switching power to switch the laser from one port to the other is equal to the Pπ of the phase shifter (2.5 mW). The estimated loss of the optical switch is around 1 dB as the phase shifter loss dominates over the losses of the two directional couplers. The coupling between the output ports is -18 dB when the switch is in the Bar state and -30 dB when it is in the Cross state. To measure the delay of the different binary configurations of the variable delay line system, we measure the group delay of electrical RF signal passes through the system. We used an external bench-top modulator and optical receiver (photodiode and TIA) to modulate and extract the RF electrical info. A Vector Network Analyzer (VNA) was used to measure the phase of S21 from which the group delay can be extracted. It is important to mention that all the delay measurements 20 are referenced to a zero-delay line (two grating couplers connected back-to-back) on the chip. Thus, the group delay of the other components of the testbench are automatically de-embedded. PSW=2.5 mW PC_B=-30 dB PC_C=-18 dB Figure 2. 13 The heat-reuse optical switch measurement results showing the output power at the bar and the cross ports versus the heater power. Figure 2.14(a) shows the measured delay of the system highlighting the maximum delay, the minimum delay, and the delays of the 16 binary coarse-tuning configurations of the 4 most significant bits (DL: 1-4). A zoomed measurements results of the delay of the 8 binary fine-tuning configurations of the 3 second least significant bits (DL: 5-7) are shown in Fig. 2.14(b). The group delay of the least significant bit (DL: 8) can’t be captures using the VNA. The minimum delay is 0.6 ns, that is correspond to the delay of the optical switches and the routing. The maximum delay when the light passes in all the delay lines is 7 ns, that leads to delay span of 6.4 ns and average measured delay step of 50 ps (25 ps when the least significant delay is enabled) . This structure has a minimum 9 dB loss at the 0.6 ns delay configuration (00000000) because to the nine cascaded 21 optical switches. The loss of the maximum delay of 7 ns (11111111 configuration) is 16.3 dB. This loss can be further reduced by optimizing the design of 2x2 MZI optical switches. To demonstrate the ultra-wideband and high-linear operation of the delay line, an ultra-wide-band (UWB) pulse spanning 1 – 9 GHz, generated using AWG, can be used to measure the delay in the time domain. Figure 2.15 illustrates the measured delayed signals at the output of the variable delay line with different delay settings (the signal pass through one delay section in each setting). The reference delay of the routing and the optical switches is around 0.6 ns. D GDLSB ns (b) XXXX001 XXXX010 XXXX011 XXXX100 XXXX101 XXXX110 GD1111111=7.0 ns XXXX111 GD0000000=0.6 ns D GD4MSB ns (a) 0000000 0001000 0010000 0011000 0100000 0101000 0110000 0111000 1000000 1001000 1010000 1011000 1100000 1101000 1110000 1111000 1111111 Figure 2. 14 Switched optical delay measurements. (c) The group delay measurements of the proposed structure versus the frequency of the modulated RF signals around the optical carrier, showing the minimum and maximum delays and all the coarse tuning 4 MSBs (DL1-DL4) configurations’ delays (d) The measured relative group delays of the fine tuning 3 LSBs (DL5-DL7) configurations. = 0.65 ns = 0.68 ns = 0.73 ns = 0.81 ns = 1.04 ns = 1.46 ns = 2.28 ns = 3.89 ns Figure 2. 15 Optical 8-bit switchable delay line time domain measurements using 8 GHz bandwidth UWB modulated signal, showing the delay values of the 8 delay line sections. 22 The binary switched delay line has a delay resolution of 25 ps. Some applications require continuous tuning of the delay value. In this case, a continuously tuned variable delay line may be needed after the proposed switched delay line to provide a 25 ps fine-tune delay. This can be implemented using a microring modulator, but this approach suffers from thermal sensitivity and narrow wavelength operation. A similar structure to that used to implement the efficient heat reuse phase shifter can be used to implement that fine-tuned delay line. With a stretched design of this phase shifter (with a heater length of 1.8 mm Fig. 2.16), a continues tuned delay of 93 ps/W can be achieved. To provide a tuning span of 25 ps, 270 mW of heater power is needed. LH=1.8mm Figure 2. 16 Proposed continuously tuned delay line 2.3 Application Example: Self-interference Canceller In wireless systems that support simultaneous transmit and receive (STAR), including full-duplex wireless schemes, the transmit signal can desensitize or even saturate the receiver. This so-called self-interference must be reduced at the receiver frontend to avoid unwanted saturation [41]. Selfinterference cancellation circuitry creates an auxiliary path between the transmitter and receiver to mimic the unwanted leakage path, and uses a subtractor to remove the leaked self-interference (Fig. 2.17). The auxiliary path generally consists of a bank of delays and attenuators, emulating the propagation delays and losses between the transmitter and receiver [42]. Using optical true delay line instead of electrical ones to implement the self-interference canceller has the advantage of lower loss and wider bandwidth. The drawback is the electrical-optical-electrical conversion 23 that consumes power [43]. In some prior work, the transmit and the receive signal are both converted to optical domain where delay, attenuation, and subtraction occur [44,45]. In this work, the delay in the transmit replica path is implemented in the optical domain, while the signal subtraction happens in the electrical domain. As an initial prototype, a one-tap optical selfinterference canceller is demonstrated [46]. Self-interference Canceller RX TX t a SRX STX,SI STX,c Figure 2. 17 RF self-interference cancellation concept. 2.3.1 Experimental Setup The optical delay used to build the self-interference canceller is implemented using low-loss optical delay lines described in the previous section [32]. In order to cancel different selfinterference signals, the variable switched switched binary scheme is used. Figure 2.18, shows the experimental setup using the optical delay line chip to perform a one-tap self-interference cancellation. A directional coupler is used to couple a small portion (-10 dB) of the transmitted RF signal from the main transmitter path to a replica path. This signal is then modulated on an optical carrier using Mach Zehnder intensity modulator (MZM), and fed to the switched delay-line silicon photonic integrated circuit. The delayed output signal is then converted back to the electrical 24 domain using an external optical receiver (photodiode and transimpedance amplifier). A variable gain amplifier is used to balance the amplitudes of the two paths prior to subtraction using a 180o hybrid coupler. Delay Line PIC IR laser Intensity Modulator Polarizer PD TIA Optical Rx Front-End R Fop R Fip D C DC Source BiasT VRF-op Electrical Amplifier Electrical Amplifier VRF-in C=-10 dB Coupler C=-3 dB Coupler Variable Gain Amplifier Transmitter Receiver Self-interference Path Replica (Cancellation) Path Figure 2. 18 Experimental setup testbench diagram of the self-interference cancellation measurements. 2.3.2 Measurement Results To demonstrate the ultra-wideband operation of the self-interference canceller, an ultra-wide-band (UWB) pulse spanning 1 – 9 GHz, generated using AWG, is used as the input. The selfinterference cancelling measurements is demonstrated using the setup shown in Fig. 2.18. We mimicked a self-interference path with 3 ns group delay between the two antennas using coaxial cable. The detected UWB pulse at the receiver output when the cancellation is enabled/disabled (the optical delay line path is connected/disconnected) is shown in Fig. 2.19. A wideband (8 GHz) self-interference cancelling is achieved with cancelation depth of 14 dB, this value can be improved by using a linear optical modulator. The spectrum of the receiver output signal is shown in Fig. 2.20. This amount of cancellation can be sufficient at the receiver front-end (RF section). Further cancellation is needed in the analog and the digital part of the receiver. Future work 25 includes extending the scheme to a multi-tap implementation and reducing the loss in the optical path (especially coupling loss between the fiber and PIC). 14 dB Figure 2. 19 Receiver output RF voltage (VRF-op) time response of 8 GHz bandwidth (1-9 GHz) UWB transmitted signal with and without the self-interference cancellation. Figure 2. 20 Receiver output RF voltage (VRF-op) spectrum response of 8 GHz bandwidth (1-9 GHz) UWB transmitted signal with and without the self-interference cancellation. 26 2.3.3 Linear Optical Modulator Most of the applications that require optical analog signal processing (like self-interference cancellation, microwave photonics, and RF over fiber) need an optical modulator to convert the data to the optical domain. In this work, we propose a linear single-side band optical modulator [47]. Using a linear modulator can increase the cancellation of the self-interference canceller to more than 14 dB. Such systems requiring high linearity need an optical modulator that can reject the carrier, sideband, and most of the harmonics components. Rejecting the unwanted frequency components of the optical modulator can be done using high Q filters at the output of the modulator or using a Dual MZI in a quadrature modulation style [48-50]. Figure 2.21 shows the schematic diagram of the proposed single-sideband optical modulator. The optical signal is divided and routed to four charge depletion modulators (in dual MZIs configuration) that are modulated with quadrature (90o phase difference) RF signals (+I,-I,+Q,-Q). The phase difference between each MZI branch pair should be set to 180o (using heater phase shifter (PS)) to cancel the carrier and the even harmonics at the output of each MZI. To calibrate that phase difference, we used a photodiode to sense optical power at both the MZIs outputs when there is no modulation signal (VRF). The relative phase between the two MZIs determines which sideband signal is rejected and which exists (0o : right sideband signal, 180 o : left sideband) as shown in Fig. 2.21. The proposed structure is designed mainly using SiN waveguides (Fig. 2.21) because of its higher power handling capability than Si waveguides [51,52]. The only silicon waveguide part is the dual MZI arms, as it includes charge depletion modulators. This ensures that the whole structure has at most four times the power handling capability of all Si waveguide modulators. The integrated single-side band modulator is fabricated using Tower Semiconductor (PH18MA) SiP process (Figs. 2.22 is a chip Micrograph). 27 P n +I=VR F(t)ej0° VH(+I) P n -I=VR F(t)ej180° VH(-I) P n +Q=VR F(t)ej90° VH(+Q) o q+Q=9 0 P n -Q=VR F(t)ej270° VH(-Q) VH(I) o /180 o qQ=0 Charge Depletion Phase Mod. Photodiode Heater Phase Shifter Grating Coupler MMI SWG NWG Coupler (90:10) o q-Q=270 o q+I=0 o q-I=180 o qI=0 PI/p Po/p 0 +1 +2 +3 -5 -4 +4+5 -3 -2 -1 -5 -4 0 +1 +2+3 +4+5 -3 -2 -1 0 +1 +2 +3 -5 -4 -3 -2 -1 +4+5 wc 0 0 +1 +2+3 +4+5 -5 -4 -3 -2 -1 o qQ=0 o qQ=180 Figure 2. 21 Schematic diagram of the single side band optical modulator showing the required phase relations at each point and the optical harmonics spectrum at the main nodes. 0.8 mm 5 mm 1 mm I/O GC EO Mod. Trans. Line +Q-Q +I -I GSGSG PS Figure 2. 22 Microphotograph of the fabricated single side-band modulator, showing the location of the building blocks and the major dimensions. The power handling capability is measured (Fig. 2.23) by testing the input-output optical power characteristic of the SSB modulator. It shows a linear response up to 22 dBm (160mW) of input 28 power. The measured loss is 7 dB (3 dB EO modulator, 1.7 dB SiN PS, 1 dB Si PS, 1.3 dB MMIs, and Si-SiN WG converters). The SSB modulator was tested with 100 MHz and 1 GHz RF signals. To detect the +ve and -ve modulation harmonics, a high-resolution optical spectrum analyzer is needed. Otherwise, as shown in Fig. 2.24, the modulator output can be mixed with another laser shifted by ωIF in frequency (5 GHz and 10 GHz for 100 MHz and 1 GHz RF signals, respectively) around wavelength of 1550 nm. The second-order intermodulation component (ω1- ω2) that includes all the modulator harmonics will appear at ωIF after the photodiode and can be detected using electrical spectrum analyzer. The output power spectrums of both test signals are shown in Fig. 2.25(a) and Fig.2.25(b) for both right and left single sideband settings. The SSB modulator achieves ̴20 dB sideband rejection and ̴16 dB carrier rejection. The results of the 1GHz RF signal left and right single-sideband settings are different because of the photodiode frequency response, which has 11.5 GHz BW3dB. Better results can be achieved by calibrating the quadrature optical signals amplitude and phase imbalances. Optical Loss 7dB Figure 2. 23 Optical linearity measurement results showing the output power vs input power response and the measured optical loss of the modulator. 29 DUT Polarizer Tunable Laser Coupler 50:50 (Combiner) PD TIA Optical Rx Front-End VRF-in VRF-op Fixed Laser +I -I+Q-Q w1 w2 =w1 - wIF 0 wIF w2 w1 wIF Figure 2. 24 Test setup schematic diagram showing the fiber array coupling and the RF signals connecting to the chip (DUT), the power harmonics spectrum at the main points are also shown. 15 dB 0 18 dB -3 -2 -1 + 1 + 2 + 3 (b) 17 dB 0 22 dB -3 -2 -1 + 1 + 2 + 3 o qQ=0 o qQ=180 16 dB 0 20 dB -3 -2 -1 + 1 + 2 + 3 15 dB 0 20 dB -3 -2 -1 + 1 + 2 + 3 (a) o qQ=0 o qQ=180 Figure 2. 25 The output power spectrum of the best measured single sideband and carrier rejection operation for (a) 100 MHz and (b) 1 GHZ modulation RF signals, showing both right and left side-band cases. 30 Chapter 3 Optically Biased and Controlled Signal Processing Silicon photonics integrated circuits (Si PICs) are now at the heart of high-speed, energy-efficient fiber-optical communication transceivers utilized within data centers [53,54]. Si PICs are major enablers of distributed processing of large-scale AI/ML models [55,56]. In these scenarios, data processing still predominantly takes place in the electrical domain, necessitating opto-electric (O/E) and electro-optic (E/O) data domain conversions. Our hypothesis is that performing proper signal processing on the optically-modulated data may reduce the power consumption and latency across the system while maintaining security. Optical signal processing may occur at different remote nodes across an optical network [57,58]. Providing uninterrupted and reliable electrical power and control signals to some of the nodes may be costly or not possible. In these cases, the required power and control signals may be provided optically from a remote site. A remotely powered, controlled, and monitored optical switching, radio over fiber system, and data sequence detection was demonstrated in a benchtop setting [59-64]. It is possible that other systems such as optical phased array lidars and radio over fiber transceivers implemented in Si PIC [65,66], where the information already resides in the optical domain, benefit from optical signal processing as well. 31 In this chapter, we demonstrate photonic integrated circuits (PIC) capable of performing basic optical signal processing tasks: (1) amplitude modulation and switching, (2) two-tap sequence detection [67]. 3.1 All-Optical remote biasing and controlling concept The proposed all-optical remotely controlled and biased signal processing system uses optical signals to bias and control the optical processing unit. Different wavelengths may be used to carry the data, control, and bias optical channels. The control and bias signals were delivered in the same fiber link with the main optical data in a WDM configuration. The conceptual schematic of our all-optical signal processor is shown in Fig. 3.1. A wavelength demultiplexer, realized as an array of series-coupled microring resonators, is used to separate the optical signals that carry data, control, and bias. The optical data provides the input to the optical signal processor. The control and biased optical signals are fed to optical-power-to-voltage converters realized as series stacked photodiodes operating in photovoltaic mode. The generated voltages are then used to bias and control the optical signal processor. This work is realized in the Tower Semiconductor commercial silicon photonics process (PH18MA) featuring silicon thickness of 220 nm on top of a 3µm buried silicon oxide layer. Single mode strip Si waveguide with 500 nm width is used in most of the designs. Optical Power to Voltage Converters lD Optical Signal Processor lC1 - lcn ld Wavelength Demultiplexer Input Data Control/Bias Signals Vc1 - Vcn Output Optical Data lCi Silicon Photonics Chip Input Optical WDM Signal P P P P P Figure 3. 1 Conceptual diagram of the all-optical signal processor. 32 3.2 Building Blocks The complexity of the optical signal processing unit determines the wavelength demultiplexer number of channels and the optical voltage converter maximum output voltage. In this section, different design sizes are introduced to accommodate different processing unit complexities. 3.2.1 Wavelength Demultiplexer The wavelength demultiplexer, shown in Fig. 3.2(a), is implemented using an array of microring resonator filters. To be more tolerant to the fabrication and temperature variations, the filters are designed to have a wideband and flat-top response. We used five identical series-coupled ring resonators to implement each filter [68,69]. The coupled ring resonators have a race-track geometry with low loss 180o Euler bends. The resonators were designed to have a small strip waveguide width of 0.4 µm so that the required coupling coefficient can be achieved with a smaller coupling length. The Euler bends have end-to-end gap of 5 µm and simulated loss of 0.07 dB. These result in a high-quality factor (Q) resonator with a smaller roundtrip length (Lrt) and wider free spectral range (FSR). Using symmetric coupling coefficient between the coupled rings introduces large ripples in the passband region of the filter. To achieve a flat top response from the series coupled ring resonator, their power coupling coefficient from top to bottom (including busring coupling as shown in Fig. 3.2(a), are designed to be 0.45, 0.09, 0.05, 0.05, 0.09, and 0.45, respectively [69]. The coupling coefficients are controlled by adjusting the corresponding coupling gaps. The gaps between the bus-ring and the ring-ring waveguides from top to bottom are 0.2 µm, 0.32 µm, 0.37 µm, 0.37 µm, 0.32 µm, and 0.2 µm, respectively. The roundtrip lengths (Lrt) of the first channel resonators’ are 25.7 μm. The Lrt of the subsequent filter channels are incremented by 0.24 μm, 0.14 μm, and 0.11 μm steps for the three, five, and seven channel designs, respectively. 33 These values make the channels equally spaced within the FSR of the ring resonators. Three different wavelength demultiplexer designs were fabricated with number of channels (Nch) of 3, 5, and 7. Figure 3.2(b) is a micrograph of a 3-channel wavelength multiplexer. (a) N Input WDM Signal ld lc1 lcn P P P Euler Bend q=180O L=9.4 µm Lrt Ch.1 Ch.2 Ch.N Output Seperated Signals Output Monitor Signal K=0.45 K=0.09 K=0.09 K=0.45 K=0.05 K=0.05 ch (b) 10 µm Figure 3. 2 Wavelength demultiplexer fabricated designs and measurement results. (a) Schematic diagram of the series coupled ring resonator-based wavelength demultiplexer showing the main design specs. (b) Micrograph of the fabricated 3-channel wavelength demultiplexer. The measured transfer function of the drop ports of the ring resonators are shown in Fig. 3.3. In all the measurements in this chapter, grating couplers and fiber array are used to couple the optical signals into and out of the fabricated chip. The total measured coupling loss is around 8 dB, this includes both the grating coupler and the fiber array losses. The insertion loss of the filters varies between 2 to 5 dB. Each filter has 3 dB bandwidth (BW-3dB) of 2.4 nm and free spectral range of 23 nm. The channels center to center spacing are 7.6 nm, 4.6 nm, and 3.3 nm for the three, five, and seven channel designs, respectively. 34 Nch= 3 Nch= 5 Nch= 7 Figure 3. 3 Measured transfer function of three different coupled ring resonators wavelength demultiplexer designs with different number of channels (Nch), 3-channel, 5-channel, and 7-channel. The measured filter responses aren’t perfectly flat top likely due to the fabrication mismatches between the five coupled rings round-trip phases and the coupling between them. Behavior model Monte-Carlo (random process variation) simulation (Fig. 3.4) was used to compare the transfer function variation of the coupled ring versus a regular series ring resonator. The single ring suffers from large center wavelength shifts. The simulation results was also used to check the yield of the filter response with random refractive index and coupling coefficient variations; the transfer function achieved acceptable ripples (<2 dB) for 95% of the samples. This fabrication variation can be later calibrated using micro-heaters on top of the coupled rings and the coupling regions. A standalone single ring resonator version of the wavelength demultiplexer was measured (Fig. 3.5). Although the resonance wavelength of the single ring resonators is more sensitive to the fabrication variation, but luckily all center wavelength of the channels are shifted almost was the same amount, keeping the distance between the channels almost the same (not as agood as the coupled ring resonator design). However, the local temperature variation still a challenge for this design of wavelength demultiplexer. 35 (a) (b) Pin Pout Pin Pout Figure 3. 4 Monte-Carlo simulations of coupled ring resonator and single ring resonator, (a) and (b), respectively. Nch= 3 Nch= 5 Nch=7 Figure 3. 5 Measured transfer function of three different single ring resonators wavelength demultiplexer designs with different number of channels (Nch), 3-channel, 5-channel, and 7-channel. 3.2.2 Optical Power to Voltage Converter Photodiode is the opto-electro device that absorbs the optical power and converts it to electrical current and voltage. There are two modes of operation of the photodiodes, photovoltaic and photoconductive (as shown in Fig. 3.6). The photovoltaic mode is when the photodiode operates 36 in the forward region due to its built-in generated voltage without any external bias. This mode has nonlinear transfer function between the input optical power and output electrical voltage, and it operates in low-speed modulation or DC cases due to its large output impedance. On the other hand, the photoconductive uses external supply voltage (VDD) and resistance to bias the photodiode in the reverse region and to obtain the output voltage across the resistance. VD ID VOC RL VDD VDD RL Pi p Photoconductive Photovoltaic 0 Pip Vop Pip PD Vop VDD RL PD Vop Pip VDD Vop 0 Pip VOC Figure 3. 6 Photodiode modes of operation showing the I-V diode characteristics, circuit implementation, and input optical power to output voltage transfer function. In this design, a set of series stacked photodiodes operating in the photovoltaic mode (Fig. 3.7(a)) are used to convert the optical control and bias signals to the corresponding DC control voltages depend on the optical power values of these signals [64,70]. The maximum voltage generated across one non-biased diode operated in the photovoltaic mode is limited by the photodiode open circuit voltage (≈0.35 V for Germanium photodiode). By connecting the photodiodes in series configuration, the maximum generated voltage can be expanded as the 37 voltages across each diode are added in series. A multi-mode interferometer (MMI) based distribution network is used to deliver the input optical control signal to the photodiodes. The photodiode in the photovoltaic mode has the advantages of not needing electrical bias; but, on the other hand, it is inefficient for driving a low resistance load (it works best with capacitive loads that do not drain DC current). Hence, it is more suitable to bias charge depletion modulators and not charge injection or thermo-optic modulators. Five different optical power to voltage converters with numbers of series photodiodes (Npd) of 1, 2, 4, 8, and 16 were fabricated. We used the PH18MA Tower Semiconductor PDK Germanium on Silicon vertical P-I-N photodiode, where a germanium layer is formed on top of the Si strip waveguide to absorb the light. The photodiode width is 8.6 µm and the length is 15 µm. Tapers are used to connect the 0.5 µm MMI network waveguides to the 8.6 µm PD waveguides. A micrograph of the fabricated optical to voltage converter with Npd=16 is shown in Fig. 3.7(b). lCi P MMI PD Npd VCi (a) (b) 10 µm MMI Taper PD 50 µm Figure 3. 7 Optical power to voltage converter fabricated designs based on series stacked photovoltaic photodiodes. (a) schematic diagram, (b) chip micrograph of 16 stacked photodiodes, with a zoomed-in micrograph of 4 photodiodes. Figure 3.8, shows the current-voltage characteristic of the fabricated photodiode when the input power ≈ 3 mW. The measured open circuit (ID=0) voltages of the combined series photodiodes are 0.35 V, 0.7 V, 1.25 V, 2.35 V, and 4.2 V, respectively. The measured converted output DC voltage versus the input optical power is shown in Fig. 3.9. As expected, the output voltage starts to saturate as it reaches the diode open circuit voltages. The optical power to voltage 38 converter design with Npd=16 converts a 1.5 mW input optical power to 3.75 V output DC voltage. The control signal speed is limited by the optical to voltage converter bandwidth. In our design using photovoltaic diodes, the measured bandwidth is around 10 MHz which is sufficient for controlling or calibrating the optical processor. On the other hand, using photoconductive photodiodes can extend the bandwidth to GHz range, but it requires biasing. (a) (b) Figure 3. 8 Measured current voltage characteristic of the stacked Si-Ge photodiodes for different numbers of series photodiodes: 1, 2, 4, 8, and 16. Figure 3. 9 Measured open-circuit output voltage versus input optical power for different numbers of series photodiodes (Npd): 1, 2, 4, 8, and 16. 39 3.3 All-Optical Signal Processing Demonstration In this section, we demonstrate two examples of the all-optically controlled and biased signal processor using the building blocks mentioned in the previous section. The first prototype is an amplitude modulator, and the second prototype is a two-tap sequence detector. 3.3.1 Amplitude Modulator One of the simplest optical signal processors is the amplitude modulator which is used in most of the integrated photonics systems. Our amplitude modulator is implemented with balanced MachZehnder Interferometers (MZI) with charge depletion phase modulators, as shown in Fig. 3.10(a). The driving voltages of these phase modulators are derived optical power to voltage converters. The required driving voltage of these modulators should be small; otherwise, the required optical power needed to generate the driving voltages will be large. Thus, these modulators should be designed to be long and efficient (low Vπ.L). The length of the implemented modulators is 4.85 mm limited by the 5 mm × 5 mm available die area. The ridge waveguide used to implement the phase modulator has a strip width of 0.5 µm. To improve the modulator efficiency, a shifted pnjunction modulator geometry is used [71,72]. It is well known from the plasma effect that the hole concentration change introduces more phase shift to the optical field than the electron concentration change [73]. Therefore, the pn junction is shifted by 50 nm from the center to maximize the hole density in the center of the waveguide where the optical field is maximum. A standalone MZI is used to test the 4.85 mm length charge depletion modulator; the measured Vπ is around 3.75 V (Vπ. Lπ=1.8 V.cm). The measured loss is around 12.5 dB (2.5 dB/mm). The amount of required optical power at the optical to voltage converter input to generate that Vπ voltage is 1.5 mW. The amplitude modulator is a balanced design with phase modulators in both 40 arms of the MZI to achieve a high extinction ratio. The control signals feeding the modulators are either CW or low-speed modulated waveforms. Therefore, the modulators need not be designed to support high modulation speeds. The two phase modulators are controlled independently through separate optical power to voltage converters each realized as 16 series stacked photodetectors. Three wavelengths, one for input data and two for phase modulator control voltages, are needed in the proposed WDM scheme. A three-channel wavelength demultiplexer is used to split these signals. The wavelengths used for the data and control signals are centered at 1546 nm, 1553 nm, and 1559 nm, respectively. The total active area of the fabricated all optical amplitude modulator is around 0.6 mm2 , as shown in Fig. 3.10(b). Np d=16 Np d=16 Vc Va P n P n Va Vc 3 Channels Wavelength DeMux 2 Optical to Voltage Converters MMI Charge Depletion Phase Mod. Grating Coupler Amplitude Modulator Input Output Monitor ld P lc1 P lc2 P VC1 VC2 P M1 P M2 4.85 mm Ch.2 1546 nm Ch.3 1553 nm Ch.1 1559 nm ldip P lc2ip P lc1ip P ldop P (a) (b) 5 mm Intput Output Monitor I/O GC WL DeMux OV Conv. 0.6 mm Amp. Mod. 0.1 mm Figure 3. 10 Optically-controlled amplitude modulator: (a) schematic diagram, (b) fabricated device micrograph. To measure the all-optical controlled performance of the amplitude modulator, two tunable laser sources (one for the input power and one for control signal) are combined using a 50:50 coupler. The output of coupler carries the input wavelength division multiplexing signal that is then inserted to the fabricated chip. The measured output optical power versus the optical power 41 of the control signals at each of the phase modulators in the balanced MZI are shown in Fig. 3.11. Due to fabrication mismatches between the two MZI arms, the response of the amplitude modulator as a function of the two phase modulators are not identical. The measured results show that the amplitude modulator can be fully tuned using 0.25 mW and 18.8 mW optical power when controlling PM1 and PM2, respectively. The corresponding output power peak to null ratios are 15 dB, and 18 dB, respectively. 15 dB 18 dB 0.25 18.8 Figure 3. 11 Optically-controlled amplitude modulator measurements showing the output power versus the input optical control powers that control the two arms of the amplitude modulator MZI. By using a 2×2 coupler at the input and the output of the balanced MZI instead of the MMI, an all-optically controlled optical switch may be realized. The output coupling to the bar and the cross ports depends on the phase difference between the MZI arms. A standalone voltage driven (not all optical controlled) version was fabricated as shown in Fig. 3.12. 42 Vc Va P n P n Charge Depletion Phase Mod. Output VC1 VC2 PM1 4.85 mm Directional Coupler Pout,C Optical switch Input Vc PM Va 2 Pout,B Pin Figure 3. 12 Schematic diagram of electrically-controlled optical switch. The coupling between the output ports is -20 dB when the switch is in the cross state and -27 dB when it is in the bar state, as shown in Fig. 3.13. The loss of the optical switch is around 12.5 dB as the phase shifter loss dominates over the losses of the two directional couplers. The amount of voltage required to operate the optical switch in the bar and the cross states are 0.5 V and 4 V (VC1), respectively. In case of all-optical scheme is used, these values of voltage correspond to optical control power values of 0.1 mW and 2.25 mW, respectively. PC,C=-17 dB PC,B=-16 dB VSW=3.5 V PC,B=-27 dB PC,C=-20 dB (b) (a) Figure 3. 13 Electrically-controlled optical switch measurements showing the output power versus the input electrical control voltages that control the two arms of the optical switch MZI: (a) VC1 (upper arm), (b) VC2 (lower arm). 43 3.3.2 Two-Tap Sequence Detector To demonstrate the proposed all-optical controlled signal processing system with a more complex processing unit, an all-optically-controlled two-tap symbol sequence detector is implemented. This function can be obtained by coherently adding the input data stream to a delayed version of itself. This can be implemented using two feedforward waveguides in an asymmetric MZI scheme [63,74] where one branch includes a delay line equal to the symbol rate of the modulated optical input data. The functional operation is as follows: (1) the input optical data stream is equally divided to two branches; (2) the data in one branch is delayed by a symbol period; (3) the carrier phases of both branches are matched, and (4) the resulting signals from two branches are combined again. As an illustrative example, let us assume an OOK modulation where the optical power is for the “1” symbol and for the “0” symbol. Assuming lossless implementation, the optical output power level will be when two consecutive ones (11) appear at the input, when two consecutive zeros (00) appear at the input, and 0 25(√ + √)^2 when a sequence of (01) or (10) appears in the input. Therefore, this scheme can discriminate (00), (11), and (10)/(01) sequences. To discriminate (10) versus (01), intentional mismatch can be introduced in the loss of the two arms of the asymmetric MZI. As an example, assume the optical loss in the delayed arm in the otherwise lossless structure is < 1. The output power levels corresponding to (00), (01), (10), and (11) sequences of an OOK modulation will be 00 0 25(1 + √)^2 , 01 0 25(√ + √√)^2 , and 10 0 25(√ + √√)^2, and 11 0 25(1 + √)^2, respectively. These are four distinct levels that can discriminate the input consecutive symbol sequences, however these levels cannot be equally spaced. In a special case where ≅ 0 and ≅ 0 5, the output optical power levels corresponding to (00), (01), (10), and (11) sequences will be 44 0, 0 125, 0 25, and 0 73, respectively. Figure 3.14 shows the modelled output of a twotap sequence detector in this case. t f PIN(t) POUT(t) a Loss=L 0.5*PH 0.5*PL 0.5*PH 0.5*PL L*0.5*PH L*0.5*PL 0.5*PH a=1 f=0 0.5*PL PH PL 1 0 P00 P01 P10 P11 00 01 10 11 Figure 3. 14 Conceptual diagram of the two-tap sequence detector showing the dynamic response for an OOK input data. The schematic level diagram of the all-optically controlled two-tap sequence detector is shown in Fig. 3.15. In this design, the delay line is constructed in a meandered layout consisting of lowloss multi-mode straight waveguides, single-mode Euler waveguide bends, with parabolic tapers connecting the two [32]. An amplitude modulator is realized before the asymmetric MZI to control the input data power ratio in the MZI arms. This ratio may be adjusted to provide the desired discrimination levels in the detected consecutive bit sequences. The amplitude modulator implementation is similar as that described in the previous section, a balanced MZI with charge depletion phase modulators. A 2×2 coupler is used at the output to route the weighted portion of the optical data to the two arms of the asymmetric MZI. Charge depletion phased modulators are used in the asymmetric MZI arms to compensate for the phase mismatch due to the fabrication mismatch and the delay line induced phase. This system uses a three channel wavelength demultiplexer to separate the input data steam and the two optical signals that control the amplitude and phase modulators. The two control optical signals are then converted to electrical voltage using an optical to voltage converter with 16 series stacked photodiodes. To reduce the design complexity, only the phase modulator in one arm of the amplitude modulator and the asymmetric MZI are controlled. The fabricated design micrograph is shown in Fig. 3.15. While a two-tap scheme is demonstrated, the approach may be extended to larger number of taps for detecting 45 longer data sequences. The number of taps can be extended by using lattice configuration (cascaded MZI) with incremental delay values equal to the integral multiplication of the symbol rate. For example, a 4-tap correlator will have two cascaded MZIs with delay lines of 0T, 1T, 2T, and 3T [63]. (a) Np d=16 Np d=16 Vc Va P n P n 3 Channels Wavelength DeMux 2 Optical to Voltage Converters Charge Depletion Phase Mod. Grating Coupler Amplitude Modulator Input Output Monitor ld P lc1 P lc2 P VC1 VC2 P M1 P M2 4.85 mm Ch.2 1546 nm Ch.3 1553 nm Ch.1 1559 nm ldip P lc2ip P lc1ip P Directional Coupler t = 0.8 ns Delay Line Vc Va P n P n 4.85 mm ldop P ldop P Asymmetric MZI 2-Tap Correlator EA EB (b) 5 mm I/O GC WL DeMux OV Conv. 0.6 mm Amp. Mod. 0.6 mm Delay Line Phase Mod. Figure 3. 15 Optically-controlled two-tap sequence detector: (a) schematic diagram, (b) fabricated device micrograph. The first step of the measurements is to calibrate the amplitude modulator and the asymmetric MZI phase difference. The amplitude modulator can be calibrated by observing the extinction ratio of the system output as the input wavelength or frequency is continuously swept. We used a vector network analyzer (VNA) to perform this measurement. Port 1 of the VNA goes through an external optical modulator to modulate a laser signal. The modulated signal is then fed to the chip. The output is connected to port 2 of the VNA. Measured S21 responses for different values of optical control power signal (Pλc1ip) are shown in Fig. 3.16. The extinction ratio (peak to null ratio) is maximum when the amplitudes of the two MZI arms (EA and EB points) are balanced. The results show that the amplitude modulator control signal power (Pλc1ip) of 2.5 mW, corresponding to the 46 maximum extinction ratio, makes |EA|=|EB|. When Pλc1ip is less than 2.5 mW the optical data power at the delayed (upper) arm is less than the reference (bottom) arm (|EA|<|EB|), and vice versa when Pλc1ip is more than 2.5 mW, |EA|<|EB|. The phase difference between the two arms of the asymmetric MZI can be calibrated by observing the peak and the null point at the output while changing the phase modulator optical control signal (Pλc2ip). When the optical signal at the end of the asymmetric MZI arms are in phase (out of phase), the output is maximum (minimum). The Pλc2ip value of 0 mW and 4.2 mW corresponds to these two cases, when the amplitude modulator is in the equal power configuration (|EA|=|EB|). Figure 3. 16 VNA frequency sweep measurements of the optically-controlled two-tap sequence detector showing the optical transmission for different values of the optical control signal that feeds the amplitude modulator. In order to demonstrate the dynamic measurements, we used an arbitrary waveform generator to generate PRBS and external modulator to generate the optical data to the correlator. Along with 47 the optical data, two optical signals carrying the control signals are combined in a WDM configuration and coupled to the chip. The PRBS optical data is on channel 2 centered at 1546 nm. The optical control signals are inserted on channel 1 (controlling the phase difference of the asymmetric MZI) and channel 3 (controlling the amplitude modulator) centered at 1559 nm and 1553 nm, respectively. The output is then detected using a digital storage oscilloscope. The PRBS data rate is 1.25 Gbps as the delay line used in the two-tap sequence detector has delay of 0.8 ns. Figure 3.17(a) shows the measured output when the optical data at the asymmetric MZI arms’ ends are in phase (Pλc2ip ≈ 0 mW) – this implies that two consecutive bits are added coherently at the output. The optical output is highest when the two consecutive bits are 11, lowest in case of 00, and midway for 10 and 01 cases. The results are reported for three cases. In a first case, Pλc1ip = 2.5 mW resulting in |EA|=|EB|; in this case, the (10) and (01) sequences result in the same output power levels. In a second case, Pλc1ip = 1 mW resulting in |EA|<|EB|; in this case, the later optical bit has larger optical power than the earlier (delayed) optical bit, hence the (01) sequence has larger optical output than the (10) sequence. Finally, in a third case, Pλc1ip = 5 mW resulting in |EA|>|EB|; in this case, the (10) sequence has larger optical output than the (01) sequence. The second and the third cases represent the desired sequence detection configurations as all the four sequences are discriminated. Similar measurements may be conducted (Fig. 3.17(b)) for the case where the optical data at the asymmetric MZI arms’ ends are out of phase (Pλc2ip ≈ 4.2 mW). In this scenario, each two consecutive bits are subtracted, hence the (11) and (00) result in low output power levels, while the (10) and (01) sequences result in high output power levels. The results are reported for the same three amplitude modulator cases and optical control signal (Pλc1ip) values described in Fig. 3.17(a). 48 (a)|EA|=|EB| |EA|<|EB| |EA|>|EB| EA - EB =0o 1 0 00 01/10 11 00 11 01 10 00 11 10 01 (b)|EA|=|EB| |EA|<|EB| |EA|>|EB| EA - EB =180o 1 0 00/11 01/10 01 10 10 01 00 00 11 11 Figure 3. 17 Optically-controlled two-tap sequence detector dynamic measurements for OOK input modulated signal. PRBS OOK signal is the input to the correlator (in Red), the optical output of the modulator (in Blue) for three different cases of optical power ratios at the end of the asymmetric MZI branches (three amplitude modulator settings). Top: the power ratio is the same (|EA|=|EB|), middle: the power in the non-delayed arm is larger (|EA|<EB|), and bottom: the power in the delayed arm is larger (|EA|>EB|). This is shown for two cases when the phase difference in the optical fields at the point Ea and EB are in phase and out of phase, (a) and (b) respectively. 49 We also tested the two-tap sequence detector with higher order modulations, PAM-3 and PAM-4 with the same symbol rate of 1.25 Gbaud, as shown in Fig. 3.18, and Fig. 3.19, respectively. As there are more combinations of two-bit sequences, for clarity the results are only shown for one specific case: the optical data at the asymmetric MZI arms’ ends are in phase (Pλc2ip ≈ 0 mW) and have the same power (Pλc1ip = 2.5 mW (|EA|=|EB|)). In this case, there are 6 output optical levels for the PAM-3 input and 10 levels for the PAM-4 input. The proposed structure consists of complex taps (attenuator and phase shifter) can be flexibly adjusted in terms of amplitude and phase, enabling operations on both amplitude and phase-encoded data streams like QPSK and QAM modulated signals. This asymmetric MZI scheme can be used also as FIR filter [75], as shown from the frequency response measurements (Fig. 3.16). However, the delay line should be designed with a smaller value in order to increase the FSR and make it useful as a microwave photonics filter. Also, higher order FIR filter can be implemented by cascading asymmetric MZIs (lattice configuration). |EA|=|EB| EA - EB =0o 0 1 2 00 01/10 02/20 11 12/21 22 Figure 3. 18 Optically-controlled two-tap sequence detector dynamic measurements for PAM-3 input modulated signal. PRBS signal is the input to the correlator (in Red), the output of the modulator (in Blue) for the same optical power ratios at the end of the asymmetric MZI branches (one amplitude modulator setting), the power ratio is the same (|EA|=|EB|). These results are when the optical fields at the point EA and EB are in phase. 50 |EA|=|EB| EA - EB =0o 0 1 3 2 00 01/10 02/20 11 12/21 22 03/30 13/31 33 23/32 Figure 3. 19 Optically-controlled two-tap sequence detector dynamic measurements for PAM-4 input modulated signal. PRBS signal is the input to the correlator (in Red), the output of the modulator (in Blue) for the same optical power ratios at the end of the asymmetric MZI branches (one amplitude modulator setting), the power ratio is the same (|EA|=|EB|). These results are when the optical fields at the point EA and EB are in phase. The loss of the sequence detector is dominated by the loss of the charge depletion phase modulator. The phase modulator loss can be reduced by shortening its length. On the other hand, this will increase the required driving voltage from the optical to voltage converter. This can be achieved by cascading more photodiodes in series. The total power consumption (PT) of the 2-tap sequence detector consists of two portions: the input power consumption (Pin) and the optical-tovoltage converter power consumption (POVC), and it can be expressed as PT= Pin+POVC (Fig. 3.20). The total power consumption can be plotted versus the number of photodiodes of each optical-tovoltage converter. This was obtained for two different scenarios: the target output power of the correlator is fixed value and equal to 0.1 mW (Fig. 3.21), and the of the correlator drives another optical-to-voltage converter to achieve π phase shift (Fig. 3.22). 51 NPD NPD Vc Va P n P n 2 Optical to Voltage Converters Charge Depletion Phase Mod. Amplitude Modulator VC1 VC2 PM1 PM2 Lmod Directional Coupler t = 0.8 ns Delay Line Vc Va P n P n Lmod Asymmetric MZI 2-Tap Correlator Pin POVC Pout PT Figure 3. 20 Two-tap correlator schematic with the different power consumption portions. Figure 3. 21 Two-tap sequence detector power consumption for different optical to voltage converter sizes in the case of targeted output power of 0.1 mW. 52 Figure 3. 22 Two-tap sequence detector power consumption for different optical to voltage converter sizes in the case of driving a optical to voltage converter for π phase shift. 53 Chapter 4 Universal Optical Input-Optical Output Logic Gates Digital logic is ubiquitous in computing and signal processing platforms. The reduction of size and energy consumption of electronic digital logic gates is the main driver behind CMOS technology scaling [76]. From this perspective, it is hard to conceive alternate technologies that can outperform electronic digital gates. However, there are applications where electronic processing of information is not possible or easy due to the difficulty in routing electrical signals or accessing electrical power supply, electromagnetic interference, or security concerns [57,58]. Data can be transferred to remote locations over optical fibers without much fear of electromagnetic interference. It would be useful to be able to process this data in the optical domain without requiring electronics circuitry and power supply [60-62,67]. Optical information processing may occur in analog or digital domains. There is recent emphasis on analog optical processors that can realize vector-vector, vector-matrix, or matrixmatrix multiplication at high speeds and low energy costs [77,78]. Digital optical processors naturally require digital logic gates. There have been several past attempts to realize optical digital logic gates [79-83]. There are two primary approaches to implementing optical logic gates, namely, all-optical approach and optical-directed logic approach. In all-optical digital logic gates, the operands and the logic operation are in the optical domain. Past implementations of all optical logic primarily depend on coherent addition/subtraction of 54 optical fields using for instance multimode interferometer (MMI) or topology optimized inverse designed structures [84,85]. An interferometer with a 180º phase shifter in one arm functions as an exclusive or (XOR) gate. Assume the two inputs are in-phase coherent optical signals that may have either zero or power levels corresponding to “0” and “1” logic levels. The output power level will be zero when both inputs have the same power (corresponding to “00” or “11” logic levels) and will be /2 when only one input has power (corresponding to “01” and “10” logic levels). In other words, the output levels of zero and /2 correspond to “0” and “1” logic levels. The main drawback of these approaches is that the gate function depends on the relative phases of the input optical signals. On the other hand, the phase of the gate output depends on the inputs. For instance, it the aforementioned XOR gate, the output phases of the two cases corresponding to “01” and “10” logic levels will have 180º phase difference. In other words, the “01” and “10” outputs are not truly the same which will be problematic when gates are cascaded. The other shortcoming of this approach is that the output high logic level (/2 in the past example) is always lower than the input high logic level (). This too causes problems when gates are cascaded. Electronic digital logic gates rely on the nonlinear input-output transfer function. Optical nonlinearity, such as two-photon absorption, may be used to create digital logic gates [86,87]. These approaches typically require relatively high optical power levels. The optical directed logic on the other hand operates with electrical operands and optical logic operation. This is mainly constructed using network of micro-ring/desk or Mach-Zehnder interferometers (MZI) that act as switch and controlled by the electrical operands [88-90]. In a hybrid approach, the electrical operands of the directed-logic core are generated from optical signals [91]. In this chapter, we demonstrate optical-input optical-output logic gates that leverage an internal optical-electrical conversion [92]. Specifically, we demonstrate universal logic gates NOR and 55 NAND, from which any digital logic circuit can be demonstrated, using a commercial foundry silicon photonics process. 4.1 All-optical Switch Implementation To implement logic operation in any domain, we need to obtain a nonlinear sigmoid-type inputoutput transfer function. In the electrical domain, CMOS transistors are used to implement an electrical switch that achieves this required nonlinear behavior to achieve the different logic operations. Our goal is to implement an analogous device in the optical domain that can provide a nonlinear response without using any nonlinear material. Figure 4.1 shows the NOT gate (inverter) transfer function in the electrical domain and the equivalent conceptual gate in the optical domain. Vi NOT Vop=Vip NOT Pi Pop=Pip Vip Vop V0 V1 Pip Pop P0 P1 Electrical Optical (a) (b) Figure 4. 1 NOT logic gate block diagram and transfer function: (a) Electrical implementation, (b) optical implementation. The proposed optical-input optical-output switch consists of microring modulator and opticalto-voltage converter (photodiode), as shown in Fig. 4.2(a). The all-optical switch relies on the optical-electrical-optical conversion process. The photodiode converts the input optical power to an output voltage that is used to switch the microring (that acts as an electro-optical switch). In other words, the input power shifts the resonant wavelength of the microring modulator and changes the optical transmission across the microring modulator (Fig. 4.2(b)). In case the operating 56 wavelength of supply power to the ring modulator Psup is matched to the unmodulated resonant wavelength of the ring, then the output power Pop value is low when Pip is low and high when Pip is high. In this case, a non-inverting nonlinear transfer function can be obtained, as shown in Fig. 4.2(c). On the other hand, if the operating wavelength matches the maximum modulated wavelength of the microring, then the inverting nonlinear transfer function can be achieved. This all-optical switch is the core device of the proposed logic gates. Pi p P n Psup Pop Vmod Pop lc2 lc1 Pip Pop Psup l Pi p(aVmod) ... lc1 lc2 (a) (b) (c) Figure 4. 2 Microring modulator based all-optical switch: (a) schematic diagram, (b) microring transmission as function of the input power, (c) the switch nonlinear transfer function for inverting and non-inverting cases. 4.2 Zero-bias Low Speed Logic Gate In this section we propose a Mbps range all-optical logic gate that leverage an internal opticalelectrical conversion without using any electrical supply voltage or control signal. This gate can be used to implement logic circuits for different applications like: optical packet switching, optical system calibration, lidar. 57 4.2.1 Concept and Building Blocks The proposed all-optical universal logic gate shown in Fig. 4.3 has two optical inputs (operands), one optical output, and one continuous wave (CW) optical source acting as the “supply” that is analogous to the voltage supply of an electronic digital logic gate. The optical inputs can have power levels of 0 and PH corresponding to “0” and “1” logic levels. The output logic level depends on the combination of the two input signal levels and the “supply” level. The optical power of the combined input signals, once converted to an electrical voltage through a photovoltaic (zerobiased) photodetector, determines the resonant wavelength of a microring modulator that is coupled to the “supply” line. This resonance shift will then determine whether the “supply” signal is coupled to the output or not. A major feature of this optical gate is that it does not require any electronic supply voltage source. A B Psup Pout 1 (CW) 2x1 q Combiner P n Phase Shifter Optical-Voltage Converter Ring Modulator Pm Vm PA PB Y Optical Logic Gate Figure 4. 3 Conceptual diagram of the all-optical zero-biased logic gate with optical input combining. In case of coherent in-phase optical logic combining (Fig. 4.4(a)), let us assume the unmodulated resonant wavelength of the microring modulator (λum) is equal to the wavelength of the “supply” line (λsup). In this case, in the absence of any input signal (both at zero power or “0” logic level), the “supply” does not couple to the output. In other words, the output power level will 58 be zero or “0” logic level. Once either or both input signals are present (logic “1”), the photovoltaic photodiode will generate a sufficiently high voltage to shift the resonant wavelength of the microring modulator so that the “supply” line couples to the output. In other words, the output power level will be at the “1” logic level. This will emulate an OR logic function (Fig. 4.5(a)). Alternatively, let us assume the unmodulated resonant wavelength of the microring modulator is detuned, but close enough, from the wavelength of the “supply” line. In this case, in the absence of any input signal (both at zero power or “0” logic level), the “supply” couples to the output resulting in “1” logic level. Once either or both input signals are present (logic “1”), the voltage generated by the photovoltaic photodiode will shift the resonant wavelength of the microring modulator to be equal or very close to the wavelength of the “supply” line. Therefore, the “supply” signal does not couple to the output resulting in zero output power corresponding to “0” logic level. This will emulate a NOR logic function (Fig. 4.5(b)). The same gate with only one applied input (single operand) will act as a NOT logic function. Naturally, proper gate operation depends on the appropriate resonant shift of the microring modulator as a function of input signal power levels. In fact, the OR and NOR gates explained above require the resonant shifts corresponding to the presence of optical power at one or both inputs to be nearly the same. Fortunately, the photovoltaic photodiode offers a nonlinear response between its input optical power level and its output generated voltage. On the other hand, the resonant wavelength shift of the microring modulator is almost a linear function of the modulating voltage. Therefore, the transfer function between the optical power of the combined input signals and the resonant wavelength of the microring modulator is nonlinear (Fig. 4.4(b)). 59 (a) A B Psup Pout (CW) P n Pm Vm PA PB Y lRM (b) lRM Pm PH l00 0.5PH 0 2PH l01/10 l11 (uncorrelated) (correlated) (Vm) Figure 4. 4 Conceptual diagram of the all-optical zero-biased logic gate with coherent in-phase or uncorrelated optical input combining. (a) schematic diagram of the logic gate showing the main building blocks with the optical inputs combine in the optical domain. (b) Resonant wavelength shift of the micro-ring resonator as a function of combined power level input to the photovoltaic photodiode. Pout Psup (a) Psup PH PH / 2PH PH l lsup l11 Psup Pout Psup 0 / PH 0.5PH PH / 0 l01/10 Psup 0 0 0 l00 l00 l01/10 l11 Pout Pout Psup Pout Psup (b) Psup PH PH / 2PH PH l lsup l11 Psup 0 / PH 0.5PH PH / 0 l01/10 Psup 0 0 0 l00 l00 l01/10 l11 Pout Psup Pout Pout OR NOR Figure 4. 5 Logic operation of optical gate with coherent in-phase or uncorrelated optical input combining (a) Operational principle of the OR gate for different input combinations. (b) Operational principle of the NOR gate for different input combinations. The optical inputs (operands) may be combined in the optical or electrical domains. In the case of optical combining, coherent and incoherent cases may be considered. In the coherent case, both inputs are generated from the same optical source. The output power level of a coherent combiner depends on the relative phases of the two inputs. The output power will be zero when both inputs 60 have zero power, /2 when only one input is nonzero at power level, and a value that can be anywhere between zero and 2 when both inputs are nonzero at power levels with a relative phase shift. The combined power is equal to zero (2) for 180º (0º) phase shift between the two inputs. A phase modulator prior to the combiner is hence necessary in the case of coherent input sources to ensure that the two coherent inputs are added in phase for the proper operation of the OR and NOR gates. If the two inputs are derived from independent sources, the output power of the incoherent combiner will be 0 when both inputs have zero power, /2 when only one input is nonzero at power level, and when both inputs are nonzero at power level. Figure 4.6 summarize the out power of the combiner for the different cases. As explained above, in the case of optical power combining, the resonant wavelength shift of the microring modulator is a nonlinear function of the combined power levels. Specifically, the resonant shifts caused by output power levels /2, , and 2 are not far (Fig. 4.4(b)). PA PB Pm 0.5PH 01/10 00 11 0 PH 0.5PH 01/10 00 11 0 2PH 1 0 PH 0 PH 0 1 0 2x1 Combiner 0.5PH 01/10 0 00/11 Correlated Uncorrelated q q=0 q=p Two Operands PA Pm PH 0 1 0 2x1 q Combiner 0.5PH 0 1 0 One Operand Figure 4. 6 The combiner output power for one and two input optical data cases. In case of the two operands, the output power is shown for three different cases: the 2 input lasers carriers are uncorrelated, correlated and in phase, and lastly correlated and out of phase. 61 The goal of this work is to implement a universal optical logic gate that can be used for one and two-operands logic operations. Hence, even for the one operand operations (Buffer and NOT), the input optical power (PA) passes by the combiner, as shown in Fig. 4.7(a). This results in the drawback of losing half of the signal power (Fig. 4.7(b)) unnecessarily before the input of the optical-voltage converter (Pm). The operation of Buffer and NOT gates are described in Fig. 4.8. (a) A Psup Pout (CW) P n Pm Vm PA Y lRM (b) lRM Pm l0 0.5PH 0 l1 (Vm) Figure 4. 7 Conceptual diagram of the all-optical zero-biased logic gate with one operand (in case of optical combining). (a) schematic diagram of the logic gate showing the main building blocks. (b) Resonant wavelength shift of the micro-ring resonator as a function of power level input to the photovoltaic photodiode. (a) l lsup Psup Pout Psup PH 0.5PH l1 Psup 0 0 l0 l0 l1 Pout Pout Psup (b) Pout Psup l lsup Psup PH 0.5PH l1 Psup 0 0 l0 l1 Pout Psup Pout l0 Buffer NOT Figure 4. 8 Logic operation of optical gate with one operand (in case of optical combining). (a) Operational principle of the Buffer gate for different input combinations. (b) Operational principle of the NOT gate for different input combinations. 62 In the case of optical power combining with coherent inputs, the necessary phase modulator prior to power combiner may be adjusted judiciously to create XOR and XNOR gate functions. Specifically, imagine the phase modulator creates 180º phase shift between the two signals at the combiner input (Fig. 4.9(a)). This means that the coherent combiner output when both input power levels are equal (either at zero or ) is equal to zero. Therefore, the resonant wavelength of the microring modulator (Fig. 4.9(b)) and the logic gate output will be the same when both inputs are either zero or (logic levels 00 or 11). In the first case, assume the unmodulated resonant wavelength of the microring modulator is equal to the wavelength of the “supply” line. The “supply” signal will not couple to the output when both input signals have the same power level (output logic 0). The “supply” signal will couple to the output when only one of the inputs has nonzero power, due to the resonant shift of the microring modulator, resulting in output logic 1. This will emulate the XOR gate function (Fig. 4.10(a)). In a second case, when the unmodulated resonant wavelength of the microring modulator is unequal, but close, to the wavelength of the “supply” line, the “supply” signal will couple to the output when both input power levels are equal resulting in output logic level 1. When only one input has power, the resonant wavelength of the microring modulator will shift in a way that the “supply” does not couple to the output resulting in logic level 0. This will emulate the XNOR gate function (Fig. 4.10(b)). As an alternative approach to optical power combining, the two optical input signals can be converted to electric voltages through photovoltaic photodiodes that are connected in series (Fig. 4.11(a)). The overall voltage across the series-connected photodiodes is hence the addition of individual voltages across each photodiode. Signal combining in electrical domain is not sensitive to the wavelengths or coherency of the two optical inputs. Unlike the case of optical power combining, the resonant wavelength shift of the microring modulator is a linear function of the 63 input power levels (Fig. 4.11(b)). This is because irrespective of the nonlinear characteristic of each photovoltaic photodiode converting to , the combined voltage that is applied to the microring modulator is always a linear function of the total input power. The modulating voltage will be 0, , and 2 when both input power levels are zero (00 logic input), only input power level is (01 and 10 input logics), and both input power levels are (11 input logic), respectively. This feature can be used to realize other gate functions. For instance, consider the case where the unmodulated resonant wavelength of the microring modulator is far enough from the wavelength of the “supply” source in a way that modulating voltage 2 is needed to shift the resonant wavelength of the microring modulator to match the wavelength of the supply source. Modulating voltage does not provide sufficient wavelength shift to match the “supply” wavelength. This gate will then emulate NAND function (Fig. 4.12(c)). OR and XNOR functions can be also obtained as shown in Fig. 4.12(a) and Fig. 4.12(b), respectively. (a) A B Psup Pout (CW) P n Pm Vm PA PB Y lRM p (b) lRM Pm l00,l110 0.5PH l01/10 (Vm) Figure 4. 9 Conceptual diagram of the all-optical zero-biased logic gate with coherent out-of-phase input combining. (a) schematic diagram of the logic gate showing the main building blocks with the optical inputs combine coherently in the optical domain with 180º phase shift. (b) Resonant wavelength shift of the micro-ring resonator as a function of combined power level input to the photovoltaic photodiode. 64 (a) Psup PH PH l lsup l11 Psup Pout Psup 0 / PH 0.5PH PH / 0 l01/10 Psup 0 0 0 l00 l00,l11 l01/10 Pout Pout Psup 0 Pout (b) Pout Psup Psup PH PH l lsup l11 Psup 0 / PH 0.5PH PH / 0 l01/10 Psup 0 0 0 l00 l01/10 Pout Psup Pout 0 l00,l11 Pout Psup XOR XNOR Figure 4. 10 Logic operation of optical gate with with coherent out-of-phase input combining. (a) Operational principle of the XOR gate for different input combinations. (b) Operational principle of the XNOR gate for different input combinations. (b) lRM (PA,PB) l00 (0,0) l01/10 l11 (Vm) (0,PH) / (PH,0) (PH,PH) (a) A B Psup Pout (CW) P n PA PB Y lRM Vm VPD,A VPD,B Figure 4. 11 Conceptual diagram of the all-optical zero-biased logic gate with electrical input combining. (a) schematic diagram of the logic gate showing the main building blocks with the optical inputs combine in the electrical domain. (b) Resonant wavelength shift of the micro-ring resonator as a function of power level of each input operand. (a) (b) PH PH l lsup 0 / PH PH / 0 Psup 0 0 l00 l00 l01/10 l11 Pout Psup Psup l01/10 Psup Pout Psup l11 0 VPD 2VPD Pout Psup Pout (c) PH PH l lsup 0 / PH PH / 0 Psup 0 0 l00 l00 l01/10 l11 Pout Psup Psup l01/10 Pout Psup Psup l11 0 VPD 2VPD Pout Psup Pout l00 l01/10 l11 PH PH l lsup 0 / PH PH / 0 Psup 0 0 l00 Pout Pout Psup Psup Pout Psup l01/10 Psup Pout Psup l11 0 VPD 2VPD OR XNOR NAND Figure 4. 12 Logic operation of optical gate with electrical input combining. (a) Operational principle of the OR gate for different input combinations. (b) Operational principle of the XNOR gate for different input combinations. (c) Operational principle of the NAND gate for different input combinations. 65 The electrical input combining version operates for one operand case as well (Fig. 4.13). The main advantage here compared to the optical input combining is that we don’t lose half of the signal as the case of the optical combiner. The Buffer and NOT gates in the electrical combining implementation are described in Fig. 4.14. (b) lRM (PA) l0 (0) l1 (Vm) (PH) (a) A Psup Pout (CW) P n PA Y lRM Vm VPD,A VPD,B Figure 4. 13 Conceptual diagram of the all-optical zero-biased logic gate with one operand (in case of electrical combining). (a) schematic diagram of the logic gate showing the main building blocks. (b) Resonant wavelength shift of the micro-ring resonator as a function of power level input to the photovoltaic photodiode. (a) (b) PH Psup 0 l0 Psup l1 0 VPD Pout Psup Pout PH Psup 0 l0 Pout Psup Pout Psup l1 0 VPD l lsup l0 l1 Pout Psup Pout Psup l lsup l0 l1 Buffer NOT Figure 4. 14 Logic operation of optical gate with one operand (in case of optical combining). (a) Operational principle of the Buffer gate for different input combinations. (b) Operational principle of the NOT gate for different input combinations. 66 There are two mechanisms to obtain the different logic operations. As described before, the ring modulator resonance wavelength can be detuned (using a heater) to match the supply wavelength for different operations. Alternatively, the supply wavelength can be tuned to match the ring modulator wavelength corresponding to the different logic operations, as shown in Fig. 4.15 and Fig. 4.16, for the optical and electrical input combining implementations, respectively. (a) Pout Psup l 00 01/10 11 (dB) lOR lNOR Pout Psup l 0 1 (dB) lBuff lNOT Pout Psup l 00 01/10 11 (dB) lOR lNOR Pout Psup l 00 11 01/10 (dB) lXOR lXNOR (c) (b) (d) Figure 4. 15 Ring modulator resonance shift in case of optical input combining for different input cases (a) one operand, (b) two uncorrelated operands, (c) two correlated (in-phase) operands, (d) two correlated (out-of-phase) operands. (a)Pout Psup l 0 1 (dB) lBuff lNOT Pout Psup l 00 01/10 11 (dB) lOR lXNOR lNAND (b) Figure 4. 16 Ring modulator resonance shift in case of electrical input combining for different input cases (a) one operand, (b) two operands. 67 It is worth mentioning that the proposed photonics circuit can also function (in the case of the Buffer gate) as an optical repeater or a wavelength shifter. As an optical repeater, the output optical power (Pout) can be amplified by providing high supply power (Psup). Also, the output wavelength depends on the supply carrier wavelength, not the input carrier wavelength. Hence, the output (Pout) wavelength can be converted by tuning the supply (Psup) wavelength. 4.2.2 Implementation and Fabrication The zero-bias universal optical logic gates are implemented in the Tower Semiconductor PH18MA foundry silicon photonics process. The 220 nm thick silicon layer is on top of a 3 μm buried silicon oxide layer. The primary waveguide structure in most of the devices is a single-mode strip silicon waveguide with 500 nm width. Grating couplers are used to couple the light into and out of the chip. The schematic diagram of the logic gate is shown in Fig. 4.17(a). The 2×1 combiner is realized using multi-mode interferometer (MMI) structure. The MMI has compact dimension of 2 µm × 3.5 µm and measured excess loss of 0.15 dB. In order to set the phase relation of the input logic in case of the two operands (PA and PB) with correlated carriers, geometrically-optimized (low loss), heat-reuse (efficient) thermo-optic phase shifters are used (design B in [39]). One phase shifter is needed to set the phase difference between the two inputs carriers and the other one is just a dummy to match the loss and delay between the two paths. The measured loss of the phase shifter is 1 dB and the is 2.5 mW. A 90:10 directional coupler is used to tap -10 dB of the combined input logic power for monitoring purpose. The photodiode in photovoltaic mode operates in open circuit configuration (or capacitive load) where maximum power efficiency is achieved. Resistive loads less than the internal resistance of the photodiode reduce the generated output voltage significantly. This internal 68 resistance limits the intrinsic speed of the photovoltaic photodiode to 10s of MHz depends on the technology and the device size. The photovoltaic photodiode is more suitable to drive charge depletion optical modulators and not charge injection or thermo-optic modulators as the latter two draw currents (resistive load). The main design challenge when using a photovoltaic photodiode is the limited output voltage range. The maximum voltage generated across one photovoltaic diode is limited by the photodiode open circuit voltage; this value is around 0.35 V for the germanium photodiode that is used in this technology. This issue can be solved by connecting the photodiodes in series. In this case, the voltages across the series-connected diodes are added and the maximum output voltage is extended. An MMI-based optical distribution network is used to deliver the input optical power to 16 series-connected photodiodes. The PH18MA Tower Semiconductor PDK photodiode is implemented in a germanium on silicon vertical P-I-N configuration, where a germanium layer is formed on top of the Si strip waveguide to absorb the light. The photodiode has a width of 8.6 μm and a length of 15 μm. To connect the 0.5 μm width MMI network waveguides to the 8.6 μm width photodiode waveguides, linear tapers are used. The measured responsivity of the photodiode is around 0.85 A/W. (a) MMI PD N=16 Psup PA PB Pout P n Va Vc n P Lmod 2 Ring Modulator MMI Pm Vm Grating Coupler Optical-Voltage Converter VC2 VC1 Phase shifter Pmonitor Directional Coupler (OVC) (PS) (RM) (GC) (b) RM 380 µm 380 µm OVC Psup PA PB Pout Pmonitor PS+MMI GC Figure 4. 17 Optical-input optical-output zero-biased logic gate with optical input combining. (a) Schematic diagram of proposed design showing the building blocks and the input-output ports. (b) Micrograph of the fabricated logic gate with ring modulator length of 250 µm showing the main building devices and the area size. 69 The microring modulator is implemented in longitudinal rate-race layout with charge depletion modulator on both sides (Fig. 4.17(a)). One of the main design goals of the modulator is to increase the modulation efficiency, i.e., the percentage of the modulator length with respect to the total round-trip length of the ring modulator. This ensures the maximum possible wavelength shift tuning for the same applied modulating voltage value. The microring resonator coupling length and the waveguide bends radius should then be minimized. Also, the total loss of the ring modulator should be minimized to achieve high quality factor (Q) and small full-width halfmaximum (FWHM) that lead to better switching extension ratio. For the same reason, the microring modulator is designed to work under critical coupling condition. The microring resonators have a narrow strip waveguide width of 0.4 μm (less optical field confinement, hence strong coupling) so that the targeted critical resonance coupling coefficient can be obtained with a smaller coupling length (20 μm in our design). Euler 90o waveguide bends with 5 μm radius are used to minimize the un-modulated length without introducing high loss to the ring; the simulated loss is 0.02 dB. The standard technology lateral P-I-N built into ridge waveguide charge depletion phase modulator was used to implement the modulated section of the ring resonator. The ridge waveguide used to implement the charge depletion modulator has a strip width of 0.45 μm, and total modulation length of . Ridge to strip waveguide tapers with length of 10 μm are used to connect the two modulator sections inside the ring resonator. Charge depletion modulator is suitable to be driven with the photovoltaic mode photodiodes as it does not drain any current. The loss of the phase modulator is 2.5 dB/mm and the modulation efficiency is 1.8 V.cm. High modulator efficiency is needed to induce more resonance shift. Three different version of the logic gate with three different of 250 μm, 500 μm, and 1000 μm were fabricated. The unmodulated length that includes the coupling region, the bends, and the ridge to strip tapers is 110 μm. This 70 makes the ring modulation efficiency equal to 70%, 82%, and 90% for the ring with the modulation lengths of 250 μm, 500 μm, and 1000 μm, respectively. A micrograph of the fabricated opticaloptical logic gate with ring modulator length of 250 μm is shown in Fig. 4.17(b). The active area of the optical logic gate is around 0.1 mm2 . Figure 4.18, shows the alternate way to implement the zero-biased logic gate, by cascading two sets of 8 stacked photodiode and add the logic inputs as voltages in the electrical domain. This circuit wasn’t fabricated, only the optical to voltage converter section was fabricated as a standalone test structure. Psup PA PB Pout P n Va Vc n P Lmod 2 Ring Modulator Vm Grating Coupler Optical-Voltage Converter N=8 Vm,A MMI PD N=8 Vm,B Figure 4. 18 Schematic diagram of an alternative design of the logic gate with electrical logic operands combining. 4.2.3 Measurement Results In this section, we experimentally demonstrate the operation of the optical logic gate. First, the measurement results of the optical to voltage converter and the static response of the optical-optical logic gate are shown. Then, the dynamic responses for different logic operations of the logic gate are shown. Lastly, the dynamic speed limit of the proposed logic gate is presented. The measurement setup relies on external intensity modulator to modulate the optical carrier with 71 electrical data, and polarization controllers to optimize the coupling efficiency to the chip through the grating couplers. The temperature mismatch between the two off-chip input paths creates a time-varying phase offset between the two input signals when generated from the same source (coherent case). Therefore, the reported experiments correspond to the incoherent input signals. In the static response characterization, we measure the performance of the optical-to-voltage converters and the microring modulator. To test the zero-bias optical power to voltage converter, a standalone test structure with the combiner and the optical power to voltage converter was used (refer to Fig. 4.17(a)). Figure 4.19(a) shows the measured output voltage versus the optical input CW power levels ( and ). This measurement was conducted for different input logic configurations: PAB=11 when both and are ON and are swept simultaneously, =01 when =0 and is ON and swept, =10 when =0 and is ON and swept, and =00 when both =0 and =0 ( is 0 in this case). In case of =01/10 the input power to the optical power to voltage converter is half or and it is equal to or when =11, as discussed in combiner operation in the concept section. As expected, the optical power to voltage transfer function is nonlinear, the output voltage starts to saturate as it reaches the diode open circuit voltages. At any given input optical power larger than 0.1 mW, the measured output voltage () for the case of input logic 10/01 and 11 are very close to each other, around 0.4 V difference. This makes the corresponding resonance wavelengths close to each other as discussed earlier. The optical voltage converter in the case of the electrical domain combining (refer to Fig. 4.18) is also tested using standalone test structure. The measured output voltage versus the optical input CW power levels ( and ) for the same measurement scenarios is shown in Fig. 4.19(b). As expected, the generated voltage in case of “11” logic input is as twice the case of “01/10”. 72 The logic gate wavelength transmission resonance wavelengths for two operand (A and B) and one operand (A) cases are shown in Fig. 6(a) and Fig. 6(b), respectively, where the logic high optical power is 0.1 mW and is 0 mW. For the two operands case, the separation (∆λr1) between the resonance wavelengths corresponding to input logic level “00” (λ00) and “01/10” (λ01/λ10) is much larger than the shift (∆λr2) between the resonance wavelengths corresponding to the input logic levels “01/10” (λ01/λ10) and “11” (λ11). As explained before, to realize the OR gate function, the unmodulated resonant wavelength of the microring modulator (“00” resonant wavelength) is set to be equal to the “supply” wavelength. To realize the NOR gate function, the modulated resonant wavelength of the microring modulator corresponding to “01/10” and “11” input logic levels is set to be equal to the “supply” wavelength. For one operand operation, the two-resonance wavelength corresponding to input logic levels “0” (λ0) and “1” (λ0) are clearly separated (∆λr1), Buffer and NOT operations can be obtained at these wavelengths, respectively. As the microring modulating voltage Vm increases the microring modulator quality factor drops as the carriers in the charge depletion modulator increases. Hence, the resonance curves in case of input logic of 01/10 and 11 have lower extension ratios than the case of input logic 00. (a) (b) Figure 4. 19 Optical power to voltage characterization. Measured open-circuit output voltage versus input static logic optical power ( or ) for different input logic configurations (00, 01,10, and 11) for two configurations: (a) optical combining and 16 stacked photodiodes, (b) electrical combining using 2 series sets of 8 stacked photodiodes. 73 l0=1550.389 l1=1550.434 lBuff lNOT (b) l0 0=1550.388 l1 1=1550.438 l0 1=1550.433 l1 0=1550.432 lOR lNOR (a) Figure 4. 20 Optical-optical logic gate static measurements. Measured wavelength transmission of the optical logic gate for different input logic cases (with high logic optical power =0.1mW) in case of: (a) two operands, (b) one operand. Based on the bandwidth results in the following section, we used 10 Mbps PRBS OOK data to test the dynamic performance of the all-optical logic gate. An arbitrary waveform generator was used to generate PRBS and external modulators to generate the optical data to the logic gate ( 74 and ). The power level of the two logic inputs ( and ) in the two-operand case are matched by observing the optical power levels of the monitor signal which is a small replica of signal after the optical combiner . When , the monitor signal should have three power levels: low power level for “00” input, mid power level for “01” and “10” inputs, and high power level for “11” input. The input, the monitor and the output data are detected using a digital storage oscilloscope. The ring modulator input carrier wavelength is matched to the resonance wavelength of the desired operation as mentioned in the static measurements section as shown Fig. 4.20(a) and Fig. 4.20(b). The dynamic measurement results for two operands case showing the logic operations of OR and NOR are shown in Fig. 4.21(a). The logic operations of Buffer and NOT for the one operand case are shown in Fig. 4.21(b). The OR operation has two “1” output levels as in this case the ring resonator is working at the input logic “00” null and it sees a slightly different transmission for the input logic “01/10” and “11” cases (shown in the static responses Fig. 4.20(a)), as the ring resonator have different resonance shift for these two cases. On the other hand, the NOR operation work at the intersection wavelength of the input logic resonances “01/10” and “11” for the “0” output, hence it has only one “0” level. NOR is a universal logic gate that can be used to implement anu logic function. The output detected voltage for the case of the NOT and the NOR operation is lower than the cases of Buffer and OR as the ring modulator has lower extension ratio at these wavelengths. There are two factors that limit the switching speed of the proposed architecture: (1) the microring modulator build up and decay times, (2) the electrical resistance and capacitance time constant at the microring modulator’s voltage modulating node [89,93,94]. The optical delay can be determined by the photon lifetime in the microring cavity which defined as ℎ /2. The smallest ring modulator (=250 μm) has the largest Q and hence the largest optical delay ℎ 75 = 18 ps. The electron RC time constant is ( + ), where and are the photovoltaic photodiodes equivalent internal resistance and capacitance, respectively, and is the ring modulator capacitance (Fig. 4.22). This value depends on the applied reverse voltage of the charge depletion modulator as is inversely proportional to the reverse voltage. In case of the photovoltaic mode operation of the photodiode, is in the range of 10s-100s of ns and it dominates the total delay of the system expressed as ℎ + . The -3dB bandwidth (−3) of the logic gate can be defined as −3 2 2 2/2, where is the average 10% - 90% rise ( ) and fall time () of the system ( 0 5( + )). The maximum operated data rate (DR) is directly proportional to the −3 and can be defined as 2 9−3 for the NRZ data. To measure the BW-3dB of the optical logic gate, a 2 MHz square-wave signal pulse train is applied as the input A while the gate operates in the Buffer mode, and and of the output data are observed. This test was conducted for all the ring designs (=250 μm, 500 μm, and 1000 μm). Different optical square-wave amplitude powers are used to capture the dependence of the on the applied modulating voltage (Fig. 4.23). As the switching power increases, the switching modulating voltage increases, and hence the reduces and the −3 increases, as shown in Fig. 4.24. In case of the buffer operation, is smaller than as the final voltage in case of the rising edge is larger than the case of the falling edge and hence the equivalent is smaller in the case of the rising edge. Also, it can be noticed the smallest microring design (=250 μm) has the higher −3 as it has the smallest ; the other part of the node capacitance doesn’t depend on . 76 (a) B out (A OR B) out (A NOR B) A lOR=1550.388 lNOR=1550.435 (b) lBuff=1550.389 lNOT=1550.434 A out (BUF A) out (NOT A) Figure 4. 21 Optical-optical logic gate dynamic measurements for 10 Mbps OOK input modulated signal. PRBS OOK signal is the input to the logic gate and (in Red), and the optical output of the logic gate (in Blue) showing the operation of OR and NOR in case of two operands and NOT and Buffer in case of one operand in (a) and (b), respectively. IPD RPD CPD CR M Photodiode Ring Modulator Figure 4. 22 Photodiode and ring modulator circuit model for speed measurements. 77 PA PA PA PA monitor out Figure 4. 23 Optical logic gate speed measurements. Measured transient response with input square wave 2 MHz logic input signal () for different optical carrier high level power of both the monitor signal (monitor the input power to the optical power to voltage converter) in green (top) and the logic gate output signal in blue (bottom) for the microring design with =250μm. tr tf Figure 4. 24 The measured rise time and fall time (10%-90%) of the logic gate output for different logic input power (top), and the corresponding -3dB bandwidth values (bottom) for different designs. 78 4.2.4 Logic Gate Cascadabilty An optical digital circuit will consist of several universal optical logic gates. Each optical gate will drive one or more subsequent optical logic gates. The output optical power level of each logic gate should be sufficient to drive the subsequent logic gates. The output power level of our universal optical logic gate depends on the optical power levels of the logic input operands ( and ) and the optical power level of the “supply bus”, , that feeds the ring modulator. Figure 4.25(a) shows the ring modulator transmission ⁄ versus the input logic power level () in the single-operand case for three different ring modulator designs having of 250 μm, 500 μm, and 1000 μm. We can compare the performance of the three designs of the microring modulator with Lmod of 250 μm, 500 μm, and 1000 μm in terms of their quality factor (Q) and resonant wavelength shift. When logic high optical power PH is 0.1 mW, the separation between the resonant wavelengths at 00 and 01/10 input logic are 44 pm, 50 pm, and 55 pm. The separation between the resonant wavelengths at 01/10 and 11 input logic equals 6 pm, 9 pm, and 11 pm for Lmod of 250 μm, 500 μm, and 1000 μm, respectively. The ratios between these resonance shift values match the ring modulation efficiency values (70%, 82%, and 90%, respectively). The smallest ring (Lmod=250 μm) has the lowest ring modulation efficiency and hence lowest resonance wavelength shifts. On the other hand, the measured Qs of the three designs are 22100, 17200, and 15500 for the ring with Lmod of 250 μm, 500 μm, and 1000 μm, respectively. Table 4.1 summarize the measured characteristics (Q, full-wave half-maximum (FWHM), insertion loss, free spectrul range (FSR)) of the three designs of the microring modulator. The smallest ring (Lmod=250 μm) has the lowest dominant loss (modulator loss) inside the ring; hence, it has the highest Q. To achieve better optical switching (higher extension ratio between output “0” and “1” power levels), we need both higher 79 Q (sharper resonance role-off) and more resonance shift. Here, we have a tradeoff between these two factors for the three designs of the ring. In order to determine which design has the largest logic output extension ratio, the ring modulator transmission (Pout/Psup) vs the input logic power level (PA) can be measured for the three designs of the ring modulator for the Buffer operation, as described earlier. In summary, the does not affect the results significantly, as the increase in resonance shift for modulators with larger is offset by the decrease of corresponding . Overall, the smallest ring modulator achieves a little more efficient switching. Table 4. 1 Microring Modulator Measured Characteristics Lmod (μm) Insertion Loss (dB) FWHM (nm) Q (nm/nm) FSR (nm) 250 0.5 0.07 22,100 1.66 500 0.9 0.09 17,200 1 1000 1.5 0.1 15,500 0.56 To ensure straightforward cascadability of such optical gates, the input and output logic levels should be the same. The total optical power consumed in one such optical logic gate is + + 2 + ⁄(⁄) 2 + ⁄(⁄), where we used the fact that in a proper logic gate, input and output logic levels should be the same (all equal to PA). Figure 4.25(b) shows the total required optical power, , versus logic high optical level, PA, using the measured ⁄ data shown in Fig. 4.25(a). The logic high optical power level that can switch the optical gate at the smallest overall optical power required by the gate is found to be =30 mW. The corresponding optimum ⁄ values (⁄) are 0.28, 0.26, and 0.21 and , values are 160 mW, 170 mW, and 200 mW for of 250 μm, 500 μm, and 1000 μm, respectively. 80 PH=0.03 mW PT,min 0.20 0.17 0.16 (b) 0.21 PH 0.26 0.28 Pout Psup opt ( ) (a) Figure 4. 25 Optical logic gate cascadability. (a) Measured optical logic gate transfer function (output transmission Pout/Psup versus the input logic power PA) for three different ring modulator geometries. (b) Total optical power needed for one optical logic gate versus the input logic power PA. In summary, the optical logic gate built using =250 μm will require a total optical power =160 mW to operate. The optical logic gate will require more power to drive multiple similar 81 optical logic gates. The total required power for an optical gate driving similar gates (fanout of as shown in Fig. 4.26(a)) is equal to 2 + ⁄(⁄). The minimum total energy consumption of such a gate will be given by , 2 + (⁄) ⁄ Figure 4.26(b) shows the , for different fanout value for the three values. In a complex digital logic circuit, the input optical power should be considered only in the input stages because the input power levels of the subsequent stages are provided by the supply powers of preceding stages. (a) PH Psup Pout PA PB FPH N=16 P n Va Vc n P Optical Logic Gate PH FPH/ Pout Psup opt ( ) Lmod 2 (b) Figure 4. 26 Optical logic gate cascadability with fanout. (a) Conceptual diagram of an optical logic gate driving F similar optical logic gates. (d) The minimum total power consumption of an optical logic gate versus different values of fanout (F). 82 4.3 Biased High Speed Logic Gate In this section we propose a Gbps range all-optical logic gate that leverage an internal opticalelectrical conversion that operates with electrical supply. This gate can be used to implement high speed logic circuits for different applications like: optical computing. 4.3.1 Concept and Building Blocks The proposed high-speed optical operands universal logic gate shown in Fig. 4.27 has the same structure as the gate proposed in the previous section. Two inputs (operands) in the optical domain, one optical output, and one supply CW optical source. The difference between this design and the previous one is that the optical-to-voltage conversion occurs using photoconductive (reversebiased) photodiodes. This allows the Gbps operation speed but at the cost of the necessity of an electrical supply. The optical operands are in OOK format with power levels of 0 and PH corresponding to “0” and “1” logic levels. The output logic level depends on the two inputs logic power (PA and PB) and Psup. The optical power of each input logic is first converted to electrical current using a photoconductive photodiode, and then the two currents are combined in the electrical domain and converted to a modulating voltage through a resistance. The value of this modulating voltage determines the resonant wavelength of a microring modulator that is coupled to the “supply” line. Whether or not the Psup signal is coupled to the output depends on the microring resonance shift. The main feature of this design is that signal combining in electrical domain is not sensitive to the wavelengths or coherency of the two optical inputs. 83 A B Psup Pout 1 (CW) P n Optical-Voltage Converter Ring Vm Modulator PA PB Y Optical Logic Gate VDD GND IA IB lRM R Figure 4. 27 Conceptual diagram of the optical operands high speed logic gate. The principle of operation is very similar to the electrical input combining implantation of the previous structure. The overall current passing across the resistance is the addition of individual currents generated from each photodiode. The resonant wavelength shift of the microring modulator is a linear function of the input power levels (Fig. 4.28). This is because the linear characteristic of each photovoltaic photodiode and also each photodiode is converting to , the combined current that converts to voltage that is applied to the microring modulator is always a linear function of the total input logic combination. The modulating voltage will be 0, , and 2 when both input power levels are zero (00 logic input), only input power level is (01 and 10 input logics), and both input power levels are (11 input logic), respectively. The three equally separated modulating voltages generate three separated resonant wavelengths of the microring modulator. This feature can be used to realize OR, XOR, and NAND functions as shown in Fig. 4.29. This design of the logic gate is universal and can operate for one operand case as well (Fig. 4.30). The Buffer and NOT gates principle of operations are described in Fig. 4.31. 84 lRM (PA,PB) l00 (0,0) l01/10 l11 (Vm) (0,PH) / (PH,0) (PH,PH) Figure 4. 28 Resonant wavelength shift of the micro-ring resonator of the high speed optical logic gate as a function of power level of each input operand. (a) (b) PH PH l lsup 0 / PH PH / 0 Psup 0 0 l00 l00 l01/10 l11 Pout Psup Psup l01/10 Psup Pout Psup l11 Pout Psup Pout (c) PH PH l lsup 0 / PH PH / 0 Psup 0 0 l00 l00 l01/10 l11 Pout Psup Psup l01/10 Pout Psup Psup l11 Pout Psup Pout l00 l01/10 l11 PH PH l lsup 0 / PH PH / 0 Psup 0 0 l00 Pout Pout Psup Psup Pout Psup l01/10 Psup Pout Psup l11 OR XNOR NAND 0 RIPD 2RIPD 0 RIPD 2RIPD 0 RIPD 2RIPD Figure 4. 29 Logic operation of high speed optical gate. (a) Operational principle of the OR gate for different input combinations. (b) Operational principle of the XNOR gate for different input combinations. (c) Operational principle of the NAND gate for different input combinations. lRM (PA) l0 (0) l1 (Vm) (PH) (a) (b) A Psup Pout 1 (CW) P n Optical-Voltage Converter Ring Vm Modulator PA Y Optical Logic Gate VDD GND IA IB lRM R Figure 4. 30 Conceptual diagram of the optical operands high speed logic gate with one operand (a) schematic diagram of the logic gate showing the main building blocks. (b) Resonant wavelength shift of the micro-ring resonator as a function of power level input to the photoconductive photodiode. 85 (a) (b) PH Psup 0 l0 Psup l1 Pout Psup Pout PH Psup 0 l0 Pout Psup Pout Psup l1 0 RIPD 0 RIPD l lsup l0 l1 Pout Psup Pout Psup l lsup l0 l1 Buffer NOT Figure 4. 31 Logic operation of the high speed optical gate with one operand. (a) Operational principle of the Buffer gate for different input combinations. (b) Operational principle of the NOT gate for different input combinations. As described in the previous section, instead of detuning the microring resonant wavelengths to match the supply wavelength, the supply wavelength can be tuned to match the different resonant wavelengths of the microring depending on the input logic combinations (Fig. 4.32). Also, the optical amplification and the wavelength conversion function can be obtained from this device in the same way as the zero-biased design. (b)Pout Psup l 0 1 (dB) lBuff lNOT Pout Psup l 00 01/10 11 (dB) lOR lXNOR lNAND (a) Figure 4. 32 Ring modulator resonance shift of the high-speed logic gate for different input cases (a) two operands, (b) onw operands. 4.3.2 Implementation and Fabrication The biased universal optical-input optical-output logic gate is implemented in the Tower Semiconductor PH18MA foundry silicon photonics process. The primary waveguide structure in most of the devices is a single-mode strip silicon waveguide with 500 nm width and the silicon layer thickness is 220nm with half etch capability for the ridge waveguide implementation. The 86 schematic diagram of the logic gate is shown in Fig. 4.33. By using Add-drop micro-ring we obtain the complementary of Pout from the drop port. P n Va Vc n P VD D PD R GND Vm Lmod 2 Ring Modulator (RM) Optical-Voltage Converter (OVC) Grating Coupler (GC) Psup PA PB Pout Figure 4. 33 Schematic diagram of the proposed high speed optical logic gate. The same topologies used to implement the photodiode and the microring modulator in the zero-biased logic gate (section 4.2.2) are employed here in this design. The only difference is that the layout is designed for high-speed operation by electromagnetically simulating all the electrical nodes and reducing the parasitic capacitance. The resistance (R) that converts the photodiode current to modulating voltage is implemented using the PDK TiN metal resistance. The square resistance of this type of resistance is 12 Ω. A total of twelve different versions of the logic gate designs are fabricated using the combination of four different microring modulator lengths (Lmod) (75 μm, 150 μm, 250 μm, 500 μm) and three different R values (500 Ω, 100 Ω, 50 Ω). 4.3.3 Simulation Results The fabricated logic gates had not yet been received when this thesis was written. Hence, we could not obtain the measurement characterization of this version of the optical logic gate. This section includes the main simulation results of the high-speed logic gate. 87 The circuit model of the high-speed logic gate is shown in Fig. 4.34. As described earlier, the modulating voltage Vm has a linear relation with the applied voltage to the photodiode operating in photoconductive mode. It can be expressed as Vm=RIPD=RPARres, where Rres is the responsivity of the photodiode (measured value of 0.85 A/W), and R is the current to voltage converter. The DC measurement of the modulating voltage Vm versus the photodiode current IPD (that represents the input logic power PA) is shown in Fig. 4.35 for R=100 Ω. The slope of this linear relation is R. RPD CPD IPD Photodiode A R CR M Ring Modulator VDD GND CPD RPD IPD Photodiode B Figure 4. 34 Circuit model of the high-speed optical logic gate Figure 4. 35 The modulating voltage Vm versus the photodiode current representing the input logic power. 88 The speed limitation in this circuit is similar to the zero-biased logic gate; the photon lifetime in the cavity (ℎ /2) is much less than the RC time constant ( (//0 5)(2 + )) of the circuit, ), where and are the photovoltaic photodiode internal resistance and capacitance, is the ring modulator capacitance (Fig. 4. 34). As R is much less than RPD, we can rewrite the RC time constant as (2 + ). The -3dB bandwidth (−3) of the logic gate can be defined as −3 (+ℎ) 2 ≈ 2 2 2/2, where is the average 10% - 90% rise ( ) and fall time () of the system ( 0 5( + )). The maximum operated data rate (DR) is directly proportional to the −3 and can be defined as 2 9−3 for the NRZ data. Figure 4.36 shows the AC simulation (using the PDK models and the EM simulated layout) of the circuit model with R=100 Ω and Lmod=150 µm. The simulated bandwidth is 6.5 GHz (doesn’t include the photon lifetime (ℎ) effect). Transient simulation of the logic gate operation (NOT) is also reported for 5 Gbps and 10 Gbps PRBS data as shown in Fig. 4.37, in this simulation the PRBS data is modeled by transit current source. Figure 4. 36 The high-speed logic gate simulated AC response. 89 Figure 4. 37 OOK PRBS transit simulation of the high-speed logic gate. There is a Power-Speed trade of in this implementation of the high-speed logic gate. As R increases the speed (−3) decreases and the required logic power (PA) to generate a certain Vm reduces. Hence, the power consumption and the speed are both inversely proportional R. Table 4.2 shows the simulated bandwidth of the logic gate for all values of R for Lmod=150 µm. In the used PDK the CPD is more dominate than Cmod, that is why these values doesn’t change much for the different Lmod designs. Table 4. 2 Simulated bandwidth of the high-speed logic gate for different R values. R (Ω) −3 (GHz) 50 13 100 6.5 500 1.3 90 We can measure the efficiency of the logic gate using the following expression: EE=PT/DR(energy per bit). As described in the zero-biased logic gate, the total optical power consumed in one such optical logic gate is + + 2 + ⁄(⁄) 2 + ⁄(⁄), where we used the fact that in a proper logic gate, input and output logic levels should be the same (all equal to PA). We can rewrite the energy efficiency as, (2 + ⁄(⁄))/(2 9−3). Energy efficiency isn’t a function of R as it affects bandwidth and PA in the same relation as described before; hence, we considered only the effect of Lmod. First, we find the optimum ring transfer function (⁄) to get the minimum energy efficiency ( (2 + (⁄) ⁄ )/(2 9−3)) by changing PA at Lmod=150 µm. The simulated (⁄) is equal to -5 dB, as shown in Fig. 4.38. This can be repeated for different Lmod, as shown in Fig. 4.39. The simulated energy per bit is around 10 pJ/bit. Figure 4. 38 High-speed logic gate energy per bit versus the microring modulator transmission. 91 Figure 4. 39 High-speed logic gate energy per bit versus the microring modulator length. 4.4 Logic Circuits Examples The proposed optical logic gates can be used to implement different logic circuits that perform complex digital functions. This section shows two examples of the implementation of optical logic circuits: full adder and pattern detector. Both examples are implemented using the biased highspeed logic gate and sent for fabrication using Tower Semiconductor (PH18MA). The fabricated logic circuits had not yet been received when this thesis was written; hence, we only show the simulation results. 4.4.1 Full Adder Full adders are a key building block in any processing unit. For instance, it can be used to obtain the average weights in the distributed processing of large-scale AI/ML models. The full adder can be implemented using NOR-only gates (Fig. 4.40(a)) or the regular implementation that consists 92 of XOR, AND, and OR gates (Fig. 4.40(b)). The NOR-only implementation has the drawback of a large area, and the logic signals propagate through a high number of gates; hence, we considered the regular implementation. A modified version of the regular implementation was used in order to get rid of the AND gate and use the NAND gate instead. We can obtain NAND operation using a single gate instead of the AND operation, which requires two gates (NAND and NOT), as described in the optical logic gates implementation sections. With the proposed implementation the full adder is implemented using two gates only (XOR and NAND). The optical implementation of the full adder using the proposed high-speed optical logic gates is shown in Fig. 4.41. The XOR gate is implemented using XNOR gate followed by NOT gate, it can be implemented using one gate if we used add-drop microring modulator to implement the gate. NOR NOR NOR NOR NOR NOR NOR NOR A B Ci S NOR Co A B Ci S Co XOR XOR NAND NAND NAND A B Ci S Co XOR XOR AND AND OR Half Adder Half Adder (a) (b) Figure 4. 40 Full adder gate-level implementation: (a) NOR-only, (b) XOR and NAND. 93 A B Ci S Co CW CW CW CW Cross CW A B NAND3 P n Va Vc n P VR P DR GND VH Y CW A B NAND2 P n Va Vc n P VR P D R GND VH Y CW A B NAND1 P n Va Vc n P VR P D R GND VH Y CW CW Y XNOR2 P n Va Vc n P VR P D R GND VH A B CW Y XNOR1 P n Va Vc n P VR P D R GND VH A B CW Y NOT1 P n Va Vc n P VR P D R GND VH A CW Figure 4. 41 Full adder implementation using the high-speed optical logic gate. In order to add N-bit data A and B, given that the optical data is transferred serially in the optical link, we need a de-serializer to obtain the data in parallel form, and then we can use N full adder. After performing the addition in the parallel form, the data can be serialized again using a serializer (Fig. 4.42). An alternate way, which is more efficient in terms of area and power, is to reuse a single full adder by feedback the 1-bit delayed carry-out data as input to the carry-in port (Fig. 4.43). The optical logic gate implementation is shown in Fig. 4.44. Optical switches at the carry-in and the carry-out ports are used in order to connect or disconnect the carry feedback; thus, this implementation can also be used as a 1-bit full adder (as Fig. 4.41). Behavioral model simulation of the serial full adder is shown in Fig. 4.45. Output DeSerializer DeSerializer Input Serializer A an a2 a1 a0 B bn b2 b1 b0 a0 an b0 bn s0 s1 sn cn+1 A+B xn x2 x1 x0 A B FA B A S Ci Co FA B A S Ci Co FA B A S Ci Co a1 b1 A+B Figure 4. 42 N-bit data parallel addition 94 an a2 a1 a0 bn b2 b1 b0 + sn s2 s1 s0 cn c2 c1 c0 0 0 0 cn FA an a2 a1 a0 B bn b2 b1 b0 A sn s2 s1 s0 S cn c2 c1 c0 cn c2 c1 c0 Ci Co t = Tb cn 0 0 0 Figure 4. 43 N-bit data serial addition A B Ci S Co CW CW CW CW Cross CW A B NAND3 P n Va Vc n P VR P DR GND VH Y CW A B NAND2 P n Va Vc n P VR P D R GND VH Y CW A B NAND1 P n Va Vc n P VR P D R GND VH Y CW CW Y XNOR2 P n Va Vc n P VR P D R GND VH A B CW Y XNOR1 P n Va Vc n P VR P D R GND VH A B CW Y NOT1 P n Va Vc n P VR P D R GND VH A CW VC Optical Switch VC Optical Switch t =0.2ns Figure 4. 44 Serial Full adder implementation using the high-speed optical logic gate. Figure 4. 45 Serial full adder behavioral simulation 95 4.4.2 Pattern Detector Pattern detection is an essential function in optical packet switching; it is needed to recognize the packet’s header and route the packet accordingly. The optical XNOR or the XOR gates can be used to implement a pattern detector. The output of the XOR gate is 0 (minimum output power) when both logic inputs are the same, and vice versa for the XNOR gate; the output power is maximum “1” when the logic inputs are identical. Figure 4.46 shows the implementation of the optical pattern detector. Every window of N-bit of the input data is de-serialized using a set of scaled delay line, then compared with the targeted pattern using N parallel XNOR. The target pattern is generated using CW laser, splitters, and N parallel optical switches, and it can be changed by controlling the transmission of the optical switches. The output of the XNOR gates is then combined using a MMI network. As we combine the power coherently, the phase of the XNOR outputs needs to be calibrated. The ratio of the output power of the detector (Pdet) over the XNOR output (PH) is simulated versus the number of bits similarity (X) with the targeted pattern for different N-bit values is shown in Fig. 4.47. xx xn x2 x1 x0 xx Input Data t = Tb nt (n-1)t xn xn-1 x1 x0 MMI Network Delay Lines Deserializer Combiner Pdet Output A B XNOR Y Phase shifter VCn VCn-1 VC1 VC0 Splitter Optical Switch (Splitter) zn zn-1 z1 z0 Input CW IR laser A B XNOR Y A B XNOR Y A B XNOR Y Vpn Vpn-1 Vp1 Vp0 Figure 4. 46 Optical pattern detector implementation 96 Figure 4. 47 Optical pattern detector output power as function of x bit similarity between the input data and the target pattern. 97 Chapter 5 Conclusion and Future Work This thesis experimentally demonstrated integrated photonics circuits and systems for analog and digital optical signal processing. The proposed circuits and systems are implemented on chip in a compact form using the photonics silicon on insulator (SOI) technology. They were fabricated using Tower Semiconductor commercial foundry process (PH18MA). Different state-of-the-art passive and active (electro-optic) photonic devices were designed to implement three examples of optical signal processing systems. Low loss tunable true time delay line, which is the primary enabler for analog signal processing, was proposed in chapter three. Universal all-optical logic gate, which is the key building block of any digital signal processing unit, was proposed in chapter five. And remotely optically biased and controlled signal processing concept, which can be used for both analog and digital signal processors, is demonstrated in chapter four. In the following paragraphs we summarize the work of each chapter and the possible direction for future research. To begin with, we demonstrate a low loss, area efficient, optical delay line using wide straight waveguides and low-loss parabolic tapers to convert to single mode waveguides where geometrically-optimized bends are used (two tapers and bend loss = 0.048 dB). The measured loss is 0.25 dB/ns (3.3 dB/m) of straight waveguide delay and total loss of 1.16 dB including the bends losses. This low loss delay line is used in a 8-bit binary switched delay line binary scheme to obtain a variable delay line. The design has a tunable range of 6.4 ns with 0.025 ns resolution, and 98 maximum loss of 16.3 dB for the largest delay of which around 9 dB is due to the nine 2x2 MZI optical switches. This loss can be further reduced by optimizing the design of 2x2 MZI optical switches. In the future, a continuously tuned thermos-optic delay line can be used to fine tune the delay within the switched step resolution (25 ps). Using the 8-bit switched low-loss optical delayline, a radiofrequency self-interference cancellation across an instantaneously ultra-wide bandwidth is experimentally demonstrated. Cancellation of 14 dB is achieved for 8 GHz UWB signal. Also, a high-power single side band modulator was introduced as a linear optical modulator for wideband applications. Measured average 16 dB carrier rejection and 20 dB sideband rejection for 1GHz modulation around 1550nm. As a future research direction, the proposed switched optical delay line can be used in other applications like microwave processing (like implementing FIR filters). Then, the remotely controlled and biased optical signal processing concept was introduced. we have demonstrated an integrated optically controlled amplitude modulator and two-tap sequence detector that utilizes a WDM scheme to separate the data and control channels. Wideband coupled ring resonator filters are used to separate the control and data channels (BW-3dB = 2.7 nm & FSR = 23 nm). The optical signals from control channels are converted to sufficiently large electrical DC voltages (4 V DC voltage from 2.25 mW optical power) using a stacked photodiode configuration. In the all-optical amplitude modulator, 0.25 mW optical power in the control channel is sufficient to modulate the output power of the data channel by 15 dB. Also, we showed the results of an all-optical controlled two-tap sequence detector for different modulation schemes, OOK, PAM3, and PAM 4, at different settings. A maximum control signal power of 5 mW is needed to calibrate and bias the sequence detector. The tested symbol rate was 1.25 Gbaud; this can be easily increased by reducing the delay of the correlator tap. This sequence detector may be 99 measured to detect other complex modulation formats. In the future, other all-optical processing circuits can be implemented using the same approach. We can accommodate more control signals for complex processing units by reducing the FSR of the wavelength demultiplexer and increasing the number of channels. The loss of the charge depletion modulator can be reduced by shortening its length. This will increase the required driving voltage from the optical to voltage converter, achievable by cascading more photodiodes in series. Reducing the phase modulator loss can enable the implementation of more complex structures without the concern of introducing huge optical loss. For instance, the sequence detector scheme may be extended to detect longer sequences. Lastly, an integrated universal cascadable optical logic gate was demonstrated. Two versions were proposed: moderate-speed (Mbps) zero-biased gate and high-speed (Gbps) biased gate. Different logic operations including, NOT, Buffer, OR, NOR, XOR, XNOR, and NAND, may be realized using the two proposed versions of the logic gates. The proposed circuit can also function as an optical repeater or as a wavelength converter. The zero-biased logic gate combines the power level of the optical operands, then converts it to electrical voltage using photodiodes operating in the photovoltaic (zero-bias) mode and shifts the resonance wavelength (change the transmission) of a microring resonator depending on the combined power level. The main advantage of the proposed structure is that it doesn’t rely on any electrical source or battery. The measured 3dB bandwidth of the proposed structure can reach 8 MHz at an input logic optical power of 2 mW; this slow speed is due to the slow transit response of the photodiode operating in the photovoltaic mode. The dynamic response of the logic gate is tested using 10 Mbps OOK PRBS data. The total optical power required for one such universal logic gate is 160 mW. The Mbps speed range is suitable for some applications like lidar, optical packet switching, or optical system calibration. The electrically biased logic gate has the same concept of operation, except it uses photodiodes 100 operating in the photoconductive mode and combines the logic operands in the electrical domain in the form of currents. The main advantage of this design is that it can support high-speed operations; the simulation results show 3-dB bandwidth of 13 GHz. This version of the logic gate can be used for high-speed applications like optical computing. We also proposed two logic circuit examples that can be implemented using the proposed logic gates: a full adder and a pattern detector. More complex all-optical logic circuits using the proposed universal all-optical logic gates may be created. The logic gate can be modified to obtain the logic operation and its complementary, simultaneously, by using an Add-Drop ring modulator and getting the output data from the through and the drop ports. As a future research direction, we can use the proposed optical circuits in this thesis, which are key enablers for optical signal processing, to implement all-optical processing engines. For instance, all-optical packet switching, and all-optical computing units can be realized. 101 References [1] Kumar, Shiva, and M. Jamal Deen. Fiber optic communications: fundamentals and applications. John Wiley & Sons, 2014. [2] Agrawal, Govind P. Fiber-optic communication systems. John Wiley & Sons, 2012. [3] Kareem, Fairoz Q., et al. "A survey of optical fiber communications: challenges and processing time influences." Asian Journal of Research in Computer Science 7.4 (2021): 48-58. [4] Davis, Christopher C., and Thomas E. Murphy. "Fiber-optic communications." IEEE Signal Processing Magazine 28.4 (2011): 147-150. [5] Stauffer, David Robert, et al. High speed serdes devices and applications. Springer Science & Business Media, 2008. [6] Zhang, Jianmin, et al. "Design and modeling for chip-to-chip communication at 20 Gbps." 2010 IEEE International Symposium on Electromagnetic Compatibility. IEEE, 2010. [7] Hollis, Timothy M. Circuit and Modeling Solutions for High-Speed Chip-To-Chip Communication. Brigham Young University, 2007. [8] Jeff Hockert, “Integrated Photonics Set to Light Up the Data Center,” Intel Tech, May 10,2021. [9] S. J. Ben Yoo, "Prospects and Challenges of Photonic Switching in Data Centers and Computing Systems," J. Lightwave Technol. 40, 2214-2243 (2022). [10] Cisco, “Global data center IP traffic from 2012 to 2021, by data center type (in exabytes per year),” Mar. 2021. [11] “Impact of AI on Electronics and Semiconductor Industries”, IBS, April 2020. [12] Andrae, Anders S.G., and Tomas Edler. 2015. "On Global Electricity Usage of Communication Technology: Trends to 2030" Challenges 6, no. 1: 117-157. 102 [13] Walnum, Hans Jakob & Andrae, Anders. (2016). The Internet: Explaining ICT Service Demand in Light of Cloud Computing Technologies. 10.1007/978-3-319-38807-6_13. [14] Van Heddeghem, Ward, et al. "A power consumption sensitivity analysis of circuitswitched versus packet-switched backbone networks." Computer Networks 78 (2015): 42- 56. [15] Yoo, SJ Ben. "Energy efficiency in the future internet: The role of optical packet switching and optical-label switching." IEEE Journal of Selected Topics in Quantum Electronics 17.2 (2010): 406-418. [16] ASPENCORE Network in IoT times, “How to Avoid HPC Data Traffic Jams with HighSpeed Interface IP,” December, 2020. [17] Lee, Jri, et al. "Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies." IEEE Journal of Solid-State Circuits 50.9 (2015): 2061-2073. [18] Tang, Zixiang, et al. "112Gbps High-speed SerDes Transmitter Based on Duo-Binary Pam4 Encoding." 2021 6th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2021. [19] R.S. Tucker, The role of optics and electronics in high-capacity routers, J. Lightwave Technol. 24, pp. 4655-4673, 2006. [20] Wu, J., Ma, H., Yin, P., Ge, Y., Zhang, Y., Li, L., Zhang, H. and Lin, H. (2021), TwoDimensional Materials for Integrated Photonics: Recent Advances and Future Challenges. Small Sci., 1: 2000053. [21] Chao Xiang, Warren Jin, and John E. Bowers, "Silicon nitride passive and active photonic integrated circuits: trends and prospects," Photon. Res. 10, A82-A96 (2022) [22] Arafin, Shamsul, and Larry A. Coldren. "Advanced InP photonic integrated circuits for communication and sensing." IEEE Journal of Selected Topics in Quantum Electronics 24.1 (2017): 1-12. [23] Koch, Thomas L., and Uziel Koren. "Semiconductor photonic integrated circuits." IEEE Journal of Quantum Electronics 27.3 (1991): 641-653. [24] Dong, Po, et al. "Silicon photonic devices and integrated circuits." Nanophotonics 3.4-5 (2014): 215-228. [25] Absil, Philippe P., et al. "Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O’s." Optics express 23.7 (2015): 9369-9378. 103 [26] Pérez-López, D., López, A., DasMahapatra, P. et al. Multipurpose self-configuration of programmable photonic circuits. Nat Commun 11, 6359 (2020). [27] L. Zhuang, C. Roeloffzen, M. Hoekman, K. Boller, and A. Lowery, "Programmable photonic signal processor chip for radiofrequency applications," Optica 2, 854-859 (2015). [28] P. Toliver, R. Menendez, T. Banwell, A. Agarwal, T. Woodward, N. Feng, P. Dong, D. Feng, W. Qian, H. Liang, D. Lee, B. Luff, and M. Asghari, "A Programmable Optical Filter Unit Cell Element for High Resolution RF Signal Processing in Silicon Photonics," in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2010), paper OWJ4. [29] M. Rasras, C. Madsen, M. Capuzzo, E. Chen, L. Gomez, E. Laskowski, A. Griffin, A. Wong-Foy, S. Patel, A. Gasparyan, J. Le Grange, and A. Kasper, "Integrated variable optical delay lines using high index contrast waveguide," in Optical Amplifiers and Their Applications/Integrated Photonics Research, Technical Digest (CD) (Optical Society of America, 2004), paper IThA5. [30] J. Bauters, M. Heck, D. John, D. Dai, M. Tien, J. Barton, A. Leinse, R. Heideman, D. Blumenthal, and J. Bowers, "Ultra-low-loss high-aspect-ratio Si3N4 waveguides," Opt. Express 19, 3163-3174 (2011). [31] R. L. Moreira et al., "Integrated Ultra-Low-Loss 4-Bit Tunable Delay for Broadband Phased Array Antenna Applications," in IEEE Photonics Technology Letters, vol. 25, no. 12, pp. 1165-1168, June15, 2013, doi: 10.1109/LPT.2013.2261807. [32] S. Idres and H. Hashemi, "Optical Binary Switched Delay Line based on Low Loss Multimode Waveguide," in Optical Fiber Communication Conference (OFC) 2022, S. Matsuo, D. Plant, J. Shan Wey, C. Fludger, R. Ryf, and D. Simeonidou, eds., Technical Digest Series (Optica Publishing Group, 2022), paper Th1D.2. [33] D. Melati and A. Melloni, "On-chip continuously tunable optical delay line based on cascaded Mach-Zehnder interferometers," in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2018), paper M3I.5. [34] Chrostowski, Lukas, and Michael Hochberg. Silicon photonics design: from devices to systems. Cambridge University Press, 2015. [35] T. Ye, Y. Fu, L. Qiao, and T. Chu, "Low-crosstalk Si arrayed waveguide grating with parabolic tapers," Opt. Express 22, 31899-31906 (2014). [36] Y. Fu, T. Ye, W. Tang, and T. Chu, "Efficient adiabatic silicon-on-insulator waveguide taper," Photon. Res. 2, A41-A44 (2014). 104 [37] M. Nakai, T. Nomura, S. Chung, and H. Hashemi, "Geometric Loss Reduction in Tight Bent Waveguides for Silicon Photonics," in Conference on Lasers and Electro-Optics, OSA Technical Digest (online) (Optical Society of America, 2018), paper JW2A.70. [38] S. Chung, M. Nakai, and H. Hashemi, "Low-power thermo-optic silicon modulator for large-scale photonic integrated systems," Opt. Express 27, 13430-13459 (2019). [39] M. Nakai, S. Chung, and H. Hashemi, "Low-power thermo-optic silicon modulator geometrically optimized for photonic integrated circuits," in Conference on Lasers and Electro-Optics, OSA Technical Digest (Optical Society of America, 2020), paper STh4O.8. [40] S. Idres and H. Hashemi, "Low-Power SiN Thermo-Optic Phase Modulator Operating in Red Visible Wavelength Range," in Conference on Lasers and Electro-Optics, OSA Technical Digest (Optical Society of America, 2020), paper JTh2B.7. [41] B. Debaillie et al., "Analog/RF Solutions Enabling Compact Full-Duplex Radios," in IEEE Journal on Selected Areas in Communications, vol. 32, no. 9, pp. 1662-1673, Sept. 2014, doi: 10.1109/JSAC.2014.2330171. [42] K. E. Kolodziej, J. G. McMichael and B. T. Perry, "Multitap RF Canceller for In-Band Full-Duplex Wireless Communications," in IEEE Transactions on Wireless Communications, vol. 15, no. 6, pp. 4321-4334, June 2016, doi: 10.1109/TWC.2016.2539169. [43] H. Luo, M. Holm and T. Ratnarajah, "On the performance of active analog self-interference cancellation techniques for beyond 5G systems," in China Communications, vol. 18, no. 10, pp. 158-168, Oct. 2021, doi: 10.23919/JCC.2021.10.011. [44] Xiuyou Han, Xinxin Su, Meng Chao, Xindi Yang, Weiheng Wang, Shuangling Fu, Yicheng Du, Zhenlin Wu, and Mingshan Zhao, "Integrated photonic RF self-interference cancellation on a silicon platform for full-duplex communication," Photon. Res. 11, 1635- 1646 (2023). [45] Linbojie Huang, Yucheng Zhang, Xiaolei Li, Lei Deng, Mengfan Cheng, Songnian Fu, Ming Tang, and Deming Liu, "Microwave photonic RF front-end for co-frequency co-time full duplex 5G communication with integrated RF signal self-interference cancellation, optoelectronic oscillator and frequency down-conversion," Opt. Express 27, 32147-32157 (2019). [46] S. Idres and H. Hashemi, "Ultra-Wideband Radiofrequency Self-Interference Canceller Using Silicon Photonics Switched DelayLines," in Conference on Lasers and ElectroOptics, Technical Digest Series (Optica Publishing Group, 2024), paper JTh2A.86. 105 [47] S. Idres and H. Hashemi, "Integrated Single Side Band Quadrature Dual-MZI Modulator for High Optical Power Applications," in Frontiers in Optics + Laser Science 2023 (FiO, LS), Technical Digest Series (Optica Publishing Group, 2023), paper JTu4A.2. [48] M. Izutsu et al., “Integrated Optical SSB Modulator/Frequency Shifter,” IEEE J. Quantum Electron. 17, 11 (1981). [49] Bouchaib Hraimel, Xiupu Zhang, Yinqing Pei, Ke Wu, Taijun Liu, Tiefeng Xu, and Qiuhua Nie, "Optical Single-Sideband Modulation With Tunable Optical Carrier to Sideband Ratio in Radio Over Fiber Systems," J. Lightwave Technol. 29, 775-781 (2011) [50] A. Kodigala, M. Gehl, C. T. DeRose, D. Hood, A. T. Pomerene, C. Dallo, D. Trotter, P. Moore, A. L. Starbuck, J. Lee, G. Biedermann, and A. L. Lentine, "Silicon Photonic SingleSideband Generation with Dual-Parallel Mach-Zehnder Modulators," in Conference on Lasers and Electro-Optics, OSA Technical Digest (Optica Publishing Group, 2019), paper STh4N.6. [51] S. Chung, H. Abediasl and H. Hashemi, "A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 275-296, Jan. 2018, doi: 10.1109/JSSC.2017.2757009. [52] Lanxuan Zhang, Yingzhi Li, Yu Hou, Yubing Wang, Min Tao, Bosong Chen, Quanxin Na, Yuxuan Li, Zihao Zhi, Xiaobin Liu, Xueyan Li, Fengli Gao, Xianshu Luo, Guo-Qiang Lo, and Junfeng Song, "Investigation and demonstration of a high-power handling and largerange steering optical phased array chip," Opt. Express 29, 29755-29765 (2021). [53] Hyun-Kyu Kim, Minkyu Kim, Min-hyeong Kim, Youngkwan Jo, Stefan Lischke, Christian Mai, Lars Zimmermann, and Woo-Young Choi, "Si photonic-electronic monolithically integrated optical receiver with a built-in temperature-controlled wavelength filter," Opt. Express 29, 9565-9573 (2021). [54] Joris Lambrecht, Jochem Verbist, Hannes Ramon, Michael Vanhoecke, Johan Bauwelinck, Xin Yin, and Gunther Roelkens, "Low-Power (1.5 pJ/b) Silicon Integrated 106 Gb/s PAM4 Optical Transmitter," J. Lightwave Technol. 38, 432-438 (2020) [55] Q. Cheng, J. Kwon, M. Glick, M. Bahadori, L. P. Carloni and K. Bergman, "Silicon Photonics Codesign for Deep Learning," in Proceedings of the IEEE, vol. 108, no. 8, pp. 1261-1282, Aug. 2020, doi: 10.1109/JPROC.2020.2968184. [56] Shen, Y., Harris, N., Skirlo, S. et al. Deep learning with coherent nanophotonic circuits. Nature Photon 11, 441–446 (2017). https://doi.org/10.1038/nphoton.2017.93 [57] B. Mukherjee, "WDM optical communication networks: progress and challenges," in IEEE Journal on Selected Areas in Communications, vol. 18, no. 10, pp. 1810-1824, Oct. 2000, doi: 10.1109/49.887904. 106 [58] M. Ruffini et al., "DISCUS: an end-to-end solution for ubiquitous broadband optical access," in IEEE Communications Magazine, vol. 52, no. 2, pp. S24-S32, February 2014, doi: 10.1109/MCOM.2014.6736741. [59] A. Fallahpour, A. Minoofar, F. Alishahi, K. Zou, S. Idres, H. Hashemi, J. Habif, M. Tur, and A. Willner, "Experimental Demonstration of Remotely Controlled and Powered Optical Switching Based on Laser-Delivered Bias and Control Signals," in Conference on Lasers and Electro-Optics, J. Kang, S. Tomasulo, I. Ilev, D. Müller, N. Litchinitser, S. Polyakov, V. Podolskiy, J. Nunn, C. Dorrer, T. Fortier, Q. Gan, and C. Saraceno, eds., OSA Technical Digest (Optica Publishing Group, 2021), paper STh1F.7. [60] A. Fallahpour, A. Minoofar, F. Alishahi, K. Zou, S. Idres, H. Hashemi, J. Habif, M. Tur, and A. Willner, "Experimental demonstration of remotely powered, controlled, and monitored optical switching based on laser-delivered signals," Opt. Lett. 46, 4589-4592 (2021). [61] M. W. AlTaha, H. Jayatilleka, Z. Lu, J. F. Chung, D. Celo, D. Goodwill, E. Bernier, S. Mirabbasi, L. Chrostowski, and S. Shekhar, "Monitoring and automatic tuning and stabilization of a 2×2 MZI optical switch for large-scale WDM switch networks," Opt. Express 27, 24747-24764 (2019). [62] J. D. López-Cardona, R. Altuna, D. S. Montero and C. Vázquez, "Power Over Fiber in CRAN With Low Power Sleep Mode Remote Nodes Using SMF," in Journal of Lightwave Technology, vol. 39, no. 15, pp. 4951-4957, Aug.1, 2021, doi: 10.1109/JLT.2021.3080631. [63] F. Alishahi, A. Minoofar, A. Fallahpour, K. Zou, H. Zhou, J. Habif, M. Tur, and A. E. Willner, "Experimental Demonstration of Remotely Controlled and Powered Tunable Optical 2-4 Taps Correlator of a 20-100 Gbit/s QPSK Channel Based on Laser-Delivered Bias and Control Signals," in Optical Fiber Communication Conference (OFC) 2021, P. Dong, J. Kani, C. Xie, R. Casellas, C. Cole, and M. Li, eds., OSA Technical Digest (Optica Publishing Group, 2021), paper W6A.20. [64] S. Idres, A. Fallahpour, A. Willner, J. Habif, and H. Hashemi, "Integrated All-Optical Controlled Amplitude Modulator Using Laser Delivered Signals," in Conference on Lasers and Electro-Optics, Technical Digest Series (Optica Publishing Group, 2022), paper JTh3A.48. [65] S. Chung, M. Nakai, S. Idres, Y. Ni and H. Hashemi, "19.1 Optical Phased-Array FMCW LiDAR with On-Chip Calibration," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 286-288. [66] K. Van Gasse, J. Van Kerrebrouck, A. Abbasi, J. Verbist, G. Torfs, B. Moeneclaey, G. Morthier, X. Yin, J. Bauwelinck, and G. Roelkens, "III-V-on-Silicon Photonic Transceivers for Radio-Over-Fiber Links," J. Lightwave Technol. 36, 4438-4444 (2018). 107 [67] S. Idres, J. Habif, and H. Hashemi, "Optically biased and controlled signal processing in silicon photonics," Opt. Express 32, 6130-6140 (2024). [68] A. Melloni and M. Martinelli, "Synthesis of direct-coupled-resonators bandpass filters for WDM systems," in Journal of Lightwave Technology, vol. 20, no. 2, pp. 296-303, Feb. 2002. [69] F. Xia, M. Rooks, L. Sekaric, and Y. Vlasov, "Ultra-compact high order ring resonator filters using submicron silicon photonic wires for on-chip optical interconnects," Opt. Express 15, 11934-11941 (2007). [70] A. S. Nagra, O. Jerphagnon, P. Chavarkar, M. VanBlaricum and R. A. York, "Bias free optical control of microwave circuits and antennas using improved optically variable capacitors," 2000 IEEE MTT-S International Microwave Symposium Digest (Cat. No.00CH37017), 2000, pp. 687-690 vol.2, doi: 10.1109/MWSYM.2000.863276. [71] N. Feng, S. Liao, D. Feng, P. Dong, D. Zheng, H. Liang, R. Shafiiha, G. Li, J. Cunningham, A. Krishnamoorthy, and M. Asghari, "High speed carrier-depletion modulators with 1.4Vcm VπL integrated on 0.25μm silicon-on-insulator waveguides," Opt. Express 18, 7994- 7999 (2010). [72] Xi Xiao, Hao Xu, Xianyao Li, Zhiyong Li, Tao Chu, Yude Yu, and Jinzhong Yu, "Highspeed, low-loss silicon Mach–Zehnder modulators with doping optimization," Opt. Express 21, 4116-4125 (2013). [73] R. Soref and B. Bennett, "Electrooptical effects in silicon," in IEEE Journal of Quantum Electronics, vol. 23, no. 1, pp. 123-129, January 1987, doi: 10.1109/JQE.1987.1073206. [74] M. S. Rasras et al., "A Programmable 8-bit Optical Correlator Filter for Optical Bit Pattern Recognition," in IEEE Photonics Technology Letters, vol. 20, no. 9, pp. 694-696, May1, 2008. [75] Yang Liu, Amol Choudhary, David Marpaung, and Benjamin J. Eggleton, "Integrated microwave photonic filters," Adv. Opt. Photon. 12, 485-555 (2020). [76] Kwyro Lee et al., "The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application," in IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1415-1422, July 2005. [77] Shen, Y., Harris, N., Skirlo, S. et al. Deep learning with coherent nanophotonic circuits. Nature Photon 11, 441–446 (2017). [78] Feldmann, J., Youngblood, N., Karpov, M. et al. Parallel convolutional processing using an integrated photonic tensor core. Nature 589, 52–58 (2021). 108 [79] H. Taylor, "Guided wave electrooptic devices for logic and computation," Appl. Opt. 17, 1493-1498 (1978). [80] J. Hardy and J. Shamir, "Optics inspired logic architecture," Opt. Express 15, 150-165 (2007). [81] Lei Zhang, Ruiqiang Ji, Lianxi Jia, Lin Yang, Ping Zhou, Yonghui Tian, Ping Chen, Yangyang Lu, Zhenyu Jiang, Yuliang Liu, Qing Fang, and Mingbin Yu, "Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators," Opt. Lett. 35, 1620-1622 (2010). [82] Yulan Fu, Xiaoyong Hu, Qihuang Gong, “Silicon photonic crystal all-optical logic gates,” Physical Letters A, vol. 377, no. 3-4, pp. 329-333 (2013) [83] Qiu, C., Xiao, H., Wang, L. et al., “Recent advances in integrated optical directed logic operations for high performance optical computing: a review,” Front. Optoelectron. 15, 1 (2022). [84] S. Mohammadnejad, Z. F. Chaykandi and A. Bahrami, "MMI-Based Simultaneous AllOptical XOR–NAND–OR and XNOR–NOT Multilogic Gate for Phase-Based Signals," in IEEE Journal of Quantum Electronics, vol. 50, no. 12, pp. 1-5, Dec. 2014. [85] Lu He, Furong Zhang, Huizhen Zhang, Ling-Jun Kong, Weixuan Zhang, Xingsheng Xu, and Xiangdong Zhang, “Topology-Optimized Ultracompact All-Optical Logic Devices on Silicon Photonic Platforms,” ACS Photonics 9(2), 597-604(2022). [86] Q. Xu and M. Lipson, "All-optical logic based on silicon micro-ring resonators," Opt. Express 15, 924-929 (2007). [87] A. Bogoni, X. Wu, Z. Bakhtiari, S. Nuccio, and A. Willner, "640 Gbits/s photonic logic gates," Opt. Lett. 35, 3955-3957 (2010). [88] Tian, Y., Liu, Z., Xiao, H. et al. Experimental demonstration of a reconfigurable electrooptic directed logic circuit using cascaded carrier-injection micro-ring resonators. Sci Rep 7, 6410 (2017). [89] Gostimirovic, D., Ye, W.N. Ultracompact CMOS-compatible optical logic using carrier depletion in microdisk resonators. Sci Rep 7, 12603 (2017). [90] Zhoufeng Ying and Richard Soref, "Electro-optical logic using dual-nanobeam MachZehnder interferometer switches," Opt. Express 29, 12801-12812 (2021). [91] R. Soref, F. De Leonardis, Z. Ying, V. M. N. Passaro, and R. T. Chen, “Silicon-Based Group-IV O-E-O Devices for Gain, Logic, and Wavelength Conversion,” ACS Photonics 7(3), 800–811(2020). 109 [92] S. Idres, J. Habif, and H. Hashemi, "Optical Input – Optical Output Logic Gates Using Ring Modulator and Photovoltaic Diodes," in Conference on Lasers and Electro-Optics, Technical Digest Series (Optica Publishing Group, 2024), paper JTh2A.112. [93] L. Del Bino, N. Moroney, and P. Del’Haye, "Optical memories and switching dynamics of counterpropagating light states in microresonators," Opt. Express 29, 2193-2203 (2021). [94] Alexoudi, T., Kanellos, G.T. & Pleros, N. Optical RAM and integrated optical memories: a survey. Light Sci Appl 9, 91 (2020).
Abstract (if available)
Abstract
Optical signal processing can play an important role in numerous optical systems broadly used in today’s world, such as optical interconnects and networking, optical computing and machine learning, RF over fiber, lidar, etc. While these systems contain and transmit the data in the optical format, the information processing occurs primarily using CMOS circuits in the electrical domain, which necessitates power-hungry and latency-inducing opto-electric-opto conversion. Performing appropriate signal processing on the optically modulated information signal may reduce the power consumption and latency across the system while bolstering security and high-speed data rate. Silicon photonics integrated silicon (Si PIC), along with the advances in materials and devices, are the key enabling technologies growing the optical signal processing practical utilization.
This thesis features different integrated optical signal processing circuits and systems in both the analog and digital domains. True time delay lines are key enablers in analog optical signal processing; therefore, a low-loss variable delay line, leveraging wide straight waveguides and compact bends, is implemented. Targeting optical signal processing occurs at remote nodes with hard access to reliable electrical supply and control signals. An all-optical remotely controlled and biased signal processing system, utilizing WDM laser-delivered bias and control signals, is proposed. Two examples are employed to demonstrate this system: an amplitude modulator and a two-tap sequence detector. Universal optical input – optical output cascadable logic gates are also reported, facilitating digital optical signal processing. These proposed optical processing systems and circuits are fabricated in a commercial silicon photonics process and experimentally demonstrated.
Linked assets
University of Southern California Dissertations and Theses
Conceptually similar
PDF
Integrated large-scale monolithic electro-optical systems in standard SOI CMOS process
PDF
Silicon integrated devices for optical system applications
PDF
High-speed and reconfigurable all-optical signal processing for phase and amplitude modulated signals
PDF
Silicon micro-ring resonator device design for optical interconnect systems
PDF
Integrated silicon waveguides and specialty optical fibers for optical communications system applications
PDF
Reconfigurable and flexible high-speed optical signal processing and spectrally shared optical subsystems
PDF
Reconfigurable high‐speed optical signal processing and high‐capacity optical transmitter
PDF
Surface acoustic wave waveguides for signal processing at radio frequencies
PDF
Optical signal processing for high-speed, reconfigurable fiber optic networks
PDF
Reconfigurable high speed optical signal processing for optical communication and modulation format manipulation
PDF
Reconfigurable high-speed processing and noise mitigation of optical data
PDF
Applications of all optical signal processing for advanced optical modulation formats
PDF
Investigations of Mie resonance-mediated all dielectric functional metastructures as component-less on-chip classical and quantum optical circuits
PDF
Resonant light-matter interactions in nanophotonic structures: for manipulating optical forces and thermal emission
PDF
All-optical signal processing toward reconfigurable optical networks
PDF
Optical wave mixing for tunable delays and high‐speed signal processing
PDF
Nonlinear optical signal processing for high-speed, spectrally efficient fiber optic systems and networks
PDF
Single photon emission characteristics of on-chip integrable ordered single quantum dots: towards scalable quantum optical circuits
PDF
A variation aware resilient framework for post-silicon delay validation of high performance circuits
PDF
Architectures and integrated circuits for RF and mm-wave multiple-antenna systems on silicon
Asset Metadata
Creator
Idres, Samer Sayed Bahr
(author)
Core Title
Silicon photonics integrated circuits for analog and digital optical signal processing
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Degree Conferral Date
2024-05
Publication Date
05/21/2024
Defense Date
04/25/2024
Publisher
Los Angeles, California
(original),
University of Southern California
(original),
University of Southern California. Libraries
(digital)
Tag
all-optical signal processing,analog optical signal processing,digital optical signal processing,OAI-PMH Harvest,optical full adder,optical logic circuits,optical logic gates,optical sequence detection,optical switching,optical true time delay line,optically controlled signal processing,RF self-interference canceller,silicon photonics integrated circuit
Format
theses
(aat)
Language
English
Contributor
Electronically uploaded by the author
(provenance)
Advisor
Hashemi, Hossein (
committee chair
), Povinelli, Michelle (
committee member
), Ravichandran, Jayakanth (
committee member
)
Creator Email
bahr.samer@gmail.com,idres@usc.edu
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-oUC113950175
Unique identifier
UC113950175
Identifier
etd-IdresSamer-12987.pdf (filename)
Legacy Identifier
etd-IdresSamer-12987
Document Type
Dissertation
Format
theses (aat)
Rights
Idres, Samer Sayed Bahr
Internet Media Type
application/pdf
Type
texts
Source
20240521-usctheses-batch-1158
(batch),
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Access Conditions
The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the author, as the original true and official version of the work, but does not grant the reader permission to use the work if the desired use is covered by copyright. It is the author, as rights holder, who must provide use permission if such use is covered by copyright.
Repository Name
University of Southern California Digital Library
Repository Location
USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA
Repository Email
cisadmin@lib.usc.edu
Tags
all-optical signal processing
analog optical signal processing
digital optical signal processing
optical full adder
optical logic circuits
optical logic gates
optical sequence detection
optical switching
optical true time delay line
optically controlled signal processing
RF self-interference canceller
silicon photonics integrated circuit