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Integrating material growth and device physics: building blocks for cost effective emerging electronics and photonics devices
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Content
Integrating Material Growth and Device Physics:
Building Blocks for Cost Effective Emerging Electronics
and Photonics Devices
by
Hyun Uk Chae
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
August 2024
Copyright 2024 Hyun Uk Chae
ii
To all the people who made me to stand where I am today
iii
Acknowledgments
The reason I find myself here, writing this, is not solely due to my own efforts but rather the continuous
support and cheers from the people whom I love, whom I met, and whom I have worked on during my time
at USC.
I must begin by acknowledging my advisor, Rehan Kapadia. I still remember first meeting him in his office.
He was passionate about introducing all the research works (Material growth, Hot Electron
Electrochemistry, and Photoemission) in his group. I had no idea what those were then, and I didn’t realize
I would work on all those topics throughout my Ph.D. journey. With his successful research guidance, I
could explore various research topics. I can indeed say that by doing research with him, I could broaden
my research insight in various fields, including material science, electronics, photonics, and device physics.
Throughout my Ph.D. program, he was always supportive of what I had done, no matter whether it was a
sequence of failures. Without his strong driving force to explore different research topics, I couldn’t be here
with all the achievements that I have done. Thanks to his support, I had a valuable opportunity to meet
people in and out of the USC research community and build an academic connection. He not only supported
and inspired my research work with insightful academic advice and guidance but also focused on cultivating
me as an independent researcher. I can say that it’s not only a research advisor but one of my life mentors
who can make someone feel that I want to live my life as passionately as him. I’ll take all the lessons in my
future life.
I extend my gratitude to several other professors who significantly impacted my Ph.D. experience. Professor
Michelle Povinelli provided me with the opportunity to collaborate with her research group in the field of
photonics, offering unwavering support throughout. Professor Steve Cronin generously allowed me access
to essential equipment for my research. Professor Wei Wu's teachings during my early days at USC laid
the groundwork for my subsequent research works. Professor Andrea Armani provided a valuable
opportunity to work on organic materials. Professor Zhenglu Li helped a lot in growth research work with
a clear explanation of the DFT field. Professor Yu-Tsun Shao's insights and shared knowledge further
enriched my research. Special thanks to professors, from whom I took courses, Prof. Levi, Prof. Dapkus,
Prof. Prata, and Prof. Tanguay. Outside of USC, I would like to acknowledge few of our research
collaborators; Prof. Siddharth Karkare from ASU, Prof. Peng Zhang from MSU, and Prof. Kunal Mukherjee
from Stanford. My time at NASA JPL MDL was invaluable to my research journey. I am thankful to Dr.
Frank Greer for his mentorship and for fostering an environment of intellectual growth within MDL.
Special thanks to the place where I spent the majority of my time at USC, the Nanofabrication Lab, and the
cleanroom staffs. Dr. Donghai Zhu, with his various help in processing my device. Thanks to other staff,
Dr. Shivakumar Bhaskaran, Alfonso Jimenez, Joey Vo, and Eugene Yoon. Dr. Amir Avishai's contributions
to material characterization at the Core Nano Imaging Center are deeply appreciated.
I cannot help but say my incredible research partners whom I met in and out of our research lab. For former
members: Dr. Debarghya Sarkar, my lab mentor, taught me all the necessary device fab and knowledge.
Dr. Jun Tao, with whom I created a special bond beyond just a research lab mate, and Dr. Qinfeng Lin, who
trained me on a hot electron device project, the first core part of my research work at USC. Dr. Fatemeh
iv
Razefier taught me about various electron emission setups and research that she worked on, and we ended
up extending this research topic broader now. Dr. Ragib Ahsan is the best research partner and friend I have
ever had in my Ph.D. journey in this lab. I couldn’t have achieved all these fantastic research works without
him. Thanks to the junior members who closely worked with me, Juan Sanchez Vazquez, Zezhi Wu, and
Anika Tabassum Priyoti, who helped me a lot on my research work. Thanks to other junior members and
friends outside of our research lab whom I met during my Ph.D. journey.
I would like to express my sincere gratitude to my Korean friends whom I met here and who helped me to
lead the Korean Graduate Student Association (KGSA) as a president for two years from 2020-2022.
Special thanks to my dear friends Thomas Choi and Chanwook Oh, with whom I share a profound bond as
USC 92 ECE Ph.D. Trio.
Lastly, I express my deepest appreciation to my fiancée (soon to be my wife!), Daye Nam. Meeting her
during my time at USC was the highlight of my life. Our enduring long-distance relationship between Los
Angeles and Pittsburgh has only strengthened our bond over time, and I am grateful for her unwavering
support through the challenges we faced. I also extend my heartfelt thanks to my parents, Youngseok Chae
and Misun Park, and my younger brother, Seungjae Chae, whose constant support and belief in me have
strengthened me. I dedicate this dissertation to my fiancée and family.
v
Table of Contents
ACKNOWLEDGMENTS ............................................................................................................ III
ABSTRACT.................................................................................................................................VII
CHAPTER 1. INTRODUCTION ................................................................................................... 1
1.1 FUTURE OF ELECTRONICS AND PHOTONICS..................................................................................1
1.2 HOT ELECTRON ELECTROCHEMISTRY .........................................................................................4
1.3 NEXT-GENERATION PHOTOEMISSION DEVICE.............................................................................5
1.4 MONOLITHIC III-V ON METAL FOR STEADY-STATE METASURFACE...........................................6
1.5 EPITAXIAL TRANSFER OF III-V ON METAL FOR ELECTRICALLY TUNABLE METASURFACE .......6
1.6 DEFECT FILTERING AT THE INTERFACE OF MOCVD/TLP HETEROGENOUS EPITAXIAL III-V ON
SILICON......................................................................................................................................................7
1.7 OVERVIEW OF THE DISSERTATION...............................................................................................7
CHAPTER 2. HOT ELECTRON ELECTROCHEMISTRY ....................................................... 13
2.1 INTRODUCTION...........................................................................................................................13
2.2 HOT ELECTRON ELECTROCHEMISTRY -METAL BASED DEVICE.................................................13
2.3 HOT ELECTRON ELECTROCHEMISTRY - GRAPHENE-BASED DEVICE .........................................24
CHAPTER 3. NEXT-GENERATION PHOTOEMISSION DEVICE......................................... 33
3.1 INTRODUCTION...........................................................................................................................33
3.2 PHOTOEMISSION THROUGH GIS STRUCTURE.............................................................................35
3.3 PHOTOEMISSION THROUGH WAVEGUIDE INTEGRATED DEVICE .................................................39
3.4 SUMMARY...................................................................................................................................42
CHAPTER 4. III-V INTEGRATED METASURFACE IN MID-IR........................................... 44
4.1 INTRODUCTION...........................................................................................................................44
4.2 TLP III-V GROWTH ON METAL FOR STEADY-STATE METASURFACE .......................................45
4.3 SUMMARY...................................................................................................................................53
CHAPTER 5. EPITAXIAL TRANSFER OF III-V ON METAL FOR ELECTRICALLY
TUNABLE METASURFACE...................................................................................................... 55
5.1 INTRODUCTION...........................................................................................................................55
vi
5.2 DEVICE OPERATION PRINCIPLE.................................................................................................58
5.3 SUMMARY...................................................................................................................................66
CHAPTER 6. DEFECT FILTERING AT THE INTERFACE OF MOCVD/TLP
HETEROGENOUS EPITAXIAL III-V ON SILICON................................................................ 70
6.1 INTRODUCTION...........................................................................................................................70
6.2 EXPERIMENTAL AND THEORETICAL DETAILS............................................................................71
6.3 SUMMARY...................................................................................................................................76
vii
Abstract
As Moore’s Law reaches an endpoint, this situation calls for the development of new
functionalities in electronics and photonics device research. Various types of materials and devices
have been studied to address these issues. This thesis shows recent research progress on creating
new functionalities in emerging electronics and photonics devices and the physics and material
science behind them utilizing the non-equilibrium hot electrons and III-V semiconductors.
Multiple factors inspired these; first, the superior properties of non-equilibrium hot electrons in
many different fields, such as electrochemistry and vacuum electronics. Here, we showed a high
quantum efficiency device to derive the hydrogen evolution reaction (HER) with hot electrons
collected from the metal-insulator-semiconductor (MIS) structure. Similar types of structures can
be used in photoemission applications which mimic the negative electron affinity (NEA)
photocathode. From a material perspective, III-V semiconductors integrated in a non-epitaxial
substrate realize new functionality devices. Our progress in successfully achieving monolithic IIIV integration on metallic substrate with the low-temperature templated liquid phase (LT-TLP)
method was shown to build a metasurface in the Mid-IR range. Epitaxial transfer of p-i-n GaAs
on metal to create an electrically tunable metasurface was presented as an alternative III-V
integration method. In addition, TLP growth was used as a defect filtering layer to reduce the
defect density introduced at the III-V/Si interface, which is the long-desired goal in the materials
community to integrate III-V directly grown on Si. Based on these results, characterization and
analysis of high-quality III-V semiconductor monolithically grown on Si is presented.
viii
1
Chapter 1. Introduction
1.1 Future of electronics and photonics
As reported in IDC, the global datasphere is expected to grow from 6 Zettabytes (ZB) in 2015 to
19,267 ZB by 2035. One zettabyte is equivalent to a trillion gigabytes (GB). To handle this massive
amount of data storage and transmission, speed but consuming less power is always desired.
Silicon electronics has been ruled out by the semiconductor industry for the past few decades,
ever since the first integrated circuit was invented in 1958.2 Now the size of the individual
transistors composing IC went down to 2nm gate length, there is limited space for electronics to
be further revolutionized.3-6 More advanced approaches are highly desired to overcome this
limitation and break through current criteria. To extend Moore’s Law, seeking new types of
devices and material platforms are highly desired. Two main agendas can be followed: i) novel
device design which can maximize the physics underlying it and ii) exploring materials that can
Figure 1.1 Annual size of global datasphere, Source:IDC
Figure 1.1 Annual size of global datasphere source: IDC
FiFigure 1.2 Process flow of wafer boding to SOI photonic integrated circuit and application of III-V photonics in many
different applications, Copyright 2022, Springer Nature.gure 3.1 Annual size of global datasphere, Source:IDC
Figure 1.1 Annual size of global datasphere source: IDC
2
be utilized in both electronics and photonics superior to silicon, to enable low power and highperformance digital logic circuits, and photonic integrated circuits (PIC) as well.
In terms of device structure perspective, hot electron-based devices and physics have been studied
and utilized in many different fields. Due to their short lifetime before thermalization, an optimized
device structure to capture the non-equilibrium carriers is highly desired.7
With this, utilizing hot
electrons can be applied to various applications such as electrochemical reactions or electron
emission for vacuum electronics.8-10
In terms of material perspective, various types of materials have been studied to replace the
channel material for better carrier transportation. The two-dimensional (2D) materials, perovskite,
and organic materials are widely studied for different applications such as flexible electronics,
energy devices, and biocompatible medical devices.11-15 III-V materials have been most widely
studied than any other emerging materials from many different perspectives. Thanks to their
superior properties in both electronics and photonics applications, tons of research have been
conducted. Even though, III-V has been impeded in the silicon industry due to two main reasons:
i) Cost of the epitaxial wafer and complexity of the growth system and ii) controlling the material
quality when integrated in silicon substrates. Specifically, challenges associated with high-quality
III-V growth on Si and other non-lattice matched substrates are a significant roadblock preventing
the widespread adoption of III-V transistors for logic device applications and silicon integrated
III-V photonics so far. Several techniques to overcome this limitation have been applied such as
epitaxial lift-off (ELO), wafer bonding, epitaxial lateral overgrowth16, nanowires17,18,19,20, and
direct growth21,22,23,24 have been developed, however, these techniques still face significant
obstacles. Specifically, transfer process (Figure 1.2) is one of the widely accepted methods in
3
photonics integration, however, due to the costive III-V epitaxial wafers, the size of alternative
growth and transfer approaches are limited in size and scale by available substrates. This is
acceptable for small scale applications, but there are many practical applications that may require
larger scale devices (e.g. 300 mm or greater). Growth on III-V substrates and transfer is limited to
wafer scales (e.g. 4” for InP or 6” for GaAs). To target this problem, integrated photonics taking
advantage of silicon infrastructure has been spotlighted past few years. One of the main restrictions
of photonic integrated circuits (PIC) is their optical component integration directly on silicon. IIIV semiconductor is one of the main building blocks for future integrated photonics thanks to their
superior optical and photonic properties.
In this thesis, we will focus on the various topics of new device functionalities and material
integration. This chapter will introduce an overview of those topics, non-equilibrium hot electron
devices, and their physics, and their specific application will be dealt with. III-V integration on a
Figure 1.4 Process flow of wafer boding to SOI photonic integrated circuit and application of III-V photonics in many
different applications, Copyright 2022, Springer Nature.
Figure 1.2 Process flow of wafer boding
Figure 2.1 Proof of concept MIS device demonstrated for hot electron electrochemistry
device.cations, Copyright 2022, Springer Nature.
4
silicon platform to create different device functionalities and growth of high-quality material
through a defect filtering mechanism will be introduced.
1.2 Hot Electron Electrochemistry
Generation and extraction of hot electrons from the surface of metallic materials or
semiconductors have been widely studied past few years.25-28 Small, but highly energetic
population of non-thermal equilibrium carriers with energies above the Fermi level has drawn lots
of research interest in many different aspects. In this proposal, we will discuss the previous work
our group has been conducted to maximize the efficiency of those hot electrons in several different
fields. One can be an electrochemical reaction, which requires a potential barrier to overcome for
specific chemical reactions to occur. Using hot electrons to drive electrochemical reactions has
drawn considerable interest in driving high-barrier reactions and enabling efficient solar to fuel
conversion.29-31 However, the conversion efficiency from hot electrons to electrochemical products
is typically low due to high hot electron scattering rates. We have presented a high quantum
efficiency to derive hydrogen evolution reaction (HER) with hot electrons collected from metalinsulator-semiconductor (MIS) structure.9, 10 It is shown that the hydrogen evolution reaction
(HER) can be efficiently modulated by hot electrons injected into a thin gold film by an Au-Al2O3-
Si MIS junction. Later this demonstration work was further extended by replacing the metallic
layer to graphene which has larger benefit over the metallic layer. By simultaneously measuring
the currents from the solution, graphene, and silicon terminals during the experiments, we find that
the HER rate can be decomposed into three components: (i) thermal electron, corresponding to the
thermal electron distribution in graphene (ii) hot electron, corresponding to electrons injected from
silicon into graphene which drive the HER before fully thermalizing and (iii) silicon direct
5
injection, corresponding to electrons injected from Si into gold that drive the HER. In addition to
exploring the hot electron physics, we have further illuminated the role of surface adhesion and
electron transfer mechanism between the reaction surface and adsorbed hydrogen atom by using
the intentionally defective graphene achieved by plasma dry etching. A detailed study and
explanation will be shown in Chapter 2 of this thesis.
1.3 Next-Generation Photoemission Device
High brightness photoemitters are required in many applications such as ultrafast Electron
Diffraction and X-Ray free electron Lasers32, 33
. High brightness beams require rapid response
times, low mean transverse energies (MTE), and high quantum efficiencies. Negative electron
affinity (NEA) cathodes, composed of a GaAs wafer and a Cs/O surface layer, have been shown
to simultaneously exhibit good external quantum efficiencies (EQE) of ~10-2
and reasonable MTEs.
Here, we demonstrate two novel device structures for the next-generation photoemission device.
The first is a waveguide-integrated photoemission device. To increase the efficiency of light
coupling into the photoemissive surface, a waveguide in combination with a grating coupler has
been introduced to facilitate the integration of the photoemission process. We directly grow Cs3Sb
thin film on top of the waveguide to build an integrated photonics electron beam. The second
device demonstrates the electronically tunable negative electron affinity photocathode. The
voltage is applied between the semiconductor and graphene, generating an electric field which
mimics the surface dipole field in an NEA photocathode. Due to the monolayer thickness of the
graphene, electrons injected into graphene do not require transport to the emitting surface. This
device is air-stable with a simple ex-situ fabrication flow while preserving the advantages of NEA
photocathodes. More detail analysis and experimental results will be shown in the following
chapter 3.
6
1.4 Monolithic III-V on Metal for Steady-State Metasurface
In this section, a large single crystalline III-V material grown directly on the metallic substrate as
a building block for the mid-IR thermal emitter is presented. Among all metal substrates,
molybdenum and tungsten have superior properties that enable III-V TLP growth. Based on the
templated liquid phase (TLP) growth technique, we successfully achieved a larger area of single
crystalline, which can be used for further device fabrication. The geometrically tunable thermal
emitter is presented as a proof-of-concept device with this growth technique; however, this can be
further extended towards an electrically tunable device by properly designing the top electrode and
isolating it from the bottom metal substrates.
1.5 Epitaxial Transfer of III-V on Metal for Electrically Tunable Metasurface
III-V semiconductor has been widely studied for electrical dynamically tunable metasurfaces due
to their large refractive index tunability in the mid to far-infrared. In this section, we use an
epitaxial transfer approach to transfer the semiconductor on a highly reflective metal surface,
analogous to approaches used for photovoltaic and optoelectronic devices. This approach offers
two main benefits vs direct growth directly on III-V wafers. First, it eliminates the use of heavily
doped III-Vs as a reflector, improving the ultimate quality factor of the device and reducing the
burden of constructing a complex device structure through a simple fabrication approach, and
second, it enables lower cost, scalable manufacturing using pick and place or direct transfer
approaches, analogous to those explored for microLEDs manufacturing. Here, along with the
experimental data, we carried out both optical and electrical device simulations to quantify the
electron injection and resulting optical effects, allowing us to compare the results and approach
them to previous work.34-36
7
1.6 Defect Filtering at the Interface of MOCVD/TLP Heterogenous Epitaxial
III-V on Silicon
Integrating III-V semiconductor material is a key component in achieving advanced electronics
and photonics applications for the future ‘extended’ Moore’s Law regime. Specifically, to realize
integrated photonics with silicon-based fabrication, combining the high-quality photon
source/detectors in the system is significant. To realize heterogeneous integration through direct
growth, it is necessary to use lattice-matching buffer layers. This imposes a significant growth
challenge: for tightly integrated CMOS, thick lattice-matching buffer layers for each material must
be grown with nanometer spacing, a significant challenge considering. As such, enabling high
quality growth without the use of lattice matching layers would provide a clear path towards direct
growth of III-V CMOS. Multiple approaches to achieve growth without thick lattice matching
buffers have been presented, such as rapid melt growth (RMG), and template assisted selective
epitaxy (TASE). However, each of the growth techniques suffers from different challenges.
Templated liquid phase growth is one of the promising growth techniques which uses one stone to
catch two birds, the cost, and the material quality of the grown film. Heterogenous TLP III-V on
silicon to filter out defects introduced at the III-V/Si interface will be presented in the chapter 6.
1.7 Overview of the Dissertation
This dissertation consists of five chapters. Chapter 1(this chapter) begins with an overview of all
the research, including hot electron-based devices and III-V material research and their
applications in various research fields, from which the opportunities and strength of III-V
semiconductor-based devices are illustrated. Chapter 2 presents hot electron-based
8
electrochemical device and their application. Chapter 3 presents the next-generation
photoemission devices realized through semiconductor device structure. Chapter 4 presents the
integration of III-V on the metallic substrate through a novel growth technique to realize a steadystate metasurface. Chapter 5 introduces the epitaxial transfer of III-V material on the metallic
substrate to create an electrically tunable metasurface in the mid-IR range. Chapter 6 presents the
defect-filtering through TLP III-V growth on top of a defective III-V/Si substrate, which can be
used for high-performance optoelectronics and photonics devices in photonics integrated circuits.
9
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10
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13
Chapter 2. Hot Electron Electrochemistry
2.1 Introduction
Efficiently using hot electrons before thermalization has been an aim of fields such as hotelectron transistors, solar cells, plasmonic, photoemission, memory, and solar-to-fuel devices.
However, non-equilibrium electrons exhibit lifetimes of ~1-100 fs due to electron-electron and
electron-phonon interactions1-3
. These ultra-short hot carrier lifetimes drive the thermalization
process to dominate over most other technologically relevant processes, causing devices to have
low hot-electron efficiencies generally. Multiple strategies have been explored to overcome these
challenges, including engineering systems with low-electron densities and weak electron-phonon
coupling, such as quantum dots, minimizing the transit length of hot electrons, by creating devices
using 2-D materials, and the search for new materials with naturally favorable scattering rates,
such as perovskites. However, the overall efficiency of these hot electron devices has mainly
precluded their practical use. Here in this proposal, a well-designed device structure having a
metal-insulator-semiconductor (MIS) stack to generate and collect the hot electrons efficiently and
utilize them in two different research fields is presented. If one can extract the hot electrons from
the designed device structure before they thermalize, it can be used to derive chemical reactions
that require certain chemical potentials in electrochemical reactions such as hydrogen evolution
reaction (HER).
2.2 Hot electron electrochemistry -Metal Based Device
By taking advantage of hot electrons, one can overcome a chemical potential barrier to initiate
the chemical reaction. With MIS structure under biased conditions, the thermal electrons in the
silicon device will become hot electrons in a metal layer, which got separated by an oxide layer
14
after tunneling. For this tunneled electron accelerated by an external electric field, if there were no
other terminals in this device, those electrons would then cool to the Fermi level of the top layer,
with the excess energy being dissipated as heat. However, in these devices, the top layer is also in
contact with a solution, enabling electrons in the Au to drive electrochemical reactions. Thus,
depending on the relative rates of cooling and reaction, the injected hot electrons in Au can traverse
multiple pathways. In the first demonstration work, we choose a thin metallic layer (~12nm) as a
proof of concept, as shown in Figure 2.1.
Figure 2.1 shows the basic device structure, which consists of an n-type silicon wafer, an aluminum
oxide insulator layer, and a thin gold layer. The entire device is encapsulated in an epoxy, leaving
only the top gold layer exposed, and is immersed in a 0.5 M H2SO4 solution cartoon schematic of
the band diagram is shown in Figure 2.1 b. MIS junctions enable injection of the highest energy
hot electrons compared to metal−insulator−metal tunnel (MIM) junctions, or
metal−semiconductor (MS) junctions. In MIM junctions, the large density of states around the
Fermi levels of the metals causes large currents to flow with relatively smaller applied biases,
limiting the energy at which hot electrons can be injected. For MS junctions, the offset between
the semiconductor conduction band and metal Fermi level is pinned at the interface, which causes
Figure 2.1 Proof of concept MIS device demonstrated for hot electron electrochemistry device.
Figure 2.1 Proof of concept MIS device demonstrated for hot electron electrochemistry device.
15
the hot electrons' injected energy to be fixed by the Schottky barrier height. In this device, as the
voltage across the MIS junction increases, there will be an increase in both the current and the
energy at which the hot electrons are injected. This behavior occurs due to the insulator layer
depinning the semiconductor conduction band from the metal Fermi level at the junction. Thus,
the MIS structure is expected to generate the hottest electrons in the metal when compared to MS
or MIM structures.
With this fabricated MIS structure, the electrochemical measurement was carried out using a
potentiostat with two working electrodes to apply independent bias voltages between the gold and
solution terminals (VAu-Solution) and the gold and silicon terminals (VAu-Si). We use a platinum wire
as a counter electrode in the solution and an Ag/AgCl reference electrode. More detailed
measurement setup can be found in the later part of this section.
16
To study the redox behavior of these devices, we carried out two types of ISolution measurements.
First, we sweep the voltage of the Au-Solution (VAu-Solution) junction and simultaneously step the
voltage of the Au-Silicon (VAu-Si) junction. Figures 2.2 a,b plot the linear and log scale results of
these measurements, respectively. From the linear scale plot (Fig. 2.2 a), as the voltage between
the Au-Silicon junction increases, the turn-on voltage for hydrogen reduction is reduced, and
current density increases. For an applied VAu-Solution = -1.5 V, the current increases from ~13
mA/cm2
to ~ 42 mA/cm2 when VAu-Si = 2 V. From the log-scale current plots, we can more clearly
see the reduction curves shift as the VAu-Si voltage is increased. This shift to lower voltages between
Figure 2.2 Linear sweep voltammetry (LSV) curves of 12nm Au MIS device. (a) Linear scale solution current density vs
applied Au-Solution voltage for varying Au-Si diode voltages and (b) log scale of (a). (c) Solution current density vs applied
Au-Si voltage for varying Au-Solution voltages and (d) log scale of (c). (e) Tafel relation for the low VAu-Si and (f) high VAu-Si.
a
b
c
d
10-6
10-5
10-4
10-3
10-2
10-1
100
101
JSolution (mA/cm
2
)
0.5 1.0 1.5
VAu-Si (V)
VAu-Solution = -0.2V
VAu-Solution = -0.4V
VAu-Solution = -0.6V
VAu-Solution = -0.8V
20
18
16
14
12
10
8
6
4
2
0
JSolution (mA/cm
2
)
0.5 1.0 1.5
VAu-Si (V)
VAu-Solution = -0.2V
VAu-Solution = -0.4V
VAu-Solution = -0.6V
VAu-Solution = -0.8V
Hot electron shift
50
45
40
35
30
25
20
15
10
5
0
JSolution (mA/cm
2
)
-1.0 0.0 1.0
VAu-Solution (V vs Ag/AgCl)
VAu-Si = 0V
VAu-Si = 0.5V
VAu-Si = 1.0V
VAu-Si = 1.5V
VAu-Si = 2.0V
Hot electron shift
10-6
10-5
10-4
10-3
10-2
10-1
100
101
JSolution (mA/cm
2
)
-1.0 0.0 1.0
VAu-Solution (V vs Ag/AgCl)
VAu-Si = 0V
VAu-Si = 0.5V
VAu-Si = 1.0V
VAu-Si = 1.5V
VAu-Si = 2.0V
e
f
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
Overpotential (η)
-5.0 -2.5 0.0
log j (mA/cm
2
)
VAu-Si = 0V
VAu-Si = 0.5V
127mV/dec
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
Overpotential (η)
-5.0 -2.5 0.0
log j (mA/cm
2
)
VAu-Si = 1.0V
VAu-Si = 1.5V
VAu-Si = 2.0V
i) 175mV/dec
ii) 190mV/dec
17
the gold and solution is attributed to the increased flux of electrons impinging on the gold solution
surface, caused by the injection of hot electrons into the gold from the Si. To understand the effect
of the Au-Si junction voltage, we have swept VAu-Si while stepping VAu-Sol. Figure 2.2 c shows the
results on a linear scale. In all cases of current vs VAu-Si, there is a turn-on voltage, which becomes
smaller as the VAu-Solution voltage is increased. This should occur as the higher voltage will change
both the concentration of [H+
] at the gold/solution interface, and modify the energy barrier. Figure
2d shows the same graphs on a log scale. At low diode voltages, the solution current is nearly
constant, limited by the thermal electrons in gold. Once VAu-Si becomes sufficiently large, we see
an exponential increase in the current until the linear regime shown in Figure 2c. The initial
exponential increase is attributed to the increase in energy of the electrons injected into gold.
Finally, there is a clear difference in the current levels at which the crossover from exponential to
linear occurs. These data show the electrochemical reaction rate on the gold surface dramatically
shifts due to the Au-Si junction.
To analyze the electrocatalytic activity and to elucidate the reaction mechanism of hot electron
devices, a Tafel analysis is introduced. In conventional electrochemistry, the Tafel equation is well
defined as:
(1) 𝜂 = 𝑎 + 𝑏 𝑙𝑜𝑔10𝐽𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛
where η is the overpotential, which is the difference between the electrode potential and the
standard electrode potential, 𝑎 =
2.303𝑅𝑇
𝛼𝐹
𝑙𝑜𝑔10(𝐽0
) ,where R=8.314 Jmol-1K-1
is the universal gas
constant, F= 96485.3 Cmol-1
is the Faraday constant, 𝐽0
is the exchange current density, α is the
phenomenological charge transfer coefficient and 𝑏 =
2.303𝑅𝑇
𝛼𝐹
is called the Tafel slope. For a single
18
electron transfer process, α is often found to be ~0.5 which leads the Tafel slope to be ~120
mV/dec40-42. It is noteworthy that the Tafel equation originates from the Butler-Volmer equation:
(2) 𝐽𝑆𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 𝐽0 ∗ (𝑒
−
αFη
RT − 𝑒
(1−α)Fη
RT )
where the second exponential term becomes negligible at large overpotential and reduces to the
simplified Tafel equation4, 5
. Figure 2.2 e,f shows the Tafel slopes of different regions of the
solution current density at different VAu-Si conditions. As shown in the Figure 2.2 e, when VAu-Si =
0 and 0.5V, which generates no or less hot electrons, the Tafel slope is ~127 mV/dec, which is
close to the often observed 120 mV/dec. This Tafel slope indicates that the hydrogen evolution
reaction happening at the electrode is predominantly limited by the single electron transfer step,
which is popularly known as the Volmer reaction step (H+ + e- = Hads)
4-6
. With increasingly
negative overpotential, Tafel slope starts increasing and the solution current density starts getting
saturated. This saturation can be attributed to a number of factors: (i) as the current increases, the
reaction gets limited by the mass transport to and from electrode4-6
, (ii) adsorption of reduced
hydrogen atoms at the electrode4-6
, and (iii) deviation from the conventional Tafel equation at
higher overpotentials. The charge transfer coefficient, α=0.5 is generally not applicable at higher
overpotentials when the change in the activation energy of the redox reaction with overpotential
starts becoming non-linear6
. Since our MIS device does not show any Tafel slope that is below
100 mV/dec, the reaction mechanism is not being limited by either the Heyrovsky step (H+ + Hads
+ e-= H2, Tafel slope of 40 mV/dec) or the Tafel step (Hads + Hads = H2, Tafel slope of 30 mV/dec)40-
42. When there is a large positive VAu-Si, as shown in the Figure 2f, we can see that there are two
different regions with different Tafel slopes. We observe a Tafel slope of i) ~175 mV/dec, and ii)
19
~190 mV/dec at lower and higher overpotentials respectively. While the Tafel equation works
reasonably for the lower VAu-Si case, it deviates from the ideal form for hot electron cases. This
deviation stems from the fact that the derivation of the Butler-Volmer equation considers electron
flow from the Fermi level of the electrode to the redox states. Since the hot electrons have
considerably higher energy than the Fermi level, the conventional Tafel slopes do not manifest
themselves in the higher VAu-Si cases. For high VAu-Si, we attribute the Tafel slope (~175 mV/dec)
at the lower overpotential to the hot electrons being transmitted to the redox states with
considerably larger transmission probability than the thermal electrons in gold. With the increasing
overpotential, the transmission probability of the hot electrons does not increase considerably
while the supply of the hot electrons remains constant which leads to a saturation of the current
followed by the first exponential increase. As the overpotential increases further, the thermal
electrons of gold also acquire a considerably large transmission probability and we can see the
second exponential increase in current with a different Tafel slope (~190 mV/dec). While
apparently it seems that the charge transfer efficiency (α~0.31) has decreased compared to the VAuSi = 0 case (α~0.47), it is noteworthy that the magnitude of current density increased considerably.
At this higher current density, the mass transport limitation, ohmic losses and adsorption will also
be higher which may collectively manifest as a larger Tafel slope.
To ensure that the observed currents do not result from any experimental artifact, we have carried
out a set of control experiments. One of the critical factors of exploring hot electron transfer
between the electrolyte and the electrode is the voltage drop across the electrode film. During the
hot electron transfer from Au electrode to the solution, hot electrons can lose their energy across
the surface region before counted to HER. Two possible factors are implied: the surface roughness
20
of the electrode and the shape of the contact. Figure 2.3.a shows the hot electron flow map of the
device. When the surface is not smooth enough, hot electrons lose their energy due to scattering
during the emission process. Furthermore, if contact is not uniform across the surface, they might
have different potentials in different regions along the surface. Silver paste rectangular ring shape
contact was used to reduce the voltage drop across the thin Au film in all the devices measured to
eliminate the non-uniform voltage distribution across the film. To verify the ring contact to the
device we fabricated, coincidence between the measurement of our device (red curve) and
simulation from a modeled device with Sentaurus (blue curve) of schottky I-V measurement was
presented in Fig 2.3 b. Inset image shows our fabricated device with ring contact on it. The
resistivity of different thickness of gold was measured by 4-probe measurement to use as an input
Figure 2.3 (a) Hot electron flow map across the device, showing hot electron go through along the Au surface resistance
depend on the conditions of the film. (b) Close fitting results of experiment and simulation schottky curves. (c) Sentaurus
electrostatic potential simulation with the silver ring contact modeled device. (d) Control device schematic (e) Microscope
image of Au film with holes. (f) Solution current measurement of control device.
21
parameter for Sentaurus simulation. Figure 2.3 c shows the Sentaurus simulation results of the
electrostatic potential distribution on the thin gold surface from ring contact to center of the
thin film. Difference of the highest electrostatic potential (0.3609V) to the lowest point (0.3547V)
is 0.0062V, which can be assumed as negligible voltage drop along the surface region. Larger
voltage drop might distract the hot electron directly accumulated to the reaction occurred in the
interface between Au film and electrolyte.
Controlling the surface roughness of thin Au film is also significant because of the sheet
resistance and the holes created due to discontinuity in the thin film. Conventional E-Beam
evaporated gold film has a rough surface with RMS ~4.4nm as measured with Atomic Force
Microscope (AFM) (Figure 2.4), which might be the main problem of increasing film resistivity.
In this work, thin gold films evaporated in the cryo stage (90K) were used for all the measured
Figure 2.4. AFM analysis of the 12nm Au film (a) 12nm Au film, showing the RMS ~0.78nm and (b) 12nm Au evaporated in
room temperature condition. RMS ~ 4.4nm shows more roughness surface of the Au film.
22
devices to reduce the surface roughness. Besides, to clarify the roughness of Au effects on the hot
electron injection, we modeled a control device which contains small holes with 1um radius with
a 30um pitch in thick gold. In Figure 2.3.e, different values of the current and the voltage were
applied to Au base region through VAu-Si (0mA,10mA, 0.71V,1.0V,1.5V,2.0V). Curve shifting
was not found in different conditions, which we can verify that there are no hot electron injections
directly from Si region through small holes, which represent the roughness of Au film. In all
different measured conditions, it shows no current change, which we can say that small holes in
thick gold do not contribute to the current by directly injected from the silicon side.
Finally, several types of control devices were designed and investigated to solidify the idea of hot
electron transfer. First, different thickness of Au base film and doping concentration of Si emitter
was made. Depend on the Au base thickness, two different types of transfer mechanism can be
found. When more current injected through Au- Si region (0, 1, 10mA) in 12nm Au base, we can
see the hot electron effect in the solution current. Unlike 12nm Au device, having thick Au did not
show the hot electron effect. Thicker Au base would lead to more considerable cooling of the hot
electrons before reaching the Au/electrolyte interface. Intuitively, as the Au thickness becomes
sufficiently large, all hot electrons will thermalize before reaching the Au/electrolyte interface;
thus, a thin Au layer is preferred for hot electron transfer.
23
The Au device work was introduced as a first demonstration work. This metallic layer was later
replaced with graphene in follow-up section due to i) the low electron−phonon coupling and
electron density when compared to metals and ii) the single layer physical structure. The lower
electron scattering rates are important in reducing the hot electron cooling pathways, and the single
layer structure enables every hot electron to be at the surface, maximizing the probability of driving
electrochemical reactions. So, we use a semiconductor-insulator-graphene junction to controllably
create a hot electron population via tunneling of electrons from the semiconductor conduction band
into the graphene layer and subsequently use the injected electron population to modulate the
electrochemical reaction rate between the graphene and an aqueous solution. More details on
device operation with current components will be presented as well.
Figure 2.5. Control devices band diagram and measurements. (a) Band diagram of MS HET with ~12nm Au, (b) with ~100nm
Au and (c) with heavily doped Si emitter. (d) Solution current result from device ‘a’, as injected current to base increased, it shows
hot electron effect. (e) from device ‘b’, showing no hot electron effect due to thick Au region, and f, from device ‘c’, no hot
electrons generated from emitter region, due to narrow barrier.
24
2.3 Hot electron electrochemistry - Graphene-Based Device
Figure 2.6 shows a schematic of the device structure which consists of a moderately doped ntype silicon wafer, an aluminum oxide insulator layer, and a graphene layer. The device is
encapsulated with the epoxy to ensure only the graphene is in contact with the solution. After
fabrication we carried out dry I-V measurements to observe the diode behavior of the SIG device.
Figure 2.7 a show the both linear and log scale plots of the device I-V characteristic. As shown in
the I-V curves, the diode shows two exponential regions, with different slopes, which can be
expected in a semiconductor-insulator-metal device, as the current may be limited by (i) injection
over the silicon depletion region barrier, (ii) tunneling through the oxide, or (iii) parasitics. Here,
the current appears to be limited by silicon injection between the voltage region of 0 V – 0.4 V,
and then appears to be tunneling limited between 0.4 V – 1.9 V. To ensure that the graphene was
successfully transferred onto device, we carried out Raman spectroscopy on multiple points on the
device surface. A representative Raman spectrum of graphene is shown in Figure 2.7 b with sharp
Figure 2.6 Schematic and Band diagram of device structure at the positively biased graphene-Si junction showing the
injection of hot electrons.
25
2D and G peaks labeled at 2680 cm-1
and 1580 cm-1
, respectively. The relative ratio of the
measured I2D/IG peak intensity is ~2, clearly identifying the monolayer graphene.
7
Figure 2.8 shows the schematic of the hot electron electrochemistry device measurement set up.
This potentiostat measurement setup uses two working electrodes to apply bias between the
Figure 2.8 Hot electron electrochemistry measurement set up to bias independent voltage to the system.
Figure 2.7 I-V measurement in both linear and log scale for GIS structure. Raman spectroscopy of graphene showing 2
different peaks.
26
graphene/silicon and graphene/solution, respectively. Thus, we have two sets of counter electrodes
(CE 1 & CE 2), working electrodes (WE 1 & WE 2), and reference electrodes (RE 1 & RE 2). In
a normal potentiostat, current flows between the working electrode and the counter electrode,
while the reference electrode is used to set the voltage with working electrode. First, to apply
voltage between the graphene and solution, which is the typical electrochemical measurement set
up, we connect WE 1 to the graphene, CE 1 to a platinum wire in the solution, and RE 1 to a 3M
Ag/AgCl. To apply voltage between the graphene and silicon at the same time, we connect the
silicon to WE 2, the graphene to RE 2, and the platinum wire to CE 2. This allows us to control
the two different voltages (VGraphene-Solution and VGraphene-Silicon) independently. By sharing the
platinum for both CE1 and CE2, we can get the all the current source occurring inside the system.
𝐼𝑊𝐸1 and 𝐼𝑊𝐸2
represent working electrode current in channel 1 and 2. 𝐼𝐶𝐸1 and 𝐼𝐶𝐸2
indicate
counter electrode current in channel 1 and 2, which are connected in series to a Keithly Multimeter
to measure the total solution current more precisely since the current directly coming from
potentiostat has low resolution.
27
By using this setup, we studied the redox behavior of graphene devices. Here, we carried out two
types of ISolution measurements. The measured potentials here are rescaled to the RHE by using the
equation ERHE = EAg/AgCl + 0.197V + 0.0592V*pH. First, we carry our linear sweep voltammetry
(LSV) of the Graphene-Solution (VGraphene-Solution) junction while simultaneously stepping the
voltage of the Graphene-Silicon (VGraphene-Si) junction from 0V to 2V with 0.5V steps. Figures 2.2.5
(a) shows the plots of the LSV. As the voltage between the Graphene-Silicon junction increases,
the turn-on voltage for HER is reduced, and the current density at a given applied voltage increases.
Particularly interesting is the cases of VGraphene-Si =1.5 and 2.0 V. We see dramatic increases in the
current, with the largest currents observed >~100 mA/cm2
. Figure 2.9 (b) on the other hand shows
the plot of LSV of the Graphene-Silicon voltage while stepping with a fixed voltage across the
Graphene-Solution junction.
Figure 2.9 (a) Linear scale solution current density vs applied Graphene-Solution voltage for varying Graphene-Si diode
voltages and (b) Solution current density vs applied Graphene-Si voltage for stepping Graphene-Solution voltages.
28
To analyze the source of this result from the device, we carried out the identical experiment with
the device which does not have graphene on top of the insulator layer. Figure 2.10 (a) shows the
solution current density vs Graphene-Solution voltage. Comparing the same amount of voltage,
VWE-Si = 2V biased condition, which the working electrode represent graphene for the first device
and aluminum oxide for the second device, the no-graphene device shows less current with
~5mA/cm2
at potential (V vs RHE) = - 0.3V, while the graphene device shows ~80mA/cm2
, for
which the relative ratio is ~18. In addition, we measured the HER in same electrolyte by using
both platinum and palladium electrode, which are excellent electrocatalysts due to their near ideal
positions on the volcano plots. Figure 2.10 (b) shows the measured current density of platinum and
palladium electrodes evaporated on top of the insulator layer as well. At VGraphene-Si = 2.0V, this is
noteworthy that none of the previous works have presented higher value than platinum in
Figure 2.10 (a) Solution current density comparison with the no-graphene device. (b) Solution current density of Pt and Pd at
the same scale of current density.
29
both turn on voltage and current density at same voltage vs the reference electrode. The current
density is ~2 times and ~4 times higher than the platinum and palladium, respectively.
To deeply understand the behavior of the device, we tracked the current components that allow the
graphene to have high currents by studying each of the three measured current components (ISolution,
IGraphene, ISi) from the potentiostat system. Figure 2.11 shows the schematic of the measured current
components, and the internal current components which compose them. The source of hot
electrons in the graphene is the injection of electrons from the silicon conduction band tunneling
through the oxide layer. In our measurement, the total redox current is measured through the ISolution
current component. The platinum counter electrode is shared by two working electrodes (Graphene
and Silicon), the total current can be measured by collecting all the current components flow into
Pt counter electrode. The electrochemical reduction current on the graphene is separated into three
components, reduction due to the thermal electron population of graphene itself, IThermal Electron,
reduction due to the hot-electron population, IHot Electron, and a direct electrochemical reduction
Figure 2.11 Schematic of current components flowing inside the system. Major currents (i.e. ISi, IGraphene, and ISolution ) are
composed with different minor current components. Measurement of three major currents of the closed system, under
different Graphene-Si voltages.
30
component from the silicon to the solution, IDirect Injection, which is the most significant factor in
this work. These correspond to the measured components from the following relationships.
ISolution = -(IGraphene + ISilicon) (1)
IGraphene = IThermal Electron + IHot Electron – IGraphene-Si (2)
ISi = IGraphene-Si + IDirect Injection (3)
From these relationships, we can see that when VGraphene-Si = 0 V, IGraphene-Si = 0 A, since none of
the electron is tunneling from silicon conduction band. This shows the traditional 3-electrode
measurement where the graphene is the working electrode, and all the total solution component
comes from thermal electrons of graphene, which refers to the ISolution = -IGraphene
The first ever introduced graphene based hot electron electrochemistry device shows the great
performance on HER. However, the catalytic properties of graphene are limited by the large
hydrogen adsorption energy and lack of electrochemically active sites. To address this limitation,
Figure 2.12 (a) Schematic of the procedure of plasma etching of graphene (b) Raman spectroscopy of PG and EG transferred
on top of Al2O3/silicon
31
we have investigated a n-silicon/insulator/plasma etched graphene (SIEG) device where a short
dry etch process is used to dramatically increase the number of active sites on the graphene surface
by creating a greater number of active edge sites per unit area.
8 This increases hydrogen adsorption
at a given potential. Previously, this has been shown to improve the properties of devices with cold
electrons. However, by applying this material modification to the hot electron chemistry device, it
improves the device performance. The improved result is not included in this thesis, can be found
in the peer reviewed journal paper.9
32
References
1. C.-K. Sun, F. Vallée, L. Acioli, E. Ippen, J. Fujimoto, Femtosecond-tunable measurement
of electron thermalization in gold. Physical Review B 50, 15337 (1994).
2. C. Guo, G. Rodriguez, A. J. Taylor, Ultrafast dynamics of electron thermalization in gold.
Physical review letters 86, 1638 (2001).
3. N. C. Brandt, E. L. Keller, R. R. Frontiera, Ultrafast surface-enhanced Raman probing of
the role of hot electrons in plasmon-driven chemistry. The journal of physical chemistry
letters 7, 3179-3185 (2016).
4. T. Shinagawa, A. T. Garcia-Esparza, K. Takanabe, Insight on Tafel slopes from a
microkinetic analysis of aqueous electrocatalysis for energy conversion. Scientific reports
5, 13801 (2015).
5. S. Fletcher, Tafel slopes from first principles. Journal of Solid State Electrochemistry 13,
537-549 (2009).
6. D. Vanmaekelbergh, Electron Transfer at electrodes and Interfaces. Electron Transfer in
Chemistry, 126-188 (2001).
7. A. Eckmann et al., Probing the nature of defects in graphene by Raman spectroscopy. Nano
letters 12, 3925-3930 (2012).
8. L. G. Cançado et al., Quantifying defects in graphene via Raman spectroscopy at different
excitation energies. Nano letters 11, 3190-3196 (2011).
9. H. U. Chae, R. Ahsan, J. Tao, S. B. Cronin, R. Kapadia, Increasing the Hot‐Electron Driven
Hydrogen Evolution Reaction Rate on a Metal‐Free Graphene Electrode. Advanced
Materials Interfaces 8, 2001706 (2021).
33
Chapter 3. Next-Generation Photoemission Device
3.1 Introduction
Electron emission cathodes are used in a wide variety of applications, including but not limited
to, electron microscopes, electron beam lithography, free electron lasers, and displays.1-4 For the
electron emission to happen, there are multiple pathways to emit out the electrons from the emitting
surface. Figure 3.1 shows the different types of emission processes. Thermionic/Photoemission
does not require much of an electric field through the vacuum since the electrons already gain
enough energy to tunnel through the vacuum barrier.
If they do not have enough energy to tunnel through the vacuum barrier, they might need enough
electric field which helps to tunnel the barrier. Lastly, a pure field emission can pull out the thermal
Figure 3.1 Electron emission processes
34
electrons from the emitting surface by applying a high electric field. Different approaches to pull
out the electrons can be used in different fields based on their purpose; however, field emission
and thermal emission have significant drawbacks. To excite the electrons from the equilibrium
states, they either need thermal energy (heat) or high electric field (electrical) to emit out the
electrons from the emitting surface. These robust conditions might degrade the emitter, ends up
reducing the efficiency and longevity of the emitters. Photoemission, on the other hand, as it uses
photon energy as an energy source for the electrons, does not require any robust
condition to generate the non-equilibrium electrons. There are several factors to check while
designing a photo emitter: i) Rapid response time to incoming photons, ii) having low mean
transverse energy, and iii) the quantum efficiency of the device. To satisfy all these requirements,
GaAs based negative electron affinity device was introduced and widely studied. GaAs
photoemitter works by cesiating the GaAs surface to create the dipole at the GaAs surface. When
the electrons get excited to the GaAs conduction band, it will come out to vacuum level as the
band diagram shows in the Fig 3.2. This approach does not require any high electric field to drag
out the electrons from the emitter surface and use light as an input source. Since the photoexcited
Figure 3.2 Band diagram of negative electron affinity photoemitter with GaAs wafer, HELAC device fabricated with silicon
and graphene: Band diagram of HELAC device.
35
at the GaAs surface already high energy compared to the vacuum energy level thanks to the
cesiated surface. This effect is called as “Negative electron affinity” since the energy level of
vacuum is already lower than the emitter surface.
5 Here, in this thesis, we introduce two different
types of photoemission devices realized by integrating device physics and nanofabrication.
Waveguide-integrated photoemission realizes the absorption of photons by the absorber films
through evanescent coupling. It can initiate new photoemission mechanisms, leading to brighter
electron beams and enabling unprecedented shaping of emitted electrons. In addition, a properly
designed hot electron device composed of a graphene-insulator-semiconductor device, which is
air-stable and has a simple fabrication process while retaining NEA photocathodes' advantages,
will be introduced.
3.2 Photoemission through GIS Structure
We have utilized a similar device structure, which was used for electrochemistry by using the hot
electrons in the previous section for photoemission. Instead of using the hot electrons to derive the
chemical reaction, this device can be used to collect the hot electrons through a vacuum space.
Compared to GaAs based photoemitter, this device is easy to fabricate, and stable but using this
negative electron affinity behavior. Here, we named this device used in the photoemission as hot
36
electron laser assisted cathode, which called as HELAC. Detail fabrication steps and device
operations are listed below. Unlike the hot electron device demonstrated for the electrochemistry
work, HELAC device require the p-type silicon wafer as an ‘electron source’ to collect the minority
carrier generated from the light source. The device is a three-layer stack of (i) a semiconductor,
which absorbs incident photons, (ii) a monolayer of graphene, which acts as the gate, and (iii) an
insulator, which allows a voltage drop between the semiconductor and graphene. Moderately
doped p-type silicon wafer was used as a substrate, followed by depositing 10nm SiO2 as a tunnel
oxide with PECVD and deposit top contact and transfer the chemical vapor deposition (CVD)
grown graphene. Ti/Au was used as a top contact layer and Ti/Pd is deposited at the backside of
wafer as an ohmic contact for p type silicon. With this device structure, when the voltage is applied
between the semiconductor and graphene, it creates an electric field which. Figure 3.3 shows a
band diagram simulated with TCAD Sentaurus, at the semiconductor-insulator-graphene junction.
When a small amount of bias is applied across the junction, electrons from the silicon conduction
band will tunnel through the oxide barrier and inject into the graphene with energies close to the
Figure 3.3 Simulated band diagram of SIG device under the non-biased condition and 3 V biased across the graphene-silicon
junction.
-4
-2
0
2
Energy (eV)
49.96 49.97 49.98 49.99 50.00 50.01
x (µm)
VGr-Si = 0V
-6
-4
-2
0
2
Energy (eV)
49.96 49.97 49.98 49.99 50.00 50.01
x (µm)
VGr-Si = 3V
37
Fermi level. These will be collected as current from the graphene contact. However, when 3 V is
applied across the device, as the right figure shows the electrons injected into the graphene will
have energy significantly greater than the Fermi level. As more bias is applied to the junction, the
injected electrons will have energy greater than the graphene workfunction and will be emitted
into vacuum. This is like the effect of a negative electron affinity coating, such as cesiation of a
GaAs, but is completely air stable and electrically tunable. To operate these devices, a bias will
first be applied across the semiconductor-graphene junction, and then a pulsed laser will modulate
the emitted electron beam. As Figure 3.4 shows, to collect the emitted-out electrons from the
HELAC device we need two independent voltage tuning. To bias the semiconductor-graphene
junction, we need VGr-Si to be applied. Simultaneously, the VAnode is applied on top of the HELAC
device to create an electric field to drag out the electrons from the emitting surface. As more biased,
the injected electrons will have greater energy than graphene workfunction. To measure this device,
we used 635nm CW laser to excite the electrons inside the HELAC device. To measure the
emission current, we have built the set up to bias the two different terminals separately. Here the
applied electric field is only 8V/mm, low that cannot drive any field emission from the graphene.
Figure 3.4 HELAC device measurement set up
38
And while anode voltage is fixed, we sweep the diode voltage to see the generated hot electrons
contributing to the emission current. Here the result shows that different measurements from
different devices. Figure 3.5 (a) shows the photoemission current from 5 different set of devices.
All the devices have uniform performance, showing the maximum emission current at ~10 uA.
One noticeable part in the device is that it does not emit out any electrons below the threshold
voltage which is around ~78V. However, once VGr-Si > 8 V, we begin to see emitted current, despite
there being no change in the anode-cathode voltage. This is analogous to shining a laser on a
cesiated GaAs surface, resulting in photoemission of carriers.
Figure 3.5 (b) presents the time-dependent photoemission current measurement for different VGrSi demonstrating the on-off of the photoemission in light and dark, respectively. Conspicuously,
the photoemission current increases with increasing bias voltage between silicon and graphene.
Figure 3.5 Emission current with graphene-silicon voltage sweep, I-V and I-t measurement
39
3.3 Photoemission through waveguide integrated device
In this subsection, another type of device is used to enable the highly efficient photoemission. In
the previous device, the light was shone on top of the device, where we lost a large portion of
power through reflection at the top surface and were limited by the absorption length of the
semiconductor. Here, the waveguide-integrated photoemission device will be introduced to absorb
the light coupled into the device fully, and the absorber material on top of it can absorb and emit
the electrons. The schematic in Figure 3.6a illustrates the fabrication process of the integrated
photocathode. Stoichiometric Si3N4 was deposited on a SiO2/Si substrate by low-pressure chemical
vapor deposition (LPCVD) to create a low-loss waveguide. The waveguide is approximately 1 mm
in length, 400 nm in thickness, and has a variable width between 1-100 μm. Electron beam
lithography was used to pattern the grating coupler and waveguide structure, while reactive ion
etching (RIE) was used to etch the Si3N4. Figure 3.6 b shows the finite difference time domain
(FDTD) result of the transmission profile at the end of the waveguide at different wavelengths.
We designed and determined the final grating coupler design by selecting the highest transmission
wavelength. Figure 3.6 c shows the scanning electron microscope (SEM) images of the fabricated
grating coupler with the waveguide. Then, a thin layer of Cs3Sb was deposited on the waveguide,
creating a Si/SiO2/Si3N4/Cs3Sb/vacuum structure. Figure 3.6 d shows the quantum efficiency (QE)
of Cs3Sb over the growth time. The growth was stopped at ~1% QE, giving us a ~20 nm film. A
polarized femtosecond pulsed laser beam was illuminated on top of the grating coupler to couple
the desired wavelength into the integrated structure. The beam diameter is approximately 100 μm.
40
Photoemission electron microscopy (PEEM) was employed to image the surface of the
photocathode while light was illuminated into the grating coupler. Figure 3.7 displays PEEM
images illustrating confinement at various coupling wavelengths. The grating coupler was
designed to couple with the 532 nm wavelength. The images reveal the generation of transverse
patterns along the waveguide's length. Notably, the pattern's period increases when transitioning
from 𝜆 = 520 nm to 𝜆 = 538 nm. Interestingly, the beating pattern appears while the modes are
confined within the waveguide. The period of the beating pattern increases from 100 𝜇m to 250
𝜇m and disappears when the wavelength is out of range, where the grating coupler cannot support
any modes in the waveguide. The beating patterns possibly originate from the interference of
different modes propagating with slightly different wavevectors. For two modes with wavevectors
β1 and β2, the interfered wave will have an envelope of wavevector |β1- β2|/2. This gives a spatial
Figure. 3.6 (a) Schematic of the fabrication process of integrated photonics cathode (b) Lumerical FDTD simulation of
transmission of 532 nm beam across the grating coupler and waveguide (c) SEM images of fabricated grating coupler and
waveguide. (d) Quantum efficiency of Cs3Sb along growth time.
41
periodicity of 4𝜋/(|β1-β2|). Further theoretical investigation is underway to deeply understand these
transverse patterns along the length of the waveguide.
In the previous section, we demonstrated the feasibility of light coupling into the grating coupler
and waveguide to emit electrons in a confined structure. Employing the same approach, we
designed the integrated structure as a splitting waveguide with various widths to divide the coupled
light into different branches. Figure 3.8a shows optical microscope images of the fabricated
splitting waveguide structure. Using the same experimental setup, PEEM images reveal
photoemission confined only to the waveguide regions. Second waveguides are split from the main
waveguide with widths of 1, 2, 5, 10, and 20 𝜇m. This result shows a unique method of
photoemission where the shape of the beam can be controlled by the designed integrated
photocathodes. Though we only show the results of line-shaped photoemission in this study, these
findings demonstrate the potential of this work, illustrating the versatility of shaping
photoemission beams.
Figure 3.7 PEEM image showing confined emission from Cs3Sb photocathode at (a) 𝜆 = 520 nm, (b) 𝜆 = 528 nm, (c) 𝜆 =
532 nm, (d) 𝜆 = 538 nm.
42
3.4 Summary
Two different photoemission devices have been introduced: i) HELAC device composed of
graphene-insulator-semiconductor structure and ii) integrated photonics device combining
dielectric waveguide with a thin layer of semiconductor layer as a light absorber. Designing a
proper device is key to efficiently collecting electrons. These demonstrations establish the proof
of principle feasibility for tailored emission from photonics-integrated photocathodes. Moreover,
an interesting physical phenomenon was found, showing a beating pattern originating from the
interference of two different modes. In addition, splitting waveguides in various widths shows the
ability to shape emitted electrons transversely along the waveguide's length. These findings could
mark an initial stride toward technologically advanced photocathodes characterized by a new way
of interacting light into the integrated photocathodes and the novel approach to control
photoemission.
Figure 3.8 (a) Optical microscope images of splitting waveguide structure (b) PEEM images of splitting waveguide
43
References
1. T. Yoshikawa et al. (Google Patents, 1999).
2. W. Lei et al., A graphene-based large area surface-conduction electron emission display.
Carbon 56, 255-263 (2013).
3. A. Kojima, H. Ohyi, N. Koshida, Sub-50 nm resolution surface electron emission
lithography using nano-Si ballistic electron emitter. Journal of Vacuum Science &
Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and
Phenomena 26, 2064-2068 (2008).
4. G. H. Fecher, O. Schmidt, Y. Hwu, G. Schönhense, Multiphoton photoemission electron
microscopy using femtosecond laser radiation. Journal of electron spectroscopy and
related phenomena 126, 77-87 (2002).
5. J. van der Weide et al., Negative-electron-affinity effects on the diamond (100) surface.
Physical Review B 50, 5803 (1994).
44
Chapter 4. III-V Integrated Metasurface in Mid-IR
4.1 Introduction
A new approach recently introduced as a potential candidate for heterogeneous material
integration on Si back-end dielectrics and metals that simultaneously addresses the cost, scalability,
and material quality issue is the templated liquid phase (TLP) growth. It has been demonstrated
that single crystals of compound semiconductors can be non-epitaxially directly grown on multiple
amorphous substrates in deterministic geometries and locations by the TLP approach.1-3 Even
though the TLP approach has been proposed as an outstanding option for heterogeneous III-V
semiconductors integration, there are several constraints that need to be solved. Those challenges
include:
a. Smaller grain size: Dimensions of single crystalline mesa grown by previously reported
TLP method were generally smaller than 10 m. To design and build device level
integration, it’s typically required to synthesis high uniform template with dimensions
larger than 100 m for different kinds of applications.
b. By patterning the initial group III metals, it is possible to form single crystalline ‘mesas’
of III-V with arbitrary controlled shapes on SiO2 surfaces. However, all the mesas across
the wafer have independent orientations, which is not desirable for high performance
electronic or photonic circuitry due to transport, optical and band structure variation from
mesa to mesa.
45
In this section, the results for solving the issues above are demonstrated. Large crystalline III-V
growth was introduced on top of a metallic substrate. Specifically, we demonstrate an InAs-based
thermal metasurface for the mid-infrared range. Metasurface design was carried out using direct
growth of InAs on metal. We characterize the infrared reflectivity (absorptivity) of the metasurface
across a broad range of wavelengths from 2-15 microns. These experimental results present a
possibility upon which a carrier-injection-based tunable infrared emission and absorption using
the proposed structure. The top and the bottom metal layer in our designed grating can potentially
be utilized as electrical contacts for carrier injection and in the future, the InAs dielectric layer can
be doped to support a p-i-n structure.
4.2 TLP III-V Growth on Metal for Steady-State Metasurface
Direct growth of single crystal III-V thin film on top of metal has been desired to design a
different type of optoelectronics and photonics devices like dynamic tuning photonics devices such
as metal-semiconductor-metal (MSM) resonator, where the top metal layer is defined into a subwavelength resonator element and bottom metal layer as a reflector. In previous research, heavily
doped layer was used to mimic the metal layer by using either metal-organic chemical vapor
deposition (MOCVD) or molecular beam epitaxy (MBE), which is not only cost-inefficient but
has poor reflectivity.
34 Here in this work, we have demonstrated III-V directly grown on metal,
specifically on top of Mo and W to build a platform for the device application. The growth was
carried at a growth temperature of 300°C by low temperature templated liquid phase (LT-TLP)
method. Unlike our previous grown templates on top of amorphous substrates, it is noteworthy
that the size of the grown InAs area is over > 50 μm domain size with various InAs thickness (from
~100 nm up to μm scale) by tuning the initial indium template thickness. This approach enables
46
us to control the size of the grown crystalline, which potentially can be used to grow single
crystalline size up to mm scale by optimizing the growth conditions and processes, opening the
new door to breakthrough the large area III-V thin film growth for device application.
Figure 4.1 schematically illustrates the III-V material growth process, which uses low temperature
templated liquid phase (LT-TLP) growth. The detail process flow of LT-TLP will be shown in the
later part of this section. Indium (In) mesas capped by silicon dioxide (SiO2), in the shape of
desired templates, are fabricated using conventional lithography, evaporation, and lift-off on a
heavily doped n-type Si carrier wafer, with a 200 nm layer of sputtered molybdenum (Mo) or
tungsten (W). Here, the molybdenum and tungsten were selected as the bottom mirror layer due to
the wetting of indium on their surfaces as well as the low solubility in indium at the growth
temperatures.4 To realize high-quality and smooth growth of InAs, the evaporated indium film
confined between the top and bottom capping layer must be thermodynamically stable at a given
temperature, otherwise the liquid indium layer dewets. Previous studies have established a growth
Figure 4.1 Schematic of LT-TLP growth of InAs on top of metal on Si and device fabrication process.
47
model that illustrates the relationship between the critical template size and the surface energies of
top and bottom layers.3 Based on this model and subsequent experiments, there is a critical
template size above which the indium cannot sustain its shape inside the designed cavity on
amorphous substrates. Figure 4.2 (a) briefly shows the schematic of liquid indium confined by top
capping layer and bottom metal substrate. Liquid indium confined without forming any voids can
be determined by several parameters such as size of template (R), height of evaporated indium (h),
surface energy between top capping layer and indium (𝛾𝑡𝑙), and bottom substrate and indium (𝛾𝑏𝑙).
This template can be simply modeled as a cylindrical shape, where free energy of liquid indium
confinement is:
𝐹𝐶𝑜𝑛𝑓𝑖𝑛𝑒𝑚𝑒𝑛𝑡 = 𝜋𝑅
2
(𝛾𝑡𝑙 + 𝛾𝑏𝑙) + 2𝜋𝑅ℎ𝛾𝑙𝑣
where the first term on the right hand side represents the energetic contribution from top capping
layer-liquid indium interface and bottom capping layer – liquid indium interface, with having area
of 𝜋𝑅
2
at both sides. The second term represents the contribution from the liquid indium-vapor
interface, which has area of 2𝜋𝑅ℎ, where 𝛾𝑙𝑣 is surface energy between liquid indium - peripheral
Figure 4.2 (a) Schematic of liquid indium confined between top capping layer and bottom metal. (b) Reflection and
surface energy from different metals.
48
vapor interface. Given that all other parameters are constant here, to maximize the free energy of
confinement, choosing the proper metallic substrate (higher 𝛾𝑏𝑙) plays an important role in the
growth of these devices. To satisfy both growth and device constraints, the chosen metal should
(i) have minimal solubility in indium at the growth temperatures, (ii) have the appropriate surface
energy, and (iii) have good reflectivity for the target wavelength range. Mo and W meet the growth
constraints and exhibit reasonable reflectivity in the desired range, while Au shows excellent
reflectivity but does not satisfy the other two constraints. Figure 4.2 (b) shows the comparison for
surface energy and reflectivity of Au, Mo, and W. Here, Mo (3.8 J/m2
) and W (4.6 J/m2
) have the
highest surface energies, enabling the confinement of indium inside the mesa without dewetting,
allowing formation of a high-quality InAs film with large crystalline area without forming any
voids.
5 On the other hand, Au (1.28 J/m2), which has a lower surface energy compared to other
two metals is not as effective in preventing dewetting of the liquid indium at our target template
size and height. Additionally, the mixing of Au and In at the growth temperatures cause
incorporation of gold into the grown material, which dramatically reduces material quality.
Figure. 4.3 Schematic of low temperature templated liquid phase growth
49
Figure 4.3 shows the schematic of low temperature TLP growth system. InAs growth is carried
out by heating the SiO2/indium/tungsten stack in a dual-zone tube furnace. The sample is placed
in lower temperature (300 oC) zone, while precursor gas first flows through a high temperature
cracking zone and then reacts with the growth substrate at lower temperature zone. After the first
nucleation occurs within the indium template, the balance between the growth rate at that
temperature and the nucleation rate determined by group V flux and diffusion of the group V
species in liquid group III metal leads to formation of the first nucleus. Once the first nucleus is
formed, diffusion of dissolved As to the growing nucleus suppresses additional nucleation events
in the same mesa. Thus, the entire group III metal mesa is transformed into a single crystalline III–
V semiconductor, retaining the same geometry as the deposited metal In. The low growth
temperatures used here are compatible with back-end CMOS integration, which ultimately enable
integration with control electronic.
6
Controlling the thickness of the grown III-V layer is critical for designing and tuning the optical
modes that are present in the final devices. Since the thickness of the film from conventional
growth technique is determined by the time of the growth and flow of the precursors. Here, in LTFigure 4.4 FT-IR reflection result from different InAs thickness
50
TLP growth, by modifying the thickness of the initially deposited indium, the thickness of the
resulting InAs mesa is controlled. To verify the film thickness, cross-sections of the grown films
were created and inspected using a focused ion beam scanning electron microscope (FIB-SEM).
Next, reflectivity of the InAs-metal stack was measured using Fourier Transform Infrared
Spectroscopy (FT-IR). The InAs layer forms a Fabry-Perot cavity, with the metallic layer serving
as a bottom mirror, and the InAs-air interface as the top mirror. As shown in Fig. 4.4, thicker InAs
results shifts the fundamental mode to longer wavelengths.
Figure 4.5 (a) shows the scanning electron microscope (SEM) images of a top view of the grown
TLP InAs mesa on top of W. Grown size of InAs mesa is ~2500 m2
(scale bar 10m). To
characterize the grown InAs, a cross-section was created using FIB-SEM and then Transmission
Kikuchi Diffraction (TKD) patterns of the material along the entire length of the cross section were
obtained. An inverse pole figure in the z-direction (IPF), illustrates that the grown InAs is single
crystalline with a pair of 60°
twin boundaries.
Figure 4.5 (a) Top SEM images of fabricated InAs MSM metasurface, cross bar 10 m, (b) Cross section SEM images along
with TKD pattern showing
51
In addition, energy dispersive spectroscopy (EDS) was conducted to verify the composition of
our grown sample. As we grow III-V semiconductor on top of tungsten, we can see tungsten signal
from the bottom of the grown InAs. Top tungsten signal was captured due to the deposition to
prepare a Lamella in FIB-SEM. Optoelectronic characterization of the TLP-grown InAs layer was
carried out by performing Raman spectrum analysis. Fig. 4.6 (b) shows the Raman spectrum of
TLP-grown InAs, overlapped with that of an undoped, InAs single-crystalline wafer as a reference.
The transverse (TO) mode and longitudinal (LO) mode peaks are observed at 218.4 cm-1 and 239.5
cm-1
. These two peaks are consistent with other published data.7
Figure 4.6 (a) EDS Polarization, cross bar 500 nm, (b) Raman spectroscopy of TLP InAs and bulk InAs wafer.
52
Experimental devices are fabricated to determine the grown InAs/W template can be used as a
photonics device platform. Figure 4.7 (a) shows a schematic, optical microscope image, and SEM
image of the MSM device. An Au metal grating is fabricated by using electron beam lithography
for pattern definition, followed by 5nm Ti/50nm Au electron beam deposition and lift off. The
device shown in the optical microscope and SEM image has a 600 nm grating width and 1.5 um
grating pitch. Figure 4.7 (b) shows the measured reflection FT-IR results. We measured reflection
spectrum instead of showing the direct emission measurement from the fabricated metasurface.
Since reflectivity (R) and transmissivity (T) are directly related to absorptivity (α) by α = 1 -R - T,
and these structures are opaque, T = 0 and reflectivity measurements are directly related to
absorptivity.8
Based on Kirchhoff’s law of thermal radiation emissivity and absorptivity are
equal.
9 Therefore, MSM structures presented here acts as wavelength selective thermal
emitters/absorbers at the measurement temperatures. Future experiments at elevated temperatures
Figure 4.7 (a) Schematic of MSM cavity with optical microscope and SEM images. Cross bar 3 m and 1 m, respectively.
(b) Reflectivity measurement taken by FT-IR with different grating widths.
53
can be used to elucidate the effect of changing semiconductor properties on the
emission/absorption spectrum. The reflection spectrum shows several valleys, which shift to
higher wavelengths as the grating width is increased from 600nm to 1m. Based on the grating
width, different spectral features can be created at w=600nm = 7.1m, w=800nm = 8.5m, and w=1m
= 10.05m, respectively. We demonstrated that the mid-wave infrared resonances shift with
geometrical tuning of the grating width. For the devices studied in this work, we have shown the
geometrical tuning of the metasurface only, however, in future work, incorporation of electrical
tuning of the refractive index in the InAs layer may be used to provide dynamic control over
absorptivity and emissivity.
4.3 Summary
In conclusion, we demonstrate a direct, III-V growth technique on metal to build meta-surfaces
with tunable absorption/emission spectra in the infrared regime. It is shown that the thickness of
the grown film can be precisely controlled, which, in turn, allowing the tuning of Fabry-Perot
resonances. Metallic strips were fabricated on top of the grown, InAs semiconductor layer to create
an MSM resonance. We demonstrated that the midwave infrared resonances shift with geometrical
tuning of the grating width. For the devices studied in this work, the transmission through the
device is zero due to the metallic back mirror, linking absorption and emission. In future work,
incorporation of electrical tuning of the refractive index in the InAs layer may be used to provide
dynamic control over absorptivity and emissivity.
54
References
1. R. Kapadia et al., A direct thin-film path towards low-cost large-area III-V photovoltaics.
Scientific reports 3, 1-7 (2013).
2. K. Chen et al., Direct growth of single-crystalline III–V semiconductors on amorphous
substrates. Nature communications 7, 1-6 (2016).
3. D. Sarkar et al., Confined liquid-phase growth of crystalline compound semiconductors on
any substrate. ACS nano 12, 5158-5167 (2018).
4. J. Park et al., Dynamic thermal emission control with InAs-based plasmonic metasurfaces.
Science advances 4, eaat3163 (2018).
5. C. E. T. White, H. Okamoto, Phase Diagrams of Indium Alloys and Their Engineering
Applications. (Indium Corporation of America, 1992).
6. L. Vitos, A. Ruban, H. L. Skriver, J. Kollár, The surface energy of metals. Surface science
411, 186-202 (1998).
7. D. Sarkar et al., Low Temperature Growth of Crystalline Semiconductors on Nonepitaxial
Substrates. Advanced Materials Interfaces 7, 1902191 (2020).
8. T. Li et al., Effect of growth temperature on the morphology and phonon properties of InAs
nanowires on Si substrates. Nanoscale research letters 6, 1-7 (2011).
9. J. R. Howell, M. P. Mengüç, K. Daun, R. Siegel, Thermal radiation heat transfer. (CRC
press, 2020).
55
Chapter 5. Epitaxial Transfer of III-V on Metal for Electrically
Tunable Metasurface
5.1 Introduction
In the previous section, we discussed one way of fabricating steady-state metasurface through
III-V TLP growth on a metallic substrate. In this section, we use an epitaxial transfer approach to
transfer the semiconductor on a highly reflective metal surface, analogous to approaches used for
photovoltaic and optoelectronic devices. The epitaxial transfer is a cost-effective way to integrate
the III-V on top of the target substrate. Unlike direct growth introduced in the previous section, it
can create different junctions, which can be used as electrically tunable metasurfaces by injecting
a carrier. Several material systems and tuning mechanisms have been explored including phase
change materials, 2D materials, insulator-to-metal phase transitions, thermo-optic effects, thermal
or optical free-carrier effects, liquid crystal-based tuning, and MEMS-based tuning1-5
. While
thermally driven tuning, such as in phase change materials and metal-insulator transitions, is large,
the low switching speed limits its use in high-speed applications. Here, along with the experimental
data, we carried out both optical and electrical device simulations to quantify the electron injection
and resulting optical effects.
6-8 Epitaxial Transfer of GaAs p-i-n junction on Metallic substrate
Figure 5.1 shows the overall device fabrication of electrically tunable metasurfaces through GaAs
p-i-n diode. The semiconductor layer comprises a GaAs p-i-n junction, which is cultivated using
Metal Organic Chemical Vapor Deposition (MOCVD). This junction is engineered to facilitate
refractive index adjustment by injecting free carriers. The heavily doped n++ (n = 1 ×1019 cm-3
)
and p++ (p = 1 ×1019 cm-3
) layers form the p-n junction and reduce contact resistance. This GaAs
p-i-n layer is grown on top of an AlAs sacrificial layer on a standard 2-inch GaAs wafer (AXT Inc,
56
(100) orientation, semi-insulating). Subsequently, conventional epitaxial liftoff (ELO) is utilized
to transfer the tuning layer onto the metallic layer. Preserving the quality of the GaAs epitaxial
layer during transfer is imperative, as surface roughness can lead to optical loss and significantly
impact mode confinement. To address this concern, the transfer is facilitated using Apiezon wax
as a carrier.
An inadequate transfer process risks harming the GaAs epitaxial layer, potentially caused by
pressure, temperature, or insufficient drying time. Such damage could compromise the quality of
the manufactured metasurface. To mitigate this risk, we ensure the GaAs transfer onto the metallic
Figure 5.1 (a) Schematic of epitaxial transfer towards electrically tunable metasurface fabrication. (b) False color SEM
images of MSM stack. (c) Photoluminescent measurement from transferred GaAs layer. (d) XRD of transferred GaAs film.
57
layer was conducted with consistent and adequate pressure. This was achieved by utilizing a
Tungsten cube (Midwest tungsten, 1cm3
, 18 grams) at room temperature overnight, allowing
sufficient time for thorough drying to eliminate any trapped water molecules between the layers.
Figure 5.2 presents the optical microscope image of the transferred GaAs on top of the target
substrates with and without a proper transfer process. This process aimed to enhance the adhesion
of the GaAs film, facilitating subsequent device fabrication. Following this, the GaAs layer
underwent cleaning using oxygen plasma to eliminate any lingering organic residues or
contaminants from previous steps.
Figure 5.2. Optical microscope images of (a) high quality GaAs transfer and (b) low quality GaAs transfer.
GaAs
a b
Cracked
GaAs
58
5.2 Device Operation Principle
To investigate the effect of electrical bias on the optical response, we first characterized the
electrical properties of the fabricated p-i-n device. Figure 5.3 displays the current density plotted
as a function of applied bias for the GaAs p-i-n device. The fabricated p-i-n structure exhibits the
expected p-i-n junction diode behavior, indicating successful fabrication and transfer of a working
diode showing ~0.07 A/cm2
at 1V of forward biased condition with an ideality factor of ~2.4.
Figure 5.4 shows the responsivity of the p-i-n structure under three different visible wavelengths,
verifying the well-behaved diode behavior under light response as well. 9-11 The carrier injection
rate can be determined by the current density injected into the device in the forward bias regime.
Figure 5.3 (a) Device I-V curve measured from GaAs p-i-n structure. (b) Sentaurus simulation result of electron density vs
current density. Color map of device stack at (c) unbiased case and (d) 1V forward biased to MSM structure.
59
To correlate the current density with carrier concentration, we simulated the device structure using
a 2-D Technology computer-aided design (TCAD) Sentaurus simulation, which self-consistently
solves the drift-diffusion and Poisson equations.12 The injected electron density was then extracted
from this simulation based on the amount of current input into the same device structure (50 nm
p++ / 150 nm intrinsic /50 nm n++ GaAs layers). Figure 5.3 b shows the electron density in the
intrinsic region vs current density. From our experimental data shown in Fig 5.3a, we extracted
that our maximum current density is ~107 A/m2
, which can be converted into ~1018 cm-3
carrier
density. Figure 5.3c and d visualizes the carrier concentration inside the MSM structure in different
biased cases. For non-biased cases, the carrier distribution happened mainly due to the carrier
diffusion from heavily doped layers. However, most of the concentration is still uniform with the
intrinsic carrier concentration of GaAs. Under forward-biased conditions, as carriers are injected,
Figure 5.4 Photoresponsivity of GaAs p-i-n structure from three different wavelength (RGB) laser.
60
the total number of carriers within the intrinsic layer increases, resulting in a higher concentration
at a steady state. Notably, unlike depletion-based electrical tuning devices, the p-i-n structure
facilitates systematic control over the carrier concentration within the intrinsic layer, allowing for
a clearer understanding of the extent to which this mechanism tunes optical parameters.
Figure 5.5 a shows the schematic of the device structure in a biased condition under Fourier
Transform Infrared Spectroscopy (FT-IR) setup. Figure 5.5 b plots the z-component of the H-field
at XYZ (µm) as a function of x and y under 1.8 µm metal strip width, showing the excellent
Figure 5.5 (a) Schematic of carrier modulation within the device under FT-IR measurement. (b) Color map of mode confined
in H-field profile in designed MSM structure. (c) Calculated refractive index of GaAs in IR range with Drude model. (d)
Experimental result of normalized R vs wavelength across the different carrier concentration. (e) Simulation result vs
experimental result on maximum tuning cases. (f) Peak wavelength vs carrier density for both experimental and simulation
results.
61
confinement of the field between the gold grating and metallic substrate. Based on the Drude model,
the carrier concentration of the semiconductor can be directly linked to the optical parameters.
Here, we calculated the refractive index of the doped GaAs using the Drude approximation to see
the effect of carrier concentration on the n and k when the structure is biased.
13-15 The dielectric
constant ε of a semiconductor substrate can be modeled using the Drude approximation:
𝜀 = 𝜀∞ (1 −
𝜔𝑝
2
𝜔2 + 𝑖𝜔Γ
) = 𝜀∞(1 −
𝜔𝑝
2
𝜔2
+ 𝑖
𝜔𝑝
2Γ
𝜔(𝜔2 + Γ
2)
)
where 𝜀∞is the high-frequency dielectric constant, 𝜔 is the angular frequency. Here, the plasma
frequency 𝜔𝑝and the relaxation frequency Γ are given by:
𝜔𝑝
2 =
𝑁𝑞
2
𝜀0𝜀∞𝑚∗
and
Γ =
1
𝜏
=
𝑞
𝜇𝑚∗
where τ is the scattering time, m* is the electron effective mass, μ is the electron mobility, q is the
electron charge, and N is the electron density (Here, we are assuming complete ionization of
dopants so that N= ND or NA). We calculated the permittivity using the following values for n-type
(p-type) GaAs: 𝜀∞=10.89, m*=0.067∙m0 (0.52∙m0), and μ=8000 (400) cm2
/V∙s. By varying the
carrier concentration, N, we produced the plots of refractive index as a function of wavelength
seen in Fig.5.5c (n for the solid line, k for the dotted line). Based on the data presented in the figure,
it is evident that there is a significant alteration in refractive index with increasing carrier
concentration at longer wavelengths. Specifically, the refractive index of GaAs shifts from n = 3.3
62
to n = 3.15 at 8μm. To observe the effect of carrier injection to the GaAs layer, we have optimized
the MSM grating design for the 8-10μm mid-IR region while also considering other wavelength
regions for comparison.
Based on the carrier injection analysis conducted in the previous session, we performed FT-IR
reflection measurements under biased conditions. Figure 5.5 d presents the normalized reflectivity
based on the injected carrier concentration into the device. The reflection was normalized to the
peak resonance to facilitate a clear visualization of the impact of carrier injection on the resonance
wavelength shift. The projected carrier concentration ranged from 1x1015 cm-3
, corresponding to
the carrier concentration in the unbiased case, to 1x1018 cm-3
(with 4 - 5 V applied voltage, voltage
varies due to fabrication non-idealites), representing the maximum current density injected into
the experimental device. During forward bias, the resonance wavelength shifts to lower
wavelengths by a maximum of approximately ~ 180 nm. Also, it shows systematic tuning with
different levels of current injection. A similar shift (~200 nm) was reported by both Iyer et al. and
Figure 5.6 (a) Schematic of unit cell constructing MSM metasurface. Reflection spectrum with different grating widths shows
peak resonance at (b) 6.4 m and (c) 7.8 m. Inset image shows SEM of specific grating widths. (d) Wavelength shift vs peak
resonance wavelength.
63
Pirotta et al. at resonance near 13.5 m and 10 m, respectively. 7,8 However, both devices relied
on complex heterostructures to enhance the response to carrier modulation, greatly increasing the
complexity of the device. Here, we have demonstrated similar performance with a simple
homojunction and at a lower wavelength. This is attributed to the use of a high-quality bottom
mirror and the design of the structure to maximize overlap between the optical mode and index
tuning region in the semiconductor. Notably, all the shifts observed in Figure 5.5d due to electron
injection were blue shifts, in contrast to the thermo-optic (TO) effects resulting from Joule heating,
which induce a red shift.8,16 This will be discussed in more detail in the next part of this paper. We
have carried out the Finite difference time domain (FDTD) to verify our experimental result using
the structure built in Figure 3b. According to FDTD electromagnetic simulations, this ~180 nm
blue shift corresponds to a change of ∼0.2 in the real part of the i-GaAs refractive index and an
associated free-carrier accumulation. Figure 5.5 e shows the reflection along with the simulation
data to compare with our experimental result. With the designed structure, the original resonance
wavelength shows up at Wsim=1.8 µm = ~8.6 m, while the resonance of the experiment comes at
Wexp=1.8 µm = ~8.7 m. We have selected this region as a target resonance wavelength due to the
large tunability of n of GaAs at this longer wavelength. Both experimental and simulation data
show a blue shift in the resonance wavelength, and the amount of shift is comparable, with good
overall agreement. The width and shift of the experimental resonance can be attributed to loss in
the device, imperfections in the top and bottom Au mirrors not captured in the simulation, and
surface roughness of the transferred GaAs film. Despite these slight deviations, the fundamental
mechanism of electrical tuning of metasurfaces is observable in these data. Figure 5.5 f displays
the peak resonance wavelength vs carrier density to compare the trend of resonance wavelength
shift in both simulation and experimental data. In both cases, the peak resonance blue shifts as we
64
increase the carrier concentration. While the experimental peak resonance is slightly shifted to the
simulation results, the overall trend agrees very well between the experiment and simulation. These
results, obtained by combining electrical and optical simulations, further strengthen our
understanding of how carrier concentration affects the optical parameters of III-V tuning layers in
metasurfaces.
We have explored various geometric structures to serve as a versatile platform for tunable
metasurfaces, accommodating different resonance wavelengths. As depicted in Figure 5.6a, the
unit cell of the MSM structure features a grating width (W), which can be adjusted while keeping
the GaAs thickness constant. To assess how the MSM mode evolves with changes in grating width
and to validate the efficacy of electrical tuning across different wavelength ranges, we fabricated
two additional grating widths, denoted as W = 2.4 μm and 3 μm. The experimental results,
illustrated in Figures 5.6b and 5.6c, show the FT-IR spectra for these structures, revealing
resonance peaks around Wexp=2.4 µm = 6.4 μm and Wexp=3 µm = 7.8 μm in unbiased conditions (green
solid line), respectively. Both cases exhibit a blue shift of approximately 56 nm and 79 nm under
forward bias conditions (red solid line). Furthermore, it's noteworthy that the shift in the mid-IR
range becomes more pronounced as the resonance wavelength increases, as shown in Figure 5.6d.
These findings provide valuable insights into the design and understanding of metasurfaces for
mid-IR applications. As previously elucidated, the Drude model establishes a link between doping
concentration and refractive index. However, a more comprehensive exploration of the factors
influencing the optical properties of materials within real devices is essential to comprehend the
electrical tuning effect. GaAs refractive index reduces with the increase of carrier concentration,
and this is caused by the injected carrier causing the band filling of the conduction band, which is
65
known as the Moss-Burstein effect, where the effective bandgap change (∆𝐸𝑔) can be expressed
as
∆𝐸𝑔 =
ℎ
2
8𝑚 ∗𝑒ℎ
(
3𝑛𝐶𝐵
𝜋
)
2/3
where h is plank constant, m*eh is the reduced effective mass of the charge carriers and nCB is the
concentration of electrons in the conduction band.17 Under forward bias conditions in the MSM
structure, the carrier concentration in the GaAs layer increases, resulting in an augmented effective
bandgap and a subsequent decrease in refractive index. This behavior aligns with the principles
outlined in Moss and Ravindra's relation.18 It's important to note that while this elucidates the shift
in MSM resonance modes effectively, there is also the possibility of TO tuning induced by Joule
heating occurring concurrently. 19, 20 Unlike carrier injection, TO tuning of GaAs increases the
refractive index when the temperature increases. Both simulation and experimental studies reveal
the trend of refractive index increase with temperature increase in GaAs. The main reason for the
refractive index changes due to the temperature increase is the thermal expansion of the lattice,
which causes the effective bandgap to decrease. Moss and Ravindra's relation again explains the
increase in refractive index.16, 20, 21 However, our observed shift in resonance wavelength,
consistent with the expected trend due to the EO effect, substantiates that the shift induced by
forward bias results from carrier injection. Given that the heat generated due to Joule heating
remains constant across different wavelengths, the dominant influence on effective refractive
index shift occurs when the EO tuning surpasses TO tuning. Though delving into the detailed
mechanisms behind these behaviors in various wavelength ranges exceeds the scope of this paper.
66
5.3 Summary
In conclusion, we demonstrate that the epitaxially transferred GaAs on the metallic surface can
be a platform for electrically tunable metasurfaces. The p-i-n diode was fabricated with the
transferred GaAs, which can act as carrier injection-based MSM metasurfaces. Metallic strips were
fabricated on the transferred GaAs layer to create an MSM resonance. Along with the device
simulation, we calculated the amount of carrier injected into the device with the current level
achieved from device modeling. The Drude model and Moss-Burstein effect verify the relationship
between carrier concentration and refractive index. FT-IR reflectance measurement while biasing
the device shows a shift in resonance wavelength at different IR regimes. Blue shifts from the
result verify that the tuning behavior is from the carrier injection-induced refractive index, which
is the opposite direction of TO tuning. The proposed method offers a promising path toward
developing dynamic and tunable metasurface components with potential applications in various
fields such as sensing, imaging, and communication.
67
References
1. E. Arbabi et al., MEMS-tunable dielectric metasurface lens. Nature communications 9, 1-
9 (2018).
2. Y. Liu et al., Dynamic thermal camouflage via a liquid-crystal-based radiative metasurface.
Nanophotonics 9, 855-863 (2020).
3. Y. Zhang et al., Electrically reconfigurable non-volatile metasurface using low-loss optical
phase-change material. Nature Nanotechnology 16, 661-666 (2021).
4. X. Liu et al., Taming the blackbody with infrared metamaterials as selective thermal
emitters. Physical review letters 107, 045901 (2011).
5. C. H. Chu et al., Active dielectric metasurface based on phase‐change medium. Laser &
Photonics Reviews 10, 986-994 (2016).
6. J. Park et al., Dynamic thermal emission control with InAs-based plasmonic metasurfaces.
Science advances 4, eaat3163 (2018).
7. S. Pirotta et al., Fast amplitude modulation up to 1.5 GHz of mid-IR free-space beams at
room-temperature. Nature communications 12, 799 (2021).
8. P. P. Iyer, M. Pendharkar, C. J. Palmstrøm, J. A. Schuller, III–V heterojunction platform
for electrically reconfigurable dielectric metasurfaces. ACS Photonics 6, 1345-1350 (2019).
9. A. C. Warren et al., 1.3-mu m PiN photodetector using GaAs with As precipitates (GaAs:
As). IEEE Electron Device Letters 12, 527-529 (1991).
10. D.-M. Geum et al., Monolithic integration of visible GaAs and near-infrared InGaAs for
multicolor photodetectors by using high-throughput epitaxial lift-off toward highresolution imaging systems. Scientific Reports 9, 18661 (2019).
68
11. G. Lioliou, X. Meng, J. Ng, A. Barnett, Characterization of gallium arsenide X-ray mesa
pin photodiodes at room temperature. Nuclear Instruments and Methods in Physics
Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
813, 1-9 (2016).
12. S. D. U. Guide, G. Version, Synopsys. San Jose, CA, (2008).
13. Y. C. Jun et al., Active tuning of mid-infrared metamaterials by electrical control of carrier
densities. Optics express 20, 1903-1911 (2012).
14. C. Kittel, Introduction to solid state physics Eighth edition. (2021).
15. P. Paskov, Refractive indices of InSb, InAs, GaSb, InAs x Sb 1− x, and In 1− x Ga x Sb:
effects of free carriers. Journal of applied physics 81, 1890-1898 (1997).
16. M. A. Khan, H. Algarni, N. Bouarissa, Temperature dependence of the optical and lattice
vibration properties in gallium arsenide. Optik 176, 366-371 (2019).
17. S. Gahlawat, J. Singh, A. K. Yadav, P. P. Ingole, Exploring Burstein–Moss type effects in
nickel doped hematite dendrite nanostructures for enhanced photo-electrochemical water
splitting. Physical Chemistry Chemical Physics 21, 20463-20477 (2019).
18. R. Reddy, S. Anjaneyulu, Analysis of the Moss and Ravindra relations. Physica status
solidi (b) 174, K91-K93 (1992).
19. N. M. Ravindra et al., Temperature-dependent emissivity of silicon-related materials and
structures. IEEE Transactions on semiconductor manufacturing 11, 30-39 (1998).
20. T. Skauli et al., Improved dispersion relations for GaAs and applications to nonlinear optics.
Journal of Applied Physics 94, 6447-6455 (2003).
69
21. J. Talghader, J. Smith, Thermal dependence of the refractive index of GaAs and AlAs
measured using semiconductor multilayer optical cavities. Applied Physics Letters 66, 335-
337 (1995).
70
Chapter 6. Defect Filtering at the Interface of MOCVD/TLP
Heterogenous Epitaxial III-V on Silicon
6.1 Introduction
Heterogeneous integration of high-quality III-V crystalline semiconductor materials on silicon
and building a platform for electronics and photonics have been desired by the material and device
community for the past few decades. Heterogenous III-V integration has been impeded in the
silicon industry for two reasons: i) cost of the epitaxial wafer and complexity of the growth system
and ii) controlling the material quality when integrated into silicon substrates.1-2 Specifically,
challenges associated with high-quality III-V growth on Si and other non-lattice matched
substrates are a significant roadblock preventing the widespread adoption of III-V transistors for
logic devices and silicon-integrated III-V photonics so far. Several techniques to overcome this
limitation have been applied, which can be divided into two classes: i) epitaxial transfer and ii)
direct growth. 3-6 The first case includes epitaxial lift-off (ELO), which uses a sacrificial layer to
transfer the epi layer to target substrates, and the other method is wafer bonding.
A new approach recently introduced as a potential candidate for heterogeneous material integration
on Si back-end dielectrics and metals that simultaneously addresses the cost, scalability, and
material quality issue is the templated liquid phase (TLP) growth. 7-10 Here, we have shown the
crystalline orientation matched, defect-filtered TLP growth (DF-TLP) by employing this growth
technique supported with the metal-organic chemical vapor deposition (MOCVD) growth to
provide a seed layer. We could achieve the high-quality III-V heterogeneously grown on silicon,
which shows excellent material quality.
71
6.2 Experimental and Theoretical Details
DF-TLP is based on a liquid-solid (LS) phase transformation process where nucleation is initiated
from supersaturated liquid group III.
Figure 6.1a-f shows the schematic of the growth process in which the crystalline orientation
matches with TLP growth combined with the MOCVD system. As used in the typical III-V/Si
heterogeneous integration, the substrate was prepared using the conventional MOCVD growth on
top of (100) silicon wafer. By growing a III-V seed layer on top of (100) silicon wafer, crystalline
orientation matched (100) III-V layer can be achieved. However, as expected, due to the i) lattice
mismatch, ii) thermal expansion difference, and iii) nonpolar nature of (100) silicon substrate,
various types of defects could be found at the III-V/Si interface such as anti-phase boundaries
(APBs), misfit dislocations (MDs), and threading dislocation (TDs).
2, 11, 12 Figure 6.1g shows the
cross-section scanning tunneling electron microscope (STEM) image of the grown MOCVD seed
layer on top of the silicon substrate. The various defects will propagate through the entire III-V
layer, producing low-quality material. These defects are critical for optoelectronic devices'
performance since they can act as i) a leakage path for a dark current and ii) a non-radiative
Figure 6.1 Schematic of DF-TLP III-V growth on silicon substrate and SEM images
72
recombination center for optoelectronic and photonics devices. So, minimizing the defect densities
and growing defect-free III-V have long been desired since the III-V optoelectronic devices were
introduced and studied. Unlike other approaches using a costive and complicated material growth
system and structure, which involves a sequence of fabrication steps, we used DF-TLP growth as
a primary growth process to ensure the quality of the grown III-V layer on top of the MOCVD
seed layer. DF-TLP growth is a liquid-based growth with different thermodynamics and nucleation
mechanisms compared to conventional MOCVD or MBE growth, so a detailed analysis of the
growth processes needs to be studied and elucidated. The process flow of TLP growth can be found
in Chapter 4 and other peer-reviewed journals. 7-10 The brief schematic with SEM images of TLP
growth is shown in figure 6.1h, showing the SEM images of InP nucleation turned into fully grown
mesa on top of the MOCVD seed layer. Here, the MOCVD seed layer provides the crystalline
information, while the main growth process happens when our liquid phase indium gets
supersaturated with group V components either with phosphorous or arsenic and then grows while
filtering out the defects.
73
As shown from the previous STEM images, most defects will propagate through the layer without
any filtering mechanisms in III-V/Si interface. Notably, our DF-TLP growth is not a layer-by-layer
growth but rather having islands grow and enlarge starting from the initial nucleation point,
depending on the growth condition. We conducted cross-section STEM and Plan view TEM on
the grown DF-TLP III-V layer to elucidate how the defect filtering mechanism happens. Figure
6.2a shows the cross-section STEM images showing three different stacks with different defects.
Starting with the Si wafer, the III-V layer (InP + GaAs) grown on top of Si shows a large number
of defects, including TDs, SFs, and APBs. The STEM images of TLP III-V layer shows that highFigure 6.2 (a) Cross section STEM image of TLP/MOCVD III-V on Si (b)-(c) Plan View STEM images of DF-TLP layer, (d)
ECCI of MOCVD III-V layer showing dislocation densities.
74
quality InP was grown on top of a defective seed layer. Threading dislocation density (TDD) was
analyzed through Plan view STEM and electron channeling contrast imaging (ECCI). TDD
reduces from ~2.7x109
cm-2
(MOCVD substrate) to ~2x107
cm-2
(TLP III-V) with a defect filtering
mechanism. This is a promising result given that reducing 2 orders of magnitude defect density
through one single growth process has never been shown with other works. To track the
mechanism of this defect filtering, we simply modeled the DF-TLP growth process. It is generally
true that a defective surface will have a higher surface energy compared to a perfect surface.
Surface energy is a measure of the energy required to create a new surface, and defects on a surface
can increase the surface energy by creating additional surface area or by disrupting the orderly
arrangement of atoms at the surface. In some cases, the surface energy of a defective surface can
be significantly higher than that of a perfect surface, depending on the type and density of the
defects present. Given this, when the group III metal (indium) melted above it's melting
temperature up to the growth temperature (TG), voids might be formed where the liquid indium
has a problem wetting the surface compared to the perfect surface. Figure 6.3 shows the growth
schematic of the defect filtering mechanism. Based on the surface energy on different spots within
the substrate, the initial nucleation forms at the non-defective position which has lower surface
energy. Once the nucleation happens, it laterally grows towards InP's (111) facet. Based on
experiments and theoretical calculation, it shows the surface energy of (111) is smaller than (100)
in InP. 13, 14
75
Which means, thermodynamically it is more favorable to nucleate on top of low energy surface
(defect-free area) because low surface energy is generally preferred in nucleation and growth. After
all, it can lead to more stable surfaces and lower energy barriers for forming new phases. This
leads to the growth of TLP InP towards (111) direction, instead of growing on top of defective
(100) substrate, increasing the probability of defect filtering throughout the growth process.
To check the quality of the grown TLP layer, we performed a material quality check with several
methods. Figure 4 (a) shows the photoluminescent (PL) measurement from two different spots,
where the photodetector counts the photon emission from the spot of the grown TLP layer and the
MOCVD substrate. As expected, the counts from the MOCVD substrate are significantly low,
given the fact that it has various types of defects that act as a non-radiative recombination center.
While the grown TLP area shows a significant number of higher counts. This indicates that the
Figure 6.3 Schematic of DF-TLP growth mechanism and STEM image of InP/Indium interface on MOCVD InP Substrate.
76
quality of the grown crystalline does not flow with the quality of the bottom substrate which
usually happens for the layer-by-layer growth happens in the conventional growth techniques,
rather filtering all the defects shown at the bottom substrate. For better understanding, we have
mapped out the PL intensity in a heat map to find the boundary between the grown film and the
substrate. It is clearly showing that only the grown mesa is having a higher PL intensity compared
to the MOCVD substrate.
6.3 Summary
Overall, DF-TLP growth is an excellent candidate for the heterogeneous growth of III-V on top of
silicon with a unique defect filtering mechanism. Notably, the integration approach demonstrated
in this chapter does not require any complicated defect filtering approaches such as ARTs and
Figure. 6.4 PL measurement on MOCVD InP and DF-TLP InP
77
SLSs design, or a thick buffer layer to mitigate the defect density. It potentially provide another
platform for high-quality and cost-effective III-Vs integration on Si.
78
References
1. D. Liang, J. E. Bowers, Recent progress in heterogeneous III-V-on-silicon photonic
integration. Light: Advanced Manufacturing 2, 59-83 (2021).
2. J. M. Ramirez et al., III-V-on-silicon integration: from hybrid devices to heterogeneous
photonic integrated circuits. IEEE Journal of Selected Topics in Quantum Electronics 26,
1-13 (2019).
3. S. Bao et al., A review of silicon-based wafer bonding processes, an approach to realize
the monolithic integration of Si-CMOS and III–V-on-Si wafers. Journal of Semiconductors
42, 023106 (2021).
4. N. Daix et al., Towards large size substrates for III-V co-integration made by direct wafer
bonding on Si. APL materials 2, (2014).
5. K. Tanabe, D. Guimard, D. Bordel, S. Iwamoto, Y. Arakawa, Electrically pumped 1.3 μm
room-temperature InAs/GaAs quantum dot lasers on Si substrates by metal-mediated wafer
bonding and layer transfer. Optics express 18, 10604-10608 (2010).
6. H. Kum et al., Epitaxial growth and layer-transfer techniques for heterogeneous integration
of materials for electronic and photonic devices. Nature Electronics 2, 439-450 (2019).
7. D. Sarkar et al., Low Temperature Growth of Crystalline Semiconductors on Nonepitaxial
Substrates. Advanced Materials Interfaces 7, 1902191 (2020).
8. J. Tao et al., High mobility large area single crystal III–V thin film templates directly grown
on amorphous SiO2 on silicon. Applied Physics Letters 117, 042103 (2020).
9. D. Sarkar et al., Confined liquid-phase growth of crystalline compound semiconductors on
any substrate. ACS nano 12, 5158-5167 (2018).
79
10. H. U. Chae et al., Monolithic III–V on Metal for Thermal Metasurfaces. ACS nano 16,
18497-18502 (2022).
11. H. Schmid et al., Template-assisted selective epitaxy of III–V nanoscale devices for coplanar heterogeneous integration with Si. Applied Physics Letters 106, 233101 (2015).
12. T. Grassman et al., MOCVD-grown GaP/Si subcells for integrated III–V/Si multijunction
photovoltaics. IEEE Journal of Photovoltaics 4, 972-980 (2014).
13. N. Sibirev, M. Timofeeva, A. Bol’shakov, M. Nazarenko, V. Dubrovskiĭ, Surface energy
and crystal structure of nanowhiskers of III–V semiconductor compounds. Physics of the
Solid State 52, 1531-1538 (2010).
14. J. Cahn, R. Hanneman, (111) Surface tensions of III–V compounds and their relationship
to spontaneous bending of thin crystals. Surface science 1, 387-398 (1964).
Abstract (if available)
Abstract
As Moore’s Law reaches an endpoint, this situation calls for the development of new functionalities in electronics and photonics device research. Various types of materials and devices have been studied to address these issues. This thesis shows recent research progress on creating new functionalities in emerging electronics and photonics devices and the physics and material science behind them utilizing the non-equilibrium hot electrons and III-V semiconductors. Multiple factors inspired these; first, the superior properties of non-equilibrium hot electrons in many different fields, such as electrochemistry and vacuum electronics. Here, we showed a high quantum efficiency device to derive the hydrogen evolution reaction (HER) with hot electrons collected from the metal-insulator-semiconductor (MIS) structure. Similar types of structures can be used in photoemission applications which mimic the negative electron affinity (NEA) photocathode. From a material perspective, III-V semiconductors integrated in a non-epitaxial substrate realize new functionality devices. Our progress in successfully achieving monolithic III-V integration on metallic substrate with the low-temperature templated liquid phase (LT-TLP) method was shown to build a metasurface in the Mid-IR range. Epitaxial transfer of p-i-n GaAs on metal to create an electrically tunable metasurface was presented as an alternative III-V integration method. In addition, TLP growth was used as a defect filtering layer to reduce the defect density introduced at the III-V/Si interface, which is the long-desired goal in the materials community to integrate III-V directly grown on Si. Based on these results, characterization and analysis of high-quality III-V semiconductor monolithically grown on Si is presented.
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Integrating material growth and device physics: building blocks for cost effective emerging electronics and photonics devices
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