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Carbon nanotube nanoelectronics and macroelectronics
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Carbon nanotube nanoelectronics and macroelectronics
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Content
CARBON NANOTUBE NANOELECTRONICS AND MACROELECTRONICS
By
Chuan Wang
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
August 2011
Copyright 2011 Chuan Wang
ii
Dedication
Dedicated to my family.
iii
Acknowledgements
I will always remember the past four years studying at USC as a PhD student.
There are numerous people who have helped, encouraged, and inspired me, giving me
valuable advices on both research and various aspects of my life. I would like to thank
them all for making this dissertation possible.
First of all, I wish to thank my advisor, Prof. Chongwu Zhou, for all his guidance,
encouragement, support, and patience. His sincere interests in nanotechnology, and
knowledge in interdisciplinary areas have been a great inspiration to me. I am also very
grateful for his valuable suggestions and help for my academic career. Without his help,
most of the work in this dissertation could not be achieved.
I would also like to express my gratitude to my dissertation committee members
Prof. Steve Cronin and Prof. Mark Thompson for their very helpful insights, comments
and suggestions as well as Prof. Jia Grace Lu and Prof. Alice Parker for serving on my
qualifying exam committee.
Many thanks also go to Prof. Yunyi Fu from Peking University, who was the
advisor for my master’s study. His introduction to the field of nanoscience and
nanotechnology as well as his training and motivation about how to perform scientific
research are valuable and have greatly helped my PhD study here at USC.
Moreover, I would like to thank the former group members and my fellow
graduate students. Dr. Koungmin Ryu, Dr. Fumiaki Ishikawa, Dr. Po-Chiang Chen, Dr.
Lewis Gomez, Dr. Akshay Kumar, Alexander Badmaev, Hsiao-Kang Chang, Anuj
iv
Madaria, Yi Zhang, Haitian Chen, Jialu Zhang, Yue Fu, Yuchi Che, Xue Lin, Jia Liu,
Zhen Li, Jing Xu, Jing Qiu, Shelley Wang, Maoqing Yao, Nappadol Aroonyadet,
Mingyuan Ge, Jiepeng Rong, Luyao Zhang, Xin Fang, Pyojae Kim, Younghyun Na,
Kuan-Teh Li, Ning Yang, and Liang Chen. All of you are not only excellent researchers
but also fabulous person, and I really enjoyed working with you in such a friendly,
encouraging, and active group.
Additionally, I would like to acknowledge all of the collaborators including Prof.
Kang L. Wang, Dr. Kosmas Galatsis, Alborz Jooyaie, Mingqiang Bao from UCLA, Dr.
Ming Zheng from National Institute of Standards and Technology, Prof. H.-S. Philip
Wong from Stanford University, and Prof. Mark Hersam from Northwestern University,
who have provided invaluable support and suggestions throughout this process. Your
expertise in different research areas has greatly helped me diversify my knowledge and
broaden my vision.
Lastly, and most importantly, I greatly appreciate the endless love, support, and
encouragement from my parents, my family, and my girlfriend Xing Huang. I would not
have all these achievements today without you.
v
Table of Contents
Dedication ........................................................................................................................... ii
Acknowledgements ............................................................................................................ iii
List of Figures ................................................................................................................... vii
Abstract ............................................................................................................................ xix
Chapter 1. Introduction ....................................................................................................... 1
1.1 Introduction of carbon nanotubes .......................................................................... 1
1.2 Electrical properties of carbon nanotubes .............................................................. 2
1.3 Carbon nanotubes for beyond-silicon electronics ................................................ 10
1.4 Outline of the dissertation .................................................................................... 12
Chapter 1. References ................................................................................................ 18
Chapter 2. Wafer-Scale Nanotube-on-Insulator Approach for Submicron Devices and
Integrated Circuits Using Aligned Nanotubes .................................................................. 20
2.1 Introduction .......................................................................................................... 20
2.2 Wafer-scale aligned carbon nanotube synthesis ................................................... 22
2.3 Wafer-scale aligned nanotube transfer ................................................................. 24
2.4 Field-effect transistors using aligned carbon nanotubes ...................................... 26
2.5 Integrated CMOS nanotube circuits..................................................................... 34
2.6 Summary .............................................................................................................. 44
Chapter 2. References ................................................................................................ 45
Chapter 3. Metal Contact Engineering and Registration-Free Fabrication of CMOS
Integrated Circuits Using Aligned Carbon Nanotubes...................................................... 48
3.1 Introduction .......................................................................................................... 48
3.2 Air-stable n-type nanotube field-effect transistors using Gd contacts ................. 50
3.3 Carbon nanotube diode using Pd and Gd contacts ............................................... 60
3.4 Integrated CMOS nanotube inverter .................................................................... 61
3.5 Summary .............................................................................................................. 64
Chapter 3. References ................................................................................................ 65
Chapter 4. Synthesis and Device Applications of High-Density Aligned Carbon
Nanotubes Using Low-Pressure Chemical Vapor Deposition and Stacked Multiple
Transfer ............................................................................................................................. 68
4.1 Introduction .......................................................................................................... 68
4.2 Ultra high density aligned nanotube synthesis ..................................................... 70
4.3 Stacked multiple transfer technique ..................................................................... 73
vi
4.4 Electrical properties of the high density aligned nanotubes ................................ 77
4.5 High performance submicron nanotube transistors ............................................. 82
4.6 Summary .............................................................................................................. 87
Chapter 4. References ................................................................................................ 88
Chapter 5. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors
for Display Applications ................................................................................................... 92
5.1 Introduction .......................................................................................................... 92
5.2 Separated carbon nanotube thin-film deposition technique ................................. 94
5.3 Separated carbon nanotube thin-film transistors .................................................. 98
5.4 Comparing TFTs using separated and CVD-grown nanotubes ......................... 100
5.5 Numerical simulation of nanotube percolation network .................................... 107
5.6 Display electronics using separated nanotube thin-film transistors ................... 109
5.7 Summary .............................................................................................................112
Chapter 5. References ...............................................................................................113
Chapter 6. Macroelectronic Integrated Circuits Using High-Performance Separated
Carbon Nanotube Thin-Film Transistors .........................................................................117
6.1 Introduction .........................................................................................................117
6.2 Effect of semiconducting nanotube purity on transistor performance ................119
6.3 Integrated circuits using separated nanotube thin-film transistors .................... 133
6.4 Summary ............................................................................................................ 139
Chapter 6. References .............................................................................................. 140
Chapter 7. Radio Frequency and Linearity Performance of Transistors Using High-Purity
Semiconducting Carbon Nanotubes ................................................................................ 144
7.1 Introduction ........................................................................................................ 144
7.2 Separated nanotube RF transistor fabricaion ..................................................... 147
7.3 DC characteristics of the separated nanotube RF transistors ............................. 149
7.4 RF characteristics of the separated nanotube RF transistors ............................. 152
7.5 Linearity characteristics of the separated nanotube RF transistors .................... 157
7.6 Summary ............................................................................................................ 162
Chapter 7. References .............................................................................................. 163
Chapter 8. Conclusions and Future Directions ............................................................... 166
8.1 Conclusions ........................................................................................................ 166
8.2 Future directions on aligned carbon nanotubes ................................................. 167
8.3 Future directions on nanotube thin-film electronics .......................................... 172
Chapter 8. References .............................................................................................. 176
Bibliography ................................................................................................................... 177
vii
List of Figures
Figure 1.1 Schematic diagram of graphene layer. A carbon nanotube can be
constructed by cutting a graphene layer along lines of OB and
AB’, and then rolling it up into a tube, so that O meets A and B
meets B’. Vector OA is called the chiral vector (C
h
).
3
Figure 1.2 Schematic diagrams of Armchair, Zigzag, and Chiral nanotubes. 4
Figure 1.3 The energy dispersion relations for graphene with γ
0
= 3.013 eV , s
= 0.129 and ε
2p
= 0. The inset shows the energy dispersion along
the high symmetry lines between the Γ, M, and K points.
5
Figure 1.4 The wave vector k for one-dimensional carbon nanotubes is
shown in the two-dimensional Brillouin zone of graphene
(hexagon) as bold lines for (a) metallic and (b) semiconducting
carbon nanotubes.
8
Figure 1.5 Dispersion relations for a metallic (3,3) nanotube (upper) and a
semiconducting (4,2) nanotube (lower).
9
Figure 1.6 Density of states for a (10,0) semiconducting nanotube and a
(9,0) metallic nanotube.
10
Figure 1.7 Outline of the dissertation. 13
Figure 2.1 Photograph of a 4 inch quartz wafer with aligned nanotubes and
patterned electrodes. Inset: SEM images of aligned nanotubes
between electrodes at different locations of the wafer.
22
Figure 2.2 Wafer-scale aligned carbon nanotube synthesis. (a) Photograph of
a 4 inch sapphire wafer with aligned nanotubes. (b) Schematic
diagram of 9 feet-long furnace for wafer-scale nanotube growth.
(c) and (d) SEM images of aligned nanotubes and temperature
flow charts for the annealing and the nanotube growth on
sapphire and quartz wafer, respectively.
23
Figure 2.3 Wafer-scale aligned nanotube synthesis, transfer, and fabrication.
(a) Schematic diagram and photograph of full wafer synthesis of
aligned nanotubes on a 4 inch quartz wafer. Inset shows SEM
image of aligned nanotubes. (b–f) Schematic diagrams and
photographs showing the transfer procedure, i.e., gold film
deposition (b), peeling off the gold film with nanotubes (c),
25
viii
transfer of the gold film with nanotubes onto a Si/SiO
2
substrate
(d), etching away the gold film (e), and device fabrication on the
transferred nanotube arrays (f).
Figure 2.4 Photo images of nanotube devices and circuits built on a 4 inch
Si/SiO
2
wafer: 1, back-gated transistor; 2, top-gated transistor; 3,
CMOS inverter; 4, NOR logic gate; and 5, NAND logic gate.
26
Figure 2.5 Characteristics of back-gated transistors down to submicron
channel length. (a) Schematic diagram of a back-gated transistor
built on transferred nanotubes. (b) SEM image of a transistor
with submicron channel length. (c) Transfer (I
ds
–V
g
)
characteristics of transistors with different L = 0.5, 0.75, 1, 2, 5,
10, and 20 μm, and W = 100 μm. (d) Normalized on and off-
current densities and transconductance (g
m
) derived from (c).
(e–g) Electrical breakdown study of the transistors; I
ds
–V
g
curves
for a typical transistor after consecutive electrical breakdown (e),
I
ds
–V
g
curves and I
ds
–V
ds
curves of the transistor in (e) after three
rounds of electrical breakdown (f), and Statistics of devices
before and after electrical breakdown (g). (h) I
ds
–V
g
curves of two
representative devices, with one (black) and two (red) steps of
transfer, respectively. Inset illustrates the multiple transfer
process.
27
Figure 2.6 I
ds
–V
g
and g
m
–V
g
curve from a device with 50 μm channel length. 29
Figure 2.7 Distribution of on/off ratio and on-current density of 50 devices
before (a) and after (b) electrical breakdown, respectively.
31
Figure 2.8 Top-gated transistors for doping and truly integrated CMOS
inverters. (a, b) Schematic diagram and SEM image of a
top-gated transistor, respectively. (c) I
ds
–V
g
curves of the
transistor with L = 3 μm and W = 25 μm at different V
ds
= 0.1 to
1.1 V in step of 0.1 V. Inset: I
ds
–V
g
curve in logarithm scale. (d)
I
ds
–V
ds
curves at different V
g
= -20, -15, -10, 10, 15, and 20 V for
the same device in (c). (e) I
ds
–V
g
curves of the top-gated
transistor before (red) and after (black) K doping. (f) Voltage
transfer characteristic (VTC) of a CMOS inverter with selective
K doping. Inset: schematic diagram (left) and photograph (right)
of the circuit. (g) I
ds
–V
g
curves of a dual-gated transistor before
(red, back gate at -20 V) and after (black, back gate at 20 V)
electrostatic doping. (h) I
ds
–V
g
curves at different V
bg
= -20 to 20
V for the same device in (e), showing a significant shift of
threshold voltage and enhancement of n-type conduction.
33
ix
Figure 2.9 (a, b) I
ds
–V
g
curves of a back-gated device before (a) and after (b)
PEI doping, respectively. (c, d) SEM images of the top-gated
devices before (c) and after (d) soaked in N
2
H
4
, respectively. (e,
f) I
ds
–V
g
curves before and after N
2
H
4
doping on the back-gated
devices without (e) and with (f) PMMA passivation, respectively.
36
Figure 2.10 PMOS NOR and NAND gates with top-gated transistors. (a-c)
Schematic diagrams of a defect-influence layout and two
defect-tolerate layouts with two transistor in parallel,
respectively. (d, e) Output characteristics of PMOS NOR and
NAND, respectively. Inset: SEM image of integrated pull-up
networks and schematic diagram of PMOS circuits. (f, g) Output
characteristics of PMOS NAND with pull-up network (b) and (c),
respectively, where the nanotube density was not uniform in the
circuit, as depicted in schematic diagram in inset.
38
Figure 2.11 (a, b) I
DD
–V
A
curves at different V
B
= 5, 0, -5 V from the two
different types of NAND pull-up networks, as shown in SEM
images and schematic diagrams.
40
Figure 2.12 Defect-tolerant CMOS NOR and NAND with individual
back-gated transistors. (a, b) Schematic diagrams of CMOS NOR
and NAND, respectively. (c, d) SEM images of CMOS NOR and
NAND, respectively. (e, f) Output characteristics of CMOS NOR
and NAND, respectively.
42
Figure 2.13 (a, b) I
DD
–V
A
curves of the pull-up network (in dotted line) in the
CMOS NAND before and after potassium doping, respectively.
(c, d) I
DD
–V
A
curves of the pull-down network (in dotted line) in
the CMOS NAND before and after potassium doping,
respectively.
43
Figure 3.1 Fabrication of the back-gated n-type nanotube transistors and
their electrical properties. (a) Simplified process flow of the
n-type nanotube transistor fabrication including aligned nanotube
synthesis on quartz substrate (left) (inset: SEM image of the
aligned nanotubes), transfer to Si/SiO
2
substrate, and Gd metal
electrode patterning by photolithography and lift-off process. The
optical photographs of the completed chip and a typical device
are shown in the right. (b, c) Schematic diagram (b) and SEM
image (c) of the n-type aligned nanotube transistor with Gd metal
contacts. (d) Transfer (I
D
–V
G
) characteristics of a typical n-type
nanotube transistor (L = 4 μm, W = 8 μm) measured at V
D
= 1 V
before and after electrical breakdown. (e) Transfer characteristics
52
x
of the same device measured under different drain voltages after
electrical breakdown. (f) Output (I
D
–V
D
) characteristics of the
same device measured under different gate voltages.
Figure 3.2 Linear region output characteristics of the Gd-contacted nanotube
transistor.
53
Figure 3.3 Transfer (I
D
–V
G
) characteristics of the Gd-contacted nanotube
transistors measured in ambient environment showing n-type or
ambipolar behavior. (a) Transfer characteristics of a typical
n-type device plotted in linear scale. (b) Transfer characteristics
of a typical ambipolar device plotted in linear scale. (c) Transfer
characteristics of the n-type and ambipolar devices plotted in
logarithm scale.
54
Figure 3.4 Electrical properties of the passivated transistor with Gd
source/drain extensions. (a) Schematic diagram showing the
fabrication process of the passivated individual-gated n-type
transistor. Starting from the individual back-gated transistor with
Ti/Pd metal contacts, Gd source and drain extensions are
patterned by e-beam lithography, followed by SiO
2
passivation
deposited by e-beam evaporation. (b) Transfer characteristics of
an individual back-gated transistor (L = 2 μm, W = 5 μm) with
Ti/Pd metal contacts. (c) Transfer characteristics of the same
device after adding Gd source/drain extensions by e-beam
lithography. (d) Transfer characteristics of the same device with
Ti/Pd plus Gd source/drain extensions before and after SiO
2
passivation measured at V
D
= 1 V. (e) Transfer characteristics of a
typical device with only Ti/Pd metal contacts before and after
SiO
2
passivation measured at V
D
= 1 V .
57
Figure 3.5 Transfer (I
D
–V
G
) characteristics of a Gd-contacted nanotube
transistor measured at V
D
= 1 V before and after PMMA
passivation.
58
Figure 3.6 Aligned nanotube PN junction based on Pd and Gd metal
contacts. (a) Schematic diagram of a PN junction based on Pd
and Gd metal contacts. (b) Optical microscope image of a typical
PN diode device. (c) SEM image (with artificial color) of a
typical PN diode device. (d, e) I–V characteristics of the diode
device plotted in linear (d) and logarithm (e) scale, respectively.
(f) I–V characteristics measured under different gate voltages. (g,
h, i) Energy band diagrams showing the equilibrium (g),
forward-bias (h), and reverse-bias (i) of the diode, respectively.
61
xi
Figure 3.7 Integrated nanotube CMOS inverter based on Pd and Gd metal
contacts. (a, b) Schematic diagram (a) and optical microscope
image (b) of the integrated CMOS inverter with different source
drain metal contacts, Pd for p-type branch, and Gd for n-type
branch. (c) SEM image (with artificial color) showing the n-type
branch of the CMOS inverter with Gd source/drain extensions.
(d, e) Transfer characteristics of the p-type pull-up branch (d) and
n-type pull-down branch (e) of the CMOS inverter, respectively.
Inset: energy band diagram of the corresponding devices. (f)
Transfer characteristics of the p- and n-type transistors and the
simulated inverter voltage transfer characteristic. (g) Measured
and simulated voltage transfer characteristics of the CMOS
inverter.
63
Figure 4.1 High-density aligned carbon nanotubes synthesized by
low-pressure chemical vapor deposition. (a) FE-SEM image
showing the aligned nanotubes grown on quartz substrate. (b)
FE-SEM image at high magnification showing the as-grown
aligned nanotubes with an average density of 27 tubes/ μm. (c)
AFM image showing the aligned nanotubes with an average
density of 19 tubes/ μm. (d) Diameter distribution of the
nanotubes extracted from the AFM image. The diameter is
1.388 ±0.457 nm. (e, f) Raman spectra showing the (e) D-band
and (f) G’-band of the as-grown aligned nanotubes with
high-density (30 tubes/ μm) using ethanol LPCVD and typical
density (5 tubes/ μm) using methane CVD. (e) Inset: RBM of the
high density nanotube sample.
71
Figure 4.2 Using stacked multiple transfer to further increase the nanotube
density. (a) Schematic illustration showing the stacked multiple
transfer process. (b) FE-SEM image of the as-grown aligned
nanotubes on quartz substrate with a density of 15 tubes/ μm. (c,
d, e) FE-SEM images showing the aligned nanotubes transferred
to Si/SiO
2
substrates with one-time, two-time and four-time
transfer, respectively. The corresponding average densities are 15
tubes/ μm, 29 tubes/ μm, and 55 tubes/ μm.
75
Figure 4.3 Electrical measurements of the back-gated nanotube transistors
using nanotubes with one-time, two-time and four-time transfer.
(a) Schematic illustration of the back-gated transistor with
high-density aligned nanotubes. (b) Plot of the current density
(I
on
/W) versus channel length (L) for devices fabricated using
nanotubes with different density. (c) Plot of I
on
/W versus the
reciprocal of channel length (1/L) for devices fabricated using
78
xii
nanotubes with different density. (d, e) Plots of (d) the
normalized transconductance (g
m
/W), and (e) device mobility
( μ
device
) versus channel length for devices fabricated using
nanotubes with different density. (f) Plot showing the I
on
/W,
I
on
/W
eff
, g
m
/W and g
m
/W
eff
versus nanotube density for the
high-density aligned nanotube transistors.
Figure 4.4 Electrical properties of high performance submicron transistors
with high-density aligned nanotubes. (a) Schematic diagram of
the high performance submicron nanotube transistor with Ti/Au
individual back-gate and 50 nm HfO
2
high- κ dielectric. (b)
FE-SEM image showing the channel of a submicron high
performance transistor. The channel length is 0.5 μm and the
aligned nanotubes in the channel have an average density of 30
tubes/ μm. (c, d) Transfer (I
D
–V
G
) characteristics (red: linear scale,
green: log scale) and g
m
–V
G
characteristics (blue) of a high
performance nanotube transistor (L = 0.5 μm, and W = 50 μm)
measured at V
D
= 1V (c) before and (d) after electrical
breakdown, respectively. (e) Comparison of the transfer
characteristics of the same device before and after electrical
breakdown. (f) Output (I
D
–V
D
) characteristics of the same device
after electrical breakdown.
83
Figure 4.5 Benchmarking the high performance submicron nanotube
transistors using high-density aligned nanotubes with the
previously published work. The drive-current (I
on
/W) is plotted
versus year for the previously published aligned nanotube
transistor work at USC, UIUC, Stanford, and Duke.
86
Figure 5.1 Wafer-scale deposition of separated carbon nanotubes and
fabrication of SN-TFTs. (a) Schematic diagram of APTES
assisted nanotube deposition on Si/SiO
2
substrate. (b) Length
distribution of the separated nanotubes used in this study (95%
semiconducting nanotubes purchased from NanoIntegris, Inc.),
the average nanotube length is 1.716 μm. (c, d) FE-SEM images
of separated nanotubes deposited on Si/SiO
2
substrates with (c)
and without (d) APTES functionalization, respectively. (e)
Photograph of 3 in. Si/SiO
2
wafer after APTES assisted
nanotubes deposition. Inset: FE-SEM images showing nanotubes
deposited at different locations on the wafer, the locations of the
SEM images on the wafer correspond to the approximate
locations on the wafer where the images were taken. All the scale
bars are 5 μm. (f) Photograph of the same wafer after electrode
patterning. The wafer consists of SN-TFTs used in this study and
95
xiii
other types of electronic devices. Such SN-TFTs are made with
channel width (W) of 10, 20, 50, 100, and 200 μm, and channel
length (L) of 4, 10, 20, 50, and 100 μm.
Figure 5.2 UV-Vis-NIR absorption spectra of mixed (blue) and 95%
semiconducting (red) nanotube solutions.
96
Figure 5.3 Electronic properties of back-gated SN-TFTs (a) Schematic
diagram of a back-gated transistor built on separated nanotube
thin-film with Ti/Pd (5 Å /70 nm) contacts and SiO
2
(50nm) gate
dielectric. (b) FE-SEM image of a typical SN-TFT with 4 μm
channel length. (c, d) Output (I
D
–V
D
) characteristics of a typical
SN-TFT (L = 20 μm, and W = 100 μm) in triode region (c) and
saturation region (d), respectively. (e) Transfer (I
D
–V
G
)
characteristics (red: linear scale, green: log scale) and g
m
–V
G
characteristics (blue) of the same device with V
D
= 1V . (f) Current
density (I
on
/W) measured at V
D
= 1V and threshold voltage (V
th
)
of 10 representative SN-TFTs showing the uniformity of devices.
The red line represents the average value.
99
Figure 5.4 (a) FE-SEM image of a typical TFT based on CVD grown mixed
nanotubes with 10 μm channel length. (b) Transfer (I
D
–V
G
)
characteristics (red: linear scale, green: log scale) and g
m
–V
G
characteristics (blue) of a typical device (L = 20 μm, and W = 100
μm) measured at V
D
= 1V. (c) Transfer (I
D
–V
G
) characteristics of
the device measured at different V
D
. (d) Output (I
D
–V
D
)
characteristics of the devices measured at different V
G
.
102
Figure 5.5 Statistical study of 200 nanotube TFTs based on separated
nanotubes and mixed nanotubes. (a) Plot of current density
(I
on
/W) versus channel length for TFTs fabricated on separated
nanotubes and mixed nanotubes. (b) Plot of average on current
(I
on
) versus channel width for TFTs fabricated on separated
nanotubes and mixed nanotubes, with various channel lengths (4,
10, 20, 50, 100μm). (c) Plot of average on/off ratio (I
on
/I
off
)
versus channel length for TFTs fabricated on separated nanotubes
and mixed nanotubes. (d) Plot of average transconductance per
unit width (g
m
/W) and average device mobility ( μ
device
) versus
channel length for TFTs fabricated on separated nanotubes and
mixed nanotubes.
103
Figure 5.6 Simulation of nanotube thin-film percolation network. (a)
Randomly generated nanotube percolation networks of separated
nanotubes (top) and mixed nanotubes (bottom) for devices with L
108
xiv
= 10 μm and W = 20μm. The red and blue lines represent metallic
and semiconducting nanotubes, respectively (b) comparison
between the simulation data derived from the percolation network
and measurement data.
Figure 5.7 OLED control circuit by SN-TFT. (a) Transfer (I
D
–V
G
)
characteristics under different drain voltages for the device used
to control the OLED (L = 20 μm, and W = 100 μm), Inset: optical
microscope image of the device. (b) Characteristics of the OLED
control circuit where the current flow through the OLED (I
OLED
)
is measured by sweeping the V
DD
and Input voltage V
G
. Various
curves correspond to various values of V
G
from -10 V to 10 V in
2 V steps. (c) Two terminal measurement of the OLED showing
the current through the OLED (I
OLED
) (red line) and OLED light
intensity (green line) versus the voltage applied across the OLED
(V
OLED
). (d) Plot of the current through the OLED (I
OLED
) (red
line) and OLED light intensity (green line) versus V
G
with V
DD
=
5 V . Inset: The circuit diagram of an OLED driven by a SN-TFT.
110
Figure 5.8 Photographs of the OLED driven by SN-TFT under different
inputs showing the turn-on and turn-off of the OLED.
111
Figure 6.1 Comparison of nanotubes separated by density gradient
ultracentrifugation with different purities of semiconducting
nanotubes. (a) Photograph of P3 (unsorted), 95%
semiconducting, and 98% semiconducting single-walled carbon
nanotube solution. (b) UV–Vis–NIR absorption spectra of the
as-prepared P3 arc-discharge nanotubes (blue trace), 95%
semiconducting separated nanotubes (red trace), and 98%
semiconducting separated nanotubes (green trace). (c) FE-SEM
images of 95% semiconducting separated nanotubes deposited on
Si/SiO
2
substrates with APTES functionalization, the average
density is 41 tubes/µm
2
. (d) Length distribution of the 95%
semiconducting separated nanotubes, the average nanotube length
is 0.97 µm. (e) FE-SEM images of 98% semiconducting
separated nanotubes deposited on Si/SiO
2
substrates with APTES
functionalization, the average density is 46 tubes/µm
2
. (f) Length
distribution of the 98% semiconducting separated nanotubes, the
average nanotube length is 0.81 µm. (g) Schematic diagram of a
back-gated SN-TFT. (h) Schematic diagram of an
individual-gated SN-TFT.
121
xv
Figure 6.2 Electrical properties of back-gated SN-TFTs using 95% and 98%
semiconducting nanotubes. (a) Optical microscope image of the
SN-TFT array fabricated on a silicon substrate with 50 nm SiO
2
acting as gate dielectric. (b) FE-SEM image showing the channel
of a typical back-gated SN-TFT with 10 μm channel length. (c,
d) Transfer characteristics (I
D
–V
G
) of the SN-TFTs using 95% (c)
and 98% (d) semiconducting nanotubes with various channel
lengths (4, 10, 20, 50, and 100 μm) and 100 μm channel width
plotted in logarithm scale. (e) Transfer characteristics (red, linear
scale; green, log scale) and g
m
–V
G
characteristics (blue) of a
typical SN-TFT (L = 50 μm, W = 100 μm) using 95%
semiconducting nanotubes. (f) Output characteristics (I
D
–V
D
) of
the same device in panel e. (g) Transfer characteristics (red, linear
scale; green, log scale) and g
m
–V
G
characteristics (blue) of a
typical SN-TFT (L = 100 μm, W = 50 μm) using 98%
semiconducting nanotubes. (h) Output characteristics of the same
device in panel g.
124
Figure 6.3 Statistical study of 175 SN-TFTs using separated nanotubes with
95% and 98% semiconducting nanotubes, as well as comparison
of key device performance metrics. Plot of (a) current density
(I
on
/W), (b) average on/off ratio (I
on
/I
off
), (c) normalized
transconductance (g
m
/W), and (d) device mobility ( μ
device
) versus
channel length for TFTs fabricated on separated nanotubes with
95% (black trace) and 98% (red trace) semiconducting nanotubes.
128
Figure 6.4 Current density (I
on
/W) (a), on/off ratio (b), and mobility (c)
measured at V
D
= 1 V for 12 representative TFTs using 95% and
98% semiconducting nanotubes with channel length of 10 μm. The
red lines represent the average values.
130
Figure 6.5 Integrated inverter circuits using separated carbon nanotubes. (a,
d) Schematic of two different diode-load inverters using SN-TFTs
with different device dimensions. (b, e) Optical microscope
images of these two corresponding inverters. (c, f) Inverter
voltage transfer characteristic (red trace) and voltage gain (blue
trace) of these two corresponding inverters. Both inverters work
with a V
DD
of 3 V and exhibit symmetric input/output behavior.
(g) Inverter voltage transfer characteristics measured at different
supply voltages (V
DD
). (h) Curve showing the dependence
between the inverter voltage gain and supply voltage. Inset:
schematic of the circuit with parasitic resistance at the output
node.
134
xvi
Figure 6.6 Integrated 2-input NAND and NOR circuits using separated
carbon nanotubes. (a, d) Schematic of diode-load 2-input NAND
and NOR circuits using SN-TFTs. (b, e) Optical microscope
images of the corresponding NAND and NOR circuits. (c, f)
Output characteristics of the corresponding NAND and NOR
circuits. The supply voltages for both circuits are V
DD
= 2 V.
Input voltages of 3 and 0V are treated as logic “1” and “0”,
respectively.
138
Figure 7.1 Scalable fabrication of the aluminium back-gated separated
nanotube RF transistors. (a) Schematic showing the
APTES-assisted separated nanotube deposition process for the
separated nanotube RF transistor fabrication. (b) A wafer of the
separated nanotube RF transistors. (c) Optical microscope image
of the nanotube RF transistor. (d) Zoom-in optical microscope
image showing two pairs of channels, the aluminium back-gate,
and Pd S/D extensions of the nanotube RF transistor. (e) SEM
image showing the channel of the device with a channel length of
500 nm.
148
Figure 7.2 DC characteristics of the separated nanotube RF transistors. (a)
Transfer characteristics (I
DS
–V
GS
) of the separated nanotube RF
transistor (L = 0.5 μm, W = 500 μm) measured at various V
DS
. (b)
g
m
–V
GS
characteristics measured at V
DS
= -1 V. (c) Output
(I
DS
–V
DS
) characteristics measured at various V
GS
from -2 to 2V .
151
Figure 7.3 RF characteristics of the separated nanotube RF transistors. (a)
Schematic showing the RF measurement setup. (b) As-measured
S parameters for the separated nanotube RF transistor (dual
channel with L = 0.5 μm, W = 500 μm) from 50 MHz to 5 GHz.
The transistor is biased at V
GS
= 0 V and V
DS
= -1 V for maximum
g
m
. (c) Extrinsic and Intrinsic current gain h
21
, and maximum
available gain G
max
derived from the measured S parameters from
50 MHz to 5 GHz. (d) Transconductance and intrinsic cutoff
frequency as a function of V
GS
.
153
Figure 7.4 RF measurement results of the open and short structures for the
SOLT de-embedding. (a–c) Layout (a), measured S
11
(b), and
measured S
21
(c) of the open structure. (d–f) Layout (d), measured
S
11
(e), and measured S
21
(f) of the short structure.
155
Figure 7.5 Extrinsic and intrinsic current gain (h
21
) of the separated
nanotube RF transistor measured at V
GS
= -0.4 V (a), -0.2 V (b), 0
V (c), and 0.2 V (d).
156
xvii
Figure 7.6 Transfer (I
DS
-V
GS
) characteristics of the separated nanotube RF
transistors measured with forward and backward gate voltage
sweeps.
157
Figure 7.7 Linearity characteristics of the separated nanotube RF transistors.
(a) Schematic showing the two-tone measurement setup to
capture the nonlinearity of the separated nanotube RF transistors.
(b) Single-tone harmonic distortion characterization results
showing the output spectrum of the device with various input
power levels from -10 to 12 dBm. (c) Output power of the
fundamental as a function of input power to extract the 1 dB gain
compression point (P1dB). (d) Two-tone intermodulation
characterization results showing the output spectrum with various
input power levels from 6 to 16 dBm. (e) Output power of the
fundamental and third-order intermodulation as a function of the
input power to extract the IIP3 and OIP3.
159
Figure 7.8 Near f
t
two-tone intermodulation characterization results showing
the output spectrum of the separated nanotube RF transistor with
two input tones at 1 GHz and 1.1 GHz.
161
Figure 8.1 Chirality-controlled metallic carbon nanotube growth using C90.
(a) Schematic diagram illustrating the growth mechanism. (b)
SEM image of the nanotubes grown from C90. (c) AFM image of
the nanotubes grown from C90. (d) Diameter distribution of the
nanotubes grown from C90. Most nanotubes have diameter very
close to the diameter of (5,5) nanotubes (0.68 nm).
168
Figure 8.2 Electrical properties of the carbon nanotubes grown from C90.
(a–d) SEM image (a), AFM image (b), cross section height
information extracted from AFM (c), and transfer/output
characteristics (d) of an individual nanotube transistor. The
diameter of the nanotube in the transistor is around 0.7 nm. (e)
Transfer characteristics of 15 individual nanotube transistors with
10 of them being metallic.
169
Figure 8.3 Chirality-controlled semiconducting nanotube growth using
prepurified (6,5) nanotube seeds. (a) Schematic illustrating the
nanotube cloning process. (b) AFM image and diameter
distribution of the pristine (6,5) nanotubes before CVD cloning. (c)
AFM image and diameter distribution of the (6,5) nanotubes after
cloning.
171
xviii
Figure 8.4 Integrated CMOS logic circuits using separated nanotube thin-film
transistors. (a, b) Transfer characteristics (a) and output
characteristics (b) of a typical separated nanotube TFT before (red)
and after (blue) ALD passivation. (c) Schematic diagram of an
integrated CMOS inverter using air-stable n-type nanotube TFT
obtained from the ALD passivation approach. (d) Voltage transfer
characteristics of the integrated CMOS nanotube inverter. (e, f)
Output characteristics of the integrated CMOS NAND (e) and
NOR (f) logic gates.
173
Figure 8.5 Design of 2-bit nanotube CPU. (a) Datapath and instruction set of
the 2-bit nanotube CPU. (b) Optical microscope image showing
the layout of the completed nanotube TFT CPU.
175
xix
Abstract
In this dissertaion, I discuss the applications of carbon nanotubes in digital
integrated circuits, display electronics, and radio-frequency electronics. Despite the fact
that researchers have previously demonstrated excellent field-effect transistors and
integrated circuits using an individual single-walled carbon nanotube, the real challenge
is to integrate those devices, minimize the device-to-device performance variation, and to
make the fabrication process scalable and compatible with industry standards. To
overcome these challenges, instead of using individual carbon nanotube for electronic
devices, developing assembly techniques that are capable of providing thin films of
highly orderd and uniformly distributed carbon nanotubes is indispensable
With demonstrating scalable, practical, and high performance carbon nanotube
electronics as the major objective of my PhD research, I have developed two material
platforms, both of which are capable of providing high-performance nanotube transistors
at complete wafer-scale. The two material platforms are horizontally aligned carbon
nanotubes and thin-films of preseparated high purity semiconducting carbon nanotubes.
Besides scalable material platforms, many other essential technology components,
including metallic nanotube removal, increasing nanotube density, and methods to obtain
air-stable n-type nanotube transistors have also been demonstrated. On the basis of the
above achievements, I have further demonstrated various kinds of electronic applications
including integrated circuits, display electronics, and radio-frequency electronics.
xx
The dissertation is structured as follows. First, chapter 1 gives a brief introduction
to the electronic properties of carbon nanotubes, which serves as the knowledge
background for the following chapters of the dissertation. In chapters 2, 3, and 4, the
works related to horizontally aligned carbon nanotubes grown using chemical vapor
deposition are presented. The topics include wafer-scale processing of aligned carbon
nanotube electronics, improving nanotube density for better device performance, and
using metal contact engineering for air-stable n-type nanotube transistors and CMOS
integrated circuits. Chapters 5, 6, and 7 discuss the work related to separated nanotube
thin-films, where techniques for separated nanotube thin-film assembly, fabrication of
high-performance separated nanotube thin-film transistors, and applications in integrated
circuits, display electronics, and radio-frequency electronics are explored. Finally, a brief
summary is drawn, and some future research directions are proposed in Chapter 8.
This dissertation, through experimental demonstration, proofs the potential and
feasibility of using carbon nanotubes for future beyond-silicon nanoelectronics and
macroelectronics.
1
Chapter 1. Introduction
1.1 Introduction of carbon nanotubes
Carbon nanotubes were first discovered by Sumio Iijima at NEC Laboratory in
Japan in 1991, when he was using high resolution transmission electron microscopy
(HRTEM) to observe the C
60
grown using arc-discharge method [1]. Carbon nanotubes
can be considered as graphene sheets with honeycomb structure being rolled up into
seamless, hollow cylinders. Depending on the number of graphene layers used, nanotubes
can be categorized into single-walled carbon nanotube (SWNT) and multi-walled carbon
nanotube (MWNT).
SWNTs hold great potiential for the applications in solid-state devices due to its
small size, which is smaller than the most advanced semiconductor devices obtained so
far, as well as its superior electronic properties. For instance, the electronic structure of
carbon nanotube heavily depends on its geometry, i.e. chiral vector, and the nanotubes
can be either metallic or semiconducting. For the semiconducting nanotubes, they have
very long mean free path (in the order of a few hundred nanometers) for the carriers and
thus offer scattering-free ballistic transport [2]. The carrier mobility of semiconducting
nanotubes is experimentally measured to be > 10,000 cm
2
/Vs [3,4], which is much better
than the state-of-the-art silicon transistors, indicating that carbon nanotubes are superior
semiconducting materials. As for metallic nanotubes, they have high current-carrying
capability (> 10
10
A/cm
2
), which is better than the best metal interconnection material,
and overcomes the problem of electromigration due to the strong C-C bond. SWNTs also
2
exhibit excellent thermal conductivity [5], and extraordinary mechanical properties, with
Young’s modulus over 1 TPa [6] and tensile strength over 200 GPa. Furthermore, due to
the ultra-high surface-to-volume ratio of carbon nanotubes, they can be also employed to
work as high-performance chemical sensors [7] and biosensors [8]. In a word, carbon
nanotubes, due to their unique nanostructure with remarkable electronic and mechanical
properties, have stimulated enormous interest for both fundamental research and various
kinds of future applications.
1.2 Electrical properties of carbon nanotubes
The electrical property of the nanotube depends on how one rolls the graphene
sheet to make a nanotube. As shown in Figure 1.1 [9], we can cut the graphene sheet
along the lines of OB and AB’ and then roll it up into a nanotube, so that O meets A, and
B meets B’. The chiral vector (C
h
) OA
u uu r
is defined on the hexagonal lattice as
12
OA ma na =+
uu urur uu r
, where
1
a
ur
and
2
a
u u r
are two basic vectors shown in Figure 1.1, and m
and n are two integers that can be used to fully define the structure of this nanotube. The
chiral angle ( θ) is measured relative to the direction defined by
1
a
u r
.
For instance, the corresponding chiral vector in Figure 1.1 is (m, n) = (4, 2), and
the unit cell of this nanotube is bounded by the rectangle OBB’A. Different types of
carbon nanotubes have different values of m and n. Figure 1.2 displays the schematic
diagram of three kinds of carbon nanotubes: Armchair, Zigzag, and Chiral nanotubes.
Armchair nanotubes (named so, because the edge configuration is similar to an armchair)
3
have m = n and a chiral angle of 30°. Zigzag nanotubes correspond to either m or n is 0,
and have a chiral angle of 0°. The rest of the nanotubes are generally called chiral
nanotubes. Based on the chiral vector (m, n), we can further calculate the geometric
parameters of the carbon nanotube such as the diameter
22
3//
tCC h
da mmnn C π π
−
=++= , and chiral angle
1
tan [ 3 /(2 )] mn m θ
−
=+ [9].
Figure 1.1 Schematic diagram of graphene layer. A carbon nanotube can be constructed by cutting a graphene layer
along lines of OB and AB’, and then rolling it up into a tube, so that O meets A and B meets B’. Vector OA is called the
chiral vector (C
h
) [9].
The electronic structure of a SWNT can be obtained simply from that of graphene
[10]. In graphene, three σ bonds hybridize in a sp
2
configuration, while the other 2p
z
orbital, which is perpendicular to the graphene plane, makes π covalent bonds. It is
known that the π electrons are valence electrons which are relevant for the transport and
4
other solid state properties. Therefore, only π energy bands for graphene are considered
to determine the electrical properties of graphene. To find the 2D energy dispersion
relations of graphene, we solve the eigenvalue problem for a (2×2) Hamiltonian H and a
(2×2) overlap integral matrix S, associated with the two inequivalent carbon atoms in 2D
graphene [10],
20
02
()
()
p
p
f k
H
fk
εγ
γε
∗
− ⎛⎞
=
⎜⎟
−
⎝⎠
and
1()
() 1
sf k
S
sf k
∗
⎛⎞
=
⎜⎟
⎝⎠
(1)
where ε
2p
is the site energy of the 2p atomic orbital and
/3 /2 3
() 2 cos
2
xx
y ik a ik a
ka
fk e e
−
=+ (2)
where
12
3
CC
aa a a
−
== = .
Figure 1.2 Schematic diagrams of Armchair, Zigzag, and Chiral nanotubes.
5
Solution of the secular equation det(H-ES) = 0 implied by Eq. (1) leads to the eigenvalues
20
2
()
()
1()
p
gD
k
Ek
sk
ε γω
ω
±
±
=
m
(3)
where γ
0
is the C-C transfer energy, s denotes the overlap of the electronic wave function
on adjacent sites, and E
+
and E
−
correspond to the π* and π energy bands, respectively.
Here we conventionally use γ
0
> 0. The function () k ω in Eq. (3) is given by
2
2
3
() () 1 4cos cos 4cos
22 2
yy
x
ka ka
ka
kfk ω==+ + (4)
Figure 1.3 The energy dispersion relations for graphene with γ
0
= 3.013 eV, s = 0.129 and ε
2p
= 0. The inset shows the
energy dispersion along the high symmetry lines between the Γ, M, and K points [10].
By pluging Eq. (4) into Eq. (3), we can obtain the electronic energy dispersion
relations for graphene as a function of the two-dimensional wave vectors k in the
Brillouin zone, and the result is plotted in Figure 1.3 [10]. The plot indicates that an
6
isolated sheet of graphene is a zero-gap semiconductor whose electronic structure near
the Fermi energy is given by an occupied π band and an empty π* band. These two bands
have linear dispersion and, as shown in Figure 1.3, meet at the Fermi level at the K point
in the Brillouin zone. The Fermi surface of an ideal graphene sheet consists of the six
corner K points.
The band structure of the nanotube can be further derived based on the results
from graphene. When forming a tube, owing to the periodic boundary conditions imposed
in the circumferential direction, the electron wavevector along that direction is quantized.
As shonw in Figure 1.4 [10], the wave vector (K
1
) along the circumferential direction of
nanotube becomes quantized due to the periodic boundary condition, and the wave vector
(K
2
) along the nanotube axis remains continuous for a nanotube of infinite length.
Therefore, based on the energy dispersion relations of graphene, the 1D energy dispersion
relations of a SWNT are given by
2
21
2
( ) , , = 1, ,N
gD
E k E k k and
TT
μ
ππ
μμ
±±
⎛⎞
⎛⎞
=+ −<<
⎜⎟
⎜⎟
⎜⎟
⎝⎠
⎝⎠
Κ
Κ
Κ
K (5)
where T is the magnitude of the translational vector T, k is a 1D wave vector along the
nanotube axis, and N denotes the number of hexagons of the graphene honeycomb lattice
that lie within the nanotube unit cell. T and N can be calculated using the following
equations,
33
ht
RR
Cd
T
dd
π
== , and
22
2( )
R
nm mn
N
d
++
= (6)
7
The N pairs of energy dispersion curves given by Eq. (5) correspond to the cross
sections of the cuts made on the lines of
22 1
/ k μ + KK K on the graphene energy
dispersion relationship shown in Figure 1.3. From the equation, we can find that due to
the quantization in the nanotube circumferential direction, only a certain set of k states of
the planar graphene sheet is allowed, as indicated by the lines in Figure 1.4. Depnding on
the chirality (m, n) of the nanotube, if the allowed states (the lines in Figure 1.4) pass
through a K point of the 2D Brillouin Zone, then the nanotube has a zero energy gap and
a nonzero density of states at the Fermi level, resulting in a one-dimensional metal with 2
linear dispersing bands. On the other hand, if the cutting lines do not pass through any of
the K points, then the nanotube is semiconducting with a finite energy gap between the
valence and conduction bands. Moreover, it is important to note that the states near the
Fermi energy in both the metallic and the semiconducting nanotubes are all from states
near the K point, and hence their transport and other properties are related to the
properties of the states on these allowed lines. For example, the conduction band and
valence bands of a semiconducting nanotube come from states along the lines closest to
the K point.
The general rules for the metallicity of the single-walled carbon nanotubes are as
follows: (m, m) nanotubes (armchair nanotubes) are all metallic; (m, n) nanotubes with
m-n = 3j, where j is a nonzero integer, are very tiny-gap semiconductors; and all others
are large-gap semiconductors. Based on this rule of thumb, we can infer that one third of
the nanotubes are metallic and the other two thirds are semiconducting. Moreover, the
bandgap for a semiconducting nanotube is dependent on its diameter. As the nanotube
8
radius R increases, the bandgaps of the large-gap and tiny-gap nanotubes decreases with
1/R and 1/R
2
dependence, respectively.
Figure 1.4 The wave vector k for one-dimensional carbon nanotubes is shown in the two-dimensional Brillouin zone of
graphene (hexagon) as bold lines for (a) metallic and (b) semiconducting carbon nanotubes [10].
As an example, Figure 1.5 shows the band structures of two nanotubes with
different chiralities, showing different electrical propertie [11]. Figure 1.5a corresponds
to a (3, 3) armchair nanotube, which according to the metallicity rule, should be metallic.
From the diespersion relations, we can find that the allowed states include the K point,
therefore the nanotube has zero bandgap as shown in the top right figure. For the case of
Figure 1.5b, which represents the band structure of a (4, 2) semiconducting nanotube, the
allowed states do not include the K point, and one can clearly see the existance of a band
gap from the E-k relationship.
9
Figure 1.5 Dispersion relations for a metallic (3,3) (upper) and a semiconducting (4,2) nanotube (lower) [11].
Furthermore, based on the energy dispersion relations, the 1D density of states
(DOS) in units of states/C-atom/eV of the nanotube can be calculated by the following
equation,
1
1
() ( ( ) )
2 ()
N
T
DE E k EdE
N dE k
dk
μ
μ
μ
δ
π
±
±
±=
=−
∑∑
∫
(7)
Figure 1.6 shows the comparison of DOS for semiconducting (10, 0) and metallic
(9, 0) nanotubes [12]. We can notice the difference between these two cases near the
Fermi level E
F
located at E = 0, where the DOS is zero for semiconducting nanotubes,
and is non-zero for metallic ones. In addition, the more interesting things are the kinks in
DOS, which are the characteristics of 1D systems and are called Van Hove singularities.
a
b
10
These Van Hove singularities are very important for determining many solid state
properties of carbon nanotubes, such as the spectra observed by scanning tunneling
spectroscopy, optical absorption, and resonant Raman spectroscopy.
Figure 1.6 Density of states for a (10,0) semiconducting nanotube and a (9,0) metallic nanotube [12].
1.3 Carbon nanotubes for beyond-silicon electronics
In 1965, Gordon E. Moore predicted that the number of transistors in the
cutting-edge integrated circuit chips is doubling approximately every two years without
significant increase in the cost, allowing more functionality and complexity to be packed
into a single chip [13]. This prediction is known as the famous “Moore’s Law” and it has
remained to be true for more than 40 years. The driving force for Moore’s Law is the
continued scaling-down of both horizontal and vertical physical dimensions of
silicon-based complementary metal oxide semiconductor (CMOS) transistors. As of 2011,
the semiconductor industry has already reached 32 nm technology node for
manufacturing, 22 nm and 15 nm under research and development. By making the
transistors progressively smaller, the device performance can be improved, and power
consumption and cost per transistor can be reduced. However, it is unfortunately that
11
such scaling-down will not continue forever and will probably reach its ultimate limit by
the year 2020 as forcasted in the International Technology Roadmap for Semiconductors
(ITRS) 2009 [14].
The reason is that as the size of the silicon-based CMOS transistors approaching
atomistic and quantum mechanical physics boundaries, many challenges start to reveal.
First of all, from the transistor point of view, as the gate dielectric gets thinner and
thinner, the gate leakage current increases; due to short channel effect, the off-current and
subthreshold slope increases; shallower junction leads to increased parasitic source/drain
resistance; increased doping leads to mobility degradation; operating voltage also gets
lower and lower, etc. Secondly, line edge/width roughness, variations in oxide thickness,
fixed charges/traps, and random dopant fluctuation lead to increased process variability
and large device-to-device variations. Besides, there are also other technical challenges
such as photolighotraphy resolution limitation, power-thermal challenges due to
increased power density, and reliability challenges due to reduced lift-time. Furthermore,
the concern is not only about the inability of the devices themselves to operate steadily at
extremly small dimensions, but also the economical constraints due to the increased cost
for research, development, and manufacture.
To overcome the above-mentioned challenges for the year 2020 and beyond,
alternative device structures, architectures, or materials are essential. The research
options include non-planar silicon transistors, III-V compound semiconductors,
nanowires, carbon nanotubes, spin-based field-effect transistors, etc. As discussed
previously, carbon nanotubes possess extraordinary electrical properties and are
12
envisioned as one of the most promising candidates for beyond-silicon electronics. With
a diameter of only 1 to 2 nm, they are already significantly smaller than the latest silicon
transistors. Besides, depending on the chiral vector, they can be either metallic or
semiconducting. For the semiconducting nanotubes, they have very long carrier mean
free path, offer dissipationless ballistic transport [2], and the mobility can be as high as
100,000 cm
2
/Vs [3,4]. For the metallic nanotubes, the current-carrying capability is way
better than copper, free of electromigtration, and are ideal for interconnections [15-17].
With such superior electronic properties, carbon nanotubes have wide range of
applications in nanoelectronics and macroelectronics. These applications include but are
not limited to integrated circuits, radio-frequency electronics, flexible electronics, display
electronics, and printed electronics.
1.4 Outline of the dissertation
Researchers have previously demonstrated excellent field-effect transistors [18-20]
and integrated circuits [21-24] using an individual single-walled carbon nanotube.
Ballistic nanotube transistors with on-current density (I
on
/W) larger than 3000 µA/µm and
hole moblity larger than 4000 cm
2
V
-1
s
-1
, which are way better than silicon, has also been
achieved [2]. Nevertheless, although significant progress has been made with individual
nanotube transistors, the real challenge is to integrate those devices, minimize the
device-to-device performance variation, and to make the fabrication process scalable and
compatible with industry standards. To overcome these challenges, instead of using
individual carbon nanotube for electronic devices, developing assembly techniques that
13
are capable of providing thin-films of highly orderd and uniformly distributed carbon
nanotubes is indispensable.
Figure 1.7 Outline of the dissertation.
With demonstrating scalable, practical, and high performance carbon nanotube
electronics as the major objective of my PhD research, the outline of this dissertation can
be briefly summarized in Figure 1.7. To address the scalability issue, I have developed
two material platforms, both of which are capable of providing high-performance
nanotube transistors at complete wafer-scale. The two material platforms are horizontally
aligned carbon nanotubes and thin-films (random, uniform networks) of preseparated
high purity semiconducting carbon nanotubes, whose scanning electron microscopy
images are exhibited in Figure 1.7. Besides scalable material platforms, many other
essential technology components, including metallic nanotube removal, increasing
nanotube density, and methods to obtain air-stable n-type nanotube transistors have also
14
been demonstrated. On the basis of the above achievements, I have further demonstrated
various kinds of electronic applications including integrated circuits, radio-frequency
electronics, display electronics, and tranparent/flexible electronics using carbon
nanotubes.
The dissertation is structured as follows. First, chapter 1 gives a brief introduction
to the electronic properties of carbon nanotubes, which serves as the knowledge
background for the following chapters of the dissertation. In chapters 2, 3, and 4, the
works related to horizontally aligned carbon nanotubes grown using chemical vapor
deposition are presented. The topics include wafer-scale processing of aligned carbon
nanotube electronics, improving nanotube density for better device performance, and
using metal contact engineering for air-stable n-type nanotube transistors and CMOS
integrated circuits. Chapters 5, 6, and 7 discuss the work related to separated nanotube
thin-films, where techniques for separated nanotube thin-film assembly, fabrication of
high-performance separated nanotube thin-film transistors, and applications in integrated
circuits, display electronics, and radio-frequency electronics are explored. Finally, a brief
summary is drawn, and some future research directions are proposed in Chapter 8.
To be more specific, in chapter 2, I report the wafer-scale processing of aligned
carbon nanotube devices and integrated circuits, including progress on essential
technological components such as wafer-scale synthesis of aligned nanotubes,
wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal, chemical
doping, and defect-tolerant integrated circuit design. We have achieved synthesis of
massively aligned nanotubes on complete 4 inch quartz and sapphire wafers, which were
15
then transferred to 4 inch Si/SiO
2
wafers. CMOS-analogous fabrication was performed to
yield transistors and circuits with features down to 0.5 μm, with high current density ~ 20
μA/μm, and good on/off ratios. In addition, chemical doping has been used to build fully
integrated nanotube inverter with a gain of 5, and a defect-tolerant design has been
employed to demonstrate more sophisticated logic gates such as NAND and NOR.
In chapter 3, I report the progress on metal contact engineering for n-type aligned
nanotube transistors and CMOS integrated circuits. By using Pd as source/drain contacts
for p-type transistors, small work function metal Gd as source/drain contacts for n-type
transistors, and evaporated SiO
2
as a passivation layer, I have achieved n-type transistor,
PN diode, and integrated CMOS inverter with an air-stable operation. Compared with
other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine
doping, etc., using low work function metal contacts for n-type nanotube devices is not
only air-stable but also integrated circuit fabrication compatible. This platform shows
significant advantage in terms of scalability and reproducibility and suggests a practical
and realistic approach for nanotube-based CMOS integrated circuit applications.
Chapter 4 discusses the combined use of low-pressure chemical vapor deposition
and stacked multiple transfer to achieve ultra high-density aligned nanotubes. By using
an optimized nanotube synthesis recipe, I have achieved aligned carbon nanotube array
with density as high as 30 tubes/µm. In addition, a facile stacked multiple transfer
technique has been developed to further increase the nanotube density to 55 tubes/µm.
Furthermore, high-performance submicron carbon nanotube field-effect transistors have
been fabricated on the high-density aligned nanotubes, and benchmarking with the
16
aligned carbon nanotube transistors in the literature indicates that our devices exhibit the
best performance so far, which can be attributed to both the increased nanotube density
and scaling down of channel length. This work shows the great potential of using such
high-density aligned nanotubes for high performance nanoelectronics and analog/RF
applications.
Chapter 5 introduces the wafer-scale processing of thin-film transistors using
semiconducting enriched nanotubes separated by density gradient ultracentrifugation and
their application in display electronics. Key technology components including
wafer-scale assembly of high-density, uniform separated nanotube networks, high-yield
fabrication of devices with superior performance, and demonstration of organic
light-emitting diode (OLED) switching controlled by a separated nanotube thin-film
transistor will be discussed. I have achieved solution-based assembly of high density and
uniform networks with high-purity semiconducting carbon nanotubes on complete 3 inch
Si/SiO
2
wafers, and further carried out wafer-scale fabrication to produce transistors with
high yield (> 98%), small sheet resistance (~ 25 k Ω/sq), high current density (~ 10
μA/μm), excellent on/off ratios (> 10
4
), and superior mobility (~ 52 cm
2
V
-1
s
-1
). In
addition, OLED control circuit has been demonstrated and the modulation in the output
light intensity exceeds 10
4
. This approach can be easily scaled to large areas and could
serve as critical foundation for future nanotube-based display electronics.
In chapter 6, I report the application of the above-discussed high-performance
separated nanotube thin-film transistors for macroelectronic integrated circuits. I have
systematically compared the performance of thin-film transistors using differenct purities
17
of semiconducting nanotubes, and the results suggest that while lower purity (95%)
semiconducting nanotubes are ideal for applications requiring high mobility (up to 67
cm
2
V
-1
s
-1
) such as analog and radio frequency applications, higher purity (98, 99%)
semiconducting nanotubes are ideal for applications requiring high on/off ratios (>10
4
with channel length down to 4 μm). Based on the above design considerations, integrated
logic gates such as inverter, NAND, and NOR have been designed and demonstrated and
symmetric input/output behavior is achieved, which is crucial for the cascading of
multiple stages of logic blocks for more sophisticated integrated circuits.
Chapter 7 reports the radio frequency (RF) and linearity performance of
transistors using high-purity semiconducting carbon nanotubes. RF transistors with
channel lengths down to 500 nm are fabricated and such transistors exhibit cutoff
frequency (f
t
) of 5 GHz and maximum oscillation frequency (f
max
) of 1.5 GHz. Besides
the cutoff frequency, the other important figure of merit for the RF transistors is the
device linearity. For the first time, I report carbon nanotube RF transistor linearity
metrics up to 1 GHz. Without the use of active probes to provide the high impedance
termination, the measurement bandwidth is therefore not limited, and the linearity
measurements can be conducted at the frequencies where the transistors are intended to
be operating. I conclude that semiconducting nanotube-based transistors are potentially
promising building blocks for highly linear RF electronics and circuit applications.
Chapter 8, in the end, summarizes this dissertation and proposes two future
research directions including chirality-controlled carbon nanotube synthesis, and flexible
central processing unit (CPU) using separated carbon nanotube thin-film transistors.
18
Chapter 1. References
1. Iijima, S. Helical Microtubules of Graphitic Carbon. Nature 1991, 354, 56–58.
2. Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654–657.
3. Durkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39.
4. Zhou, X.; Park, J. Y.; Huang, S.; Liu, J.; McEuen, P. L. Band Structure, Phonon
Scattering, and the Performance Limit of Single-Walled Carbon Nanotube
Transistors. Phys. Rev. Lett. 2005, 95, 146805-1–146805-4.
5. Ruoff, R. S.; Lorents, D. C. Mechanical and Thermal Properties of Carbon
Nanotubes. Carbon 1995, 33, 925–930.
6. Treacy, M. M. J.; Ebbesen, T. W.; Gibson, J. M. Exceptionally High Young's
Modulus Observed for Individual Carbon Nanotubes. Nature 1996, 381, 678–680.
7. Kong, J.; Franklin, N. R.; Zhou, C.; Chapline, M. G.; Peng, S.; Cho, K.; Dai, H.
Nanotube Molecular Wires as Chemical Sensors. Science 2000, 287, 622–625.
8. Chen, R. J.; Bangsaruntip, S.; Drouvalakis, K. A.; Kam, N. W. S.; Shim, M; Li, Y.;
Kim, W.; Utz, P. J.; Dai, H. Noncovalent Functionalization of Carbon Nanotubes
for Highly Specific Electronic Biosensors. Proc. Nat. Acad. Sci. 2003, 100,
4984–4989.
9. Dresselhaus, M. S.; Dresselhaus, G.; Avouris, Ph. (Eds.) Carbon Nanotubes –
Synthesis, Structure, Properties, and Applications. Springer: Berlin, 2001.
10. Saito, R.; Dresselhaus, G.; Dresselhaus, M. S. Physical Properties of Carbon
Nanotubes. Imperial College Press: London, 1998.
11. Appenzeller, J.; Joselevich, E.; Honlein, W. Carbon Nanotubes for Data Processing.
Waser, R. (Ed.) Chapter 19 in Nanoelectronics and Information Technology.
Wiley-VCH: Weinheim, 2003.
12. Saito, R.; Fujita, M.; Dresselhaus, G.; Dresselhaus, M. S. Electronic Structure of
Chiral Graphene Tubules. Appl. Phys. Lett. 1992, 60, 2204–2206.
13. Moore, G. E. Cramming More Components onto Integrated Circuits. Electronics
1965, 38, 114–117.
19
14. International Technology Roadmap for Semiconductors 2009 Edition Executive
Summary.
http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_ExecSum.pdf
15. Li, J.; Ye, Q.; Cassell, A.; Ng, H. T.; Stevens, R.; Han, J.; Meyyappan, M.
Bottom-Up Approach for Carbon Nanotube Interconnects. Appl. Phys. Lett. 2003,
82, 2491–2493.
16. Naeemi, A.; Meindl, J. Design and Performance Modeling for Single-Walled
Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale
Integrated Systems. IEEE Transactions on Electron Devices. 2007, 54, 26–37.
17. Close, G. F.; Yasuda, S.; Paul, B.; Fujita, S.; Wong, H.-S. P. A 1 GHz Integrated
Circuit with Carbon Nanotube Interconnects and Silicon Transistors. Nano Lett.
2008, 8, 706–709.
18. Tans, S.; Verschueren, A.; Dekker, C. Room-Temperature Transistor Based on a
Single Carbon Nanotube. Nature 1998, 393, 49–52.
19. Javey, A.; Guo, J.; Farmer, D.; Wang, Q.; Wang, D.; Gordon, R.; Lundstrom, M.;
Dai, H. Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts
and High- κ Gate Dielectrics. Nano Lett. 2004, 4, 447–450.
20. Javey, A.; Guo, J.; Farmer, D.; Wang, Q.; Yenilmez, E.; Gordon, R.; Lundstrom, M.;
Dai, H. Self-Aligned Ballistic Molecular Transistors and Electrically Parallel
Nanotube Arrays. Nano Lett. 2004, 4, 1319–1322.
21. Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon
Nanotube Transistors. Science 2001, 294, 1317–1320.
22. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, P. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
23. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays
for Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2,
929–932.
24. Chen, Z.; Appenzeller, J.; Lin, Y .; Oakley, J. S.; Rinzler, A. G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, P. An Integrated Logic Circuit Assembled on a Single
Carbon Nanotube. Science 2006, 311, 1735.
20
Chapter 2. Wafer-Scale Nanotube-on-Insulator Approach for
Submicron Devices and Integrated Circuits Using Aligned
Nanotubes
2.1 Introduction
Single-walled carbon nanotubes (SWNTs) are expected to offer much better
performance for electronics than traditional silicon due to their high carrier mobility and
current-carrying capacity. Nanotubes can work as ballistic and high mobility transistors
[1,2], and integrated logic circuits such as inverters and ring-oscillators [3-7] have been
constructed using individual nanotubes. Recently, significant advance has been made
using randomly grown nanotube networks for flexible devices and circuits [8]; however,
the stripe-patterning used to remove heterogeneous percolative transport through metallic
nanotube networks cannot be easily scaled to submicron regime, and only PMOS
transistors were demonstrated for the reported circuits. In parallel, aligned nanotubes,
with potentially significant advantages over randomly grown nanotubes in terms of
manipulation and integration of nanotubes for device applications, have been grown on
either sapphire or quartz substrates from several research groups [9-12], or deposited on
solid or flexible substrates by dielectrophoresis method for submicron RF devices [13-14].
Based on massively aligned SWNTs grown on sapphire, we have further reported a
high-yield, registration-free nanotube-on-insulator approach to fabricate nanotube devices
[15], in a way analogous to the silicon-on-insulator process adopted by the semiconductor
industry. The aligned nanotube devices such as transistors [16], RF devices [17], and high
21
frequency transistor oscillator [18] have also been made based on aligned nanotubes on
quartz with good uniformity over chip scale and minimized parasitic capacitance.
However, previous studies [15-18] on aligned nanotube devices usually share the
following drawbacks: 1) small sample size which prevents wafer-scale fabrication and
integration, 2) micron-scale channel length that limits the transistor performance, and 3) a
lack of controlled doping that prevented truly integrated circuits with p-type and n-type
transistors on one chip. To demonstrate truly integrated nanotube circuits and wafer-scale
fabrication, technological components such as wafer-scale synthesis and transfer of
aligned nanotubes, and integrated submicron-scale device fabrication and tuning, are
highly desired for the high-performance integrated nanotube circuits. In addition,
defect-tolerant circuit design would also be an essential feature for such integrated
nanotube circuits.
Here, we report our recent advance on full wafer-scale processing of massively
aligned carbon nanotube arrays for high-performance submicron channel transistors and
integrated nanotube circuits, including the following essential components. 1) The
massive highly aligned nanotubes were successfully grown on 4 inch quartz and sapphire
wafers via meticulous temperature control, and then transferred onto Si/SiO
2
wafers using
a facile transfer printing method. 2) Wafer-scale device fabrication was performed on 4
inch Si/SiO
2
wafer to yield submicron channel transistors and circuits with high
on-current density ~ 20 μA/μm and good on/off ratios. 3) Chemical doping methods
[19-23] were successfully demonstrated to get CMOS inverters with a gain ~5. 4)
Defect-tolerant circuit design for NAND and NOR was proposed and demonstrated to
22
guarantee the correct operation of logic circuit, regardless of the presence of mis-aligned
or mis-positioned nanotubes. Our wafer-scale nanotube-on-insulator processing using
multiple aligned nanotubes shows significant advantage over conventional processes
based on individual nanotubes with respect to current output and device uniformity, and
suggests a practical and realistic approach for integrated nanotube circuit applications.
2.2 Wafer-scale aligned carbon nanotube synthesis
Aligned nanotube growth was previously limited to small pieces of quartz or
sapphire substrates [15,16], as growing nanotubes over complete 4 inch wafers has been
very difficult due to the quartz wafer breakage during temperature ramping and the
difficulty in uniform growth on complete wafers. Here, we successfully synthesized
aligned SWNTs arrays (Figure 2.1 and 2.2a) on 4 inch quartz and sapphire wafers by
overcoming the above-mentioned technical difficulties.
Figure 2.1 Photograph of a 4 inch quartz wafer with aligned nanotubes and patterned electrodes. Inset: SEM images of
aligned nanotubes between electrodes at different locations of the wafer.
23
First, both quartz and sapphire wafers were annealed to improve the alignment of
nanotubes at 900 °C and 1100 °C for 1.5 hrs in air, respectively. In particular, the
thermally robust a-plane sapphire wafer can be annealed at 1100 °C at high ramping rate
(45 °C/min) as shown in Figure 2.2c, while the 4 inch quartz wafer required meticulous
temperature control (extremely slow ramping rate < 1 °C/min) to avoid wafer breakage
due to the phase transformation [24] of quartz from alpha (α) to beta (β) around 573 °C,
as shown in Figure 2.2d.
Figure 2.2 Wafer-scale aligned carbon nanotube synthesis. (a) Photograph of a 4 inch sapphire wafer with aligned
nanotubes. (b) Schematic diagram of 9 feet-long furnace for wafer-scale nanotube growth. (c) and (d) SEM images of
aligned nanotubes and temperature flow charts for the annealing and the nanotube growth on sapphire and quartz wafer,
respectively.
(b)
(c)
(d)
(a)
24
In addition, we used the same total gas flow rate for both the ramping up step
(3000 sccm Ar and 600 sccm H
2
) and the growth step (3000 sccm CH
4
and 600 sccm H
2
)
to minimize the temperature perturbation. The uniform temperature on entire wafer is
also an essential requirement for the uniform wafer-scale growth of aligned nanotubes on
both quartz and sapphire wafers. Therefore, a 9 feet-long growth furnace with three-zone
temperature controller (Figure 2.2b) was used for this study.
2.3 Wafer-scale aligned nanotube transfer
After growth (Figure 2.3a), we used a facile transfer method to transfer the
aligned nanotubes from 4 inch quartz or sapphire wafers to 4 inch Si/SiO
2
wafers as
following. A 100 nm thick gold film was first deposited onto the aligned SWNTs on the
original substrate to ensure conformal contact between nanotubes and the gold film
(Figure 2.3b). To transfer SWNTs onto the targeting substrate, our key innovation is the
use of Revalpha thermal tape (from Nitto Denko), which has an interesting
temperature-dependent adhesive property: it is highly adhesive at room temperature, but
loses its adhesion at a moderate temperature of 120 °C. This tape was pressed against the
original substrate with nanotubes covered by the gold film, and then peeled off together
with the gold film and nanotubes (Figure 2.3c). The nanotube / gold film / thermal tape
trilayer structure was pressed against the target substrate, and the tape was then released
by simply heating to 120 °C (Figure 2.3d). The gold film was subsequently removed
using gold etchant, thus leaving a nice array of massively aligned SWNTs on the target
substrate (Figure 2.3e). SEM images of transferred nanotubes on Si substrate with 50
25
nm thickness of SiO
2
are shown in inset of Figure 2.3e. The device fabrication based on
transferred nanotubes on 4 inch Si/SiO
2
wafer (Figure 2.3f) was obtained by standard
silicon CMOS technology such as projection photolithography using a stepper with 0.5
μm resolution for submicron device patterning, metal deposition for electrodes, and
high- κ dielectric (HfO
2
or Al
2
O
3
) deposition for gate dielectric. Figure 2.4 shows the
photo images of nanotube devices built on a 4 inch Si/SiO
2
wafer, and a typical chip is
consisted of 5 different types of devices, including back-gated transistors, top-gated
transistors, CMOS inverters, and CMOS NOR and NAND logic gates.
Figure 2.3 Wafer-scale aligned nanotube synthesis, transfer, and fabrication. (a) Schematic diagram and photograph of
full wafer synthesis of aligned nanotubes on a 4 inch quartz wafer. Inset shows SEM image of aligned nanotubes. (b–f)
Schematic diagrams and photographs showing the transfer procedure, i.e., gold film deposition (b), peeling off the gold
film with nanotubes (c), transfer of the gold film with nanotubes onto a Si/SiO
2
substrate (d), etching away the gold
film (e), and device fabrication on the transferred nanotube arrays (f).
quartz
gold film deposition
b
Si/SiO
2
substrate
d
Transfer gold film with CNTs
CNTs
quartz
1um
a
Aligned CNTs growth
quartz
Thermal tape
c
Peel-off gold film with CNTs
e
Etch away gold film
Si/SiO
2
substrate
Transferred CNTs
2um
f
Electrode patterning
Si/SiO
2
substrate
electrodes
CNTs
26
Figure 2.4 Photo images of nanotube devices and circuits built on a 4 inch Si/SiO
2
wafer: 1, back-gated transistor; 2,
top-gated transistor; 3, CMOS inverter; 4, NOR logic gate; and 5, NAND logic gate.
2.4 Field-effect transistors using aligned carbon nanotubes
We first characterized the electrical properties of nanotube transistors as basic
components for nanotube circuits. Compared with previous work [15,16] with micron or
tens of micron channel length, we have pushed the channel length to submicron. Figure
2.5 shows a schematic diagram, SEM image, and electrical characteristics of back-gated
nanotube devices.
27
Figure 2.5 Characteristics of back-gated transistors down to submicron channel length. (a) Schematic diagram of a
back-gated transistor built on transferred nanotubes. (b) SEM image of a transistor with submicron channel length. (c)
Transfer (I
ds
–V
g
) characteristics of transistors with different L = 0.5, 0.75, 1, 2, 5, 10, and 20 μm, and W = 100 μm. (d)
Normalized on and off- current densities and transconductance (g
m
) derived from (c). (e–g) Electrical breakdown study
of the transistors; I
ds
–V
g
curves for a typical transistor after consecutive electrical breakdown (e), I
ds
–V
g
curves and
I
ds
–V
ds
curves of the transistor in (e) after three rounds of electrical breakdown (f), and Statistics of devices before and
after electrical breakdown (g). (h) I
ds
–V
g
curves of two representative devices, with one (black) and two (red) steps of
transfer, respectively. Inset illustrates the multiple transfer process.
10
-6
10
-5
10
-4
I
ds
(A)
-10 -5 0 5 10
V
g
(V)
Before Breakdown
1st Breakdown
2nd Breakdown
3rd Breakdown
+ Before electrical breakdown
+ After electrical breakdown
-120
-100
-80
-60
-40
-20
0
I
ds
(μΑ)
-10 -5 0 5 10
V
g
(V)
-60
-40
-20
0
I
ds
(μΑ )
-1.5 0.0
V
ds
(V)
-1 V
-0.8 V
-0.6 V
-0.4 V
-0.2 V
f e
g h
1 µm
b
500 nm
a
c d
1.5
1.0
0.5
I
ds
(m A )
-10 -5 0 5 10
V
g
(V)
L = 0.5 µm
L = 0.75 µm
L = 1 µm
L = 2 µm
L = 5 µm
L = 10 µm
L = 20 µm
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I
ds
(mA )
-10 -5 0 5 10
V
g
(V)
2nd transfer
1st transfer
80
60
40
20
g
m
(μ S)
5 6 7 8
1
2 3 4 5 6 7 8
10
2
L(μm)
2
4
6
8
10
-6
2
4
6
8
10
-5
I
ds
/W (A/µm )
g
m
I
on
I
off
10
-8
10
-7
10
-6
10
-5
10
-4
I
on
/W (A / μm)
10
1
10
2
10
3
10
4
I
on
/I
off
V
g
from -8V to 8V
28
Based on the transferred nanotubes on Si with 50 nm SiO
2
, 5 Å Ti and 70 nm Pd
were deposited as Source/Drain electrodes (Figure 2.5a), followed by the removal of
nanotubes outside the active channel with O
2
plasma. Such devices were made with
channel length (L) of 0.5, 0.75, 1, 2, 5, 10, 20 μm and channel width (W) of 2, 5, 10, 20,
50, 100 μm. The SEM image in Figure 2.5b shows a typical submicron channel device
with 2-3 tubes/ μm. Figure 2.5c exhibits the current-gate voltage (I
ds
–V
g
) characteristics of
the transistors at V
ds
= 1 V with W = 100 μm and various channel lengths, showing
on-currents at V
g
= -10 V varying from several tens of μA to 1.8 mA, reversely
proportional to the channel length. The normalized on and off- current densities (I
ds
/W)
are further deduced from the same devices in Figure 2.5c, and the transconductances (g
m
)
are also calculated from the linear proportion of the transfer curves, as shown in Figure
2.5d. The highest on-current density in a transistor with W = 100 μm and L = 0.5 μm is up
to 20 μA/ μm, and g
m
is close to 100 μS. This on-current density is the highest achieved so
far for aligned nanotube transistors, as a result of the submicron channel length we used.
The performance of these devices can be improved even further with higher-density
nanotubes.
In addition, the effective mobility ( μ) of the device was calculated by applying the
following equation [16]
d
dw g
dI L
VCW dV
μ=⋅ (1)
where L is the channel length, and W is the channel width. C
w
is the specific capacitance
per unit area of the aligned nanotube channel calculated as follow,
29
1
0
1 sinh(2 )
log
2
w
Q
s
D
C
tD
C
RD
π
πε ε π
−
=
⎡ ⎤
⎡ ⎤
+⋅
⎢ ⎥
⎢ ⎥
⎣ ⎦
⎣ ⎦
(2)
where D is the density of nanotubes, C
Q
is the quantum capacitance of nanotubes, t is the
thickness of the dielectric layer, R is the radius of nanotubes, and ε
s
is the dielectric
constant at the interface where the nanotubes are placed. For our case, a device with 50
μm channel length was chosen to minimize the effects of contact, and device mobility
was estimated using the maximum g
m
which was extracted from the I
ds
–V
g
curves as
shown in Figure 2.6. In addition, D = 2 tubes/ μm, t = 50 nm, R = 0.6 nm (measured by
AFM), and ε
s
was estimated to be 4. The value of C
Q
(= 4.0×10
-10
F/m) was taken from a
previous report [25]. The effective device mobility was calculated to be 2685 cm
2
V
-1
s
-1
.
By assuming one third of the nanotubes are metallic, one can further derive a nanotube
mobility of 3571 cm
2
V
-1
s
-1
.
Figure 2.6 I
ds
–V
g
and g
m
–V
g
curve from a device with 50 μm channel length.
30
To improve the on/off ratio (I
on
/I
off
), controlled electrical breakdown [26] was
used to remove metallic and high-leakage semiconducting nanotubes. Specifically, we
developed an automated electrical breakdown process by setting target on/off ratio and
on-current, and then using computer control to perform multiple steps of breakdown until
the target values were reached. This process, when combined with an automatic probe
station, can make electrical breakdown fairly practical for wafer-scale processing. The
backgate was set to 15 V to turn off the desired semiconducting nanotubes, while the
source/drain voltage (V
ds
) was swept from 0 to -35 V to electrically stress and break the
undesired tubes. The I
on
/I
off
of a transistor with W = 100 μm and L = 0.75 μm in Figure
2.5e significantly increased from ~2 to 10
3
with multiple steps of electrical breakdown,
accompanied by a moderate degradation of the on current. After electrical breakdown,
Figure 2.5f and inset show the I
ds
–V
g
curves at different V
ds
from -0.2 to -1 V and I
ds
–V
ds
curves at different V
g
from – 8 to 8 V. Figure 2.5g is a statistical study of about 50
devices from altogether 10 chips with L = 0.75 μm and various W before and after
electrical breakdown, where the on-state current density is plotted v.s. the on/off ratio. I
on
is measured at V
ds
= 1 V and V
g
= -10 V, and I
off
is measured at V
ds
= 1 V and V
g
= 10 V.
Before breakdown, the devices exhibited on/off ratios in the range of 1 to 10, due to the
presence of metallic nanotubes. In contrast, after electrical breakdown, the on/off ratios
underwent significant improvement to the range of 10
2
to 10
5
, which can be used as
building blocks for the following nanotube circuits. More details about the on/off ratio
and on-state current distribution can be found in Figure 2.7, where Figure 2.7a and b
show the distribution of on-current density and on/off ratio of 50 devices before and after
31
electrical breakdown, respectively. Through electrical breakdown, we successfully tuned
the devices to obtain higher on/off ratio (10
3
) than before breakdown, even though the
on-current density decreased from 7.69 to 1.68 μA/ μm due to the loss of nanotubes.
Figure 2.7 Distribution of on/off ratio and on-current density of 50 devices before (a) and after (b) electrical
breakdown, respectively.
In addition to the tuning of the on/off ratio using electrical breakdown, we can
adjust the transistor conductance by performing multiple steps of nanotube transfer to
increase the tube density. Figure 2.5h shows the I
ds
–V
g
curves of two representative
devices, with one and two steps of transfer, respectively. Devices fabricated in the double
transfer region showed ~2.2 times more current per unit width in Figure 2.5h. Multiple
32
nanotube transfer is a novel technique to compensate the decreased current after electrical
breakdown, and additional transfers can be performed to achieve even higher current
densities.
Besides the back-gated devices, top-gated devices were fabricated by defining
top-gate electrodes on back-gated devices. Compared with the common back-gate
devices, the top-gate structure has an intrinsic benefit such as individual control of each
transistor in a nanotube circuit. In order to make the top-gate electrodes, we first
performed the patterning using photolithography, deposited 50 nm Al
2
O
3
using atomic
layer deposition(ALD) as top-gate dielectric, and then deposited 5 nm Ti/45 nm Pd as the
top-gate electrodes, followed by lift-off process. Figure 2.8a illustrates a schematic
diagram of a top-gated device, where top gate partially covers the active channel so that
nanotubes can be exposed to n-type dopants such as potassium. In Figure 2.8b, one can
clearly see nanotubes which bridge between S/D electrodes and are partially covered by
Al
2
O
3
and top-gate. Figure 2.8c and d are the typical transfer characteristics (I
ds
–V
g
curves) and output characteristics (I
ds
–V
ds
curves) for a transistor with W = 25 μm, L = 3
μm, and top-gate length = 1 μm after proper electrical breakdown. The I
ds
–V
ds
curves
appear to be very linear, indicating that ohmic contacts are formed between the electrodes
and the nanotubes. The on-current is measured to be 20 μA, corresponding to a current
density of 0.8 μA/ μm, and the on/off ratio exceeds 10
4
. We used such devices in the
following doping study.
33
Figure 2.8 Top-gated transistors for doping and truly integrated CMOS inverters. (a, b) Schematic diagram and SEM
image of a top-gated transistor, respectively. (c) I
ds
–V
g
curves of the transistor with L = 3 μm and W = 25 μm at
different V
ds
= 0.1 to 1.1 V in step of 0.1 V . Inset: I
ds
–V
g
curve in logarithm scale. (d) I
ds
–V
ds
curves at different V
g
= -20,
-15, -10, 10, 15, and 20 V for the same device in (c). (e) I
ds
–V
g
curves of the top-gated transistor before (red) and after
(black) K doping. (f) Voltage transfer characteristic (VTC) of a CMOS inverter with selective K doping. Inset:
schematic diagram (left) and photograph (right) of the circuit. (g) I
ds
–V
g
curves of a dual-gated transistor before (red,
back gate at -20 V) and after (black, back gate at 20 V) electrostatic doping. (h) I
ds
–V
g
curves at different V
bg
= -20 to 20
V for the same device in (e), showing a significant shift of threshold voltage and enhancement of n-type conduction.
1.5
1.0
0.5
0.0
V
out
(V)
2.5 2.0 1.5 1.0 0.5 0.0
V
in
(V)
Gain ≈ 5
p-type
n-type
15
10
5
0
I
ds
(μΑ)
-4 -2 0 2 4
V
g
(V)
15
10
5
0
-5
-10
-15
I
ds
(μΑ)
-1.0 -0.5 0.0 0.5 1.0
V
ds
(V)
10
8
6
4
2
I
ds
(μΑ)
-4 -2 0 2 4
V
g
(V)
Before K doping
After K doping
a
c d
e f
2.5
2.0
1.5
1.0
0.5
I
ds
(μΑ)
-10 -5 0 5 10
V
g
(V)
600
500
400
300
200
100
I
ds
(nA)
Before electrostatic doping
After electrostatic doping
g
6
10
-8
2
4
6
10
-7
2
4
6
10
-6
2
I
ds
(μΑ)
-10 -5 0 5 10
V
g
(V)
V
bg
: -20 V to 20 V
h
10
-8
10
-7
10
-6
10
-5
I
ds
(μΑ)
-4 -2 0 2 4
V
g
(V)
b
34
2.5 Integrated CMOS nanotube circuits
One of the most important characteristics of CMOS circuits is low static power
consumption. Significant power is only drawn when the CMOS circuits are switching
between on and off states. Unlike doping in silicon CMOS processes, nanotubes can not
be easily doped via ion implantation. The ability to obtain both p- and n-type nanotube
FETs, therefore, is important to construct complementary electronics. A p-type nanotube
device can be doped electrostatically, substitutionally, or via charge transfer to convert it
into an n-type one. Four different methods, with potassium [21,22] and electrostatic [23]
doping for top-gated devices, and polyethilenimine (PEI) [19] and hydrazine (N
2
H
4
) [20]
for back-gated ones, have been studied here to produce n-type transistors and to evaluate
the most practical way for integrated circuits. In order to dope nanotube devices with
potassium, we first spin-coated polymethylmethacrylate (PMMA) as a capping layer for
p-type transistor, and then opened up the window for other devices which can be altered
into n-type after doping, as shown in inset of Figure 2.8f. This device was loaded into
high vacuum (~ 10
-5
torr), followed by the evaporation of potassium. Figure 2.8e shows
the I
ds
–V
g
characteristics of the top-gated transistor before and after potassium doping.
This doping produced n-type transistor by shifting the Fermi level of nanotubes to the
conduction band, and the conductance of the transistor increased at positive gate voltage.
Based on the transferred nanotube devices, we performed four different types of
doping methods including potassium, electrostatic, polyethilenimine (PEI), and hydrazine
(N
2
H
4
), in order to get n-type devices for CMOS circuits. The following shows in-depth
studies of PEI and N
2
H
4
doping with relative advantages and disadvantages discussed.
35
Figure 2.9a and b show I
ds
–V
g
curves of a back-gated device before and after PEI doping,
respectively. One can clearly see that the on/off ratio significantly decreased from 10
5
to
10 after PEI doping presumable due to the leakage through PEI. Such n-type devices with
poor on/offs ratio cannot be applicable to CMOS circuits, even though PEI doping is a
simple process compared with other doping methods. N
2
H
4
, known as a strong base, was
also studied here as an n-type dopant. SEM image in Figure 2.9c clearly shows the ALD
Al
2
O
3
gate-dielectric layer under a gate electrode (50 nm in thickness) before the sample
was soaked in N
2
H
4
. However, we observed that the Al
2
O
3
dielectric layer was
completely etched away after the sample was soaked in N
2
H
4
for 30 minute, as shown in
Figure 2.9d. Furthermore, we noticed that N
2
H
4
can diffuse through even a relatively
thick layer of photoresist such as PMMA, leading to difficulty in passivation of p-type
devices. In Figure 2.9e and f, p-type devices were converted into n-type ones, regardless
of whether PMMA passivation was used. As a result, N
2
H
4
doping cannot be a feasible
doping method for the integrated CMOS circuits.
The potassium doping has clear advantage over other doping methods such as PEI
showing low on-off ratio, and N
2
H
4
with toxicity and difficulty in integration. Armed
with potassium doping, we have constructed a truly integrated CMOS aligned nanotube
inverter, i.e., with the p-type and n-type transistors residing on one chip and located side
by side. Figure 2.8f includes the voltage transfer characteristics (VTC), the schematic
diagram, and the photo image of the CMOS inverter. Our inverter was operated with a
V
DD
= 2 V and an input voltage range from 0 to 2.5 V, and the gain deduced from VTC
36
data was 5, which can be high enough to drive a more complicated logic circuit such as a
ring oscillator.
Figure 2.9 (a, b) I
ds
–V
g
curves of a back-gated device before (a) and after (b) PEI doping, respectively. (c, d) SEM
images of the top-gated devices before (c) and after (d) soaked in N
2
H
4
, respectively. (e, f) I
ds
–V
g
curves before and
after N
2
H
4
doping on the back-gated devices without (e) and with (f) PMMA passivation, respectively.
In addition to potassium doping, electrostatic doping has been studied on
top-gated transistors with Si common back-gate. We utilized electrostatic doping effects
[23] in the dual-gate nanotube FET to obtain the polarity control (p or n) and to tune the
threshold voltage of FET. Figure 2.8g exhibits the current-gate voltage (I
ds
–V
g
)
characteristics of the dual-gated transistor, and clearly shows p- and n-type properties at
37
back-gate voltage (V
g
) = -20 V and 20 V, respectively, which can be understood as
following. For sufficiently negative (or positive) back-gate voltage, the Schottky barriers
are thinned enough to allow for hole (or electron) tunnelling from the metal contact into
the nanotube, and thus the nanotube channel can be electrostatically doped into p-type or
n-type. Therefore, varying the top gate voltage can switch on and off the transistor with
the assist of back-gate voltage, which determines the type of majority carrier and the
device on-current. In our device, the n-type conduction is slightly lower than the p-type
conduction, which is attributed to asymmetrical Schottky barrier heights for holes and
electrons, and environmental doping effect from O
2
and moisture. We also measured the
current v.s the top-gate voltage (I
ds
–V
g
) at different back-gate voltage (V
bg
) from -20 to 20
V, and a significant shift of threshold voltage and enhancement of n-type conduction
were observed from 0 to -6 V, as shown in Figure 2.8h. Compared with other doping
methods such as potassium and hydrazine, which are not stable in air, the electrostatic
doping is stable and tunable, but requires sophisticated device structure and circuit
design.
Based on the top-gated aligned nanotube transistors, more sophisticated PMOS
circuits have also been demonstrated. It is, however, inevitable that there are misaligned
or misoriented nanotubes in these devices, which can result in incorrect logic behavior.
Therefore, an innovative circuit design such as defect-tolerate structure is required to
guarantee the correct logic behavior. We hereby report defect-immune circuit layouts for
PMOS NOR and NAND circuits. Figure 2.10a–c show a defect-influence layout, and two
defect-tolerate layouts with transistors connected in parallel, respectively.
38
Figure 2.10 PMOS NOR and NAND gates with top-gated transistors. (a-c) Schematic diagrams of a defect-influence
layout and two defect-tolerate layouts with two transistor in parallel, respectively. (d, e) Output characteristics of
PMOS NOR and NAND, respectively. Inset: SEM image of integrated pull-up networks and schematic diagram of
PMOS circuits. (f, g) Output characteristics of PMOS NAND with pull-up network (b) and (c), respectively, where the
nanotube density was not uniform in the circuit, as depicted in schematic diagram in inset.
For Figure 2.10a, misaligned nanotubes outside the gates are not under the control
of either gate and therefore may impair the logic operation. In Figure 2.10b, the
1.0
0.8
0.6
0.4
0.2
0.0
Vou t (V )
Gate A
Gate B
"1"
"1"
"0"
"1"
"1"
"0"
"0"
"0"
1.0
0.8
0.6
0.4
0.2
0.0
Vou t (V )
"1"
"1"
Gate A
Gate B
"1"
"0"
"0"
"1"
"0"
"0"
1.0
0.8
0.6
0.4
0.2
0.0
Vou t (V )
Gate A
Gate B
"1"
"1"
"1"
"0"
"0"
"1"
"0"
"0"
d e
f
Vdd
Output
A B
Output
Output
Vdd
A
B
Vdd
Output
B A
a
bc
etched
nanotube
g
1.0
0.8
0.6
0.4
0.2
0.0
Vou t (V )
Gate A
Gate B
"1"
"1"
"1"
"0"
"0"
"1"
"0"
"0"
Ι
Π
39
nanotubes lying between gate A and B are removed using oxygen plasma etching, and
thus this design is immune to such misaligned nanotubes. Furthermore, Figure 2.10c
represents an even better design, where two transistors controlled by gate A and B are
connected in parallel and utilize the same bunch of aligned nanotubes. This design
enables virtually identical device performance between two parallel transistors, as shown
in Figure 2.11.
Ideally the pull-up branch of a PMOS NAND would require transistors A and B
to be rather symmetrical, i.e., to deliver similar transistor characteristics. We have
proposed two kinds of defect-tolerant designs for PMOS logic circuits above. However,
one showed much better performance than the other when the nanotube distribution was
not uniform. Therefore, we performed in-depth study about the transfer characteristics of
the pull-up network for two designs. Figure 2.11 displays the current through two parallel
transistors with V
DD
= 1 V, V
out
= 0 V, V
A
swept from -5 V to 5 V, and V
B
set at 5 V, 0 V,
and -5 V for different curves. Of particular interest is the current values at point I and II,
which correspond to the currents at (V
A
, V
B
) = (-5 V, 5 V) and (5 V, -5 V), respectively.
For symmetrical transistors, these two current values should be more or less equivalent.
Based on the NAND design in schematic of Figure 2.11a, such design showed significant
difference between the point Ι and II. This is attributed to the nonuniform nanotube
density, which was further proved by the SEM image in Figure 2.11a. In contrast, for the
NAND design in Figure 2.11b, two transistors, which were built on the same nanotube
arrays in the SEM image, showed equivalent performance between point I and II, as
shown in the I
DD
–V
A
curves in Figure 2.11b.
40
Figure 2.11 (a, b) I
DD
–V
A
curves at different V
B
= 5, 0, -5 V from the two different types of NAND pull-up networks, as
shown in SEM images and schematic diagrams.
We fabricated PMOS circuits using the defect-immune layout. Figure 2.10d and e
include SEM images of the integrated pull-up networks, the schematic diagrams, and the
output characteristics for PMOS NOR and NAND, respectively. 20M Ω resistive load was
chosen so that it was between the on-state resistance and the off-state resistance of the
transistors. The NAND and NOR circuits were both operated with a V
DD
of 1V. 10V and
-10V applying on gate A and B were treated as logic “1” and “0”, redspectively. For the
NAND, the output was “1” when either one of the two inputs was “0”, while for the NOR,
the output was “0” when either one of the two inputs was “1”. These output
characteristics confirm that our circuits realized the logic function correctly. However,
the design in Figure 2.10b may suffer from the problem of having nonuniform nanotube
41
density and consequently different characteristics for gate A and B. Figure 2.10f shows
the data and schematic diagram of a PMOS NAND gate, where the nanotube density
happened to be nonuniform. One can clearly see that the outputs were asymmetric
between the point Ι and II, and also the transfer characteristics for gate A and B showed a
significant difference in terms of on-current (Figure 2.11a). The low output at the point II
was attributed to the relatively large DC current leakage through the pull-down resistor,
which was comparable to the on-current of transistor controlled by gate A. In contrast, for
the NAND with design shown in Figure 2.10c and g inset, the transistor transfer
characteristics (Figure 2.11b) and the outputs of circuits were more symmetric than the
ones in Figure 2.10f. This confirms that the NAND design in Figure 2.10c performed the
logic function correctly even with nonuniform nanotube density and misaligned
nanotubes.
While PMOS logic is easy to design and manufacture, it has several shortcomings
as well. The worst problem is that current flows through the pull-down resistor when the
pull-up network is active, as discussed above. This leads to static power dissipation even
when the circuit sits idle. In order to overcome such problem, CMOS nanotube circuits
have been studied here using the defect-tolerant design with individual back-gates for
efficient chemical doping. Specifically, the individual back-gated devices have relative
advantages over the top-gated ones, such as easy chemical doping and electrical
breakdown owing to the fully exposed device structure. For the individual back-gated
devices, we first defined individual back-gate electrodes on Si/SiO
2
wafer via
photolithography, 5 nm Ti/ 45 nm Au deposition, and a lift-off process. 50 nm ALD HfO
2
42
was deposited as the gate-dielectric, and then the aligned nanotubes were transferred.
Finally, the source/drain electrodes were formed. The CMOS NOR and NAND are
depicted in Figure 2.12a and b, respectively.
Figure 2.12 Defect-tolerant CMOS NOR and NAND with individual back-gated transistors. (a, b) Schematic diagrams
of CMOS NOR and NAND, respectively. (c, d) SEM images of CMOS NOR and NAND, respectively. (e, f) Output
characteristics of CMOS NOR and NAND, respectively.
After the device fabrication, we performed the potassium doping to get n-type
devices as mentioned in the CMOS inverter study. Figure 2.12c and d show SEM images
1.0
0.8
0.6
0.4
0.2
0.0
V out (V )
Gate A
Gate B
"1"
"1"
"1"
"0"
"0"
"1"
"0"
"0"
a b
d
1.0
0.8
0.6
0.4
0.2
0.0
V out (V )
Gate A
Gate B
"1"
"1"
"1"
"0"
"0"
"1"
"0"
"0"
e f
c
43
of the CMOS NOR and NAND, respectively. The pull-up and pull-down networks were
built on the same nanotube arrays, and the pull-down network was converted from p-type
into n-type after potassium doping, as described below.
Figure 2.13a and b show the I
DD
–V
A
curves of the CMOS NAND pull-up network
before and after potassium doping, respectively. Owing to the PMMA passivation, there
was no significant difference in the transfer characteristics, indicating the p-type
transistors were protected from potassium doping. For the CMOS NAND pull-down
network shown in Figure 2.13c and d, the p-type devices in Figure 2.13c were
successfully converted into n-type in Figure 2.13d after potassium doping. Compared
with the PMOS circuits, the CMOS logic circuits showed almost ideal performance,
where the outputs were close to 0 V or 1.0 V, as shown in Figure 2.12e and f.
Figure 2.13 (a, b) I
DD
–V
A
curves of the pull-up network (in dotted line) in the CMOS NAND before and after
potassium doping, respectively. (c, d) I
DD
–V
A
curves of the pull-down network (in dotted line) in the CMOS NAND
before and after potassium doping, respectively.
44
2.6 Summary
In summary, we have reported significant progress on CMOS-analogous
wafer-scale processing of integrated aligned nanotube circuits, including progress on
wafer-scale synthesis and transfer of aligned nanotubes, metallic nanotube removal and
chemical doping, and defect-tolerant integrated nanotube circuits. Synthesis of massive
aligned nanotubes has been achieved on complete 4 inch quartz and sapphire substrates,
followed by successful transfer of the nanotubes to 4 inch Si/SiO
2
wafers. CMOS
analogous fabrication was performed to yield transistors and circuits with features down
to 0.5 μm, with high current density ~ 20 μA/μm and good on/off ratios. In addition,
extensive chemical doping has been studied and used to build fully integrated
complementary inverter with a gain ~ 5, and defect-tolerant designs have been proposed
and employed for NAND and NOR gates. Our work represents significant advance
toward the challenging task of nanotube assembly and integration for future
beyond-silicon integrated circuits.
45
Chapter 2. References
1. Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654–657.
2. Durkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39.
3. Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon
Nanotube Transistors. Science 2001, 294, 1317–1320.
4. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, Ph. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
5. Liu, X.; Lee, C.; Han, J.; Zhou, C. Carbon Nanotube Field-Effect Inverters. Appl.
Phys. Lett. 2001, 79, 3329–3331.
6. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays
for Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2,
929–932.
7. Chen, Z.; Appenzeller, J.; Lin, Y.; Oakley, J. S.; Rinzler, A.G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, Ph. An Integrated Logic Circuit Assembled on a Single
Carbon Nanotube. Science 2006, 311, 1735.
8. Cao, Q.; Kim, H.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.;
Alam, M. A.; Rogers, J. A. Medium-Scale Carbon Nanotube Thin-Film Integrated
Circuits on Flexible Plastic Substrates. Nature 2008, 454, 495–500.
9. Ismach, A.; Segev, L.; Wachtel, E.; Joselevich, E. Atomic-Step-Templated
Formation of Single Wall Carbon Nanotube Patterns. Angew. Chem. Int. Ed. 2004,
43, 6140 –6143.
10. Kocabas, C.; Hur, S.; Gaur, A.; Meitl, M. A.; Shim, M.; Rogers, J. A. Guided
Growth of Large-Scale, Horizontally Aligned Arrays of Single-Walled Carbon
Nanotubes and Their Use in Thin-Film Transistors. Small 2005, 1, 1110–1116.
11. Han, S.; Liu, X.; Zhou, C. Template-Free Directional Growth of Single-Walled
Carbon Nanotubes on a- and r-Plane Sapphire. J. Am. Chem. Soc. 2005, 127,
5294–5295.
12. Ago, H.; Nakamura, K.; Ikeda, K.; Uehara, N.; Ishigami, N.; Tsuji, M. Aligned
Growth of Isolated Single-Walled Carbon Nanotubes Programmed by Atomic
Arrangement of Substrate Surface. Chem. Phys. Lett. 2005, 408, 433–438.
46
13. Louarn, A. L.; Kapche, F.; Bethoux, J. M.; Happy, H.; Dambrine, G.; Deryche, V.;
Chenevier, P.; Izard, N.; Goffman, M. F.; Bourgoin, J. P. Intrinsic Current Gain
Cutoff Frequency of 30 GHz with Carbon Nanotube Transistors. Appl. Phys. Lett.
2007, 90, 233108.
14. Chimot, N.; Derycke, V.; Goffman, M. F.; Bourgoin, J. P.; Happy, H.; Dambrine, G.
Gigahertz Frequency Flexible Carbon Nanotube Transistors. Appl. Phys. Lett. 2007,
91, 153111.
15. Liu, X.; Han, S.; Zhou, C. Novel Nanotube-on-Insulator (NOI) Approach toward
Single-Walled Carbon Nanotube Devices. Nano Lett. 2006, 6, 34–39.
16. Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S.
V.; Rogers, J. A. High-Performance Electronics Using Dense, Perfectly Aligned
Arrays of Single-Walled Carbon Nanotubes. Nat. Nanotechnol. 2007, 2, 230–236.
17. Kocabas, C.; Kim, H.-S.; Banks, T.; Rogers, J. A.; Pesetski, A. A.; Baumgardner, J.
E.; Krishnaswamy, S. V.; Zhang, H. Radio Frequency Analog Electronics Based
on Carbon Nanotube Transistors. Proc. Nat. Acad. Sci. 2008, 105, 1405–1409.
18. Pesetski, A. A.; Baumgardner, J. E.; Krishnaswamy, S. V.; Zhang, H.; Adam, J. D.;
Kocabas, C.; Banks, T.; Rogers, J. A. A 500 MHz Carbon Nanotube Transistor
Oscillator. Appl. Phys. Lett. 2008, 93, 123506.
19. Shim, M.; Javey, A.; Kam, N. W. S.; Dai, H. Polymer Functionalization for
Air-Stable n-Type Carbon Nanotube Field-Effect Transistors. J. Am. Chem. Soc.
2001, 123, 11512–11513.
20. Klinke, C.; Chen, J.; Afzali, A.; Avouris, Ph. Charge Transfer Induced Polarity
Switching in Carbon Nanotube Transistors. Nano Lett. 2005, 5, 555–558.
21. Kong, J.; Zhou, C.; Yenilmez, E.; Dai, H. Alkaline Metal-Doped n-type
Semiconducting Nanotubes as Quantum Dots. Appl. Phys. Lett. 2000, 77,
3977–3979.
22. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, Ph. Controlling Doping and
Carrier Injection in Carbon Nanotube Transistors. Appl. Phys. Lett. 2002, 80,
2773–2775.
23. Lin, Y.; Appenzeller, J.; Knoch, J.; Avouris, Ph. High-Performance Carbon
Nanotube Field-Effect Transistor with Tunable Polarity. IEEE Transactions on
Nanotechnology 2005, 4, 481–489.
47
24. Heaney, P. J.; Veblen, D. R. Observations of the α- β Phase Transition in Quartz: A
Review of Imaging and Diffraction Studies and Some New Results. American
Mineralogist 1991, 76, 1018–1032.
25. Rosenblatt, S.; Yaish, Y.; Park, J.; Gore, J.; Sazonova, V.; McEuen, P. L. High
Performance Electrolyte Gated Carbon Nanotube Transistors. Nano Lett. 2002, 2,
869–872.
26. Collins, P. G.; Arnold, M. S.; Avouris, Ph. Engineering Carbon Nanotubes and
Nanotube Circuits Using Electrical Breakdown. Science 2001, 292, 706–709.
48
Chapter 3. Metal Contact Engineering and Registration-Free
Fabrication of CMOS Integrated Circuits Using Aligned
Carbon Nanotubes
3.1 Introduction
Single-walled carbon nanotubes offer extraordinary electrical properties [1-5],
such as high intrinsic carrier mobility and current-carrying capacity and are envisioned as
a potential candidate for the next generation beyond silicon transistor and integrated
circuit applications. They have been used extensively to demonstrate ballistic and
high-mobility transistors [6-8] and various integrated logic circuits and ring oscillators
[9-13]. For logic circuit applications, it is of course desirable to have complementary
metal-oxide semiconductor (CMOS) operation since it gives rail-to-rail swing, larger
noise margin, and, most importantly, small static power consumption. However, the
CMOS operation gives rise to difficulties when using nanotube-based devices since
nanotubes typically exhibit p-type behavior in ambient environments. In order to convert
the nanotube devices into n-type, many approaches have been reported in the literature
such as vacuum annealing, potassium doping, chemical doping, and electrostatic gating
[10,14-16]. However, all of the works mentioned above have their own drawbacks. For
example, the vacuum annealing and potassium doping techniques are not air stable, while
chemical doping, even though can be air stable and sounds appealing, is not yet
compatible with the state-of-the-art integrated circuit fabrication process.
49
Alternatively, n-type transistors can also be achieved by metal contact
engineering. It is well-known that Palladium (Pd), with a large work function, will align
with the valence band of the carbon nanotubes and form ohmic contacts for holes.
Consequently, the devices with Pd conacts will exhibit p-type behavior. Thus it is natural
to hypothesize that by using metals with small work function as the electrodes, it should
be possible to obtain n-type conduction from the nanotubes as well. Recently, significant
advance has been made on the above-mentioned topic by using small work function
metals, such as scandium (Sc) and Yttrium (Y), to demonstrate CMOS inverters and
diodes on individual carbon nanotube [17-19]. This technique nevertheless has some
drawbacks. For example, in order to use individual nanotube for transistors, it is
inevitably necessary to identify the semiconducting nanotubes beforehand, and the
ensuing device fabrication process will also require locating of one specific nanotube and
e-beam writing, which make the process not scalable. Moreover, individual nanotube
devices are typically more vulnerable and can give large device-to-device variation.
Using parallel aligned carbon nanotubes can be one straightforward solution to
the above-mentioned problems faced by individual nanotube devices. Recently, several
groups including our own have reported the growth of massively aligned nanotubes on
sapphire or quartz substrates [20-24]. Based on the aligned nanotubes, we have proposed
a nanotube-on-insulator platform and demonstrated high-performance submicrometer
transistors and CMOS integrated circuits, such as inverter, NAND, and NOR using both
chemical and potassium doping [25-27]. The advantages of aligned nanotubes include
registration-free fabrication, high device yield, and small device-to-device variation,
50
which are exactly the shortcomings of the individual nanotube devices. Of course, the
aligned nanotube platform also faces difficulty, which is the removal of metallic
nanotubes. However, this is easily solved by using our automated electrical breakdown
process, as described in chapter 2 and our previous publication [27].
In this work, we apply metal contact engineering to our existing aligned nanotube
platform. Combining small work function metal Gadolinium (Gd) for n-type contact [28]
and large work function metal Pd for p-type contact, we have demonstrated
registration-free fabrication of air-stable n-type aligned nanotube transistors,
PN-junctions, and CMOS integrated inverters. Our aligned nanotube approach for CMOS
integrated circuits shows significant advantage over individual nanotube platforms with
respect to scalability and reproducibility and suggests a practical and realistic approach
for nanotube-based CMOS integrated circuit applications.
3.2 Air-stable n-type nanotube field-effect transistors using Gd contacts
Figure 3.1a illustrates the fabrication process of the back-gated n-type nanotube
transistors, which begins with aligned nanotube synthesis on quartz substrates with
evaporated iron catalysts defined by photolithography. The samples are annealed in air at
900 °C for 2 hours, and chemical vapor deposition (CVD) is used to grow aligned
nanotubes between the catalyst islands with CH
4
(2000 sccm) and H
2
(300 sccm) as the
feeding gases at 900 °C. The scanning electron microscopy (SEM) image of the aligned
nanotubes on quartz substrate is shown in the inset of Figure 3.1a. After synthesis, the
nanotubes are then transferred to Si/SiO
2
substrates using a facile gold film and thermal
51
releasing tape method, as reported in the previous chapter and our previous publications
[26,27].
Following the nanotube transfer is the device fabrication process. SiO
2
with a
thickness of 500 nm is used to act as the back-gate dielectric, and the source and drain
electrodes are patterned by photolithography. In order to achieve nanotube transistors
with n-type behavior in air, metals with small work function need to be used, which will
allow the Fermi level of the electrodes to align with the conduction band of the carbon
nanotubes and thus gives ohmic contact for electrons and a large schottky barrier for
holes. In this work, Gd with a work function of ~ 3.1 eV [28] is used as the metal
contacts, and 70 nm Gd is deposited by thermal evaporation followed by the lift-off
process to form the source and drain metal contacts. Figure 3.1a shows optical
microscope images of the back-gated n-type aligned nanotube transistors after the
fabrication. The schematic diagram and SEM image of the devices are shown in Figure
3.1b and c, respectively.
The electrical properties of the devices are characterized, and all the
measurements are carried out in air. For the aligned nanotube devices, due to the presence
of both metallic and semiconducting nanotubes, metallic nanotube removal technique,
such as electrical breakdown, is necessary. More information about the electrical
breakdown process can be found in the literature [29] and our previous publications
[26,27].
52
Figure 3.1 Fabrication of the back-gated n-type nanotube transistors and their electrical properties. (a) Simplified
process flow of the n-type nanotube transistor fabrication including aligned nanotube synthesis on quartz substrate (left)
(inset: SEM image of the aligned nanotubes), transfer to Si/SiO
2
substrate, and Gd metal electrode patterning by
photolithography and lift-off process. The optical photographs of the completed chip and a typical device are shown in
the right. (b, c) Schematic diagram (b) and SEM image (c) of the n-type aligned nanotube transistor with Gd metal
contacts. (d) Transfer (I
D
–V
G
) characteristics of a typical n-type nanotube transistor (L = 4 μm, W = 8 μm) measured at
V
D
= 1 V before and after electrical breakdown. (e) Transfer characteristics of the same device measured under different
drain voltages after electrical breakdown. (f) Output (I
D
–V
D
) characteristics of the same device measured under
different gate voltages.
Figure 3.1d shows the transfer (I
D
–V
G
) characteristics for a typical n-type
nanotube transistor (L = 4 μm, W = 8 μm) measured at V
D
= 1 V before and after
electrical breakdown. Before breakdown, the device exhibits on/off ratio of around 2.
After electrical breakdown, the on/off ratio is improved to around 1000 with a trade-off
-10 -5 0 5 10
0
1
2
3
4
VD = 1.0 V
VD = 0.8 V
VD = 0.6 V
VD = 0.4 V
VD = 0.2 V
Drain Current (μA)
Gate Voltage (V)
a
b
c
d
Nanotube transfer and
Electrode patterning
012 34 5
0
3
6
9
12
15
Drain Current (μA)
Drain Voltage (V)
VG is from -10V to 0V
in 1V steps
e
f
5 µm
-10 -5 0 5 10
10n
100n
1u
10u
V
D
= 1 V
Before electrical breakdown
After electrical breakdown
Drain Current (A)
Gate Voltage (V)
53
with the on current. Figure 3.1e shows the transfer characteristics of the device after
electrical breakdown measured under different drain voltages, and Figure 3.1f shows
output characteristics (I
D
–V
D
) of the device measured under different gate voltages. From
the transfer characteristic, one can find that the transistor exhibits clear n-type behavior.
For the output characteristics, it appears to be very linear for V
D
smaller than 1 V as
shown in Figure 3.2, indicating that ohmic contacts are formed between the Gd electrodes
and the nanotubes. Under higher V
D
, the device exhibits saturation behavior which
indicates nice field-effect operation.
Figure 3.2 Linear region output characteristics of the Gd-contacted nanotube transistor.
Ideally, all Gd-contacted nanotube transistors should exhibit predominant n-type
behavior as the device shown in Figure 3.1. In practice, when measuring the
Gd-contacted devices in ambient environment without any passivation layer, some
devices do exhibit predominant n-type behavior (Figure 3.3a), while some other devices
also exhibit ambipolar behavior (Figure 3.3b). The reason is that the nanotubes are
0.0 0.2 0.4 0.6 0.8 1.0
0
1
2
3
4
Drain Current (μA)
Drain Voltage (V)
VG is from -10V to 0V
in 1V steps
54
always heavily p-doped in air due to the adsorption of oxygen, leading to the charge
transfer to nanotubes, and shifting the Fermi level of the nanotubes to close to the valence
band [10,30-33]. Therefore, part of the as-made devices exhibit ambipolar behavior
instead of clear n-type behavior. The difference between the n-type devices and
ambipolar devices can be attributed to either different environmental oxygen doping, or
different nanotubes in the channel (different diameters, i.e. different bandgap). In order to
suppress the p-type conduction of the ambipolar devices, SiO
2
passivation is necessary as
will be discussed below.
Figure 3.3 Transfer (I
D
–V
G
) characteristics of the Gd-contacted nanotube transistors measured in ambient environment
showing n-type or ambipolar behavior. (a) Transfer characteristics of a typical n-type device plotted in linear scale. (b)
Transfer characteristics of a typical ambipolar device plotted in linear scale. (c) Transfer characteristics of the n-type
and ambipolar devices plotted in logarithm scale.
a b
c
-10 -5 0 5 10
10n
100n
1u
10u
Drain Current (A)
Gate Voltage (V)
N-type behavior
Ambipolar behavior
VD = 1V
-10 -5 0 5 10
0
1
2
3
4
Drain Current (μA)
Gate Voltage (V)
VD = 1 V
N-type
-10 -5 0 5 10
0
3
6
9
12
15
Drain Current (μA)
Gate Voltage (V)
VD = 1 V
Ambipolar
55
Even though the above-mentioned back-gated transistor with Gd contacts only
approach is straightforward and simple, there are some shortcomings. First, due to the
adsorption of oxygen on nanotubes, the nanotubes are always heavily p-doped, so the
devices sometimes exhibit ambipolar behavior instead of predominant n-type behavior as
discussed above. Second, Gd (and other small work function metals) is susceptible to air
and moisture, will be oxidized relatively easily in air, and the resistivity will increase
greatly in a few days after device fabrication. Finally, since the transferred aligned
nanotubes cover the entire substrate, oxygen plasma is necessary to remove the unwanted
nanotubes outside the device channel region to achieve accurate channel length and width
and to remove the possible leakage in the devices. However, Gd can be attacked by O
2
plasma, so the unwanted nanotube etching has to be done prior to the electrode patterning,
which adds one more step of alignment mark patterning to the fabrication process.
Because of the three reasons mentioned above, it is crucial to develop a
passivation technique for Gd contacts, and we propose to use the e-beam evaporated SiO
2
for this purpose. The schematic diagram of the passivated n-type device fabrication
process is shown in Figure 3.4a. In brief, the device fabrication begins with the individual
back-gated aligned nanotube transistors with Ti/Pd contacts. The benefit of using
individual back-gated structures is the individual control of each transistor in a nanotube
circuit, and the fabrication process of the individual back-gated Ti/Pd-contacted device is
discussed below. First, Ti/Au back-gate is patterned by photolithography and lift-off
process, and 50 nm Al
2
O
3
high- κ dielectric is deposited on top of the Ti/Au back-gate by
atomic layer deposition (ALD). Aligned nanotubes are then transferred to the ALD layer
56
using the method discussed in chapter 2. After nanotube transfer, the source/drain
electrodes are patterned by photolithography, and 5 Å Ti and 70 nm Pd are deposited by
e-beam evaporation followed by the lift-off process to form the source and drain metal
contacts. Finally, one more step of photolithography plus O
2
plasma is used to remove the
unwanted nanotubes outside the device channel region in order to achieve accurate
channel length and width and to remove the possible leakage in the devices.
The transfer characteristics of the pristine device (L = 2 μm, W = 5 μm) after
electrical breakdown are shown in Figure 3.4b, which shows p-type behavior as expected
since Pd is known to form ohmic contacts for holes due to its large work function.
E-beam lithography is used to pattern source/drain extensions with 500 nm extension into
the channel and with width equal to the transistor channel width. Gd contacts are then
deposited by thermal evaporation and lift-off process. In this Ti/Pd contact pads plus Gd
source/drain extension configuration, the effect from the Gd extensions should be more
dominant since the Gd extensions are closer to the nanotube channel than the Ti/Pd
contact pads.
Figure 3.4c shows the transfer characteristics of the same devices shown in Figure
3.4b after the Gd contacts deposition. Comparing Figure 3.4c with b, one can find the
transition from p-type behavior to ambipolar behavior. It is likely that the nanotubes are
heavily p-doped in air due to the adsorption of oxygen on the nanotubes, so the devices
exhibit ambipolar behavior instead of predominant n-type behavior. SiO
2
passivation is
demonstrated to be effective for suppressing the p-type conduction of the ambipolar
57
devices, as discussed below, and the SiO
2
capping layer is deposited by e-beam
evaporation.
Figure 3.4 Electrical properties of the passivated transistor with Gd source/drain extensions. (a) Schematic diagram
showing the fabrication process of the passivated individual-gated n-type transistor. Starting from the individual
back-gated transistor with Ti/Pd metal contacts, Gd source and drain extensions are patterned by e-beam lithography,
followed by SiO
2
passivation deposited by e-beam evaporation. (b) Transfer characteristics of an individual back-gated
transistor (L = 2 μm, W = 5 μm) with Ti/Pd metal contacts. (c) Transfer characteristics of the same device after adding
Gd source/drain extensions by e-beam lithography. (d) Transfer characteristics of the same device with Ti/Pd plus Gd
source/drain extensions before and after SiO
2
passivation measured at V
D
= 1 V. (e) Transfer characteristics of a typical
device with only Ti/Pd metal contacts before and after SiO
2
passivation measured at V
D
= 1 V .
-10 -5 0 5 10
0.0
0.5
1.0
1.5
2.0
2.5
V
D
= 1 V
Before SiO
2
passivation
After SiO
2
passivation
Drain Current (μA)
Gate Voltage (V)
-10 -5 0 5 10
0
1
2
3
4
V
D
= 1 V
Before SiO
2
passivation
After SiO
2
passivation
Drain Current (μA)
Gate Voltage (V)
a
c
d
b
e
Pristine Ti/Pd-contacted device After adding Gd extensions After SiO
2
passivation
-10 -5 0 5 10
0
1
2
3
4
VD = 1.0 V
VD = 0.8 V
VD = 0.6 V
VD = 0.4 V
VD = 0.2 V
Drain Current (μA)
Gate Voltage (V)
-10 -5 0 5 10
0
1
2
3
4
5
6
VD = 1.0 V
VD = 0.8 V
VD = 0.6 V
VD = 0.4 V
VD = 0.2 V
Drain Current (μA)
Gate Voltage (V)
Ti/Pd contacts Ti/Pd + Gd contacts
Shift of V
T
Shift of V
T
58
The transfer characteristics of the device with Gd source/drain extensions before
and after passivation are shown in Figure 3.4d. The figure indicates that after passivation
the p-type conduction is suppressed, and the n-type conduction becomes predominant.
The suppression of p-type conduction is likely due to the desorption of adsorbed oxygen
in the high-vacuum chamber and to the ensuing SiO
2
passivation, which makes the
nanotubes more intrinsic. We have also tested poly(methyl methacrylate) (PMMA)
passivation for the Gd-contacted devices and have found that it is ineffective for
suppressing the p-type conduction of the pristine ambipolar devices as opposed to the
effective SiO
2
passivation. The data in Figure 3.5 shows that for those Gd-contacted
devices which exhibit ambipolar transfer characteristics in ambient environment, even
with PMMA passivation, the transfer characteristics still remain to be amiboplar. This
observation is in consistent with the literature that nanotube transistors can be converted
into n-type by PMMA passivation only upon low oxygen exposure (10
-2
Torr) but not
under ambient air pressure [10].
Figure 3.5 Transfer (I
D
–V
G
) characteristics of a Gd-contacted nanotube transistor measured at V
D
= 1 V before and after
PMMA passivation.
-15 -10 -5 0 5 10 15
30
40
50
60
70
Drain Current (μA)
Gate Voltage (V)
Before PMMA passivation
After PMMA passivation
VD = 1V
59
Moreover, we have also observed that the n-type on-current degraded after the
SiO
2
passivation, and this is observed from most devices tested. The degradation of the
n-type on-current might be related to either the oxidation of Gd in air during the device
fabrication process, before the SiO
2
passivation layer is deposited, or the SiO
2
passivation,
which leads to increased carrier scattering at the oxide/nanotube interface.
SiO
2
passivation is also performed to Pd-contacted transistors and the results are
shown in Figure 3.4e. Suppression of p-type conduction is also observed from these
devices. However, the device remains to be p-type after passivation. This is because Pd
aligns with the valence band of carbon nanotubes, so the schottky barrier for electrons is
still significant even though the nanotubes themselves become more intrinsic, and thus
the electron conduction is still much weaker compared with hole conduction. Moreover,
from both Gd- and Pd-contacted transistors shown in Figure 3.4d and e, one can observe
the shift of threshold voltage, which indicates the shift of Fermi level of carbon
nanotubes after passivation. Before passivation, the adsorption of oxygen in air leads to
the charge transfer to the nanotubes, resulting in p-doping and shifting the Fermi level of
the nanotubes to close to the valence band [10,30-33]. After passivation, due to the
desorption of oxygen, the Fermi level of the carbon nanotubes shifts from close to the
valence band to approximately the middle of the bandgap. As a consequence, the
threshold voltage shifts toward a more negative value for both Gd-contacted n-type and
Pd-contacted p-type devices.
60
3.3 Carbon nanotube diode using Pd and Gd contacts
Using similar approach, diode devices can also be achieved. The schematic
diagram and the optical microscope and SEM images (with artificial color) of the diode
device are shown in Figure 3.6a–c, respectively. The device fabrication is similar to the
above-mentioned passivated individual-gated n-type transistor, except that the Gd
extension is only patterned to one of the electrodes. In this case, Pd will align with the
valence band and form ohmic contact for holes at one terminal, and Gd will align with
the conduction band and form ohmic contact for electrons at the other terminal. This will
result in the PN-junction, and the corresponding energy band diagram in equilibrium,
forward bias and reverse bias are shown in Figure 3.6g–i, respectively. With positive
voltages applied to the p-side, the device operates in the forward-bias region, and the
barrier height reduces. Consequently, current flow increases exponentially with the
applied positive bias voltage. In contrast, with negative voltages applied to the p-side, the
device operates in the reverse-bias region, and the barrier height increases, preventing the
current from flowing. The above-mentioned processes translate into the two-terminal I–V
characteristic of the PN-junction shown in Figure 3.6d and e (linear and logarithm scale,
respectively), which exhibits clear rectifying behavior. Moreover, by changing the gate
voltages applied to the diode, the engery band of the nanotube in the channel can be
modulated, and this results in the modulation of the current. The gate dependence of the
I–V characteristics of the diode is plotted in Figure 3.6f.
61
Figure 3.6 Aligned nanotube PN junction based on Pd and Gd metal contacts. (a) Schematic diagram of a PN junction
based on Pd and Gd metal contacts. (b) Optical microscope image of a typical PN diode device. (c) SEM image (with
artificial color) of a typical PN diode device. (d, e) I–V characteristics of the diode device plotted in linear (d) and
logarithm (e) scale, respectively. (f) I–V characteristics measured under different gate voltages. (g, h, i) Energy band
diagrams showing the equilibrium (g), forward-bias (h), and reverse-bias (i) of the diode, respectively.
3.4 Integrated CMOS nanotube inverter
Furthermore, an integrated CMOS inverter is demonstrated with different source
drain metal contacts for optimum pull-up and pull-down performance. The schematic
diagram and optical microscope image of the integrated CMOS inverter are shown in
Figure 3.7a and b. This CMOS inverter features an individual Ti/Au back-gate, a
Pd-contacted p-type device and a Gd-contacted n-type device. Figure 3.7c is the SEM
image (with artificial color) showing the n-type branch of the CMOS inverter, which
b a
e
c
f
-1.0 -0.5 0.0 0.5 1.0
0
10
20
30
40
50
Drain Current (nA)
Drain Voltage (V)
-1.0 -0.5 0.0 0.5 1.0
10
-14
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
Drain Current (A)
Drain Voltage (V)
-1.0 -0.5 0.0 0.5 1.0
0
200
400
600
800
Drain Current (nA)
Drain Voltage (V)
VG = -6V
VG = -4V
VG = -2V
VG = 0V
VG = 2V
VG = 4V
VG = 6V
d
g h i
62
clearly highlights the aligned carbon nanotubes in the channel, original Ti/Pd metal
contacts, Gd source/drain extensions, and Ti/Au back-gate. The transfer characteristics of
the p-type pull-up branch and n-type pull-down branch of the CMOS inverter are shown
in Figure 3.7d and e, respectively, and the corresponding energy band diagrams are
shown as the insets. From their transfer characteristics, we can further derive the output
resistance of the p-type and n-type transistors at different gate voltages. Based on the
derived output resistances and by treating these two transistors as a voltage divider, we
can obtain the simulated inverter voltage transfer characteristics (VTC), as shown in
Figure 3.7f. To measure the VTC of the inverter, 3 V is applied as the V
DD
, and the input
voltage is swept from 0 to 5 V. The measurement results are compared with the
simulation results obtained from Figure 3.7f and the corresponding inverter voltage
transfer characteristics are plotted in Figure 3.7g. From the figure, one can find that the
measurement results match the simulation results well. As input voltage increases, the
output voltage switches from V
DD
to 0, indicating nice CMOS inverter operation. The
switching threshold happens at around V
IN
= 2.65 V when both NMOS and PMOS are
simultaneously on, and this results in a maximum gain of 3.6. The inverter switching
threshold of 2.65 V is slightly larger than one-half of the input sweeping range (2.5 V),
which is because the Pd-contacted p-type device is more conductive than the
Gd-contacted n-type device, resulting in an inverter with stronger pull-up strength.
63
Figure 3.7 Integrated nanotube CMOS inverter based on Pd and Gd metal contacts. (a, b) Schematic diagram (a) and
optical microscope image (b) of the integrated CMOS inverter with different source drain metal contacts, Pd for p-type
branch, and Gd for n-type branch. (c) SEM image (with artificial color) showing the n-type branch of the CMOS
inverter with Gd source/drain extensions. (d, e) Transfer characteristics of the p-type pull-up branch (d) and n-type
pull-down branch (e) of the CMOS inverter, respectively. Inset: energy band diagram of the corresponding devices. (f)
Transfer characteristics of the p- and n-type transistors and the simulated inverter voltage transfer characteristic. (g)
Measured and simulated voltage transfer characteristics of the CMOS inverter.
0 1 23 45
0.0
0.3
0.6
0.9
1.2
1.5
VD = 1.0 V
VD = 0.8 V
VD = 0.6 V
VD = 0.4 V
VD = 0.2 V
Drain Current (μA)
Gate Voltage (V)
01 23 45
0.0
0.1
0.2
0.3
0.4
0.5
VD = 1.0 V
VD = 0.8 V
VD = 0.6 V
VD = 0.4 V
VD = 0.2 V
Drain Current (μA)
Gate Voltage (V)
01 23 45
0.0
0.5
1.0
1.5
Gate Voltage (V)
Drain Current (μA)
Inverter VTC
simulation results
0
1
2
3
Output Voltage (V)
01 23 45
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Simulation Results
Measurement Results
Output Voltage (V)
Input Voltage (V)
Gain = 5.1 (Simulation)
Gain = 3.6 (Measurement)
b
d e
f g
c
a
64
3.5 Summary
In summary, we have reported significant progress on metal contact engineering for
air-stable n-type transistors, PN junctions, and CMOS integrated circuits using
horizontally aligned carbon nanotubes. This scalable approach can serve as the building
block for future nanotube-based CMOS integrated circuit applications.
65
Chapter 3. References
1. Bockrath, M.; Cobden, D.; McEuen, P.; Chopra, N.; Zettl, A.; Thess, A.; Smalley, R.
Single-Electron Transport in Ropes of Carbon Nanotubes. Science 1997, 275,
1922–1925.
2. Wildoer, J.; Venema, L.; Rinzler, A.; Smalley, R.; Dekker, C. Electronic Structure of
Atomically Resolved Carbon Nanotubes. Nature 1998, 391, 59–62.
3. Odom, T.; Huang, J.; Kim, P. Lieber, C. Atomic Structure and Electronic Properties
of Single-Walled Carbon Nanotubes. Nature 1998, 391, 62–64.
4. Tans, S.; Verschueren, A.; Dekker, C. Room-Temperature Transistor Based on a
Single Carbon Nanotube. Nature 1998, 393, 49–52.
5. Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, P. Single- and Multi-Wall
Carbon Nanotube Field-Effect Transistors. Appl. Phys. Lett. 1998, 73, 2447–2449.
6. Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654–657.
7. Durkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39.
8. Zhou, X.; Park, J. Y.; Huang, S.; Liu, J.; McEuen, P. L. Band Structure, Phonon
Scattering, and the Performance Limit of Single-Walled Carbon Nanotube
Transistors. Phys. Rev. Lett. 2005, 95, 146805-1–146805-4.
9. Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon
Nanotube Transistors. Science 2001, 294, 1317–1320.
10. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, P. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
11. Liu, X.; Lee, C.; Han, J.; Zhou, C. Carbon Nanotube Field-Effect Inverters. Appl.
Phys. Lett. 2001, 79, 3329–3331.
12. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays
for Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2,
929–932.
13. Chen, Z.; Appenzeller, J.; Lin, Y .; Oakley, J. S.; Rinzler, A. G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, P. An Integrated Logic Circuit Assembled on a Single
Carbon Nanotube. Science 2006, 311, 1735.
66
14. Shim, M.; Javey, A.; Kam, N. W. S.; Dai, H. Polymer Functionalization for
Air-Stable n-Type Carbon Nanotube Field-Effect Transistors. J. Am. Chem. Soc.
2001, 123, 11512–11513.
15. Klinke, C.; Chen, J.; Afzali, A.; Avouris, P. Charge Transfer Induced Polarity
Switching in Carbon Nanotube Transistors. Nano Lett. 2005, 5, 555–558.
16. Lin, Y.; Appenzeller, J.; Knoch, J. Avouris, P. High-Performance Carbon Nanotube
Field-Effect Transistor with Tunable Polarities. IEEE Trans. Nanotechnol. 2005, 4,
481–489.
17. Zhang, Z.; Liang, X.; Wang, S.; Yao, K.; Hu, Y .; Zhu, Y .; Chen, Q.; Zhou, W.; Li, Y .;
Yao, Y.; Zhang, J.; Peng, L. Doping-Free Fabrication of Carbon Nanotube Based
Ballistic CMOS Devices and Circuits. Nano Lett. 2007, 7, 3603–3607.
18. Wang, S.; Zhang, Z.; Ding, L.; Liang, X.; Shen, J.; Xu, H.; Chen, Q.; Cui, R.; Li, Y .;
Peng, L. A Doping-Free Carbon Nanotube CMOS Inverter-Based Bipolar Diode
and Ambipolar Transistor. Adv. Mater. 2008, 20, 3258–3262.
19. Ding, L.; Wang, S.; Zhang, Z.; Zeng, Q.; Wang, Z.; Pei, T.; Yang, L.; Liang, X.;
Shen, J.; Chen, Q.; Cui, R.; Li, Y.; Peng L. Y-Contacted High-Performance n-Type
Single-Walled Carbon Nanotube Field-Effect Transistors - Scaling and Comparison
with Sc-Contacted Devices. Nano Lett. 2009, 9, 4209–4214.
20. Ismach, A.; Segev, L.; Wachtel, E.; Joselevich, E. Atomic-Step-Templated
Formation of Single Wall Carbon Nanotube Patterns. Angew. Chem., Int. Ed. 2004,
43, 6140–6143.
21. Ismach, A.; Kantorovich, D.; Joselevich, E. Carbon Nanotube
Graphoepitaxy: Highly Oriented Growth by Faceted Nanosteps. J. Am. Chem. Soc.
2005, 127, 11554–11555.
22. Han, S.; Liu, X.; Zhou, C. Template-Free Directional Growth of Single-Walled
Carbon Nanotubes on a- and r-Plane Sapphire. J. Am. Chem. Soc. 2005, 127,
5294–5295.
23. Kocabas, C.; Hur, S.; Gaur, A.; Meitl, M.; Shim, M.; Rogers, J. Guided Growth of
Large-Scale, Horizontally Aligned Arrays of Single-Walled Carbon Nanotubes and
Their Use in Thin-Film Transistors. Small 2005, 1, 1110–1116.
24. Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S.
V.; Rogers, J. A. High-Performance Electronics Using Dense, Perfectly Aligned
Arrays of Single-Walled Carbon Nanotubes. Nat. Nanotechnol. 2007, 2, 230–236.
67
25. Liu, X.; Han, S.; Zhou, C. Novel Nanotube-on-Insulator (NOI) Approach toward
Single-Walled Carbon Nanotube Devices. Nano Lett. 2006, 6, 34–39.
26. Wang, C.; Ryu, K.; Badmaev, A.; Patil, N.; Lin, A.; Mitra, S.; Wong, H.-S. P.; Zhou,
C. Device Study, Chemical Doping and Logic Circuits Based on Transferred
Aligned Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2008, 93,
033101-1–033101-3.
27. Ryu, K.; Badmaev, A.; Wang, C.; Lin, A.; Patil, N.; Gomez, L.; Kumar, A.; Mitra,
S.; Wong, H.-S. P.; Zhou, C. CMOS-Analogous Wafer-Scale Nanotube-on-Insulator
Approach for Submicrometer Devices and Integrated Circuits Using Aligned
Nanotubes. Nano Lett. 2009, 9, 189–197.
28. Kim, H.; Jeon, E.; Kim, J.; So, H.; Chang, H.; Lee, J.; Park, N. Air-Stable n-type
Operation of Gd-Contacted Carbon Nanotube Field Effect Transistors. Appl. Phys.
Lett. 2008, 93, 123106-1–123106-3.
29. Collins, P. G.; Arnold, M. S.; Avouris, P. Engineering Carbon Nanotubes and
Nanotube Circuits Using Electrical Breakdown. Science 2001, 292, 706–709.
30. Collins, P. G.; Bradley, K.; Ishigami, M.; Zettl, A. Extreme Oxygen Sensitivity of
Electronic Properties of Carbon Nanotubes. Science 2000, 287, 1801–1804.
31. Sumanasekera, G. U.; Adu, C. K. W.; Fang, S.; Eklund, P. C. Effects of Gas
Adsorption and Collisions on Electrical Transport in Single-Walled Carbon
Nanotubes. Phys. Rev. Lett. 2000, 85, 1096–1099.
32. Bradley, K.; Jhi, S.-H.; Collins, P. G.; Hone, J.; Cohen, M. L.; Louie, S. G.; Zettl, A.
Is the Intrinsic Thermoelectric Power of Carbon Nanotubes Positive? Phys. Rev.
Lett. 2000, 85, 4361–4364.
33. Jhi, S.-H.; Louie, S. G.; Cohen, M. L. Electronic Properties of Oxidized Carbon
Nanotubes. Phys. Rev. Lett. 2000, 85, 1710–1713.
68
Chapter 4. Synthesis and Device Applications of High-Density
Aligned Carbon Nanotubes Using Low-Pressure Chemical
Vapor Deposition and Stacked Multiple Transfer
4.1 Introduction
The application of carbon nanotubes in solid-state electronic devices has
stimulated considerable interest due to the extraordinary electronic properties carbon
nanotubes can offer [1-5]. Among various types of devices, carbon nanotube field-effect
transistors have been extensively used in the demonstration of digital [6-10], analog, and
radio-frequency (RF) [11-16] integrated circuits. Transistors using single nanotubes have
been studied and found to offer way better performance compared to silicon transistors in
terms of drive-current density, normalized transconductance, mobility etc, when the
performance metrics are normalized to the nanotube diameter. Besides single nanotube
transistors, another approach is to employ multiple parallel aligned nanotubes and treat
them as a thin-film transistor. Among many nanotube synthesis techniques, aligned
carbon nanotube growth [17-23] is most desirable for electronic devices owing to its
advantages of registration-free fabrication, high device yield, superior device
performance, and small device-to-device variation. For aligned nanotubes, one of the
most important metrics is the nanotube density. High-density aligned nanotubes can be
extremely helpful in improving the current driving capability, transconductance, and
cut-off frequency of devices.
69
Inspired by the superior electronic properties of carbon nanotubes and the
significant advantage aligned nanotubes can offer, field-effect transistors using aligned
nanotubes have been reported by many research groups including our own [21-24].
However, in those reports, the nanotube density has typically been restricted to 5 to 10
tubes/µm, which greatly limits the electrical performance such as drive-current and
transconductance of the nanotube transistors. As a result, producing high-density aligned
nanotubes has become one of the greatest challenges, and significant effort has been
devoted to the optimized one-step synthesis [25] and the recently-reported two-step
synthesis [26]. On the other hand, little has been done to investigate the potential
applications of such high-density aligned nanotubes for high performance nanotube
transistors.
In this chapter, we report another method of producing high-density aligned
nanotubes, as well as their application in high performance submicron nanotube
transistors. We report the use of low-pressure chemical vapor deposition (LPCVD) to
reproducibly achieve perfectly aligned nanotubes with density as high as 30 tubes/ μm. A
stacked multiple transfer technique was then used to transfer the aligned nanotubes from
multiple starting samples to one target substrate, thus allowing us to double, triple, or
quadruple the nanotube density. A density of 55 tubes/ μm has been demonstrated and
further increases can be envisioned. Carbon nanotube field-effect transistors were then
fabricated on the high-density aligned nanotubes. Electrical measurements found that for
the devices with channel length L = 0.5 μm, the increase in nanotube density leads to
five-fold and eight-fold increases in the on-current density (I
on
/W) and normalized
70
transconductance (g
m
/W), respectively, compared with our previous devices fabricated on
nanotubes with a typical density of 5 tubes/ μm [24]. Moreover, benchmarking with the
aligned carbon nanotube transistors in the literature indicates that our devices exhibit the
best performance so far, which is attributed to both the increased nanotube density and
scaling down of channel length. The electrical measurements also suggest the great
potential of using our high-density aligned nanotubes for analog and RF devices and
circuits.
4.2 Ultra high density aligned nanotube synthesis
High-density aligned nanotubes were synthesized using LPCVD with an ethanol
bubbler and was carried out at 500 Torr. We have tested various growth conditions within
the range of 850 °C < T < 950 °C, 300 Torr < P < 760 Torr, and found 900 °C and 500
Torr to be the optimum growth condition for our CVD system. More details about the
nanotube synthesis process are described as follows. Photolithography was used to
pattern stripes on the stable-temperature (ST)-cut quartz substrate (Hoffman Materials
Inc.). 2 Å iron was then deposited using thermal evaporator followed by the lift-off
process to form the catalyst stripes. The samples were first annealed in air at 900 °C for 1
hour, and LPCVD was then used to grow aligned nanotubes between the catalyst stripes
at 900 °C. The feed gases were 300 sccm H
2
and 120 sccm Ar flowing through an ethanol
bubbler kept at 0 °C. The furnace was connected to a mechanical pump and the pressure
inside the quartz tube was kept constant at 500 Torr using a butterfly valve.
71
Figure 4.1 High-density aligned carbon nanotubes synthesized by low-pressure chemical vapor deposition. (a)
FE-SEM image showing the aligned nanotubes grown on quartz substrate. (b) FE-SEM image at high magnification
showing the as-grown aligned nanotubes with an average density of 27 tubes/ μm. (c) AFM image showing the aligned
nanotubes with an average density of 19 tubes/ μm. (d) Diameter distribution of the nanotubes extracted from the AFM
image. The diameter is 1.388 ± 0.457 nm. (e, f) Raman spectra showing the (e) D-band and (f) G’-band of the as-grown
aligned nanotubes with high-density (30 tubes/μm) using ethanol LPCVD and typical density (5 tubes/ μm) using
methane CVD. (e) Inset: RBM of the high density nanotube sample.
a b
c
0.5 1.0 1.5 2.0 2.5
0
1
2
3
4
5
6
7
8
Number of Tubes
Diameter (nm)
Average d = 1.388 nm
d
e
2400 2500 2600 2700 2800 2900
Raman Shift (cm
-1
)
Ethanol LPCVD
Methane CVD
f
1300 1400 1500 1600 1700
Raman Shift (cm
-1
)
Ethanol LPCVD
Methane CVD
D band
G band
G’ band
150 200 250 300
Raman Shift (cm
-1
)
186.97 cm
-1
72
After synthesis, field-emission scanning electron microscopy (FE-SEM) was used
to inspect the sample, and an image of the as-grown nanotubes on quartz substrate is
shown in Figure 4.1a. The image shows high-density uniform aligned nanotube growth
between the catalyst stripes. The width of the catalyst stripe is 4 μm and the distance
between two different stripes is 100 μm. Our LPCVD synthesis process is very
reproducible, and uniform growth can be achieved throughout the sample. Using this
LPCVD recipe, a typical nanotube density of 15 ~ 20 tubes/ μm can be achieved
throughout the sample, while a density of 30 tubes/ μm can be achieved under optimal
growth conditions at certain locations of the sample. Figure 4.1b shows an FE-SEM
image of the aligned nanotubes at higher magnification, and the average nanotube density
is measured to be around 27 tubes/ μm. Atomic force microscopy (AFM) was used to
quantify the nanotube diameter, and the AFM image of the high-density aligned
nanotubes is shown in Figure 4.1c. The nanotube density is around 19 tubes/ μm in this
image and the diameter distribution is plotted in Figure 4.1d, from which the nanotube
diameter is measured to be 1.388 ± 0.457 nm.
Carbon nanotube structural defects and impurities play an important role in
determining the ultimate transport properties of nanotube-based devices. We performed
micro-Raman spectroscopy measurements using an excitation laser energy of 2.32 eV on
the high-density aligned nanotubes as well as on the nanotube arrays with regular
nanotube density (~5 tubes/ μm) that were obtained using methane as the carbon source.
Typical normalized stacked Raman spectra of high and low nanotube density samples
show a nearly identical D-band to G-band intensity ratio (I
D
/I
G
) of 0.017 (Figure 4.1e),
73
which suggests that the use of ethanol during high-density nanotube synthesis did not
yield increased structural defects or additional oxygen functionalities on the nanotubes.
However, a significant broadening of the Raman G’-band of around 31.6 cm
-1
gives
evidence of an increased inter-tube interaction for high-density nanotubes (Figure 4.1f).
This can be attributed to the formation of nanotube bundles or to the close proximity of
certain nanotubes forming the parallel arrays on the high-density sample. Moreover, the
radial breathing mode (RBM) frequency of the high density sample (shown in the inset of
Figure 4.1e) is 186.97 cm
-1
. This corresponds to a diameter of 1.326 nm and the value
agrees with the AFM measurement results.
4.3 Stacked multiple transfer technique
Compared with the density of 5 tubes/ μm reported in our previous publications
[23,24], the above-reported nanotube density of 30 tubes/ μm using ethanol LPCVD is a
significant improvement. To further improve the nanotube density, multiple transfer can
be used which allows us to transfer nanotubes from multiple quartz samples to one target
substrate thus multiplying the density. The multiple transfer technique utilizes the gold
film plus thermal release tape method reported in our previous publications [23,24],
which allows the transfer of the as-grown nanotubes from quartz substrates to Si/SiO
2
substrates or many other substrates. For the transfer process, 30 nm gold film was
deposited onto the quartz substrates containing nanotubes, and thermal release tape (#
3198M from Nitto Denko) was used to peel off the gold film together with the nanotubes,
which was then pressed with a polydimethylsiloxane (PDMS) stamp against the targeted
74
substrates preheated on a hotplate at 140 °C for 10 seconds. After this process, the
thermal tape was peeled off with the PDMS stamp. Finally, oxygen plasma was used to
clean the tape residue and gold etchant was used to remove the gold film, leaving only
aligned nanotubes on the target substrate.
We have previously reported the layer-by-layer multiple transfer technique [23],
in which we transfer the nanotubes to Si/SiO
2
substrates using gold film, etch away the
gold, and then repeat the transfer. However, this technique was limited to two samples,
beyond which the adhesion between the gold film and the substrate became problematic.
Here in order to overcome the adhesion problem, we developed a stacked multiple
transfer method, in which the gold film containing the aligned nanotubes can be
repeatedly transferred on top of the previous gold film, and etched at the same time using
the gold etchant, so that the nanotubes would collapse onto the substrates. We have tested
our stacked multiple transfer technique and found that the same transfer process can be
repeated up to four times without any adhesion problem. The schematic of the
above-mentioned multiple transfer process is illustrated in Figure 4.2a, and the FE-SEM
images of the aligned nanotubes before transfer, after one-time transfer, two-time transfer,
and four-time transfer are shown in Figure 4.2b–e, respectively. The corresponding
densities are 15 tubes/ μm, 15 tubes/ μm, 29 tubes/ μm, and 55 tubes/ μm. From the SEM
images, one can find that the multiple transfer process indeed increases the nanotube
density effectively.
75
Figure 4.2 Using stacked multiple transfer to further increase the nanotube density. (a) Schematic illustration showing
the stacked multiple transfer process. (b) FE-SEM image of the as-grown aligned nanotubes on quartz substrate with a
density of 15 tubes/ μm. (c, d, e) FE-SEM images showing the aligned nanotubes transferred to Si/SiO
2
substrates with
one-time, two-time and four-time transfer, respectively. The corresponding average densities are 15 tubes/ μm, 29
tubes/ μm, and 55 tubes/ μm.
We observed that the stacked multiple transfer process is sensitive to the thickness
of the gold film. In order to achieve high-yield transfer, it is crucial to use thin gold film
As‐grown aligned
nanotubes on quartz
Gold film plus
thermal releasing tape
Transfer to Si/SiO
2
substrate by
stacked transfer
Gold etching
High‐density aligned
nanotubes on Si/SiO
2
a
b c
d e
76
and keep the perturbation during the gold etching process to a minimum. We have tested
the multiple transfer using 30nm and 100nm gold films and have found that when thin
gold film (30 nm) is used, the nanotubes all collapse onto the substrates during the
etching process for samples with one-time, two-time, and three-time transfers. The
transfer yield is close to 100% and the nanotubes remain relatively straight for all the
samples tested. In contrast, when thicker gold film (100 nm) is used, the transfer yield
decreases as the number of transfers goes up. Moreover, as the density increases, the
demands on the orientational alignment increases. Therefore, it is crucial to use
accurately diced samples and perform careful alignment during the multiple transfer
process.
We also note that the nanotubes after transfer are not as straight as before, which
can be attributed to the perturbation experienced by the nanotubes during the gold etching
and deionized (DI) water rinsing step. This slight waviness can still lead to increased
tube-to-tube interactions, and may result in unwanted cross-talking and limit the
high-frequency performance of the nanotube transistors. Therefore, methods to improve
the straightness of the transferred nanotubes such as the use of supercritical drying during
the etching process are worthy of further investigation. Moreover, by combining our
LPCVD and stacked multiple transfer technique, it should be possible to achieve a
nanotube density of 100 tubes/ μm or 200 tubes/ μm in the future, which is critical in order
to ensure sufficient performance gains over state-of-the-art silicon complementary
metal-oxide-semiconductor (CMOS) transistors with shrinking lithographic dimensions
[27].
77
4.4 Electrical properties of the high density aligned nanotubes
High-density aligned carbon nanotubes are very important and desirable for
analog and RF applications where the frequency response of the device matters [28,29].
Intuitively, higher nanotube density will result in higher drive-current and larger
transconductance. Since the cut-off frequency of the device is /[2 ( )]
T m gs gd
fg C C π ≈× + ,
increasing the nanotube density should increase the device cut-off frequency
approximately proportionally [29]. Moreover, if we define the nanotube filling ratio as
nanotube density times nanotube diameter divided by one micron, as the nanotube
density increases, the filling ratio increases. Ideally, we want the device channel to be
covered with closely packed aligned carbon nanotubes with a filling ratio of 100%. This
will increase the transconductance (g
m
) without a significant increase in the parasitic
capacitance, allowing the maximum RF performance to be achieved [29].
To evaluate the electrical performance of such high-density aligned nanotubes
based on multiple transfer, back-gated transistors were fabricated. 50 nm SiO
2
was used
as the back-gate dielectric, and the source/drain electrodes were patterned by
photolithography. 2 nm Ti and 60 nm Pd were deposited by e-beam evaporation,
followed by the lift-off process to form the source and drain metal contacts.
Photolithography plus O
2
plasma was used to remove the unwanted nanotubes outside the
device channel region in order to achieve accurate channel length and width, and to
remove any possible leakage between the devices. A schematic diagram of the
back-gated nanotube transistor used in this study is shown in Figure 4.3a. Such
78
back-gated transistors were made with channel width (W) of 10, 20, 50, 100, and 200 μm,
and channel length (L) of 4, 10, 20, 50, and 100 μm.
Figure 4.3 Electrical measurements of the back-gated nanotube transistors using nanotubes with one-time, two-time
and four-time transfer. (a) Schematic illustration of the back-gated transistor with high-density aligned nanotubes. (b)
Plot of the current density (I
on
/W) versus channel length (L) for devices fabricated using nanotubes with different
density. (c) Plot of I
on
/W versus the reciprocal of channel length (1/L) for devices fabricated using nanotubes with
different density. (d, e) Plots of (d) the normalized transconductance (g
m
/W), and (e) device mobility ( μ
device
) versus
channel length for devices fabricated using nanotubes with different density. (f) Plot showing the I
on
/W, I
on
/W
eff
, g
m
/W
and g
m
/W
eff
versus nanotube density for the high-density aligned nanotube transistors.
c d
0.00 0.05 0.10 0.15 0.20 0.25
0
10
20
30
40
One-time transfer
Two-time transfer
Four-time transfer
I
on
/W (μA/μm)
1/L (μm
-1
)
b
0 2040 6080 100
0.1
1
10
One-time transfer
Two-time transfer
Four-time transfer
g
m
/W (μS/μm)
Channel Length (μm)
0 204060 80 100
0
10
20
30
40
One-time transfer
Two-time transfer
Four-time transfer
I
on
/W (μA/μm)
Channel Length (μm)
e
f
10 20 30 40 50 60
0
15
30
45
500
550
600
650
700
I
on
/W
I
on
/W
eff
Nanotube Density (tubes/μm)
I
on
/W, I
on
/W
eff
(μA/μm)
0
2
4
6
30
40
50
60
70
g
m
/W
g
m
/W
eff
g
m
/W, g
m
/W
eff
(μS/μm)
a
0 20 40 60 80 100
0
100
200
300
400
500
600
One-time transfer
Two-time transfer
Four-time transfer
Device Mobility (cm
2
/Vs)
Channel Length (μm)
79
We have measured such back-gated nanotube transistors with various channel
lengths, channel widths, and different nanotube densities. The results are summarized in
Figure 4.3. Figure 4.3b exhibits the on-current densities (I
on
/W) versus channel length (L)
for transistors with different times of transfer and thus, different densities. The definition
of on-current here is the drain-current measured at V
D
= 1 V and V
G
= -10 V. This figure
indicates that as the nanotube density increases, the drive current also increases as
expected. The highest on-current density is around 41 μA/ μm and is achieved in the
devices with four-time transfer and channel length of 4 μm. To give more insight into the
relationship between the on-current density and channel length, the on-current density is
plotted versus the reciprocal of channel length as shown in Figure 4.3c. From the figure,
one can find that the on-current density is approximately inversely proportional to the
channel length.
Transconductance (g
m
) is another important figure of merit for nanotube
field-effect transistors as it dictates the cut-off frequency of the devices. The normalized
device transconductance (g
m
/W) of devices with various channel lengths are characterized
and are plotted in Figure 4.3d. In this figure, g
m
is extracted from the maximum slope of
the transfer characteristics measured at V
D
= 1 V, and is normalized to device channel
width. From the figure, one can find that as channel length increases, g
m
/W decreases,
which is because g
m
/W is also inversely proportional to the channel length. Moreover,
similar to the on-current density, the normalized transconductance is also approximately
proportional to nanotube density.
80
The device mobility can be further extracted based on the normalized
transconductance. Under V
D
= 1 V, devices operate in the triode region, so that the device
mobility can be calculated from the following equation
dm
device
Dox g Dox
dI g LL
VC W dV V C W
μ=⋅ = ⋅ (1)
where L and W are the device channel length and width, V
D
= 1 V, and C
ox
is the gate
capacitance per unit area. C
ox
can be calculated using the parallel plate model and the
effective device mobility can thus be derived. We note that a more rigorous model can be
used by considering the electrostatic coupling between nanotubes to derive the nanotube
mobility [21,30]. However, the model assumes that the nanotubes are equally spaced. In
order to obtain the capacitance accurately, non-ideal effects such as nanotube bundling,
uniformity of nanotube density across the device channel, and percentage of nanotubes
bridging the source/drain electrodes has to be taken into consideration, and those are
difficult to be modeled rigorously. We have calculated the effective device mobility of
transistors with various channel length, width and nanotube density, and the results are
plotted in Figure 4.3e. It is worth noting that we did not attempt to account for the contact
resistance between the nanotubes and the source/drain electrodes. Therefore, we observe
that as the channel length increases, the device mobility increases, indicating that there is
certain amount of contact resistance in the metal/nanotube contacts. As the channel
length increases, the effect of metal/nanotube contacts become less significant and the
mobility increases [21]. The highest effective device mobility from the back-gated
81
transistors is around 607 cm
2
V
-1
s
-1
achieved in devices with four-time transfer and 100
μm channel length.
To further elucidate the properties of the nanotubes, we define effective channel
width (W
eff
) as the average nanotube diameter multiplied by the total number of
nanotubes in the channel. Figure 4.3f summarizes the variation of I
on
/W, g
m
/W, effective
on-current density (I
on
/W
eff
), and effective normalized transconductance (g
m
/W
eff
) as a
function of nanotube density. The effective on-current density and effective normalized
transconductance are defined as the I
on
and g
m
of the devices normalized by the effective
channel width. I
on
/W
eff
and g
m
/W
eff
are good measures of performance per nanotube and
can be calculated from the equations below
/
/
on
on eff
I W
IW
Dd
=
⋅
,
/
/
m
meff
gW
gW
Dd
=
⋅
(2)
where D stands for the nanotube density in tubes/ μm and d is the nanotube diameter
which is measured to be around 0.0014 μm for our nanotubes. From Figure 4.3f, we can
find that I
on
/W and g
m
/W, which represent the device performance, increase
monotonically with nanotube density, while I
on
/W
eff
and g
m
/W
eff
, which represent the
nanotube performance, decrease with nanotube density. The I
on
/W
eff
decreases by about
21.1% and g
m
/W
eff
decreases by about 12.7% as the nanotube density increases from 15
tubes/ μm to 55 tubes/ μm. The slight decrease in nanotube performance can be attributed
to the formation of nanotube bundles during the multiple transfer process, and is found to
be not detrimental to overall device performance.
82
4.5 High performance submicron nanotube transistors
Similar to the silicon metal-oxide-semiconductor field effect transistors
(MOSFETs) widely used in current semiconductor industry, nanotube field-effect
transistors with better performance can also be achieved by scaling down the channel
length to the submicron regime as well as by increasing the gate strength by adopting
high- κ dielectric layer. A schematic illustration of such a high performance submicron
nanotube transistor is shown in Figure 4.4a, and the device fabrication processes are
briefly described as follows. First, individual back-gates are patterned using
photolithography on top of the Si/SiO
2
substrate, and 5 Å Ti and 50 nm Au were
deposited to act as the back-gate electrode. 50nm HfO
2
was then deposited by atomic
layer deposition (ALD) to act as the gate dielectric. High-density aligned nanotubes were
then transferred to the substrate with Ti/Au back-gate and HfO
2
gate dielectric. The rest
of the fabrication steps including the source/drain electrodes patterning and unwanted
nanotube etching are very similar to those used in the fabrication of the back-gated
transistor discussed previously except that an I-line wafer stepper (GCA Autostep 200)
was used to pattern the source/drain electrodes instead of contact aligner. The use of a
stepper allows us to achieve minimum channel length of 500 nm in a scalable manner. An
FE-SEM image of the channel of a typical high performance submicron nanotube
transistor (L = 500 nm) is shown in Figure 4.4b where the average nanotube density is
around 30 tubes/ μm.
83
Figure 4.4 Electrical properties of high performance submicron transistors with high-density aligned nanotubes. (a)
Schematic diagram of the high performance submicron nanotube transistor with Ti/Au individual back-gate and 50 nm
HfO
2
high- κ dielectric. (b) FE-SEM image showing the channel of a submicron high performance transistor. The
channel length is 0.5 μm and the aligned nanotubes in the channel have an average density of 30 tubes/ μm. (c, d)
Transfer (I
D
–V
G
) characteristics (red: linear scale, green: log scale) and g
m
–V
G
characteristics (blue) of a high
performance nanotube transistor (L = 0.5 μm, and W = 50 μm) measured at V
D
= 1V (c) before and (d) after electrical
breakdown, respectively. (e) Comparison of the transfer characteristics of the same device before and after electrical
breakdown. (f) Output (I
D
–V
D
) characteristics of the same device after electrical breakdown.
The electrical performance of such high performance devices was characterized.
Figure 4.4c–e are the transfer characteristics (I
D
–V
G
curves) measured at V
D
= 1 V for a
transistor with W = 50 μm and L = 500 nm before and after electrical breakdown. From
10
-3
10
-2
10
-1
10
0
-5.0 -2.5 0.0 2.5 5.0
0.0
0.1
0.2
0.3
0.4
0.5
Gate Voltage (V)
Drain Current (mA)
0
20
40
60
80
100
120
Transconductance (μS)
Drain Current (mA)
1
2
3
4
5
-5.0 -2.5 0.0 2.5 5.0
1
2
3
4
5
Gate Voltage (V)
Drain Current (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Transconductance (mS)
Drain Current (mA)
-5.0 -2.5 0.0 2.5 5.0
1u
10u
100u
1m
Drain Current (A)
Gate Voltage (V)
Before Breakdown
After Breakdown
a b
c d
e f
-0.8 -0.4 0.0 0.4 0.8
-0.2
-0.1
0.0
0.1
0.2
Drain Current (mA)
Drain Voltage (V)
V
G
is from -5V to
5V in 1V steps
84
the curves, one can find that before electrical breakdown, the on-state current of the
device (I
on
) measured at V
D
= 1 V and V
G
= -5 V, is 4.62 mA, which corresponds to I
on
/W
of 92.4 μA/ μm. To the best of our knowledge, this on-current density is the highest so far
report for the aligned nanotube transistors. The maximum transconductance (g
m
) of the
device is measured to be 663.3 μS, which corresponds to g
m
/W of 13.3 μS/ μm. We note
that the on-off ratio of the device is only around 3 due to the coexistence of both metallic
and semiconducting nanotubes. This result agrees with the typical 1/3 metallic nanotube
ratio assuming equal conduction from metallic and semiconducting nanotubes.
By using automated electrical breakdown techniques as discussed in our previous
work [23], metallic nanotubes were selectively removed and the on-off ratio of the device
underwent a significant improvement to around 1000, accompanied by a degradation of
the on-current of around 90% (Figure 4.4e). Assuming a 1/3 metallic nanotube ratio, one
should expect around 33% on-current degradation after electrical breakdown. The much
higher observed degradation of 90% in our measurements can be explained by the
unintentional damage of semiconducting nanotubes under large electrical stress during
the electrical breakdown process. It is possible that along with the metallic nanotubes,
some defective semiconducting nanotubes can also be damaged under high V
D
biases.
More importantly, besides the defective semiconducting nanotubes, there may be some
large diameter semiconducting nanotubes which have small bandgaps and thus will have
small on/off ratios. These semiconducting nanotubes can also be destroyed during the
electrical breakdown process since they cannot be turned-off completely. Both reasons
mentioned above account for the degradation in the on-current of 90% instead of the
85
expected 33%.
From Figure 4.4d, after the electrical breakdown, I
on
/W is 8.3 μA/ μm and g
m
/W is
2.2 μS/ μm. Compared with the results from devices fabricated using aligned nanotubes
with typical density (5 tubes/ μm) reported in our previous publication (I
on
/W = 1.7
μA/ μm and g
m
/W = 0.28 μS/ μm) [24], the values of I
on
/W and g
m
/W reported here are 5
times and 8 times better, respectively. The improvements are due to both the higher
nanotube density and the adoption of high- κ gate dielectric.
Figure 4.4f shows the output characteristics (I
D
–V
D
curves) of the device
measured under different gate biases. Under small negative V
D
biases, i.e., |V
D
| < |V
DSAT
|,
the device operates in the triode region, and the I
D
–V
D
curves appear to be linear,
indicating that Ohmic contacts instead of Schottky contacts are formed between the metal
and the nanotubes. Under larger negative V
D
biases, i.e., |V
D
| > |V
DSAT
|, the device enters
the saturation region, and the drain current begins to saturate. For curves with more
negative V
G
biases (black and red curves), no clear saturation behavior is observed from
the output characteristics. The reason is that |V
DSAT
| is larger for more negative V
G
biases,
so that the device stays in the triode region within the V
D
sweeping range. Moreover, the
asymmetric behavior in the 1st and 3rd quadrants is due to different electrostatics for
positive and negative V
D
, as reported previously [31]. In the 1st quadrant where “drain”
voltage is positive and “source” is grounded, the source and drain terminals are actually
swapped since the source for a p-type transistor is the one with higher voltage. So as
“drain” voltage increase, |V
GS
| increases so that the current increases approximately
quadratically.
86
Figure 4.5 Benchmarking the high performance submicron nanotube transistors using high-density aligned nanotubes
with the previously published work. The drive-current (I
on
/W) is plotted versus year for the previously published
aligned nanotube transistor work at USC, UIUC, Stanford, and Duke.
To justify the high performance of our high-density nanotube transistors, they are
benchmarked with previously published work, and the results are shown in Figure 4.5.
The drive-current (I
on
/W) is plotted versus year for the previously published aligned
nanotube transistor work from University of Southern California (USC) [23,32,33],
University of Illinois at Urbana-Champaign (UIUC) [15,20,21,26], Stranford University
[34,35], and Duke University [36]. From the figure, one can find that by increasing the
nanotube density and scaling down the channel length, our devices with 0.5 μm channel
length exhibit a drive-current of 92.4 μA/ μm, which is the best reported performance to
date. This indicates the great potential of using our approach for future beyond-silicon
nanoelectronics and RF applications.
2005 2006 2007 2008 2009 2010 2011
0.01
0.1
1
10
100
USC
UIUC
Stanford
Duke
This Work
Drive Current (μA/μm)
Year
87
4.6 Summary
In conclusion, we have developed LPCVD and stacked multiple transfer
technique to achieve high density aligned nanotubes with density up to 55 tubes/µm.
High performance submicron nanotube transistors have also been fabricated based on the
high-density aligned nanotubes and electrical measurements show that the devices exhibit
pronounced higher performance in terms of I
on
/W and g
m
/W compared with devices
fabricated on aligned nanotubes with typical density. Our approach holds great potential
for the high performance analog and RF applications.
88
Chapter 4. References
1. Bockrath, M.; Cobden, D.; McEuen, P.; Chopra, N.; Zettl, A.; Thess, A.; Smalley, R.
Single-Electron Transport in Ropes of Carbon Nanotubes. Science 1997, 275,
1922–1925.
2. Wildoer, J.; Venema, L.; Rinzler, A.; Smalley, R.; Dekker, C. Electronic Structure of
Atomically Resolved Carbon Nanotubes. Nature 1998, 391, 59–62.
3. Odom, T.; Huang, J.; Kim, P. Lieber, C. Atomic Structure and Electronic Properties
of Single-Walled Carbon Nanotubes. Nature 1998, 391, 62–64.
4. Tans, S.; Verschueren, A.; Dekker, C. Room-Temperature Transistor Based on a
Single Carbon Nanotube. Nature 1998, 393, 49–52.
5. Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, Ph. Single- and Multi-Wall
Carbon Nanotube Field-Effect Transistors. Appl. Phys. Lett. 1998, 73, 2447–2449.
6. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, Ph. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
7. Liu, X.; Lee, C.; Han, J.; Zhou, C. Carbon Nanotube Field-Effect Inverters. Appl.
Phys. Lett. 2001, 79, 3329–3331.
8. Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon
Nanotube Transistors. Science 2001, 294, 1317–1320.
9. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays
for Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2,
929–932.
10. Chen, Z.; Appenzeller, J.; Lin, Y.; Oakley, J. S.; Rinzler, A.G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, Ph. An Integrated Logic Circuit Assembled on a Single
Carbon Nanotube. Science 2006, 311, 1735.
11. Amlani. I.; Lewis, J.; Lee, K.; Zhang, R.; Deng, J.; Wong, H.-S. P. First
Demonstration of AC Gain from a Single-Walled Carbon Nanotube
Common-Source Amplifier. IEEE International Electron Devices Meeting (IEDM),
San Francisco, USA, 2006, pp 559–562.
12. Li, S.; Yu, Z.; Yen, S.; Tang, W.; Burke, P. Carbon Nanotube Transistor Operation at
2.6 GHz. Nano Lett. 2004, 4, 753–756.
89
13. Louarn, A.; Kapche, F.; Bethoux, J.-M.; Happy, H.; Dambrine, G.; Derycke, V.;
Chenevier, P.; Izard, N.; Goffman, M. F.; Bourgoin, J.-P. Intrinsic Current Gain
Cutoff Frequency of 30 GHz with Carbon Nanotube Transistors. Appl. Phys. Lett.
2007, 90, 233108-1–233108-3.
14. Nougaret, L.; Happy, H.; Dambrine, G.; Derycke, V .; Bourgoin, J. -P.; Green, A. A.;
Hersam, M. C. 80 GHz Field-Effect Transistors Produced Using High Purity
Semiconducting Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2009, 94,
243505-1–243505-3.
15. Kocabas, C.; Kim, H.; Banks, T.; Rogers, J.; Pesetski, A.; Baumgardner, J.;
Krishnaswamy, S.; Zhang, H. Radio Frequency Analog Electronics Based on
Carbon Nanotube Transistors. Proc. Nat. Acad. Sci. 2008, 105, 1405–1409.
16. Kocabas, C.; Dunham, S.; Cao, Q.; Cimino, K.; Ho, X.; Kim, H.; Dawson, D.;
Payne, J.; Stuenkel, M.; Zhang, H.; Banks, T.; Feng, M.; Rotkin, S. V .; Rogers, J. A.
High-Frequency Performance of Submicrometer Transistors That Use Aligned
Arrays of Single-Walled Carbon Nanotubes. Nano Lett. 2009, 9, 1937–1943.
17. Ismach, A.; Segev, L.; Wachtel, E.; Joselevich, E. Atomic-Step-Templated
Formation of Single Wall Carbon Nanotube Patterns. Angew. Chem. Int. Ed. 2004,
43, 6140 –6143.
18. Ismach, A.; Kantorovich, D.; Joselevich, E. Carbon Nanotube
Graphoepitaxy: Highly Oriented Growth by Faceted Nanosteps. J. Am. Chem. Soc.
2005, 127, 11554–11555.
19. Han, S.; Liu, X.; Zhou, C. Template-Free Directional Growth of Single-Walled
Carbon Nanotubes on a- and r-Plane Sapphire. J. Am. Chem. Soc. 2005, 127,
5294–5295.
20. Kocabas, C.; Hur, S.; Gaur, A.; Meitl, M.; Shim, M.; Rogers, J. Guided Growth of
Large-Scale, Horizontally Aligned Arrays of Single-Walled Carbon Nanotubes and
Their Use in Thin-Film Transistors. Small 2005, 1, 1110–1116.
21. Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S.
V.; Rogers, J. A. High-Performance Electronics Using Dense, Perfectly Aligned
Arrays of Single-Walled Carbon Nanotubes. Nat. Nanotechnol. 2007, 2, 230–236.
22. Patil, N.; Lin, A.; Myers, E. R.; Wong, H.-S. P.; Mitra, S. Integrated Wafer-Scale
Growth and Transfer of Directional Carbon Nanotubes and Misaligned Carbon
Nanotube Immune Logic Structures. Proceedings of the 2008 VLSI Technology
Symposium, Honolulu, USA, 2008, pp 205–206.
90
23. Ryu, K.; Badmaev, A.; Wang, C.; Lin, A.; Patil, N.; Gomez, L.; Kumar, A.; Mitra,
S.; Wong, H.-S. P.; Zhou, C. CMOS-Analogous Wafer-Scale Nanotube-on-Insulator
Approach for Submicrometer Devices and Integrated Circuits Using Aligned
Nanotubes. Nano Lett. 2009, 9, 189–197.
24. Wang, C.; Ryu, K.; Badmaev, A.; Patil, N.; Lin, A.; Mitra, S.; Wong, H.-S. P.; Zhou,
C. Device Study, Chemical Doping and Logic Circuits Based on Transferred
Aligned Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2008, 93,
033101-1–033101-3.
25. Ding, L.; Yuan, D.; Liu, J. Growth of High-Density Parallel Arrays of Long
Single-Walled Carbon Nanotubes on Quartz Substrates. J. Am. Chem. Soc. 2008,
130, 5428–5429.
26. Hong, S. W.; Banks, T.; Rogers, J. A. Improved Density in Aligned Arrays of
Single-Walled Carbon Nanotubes by Sequential Chemical Vapor Deposition on
Quartz. Adv. Mater. 2010, 22, 1826–1830.
27. Patil, N.; Deng, J.; Mitra, S.; Wong, H.-S. P. Circuit-Level Performance
Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits.
IEEE Trans. Nanotechnol. 2009, 8, 37–45.
28. Guo, J.; Hasan, S.; Javey, A.; Bosman, G..; Lundstrom, M. Assessment of
High-Frequency Performance Potential of Carbon Nanotube Transistors. IEEE
Trans. Nanotechnol. 2005, 4, 715–721.
29. Rutherglen, C.; Jain, D.; Burke, P. Nanotube Electronics for Radiofrequency
Applications. Nat. Nanotechnol. 2009, 4, 811–819.
30. Cao, Q.; Xia, M.; Kocabas, C.; Shim, M.; Rogers, J. A.; Rotkin, S. V. Gate
Capacitance Coupling of Singled-Walled Carbon Nanotube Thin-Film Transistors.
Appl. Phys. Lett. 2007, 90, 023516-1–023516-4.
31. Zhou, C.; Kong, J.; Dai, H. Electrical Measurements of Individual Semiconducting
Single-Walled Carbon Nanotubes of Various Diameters. Appl. Phys. Lett. 2000, 76,
1597–1599.
32. Liu, X.; Han, S.; Zhou, C. Novel Nanotube-on-Insulator (NOI) Approach toward
Single-Walled Carbon Nanotube Devices. Nano Lett. 2006, 6, 34–39.
33. Ishikawa, F.; Chang, H.; Ryu, K.; Chen, P.; Badmaev, A.; De Arco Gomez, L.; Shen,
G.; Zhou, C. Transparent Electronics Based on Transfer Printed Aligned Carbon
Nanotubes on Rigid and Flexible Substrates. ACS Nano 2009, 3, 73–79.
91
34. Lin, A.; Patil, N.; Ryu, K.; Badmaev, A.; De Arco Gomez, L.; Zhou, C.; Mitra, S.;
Wong, H.-S. P. Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube
Carbon Nanotube FETs. IEEE Trans. Nanotechnol. 2009, 8, 4–9.
35. Patil, N.; Lin, A.; Myers, E. R.; Ryu, K.; Badmaev, A.; Zhou, C.; Wong, H.-S. P.;
Mitra, S. Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon
Nanotubes. IEEE Trans. Nanotechnol. 2009, 8, 498–504.
36. Ding, L; Tselev, A.; Wang, J.; Yuan, D.; Chu H.; McNicholas, T. P.; Li, Y.; Liu, J.
Selective Growth of Well-Aligned Semiconducting Single-Walled Carbon
Nanotubes. Nano Lett. 2009, 9, 800–805.
92
Chapter 5. Wafer-Scale Fabrication of Separated Carbon
Nanotube Thin-Film Transistors for Display Applications
5.1 Introduction
As the most widely used channel material for thin film transistors (TFTs),
amorphous silicon suffers from drawbacks that it requires high-temperature processing
and the mobility is relatively low [1-6]. Organic TFTs as a replacement for amorphous
silicon based TFTs receives lots of attention, while on the other hand, they also suffer
from poor device mobility [7,8]. Single-walled carbon nanotubes (SWNTs) offers high
intrinsic carrier mobility and current-carrying capacity, and have already been used to
demonstrate ballistic and high mobility transistors [9-11], and integrated logic circuits
such as inverters and ring-oscillators [12-16].
Thin-films of SWNTs which possess
extraordinary conductivity, transparency and flexibility have been achieved using either
solution based filtration or chemical vapour deposition (CVD) growth, and TFTs based
on SWNTs have also been demonstrated and offers outstanding electrical properties as
expected [17-23]. However, all of the work mentioned above shares the same drawback
which is the co-existence of both metallic and semiconducting nanotubes with
approximate 33% nanotubes being metallic. Recently, significant advance has been made
on CVD grown nanotube networks for flexible devices and circuits by using
stripe-patterning to remove heterogeneous percolative transport through metallic
nanotube networks and increase the average device on/off ratio to 10
4
. This technique
93
nevertheless requires additional fabrication steps of stripe patterning and large device
dimensions [24].
Alternatively, the problem of the co-existence of metallic and semiconducting
nanotubes can be solved by using pre-separated semiconducting enriched nanotubes
produced by density gradient ultracentrifugation [25,26]. Based on the separated
nanotubes, TFTs have been demonstrated by the IBM research group. 99%
semiconducting nanotubes were deposited using a sophisticated evaporation
self-assembly method and the devices exhibited on/off ratios of more than 10
3
with
channel length L = 4 μm, sheet resistance of ~ 200 k Ω/sq, and mobility of ~ 10 cm
2
V
-1
s
-1
[27]. In spite of the significant progress, many interesting issues remain to be studied.
For example, can one use a simple and reliable method to assemble nanotubes besides the
evaporation self-assembly method? What are the key factors affecting the TFT
performance? Can one achieve even better TFT performance with separated nanotubes
of less demanding purities (<99%)?
To answer the above mentioned questions, we report our recent advance on
wafer-scale processing of SN-TFTs and their potential application in display electronics.
Surprisingly, we have produced TFTs using only 95% enriched semiconducting
nanotubes with overall better performance than previous work [27] using 99% enriched
nanotubes. Our work includes the following essential components. (1) Uniform and high
density separated nanotube thin-films were deposited onto 3 inch Si/SiO
2
wafers using a
facile solution based assembly method. (2) Wafer-scale device fabrication was performed
on 3 inch Si/SiO
2
wafers to yield SN-TFTs with high yield (> 98%), small sheet
94
resistance (~ 25 k Ω/sq), high current density (~ 10 μA/μm), high mobility (~ 52
cm
2
V
-1
s
-1
) and good on/off ratio (> 10
4
). (3) OLED control circuit has been demonstrated
using the SN-TFT with output light intensity modulation over 10
4
. Our wafer-scale
processing of SN-TFTs shows significant advantage over conventional platforms with
respect to scalability, reproducibility and device performance, and suggests a practical
and realistic approach for nanotube based integrated circuit applications.
5.2 Separated carbon nanotube thin-film deposition technique
Figure 5.1 illustrates our wafer-scale processing of SN-TFTs including
aminosilane assisted nanotube deposition and device fabrication. In order to improve the
density and uniformity of the solution based nanotube assembly, aminosilane is
introduced due to its well-known affinity to the carbon nanotubes [28,29]. In this work,
aminopropyltriethoxy silane (APTES) is used to functionalize the Si/SiO
2
surface to form
amine-terminated monolayer and the schematic of the APTES-assisted deposition is
shown in Figure 5.1a. The detailed procedure of wafer-scale separated nanotube
assembly begins with using corona discharge generator to generate UV ozone to clean the
surface of the Si/SiO
2
wafer making it hydrophilic. Next, the cleaned wafer is immersed
into diluted APTES solution (3 drops of APTES in 20 mL of isopropanol alcohol (IPA))
for 10 minutes, then rinsed with IPA and blew dry thoroughly. After APTES
functionalization, the wafer is immersed into the commercially available (NanoIntegris,
Inc.) 0.01 mg/mL separated nanotube solution with 95% semiconducting nanotubes for
95
Figure 5.1 Wafer-scale deposition of separated carbon nanotubes and fabrication of SN-TFTs. (a) Schematic diagram
of APTES assisted nanotube deposition on Si/SiO
2
substrate. (b) Length distribution of the separated nanotubes used in
this study (95% semiconducting nanotubes purchased from NanoIntegris, Inc.), the average nanotube length is 1.716
μm. (c, d) FE-SEM images of separated nanotubes deposited on Si/SiO
2
substrates with (c) and without (d) APTES
functionalization, respectively. (e) Photograph of 3 in. Si/SiO
2
wafer after APTES assisted nanotubes deposition. Inset:
FE-SEM images showing nanotubes deposited at different locations on the wafer, the locations of the SEM images on
the wafer correspond to the approximate locations on the wafer where the images were taken. All the scale bars are 5
μm. (f) Photograph of the same wafer after electrode patterning. The wafer consists of SN-TFTs used in this study and
other types of electronic devices. Such SN-TFTs are made with channel width (W) of 10, 20, 50, 100, and 200 μm, and
channel length (L) of 4, 10, 20, 50, and 100 μm.
c d
b
a
e f
0.5 1.0 1.5 2.0 2.5 3.0 3.5
0
1
2
3
4
5
6
7
8
Number of Tubes
Nanotube Length (μm)
Average CNT length = 1.716 μm
96
20 minutes. These separated nanotubes were obtained using density gradient
ultracentrifugation [25,26], where the chemical discrimination of surfactant molecules to
adsorb on metallic or semiconducting nanotubes results in a density difference between
metallic and semiconducting nanotubes. The percentage of semiconducting nanotubes in
the enriched sample is around 95%. Figure 5.2 shows the UV-Vis-NIR absorption spectra
of as prepared mixed arc-discharge nanotubes (blue trace) and separated semiconducting
nanotubes (red trace). Comparing those two traces, one can clearly see the enrichment of
semiconducting nanotubes in the separated nanotube sample.
500 600 700 800 900 1000 1100
0.6
0.8
1.0
1.2
1.4
S
22
S
33
Mixed Nanotubes
Separated Nanotubes
Absorbance (norm.)
Wavelength (nm)
M
11
Figure 5.2 UV-Vis-NIR absorption spectra of mixed (blue) and 95% semiconducting (red) nanotube solutions.
The length distribution of the semiconducting nanotubes is measured by
field-emission scanning electron microscope (FE-SEM) and the results are shown in
Figure 5.1b. The average length is measured to be 1.7 μm, which is longer than 1 μm for
99% semiconducting nanotubes as reported in the literature [27]. As a final step, IPA and
97
deionized water rinsing are used to remove the sodium dodecyl sulfate (SDS) residuals
on the nanotubes, and the wafer is blew dry with N
2
.
FE-SEM was used to inspect the surface after nanotube assembly. Figure 5.1c and
d are the SEM images of the separated nanotubes deposited on Si/SiO
2
substrates with
and without APTES functionalization, respectively. From the image, one can find that the
sample with APTES functionalization gives much higher nanotube density (24 ~ 32
tubes/ μm
2
) than the sample without APTES (< 0.5 tubes/ μm
2
). Besides high density,
APTES functionalization also helps to give uniform deposition throughout the wafer.
Figure 5.1e shows the photograph of a 3 inch Si/SiO
2
wafer after APTES assisted
nanotube deposition. There is no abnormal color or junk left on the wafer after the
deposition and cleaning process. In order to determine the deposition uniformity, SEM
images were taken at nine different locations on the wafer. In Figure 5.1e, the locations of
the SEM images on the wafer correspond to the approximate locations on the wafer
where the images were taken and all the scale bars correspond to 5 μm. The SEM images
indicate that high density, uniform deposition is achieved throughout the 3 inch wafer.
Following the nanotube deposition is the device fabrication process. 50 nm SiO
2
is used to act as the back-gate dielectric. The source and drain electrodes are patterned by
photo-lithography, and 5 Å Ti and 70 nm Pd are deposited followed by the lift-off
process to form the source and drain metal contacts. Finally, since the separated nanotube
thin film cover the entire wafer, in order to achieve accurate channel length and width,
and to remove the possible leakage in the devices, one more step of photo-lithography
plus O
2
plasma is used to remove the unwanted nanotubes outside the device channel
98
region. Figure 5.1f is a photograph of the wafer after electrode patterning. The wafer
consists of SN-TFTs used in this study and other types of electronic devices. Such
SN-TFTs are made with channel width (W) of 10, 20, 50, 100, and 200 μm, and channel
length (L) of 4, 10, 20, 50, and 100 μm.
5.3 Separated carbon nanotube thin-film transistors
We carried out systematic study of the electrical performance of the SN-TFTs as
basic components for macroelectronic integrated circuits and display electronics. Figure
5.3a shows the schematic diagram of a back-gated SN-TFT built on separated nanotube
thin-film with Ti/Pd (5 Å /70 nm) contacts and SiO
2
(50nm) gate dielectric. The SEM
image of the channel of a typical SN-TFT with 4 μm channel length is shown in Figure
5.3b. Figure 5.3c and d are the output (I
D
–V
D
) characteristics of a typical SN-TFT (L = 20
μm, and W = 100 μm) measured in triode region and saturation region, respectively. The
I
D
–V
D
curves appear to be very linear for V
D
between -1V and 1V, indicating that ohmic
contacts are formed between the electrodes and the nanotubes. Under more negative V
D
,
these devices typically exhibit saturation behavior, as shown in Figure 5.3d. Figure 5.3e
shows the transfer (I
D
–V
G
) characteristics (red: linear scale, green: log scale) and g
m
–V
G
characteristics (blue) of the same representative device with V
D
= 1V. The on-current at
V
D
= 1V is measured to be 18.5 μA, corresponding to a current density of 0.185 μA/ μm.
The on/off ratio exceeds 10
4
and the transconductance is 3.3 μS. Furthermore, due to the
high density and uniform nature of the separated nanotube thin-film deposited on Si/SiO
2
substrates with APTES functionalization, the SN-TFTs are also expected to behave
99
Figure 5.3 Electronic properties of back-gated SN-TFTs (a) Schematic diagram of a back-gated transistor built on
separated nanotube thin-film with Ti/Pd (5 Å /70 nm) contacts and SiO
2
(50nm) gate dielectric. (b) FE-SEM image of a
typical SN-TFT with 4 μm channel length. (c, d) Output (I
D
–V
D
) characteristics of a typical SN-TFT (L = 20 μm, and W
= 100 μm) in triode region (c) and saturation region (d), respectively. (e) Transfer (I
D
–V
G
) characteristics (red: linear
scale, green: log scale) and g
m
–V
G
characteristics (blue) of the same device with V
D
= 1V. (f) Current density (I
on
/W)
measured at V
D
= 1V and threshold voltage (V
th
) of 10 representative SN-TFTs showing the uniformity of devices. The
red line represents the average value.
b
a
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
-10 -5 0 5 10
0
5
10
15
20
Gate Voltage (V)
Drain Current (μA)
0
1
2
3
4
Transconductance (μS)
Drain Current (A)
-10 -8 -6 -4 -2 0
-70
-60
-50
-40
-30
-20
-10
0
Drain Current (μA)
Drain Voltage (V)
VG is from -10V to
0V in 1V steps
-1.0 -0.5 0.0 0.5 1.0
-20
-15
-10
-5
0
5
10
15
20
Drain Current (μA)
Drain Voltage (V)
VG is from -10V to
10V in 2V steps
d
e
c
1 234 5 6 789 10
0
3
6
9
12
123 45 678 9 10
-6
-5
-4
-3
-2
I
on
/W (μA/μm)
Device number
V
th
(V)
f
100
uniformly. The uniformity of the devices is illustrated in Figure 5.3f which shows the
current density (I
on
/W) measured at V
D
= 1V and threshold voltage (V
th
) of 10
representative SN-TFTs with L = 4μm. The red lines represent the average values and one
can find that those device parameters have much smaller distribution compared with
single nanotube devices.
5.4 Comparing TFTs using separated and CVD-grown nanotubes
CVD grown nanotube thin-films with mixed nanotubes have also been used to
demonstrate TFTs and significant advance has been made toward flexible devices and
integrated circuits [19,22,24]. However, the major problem of using CVD grown
nanotube networks is the co-existence of metallic and semiconducting nanotubes, with
approximate 33% nanotubes being metallic. Stripe-patterning of CVD nanotube network
has been proposed to remove heterogeneous percolative transport through metallic
nanotube networks and increase the average device on/off ratio to 10
4
. Nevertheless, this
technique requires additional fabrication steps and large device dimensions.
To get a more comprehensive understanding, we compare the performance of
SN-TFTs based on separated nanotubes (5% metallic) with TFTs based on CVD grown
mixed nanotubes (33% metallic). The mixed nanotube thin-film is grown by chemical
vapour deposition (CVD), and the CVD recipe was fine tuned to produce TFTs with a
current drive (I
on
/W) similar to SN-TFTs. The device fabrication process is briefly
described as follows. First, FeCl
3
is used as the catalyst and is deposited onto the Si/SiO
2
substrate by dip coating. The samples are then annealed in air at 900 °C for 1 hour. Then
101
the nanotubes are grown by CVD at 900 °C with CH
4
(2500 sccm) and H
2
(600 sccm) as
feeding gases. The rest of the fabrication processes including electrode patterning and
un-wanted CNT etching are exactly the same as the fabrication of SN-TFTs in terms of
dielectric thickness, metal contact material, and metal contact thickness.
Figure 5.4 summarizes the results from a typical TFT device based on CVD
grown mixed nanotubes. Figure 5.4a is the SEM image of a device with 10 μm channel
length. Figure 5.4b shows the transfer (I
D
–V
G
) characteristics (red: linear scale, green: log
scale) and g
m
–V
G
characteristics (blue) of a representative device (L = 20 μm, W = 100
μm) measured at V
D
= 1V, and Figure 5.4c shows the transfer (I
D
–V
G
) characteristics of
the same device measured at different V
D
. The dimension of this device is the same as the
SN-TFT device shown in Figure 5.3 so that it is straightforward to compare the
performance of TFTs based on mixed nanotubes and separated nanotubes. The on-current
at V
D
= 1V is measured to be 39.8 μA, corresponding to a current density of 0.398 μA/ μm.
The on/off ratio is 5.71 and the transconductance is 3.55 μS. Comparing the output
characteristics (I
D
–V
D
) of the mixed nanotubes TFT shown in Figure 5.4d and the output
characteristics (I
D
–V
D
) of the SN-TFT shown in Figure 5.3c, one can easily observe the
difference in the on/off ratio resulted from the difference in the percentage of metallic
nanotubes.
102
Figure 5.4 (a) FE-SEM image of a typical TFT based on CVD grown mixed nanotubes with 10 μm channel length. (b)
Transfer (I
D
–V
G
) characteristics (red: linear scale, green: log scale) and g
m
–V
G
characteristics (blue) of a typical device
(L = 20 μm, and W = 100 μm) measured at V
D
= 1V. (c) Transfer (I
D
–V
G
) characteristics of the device measured at
different V
D
. (d) Output (I
D
–V
D
) characteristics of the devices measured at different V
G
.
Figure 5.5 summarizes the results after the measurement of 200 nanotube TFTs
with various channel lengths and channel widths. Half of these devices are based on
separated nanotubes and the other half based on mixed nanotubes. The device yield is
more than 98%, and the few un-conductive devices are due to the peel-off of metal
contact during fabrication process.
b
d c
-1.0 -0.5 0.0 0.5 1.0
-40
-30
-20
-10
0
10
20
30
40
VG is from -10V to
10V in 2V steps
Drain Current (μA)
Drain Voltage (V)
-10 -5 0 5 10
0
5
10
15
20
25
30
35
40
45
VD = 1.0V
VD = 0.8V
VD = 0.6V
VD = 0.4V
VD = 0.2V
Drain Current (μA)
Gate Voltage (V)
10
-6
10
-5
10
-4
-10 -5 0 5 10
0
10
20
30
40
Gate Voltage (V)
Drain Current (μA)
0
1
2
3
4
Transconductance (μS)
Drain Current (A)
a
5 μm
103
Figure 5.5 Statistical study of 200 nanotube TFTs based on separated nanotubes and mixed nanotubes. (a) Plot of
current density (I
on
/W) versus channel length for TFTs fabricated on separated nanotubes and mixed nanotubes. (b) Plot
of average on current (I
on
) versus channel width for TFTs fabricated on separated nanotubes and mixed nanotubes, with
various channel lengths (4, 10, 20, 50, 100 μm). (c) Plot of average on/off ratio (I
on
/I
off
) versus channel length for TFTs
fabricated on separated nanotubes and mixed nanotubes. (d) Plot of average transconductance per unit width (g
m
/W)
and average device mobility ( μ
device
) versus channel length for TFTs fabricated on separated nanotubes and mixed
nanotubes.
Figure 5.5a exhibits the average normalized on-current densities (I
on
/W) of the
transistors with various channel lengths measured at V
D
= 1 V and V
G
= -10 V, showing
that the on-current density is approximately reversely proportional to the channel length.
The highest on-current density is measured to be 10 μA/ μm and is achieved in devices
with L = 4 μm. This value is comparable to the devices based on parallel aligned
nanotubes with a typical nanotube density of 5 tubes/ μm [31,32]. Figure 5.5b shows
0 20 40 60 80 100
0.01
0.1
1
10
Separated nanotubes
Mixed Nanotubes
I
on
/W (μA/μm)
Channel Length(μm)
0 20406080 100
10
0
10
1
10
2
10
3
10
4
Separated Nanotubes
Mixed Nanotubes
On/Off Ratio
Chanel Length(μm)
20
30
40
50
60
70
80
90
0 20406080100
10
-3
10
-2
10
-1
10
0
Solid Line: Separated Nanotubes
Dash Line: Mixed Nanotubes
Mobility (cm
2
V
-1
s
-1
)
Channel Length (μm)
g
m
/W (μS/μm)
0 50 100 150 200
10
-6
10
-5
10
-4
10
-3
10
-2
L = 4 μm
L = 10 μm
L = 20 μm
L = 50 μm
L = 100 μm
On Current (A)
Channel Width(μm)
Solid Line: Separated Nanotubes
Dash Line: Mixed Nanotubes
b a
c d
104
that the average on-current of the TFTs with various channel lengths is approximately
proportional to the channel width. The highest average on-current 1.59 mA is achieved in
devices with L = 4 μm and W = 200 μm. Based on the information in Figure 5.5b, we can
further extract the best sheet resistance of the separated nanotube thin-film to be ~ 25
k Ω/sq, which is 8 times better than 200 k Ω/sq reported in the previous publication [27].
For TFTs fabricated with separated nanotubes and mixed nanotubes, the major
difference is expected to be the on/off ratio, and the difference is explained in Figure 5.5c.
First of all, as the channel length increases, the average on/off ratio of both SN-TFTs and
Mixed nanotube TFTs increases. This can be explained by the decrease in the probability
of percolative transport through metallic nanotube networks as the device channel length
increases. On the other hand, SN-TFTs have much higher on/off ratio compared with
mixed nanotube TFTs due to the small percentage of metallic nanotubes. For the mixed
nanotube TFT, with 33% metallic nanotubes, the on/off ratio stays in the range of 2 to 10
as the channel length increases from 4 μm to 100 μm. In contrast, for SN-TFT, with only
5% metallic nanotubes, the on/off ratio improves significantly from 10 to above 10
4
as
the channel length increases from 4 μm to 100 μm. The turning point happens between 10
μm and 20 μm. When L > 20 μm, more than 90% of the devices exhibit on/off ratio
higher than 10
3
. This amount of on/off ratio is large enough for most kinds of integrated
circuit applications. Similar results have also been reported in previous work done by the
IBM research group [27]. For their work, the turning point happens between 2 μm and 4
μm. The reason that their turning point happens at smaller channel length is that they
used 99% semiconducting nanotubes. By using higher purity semiconducting enriched
105
nanotubes, on the one hand, it can help to achieve sufficient on/off ratio with smaller
channel length, thus smaller device area; on the other hand, since higher purity requires
more ultracentrifugation which will give rise to shorter nanotube length, it can cause
more nanotube percolation and hurt the mobility of the devices as discussed below.
Besides the on current density and on/off ratio, there are two more important
figures of merit for SN-TFTs, which are device transconductance (g
m
) and mobility
( μ
device
). The normalized device transconductance (g
m
/W) and mobility of devices with
various channel lengths are characterized and are plotted in Figure 5.5d. g
m
is extracted
from the maximum slope of the transfer characteristics measured at V
D
= 1 V, and is
normalized to device channel width. From the figure, one can find that as channel length
increases, g
m
/W decreases, this is because g
m
/W is also inversely proportional to channel
length.
Based on the normalized transconductance, we can further extract the mobility of
the nanotube thin-film. We note that the SN-TFTs exhibit hysteresis, so for consistency,
we used g
m
derived from the forward sweep for all the mobility calculations. Under V
D
=
1 V, devices operate in triode region, so the device mobility can be calculated from the
following equation,
dm
device
Dox g Dox
dI g LL
VC W dV V C W
μ=⋅ = ⋅ (1)
where L and W are the device channel length and width, V
D
= 1 V, g
m
is the maximum
transconductance which is extracted by taking the derivative of the transfer
characteristics, and C
ox
is the gate capacitance per unit area. The capacitance is calculated
106
by considering the electrostatic coupling between nanotubes [33] using the following
equation,
1
11 00
0
0
sinh(2 / ) 1
ln
2
ox
ox Q
ox
t
CC
R
π
πε ε π
−
−−
⎧⎫ ΛΛ ⎡⎤
=+ Λ
⎨⎬
⎢⎥
⎣⎦
⎩⎭
(2)
where 1/ Λ
0
stands for the density of nanotubes and is measured to be around 10 tubes/ μm,
C
Q
= 4.0×10
-10
F/m is the quantum capacitance of nanotubes, t
ox
= 50 nm is the thickness
of the dielectric layer, R = 1.2 nm is the radius of nanotubes, and ε
0
ε
ox
= 3.9×8.85×10
-14
F/cm is the dielectric constant at the interface where the nanotubes are placed. Based on
the equation, one can find that C
ox
= 3.46×10
-8
F/cm
2
.
For the device mobility, one interesting finding is that for the SN-TFTs, the
device mobility decreases as channel length increases, while for the mixed nanotube
TFTs, the device mobility increases as channel length increases. The highest mobility of
SN-TFTs is 52 cm
2
V
-1
s
-1
and is achieved in devices with L = 4 μm, while the highest
mobility of mixed nanotube TFTs is 86 cm
2
V
-1
s
-1
and is achieved in devices with L = 100
μm. The reason for the difference is believed to be related to nanotube length. For the
separated nanotubes, the average length is small and is measured to be 1.7 μm, so the
device mobility is limited by the percolative transport through nanotube network. As the
device channel length increases from a value comparable to the nanotube length to a
much larger value, there are significantly more tube-to-tube junctions introduced into the
conduction path, causing the device mobility to decrease. In contrast, for the mixed
nanotubes, the average length is much larger (>20 μm), so the device mobility is likely to
be limited by the metal/nanotube contacts, similar to the case for aligned nanotube
107
transistors [30-32]. As the channel length increases, the effect of metal/nanotube contacts
become less significant and the mobility increases. Our SN-TFTs exhibit mobility up to
52 cm
2
V
-1
s
-1
which is more than five times higher than the previously reported work (10
cm
2
V
-1
s
-1
) [27]. Our improvement in the device performance can be attributed to longer
nanotube length as described before. For instance, the average nanotube length in our
SN-TFTs is approximately 1.7 μm, while the nanotube length is about 1 μm for previous
work. For transistors of similar channel length, using longer nanotubes would lead to less
nanotube-nanotube junctions, and consequently higher mobility.
5.5 Numerical simulation of nanotube percolation network
In order to further assess the effect of the carbon nanotube percolation network on
the performance of nanotube TFTs [34-36], a numerical simulation of nanotube TFTs
with various channel lengths was performed to extract their on/off ratios. The simulation
consists of the following steps. First, we generate random nanotube networks that are
defined by the following parameters: density of nanotubes, nanotube length, percentage
of metallic nanotubes, channel length and width. The representative networks for
separated nanotubes and mixed nanotubes are shown in Figure 5.6a. Then we calculate
the resistance of a nanotube network in the on- and off-states, where we assume that the
resistance per unit length of a semiconducting nanotube in the on-state to be equal to the
resistance per unit length of a metallic nanotube, and 10
4
times larger in the off-state. We
also assume fixed contact resistances between metallic/metallic, metallic/semiconducting,
semiconducting/semiconducting nanotubes, and nanotubes/metal contacts. Based on the
108
resistance in the on- and off-states calculated from the randomly generated carbon
nanotube network, one can derive the on/off ratios of the devices. The simulation results
are compared with the measurement results and are plotted in Figure 5.6b. Based on the
figure, the simulation results fit the measurement results well, which indicate that the
nanotube percolation indeed plays a critical role in determining the on/off ratios of
nanotube TFTs.
Figure 5.6 Simulation of nanotube thin-film percolation network. (a) Randomly generated nanotube percolation
networks of separated nanotubes (top) and mixed nanotubes (bottom) for devices with L = 10 μm and W = 20μm. The
red and blue lines represent metallic and semiconducting nanotubes, respectively (b) comparison between the
simulation data derived from the percolation network and measurement data.
0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
0 20406080 100
10
0
10
1
10
2
10
3
10
4
10
5
Simulation
Simulation
Separated Nanotubes
CVD Mixed Nanotubes
Simulation Results
Measurement
On/Off Ratio
Chanel Length(μm)
Measurement
0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
b a
109
5.6 Display electronics using separated nanotube thin-film transistors
Our ability to fabricate high performance, uniform, high on/off ratio SN-TFTs
enable us to further explore their applications in display electronics. For the proof of
concept purpose, an OLED was connected to and controlled by a typical SN-TFT device
whose transfer characteristics are shown in Figure 5.7a. The OLED employed in this
study is a standard NPD/Alq3 OLED with multilayered configuration given as: ITO /
4-4'-bis[N-(1-naphthyl)-N-phenyl-amino]biphenyl (NPD) [40 nm] /
Tris(8-hydroxyquinoline) aluminum (Alq3) [40nm] / LiF [1nm] / Aluminum (Al)
[100nm]. The channel length of the SN-TFT is selected to be 20 μm so that the on/off
ratio reaches 10
4
and can meet the requirement for controlling the OLED to switch on
and off. The schematic of the OLED control circuit is shown in the inset of Figure 5.7b,
where one SN-TFT is connected to an external OLED, and V
DD
(< 0 V) is applied to the
cathode of the OLED. The OLED control circuit is characterized by sweeping the V
DD
and Input voltage V
G
and measure the current flow through the OLED (I
OLED
). It shows
field effect transistor like behavior, with various curves correspond to various values of
input voltage. The figure illustrates that by controlling V
DD
and V
G
that worked as the
input for the circuit, we can control the current flow through the OLED. To fully
understand the behavior of the OLED, it is further characterized and the current and
output light intensity versus applied voltage behaviors are plotted in Figure 5.7c. From
the figure, we can see that the OLED gives nice diode I-V characteristic and in terms of
the light intensity, the turn on voltage is about 3 V.
110
Figure 5.7 OLED control circuit by SN-TFT. (a) Transfer (I
D
–V
G
) characteristics under different drain voltages for the
device used to control the OLED (L = 20 μm, and W = 100 μm), Inset: optical microscope image of the device. (b)
Characteristics of the OLED control circuit where the current flow through the OLED (I
OLED
) is measured by sweeping
the V
DD
and Input voltage V
G
. Various curves correspond to various values of V
G
from -10 V to 10 V in 2 V steps. (c)
Two terminal measurement of the OLED showing the current through the OLED (I
OLED
) (red line) and OLED light
intensity (green line) versus the voltage applied across the OLED (V
OLED
). (d) Plot of the current through the OLED
(I
OLED
) (red line) and OLED light intensity (green line) versus V
G
with V
DD
= 5 V. Inset: The circuit diagram of an
OLED driven by a SN-TFT.
Based on the data in Figure 5.7b and c, we demonstrate the switching of the
OLED by applying V
DD
= 5 V to the source of the transistor and sweeping the input
voltage V
G
from -10 V to 10 V. Figure 5.7d shows the current (red curve) flowing
through the OLED, which is successfully modulated by V
G
by a factor of 1140, and this
modulation leads to the control of the OLED light intensity as shown in the green curve.
V
G
V
DD
= 5V
10
-12
10
-10
10
-8
10
-6
-10 -5 0 5 10
0
1
2
3
4
5
6
7
V
G
(V)
I
DD
(I
OLED
) (μA)
Light intensity (W/cm
2
)
V
G
V
DD
-10 -5 0 5 10
0
5
10
15
20
VD=1.0V
VD=0.8V
VD=0.6V
VD=0.4V
VD=0.2V
Drain Current (μA)
Gate Voltage (V)
10
-13
10
-11
10
-9
10
-7
10
-5
10
-3
02 4 6 8 1012
0
2
4
6
8
10
12
V
OLED
(V)
I
OLED
(mA)
Light intensity (W/cm
2
)
a b
d c
-10 -8-6-4-2 0
-80
-70
-60
-50
-40
-30
-20
-10
0
VG is from -10 V to
10 V in 2 V steps
I
DD
(I
OLED
) (μA)
V
DD
(V)
111
When V
G
= -10V, the OLED is on, and based on the measured light intensity, the
brightness is calculated to be 16.5 Cd/m
2
. When V
G
= 10V, the OLED is off and the
brightness is calculated to be < 0.001 Cd/m
2
. The modulation in the OLED brightness is
greater than 10
4
and the significant change in the light intensity can be visually seen as
shown in Figure 5.8. The optical photographs represent the OLED under various input
voltages, with 1, 2, 3, 4, 5, and 6 correspond to the inputs of -10, -8, -6, -4, -2, and 0 V,
respectively.
Figure 5.8 Photographs of the OLED driven by SN-TFT under different inputs showing the turn-on and turn-off of the
OLED.
112
5.7 Summary
In summary, we have reported significant progress on wafer-scale processing of
SN-TFTs for display applications, including progress on wafer-scale assembly of high
density, uniform separated nanotube networks; high-yield fabrication of devices with
good performance, and proof of concept demonstration of OLED switching controlled by
a SN-TFT. The APTES assisted solution based assembly of separated nanotube thin-film
has been achieved on complete 3 inch Si/SiO
2
wafers, followed by the fabrication to yield
transistors with high yield (> 98%), small sheet resistance (~ 25 k Ω/sq), high current
density (~ 10 μA/μm), high mobility (~ 52 cm
2
V
-1
s
-1
) and good on/off ratio (> 10
4
). In
addition, OLED control circuit has been demonstrated with the SN-TFT, and the
modulation in the output light intensity exceeds 10
4
. This demonstration can provide
guide to future research on SN-TFT based display electronics such as active matrix
organic light-emitting diode (AMOLED). Our work represents significant advance
toward the challenging task of large scale separated nanotube thin-film assembly and
solves the problem of co-existence of both metallic and semiconducting nanotubes in the
state-of-the-art nanotube transistor fabrication techniques.
113
Chapter 5. References
1. Dimitrakopoulos, C. D.; Mascaro, D. J. Organic Thin-Film Transistors: A Review
of. Recent Advances. IBM J. Res. Dev. 2001, 45, 11–27.
2. Forrest, S. R. The Path to Ubiquitous and Low-Cost Organic Electronic Appliances
on Plastic. Nature 2004, 428, 911–918.
3. Ju, S. H.; Yu, S. H.; Kwon, J. H.; Kim, H. D.; Kim, B. H.; Kim, S. C.; Chung, H. K.;
Weaver, M. S.; Lu, M. H.; Kwong, R. C.; Hack, M.; Brown, J. J. High Performance
2.2” QCIF Full Color AMOLED Displays Based on Electrophosphorescence. SID
Digest 2002, 37.3, 1096–1099.
4. Ucjikoga, S. Low-Temperature Polycrystalline Silicon Thin-Film Transistor
Technologies for System-on-Glass Displays. MRS Bull. 2002, 27, 881–886.
5. Street, R. A. (Ed.) Technology and Applications of Amorphous Silicon; Springer:
Berlin, 2000.
6. Snell, A. J.; Mackenzie, K. D.; Spear, W. E.; LeComber, P. G.; Hughes, A. J.
Application of Amorphous Silicon Field Effect Transistors in Addressable Liquid
Crystal Display Panels. Appl. Phys. A 1981, 24, 357–362.
7. Gelinck, G. H.; Edzer, H.; Huitema, A.; Van Veenendaal, E.; Cantatore, E.;
Schrijnemakers, L.; Van Der Putten, J. B. P. H.; Geuns, T. C. T.; Beenhakkers, M.;
Giesbers, J. B.; Hiusman, B.-H.; Meijer, E. J.; Benito, E. M.; Touwslager, F. J.;
Marsman, A. W.; Van Rens, B. J. E.; De Leeuw, D. M. Flexible Active-Matrix
Displays and Shift Registers Based on Solution-Processed Organic Transistors. Nat.
Mater. 2004, 3, 106–110.
8. Klauk, H.; Halik, M.; Zschieschang, U.; Eder, F.; Rohde, D.; Schmid, G.; Dehm, C.
Flexible Organic Complementary Circuits. IEEE Trans. Electron Devices 2005, 52,
618–622.
9. Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654–657.
10. Durkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39.
11. Zhou, X.; Park, J. Y.; Huang, S.; Liu, J.; McEuen, P. L. Band Structure, Phonon
Scattering, and the Performance Limit of Single-Walled Carbon Nanotube
Transistors. Phys. Rev. Lett. 2005, 95, 146805
114
12. Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon
Nanotube Transistors. Science 2001, 294, 1317–1320.
13. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, Ph. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
14. Liu, X.; Lee, C.; Han, J.; Zhou, C. Carbon Nanotube Field-Effect Inverters. Appl.
Phys. Lett. 2001, 79, 3329–3331.
15. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays
for Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2,
929–932.
16. Chen, Z.; Appenzeller, J.; Lin, Y.; Oakley, J. S.; Rinzler, A.G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, Ph. An Integrated Logic Circuit Assembled on a Single
Carbon Nanotube. Science 2006, 311, 1735.
17. Snow, E. S.; Novak, J. P.; Campbell, P. M.; Park, D. Random Networks of Carbon
Nanotubes as An Electronic Material. Appl. Phys. Lett. 2003, 82, 2145–2147.
18. Snow, E. S.; Campbell, P. M.; Ancona, M. G.; Novak, J. P. High-Mobility
Carbon-Nanotube Thin-Film Transistors on a Polymeric Substrate. Appl. Phys. Lett.
2005, 86, 033105-1–033105-3.
19. Artukovic, E.; Kaempgen, M.; Hecht, D. S.; Roth, S.; Gruner, G. Transparent and
Flexible Carbon Nanotube Transistors. Nano Lett. 2005, 5, 757–760.
20. Hu, L.; Hecht, D. S.; Gruner, G. Percolation in Transparent and Conducting Carbon
Nanotube Networks. Nano Lett. 2004, 4, 2513–2517.
21. Zhang, D.; Ryu, K.; Liu, X.; Polikarpov, E.; Ly, J.; Tompson, M. E.; Zhou, C.
Transparent, Conductive, and Flexible Carbon Nanotube Films and Their
Application in Organic Light-Emitting Diodes. Nano Lett. 2006, 6, 1880–1886.
22. Ishikawa, F.; Chang, H.; Ryu, K.; Chen, P.; Badmaev, A.; De Arco Gomez, L.; Shen,
G.; Zhou, C. Transparent Electronics Based on Transfer Printed Aligned Carbon
Nanotubes on Rigid and Flexible Substrates. ACS Nano 2009, 3, 73–79.
23. Cao, Q.; Rogers, J. A. Ultrathin Films of Single-Walled Carbon Nanotubes for
Electronics and Sensors: A Review of Fundamental and Applied Aspects. Adv.
Mater. 2008, 21, 29–53.
115
24. Cao, Q.; Kim, H. S.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.;
Alam, M. A.; Rogers, J. A. Medium-Scale Carbon Nanotube Thin-Film Integrated
Circuits on Flexible Plastic Substrates. Nature 2008, 454, 495–500.
25. Arnold, M. S.; Green, A. A.; Hulvat, J. F.; Stupp, S. I.; Hersam, M. C. Sorting
Carbon Nanotubes by Electronic Structure Using Density Differentiation. Nat.
Nanotechnol. 2006, 1, 60–65.
26. Arnold, M. S.; Stupp, S. I.; Hersam, M. C. Enrichment of Single-Walled Carbon
Nanotubes by Diameter in Density Gradients. Nano Lett. 2005, 5, 713–718.
27. Engel, M.; Small, J. P.; Steiner, M.; Freitag, M.; Green, A. A.; Hersam, M. C.;
Avouris, Ph. Thin Film Nanotube Transistors Based on Self-Assembled, Aligned,
Semiconducting Carbon Nanotube Arrays. ACS Nano 2008, 2, 2445–2452.
28. Chattopadhyay, D.; Galeska, I.; Papadimitrakopoulos, F. A Route for Bulk
Separation of Semiconducting from Metallic Single-Wall Carbon Nanotubes. J. Am.
Chem. Soc. 2003, 125, 3370–3375.
29. LeMieux, M. C.; Roberts, M.; Barman, S.; Jin, Y. W.; Kim, J. M.; Bao, Z.
Self-Sorted, Aligned Nanotube Networks for Thin-Film Transistors. Science 2008,
321, 101–104.
30. Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S.
V.; Rogers, J. A. High-Performance Electronics Using Dense, Perfectly Aligned
Arrays of Single-Walled Carbon Nanotubes. Nat. Nanotechnol. 2007, 2, 230–236.
31. Wang, C.; Ryu, K.; Badmaev, A.; Patil, N.; Lin, A.; Mitra, S.; Wong, H.-S. P.; Zhou,
C. Device Study, Chemical Doping, and Logic Circuits Based on Transferred
Aligned Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2008, 93,
033101-1–033101-3.
32. Ryu, K.; Badmaev, A.; Wang, C.; Lin, A.; Patil, N.; Gomez, L.; Kumar, A.; Mitra,
S.; Wong, H.-S. P.; Zhou, C. CMOS-Analogous Wafer-Scale Nanotube-on-Insulator
Approach for Submicrometer Devices and Integrated Circuits Using Aligned
Nanotubes. Nano Lett. 2009, 9, 189–197.
33. Cao, Q.; Xia, M.; Kocabas, C.; Shim, M.; Rogers, J. A.; Rotkin, S. V. Gate
Capacitance Coupling of Singled-Walled Carbon Nanotube Thin-Film Transistors.
Appl. Phys. Lett. 2007, 90, 023516-1–023516-3.
116
34. Pimparkar, N.; Kocabas, C.; Kang, S. J.; Rogers, J. A.; Alam, M. A. Limits of
Performance Gain of Aligned CNT Over Randomized Network: Theoretical
Predictions and Experimental Validation. IEEE Electron Device Lett. 2007, 28,
593–595.
35. Kocabas, C.; Pimparkar, N.; Yesilyurt, O.; Alam, M. A.; Rogers, J. A. Experimental
and Theoretical Studies of Transport through Large Scale, Partially Aligned Arrays
of Single-Walled Carbon Nanotubes in Thin Film Type Transistors. Nano Lett. 2007,
7, 1195–1202.
36. Pimparkar, N.; Cao, Q.; Kumar, S.; Murthy, J. Y.; Rogers, J. A.; Alam, M. A.
Current–Voltage Characteristics of Long-Channel Nanobundle Thin-Film
Transistors: A “Bottom-Up” Perspective. IEEE Electron Device Lett. 2007, 28,
157–160.
117
Chapter 6. Macroelectronic Integrated Circuits Using
High-Performance Separated Carbon Nanotube Thin-Film
Transistors
6.1 Introduction
Single-walled carbon nanotubes offer extraordinary electrical properties [1-5]
such as high intrinsic carrier mobility and current-carrying capacity and have already
been used extensively to demonstrate ballistic and high mobility transistors [6-8] and
integrated logic circuits such as inverters and ring-oscillators [9-13].
Thin-films of
single-walled carbon nanotubes which possess extraordinary conductivity, transparency,
and flexibility have been achieved using either solution-based filtration or chemical vapor
deposition (CVD) methods [14-21]. Compared with other popular channel material for
thin-film transistors (TFTs), such as amorphous silicon [22-24] or organic materials
[25-28], nanotube thin-films have the advantages of room-temperature processing
compatibility, transparency, and flexibility, as well as high device performance. Recently,
CVD-grown nanotube thin-films have been used to demonstrate TFTs with outstanding
electrical properties, and significant advance has been made toward flexible devices and
integrated circuits [16,19,21].
Nevertheless, the mainstream nanotube TFT approach
mentioned above shares one drawback which is the coexistence of both metallic and
semiconducting nanotubes with approximate 33% nanotubes being metallic. For
electronic applications, the problem of the coexistence of metallic and semiconducting
nanotubes can be solved by using preseparated nanotubes with high purity
118
semiconducting nanotubes [29,30]. Based on the separated nanotubes, TFTs have been
demonstrated by the IBM research group using an evaporation self-assembly method [31]
and our group using the solution-based aminosilane-assisted wafer-scale separated
nanotube deposition technique [32]. In those previous reports, high performance
separated nanotube thin-film transistors (SN-TFTs) have been demonstrated, which
exhibit on/off ratio of more than 10
4
, on-current density up to 10 μA/μm, and mobility up
to 50 cm
2
V
-1
s
-1
. In spite of the significant progress, many interesting issues remain to be
studied. For example, what are the key factors affecting the SN-TFT performance? Is
there any trade-off in terms of device performance when using separated semiconducting
nanotubes of different purities? Can we assemble the SN-TFTs for integrated circuit
applications?
To answer the above-mentioned questions, we report our recent advance on the
application of high-performance SN-TFTs for macroelectronic integrated circuits. Our
work includes the following essential components. (1) We have measured SN-TFTs with
various channel lengths and widths, systematically compared the key performance
metrics such as on-current density, on/off ratio, transconductance, and mobility of
devices using separated nanotubes with 95% and 98% semiconducting nanotubes. From
the comparison, we have observed that while 95% semiconducting nanotubes are ideal
for applications requiring high mobility (up to 67 cm
2
V
-1
s
-1
) such as analog and radio
frequency applications, 98% semiconducting nanotubes are ideal for applications
requiring high on/off ratio (>10
4
with channel length down to 4 μm). This trade-off
between the mobility and on/off ratio can serve as the guidance for SN-TFT device
119
optimization for integrated circuit applications. (2) Integrated inverter design using
SN-TFTs has been systematically investigated. Studies find that due to the highly
uniform nature of our SN-TFTs, the integrated inverters can be readily designed using the
conventional silicon field-effect transistor circuit design theory. By simply changing the
dimensions of the switching and load transistors in the layout design, inverters with
different voltage gains can be achieved and the measurement results are in consistence
with the theoretical calculations. Moreover, these inverters with SN-TFTs exhibit
symmetric input/output behavior, which allows the cascading of multiple stages of logic
blocks and large scale integration. (3) In addition to inverters, more sophisticated logic
circuits such as 2-input NAND and NOR have also been demonstrated. Our SN-TFT
platform shows significant advantages over conventional platforms with respect to
scalability, reproducibility, and device performance, and suggests a practical and realistic
approach for nanotube-based macroelectronic integrated circuit applications.
6.2 Effect of semiconducting nanotube purity on transistor performance
We have characterized the separated nanotubes with different purities of
semiconducting nanotubes and compared them with the unsorted nanotubes with
approximately 33% metallic nanotubes. Figure 6.1a is a photograph showing the unsorted
arc-discharge P3 (Carbon solutions, Inc.) as well as 95% and 98% semiconducting
single-walled carbon nanotube solution used in this study. The separated 95% and 98%
semiconducting nanotubes (IsoNanotubes-S ™) were obtained from NanoIntegris, Inc.
These samples were enriched by density gradient ultracentrifugation, where the chemical
120
discrimination of surfactant molecules to adsorb on metallic or semiconducting nanotubes
results in a density difference between metallic and semiconducting nanotubes. By
repeating the same separation process, the purity of semiconducting nanotubes can be
continuously improved. Figure 6.1b shows the UV–Vis–NIR absorption spectra of the
as-prepared P3 arc-discharge nanotubes (blue trace), 95% semiconducting separated
nanotubes (red trace), and 98% semiconducting separated nanotubes (green trace).
Comparing those three traces, one can clearly see the enrichment of semiconducting
nanotubes in the separated nanotube sample indicated by the decrease in M
11
peak and
increase in S
22
, S
33
peaks.
To deposit high density, uniform separated nanotube thin-film onto the Si/SiO
2
substrates for device fabrication, we use the solution-based aminosilane-assisted
separated nanotube deposition technique reported in the publication of Bao et al. [33] and
in our previous publication [32].
Using this method, uniform nanotube networks can be
assembled on top of the Si/SiO
2
substrates. This is done by immersing the Si/SiO
2
substrate into diluted aminopropyltriethoxy silane (APTES) solution (1% APTES in
isopropanol alcohol (IPA)) for 10 minutes in order to functionalize the surface with
amine-terminated monolayer. The sample is then rinsed with IPA, blown dry thoroughly
and then immersed into the commercially available 0.01 mg/mL separated nanotube
solution with 95% or 98% semiconducting nanotubes (NanoIntegris Inc.) for 20 minutes,
after which uniform nanotube networks are formed on top of the substrates.
121
Figure 6.1 Comparison of nanotubes separated by density gradient ultracentrifugation with different purities of
semiconducting nanotubes. (a) Photograph of P3 (unsorted), 95% semiconducting, and 98% semiconducting
single-walled carbon nanotube solution. (b) UV–Vis–NIR absorption spectra of the as-prepared P3 arc-discharge
nanotubes (blue trace), 95% semiconducting separated nanotubes (red trace), and 98% semiconducting separated
nanotubes (green trace). (c) FE-SEM images of 95% semiconducting separated nanotubes deposited on Si/SiO
2
substrates with APTES functionalization, the average density is 41 tubes/µm
2
. (d) Length distribution of the 95%
semiconducting separated nanotubes, the average nanotube length is 0.97 µm. (e) FE-SEM images of 98%
semiconducting separated nanotubes deposited on Si/SiO
2
substrates with APTES functionalization, the average density
is 46 tubes/µm
2
. (f) Length distribution of the 98% semiconducting separated nanotubes, the average nanotube length is
0.81 µm. (g) Schematic diagram of a back-gated SN-TFT. (h) Schematic diagram of an individual-gated SN-TFT.
a
0.00.5 1.01.5 2.02.5
0
1
2
3
4
5
6
7
Number of Tubes
Nanotube Length (μm)
0.0 0.5 1.0 1.5 2.0 2.5
0
1
2
3
4
5
6
7
8
9
Number of Tubes
Nanotube Length (μm)
b
c
f
e
g h
d
95% Semiconducting
98% Semiconducting
95% Semiconducting
98% Sesmiconducting
500 600 700 800 900 1000 1100
0.4
0.6
0.8
1.0
1.2
1.4
P3 (Unsorted) SWNTs
95% Semiconducting SWNTs
98% Semiconducting SWNTs
S
22
S
33
Absorbance (norm.)
Wavelength (nm)
M
11
122
Compared with the work we reported previously [32], the nanotube network
deposited here has higher density due to the optimized nanotube deposition recipe, which
leads to improved device performance in terms of mobility as discussed below.
Field-emission scanning electron microscope (FE-SEM) is used to inspect the samples
after nanotube assembly and the SEM images of the 95% and 98% semiconducting
nanotubes deposited on Si/SiO
2
substrates are shown in Figure 6.1 panels c and e,
respectively. From the image, one can find that the samples with APTES
functionalization give high density uniform nanotube deposition throughout the sample.
The average nanotube density for the 95% semiconducting nanotubes is measured to be
41 tubes/ μm
2
and the average nanotube density for the 98% semiconducting nanotubes is
measured to be 46 tubes/ μm
2
. Information about the deposition uniformity throughout a 3
inch wafer can be found in our previous publication [32]. The length distribution of the
95% and 98% semiconducting nanotubes are also characterized based on the SEM
images, and the corresponding histograms are plotted in Figure 6.1d and 1f, respectively.
The length of the 95% semiconducting nanotubes is measured to be 0.97 0.63 m μ ± , and
the length of the 98% semiconducting nanotubes is measured to be 0.81 0.41 m μ ± .
The deposited separated nanotube thin-films are used for the fabrication of
back-gated SN-TFTs and individual-gated SN-TFTs. The back-gated SN-TFT uses the
highly doped silicon substrate as the gate and 50 nm SiO
2
as the gate dielectric and can
be used as a simple platform for characterizing and comparing the electrical performance
of the separated nanotube thin-films. On the other hand, the individual-gated SN-TFT has
photolithography patterned Ti/Au gate where the individual gating allows the individual
123
control of every transistor in an integrated circuits. The schematic diagrams of the
back-gated and individual-gated SN-TFTs are shown in Figure 6.1 panels g and h,
respectively.
For the fabrication of the back-gated SN-TFTs, 50 nm SiO
2
is used to act as the
back-gate dielectric. The source and drain electrodes are patterned by photolithography,
and 5 Å Ti and 60 nm Pd are deposited followed by the lift-off process to form the source
and drain metal contacts. Finally, since the separated nanotube thin film covers the entire
wafer, in order to achieve accurate channel length and width, and to remove the possible
leakage in the devices, one more step of photolithography plus O
2
plasma is used to
remove the unwanted nanotubes outside the device channel region.
For the fabrication of the individual-gated SN-TFT and integrated circuits which
will be discussed later, Ti/Au back-gate electrodes are first patterned by photolithography
and lift-off process. 50 nm Al
2
O
3
high- κ dielectric and 5 nm SiO
2
are then deposited on
top of the Ti/Au back-gate by atomic layer deposition and e-beam evaporation,
respectively. Vias are then patterned using photolithography, and buffered oxide etch
(BOE) is used to remove the oxide layer in the vias to allow the interconnection between
the gate and drain of the transistor to form the diode-connected load transistor. The
separated nanotube thin-film is then deposited on the dielectric layer using the method
discussed above, and the rest of the fabrication steps including the source/drain electrodes
patterning and unwanted nanotube etching are the same as the back-gate transistor
fabrication discussed above.
124
Figure 6.2 Electrical properties of back-gated SN-TFTs using 95% and 98% semiconducting nanotubes. (a) Optical
microscope image of the SN-TFT array fabricated on a silicon substrate with 50 nm SiO
2
acting as gate dielectric. (b)
FE-SEM image showing the channel of a typical back-gated SN-TFT with 10 μm channel length. (c, d) Transfer
characteristics (I
D
–V
G
) of the SN-TFTs using 95% (c) and 98% (d) semiconducting nanotubes with various channel
lengths (4, 10, 20, 50, and 100 μm) and 100 μm channel width plotted in logarithm scale. (e) Transfer characteristics
(red, linear scale; green, log scale) and g
m
–V
G
characteristics (blue) of a typical SN-TFT (L = 50 μm, W = 100 μm)
using 95% semiconducting nanotubes. (f) Output characteristics (I
D
–V
D
) of the same device in panel e. (g) Transfer
characteristics (red, linear scale; green, log scale) and g
m
–V
G
characteristics (blue) of a typical SN-TFT (L = 100 μm, W
= 50 μm) using 98% semiconducting nanotubes. (h) Output characteristics of the same device in panel g.
a
c
95% Semiconducting
d
f e
b
-10 -5 0 5 10
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
I
on
/W (μA/μm)
Gate Voltage (V)
L = 4 μm
L = 10 μm
L = 20 μm
L = 50 μm
L = 100 μm
V
D
= 1 V
-5 -4 -3 -2 -1 0
-140
-120
-100
-80
-60
-40
-20
0
Drain Current (μA)
Drain Voltage (V)
V
G
is from -10 V to
0V in 1V steps
-10 -5 0 5 10
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
I
on
/W (μA/μm)
Gate Voltage (V)
L = 4 μm
L = 10 μm
L = 20 μm
L = 50 μm
L = 100 μm
V
D
= 1 V
g
-5 -4 -3 -2 -1 0
-10
-8
-6
-4
-2
0
Drain Current (μA)
Drain Voltage (V)
V
G
is from -10 V to
0V in 1V steps
h
98% Semiconducting
95% Semiconducting
95% Semiconducting
98% Semiconducting
98% Semiconducting
10
-7
10
-6
10
-5
-10 -5 0 5 10
0
10
20
30
40
Gate Voltage (V)
Drain Current (μA)
V
D
= 1 V
0
1
2
3
4
5
6
Transconductance (μS)
Drain Current (A)
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
-10 -5 0 5 10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Gate Voltage (V)
Drain Current (μA)
V
D
= 1 V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Transconductance (μS)
Drain Current (A)
125
We first use the back-gated SN-TFTs to directly compare the electrical
performance of the 95% and 98% semiconducting nanotube thin-films. The nanotube
deposition, devices fabrication for both nanotube samples are carried out at the same time
so that any variation in the sample preparation and device fabrication process can be
minimized. Such SN-TFTs are made with channel widths (W) of 10, 20, 50, 100, and 200
μm, and channel lengths (L) of 4, 10, 20, 50, and 100 μm. A microscope image of the
fabricated SN-TFT array is shown in Figure 6.2a and the SEM image of the channel of a
typical SN-TFT with 10 μm channel length is shown in Figure 6.2b.
We have carried out systematic study of the electrical performance of the
SN-TFTs as basic components for macroelectronic integrated circuits. Figure 6.2 panels c
and d are the transfer characteristics (I
D
–V
G
) of the SN-TFTs using 95% (Figure 6.2c) and
98% (Figure 6.2d) semiconducting nanotubes with various channel lengths (4, 10, 20, 50,
and 100 μm) and 100 μm channel width plotted in logarithm scale. All the curves are
measured at V
D
= 1 V. From the figures, we can have the following straightforward
observations. (1) Devices from both nanotube samples show p-type field-effect behavior
and much higher on/off ratio compared with the devices fabricated using unsorted
nanotubes, which typically exhibit an on/off ratio of around 2–3. (2) As the device
channel length increases, the on/off ratio increases while the on-current decreases.
Especially for the SN-TFTs with 95% semiconducting nanotubes, the on/off ratio
improves significantly from around 10 to over 10
4
as the channel length increases from 4
to 100 μm. (3) The devices using 98% semiconducting nanotubes exhibit better on/off
ratios but lower on-current than the devices using 95% semiconducting nanotubes.
126
Figure 6.2 panels e and g exhibit the transfer characteristics (red, linear scale;
green, log scale) and g
m
–V
G
characteristics (blue) of two typical SN-TFTs using 95% and
98% semiconducting nanotubes measured at V
D
= 1 V. For the 95% semiconducting
nanotube SN-TFT (Figure 6.2e), the channel length and width of the device are L = 50
μm and W = 100 μm, respectively. The on-current (I
on
) at V
D
= 1 V, V
G
= –10V is
measured to be 35.6 μA, corresponding to an on-current density (I
on
/W) of 0.356 μA/ μm.
The transconductance (g
m
) extracted from the maximum slope of the transfer
characteristics is 4.6 μS and the on/off ratio is 482. For the 98% semiconducting
nanotube SN-TFT (Figure 6.2g), the channel length is 100 μm and channel width is 50
μm. The on-current density is 0.058 μA/ μm, transconductance is 0.53 μS and on/off ratio
is 3x10
5
. The corresponding output characteristics (I
D
–V
D
) of these two SN-TFTs are
plotted in Figure 6.2 panels f and h, respectively. The output characteristics appear to be
very linear under small V
D
biases, indicating that ohmic contacts are formed between the
metal electrodes and the nanotubes. Under more negative V
D
biases, the devices exhibit
saturation behavior, indicating nice field-effect operation.
On the basis of the transconductance, we can further extract the device mobility of
the SN-TFTs. Under V
D
= 1 V, devices operate in the triode region, so the device
mobility can be calculated from the following equation,
dm
device
Dox g Dox
dI g LL
VC W dV V C W
μ=⋅ = ⋅ (1)
127
where L and W are the device channel length and width, V
D
= 1 V, and C
ox
is the gate
capacitance per unit area. The capacitance is calculated by considering the electrostatic
coupling between nanotubes using the following equation [34,35],
1
11 00
0
0
sinh(2 / ) 1
ln
2
ox
ox Q
ox
t
CC
R
π
πε ε π
−
−−
⎧⎫ ΛΛ ⎡⎤
=+ Λ
⎨⎬
⎢⎥
⎣⎦
⎩⎭
(2)
where 1/ Λ
0
stands for the density of nanotubes and is measured to be around 10 tubes/ μm,
C
Q
= 4.0 x 10
-10
F/m is the quantum capacitance of nanotubes and the value is taken from
a previous report [36], t
ox
= 50 nm is the thickness of the dielectric layer, R = 1.2 nm is
the radius of nanotubes, and ε
0
ε
ox
= 3.9 x 8.85 x 10
-14
F/cm is the dielectric constant at the
interface where the nanotubes are placed. On the basis of Equation 2, one can find that
C
ox
= 3.46 x 10
-8
F/cm
2
. Using this C
ox
value and on the basis of the device geometry and
normalized transconductance g
m
/W, the device mobility is calculated to be 67 cm
2
V
-1
s
-1
for the 95% semiconducting nanotube SN-TFT, and 31 cm
2
V
-1
s
-1
for the 98%
semiconducting nanotube SN-TFT.
To get a more comprehensive understanding, we compare the key device
performance metrics such as on-current density, on/off ratio, transconductance, and
mobility for SN-TFTs based on separated nanotubes with different purities of
semiconducting nanotubes. Figure 6.3 summarizes the results after the measurement of
175 SN-TFTs with various channel lengths, channel widths, and different semiconducting
nanotube purities. Out of the devices measured, 100 of them are fabricated on 95%
semiconducting nanotubes, and 75 of them are fabricated on 98% semiconducting
nanotubes.
128
Figure 6.3 Statistical study of 175 SN-TFTs using separated nanotubes with 95% and 98% semiconducting nanotubes,
as well as comparison of key device performance metrics. Plot of (a) current density (I
on
/W), (b) average on/off ratio
(I
on
/I
off
), (c) normalized transconductance (g
m
/W), and (d) device mobility ( μ
device
) versus channel length for TFTs
fabricated on separated nanotubes with 95% (black trace) and 98% (red trace) semiconducting nanotubes.
Figure 6.3a exhibits the normalized on-current densities (I
on
/W) of the transistors
with various channel lengths measured at V
D
= 1 V and V
G
= -10 V, showing that the
on-current density is approximately inversely proportional to the channel length for both
95% and 98% semiconducting nanotubes. The highest on-current density from SN-TFTs
using 95% semiconducting nanotubes is measured to be 5.2 μA/ μm and the highest
on-current density from SN-TFTs using 98% semiconducting nanotubes is measured to
d
0 20 406080 100
0.1
1
95% Semiconducting SWNTs
98% Semiconducting SWNTs
I
on
/W (μA/μm)
Channel Length (μm)
0 2040 6080 100
10
1
10
2
10
3
10
4
10
5
95% Semiconducting SWNTs
98% Semiconducting SWNTs
On/Off Ratio
Chanel Length (μm)
b a
c
0 20 406080 100
20
30
40
50
60
70
95% Semiconducting SWNTs
98% Semiconducting SWNTs
Mobility (cm
2
V
-1
s
-1
)
Channel Length (μm)
0 20 406080 100
10
-2
10
-1
10
0
95% Semiconducting SWNTs
98% Semiconducting SWNTs
g
m
/W (μS/μm)
Channel Length (μm)
129
be 1.0 μA/ μm. Both values are achieved in devices with L = 4 μm. Comparing the data
for transistors using 95% and 98% semiconducting nanotubes, one can easily find that the
average on-current density of 95% semiconducting nanotubes is higher than the
on-current density of 98% semiconducting nanotubes by a factor of 3–7 at all device
channel lengths measured. The difference in the on-current density can be attributed to
the difference in nanotube lengths. For instance, the average length for the 95%
semiconducting nanotubes is approximately 0.97 μm, while the average length for the
98% semiconducting nanotubes is about 0.81 μm. For transistors of similar channel
length, using longer nanotubes would lead to less nanotube–nanotube junctions, and
consequently better performance. Besides, for devices using both 95% and 98%
semiconducting nanotubes, the measurement results exhibit very small error bar,
indicating the highly uniform nature of the SN-TFTs.
Due to the high density and uniform nature of the separated nanotube thin-film
deposited on Si/SiO
2
substrates with APTES functionalization, the corresponding thin-film
transistors (TFTs) are also expected to behave uniformly. The uniformity of the devices is
illustrated in Figure 6.4, which shows the current density (I
on
/W) (Figure 6.4a), on/off ratio
(Figure 6.4b), and mobility (Figure 6.4c) measured at V
D
= 1 V for 12 representative TFTs
using 95% and 98% semiconducting nanotubes with channel length L = 10 μm. From the
figures, one can find that the TFT device performance metrics exhibit very small
distribution, indicating very good device uniformity.
130
Figure 6.4 Current density (I
on
/W) (a), on/off ratio (b), and mobility (c) measured at V
D
= 1 V for 12 representative TFTs
using 95% and 98% semiconducting nanotubes with channel length of 10 μm. The red lines represent the average values.
For SN-TFTs fabricated using separated nanotubes with different purities of
semiconducting nanotubes, besides the difference in on-current density discussed
previously, the other major difference is expected to be the on/off ratio and the difference
is explained in Figure 6.3b. First of all, as the channel length increases, the average on/off
ratio of SN-TFTs using both 95% and 98% semiconducting nanotubes increases. This can
be explained by the decrease in the probability of percolative transport through metallic
nanotube networks as the device channel length increases. On the other hand, SN-TFTs
12 3 4 56
0
1
2
3
12 3 4 56
0.0
0.1
0.2
0.3
0.4
I
on
/W (μA/μm)
95% Semiconducting
Device number
98% Semiconducting
1 2345 6
10
0
10
2
10
4
10
6
1 2 3 456
10
0
10
2
10
4
10
6
On/Off Ratio
95% Semiconducting
Device number
98% Semiconducting
a b
c
123 45 6
0
20
40
60
80
1 2 3 456
0
20
40
60
80
Mobility (cm
2
V
-1
s
-1
)
95% Semiconducting
Device number
98% Semiconducting
131
with 98% semiconducting nanotubes have much higher on/off ratio compared with
SN-TFTs with 95% semiconducting nanotubes, especially at small channel lengths,
which can be naturally attributed to the small percentage of metallic nanotubes. For
SN-TFTs with 95% semiconducting nanotubes, the on/off ratio improves significantly
from around 10 to above 10
4
as the channel length increases from 4 to 100 μm. In
contrast, for the SN-TFTs 98% semiconducting nanotubes, the device on/off ratio stays
above 10
4
at all channel lengths.
Interestingly, the data shown in Figure 6.3a and b reveal a trade-off between
drive-current and on/off ratio. By using separated nanotubes with higher purity of
semiconducting nanotubes, on one hand, it can help to achieve sufficient on/off ratio with
smaller channel length, thus smaller device area; on the other hand, since higher purity
requires more ultracentrifugation which will give rise to shorter nanotube length, it can
cause more nanotube percolation and hurt the overall devices performance such as
on-current density discussed previously and mobility as will be discussed below.
Besides the on-current density and on/off ratio, there are two more important
figures of merit for SN-TFTs, which are device transconductance (g
m
) and mobility
( μ
device
). The normalized transconductance (g
m
/W) of devices with various channel lengths
are characterized and are plotted in Figure 6.3c; g
m
is extracted from the maximum slope
of the transfer characteristics measured at V
D
= 1 V, and is normalized to device channel
width. From the figure, one can find that as channel length increases, g
m
/W decreases.
This is because g
m
/W is also inversely proportional to channel length. Moreover, similar
to I
on
/W, the SN-TFTs using 95% semiconducting nanotubes also exhibit better
132
performance in terms of g
m
/W compared with SN-TFTs using 98% semiconducting
nanotubes.
Using the data for the normalized transconductance plotted in Figure 6.3c and
Equation 1, we can calculate the devices mobility of the SN-TFTs, and the data is plotted
in Figure 6.3d. Interestingly, the device mobility of the SN-TFTs with 95% and 98%
semiconducting nanotubes follows different trends. For the SN-TFTs with 95%
semiconducting nanotubes, the device mobility decreases as channel length increases,
while for the SN-TFTs with 98% semiconducting nanotubes, the device mobility
increases as channel length increases. The reason for the decreasing trend of the SN-TFTs
using 95% semiconducting nanotubes is attributed to the percolative transport through the
nanotube network. As the device channel length increases from a value comparable to the
nanotube length to a much larger value, there are significantly more tube-to-tube
junctions introduced into the conduction path, causing the device mobility to decrease
[32]. On the other hand, it is not yet clear why the SN-TFTs using 98% semiconducting
nanotubes show increasing trend in the device mobility as the channel length increases,
and this is currently under further investigation in our group. Another important point is
that devices using 95% semiconducting nanotubes exhibit higher mobilities than devices
using 98% semiconducting nanotubes. Besides the difference in the purity of
semiconducting nanotubes, other factors such as nanotube length, density of nanotube
network, etc. also play a role in determining the ultimate electrical performance of the
SN-TFTs, resulting in the difference between the 95% and 98% semiconducting
nanotubes in terms of device mobility, as well as on-current density, transconductance,
133
and on/off ratio discussed before. The reason is that the difference in nanotube length and
density can affect the nanotube percolation network, changing the amount of tube-to-tube
junctions, and the probability of metallic conduction path formation between the source
and drain electrodes. Numerical simulations have been performed by our group and other
groups [32,37-39] to fully assess such effect on the performance of nanotube TFTs.
6.3 Integrated circuits using separated nanotube thin-film transistors
Our ability to fabricate high performance, uniform, high on/off ratio SN-TFTs
enable us to further explore their applications in digital integrated circuits. We have
already discussed the trade-off between on-current and on/off ratio for different purities
of semiconducting nanotubes, and we choose to use the separated nanotubes with 98%
semiconducting nanotubes for the digital integrated circuit fabrication. The reason is that
for digital application, it is desirable to have large switching, preferably rail-to-rail, in
order to achieve large noise margin. More importantly, the off-state current has to be low
to reduce the static power consumption. Therefore, it is more important for the transistors
to have a large on/off ratio rather than high on-current. For SN-TFTs with 98%
semiconducting nanotubes, At all channel lengths measured, more than 95% of the
devices exhibit on/off ratio higher than 10
4
. This amount of on/off ratio is large enough
for most kinds of integrated circuit applications.
134
Figure 6.5 Integrated inverter circuits using separated carbon nanotubes. (a, d) Schematic of two different diode-load
inverters using SN-TFTs with different device dimensions. (b, e) Optical microscope images of these two
corresponding inverters. (c, f) Inverter voltage transfer characteristic (red trace) and voltage gain (blue trace) of these
two corresponding inverters. Both inverters work with a V
DD
of 3 V and exhibit symmetric input/output behavior. (g)
Inverter voltage transfer characteristics measured at different supply voltages (V
DD
). (h) Curve showing the dependence
between the inverter voltage gain and supply voltage. Inset: schematic of the circuit with parasitic resistance at the
output node.
For the proof of concept purpose, we demonstrate the basic digital functional
blocks such as inverter, 2-input NAND, and NOR using SN-TFTs. The fabrication
a b c
d
e f
g h
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Gain
Output Voltage(V)
Input Voltage (V)
Max Gain = 1.45
0.0
0.5
1.0
1.5
2.0
0 1 234 56 7
0
1
2
3
4
5
6
7
Gain = 4.23
Gain = 3.76
Gain = 3.15
V
DD
= 3V
V
DD
= 5V
V
DD
= 7V
Output Voltage (V)
Input Voltage (V)
345 67
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
Gain
V
DD
(V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Gain
Output Voltage(V)
Input Voltage (V)
Max Gain = 2.78
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
135
process of these integrated circuits is similar to the individual back-gated SN-TFTs and is
discussed previously. We start with the inverter design and find that the highly uniform
nature of the SN-TFTs allows us to optimize the circuit performance using the
conventional silicon transistor circuit design theory. As an example, for the diode-load
inverter investigated in Figure 6.5, the output impedance looking into the source of the
diode-connected SN-TFTs is 1/g
m_load
, and the voltage gain of the inverter is given by
_
/
V m out m m load
AgR g g =≈ . For transistors operating in the saturation region, the
transconductance can be calculated by 2(/)
mpox sd
gCWLI μ = , where μ
p
is the mobility
of the devices, C
ox
is the gate capacitance per unit area, and I
sd
is the source–drain current
of the transistor. Considering that the current flowing through the switching transistor (I
sd
)
is equal to current flowing through the diode-connected transistor (I
sd_load
), we can find
the gain of the diode-load inverter to be equal to
_ _
2(/)
2( / )
pox sd
mload
V
m load load p ox load load sd load
CW LI
gL W
A
gWL CW L I
μ
μ
== = ⋅ (3)
where W, L, W
load
, and L
load
, are the channel width, channel length for the switching
transistor, and channel width, channel length for the diode-load transistor, respectively.
The schematics of two diode-load inverters with different geometries used in this
study are shown in Figure 6.5 panels a and d. By design, inverter 1 has W = 100 μm, L =
50 μm, W
load
= 100 μm, L
load
= 150 μm; while inverter 2 has W = 100 μm, L = 40 μm,
W
load
= 50 μm, L
load
= 150 μm. The corresponding optical microscope images of these
two inverters are shown in Figure 6.5 panels b and e, respectively. In the circuit, one
transistor is acting as the switching transistor and is connected between the supply
136
voltage V
DD
and the output, and the other transistor is configured as a diode-load and is
connected between the output and ground. The inverters are characterized by sweeping
input voltage V
IN
and measure the output voltage V
OUT
. The corresponding inverter
voltage transfer characteristics are plotted in Figure 6.5 panels c and f, respectively. For
the measurement, V
DD
is biased at 3 V and V
IN
is swept between 0 and 3V. Measurements
reveal that for both inverters, as input voltages increase from 0 to 3V, output voltages
decrease from 3 to 0V, meaning that they are functioning correctly as logic inverters. The
maximum voltage gain measured is 1.45 for inverter 1 and 2.78 for inverter 2. According
to the conventional diode-load inverter circuit design equation discussed before (Equation
3) and the device dimensions, we have
1
31.73
V
A=≈ for inverter 1 and
2
7.5 2.74
V
A=≈ for inverter 2. This means that our measurement results are consistent
with the conventional circuit design theory, and by simply changing the dimension of the
switching and load transistors in the layout design, we can achieve inverters with
different voltage gains.
Another very important merit for the inverters using SN-TFTs is that they offer
symmetric input/output behavior, meaning that both input and output are operating under
the same voltage range (0–3V in this case). This character is important for single power
supply voltage operation and is crucial for cascading logic blocks for larger scale
integration where the output of the preceding logic block needs to be able to drive the
ensuing logic block directly.
The relationship between the gain of the inverters and the power supply voltage is
also studied, and the voltage transfer characteristics for an inverter measured under
137
different V
DD
are shown in Figure 6.5g. From the figure, we find that the inverter keeps
showing symmetric input/output behavior under all supply voltages. Besides, if we plot
the voltage gain versus V
DD
(Figure 6.5h), we see a monotonic increase in maximum
voltage gain as the V
DD
increases. It is worth noting that for the diode-load inverters, the
voltage gain is ideally independent of V
DD
as shown in Equation 3. The reason we see the
increasing trend is due to the finite input impedance of the measurement instrument (HP
4156B in this case). Since the input impedance of the measurement instrument (R
P
) is
not infinitely large compared with the output impedance of the SN-TFT used in the
inverters, the instrument draws some amount of current (I
Rp
). As V
DD
increases, the
output DC level at the maximum voltage gain increases, causing I
Rp
to increase. From
Kirchhoff current law, we have I
sd
= I
sd_load
+ I
Rp
, so as V
DD
increases, I
sd_load
is getting
smaller and smaller compared with I
sd
. Furthermore, based on Equation 3, the inverter
voltage gain is proportional to
_
/
sdsdload
II , this explains why the voltage gain
increases as the power supply voltage increases.
In addition to inverters, more sophisticated circuits such as 2-input NAND and
NOR have also been demonstrated. Figure 6.6 shows the schematics (Figure 6.6a and d),
optical microscope images (Figure 6.6b and e) and output characteristics (Figure 6.6c and
f) of the NAND and NOR, respectively. Both logic blocks employ a diode-connected
SN-TFT in the pull-down network similar to the inverters and they are both operated with
a V
DD
of 2 V. The 3 V and 0 V applied on gate A and B are treated as logic “1” and “0”,
respectively. For the NAND, the output is “1” when either one of the two inputs is “0”
(Figure 6.6c), while for the NOR, the output is “0” when either one of the two inputs is
138
“1” (Figure 6.6f). These output characteristics confirm that our circuits are realizing the
logic function correctly. With the combination of these basic logic blocks, more
sophisticated logic circuits which require cascading multiple stages of logic gates can be
readily constructed, and the work is currently ongoing in our group.
Figure 6.6 Integrated 2-input NAND and NOR circuits using separated carbon nanotubes. (a, d) Schematic of
diode-load 2-input NAND and NOR circuits using SN-TFTs. (b, e) Optical microscope images of the corresponding
NAND and NOR circuits. (c, f) Output characteristics of the corresponding NAND and NOR circuits. The supply
voltages for both circuits are V
DD
= 2 V . Input voltages of 3 and 0V are treated as logic “1” and “0”, respectively.
0.0
0.3
0.6
0.9
1.2
1.5
Gate B: "0" "1" "0" "1"
Gate A: "0" "0" "1" "1"
Output Voltage(V)
a b c
d e f
0.0
0.3
0.6
0.9
1.2
1.5
Gate B: "0" "1" "0" "1"
Output Voltage(V)
Gate A: "0" "0" "1" "1"
NAND
NOR
139
6.4 Summary
In conclusion, we report the progress on the application of separated nanotube
thin-film transistors for macroelectronic integrated circuits, including progress on the
direct comparison of key performance metrics of devices using separated nanotubes with
95% and 98% semiconducting nanotubes, and the demonstration of integrated digital
logic blocks with symmetric input/output behavior. We have revealed the trade-off
between the on-current density and on/off ratio for the SN-TFT device optimization, and
the optimized SN-TFTs with excellent yield, current density, mobility, and on/off ratio
have been used to demonstrate integrated digital logic circuits such as inverter, NAND,
and NOR. Moreover, we have demonstrated that it is possible to tune the circuit
performance by simply changing the device dimensions in the layout design, and the
experimental results are in accordance with conventional silicon field-effect transistor
circuit design theory. Our work represents significant advance in the separated nanotube
thin-film electronics, which solves the problem of coexistence of both metallic and
semiconducting nanotubes in the state-of-the-art nanotube transistor fabrication
techniques, and can provide guide to future research on SN-TFT based integrated circuits.
140
Chapter 6. References
1. Bockrath, M.; Cobden, D.; McEuen, P.; Chopra, N.; Zettl, A.; Thess, A.; Smalley, R.
Single-Electron Transport in Ropes of Carbon Nanotubes. Science 1997, 275,
1922–1925.
2. Wildoer, J.; Venema, L.; Rinzler, A.; Smalley, R.; Dekker, C. Electronic Structure of
Atomically Resolved Carbon Nanotubes. Nature 1998, 391, 59–62.
3. Odom, T.; Huang, J.; Kim, P. Lieber, C. Atomic Structure and Electronic Properties
of Single-Walled Carbon Nanotubes. Nature 1998, 391, 62–64.
4. Tans, S.; Verschueren, A.; Dekker, C. Room-Temperature Transistor Based on a
Single Carbon Nanotube. Nature 1998, 393, 49–52.
5. Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, P. Single- and Multi-Wall
Carbon Nanotube Field-Effect Transistors. Appl. Phys. Lett. 1998, 73, 2447–2449.
6. Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654–657.
7. Durkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39.
8. Zhou, X.; Park, J. Y.; Huang, S.; Liu, J.; McEuen, P. L. Band Structure, Phonon
Scattering, and the Performance Limit of Single-Walled Carbon Nanotube
Transistors. Phys. Rev. Lett. 2005, 95, 146805
9. Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon
Nanotube Transistors. Science 2001, 294, 1317–1320.
10. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, P. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
11. Liu, X.; Lee, C.; Han, J.; Zhou, C. Carbon Nanotube Field-Effect Inverters. Appl.
Phys. Lett. 2001, 79, 3329–3331.
12. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays
for Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2,
929–932.
13. Chen, Z.; Appenzeller, J.; Lin, Y .; Oakley, J. S.; Rinzler, A. G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, P. An Integrated Logic Circuit Assembled on a Single
Carbon Nanotube. Science 2006, 311, 1735.
141
14. Snow, E. S.; Novak, J. P.; Campbell, P. M.; Park, D. Random Networks of Carbon
Nanotubes as an Electronic Material. Appl. Phys. Lett. 2003, 82, 2145–2147.
15. Snow, E. S.; Campbell, P. M.; Ancona, M. G.; Novak, J. P. High-Mobility
Carbon-Nanotube Thin-Film Transistors on a Polymeric Substrate. Appl. Phys. Lett.
2005, 86, 033105-1–033105-3.
16. Artukovic, E.; Kaempgen, M.; Hecht, D. S.; Roth, S.; Gruner, G. Transparent and
Flexible Carbon Nanotube Transistors. Nano Lett. 2005, 5, 757–760.
17. Hu, L.; Hecht, D. S.; Gruner, G. Percolation in Transparent and Conducting Carbon
Nanotube Networks. Nano Lett. 2004, 4, 2513–2517.
18. Zhang, D.; Ryu, K.; Liu, X.; Polikarpov, E.; Ly, J.; Tompson, M. E.; Zhou, C.
Transparent, Conductive, and Flexible Carbon Nanotube Films and Their
Application in Organic Light-Emitting Diodes. Nano Lett. 2006, 6, 1880–1886.
19. Ishikawa, F.; Chang, H.; Ryu, K.; Chen, P.; Badmaev, A.; De Arco Gomez, L.; Shen,
G.; Zhou, C. Transparent Electronics Based on Transfer Printed Aligned Carbon
Nanotubes on Rigid and Flexible Substrates. ACS Nano 2009, 3, 73–79.
20. Cao, Q.; Rogers, J. A. Ultrathin Films of Single-Walled Carbon Nanotubes for
Electronics and Sensors: A Review of Fundamental and Applied Aspects. Adv.
Mater. 2008, 21, 29–53.
21. Cao, Q.; Kim, H. S.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.;
Alam, M. A.; Rogers, J. A. Medium-Scale Carbon Nanotube Thin-Film Integrated
Circuits on Flexible Plastic Substrates. Nature 2008, 454, 495–500.
22. Street, R. A. (Ed.) Technology and Applications of Amorphous Silicon; Springer:
Berlin, 2000.
23. Ucjikoga, S. Low-Temperature Polycrystalline Silicon Thin-Film Transistor
Technologies for System-on-Glass Displays. MRS Bull. 2002, 27, 881–886.
24. Snell, A. J.; Mackenzie, K. D.; Spear, W. E.; LeComber, P. G.; Hughes, A. J.
Application of Amorphous Silicon Field Effect Transistors in Addressable Liquid
Crystal Display Panels. Appl. Phys. A 1981, 24, 357–362.
25. Dimitrakopoulos, C. D.; Mascaro, D. J. Organic Thin-Film Transistors: A Review
of Recent Advances. IBM J. Res. Dev. 2001, 45, 11–27.
142
26. Forrest, S. R. The Path to Ubiquitous and Low-Cost Organic Electronic Appliances
on Plastic. Nature 2004, 428, 911–918.
27. Gelinck, G. H.; Edzer, H.; Huitema, A.; Van Veenendaal, E.; Cantatore, E.;
Schrijnemakers, L.; Van Der Putten, J. B. P. H.; Geuns, T. C. T.; Beenhakkers, M.;
Giesbers, J. B.; Hiusman, B.-H.; Meijer, E. J.; Benito, E. M.; Touwslager, F. J.;
Marsman, A. W.; Van Rens, B. J. E.; De Leeuw, D. M. Flexible Active-Matrix
Displays and Shift Registers Based on Solution-Processed Organic Transistors. Nat.
Mater. 2004, 3, 106–110.
28. Klauk, H.; Halik, M.; Zschieschang, U.; Eder, F.; Rohde, D.; Schmid, G.; Dehm, C.
Flexible Organic Complementary Circuits. IEEE Trans. Electron Devices 2005, 52,
618–622.
29. Arnold, M. S.; Green, A. A.; Hulvat, J. F.; Stupp, S. I.; Hersam, M. C. Sorting
Carbon Nanotubes by Electronic Structure Using Density Differentiation. Nat.
Nanotechnol. 2006, 1, 60–65.
30. Arnold, M. S.; Stupp, S. I.; Hersam, M. C. Enrichment of Single-Walled Carbon
Nanotubes by Diameter in Density Gradients. Nano Lett. 2005, 5, 713–718.
31. Engel, M.; Small, J. P.; Steiner, M.; Freitag, M.; Green, A. A.; Hersam, M. C.;
Avouris, P. Thin Film Nanotube Transistors Based on Self-Assembled, Aligned,
Semiconducting Carbon Nanotube Arrays. ACS Nano 2008, 2, 2445–2452.
32. Wang, C.; Zhang, J; Ryu, K.; Badmaev, A.; Gomez, L.; Zhou, C. Wafer-Scale
Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display
Applications. Nano Lett. 2009, 9, 4285–4291.
33. LeMieux, M. C.; Roberts, M.; Barman, S.; Jin, Y. W.; Kim, J. M.; Bao, Z.
Self-Sorted, Aligned Nanotube Networks for Thin-Film Transistors. Science 2008,
321, 101–104.
34. Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S.
V.; Rogers, J. A. High-Performance Electronics Using Dense, Perfectly Aligned
Arrays of Single-Walled Carbon Nanotubes. Nat. Nanotechnol. 2007, 2, 230–236.
35. Cao, Q.; Xia, M.; Kocabas, C.; Shim, M.; Rogers, J. A.; Rotkin, S. V. Gate
Capacitance Coupling of Singled-Walled Carbon Nanotube Thin-Film Transistors.
Appl. Phys. Lett. 2007, 90, 023516-1–023516-3.
36. Rosenblatt, S.; Yaish, Y.; Park, J.; Gore, J.; Sazonova, V.; McEuen, P. L. High
Performance Electrolyte Gated Carbon Nanotube Transistors. Nano Lett. 2002, 2,
869–872.
143
37. Pimparkar, N.; Kocabas, C.; Kang, S. J.; Rogers, J. A.; Alam, M. A. Limits of
Performance Gain of Aligned CNT Over Randomized Network: Theoretical
Predictions and Experimental Validation. Electron Device Lett. 2007, 28, 593–595.
38. Kocabas, C.; Pimparkar, N.; Yesilyurt, O.; Alam, M. A.; Rogers, J. A. Experimental
and Theoretical Studies of Transport through Large Scale, Partially Aligned Arrays
of Single-Walled Carbon Nanotubes in Thin Film Type Transistors. Nano Lett. 2007,
7, 1195–1202.
39. Pimparkar, N.; Cao, Q.; Kumar, S.; Murthy, J. Y.; Rogers, J. A.; Alam, M. A.
Current–Voltage Characteristics of Long-Channel Nanobundle Thin-Film
Transistors: A “Bottom-Up” Perspective. Electron Device Lett. 2007, 28, 157–160.
144
Chapter 7. Radio Frequency and Linearity Performance of
Transistors Using High-Purity Semiconducting Carbon Nanotubes
7.1 Introduction
The application of single-walled carbon nanotubes in advanced electronics has
been heavily exploited for over a decade. This interest stems from the fact that carbon
nanotubes offer a combination of small size, high mobility, ballistic transport, large
current density, and low intrinsic capacitance [1-5]. They have been used extensively to
demonstrate various kinds of integrated circuits such as logic gates, ring oscillators, and
decoders [6-11].
However, due to the coexistence of both metallic and semiconducting
nanotubes, the on/off ratio is typically very small for the as-made transistors using a large
number of nanotubes [12-14], and various techniques including electrical breakdown [15],
stripe patterning [11], or using presorted semiconducting nanotubes [16-18] are necessary
in order to boost the on/off ratio of transistors significantly. Therefore, for the carbon
nanotubes, instead of digital circuit applications, a more realistic application is the
high-performance analog or radio frequency (RF) devices, where manufacturing
tolerances are relaxed and the performance metrics required are more suited to the
materials and device properties of nanotubes, especially since the transistors do not need
to be fully turned off.
Previously, many groups have investigated the potential of using carbon
nanotubes for RF applications and have demonstrated the operation of those transistors in
the gigahertz frequency range [19-23]. However, in those reports, mainly chemical vapor
145
deposition (CVD)-grown nanotubes, which consist of mixed metallic and semiconducting
nanotubes, are used. The existence of the metallic nanotubes causes leakage current in the
off-state and results in low on/off ratios. Although for analog/RF application, the on/off
ratio is not as crucial as for digital applications, low on/off ratio can still result in low
efficiency for applications such as power amplifiers and degrade the transconductance
(g
m
) and cutoff frequency (f
t
) of the RF transistors.
Recent reports have shown that the semiconducting nanotubes can be separated
from the metallic nanotubes using density gradient ultracentrifugation, resulting in
nanotube solution with up to 99% semiconducting nanotube purity [24,25]. By using such
prepurified semiconducting nanotubes, the RF performance is expected to be further
improved. With semicondcuting nanotubes assembled by dielectrophoresis [26], RF
transistors with an impressive cutoff frequency of 80 GHz have been demontrated by
Happy and co-workers [21]. Despite the significant progress, there is still room for
further improvement in terms of scalability. We have previously reported an
aminopropyltriethoxysilane (APTES)-assisted separated nanotube deposition technique
that is capable of depositing high-density and uniform semiconducting nanotube thin
films at complete wafer scale [17,18]. In this regard, it would be interesting to investigate
the performance of nanotube RF transistors fabricated using such scalable platforms. In
this work, we have demonstrated that such RF transistors can be fabricated at complete
wafer scale, and electrical characterization reveals that such devices also exhibit large
transconductance, current drive, and gigahertz operation.
146
Moreover, it is also important to point out that other than f
t
, another even more
important figure of merit for RF transistors is the device linearity. It is crucial to not only
amplifying signals at high frequency but also amplifying signals linearly in order to
maintain the fidelity of the signals. Linearity is also an extremely important property in
signal-rich environments due to interference and intermodulation from other
communication bands and channels. Transistors based on one-dimensional (1D) materials
have recently been predicted to offer much better linearity characteristics than traditional
bulk devices, which is fundamentally due to the combination of the unique 1D transport
properties and the 1D density of states of carriers in the transistor channel [27]. To test
the linearity of the nanotube transistor, there have been few studies where a common
source configuration nanotube transistor loaded with a high impedance resistor on the
drain, terminated with a high impedance active probe, has been driven with two
low-frequency tones to characterize the circuit’s harmonic distortion [28]. However,
since the active probes are used in the study to provide the high impedance termination
required for the low current drive nanotube devices, the operational bandwidth is small,
limited to order of kilohertz, and the measured nonlinearity metrics are not valid for the
frequencies under which the nanotube transistors are intended to be implemented and
operated at (i.e., gigahertz frequency).
In this work, we have, to the best of our knowledge, for the first time,
characterized the key device linearity metrics with standard 50 Ω terminations and
conducted the two-tone test of the nanotube RF devices at gigahertz frequency, which is
the intended operating frequency of the transistor. We performed nonlinearity
147
measurements using both single-tone and two-tone, where major device linearity figures
of merits such as the -1 dB gain compression point (P1dB) and input/output third-order
intercept points (IIP3/OIP3 or ITOI/OTOI) were extracted. Our work shows that, in line
with theoretical predictions, the semiconducting nanotube-based transistors are promising
building blocks for future highly linear RF electronics and circuits.
7.2 Separated nanotube RF transistor fabricaion
Figure 7.1a illustrates the fabrication process and shows the schematic of the
completed separated nanotube RF transistor. The device fabrication process is briefly
discussed as follows. First, the substrate is chosen to be a highly resistive silicon wafer
( ρ > 5 k Ω·cm) with 200 nm SiO
2
to ensure minimum parasitics from the substrates. The
titanium/gold (0.5/50 nm) probing pads are first patterned using contact aligner and
lift-off process. After that, aluminum back-gates (40 nm) are patterned using e-beam
writing, and the sample is heated to 200 °C in oxygen to oxidize the surface of the
aluminum to form 2–3 nm Al
2
O
3
as gate dielectric. The reason to use Al/Al
2
O
3
gate
stacking instead of the traditional top-gate structure with high- κ dielectric such as Al
2
O
3
and HfO
2
deposited by atomic layer deposition (ALD) is that the thermal oxidization of
Al to form Al
2
O
3
is a self-limiting process, resulting in high-quality, ultrathin gate
dielectric, which leads to better gate strength and larger transconductance. In contrast, it
is very difficult to obtain leakage-free Al
2
O
3
dielectric with such small thickness using
ALD.
148
Figure 7.1 Scalable fabrication of the aluminium back-gated separated nanotube RF transistors. (a) Schematic showing
the APTES-assisted separated nanotube deposition process for the separated nanotube RF transistor fabrication. (b) A
wafer of the separated nanotube RF transistors. (c) Optical microscope image of the nanotube RF transistor. (d)
Zoom-in optical microscope image showing two pairs of channels, the aluminium back-gate, and Pd S/D extensions of
the nanotube RF transistor. (e) SEM image showing the channel of the device with a channel length of 500 nm.
As a next step, high density and uniform separated 95% semiconducting
nanotubes (IsoNanotubes-S from NanoIntegris, Inc.) with an average length of 1 μm are
deposited using the APTES-assisted separated nanotube deposition technique as
discussed in our previous publications [17,18]. With the deposited semiconducting
nanotube thin film acting as the conduction channel, the palladium source/drain
extensions are patterned using e-beam writing to further shrink the device channel length
a
b c
d e
149
down to 500 nm. Palladium is used here as the source/drain metal contacts due to its large
work function, which offers Schottky-barrier-free contacts to the nanotubes for hole
injection [5]. As a final step, e-beam writing plus oxygen plasma is used to remove the
unwanted nanotubes outside the device channel region in order to achieve accurate
channel length and width and to remove the possible leakage in the devices.
The above-described APTES-assisted separated nanotube deposition method and
the RF transistor fabrication process is scalable and can thus be performed at wafer scale.
A 3 inch wafer with the RF transistors is shown in Figure 7.1b. The optical microscope
image of the separated nanotube RF transistor is shown in Figure 7.1c, where the device
is configured into the ground-signal-ground (GSG) coplanar waveguide structure so that
we can perform microwave measurements. The device contains a pair of nanotube
channels with a channel width of 500 μm and a channel length of 500 nm. Figure 7.1d is
a zoom-in optical microscope image, where we can clearly identify two pairs of channels,
the Ti/Au pads, Al back-gate and Ti/Pd source/drain extensions. The SEM image of the
device channel region after nanotube deposition is shown in Figure 7.1e. The strip in the
center corresponds to the aluminum back-gate, and the top and bottom metal electrodes
are the Ti/Pd source/drain extensions. The channel length is 500 nm, and one can find
that the channel is covered by a high-density semiconducting nanotube network.
7.3 DC characteristics of the separated nanotube RF transistors
We have first characterized the DC performance of the separated nanotube RF
transistors, and the results are summarized in Figure 7.2. Figure 7.2a is the transfer
150
characteristics (I
DS
–V
GS
curves) measured at various drain voltages (V
DS
) for one channel
of the nanotube RF transistor with W = 500 μm and L = 500 nm. From the curves, one
can find that the on-state current of the device (I
on
) measured at V
DS
= -1 V and V
GS
= -2
V, is 9.06 mA, which corresponds to an on-state current density (I
on
/W) of 18.12 μA/ μm.
The off-state current (I
off
) measured at V
DS
= -1 V and V
GS
= 2 V, is 1.93 mA, so that we
can calculate the on/off ratio of the device to be 4.69. The device cannot be completely
depleted due to the 500 nm channel length used. As reported in our previous publication,
for devices using 95% semiconducting nanotubes, the on/off ratio is heavily dependent
on the device channel length [17,18]. As the channel length decreases, the on/off ratio
decreases, and the on/off ratio is always below 10 when a channel length of less than 4
μm is used. Using either longer channel length (> 10 μm) or separated nanotube solution
with even higher purity (e.g., 99%) of semiconducting nanotubes would lead to a
significant improvement in on/off ratio but also with a significantly reduced
transconductance [18]. In principle, by using semiconducting nanotubes with higher
purity, the device transconductance and thus RF performance should be improved,
considering that the nanotubes are still exactly the same as the lower purity sample in
terms of length, diameter, and band gap. However, for the nanotube samples we used in
this study, higher-purity semiconducting nanotubes (98 and 99%) tend to have shorter
length compared with lower purity ones (95%). Therefore, although the transistors using
98% semiconducting nanotubes exhibit much better on/off ratio, the on-current density
and transconductance are, in fact, lower than the transistors using 95% semiconducting
nanotubes by a factor of 3~7 [18]. This trade-off between on/off ratio and
151
transconductance can be attributed to more tube-to-tube junctions resulting from shorter
nanotubes. On the basis of the discussion above, our choice of using 95% semiconducting
nanotubes is well justified because transconductance is the most crucial parameters for
the RF device instead of the on/off ratio.
Figure 7.2 DC characteristics of the separated nanotube RF transistors. (a) Transfer characteristics (I
DS
–V
GS
) of the
separated nanotube RF transistor (L = 0.5 μm, W = 500 μm) measured at various V
DS
. (b) g
m
–V
GS
characteristics
measured at V
DS
= -1 V. (c) Output (I
DS
–V
DS
) characteristics measured at various V
GS
from -2 to 2V.
Figure 7.2b shows the g
m
–V
GS
curve derived from the I
DS
–V
GS
characteristics. The
maximum g
m
is measured to be 2.81 mS when V
GS
is around 0 V, and the corresponding
g
m
/W is 6.28 µS/µm. Figure 7.2c is the output characteristics (I
DS
–V
DS
curves) of the
-2 -1 0 1 2
0
-2
-4
-6
-8
-10
VDS = -1.0V
VDS = -0.8V
VDS = -0.6V
VDS = -0.4V
VDS = -0.2V
Drain Current (mA)
Gate Voltage (V)
-1.5 -1.2 -0.9 -0.6 -0.3 0.0
-12
-10
-8
-6
-4
-2
0
VG is from -2V to 2V
in 0.2V steps
Drain Current (mA)
Drain Voltage (V)
a b
c
-2 -1 0 1 2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
g
m
(mS)
Gate Voltage (V)
VDS = -1V
152
device measured under different gate biases. We can see that the I
DS
–V
DS
curves appear to
be linear at low drain biases, indicating that ohmic contacts instead of Schottky contacts
are formed between the metal electrodes and the nanotubes. Under higher biases, the
current begins to saturate, and the saturation behavior is superimposed on the metallic
behavior of the nanotube RF transistor. This leads to improved R
out
, which is useful in
order to obtain a voltage gain.
7.4 RF characteristics of the separated nanotube RF transistors
We have further characterized the RF performance of the separated nanotube
transistor using vector network analyzer (VNA), and the measurement setup is shown in
Figure 7.3a. The sources are grounded, and the DC biases are supplied to the gate and
drain terminal through the bias-T. For the RF measurement, the gate is biased at V
GS
= 0
V and the drain is biased at V
DS
= -1 V, as this is the bias condition that gives the
maximum g
m
, as confirmed by the DC measurement. The measured S parameters from 50
MHz to 5 GHz are plotted in Figure 7.3b. From the S parameters, we can further derive
the h
21
, which corresponds to the current gain, and the maximum available gain (G
max
)
using the following equations [22]
21
21
11 22 12 21
2
(1 )(1 )
s
h
ss ss
−
=
−+ +
(1)
21
max
12
S
G
S
= for K < 1 or
2 21
max
12
(1)
S
GKK
S
= −− for K > 1 (2)
where K is the stability factor that can be calculated using the following equation
153
22 2
11 22 12 21 11 22
12 21
1
2
SS S S S S
K
SS
+− − −
= (3)
The derived h
21
(red trace) and G
max
(green trace) are plotted as a function of
frequency in Figure 7.3c. From the figure, one can find that, at 1 GHz, the current gain
h
21
drops to 0 dB. So the as-measured (i.e., extrinsic) cutoff frequency (f
t_extrinsic
) of the
separated nanotube RF transistor is 1 GHz. From the G
max
curve, we can also find that the
unity power gain frequency f
max
is 1.5 GHz.
Figure 7.3 RF characteristics of the separated nanotube RF transistors. (a) Schematic showing the RF measurement
setup. (b) As-measured S parameters for the separated nanotube RF transistor (dual channel with L = 0.5 μm, W = 500
μm) from 50 MHz to 5 GHz. The transistor is biased at V
GS
= 0 V and V
DS
= -1 V for maximum g
m
. (c) Extrinsic and
Intrinsic current gain h
21
, and maximum available gain G
max
derived from the measured S parameters from 50 MHz to 5
GHz. (d) Transconductance and intrinsic cutoff frequency as a function of V
GS
.
a
i
1
+
i
1
-
i
2
+
Port 1
AC in
Port 2
AC out
V
gs, bias
V
ds, bias
i
1
+
i
1
-
i
2
+
Port 1
AC in
Port 2
AC out
V
gs, bias
V
ds, bias
100MHz 1GHz 5GHz
-50
-40
-30
-20
-10
0
VGS = 0V, VDS = -1V
S11
S12
S21
S22
S-parameters (dB)
Frequency
b
d c
-0.4 -0.2 0.0 0.2
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
1
2
3
4
5
gm
g
m
(mS)
Gate Voltage (V)
VDS = -1V
ft_intrinsic
f
t_intrinsic
(GHz)
100MHz 1GHz 5GHz
-20
-10
0
10
20
30
40
50
VGS = 0V, VDS = -1V
ft_intrinsic = 5GHz
h21_extrinsic
h21_intrinsic
Gmax
fmax = 1.5GHz
Gain (dB)
Frequency
ft_extrinsic = 1GHz
154
The extrinsic cutoff frequency of the transistor is largely affected by the parasitic
capacitance, and if we perform short-open-load-through (SOLT) de-embedding, we can
rule out the effect from the parasitic capacitance and deduce the intrinsic cutoff frequency
(f
t_intrinsic
) of the separated nanotube RF transistor. In particular, considering the small size
of the nanotubes in the channel in comparison with the GSG pads incorporated for
probing measurement, the parasitic capacitance could strongly degrade the corresponding
AC performance. In order to remove the parasitic effect and deduce the intrinsic cutoff
frequency of the separated nanotube RF transistor, a short/open scheme is used for this
purpose, and the device under test (DUT) is de-embedded according to the following
equation
111
_int
(( ) ( ) )
device rinsic meas open short open
YYY YY
− −−
=− − − (4)
where the S parameters for the measured device, open (Figure 7.4a–c), and short (Figure
7.4d–f) structures are converted to Y parameters, and the intrinsic S parameters of the
device are in turn converted back from the intrinsic Y parameters derived using the above
equation. A “through” structure would not have modified the results considerably for the
frequency regime we are interested in. The de-embedding open/short structures are done
by actual on-die probing measurements, where the open/short structures are fabricated on
the same wafer with the separated nanotube RF transistors studied in this work, and with
exactly the same dimensions. The results for the measured on-die open/short structures
are presented in Figure 7.4. On the basis of the SOLT de-embedding scheme discussed
above, we have deduced the intrinsic h
21
of the separated nanotube RF transistor, which is
155
plotted as the blue trace in Figure 7.3c. From the figure, the intrinsic cutoff frequency is
derived to be 5 GHz.
Figure 7.4 RF measurement results of the open and short structures for the SOLT de-embedding. (a–c) Layout (a),
measured S
11
(b), and measured S
21
(c) of the open structure. (d–f) Layout (d), measured S
11
(e), and measured S
21
(f) of
the short structure.
Moreover, the measured h
21
and thus the cutoff frequency of the separated
nanotube RF transistor exhibits gate bias dependence as illustrated in Figure 7.3d. This is
because f
t
is approximately proportional to g
m
, which is a function of the gate voltage.
The extrinsic and intrinsic h
21
of the separated nanotube transistor measured at V
DS
= -1 V
and V
GS
equals -0.4 V, -0.2 V, 0 V, and 0.2 V are shown in Figure 7.5a, b, c, and d,
respectively. From the results, one can find that as the gate voltage varies from -0.4 to 0.2
V, the measured cutoff frequency of the device also varies and peaks at V
GS
= 0 V. The
variation of f
t
follows the variation of g
m
since f
t
is proportional to g
m
(Figure 7.3d). The
shift of around 0.24 V between the g
m
and f
t
curves can be attributed to the device
freq (50.00MHz to 5.000GHz)
S(1,1)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.0 5.0
-60
-50
-40
-30
-70
-20
freq, GHz
dB(S(2,1))
freq (50.00MHz to 5.000GHz)
S(1,1)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.0 5.0
-100
-90
-80
-70
-60
-110
-50
freq, GHz
dB(S(2,1))
b c a
d e f
156
hysteresis. As shown in Figure 7.6, we have observed certain amount of hysteresis in the
transfer characteristics of the separated nanotube RF transistor when the devices are
measured with both forward and backward gate voltage sweeps. The magnitude of the
hysteresis (evaluated at half of I
max
at V
DS
= -1 V) is measured to be 0.24 V when V
GS
is
swept from -2 to 2 V. This explains the shift of ~ 0.24 V between the g
m
–V
GS
and f
t
–V
GS
characteristics presented in Figure 7.3d.
Figure 7.5 Extrinsic and intrinsic current gain (h
21
) of the separated nanotube RF transistor measured at V
GS
= -0.4 V
(a), -0.2 V (b), 0 V (c), and 0.2 V (d).
100MHz 1GHz 5GHz
-20
-10
0
10
20
30
40
50
ft_intrinsic = 1.63GHz
h21_extrinsic
h21_intrinsic
Gain (dB)
Frequency
ft_extrinsic = 434.1MHz
V
GS
= -0.4V
100MHz 1GHz 5GHz
-20
-10
0
10
20
30
40
50
V
GS
= -0.2V
ft_intrinsic = 3.03GHz
h21_extrinsic
h21_intrinsic
Gain (dB)
Frequency
ft_extrinsic = 706.7MHz
100MHz 1GHz 5GHz
-20
-10
0
10
20
30
40
50
V
GS
= 0V
ft_intrinsic = 4.98GHz
h21_extrinsic
h21_intrinsic
Gain (dB)
Frequency
ft_extrinsic = 0.99GHz
100MHz 1GHz 5GHz
-20
-10
0
10
20
30
40
50
ft_intrinsic = 2.71GHz
h21_extrinsic
h21_intrinsic
Gain (dB)
Frequency
ft_extrinsic = 638.5MHz
V
GS
= 0.2V
a
b
c d
157
Figure 7.6 Transfer (I
DS
-V
GS
) characteristics of the separated nanotube RF transistors measured with forward and
backward gate voltage sweeps.
Furthermore, owing to the uniformity of the separated nanotube thin film
deposited using APTES, the transistors also behave uniformly. For the six transistors for
which we characterized the RF performance, the deduced intrinsic f
t
values under the
optimal bias conditions only vary from 3.05 to 4.98 GHz, and the average performance
from those transistors is 3.86 GHz.
7.5 Linearity characteristics of the separated nanotube RF transistors
Besides the cutoff frequency, linearity is another important figure of merit for RF
transistors. We have performed both single-tone and two-tone measurements using the
test bench setup illustrated in Figure 7.7a. Since our separated nanotube RF transistors
provide high current drive, on the order of 10 to 20 mA, we do not need to resort to
high-impedance probes or terminations as opposed to the previous report [28].
-2 -1 0 1 2
0
-2
-4
-6
-8
-10
VDS = -1.0V
VDS = -0.8V
VDS = -0.6V
VDS = -0.4V
VDS = -0.2V
Drain Current (mA)
Gate Voltage (V)
0.24 V
158
Consequently, the measurement bandwidth is not limited. For the measurement, two
tones at adjacent frequencies are applied to the gate of the nanotube RF transistors
through a power combiner. The two tones are applied all the way up to the extrinsic f
t
limit of the nanotube RF transistors, as reported below, and not just in the kilohertz and
sub-kilohertz range in the previous report [28]. Besides, despite the high current drive
and g
m
of our separated nanotube RF transistors, we decided not to focus on the gain
from the device, as we chose to incorporate standard 50 Ω terminations (for both the
spectrum analyzer and the load) in order to observe the high-frequency behavior of the
device. Nevertheless, it is worth noting that the absence of gain may affect the linearity
measurement in the circuit level since the output signal level is limited. Possible solutions
to this issue include increasing the nanotube density in order to improve g
m
/W or further
enlarging the device channel width. In order to achieve gain from the transistors directly
driving 50 Ω loads, g
m
×
R
out
should be greater than 1, where the total impedance seen at
the output node (R
out
) equals the output resistance of the transistor (r
o
) in parallel with the
input impedance of the measurement instrument (50 Ω) and the 50 Ω load resistor.
Assuming r
o
is much larger than 50 Ω, R
out
is therefore approximately 25 Ω, which means
that the device transconductance needs to be larger than 40 mS so that g
m
×
25 > 1. We are
currently working on the above proposed solutions to further increase the
transconductance in order to obtain gain from the transistors.
159
Figure 7.7 Linearity characteristics of the separated nanotube RF transistors. (a) Schematic showing the two-tone
measurement setup to capture the nonlinearity of the separated nanotube RF transistors. (b) Single-tone harmonic
distortion characterization results showing the output spectrum of the device with various input power levels from -10
to 12 dBm. (c) Output power of the fundamental as a function of input power to extract the 1 dB gain compression
point (P1dB). (d) Two-tone intermodulation characterization results showing the output spectrum with various input
power levels from 6 to 16 dBm. (e) Output power of the fundamental and third-order intermodulation as a function of
the input power to extract the IIP3 and OIP3.
a
c
d e
6 8 10 12 14 16 18
-80
-70
-60
-50
-40
-30
-20
3rd-order
Intermodulation
2ω
2
− ω
1
2ω
1
− ω
2
ω
2
Input Power = 6 dBm
Input Power = 8 dBm
Input Power = 10 dBm
Input Power = 12 dBm
Input Power = 14 dBm
Input Power = 16 dBm
Output Power (dBm)
Frequency (MHz)
ω
1
Fundamental
10 15 20 25 30 35
-80
-70
-60
-50
-40
-30
-20
3ω
0
2ω
0
Input Power = -10dBm
Input Power = -8dBm
Input Power = -6dBm
Input Power = -4dBm
Input Power = -2dBm
Input Power = 0dBm
Input Power = 2dBm
Input Power = 4dBm
Input Power = 6dBm
Input Power = 8dBm
Input Power = 10dBm
Input Power = 12dBm
Output Power (dBm)
Frequency (MHz)
ω
0
b
-10 -5 0 5 10
-55
-50
-45
-40
-35
-30
-25
Output Power (dBm)
Input Power (dBm)
CP
-1dB
> 12 dBm
5 10 15202530 35 40
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Fundamental
3rd-order Intermodulation
IIP3 = 36.3 dBm
Output Power (dBm)
Input Power (dBm)
OIP3 = -9.1 dBm
IP
3
160
For the linearity measurement, the device is characterized for single-tone
(second-order and third-order harmonic distortion for 1 dB compression point) as well as
two-tone intermodulation distortion (third-order intercept point analysis). Figure 7.7b
shows the results of the single-tone measurement, where the separated nanotube RF
transistor biased with V
GS
= 0 V (for peak g
m
and f
T
) and V
DS
= -1V is driven with a
single tone of varying power levels at 9 MHz. From the output spectrum captured using
the spectrum analyzer, one can find the fundamental ( ω
0
), the second-order (2 ω
0
) and
third-order (3 ω
0
) harmonic components. If we extract the output power of the
fundamental from Figure 7.7b and plot it as a function of input power, we can obtain the
compression point plot as shown in Figure 7.7c. This figure indicates that the output
power increases linearly as the input power up to 12 dBm, and no gain compression can
be observed. This means that the P1dB of the separated nanotube RF transistor is above
12 dBm; that is, the device operates linearly up to an input power of 12 dBm (~ 16 mW).
Figure 7.7d illustrates the intermodulation distortion performance of our separated
nanotube RF transistors in accordance with the test-bench presented in Figure 7.7a. We
conducted the two-tone test with two tones at 9 MHz ( ω
1
) and 11 MHz ( ω
2
) to ensure the
third-order intermodulations ( ω
1
+ 2 ω
2
and 2 ω
1
+ ω
2
) that fall close to the tones are
observable and measurable accurately. On the basis of Figure 7.7d, the power level of the
fundamentals and third-order intermodulations are extracted and are plotted as a
functional of input power (Figure 7.7e). In theory, as the input power increases, the
power of the third-order intermodulations increases 3 times faster than the fundamental.
Therefore, we can perform extrapolation and find the point where the power of the
161
third-order intermodulation is equal to the power of the fundamental. This is the so-called
third-order intercept point, and the corresponding input and output power levels are
defined as IIP3 and OIP3. From Figure 7.7e, the IIP3 is measured to be 36.3 dBm (~ 4.3
W) and the OIP3 is measured to be -3.3 dB (~ 0.5 mW) for the separated nanotube RF
transistors. We have also performed the two-tone intermodulation distortion
measurements with two tones at 1 GHz ( ω
1
) and 1.1 GHz ( ω
2
), which are at the extrinsic
f
t
limit (1 GHz) of the separated nanotube RF transistors, and the results are shown in
Figure 7.8. The results indicate that the power gain does not decrease much even when
the input frequency is at 1 GHz. Besides, from the figure, we can find that only the
second-order intermodulation ( ω
1
+ ω
2
) is visible. The third-order intermodulations
( ω
1
+2 ω
2
and 2 ω
1
+ ω
2
) are already below the noise floor, which is an indication of good
linearity at such frequencies.
Figure 7.8 Near f
t
two-tone intermodulation characterization results showing the output spectrum of the separated
nanotube RF transistor with two input tones at 1 GHz and 1.1 GHz.
1.0 1.5 2.0 2.5
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
2nd-order harmonics
2ω
2
2ω
1
Output Power (dBm)
Frequency (GHz)
ω
1
= 1 GHz
ω
2
= 1.1 GHz
Fundamental
ω
2
ω
1
ω
1
+ ω
2
2nd-order Intermodulation
162
7.6 Summary
As a conclusion, we have demonstrated the scalable fabrication of RF transistors
with cutoff frequency up to 5 GHz using separated nanotube networks. With direct 50 Ω
termination, the linearity figures of merit of the transistors including P1dB, IP3 have been
characterized, for the first time, at the frequencies where the transistors are intended to be
operating. Our work reveals that the semiconducting nanotube-based transistors are
potentially promising building blocks for future highly linear RF electronics and circuits.
163
Chapter 7. References
1. Durkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39.
2. Zhou, X.; Park, J. Y.; Huang, S.; Liu, J.; McEuen, P. L. Band Structure, Phonon
Scattering, and the Performance Limit of Single-Walled Carbon Nanotube
Transistors. Phys. Rev. Lett. 2005, 95, 146805-1–146805-3.
3. Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654–657.
4. Javey, A.; Guo, J.; Farmer, D.; Wang, Q.; Yenilmez, E.; Gordon, R.; Lundstrom, M.;
Dai, H. Self-Aligned Ballistic Molecular Transistors and Electrically Parallel
Nanotube Arrays. Nano Lett. 2004, 4, 1319–1322.
5. Javey, A.; Guo, J.; Farmer, D.; Wang, Q.; Wang, D.; Gordon, R.; Lundstrom, M.;
Dai, H. Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts
and High- κ Gate Dielectrics. Nano Lett. 2004, 4, 447–450.
6. Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon
Nanotube Transistors. Science 2001, 294, 1317–1320.
7. Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, P. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
8. Liu, X.; Lee, C.; Han, J.; Zhou, C. Carbon Nanotube Field-Effect Inverters. Appl.
Phys. Lett. 2001, 79, 3329–3331.
9. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays
for Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2,
929–932.
10. Chen, Z.; Appenzeller, J.; Lin, Y .; Oakley, J. S.; Rinzler, A. G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, P. An Integrated Logic Circuit Assembled on a Single
Carbon Nanotube. Science 2006, 311, 1735.
11. Cao, Q.; Kim, H. S.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.;
Alam, M. A.; Rogers, J. A. Medium-Scale Carbon Nanotube Thin-Film Integrated
Circuits on Flexible Plastic Substrates. Nature 2008, 454, 495–500.
164
12. Wang, C.; Ryu, K.; Badmaev, A.; Patil, N.; Lin, A.; Mitra, S.; Wong, H.-S. P.; Zhou,
C. Device Study, Chemical Doping and Logic Circuits Based on Transferred
Aligned Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2008, 93,
033101-1–033101-3.
13. Ryu, K.; Badmaev, A.; Wang, C.; Lin, A.; Patil, N.; Gomez, L.; Kumar, A.; Mitra,
S.; Wong, H.-S. P.; Zhou, C. CMOS-Analogous Wafer-Scale Nanotube-on-Insulator
Approach for Submicrometer Devices and Integrated Circuits Using Aligned
Nanotubes. Nano Lett. 2009, 9, 189–197.
14. Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S.
V.; Rogers, J. A. High-Performance Electronics Using Dense, Perfectly Aligned
Arrays of Single-Walled Carbon Nanotubes. Nature Nanotechnol. 2007, 2,
230–236.
15. Collins, P. G.; Arnold, M. S.; Avouris, P. Engineering Carbon Nanotubes and
Nanotube Circuits Using Electrical Breakdown. Science 2001, 292, 706–709.
16. Engel, M.; Small, J. P.; Steiner, M.; Freitag, M.; Green, A. A.; Hersam, M. C.;
Avouris, P. Thin Film Nanotube Transistors Based on Self-Assembled, Aligned,
Semiconducting Carbon Nanotube Arrays. ACS Nano 2008, 2, 2445–2452.
17. Wang, C.; Zhang, J; Ryu, K.; Badmaev, A.; Gomez, L.; Zhou, C. Wafer-Scale
Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display
Applications. Nano Lett. 2009, 9, 4285–4291.
18. Wang, C.; Zhang, J.; Zhou, C. Macroelectronic Integrated Circuits Using
High-Performance Separated Carbon Nanotube Thin-Film Transistors. ACS Nano,
2010, 4, 7123–7132.
19. Li, S.; Yu, Z.; Yen, S.; Tang, W.; Burke, P. Carbon Nanotube Transistor Operation at
2.6 GHz. Nano Lett. 2004, 4, 753–756.
20. Louarn, A.; Kapche, F.; Bethoux, J.-M.; Happy, H.; Dambrine, G.; Derycke, V.;
Chenevier, P.; Izard, N.; Goffman, M. F.; Bourgoin, J.-P. Intrinsic Current Gain
Cutoff Frequency of 30 GHz with Carbon Nanotube Transistors. Appl. Phys. Lett.
2007, 90, 233108-1–233108-3.
21. Nougaret, L.; Happy, H.; Dambrine, G.; Derycke, V.; Bourgoin, J.-P.; Green, A. A.;
Hersam, M. C. 80 GHz Field-Effect Transistors Produced Using High Purity
Semiconducting Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2009, 94,
243505-1–243505-3.
165
22. Kocabas, C.; Kim, H.; Banks, T.; Rogers, J.; Pesetski, A.; Baumgardner, J.;
Krishnaswamy, S.; Zhang, H. Radio Frequency Analog Electronics Based on
Carbon Nanotube Transistors. Proc. Natl. Acad. Sci. 2008, 105, 1405–1409.
23. Kocabas, C.; Dunham, S.; Cao, Q.; Cimino, K.; Ho, X.; Kim, H.; Dawson, D.;
Payne, J.; Stuenkel, M.; Zhang, H.; Banks, T.; Feng, M.; Rotkin, S. V .; Rogers, J. A.
High-Frequency Performance of Submicrometer Transistors That Use Aligned
Arrays of Single-Walled Carbon Nanotubes. Nano Lett. 2009, 9, 1937–1943.
24. Arnold, M. S.; Green, A. A.; Hulvat, J. F.; Stupp, S. I.; Hersam, M. C. Sorting
Carbon Nanotubes by Electronic Structure Using Density Differentiation. Nat.
Nanotechnol. 2006, 1, 60–65.
25. Arnold, M. S.; Stupp, S. I.; Hersam, M. C. Enrichment of Single-Walled Carbon
Nanotubes by Diameter in Density Gradients. Nano Lett. 2005, 5, 713–718.
26. Krupke, R.; Hennrich, F.; Löhneysen, H. V.; Kappes, M. M. Separation of Metallic
from Semiconducting Single-Walled Carbon Nanotubes. Science 2003, 301, 344.
27. Wang, R.; Zhuge, J.; Huang, R.; Tian, Y.; Xiao, H.; Zhang, L.; Li, C.; Zhang, X.;
Wang, Y. Analog/RF Performance of Si Nanowire MOSFETs and the Impact of
Process Variation. IEEE Trans. Electron Devices 2007, 54, 1288–1294.
28. Pesetski, A. A.; Baumgardner, J. E.; Folk, E.; Przybysz, J. X.; Adam, J. D.; Zhang,
H. Carbon Nanotube Field-Effect Transistor Operation at Microwave Frequencies.
Appl. Phys. Lett. 2006, 88, 113103-1–113103-3.
166
Chapter 8. Conclusions and Future Directions
8.1 Conclusions
As a conclusion, this dissertation discusses the application of carbon nanotubes
for scalable, practical, and high performance nanoelectronics and macroelectronics. To
overcome the challenges of nanotube transistor integration, minimizing the
device-to-device performance variation, and making the fabrication process scalable and
compatible with industry standards, I have developed assembly techniques that are
capable of providing thin-films of highly ordered and uniformly distributed carbon
nanotubes at complete wafer-scale. These two material platforms include horizontally
aligned carbon nanotubes and thin-films of preseparated high purity semiconducting
carbon nanotubes. Besides scalable material platforms, many other essential technology
components, including metallic nanotube removal, increasing nanotube density, and
methods to obtain air-stable n-type nanotube transistors have also been demonstrated. On
the basis of the above achievements, I have further demonstrated various kinds of
electronic applications including integrated circuits, display electronics, and
radio-frequency electronics.
The works related to horizontally aligned carbon nanotubes grown using chemical
vapor deposition are presented in chapters 2, 3, and 4. The topics include wafer-scale
processing of aligned carbon nanotube electronics, improving nanotube density for better
device performance, and using metal contact engineering for air-stable n-type nanotube
transistors and CMOS integrated circuits. Chapters 5, 6, and 7 discuss the work related to
167
separated nanotube thin-films, where techniques for separated nanotube thin-film
assembly, fabrication of high-performance separated nanotube thin-film transistors, and
applications in integrated circuits, display electronics, and radio-frequency electronics are
explored.
This dissertation, through experimental demonstration, proves the potential and
feasibility of using carbon nanotubes for future beyond-silicon nanoelectronics and
macroelectronics.
8.2 Future directions on aligned carbon nanotubes
In order to achieve predictable and uniform device performance for more
sophisticated large scale integrated nanotube circuits, it is important to control the
electronic type (metal, semiconducting) and ultimately the chirality of the carbon
nanotubes. For carbon nanotubes grown using CVD, it is believed that their diameters are
determined by the size of the catalytic metal particles. Previously, researches have
reported the use of nanosphere lithography to control the size of the catalysts in hope of
achieving chirality-controlled nanotube synthesis [1]. However, in that work, even by
using catalyst particles defined by polystyrene nanosphere lithography, it is still hard to
control the size of catalyst perfectly accurate, and the nanotubes grown by such method
still exhibit certain amount of diameter distribution. Secondly, even if the catalyst size
and nanotube diameter can be controlled perfectly, a given diameter can still correspond
to many possible chiralities. Therefore, in order to achieve control over the chirality of
the nanotubes, alternative approaches need to be taken.
168
We believe that in order to achieve chirality-controlled carbon nanotube growth, it
is important to move away from metal-catalyzed CVD and use chirality-pure nanotube
seed for cloned growth instead. Here we propose two approaches to grow chirality-pure
metallic and semiconducting nanotubes, respectively. In order to obtain chirality-pure
metallic nanotubes, C90 molecules can be used and the growth mechanism is illustrated
in Figure 8.1a. The C90 molecules can be deposited onto the quartz growth substrate
using spin-coating followed by air annealing at 400 °C and water vapor annealing at
900 °C to open the cap of the C90 molecules. After that, standard CVD recipe as
discussed in chapter 2 is used to grow carbon nanotubes from the C90 seed. Due to the
molecular structure of C90, the chirality of the as-grown nanotubes are expected to be
(5,5) as shown in the schematic.
Figure 8.1 Chirality-controlled metallic carbon nanotube growth using C90. (a) Schematic diagram illustrating the growth
mechanism. (b) SEM image of the nanotubes grown from C90. (c) AFM image of the nanotubes grown from C90. (d)
Diameter distribution of the nanotubes grown from C90. Most nanotubes have diameter very close to the diameter of (5,5)
nanotubes (0.68 nm).
a
b c d
0.6 0.9 1.2 1.5 1.8
0
5
10
15
20
25
30
Number of Nanotubes
Diameter (nm)
Diameter of (5,5) nanotubes
0.68 nm
d = 0.857 ± 0.255nm
169
The SEM image, AFM image, and diameter distribution of nanotubes grown from
C90 are shown in Figure 8.1b, c, and d, respectively. From the figures, one can find that
nanotubes can indeed be grown from C90 without any metal catalytic particles. The
diameter of nanotubes determined by AFM is 0.857 ± 0.255 nm, with most nanotubes
having diameters very close to the diameter of (5,5) nanotubes (0.68 nm). The small
deviation from 0.68 nm can be attributed to the accuracy of AFM for determining the
diameter since the nanotubes may not be lying completely flat on the substrate.
Figure 8.2 Electrical properties of the carbon nanotubes grown from C90. (a–d) SEM image (a), AFM image (b), cross
section height information extracted from AFM (c), and transfer/output characteristics (d) of an individual nanotube
transistor. The diameter of the nanotube in the transistor is around 0.7 nm. (e) Transfer characteristics of 15 individual
nanotube transistors with 10 of them being metallic.
To further characterize the nanotubes grown from C90, we have fabricated
transistors and measured their electrical properties. In order to get conclusive information,
a
0.00.1 0.20.3 0.4 0.5
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Height (nm)
Distance (μm)
0.737 nm
-5.0 -2.5 0.0 2.5 5.0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
Drain Current (nA)
Gate Voltage (V)
V
D
= 1 V
-5.0 -2.5 0.0 2.5 5.0
1E-4
1E-3
0.01
0.1
1
10
Drain Current (nA)
Gate Voltage (V)
b c
d
-1.0 -0.5 0.0 0.5 1.0
-0.5
0.0
0.5
1.0
1.5
Drain Current (nA)
Drain Voltage (V)
V
G
= 0 V
e
170
we have fabricated transistors consisting of only one individual nanotube using ebeam
writing. The data for a typical C90 nanotube transistor are shown in Figures 8.2a–d.
Figure 8.2a and b are the SEM and AFM images of the C90 nanotube transistor, and the
diameter of the nanotube is measured to be around 0.7 nm by AFM as shown in Figure
8.2c. From the transfer and output characteristics shown in Figure 8.2d, we can find that
it is a metallic nanotube with no gate modulation. If we can further determine that the
nanotube is an armchair nanotube (m=n) instead of tiny-gap semiconducting nanotube
(m-n=3j, where j is a nonzero integer), then we can conclude that this nanotube must be
(5,5) nanotube as other armchair nanotubes ((4,4), (6,6), (7,7) etc.) all have diameters
very different from 0.7 nm. This can be done by performing low-temperature electrical
measurements. We have also measured the transfer characteristics of 15 individual
nanotube transistors as shown in Figure 8.2e and have found that 10 of them (66%) are
metallic. This percentage is higher than the theoretical 33% metallic nanotube ratio,
indicating that we have certain yield of cloned metallic nanotube growth.
In order to achieve chirality-controlled semiconducting nanotube growth,
chirality-pure semiconducting nanotube seed can be used. Researchers have demonstrated
chirality-based nanotube separation using either DNA [2] or density gradient
ultracentrifugation (DGU) (Hersam et al. Northwestern University), resulting in (6,5)
nanotubes with up to 99% purity. Such prepurified (6,5) nanotubes can be deposited on
the substrates by either drop-coating or spin-coating and used as seeds for further cloned
CVD growth to elongate the nanotubes and the corresponding schematic diagram is
shown in Figure 8.3a. The AFM image and diameter distribution of the pristine (6,5)
171
nanotube seeds before CVD cloning are shown in Figure 8.3b, from which one can find
that the average length of the pristine (6,5) nanotube seeds is smaller than 1 μm. After
CVD cloning, nanotubes with significantly longer length can be found as shown in Figure
8.3c, while the diameter of the cloned nanotubes remains almost unchanged. This is a
strong indication of cloned growth with the chirality of the nanotube seed preserved in
the cloned nanotubes.
Figure 8.3 Chirality-controlled semiconducting nanotube growth using prepurified (6,5) nanotube seeds. (a) Schematic
illustrating the nanotube cloning process. (b) AFM image and diameter distribution of the pristine (6,5) nanotubes before
CVD cloning. (c) AFM image and diameter distribution of the (6,5) nanotubes after cloning.
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
0
1
2
3
4
5
6
7
d = 0.996 ± 0.175nm
Numbebr of nanotubes
Diameter (nm)
a
b
c
0.60.8 1.01.2 1.4 1.6 1.82.0
0
1
2
3
4
5
6
7
8
9
10
11
d = 1.021 ± 0.337nm
Number of Nanotubes
Diameter (nm)
172
In summary, we have demonstrated that nanotubes can be grown from nanotube
seeds without any metal catalysts and have provided some indirect evidence that we
might indeed have chirality-controlled nanotube growth. The next step is to determine the
chirality of the cloned nanotubes accurately, which can be done by Rayleigh scattering
spectroscopy, transmission electron microscopy (TEM), or scanning tunneling
microscopy (STM). After the chiralities of the nanotubes can be accurately characterized,
the percentage of nanotubes with chirality-controlled growth can be further determined.
The next step would be to optimize the CVD recipe in order to further improve the
cloning yield. Finally, the carbon nanotubes with well-controlled chiralities can be
utilized for electronic devices and more sophisticated integrated circuits.
8.3 Future directions on nanotube thin-film electronics
For the separated nanotube thin-film electronics, the next step is to go toward
more sophisticated nanotube CMOS integrated circuits such as central processing unit
(CPU). For CMOS operation, both p-type and n-type nanotube thin-film transistors
(TFTs) are required, and the air-stable n-type TFTs can be obtained by adding a high- κ
oxide passivation layer (HfO
2
or Al
2
O
3
) deposited by atomic-layer deposition (ALD) as
discussed in our previous publication [3]. From the transfer and output characteristics
shown in Figures 8.4a and b, one can find that after the ALD passivation, the same device
can be converted from p-type to n-type with almost perfectly symmetric electrical
behavior in terms of on-current, transconductance and threshold voltage. The reason for
such carrier-type conversion is found to be the desorption of oxygen molecules and
173
accumulation of positive fixed charge in the nanotude dielectric layer interface caused by
the ALD deposition process.
Figure 8.4 Integrated CMOS logic circuits using separated nanotube thin-film transistors. (a, b) Transfer characteristics
(a) and output characteristics (b) of a typical separated nanotube TFT before (red) and after (blue) ALD passivation. (c)
Schematic diagram of an integrated CMOS inverter using air-stable n-type nanotube TFT obtained from the ALD
passivation approach. (d) Voltage transfer characteristics of the integrated CMOS nanotube inverter. (e, f) Output
characteristics of the integrated CMOS NAND (e) and NOR (f) logic gates.
On the basis of the aforementioned symmetric n-type and p-type nanotube TFTs,
we can further obtain integrated CMOS logic circuits. Figure 8.4c shows the schematic
diagram of an integrated CMOS inverter. The key innovation is to integrate the nanotube
a b
d
c
-5.0 -2.5 0.0 2.5 5.0
0
3
6
9
12
15
18
0.2 V
0.4 V
0.6 V
0.8 V
V
D
= 1 V
0.2 V
0.4 V
0.6 V
0.8 V
N-CNTFET P-CNTFET
Drain Current (μA)
Gate Voltage (V)
V
D
= 1 V
-1.0 -0.5 0.0 0.5 1.0
0
3
6
9
12
15
18
0
3
6
9
12
15
18
I
ds
(μA)
P-CNTFET
-I
ds
(μA)
Drain Voltage (V)
N-CNTFET
V
G
is from -5 V to 5 V
in 1 V step
e f
174
TFTs on different metal layers in order to achieve either p-type or n-type behavior. The
n-type nanotube TFT will be sitting at the bottom of the stacking (right transistor in the
schematic), using bottom layer metal as the source/drain contacts, and top-gated with
HfO
2
deposited by ALD as the gate dielectric. Due to the ALD passivation effect, this
transistor will exhibit n-type behavior. In contrast, the p-type TFT will be sitting on the
top layer of the stacking (left transistor in the schematic) and back-gated with the same
HfO
2
dielectric. Since the transistor is exposed in ambient environment, it will remain to
be p-type. The voltage and current transfer characteristics of the inverter using such
design are presented in Figure 8.4d. Such inverter works with a V
DD
of 3 V, exhibits
symmetric input/output behavior with rail-to-rail output, and with a maximum gain of
11.6. Moreover, the current is zero when the output reaches its boundary, meaning that
the static power consumption is almost zero as long as the inverter stays in “0” or “1”
state, which is due to the advantage of CMOS operation. Similarly, integrated CMOS
NAND and NOR logic gates are also demonstrated, whose output characteristics are
shown in Figure 8.4e and f, respectively. For the NAND, the output is “1” when either
one of the two inputs is “0” (Figure 8.4e), while for the NOR, the output is “0” when
either one of the two inputs is “1” (Figure 8.4f). These output characteristics confirm that
our circuits are realizing the logic function correctly.
The above-discussed approach for integrated CMOS nanotube circuits is highly
scalable and reproducible. With the combination of these basic logic blocks, more
sophisticated logic circuits, which require cascading of multiple stages of such logic gates
can be readily constructed. One interesting project that is worthy of further investigation
175
would be to build an integrated nanotube CPU. For the proof-of-concept purpose, I
propose a 2-bit CPU whose design is shown in Figure 8.5a. The instructions are designed
to be 7-bit and the format is Oper [2:0] Add1 [1:0] Add2 [1:0]. The first 3 bits of the
instruction control the operation that the CPU is going to execute, and the rest 4 bits
provide the address for two register files. The arithmatic logic unit (ALU) is designed to
be able to execute AND, OR, NOT, and ADD functions, and CPU also provide WRITE
functional to write data into the register file. The layout of the completed nanotube CPU
is shown in Figure 8.5b and the measurement is currently ongoing in our group.
Figure 8.5 Design of 2-bit nanotube CPU. (a) Datapath and instruction set of the 2-bit nanotube CPU. (b) Optical
microscope image showing the layout of the completed nanotube TFT CPU.
Moreover, owing to the inherent advantage of carbon nanotube thin-film, the
flexibility and transparency, and our solution-based separated nanotube deposition
technique, which allows low-temperature fabrication, this CPU can also be made on
flexible substrates such as polyethylene terephthalate (PET). One can envision that the
demonstration of a flexible nanotube CPU would be a truly remarkable milestone in
nanotube macroelectroncis, and can find tremendous applications in future lost-cost,
high-performance flexible thin-film electronics and display electronics.
a b
176
Chapter 8. References
1. Ryu, K.; Badmaev, A.; Gomez, L.; Ishikawa, F.; Lei, B.; Zhou, C. Synthesis of
Aligned Single-Walled Nanotubes Using Catalysts Defined by Nanosphere
Lithography. J. Am. Chem. Soc. 2007, 129, 10104–10105.
2. Tu, X.; Manohar, S.; Jagota, A.; Zheng, M. DNA Sequence Motifs for
Structure-Specific Recognition and Separation of Carbon Nanotubes. Nature 2009,
460, 250–253.
3. Zhang, J.; Wang, C.; Fu, Y.; Che, Y.; Zhou, C. Air-Stable Conversion of Separated
Carbon Nanotube Thin-Film Transistors from p-Type to n-Type Using Atomic
Layer Deposition of High- κ Oxide and Its Application in CMOS Logic Circuits.
ACS Nano 2011, 5, 3284–3292.
177
Bibliography
Ago, H.; Nakamura, K.; Ikeda, K.; Uehara, N.; Ishigami, N.; Tsuji, M. Aligned Growth of
Isolated Single-Walled Carbon Nanotubes Programmed by Atomic Arrangement of
Substrate Surface. Chem. Phys. Lett. 2005, 408, 433–438.
Amlani. I.; Lewis, J.; Lee, K.; Zhang, R.; Deng, J.; Wong, H.-S. P. First Demonstration of
AC Gain from a Single-Walled Carbon Nanotube Common-Source Amplifier. IEEE
International Electron Devices Meeting (IEDM), San Francisco, USA, 2006, pp 559–562.
Appenzeller, J.; Joselevich, E.; Honlein, W. Carbon Nanotubes for Data Processing.
Waser, R. (Ed.) Chapter 19 in Nanoelectronics and Information Technology. Wiley-VCH:
Weinheim, 2003.
Arnold, M. S.; Green, A. A.; Hulvat, J. F.; Stupp, S. I.; Hersam, M. C. Sorting Carbon
Nanotubes by Electronic Structure Using Density Differentiation. Nat. Nanotechnol.
2006, 1, 60–65.
Arnold, M. S.; Stupp, S. I.; Hersam, M. C. Enrichment of Single-Walled Carbon
Nanotubes by Diameter in Density Gradients. Nano Lett. 2005, 5, 713–718.
Artukovic, E.; Kaempgen, M.; Hecht, D. S.; Roth, S.; Gruner, G. Transparent and Flexible
Carbon Nanotube Transistors. Nano Lett. 2005, 5, 757–760.
Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon Nanotube
Transistors. Science 2001, 294, 1317–1320.
Bockrath, M.; Cobden, D.; McEuen, P.; Chopra, N.; Zettl, A.; Thess, A.; Smalley, R.
Single-Electron Transport in Ropes of Carbon Nanotubes. Science 1997, 275, 1922–1925.
Bradley, K.; Jhi, S.-H.; Collins, P. G.; Hone, J.; Cohen, M. L.; Louie, S. G.; Zettl, A. Is the
Intrinsic Thermoelectric Power of Carbon Nanotubes Positive? Phys. Rev. Lett. 2000, 85,
4361–4364.
Cao, Q.; Kim, H. S.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.; Alam,
M. A.; Rogers, J. A. Medium-Scale Carbon Nanotube Thin-Film Integrated Circuits on
Flexible Plastic Substrates. Nature 2008, 454, 495–500.
Cao, Q.; Rogers, J. A. Ultrathin Films of Single-Walled Carbon Nanotubes for
Electronics and Sensors: A Review of Fundamental and Applied Aspects. Adv. Mater.
2008, 21, 29–53.
178
Cao, Q.; Xia, M.; Kocabas, C.; Shim, M.; Rogers, J. A.; Rotkin, S. V. Gate Capacitance
Coupling of Singled-Walled Carbon Nanotube Thin-Film Transistors. Appl. Phys. Lett.
2007, 90, 023516-1–023516-4.
Chattopadhyay, D.; Galeska, I.; Papadimitrakopoulos, F. A Route for Bulk Separation of
Semiconducting from Metallic Single-Wall Carbon Nanotubes. J. Am. Chem. Soc. 2003,
125, 3370–3375.
Chen, Z.; Appenzeller, J.; Lin, Y.; Oakley, J. S.; Rinzler, A.G.; Tang, J.; Wind, S. J.;
Solomon, P. M.; Avouris, Ph. An Integrated Logic Circuit Assembled on a Single Carbon
Nanotube. Science 2006, 311, 1735.
Chen, R. J.; Bangsaruntip, S.; Drouvalakis, K. A.; Kam, N. W. S.; Shim, M; Li, Y.; Kim,
W.; Utz, P. J.; Dai, H. Noncovalent Functionalization of Carbon Nanotubes for Highly
Specific Electronic Biosensors. Proc. Nat. Acad. Sci. 2003, 100, 4984–4989.
Chimot, N.; Derycke, V.; Goffman, M. F.; Bourgoin, J. P.; Happy, H.; Dambrine, G.
Gigahertz Frequency Flexible Carbon Nanotube Transistors. Appl. Phys. Lett. 2007, 91,
153111.
Close, G. F.; Yasuda, S.; Paul, B.; Fujita, S.; Wong, H.-S. P. A 1 GHz Integrated Circuit
with Carbon Nanotube Interconnects and Silicon Transistors. Nano Lett. 2008, 8,
706–709
Collins, P. G.; Arnold, M. S.; Avouris, Ph. Engineering Carbon Nanotubes and Nanotube
Circuits Using Electrical Breakdown. Science 2001, 292, 706–709.
Collins, P. G.; Bradley, K.; Ishigami, M.; Zettl, A. Extreme Oxygen Sensitivity of
Electronic Properties of Carbon Nanotubes. Science 2000, 287, 1801–1804.
Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, Ph. Carbon Nanotube Inter- and
Intramolecular Logic Gates. Nano Lett. 2001, 1, 453–456.
Derycke, V.; Martel, R.; Appenzeller, J.; Avouris, Ph. Controlling Doping and Carrier
Injection in Carbon Nanotube Transistors. Appl. Phys. Lett. 2002, 80, 2773–2775.
Dimitrakopoulos, C. D.; Mascaro, D. J. Organic Thin-Film Transistors: A Review of.
Recent Advances. IBM J. Res. Dev. 2001, 45, 11–27.
Ding, L; Tselev, A.; Wang, J.; Yuan, D.; Chu H.; McNicholas, T. P.; Li, Y.; Liu, J.
Selective Growth of Well-Aligned Semiconducting Single-Walled Carbon Nanotubes.
Nano Lett. 2009, 9, 800–805.
179
Ding, L.; Wang, S.; Zhang, Z.; Zeng, Q.; Wang, Z.; Pei, T.; Yang, L.; Liang, X.; Shen, J.;
Chen, Q.; Cui, R.; Li, Y.; Peng L. Y-Contacted High-Performance n-Type Single-Walled
Carbon Nanotube Field-Effect Transistors - Scaling and Comparison with Sc-Contacted
Devices. Nano Lett. 2009, 9, 4209–4214.
Ding, L.; Yuan, D.; Liu, J. Growth of High-Density Parallel Arrays of Long
Single-Walled Carbon Nanotubes on Quartz Substrates. J. Am. Chem. Soc. 2008, 130,
5428–5429.
Dresselhaus, M. S.; Dresselhaus, G.; Avouris, Ph. (Eds.) Carbon Nanotubes – Synthesis,
Structure, Properties, and Applications. Springer: Berlin, 2001.
Durkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2004, 4, 35–39.
Engel, M.; Small, J. P.; Steiner, M.; Freitag, M.; Green, A. A.; Hersam, M. C.; Avouris,
Ph. Thin Film Nanotube Transistors Based on Self-Assembled, Aligned, Semiconducting
Carbon Nanotube Arrays. ACS Nano 2008, 2, 2445–2452.
Forrest, S. R. The Path to Ubiquitous and Low-Cost Organic Electronic Appliances on
Plastic. Nature 2004, 428, 911–918.
Gelinck, G. H.; Edzer, H.; Huitema, A.; Van Veenendaal, E.; Cantatore, E.;
Schrijnemakers, L.; Van Der Putten, J. B. P. H.; Geuns, T. C. T.; Beenhakkers, M.;
Giesbers, J. B.; Hiusman, B.-H.; Meijer, E. J.; Benito, E. M.; Touwslager, F. J.; Marsman,
A. W.; Van Rens, B. J. E.; De Leeuw, D. M. Flexible Active-Matrix Displays and Shift
Registers Based on Solution-Processed Organic Transistors. Nat. Mater. 2004, 3,
106–110.
Guo, J.; Hasan, S.; Javey, A.; Bosman, G..; Lundstrom, M. Assessment of
High-Frequency Performance Potential of Carbon Nanotube Transistors. IEEE Trans.
Nanotechnol. 2005, 4, 715–721.
Han, S.; Liu, X.; Zhou, C. Template-Free Directional Growth of Single-Walled Carbon
Nanotubes on a- and r-Plane Sapphire. J. Am. Chem. Soc. 2005, 127, 5294–5295.
Heaney, P. J.; Veblen, D. R. Observations of the α- β Phase Transition in Quartz: A
Review of Imaging and Diffraction Studies and Some New Results. American
Mineralogist 1991, 76, 1018–1032.
Hong, S. W.; Banks, T.; Rogers, J. A. Improved Density in Aligned Arrays of
Single-Walled Carbon Nanotubes by Sequential Chemical Vapor Deposition on Quartz.
Adv. Mater. 2010, 22, 1826–1830.
180
Hu, L.; Hecht, D. S.; Gruner, G. Percolation in Transparent and Conducting Carbon
Nanotube Networks. Nano Lett. 2004, 4, 2513–2517.
Iijima, S. Helical Microtubules of Graphitic Carbon. Nature 1991, 354, 56–58
International Technology Roadmap for Semiconductors 2009 Edition Executive Summary.
http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_ExecSum.pdf
Ishikawa, F.; Chang, H.; Ryu, K.; Chen, P.; Badmaev, A.; De Arco Gomez, L.; Shen, G.;
Zhou, C. Transparent Electronics Based on Transfer Printed Aligned Carbon Nanotubes
on Rigid and Flexible Substrates. ACS Nano 2009, 3, 73–79.
Ismach, A.; Kantorovich, D.; Joselevich, E. Carbon Nanotube Graphoepitaxy: Highly
Oriented Growth by Faceted Nanosteps. J. Am. Chem. Soc. 2005, 127, 11554–11555.
Ismach, A.; Segev, L.; Wachtel, E.; Joselevich, E. Atomic-Step-Templated Formation of
Single Wall Carbon Nanotube Patterns. Angew. Chem. Int. Ed. 2004, 43, 6140 –6143.
Javey, A.; Guo, J.; Farmer, D.; Wang, Q.; Wang, D.; Gordon, R.; Lundstrom, M.; Dai, H.
Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High- κ
Gate Dielectrics. Nano Lett. 2004, 4, 447–450.
Javey, A.; Guo, J.; Farmer, D.; Wang, Q.; Yenilmez, E.; Gordon, R.; Lundstrom, M.; Dai,
H. Self-Aligned Ballistic Molecular Transistors and Electrically Parallel Nanotube Arrays.
Nano Lett. 2004, 4, 1319–1322.
Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654–657.
Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon Nanotube Transistor Arrays for
Multistage Complementary Logic and Ring Oscillators. Nano Lett. 2002, 2, 929–932.
Jhi, S.-H.; Louie, S. G.; Cohen, M. L. Electronic Properties of Oxidized Carbon
Nanotubes. Phys. Rev. Lett. 2000, 85, 1710–1713.
Ju, S. H.; Yu, S. H.; Kwon, J. H.; Kim, H. D.; Kim, B. H.; Kim, S. C.; Chung, H. K.;
Weaver, M. S.; Lu, M. H.; Kwong, R. C.; Hack, M.; Brown, J. J. High Performance 2.2”
QCIF Full Color AMOLED Displays Based on Electrophosphorescence. SID Digest 2002,
37.3, 1096–1099.
Kang, S. J.; Kocabas, C.; Ozel, T.; Shim, M.; Pimparkar, N.; Alam, M. A.; Rotkin, S. V.;
Rogers, J. A. High-Performance Electronics Using Dense, Perfectly Aligned Arrays of
Single-Walled Carbon Nanotubes. Nat. Nanotechnol. 2007, 2, 230–236.
181
Kim, H.; Jeon, E.; Kim, J.; So, H.; Chang, H.; Lee, J.; Park, N. Air-Stable n-type
Operation of Gd-Contacted Carbon Nanotube Field Effect Transistors. Appl. Phys. Lett.
2008, 93, 123106-1–123106-3.
Klauk, H.; Halik, M.; Zschieschang, U.; Eder, F.; Rohde, D.; Schmid, G.; Dehm, C.
Flexible Organic Complementary Circuits. IEEE Trans. Electron Devices 2005, 52,
618–622.
Klinke, C.; Chen, J.; Afzali, A.; Avouris, Ph. Charge Transfer Induced Polarity Switching
in Carbon Nanotube Transistors. Nano Lett. 2005, 5, 555–558.
Kocabas, C.; Dunham, S.; Cao, Q.; Cimino, K.; Ho, X.; Kim, H.; Dawson, D.; Payne, J.;
Stuenkel, M.; Zhang, H.; Banks, T.; Feng, M.; Rotkin, S. V.; Rogers, J. A.
High-Frequency Performance of Submicrometer Transistors That Use Aligned Arrays of
Single-Walled Carbon Nanotubes. Nano Lett. 2009, 9, 1937–1943.
Kocabas, C.; Hur, S.; Gaur, A.; Meitl, M. A.; Shim, M.; Rogers, J. A. Guided Growth of
Large-Scale, Horizontally Aligned Arrays of Single-Walled Carbon Nanotubes and Their
Use in Thin-Film Transistors. Small 2005, 1, 1110–1116.
Kocabas, C.; Kim, H.-S.; Banks, T.; Rogers, J. A.; Pesetski, A. A.; Baumgardner, J. E.;
Krishnaswamy, S. V.; Zhang, H. Radio Frequency Analog Electronics Based on Carbon
Nanotube Transistors. Proc. Nat. Acad. Sci. 2008, 105, 1405–1409.
Kocabas, C.; Pimparkar, N.; Yesilyurt, O.; Alam, M. A.; Rogers, J. A. Experimental and
Theoretical Studies of Transport through Large Scale, Partially Aligned Arrays of
Single-Walled Carbon Nanotubes in Thin Film Type Transistors. Nano Lett. 2007, 7,
1195–1202.
Kong, J.; Franklin, N. R.; Zhou, C.; Chapline, M. G.; Peng, S.; Cho, K.; Dai, H. Nanotube
Molecular Wires as Chemical Sensors. Science 2000, 287, 622–625.
Kong, J.; Zhou, C.; Yenilmez, E.; Dai, H. Alkaline Metal-Doped n-type Semiconducting
Nanotubes as Quantum Dots. Appl. Phys. Lett. 2000, 77, 3977–3979.
Krupke, R.; Hennrich, F.; Löhneysen, H. V.; Kappes, M. M. Separation of Metallic from
Semiconducting Single-Walled Carbon Nanotubes. Science 2003, 301, 344.
LeMieux, M. C.; Roberts, M.; Barman, S.; Jin, Y. W.; Kim, J. M.; Bao, Z. Self-Sorted,
Aligned Nanotube Networks for Thin-Film Transistors. Science 2008, 321, 101–104.
Li, J.; Ye, Q.; Cassell, A.; Ng, H. T.; Stevens, R.; Han, J.; Meyyappan, M. Bottom-Up
Approach for Carbon Nanotube Interconnects. Appl. Phys. Lett. 2003, 82, 2491–2493.
182
Li, S.; Yu, Z.; Yen, S.; Tang, W.; Burke, P. Carbon Nanotube Transistor Operation at 2.6
GHz. Nano Lett. 2004, 4, 753–756.
Lin, Y.; Appenzeller, J.; Knoch, J. Avouris, P. High-Performance Carbon Nanotube
Field-Effect Transistor with Tunable Polarities. IEEE Trans. Nanotechnol. 2005, 4,
481–489.
Lin, A.; Patil, N.; Ryu, K.; Badmaev, A.; De Arco Gomez, L.; Zhou, C.; Mitra, S.; Wong,
H.-S. P. Threshold V oltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube
FETs. IEEE Trans. Nanotechnol. 2009, 8, 4–9.
Liu, X.; Han, S.; Zhou, C. Novel Nanotube-on-Insulator (NOI) Approach toward
Single-Walled Carbon Nanotube Devices. Nano Lett. 2006, 6, 34–39.
Liu, X.; Lee, C.; Han, J.; Zhou, C. Carbon Nanotube Field-Effect Inverters. Appl. Phys.
Lett. 2001, 79, 3329–3331.
Louarn, A. L.; Kapche, F.; Bethoux, J. M.; Happy, H.; Dambrine, G.; Deryche, V.;
Chenevier, P.; Izard, N.; Goffman, M. F.; Bourgoin, J. P. Intrinsic Current Gain Cutoff
Frequency of 30 GHz with Carbon Nanotube Transistors. Appl. Phys. Lett. 2007, 90,
233108-1–233108-3.
Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, P. Single- and Multi-Wall
Carbon Nanotube Field-Effect Transistors. Appl. Phys. Lett. 1998, 73, 2447–2449.
Moore, G. E. Cramming More Components onto Integrated Circuits. Electronics 1965, 38,
114–117.
Naeemi, A.; Meindl, J. Design and Performance Modeling for Single-Walled Carbon
Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated
Systems. IEEE Transactions on Electron Devices. 2007, 54, 26–37.
Nougaret, L.; Happy, H.; Dambrine, G.; Derycke, V.; Bourgoin, J. -P.; Green, A. A.;
Hersam, M. C. 80 GHz Field-Effect Transistors Produced Using High Purity
Semiconducting Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2009, 94,
243505-1–243505-3.
Odom, T.; Huang, J.; Kim, P. Lieber, C. Atomic Structure and Electronic Properties of
Single-Walled Carbon Nanotubes. Nature 1998, 391, 62–64.
Patil, N.; Deng, J.; Mitra, S.; Wong, H.-S. P. Circuit-Level Performance Benchmarking
and Scalability Analysis of Carbon Nanotube Transistor Circuits. IEEE Trans.
Nanotechnol. 2009, 8, 37–45.
183
Patil, N.; Lin, A.; Myers, E. R.; Ryu, K.; Badmaev, A.; Zhou, C.; Wong, H.-S. P.; Mitra, S.
Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes. IEEE
Trans. Nanotechnol. 2009, 8, 498–504.
Patil, N.; Lin, A.; Myers, E. R.; Wong, H.-S. P.; Mitra, S. Integrated Wafer-Scale Growth
and Transfer of Directional Carbon Nanotubes and Misaligned Carbon Nanotube Immune
Logic Structures. Proceedings of the 2008 VLSI Technology Symposium, Honolulu, USA,
2008, pp 205–206.
Pesetski, A. A.; Baumgardner, J. E.; Folk, E.; Przybysz, J. X.; Adam, J. D.; Zhang, H.
Carbon Nanotube Field-Effect Transistor Operation at Microwave Frequencies. Appl.
Phys. Lett. 2006, 88, 113103-1–113103-3.
Pesetski, A. A.; Baumgardner, J. E.; Krishnaswamy, S. V.; Zhang, H.; Adam, J. D.;
Kocabas, C.; Banks, T.; Rogers, J. A. A 500 MHz Carbon Nanotube Transistor Oscillator.
Appl. Phys. Lett. 2008, 93, 123506.
Pimparkar, N.; Cao, Q.; Kumar, S.; Murthy, J. Y.; Rogers, J. A.; Alam, M. A.
Current–Voltage Characteristics of Long-Channel Nanobundle Thin-Film Transistors: A
“Bottom-Up” Perspective. IEEE Electron Device Lett. 2007, 28, 157–160.
Pimparkar, N.; Kocabas, C.; Kang, S. J.; Rogers, J. A.; Alam, M. A. Limits of
Performance Gain of Aligned CNT Over Randomized Network: Theoretical Predictions
and Experimental Validation. IEEE Electron Device Lett. 2007, 28, 593–595.
Rosenblatt, S.; Yaish, Y.; Park, J.; Gore, J.; Sazonova, V.; McEuen, P. L. High
Performance Electrolyte Gated Carbon Nanotube Transistors. Nano Lett. 2002, 2,
869–872.
Ruoff, R. S.; Lorents, D. C. Mechanical and Thermal Properties of Carbon Nanotubes.
Carbon 1995, 33, 925–930.
Rutherglen, C.; Jain, D.; Burke, P. Nanotube Electronics for Radiofrequency Applications.
Nat. Nanotechnol. 2009, 4, 811–819.
Ryu, K.; Badmaev, A.; Gomez, L.; Ishikawa, F.; Lei, B.; Zhou, C. Synthesis of Aligned
Single-Walled Nanotubes Using Catalysts Defined by Nanosphere Lithography. J. Am.
Chem. Soc. 2007, 129, 10104–10105.
Ryu, K.; Badmaev, A.; Wang, C.; Lin, A.; Patil, N.; Gomez, L.; Kumar, A.; Mitra, S.;
Wong, H.-S. P.; Zhou, C. CMOS-Analogous Wafer-Scale Nanotube-on-Insulator
Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes.
Nano Lett. 2009, 9, 189–197.
184
Saito, R.; Dresselhaus, G.; Dresselhaus, M. S. Physical Properties of Carbon Nanotubes.
Imperial College Press: London, 1998.
Saito, R.; Fujita, M.; Dresselhaus, G.; Dresselhaus, M. S. Electronic Structure of Chiral
Graphene Tubules. Appl. Phys. Lett. 1992, 60, 2204–2206.
Shim, M.; Javey, A.; Kam, N. W. S.; Dai, H. Polymer Functionalization for Air-Stable
n-Type Carbon Nanotube Field-Effect Transistors. J. Am. Chem. Soc. 2001, 123,
11512–11513.
Snell, A. J.; Mackenzie, K. D.; Spear, W. E.; LeComber, P. G.; Hughes, A. J. Application
of Amorphous Silicon Field Effect Transistors in Addressable Liquid Crystal Display
Panels. Appl. Phys. A 1981, 24, 357–362.
Snow, E. S.; Campbell, P. M.; Ancona, M. G.; Novak, J. P. High-Mobility
Carbon-Nanotube Thin-Film Transistors on a Polymeric Substrate. Appl. Phys. Lett. 2005,
86, 033105-1–033105-3.
Snow, E. S.; Novak, J. P.; Campbell, P. M.; Park, D. Random Networks of Carbon
Nanotubes as an Electronic Material. Appl. Phys. Lett. 2003, 82, 2145–2147.
Street, R. A. (Ed.) Technology and Applications of Amorphous Silicon; Springer: Berlin,
2000.
Sumanasekera, G. U.; Adu, C. K. W.; Fang, S.; Eklund, P. C. Effects of Gas Adsorption
and Collisions on Electrical Transport in Single-Walled Carbon Nanotubes. Phys. Rev.
Lett. 2000, 85, 1096–1099.
Tans, S.; Verschueren, A.; Dekker, C. Room-Temperature Transistor Based on a Single
Carbon Nanotube. Nature 1998, 393, 49–52.
Treacy, M. M. J.; Ebbesen, T. W.; Gibson, J. M. Exceptionally High Young's Modulus
Observed for Individual Carbon Nanotubes. Nature 1996, 381, 678–680.
Tu, X.; Manohar, S.; Jagota, A.; Zheng, M. DNA Sequence Motifs for Structure-Specific
Recognition and Separation of Carbon Nanotubes. Nature 2009, 460, 250–253.
Ucjikoga, S. Low-Temperature Polycrystalline Silicon Thin-Film Transistor Technologies
for System-on-Glass Displays. MRS Bull. 2002, 27, 881–886.
Wang, C.; Badmaev, A.; Jooyaie, A.; Bao, M.; Wang, K. L.; Galatsis, K.; Zhou, C. Radio
Frequency and Linearity Performance of Transistors Using High-Purity Semiconducting
Carbon Nanotubes. ACS Nano 2011, 5, 4169–4176.
185
Wang, C.; Ryu, K.; Badmaev, A.; Patil, N.; Lin, A.; Mitra, S.; Wong, H.-S. P.; Zhou, C.
Device Study, Chemical Doping and Logic Circuits Based on Transferred Aligned
Single-Walled Carbon Nanotubes. Appl. Phys. Lett. 2008, 93, 033101-1–033101-3.
Wang, C.; Ryu, K.; Badmaev, A.; Zhang, J.; Zhou, C. Metal Contact Engineering and
Registration-Free Fabrication of CMOS Integrated Circuits using Aligned Carbon
Nanotubes. ACS Nano 2011, 5, 1147–1153.
Wang, C.; Ryu, K.; Gomez, L.; Badmaev, A.; Zhang, J.; Lin, X.; Che, Y.; Zhou, C.
Synthesis and Device Applications of High-Density Aligned Carbon Nanotubes Using
Low-Pressure Chemical Vapor Deposition and Stacked Multiple Transfer. Nano Research
2010, 3, 831–842.
Wang, C.; Zhang, J; Ryu, K.; Badmaev, A.; Gomez, L.; Zhou, C. Wafer-Scale Fabrication
of Separated Carbon Nanotube Thin-Film Transistors for Display Applications. Nano Lett.
2009, 9, 4285–4291.
Wang, C.; Zhang, J.; Zhou, C. Macroelectronic Integrated Circuits Using
High-Performance Separated Carbon Nanotube Thin-Film Transistors. ACS Nano 2010, 4,
7123–7132.
Wang, R.; Zhuge, J.; Huang, R.; Tian, Y .; Xiao, H.; Zhang, L.; Li, C.; Zhang, X.; Wang, Y .
Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation.
IEEE Trans. Electron Devices 2007, 54, 1288–1294.
Wang, S.; Zhang, Z.; Ding, L.; Liang, X.; Shen, J.; Xu, H.; Chen, Q.; Cui, R.; Li, Y .; Peng,
L. A Doping-Free Carbon Nanotube CMOS Inverter-Based Bipolar Diode and Ambipolar
Transistor. Adv. Mater. 2008, 20, 3258–3262.
Wildoer, J.; Venema, L.; Rinzler, A.; Smalley, R.; Dekker, C. Electronic Structure of
Atomically Resolved Carbon Nanotubes. Nature 1998, 391, 59–62.
Zhang, Z.; Liang, X.; Wang, S.; Yao, K.; Hu, Y .; Zhu, Y .; Chen, Q.; Zhou, W.; Li, Y .; Yao,
Y.; Zhang, J.; Peng, L. Doping-Free Fabrication of Carbon Nanotube Based Ballistic
CMOS Devices and Circuits. Nano Lett. 2007, 7, 3603–3607.
Zhang, D.; Ryu, K.; Liu, X.; Polikarpov, E.; Ly, J.; Tompson, M. E.; Zhou, C. Transparent,
Conductive, and Flexible Carbon Nanotube Films and Their Application in Organic
Light-Emitting Diodes. Nano Lett. 2006, 6, 1880–1886.
Zhang, J.; Wang, C.; Fu, Y .; Che, Y .; Zhou, C. Air-Stable Conversion of Separated Carbon
Nanotube Thin-Film Transistors from p-Type to n-Type Using Atomic Layer Deposition
of High- κ Oxide and Its Application in CMOS Logic Circuits. ACS Nano 2011, 5,
3284–3292.
186
Zhou, C.; Kong, J.; Dai, H. Electrical Measurements of Individual Semiconducting
Single-Walled Carbon Nanotubes of Various Diameters. Appl. Phys. Lett. 2000, 76,
1597–1599.
Zhou, X.; Park, J. Y.; Huang, S.; Liu, J.; McEuen, P. L. Band Structure, Phonon
Scattering, and the Performance Limit of Single-Walled Carbon Nanotube Transistors.
Phys. Rev. Lett. 2005, 95, 146805-1–146805-4.
Abstract (if available)
Abstract
In this dissertaion, I discuss the applications of carbon nanotubes in digital integrated circuits, display electronics, and radio-frequency electronics. Despite the fact that researchers have previously demonstrated excellent field-effect transistors and integrated circuits using an individual single-walled carbon nanotube, the real challenge is to integrate those devices, minimize the device-to-device performance variation, and to make the fabrication process scalable and compatible with industry standards. To overcome these challenges, instead of using individual carbon nanotube for electronic devices, developing assembly techniques that are capable of providing thin films of highly orderd and uniformly distributed carbon nanotubes is indispensable ❧ ❧ With demonstrating scalable, practical, and high performance carbon nanotube electronics as the major objective of my PhD research, I have developed two material platforms, both of which are capable of providing high-performance nanotube transistors at complete wafer-scale. The two material platforms are horizontally aligned carbon nanotubes and thin-films of preseparated high purity semiconducting carbon nanotubes. Besides scalable material platforms, many other essential technology components, including metallic nanotube removal, increasing nanotube density, and methods to obtain air-stable n-type nanotube transistors have also been demonstrated. On the basis of the above achievements, I have further demonstrated various kinds of electronic applications including integrated circuits, display electronics, and radio-frequency electronics. ❧ ❧ The dissertation is structured as follows. First, chapter 1 gives a brief introduction to the electronic properties of carbon nanotubes, which serves as the knowledge background for the following chapters of the dissertation. In chapters 2, 3, and 4, the works related to horizontally aligned carbon nanotubes grown using chemical vapor deposition are presented. The topics include wafer-scale processing of aligned carbon nanotube electronics, improving nanotube density for better device performance, and using metal contact engineering for air-stable n-type nanotube transistors and CMOS integrated circuits. Chapters 5, 6, and 7 discuss the work related to separated nanotube thin-films, where techniques for separated nanotube thin-film assembly, fabrication of high-performance separated nanotube thin-film transistors, and applications in integrated circuits, display electronics, and radio-frequency electronics are explored. Finally, a brief summary is drawn, and some future research directions are proposed in Chapter 8. ❧ ❧ This dissertation, through experimental demonstration, proofs the potential and feasibility of using carbon nanotubes for future beyond-silicon nanoelectronics and macroelectronics. ❧
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Wang, Chuan
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Carbon nanotube nanoelectronics and macroelectronics
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Viterbi School of Engineering
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Doctor of Philosophy
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Electrical Engineering
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06/16/2011
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