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Carbon material-based nanoelectronics
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Content
CARBON MATERIAL-BASED
NANOELECTRONICS
by
Yuchi Che
Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
DEPARTMENT OF ELECTRICAL ENGINEERING – ELECTROPHYSICS
March 2014
Copyright 2014 Yuchi Che
ii
Dedication
Dedicated to my family and my friends, for their support, understanding and love.
iii
Acknowledgements
It has been four and half years since I first started my PhD program in the fall of
2009. This experience is so important to me that I will take it as the most valuable memory
in my life. Here, I met a lot of people who may influence my whole life. When I look back
for the past few years, I realize that I have gained so much in both professional knowledge
and philosophy of life. I really appreciate this opportunity USC offers me and all the help
I received during the past several years.
First of all, I would like to thank my advisor Dr. Chongwu Zhou. As my advisor, he
provides me the best opportunity, resources, and freedom to explore in the scientific field.
He teaches me to be an independent thinker, a professional researcher, and an organized
instructor. I can never achieve this dissertation without his generous guidance and
continuous support.
I would also like to thank Professor Steve Cronin and Professor Wei Wu for serving
as my dissertation committee, for their valuable suggestions and help, as well as Professor
Mark Thompson and Professor Daniel Dapkus as my qualify committee.
And I also want to express my appreciation to my group members. I started my PhD
program with the help from Dr. Lewis Gomez, Dr. Chuan Wang, Dr. Alexander Badmaev,
and Dr. Jialu Zhang. I would like to thank them for their helpful guidance and help in my
junior years. I also want to thank the group member Dr. Fumiaki Ishikawa, Dr. Po-Chiang
iv
Chen, Dr. Akshay Kumar, Dr. Hsiao-Kang Chang, Dr. Anuj Madaria, Dr. Yi Zhang, Dr.
Bilu Liu, Dr. Gang Liu, Haitian Chen, Jia Liu, Maoqing Yao, Shelley Wang, Xue Lin, Zhen
Li, Jing Qiu, Jing Xu, Kuan-The Li, Luyao Zhang, Noppadol Aroonyadet, Jiepeng Rong,
Mingyuan Ge, Hui Gui, Pyojae Kim, Younghyun Na, Rebecca Lee, Ning Yang, Pattaramon
Vuttipittayamongkol, Liang Chen, Xin Fang, Ahmad Abbas, Dr. Yung-Chen Lin, Sen Cong,
Yu Cao, Anyi Zhang, Yuqiang Ma, Fanqi Wu, Xuan Cao, Chenfei Shen, Yihang Liu. I
enjoyed the past several years of my PhD study accompanied by all of you. Thank you for
encouraging me, helping me, and offering me this friendly and stimulating environment.
I also want to thank all of the collaborators, Professor Kang L. Wang, Professor
Kosmas Galatsis, Dr. Albortz Jooyaie from UCLA, Dr. Ming Zheng from National Institute
of Standards and Technology, Professor H.-S. Philip Wong from Stanford University, for
their paramount help in my research projects.
Last, and the most importantly, I would like to thank my parents, my family, my
boyfriend Wayne Chen, and all my friends for their unconditional support, encouragement,
love, and understanding. Thank you for always being here for me. I can never make this
achievement without any of you.
v
Table of Contents
Dedication ...................................................................................................................... ii
Acknowledgements ...................................................................................................... iii
List of Table ................................................................................................................. vii
List of Figures ............................................................................................................ viii
Abstract ....................................................................................................................... xiv
Chapter 1: Introduction .................................................................................................. 1
1.1 Introduction of graphene and carbon nanotube .................................................... 1
1.2 Structure and electric properties of graphene and nanotube ................................ 3
1.2.1 Structure and electric properties of graphene ................................................ 3
1.2.2 Structure and electric properties of nanotube ................................................ 7
1.3 Outline of the dissertation .................................................................................. 12
Chapter 1. References .............................................................................................. 17
Chapter 2: Selective Synthesis and Device Applications of Semiconducting Single-Walled
Carbon Nanotubes Using Isopropanol as Feedstock ................................................... 20
2.1 Introduction ........................................................................................................ 20
2.2 Aligned nanotube synthesis with IPA carbon feedstock .................................... 23
2.3 Electrical characterization and Raman spectrum ............................................... 26
2.4 Mass spectroscopy .............................................................................................. 31
2.5 Application: thin-film transistor ......................................................................... 36
2.5 Summary ............................................................................................................ 38
Chapter 2. References .............................................................................................. 40
Chapter 3: Self-Aligned Fabrication of Graphene RF Transistors with T-Shaped Gate44
3.1 Introduction ........................................................................................................ 44
3.2 Self-aligned T-gate fabrication ........................................................................... 46
3.3 DC characterization of T-gate graphene transistor............................................. 53
3.4 RF characterization of T-gate graphene transistor ............................................. 56
3.5 Summary ............................................................................................................ 58
Chapter 3. References .............................................................................................. 60
vi
Chapter 4. Self-Aligned T-gate High-Purity Semiconducting Carbon Nanotube RF
Transistors Operated in Quasi Ballistic Transport and Quantum Capacitance Regime62
4.1 Introduction ........................................................................................................ 62
4.2 Self-aligned T-gate separate nanotube transistor ............................................... 64
4.3 DC characterization of separate nanotube transistor .......................................... 68
4.4 RF characterization of separate nanotube transistor .......................................... 72
4.5 Linearity measurement of separate nanotube transistor ..................................... 76
4.6 Summary ............................................................................................................ 80
Chapter 4. References .............................................................................................. 81
Chapter 5: T-gate Aligned Nanotube Radio Frequency Transistors and Analog Circuits
realization ..................................................................................................................... 84
5.1 Introduction ........................................................................................................ 84
5.2 T-gate aligned nanotube transistor ..................................................................... 86
5.3 Linearity measurement of T-gate aligned nanotube transistor ........................... 91
5.4 T-gate aligned nanotube transistor-based mixer ................................................ 94
5.5 T-gate aligned nanotube transistor-based frequency doubler ............................ 96
5.6 Summary ............................................................................................................ 98
Chapter 5. References ............................................................................................ 100
Chapter 6: Conclusions and Future Directions .......................................................... 103
6.1 Conclusion ........................................................................................................ 103
6.2 Future directions ............................................................................................... 104
6.2.1 Future directions on radio frequency transistor optimization .................... 105
6.2.2 Future directions on radio frequency circuit configuration ....................... 113
6.2.3 Future directions on flexible radio frequency electronics ......................... 116
Chapter 6. References ............................................................................................ 119
Bibliography .............................................................................................................. 120
vii
List of Table
Table 1 Normalized value of relative intensity of possible species from mass spectrometry
of synthesis condition ...................................................................................... 36
viii
List of Figures
Figure 1. 1 Mother of graphitic forms. Graphene is a 2D building material of all other
dimensionalities. It can be wrapped up into 0D buckyballs, rolled into 1D nanotubes
or stacked into 3D graphite. ............................................................................... 1
Figure 1. 2 Graphene hexagonal lattice. (a) real space lattice of graphene, a1 and a2 are
primitive vectors, the dotted rhombus is the unite cell, (b) reciprocal lattice of
graphene, b1 and b2 are reciprocal vectors, K, M and Γ are high symmetric points.
............................................................................................................................ 4
Figure 1. 3 The energy dispersion relations for graphene are shown throughout the whole
region of the Brillouin zone. The inset shows the energy dispersion along the high
symmetry lines between the Γ, M, and K points. .............................................. 7
Figure 1. 4 Schematic diagram of graphene sheet. Structure of a carbon nanotube defined
with the chiral vector C (5,2), the translation vector T (4,3). ............................ 8
Figure 1. 5 Schematic diagrams of armchair, zigzag, and chiral nanotube. .................. 9
Figure 1. 6 The wave vector k for 1D carbon nanotube is shown in 2D Brillouin zone of
graphene as bold lines for (a) metallic and (b) semiconducting carbon nanotubes.
.......................................................................................................................... 11
Figure 1. 7 Schematics of (a) metallic and (b) semiconducting nanotube band structure.
.......................................................................................................................... 11
Figure 1. 8 Density of states for (9,0) metallic nanotube and (10,0) semiconducting
nanotube. .......................................................................................................... 12
Figure 1. 9 Electronic application of carbon nanotube in Nano/RF electronics (a), and
Macroelectronics (b). ....................................................................................... 14
Figure 1. 10 Outline of the dissertation ....................................................................... 15
ix
Figure 2. 1 Wafer-scale carbon nanotube synthesis using isopropanol and electrical
characteristics of the back-gated nanotube devices. (a) Photograph of a four-inch
wafer with aligned nanotubes grown. (b) An SEM image of aligned nanotubes
grown from isopropanol carbon feedstock. (c) Schematic and an SEM image of a
back-gated isopropanol-synthesized nanotube transistor. (d) ISD-VGS curves of back-
gate devices with isopropanol- and ethanol-synthesized nanotubes. (e) On/off ratio
distribution for devices with isopropanol- and ethanol-synthesized carbon
nanotubes. (f) Transfer and (g) Output characteristics of a representative back-gated
transistor with isopropanol-grown carbon nanotubes. ..................................... 25
Figure 2. 2 (a) An SEM image of a representative individual nanotube device with a 4 μm
channel length. (b) Transfer characteristics of 38 individual nanotube transistors,
with red traces representing the metallic nanotubes and blue traces representing the
semiconducting ones. The percentage of devices with on/off ratio higher than 10 is
around 90%. The nanotubes were grown from isopropanol CVD................... 29
Figure 2. 3 Micro-Raman characterization. (a) RBMs of isopropanol-synthesized
nanotubes and (b) RBMs of ethanol-synthesized nanotubes using a 532 nm laser.
(c) RBMs of isopropanol-synthesized nanotubes and (d) RBMs of ethanol-
synthesized nanotubes using a 633 nm laser.................................................... 30
Figure 2. 4 Mass spectra taken at the exhaust of the CVD system for ethanol (red trace)
and isopropanol (blue trace)............................................................................. 35
Figure 2. 5 TFTs using networks of isopropanol-synthesized nanotubes. (a) An SEM image
of a nanotube network. (b) An SEM image of a back-gated TFT. (c) Transfer and
(d) output characteristics of the device in (b). ................................................. 38
x
Figure 3. 1 Fabrication flow and schematic diagram of self-aligned transistors based on the
T-shaped gate stack. (a) Bilayer PMMA resist is exposed with high dose and
adjacent low dose and developed. (b) Al film is deposited at normal direction to the
substrate to form a T-shaped gate. (c) PMMA resist is removed and Al gate is
oxidized in air to form thin Al2O3 layer all around the gate, including the interface
with graphene. (d) Thin Pd layer is deposited to form self-aligned source and drain
contacts. Schematic image (e) and cross section SEM image (f) of a complete self-
aligned graphene transistor. ............................................................................. 49
Figure 3. 2 Electrical properties of the self-aligned graphene transistors. Photographs of 12
inch Si wafer with transferred large area CVD grown graphene (a) and 2 inch Si
wafer with fabricated graphene transistors (b). (c) Artificial color SEM image of a
self-aligned graphene transistor with the dual gate configuration, with the scale bar
being 10 µm. (d) Zoomed in SEM image of the transistor active area. (e) Two-
dimensional plot of a graphene transistor conductance as a function of the top gate
and back gate voltages. (f) Top gate voltage at the charge neutrality point versus
back gate voltage. The slope of the lines gives the ratio of top gate dielectric
capacitance to the bottom gate dielectric capacitance equal to 130. (g) Gate leakage
current of few graphene transistors, both source and drain are grounded. Dielectric
breakdown voltage is higher than 2.5 V. (h) Scaled resistance of a graphene
transistor versus top gate voltage. Black curve is the experimental result and red
curve is the model fitting. ................................................................................ 53
Figure 3. 3 DC output and transfer characteristics of two graphene transistors of 170 nm
(a, b and c) and 110 nm (d, e and f) channel length. Scaled transistor current (IDS/W)
vs drain voltage (VDS) (a) and gate voltage (b); and scaled transconductance (gm/W)
vs gate voltage (VG) (c) for the transistor with 170nm gate length. Scaled transistor
current (IDS/W) vs drain voltage (VDS) (a) and gate voltage (b); and scaled
transconductance (gm/W) vs gate voltage (VG) (c) for the transistor with 110nm gate
length. Back gate (substrate) voltage was kept constant and equal to 0 V for all
plots. ................................................................................................................. 55
Figure 3. 4 RF performance of graphene transistors. (a,b) Current gain (H21) before (black
line) and after(red line) the de-embedding procedure and maximum available gain
(MAG) (green line) for two graphene transistors with 170 nm channel length (a)
and 110 nm channel length (b). (c) Plot of fT, fmax, and intrinsic gate delay (gm/2πCg),
evaluated from DC measurements, versus gate bias (VG) for the 110 nm transistor.
.......................................................................................................................... 58
xi
Figure 4. 1 Fabrication of self-aligned T-gate transistors based on uniform separated
nanotube thin film on Si/SiO2 substrates. (a) SEM image of a separated nanotube
film. (b) Photograph of a 4 inch Si/SiO2 wafer with fabricated separated nanotube
devices. (c) Zoomed-in optical image of an RF transistor with 50 µm channel
width. (d) Schematic diagram of the self-aligned T-gate transistor with separated
nanotubes as the channel. (e) SEM image of the channel region of a transistor. (f)
Perspective-view SEM image of a T-shaped gate structure. ........................... 68
Figure 4. 2 DC characteristics of self-aligned nanotube transistors. (a) Transfer
characteristics (IDS-V GS) with nanotube device of back-gate and top-gate control.
(b) Transfer characteristics (IDS-VGS) of the nanotube transistor with various VDS.
(c) Output (IDS-VDS) characteristics of the nanotube transistor with various VGS. (d)
gm-V GS characteristics measurement at various VDS. (e) gm-V GS characteristics
measured with devices of channel length ranged from 140 nm to 300 nm. (f) gm-
V GS characteristics measured with devices of channel length ranged from 400 nm
to 600 nm. (g) Conductance versus V GS under VDS = 0.2V of single nanotube self-
aligned T-gate device. ...................................................................................... 72
Figure 4. 3 RF characteristics of a separated nanotube RF transistor on Si/SiO 2 substrate
(a-d) and a similar transistor on quartz substrate. (a) Smith chart of as-measured S
parameters of the separated nanotube RF transistor on Si/SiO2 (L = 140 nm, W =
50 µm). (b) As-measured S parameters of the separated nanotube RF transistor. (c)
Extrinsic and intrinsic current-gain H21 and maximum available gain Gmax of the
device on Si/SiO2 substrate derived from the measured S parameters from 50 MHz
to 10 GHz (d) Transconductance and intrinsic cut-off frequency versus gate bias.
(e) Extrinsic and intrinsic current gain H21 and maximum available gain Gmax of the
device on quartz substrate derived from the measured S parameters from 50 MHz
to 10 GHz. (f) fmax and ft of different T-gate transistors on quartz substrate. .. 75
Figure 4. 4 Linearity characteristics of T-gate self-aligned separated nanotube RF
transistors. (a) Schematic of load and source pull setup system to capture the
nonlinearity for the separated nanotube RF transistor. (b, c) Source impedance at
the source tuner for 8 dB of power gain at 200 MHz (b) and 500 MHz (c). (d, e) 1-
dB compression point plots at 200 MHz (d) and 500 MHz (e). ...................... 79
xii
Figure 5. 1 (a) SEM image of aligned carbon nanotubes on a quartz substrate (Density: 5
SWNTs/µm). (b) Schematic of a self-aligned T-gate aligned nanotube RF
transistor. (c) Top-view SEM image of T-shape gate transistor (T-gate cap: 150 nm,
base: ~100 nm). (d) Optical image of T-gate aligned nanotube RF transistor with
channel width of 80 µm. (e) Transfer characteristics of T-gate aligned nanotube RF
transistor. (f) Scaled transconductance (gm/W) versus gate voltage (Vgs) curve for
aligned nanotube RF transistor. ....................................................................... 89
Figure 5. 2 RF performance of self-aligned T-gate aligned nanotube transistor. (a) Current
gain (H21) before (black curve) and after (red curve) the de-embedding procedure.
(b) Extrinsic power gain (MAG) curve. (c,d) Extrinsic (c) and intrinsic (d) cut-off
frequency versus channel length from previous publication and our work. .... 91
Figure 5. 3 Linearity performance of self-aligned T-gate aligned nanotube transistor. (a)
Schematic of single/two tone test for aligned nanotube transistor. (b) Output power
of the fundamental versus input power. (c,d) Output power of the fundamental and
third-order intermodulation as a function of the input power measured in the
frequency region of 3 GHz (c) and 5 GHz (d). ................................................ 93
Figure 5. 4 Mixer application of self-aligned T-gate aligned nanotube transistor. (a) Output
spectrum for an aligned nanotube mixer, which shows the first, second, and third
order mixing products with a high conversion gain of -24.5 dB at LO power of -3.5
dBm. (b) Conversion gain versus gate voltage for aligned nanotube mixer. (c)
Conversion gain versus frequency for aligned nanotube mixer. ...................... 96
Figure 5. 5 Frequency doubler application of self-aligned T-gate aligned nanotube
transistor. (a) IDS-V GS curve of an ambipolar aligned nanotube transistor. (b) Circuit
schematic of an aligned nanotube frequency doubler with measurement setup using
an oscilloscope. (c,d) Output waveforms of frequency doubler in linear
amplification region and doubler region with sinusoidal wave with input Vpp = 450
mV at frequency of 10 KHz (c) and input Vpp = 500 mV at frequency of 50 KHz
(f). (e) Schematic of frequency doubler with measurement setup using a spectrum
analyzer. (f,g) Output spectrum of frequency doubler with a 100 MHz input signal
with power level of 0 dBm (f) and a 500 MHz input signal with power level of 5
dBm (g). ........................................................................................................... 98
xiii
Figure 6. 1 SEM of aluminum gate (a) and ALD with Ti/Au gate (b) ...................... 106
Figure 6. 2 Radio frequency performance of carbon nanotube transistor with aluminum
gate (a) and Ti/Au gate (b). ............................................................................ 107
Figure 6. 3 (a) SEM of large diameter separated nanotube thin film. (b) Optical absorption
spectra of large diameter separated nanotubes. .............................................. 108
Figure 6. 4 Transfer characteristics of self-aligned T-gate transistor made of smaller
diameter (~1.4 nm) and larger diameter (~1.6 nm)........................................ 109
Figure 6. 5 Transconductance versus gate voltgae of self-aligned T-gate transistor made of
smaller diameter (~1.4 nm) and larger diameter (~1.6 nm). .......................... 109
Figure 6. 6 Output characteristics of self-aligned T-gate transistor made of smaller
diameter (~1.4 nm) and larger diameter (~1.6 nm)........................................ 110
Figure 6. 7 Maximum available gain of large diameter carbon nanotube RF transistors111
Figure 6. 8 Statistic study of power gain cut-off frequency of small diameter and large
diameter carbon nanotube transistors............................................................. 112
Figure 6. 9 Low noise amplifier schematic ................................................................ 114
Figure 6. 10 Schematic of noise figure measurement by noise figure meter/analyzer115
Figure 6. 11 Schematic of T-gate design and process flow chart for flexile thin film
transistors ....................................................................................................... 117
xiv
Abstract
In this dissertation, I discuss the solution for the major challenge for carbon
nanotube-based nanoelectronics, and explore the radio frequency application of carbon-
based material including graphene and nanotube.
Chapter 1 is a brief introduction of carbon nanotube and graphene in electronics
field as the foundation for the whole dissertation. Chapter 2 to 5 report the work I have
finished in the past four and half years. Chapter 6 discusses the future directions of carbon-
based nanoelectronics.
Chapter 2 reports a method we developed to obtain predominantly semiconducting
nanotubes from direct CVD growth. By using isopropanol as the carbon feedstock,
semiconducting nanotube purity of above 90% is achieved, which is unambiguously
confirmed by both electrical and micro-Raman measurements. Mass spectrometric study
was performed to elucidate the underlying chemical mechanism. Furthermore, high
performance thin-film transistors with an on/off ratio above 10
4
and mobility up to 116
cm
2
/V∙s have been achieved using the isopropanol-synthesized nanotube networks grown
on silicon substrate. The method reported in this contribution is easy to operate and the
results are highly reproducible. Therefore, such semiconducting predominated single-
walled carbon nanotubes could serve as an important building block for future practical
and scalable carbon nanotube electronics.
xv
Chapter 3 presents a scalable method for fabrication of self-aligned graphene
transistors by defining T-shaped gate on top of graphene, followed by self-aligned source
and drain formation by depositing Pd with the T-gate as a shadow mask. This transistor
design provides significant advantages such as elimination of misalignment, reduction of
access resistance by minimizing ungated graphene, and reduced gate charging resistance.
To achieve high yield scalable fabrication, we have combined the use of large-area
graphene synthesis by chemical vapor deposition, wafer scale transfer, and e-beam
lithography to deposit T-shaped top gates. The fabricated transistors with gate lengths in
the range of 110 to 170 nm exhibited excellent performance with peak current density of
1.3 mA/µm and peak transconductance of 0.5 mS/µm, which is one of the highest
transconductance values reported. In addition, the T-gate design enabled us to achieve
graphene transistors with extrinsic current-gain cut-off frequency of 23 GHz and maximum
oscillation frequency of 10 GHz. These results represent important steps toward self-
aligned design of graphene transistors for various applications.
In Chapter 4, we introduce the self-aligned fabrication method for carbon nanotube
RF transistors. In this way, the channel length can be scaled down to 140 nm which enables
quasi ballistic transport, and the gate dielectric is reduced to 2-3 nm aluminum oxide,
leading to quasi quantum capacitance operation. A current-gain cut-off frequency (ft) up to
22 GHz and a maximum oscillation frequency (fmax) of 10 GHz are demonstrated.
xvi
Furthermore, the linearity properties of nanotube transistors are characterized by using the
1-dB compression point measurement with positive power gain for the first time, to our
knowledge. Our work reveals that the importance and potential of separated
semiconducting nanotubes for various RF applications.
Chapter 5 discusses about the aligned nanotube transistor study and further explores
radio frequency circuit application of aligned nanotube array transistors. We constructed
T-gate aligned nanotube array RF transistors with the extrinsic current-gain cut-off
frequency of 25 GHz as the best on-chip performance for nanotube RF transistors reported
to date. Correspondingly, the intrinsic current-gain cut-off frequency of 102 GHz was
achieved after de-embedding, which is among the highest value for nanotube-based RF
transistors. Furthermore, we studied the linearity properties of aligned nanotube transistors
through single-tone (P1dB) and two-tone (IP3) measurements with direct 50 Ω termination
up to 8 GHz. Armed with the excellent extrinsic RF performance, we configured nanotube-
based circuits including a mixer and a frequency doubler, operated in the gigahertz
frequency regime. Our work confirms the great potential of carbon nanotubes for radio
frequency applications, and the self-aligned T-gate RF transistor design may become a
building block for future nanotube-based RF transistors and circuits.
In Chapter 6, future direction on carbon-based material nanoelectronincs is briefly
discussed. In the field of radio frequency (RF) electronics, RF device design can be further
xvii
optimized for better performance. Noise figure is another important figure of merit for RF
transistors and circuits beside linearity. With the excellent transistor performance achieved
in previous work, I propose to further realize amplifier circuit with positive gain such as
low noise amplifier (LNA) and power amplifier (PA). Through combing the CMOS
technology platform with the carbon-based radio frequency transistors, we can study the
CMOS-Carbon hybrid radio frequency circuit to fulfill the advantage of the low cost for
traditional CMOS technology and the high performance provided by carbon-based
nanomaterial. It will be meaningful to further analyze the noise figure of the carbon
nanotube-based as the important parameter of nanotube RF transistors. As an interesting
topic, flexible analog electronics based on nanotube material based on T-gate design may
have the potential in higher performance in flexible electronics field.
In summary, this dissertation starts from the material synthesis and preparation to
the device and circuit application of carbon-based material. The electronic application
shows the great potential of carbon-based material in the nanoelectronics and radio
frequency electronics. It can be predicted that carbon-based material nanoelectronics is
very promising for beyond silicon electronics due to the unique electronic properties.
1
Chapter 1: Introduction
1.1 Introduction of graphene and carbon nanotube
Graphitic materials have different kinds of dimensions (Figure 1.1). Starting with
flat monolayer of carbon atoms, it forms graphene sheet with 2D honeycomb lattice.
Monolayer Graphene sheets can be rolled up into seamless, hollow cylinders, as 1D
nanotube structure. Moreover, it can also be wrapped up into 0D fullerenes or stacked into
3D graphite.
1
Figure 1. 1 Mother of graphitic forms. Graphene is a 2D building material of all other
dimensionalities. It can be wrapped up into 0D buckyballs, rolled into 1D nanotubes or
stacked into 3D graphite.
2
Graphene as the atomic monolayer material was first isolated from bulk graphite
by Novoselov, Geim and co-workers, and can be obtained on top of non-crystalline
substrates. Recently, graphene becomes a rising star in physics and electronics research
community. As one-atomic thick two dimensional sheets, graphene exhibits exceptional
electronic properties. The charge carriers of graphene also have long mean free path with
scattering so that graphene is predicted to have extraordinary charger carrier mobility (10
6
cm
2
V
-1
S
-1
).
1
Moreover, graphene has special properties such as bipolar electric filed effect,
anomalous quantum hall effect, and linear energy dispersion relation at low energy. Due to
its unique structure and electric properties, graphene has generated enormous interest in
electronics application research filed.
Carbon nanotubes were first discovered by Sumio Iijima at NEC Laboratory in
Japan in 1991.
2
Due to unique mechanical and electronic properties, carbon nanotubes have
attracted tremendous attentions in science study for past 20 years and show great potential
in next generation electronic application as a promising candidate compared with other
novel material.
3, 4
As one dimension material, carbon nanotubes have the advantage in
nanotechnology field because the diameter of carbon nanotube is around a few nanometers.
In terms of electronics properties, nanotubes can be either metallic or semiconducting,
depending on the diameter and orientation of hexagons (chiral vector), which makes carbon
nanotube-based integrated circuit possible. Due to the long mean free path (in the order of
3
a few hundred nanometers), carbon nanotubes can offer scatter-free ballistic transport for
short channel devices.
5
Moreover, metallic carbon nanotubes have high electric current
density of 4× 10
10
A/cm
2
), which is 1000 times better than other metals used for
interconnections such as copper, overcoming the electromigration problem through strong
C-C bond. On the other hand, carbon nanotubes own ultra-high thermal conductivity,
Young’s Modulus (5 TPa), and other excellent mechanical properties. Based on the
extraordinary properties, carbon nanotubes have been studied and applied extensively in
material, biology, and physics research filed. Among these, the unique electric properties
make carbon nanotubes a promising building block in further development of nano-scale
semiconducting device and circuit.
1.2 Structure and electric properties of graphene and nanotube
1.2.1 Structure and electric properties of graphene
Graphene is a monolayer of graphite with hexagonal lattice. The unit cell and the
Brillouin zone of graphene are shown in figure 1.2a and 1.2b.
4
Figure 1. 2 Graphene hexagonal lattice. (a) real space lattice of graphene, a1 and a2 are
primitive vectors, the dotted rhombus is the unite cell, (b) reciprocal lattice of graphene,
b1 and b2 are reciprocal vectors, K, M and Γ are high symmetric points.
In real space, the distance between two carbon atoms is 0.142 nm. The primitive
vector of unit cell is
1
a and
2
a , which can be expressed as following:
12
4
, 3 ,
3
b b a
a
)
2
,
2
3
( ),
2
,
2
3
(
2 1
a
a a
a
a a
Where |
1
a | = |
2
a |= 3a = 0.246 nm.
Correspondingly, in reciprocal space, the unit vector is
1
b and
2
b , which can be
written as
)
2
,
3
2
( ),
2
,
3
2
(
2 1
a a
b
a a
b
Where |
1
b | = |
2
b | =
4
3a
. As shown in Figure 1., the direction of reciprocal unit
vectors
1
b and
2
b is rotated by 90 ° from the real space unit vectors
1
a and
2
a .
5
The first Brillouin zone is selected as a basic hexagon, where the three high
symmetric points Γ (center), Κ (the corner of hexagon) and Μ (the edge center) are defined.
In this way, the energy dispersion relation can be derived from these three points.
6
Each carbon atoms has three σ bonds which hybridize in a sp
2
configuration, while
the other spz orbital, which is perpendicular to the graphene plane, makes π covalent bonds.
And the π energy bonds are the most important for determining the solid state properties
of graphene.
In the tight bonding method, the Hermitian matrix H and the overlap integral matrix
S need to be solved. Because graphene lattice has two inequivalent carbon atoms at A and
B as shown in Figure 1.a, two Bloch functions, constructed from atomic orbital for carbon
atoms at A and B, provide the basis functions for graphene. In this way, the Hermitian
matrix H and the overlap integral matrix S can be deduced as following to find the 2D
energy dispersion relation of graphene.
p
p
tf
tf
H
2
*
2
(k) -
(k) -
and
1 (k)
(k) 1
*
sf
sf
S
where
p 2
is the site energy of the 2p atomic orbital. By soling the secular equation
det [H-ES] = 0, eigenvalues ) (k E and () fk can be obtained as following
)
2
k
( cos 2 (k)
y 3 2 / - 3 /
a
e e f
a ik a ik
x x
,
(k) 1
(k)
(k)
2p
2
s
t
E
D g
Where
C C
a a a a
- 2 1
3 , t is the transfer integral, s is the overlap of the
6
electronic wave function on adjacent sites, the + signs in the numerator and denominator
go together giving the bonding π energy band, and likewise for the – signs.
The energy dispersion relation of graphene throughout the Brillouin zone are plotted in
Figure 1.3, while the inset shows the energy dispersion relations along the high symmetry
axes along the perimeter of the triangle Γ M K. We set the parameters t = 3.013 eV, s =
0.129 and ε2p = 0. The upper part of the energy dispersion curves describes the anti-bonding
π* band and the lower half is the π energy band. These two bands are degenerate at K points,
where the density of states is zero. As a result, graphene is zero bandgap material. In low
energy, the energy dispersion relation is linear an can be expressed as
( ) | |
F
E k k
( ) | |
F
E k k , where
F
is around 10
6
m/s as the Fermi velocity.
7
Figure 1. 3 The energy dispersion relations for graphene are shown throughout the whole
region of the Brillouin zone. The inset shows the energy dispersion along the high
symmetry lines between the Γ, M, and K points.
1.2.2 Structure and electric properties of nanotube
Carbon nanotube is considered to be formed by rolling up a sheet of graphene along
a chiral vector
h
C . As discussed in the previous section about graphene structure, there are
two basis vectors
1
a and
2
a . In this way, the chiral vector
h
C can be expressed as
12
na ma , shown figure 1.4.
8
Figure 1. 4 Schematic diagram of graphene sheet. Structure of a carbon nanotube defined
with the chiral vector C (5,2), the translation vector T (4,3).
Carbon nanotubes can be divided into two categories, achiral and chiral.
7
Achiral
carbon nanotubes include armchair and zigzag nanotubes based on the shape of the cross
sectional ring. For armchair nanotubes, m equals to n and chiral angle is 30 °. For zigzag
nanotubes, either m or n is 0 and chiral angle is 0 °. All armchair nanotubes (n,n) are
metallic. For zigzag nanotubes, they are metallic only when n is the integer multiple of
three, the rest of zigzag nanotubes are semiconducting. Similarly, chiral nanotubes of which
n-m is the integer multiple of three are metallic, and the rest of chiral nanotube are
semiconducting. Based on the chiral vectors, we can deduce the diameter of carbon
nanotube (n,m) as following:
22
||
h
t
C a
d n m nm
.
9
Figure 1. 5 Schematic diagrams of armchair, zigzag, and chiral nanotube.
Based on the previous discussion about the energy dispersion relation of graphene
sheet, band structure of nanotubes can be further derived as follow.
When rolling up the graphene sheet to form a nanotube, due to the periodic
boundary condition imposed in the circumferential direction, the electron wavevector
along that direction is quantized. Figure 1.6 shows that the wave vector (K1) along the
circumferential direction is quantized owning to the periodic boundary conditions, while
the wave vector (K2) along the nanotube is continuous for nanotube with infinite length.
Thus, with the energy dispersion relation as discussed before, the 1D energy dispersion
relation of carbon nanotube is derived as
2
1
2
( ) ( )
||
K
E k E k K
K
, ( 1,..., 1, N and k
TT
)
10
Here T is the magnitude of the translation vector T (
33
ht
RR
Cd
T
dd
), N is the
number of hexagons of the graphene honeycomb lattice which lie with the unite cell
(
22
2( )
R
n m nm
N
d
), k is the 1D wave vector along the nanotube axis. Due to the
quantization, only a certain set of k states of the planar graphene sheet is allowed as shown
by the solid lines in figure 1.6. Based on the chirality of the nanotube (n,m), if the line
section cross through the K point of the graphene sheet 2D Brillouin zone, the 1D energy
band of the nanotube has zero bandgap and nonzero density of states at the Fermi level. It
behaves like 1D metal with 2 linear dispersing bands as shown in figure 1.7a. Otherwise,
the nanotube is semiconducting with finite energy bandgap between the valence and
conduction bands as shown in figure 1.7b.
Another condition for metallic nanotube is that the ratio of the length of YK to the
length of
1
K is an integer. In this case, one of lines cross through K point, because YK can
be expressed as
1
2
3
nm
YK K
Above all, the general rule metallic nanotubes is that (2n+m) or (n-m) is a multiple
of 3. With this rule of thumb, it can be inferred that one third of nanotubes are metallic and
the rest are semiconducting. The bandgap of the nanotube can be determined as a function
of diameter
4
3
F
g
t
E
d
.
11
Figure 1. 6 The wave vector k for 1D carbon nanotube is shown in 2D Brillouin zone of
graphene as bold lines for (a) metallic and (b) semiconducting carbon nanotubes.
Figure 1. 7 Schematics of (a) metallic and (b) semiconducting nanotube band structure.
Furthermore, the 1D density of state (DOS in unites of states/C-atom/eV of the
nanotube can be expressed as:
1
1
( ) ( ( ) )
() 2
N
T
D E E k E dE
dE k N
dk
12
As presented in figure 1.8a and b, semiconducting nanotube (10,0) and metallic
nanotube (9,0) have different DOS distribution. For semiconducting nanotube, the DOS is
zero near the Fermi level at E=0, while for metallic nanotube the DOS is nonzero. The
kinks in DOS of nanotube are characteristics of 1D structure, called Van Hove singularities,
which is very significant for the sold state properties of nanotube.
Figure 1. 8 Density of states for (9,0) metallic nanotube and (10,0) semiconducting
nanotube.
1.3 Outline of the dissertation
In the nanoelectronics field, carbon nanotubes (CNT) have advantages owing to
their one dimensional geometry. The inherently small geometric size of single-wall carbon
nanotubes (SWCNTs) of ~ 1 nm leads to the optimization of the coupling between the gate
13
and the channel of a transistor and provides great potential in the application of nano-scale
devices and circuits.
3, 4, 8-21
The chemical bonds of all the C atoms in carbon nanotube are
satisfied without dangling bonds, so a high dielectric constant and crystalline insulator can
be applied in carbon nanotube-based devices.
22
In the application of nanoelectronics, semiconducting SWCNTs are usually used as the
channel material. Due to the one-dimensional transport and long mean free path (in the
order of a few hundred nanometers), carbon nanotubes can offer scattering-free ballistic
transport and enable the possibility of ballistic transport for short channel devices, resulting
in low power dissipation.
5, 22, 23
The good thermal conductivity of SWCNTs also brings
benefits for reducing power consumption in devices and circuits. All these unique
geometrical, electronic, thermal, chemical and mechanical properties make carbon
nanotube field effect transistor (CNTFET) very competitive in future nanoelectronics.
24-26
In the application of macroelectronics, nanotubes have many advantages as well, transistors
based on CNT random network exhibit superior properties in terms of their electrical
performance, reliability, flexibility, transparency, and printability
27-36
, so multifunctional
and multipurpose transistors and circuits become feasible.
14
Figure 1. 9 Electronic application of carbon nanotube in Nano/RF electronics (a), and
Macroelectronics (b).
The outline of my Ph.D. thesis is summarized in Figure 1.10. In this dissertation, I
will discuss the material preparation of carbon nanotube and further extend to the
application in nanoelectronics and radio frequency electronics.
Nano/RF
electronics
CPU Memory
RF Electronics Computer Display Electronics
Macro-
electronics
Touch Screen
Printed Electroncis
Flexible Electronics
a b
15
Figure 1. 10 Outline of the dissertation
Chapter 1 is a brief introduction of carbon nanotube and graphene in electronics
field as the foundation for the whole dissertation. Chapter 2 discusses the development of
high-purity semiconducting nanotube synthesis and the application on the thin film
transistor. Chapter 3 brings up the self-aligned T-gate design on carbon-based material
(graphene and carbon nanotube) radio frequency transistors. Chapter 4 and 5 focus on the
radio frequency electronics application of carbon nanotube (separated nanotube thin film
and aligned nanotube array) with the self-aligned T-gate design. The important figure of
merit in analog electronics, linearity of CNTFET is studied and analyzed in Chapter 4, as
Digital circuit
Analog circuit
Selective synthesis
Self-aligned T-gate
Thin-film-transistor
Linearity
Circuit application
Aligned Nanotubes
Separated Nanotube
Thin-Film
2 µm
Graphene
16
an advantage of carbon nanotube-based RF electronics. In chapter 5, significant carbon
nanotube-based analog circuits including mixer, amplifier, and frequency doublers were
further configured and characterized, showing great potential of carbon nanotube RF
circuits and systems. Finally, chapter 6 summarizes the work in carbon nanotube-based
nanoelectronics and RF electronics and discusses about the future direction including
device optimization, hybrid circuit, and flexible RF electronics on the carbon nanotube-
based electronics field.
17
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20
Chapter 2: Selective Synthesis and Device Applications of
Semiconducting Single-Walled Carbon Nanotubes Using
Isopropanol as Feedstock
2.1 Introduction
The outstanding potential of using carbon nanotubes for beyond-silicon
nanoelectronics stems from the fact that they offer a combination of small size, high
mobility, ballistic transport, and small intrinsic capacitance.
1-9
However, one of the major
challenges remain to be solved is how to make the nanotube electronics practical and
scalable. To address this issue, the guided chemical vapor deposition (CVD) growth of
horizontally aligned single-walled carbon nanotubes on certain crystalline substrates like
quartz and sapphire developed by many groups including our own
10-12
is proven to be a
great platform for wafer-scale integration of aligned nanotubes into circuits and functional
electronic systems.
9, 13, 14
Due to significant effort devoted to the synthesis of single-walled
carbon nanotubes, high density and good alignment have been achieved in previous
studies,
15-17
which have great advantage on the device performance of nanotube electronics.
However, the co-existence of metallic and semiconducting nanotubes still remains to be a
major problem, which hampers further development of nanoelectronics based on carbon
nanotubes. To solve this problem, selective elimination using electrical breakdown is
21
widely used for device study.
18
However, this technique hurts the conductivity of nanotubes
and is hardly scalable to systems containing millions or billions of transistors. Meanwhile,
methods of separating metallic nanotubes from semiconducting ones have been studied by
using various approaches.
19-22
However, chemical separation treatment induces defects in
nanotubes and leads to contamination, which degrades the performance of nanotubes in
terms of mobility. Therefore, it is very desirable to achieve controlled growth of
semiconducting nanotubes through CVD directly.
Previously, semiconducting enriched nanotubes have been synthesized using
techniques such as gas phase
23
and supported catalyst CVD.
24-26
However, those nanotubes
typically come as bundles and consequently cannot be easily used for nanoelectronic
devices and circuits, which would prefer highly aligned nanotube distributed over
insulating substrates. For this goal, several groups have reported the synthesis of
predominant semiconducting nanotubes on flat substrates, including approaches using
ethanol/methanol mixture carbon feedstocks,
27
UV irradiation during CVD,
28
and plasma-
enhanced CVD,
29-31
respectively. Nevertheless, some of those techniques require
complicated processes and the introduction of UV light or plasma may decrease nanotube
density. Moreover, the underlying mechanism for the selective growth of semiconducting
single-walled carbon nanotubes is not well understood and some research groups have
devoted efforts in this matter of hot debates.
32-35
Therefore, more research is needed to
22
develop a simple and reliable approach for the selective synthesis of semiconducting
nanotubes and to advance scientific understanding of the mechanism behind. Here, we
report a facile, robust and high effective approach with the use of isopropanol (isopropanol
alcohol or IPA) to synthesize predominantly semiconducting nanotubes from CVD directly.
Using isopropanol as the feedstock, arrays of aligned semiconducting carbon nanotubes
have been grown on quartz substrates up to four inch wafers. The percentage of
semiconducting nanotubes is confirmed to be 97.6% for our best sample and about 90%
using both individual nanotube electrical measurements and micro-Raman spectroscopy.
Furthermore, mass spectrometry was used to elucidate the underlying mechanism, which
suggests that the presence of right amount of water species from isopropanol
decomposition played a key role for the selective growth of semiconducting single-walled
nanotubes. It should be noted that we also performed nanotube synthesis on silicon
substrates using our isopropanol-based CVD process. As an example of application, we
have fabricated thin-film transistors (TFTs) from the as-grown isopropanol-synthesized
nanotube networks on silicon substrate and an on/off ratio over 10
4
and mobility up to 116
cm
2
/V∙s have been achieved, which represents one of the best reported performances for
TFTs up to date. The method reported here is facile, robust, and the results are highly
reproducible. It could serve as a useful platform for practical and scalable carbon nanotube
electronics.
23
2.2 Aligned nanotube synthesis with IPA carbon feedstock
Figure 2.1 illustrates our aligned semiconducting carbon nanotube synthesis
platform and the corresponding electrical performance of the as-grown nanotubes. Aligned
carbon nanotubes have been successfully synthesized on both small substrates and four
inch quartz wafers with isopropanol as the carbon feedstock, as shown in Figure 2.1a and
1b. A representative scanning electron microscopy (SEM) image of the nanotubes
synthesized from isopropanol is shown in Figure 2.1b with an average density of 4
tubes/μm and AFM characterization suggests a diameter distribution of 1.38 ± 0.23 nm
(Figure S1 in the Supporting Information.). After growth, the nanotubes were transferred
from quartz growth substrates to Si/SiO2 substrates with 500 nm SiO2 using the method
reported in our previous publication,
9
followed by the deposition of 0.5 nm Ti/ 50 nm Pd
source/drain metal contacts. Then, the nanotubes outside the transistor channel were etched
away using lithography followed by oxygen plasma. The schematic and an SEM image of
a representative device consisting of horizontally aligned arrays of isopropanol-
synthesized carbon nanotubes are shown in Figure 2.1c. As a comparison, we have also
synthesized and studied aligned nanotubes using ethanol as the feedstock, which possess a
similar nanotube density to isopropanol-synthesized samples (Figure S1 in the Supporting
Information). Figure 2.1d compares the electric characteristics of aligned nanotube
24
transistors with isopropanol- (red trace) and ethanol-synthesized (blue trace) carbon
nanotubes. Both devices have channel widths of 50 μm and contain approximately 200
nanotubes in the channel. The on/off ratio for the transistor using isopropanol-synthesized
nanotubes is 42 as compared to 2.1 for the transistor using ethanol-synthesized nanotubes.
If we follow the method used in previous publication
27
and assume that the metallic
nanotubes are equally conductive as the semiconducting ones in their on-state, the
percentage of semiconducting nanotubes of the isopropanol-synthesized nanotube sample
in Figure 2.1d is estimated to be 97.6%. As a comparison, the ethanol-synthesized nanotube
sample in Figure 2.1d contains only roughly 52.4% of semiconducting nanotubes, which
is not far away from 67% semiconducting ratio as predicted by theory and validated by
experiments.
36
A number of such transistors using both isopropanol- and ethanol-
synthesized nanotubes were measured and the on/off ratio distributions were plotted in
Figure 2.1e. I It is obvious that the average on/off ratio of the devices using isopropanol-
synthesized nanotubes is much higher than that using ethanol-synthesized nanotubes. The
medium on/off ratios are 20 and 3.5 for isopropanol- and ethanol-synthesized nanotubes,
respectively. Based on the analysis presented above, one can estimate the percentage of
semiconducting nanotubes to be 95% for isopropanol-synthesized nanotubes and 71.4%
for ethanol-synthesized nanotubes. The transfer characteristics and output characteristics
for representative transistors using isopropanol-synthesized nanotubes are shown in Figure
25
2.1f and 2.1g, respectively. Both exhibit p-type behavior and linear I-V curves, indicating
ohmic contacts have been achieved.
Figure 2. 1 Wafer-scale carbon nanotube synthesis using isopropanol and electrical
characteristics of the back-gated nanotube devices. (a) Photograph of a four-inch wafer
-20 -10 0 10 20
0.01
0.1
1
10
52.4% semiconducting
I
on
/I
off
= 2.1
Isopropanol
Ethanol
I
SD
/W ( A/ m)
Gate Voltage (V)
I
on
/I
off
= 42
97.6% semiconducting
Isopropanol Ethanol
1
10
100
Samples
On/Off Ratio
Isopropanol
Ethanol
-10 -5 0 5 10
0
2
4
6
8
10
12
14
0.2 V
0.4 V
0.6 V
0.8 V
Drain Current ( A)
Gate Voltage (V)
V
D
= 1 V
-1.0 -0.5 0.0 0.5 1.0
-15
-10
-5
0
5
10
15
Drain Current ( A)
Drain Voltage (V)
V
G
from -10 to 10 V
in 2 V step
Ti/Pd
a
d
c b
f g
e
26
with aligned nanotubes grown. (b) An SEM image of aligned nanotubes grown from
isopropanol carbon feedstock. (c) Schematic and an SEM image of a back-gated
isopropanol-synthesized nanotube transistor. (d) ISD-VGS curves of back-gate devices with
isopropanol- and ethanol-synthesized nanotubes. (e) On/off ratio distribution for devices
with isopropanol- and ethanol-synthesized carbon nanotubes. (f) Transfer and (g) Output
characteristics of a representative back-gated transistor with isopropanol-grown carbon
nanotubes.
2.3 Electrical characterization and Raman spectrum
To be more rigorous, the percentage of semiconducting nanotubes is further
evaluated by individual nanotube device measurements as illustrated in Figure 2.2. For
isopropanol-synthesized nanotubes, we patterned narrow channel devices by using a
stepper with a 0.5 μm resolution. A typical SEM image of the individual nanotube transistor
is shown in Figure 2.2a, whose channel is defined by projection photolithography and
oxygen plasma etching. A large number of such transistors were fabricated and 38 devices
with one individual nanotube were selected, and their transfer characteristics were
measured as shown in Figure 2.2b. For the measurements, the gate voltage (VG) was swept
from -20 to 20 V with a constant drain bias (VD) of 0.2 V. From the results, we found that
the percentage of devices with on/off ratios above 10 is ~90%, which is much higher than
the theoretical 67% semiconducting nanotubes ratio.
36
The typical transfer characteristics
of metallic single nanotube transistor and semiconducting single nanotube transistor are
shown in Figure 2.2c and 2d, respectively. The statistics of on/off ratios and on current of
27
individual nanotube transistors are shown in Figure 2.2e and 2f, respectively. Furthermore,
the decent on-current of such individual nanotube transistors confirms the preservation of
good electrical quality in the isopropanol-synthesized nanotubes.
Resonant Raman spectroscopy was further used to characterize the nanotubes from
different carbon feed stocks. Radial breathing modes (RBMs) were used to distinguish the
semiconducting nanotubes from metallic nanotubes. A number of RBM spectra were
acquired in both isopropanol and ethanol-synthesized nanotube samples by applying lasers
with wavelengths (energy) of 533 nm (2.33 eV ), 632 nm (1.98 eV ), and 785 nm (1.58
eV ). Figure 2.3a and 3b show the Raman spectra recorded with 533 nm excitation line for
isopropanol- (Figure 2.3a) and ethanol-synthesized nanotubes (Figure 2.3b), respectively.
Raman peaks from quartz substrate are labeled with “*”. The figures show that all RBM
frequencies distribute from 140 to 180 cm
-1
, which belong to the semiconducting
nanotubes.
37
This is as expected because the nanotubes that are in resonance with 533 nm
laser excitation should be semiconducting according to the diameter distributions of as-
grown nanotubes (Figure S1 in Supporting Information). In Figure 2.3c and 3d, the RBM
spectra scanned using a 632 nm laser reveal that all RBMs for isopropanol-synthesized
nanotubes lie in the semiconducting region (Figure 2.3c), while RBMs for both
semiconducting and metallic nanotubes were clearly observed in the ethanol-synthesized
nanotubes (Figure 2.3d), which is consistent with our electrical measurements on both
28
aligned nanotube array and individual nanotube devices. As for the 785 nm laser, no
obvious RBMs were observed in both samples (data not shown) probably due to the low
power of 785 nm laser we have. With the information above, we further conclude that
nanotubes produced from isopropanol as carbon feedstock are predominant
semiconducting ones as compared to ethanol. In order to examine the quality of the as-
grown nanotubes, the Raman D-band to G-band ratio at multiple locations for both samples
were measured (Figure S4 in Supporting Information). The results reveal that the D/G
ratios of nanotubes from isopropanol and ethanol are similar, ~0.04 on average, indicating
overall very high quality of nanotubes synthesized using both carbon feed stocks. We note
that only nanotubes in resonance with the laser energy would give Raman signal. While
Raman can be a very useful tool to characterize nanotubes, Raman spectra alone does not
provide definitive conclusion about what kind of nanotubes are present or not present. We
have therefore carried out extensive electrical measurements on individual nanotube
transistors, as discussed in Figure 2.2.
29
Figure 2. 2 (a) An SEM image of a representative individual nanotube device with a 4 μm
channel length. (b) Transfer characteristics of 38 individual nanotube transistors, with red
traces representing the metallic nanotubes and blue traces representing the semiconducting
ones. The percentage of devices with on/off ratio higher than 10 is around 90%. The
nanotubes were grown from isopropanol CVD.
2 μm
-20 -10 0 10 20
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
Semiconducting
Metallic
Drain Current (A)
Gate Voltage (V)
a b
30
Figure 2. 3 Micro-Raman characterization. (a) RBMs of isopropanol-synthesized
nanotubes and (b) RBMs of ethanol-synthesized nanotubes using a 532 nm laser. (c) RBMs
of isopropanol-synthesized nanotubes and (d) RBMs of ethanol-synthesized nanotubes
using a 633 nm laser.
100 120 140 160 180 200 220 240
Raman Shift (cm
-1
)
Intensity (a.u.)
*
*
Metallic Semiconducting
*
Isopropanol
533 nm
100 120 140 160 180 200 220 240
Raman Shift (cm
-1
)
Intensity (a.u.)
*
*
Metallic Semiconducting
*
Ethanol
533 nm
100 120 140 160 180 200 220 240
Raman Shift (cm
-1
)
Intensity (a.u.)
*
Semiconducting Metallic
*
Isopropanol
632 nm
100 120 140 160 180 200 220 240
*
Intensity (a.u.)
Raman Shift (cm
-1
)
Semiconducting
Metallic
*
Ethanol
632 nm
a b
c d
31
2.4 Mass spectroscopy
All the results above unambiguously confirm that predominately semiconducting
nanotubes were produced by using isopropanol as the carbon feed source. While this
finding is immensely useful for device applications using carbon nanotubes, it is necessary
to further understand the chemical mechanism behind such selective growth behavior. We
have performed a mass spectrometric
38
study to compare the CVD processes for both
isopropanol and ethanol, and the results are shown in Figure 2.4. We note that mass
spectrometry is a very useful tool to decipher the secret of nanotube CVD, as have been
reported by Harutyunyan’s group and some other groups.
39-42
In this experiment, mass
spectrometry was performed with the Omnistar from Pfeiffer (Model GSD301). In the
measurement setup, the detector was connected to the exhaust port of a one inch tube CVD
system. Using this setup, the species at the CVD exhaust port for both ethanol and
isopropanol was quantitatively measured. Figure 2.4a presents the intensity versus mass-
to-charge ratio during synthesis. In order to get accurate results during synthesis, both
hydrogen and argon were first flowed for 5 minutes to purge the system of residual air.
After that, the temperature was increased to 900 °C with continued flow of hydrogen, and
standard CVD was carried out at 900 °C by flowing argon through an ethanol or
isopropanol bubbler. A set of mass spectra were taken with a peak at M/Z = 20 for Ar
2+
in
Figure 2.4 was used to normalize all the curves. We took several mass spectra during the
32
15-minute growth period (blue trace for isopropanol and red trace for ethanol), and the data
was consistent throughout the entire synthesis period. Here, the flow rates for both
synthesis processes were 300 sccm of hydrogen and 160 sccm of argon, the same with the
growth procedure mentioned previously.
On the basis of the mass spectrometric results, several main species and their
relative intensity are presented in Table 1. The main hydrocarbon species detected are CH3
+
,
CH4 and C2H4, while other species like C2H2
+
and C2H5
+
have trivial signals. By calculating
the ratios between the main hydrocarbon species and water for isopropanol CVD, we
obtained ratios of 3.9, 4.7 and 1.3 for CH3
+
, CH4 and C2H4, respectively. Similarly, for
ethanol CVD, we obtained ratios of 4.6, 5.4 and 3.1 for CH3
+
, CH4 and C2H4, respectively.
Interestingly, we noted that the hydrocarbons to water ratios are consistently lower in
isopropanol CVD than that in ethanol CVD, indicating a relatively high concentration of
water in isopropanol CVD process. Particularly, we note that the ratios of C2H4 to H2O are
significantly different in two systems, i.e., 1.3 for isopropanol CVD versus 3.1 for ethanol
CVD. As water concentration has a profound effect on the selective growth of SWCNTs
with given property,
43
we believe this is the main difference between the two systems. Our
results suggest that one can selective grow predominantly semiconducting nanotubes when
having the right amount of water vapor present in the CVD environment, and isopropanol
CVD happens to provide that environment. This is consistent with a recent study where a
33
suitable amount of water was directly introduced into CVD process for the selective growth
of semiconducting single-walled carbon nanotubes.
43
In contrast, ethanol CVD produces
relatively low water concentration than isopropanol CVD, and the preferential growth of
semiconducting nanotubes was not observed.
The mechanism of our observed preferential growth of semiconducting nanotubes
may involve multiple factors, such as suppression of metallic nanotube growth and/or
selective etching of metallic nanotubes in the isopropanol CVD environment after their
growth. In order to further investigate this point, we performed control experiments by
loading samples pre-deposited with separated high purity semiconducting nanotubes
(IsoNanoIntegris, 99% purity) and metallic nanotubes (IsoNanoIntegris, 98% purity) into
the same isopropanol CVD system. The use of such separated nanotubes clearly
distinguishes different behavior of semiconducting nanotubes with that of metallic ones in
the isopropanol CVD environment. Another reason of choosing these nanotubes is that they
have a very low content of metal residual, which excluding the re-growth of nanotubes
from metal catalysts.
17
The separated nanotubes used in this experiment were extensively
washed to remove surfactants before loading into CVD furnace. After the samples went
through the standard isopropanol CVD process, no noticeable change in their density and
length was observed for both semiconducting and metallic nanotubes based on the
comparison of the AFM images (Figure S6 in Supporting Information). This indicates that
34
the isopropanol CVD does not provide selective etching of either metallic or
semiconducting nanotubes. Our results suggest that the selective growth of semiconducting
nanotubes using isopropanol carbon feedstock mostly likely occurs through suppression of
the growth of metallic nanotubes at the very beginning of nucleation. This can be
understood as short caps of metallic and semiconducting nanotubes right after nucleation
may have very different chemical reactivity.
28, 44
We note that our post treatment
experiments using separated nanotubes cannot completely imitate the CVD process of
aligned nanotube growth. As in the CVD process, the presence of metal catalysts may have
influence on the growth of SWCNTs with given property.
33
Nevertheless, our results show
that the presence of the right amount of water in the isopropanol CVD environment leads
to the preferential growth of semiconducting SWCNTs, which is consistent with some of
the previous work regarding the effect of water species on SWCNT growth,
27, 43
albeit with
a lot difference in experimental details. For instance, while ethanol alone does not lead to
the preferential growth of semiconducting SWCNTs, previously Ding et al.
27
have reported
the use of mixed ethanol and methanol for preferential growth, probably because
decomposition of methanol leads to more water species and OH radicals during the CVD
process than ethanol alone.
35
Figure 2. 4 Mass spectra taken at the exhaust of the CVD system for ethanol (red trace)
and isopropanol (blue trace).
M/Z Possible species Isopropanol Ethanol
15 CH3
+
2.25 6.87
16 CH4 2.7 8.15
18 H2O 0.58 1.5
26 C2H2
+
0.049 0.32
28 C2H4 0.75 4.7
29 C2H5
+
0.152 1
14 16 18 20 22 24 26 28 30 32 34
Ethanol
Isopropanol
M/Z
Relative intensity (a.u)
36
Table 1 Normalized value of relative intensity of possible species from mass spectrometry
of synthesis condition
2.5 Application: thin-film transistor
The synthesis of predominantly semiconducting nanotubes using isopropanol may
find many applications. As an example, below we report the use of isopropanol nanotube
networks grown directly on silicon substrates for TFTs, which have great potential for
display electronics, and flexible and transparent electronics.
8, 45-50
While the transistors
utilizing aligned array of semiconducting nanotubes reported above exhibit on/off ratios in
the range of 10 to 100, much higher on/off ratios are required for various applications and
can be achieved by producing random networks of isopropanol-synthesized carbon
nanotubes. By using such percolative carbon nanotube networks, the probability of having
a metallic nanotube conduction path between source and drain can be significantly
minimized and thus high on/off ratios can be achieved as reported in our previous work
using separated nanotubes.
46-50
The fabrication of the isopropanol-synthesized nanotube
TFTs begins with the evaporation of 1 Å iron catalyst film over Si/SiO2 substrates. The
similar isopropanol CVD process was used to grow nanotube networks on Si/SiO2
substrates. Source and drain electrodes (Ti/Pd) were then patterned and back-gated
transistors were fabricated after etching away the unwanted nanotubes outside the active
37
channel region. The SEM images of the as-grown carbon nanotube thin film on a Si/SiO2
substrate is shown in Figure 2.5a, and a representative nanotube TFT with a channel width
of 20 μm and a channel length of 50 μm is presented in Figure 2.5b. As shown in the image,
the nanotubes form a random network, which help to eliminate metallic nanotube
conduction path. The electrical characteristics of this device are plotted in Figure 2.5c and
5d. Figure 2.5c illustrates the transfer characteristics (ID-VG) at various drain biases in both
linear and logarithm scale and Figure 2.5d presents the output characteristics (ID-VD) at
various VG biases. The on/off ratio of this transistor is up to 10
4
(Figure 2.5c inset) and an
effective device mobility of 116 cm
2
/V∙s is derived, which represents one of the best
mobility for thin-film transistors published up to date (Figure S7 in the Supporting
Information). Our result shows the great potential of using isopropanol-synthesized
nanotube networks for high-performance thin-film macroelectronics.
38
Figure 2. 5 TFTs using networks of isopropanol-synthesized nanotubes. (a) An SEM image
of a nanotube network. (b) An SEM image of a back-gated TFT. (c) Transfer and (d) output
characteristics of the device in (b).
2.5 Summary
To summarize, we have developed a facile, robust, and reproducible CVD approach
to grow predominantly semiconducting carbon nanotubes by using isopropanol as the
carbon feedstock. Both electrical and Raman characterization unambiguously confirms the
significantly improved percentage of semiconducting nanotubes. We have also performed
-5 -4 -3 -2 -1 0
-10
-8
-6
-4
-2
0
V
G
from -10 to 10 V
in 2 V step
Drain Current ( A)
Drain Voltage (V)
-20 -10 0 10 20
0.0
0.5
1.0
1.5
2.0
2.5
0.2 V
0.6 V
0.6 V
0.8 V
Drain Current ( A)
Gate Voltage (V)
V
D
= 1 V
50µm
-20 -10 0 10 20
10
-4
10
-3
10
-2
10
-1
10
0
Drain Current ( A)
Gate Voltage (V)
20 μm
Device SEM
a b
c d
39
mass spectrometric study for different carbon feedstocks to understand the underlying
mechanism behind this finding and found that water concentration may plays a critical role
in the observed selective growth behavior. Finally, TFTs with an on/off ratio up to 10
4
and
mobility up to 116 cm
2
/V∙s were demonstrated using the isopropanol-synthesized
nanotubes, which show the great potential for future applications in nanotube-based
macroelectronics.
40
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44
Chapter 3: Self-Aligned Fabrication of Graphene RF
Transistors with T-Shaped Gate
3.1 Introduction
Graphene has attracted tremendous attention as a channel material for future
electronic devices, due to its outstanding electronic properties
1-4
. In particular, high charge
carrier mobility and saturation velocity, as well as strong carrier density modulation by
electric field, result in very high transconductance for graphene field-effect transistors
(FETs)
5-8
. Moreover, single atomic layer thickness provides ultimate electrostatic
geometry for scaling down channel lengths. Gate stacks, with equivalent oxide thickness
(EOT) of 1.5 nm, which satisfy lateral gate scaling down few nanometers, have been
demonstrated for graphene FETs
9
. Significant advance has been made in the past for
various graphene-based electronic devices and circuits
10-17
; however, most of previous
devices are not based on self-aligned transistor design and fabrication. In contrast, self-
aligned transistor design has been the foundation for silicon transistor and the
semiconductor for the past several decades, as the self-aligned process uses a predefined
poly-silicon gate as a mask to form aligned source and drain automatically, which leads to
minimized overlap between gate and source/drain, greatly simplified fabrication, and
45
significantly improved device yield. As further evidence for the importance of self-aligned
design, various self-aligned transistors have been reported for carbon nanotubes
6,
18-20
In
spite of the utmost importance, self-aligned design and fabrication for graphene transistors
have not been fully explored.
In this paper we report a scalable and reliable method for the fabrication of self-
aligned graphene FETs. In order to optimize the design of the graphene FET, we propose
a T-shaped top gate stack (or mushroom gate) patterned through standard lithographical
methods. The T-shaped gate stack allows self-aligned source and drain formation by
depositing Pd with the T-gate mask. We employed a simplified fabrication flow to obtain
Al/Al2O3 T-shaped gate stack with thin high quality dielectric of equivalent oxide thickness
down to 2.3 nm and gate lengths down to 100 nm. Combining this fabrication procedure
with large area graphene films grown by chemical vapor deposition (CVD) method, we
achieved scalable high yield fabrication of large number of graphene FETs on Si/SiO2
substrates. The peak transconductance of the fabricated graphene FETs reaches 0.5 mS/µm,
which is among the highest reported for graphene FETs. Actual transistor performance
with current gain cut-off frequency of 23 GHz and maximum oscillation frequency of 10
GHz are obtained for a transistor with 110 nm gate length. The developed fabrication
methods are highly scalable and suitable for further scaling down of device dimensions.
46
3.2 Self-aligned T-gate fabrication
Figure 3.1 illustrates the scalable fabrication of self-aligned graphene transistors
based on the T-shaped gate. Large area single-layer graphene films were synthesized on
copper foils by a low pressure CVD method and subsequently transferred onto highly
resistive silicon wafer (ρ > 5 kΩ·cm) with 300 nm thick top SiO2 layer, , similarly to the
previous reports
17, 21, 22
. Titanium/palladium (0.5/50 nm) probing pads are first patterned
using contact aligner and lift-off process. After this, bilayer electron beam resist, with the
top layer, the copolymer of methyl methacrylate and methacrylic acid P(MMA-MAA),
being more sensitive than the bottom layer, polymethyl methacrylate (PMMA) with 950k
molecular weight, is used to fabricate T-shaped top gate stack. The bilayer resist was
exposed with high dose at the gate position center and low dose at the adjacent area in the
same exposure run. After the deposition of aluminium film (140 nm), a standard lift-off
process produces the T-shaped gate stack. The Al gate electrodes were then oxidized in air,
forming a thin dielectric layer between graphene and Al gate. Finally, a thin layer of
palladium (12 nm) was deposited on top of the T-shaped gate to create aligned source and
drain electrodes for the graphene FET. The self-aligned FET design and fabrication process
flow are illustrated in Figure 3.1. In order to fabricate a T-shaped top gate stack, we used
bilayer electron beam resist and consequent development of the bilayer resist defined the
pattern shown in Figure 3.1a. In addition, we have also employed the standard trilayer resist
47
recipe for T-gate patterning and similar results were achieved. The resulting side wall
profile of the bilayer resist mask provided easy lift-off after aluminum (Al) film deposition,
which left behind a T-shaped gate electrode (as shown in Figures 1c). The Al gate
electrodes were then oxidized in air, forming a thin dielectric layer between graphene and
Al gate. The oxidation of Al at the interface with graphene was previously reported and
attributed to the diffusion of oxygen due to weak physical interaction between graphene
surface and Al atoms
23
. Finally, a thin layer of palladium was deposited on top of the T-
shaped gate, creating perfectly aligned source and drain electrodes for the graphene FET
(Figure 3.1d). Figure 3.1f shows a cross-sectional SEM image of a complete device
obtained after cleaving the substrate across the transistor channel. The metal source, drain
and gate electrodes were precisely aligned to each other and well separated with short
ungated graphene sections. This air gap leads to significant reduction of the parasitic fringe
capacitance. The advantage of an air gap has been recently reported by Ding et al.
6
. The
separation distance is controlled by the length of the T-gate cap relative to the length of the
T-gate base, which can be adjusted by the bilayer exposure recipe. We note that the
standard T-gate technology used by the semiconductor industry usually employs the
trilayer resist recipe to define a very wide T-cap to reduce gate charging resistance;
however, here we intentionally used a relatively narrow T-cap, as a wide T-cap can lead to
large area of ungated graphene and thus high access resistance between the self-aligned
48
source/drain and gated graphene. For such T-gate with narrow cap, we find that the bilayer
resist recipe works very well and is simpler to process than the trilayer recipe.
In this report, we obtained gate lengths from 170 nm down to 110 nm, with the
length of the ungated graphene sections about 20 to 40 nm. This geometry allows
simultaneous reduction of the access resistance, fringe gate-source, and gate-drain
capacitance, and gate resistance. The length of the ungated sections can be further reduced
by angle deposition of the source/drain metal film, which may lead to a trade-off between
further reduction of the access resistance and increase of the parasitic fringe capacitance.
Based on the calculation using the gate dimension and experimental measurements, we
estimate the gate charging resistance to be ~1 Ω/µm of the gate width for 100 nm long
channel.
49
Figure 3. 1 Fabrication flow and schematic diagram of self-aligned transistors based on the
T-shaped gate stack. (a) Bilayer PMMA resist is exposed with high dose and adjacent low
dose and developed. (b) Al film is deposited at normal direction to the substrate to form a
T-shaped gate. (c) PMMA resist is removed and Al gate is oxidized in air to form thin
Al2O3 layer all around the gate, including the interface with graphene. (d) Thin Pd layer is
deposited to form self-aligned source and drain contacts. Schematic image (e) and cross
section SEM image (f) of a complete self-aligned graphene transistor.
200nm
Gate structure
Al/Al
2
O
3
10 nm Pd
(Self-aligned S/D)
Graphene
SiO
2
(300nm)
Si (high resistivity)
Graphene
Al/Al
2
O
3 Pd(Self-aligned S/D)
S D
SiO
2
(300nm)
Si (high resistivity)
Graphene
S D
P(MMA-MAA)
PMMA
high dose
low dose
E-beam exposure
SiO
2
(300nm)
Si (high resistivity)
Graphene
Al/Al
2
O
3
S D
SiO
2
(300nm)
Si (high resistivity)
Graphene
S D
Al
a
b
c d
e
f
50
The above-mentioned fabrication method allowed us to achieve highly scalable and
reliable fabrication of graphene transistors on complete Si wafers. CVD graphene synthesis
on copper foils is readily extendable to very large areas by rolling up the foil
21,22
. In our
case, we achieved graphene synthesis on copper foils as large as 12 inch in a 4 inch CVD
chamber, furthermore, we successfully transferred the synthesized graphene to 12 inch Si
wafers (Figure 3.2a). We carried out the fabrication of the T-gate graphene transistors for
2 inch wafer size due to the limitation of our lithography equipment. Figure 3.2b shows a
2 inch Si wafer with the fabricated graphene transistors. Figure 3.2c and d show the top-
view SEM images of a typical graphene T-gate transistor.
We first characterized the T-shaped Al/Al2O3 gate stack performance using
electrical measurements. Figure 3.2e shows the conductance of a graphene FET as a
function of the top gate voltage VG and the back gate voltage VBG. By comparing the shift
of the charge neutrality point VCNP (defined as the top gate voltage at the minimum
conductance point), with the change of the back gate voltage VBG, as shown in Figure 3.2f,
we can find the top gate capacitance to be 130 times larger than the back gate capacitance
5,
9, 24
. For 300 nm SiO2 back gate dielectric, we estimate the back gate and top gate
capacitances to be 11.8 nF/cm
2
and 1500 nF/cm
2
, respectively. This capacitance
corresponds to a dielectric with EOT of 2.3 nm, and hence we can estimate the thickness
of the Al2O3 dielectric to be about 3 to 5 nm. The Al2O3 dielectric exhibits excellent
51
insulator behavior with nearly 100% yield across all the devices. According to the electrical
measurement, the dielectric breakdown voltage is higher than 2.5 V, as shown in Figure
3.2g. This fabrication method provides a simple and reliable method to obtain gate stacks
with high-quality dielectric for graphene devices. The mobility µ and contact resistance RC
of a graphene FET can be extracted by fitting the source-drain linear resistance RDS with
the formula: RDSW = 2RCW + L/[µe (n0
2
+ n
2
)
1/2
], where L is the gate length, W is the
channel width, n0 is the residual carrier density, and n is the carrier density due to top gate
modulation
6
24-26
. Figure 3.2h shows the measurement and the fit of the resistance of a
graphene FET with 170 nm gate length. We find the hole mobility equal to 1500 cm
2
/V∙s,
residual carrier concentration n0 of 5×10
11
cm
-2
and scaled contact resistance RCW of about
400 Ω·µm. These parameters are not as good as the values of exfoliated graphene, but
comparable to the values for other graphene FETs.
52
3 μm
Drain
Gate
Source
Source
Gate
Graphene film
c d
a b
10
-13
10
-11
10
-9
10
-7
10
-5
I
G
(A)
3.0 2.0 1.0 0.0
V
G
(V)
1600
1400
1200
1000
R
DS
(ohm*µm)
-1.5 -1.0 -0.5 0.0
V
G
- V
CNP
(V)
µ = 1500 cm
2
/V/s
40
30
20
10
0
-10
-20
V
BG
(V)
2.0 1.5 1.0 0.5 0.0 -0.5
V
G
(V)
1.1
1.0
0.9
0.8
0.7
0.6
G
DS
(mA/V)
e f
g h
1.9
1.8
1.7
1.6
V
CNP
(V)
40 30 20 10 0 -10
V
BG
(V)
C
TG
/ C
BG
= 130
53
Figure 3. 2 Electrical properties of the self-aligned graphene transistors. Photographs of 12
inch Si wafer with transferred large area CVD grown graphene (a) and 2 inch Si wafer with
fabricated graphene transistors (b). (c) Artificial color SEM image of a self-aligned
graphene transistor with the dual gate configuration, with the scale bar being 10 µm. (d)
Zoomed in SEM image of the transistor active area. (e) Two-dimensional plot of a graphene
transistor conductance as a function of the top gate and back gate voltages. (f) Top gate
voltage at the charge neutrality point versus back gate voltage. The slope of the lines gives
the ratio of top gate dielectric capacitance to the bottom gate dielectric capacitance equal
to 130. (g) Gate leakage current of few graphene transistors, both source and drain are
grounded. Dielectric breakdown voltage is higher than 2.5 V. (h) Scaled resistance of a
graphene transistor versus top gate voltage. Black curve is the experimental result and red
curve is the model fitting.
3.3 DC characterization of T-gate graphene transistor
Figure 3.3 shows the output and transfer characteristics of two graphene FETs with
a channel length of 170 nm (Figure 3.3a-c) and 110 nm (Figure 3.3d-f), respectively. For
the output characteristics (Figure 3.3a), the drain voltage sweeps from 0 V to -1.2 V, with
the top gate voltage step of +0.2 V starting from -1.6 V for the top curve. The transistors
exhibit large drive current densities up to 1.3 mA/µm and ~50% gate modulation, as well
as appreciable current saturation with output conductance as low as 0.2 mS/µm. The
transfer curves (Figure 3.3b) and transconductance curves (Figure 3.3c) are obtained with
gate voltage swept from -1.5V to 1V, and the drain voltage varied from -1.1 V to -0.1 V
(in -0.2 V step) from the top to bottom curves. The saturation in Id-Vds curves at
intermediate gate voltages shown in Fig. 3a is consistent with previous reports
17,24
, and is
believed to be a result of the presence of the minimal density point close to the drain under
54
the right combination of gate voltage and drain voltage
24
. A peak scaled transconductance
gm/W up to 0.5 mS/µm was achieved for the 170 nm device. From comparison, the on/off
current ratio and transconductance of the transistors with 110 nm channel length are lower
than those of the transistors with 170 nm channel length. For example, the peak
transconductance, for 110 nm gate length is measured to be 0.27 mS/µm (Figure 3.3f).
Similar channel dependence was reported before
14
. One possible reason is the significant
contact resistance in our devices has more pronounced influence on the performance of
short channel transistors than long channel transistors. Moreover, quasi-ballistic transport
and strong interband tunneling in graphene may exert influence on short channel
transistors, as suggested before
14
.
55
Figure 3. 3 DC output and transfer characteristics of two graphene transistors of 170 nm
(a, b and c) and 110 nm (d, e and f) channel length. Scaled transistor current (IDS/W) vs
drain voltage (VDS) (a) and gate voltage (b); and scaled transconductance (gm/W) vs gate
voltage (VG) (c) for the transistor with 170nm gate length. Scaled transistor current (IDS/W)
vs drain voltage (VDS) (a) and gate voltage (b); and scaled transconductance (gm/W) vs gate
voltage (VG) (c) for the transistor with 110nm gate length. Back gate (substrate) voltage
was kept constant and equal to 0 V for all plots.
56
3.4 RF characterization of T-gate graphene transistor
We further characterized the high frequency performance of the graphene
transistors by standard on-chip S-parameters measurements with a vector network analyzer
over the frequency range of 0.05 to 10 GHz. The measurements were first calibrated to the
probe tips using an off-chip calibration substrate by a standard short-open-load-through
(SOLT) procedure. A de-embedding procedure was then used to eliminate the effect of the
co-planar waveguide pads on the RF performance by measuring on-chip ‘open’ and ‘short’
test structures. The ‘open’ test structure consisted of only large photolithography-defined
pads outside the active area of the transistors, while the short test structure has additional
metal film shorting the gate-source and drain-source pads. The S-parameters after this de-
embedding procedure are determined by the graphene transistor channel, top gate electrode
with gate interconnect, and ~1 µm long metal source and drain electrodes outside the
channel. We call the de-embedded results the ‘device’ performance, since it is the
performance that is accessible for actual integrated on-chip circuits. Figure 3.4 shows the
current gain (H21) and maximum available gain (MAG) for two transistors with channel
lengths of 170 nm (Figure 3.4a) and 110 nm (Figure 3.4b). The ‘measured’ and ‘device’
current gains are the results before and after the de-embedding procedure, respectively. A
current-gain cut-off frequency (fT) of 15 GHz and maximum oscillation frequency (fmax) of
8 GHz are obtained for the 170 nm device, and fT of 23 GHz and fmax of 10 GHz are obtained
57
for the 110 nm device. Altogether we have fabricated 20 devices, and all the devices
showed fT in the range of 5 GHz to 25 GHz.
The highest achievable current-gain cut-off frequency in a FET is limited by the
intrinsic gate delay and given by fT = gm/2πCg, where Cg is the total gate capacitance. Figure
3.4c shows the comparison between the intrinsic gate delay frequency which is evaluated
from the DC measurements of the transconductance and gate capacitance, and the ‘device’
current-gain cut-off frequency and maximum oscillation frequency from the RF
measurements. We find the ‘device’ current-gain cut-off frequency to be relatively close
to the intrinsic gate delay frequency value, which shows that the parasitic effects of the T-
shaped gate transistor play a small role and justifies the improved device design.
Owing to the T-gate design, our transistors exhibit excellent microwave power gain
with fmax up to 10 GHz, which is comparable to the best reported values
8, 17
. The current-
gain cut-off frequency (fT) of our transistors, however, is lower than some of the reported
values in literature
16,17,26
. We note that the main factors limiting the performance may
include graphene-metal contact resistance, and inhomogeneity of carrier concentration due
to impurities, corrugation and wrinkles in the graphene channel, and quality of the
graphene/dielectric interface. Further improvement of both fT and fmax of the graphene FETs
can be achieved by using the T-gate transistor design with metal-graphene junction and
transferred graphene quality improved.
58
Figure 3. 4 RF performance of graphene transistors. (a,b) Current gain (H21) before (black
line) and after(red line) the de-embedding procedure and maximum available gain (MAG)
(green line) for two graphene transistors with 170 nm channel length (a) and 110 nm
channel length (b). (c) Plot of fT, fmax, and intrinsic gate delay (gm/2πCg), evaluated from
DC measurements, versus gate bias (VG) for the 110 nm transistor.
3.5 Summary
In summary, we have developed a scalable self-aligned fabrication method utilizing
a T-shaped gate structure to fabricate graphene transistors. By using the T-shaped gate
design, we successfully scaled the channel length of graphene transistor down to 110 nm
with good alignment. The graphene transistors with gate lengths in the range of 110 to 170
nm exhibit excellent on-chip device performance with a peak transconductance up to 0.5
mS/µm. The developed fabrication method is highly scalable and reliable, which allows
the fabrication of large number of self-aligned graphene transistors with high yield. In
addition, while the work reported above deals with analog RF transistors, our self-aligned
10
0
10
1
10
2
10
3
Gain
0.1 1 10
Frequency (GHz)
H
21
device
H
21
measured
MAG
10
0
10
1
10
2
10
3
Gain
0.1 1 10
Frequency (GHz)
H
21
device
H
21
measured
MAG
35
30
25
20
15
10
5
0
f
T
, f
max
(GHz)
0.8 0.4 0.0 -0.4
V
G
(V)
f
T
f
max
g
m
/ 2 πC
gs
a b c
59
T-gate fabrication can be combined with patterned or assembled graphene ribbons with a
bandgap to produce high performance transistors with high on/off ratio for digital
electronics. Moreover, this simple fabrication approach to obtain self-aligned transistor can
work as an excellent platform for realization of highly scaled transistors based on other
carbon nanostructures, such as carbon nanotubes and graphene nanoribbons. Our work
represents an important step toward practical implementation of graphene devices and
circuits.
60
Chapter 3. References
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Noise Graphene FETs in Ambipolar RF Applications, IEEE Electron Device
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15. Yang, X.; Liu, G.; Balandin, A. A.; Mohanram, K. Triple-Mode Single-Transistor
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62
Chapter 4. Self-Aligned T-gate High-Purity Semiconducting
Carbon Nanotube RF Transistors Operated in Quasi Ballistic
Transport and Quantum Capacitance Regime
4.1 Introduction
Due to their unique properties including small size, high mobility, ballistic
conductance, large current density, resistance against electro-migration, and low
capacitance,
1-3
single-walled carbon nanotubes are considered as promising candidates for
next generation digital and analog electronics. It has been demonstrated that nanotubes can
be used in integrated logic circuits such as inverters, ring oscillators, decoders, and thin-
film macro-scale electronics such as AMOLED displays.
4-13
On the other hand, carbon
nanotubes have attracted significant research efforts as material for future analog radio
frequency (RF) electronics.
14-23
A combination of very high carrier mobility and current
density with extremely small size and intrinsic capacitance make nanotubes a highly
promising material for ultra-fast transistors.
Most previous effort on CNT RF electronics
focused on nanotubes prepared using chemical vapor deposition (CVD),
17
which involves
high temperature processing, usually provides around one third metallic nanotubes and two
thirds semiconducting nanotubes, and is often limited to sample size. In contrast, separated
carbon nanotubes can provide high purity semiconducting nanotubes up to 95%, 98%, and
63
99%, and can be dispersed at room temperature at wafer scale.
24, 25
However, there has
been rather limited study on RF electronics using separated carbon nanotube, and two
notable examples are RF transistors based on separated nanotubes using
dielectrophoresis,
16
and our own work using separated CNT networks with oxidized
aluminum as the back gate.
20
We note that there has been no report of self-aligned RF
transistors based on separated semiconducting nanotubes, even though self-aligned
fabrication schemes have been recognized as an important way to scale down channel
length and reduce parasitic capacitance for radio frequency transistors.
26-28
In addition, RF
transistors with high linearity are highly desired to reduce signal distortion and carbon
nanotube RF transistors are predicted to offer good performance and high linearity when
operated in the ballistic transport and quantum capacitance regime; however, realization of
such transistors has been proved to be very challenging.
In this paper, we report self-aligned T-gate fabrication and linearity performance of
radio frequency transistors based on high purity 98% semiconducting carbon nanotubes.
The channel length can be scaled down to 140 nm, which enables quasi ballistic transport,
and the gate dielectric is reduced to 2-3 nm aluminum oxide, leading to quasi quantum
capacitance operation. Measurements revealed highly linear I-V GS curves and gm with very
small variation for the transistors under active operation. We demonstrated RF transistors
consisted of separated semiconducting nanotube networks of current-gain cut-off
64
frequency (ft) up to 22 GHz and maximum oscillation frequency (fmax) of 10 GHz.
Furthermore, we studied the device linearity for our self-aligned T-gate nanotube transistor
as an important figure of merit. To the best of our knowledge, the 1-dB compression point
measurement with positive power gain was performed for nanotube devices for the first
time. Our results show that semiconducting nanotube transistors have great potential for
high frequency applications. The self-aligned T-gate fabrication has also been recently
applied to graphene transistors by us.
29
4.2 Self-aligned T-gate separate nanotube transistor
Figure 4.1a shows a field emission scanned electron microscope (FESEM) image
of a typical high-density and uniform-separated 98% semiconducting nanotubes thin film
(IsoNanotube-S from NanoIntegris, Inc). Highly resistive silicon wafer (ρ > 5 kΩ·cm) with
300 nm SiO2 was used as substrate in order to reduce parasitic capacitance. We obtained
uniform thin film of separated nanotubes over full wafer by using the solution-based
deposition method with aminopropyltriethoxy silane (APTES) functionalization as
reported in our previous work.
10, 11
This highly scalable deposition method enables further
wafer scale fabrication of nanotube radio frequency transistors. Here, ground-signal-
ground (GSG) coplanar waveguide structure was used to probe separated nanotube RF
transistors as shown in Figure 4.1b. The zoom-in optical microscope image of a separated
65
nanotube RF transistor is presented in Figure 4.1c. Figure 4.1d exhibits the schematic
image of separated nanotube transistors fabricated with T-shaped gate design. The carbon
nanotube network shown in Figure 4.1d is based on the SEM image in Figure 4.1a. With
bilayer electron beam resist of different sensitivity, a step-shaped side wall profile of the
bilayer resist was achieved by exposing high dose at the gate position center and low dose
at the adjacent area. After the deposition of aluminum (Al) film, a standard lift-off process
produces the T-shaped gate (T-gate) stack. By heating the sample to 150 °C in air for about
one hour, the oxidation of Al T-gate in air forms a thin dielectric layer at the interface
between nanotubes and gate electrode. Finally, palladium was deposited to create a self-
aligned source and drain electrodes with the T-shaped gate working as a shadow mask. The
SEM image of a representative separated nanotube RF transistor with 50 µm channel width
is shown in Figure 4.1e. Figure 4.1f presents the perspective-view SEM image of a
complete T-shaped structure. This self-aligned fabrication process provides a well-aligned
separation with a small air gap between gate and source/drain electrodes, which
significantly reduces parasitic fringe capacitance. The channel length of a nanotube
transistor is then set by the foot of the T-gate structure. In this report we obtained channel
lengths from 600 nm down to 140 nm. The separation between source and drain electrodes
is created by the T-gate cap, which can be controlled to be longer than T-gate foot by 40
nm or so. The self-aligned source/drain deposition usually leads to small ungated nanotube
66
section ~10-20 nm for each side of source and drain. Combination of uniform high-density
semiconducting nanotube films and T-gate self-aligned fabrication technique provides a
platform for scalable and reliable fabrication of nanotube RF transistors, which pave the
way for further study on the DC and RF performance of these devices.
Firstly, we characterized the DC performance of self-aligned T-gate separated
nanotube RF transistors. Figure 4.2a illustrates the transfer characteristics of back-gated
modulation (black trace) and top-gated modulation (red trace) for a separated nanotube
transistor with channel width W = 50 μm. The transistor had a channel length of 4 μm
before the self-aligned source/drain deposition. The black curve presents the back-gate
dependence with VBG swept from -20 to 20 V at drain bias of 1 V. It exhibits a good on/off
ratio over 10
3
,
which is decent for high-purity separated nanotube transistors.
10
After the
self-aligned source/drain deposition, the effective channel length scaled down to 140 nm,
and the top-gate transfer characteristics were measured with VTG swept from -1.5 V to 1 V
at drain bias of 0.2 V. As we discussed in our previous publication, self-oxidized aluminum
oxide provides high quality dielectric without leakage current within the voltage we used.
It is obvious that gate modulation of the nanotube transistor improved significantly after
the self-aligned source/drain patterned. With the on-state current density of 1.1 μA/μm and
the off-state current density of 0.14 μA/μm, the on/off ratio of top-gate I-VG curve is around
7.9. The reduction in on/off ratio after self-aligned source and drain deposition is related to
67
the channel length reduction from 4 μm to 140 nm, as metal tubes can bridge the source
and drain directly when the channel length gets reduced. We note that this on/off of 7.9 was
achieved for a channel of 140 nm by using 98% semiconducting nanotube solution, and it
compares favorably with an on/off ratio of 4.7 we reported before for a channel of 500 nm
using 95% semiconducting nanotube solution.
25
In addition, while semiconducting
nanotubes contribute to transconductance for the nanotube transistor, metallic nanotubes
do not contribute to transconductance and yet contribute to gate-channel capacitance. As a
result, using semiconducting nanotubes of higher purity (such as 98% used here) should be
beneficial for the transistor frequency performance.
2µm
20µm
200 nm
a c b
d f e
68
Figure 4. 1 Fabrication of self-aligned T-gate transistors based on uniform separated
nanotube thin film on Si/SiO2 substrates. (a) SEM image of a separated nanotube film. (b)
Photograph of a 4 inch Si/SiO2 wafer with fabricated separated nanotube devices. (c)
Zoomed-in optical image of an RF transistor with 50 µm channel width. (d) Schematic
diagram of the self-aligned T-gate transistor with separated nanotubes as the channel. (e)
SEM image of the channel region of a transistor. (f) Perspective-view SEM image of a T-
shaped gate structure.
4.3 DC characterization of separate nanotube transistor
More DC analysis of the self-aligned T-gate separated nanotube RF device is
presented in Figure 4.2, including transfer characteristics (IDS-V GS curves) at various drain
bias (Figure 4.2b) and output characteristics (IDS-VDS curves) with different gate bias
(Figure 4.2c). One can note that the IDS-V GS curves shown in Figure 4.2b are very linear
for gate voltage between -0.5 V and -1.2 V , corresponding to active transistor operation.
The on-current of the nanotube transistor reaches 36 μA/μm at VDS = -1.5 V. Saturation of
drain current is observed under high bias (Figure 4.2c), which is crucial to obtain voltage
gain. Besides, the gm-VGS curves derived from IDS-V GS curves are plotted in Figure 4.2d.
We note that the transconductance remains rather flat for V GS between -0.5 V and -1.2 V ,
indicating the potential for high linearity operation. By tuning the T-gate fabrication recipe,
we scaled transistor channel length from 600 nm down to 140 nm. Figure 4.2e and 2f
presents the gm-V GS curves of devices at VDS = 0.2V with channel length ranged from 140
nm to 300 nm and from 400 nm to 600 nm, respectively. It illustrates that transconductance
69
increases with reduced channel lengths. As presented in Figure 4.2d and 2e, self-aligned T-
gate separated nanotube transistors of 140 nm channel length show good linearity,
supported by the flat gate dependence curves. As a good comparison, significant work in
nanotube RF transistor has been achieved by Rogers’s group,
17, 30
while a carbon nanotube
RF transistor made by Rogers’s group has a channel of 700 nm and HfO2 gate dielectric of
50 nm,
30
and the device showed variation of gm from 2.5 mS at V GS = -0.8 V , to a peak
value of 5 mS at V GS = -0.2 V , and then a lower value of 3 mS at V GS = 0.2 V.
30
In contrast,
our transistors exhibited very uniform gm and very high linearity, as shown in Figure 4.2b
and 2d. We attribute the linearity of our devices to quasi ballistic transport as a result of
short channel length (140 nm in Figure 4.2b and 2d) and quasi quantum capacitance
operation due to the ultrathin gate dielectric (2-3 nm Al2O3) we used. It was predicted
before that nanotube transistor operated in the ballistic transport and quantum capacitance
regime can offer high linearity.
31
Previously, extensive study was carried by Dai et al. on
nanotube ballistic transport, which revealed mean free path of ~100 nm.
32
The self-aligned
T-gate design eliminates misalignment and thus enabled us to fabricate nanotube transistors
with channel length down to 140 nm, which is comparable to the mean free path and
therefore results in quasi ballistic transport.
As further evidence, we fabricated a self-aligned T-gate transistor with a single
nanotube, and the conductance is measured to be 0.13 × (4e
2
/h) at VDS = 0.2 V and V GS = -
70
1 V as shown in figure 4.1g. Transmission coefficient of 0.13 is an underestimate of the
real value as the transistor has metal-nanotube contact resistance and access resistance due
to ungated nanotubes in series with the active channel resistance. We nevertheless note that
the transmission coefficient of 0.13 is comparable to some of the devices reported.
32
Regarding to quantum capacitance operation, we can calculate gate capacitance Cw of
carbon nanotube in following equation:
33
Here, CQ is the quantum capacitance of nanotubes, D is the density of nanotube, εs
is the dielectric constant, t is the thickness of the dielectric layer, and R is the radius of
nanotube. With the device parameters, the electrostatic gate capacitance Cg for our T-gate
nanotube transistor is ~3.5×10
-10
F/m, which is close to the quantum capacitance value of
4×10
-10
F/m. We stress that even better linearity can be achieved by further reduction of
channel length to ensure complete ballistic transport, and by possibly replacing ultrathin
Al2O3 with other ultrathin high κ dielectric, such as HfO2.
=
71
-20 -15 -10 -5 0 5 10
0
5
10
15
20
25
Backgate Vds = 1V
Drain Current ( A)
Gate Voltage (V)
0
10
20
30
40
50
60
Drain Current ( A)
Topgate Vds = 0.2V
-1.0 -0.5 0.0 0.5 1.0
0.0
-0.5
-1.0
-1.5
Drain Current (mA)
Gate Voltage (V)
VDS = -0.1V to -1.5V
Step -0.2V
-1.5 -1.0 -0.5 0.0
0
40
80
120
160
200
240
140 nm
270 nm
300 nm
g
m
( S)
Gate Voltage (V)
-1.5 -1.0 -0.5 0.0
10
15
20
25
30
35
40
45
400 nm
520 nm
600 nm
g
m
( S)
Gate Voltage (V)
-1.0 -0.5 0.0 0.5 1.0
0.00
0.03
0.06
0.09
0.12
0.15
Vds = 0.2V
G (4e
2
/h)
Gate Voltage (V)
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
-2.0
-1.5
-1.0
-0.5
0.0
Drain Current (mA)
Drain Voltage (V)
VGS = 1V to -1.6V
Step -0.2V
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2
0.0
0.3
0.6
0.9
1.2
1.5
1.8
V
ds
= -0.1 V
V
ds
= -0.3 V
V
ds
= -0.7 V
V
ds
= -0.9 V
g
m
(mS)
Gate Voltage (V)
Vds = -0.1V to -1.1V
a b
c d
e f
g
72
Figure 4. 2 DC characteristics of self-aligned nanotube transistors. (a) Transfer
characteristics (IDS-V GS) with nanotube device of back-gate and top-gate control. (b)
Transfer characteristics (IDS-V GS) of the nanotube transistor with various VDS. (c) Output
(IDS-VDS) characteristics of the nanotube transistor with various VGS. (d) gm-V GS
characteristics measurement at various VDS. (e) gm-V GS characteristics measured with
devices of channel length ranged from 140 nm to 300 nm. (f) gm-V GS characteristics
measured with devices of channel length ranged from 400 nm to 600 nm. (g) Conductance
versus V GS under VDS = 0.2V of single nanotube self-aligned T-gate device.
4.4 RF characterization of separate nanotube transistor
The high frequency behavior of the self-aligned T-gate separated nanotube RF
transistors with 140 nm channel length was characterized by measuring S-parameters
directly with a vector network analyzer (VNA) over the frequency range from 0.05 to 10
GHz. The calibration of the measurement to the probe tips was performed by using off-
wafer short-open-load-through (SOLT) standard. Figure 4.3a and 3b illustrate the as-
measured S-parameters for the device structure presented in Figure 4.1e. The gate electrode
was biased at V GS = -1.1 V and drain electrode was biased at VDS = -1.5 V , since this bias
condition provides an optimal gm, confirmed by DC measurement. Figure 4.3c presents
both the extrinsic (before de-embedding) and intrinsic (after de-embedding) current-gain
(H21), and maximum available gain (MAG) frequency response of the nanotube RF
transistor. To exclude the parasitic capacitance from the probing measurement, a de-
embedding procedure was used to eliminate the effect of co-planar waveguide pads on the
RF performance by measuring the on-chip ‘open’ and ‘short’ test structures. In this de-
73
embedding method, the ‘open’ structure only consists of co-planar waveguide pads outside
the active area of nanotube transistor and the ‘short’ structure has additional metal film
shorting the gate-source and drain-source pads. As a result, the intrinsic device
performance after our de-embedding includes all the important device features such as T-
shaped gate and self-aligned source and drain electrode, which is important and meaningful
for circuit application. This kind of de-embedding procedure was applied to as-measured
S-parameters to obtain the ‘device’ performance. From Figure 4.3c, one can find the
current-gain cut-off frequency (ft) to be about 1 GHz before de-embedding and 22 GHz
after de-embedding. The Gmax curve indicates 10 GHz of unity power gain frequency fmax
both before and after de-embedding. Figure 4.3d presents the gate bias dependence of the
intrinsic cut-off frequency. The peak of cut-off frequency 23 GHz occurs at gate bias -0.9
V . Since ft is proportional to gm, the variation of ft follows the variation of gm, while the
small shift between gm and ft may come from the hysteresis of the nanotube transistor. The
frequency response of this self-aligned T-gate separated nanotube transistor is significantly
improved from our previous separated nanotube transistor of 5 GHz cut-off frequency,
25
and we attribute the improvement to the improved gm and reduced parasitic capacitances
with the self-aligned T-gate technology. In addition, the unity power gain frequency fmax of
10 GHz reported in this paper is one of the best performances for nanotube transistors
reported to the date.
74
To confirm the intrinsic frequency performance of separated nanotube T-gate RF
devices, we also performed the fabrication on quartz substrate to exclude the effects of
parasitic capacitances. The devices on quartz substrate exhibit DC characteristics similar
to devices on silicon substrate. Both extrinsic and intrinsic frequency response of a T-gate
separated nanotube transistor with 30 μm channel width on quartz substrate are illustrated
in Figure 4.3e. It shows an extrinsic current-gain cut-off frequency of 12 GHz and power
gain frequency of 8 GHz, which are comparable to the intrinsic performance of T-gate
separated nanotube devices on silicon substrate discussed previously, proving the validity
of our de-embedding method. Importantly, the extrinsic and intrinsic performances of T-
gate devices on quartz substrate are approximately the same because the insulating quartz
substrate reduces the parasitic capacitance significantly. Figure 4f is a plot of ft and fmax
from different T-gate transistors with channel length of ~140 nm on quartz substrate,
showing high yield and uniformity with cut-off frequency ranged from 4 GHz to 12 GHz.
75
Figure 4. 3 RF characteristics of a separated nanotube RF transistor on Si/SiO2 substrate
(a-d) and a similar transistor on quartz substrate. (a) Smith chart of as-measured S
parameters of the separated nanotube RF transistor on Si/SiO2 (L = 140 nm, W = 50 µm).
(b) As-measured S parameters of the separated nanotube RF transistor. (c) Extrinsic and
100MHz 1GHz 10GHz
-60
-40
-20
0
S-Parameter (dB)
Frequency
S11
S12
S21
S22
100MHz 1GHz 10GHz
1
10
100
Gain (dB)
Frequency
H21_extrinsic
H21_intriisc
Gmax_extrinsic
Gmax_intrinsic
1 2 3 4 5 6
0
3
6
9
12
15
f
max
f
max
(GHz)
Device #
0
3
6
9
12
15
f
t
(GHz)
f
t
100MHz 1GHz 10GHz
1
10
100
Gain (dB)
Frequency
H21_extrinsic
H21_intrinsic
Gmax_extrinsc
Gmax_intrinsic
-1.2 -0.9 -0.6 -0.3 0.0
18
20
22
24
g
m
(mS)
f
t
f
t
(GHz)
V
gs
(V)
0.0
0.5
1.0
1.5
g
m
a b
c d
e f
76
intrinsic current-gain H21 and maximum available gain Gmax of the device on Si/SiO2
substrate derived from the measured S parameters from 50 MHz to 10 GHz (d)
Transconductance and intrinsic cut-off frequency versus gate bias. (e) Extrinsic and
intrinsic current gain H21 and maximum available gain Gmax of the device on quartz
substrate derived from the measured S parameters from 50 MHz to 10 GHz. (f) fmax and ft
of different T-gate transistors on quartz substrate.
4.5 Linearity measurement of separate nanotube transistor
Linearity is a significant figure of merit for analog and RF/microwave circuit and
system designs. Carbon nanotubes are anticipated to enable emerging designs and systems
requiring highly linear transistors. Here, we also performed the linearity analysis for our
self-aligned T-gate separated nanotubes transistors. As known, there are a few figure of
merit capturing nonlinearity, and 1-dB compression point and the inter-modulation
distortion are the most common ones. Between the two metrics, 1-dB compression point is
a device performance metric, whereas the inter-modulation products are usually specified
for circuits and devices as parts of a system. Furthermore, the inter-modulation products
metrics (third-order intercept point IIP3) points are usually higher than the 1-dB
compression point by about 10 dB.
In order to characterize the nonlinearity metrics, the device under test should have
either voltage gain or power gain. In previous publications, the linearity performance of
the carbon-based transistors was estimated indirectly,
25, 26
either through use of the
transistor in a mixer or a resistively loaded transistor. In this work, we present the 1-dB
77
compression point measurement of separated nanotube transistors with positive power gain,
to our knowledge, for the first time. This is novel in the way of providing nonlinearity
performance information about the device directly, which also has a positive power gain.
Moreover, the device was characterized in a large signal domain, within the context it will
be used in designing the circuit with, which is another novel part of characterization work.
The self-aligned T-gate separated nanotube transistors were used in constructing a
class-A power amplifier, and to capture the impedance as well as nonlinearity information,
their available power gain contours and impedance were characterized in a load/source pull
system. The test setup is illustrated in Figure 4.4a. The load and source tuners synthesized
a known/adjustable input and output impedance for the device under test (DUT). The
reflected power and transmitted power was measured, corresponding to each input/output
impedance, in order to characterize the available power gain corresponding to termination
impedances seen by the DUT. The available power gain contours at 200 MHz and 500 MHz
were measured. The contours were significant in choosing the source impedance required
in order to achieve the fixed available power gain, and the load impedance was conjugate
matched on the output side. The available power gain contours at 200 MHz and 500 MHz
are shown in Figure 4.4b and 4c, respectively. As expected, as frequency was increased,
the radii of the contours corresponding to a fixed available power gain decreased, reducing
the flexibility in choosing the impedance. The 1-dB compression point was measured by
78
fixing the source impedance, corresponding to a particular available power gain, and
sweeping the power level from a low starting input power to higher values. Two 1-dB
compression point plots, at 200 MHz and 500 MHz input frequency are illustrated in Figure
4.4d and 4e, respectively. The 200 MHz input frequency measurement is synthesized to
achieve an available power gain of 8 dB, and reveals a 1-dB output referred compression
point of 11.6 dBm (Figure 4.4d). The 500 MHz input frequency measurement is
synthesized to achieve an available power gain of 6 dB, and reveals a 1-dB output referred
compression point of 11.9 dBm (Figure 4.4e).
79
Figure 4. 4 Linearity characteristics of T-gate self-aligned separated nanotube RF
transistors. (a) Schematic of load and source pull setup system to capture the nonlinearity
for the separated nanotube RF transistor. (b, c) Source impedance at the source tuner for 8
reflect coupler source coupler
RF
source
Source Tuner CNT FET Load Tuner
Bias-T
Power
sensor A
Power
sensor B
Reflect
power
sensor
Bias-T
cir_pts (0.000 to 51.000)
GaCircle1
23
0.528 / 17.800
m1
m1
indep(m1)=
GaCircle1=0.960 / 25.283
gain=8.000000
impedance = Z0 * (0.418 + j4.421)
23
cir_pts (0.000 to 51.000)
GaCircle1
23
0.528 / 17.800
m1
m1
indep(m1)=
GaCircle1=0.855 / 8.615
gain=8.000000
impedance = Z0 * (6.671 + j6.341)
23
-8 -6 -4 -2 0 2 4 6
0
2
4
6
8
10
12
14
Output Power (dBm)
Input Power (dBm)
-8 -6 -4 -2 0 2 4 6 8
-3
0
3
6
9
12
15
Output Power (dBm)
Input Power (dBm)
a
b c
d e
80
dB of power gain at 200 MHz (b) and 500 MHz (c). (d, e) 1-dB compression point plots at
200 MHz (d) and 500 MHz (e).
4.6 Summary
In conclusion, we applied the scalable self-aligned T-shaped gate design to
semiconducting nanotube RF transistors. The nanotube transistors exhibit excellent on-
chip device performance with channel length scaling down to 140 nm. With T-shaped gate
structure, a cut-off frequency up to 22 GHz and power gain frequency of 10 GHz for
separated nanotube transistor are achieved. The T-shaped gate design enables high-yield
wafer-scale fabrication with controllable gate length scaling. Furthermore, we also
characterized the linearity properties of nanotube transistors, with the 1-dB compression
point measurement, in source/load pull setup, with positive power gain to our knowledge,
for the first time. Meanwhile, we are still working on the optimization of separated
nanotube RF transistor fabrication, including using higher purity pre-separated
semiconducting nanotube solution, improving the uniformity of nanotube film, further
reducing device dimension, and decreasing parasitic effects such as access resistance from
ungated section. Above all, our work reveals that the semiconducting nanotube RF
transistor is an interesting and promising direction in high frequency device and circuit
exploration.
81
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Peng, L. M., Self-Aligned U-Gate Carbon Nanotube Field-Effect Transistor with
83
Extremely Small Parasitic Capacitance and Drain-Induced Barrier Lowering. ACS
Nano. 2011, 5, 2512-2519.
28. Farmer, D. B.; Lin, Y . M.; Avouris, P., Graphene Field-Effect Transistors with Self-
Aligned Gates. Appl. Phys. Lett. 2010, 97.
29. Badmaev, A.; Che, Y . C.; Li, Z.; Wang, C.; Zhou, C. W., Self-Aligned Fabrication
of Graphene Rf Transistors with T-Shaped Gate. ACS Nano. 2012, 6, 3371-3376.
30. Kocabas, C.; Dunham, S.; Cao, Q.; Cimino, K.; Ho, X. N.; Kim, H. S.; Dawson, D.;
Payne, J.; Stuenkel, M.; Zhang, H., et al., High-Frequency Performance of
Submicrometer Transistors That Use Aligned Arrays of Single-Walled Carbon
Nanotubes. Nano Lett. 2009, 9, 1937-1943.
31. Baumgardner, J. E.; Pesetski, A. A.; Murduck, J. M.; Przybysz, J. X.; Adam, J. D.;
Zhang, H., Inherent Linearity in Carbon Nanotube Field-Effect Transistors. Appl.
Phys. Lett. 2007, 91.
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Field-Effect Transistors. Nature. 2003, 424, 654-657.
33. Rosenblatt, S.; Yaish, Y .; Park, J.; Gore, J.; Sazonova, V .; McEuen, P. L., High
Performance Electrolyte Gated Carbon Nanotube Transistors. Nano Lett. 2002, 2,
869-872.
84
Chapter 5: T-gate Aligned Nanotube Radio Frequency Transistors
and Analog Circuits realization
5.1 Introduction
Carbon nanotube has attracted extensive attention in advanced electronics over a
decade due to unique characteristics of high mobility, large transconductance, small
dimension, and low capacitance.
1-16
Among these applications, analog electronics is of
great importance and only requires high transconductance but not high on/off ratio for RF
transistors.
9-16
Meanwhile, through a lot of significant research efforts, excellent radio
frequency (RF) performance has been demonstrated in previous publications using
nanotube networks/arrays from pre-separated high-purity semiconducting nanotube
solution and as-grown parallel nanotube arrays synthesized by chemical vapor deposition
(CVD).
11, 12, 15, 16
Kocabas et al. made radio frequency transistors based on CVD
synthesized aligned nanotube arrays and reported an extrinsic current-gain cut-off
frequency of 5 GHz.
17
And Nougaret et al. also achieved a on-chip performance of 15 GHz
current-gain cut-off frequency by using dielectrophoresis to assemble separated high-purity
semiconducting nanotubes.
13
Recently, an extrinsic current-gain cut-off frequency of 7
GHz has been reported for dielectrophoresis-assembled separated high-purity
semiconducting nanotube array transistors with channel length scaled down to 100 nm.
16
85
Those transistors based on separated semiconducting nanotubes showed intrinsic current-
gain cut-off frequency around 80 GHz
13
and 153 GHz
16
after de-embedding. It was also
discussed that good alignment of nanotubes are important for RF transistor performance.
16
The above-mentioned work has shown the great potential of nanotube-based transistors for
future high-frequency applications. However, the integration of large-area aligned
nanotube arrays based on pre-separated semiconducting nanotube solution through
dielectrophoresis (DEP) method is still a remaining obstacle for scalable fabrication of
nanotube-based electronics.
12, 16
Therefore, to advance the development of nanotube analog
circuit, scalable assembling of nanotubes and fabrication of high performance transistors
are required.
We note that there are two available ways to assemble large-scale nanotube material.
One is the wafer-scale dispersion of high-purity pre-separated semiconducting nanotube
solution with the method of surface functionalization.
15, 18, 19
This dispersion method is a
scalable room-temperature processing procedure and the high-purity of semiconducting
nanotubes brings benefits to transistor performance. We have reported decent RF
performance with nanotube networks prepared using this method.
15
However, this
assembling method provides nanotube networks instead of aligned nanotube arrays.
Another solution to achieve scalable assembling of nanotubes is the chemical vapor
deposition.
20-24
In this method, large-area horizontally aligned single-wall carbon
86
nanotubes (SWCNTs) can be obtained on certain crystalline substrates like quartz or
sapphire. In this way, this kind of parallel nanotubes provide a great platform for wafer-
scale fabrication of RF transistors and circuits. In addition, aligned geometry of as-grown
nanotubes can enhance the gate control capability and avoid the nanotube-to-nanotube
junctions introduced from solution-processed nanotubes. It is therefore very important to
further explore the potential of aligned CVD nanotubes for RF transistors and circuits.
Our group has recently developed a self-aligned T-shape gate fabrication approach
for high-performance RF transistors, and has successfully applied it to both graphene and
solution-processed separated high-purity nanotube networks.
15, 25
With this design, the
parasitic effects including fringe gate capacitance, access resistance, and gate charging
resistance can be significantly reduced. Furthermore, the channel length can be scaled
down to 140 nm and gate dielectric was reduced to 2-3 nm Al2O3, which led to the quasi-
ballistic and quasi-quantum capacitance operation for nanotubes.
15
5.2 T-gate aligned nanotube transistor
Figure 5.1a shows a field emission scanned electron microscope (FESEM) image
of aligned nanotube arrays on quartz substrate with a density of 5 SWNTs/µm grown by
chemical vapor deposition (CVD) method. Here, we used ethanol as carbon feedstock for
CVD nanotube synthesis. In Figure 5.1a, one can find aligned arrays of nanotubes with a
87
density about 5~8 SWNTs/µm synthesized on quartz substrate. This CVD approach can
produce aligned SWCNTs over complete wafers for wafer-scale fabrication, as we reported
previously.
22
As we discussed in previous report, self-aligned T-gate technology has been
proved to be a good platform for carbon nanotube radio frequency device application.
15
We
first patterned the source and drain electrodes on the aligned nanotubes on quartz substrate
directly. Here, normal ground-signal-ground (GSG) coplanar waveguide structure was used.
Then T-shaped aluminum gate was fabricated using E-beam lithography on inverted
PMMA bilayer resist.
25
Lastly, 10 nm palladium was deposited to form self-aligned source
and drain. Figure 5.1b exhibits the device schematic of T-shaped gate aligned nanotube
device. In Figure 5.1c, a top-view of gate structure is presented with a cap size of 150 nm.
The channel length of the gate structure in Figure 5.1c is estimated to be around 100 nm
according to the inspection of cross-section from well-established recipe. An optical image
of aligned nanotube RF transistor with 80 µm channel width fabricated on quartz substrate
is shown in Figure 5.1d.
The DC performance of aligned nanotube RF transistor is characterized in Figure
5.1e and 5.1f. Figure 5.1e illustrates the transfer characteristics (IDS-VGS curve) of an
aligned nanotube T-gate device with a channel width of 80 µm and channel length of 100
nm. The top-gate characteristics were measured with V GS swept from -1.5 V to 1.5 V at
drain bias VDS of -0.8 V . The on/off ratio of this device is around 2 due to the co-existence
88
of metallic and semiconducting nanotubes.
24, 26
In spite of the relative low on/off, the
aligned nanotube transistor here shows high conductance (180 µA/µm), which is about six
times higher than that of separated nanotube transistor (30 µA/µm) with similar geometry
and nanotube density.
15
Possible reasons for this difference in conductance may include
different nanotube quality, as CVD-synthesized nanotubes are known to have high quality
and nearly defect-free structures, and possible presence of residual surfactants for solution-
processed separated nanotubes. In addition, alignment of nanotube arrays can also help to
improve conductance because of the lack of nanotube-to-nanotube junction. In Figure 5.1f,
it presents the gm-V GS curve with a peak transconductance up to 60 µS/µm. According to
the information shown in Figure 5.1f, the peak transconductance of this aligned nanotube
transistor is about two times higher than that of separated nanotube transistor published
previously with similar device structure and geometry.
15
As a result, aligned nanotube
transistors with good DC performance in terms of high conductivity and transconductance
enable us to further explore high-frequency application.
89
Figure 5. 1 (a) SEM image of aligned carbon nanotubes on a quartz substrate (Density: 5
SWNTs/µm). (b) Schematic of a self-aligned T-gate aligned nanotube RF transistor. (c)
Top-view SEM image of T-shape gate transistor (T-gate cap: 150 nm, base: ~100 nm). (d)
Optical image of T-gate aligned nanotube RF transistor with channel width of 80 µm. (e)
Transfer characteristics of T-gate aligned nanotube RF transistor. (f) Scaled
transconductance (gm/W) versus gate voltage (Vgs) curve for aligned nanotube RF
transistor.
We further characterized the high-frequency performance of T-gate aligned carbon
nanotube transistors in Figure 5.2. We measured the S-parameters of the transistor
discussed in Figure 5.1 by using a vector network analyzer (VNA) with frequency range
from 0.05 to 20 GHz. The probe tips were calibrated by using off-wafer short-open-load-
through (SOLT) standard procedure. The high-frequency performance of this device was
derived from the as-measured S-parameters at VTG = -0.7 V and VDS = -0.8 V , where the
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
-10
0
10
20
30
40
50
60
VDS = -0.8V
g
m
( S/ m)
Gate Voltage (V)
a b c
d e f
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
-9
-10
-11
-12
-13
-14
-15
VDS = -0.8 V
Drain Current (mA)
Gate Voltage (V)
90
optimal transconductance occurs. Figure 5.2a presents the current-gain (H21) of aligned
nanotube RF transistor before and after de-embedding procedure. As shown in Figure 5.2a,
the current-gain curves indicate an extrinsic cut-off frequency of 25 GHz and intrinsic cut-
off frequency of 102 GHz. The extrinsic frequency performance of this aligned nanotube
transistor in this work is one of the best performance of nanotube-based transistors reported
to date. Figure 5.2b illustrates the power-gain curve of aligned nanotube transistor and it
shows an extrinsic unity power-gain frequency fmax of about 9 GHz. For comparison,
recently published extrinsic and intrinsic radio frequency performances of nanotube-based
RF transistors are shown in Figure 5.2c and d, respectively. Based on the data shown in
Figure 5.2c, our work presents the highest extrinsic current-gain cut-off frequency (25
GHz). Furthermore, the intrinsic nanotube RF performance achieved in this work (102 GHz)
is among the best performance for nanotube transistors as illustrated in Figure 5.2d.
Compared with previous reports, the improvement of the cut-off frequency in our work
results from the scaling of the channel length, excellent alignment, and good quality of
nanotube arrays. We have made about 20 transistors with gate length around 100 nm to 140
nm, and they all show consistent values of ft and fmax. These nanotube transistors with such
good performance provide us the foundation to realize radio frequency circuit operated in
gigahertz regime.
91
Figure 5. 2 RF performance of self-aligned T-gate aligned nanotube transistor. (a) Current
gain (H21) before (black curve) and after (red curve) the de-embedding procedure. (b)
Extrinsic power gain (MAG) curve. (c,d) Extrinsic (c) and intrinsic (d) cut-off frequency
versus channel length from previous publication and our work.
5.3 Linearity measurement of T-gate aligned nanotube transistor
We analyzed the linearity performance of aligned nanotube transistors with single-
tone (1dB compression point) and two-tone test (third-order intercept point). The schematic
of the measurement set up is illustrated in Figure 5.3a. The device used in the circuit
configuration has a unity power-gain frequency of 9 GHz. We first applied single-tone
100MHz 1GHz 10GHz
-5
0
5
10
15
20
25
30
Power Gain (dB)
Frequency
Gmax
fmax = 9 GHz
100MHz 1GHz 10GHz 100GHz
-10
0
10
20
30
40
50
60
70
80
ft_intrinsic = 102 GHz
Current Gain (dB)
Frequency
H21_ex
H21_in
ft_extrinsic = 25 GHz
a b
c
d
0 100 200 300 400 500 600 700 800
10 MHz
100 MHz
100GHz
1GHz
Extrinsic
UIUC (Ref.12)
IEMN (Ref.13)
IBM (Ref.16)
USC 2011 (Ref.14)
USC 2012 (Ref.15)
This work
Frequency
Channel length (nm)
10GHz
0 100 200 300 400 500 600 700 800
100MHz
1THz
100GHz
1GHz
Intrinsic
UIUC (Ref.12)
IEMN (Ref.13)
IBM (Ref.16)
USC 2011 (Ref.14)
USC 2012 (Ref.15)
This work
Frequency
Channel length (nm)
10GHz
92
signal with frequency range from 1 GHz to 8 GHz to the gate of the aligned nanotube
transistor and measured the output signal power level with a spectrum analyzer. Figure 5.3b
shows the plots of extracted output power of fundamental as a function of input power at
various frequencies. Based on the curves shown in Figure 5.3b, we can obtain the 1 dB
compression point for this nanotube device to be around 10 dBm for different frequencies.
These P1dB values indicate that this nanotube transistor can operate linearly with an input
power up to 10 dBm, which is consistent with the discussion about the linearity
performance of carbon nanotube transistors reported recently.
14, 15
Furthermore, it can be
noticed that the power gain does not degrade much even when frequency goes up to
relatively high frequency (8 GHz). In two-tone measurement, we applied two-tone signals
with adjacent frequencies to gate of the aligned nanotube transistor through a power
combiner as shown in the Figure 5.3a. We first conducted the two-tone test at 3.2 GHz and
3.4 GHz. In Figure 5.3c, the power level of the fundamentals and third-order
intermodulation (2f2-f1 or 2f1-f2) is extracted as a function of input power. As shown in
Figure 5.3c, the power of fundamentals and third-order intermondulation follow the slope
of 10 and 30 dB/decade, consistent with theoretical rate. We obtained IIP3 of 18 dBm and
OIP3 of -9 dBm at third-order intercept point for the two-tone test at 3.2 GHz and 3.4 GHz.
Similarly, another two-tone test was performed at frequency of 5 GHz and 5.3 GHz and the
extracted output power of fundamentals and third-order intermodulation are plotted as
93
function of input power in Figure 5.3d. The IIP3 and OIP3 for this two tone test are 22.3
dBm and 2.7 dBm, respectively. IIP3 and OIP3 are important figures of merit capturing the
linearity of mixer. Our results compare favorably with previous publication. For example,
here we achieved the P1dB of 10 dBm at frequency of 8 GHz, while the previous work
only studied in frequency range from 10 to 500 MHz.
14, 15
Figure 5. 3 Linearity performance of self-aligned T-gate aligned nanotube transistor. (a)
Schematic of single/two tone test for aligned nanotube transistor. (b) Output power of the
fundamental versus input power. (c,d) Output power of the fundamental and third-order
intermodulation as a function of the input power measured in the frequency region of 3
GHz (c) and 5 GHz (d).
-20 -15 -10 -5 0 5 10 15
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
1 GHz
2 GHz
5 GHz
8 GHZ
Output Power (dBm)
Input Power (dBm)
-20 -15 -10 -5 0 5 10 15 20 25 30
-60
-50
-40
-30
-20
-10
0
10
f
LO
=3.4 GHz, f
RF
=3.2 GHz
IIP3 = 18 dBm
OIP3 = -9 dBm
Fundamental
Third Order
Output Power (dBm)
Input Power (dBm)
-20 -15 -10 -5 0 5 10 15 20 25 30 35
-50
-40
-30
-20
-10
0
10
20
f
LO
=5.3 GHz, f
RF
=5 GHz
IIP3 = 22.3 dBm
OIP3 = 2.7 dBm
Fundamental
Third Order
Output Power (dBm)
Input Power (dBm)
a b
c
d
94
5.4 T-gate aligned nanotube transistor-based mixer
Armed with above-mentioned linearity, we further applied aligned nanotube radio
frequency transistors for analog circuits in the following part. The first example is mixer.
Aligned nanotube transistor-based mixer is configured by mixing the LO and RF signals at
the gate (Figure 5.3a). Figure 5.4a shows the output spectrum of mixer with the transistor
biased at V GS = 0 V and VDS = -0.6 V . The RF input frequency fRF is 1 GHz of power -14
dBm and the local oscillator frequency f LO is 1.2 GHz of power -3.5 dBm. One can find the
intermediate frequency (IF) fIF at fLO - fRF = 200 MHz and fLO + fRF = 2.2 GHz. The
conversion gain of this nanotube-transistor-based mixer is about –24.5 dB with the IF
output power of -38.5 dBm as shown in Figure 5.4a. Figure 5.4b shows that the conversion
gain varied as the gate voltage swept from -1 V to 1 V . The first peak of the conversion
gain at V GS = -0.7 V may result from the maximum transconductance gm at this bias (Figure
5.1f). While the second peak occurs nearby the minimum current point of IDS-VGS curve
(Figure 5.1e), and it has been discussed that the minimum current point is the optimal bias
point for the conversion gain of ambipolar transistor-based mixer in previous report.
27
We
further achieved mixing for frequency range from 1 GHz to 8 GHz. Figure 5.4c presents
the conversion gain of the aligned nanotube RF transistor as a function of applied frequency.
The result illustrates that conversion gain does not decrease much even when the frequency
goes up to 8 GHz. On the basis of the information above, carbon nanotube transistors show
95
great potential for mixer applications.
0.4 0.8 1.2 1.6 2.0 2.4 2.8
-60
-50
-40
-30
-20
-10 VGS = 0 V, VDS = -0.6 V
2LO
LO+RF
2RF
LO
IF= LO-RF
Power (dBm)
Frequency ( GHz)
RF
0 1 2 3 4 5 6 7 8
-32
-31
-30
-29
-28
-27
-26
-25
-24
Conversion Gain (dB)
Frequency (GHz)
Conversion gain
-1.0 -0.5 0.0 0.5 1.0
-38
-36
-34
-32
-30
-28
-26
-24
Conversion Gain (dB)
V
gs
(V)
VDS = -0.6 V
a
b
c
96
Figure 5. 4 Mixer application of self-aligned T-gate aligned nanotube transistor. (a) Output
spectrum for an aligned nanotube mixer, which shows the first, second, and third order
mixing products with a high conversion gain of -24.5 dB at LO power of -3.5 dBm. (b)
Conversion gain versus gate voltage for aligned nanotube mixer. (c) Conversion gain
versus frequency for aligned nanotube mixer.
5.5 T-gate aligned nanotube transistor-based frequency doubler
Other than amplifiers and mixers, aligned carbon nanotube transistors can find
applications in frequency doubling circuit based on the ambipolar transport property.
28
Figure 5.5a shows the transfer characteristic of an aligned carbon nanotube array transistor.
We can see that this nanotube transistor behaves nearly symmetrically around the minimum
current point (Vmincurrent = 1.2 V). A frequency doubler consisted of this device is achieved
with a circuit diagram as shown in Figure 5.5b. A current source with Idd = 830 µA is
connected to the drain electrode of the carbon nanotube transistor. In Figure 5.5c, we added
a 10 KHz input signal with a peak-to-peak a.c. voltage Vpp = 450 mV to a DC voltage Vg,DC
= 0.2 V (black curve) and Vg,DC = 1.2 V (red curve) to the gate of the nanotube transistor,
separately. The output waveforms from different bias region are illustrated in Figure 5.5c.
Based on Figure 5.5c, the red curve biased around the minimum current point presents a
sinusoidal wave with a doubled frequency. In comparison, the black curve biased in the
linear amplification region shows a sinusoidal wave with the same frequency as the input
signal. In Figure 5.5d, we also achieved the doubled frequency output (red curve) with 50
97
KHz input signal of Vpp = 500 mV biased at Vg,DC = 1.5 V . Then we further characterized
the frequency doubling function of the aligned nanotube transistor up to gigahertz range
with the help of spectrum analyzer, as shown in the schematic diagram of Figure 5.5e. The
output spectrums captured by the spectrum analyzer are presented in Figure 5.5f and 5g. In
Figure 5.5f, it can be noticed that the peak of output spectrum locates at frequency of 200
MHz, corresponding to an input signal with 100 MHz frequency, showing excellent
frequency doubling function. As shown in Figure 5.5g, even when the input frequency
increases up to 500 MHz, the output spectrum still has strong concentration at frequency
of 1 GHz. We also performed the doubler measurement with input frequency of 1 GHz,
and the results show that the output power concentrated mainly at doubled frequency 2
GHz. Our results clearly shows that aligned carbon nanotube transistors with ambipolar
transport property can serve as frequency doubler up to gigahertz regime in high-frequency
application. Our frequency doubler performance measured up to 1 GHz compares
favorably with previously reported results for carbon nanotubes. For instance, Wang et al.
reported a frequency doubler based on nanotube transistor operated in 1 KHz region.
28
We
attribute the good performance of our transistors to the self-aligned T-gate transistor design
and the resulting high extrinsic ft and fmax.
98
Figure 5. 5 Frequency doubler application of self-aligned T-gate aligned nanotube
transistor. (a) IDS-V GS curve of an ambipolar aligned nanotube transistor. (b) Circuit
schematic of an aligned nanotube frequency doubler with measurement setup using an
oscilloscope. (c,d) Output waveforms of frequency doubler in linear amplification region
and doubler region with sinusoidal wave with input Vpp = 450 mV at frequency of 10 KHz
(c) and input Vpp = 500 mV at frequency of 50 KHz (f). (e) Schematic of frequency doubler
with measurement setup using a spectrum analyzer. (f,g) Output spectrum of frequency
doubler with a 100 MHz input signal with power level of 0 dBm (f) and a 500 MHz input
signal with power level of 5 dBm (g).
5.6 Summary
In summary, we constructed T-gate aligned nanotube array RF transistors with the
extrinsic current-gain cut-off frequency of 25 GHz as the best on-chip performance for
nanotube RF transistors reported to date. Correspondingly, the intrinsic current-gain cut-
-0.22
-0.20
-0.18
-0.16
-0.14
-0.12
Voltage (V)
50 s/grid
Linear
-0.23
-0.22
-0.21
-0.20
-0.19
-0.18
-0.17
-0.16
Doubler -0.26
-0.24
-0.22
-0.20
-0.18
-0.16
-0.14
Voltage (V)
20 s/grid
Linear
-0.24
-0.22
-0.20
-0.18
Doubler
0.2 0.4 0.6 0.8 1.0 1.2 1.4
-70
-65
-60
-55
-50
-45
-40
-35
-30
Power (dBm)
Frequency ( GHz)
Input f = 500 MHz
f = 1 GHz
100 150 200 250
-70
-65
-60
-55
-50
-45
-40
-35
-30
Power (dBm)
Frequency ( MHz)
Input f = 100 MHz
f = 200 MHz
0.0 0.5 1.0 1.5 2.0
-0.65
-0.70
-0.75
-0.80
-0.85
-0.90
-0.95
VDS = -0.2 V
Drain Current (mA)
Gate Voltage (V)
a b c d
e f g
99
off frequency of 102 GHz was achieved after de-embedding, which is among the highest
value for nanotube-based RF transistors. Furthermore, we studied the linearity properties
of aligned nanotube transistors through single-tone (P1dB) and two-tone (IP3)
measurements with direct 50 Ω termination up to 8 GHz. Armed with the excellent extrinsic
RF performance, we configured nanotube-based circuits including a mixer and a frequency
doubler, operated in the gigahertz frequency regime. Our work confirms the great potential
of carbon nanotubes for radio frequency applications, and the self-aligned T-gate RF
transistor design may become a building block for future nanotube-based RF transistors
and circuits.
100
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Enaya, H. A.Zhou, C. W., Self-Aligned T-Gate High-Purity Semiconducting
Carbon Nanotube RF Transistors Operated in Quasi-Ballistic Transport and
Quantum Capacitance Regime. ACS nano 2012, 6, 6936-6943.
16. Steiner, M.; Engel, M.; Lin, Y . M.; Wu, Y . Q.; Jenkins, K.; Farmer, D. B.; Humes,
J. J.; Yoder, N. L.; Seo, J. W. T.; Green, A. A.; Hersam, M. C.; Krupke, R.Avouris,
P., High-frequency performance of scaled carbon nanotube array field-effect
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Payne, J.; Stuenkel, M.; Zhang, H.; Banks, T.; Feng, M.; Rotkin, S. V .Rogers, J. A.,
High-Frequency Performance of Submicrometer Transistors That Use Aligned
Arrays of Single-Walled Carbon Nanotubes. Nano Lett 2009, 9, 1937-1943.
18. Wang, C.; Zhang, J. L.; Ryu, K. M.; Badmaev, A.; De Arco, L. G.Zhou, C. W.,
Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for
Display Applications. Nano letters 2009, 9, 4285-4291.
19. Wang, C.; Zhang, J. L.Zhou, C. W., Macroelectronic Integrated Circuits Using
High-Performance Separated Carbon Nanotube Thin-Film Transistors. ACS nano
2010, 4, 7123-7132.
20. Han, S.; Liu, X. L.Zhou, C. W., Template-free directional growth of single-walled
carbon nanotubes on a- and r-plane sapphire. Journal of the American Chemical
Society 2005, 127, 5294-5295.
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nanotubes and their use in thin-film transistors. Small 2005, 1, 1110-1116.
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Y . C.Zhou, C. W., Synthesis and device applications of high-density aligned carbon
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102
24. Che, Y . C.; Wang, C.; Liu, J.; Liu, B. L.; Lin, X.; Parker, J.; Beasley, C.; Wong, H.
S. P.Zhou, C. W., Selective Synthesis and Device Applications of Semiconducting
Single-Walled Carbon Nanotubes Using Isopropyl Alcohol as Feedstock. ACS nano
2012, 6, 7454-7462.
25. Badmaev, A.; Che, Y . C.; Li, Z.; Wang, C.Zhou, C. W., Self-Aligned Fabrication of
Graphene RF Transistors with T-Shaped Gate. ACS nano 2012, 6, 3371-3376.
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103
Chapter 6: Conclusions and Future Directions
6.1 Conclusion
As discussed in Chapter 2 to 5, I have explored the potential of graphene and carbon
nanotube transistors in nanoelectronics and radio frequency electronics application through
the new material synthesis method and novel device design. As presented in Chapter 4 and
5, carbon nanotube RF transistors can reach current-gain cut-off frequency above 100 GHz,
as a great platform for practical analog circuit application. Furthermore, carbon nanotube,
as one-dimensional material, has the inherent property of high linearity due to ballistic
transport and quantum capacitance operation, which enable high-linear amplification
circuit applications.
1
Our single tone and two tone linearity measurement further confirm
the linearity performance of T-gate nanotube RF transistors.
2, 3
Among the current research
study in nanotube RF applications, there is limited result about system-on-chip study with
carbon nanotube transistors.
4, 5
Our platform of self-aligned T-shaped gate design is
compatible with CMOS fabrication, which makes the hybrid circuit of carbon nanotube
and traditional silicon CMOS technology feasible. With these conditions, it is of great
importance and meaning to configure carbon nanotube-based analog circuits integrated
with CMOS technology.
104
6.2 Future directions
Our original self-aligned T-gate design was based on the self-oxidized aluminum
oxide (2~3 nm) as the gate dielectric and aluminum metal as the gate electrode. In theory,
RF device performance, especially the power gain cut-off frequency, rely on the layout
design of transistors. To meet the requirement of circuit and system applications, the device
design can be further optimized through utilizing high-conductivity gate metal for smaller
gate resistivity and high-ҡ dielectric for better linearity. On the other hand, in material
aspect, carbon nanotubes also play an important role in device performance. High-purity
semiconducting nanotubes with large diameter have small bandgap, resulting in smaller
contact resistance and better conductivity in transistor performance. As a result of the
smaller contact resistance, carbon nanotube transistors made of large diameter carbon
nanotubes can perform more obvious saturation behavior in output characteristics, which
is the condition for better power gain of semiconducting transistors. In this way, it is very
meaningful to study the diameter dependence of carbon nanotubes on radio frequency
performance and to achieve better high frequency performance with large diameter
nanotubes.
Noise figure, defined as the ratio of the signal-to-noise power ratio at the input to
the signal-to-noise power ratio at the output in a two port circuit network, is another crucial
figure of merit for analog circuit application besides linearity. In order to further explore
105
the potential of carbon nanotube transistors in analog circuit application, it is necessary to
analyze the noise figure of carbon nanotube-based low noise amplifier/power amplifier.
The parameters of noise figure and linearity can serve as the foundation for the future
research on carbon nanotube-based high frequency circuit and systems. Nowadays, “quite”
(low noise) and highly-linear transistors are significant for the future development.
In flexible electronics field, low-cost, large-area and high-performance electronics
is highly required. In spite of a lot of previous studies made in this field, some materials
widely used such as polymers and small molecule organic films still have relatively poor
performance in flexible circuits. Carbon-based material including both carbon nanotube
and graphene films, have been proven to have great flexibility due to their unique
geometrical structure. Previous work about carbon nanotube transistors on PET substrate
shows the great potential of carbon nanotube in flexible electronics application.
6
Thus,
carbon nanotube-based flexible transistors and circuits is an interesting topic in the next-
generation electronic applications.
6.2.1 Future directions on radio frequency transistor optimization
Objective 1. Optimize carbon nanotube transistor design
The effects of the gate dielectric and gate metal of top-gate device can be studied to
optimize the radio frequency performance. We will first fabricate new generation of T-gate
106
carbon nanotube transistor with thicker dielectric through atomic layer deposition (ALD)
and highly-conductive metal (Ti/Au), then compare device performance of original
aluminum gate to that of the new-generation transistors. We aim to achieve better high
frequency performance by applying optimized dielectric, improving gate charging
resistance, and shorting the channel length.
We first optimized the transistor design by changing aluminum gate with high
conductive metal. For the gate deposition, we first evaporated the 2 nm of aluminum and
oxidized it to Al2O3 as gate dielectric. Then 5 nm/100 nm of Ti/Au was deposited as the
gate metal.
Figure 6.1 presents the top-view scanning electron microscope (SEM) images of T-
gate of self-oxidized aluminum (a) and Ti/Au gate electrode (b).
Figure 6. 1 SEM of aluminum gate (a) and ALD with Ti/Au gate (b)
Al: 50~80 nm length Ti/Au: 100~150 nm length
a b
107
Figure 6. 2 Radio frequency performance of carbon nanotube transistor with aluminum
gate (a) and Ti/Au gate (b).
In figure 6.2, we characterized the radio frequency of carbon nanotube transistors
with different device design. It illustrates that carbon nanotube with improved design
(black curve) has higher current-gain cut-off frequency and maximum power gain
frequency than original design with similar device geometry (red curve).
Objective 2. Diameter dependence of carbon nanotube RF transistors
100MHz 1GHz 10GHz
-10
0
10
20
30
40
50
Current Gain (dB)
Frequency
dB(h21) Ti/Au
dB(h21) Al
ft (Ti/Au) = 37GHz
ft (Al) = 5.5 GHz
100MHz 1GHz 10GHz
-10
-5
0
5
10
15
20
25
30
Power Gain (dB)
Frequency
MaxGain1_Ti/Au
MaxGain1_Al
fmax ( Ti/Au) = 20 GHz
fmax (Al) = 6.5 GHz
a b
108
Figure 6. 3 (a) SEM of large diameter separated nanotube thin film. (b) Optical absorption
spectra of large diameter separated nanotubes.
As known, contact resistance is of great importance for short channel transistor
performance. In our T-shape gate nanotube transistor, we use palladium (large work
function metal) to achieve ohmic contact with pre-separated nanotubes. The diameter of
the solution-based carbon nanotubes used in previous work is around 1.3 to 1.5 nm. It is
known that nanotube with smaller bandgap usually have smaller contact resistance than
that with larger bandgap, while contact resistance is a key factor for radio frequency
performance. Thus, we introduced larger diameter nanotubes which have smaller bandgap
into T-gate radio frequency transistor fabrication. We applied the high-purity
semiconducting nanotube with average diameter of 1.6~1.8 nm as shown in Figure 6.3 in
our transistor fabrication.
1 µm
a b
109
Figure 6. 4 Transfer characteristics of self-aligned T-gate transistor made of smaller
diameter (~1.4 nm) and larger diameter (~1.6 nm).
Figure 6. 5 Transconductance versus gate voltgae of self-aligned T-gate transistor made of
smaller diameter (~1.4 nm) and larger diameter (~1.6 nm).
-1.5 -1.0 -0.5 0.0 0.5 1.0
0
-10
-20
-30
-40
-50
-60
Vds = -1.5V
Drain Current ( A/ m)
Gate Voltage (V)
-1.5 -1.0 -0.5 0.0 0.5 1.0
-6
-8
-10
-12
-14
-16
-18
-20
-22
Vds = -1.5V
Drain Current ( A/ m)
Gate Voltage (V)
Large diameter small diameter
-1.5 -1.0 -0.5 0.0 0.5 1.0
0
5
10
15
20
25
Vds = -1.5V
gm ( S/ m)
Gate Voltage (V)
-1.5 -1.0 -0.5 0.0 0.5 1.0
0
10
20
30
40
50
60
Vds = -1.5V
gm ( S/ m)
Gate Voltage (V)
Large diameter small diameter
110
Figure 6. 6 Output characteristics of self-aligned T-gate transistor made of smaller
diameter (~1.4 nm) and larger diameter (~1.6 nm).
We measured the DC performance of T-gate device with larger diameter nanotubes
including transfer and output characteristics. Based on analysis of Figure 6.4 and 6.5, we
can noticed that the large diameter carbon nanotube transistors have high conductivity and
transconductace. The transconductance gm can go up to 60 µs/µm, which is about three
times larger than the previous small diameter transistor. As a result, the device performance
can be improved three times by theatrical estimation of ft = gm/2πCgs. Moreover, from the
output characteristics presented in 6.6, the large diameter carbon nanotube transistor with
smaller contact resistance shows obvious saturation behavior compared with normal
nanotube transistors. It predicts a higher power gain cut-off frequency for these CNTFETs.
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
Drain Current (mA)
Drain Voltage (V)
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
-1000
-800
-600
-400
-200
0
Drain Current ( A)
Drain Voltage (V)
Larger diameter Smaller diameter
111
Figure 6. 7 Maximum available gain of large diameter carbon nanotube RF transistors
As shown in Figure 6.7 above, the cut off frequency about 50 GHz and more
importantly, power gain frequency about 40 GHz (one of the best performance reported
to the date) has been achieved after the device optimization.
100MHz 1GHz 10GHz
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Ch31_R4C6_Vds=1.5Vgs=-1_de_ft.txt
Gain (dB)
freq
dB(h21)
ft= 47GHz
100MHz 1GHz 10GHz 100GHz
-10
-5
0
5
10
15
20
25
30
Ch32_R4C2_Vds=1.5Vgs=-1.3_de_fmax.txt
Gain (dB)
freq
MaxGain1
fmax=39GHz
112
Figure 6. 8 Statistic study of power gain cut-off frequency of small diameter and large
diameter carbon nanotube transistors.
According to the statistic result illustrated in Figure 6.8, it has been proven that
large diameter carbon nanotube transistors can offer higher power gain cut-off frequency
compared with normal nanotube transistors in average. All these preliminary results make
the large diameter carbon nanotube very promising material in the radio frequency
electronics application. In the next step, we are planning to apply these high-performance
transistor in circuit applications.
Large Diameter Normal
-10
0
10
20
30
40
Samples
fmax (GHz)
Large Diameter
Normal
113
6.2.2 Future directions on radio frequency circuit configuration
Objective 3. Noise figure measurement of carbon nanotube transistor-based RF circuit.
In this project, we plan to characterize the noise of carbon nanotube RF transistors.
Moreover, we will set up the simple nanotube-based analog circuit (e.g. Mixer or amplifier).
Based on the configured circuits and the primary result from transistor noise, we will bring
out different measurement strategy for noise figure characterization.
Based on the high performance achieved in 6.2.1, we plan to configure amplifier circuit of
carbon nanotube transistor with matching network. We will first investigate the device
parameters through the small-signal modeling based on the S-parameters captured by
Vector Network Analyzer (VNA).
The small signal model extracted from RF measurement can serve as a foundation
for analog circuit design. With the help of advanced design system (ADS), we can derived
the circuit parameters and configure the amplifier circuit of positive power gain. Figure 6.9
shows the schematic diagram of carbon nanotube-based low noise amplifier. Here, in order
to reduce the difficulty, we plan to do wire-bonding of carbon nanotube transistors and then
connect it to the passive components (capacitor and inductor) on PCB board. After we
prove the analog circuit with this method, we aim to combine carbon nanotube transistors
with PICS (passive integrated component substrate) technology in order the study the
potential of hybrid circuit.
114
Figure 6. 9 Low noise amplifier schematic
The noise figure has been defined the ratio of the signal-to-noise power ratio at
the input to the signal-to-noise power ratio at the output in a network.
𝑭 =
𝑺𝒊 / 𝑵𝒊
𝑺𝒐 / 𝑵𝒐
Thus the noise figure of a network is the decrease or degradation in the signal-to-
noise ratio as the signal goes through the network. A perfect amplifier would amplify the
noise at its input along with the signal, maintaining the same signal-to-noise ratio at its
input and output. A realistic amplifier, however, also adds some extra noise from its own
components and degrades the signal-to-noise ratio. A low noise figure means that very little
115
noise is added by the network. The concept of noise figure only fits networks (with at least
one input and one output port) that process signals. This note is mainly about two-port
networks; although mixers are in general three-port devices, they are usually treated the
same as a two-port device with the local oscillator connected to the third port. Figure 6.10
shows one of the methods to measure the noise figure with the aid of noise figure analyzer.
Figure 6. 10 Schematic of noise figure measurement by noise figure meter/analyzer
The degradation in a network’s signal-to-noise ratio is dependent on the
temperature of the source that excites the network. This can be proven with a calculation
116
of the noise figure F, where Si and Ni represent the signal and noise levels available at the
input to the device under test (DUT), So and No represent the signal and noise levels
available at the output. Na is the noise added by the DUT, and G is the gain of the DUT.
The following equation shows the dependence on noise at the input Ni.
𝑭 =
𝑺𝒊 /𝑵𝒊 𝑺𝒐 /𝑵𝒐 =
𝑵𝒂 + 𝑮𝑵𝒊 𝑮𝑵𝒊
Device modeling is important for measuring and reducing the noise. Through
simulation and modeling, the circuit model of carbon nanotube RF devices can be carried
out. Passive integrated circuit (PIC) can be integrated with our active devices and
maximum gain and optimization of noise reduction can be realized.
6.2.3 Future directions on flexible radio frequency electronics
Objective 4. Flexible Radio Frequency transistor
Carbon nanotube and graphene films are proved to be flexible. After traditional fabrication
of RF transistors on substrate (thin polyimide films on silicon handling wafers), we plan to
transfer the device to flexible substrate (PET). It will be very interesting to test the transistor
performance in in-situ flexibility measurement.
117
Figure 6. 11 Schematic of T-gate design and process flow chart for flexile thin film
transistors
Based on the previous work, Solution-processed carbon nanotube thin film-based
flexible transistors have been realized with high-performance, low-cost, and ambient
stability. The corresponding peak effective device mobility for the thin-film transistor on
flexible substrate is reported to be around 50 cm
2
V
–1
s
–1
. With the records, we plan to first
transfer/deposit carbon nanotube arrays/networks on thin polyimide film on silicon
118
substrate. Then standard optimized T-gate design will be applied on the nanotube material.
After the process of self-aligned T-gate structure, the carbon nanotube transistors can be
transferred onto flexible substrate such as PET, following by the flexibility measurement.
119
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Abstract (if available)
Abstract
In this dissertation, I discuss the solution for the major challenge for carbon nanotube‐based nanoelectronics, and explore the radio frequency application of carbon‐based material including graphene and nanotube. ❧ Chapter 1 is a brief introduction of carbon nanotube and graphene in electronics field as the foundation for the whole dissertation. Chapter 2 to 5 report the work I have finished in the past four and half years. Chapter 6 discusses the future directions of carbon‐based nanoelectronics. ❧ Chapter 2 reports a method we developed to obtain predominantly semiconducting nanotubes from direct CVD growth. By using isopropanol as the carbon feedstock, semiconducting nanotube purity of above 90% is achieved, which is unambiguously confirmed by both electrical and micro‐Raman measurements. Mass spectrometric study was performed to elucidate the underlying chemical mechanism. Furthermore, high performance thin‐film transistors with an on/off ratio above 10⁴ and mobility up to 116 cm²/V∙s have been achieved using the isopropanol‐synthesized nanotube networks grown on silicon substrate. The method reported in this contribution is easy to operate and the results are highly reproducible. Therefore, such semiconducting predominated single‐walled carbon nanotubes could serve as an important building block for future practical and scalable carbon nanotube electronics. ❧ Chapter 3 presents a scalable method for fabrication of self‐aligned graphene transistors by defining T‐shaped gate on top of graphene, followed by self‐aligned source and drain formation by depositing Pd with the T‐gate as a shadow mask. This transistor design provides significant advantages such as elimination of misalignment, reduction of access resistance by minimizing ungated graphene, and reduced gate charging resistance. To achieve high yield scalable fabrication, we have combined the use of large‐area graphene synthesis by chemical vapor deposition, wafer scale transfer, and e‐beam lithography to deposit T‐shaped top gates. The fabricated transistors with gate lengths in the range of 110 to 170 nm exhibited excellent performance with peak current density of 1.3 mA/µm and peak transconductance of 0.5 mS/µm, which is one of the highest transconductance values reported. In addition, the T‐gate design enabled us to achieve graphene transistors with extrinsic current‐gain cut‐off frequency of 23 GHz and maximum oscillation frequency of 10 GHz. These results represent important steps toward self‐aligned design of graphene transistors for various applications. ❧ In Chapter 4, we introduce the self‐aligned fabrication method for carbon nanotube RF transistors. In this way, the channel length can be scaled down to 140 nm which enables quasi ballistic transport, and the gate dielectric is reduced to 2-3 nm aluminum oxide, leading to quasi quantum capacitance operation. A current‐gain cut‐off frequency (ƒt) up to 22 GHz and a maximum oscillation frequency (ƒmax) of 10 GHz are demonstrated. Furthermore, the linearity properties of nanotube transistors are characterized by using the 1-dB compression point measurement with positive power gain for the first time, to our knowledge. Our work reveals that the importance and potential of separated semiconducting nanotubes for various RF applications. ❧ Chapter 5 discusses about the aligned nanotube transistor study and further explores radio frequency circuit application of aligned nanotube array transistors. We constructed T‐gate aligned nanotube array RF transistors with the extrinsic current‐gain cut‐off frequency of 25 GHz as the best on‐chip performance for nanotube RF transistors reported to date. Correspondingly, the intrinsic current‐gain cut‐off frequency of 102 GHz was achieved after de‐embedding, which is among the highest value for nanotube‐based RF transistors. Furthermore, we studied the linearity properties of aligned nanotube transistors through single‐tone (P1dB) and two‐tone (IP3) measurements with direct 50 Ω termination up to 8 GHz. Armed with the excellent extrinsic RF performance, we configured nanotube‐based circuits including a mixer and a frequency doubler, operated in the gigahertz frequency regime. Our work confirms the great potential of carbon nanotubes for radio frequency applications, and the self‐aligned T‐gate RF transistor design may become a building block for future nanotube‐based RF transistors and circuits. ❧ In Chapter 6, future direction on carbon‐based material nanoelectronincs is briefly discussed. In the field of radio frequency (RF) electronics, RF device design can be further optimized for better performance. Noise figure is another important figure of merit for RF transistors and circuits beside linearity. With the excellent transistor performance achieved in previous work, I propose to further realize amplifier circuit with positive gain such as low noise amplifier (LNA) and power amplifier (PA). Through combing the CMOS technology platform with the carbon‐based radio frequency transistors, we can study the CMOS-Carbon hybrid radio frequency circuit to fulfill the advantage of the low cost for traditional CMOS technology and the high performance provided by carbon‐based nanomaterial. It will be meaningful to further analyze the noise figure of the carbon nanotube‐based as the important parameter of nanotube RF transistors. As an interesting topic, flexible analog electronics based on nanotube material based on T‐gate design may have the potential in higher performance in flexible electronics field. ❧ In summary, this dissertation starts from the material synthesis and preparation to the device and circuit application of carbon‐based material. The electronic application shows the great potential of carbon‐based material in the nanoelectronics and radio frequency electronics. It can be predicted that carbon-based material nanoelectronics is very promising for beyond silicon electronics due to the unique electronic properties.
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University of Southern California Dissertations and Theses
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Asset Metadata
Creator
Che, Yuchi
(author)
Core Title
Carbon material-based nanoelectronics
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
04/29/2014
Defense Date
03/24/2014
Publisher
University of Southern California
(original),
University of Southern California. Libraries
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Tag
carbon nanotube,circuit,graphene,nanoelectronics,OAI-PMH Harvest,radio frequency,transistor
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Language
English
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Zhou, Chongwu (
committee chair
), Cronin, Stephen B. (
committee member
), Wu, Wei (
committee member
)
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cycyucy@gmail.com,cycyucy@hotmail.com
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https://doi.org/10.25549/usctheses-c3-404967
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Che, Yuchi
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Tags
carbon nanotube
circuit
graphene
nanoelectronics
radio frequency
transistor