Gallium arsenide nanosheets: study of stacking-fault-free nano-structure and its applications on semiconductor devices

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Content GALLIUM ARSENIDE NANOSHEETS: STUDY OF
STACKING-FAULT-FREE NANO-STRUCTURE AND ITS
APPLICATIONS ON SEMICONDUCTOR DEVICES

by

Chun-Yung Chi

A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree of
DOCTOR OF PHILOSOPY
(ELECTRICAL ENGINEERING)

May 2015

Copyright 2015 Chun-Yung Chi
1

Content
List of Figures ........................................................................................................... 3
Chapter 1 Introduction ............................................................................................... 9
1.1 Motivation ................................................................................................... 9
1.2 Metal Organic Chemical Vapor Deposition ................................................. 11
1.3 Selective Area Growth ............................................................................... 13
1.4 Process ...................................................................................................... 14
1.5 Thesis overview ......................................................................................... 17
1.6 Reference ................................................................................................... 20
Chapter 2 GaAs nanowire growth on Silicon ........................................................... 23
2.1 Introduction ............................................................................................... 23
2.2 Growth on non-polar surface ...................................................................... 24
2.2.1 (111) Silicon surface ........................................................................ 24
2.3 Growth condition ....................................................................................... 29
2.4 Experimental results .................................................................................. 31
2.4.1 Hydrogen annealing step: ................................................................ 31
2.4.2 Nucleation step:............................................................................... 38
2.4.3 Crystal quality of GaAs nanowires on (111) Silicon ......................... 46
2.5 Conclusion ................................................................................................. 48
2.6 References ................................................................................................. 50
Chapter 3 Growth of twin-free GaAs nanostructure ................................................. 52
3.1 Introduction ............................................................................................... 52
3.2 Growth Method.......................................................................................... 54
3.3 Experimental Results ................................................................................. 55
3.3.1 GaAs nanosheet on (111)B GaAs substrate ...................................... 55
3.3.2 GaAs nanosheet on (100) GaAs substrate ........................................ 66
3.4 Discussion ................................................................................................. 70
3.5 Conclusions ............................................................................................... 78
3.6 Reference ................................................................................................... 79
Chapter 4 Growth of GaAs thin-film on lattice-mismatched substrate ...................... 82
4.1 Introduction ............................................................................................... 82
4.2 Growth mode on lattice mismatched substrate ............................................ 82
4.3 Growth on non-polar surface ...................................................................... 85
4.3.1 100 Silicon surface .......................................................................... 85
4.4 Experimental results .................................................................................. 86
4.4.1 Growth on (111)B GaP substrates .................................................... 91
4.4.2 Growth on (100) GaP substrate ........................................................ 98
2

4.4.3 Growth on (111) Silicon substrates ................................................. 107
4.4.4 Growth on (100) Silicon substrates ................................................. 114
4.5 Reference .................................................................................................. 122
Chapter 5 Double Al
x
Ga
1-x
As passivation and wet oxidation on GaAs nanostructure
............................................................................................................................... 124
5.1 Introduction .............................................................................................. 124
5.2 Wet oxidation of AlGaAs .......................................................................... 125
5.3 Growth conditions .................................................................................... 126
5.4 Experimental Results ................................................................................ 127
5.4.1 Single QW structure on (100) GaAs substrate ................................. 127
5.4.2 GaAs nanosheet structures on (111)B GaP substrates ...................... 129
5.4.3 GaAs nanowire structure on (111) Silicon substrates ...................... 134
5.5 Dicussion .................................................................................................. 137
5.6 Reference .................................................................................................. 138
Chapter 6 Future work ............................................................................................ 140
6.1 Tri-gate transistor ...................................................................................... 140
6.2 Nanostructured solar cell ........................................................................... 142
6.3 Thin film tandem solar cell ....................................................................... 143
6.4 Reference .................................................................................................. 145
Bibliography .......................................................................................................... 148
3

List of Figures
Fig.1.1 Average daily solar radiation per month throughout US continent. ............... 10
Fig.1.2 Procedure of Selective-Area-Growth. (a) A thin dielectric layer is first
deposited on the substrate as a mask. (b) Nano patterns are defined with lithography
technique and transferred to dielectric layer by etching technique. (c) Nanostructures
are selectively grown on open regions. .................................................................... 15
Fig.1.3 SAG-MOCVD pattern design: nano pattern is surrounded by a fully open,
unmasked region, so called skirt region to absorb excess precursors. ....................... 16
Fig.2.2.1 Atomic configuration of Ga, As on (111) Si surface .................................. 25
Fig.2.2.2 Passivation of (111) Si .............................................................................. 27
Fig.2.2.3 Atomic configuration of Ga, As on (111) Si surface with steps .................. 28
Fig.2.2.4 As-passivation on (111) Si with steps ........................................................ 29
Fig.2.3.1 Growth condition of GaAs nanowire on (111) Si substrate ........................ 30
Fig.2.4.1 Diagrams of growth condition for L2891 and L2892 ................................ 33
Fig.2.4.2 SEM images of GaAs nanowire growth on (111) silicon substrate. (a)
hydrogen annealing at 860℃ for 20 minutes. (b) hydrogen annealing at 900℃ for
20 minutes. .............................................................................................................. 33
Fig.2.4.3 Diagram of growth condition for L2988.................................................... 35
Fig.2.4.4 SEM images of GaAs nanowires grown on (111) Si substrate with different
period of hydrogen anneal process ........................................................................... 36
Fig.2.4.5 Diagram of growth condition for L2989.................................................... 37
Fig.2.4.6 SEM images of GaAs nanowires grown on (111) Si substrate with different
hydrogen anneal temperature ................................................................................... 38
Fig.2.4.7 Diagrams of growth condition for L3107, L3112, L3113, L3128 and L3133
................................................................................................................................ 40
Fig.2.4.8 SEM images of GaAs nanowires grown with different nucleation
temperatures ............................................................................................................ 42
Fig.2.4.9 Diagram of growth condition for L3616.................................................... 44
4

Fig.2.4.10 SEM images of GaAs nucleation on (111) Si with high temperature
nucleation ................................................................................................................ 44
Fig.2.4.11 Diagram of growth condition for L3621 .................................................. 45
Fig.2.4.12 SEM images of GaAs nanowires on (111) Si substrate with high yield rate
................................................................................................................................ 45
Fig.2.4.13 Cross-section TEM images of GaAs nanowires on (111) Si ..................... 46
Fig.2.4.14 Cross-section TEM image of titled GaAs nanowire on (111) Si ............... 48
Fig. 3.3.1 (a) Macroscopic SEM image of nanosheet arrays. Nano-stripe pattern is 5
μm long and parallel to <11-2> direction. (b) Microscopic SEM image of a single
nanosheet. The inclined surfaces of the nanosheets are three {110} planes. (C)
Schematic diagram of a nanosheet as part of a <11-2>-oriented tetrahedron. ........... 56
Fig. 3.3.2 (a) Cross-section TEM image of a nanosheet from <1-10> zone axis. (b)
Cross-section TEM image of a nanosheet from <11-2> zone axis. (c) Cross-section
TEM of a nanowire at <1-10> zone axis. ................................................................. 57
Fig. 3.3.3 (a)~(c) SEM images of nanosheets grown under different growth conditions.
(d) Nanosheets growth with increased TMGa flow rate which shows suppression of
rotated triangular tip. (e) Nanosheets growth under V/III = 6 shows rotated triangular
near their tips. .......................................................................................................... 59
Fig. 3.3.4 (a) TEM image of cross-section nanosheet along <1-10>direction. The
nanosheet is composed of two stacking triangles; the upper triangle is 180° rotated
with similar feature of the beneath one. (b) HRTEM image of the boundary between
beneath and upper triangles. Stacking sequences of GaAs are different at the two sides
of the boundary which implies that this boundary is actually a twin plane. (c)~(e) FFT
images of different regions near twin plane. (f) Growth mechanism of twinned
nanosheets. .............................................................................................................. 62
Fig. 3.3.5 (a) Nanosheets growth on different length of nano-stripe patterns. (b) SEM
images of nanosheets growth on different nano-stripe patterns. Schematics of
nano-stripe patterns for nanosheets are shown in the insets. ..................................... 65
Fig.3.3.6 Schematic of different crystal orientations on (100) GaAs substrate. (a)
Side-view of (100) GaAs substrate along <011> direction. (b) Top view of (100)
GaAs substrate along <100> direction. .................................................................... 66
Fig.3.3.7 (a) Sample L4050, grown with TMGa 0.8 sccm, arsine 17 sccm (V/III
ratio 492); (b) Sample L4017, grown with TMGa 0.8 sccm, arsine 5 sccm (V/III ratio
5

144); (c) Sample L4018, grown with TMGa 0.8 scm, arsine 0.25 sccm (V/III ratio
7.24). 67
Fig.3.3.8 Sample L4069 (a) GaAs nanosheet on (100) GaAs substrate has two facets
on both sides of tilted planes. (b) Shorter nanosheets develop twin defect near the tip
of nanosheets. (c) Rotated triangles formed at the tip of nanosheet grown on (100)
GaAs substrate. ....................................................................................................... 68
Fig.3.3.9 Sample L4067 (a) No rotated triangles are observed at the tip of nanosheets.
(b) Shorter nanosheets stopped growing but longer nanosheets haven’t pinch off. .... 69
Fig. 3.4.1 (a) Schematic diagrams of twin-free and twinned cases for a nanowire
structure. (b) Schematic diagrams of twin-free and twinned cases for a nanosheet
structure. ................................................................................................................. 73
Fig. 3.4.2 (a) Total surface energy plus twin energy per unit volume for twin-free and
twinned nanowire structures. (b) Total surface energy plus twin energy per unit
volume for twin-free and twinned nanosheet structures with different length. .......... 77
Fig.4.2.1 Growth modes on lattice mismatched substrates. .............................. 84
Fig.4.4.1 SEM images of GaAs nanosheets on a (111) silicon substrate. .................. 87
Fig.4.4.2 SEM images of GaAs nucleation experiments with different periods. SEM
images of nucleation only and nucleation plus nanosheet growth are both shown. ... 89
Fig.4.4.3 TEM images of GaAs thin film growth (L3905) on (111) silicon. ............. 90
Fig. 4.4.4 Schematic image of nano-stripe patterns created by e-Beam lithography. . 91
Fig. 4.4.5 (a) Growth conditions of L4010. (b) SEM image of a single GaAs
nanosheet on (111)B GaP substrate. (c) SEM image of GaAs thin film grown from the
crossed nano-stripe pattern on a (111)B GaP substrate. (d) SEM image of GaAs thin
film grown from the crossed nano-stripe pattern on a (111)B GaAs substrate. .......... 93
Fig. 4.4.6 (a) Growth conditions of L4238. (b) Single GaAs nanosheet on a (111)B
GaP substrate. (c) Coalesced GaAs thin film from crossed nano-stripe pattern on a
(111)B GaP substrate. .............................................................................................. 95
Fig. 4.4.7 HRTEM images of GaAs nanosheets on a (111)B GaP substrate. (a),(b) A
single GaAs nanosheet on a (111)B GaP substrate. (c),(d) Coalesced GaAs thin film
grown on a crossed nano-stripe pattern on a (111)B GaP substrate. .......................... 96
Fig. 4.4.8 (a) Growth conditions of sample L4326. SEM images of GaAs nanosheets
grown on (100) GaP with different pitches. .............................................................. 99
6

Fig. 4.4.9 (a) Growth conditions of sample L4328. (b) Growth conditions of sample
L4329. (c) SEM image of L4328: GaAs nanosheets with 200 nm pitch. (d) SEM
image of L4329: GaAs nanosheets with 200 nm pitch. ........................................... 100
Fig. 4.4.10 (a) Growth conditions of sample L4333. (b) Growth conditions of sample
L4334. (c) SEM image of sample L4333. (d) SEM image of sample L4334. ........... 101
Fig. 4.4.11 TEM images of sample L4333. ............................................................. 102
Fig. 4.4.12 (a) Growth conditions of L4350. (b),(c) TEM images of sample L4350.103
Fig. 4.4.13 (a) Growth conditions of sample L4357. (b)~(e) SEM images of L4357:
GaAs nanosheets on a (111)B GaP substrate with misaligned nano-stripes along 15,
25, 35, and 45 degrees, respectively. ....................................................................... 105
Fig. 4.4.14 (a) Growth conditions of sample L4355. (b)–(d) TEM images of sample
L4355. .................................................................................................................... 106
Fig. 4.4.15 (a),(b) Two different nano-stripe pattern designs on a (111) silicon
substrate. (c) SEM image of GaAs nanosheet growth results on 1
st
pattern. (d) SEM
image of GaAs nanosheet growth results on 2
nd
pattern. ......................................... 108
Fig. 4.4.16 (a),(b) Discontinuous nano-stripe pattern designs on a (111) silicon
substrate. (b) SEM image of GaAs nanosheet growth result on 1
st
pattern. (d) SEM
image of GaAs nanosheet growth result on 2
nd
pattern. ........................................... 109
Fig. 4.4.17 (a) 1
st
and (b) 2
nd
discontinuous nano-stripe pattern designs on a (111)
silicon substrate. (c) SEM image of L4507: GaAs nanosheet growth results on the 1
st

pattern. (d) SEM image of L4507: GaAs nanosheet growth results on the 2
nd
pattern.
............................................................................................................................... 110
Fig. 4.4.18 TEM images of L4505 and L4507 on 1
st
and 2
nd
patterns. ..................... 111
Fig. 4.4.19 HRTEM image of L4507 ...................................................................... 112
Fig. 4.4.20 SEM image of L4620: GaAs nanosheet growth results on (111) silicon. (a)
GaAs nanosheet growth results of 1
st
pattern in Fig. 4.4.17. (b) GaAs nanosheet
growth results of 2
nd
pattern in Fig. 4.4.17. (c) Single GaAs nanosheet growth results
on <11-2> oriented nano-stripes. (d) Single GaAs nanosheet growth results on <1-10>
oriented nano-stripes. ............................................................................................. 113
Fig. 4.4.21 Growth results of sample L4674 with different orientation of nano-stripes.
Growth temperature: 690℃; nano-stripe pitch: 400 nm ......................................... 116
Fig. 4.4.22 Growth results as indicated by optical microscope images of sample
7

L4674 with different orientation of nano-stripes. Growth temperature: 690℃ ;
nano-stripe pitch: 200 nm ....................................................................................... 116
Fig. 4.4.23 TEM images of L4674: GaAs thin film grown from nano-stripes on (100)
silicon substrate ...................................................................................................... 117
Fig. 4.4.24 Optical micrographs of sample L4675 showing growth results with
different orientation of nano-stripes. Growth temperature: 640℃; nano-stripe pitch:
400 nm ................................................................................................................... 118
Fig. 4.4.25 Growth results of sample L4675 with different orientation of nano-stripes.
Growth temperature: 640℃; nano-stripe pitch: 200 nm ......................................... 119
Fig. 4.4.26 (a) sample L4674, growth temperature 690℃, nano-stripe pitch 200 nm,
(b) sample L4674, growth temperature 690℃, nano-stripe pitch 400 nm, (c) sample
L4675, growth temperature 640℃, naon-stripe pitch 200 nm, (d) sample L4675,
growth temperature 640℃, naon-stripe pitch 400 nm. ........................................... 120
Fig. 4.4.27 TEM images of L4675. (a),(b) GaAs thin film from 45-degree nano-stripe
pattern. (c),(d) GaAs thin film grown from 80-degree nano-stripe pattern. .............. 121
Fig. 5.4.1 Schematic of a single QW structure on a (100) GaAs substrate. L4296: The
QW is protected by a single Al
x
Ga
1-x
As layer. L4297: The QW is protected by two
Al
x
Ga
1-x
As layers. L4456: The QW is protected by a thick Al
x
Ga
1-x
As layer. .......... 127
Fig. 5.4.2 PL results for L4296, L4297 and L4456. The numbers after the sample
number denote different measurement spots. (a) PL result for L4296 and L4297:
comparison of the single and double passivation effects. (b) PL result for L4296 and
L4456: demonstration of the effect of the thickness of the Al
x
Ga
1-x
As layer on
passivation. (c) PL result for L4297 and L4456: comparison of the single and double
passivation effects with identical Al
x
Ga
1-x
As thicknesses. (d) PL result for L4297
before and after wet oxidization. ............................................................................. 128
Fig. 5.4.3 Schematic view of the cross-sectional structure of GaAs nanosheets with
AlGaAs passivation. L4482 is a bare GaAs nanosheet without an AlGaAs layer.
L4489 is a GaAs nanosheet with a 40 nm thick Al
0.8
Ga
0.2
As passivation layer. L4486
is a GaAs nanosheet with passivation layers of 20 nm Al
0.8
Ga
0.2
As and 20 nm
Al
0.9
Ga
0.1
As. ........................................................................................................... 130
Fig. 5.4.4 PL results for the GaAs nanosheet on a (111)B GaP substrate. The numbers
after the sample number denote different measurement spots. (a) PL results of sample
L4482, which is merely a bare GaAs nanosheet. (b) PL results of sample L4489: A
GaAs nanosheet with 40 nm Al
x
Ga
1-x
As. (c) PL results of sample L4486: A GaAs
8

nanosheet with double passivation layers. (d) PL results of sample L4486 after wet
oxidization. ............................................................................................................ 132
Fig. 5.4.5 Schematic view of the cross-sectional structure of a GaAs nanowire. L4601
is a bare GaAs nanowire. L4604 is a GaAs nanowire with a 10 nm thick Al
0.8
Ga
0.2
As
passivation layer. L4605 is a GaAs nanowire with a 20 nm thick Al
0.8
Ga
0.2
As
passivation layer. L4606 is a GaAs nanowire with 20 nm thick Al
0.8
Ga
0.2
As and
another 20 nm thick Al
0.9
Ga
0.1
As double passivation layers. ................................... 134
Fig. 5.4.6 PL results for GaAs nanowires on a (111) silicon substrate. The numbers
after the sample number denote different measurement spots. (a) PL results of sample
L4601: a bare GaAs nanowire structure. (b) PL results of sample L4604: a GaAs
nanowire with a 10 nm Al
0.8
Ga
0.2
As layer. (c) PL results of sample L4605: a GaAs
nanowire with a 20 nm Al
0.8
Ga
0.2
As layer. (d) PL results of sample L4606: a GaAs
nanowire with double passivation layers. ................................................................ 135
Fig. 5.4.7 PL results of sample L4606: double passivation layer structure after wet
oxidization ............................................................................................................. 136
Fig.6.1 (a) Schematic of silicon three-dimensional gate design. (b) Cross-section view
of three-dimensional gate ....................................................................................... 141
Fig.6.2 Cross-section view GaAs nanosheet (a) on silicon substrate and (b) coated
with AlGaAs shell. (c) AlGaAs shell oxidized after wet oxidization to form gate oxide.
(d) Cross-section view of tri-gate transistor made of GaAs nanosheet grown on silicon.
............................................................................................................................... 141
Fig.6.3 (a) Schematic design of nanosheet solar cell. (b) Simulated light absorption of
GaAs nanosheet solar cell. ...................................................................................... 143
Fig.6.4 (a) GaAsP nanosheet grown on silicon substrate. (b) Intersect nano-stripe
patterns or change growth condition to enhance lateral growth rate. (c) The as-grown
GaAsP thin film on nano-stripe pattern. .................................................................. 145
9

Chapter 1 Introduction
1.1 Motivation
Technology advanced in fast pace recent years, many facilities are created to
facilitate people’s life like cell phones, computers and lighting. These devices or
creations make people’s life more convenient; however they would cause another
problem: increasing energy consumption. Oil, nature gas and coal, the so called fossil
fuels are three main sources of energy which powered roughly 80% of the modern
societies. Fossil fuels produce significant atmospheric pollutions and greenhouse gas
when they are burned to generate energy; the increasing of energy consumption may
therefore result in increasing pollutions to the earth. Moreover, the storage of fossil
fuels is limited and could be used up one day. Therefore as energy consumption
increases, seeking green, alternative energy sources becomes more important.
Solar radiation, an easily accessible, pollution-free energy is one of green energy
to replace fossil fuels. The solar radiation is an instantaneous power density ranges
from 0 kW/m
2
at night to a maximum of 1 kW/m
2
during day time. Based on the
calculation using 37% as photo-electric conversion efficiency, the entire US electricity
demand can be provided by concentrator photovoltaic arrays on either 150 km x 150
km blue-area or ten 50 km x 50 km red-areas as depicted in Fig.1.1.

10

Fig.1.1 Average daily solar radiation per month throughout US continent.

It seems feasible to replace fossil fuels with photovoltaic cells; however
currently the highest photo-electric conversion efficiency of single junction silicon
photovoltaic is merely around 27.5% which quite approaches Shockley-Queisser limit.
To improve photo-electric conversion efficiency, different structures of photovoltaics
1

were proposed to reduce energy loss from hot carriers; for example:
intermediate-band cells
2
, hot carrier cells
3
, spectrum conversion cells
4
, and
multi-junction cells. Multi-junction cells or so called tandem solar cells stacks
materials with different band gaps to efficiently utilize photon energy and the
theoretic photo-electric conversion efficiency can approach 100% with multiple
material stackings. Due to lattice-mismatch and thermal expansion issues, from
crystal growth point of view, to grow materials layer-by-layer usually results in crystal
defects and those stacking defects would in turn degrade photovoltaic efficiency.
Recent years, studies of semiconductor nanostructures become more and more
popular due to its improved electrical and optical properties over its bulk counterparts.
They have been used in many applications like logic gates
5
, solar cells
6,7
, photo
detectors
8
and light emitting diodes
9–11
. The nano-size footprint of nanostructures is
helpful toward greatly reduce strain energy between lattice-mismatched materials and
11

elastically release accumulated strain energy during nanostructure growth. Therefore
nanostructure is considered as ideal structure to accomplish defect-free, high
efficiency multi-junction photovoltaic.
To better understand semiconductor nanostructure, crystal growth studies were
performed using Metal Organic Chemical V apor Deposition to achieve defect-free
III-V nanostructures for tandem photovoltaic applications.

1.2 Metal Organic Chemical Vapor Deposition
Semiconductor nanostructures can be achieved either by etching bulk material or
epitaxial growth. To obtain atomic-flat surface by etching techniques is a challenge
and because of homogeneous etching, high aspect ratio is difficult to achieve and may
cause a tapering issue. To well-control the morphology of the nanostructure, epitaxial
growth is preferred.
Two kinds of epitaxial growth techniques for nanostructures are Molecular Beam
Epitaxy (MBE) and Metal Organic Chemical Vapor Deposition (MOCVD). MBE
technique requires high vacuum for epitaxial growth and elemental sources, like
gallium or arsenic are used. Elemental sources are heated in effusion cells and
sublime as gaseous element. The growth starts when different reactants meet and react
on the wafer; for MOCVD, it doesn’t require high vacuum; epitaxial growth usually
takes place at 0.1atm. As described by its name, the process of epitaxial growth in
MOCVD utilizes vapor phase precursors which carry required elements for the target
material. Compared to MBE, the crystal growth rate of MOCVD is faster and the
most important thing: selective growth is difficult to achieve in MBE system therefore
nanostructure growth can only be done by Vapor-Solid-Liquid (VLS) technique. On
the other hand, both Selective-Area-Growth (SAG) and VLS growth techniques for
nanostructures are feasible in MOCVD system.
12

Epitaxial growth in MOCVD system relies on phase transformation from vapor
phase precursors to solid crystal layers on substrate. Precursors of group III metals,
like Ga and In used in MOCVD are usually metal-organic form because group III
elements are not volatile in normal growth temperature and pressure of MOCVD
system. Group V precursors, for example As and P have either metal-organic or
hydride forms. Metal-organic precursors are stored in the container, a so called
“bubbler” and carrier gas, either hydrogen or nitrogen, flows through the bubbler to
transport the vapor phase precursor stream. The amount of vapor phase precursor is
determined by the bubbler temperature and the pressure of bubbler outlet line. The
percentage of precursor at the bubbler outlet line can be represented as following
equation:
P

P

P

is the vapor pressure of the metal-organic precursor which is determined by
the bubbler temperature. P

is the pressure at the bubbler outlet line. The partial
pressures of each precursors in the reactor tube then can be determined as following
equation:
P

=P×
F

F

×
P

P

P

, P denote the partial pressure of group V or group III and the growth
pressure in the reactor respectively. F

and F

represent the flow rate of group
V or group III and total flow rate (carrier gas flow rate plus group III and group V
flow rate) in the reactor respectively.
When precursors are brought into the reactor tube by carrier gas, then they are
hydrodynamically transported from the gas inlet to the boundary layer for epitaxial
growth. The boundary layer is the region where velocity of laminar gas flow
uniformly decreases and finally approaches zero at the substrate surface. The velocity
13

difference within the boundary layer results in the gradient of precursor concentration
cross the boundary layer; therefore precursors can diffuse to the substrate surface.
The vapor phase group III or group V precursors in either metal-organic or
hydride forms are transported by carrier gas to the reactor through the boundary layer
and start the reaction when different reactants meet up. The epitaxial growth process
can be expressed by following chemical reactions:
R

A+BH

AB+nRH
R

A+R

′
B

AB+nRH+nR
′
H or AB+RR
′

A and B represent the element of group III or group V , R and R
′
represent
organic radical of unspecified form. In first equation describes the reaction when
metal-organic precursor of element A and hydride form precursor of element B are
used; in second equation, both precursors are metal-organic type. The cracking
process of precursors to break the bonds between group III, group V element and
organic radical or hydrogen atom is called pyrolysis. Precursors can be pyrolyzed in
two ways: homogeneous pyrolysis which occurs entirely in vapor phase or
heterogeneous pyrolysis which takes place at a solid surface.
In the whole process, precursors diffuse through the boundary layers then
pyrolyzed either homogeneously or heterogeneously to form single crystal layer upon
substrate surface.

1.3 Selective Area Growth
Two growth techniques are widely used to grow III-V nanowires:
vapor-liquid-solid (VLS) and selective area growth (SAG). Metal droplets, materials
with low eutectic point such as Au are required in VLS growth to serve as a catalyst to
14

incorporate the precursors from the vapor phase into the liquid phase at low
temperatures. The dissolved group-III and group-V atoms in the metal droplets then
precipitate at the metal/substrate boundary and deposit a thin layer of material
underneath the metal droplets. SAG, on the other hand, is carried out on a
nano-patterned substrate at higher temperatures that allow vapor phase precursors to
pyrolyze either homogeneously or heterogeneously at the substrate surface via a
vapor-solid transition resulting in layer growth without the need of a metal catalyst.
SAG is not used for nanowire growth but also for other applications such as laser
diodes
12
, DBR lasers
13
, mode profile converters
14
and optical amplifiers
15
. SAG
selectively grows crystalline materials in limited region by using mask: A layer of
dielectric material such as SiNx and SiO
2
is used as mask layer to deposit onto the
chosen substrate; the mask layer should be effective in preventing nucleation of
materials. Lithographic techniques are then used to define patterns and remove
portions of the mask to expose the underlying substrate using etching techniques. As a
result of the difference in nucleation difficulty on mask and unmasked region,
selective-area-growth is achieved and confines growths within the openings of the
dielectric mask.

1.4 Process
SAG-MOCVD requires a pre-defined pattern on the substrate before growths are
performed. There are three steps for SAG-MOCVD growth as shown in Fig.1.2. In
the first step, dielectric materials like SiNx or SiO
2
are deposited on the substrate as
the mask layer. Both lithography and etching techniques will be used to define and
transfer the pattern to the dielectric layer as second step. The last step is SAG growth
for nanostructure growth. Details of each step are listed in the following:
15

Fig.1.2 Procedure of Selective-Area-Growth. (a) A thin dielectric layer is first deposited on the substrate
as a mask. (b) Nano patterns are defined with lithography technique and transferred to dielectric layer by
etching technique. (c) Nanostructures are selectively grown on open regions.

1
st
step: Deposit dielectric layer
For selective epitaxial growth, an amorphous layer of dielectric material is
required as a mask layer to limit growths the unmasked regions only. A thin SiNx
layer is first deposited on the substrate using Plasma Enhanced Chemical Vapor
Deposition (PECVD) system. Three gases: SiH
4
, NH
3
and N
2
are used in the PECVD
system with flow rate 40 sccm, 20 sccm and 60 sccm respectively. The reaction takes
place at 275℃ under 440 mTorr with power 30mW. The deposition time is 2.5
minutes which could deposit about 28nm thick SiNx layer.

2
nd
step: Define and transfer patterns
For nanostructure SAG growth, nano-scale patterns are required. E-beam
lithography is used to create nano-scale patterns on SiNx layer.
After a thin SiNx layer is deposited on the substrate, PMMA 950 C2, one kind of
resists for ebeam lithography is spin-coated on the SiNx at 6000rpm for 45s. After
spin-coating, the substrate is anneal on hot plate at 180
。
C for 180s to bake the PMMA.
Substrate
dielectric
Substrate
Substrate
(a) (b)
(c)
16

Nano pattern region is surrounded by an unmasked region which is called the
“skirt” region as shown in Fig.1.3. Because of the growth selectivity effect, no
consumption of precursors occurs above masked region and these precursors can
diffuse to the neighboring unmasked regions and thus increase the local partial
pressure of precursors near nano-patterned region. Since the area of masked region is
much greater than the nano-patterned region, the local partial pressure of precursors
may be enhanced several times due to this selectivity effect and may affect the
nano-structures growth results. The existence of the skirt regions serve as precursor
sinks to absorb excess precursors from outside of nano-pattern region to stabilize the
effective V-III ratio within nano-pattern region.

Fig.1.3 SAG-MOCVD pattern design: nano pattern is surrounded by a fully open, unmasked region, so
called skirt region to absorb excess precursors.

The skirt region is a fully opened region while nano-pattern region is partially
opened region; the electron dosages, aperture sizes for these two regions are different.
For skirt regions, the area dosage is 180 μC/cm
2
; and for nano-pattern regions, the
area dosage is 15μC/cm
2
. The acceleration voltage of electron beam is set to 10kV for
both regions and the aperture size is 120μm and 10μm for skirt and nano-pattern
regions respectively.

skirt
Nano pattern
17

After E-beam lithography, samples are developed in MIBK:IPA (1:3) solution for
60s, then rinsed in IPA solution for 30s before Nitrogen drying. In the etch process,
Reactive-ion etching (RIE) is used; samples are etched under CF
4
gas at 100m torr at
100W for 12s.
Residual PMMA is stripped out using acetone solution with sonication for 5
minutes followed by O
2
ashing at 120W/200mT/4min.

3
rd
step: SAG growth
In this step, samples are loaded into the MOCVD reactor for SAG growth. Some
samples may need a pre-cleaning process before loading: samples are dipped in
chemical solution to remove native oxide. A GaAs substrate is dipped in diluted
hydrochloric acid (DI water: HCl = 1:1) for 30s and a silicon substrate is dipped in
7:1 buffered oxide etch solution for 3s. After chemical cleaning process, samples are
then immediately loaded into the reactor for crystal growth.

1.5 Thesis overview
Several experiments are included in this thesis including growth of GaAs on
lattice-mismatched and silicon substrates, growth of defect-free GaAs nano-structures
and passivation effect of GaAs nano-structures. Growths of GaAs on silicon
substrates are partitioned into 2 chapters: Chapter 2 and Chapter 4. In Chapter 2,
growth of GaAs nano-structure on (111) silicon substrates will be discussed; and in
Chapter 4, the focus will be put on GaAs thin film growth on lattice-matched and
silicon substrate using SAG-MOCVD growth techniques. Between Chapter 2 and
Chapter 4, study of twining effects within GaAs nano-structures and approaches of
growing defect-free GaAs nano-structures will be disclosed in Chapter 3. In the last
18

chapter: passivation of GaAs with AlGaAs and the effect of wet oxidization of
AlGaAs will be addressed in Chapter 5. Detail descriptions of each chapter are listed
in the following:

Chapter 2: GaAs nanowire growth on silicon
Due to 4% lattice-mismatch between GaAs and silicon, epitaxial growth of GaAs
on silicon is difficult and the as grown GaAs may suffer strong strain energy which
usually results in stacking faults and high defects density and could deteriorate not
only optical but also electrical properties of the as grown GaAs thin film.
Epitaxial-Lateral-Overgrowth
16–18
is the commonly used technique to grow materials
on lattice-mismatched substrate in 1980s, it efficiently reduces the defect density of
the as grown material but can’t completely remove all defects.
Based on the same idea, nano-scale pattern is used in SAG-MOCVD techniques:
GaAs nanowire grown from nano-size opening regions bear less strain energy due to
smaller area of GaAs/silicon interface. GaAs nanowires grown from these
nano-patterns benefit from the reduced strain energy thus could possibly reduce
defects development and achieve defect-free crystal. The most challenge of
GaAs/silicon integration is multi-domain issue which results from growing polar
material on non-polar substrate. Detail procedures of surface treatment for (111)
silicon substrate will be discussed in this chapter along with studies of growth
conditions to achieve high yield of GaAs nanowires on (111) silicon substrate.

Chapter 3: Growth of twin-free GaAs nanostructure
Twin defect is the main characteristic of III-V nanowires and high twin density is
commonly seen in many studies
19
; the formation of 6-fold symmetric hexagonal
nanowires on 3-fold symmetric (111) substrate implies 2-fold symmetric structure
19

developed on (111) planes: twin defect. With the help of twin defects, tetrahedron
shape of GaAs rotates 180 degree whenever a twin defect is formed
20
. Different
growth conditions were tested and proved that twin density decreases with increasing
growth temperature, decreasing of arsine partial and increasing of the size of opening
mask; however twins can’t be eliminated thermodynamically.
In Chapter 3, different patterns were tested for SAG-MOCVD growth on both
(111)B and (100) GaAs substrate. Under suitable growth condition, twin-free GaAs
nanostructure can be grown enclosed by (-1-10) facets on both substrates; by reducing
the symmetry of opening pattern: replace nano-size round patterns with nano-stripe
patterns, surface energy reduction resulted from twinning effect is suppressed and
thus the probability of twinning can be controlled. By controlling the growth
condition, only single twin can be formed within the nanostructure and the transition
of enclosed facets after twinning helps to better understand the origin of twinning
effect in III-V nanostructures.

Chapter 4: Growth of GaAs thin-film on lattice-mismatched substrate
GaAs nanosheet described in Chapter 3 exhibits some interesting characteristics
and the inherent twin-free property makes it a potential candidate for photovoltaic
application; however unlike nanowire structure, the height of nanosheet is limited by
its length; to achieve reasonable light absorption, the length of nanosheet should be
around ~μm long which is not feasible especially when growing on lattice
mismatched substrate.
Fortunately, the lateral growth rate of nanosheet structure can be greatly
enhanced by intersecting two nanosheets. With enough growth time, crossed
nanosheets eventually grow as a continuous thin film; as the contact area between
nanosheet and substrate is small, the strain energy of the as-grown GaAs thin film can
20

be lowered to certain level on lattice-mismatched substrates. Considered the
advantages of nanosheet structures: reduced strain energy, inherent twin-free property;
in this chapter, GaAs nanosheets are used on lattice-mismatched substrate like GaP
and silicon as basic elements to form continuous GaAs thin film.

Chapter 5: Double AlGaAs passivation and wet oxidation on GaAs
nanostructure
GaAs is notorious for Fermi-level pinning on the surface. Free carriers are easily
trapped in the surface states and leave depleted region underneath the surface. As the
size of GaAs structure shrinks which increases surface/volume ratio, the situation
becomes worse: for example, a thin GaAs nanowire or a thin GaAs nanosheet
structures may be fully depleted due to surface pinning effect and makes carrier
transportation difficult within GaAs nanostructures.
It is considered that As
2
O
3
is the cause of surface pinning effect and many
treatments were studied to protect GaAs surface from forming As
2
O
3
. AlGaAs is one
of candidates used to passivate GaAs surface from oxidization and the type I
alignment between AlGaAs/GaAs helps to prevent free carriers from AlGaAs/GaAs
interface as well. In this chapter, different structures of AlGaAs layers, like thickness,
double layers and wet oxidization treatment will be examined toward the performance
of passivation effect for GaAs bulk, nanowire and nanosheet structures.

1.6 Reference
(1) Brown, G. F.; Wu, J. Laser Photonics Rev. 2009, 3, 394–405.
(2) Luque, A.; Martí, A. Phys. Rev. Lett. 1997, 78, 5014–5017.
21

(3) Conibeer, G.; Ekins-Daukes, N.; Guillemoles, J.-F.; Kőnig, D.; Cho, E.-C.;
Jiang, C.-W.; Shrestha, S.; Green, M. Sol. Energy Mater. Sol. Cells 2009, 93,
713–719.
(4) Trupke, T.; Green, M. A.; Würfel, P. J. Appl. Phys. 2002, 92, 4117.
(5) Huang, Y.; Duan, X.; Cui, Y.; Lauhon, L. J.; Kim, K. H.; Lieber, C. M. Science
2001, 294, 1313–1317.
(6) Bertness, K. A.; Kurtz, S. R.; Friedman, D. J.; Kibbler, A. E.; Kramer, C.;
Olson, J. M. Appl. Phys. Lett. 1994, 65, 989.
(7) Takamoto, T.; Ikeda, E.; Kurita, H.; Ohmori, M. Appl. Phys. Lett. 1997, 70,
381.
(8) Wang, J.; Gudiksen, M. S.; Duan, X.; Cui, Y.; Lieber, C. M. Science 2001, 293,
1455–1457.
(9) Sheu, J. K.; Chang, S. J.; Kuo, C. H.; Su, Y. K.; Wu, L. W.; Lin, Y. C.; Lai, W.
C.; Tsai, J. M.; Chi, G. C.; Wu, R. K. IEEE Photonics Technol. Lett. 2003, 15,
18–20.
(10) Hersee, S. D.; Fairchild, M.; Rishinaramangalam, A. K.; Ferdous, M. S.; Zhang,
L.; Varangis, P. M.; Swartzentruber, B. S.; Talin, A. A. Electron. Lett. 2009, 45,
75.
(11) Guo, W.; Zhang, M.; Banerjee, A.; Bhattacharya, P. Nano Lett. 2010, 10,
3355–3359.
(12) Osinski, J. S.; Zou, Y.; Grodzinski, P.; Mathur, A.; Dapkus, P. D. IEEE
Photonics Technol. Lett. 1992, 4, 10–13.
(13) Silvestre, L.; Ougazzaden, A.; Delprat, D.; Ramdane, A.; Daguet, C.;
Patriarche, G. J. Cryst. Growth 1997, 170, 639–644.
(14) Takemasa, K.; Kubota, M.; Wada, H. IEEE Photonics Technol. Lett. 2000, 12,
471–473.
(15) Djordjev, K.; Dapkus, P. D. IEEE Photonics Technol. Lett. 2002, 14, 603–605.
(16) Ujiie, Y.; Nishinaga, T. Jpn. J. Appl. Phys. 1989, 28, L337–L339.
22

(17) Kim, B.; Lee, K.; Jang, S.; Jhin, J.; Lee, S.; Baek, J.; Yu, Y.; Lee, J.; Byun, D.
Chem. Vap. Depos. 2010, 16, 80–84.
(18) Kazi, Z. I.; Thilakan, P.; Egawa, T.; Umeno, M.; Jimbo, T. Jpn. J. Appl. Phys.
2001, 40, 4903–4906.
(19) Johansson, J.; Karlsson, L. S.; Svensson, C. P. T.; Mårtensson, T.; Wacaser, B.
a; Deppert, K.; Samuelson, L.; Seifert, W. Nat. Mater. 2006, 5, 574–580.
(20) Ikejiri, K.; Sato, T.; Yoshida, H.; Hiruma, K.; Motohisa, J.; Hara, S.; Fukui, T.
Nanotechnology 2008, 19, 265604.
23

Chapter 2 GaAs nanowire growth on Silicon
2.1 Introduction
Silicon technology has been successfully developed for decades and has been
used on many fields to fabricate nano-scale devices such as CPU and RAM; however
the indirect band gap property of silicon makes it difficult to serve as good optical
devices like lasers and LEDs. On the other hand, most of III-V materials are
direct-band gap materials with outstanding optical and electrical properties which
make them potential candidates for optical and electrical devices. Thus the integration
of III-V material on silicon substrates is always an interesting study.
Several challenges for III-V/silicon integration are: 1
st
: lattice mismatch: lattice
mismatch between silicon and III-V materials, for example 4% lattice mismatch
between GaAs and silicon, could cause stress within materials during crystal growth.
Strain energy accumulates as the thickness of epitaxial layer increases and when it
exceeds a certain thickness (critical thickness) dislocations could be formed to release
the strain energy. These defects break the perfection of the as-grown III-V material
and thus degrade its optical or electrical performance. 2
nd
: multi-domain issues on
polar/non-polar interface: other than dislocations, multi-domain issues could occur
during III-V growth on a silicon substrate. Silicon is composed of a single type of
atom thus it is considered a non-polar material; however III-V materials are composed
of two different atoms which have different electronegativities. Therefore, electrons
are not equally shared between two bonding atoms and would form an electric dipole.
Surfaces with different polarities may have different chemical properties, surface
reconstruction and growth behaviors. The transition of non-polar silicon materials to
polar III-V materials during III-V/silicon growth, multi-domains with different
polarities could be formed; different growth behavior of these domains may result in
24

non-uniform or other stacking faults (domain boundary) within as-grown III-V
materials.
In this chapter, the study of GaAs/silicon integration will be studied. To
minimize strain energy between GaAs/silicon, which has 4% lattice mismatch, GaAs
nanowire structures will be used, and various growth conditions toward multi-domain
issues will be studied to achieve high yield GaAs nanowires on (111) silicon substrate.

2.2 Growth on non-polar surface
2.2.1 (111) Silicon surface
Unlike the (111)B GaAs surface, the (111) silicon surface is a non-polar
surface; since III-V nano-structures have their preferred growth direction, for
example: GaAs, InAs, and GaP tend to grow along (111)B direction and InP
prefers the (111)A surface. To transform the non-polar (111) silicon surface to a
polar (111) surface, it is critical to integrate a III-V material on the silicon
substrate. The morphology of the silicon surface is thus the most important part;
in the following, atomic-flat (111) silicon surfaces and (111) silicon surfaces with
steps are discussed.

Atomically-flat surface
On atomically-flat surfaces, silicon atoms all sit on the same plane without
any steps, as shown in Fig.2.2.1(a). Since silicon is composed of single atoms,
bonds between Si-Si atoms are non-polar because silicon atoms have the same
charges. However polar bonds can be formed by forming bonds with either
group III or group V atoms on (111) silicon surfaces as shown in
Fig.2.2.1(b)~(e).

25

Four distinct atomic bonding arrangements on (111) surfaces result in two
different polar surfaces
1
: when Ga atoms form bonds with the topmost silicon
atoms or As atoms replace the topmost silicon atoms, this would form a (111)B
polar surface, as shown in Fig.2.2.1(b) and Fig.2.2.1(c) respectively. On the other
hand, an opposite polar surface (111)A would be formed when Ga atoms replace
the topmost silicon atoms or As atoms form bonds with the topmost silicon
atoms as shown in Fig.2.2.1(d) and Fig.2.2.1(e) respectively. The control of polar
surface type is important. For example, GaAs nanowires tend to grow along
(111)B directions, thus uni-directional GaAs nanowires would be formed on the
already-formed (111)B surface in the vicinity of the (111) silicon surface.
However, 3 equivalent (111)B directions on the (111)A polar surface would, in
turn, form tilted GaAs nanowires along 3 different directions which would make
it difficult for device fabrication.

Fig.2.2.1 Atomic configuration of Ga, As on (111) Si surface

(111)B
(111)B
(111)B
(111)B
As
Ga
Si
(a) (111) Silicon surface along <1-10> zone axis
(b) Ga atoms form bonds with topmost Silicon atoms (c) As atoms replace topmost Silicon atoms
(d) Ga atoms replace topmost Silicon atoms (e) As atoms form bonds with topmost Silicon atoms
26

To avoid tilted devices, the uni-polar surface is required before growth.
Detail and thorough study of surface science of silicon was blooming during the
1980s with respect to surface reconstruction and surface passivation of silicon
surfaces. In Marjorie’s study, the complicated surface reconstruction on (111)
silicon surfaces can be removed with surface passivation with arsenic atoms. The
bare (111) silicon surface, as shown in Fig.2.2.2, has many “half-filled” dangling
bonds and thus its surface could reconstruct to lower the surface energy. At
room-temperature, the 2x1 surface reconstruction is commonly seen while at
higher temperatures around 700~800
。
C, a 7x7 surface reconstruction would be
formed. Since surface reconstruction would involve re-arrangement of silicon
atoms, complicated step structures usually can be observed on the reconstructed
surface. Detail discussion about the effects of steps on the formation of
multi-domain deposits will be discussed later.
Based on these considerations, eliminating the step structure on (111)
silicon is a way to get a single-domain (111)B surface. In Fig.2.2.2, there are two
different ways to passivate (111) silicon surface proposed by Marjorie
2
. The first
is to use either hydrogen or chlorine atoms bonded to the topmost silicon surface.
With the help of hydrogen or chlorine atoms, the dangling bonds on the (111)
silicon surface are removed and thus recover the surface reconstruction back to a
1x1 surface without any step structures. However use of hydrogen or chlorine
has two disadvantages: 1
st
: H-Si bonds are weaker and easily broken above 500
。
C. Since SAG nanosheet or nanowire growth was carried out at temperatures
above 700
。
C, the passivated H-Si surface couldn’t be retained when
nanostructure growth starts and would still result in the multi-domain formation.
2
nd
: The existence of H-Si bonds could prevent As-Si bonding which would
result in limited GaAs deposition on the hydrogen-passivated silicon substrate.
27

Fortunately, other than hydrogen or chlorine passivation, arsenic itself can also
be used to passivate (111) silicon surface as also shown in Fig.2.2.2. Arsenic
passivation is different than hydrogen passivation: arsenic replaces the topmost
silicon atoms and leaves lone pairs on the (111) silicon surface. Also, As-Si
bonds are much stronger than H-Si bonds, which make it very stable against
thermal annealing and contamination. The most of important thing is the arsenic
passivated (111) silicon surface is a (111)B-like surface as shown in Fig.2.2.1(c),
which makes integration of GaAs nanostructures on silicon possible.

Fig.2.2.2 Passivation of (111) Si

Si (111):As 1x1
•Passivate Si (111) with As
•Recover 2x1 or 7x7 surface to 1x1 surface
•Very stable with thermal annealing and contamination
As
H or Cl
Si
Si (111)
•Half-filled “dangling bonds” on surface
•2x1 at room-temperature;7x7 while annealing
Si (111):H 1x1
•Hydrogen caps on Si surface
•No dangling bonds
•Break at 500˚C
28

Fig.2.2.3 Atomic configuration of Ga, As on (111) Si surface with steps

Steps on the (111) Silicon surface
As described in previous section, arsenic can perfectly passivate the (111)
silicon surface and leave the (111)B-like surface for GaAs nanostructure growth;
however it only works on an atomically-flat surface. If the (111) silicon surface
is not atomically-flat, a structure with many steps would develop, and arsenic
passivation would not guarantee a single-domain of (111) silicon surface. The
(111) silicon surface with double and mono-atomic steps are shown along
<1-10> zone axis in Fig.2.2.4. After arsine annealing, assuming that arsenic
would replace the topmost silicon surface: (111)B-like surfaces are formed on
the two sides of two-atomic steps, but with a (111)B-like surface at the one side
and a (111)A-like surface at the other side of the mono-atomic steps. Clearly,
(111) silicon surfaces with mono-atomic steps would form multi-domains at the
two sides of step structure during the arsine annealing step. And the opposite
•Partial (111)A surface nucleated
•As-terminated: 95%
•Ga-terminated: 5%~10%
J. R. Patel, J. Zegenhagen, P . E. Freeland, and M. S. Hybertsen, J. A. Golovchenko and D. M. Chen
“Arsenic and gallium atom location on silicon (111) “, J. V ac. Sci. Techno!. B 7 (4), Jull Aug 1989
•Reduced percentage of As-coverage layer due to unbroken Si:H
R. D. Bringans, Marjorie A. Olmstead. “The bonding of arsenic to the hydrogen terminated Si(111)
surface”. J. V ac. Sci. Technol. B 6 (4), Jul/Aug 1988
H or Cl
As
Ga
Si
29

polarity of these two surfaces could cause multi-domain issues for the later GaAs
growth.

Fig.2.2.4 As-passivation on (111) Si with steps

Different approaches were studied to eliminate mono-atomic steps and
leave two-atomic steps on the (111) silicon surface during 1980’s. PH value
modified BOE solution
3
or hot water
4
were proposed to obtain step-free a silicon
surface.

2.3 Growth condition
The growth conditions for GaAs nanowires on (111) silicon is shown in Fig.2.3.1
in the following:
(a) Two-atomic steps on Si (111)
(b) Mono-atomic steps on Si (111)
As anneal
As anneal
30

Fig.2.3.1 Growth condition of GaAs nanowire on (111) Si substrate

There are several important steps for growing GaAs nanowires on (111) silicon.
1
st
step is native oxide removal. Two different ways were used to clean the (111)
silicon surface: before the sample was put in the reactor, BOE dipping for 2~3
seconds was performed to etch away the native oxide, and then sample was annealed
under hydrogen ambient at a temperature above 900
。
C for 2-5 minutes for further
native oxide removal in the chamber. The chemical reactions of native oxide removal
under hydrogen anneal are shown in following equations:
Si−H+SiO
*
→ Si
∗
+H
*
O
(.)
----- Equation 1
Si
∗
+SiO
*
→SiO
(.)
----- Equation 2
The hydrogen atom from H-Si bond first reacts with silicon dioxide and recovers
the oxidized silicon surface back to clean the silicon surface and water vapor. The
clean surface can also react with silicon dioxide to leave volatile Silicon oxide.
After the native oxide is removed from silicon surface, 2
nd
step: the (111)B-like
surface formation was applied. The temperature is lowered from high temperature
used for hydrogen annealing to about 400
。
C and annealed with arsine. As disclosed in
4
th
:Nanowire Growth
•Growth temperature:740°C~790 °C
•Growth pressure:0.1 atm
•Arsine/TMG: 126~430
3
rd
:Nucleation layer formation
•As-Si bound breaks around 600°C
•Serve as seeds for NW growth
1
st
:Native Oxide Removal
•Dip in BOE (Pre-growth treatment)
•High temperature H
2
annealing
2
nd
:(111)B Surface Formation
31

the previous section, arsenic can perfectly remove dangling bonds on the (111) silicon
surface and form a (111)B-like surface; this is the purpose of this step. The arsine
flow rate for the arsine anneal step was set to 5sccm which gave a partial pressure of
about 5.43x10
-5
atm. The 3
rd
step is followed by (111)B-like surface formation: TMGa
flow is applied after 2
nd
step. Though As-Si bonds are quite stable with thermal
annealing, GaAs nanowire growth was carried out at 790
。
C, where As-Si bonds could
be easily broken. Therefore, TMGa is applied for low temperature GaAs nucleation
after (111)B-like surface formation. The TMGa flow rate at this step was set to 0.8
sccm which gave a partial pressure of 3.74x10
-7
atm.
After nucleation, the temperature is increased to 740
。
C~790
。
C for GaAs
nanowire growth, which is the 4
th
step. The partial pressure of TMGa is fixed at
3.74x10
-7
atm and the partial pressure of arsine ranges from 5.43x10
-5
to 1.85x10
-4

atm; the corresponding V/III ratio ranges from 126~430.

2.4 Experimental results
To grow GaAs nanowires on a (111) silicon substrate, the strategy adopted was
to grow a thin (111)B GaAs film on the unmasked region. Once every opening pattern
was filled with (111)B GaAs film, then regular GaAs nanowire growth conditions
which gave 100% yield of nanowires on GaAs substrate were applied. Since the
growth condition of GaAs nanowires on the (111)B GaAs substrate had already
developed, the focus would be on how to grow uni-domain (111)B GaAs thin film on
(111) silicon. Several growth conditions, like hydrogen annealing, nucleation steps
and the size of the openings were studies in the experiments.

2.4.1 Hydrogen annealing step:
The hydrogen annealing step is quite important for III-V material grown on
32

the silicon substate; the purpose of the hydrogen annealing is to remove the
native oxide on the (111) silicon surface before III-V growth; according to
Fukui
5,6
, the existence of native oxide could affect the growth of GaAs nanowires.
The most important factors of the hydrogen annealing step are annealing
temperature and annealing period. In the following, two experiments were taken
at different hydrogen annealing temperatures: figures of detailed growth
conditions for these two growth runs were shown in Fig.2.4.1. In these two
figures, pink rectangles denote the periods when arsine was flowed into the
reactor, and green rectangles denote the periods when TMGa was flowed into the
reactor. The flow rate of arsine was labeled above the pink rectangles and the
flow rate of TMGa was labeled below the green rectangles for every step.
Numbers in red below the x-axis denote the period of time (unit: minute) for each
step. Similar growth figures will be shown afterward with the same notation.

Temp (C)
860
440
740
300
20 7
17 sccm 10 sccm 10 sccm
0.8 sccm 0.8 sccm
10 30
T (min)
L2891
33

Fig.2.4.1 Diagrams of growth condition for L2891 and L2892

Two samples, L2891 and L2892 were both hydrogen annealed for 20
minutes at 860℃ and 900℃ respectively. Both nucleation steps and nanowire
growth steps were the same for these two growth runs. SEM images of these two
samples were shown below:
Fig.2.4.2 SEM images of GaAs nanowire growth on (111) silicon substrate. (a) hydrogen annealing at
860℃ for 20 minutes. (b) hydrogen annealing at 900℃ for 20 minutes.

Distinct growth behaviors of GaAs nanowires on (111) silicon were shown
in Fig.2.4.2. Only one opening out of 400 had nanowire growth in L2891 which
was annealed with hydrogen at 860℃; on the contrary, every opening had GaAs
depositions in L2892, which was annealed with hydrogen but at a higher
temperature of 900℃. From these two experiments, it seems that the GaAs
Temp (C)
900
440
740
300
20 7
17 sccm 10 sccm 10 sccm
0.8 sccm 0.8 sccm
10 30
T (min)
L2892
L2891 L2892
34

deposition rate greatly depends on the temperature of the hydrogen annealing
step. In the chemical reaction of native oxide removal equation 1, native oxide
removal starts from H-Si bonds in which the source of atomic hydrogen is from
thermal cracking of hydrogen gas. If the annealing temperature is not high
enough, a limited amount of hydrogen atoms are cracked from hydrogen gas,
thus the reaction rate of native oxide removal process would be suppressed and it
could prevent either arsenic or gallium atoms from bonding with silicon atoms
for deposition. Therefore the higher the anneal temperature, the higher the GaAs
deposition rate.
From the above experiment, it seems that the hydrogen annealing
temperature should be at least higher than 900℃; however the SEM image of
L2892 in Fig.2.4.2(b) shows a low yield rate of vertical GaAs nanowires; most of
depositions were bulk growths with unknown facets, and some tilted nanowires
were also observed. Those undesired growths may result from residual native
oxide on silicon
5,6
or the exposed Silicon surface after hydrogen annealing
process. Since SiO
2
is another kind of mask used for SAG, the existence of
residual native oxide may affect arsenic or gallium bonds with silicon and reduce
the GaAs deposition rate as shown in Fig.2.4.2(a). On the other hand, surface
morphology of the silicon substrate after hydrogen annealing could have a native
effect for GaAs nanowire growth due to the multi-domain issue.
In the next experiment, the anneal period will be examined toward the yield
rate of vertical GaAs nanowires.
35

Fig.2.4.3 Diagram of growth condition for L2988

Two samples, L2967 and L2988, were grown at almost the same growth
condition except the period of hydrogen annealing process as shown in Fig.2.4.3.
Both samples were hydrogen annealed at 965℃; L2967 was annealed for 10
minutes and L2988 was annealed for only 2 minutes. From previous experiment,
an anneal temperature higher than 900℃ is high enough for the native oxide
removal reaction; therefore, it can be assumed that native oxide removal reaction
takes place at 965℃, as well in this experiment. SEM images of growth results
for these two samples are shown below:
Temp (C)
965
440
740
300
10
10 sccm
10
T (min)
L2967
5
640
2
0.8 sccm
17 sccm
30
Temp (C)
965
440
740
300
2
10 sccm
10
T (min)
L2988
5
640
2
0.8 sccm
17 sccm
30
36

Fig.2.4.4 SEM images of GaAs nanowires grown on (111) Si substrate with different period of hydrogen
anneal process

Low magnification SEM images of L2967 and L2988 are shown in
Fig.2.4.4(a) and Fig.2.4.4(b) respectively. As can be seen, L2988 has a higher
yield rate of vertical GaAs nanowires compared to L2967. In higher
magnification SEM images Fig.2.4.4(c) and Fig.2.4.4(d), both had irregular bulk
growths, but tilted nanowires and small, short depositions were observed only in
L2967 but not in L2988. It seems that the hydrogen anneal period might not only
clean the native oxide but also change the surface conditions of the silicon
surface. Studies
4,7–10
of hydrogen annealing on silicon devices indicated that
morphology of the vicinity of the silicon surface changes along with the native
oxide removal process. Silicon atoms would migrate on the surface during
hydrogen annealing and thus change the morphology and the exposure facets. As
(a)L2967 (b)L2988
(c)L2967 (d)L2988
37

discussed in previous section, the vicinity of the surface is important for III-V
growth on silicon; if other facets other than (111) planes formed after hydrogen
annealing, multi-domains could be formed. Unlike (111) silicon facets,
multi-domain issues on other facets
11–14
are difficult to handle by merely using
arsenic passivation. Tilted nanowires in sample L2967 are an obvious indication
of multi-domain problem.
Because the mobility of silicon atoms may be related to annealing
temperature, another experiment was performed to compare the influence of
hydrogen anneal temperature toward the yield of vertical GaAs nanowires.
Sample L2989 was grown at the same growth condition as L2988, except that the
hydrogen anneal temperature was lowered from 965℃ to 945℃. Detailed
growth conditions of L2989 and SEM images are shown below:

Fig.2.4.5 Diagram of growth condition for L2989

Temp (C)
945
440
740
300
2
17 sccm 10 sccm
10
T (min)
L2989
5
640
2
0.8 sccm
30
38

Fig.2.4.6 SEM images of GaAs nanowires grown on (111) Si substrate with different hydrogen anneal
temperature

As can be seen in Fig.2.4.6, the yield rate of vertical GaAs nanowires on
(111) silicon increased a little bit by reducing the hydrogen anneal temperature.
The percentage of bulk growth decreased when annealed at lower temperature
with hydrogen. The reason for increased yield rate of vertical GaAs nanowires at
lower a hydrogen anneal temperature might also be attributed to the same
mechanism: lower annealing temperature reduces the mobility of silicon atoms
and thus suppress silicon atom migration which could form facets other than
(111).

2.4.2 Nucleation step:
Aside from hydrogen anneal process, the nucleation process is another
(a)L2989 (b)L2988
(c)L2989 (d)L2988
39

important step for GaAs nanowires growth on silicon. With an appropriate
hydrogen anneal condition, native oxide is cleaned by atomic hydrogen and
leaves an atomically-flat surface on the (111) silicon substrate. Following the
GaAs nanowire growth condition is the nucleation step which is used to
transform the non-polar (111) silicon surface to the polar (111)B GaAs surface. In
the nucleation step, the most difficult part is how to avoid multi-domains and
pre-deposit a thin (111)B-like film for GaAs nanowire growth.
Experiments started from exploring optimized nucleation temperature; since
As-Si bonds can’t be retained at temperatures above 700℃ , a series of
nucleation studies were carried out at temperatures ranging from 440℃~640℃;
detailed growth conditions for each samples are shown in the following:

Temp (C)
945
440
740
300
2
5 sccm 10 sccm
10
T (min)
L3107
2
640
0.8 sccm
30
0.8 sccm
Temp (C)
945
440
740
300
2
5 sccm 10 sccm
10
T (min)
L3112
2
590
0.8 sccm
30
0.8 sccm
Temp (C)
945
440
740
300
2
5 sccm 10 sccm
10
T (min)
L3113
2
540
0.8 sccm
30
0.8 sccm
Temp (C)
945
440
740
300
2
5 sccm 10 sccm
10
T (min)
L3128
2
490
0.8 sccm
30
0.8 sccm
40

Fig.2.4.7 Diagrams of growth condition for L3107, L3112, L3113, L3128 and L3133

All samples were Hydrogen annealed at 945℃ for 2 minutes which is the
optimized annealing process obtained from previous section; then the
temperature was lowered down to 440℃ for arsine annealing about 10 minutes.
After arsine annealing, nucleation steps took place at different temperatures. The
flow rate of TMGa and arsine for nucleation steps and the following nanowire
growth step were kept the same among these samples; the effect of nucleation
temperature toward the yield rate of vertical GaAs nanowires can thus be
obtained. SEM images of growth results are shown below:
Temperature Tilted view Top view
640℃
(L3107)

Temp (C)
945
440
740
300
2
5 sccm 10 sccm
10
T (min)
L3133
2
0.8 sccm
30
0.8 sccm
41

590℃
(L3112)

540℃
(L3113)

490℃
(L3128)

42

440℃
(L3133)

Fig.2.4.8 SEM images of GaAs nanowires grown with different nucleation temperatures

Low and high magnified SEM images for these five samples are shown in
Fig.2.4.8. Among high magnified images, it can easily tell that nucleation at
640℃ had more GaAs deposition and it seems that GaAs became difficult to
deposit when nucleation temperature decreased, leaving many empty holes.
Moreover, the percentage of bulk growth decreased with decreasing nucleation
temperature. Decreasing nucleation temperature can help inhibit bulk growth
from openings but also suppress GaAs deposition within the unmasked region.
Therefore, the yield rate of vertical GaAs nanowires increased at first when
nucleation temperature lowered from 640℃ to 540℃, and decreased later
when the nucleation temperature was further lowered to 440℃ as can be seen
from top view images in Fig.2.4.8. Unlike the VLS growth technique, arsenic
atoms come from the pyrolysis of arsine gas; the pyrolysis efficiency of arsine
gas is merely 50% at 600℃ and decreases at a lower temperature
15,16
.
Therefore even though the partial pressures of the TMGa and arsine precursors
were the same among these samples, the effective V/III ratios were different.
Nucleation that occurs at a lower temperature would have less arsenic atoms due
to low pyrolysis efficiency of arsine gas and thus resulted in the increased
43

percentage of hollow openings. As for bulk growth suppression at lower
temperature, it may be attributed to surface reconstruction of the (111) silicon
surface at a different temperature. The literature reported that when the
temperature ramped down from 900℃ to 400℃, the surface reconstruction of
(111) silicon recovered from 7x7 to 1x1, which has no steps, and then mixing of
double or triple height steps structure shows up when the temperature is
increased back to 500℃~800℃
17
through annealing. Among these samples, it
can be easily seen that when the nucleation temperature is ramped down below
500℃, bulk growth was greatly suppressed as shown in Fig.2.4.8. Therefore it
may be indicated that the suppression of bulk growth at a lower nucleation
temperature could be related to step rearrangement, which occurs below 500℃.
From the results above, it seems that there is a trade-off between bulk
growth and GaAs deposition efficiency: how to obtain a double height step
structure on the silicon surface along with a reasonable GaAs deposition rate is
the main challenge. Because of the pyrolysis efficiency limit, the nucleation
should take place at a high temperature in order to get efficient deposition rate.
So the problem is, then, how to keep double height steps on the silicon surface at
high temperature. Ohno from University of Maryland made a series study
17
for
step rearrangement on (111) silicon; his results suggested that the step structure
on the (111) silicon surface would be recovered back to a double height step
when the (111) silicon surface was annealed with arsine at 300℃ and then
ramped up to 800℃. Another nucleation experiment was done to first anneal the
(111) silicon surface with arsine at 400℃ then ramp up to 800℃ for high
temperature nucleation; the detail growth condition figure and SEM images are
shown below:
44

Fig.2.4.9 Diagram of growth condition for L3616

Fig.2.4.10 SEM images of GaAs nucleation on (111) Si with high temperature nucleation

For sample L3616, the GaAs nanowire growth step was not applied and
nucleation only occurred at a higher temperature. In Fig.2.4.10(a), a low
magnification SEM image of sample L3616 is shown; nucleations are quite
uniform in hexagonal shape over a large area. Although there was still an
undesired shape of nucleation as shown in Fig.2.4.10(b), the uniformity of
nucleation indicated single-domain had been achieved on (111) silicon substrate.
Moreover, because nucleation was performed at high temperature, pyrolysis
efficiency was higher and therefore every opening had GaAs deposited. Since
GaAs was successfully and perfectly grown on the (111) silicon surface, the next
step is to apply the GaAs nanowire growth condition using this nucleation
Temp (C)
925
790
300
5
50 sccm 10 sccm
15 T (min)
L3616
0.8 sccm 15 sccm
2.5
(a)L3616
(b)L3616
45

condition:

Fig.2.4.11 Diagram of growth condition for L3621

Tilted View (30 degree) Top view
Fig.2.4.12 SEM images of GaAs nanowires on (111) Si substrate with high yield rate

Complete growth conditions including Hydrogen anneal, low temperature
arsine anneal, high temperature nucleation and GaAs nanowire growth conditions
were applied to sample L3621. As can be seen in Fig.2.4.12, the yield rate of
vertical GaAs nanowires was greatly increased to almost 100%. In the top view
image of L3621 in Fig.2.4.12, few undesired growths were still within the
nanowire arrays; they could originate from those imperfect nucleations observed
in Fig.2.4.10.

Temp (C)
925
790
300
5
50 sccm 10 sccm
15
T (min)
L3621
0.8 sccm
30
15 sccm
L3621 L3621
46

2.4.3 Crystal quality of GaAs nanowires on (111) Silicon
The yield rate of GaAs nanowires on (111) silicon has been improved to
almost 100% with optimized hydrogen anneal and nucleation steps; though the
shape of nanowires were still hexagonal as those grown on GaAs substrate, and
stacking faults may develop within nanowires grown from a lattice-mismatched
substrate. HRTEM images for these GaAs nanowires grown on (111) silicon were
taken as shown in the following:

Fig.2.4.13 Cross-section TEM images of GaAs nanowires on (111) Si

Cross-section HRTEM images of vertical GaAs nanowire grown on a (111)
silicon substrate are shown in Fig.2.4.13. Like III-V nanowires, high twin density
was observed within GaAs nanowires in Fig.2.4.13(a). Usually twins extend on
the entire (111)B plane within the nanowire; however it is noted that near
47

GaAs/silicon interface, twins disappear and couldn’t extend to two sides of
nanowires. Clear images of the left and right side of GaAs/silicon interface are
shown in Fig.2.4.13(b) and Fig.2.4.13(c) respectively. In these two figures, it can
be clearly seen that twins were terminated at the region labeled by red triangles.
Crystal stacking seems different at the edge of the openings. At the initial stage
of nucleation, multiple nuclei may be developed at different regions within the
openings and each of them may have different crystal stacking: some are twinned
and some are not. As the size of nuclei became larger, these nuclei started to
coalesce, and the region indicated by the red triangles in Fig.2.4.13(b) and
Fig.2.4.13(c) may be the location where coalescence occurred. Due to a different
stacking sequence of each nuclei, grain boundaries were formed as can be seen in
these two figures: dark lines laid between different nuclei. After a certain
thickness, nuclei coalesced and crystal stacking synchronized, thus twins can
reach the edges of nanowires as indicated by red arrows in Fig.2.4.13(b) and
Fig.2.4.13(c).
HRTEM images of bulk growth’s cross-section were taken as well as shown
in Fig.2.4.14:

48

Fig.2.4.14 Cross-section TEM image of titled GaAs nanowire on (111) Si

Similar as Fig.2.4.13, different crystal stackings were formed at the base of
the GaAs deposition and were even more complicated. From the orientation of
twin defects which usually laid on (111)B planes, it can be concluded that
another domain was formed during nucleation step in Fig.2.4.14. Therefore,
nuclei within this opening may originate from different domains and the final
crystal stacking may be determined by the competition between nuclei from
different domains. As shown in Fig.2.4.14, deposition near the GaAs/silicon
interface seems to consist of many grains and as the nuclei coalesce, the crystal
stacking became coherent. For the deposition shown in Fig.2.4.14, the (111)A
domain dominated in the end and thus tilted GaAs nanowires was formed.

2.5 Conclusion
Integration of III-V and silicon is difficult because the two materials are
lattice-mismatched and the III-V materials are polar while silicon is a non-polar
material. Also, pre-treatment of the silicon surface is important as well. In this chapter,
Silicon
GaAs
49

GaAs nanowires were grown on a (111) silicon substrate; the small footprint of
nanowire structure helps to reduce strain energy between GaAs/silicon. Arsine
annealing was applied to form a (111)B plane on the silicon substrate to overcome the
multi-domain issue. However the vicinity of the silicon surface also plays an
important role for III-V/silicon integration. The Hydrogen annealing step, which is
used to remove native oxide from the silicon surface, may damage the vicinity of the
silicon surface: higher annealing temperature and longer annealing period make
silicon atom migration easier and increase the probability of exposing facets other
than (111) plane. However, low annealing temperature would reduce the concentration
of Hydrogen atoms cracked from Hydrogen gas and suppress native oxide removal.
An effective and non-harmful Hydrogen annealing process is important to eliminate
native oxide without change the morphology of the silicon surface. In this study,
annealing silicon at 945℃ with Hydrogen gas for 2 minutes gave an optimized result.
Prior to GaAs nanowire growth, a nucleation step is required, followed by
Hydrogen annealing. The vicinity of the silicon surface is protected with the
optimized Hydrogen annealing condition; however the step structure on (111) silicon
would result in two different domains for III-V growth. Low and high temperature
nucleation are both studied in this chapter: because of low pyrolysis efficiency of
arsine gas at lower temperatures, deposition rate is inhibited. On the other hand,
complicated step structures form at high temperatures. Thus bulk growth is serious
when nucleation is performed at high temperature but deposition rate is insufficient at
low temperature. A special treatment for the silicon substrate is required to achieve
uniform two-step structure on the (111) silicon substrate: by first annealing silicon at
400℃ and ramping up temperature to 800℃ help to change the step structure of the
vicinity of the (111) silicon surface. Also, 800℃ is high enough for arsine pyrolysis,
50

which gives a reasonable GaAs deposition rate on silicon substrate. The achieved
yield rate of vertical nanowires is up to ~100% with the optimized Hydrogen
annealing process and special nucleation step.

2.6 References
(1) Tomioka, K.; Kobayashi, Y.; Motohisa, J.; Hara, S.; Fukui, T. Nanotechnology
2009, 20, 145302.
(2) Olmstead, M. A.; Bringans, R. D.; Uhrberg, R. I. G.; Bachrach, R. Z. Phys. Rev.
B 1986, 34, 6041–6044.
(3) Higashi, G. S.; Chabal, Y. J.; Trucks, G. W.; Raghavachari, K. Appl. Phys. Lett.
1990, 56, 656.
(4) Watanabe, S.; Nakayama, N.; Ito, T. Appl. Phys. Lett. 1991, 59, 1458.
(5) Tomioka, K.; Motohisa, J.; Hara, S.; Fukui, T. Nano Lett. 2008, 8, 3475–3480.
(6) Tomioka, K.; Motohisa, J.; Hara, S.; Hiruma, K.; Fukui, T. Nano Lett. 2010, 10,
1639–1644.
(7) Lee, M.-C. M.; Wu, M. C. J. Microelectromechanical Syst. 2006, 15, 338–343.
(8) Sato, T.; Mizushima, I.; Iba, J.; Kito, M.; Takegawa, Y.; Sudo, A.; Tsunashima,
Y. In Symposium on VLSI Technology Digest of Technical Papers (Cat.
No.98CH36216); IEEE, 1998; pp. 206–207.
(9) Sudoh, K.; Iwasaki, H.; Hiruta, R.; Kuribayashi, H.; Shimizu, R. J. Appl. Phys.
2009, 105, 083536.
51

(10) Kuribayashi, H.; Hiruta, R.; Shimizu, R.; Sudoh, K.; Iwasaki, H. Jpn. J. Appl.
Phys. 2004, 43, L468–L470.
(11) Chu, S. N. G.; Nakahara, S.; Pearton, S. J.; Boone, T.; Vernon, S. M. J. Appl.
Phys. 1988, 64, 2981.
(12) Bringans, R.; Olmstead, M.; Uhrberg, R.; Bachrach, R. Phys. Rev. B. Condens.
Matter 1987, 36, 9569–9580.
(13) Ohno, T. R. J. Vac. Sci. Technol. B Microelectron. Nanom. Struct. 1990, 8,
874.
(14) Biegelsen, D. K.; Ponce, F. a.; Smith, a. J.; Tramontana, J. C. J. Appl. Phys.
1987, 61, 1856.
(15) DenBaars, S. P.; Maa, B. Y.; Dapkus, P. D.; Danner, A. D.; Lee, H. C. J. Cryst.
Growth 1986, 77, 188–193.
(16) Larsen, C. A.; Li, S. H.; Buchan, N. I.; Stringfellow, G. B.; Brown, D. W. J.
Cryst. Growth 1990, 102, 126–136.
(17) Ohno, T. R.; Williams, E. D. Appl. Phys. Lett. 1989, 55, 2628.
52

Chapter 3 Growth of twin-free GaAs nanostructure
3.1 Introduction
III-V materials have been used in many applications such as logic gates
1
, solar
cells
2,3
and photo-detectors
4
because of their superior electrical and optical properties.
III-V semiconductor nanowires have been proposed and gained a great deal of
attention in recent years owing to their potential to provide improved optical or
electrical properties over their bulk counterparts. As a result of their small contact area
with the substrate, nanowires can relax the strain due to hetero-epitaxy and avoid the
formation of dislocations between lattice-mismatched materials. Two growth
techniques are widely used to grow III-V nanowires: vapor-liquid-solid (VLS) and
selective area growth (SAG). Metal droplets, materials with low eutectic point such as
Au are required in VLS growth to serve as a catalyst to incorporate the precursors
from the vapor phase into the liquid phase at low temperatures. The dissolved
group-III and group-V atoms in the metal droplets then precipitate at the
metal/substrate boundary and deposit a thin layer of material underneath the metal
droplets. SAG, on the other hand, is carried out on a nano-patterned substrate at
higher temperatures that allow vapor phase precursors to pyrolyze either
homogeneously or heterogeneously at the substrate surface via a vapor-solid transition
resulting in layer growth without the need of a metal catalyst.

Nanowires (NW) grown by either technique are characterized by transmission
electron microscopy (TEM) to show no dislocations even for highly mismatched
NW/substrate pairs
5,6
. However, defects such as stacking-faults and twin defects are
commonly observed
7,8
in these structures for most growth conditions and processes.
Some studies
9–12
have shown that the existence of twins will reduce carrier lifetime
53

and diffusion length which may deteriorate the optoelectronic properties of twinned
nanowires. To minimize these deleterious effects, variations in the growth kinetics of
III-V nanowires have been studied in order to eliminate twins within nanowires. For
example, two temperature growth
13
and rapid growth methods
14
have been proposed
for VLS growth to reduce twin density within nanowires and the resulting twin-free
nanowires did exhibit better electric properties than twinned nanowires
9
.

Ikejiri et al.
15
proposed a model for the SAG growth of nanowires which
suggested that twin formation was an inherent part of the nanowire formation. In this
model, nucleation on the (111)B plane predominantly occurs by the formation of
tetrahedra with {110} surfaces whose long axes are aligned along either the > < 2 11
or the > < 2 1 1 direction during the initial stage of nanowire growth. A rotational
twin is developed whenever the nucleus on the (111)B surface switches between these
two tetrahedral nucleation growths. In a subsequent article by Yoshida et al.
16
, the
kinetics of twin formation were studied for different growth conditions and diameters
of mask openings to assess the effects of these parameters on the formation of twins.
In their study, no variation of the SAG growth conditions or diameter of openings
resulted in elimination of twins within SAG nanowires. Although the study provided
preliminary information about twin development within nanowires, several
phenomena have not been fully explained and understood: for example, why the
} 0 1 1 { planes of the tetrahedral nuclei vanish when they reach the boundary of the
pattern, and how } 0 1 1 { vertical side walls that seem to define the nanowire
sidewalls are formed. Similarly, why is the twin density so high in SAG nanowires,
and is there a way to form twin-free nanowires? Finally, direct proof of the correlation
between the formation of twins and rotation of tetrahedra was not shown.
54

In this chapter, we investigate the influence of the substrate pattern and
subsequent nanostructure shapes on the formation of twins in the SAG nanostructures
of III-V compound semiconductors. In the process we have discovered a defect-free
nanostructure – the nanosheet - which may have its own applications in electronic and
optoelectronic technologies. In particular, we employ nanoscale stripe patterns rather
than round patterns to form GaAs nanosheets in which twinning is greatly inhibited.
The twin-free GaAs nanostructure demonstrated herein is, to our knowledge, unique
and the characteristics of its growth morphology solidifies the model of twin
development in SAG nanostructures. Since III-V nanowires all hold high twin density,
the idea of using nanosheet structure to eliminate twins either thermodynamically or
kinetically may help to achieve other twin-free III-V nanostructures grown by the
SAG technique.

3.2 Growth Method
Selective area growth was employed to fabricate nanosheets on GaAs (111)B and
(100) substrates. Previous studies
17
of III-V nanowires have shown that vertical
nanowires can only be grown along the (111)B orientation owing to the surface
reconstruction properties of III-V materials. The substrate preparation for nanosheet
growth is the same as for nanowires: First, a thin layer of SiN
x
was deposited onto the
GaAs substrate by plasma enhanced chemical vapor deposition (PECVD). The
thickness of SiN
x
mask was around 28 nm. Nanoscale stripes were patterned onto the
substrate by electron-beam lithography and reactive ion etching was used to transfer
patterns from the photoresist into the SiN
x
mask. The orientation of 5 m μ long, 100
nm wide stripes was patterned parallel to the < 112
2
> direction on (111)B GaAs
substrate and < 011> direction on (100) GaAs substrate. The nanosheet growth was
carried out on these samples using a vertical, showerhead, low-pressure metal-organic
55

chemical vapor deposition (MOCVD) reactor. The growth pressure was 0.1 atm and
the precursors for group III and group V materials were trimethylgallium (TMGa) and
arsine (AsH
3
) respectively. The nanosheets were grown in a hydrogen ambient using
a V/III ratio of 6 or less for 30 minutes at 790 C
o
. The partial pressure of TMGa and
AsH
3
were 3.745x10
-7
atm and 2.392x10
-6
atm, respectively, unless otherwise noted.

3.3 Experimental Results
3.3.1 GaAs nanosheet on (111)B GaAs substrate
Fig. 3.3.1(a) and 3.3.1(b) are the scanning electron microscope (SEM)
images of nanosheet array samples grown with nano-stripes oriented along
> < 2 11 directions. The length of nanosheets is about 5 μm and the thickness is
around 120 nm. The predominant facets exposed on the nanosheet elements are
five equivalent {110} planes: two vertical ) 0 1 1 ( planes, and three inclined
) 0 1 1 ( planes; and the (111)B plane as top surface as shown in Fig. 1(b). The
> < 2 11 oriented nano-stripes shown here were chosen to coincide with the
orientations of the tetrahedral nuclei observed in the studies conducted by Ikejiri
et al.
15
and Yoshida et al.
16
. In those studies, early stage nuclei grown in small
openings were tetrahedra bounded by three {110} planes aligned preferentially
with the long axis of the tetrahedra along either the > < 2 11 or the > < 2 1 1
direction. In the case of nano-stripe patterns, the resultant growths oriented along
the > < 2 11 direction retain the (111)B top surface while the sides are defined
by {110} planes as shown in Fig. 1(c). The nanosheets can be seen as part of a
> < 2 11 tetrahedron structure with two inclined angles of 19
°
and 35.3
°
.
56

Fig. 3.3.1 (a) Macroscopic SEM image of nanosheet arrays. Nano-stripe pattern is 5 μm long and
parallel to <11-2> direction. (b) Microscopic SEM image of a single nanosheet. The inclined surfaces
of the nanosheets are three {110} planes. (C) Schematic diagram of a nanosheet as part of a
<11-2>-oriented tetrahedron.

Cross-sectional transmission electron microscopy (TEM) was performed to
investigate the crystal structure of the as-grown nanosheets. Cross-sectional
TEM images of nanosheets along the ) 0 1 1 ( and the ) 2 11 ( zone axes are
shown in Fig. 3.3.2(a) and 3.3.2(b), respectively. Fig. 3.3.2(c) shows the TEM
image of a typical nanowire grown by SAG using similar procedures but
employing circular patterns instead of nano-stripe patterns. The growth
conditions for forming the nanowires are described in a previous publiction
18
. A
<1-10>
<11-2>
(-10-1)
(0-1-1)
(-1-10)
(111)B
(c)
(a)
10 μm
(b)
2 μm
) 0 1 1 (
) 1 1 0 (
) 1 0 1 (
) 0 1 1 (
> < 2 11
°
3 . 35
°
19
57

high density of twins is observed within the nanowire structure, while no twins
exist within the nanosheets. From the TEM results in Fig. 3.3.2, the shape and
orientation of the patterns seem to play an important role in twin formation
within nanostructures thus providing a growth window for twin-free SAG
nanosheets.

Fig. 3.3.2 (a) Cross-section TEM image of a nanosheet from <1-10> zone axis. (b) Cross-section TEM
image of a nanosheet from <11-2> zone axis. (c) Cross-section TEM of a nanowire at <1-10> zone axis.

(a)
2um
Nanosheet
(111)B GaAs
<11-2>
<-1-1-1>
(b)
<-1-1-1>
<1-10>
Nanosheet
SiN
x
Mask
(111)B GaAs
100nm
(c) 100 nm
58

To investigate the growth window for twin-free GaAs nanosheets,
nanosheets were grown under different V/III as shown in Fig. 3.3.3(a)~(c). In Fig.
3.3.3(a) through 3.3.3(c), the TMGa flow rate is fixed and only arsine flow rate
is changed; the V/III ratios for these three samples are 434, 26 and 6 for Fig.
3.3.3(a), 3.3.3(b) and 3.3.3(c) respectively. The lateral growth of nanosheets is
reduced as the arsine flow rate decreases. Also with higher arsine flow rate, the
uniformity of nanosheets becomes worse and the facets other than {110}
surfaces are formed as shown in the white circle region in Fig. 3.3.3(a). Because
twin-free nanosheets are enclosed by five {110} planes as shown in Fig. 1(b), it
is possible that surfaces other than {110} planes arise from the merging of
> < 2 11 and > < 2 1 1 oriented tetrahedral nuclei. When the arsine flow rate is
reduced, only five equivalent } 0 1 1 { surfaces are formed. Perfect, uniform
nanosheets are formed when V/III ratio is reduced to 6. If the growth time is
increased while V/III ratio is fixed at 6, the inclined surfaces of nanosheets are
terminated at the tips and thus forming sail-like nanosheets, as shown in Fig.
3.3.3(e). However, some nanosheets show a rotated triangular shape near their
tips as shown in the circled regions. The rotated triangular tips can be eliminated
with increased TMGa flow rates as shown in Fig. 3.3.3(d). Since nanosheets can
be treated as a segment of > < 2 11 tetrahedra, the rotation of its triangular
shape may imply the development of a twin at the tip of the nanosheets, as
proposed for nanowires in Ikejiri's
15
model.
59

Fig. 3.3.3 (a)~(c) SEM images of nanosheets grown under different growth conditions. (d) Nanosheets
growth with increased TMGa flow rate which shows suppression of rotated triangular tip. (e)
Nanosheets growth under V/III = 6 shows rotated triangular near their tips.

(d)
TMGa = 2.4 sccm; V/III= 2
(a)
arsine = 17 sccm; V/III = 434
(b)
arsine = 1 sccm; V/III = 26
(c)
arsine = 0.25 sccm; V/III = 6
(e)
TMGa = 0.8 sccm; V/III= 6
2 μm
10 μm
2 μm 5 μm
2 μm
60

Fig. 3.3.4(a) shows the cross-sectional TEM image of the rotated-tip
nanosheet in Fig. 3.3.3(e) along the > < 0 1 1 zone axis. According to the TEM
image, the nanosheet can be interpreted as stacking of two triangles with a
boundary line between them. Fig. 3.3.4(b) shows a high-resolution TEM
(HRTEM) image near the boundary line in the square region in Fig. 3.3.4(a). As
shown in Fig. 3.3.4(b), the atomic arrangements in the two sections are in mirror
symmetry, which is also confirmed by the fast Fourier transform (FFT) images
of the different regions shown in Fig. 3.3.4(c) through Fig. 3.3.4(e). Fig. 3.3.4(d)
shows the FFT images of atomic arrangements near the boundary line, an
overlap of Fig. 3.3.4(c) and 3.3.4(e); the extra diffraction spots at the 1/3 of the
original reflections in Fig. 3.3.4(c) arise from twinning within the nanosheet. The
boundary line in Fig. 3.3.4(a) is a rotational twin plane near the tip of the
nanosheet. Moreover, by measuring the angles of the inclined facets on the two
stacking triangles in Fig. 3.3.4(a), the upper triangle is rotated by 180
°
relative
to the bottom triangle. Therefore, the upper triangle can be assigned as part of a
> < 2 1 1 tetrahedral structure; and the bottom triangle is part of a > < 2 11
tetrahedral structure. Combining the TEM and SEM characterizations, once a
twin is developed, the surface morphology of nanosheets is altered by the twin
formation resulting in a 180
°
rotation of the triangles near the tip. Such behavior
agrees with Ikejiri's
15
model for a nanowire in which twins are developed
between the > < 2 11 and > < 2 1 1 nuclei that subsequently form on the
(111)B plane.
61

33.32
o
18.52
o
20.62
o
33.58
o
(a)
(b)
(c)
(d)
(e)
(c)
(d)
(e)
(b)
68.07
o
62

Fig. 3.3.4 (a) TEM image of cross-section nanosheet along <1-10>direction. The nanosheet is composed
of two stacking triangles; the upper triangle is 180° rotated with similar feature of the beneath one. (b)
HRTEM image of the boundary between beneath and upper triangles. Stacking sequences of GaAs are
different at the two sides of the boundary which implies that this boundary is actually a twin plane.
(c)~(e) FFT images of different regions near twin plane. (f) Growth mechanism of twinned nanosheets.

Another change which comes after twin formation is the facet transition of
the bottom triangle growth: in Fig. 3.3.4(a), before twin was developed, the
initial triangle growth with two inclined angles of ~19
°
and ~33.58
°
enclosed by
white dotted lines was grown; one of its inclined angles increased from ~33.58
°
to
~68.07
°
corresponding to a transition of the inclined surface from a ) 0 1 1 (
plane to a (111)A plane after twin formation. The growth mechanism of the
twinned nanosheet can be deduced from the transition morphology of the
nanosheets as shown in Fig. 3.3.4(f). First, a twin-free nanosheet which is part of
a > < 2 11 tetrahedron structure forms. As the inclined facets approach the
pinch off point, a single twin is initialized on the top of (111)B surface as the 2
nd

step in the process. After a single twin is initialized, the nucleation change from a
(f)
1.Twin-free NS growth 2.Twin initializes 3.<-1-12> tetrahedron structure
initializes
4.Kink forms due to out-
expansion of <-1-12>
tetrahedron structure
5.Growth initializes at kink
regions.
6.Growth on inclined
surfaces
63

> < 2 11 tetrahedron to a > < 2 1 1 tetrahedron, and a 180
°
rotated triangle
growth is formed which is the 3
rd
step. After that, kinks are formed on the two
inclined surfaces of nanosheet which arise from the outward expansion of the
upper triangle growth on the plateau as shown in the schematic of the 4
th
step. In
the 5
th
step, growth starts to initialize in the kink regions. In twin-free nanosheets,
the growth rates on the two inclined surfaces are very slow; however, once kinks
are formed, they can serve as additional sites to promote epitaxial re-growth on
the inclined surfaces of the nanosheets. In the 6
th
step, due to the confinement of
the pattern, the growth on the inclined surfaces will not extend to the masked
region, and therefore (111)A surfaces (with lower surface energies than (110)
surfaces) are preferred terminating surfaces under SAG conditions once twin is
formed.
Nanosheet growths on specifically-designed nano-stripe patterns were also
studied. Fig. 3.3.5(a) shows nanosheets growth on different length of nano-stripe
patterns. Sail-like nanosheets are formed within shorter nano-stripe pattern while
longer nano-stripe patterns still keep a (111)B plateau on the top surface. The
inclined {110} surfaces of nanosheets self-limit the height of nanosheets once
the two sides of inclined surfaces are pinched off at the tip. Given enough growth
time, the height of nanosheet is eventually determined by the length of the
nano-stripe pattern; this means the longer the nano-stripe pattern is, the taller the
nanosheets are as seen in Fig. 3.3.5(a).

64

1 2

3 μm
2 μm
5 μm
(a)
(a)
65

3 4

Fig. 3.3.5 (a) Nanosheets growth on different length of nano-stripe patterns. (b) SEM images of
nanosheets growth on different nano-stripe patterns. Schematics of nano-stripe patterns for nanosheets
are shown in the insets.
Specifically-oriented nano-stripe patterns shown in Fig. 3.3.5(b) were
attempted to eliminate the inclined } 0 1 1 { surfaces, and their corresponding
growth results are shown in Fig. 3.3.5(b). In these sub-images, the direction of
the arrow denotes three equivalent > < 2 11 directions on 3-fold symmetric
(111)B GaAs substrate. In the 1
st
pattern, the > < 2 11 side and > < 2 1 1 side
of different nanosheets intersect. As can be seen, the lateral growth is enhanced
at these intersections. Similar behavior also occurs in the 2
nd
pattern: vertical
side-walls of nanosheets disappear due to serious lateral growth and nanosheets
coalesce with one another other over the mask region. The intersection of
different sides of nanosheets exhibited distinctive growth behavior: as shown in
the 3
rd
and 4
th
pattern, when two > < 2 1 1 sides of neighboring nanosheets
intersect, lateral growth is still limited by the nano-stripe pattern; on the other
hand, if two > < 2 11 sides of neighboring nanosheets intersect, significant
lateral growth is observed. Significant lateral growth was observed as long as the
10 μm 10 μm
(b)
66

> < 2 11 side of nanosheet intersects with any side of another nanosheet as
shown in the 1
st
and 4
th
pattern. Due to the differences in lateral growth rate at
the intersection of nanosheets, nano-stripe patterns could be used to achieve
various nano-structures; for example: a thin, twin-free GaAs layer could possibly
be grown by intersecting the > < 2 11 sides of nanosheets as shown in the 2
nd

pattern. In addition, taller nanosheets could be formed by intersecting two
> < 2 1 1 sides of different nanosheets as shown in the 3
rd
pattern. By
intersecting two > < 2 1 1 sides of nanosheets, it is possible to achieve
nanosheets with 1.5 times height of nonintersecting nanosheets.

3.3.2 GaAs nanosheet on (100) GaAs substrate

Fig.3.3.6 Schematic of different crystal orientations on (100) GaAs substrate. (a) Side-view of (100)
GaAs substrate along <011> direction. (b) Top view of (100) GaAs substrate along <100> direction.

Similar nano-stripe patterns were created on (100) GaAs substrate for
nanosheet growth. On (100) GaAs substrate, nano-stripe was along < 011>
direction. Fig.3.3.6 shows side-view and top-view of (100) GaAs substrate.
Fig.3.3.6(a) shows the side-view image of (100) GaAs substrate viewing along
<011> direction. The angle between <111>B and (100) plane is 35.3° as can be
seen in Fig.3.3.6(a) where two tilted nanowires are shown on (100) GaAs
substrate. Fig.3.3.6(b) shows the top-view image of (100) GaAs substrate
(100) GaAs
<111>B <111>B
<100>
<011> > < 1 1 0
(a)
°
3 . 35
(b)
<011>
<100> > < 1 1 0
<111>B <111>B
Nano-stripe
67

viewing along <100> direction. Two nanowires are drawn to show the
orientation relation between <011> nano-stripe and nanowires. From the
top-view image, two nanowires are perpendicular to <011> nano-stripe pattern.
Different growth conditions were tested for nanosheet growth on (100)
GaAs substrate. The flow rate of TMGa was fixed at 0.8 sccm as used for
nanosheet grown on (111)B GaAs and the arsine flow rate ranged from 0.25
sccm to 17 sccm. The value of V/III ratio for these growth runs ranges from 7.24
and 492. The growth results of nanosheet on (100) GaAs substrate are shown in
Fig.3.3.7.

Fig.3.3.7 (a) Sample L4050, grown with TMGa 0.8 sccm, arsine 17 sccm (V/III ratio 492); (b) Sample
L4017, grown with TMGa 0.8 sccm, arsine 5 sccm (V/III ratio 144); (c) Sample L4018, grown with
TMGa 0.8 scm, arsine 0.25 sccm (V/III ratio 7.24).

In Fig.3.3.7(a), GaAs deposition showed tilted (111)B planes at the two
sides; and when the partial pressure of arsine decreased, two (111)B planes were
(a)
(b)
(c)
68

kept on the top while vertical (01
2
1) planes started to develop at the side wall.
When arsine partial pressure was decreased further to 0.25 sccm, as shown in
Fig.3.3.7(c), GaAs deposition started to grow vertically as nanosheet structure on
(111)B substrate.
Due to insufficient Ga source supply, the growth rate of GaAs nanosheet on
(100) substrate (sample L4018) was limited and was about merely 0.5 /sec. To
increase the growth rate of GaAs nanosheet on (100) substrate, TMGa flow rate
was increased from 0.8 sccm to 2.4 sccm and arsine flow rate was kept at 0.25
sccm which corresponds to V/III ratio 2.41. The growth result is shown in
Fig.3.3.8:

Fig.3.3.8 Sample L4069 (a) GaAs nanosheet on (100) GaAs substrate has two facets on both sides of
tilted planes. (b) Shorter nanosheets develop twin defect near the tip of nanosheets. (c) Rotated triangles
formed at the tip of nanosheet grown on (100) GaAs substrate.

(a)
(b) (c)
69

Like nanosheet grown on (111)B substrate, in Fig.3.3.8(a); nanosheet grown
on (100) is enclosed by two vertical (110) planes and two (110) facets on both
sides of inclined edges of nanosheet structure due to two-fold symmetry of (100)
plane. On the top of nanosheet, two (111)B planes are formed instead of (100)
planes. Due to the existence of (111)B planes, twin defects start to occur when
the area of (111)B planes shrinks as shown in Fig.3.3.8(b). As can be seen, near
the tip of some nanosheets, other facets start to develop. Higher magnification
image is shown in Fig.3.3.8(c); in the picture, rotated triangles are formed at the
tip of nanosheet. Since triangles originated from (111)B planes and are rotated
180
°
with respect to each other, these rotated triangles may result from twin
defects of two (111)B planes on the top of nanosheet. Another sample: L4067
was grown under similar growth condition as L4069 but the arsine flow rate was
further decreased from 0.25 sccm to 0.15 sccm, and the TMGa flow rate was
kept; and V/III ratio became 1.45.

Fig.3.3.9 Sample L4067 (a) No rotated triangles are observed at the tip of nanosheets. (b) Shorter
nanosheets stopped growing but longer nanosheets haven’t pinch off.

In Fig.3.3.9(a) and Fig.3.3.9(b), no rotated triangles were observed at the tip
of nanosheet under low arsine partial pressure. And like nanosheet on (111)B
substrate, the height of nanosheet is determined by its length because it stops
(a) (b)
70

growing when two inclined planes have pinched off at the tip. Therefore, the
longer the nano-stripe (which determines the length of nanosheet), the taller the
nanosheet: in Fig.3.3.9(b), long nanosheets are not pinched off but shorter
nanosheets already pinched off and stopped growing.

3.4 Discussion
In this chapter, we have altered the shape of the opening to be nanometer wide
stripes aligned along the equivalent > < 2 11 directions that promote the formation of
{110} sidewall facets. Early stage nucleation in these stripes are tetrahedra with their
axis pointing along the > < 2 11 or > < 2 1 1 directions. These structures merge to
form the final structures. However, twins are quickly formed at the initial stage of
nanowire growth and thus three inclined ) 0 1 1 ( planes disappear while nanosheets
maintain these inclined ) 0 1 1 ( planes. Under growth conditions with higher AsH
3

partial pressures, mixed nucleation of > < 2 11 or > < 2 1 1 oriented nuclei form
and the bounding planes are all inclined ) 0 1 1 ( planes. There is a greater tendency
for part of the structure to exhibit an apparent twinned region along the stripe that
results from the merger of > < 2 1 1 and > < 2 11 oriented tetrahedron, as shown in
the circled region of Fig. 3.3.3(a). However, if growth is carried out under nanosheet
growth conditions at low AsH
3
partial pressures, nucleation of > < 2 1 1 oriented
tetrahedra are not favored and uniform nanosheets enclosed by three inclined ) 0 1 1 (
planes and two vertical ) 0 1 1 ( planes are formed as shown in Fig. 3.3.1(b). Under
such circumstances, the nanosheet is composed of only > < 2 11 oriented tetrahedra
71

and no 180
°
rotation twins will be formed. Nearly twin-free nanostructures can thus
be fabricated.
Growth behavior of GaAs nanosheets under different growth conditions was
further studied; twinning in nanosheets was found significantly suppressed unlike
nanowire structures which hold high twin density. The inherent property of frequent
twin defects within nanowire structures made it difficult to investigate and analyze the
cause of twinning. The morphology transition and facet formation of twinned
nanosheets, by contrast, show the slow-down process resulted from twin formation
and thus made nanosheet the best platform for studying twinning. From our nanosheet
study, twinning depends on both the thermodynamics and kinetics of the selective
area growth.
In Fig. 3.3.3, twinned or twin-free nanosheets can be formed under certain range
of AsH
3
and TMGa partial pressures. Low AsH
3
and high TMGa partial pressures are
required for twin-free nanosheets; however such growth condition corresponds to
quite low V/III ratio (less than 6) which doesn’t fall in the range of nanowire growth
condition. Considering thermodynamics
19
, the driving force for twin formation is
increased under low AsH
3
and high TMGa partial pressures. This observation
confirms that twinning is driven by the high chemical energy of MOCVD precursors
and is allowed thermodynamically.
The same growth condition for twin-free nanosheets was applied to round
opening holes and the yield of nanowire growth was found to be greatly reduced,
where most of depositions were tetrahedron growth. In a pair of papers
15,16
from
Hokkaido University, a model for formation of nanowires by selective area growth
has been proposed; it is hypothesized that under the conditions of growth (low
temperature and high AsH
3
partial pressure) used for the formation of nanowires,
72

tetrahedral nuclei bounded by {110} planes were aligned with the dominant axis of
the tetrahedra pointing to the > < 2 11 direction. Repetitive twinning results in the
formation of the hexagonal structure which is characteristic of nanowires. In this
scenario, if growth condition for twin-free nanosheets is applied to round opening
nano-patterns, the nanowire structure is less likely to form. Such a phenomenon well
supports Ikejiri’s
15
model and may explain the difficulties of forming twin-free
“hexagonal” nanowires by selective area growth.
Since round and stripe patterns result in different shapes of nanostructure growth,
the twin formation in the nanostructures may be explained by their surface energy.
The analysis of surface energy for nanowire vs. nanosheet structures along with the
change of surface energy due to twin formation may provide a clue for reducing
twinning. Observing the morphology change of nanosheets during twin formation,
three inclined ) 0 1 1 ( planes are replaced by three (111)A planes which have a lower
density of dangling bonds. Since surface energy is related to the density of dangling
bonds, the enclosed surface of the nucleation tetrahedra change from three inclined
) 0 1 1 ( planes to (111)A planes resulting in a decrease of surface energy. Thus,
twinning can provide a way to reduce surface energy. Due to the high surface/volume
ratio of nano-structures, the influence of surface energy is more important than its
bulk energy; thus twinning would be preferred if they can dramatically decrease
surface energy of nanostructure by paying a small penalty --- the formation energy of
twins.
73

Fig. 3.4.1 (a) Schematic diagrams of twin-free and twinned cases for a nanowire structure. (b) Schematic
diagrams of twin-free and twinned cases for a nanosheet structure.

(a)
(b)
74

The effect of surface energy reduction from twinning for different patterns can
thus be analyzed. In the following, total surface energy change is calculated before
and after twin formation with the assumption that the GaAs nucleation is first defined
by three inclined } 0 1 1 { planes and then by three A } 111 { planes after the twin is
formed: experimentally, the GaAs nanosheets without twins were observed to be
bounded by } 0 1 1 { planes, whereas the nanosheets with twins were found to be
bounded by A } 111 { planes after re-growth on inclined planes. We begin by
calculating the total surface energy of a nanowire; because a round pattern is used for
nanowire, the surface energy of a tetrahedron is considered. Fig. 3.4.1(a) shows the
schematics of nanowire structure for twin-free and twinned cases. In the calculation,
only a single twin is considered. The surface energy of semi-tetrahedron with height h
is calculated for both twin-free and twinned cases; however in the twinned case, a
single twin occurs just at the top surface of semi-tetrahedron: when the height of
semi-tetrahedron equals to h, a single twin is formed and after that the enclosed
surfaces of semi-tetrahedron are changed. So total surface energy including the twin
energy per unit volume (in the following, Avg_E will be used as an abbreviation) can
be derived for both cases from following equations:
Twin-free:

Twinned:

Within above equations, ①~③ denote the surface area of three inclined
planes and ④ denotes the surface area of top (111)B planes for the twin-free case; and
①’~③’denote the surface area of three inclined planes and ④’ denotes the
[(①+②+③) x E(-1-10) + ④ x E(111)B]/Volume_TwinFree
[(①’+②’+③’) x E(111)A + ④’ x E(111)B + Twin_E]/Volume_Twin
) 0 1 1 (
A ) 111 (
75

surface area of top (111)B planes for the twinned case. 0) 1 1 E( , E(111)A and
E(111)B denotes surface energies of , (111)A and (111)B surfaces of GaAs.
Fig. 3.4.2(a) shows the calculated Avg_E for both cases with surface energy of
different facets from Sibirev's
20
study; the radius of the round pattern is set to 150 nm.
In the figure, the Avg_E of semi-tetrahedron with and without a single twin at
different h is plotted. As can be seen, the Avg_E of the twinned case is always lower
than that of twin-free case, and the difference increases dramatically when h
approaches 50 nm which is the height of the apex of {110} bounded tetrahedron. Thus,
surface energy considerations always favor twin formation during nanowire growth
because it reduces surface energy of tetrahedral nuclei. From the Fig. 3.4.1(a), surface
energy difference increases dramatically when it reaches the apex of the tetrahedron
which means that twin is more favored at the apex; thus larger opening holes would
help to decrease twin density because it can postpone a dramatic increase in the
energy differences. This trend is essentially what Ikejiri
15
found. Similar calculations
are also performed for the nanosheet structure: schematic diagrams of twin-free and
twinned nanosheets are shown in Fig. 3.4.1(b), and Avg_E for both cases are
calculated from following equations:
Twin-free:

Twinned:

Fig. 3.4.2(b) shows the Avg_E of nanosheets with different lengths. The
thickness of nano-sheet is set to 150 nm in the calculation. The trend of Avg_E is
different in nanosheets structures: Avg_E of the twin-free case is lower than that of
twinned case for a range of h values for the nanosheet structure of different lengths as
shown in Fig. 3.4.2(b). Therefore, compared to nanowire structure, twin formation is
) 0 1 1 (
[(①+②+③+⑤+⑥) x E(-1-10) + ④ x E_(111)B]/Volume_TwinFree
[(①’+②’+③’) x E(111)A + ④’ x E(111)B+ (⑤’+⑥’) x E(-1-10) + Twin_E]/Volume_Twin
76

not energetically favored in the nanosheet structure. Thus, twin-free nanosheets can be
formed. When the length of the nanosheet increases, the Avg_E difference between
twin-free and twinned cases increases which means that the height of twin-free
portion of nanosheet can be increased with longer nano-stripe patterns. As shown in
Fig. 3.4.2(b), the Avg_E of twin-free and twinned case intersects at specific height h
and after that the Avg_E of twinned case becomes lower. That specific height h is
very close to the height of nanosheet's tip. This helps to illustrate why twinning is
likely to occur near the tip of nanosheets similar to what is observed in Fig. 3.3.4(a).
From above, a model based on minimization of the surface energy seems to explain
the tendency for nanowires to form twins and for nanosheets to form without them.
Since the influence of surface energy is more significant in nanostructures, twin
defects become favored if the structure formed reduces the surface energy more than
the penalty energy it incurs in forming the twin. In a nanowire structure, three {110}
planes of a tetrahedron turn into three {111} planes after twin formation; thus surface
energy is greatly lowered with twin defects. However, due to the confinement of the
nano-stripe, a nanosheet has two stable vertical ) 0 1 1 ( planes that will not be
transformed into {111} planes when a twin occurs. Since the area of these two vertical
planes is the majority part of total surface area in the nanosheets structure, the surface
energy reduction resulting from twinning is not as dramatic as that in the nanowire
structure. From point of view of kinetics, this appears to explain why the nanosheet
structure has lower twin probability than nanowire structure.
77

10 20 30 40 50 60
1E-20
1E-19
1E-18
1E-17
Radius of holes = 150nm
Twin-free NW
Twinned NW
Energy per Volume(J/nm
3
)
h (nm)

1 10 100 1000
1E-21
1E-20
1E-19
1E-18
1E-17
1E-16
Energy per Volume(J/nm
3
)
h (nm)
Twin-free NS_200nm
Twinned NS_200nm
Twin-free NS_1um
Twinned NS_1um
Twin-free NS_5um
Twinned NS_5um
Nanosheet thickness = 150nm

Fig. 3.4.2 (a) Total surface energy plus twin energy per unit volume for twin-free and twinned nanowire
structures. (b) Total surface energy plus twin energy per unit volume for twin-free and twinned nanosheet
structures with different length.

(a)
(b)
78

Surface energy reduction is the likely cause of high density of twins observed
within nanostructures. If there is a way to avoid or eliminate the surface energy
reduction caused by twinning, there may be ways to form other twin-free
nanostructures like the nanosheet. It is still unknown why the starting form of
tetrahedron is bounded by {110} planes rather than {111} planes even though {111}
surfaces have lower energy. From the observed morphology transition that occurs in
nanosheets upon twin formation as shown in Fig. 3.3.4(f), surface energy reduction
actually comes after formation of a kink at the boundary of the twin. The formation of
{111} planes seems require the formation of kinks. If there is a way to form a kink
without twins, or if it is possible to grow {111} bounded nuclei directly, surface
energy reduction would be achieved without the occurrence of twinning; therefore it
may be possible to form SAG grown twin-free nanowires.

3.5 Conclusions
Several reports have revealed twin-free GaAs nanostructures by
vapor-solid-liquid growth techniques; however twin-free nanostructures have not
previously been observed when formed by selective area growth techniques. GaAs
nanosheets grown on (111)B GaAs substrates are the first twin-free GaAs
nanostructures grown by SAG technique. From the study of nanosheets, two ways to
reduce twinning are suggested: 1
st
is using thermodynamic method by operating under
growth conditions which result in a low driving force for twinning effect. The 2
nd

method is using specifically designed patterns like the nano-stripe within which the
contribution to the surface energy of the two vertical planes increases that
mitigates the surface energy benefit brought by twin formation and thus makes
twinning less favored from the kinetics point of view. From the study of twinning
effects in nanosheets, forming {111} bounded tetrahedron nuclei or growing kinks
79

without twins could be the possible solution to SAG grown twin-free nanowires.
Further studies of nanosheets will be focused on the optical and electrical properties.

3.6 Reference
(1) Huang, Y.; Duan, X.; Cui, Y.; Lauhon, L. J.; Kim, K. H.; Lieber, C. M. Science
(New York, N.Y.) 2001, 294, 1313–7.
(2) Bertness, K. A.; Kurtz, S. R.; Friedman, D. J.; Kibbler, A. E.; Kramer, C.;
Olson, J. M. Applied Physics Letters 1994, 65, 989.
(3) Takamoto, T.; Ikeda, E.; Kurita, H.; Ohmori, M. Applied Physics Letters 1997,
70, 381.
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82

Chapter 4 Growth of GaAs thin-film on lattice-mismatched
substrate
4.1 Introduction
GaAs nanowires with hexagonal shape result from repeated formation of a high
density of twins as disclosed in Chapter 3. Energy barriers may exist within nanowires
at these twin boundaries
1
and thus inhibit carrier transport
2–7
in nano-structured solar
cells. Therefore, a way to grow defect-free GaAs materials on silicon substrates is
required. In the previous chapter, nanosheet structures grown from nano-stripe
patterns was confirmed to be a defect-free material whose lateral growth rate can be
greatly enhanced by intersecting nano-stripes. With enough time, crossed nanosheets
would eventually coalesce as continuous thin films which are also defect-free.
Therefore, defect-free GaAs thin films may be obtained on lattice-mismatched
substrates such as silicon by first growing nanosheets from unmasked regions using
SAG and then laterally growing over masked regions to form a continuous thin film
as a 2
nd
step. In this chapter, the growth of GaAs thin films on lattice mismatched
substrates will be performed and the quality of coalesced GaAs thin films will be
examined by cross-section TEM.

4.2 Growth mode on lattice mismatched substrate
To integrate GaAs materials onto silicon substrates is the main goal of this
chapter; however there are some constraints. First, there is a lattice mismatch of
approximately 4% between GaAs and silicon which makes it difficult to grow
defect-free GaAs material on silicon. Furthermore, silicon is a non-polar material
whereas GaAs is a polar material which can result in the formation of As-seeded and
Ga-seeded regions or domains that do not match at the atomic level upon coalescence.
83

We refer to the formation of these strautures as “multi-domain issues” in the rest of
this chapter. In this section, I will focus on the growth mode on lattice mismatched
substrates, and in the next section I will discuss growth on non-polar surfaces.
Epitaxial thin film growth mode depends critically on the interaction between
adatoms and the surface. Three different growth modes
8–10
occur as shown in
Fig.4.2.1. If the interaction between adatoms and other adatoms is stronger than that
between adatoms and the surface (V olmer-Weber growth), the so-called island
formation growth mode would dominate: adatoms tend to attach to each other, which
leads to three dimensional cluster or island growth. At the other extreme, if the
interaction between adatoms and the surface is stronger (Frank-van der Merwe
growth), the so-called layer-by-layer growth mode, dominates. In this mode, adatoms
preferentially attach to crystal surfaces to grow in a two-dimensional film, which
results in atomically smooth surfaces. In between these two growth modes
(Strankski-Krastanov growth) the so-called layer-plus-island growth mode would
dominate. Strankski-Krastanov growth is an intermediate mode between Frank-van
der Merwe and V olmer-Weber growth modes which features both 2D and 3D growth.
Below a critical thickness, the growth mechanism follows Frank-van der Merwe mode
and then transitions from layer-by-layer growth to V olmer-Weber growth mode as
shown in Fig.4.2.1(c). In Stranski-Krastanov mode, when the film thickness exceeds a
critical thickness, the accumulated strain reaches its maximum and then dislocations
occur to relieve the energy as shown in Fig.4.2.1(d). The edge dislocations
highlighted in red are formed at the interface of the film and the island.

84

Fig.4.2.1 Growth modes on lattice mismatched substrates.

The chemical potential of the first few deposited layers should be considered
when determining the growth mechanism. A model for the layer chemical potential
per atom has been proposed by Markov
11
as shown below:

The chemical potential of the deposited layer is related to the bulk chemical
potential, desorption energy of an adsorbate atom from the wetting layer and the
substrate, and misfit dislocation energy and homogeneous strain energy within it. The
criterion for a given film growth mode depends upon
dμ
dn
:

(a) Volmer-Weber (VW: island formation)
(b) Frank-van der Merwe (FM: layer-by-layer)
(c) Stranski-Krastanov (SK: layer-plus-island)
(d)
)] ( ) ( ) ( [ ) ( n n n n
e d a a
ε ε ϕ ϕ μ μ + + ′ − + =
∞
∞
μ :Bulk chemical potential of the adsorbate
a
ϕ
:Desorption energy of an adsorbate atom from a wetting layer of the same
material
) (n
a
ϕ′ :Desorption energy of an adsorbate atom from the substrate
) (n
d
ε :Per atom misfit dislocation energy
) (n
e
ε :Per atom homogeneous strain energy
0 <
dn
dμ
:VW growth (adatom cohesive force is stronger than surface adhesive force)
0 >
dn
dμ
:FM growth (surface adhesive force is stronger than adatom cohesive force)
85

The V olmer-Weber mode occurs when
dμ
dn
< 0 which implies that the adatom
cohesive force is stronger than the surface adhesive force, and thus adatoms tend to
form clusters. When
dμ
dn
> 0, the surface adhesive force is stronger than the adatom
cohesive force, and therefore adatoms attach to surface sites and form a smooth layer,
which is characteristic of Frank-van der Merwe growth.

4.3 Growth on non-polar surface
In Chapter 2, I discussed the step structure and multi-domain issues of (111)
silicon surfaces. Arsenic-passivated (111) silicon surfaces successfully remove the
dangling bonds on (111) silicon surface and pre-form (111) B-like surfaces for
subsequent nanowire growth. In much the same way, multi-domain issues and the
vicinity of the (100) silicon plane play an important role in the integration of III-V
nano-structures on silicon. Detailed discussion of the (111) silicon surface was
addressed in Chapter 2; in the following the characteristics of the (100) silicon plane
will be discussed.

4.3.1 100 Silicon surface
Growing III-V materials on (100) silicon presents issues, such as
lattice-mismatch and multiple domains, as those found for silicon (111) substrates.
Of these two challenges, the multi-domains issue is more difficult one to handle
since lattice-mismatch can be solved by using nano-structures or buffered layers.
However, multi-domain issues between polar and non-polar materials are related
to surface chemical potential, surface reconstruction and step structures, and these
are difficult to control.
86

On a (111) silicon surface, arsenic atoms can easily replace the topmost
silicon atoms and leave an electron lone pair to lower the surface energy. Such
As-Si bonds are quite stable and energetically preferred when compared to Ga-Si
bonds on (111) silicon. Therefore, a (111) silicon surface can be easily passivated
by arsenic atoms to form a (111)B surface using the arsine annealing process.
However, on a (100) silicon surface, electron lone pairs are already formed on the
exposed silicon atoms, and to further reduce the surface energy, the topmost
silicon atoms will form covalent bonds with adjacent surface silicon atoms,
thereby leaving a (2 x 1) reconstructed surface. Due to the tetrahedral stacking of
silicon atoms, (1 x 2) reconstructed surfaces, which are perpendicular to (2 x 1)
reconstructed surfaces, will form on different atomic layers. Therefore, the
as-grown III-V materials from these two reconstructed surfaces would be
90-degree rotated with respect to each other. This is the origin of multi-domains
on (100) silicon substrates.
Much effort has been dedicated to eliminating the multi-domain issue on
(100) silicon substrates. The most common way is to use mis-oriented silicon
substrates. A (100) silicon substrate tilted toward <011> was observed to possess
a single domain surface. The surface steps are parallel to <0-11>, with a step
height of integer multiples of the bi-atomic layer. Therefore, one domain would
self-annihilate
12
near the silicon surface and the other domain dominates.

4.4 Experimental results
To integrate GaAs nanosheets on a (111) silicon surface, hydrogen annealing,
arsine annealing and a nucleation step were used for a (111) silicon surface, following
what Fukui’s
13
method for GaAs nanowires on (111) silicon. The detailed growth
conditions are shown in the following:
87

The hydrogen anneal and arsine anneal steps are similar to those in Chapter 2.
However, the nucleation step was performed at 440
。
C instead of 790
。
C. SEM images
of the growth results are shown in Fig.4.4.1:
Fig.4.4.1 SEM images of GaAs nanosheets on a (111) silicon substrate.

Discontinuous, short GaAs nanosheets grown on a (111) silicon substrate are
shown in Fig. 4.4.1. 180
°
rotated nanosheets were observed as well, as indicated in
the red circle. This may be the result of the twinning effect at the nucleation step.
Unlike nanosheets grown on lattice matched substrates, the nanosheets in Fig. 4.4.1
were enclosed by (110) facets and other unknown facets, which implies a
multi-domain issue at the GaAs/silicon interface. As in the low temperature nucleation
experiments in Chapter 2, the deposition rate of GaAs was not high enough to cover
the un-masked region and thus discontinuous, short GaAs nanosheets were formed, as
L3874
L3874 L3874
88

can be seen in Fig. 4.4.1(b). To improve GaAs coverage over the un-masked region, a
series of experiments were performed at a higher nucleation temperature of 740 for
varying periods of time. The growth conditions employing high temperature
nucleation are shown below:

Samples were first annealed at 925 for 5 minutes to clean the native oxide,
and then the temperature was ramped down to 740 with arsine flow to passivate
the (111) silicon surface, and to transform it to a (111)B-like surface. After annealing
for 15 minutes, a high temperature nucleation step was performed for 60 seconds, 150
seconds and 300 seconds for different samples. The arsine and TMGa partial pressure
at this step is approximately 5.43x10
-4
and 1.42x10
-5
atm respectively, and the V/III
ratio is 38. Another set of samples were grown based on these three different periods
of high temperature nucleation plus GaAs nanosheet growth conditions at 790 .
SEM images for these samples are shown in Fig. 4.4.2
Nucleation
period
Only nucleation Nucleation + nanosheet
T emp (C)
925
740
300
5
50 sccm 10 sccm
15
T (min)
30.27 sccm
89

60s
150s
300s
Fig.4.4.2 SEM images of GaAs nucleation experiments with different periods. SEM images of
nucleation only and nucleation plus nanosheet growth are both shown.

As shown in Fig. 4.4.2, with increasing nucleation period, GaAs was eventually
deposited on all of the un-masked regions. Though some spots showed irregular
growth with unknown facets, most nucleations had flat (111)B top surfaces. This
implies that most regions were (111)B-like surfaces, since irregular growth would
result from a (111)A-like surface. However, after applying the GaAs nanosheet
L3898 L3886
L3893
L3903
L3905
L3906
90

growth conditions, the top surface became rugged. Furthermore, the longer the
nucleation period, the rougher the top surface, as can be seen in samples L3903 and
L3906. To investigate crystal orientation of nucleation film, HRTEM images of L3905
were taken and are shown in Fig. 4.4.3:

Fig.4.4.3 TEM images of GaAs thin film growth (L3905) on (111) silicon.

Fig. 4.4.3(a) shows the GaAs/silicon interface of L3905. The left part of the
GaAs deposition has a flat (111)B plane and the right part of deposition has a tilted
plane. The transition from a (111)B plane to a tilted plane occurred at the region
where the two nucleations coalesced. The higher magnification SEM image is shown
in Fig. 4.4.3(b). It can be seen that the base of each nucleation possessed a high
density of twins, although these disappeared at a certain thickness after the
nucleations coalesced, which transformed the nucleation on the right to a defect-free
(a)
(b) (c)
(b)
(c)
Twins
Twin-free GaAs
(111)B plane
Dislocation
Silicon
GaAs
SiNx
Silicon
Silicon
GaAs
GaAs
91

structure as shown in Fig. 4.4.3(b). Another coalescence occurred at the right side of
the thin film, and the magnified TEM image of this region is shown in Fig. 4.4.3(c),
which appears similar to Fig. 4.4.3(b). Twins were eliminated on both sides of the
nucleations after coalescence, and a dislocation was developed. To interpret the
growth mechanism of these phenomena is difficult due to the fact that there are
multiple phenomena occurring between the GaAs/silicon interface such as strain and
multi-domain issues. Moreover, due to twin defects, the crystal orientation of each
nucleation might be different, leading to another multi-domain problem.
To distinguish and isolate those factors, growth was performed on a (111)B GaP
first, then on a (111) silicon substrate. The advantages of growing on (111)B GaP
substrates are (1) GaP is already a polar substrate, and (2) the lattice constant of GaP
is similar to silicon, and thus the strain and non-polar effects on growth behavior can
be differentiated.

4.4.1 Growth on (111)B GaP substrates
Pattern design and growth conditions
Single or crossed nano-stripes were patterned by e-Beam lithography as
shown in Fig. 4.4.4.

Fig. 4.4.4 Schematic image of nano-stripe patterns created by e-Beam lithography.
1µm
1
st
pattern
2µm
1µm
0.5µm
2
nd
pattern
11-2
1-10
92

In the 1
st
pattern, each nano-stripe was along 3 equivalent <11-2> directions.
The pitch between each nano-stripe was 1 µm and the width of the nano-stripes
was 100 nm. The length of a single nano-stripe in the 2
nd
pattern was 2 µm and
the width was approximately 100 nm. The separation between adjacent
nano-stripes was 1 µm and 0.5 µm in the <1-10> and <11-2> directions,
respectively. The growth was carried out using MOCVD with TMGa, with arsine
as the source of Ga and As. The partial pressures for TMGa and arsine are 3.74 x
10
-7
and 2.71 x 10
-6
atm, respectively. The growth temperature was set at 790℃
with a rotation speed of 10 rpm.
The first growth run was performed by directly applying GaAs nanosheet
growth conditions to a (111)B GaP without a nucleation step. Fig. 4.4.5 shows
the SEM image of the growth results.

Temp (C)
790
300
0.25 sccm 10 sccm
T (min)
2.4 sccm
150
20 sccm
30
L4010
(a)
Arsine
TMGa
(b)
(c) (d)
93

Fig. 4.4.5 (a) Growth conditions of L4010. (b) SEM image of a single GaAs nanosheet on (111)B GaP
substrate. (c) SEM image of GaAs thin film grown from the crossed nano-stripe pattern on a (111)B GaP
substrate. (d) SEM image of GaAs thin film grown from the crossed nano-stripe pattern on a (111)B
GaAs substrate.

During the temperature ramp, arsine was flowed into the reactor when the
temperature was above 150 to protect the GaP substrate. When the
temperature reached 790 , GaAs nanosheet growth conditions were applied as
shown in Fig. 4.4.5(a). GaAs nanosheet growth results on the 1
st
and 2
nd
patterns
on a (111)B GaP substrate are shown in Fig. 4.4.5(c) and Fig. 4.4.5(b),
respectively. For comparison, a film grown from nanosheets on a lattice-matched
substrate with the 2
nd
pattern is shown in Fig. 4.4.5(d). As can be seen, multiple
GaAs depositions were observed within a nano-stripe; one was triangular (which
is similar to the nanosheet structure shown in Chapter 3) and the other was in a
pillar shape, which more closely resembles a nanowire structure. Unlike flat
(111)B top surfaces (as shown in Fig. 4.4.5(d)), the thin film resulting from
crossed nanosheets grown on a lattice-mismatched (111)B GaP substrate had a
rough surface, as shown in Fig. 4.4.5(c). The cause of the rough surface may be
attributed to strain between GaAs/GaP interface, since (111)B GaP is already a
polar surface. Due to a 4% lattice-mismatch, the strain between GaAs/GaP would
increase when the contact area of GaAs/GaP increases. Unlike growing on
lattice-matched substrates, the growth mode of GaAs nanosheets on GaP may
transform from layer-by-layer growth to layer-plus-island or pure island growth
depending upon the strain energy. When the growth mode becomes island
growth, the vertical growth rate increases gradually and the lateral growth rate is
suppressed. Therefore, when strain between GaAs and GaP builds up, the lateral
growth rate decreases gradually, eventually becoming zero when the growth
94

mode enters island growth. The decreasing lateral growth rate of GaAs
nanosheets on lattice-mismatched substrates may imply that there would be a
size limit
14
of GaAs nanosheets. As in Fig. 4.4.5(b), the lengths of triangular
shape depositions at different nano-stripes were almost the same. Also, for the
pillar-like deposition, as can be seen from the figure, the length and the width of
the deposition were quite close. As shown by the calculation for surface energy
in Chapter 3, when the length and the width are close, GaAs nanostructures tend
toward twin formation. Therefore these pillar-like depositions may result from
repeated twin defects, as with the growth mechanism of nanowire structure
mentioned in Chapter 3. Since a twin would rotate the GaAs crystal stacking
structure by 180 degrees on a (111)B plane, two pillar-like depositions may be of
different twin domains, which may in turn prompt irregular growth during
coalescence. Therefore, the rough surface in Fig. 4.4.5(c) may originate from
different twin domains of these pillar-like depositions.
From above experiment, the strain between GaAs and GaP due to a 4%
lattice-mismatch changed the growth mode from layer-by-layer growth to island
growth mode. And each deposition may be of different twin domain and leave
defects within the coalesced thin film. To eliminate the twin domain issue,
additional nucleation was introduced to grow a thin GaAs layer on GaP before
nanosheet growth conditions.
95

Fig. 4.4.6 (a) Growth conditions of L4238. (b) Single GaAs nanosheet on a (111)B GaP substrate. (c)
Coalesced GaAs thin film from crossed nano-stripe pattern on a (111)B GaP substrate.

As shown in Fig. 4.4.6(a), nucleation was performed at 850 with TMGa,
arsine partial pressure 5.85x10
-6
and 1.63x10
-3
atm, respectively, and the V/III
ratio was 278. After nucleation, the temperature was ramped down to 790 for
nanosheet growth. The growth result is shown in Fig. 4.4.6(c) and Fig. 4.4.6(b)
for the 1
st
and 2
nd
pattern, respectively. Within a single nano-stripe, only one
GaAs nanosheet was grown. It should be noted that there were twins near the
tip of the nanosheet which may result from the fact that the probability of
twinning increased dramatically when two tilted planes were about to meet up. A
detailed explanation and calculations were discussed in Chapter 3. In Fig.
4.4.6(c), the top surface was not as rough as that in Fig. 4.4.5(c) – a flat (111)B
GaAs surface was formed. Some voids within the red circle, or tiny holes within
Temp (C)
790
300
0.25 sccm 10 sccm
T (min)
2.4 sccm
150
10 sccm
30
L4238
850
150 sccm
12.5 sccm
45s
20 sccm
Arsine
TMGa
(a)
(b) (c)
96

the orange circle, can be observed on the coalesced film. Since the film was
formed by coalescing crossed nanosheets, these voids and tiny holes may result
from insufficient lateral growth rate in these regions. HRTEM images for the 1
st

and 2
nd
pattern of sample L4238 were as follows:

Fig. 4.4.7 HRTEM images of GaAs nanosheets on a (111)B GaP substrate. (a),(b) A single GaAs
nanosheet on a (111)B GaP substrate. (c),(d) Coalesced GaAs thin film grown on a crossed nano-stripe
pattern on a (111)B GaP substrate.

Fig. 4.4.7(a) shows the cross-sectional TEM images of a GaAs nanosheet
grown on a (111)B GaP . The contrast in brightness near the GaAs/GaP interface
indicates that high strain energy was built up. There were no twins, but a crack
GaP
GaAs
Crack
(a)
GaAs
GaP
(b)
(c)
GaAs
GaP
(d)
GaAs
GaP
SiNx mask
97

was observed within a nanosheet. Fig. 4.4.7(b) is a STEM image of a nanosheet.
The GaAs/GaP interface was brighter than other places, which confirms the high
strain energy between two lattice-mismatched materials. Within the GaAs
nanosheet, there was a region with trapezoidal shape that also had higher
brightness compared to the other regions of the GaAs nanosheet. It should be
noted that the bottom of the trapezoid is brighter than its upper region, which
suggests that the strain energy was higher in the bottom region. In Fig. 4.4.7(a),
the region circled by a dotted line is the bright trapezoid in Fig. 4.4.7(b). One of
the trapezoid edges was along the crack defect. It seems that the nanosheet
initialized from two nanosheets, and the strain energy developed at the region
where they merged together. Due to the 4% lattice-mismatch between GaAs/GaP,
when the thickness of a coalesced thin exceeds a critical thickness, the crack
forms and releases the strain energy between these nanosheets since the
brightness above the trapezoid region was the same as the other regions of the
nanosheet. Fig. 4.4.7(c) and Fig. 4.4.7(d) show the cross-sectional image of a
coalesced thin film grown from the 1
st
pattern on a (111)B GaP substrate. As can
be seen (with the exception of the brightness variation due to the bending of the
sample), no defects were observed within the coalesced GaAs thin film. V oids in
the triangular shape were formed above the SiNx mask in certain regions. The
shape of these voids may inform the method in which the nanosheets coalesced.
Instead of steady growth on a vertical (110) plane, tilted planes showed up
during coalescence and thus left voids in triangular shape above the SiNx mask.
Since the (110) surface of GaAs is stable compared to the other surfaces, the
growth rate is slow on the (110) plane. This is why the GaAs nanosheet is
enclosed by (110) planes as shown in Chapter 3. However, by intersecting
nano-stripes, GaAs deposition grown from the crossed region may have different
98

surface morphology and thus provide a way to form tilted planes for coalescence.
A higher magnification image of GaAs/GaP is shown in Fig. 4.4.7(d). No
defects were developed from GaAs/GaP and only strain induced brightness
contrast was observed. Notice that the GaAs deposition penetrates into the GaP
substrate, which could be due to serious P desorption during temperature
ramp-up.
In summary, additional high temperature nucleation before nanosheet
growth seems to successfully integrate GaAs nanosheets on a lattice-mismatched
GaP substrate. Furthermore, a defect-free GaAs thin film was grown from a
crossed nano-stripe pattern.

4.4.2 Growth on (100) GaP substrate
By using intersecting nano-stripes on a (111)B substrate, the lateral growth
rate of nanosheets can be greatly enhanced and can make coalescence easier.
However, intersecting nano-stripes do not have the same effect on (100)
substrates, as shown in Chapter 3. To make coalescence possible, nano-stripe
patterns with different pitches were fabricated.

Temp (C)
790
300
0.25 sccm 10 sccm
T (min)
2.4 sccm
150
10 sccm
30
L4326
850
150 sccm
12.5 sccm
60s
20 sccm
Arsine
TMGa
(a)
99

Fig. 4.4.8 (a) Growth conditions of sample L4326. SEM images of GaAs nanosheets grown on (100) GaP
with different pitches.

The growth conditions of L4326 was the same as L4238 except that the
nucleation period was increased from 45 seconds to 1 minute. Fig. 4.4.8 shows
the growth result of GaAs nanosheets on a (100) GaP substrate. Coalescence
occurs only when the pitch equals 200 nm; the remaining 3 pitches still have
independent nanosheets. Since the twinning effect is not commonly seen on (100)
planes, nanosheets grown on (100) GaP substrates do not have the multi-domain
issue. Other than discontinuous nanosheets grown on (100) GaP , all have two
vertical (110) planes.
Though coalescence occurred when the pitch of nano-stripes was lowered to
200 nm, it is not extensive enough to coalesce all nanosheets. To improve the
lateral growth rate, the arsine partial pressure was increased while the TMGa
200nm 400nm
600nm 800nm
100

partial pressure was fixed, as follows:

Fig. 4.4.9 (a) Growth conditions of sample L4328. (b) Growth conditions of sample L4329. (c) SEM
image of L4328: GaAs nanosheets with 200 nm pitch. (d) SEM image of L4329: GaAs nanosheets with
200 nm pitch.

The growth conditions of samples L4328 and L4329 are shown in Fig.
4.4.9(a) and Fig. 4.4.9(b), respectively. Both growth conditions are similar to
sample L4326, except that the arsine flow rate was increased from 0.25 sccm to
0.5 sccm and 1 sccm for L4328 and L4329, respectively. The arsine partial
pressure in L4326 was 2.7 x 10
-6
atm, and 5.43 x 10
-6
atm, 1.09 x 10
-5
atm for
L4328 and L4329, respectively. Fig. 4.4.9(c) and Fig. 4.4.9(d) shows growth
results on the nano-stripe pattern with 200 nm pitch. When the arsine partial
pressure increased, the lateral growth rate increased as well. Every 2 or 3
nanosheets merged together in L4328, and every 3 or 4 nanosheets merged
together in L4329. To get a continuous GaAs thin film on (100) GaP , GaAs
planar growth conditions were applied based on the growth conditions of L4329.
Temp (C)
790
300
0.5 sccm 10 sccm
T (min)
2.4 sccm
150
10 sccm
30
L4328
850
150 sccm
12.5 sccm
60s
20 sccm
Arsine
TMGa
(a)
Temp (C)
790
300
1 sccm 10 sccm
T (min)
2.4 sccm
150
10 sccm
30
L4329
850
150 sccm
12.5 sccm
60s
20 sccm
Arsine
TMGa
(b)
(c) (d)
101

Fig. 4.4.10 (a) Growth conditions of sample L4333. (b) Growth conditions of sample L4334. (c) SEM
image of sample L4333. (d) SEM image of sample L4334.

Sample L4333 was based on L4329, but with an additional 20 minutes of
GaAs planar growth conditions. L4334 was the control group within which
nanosheet growth was removed, and GaAs planar growth conditions were
directly applied. The growth results of these two samples were different in the
following two ways: (1) many concave holes were left on the top of L4333, but
L4334 showed a flat (100) GaAs top surface, and (2) the inclined side wall of the
coalesced GaAs thin film was smooth in L4333 but rough in L4334. The concave
holes may have resulted from regions with slow lateral growth, and the rough,
inclined side facets may indicate that the crystal orientation of GaAs is not
uniform. Cross-section TEM images of sample L4333 are shown below:
Temp (C)
790
300
1 sccm 10 sccm
T (min)
2.4 sccm
150
10 sccm
30
L4333
850
150 sccm
12.5 sccm
60s
20 sccm
Arsine
TMGa
(a)
50 sccm
20
30.27 sccm
Nanosheet growth
Planar
growth
Temp (C)
790
300
50 sccm 10 sccm
T (min)
30.27 sccm
150
10 sccm
20
L4334
850
150 sccm
12.5 sccm
60s
20 sccm
Arsine
TMGa
(b)
Planar
growth
(c)
(d)
102

Fig. 4.4.11 TEM images of sample L4333.

In Fig. 4.4.11(a), many defects exist within the coalesced film grown on a
(100) GaP substrate. GaAs deposition penetrated deeply into the GaP substrate,
as shown in Fig. 4.4.11(b). Some line defects indicated by the red arrows started
in the region where two GaAs depositions merged. Since (100) GaP is already a
polar material and not a twin-favored plane, there should be no multi-domain
issues for GaAs growth. The defects may result from strain between GaAs and
GaP only. However, because the GaP surface was damaged during temperature
ramp-up, the contact area between GaAs and GaP increased, which may also
increase the strain energy. To avoid this problem, TBP was flowed during
temperature ramp-up to protect the GaP substrate. The growth conditions and
cross-section TEM images are shown below.
GaAs
GaP
(a)
GaAs
GaP
(b)
103

Fig. 4.4.12 (a) Growth conditions of L4350. (b),(c) TEM images of sample L4350.

The growth conditions of L4350 are shown in Fig. 4.4.12(a). The growth
was the same as L4333 except that TBP was flowed during temperature ramp-up.
Fig. 4.4.12(b) and Fig. 4.4.12(c) are cross-section TEM images of L4350.
Compared with L4333, it can be seen clearly that application of TBP during
temperature ramped up protected the GaP substrate. With a protected GaP
substrate, defects were also reduced and only twins were observed in Fig.
4.4.12(b). A high magnification image is shown in Fig. 4.4.12, in which no line
defects were observed between two un-masked regions. Some twins were
observed which terminated within the thin film, similar to those in Fig. 4.4.12(c).
Some twins extended to the top surface of the GaAs substrate, as shown in Fig.
4.4.12(b). Though the (100) plane is not a twin-favored plane, the shape of the
GaAs nucleation consists of two (111)A and two (111)B surfaces. This may be
Temp (C)
790
300
50 sccm 10 sccm
T (min)
30.27 sccm
150
10 sccm
20
L4350
850
150 sccm
12.5 sccm
60s
40 sccm
Arsine
TMGa
(a)
Planar
growth
TBP
(b)
GaP
GaAs
(c)
GaAs
GaP
twins
104

the surface where twins initialize. The occurrence of twins may result from high
arsine partial pressure during the nanosheet growth step. To eliminate twins,
lower arsine partial pressure should be used, although this may reduce the lateral
growth rate of the nanosheets and thus prevent them from merging as a
continuous film.
Different nano-stripes along various directions were created for coalescence
purposes at low arsine partial pressure. Nano-stripes were created with a
mis-aligned angle from 15 degrees to 45 degrees toward the <0-1-1> direction.
The arsine flow rate was reduced to 0.15 sccm, which corresponds to 1.63 x 10
-6

atm with a V/III ratio of 1.45. SEM images of growth results are shown in Fig.
4.4.13:

Temp (C)
790
300
0.15 sccm 10 sccm
T (min)
2.4 sccm
150
10 sccm
30
L4357
850
150 sccm
12.5 sccm
60s
40 sccm
Arsine
TMGa
(a)
Nanosheet growth
TBP
(b) (c)
105

Fig. 4.4.13 (a) Growth conditions of sample L4357. (b)~(e) SEM images of L4357: GaAs nanosheets on
a (111)B GaP substrate with misaligned nano-stripes along 15, 25, 35, and 45 degrees, respectively.

Fig. 4.4.13(a) shows the growth conditions for sample L4357. The growth
results of the GaAs nanosheets on misaligned nano-stripes are shown in Fig.
4.4.13(b) to (e). The misaligned angles of Fig. 4.4.13(b) to (e) are 15, 25, 35, 45
degrees, respectively. The pitch between nano-stripes was 200 nm. From these
figures, we can see that the shape of the nanosheets was rugged when misaligned,
and the coalescence became more severe as the misalignment angle increased.
When the misalignment angle reached 45 degrees, the facets of deposition
became smooth and the shape of the cross-section became triangular.
Reasonable lateral growth rates can be obtained by introducing misaligned
angles to nano-stripes toward <0-1-1> direction. The next step is to apply
planar growth to form a continuous film based on L4357.
(d) (e)
106

Fig. 4.4.14 (a) Growth conditions of sample L4355. (b)–(d) TEM images of sample L4355.

Fig. 4.4.14(a) shows the growth conditions of sample L4355.
Cross-section TEM images of the coalesced film grown on 45 degree misaligned
nano-stripes are shown in Fig.4.4.14(b) to (d). As was the case for sample L4350,
the GaP surface was well protected with TBP. However, with reduced arsine flow
rate, twin defects were eliminated from L4355. In Fig. 4.4.14(b), it can be seen
that defect density was greatly reduced, and that no threading dislocations nor
twin defects exist. The only observed defects were terminated line defects near
the GaAs/GaP interface, as shown in Fig. 4.4.14(c). A closer image is shown in
Temp (C)
790
300
0.15 sccm 10 sccm
T (min)
2.4 sccm
150
10 sccm
30
L4355
850
150 sccm
12.5 sccm
60s
40 sccm
Arsine
TMGa
(a)
50 sccm
20
30.27 sccm
Nanosheet growth
Planar
growth
TBP
GaAs
GaP
(b)
(c)
GaAs
GaP
(d)
GaAs
GaP
SiNx mask
Line defect
107

Fig. 4.4.14(d), in which it can be seen that some line defects were tilted and
located above the SiNx mask. These line defects may originate from the region
where nanosheets meet. Because of strain between GaAs and GaP , atoms within
the GaAs nanosheet may be shifted from their original locations elastically, and
thus when nanosheets meet, atoms within each nanosheet cannot align well,
which results in line defects. In these regions, misfit dislocation may be
introduced to release strain energy between different nanosheets and thus form
line defects.
Though coalesced GaAs thin films still had some line defects close to the
interface of GaAs and GaP, threading dislocations and twins were eliminated and
defect density was greatly reduced with nano-stripe patterns.

4.4.3 Growth on (111) Silicon substrates
As mentioned in the previous section, there are two issues when growing
GaAs on (111) silicon. The first is lattice mismatch, and the second is
non-polar/polar material growth. In section 4.4.1, a defect-free GaAs thin film
was successfully grown on a (111)B GaP substrate, which has similar
lattice-mismatch conditions as those between GaAs and silicon. To continue
GaAs thin film growth on a (111) silicon substrate, similar high temperature
nucleation conditions were used with an additional hydrogen annealing step on
the (111) silicon substrate. However, GaAs cannot uniformly nucleate among
nano-stripe patterns, which resulted in sparse depositions as shown in Fig.
4.4.15.
108

Fig. 4.4.15 (a),(b) Two different nano-stripe pattern designs on a (111) silicon substrate. (c) SEM image
of GaAs nanosheet growth results on 1
st
pattern. (d) SEM image of GaAs nanosheet growth results on 2
nd

pattern.

Fig. 4.4.15 shows the growth results of sample L4505, for which a high
temperature nucleation step was applied as shown in the growth condition figure
above. The sample was first annealed with hydrogen at 920℃ to remove the
native oxide, and then ramped down to 440℃ for arsine annealing to achieve a
Temp (C)
920
850
300
5
50 sccm
10 sccm
T (min)
25 sccm
L4505
440
5
15 sccm
1.5
11-2
L4505
1000nm
Fill factor: 31.64%
(nano-stripe width=100nm)
(a) (b)
(c) (d)
109

(111)B-like surface formation as mentioned in Chapter 2. After low temperature
arsine annealing, the temperature was increased to 850℃ for high temperature
nucleation for 1.5 minutes. Two nano-stripe patterns were created on sample
L4505 as shown in Fig. 4.4.15(a) and Fig. 4.4.15(b). Nano-stripes were along 3
equivalent <11-2> directions on one pattern, and perpendicular to 3 equivalent
<11-2> directions on the other pattern. As can be seen, sparse GaAs depositions
were observed after high temperature nucleation on both patterns.
Other kinds of patterns were created on sample L4505 as well for
comparison. Their growth results are shown below:

Fig. 4.4.16 (a),(b) Discontinuous nano-stripe pattern designs on a (111) silicon substrate. (b) SEM image
of GaAs nanosheet growth result on 1
st
pattern. (d) SEM image of GaAs nanosheet growth result on 2
nd

pattern.

The two patterns shown in Fig. 4.4.16(a) and Fig. 4.4.16(b) are similar to
the patterns in Fig. 4.4.15(a) and Fig. 4.4.15(b), except that the nano-stripes are
750nm
1000nm
Fill factor: 25.98%
(assum nano-stripe width=100nm)
11-2
(a) (b)
(c) (d)
110

isolated, and the length of each nano-stripes is approximately 750 nm. The fill
factor reduces from 31.64% in Fig. 4.4.15 to 25.98% in Fig. 4.4.16. After
reducing the fill factor, the uniformity of GaAs depositions improved
substantially on both patterns. Unlike Fig. 4.4.15, all nano-stripes are filled with
GaAs depositions.
Another growth run (sample L4507) was then performed with the same
growth conditions but with the nucleation period increased from 1.5 minutes to
10 minutes. The SEM images of the results of this sample are shown below:

Fig. 4.4.17 (a) 1
st
and (b) 2
nd
discontinuous nano-stripe pattern designs on a (111) silicon substrate. (c)
SEM image of L4507: GaAs nanosheet growth results on the 1
st
pattern. (d) SEM image of L4507: GaAs
nanosheet growth results on the 2
nd
pattern.

In the above SEM images, a continuous GaAs thin film was formed by
coalescing isolated GaAs depositions, as shown for sample L4505 in Fig. 4.4.16.
However, the top surface of as-grown GaAs is not smooth and has some
750nm
1000nm
Fill factor: 25.98%
(assum nano-stripe width=100nm)
11-2
(a) (b)
(c) (d)
111

unknown facets and rotated triangle shape plateaus which may result from
rotational twins. TEM images for sample L4505 and sample L4507 are shown
below to compare the crystal quality of the as-grown GaAs thin films:
Pattern #1 Pattern #2

Fig. 4.4.18 TEM images of L4505 and L4507 on 1
st
and 2
nd
patterns.

In Fig. 4.4.18, TEM images of samples L4505 and L4507 at different
pattern regions are shown. In sample L4505, each isolated GaAs deposition is
twinned as shown in Fig. 4.4.18(a) and Fig. 4.4.18(b). However, after 10 minutes
of the same growth conditions, no twins are observed on sample L4507.
L4505 (a) L4505 (b)
L4507
(c)
L4507
(d)
112

Instead, many dislocations are observed. These dislocations may result from the
coalescence of twinned depositions in sample L4505 since the side wall facets of
these twinned GaAs depositions are composed of micro-surfaces of (111)A and
(111)B. Therefore, dislocations may be easily formed during coalescence of two
twinned GaAs depositions. Higher-magnification TEM images of sample L4507,
as shown in Fig. 4.4.19, clearly exhibit a high density of dislocations between
two GaAs depositions.

Fig. 4.4.19 HRTEM image of L4507

Twin defects within these standalone GaAs nanosheets may result from the
growth conditions of high temperature nucleation since high arsine partial
pressure is required to form As-Si bonds before nucleation. Another growth step
was performed with a shorter nucleation period in order to reduce the possibility
of twin defects, and then regular growth conditions of GaAs nanosheets were
applied to achieve twin-free GaAs growth. Fig. 4.4.20 shows the results of
sample L4620:
L4507
113

Fig. 4.4.20 SEM image of L4620: GaAs nanosheet growth results on (111) silicon. (a) GaAs nanosheet
growth results of 1
st
pattern in Fig. 4.4.17. (b) GaAs nanosheet growth results of 2
nd
pattern in Fig. 4.4.17.
(c) Single GaAs nanosheet growth results on <11-2> oriented nano-stripes. (d) Single GaAs nanosheet
growth results on <1-10> oriented nano-stripes.

The growth conditions of sample L4620 are shown above. The high
temperature nucleation period was reduced to 45 seconds to reduce twin defects
within GaAs nucleations, followed by regular GaAs nanosheet growth conditions
Temp (C)
920
850
300
5
50 sccm
0.25 sccm
T (min)
25 sccm
L4620
440
5
15 sccm
0.75 30
1.6 sccm
(a) (b)
(c) (d)
114

for 30 minutes. Fig. 4.4.20(a) and Fig. 4.4.20(b) show the growth results of
sample L4620 on pattern #1 and pattern#2, respectively. Fig. 4.4.20(c) and Fig.
4.4.20(d) show GaAs growth on isolated nano-stipes oriented <11-2> and
<1-10>. The top surfaces of coalesced GaAs thin films in Fig. 4.4.20(a) and Fig.
4.4.20(b) are rough and seem to consist of multi-domain growth. By
investigating the growth results on isolated nano-stripes in Fig. 4.4.20(c) and Fig.
4.4.20(d), it seems that facets other than (110) planes occur on some GaAs
depositions which may result from multi-domains. Moreover, the size of GaAs
depositions seem to be fixed , and do not extend as the length of the nano-stripes
increases. The limited size of GaAs depositions may increase the twin
probability since the surface energy reduction effect resulting from twinning
would become significant. This may explain why most of the GaAs depositions
have hexagonal shapes. As twins are developed, the crystal orientations become
more complicated within coalesced GaAs thin films, and that may be the reason
that the top surfaces of as-grown coalesced GaAs thin films are rough.

4.4.4 Growth on (100) Silicon substrates
The (100) silicon substrate, unlike (111) silicon, is such that twin defects are
not energetically preferred on the growth plane. However, both have
multi-domain issues, and on the (100) plane, these issues are more difficult to
deal with.
Nano-stripes oriented in different directions were created on a (100) silicon
substrate to study the impact of orientation on quality of as-grown GaAs thin
films. Different growth temperatures were studied for GaAs growth conditions
on (100) silicon with 200 nm and 400 nm pitches. The following figure shows
the growth conditions for GaAs thin films on (100) silicon:
115

Before being loaded into the reactor, (100) silicon samples were thermally
oxidized in a furnace for 3 minutes to overcome the damage induced by the RIE
process. After thermal oxidization, the samples were loaded into the reactor and
annealed under ambient hydrogen at 945℃ to remove the native oxide, and
then ramped down to 440℃ for low temperature nucleation. After 3 minutes of
low temperature nucleation, the temperature was increased to the temperature of
GaAs thin film growth. Fig. 4.4.21 and Fig. 4.4.22 show the growth results of
sample L4674 with nano-stripe pitches of 400 nm and 200 nm respectively.
0 degree – 14 degrees 15 degrees – 29 degrees 30 degrees – 44 degrees

45 degrees – 59 degrees 60 degrees – 74 degrees 75 degrees – 89 degrees
Temp (C)
945
T
300
2
10 sccm
T (min)
440
50 sccm
30 3
30.27 sccm 30.27 sccm
116

Fig. 4.4.21 Growth results of sample L4674 with different orientation of nano-stripes. Growth
temperature: 690℃; nano-stripe pitch: 400 nm

0 degree – 14 degrees 15 degrees – 29 degrees 30 degrees – 44 degrees

45 degrees – 59 degrees 60 degrees – 74 degrees 75 degrees – 89 degrees

Fig. 4.4.22 Growth results as indicated by optical microscope images of sample L4674 with different
orientation of nano-stripes. Growth temperature: 690℃; nano-stripe pitch: 200 nm

117

There are 15 pads on each sample. The misalignment angle increases from
left to right, and from bottom to top. For example, in the sample which has 0
degree ~ 15 degrees misaligned nano-stripe patterns, the misalignment angles of
the 4 bottom pads are 0, 1, 2, 3 degrees, respectively, from left to right, and 4, 5,
6, 7 degrees for the 4 pads in the 2
nd
row from the bottom. The region outside of
these pads is the unmasked, or “skirt” region. The smoother the as-grown GaAs
top surface, the brighter the pad appears under the optical microscope. On both
samples, the as-grown GaAs thin films show smoother surfaces when the
misalignment angle is close to the <110> direction, and becomes rougher when
the misalignment angle approaches 45 degrees. The as-grown GaAs thin films
become brighter again when the misalignment angle gets closer to 90 degrees.
Cross-section TEM images of sample L4674 with 400 nm pitch are shown
below:

Fig. 4.4.23 TEM images of L4674: GaAs thin film grown from nano-stripes on (100) silicon substrate

In Fig. 4.4.23(a), many defects were formed within the coalesced GaAs thin
film, and when these defects reached the top surface, pits were formed as shown
in Fig. 4.4.23(b). These defects may originate from either multi-domain issues,
or stress between GaAs and silicon due to lattice-mismatch. Defects with
(a) (b)
GaAs
Silicon
GaAs
dislocation
118

V-shape pits usually result from threading dislocations, and therefore the pit
density of an as-grown GaAs thin film may reflect the density of threading
dislocations within it. In Fig. 4.4.21 and Fig. 4.4.22, the pit density of the
as-grown GaAs thin film changes with different orientations of the nano-stripes.
Such phenomena may imply that the orientation of the nano-stripes may help to
reduce or suppress the formation of threading dislocations. In the following, the
growth results of sample L4675, which was grown at lower growth temperature
of 640℃, are shown.

0 degree – 14 degrees 15 degrees – 29 degrees 30 degrees – 44 degrees

45 degrees – 59 degrees 60 degrees – 74 degrees 75 degrees – 89 degrees

Fig. 4.4.24 Optical micrographs of sample L4675 showing growth results with different orientation of
nano-stripes. Growth temperature: 640℃; nano-stripe pitch: 400 nm
119

0 degree – 14 degrees 15 degrees – 29 degrees 30 degrees – 44 degrees

45 degrees – 59 degrees 60 degrees – 74 degrees 75 degrees – 89 degrees

Fig. 4.4.25 Growth results of sample L4675 with different orientation of nano-stripes. Growth
temperature: 640℃; nano-stripe pitch: 200 nm

At lower growth temperature, the as-grown GaAs thin films show smoother
top surfaces when compared with those grown at higher temperature. As shown
in Fig. 4.4.24 and Fig. 4.4.25, the as-grown GaAs thin film’s top surface is
smooth when misalignment angles approach 0 or 90 degrees, and became rough
when the misalignment angle approaches 45 degrees. This trend is similar to
sample L4674. Among these samples, the lowest pit density occurs when the
misalignment angle is approximately 80 degrees. The optical microscope images
of these pads are shown below:
120

Fig. 4.4.26 (a) sample L4674, growth temperature 690℃, nano-stripe pitch 200 nm, (b) sample L4674,
growth temperature 690℃, nano-stripe pitch 400 nm, (c) sample L4675, growth temperature 640℃,
naon-stripe pitch 200 nm, (d) sample L4675, growth temperature 640℃, naon-stripe pitch 400 nm.

Optical microscope images of sample L4674 and sample L4675 with 200
nm and 400 nm pitch nano-stripes are shown in Fig. 4.4.26. As can be seen,
GaAs grown at higher temperatures has higher pit density than GaAs grown at
lower temperatures. Furthermore, GaAs grown from smaller pitch nano-stripes
has lower pit density. To investigate the crystal quality of as-grown GaAs thin
films on (100) silicon, cross-section TEM images of GaAs thin films grown from
45-degree and 80-degree nano-stripes were taken and shown in Fig. 4.4.27:

(c) (d)
(a) (b)
121

Fig. 4.4.27 TEM images of L4675. (a),(b) GaAs thin film from 45-degree nano-stripe pattern. (c),(d)
GaAs thin film grown from 80-degree nano-stripe pattern.

Fig. 4.4.27(a) and Fig. 4.4.27(b) show cross-section TEM images of GaAs
thin films grown from 45-degree misaligned nano-stripes, and Fig. 4.4.27(c) and
Fig. 4.4.27(d) shows cross-section TEM images of GaAs thin films grown from
80-degree misaligned nano-stripes. As observed under OM, the top surface of
as-grown GaAs thin films is smoother when grown with an 80-degree
misalignment angle, and rougher when grown from a 45-degree misalignment
angle. As shown in Fig. 4.4.23, defects cause the pits in Fig. 4.4.27(a). Surface
pits result from band-like defect structures. Not only is the smoothness of the top
surface between Fig. 4.4.27(a) and Fig. 4.4.27(c) greater, but the defect density is
quite a bit lower for the GaAs thin film grown from 80-degree misalignment
nano-stripes. Furthermore, there are no band-like defect structures in Fig.
4.4.27(c). Fig. 4.4.27(b) and Fig. 4.4.27(d) show closer TEM images at the
GaAs/silicon interface for 45-degree and 80-degree misaligned nano-stripes,
Silicon
GaAs
(a)
Silicon
GaAs
(b)
Silicon
GaAs
(c)
Silicon
GaAs
(d)
122

respectively. In Fig. 4.4.27(b), two band-like defects intersect and leave a
triangular shape defect. This triangular shape defect may have resulted from
self-annihilation of anti-phase domain, as reported in previous articles
12
. Similar
defects are not seen in Fig. 4.4.27(d), and only stacking faults are observed near
the GaAs/silicon interface for the GaAs thin film grown from 80-degree
misaligned nano-stripes. The self-annihilation of anti-phase domain was
established to explain how a single domain is formed on misoriented (100)
silicon substrates. Specifically, two sets of single atomic step structures are
aligned either on <011> or <0-11>. Though the silicon substrate used in this
experiment was not misoriented, the orientation of nano-stripes may help to
expose those single atomic-step structures only, thereby eliminating the
multi-domain issue.

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(10) Venables, J. A. Introduction to Surface and Thin Film Processes; Cambridge
University Press: Cambridge, 2000.
(11) Markov, I.; Stoyanov, S. Contemp. Phys. 1987, 28, 267–320.
(12) Kawabe, M.; Ueda, T. Jpn. J. Appl. Phys. 1987, 26, L944–L946.
(13) Tomioka, K.; Motohisa, J.; Hara, S.; Hiruma, K.; Fukui, T. Nano Lett. 2010, 10,
1639–1644.
(14) Chen, Y.; Washburn, J. Phys. Rev. Lett. 1996, 77, 4046–4049.
124

Chapter 5 Double Al
x
Ga
1-x
As passivation and wet oxidation
on GaAs nanostructure
5.1 Introduction
Due to a high density of surface states, the surface Fermi level of GaAs is usually
pinned at the middle of the bandgap. Studies have shown that the Fermi level can be
unpinned on certain surface orientations
1
. Since different facets have different atomic
configurations and surface chemistry, changing the surface chemical composition may
shift the dominant surface state energy and thus help to unpin the surface Fermi level.
approaches were proposed to passivate the GaAs surface: the use of chalcogenides
like S and Se
2
, or growing an Al
x
Ga
1-x
As layer on top of the GaAs substrate. However,
the sulphidation of the GaAs surface cannot be retained for a long time, so the GaAs
surface tends to become pinned at the middle of the bandgap as time passes.
In this chapter, I will focus on Al
x
Ga
1-x
As passivation because its lattice constant
is closer to that of GaAs, which could thus avoid strain accumulation at the
Al
x
Ga
1-x
As/GaAs interface and the degradation of crystal quality. Another advantage
of Al
x
Ga
1-x
As passivation is that the band alignment of Al
x
Ga
1-x
As/GaAs is a type I
alignment, which means that there is a barrier for both electrons and holes at
Al
x
Ga
1-x
As/GaAs interface thereby preventing them from occupying the surface states.
Al
x
Ga
1-x
As wet oxidation, which has been proved to efficiently transition intermediate
product amorphous As
2
O
3
to elemental As, was also used to help remove As from the
oxidized Al
x
Ga
1-x
As layer to avoid the surface pinning effect on that surface.

125

5.2 Wet oxidation of AlGaAs
The insulating, low interface state density and high density properties of SiO
2

made it an ideal robust native oxide material for silicon-based integrated circuits.
For decades researchers have been seeking an analogous native oxide on III-V
semiconductors such as GaAs, but these native oxides tend to be chemically and
mechanically unstable and non-uniform
3,4
. Wet oxidation of Al
x
Ga
1-x
As at low
temperatures was first demonstrated to form mechanically stable Al
2
O
3
at the
University of Illinois
5
. The wet oxidation of Al
x
Ga
1-x
As is performed with water
vapor and clean nitrogen gas at approximately 400℃. The oxidization rate of
Al
x
Ga
1-x
As was found to depend greatly on the Al concentration of Al
x
Ga
1-x
As
6,7
: the
higher the Al content, the faster the oxidization rate. Thus selective oxidation of
Al
x
Ga
1-x
As can be achieved by controlling the oxidation time. Because the generated
Al
2
O
3
has low refractive index, selective wet oxidation of Al
x
Ga
1-x
As was frequently
used in VCSELs to obtain efficient electrical and optical confinement
8–13
.

As
2
O
3
+ 3 H
2
= 2 As+ 3 H
2
O
(g)
−−−(1)
As
2
O
3
+ 6 H = 2 As+ 3 H
2
O
(g)
−−−(2)

As a passivation layer, Al
x
Ga
1-x
As serves as an isolation layer to protect the
GaAs surface from exposure to air in order to eliminate the formation of amorphous
As
2
O
3,
which is considered as a cause for the Fermi-level pinning effect. However, the
Fermi-level pinning effect also occurs on Al
x
Ga
1-x
As surfaces due to native oxidation
on the surface. During thermal wet oxidation of Al
x
Ga
1-x
As, As is converted to
amorphous As
2
O
3
. Then, as shown above in equations (1) and (2), amorphous As
2
O
3

can be converted to volatile As or AsH
3
for As removal from oxide layer (with the
help of hydrogen gas or elemental hydrogen). This process is important because (1)
126

the removal of As can help to unpin the Fermi level on the surface, and (2) residual As
between the oxidized Al
x
Ga
1-x
As/GaAs interface may cause serious leakage current
issues,
7
which could degrade the electrical properties of devices.
To better protect the GaAs surface, and to avoid the leakage problem between the
Al
x
Ga
1-x
As/GaAs interface, double Al
x
Ga
1-x
As layers were used to passivate GaAs
surface, as described in this chapter. The inner Al content of inner Al
x
Ga
1-x
As is
around 80% (x = 0.8) and that of the outer Al
x
Ga
1-x
As layer is around 90% (x = 0.9).
Because of different oxidization rates for different Al content, the outer Al
x
Ga
1-x
As
layer is selectively oxidized by controlling the oxidization period, and by leaving the
inner Al
x
Ga
1-x
As un-oxidized. The purpose of the inner Al
x
Ga
1-x
As layer is to protect
the GaAs surface, while the outer, oxidized Al
x
Ga
1-x
As layer is used to protect the
inner Al
x
Ga
1-x
As layer from the Fermi level pinning effect.

5.3 Growth conditions
A series of passivation experiments were performed on (100) GaAs, (111)B GaP
and (111) silicon for planar QW, nanosheet and nanowire structures, respectively. For
nanosheets and nanowires, a thin SiN
x
mask approximately 28 nm thick was
deposited for selective area growth. The growth was carried out in a vertical,
showerhead, low-pressure metal–organic chemical vapor deposition (MOCVD)
reactor. The growth pressure was 0.1 atm. The precursors for group III were
trimethylgallium (TMGa) and trimethyAlumium (TMAl), and the precursor for group
V was arsine (AsH
3
). Detailed V/III ratios and partial pressures for each experiment
will be disclosed in each section.
After MOCVD growth, doubly passivated samples were annealed in a furnace
with water vapor and nitrogen gas at 440℃ for 7 minutes to selectively oxidize the
outer Al
x
Ga
1-x
As (x = 0.9) layer.
127

5.4 Experimental Results
5.4.1 Single QW structure on (100) GaAs substrate
Three different single QW structures were fabricated on a (100) GaAs
substrate, as shown in Fig. 5.4.1:

Fig. 5.4.1 Schematic of a single QW structure on a (100) GaAs substrate. L4296: The QW is protected by
a single Al
x
Ga
1-x
As layer. L4297: The QW is protected by two Al
x
Ga
1-x
As layers. L4456: The QW is
protected by a thick Al
x
Ga
1-x
As layer.

The parameters of each layer of these structures are listed below:

Sample L4296 was passivated with a single Al
x
Ga
1-x
As layer in which the
Al content is approximately 80% and the layer thickness is 20 nm. Sample
L4297 is passivated with double Al
x
Ga
1-x
As layers. The Al content was 80%
for the inner layer and 90% for the outer layer; both layer thicknesses are 20 nm.
Sample L4456 is passivated with a single Al
x
Ga
1-x
As layer in which the Al
content is approximately 80% and the layer thickness is 40 nm.
Photoluminescence (PL) measurements of these three samples were performed
using micro-PL with a laser wavelength 532 nm. These results are shown
GaAs substrate
GaAs buffer layer
Al
x
Ga
1-x
As; x=0.3
Single QW
Al
x
Ga
1-x
As; x=0.8
L4296
GaAs substrate
GaAs buffer layer
Al
x
Ga
1-x
As; x=0.3
Single QW
Al
x
Ga
1-x
As; x=0.8
Al
x
Ga
1-x
As; x=0.9
L4297
GaAs substrate
GaAs buffer layer
Al
x
Ga
1-x
As; x=0.3
Single QW
Al
x
Ga
1-x
As; x=0.8
L4456
70nm : layer buffer GaAs
μm 1 thickness 0.3, x As; Ga Al
20nm thickness 0.9, x As; Ga Al
20nm thickness 0.8, x As; Ga Al
4nm thickness GaAs : QW
x 1 x
x 1 x
x 1 x
= =
= =
= =
=
−
−
−
128

below:

Fig. 5.4.2 PL results for L4296, L4297 and L4456. The numbers after the sample number denote
different measurement spots. (a) PL result for L4296 and L4297: comparison of the single and double
passivation effects. (b) PL result for L4296 and L4456: demonstration of the effect of the thickness of the
Al
x
Ga
1-x
As layer on passivation. (c) PL result for L4297 and L4456: comparison of the single and double
passivation effects with identical Al
x
Ga
1-x
As thicknesses. (d) PL result for L4297 before and after wet
oxidization.

Fig. 5.4.2(a) shows the PL spectra of sample L4296 and L4297. Both
samples had two peaks, one at 680 nm and another at 750 nm. The signal at 680
nm was from the Al
x
Ga
1-x
As (x=0.3) buffer layer beneath the single QW
structure, and the signal at 750 nm was from a single QW structure. Al
x
Ga
1-x
As
with x > 0.4 is considered an indirect bandgap material, and therefore incident
light would be mainly absorbed in the QW structure or beneath the Al
x
Ga
1-x
As
(x=0.3) buffer layer. In Fig. 5.4.2(a), more photons emitted from the QW
structure were captured in sample L4297, which implies that there are fewer
600 700 800
0
6000
12000
Photon counts
Wavelength (nm)
L4297_1
L4297_2
L4297_3
L4296_1
L4296_2
L4296_3
(a)
600 700 800
0
6000
Photon counts
Wavelength (nm)
L4296_1
L4296_2
L4296_3
L4456_1
L4456_2
L4456_3
(b)
600 700 800
0
6000
12000
Photon counts
Wavelength (nm)
L4297_1
L4297_2
L4297_3
L4456_1
L4456_2
L4456_3
(c)
600 700 800
0
6000
12000
Photon counts
Wavelength (nm)
L4297_1
L4297_2
L4297_3
L4297_oxidized_1
L4297_oxidized_2
L4297_oxidized_3
(d)
129

surface states within the QW structure with a double passivation layer. Since the
thickness of the passivation layer is different for samples L4296 and L4297, the
enhancement of PL intensity may not be merely due to the double layer
passivation effect. To study the influence of Al
x
Ga
1-x
As thickness on the
passivation effect, PL spectra of samples L4296 and L4456 were taken. These
are shown in Fig. 5.4.2(b). Samples L4296 and L4456 were both passivated by
a single Al
x
Ga
1-x
As (x=0.8) with different thickness. As can be seen, the thicker
Al
x
Ga
1-x
As layer did give higher PL intensity for the peak at 750 nm. However,
the enhancement was not as great as was the case for the double passivation layer.
A comparison between samples L4297 and L4456 is also shown in Fig.5.4.2(c).
As can be seen, for the same passivation layer thickness, the double passivation
layer (20 nm Al
0.8
Ga
0.2
As + 20 nm Al
0.9
Ga
0.1
As) has nearly double the photon
counts at the 750 nm peak when compared to the single passivation layer (40 nm
Al
0.8
Ga
0.2
As). One reason could be that the band alignment of
Al
0.8
Ga
0.2
As/Al
0.9
Ga
0.1
As is type I. Furthermore, similar to Al
0.8
Ga
0.2
As/GaAs,
the outer higher Al content Al
x
Ga
1-x
As layer introduces another energy barrier
for both electrons and holes to prevent them from reaching the surface.
In Fig. 5.4.2(d), PL spectra for non-oxidized and oxidized L4297 is shown.
Since the wet oxidation rate highly depends on the Al content, only the outer
Al
0.9
Ga
0.8
As was selectively oxidized. The PL signal at 750 nm is slightly
enhanced with wet oxidation, and the uniformity of PL intensity at different spots
was enhanced as well.

5.4.2 GaAs nanosheet structures on (111)B GaP substrates
In this section, different Al
x
Ga
1-x
As structures were applied to GaAs a
nanosheet structure for a study of passivation effects. Efforts to grow QW
130

structures on nanosheet structures were performed, but the results were not good.
Therefore, instead of measuring PL from the QW structure, in this section the PL
signal from the nanosheet itself was measured to estimate the passivation of
different Al
x
Ga
1-x
As structures. To avoid the background signal from the
substrate, GaAs nanosheets were grown on a (111)B GaP substrate, which is
indirect band gap material. Detailed growth conditions of GaAs nanosheets on
(111)B GaP are listed in Chapter 4. Three different structures of nanosheet were
grown, as shown in Fig. 5.4.3.

Fig. 5.4.3 Schematic view of the cross-sectional structure of GaAs nanosheets with AlGaAs passivation.
L4482 is a bare GaAs nanosheet without an AlGaAs layer. L4489 is a GaAs nanosheet with a 40 nm
thick Al
0.8
Ga
0.2
As passivation layer. L4486 is a GaAs nanosheet with passivation layers of 20 nm
Al
0.8
Ga
0.2
As and 20 nm Al
0.9
Ga
0.1
As.

The thickness of the GaAs nanosheet was approximately 250 nm for these
three samples. Sample L4482 is a pure GaAs nanosheet without any
passivation layer; sample L4489 is a GaAs nanosheet with a single 40 nm
Al
0.8
Ga
0.2
As layer, and sample L4486 is a GaAs nanosheet with a double
passivation layer (20 nm Al
0.8
Ga
0.2
As inner layer and 20 nm Al
0.9
Ga
0.1
As outer
layer). PL spectra of these three samples are shown in Fig. 5.4.4:
GaAs
L4486
Al
0.9
Ga
0.1
As
20nm
Al
0.8
Ga
0.2
As
20nm
GaAs
L4489
40nm
GaAs
L4482
250nm Al
0.8
Ga
0.2
As
131

700 800 900
0
5000
10000
Wavelength (nm)
L4482_5E-2_1
L4482_5E-2_2
L4482_5E-2_3
L4482_5E-2_4
L4482_5E-2_5
L4482_5E-2_6
L4482_5E-2_7
1
2
3
4
5 6 7
GaAs
250nm
(a)
1
2
3
4 5 6
GaAs
L4489
40nm
(b)
Al 0.8 Ga 0.2 As
700 800 900
0
10000
20000
30000
Wavelength (nm)
L4489_5E-2_1
L4489_5E-2_2
L4489_5E-2_3
L4489_5E-2_4
L4489_5E-2_5
L4489_5E-2_6
132

Fig. 5.4.4 PL results for the GaAs nanosheet on a (111)B GaP substrate. The numbers after the sample
number denote different measurement spots. (a) PL results of sample L4482, which is merely a bare
GaAs nanosheet. (b) PL results of sample L4489: A GaAs nanosheet with 40 nm Al
x
Ga
1-x
As. (c) PL
results of sample L4486: A GaAs nanosheet with double passivation layers. (d) PL results of sample
L4486 after wet oxidization.

PL spectra for these three samples were measured from nanosheet arrays
and single nanosheets. The OM images of measured spots on nanosheet arrays
700 800 900
0
30000
60000
Wavelength (nm)
L4486_Nonoxidized_5E-2_1
L4486_Nonoxidized_5E-2_2
L4486_Nonoxidized_5E-2_3
L4486_Nonoxidized_5E-2_4
L4486_Nonoxidized_5E-2_5
L4486_Nonoxidized_5E-2_6
1
2
3
4 5 6
GaAs
L4486
Al 0.9 Ga 0.1 As
20nm
Al 0.8 Ga 0.2 As
20nm
(c)
1
2
3
4 5 6
GaAs
L4486
Al 0.9 Ga 0.1 As
20nm
Al 0.8 Ga 0.2 As
20nm
700 800 900
0
30000
60000
Wavelength (nm)
L4486_Oxidized_5E-2_1
L4486_Oxidized_5E-2_2
L4486_Oxidized_5E-2_3
L4486_Oxidized_5E-2_4
L4486_Oxidized_5E-2_5
L4486_Oxidized_5E-2_6
(d)
133

and single nanosheets are shown in Fig. 5.4.4(a) through Fig. 5.4.4(d). Fig.
5.4.4(a) shows the PL spectrum from a bare GaAs nanosheet. Within the figure,
one peak has a wider bandwidth around 750 nm, and the other peak has a
narrower bandwidth around 860 nm. The 860 nm signal peak originates from the
GaAs nanosheet and the 750 nm signal peak is the background signal, since the
same PL peak position was observed on the masked region. As can be seen in Fig.
5.4.4(a) and Fig. 5.4.4(b), PL intensity from the nanosheet array region was
boosted about 7x with a 40 nm Al
0.8
Ga
0.2
As layer. Photon counts increased
from 2,500 to 15,000 on average. However, PL signal enhancement was not
observed on single nanosheets.
The photon counts from single nanosheets was lower than that from the
nanosheet array in sample L4489. The reason may be the volume of nanosheets
within the laser spot. The diameter of the laser spot is approximately 1 μm,
which covers only 3-4 nanosheets in the array region. Considing the inclined
surface edge of a single nanosheet, the total volume of a single nanosheet is just
1/4 of the irradiated nanosheet in the array region. This value matches well with
the difference in PL intensity between the nanosheet array region and a single
nanosheet, as shown in Fig. 5.4.4(b). In Fig. 5.4.4(c), the PL spectrum of sample
L4486 is shown. As before, the PL intensity from the nanosheet array region was
greater than from a single nanosheet. However, the uniformity was not as good
as that one of spot in the nanosheet array region, which had photon counts
around 90,000, whereas the other two were close to 30,000. In Fig. 5.4.4(b)
and Fig. 5.4.4(c), further enhancement in the PL intensity was achieved on GaAs
nanosheets using a double passivation layer. Both PL intensities from the
nanosheet array region and from single nanosheets were higher in L4486 than
those in L4489. The trend is the same as the experimental results on planar QW
134

structures with the same Al
x
Ga
1-x
As thickness. Thus, double layers provide
better passivation.
Fig. 5.4.4(d) shows the PL intensity of sample L4486 after wet oxidation.
PL intensity was roughly the same before and after wet oxidation. However,
the uniformity was improved after wet oxidation.

5.4.3 GaAs nanowire structure on (111) Silicon substrates
Similar experiments were performed on GaAs nanowire structures as well.
To eliminate the background signal, GaAs nanowires were grown on a (111)
silicon substrate. Detailed growth conditions of the nanowire structure are
listed in Chapter 2. In Fig. 5.4.5, the schematic of the GaAs nanowire structure
with different configuration of Al
x
Ga
1-x
As layers is shown:

Fig. 5.4.5 Schematic view of the cross-sectional structure of a GaAs nanowire. L4601 is a bare GaAs
nanowire. L4604 is a GaAs nanowire with a 10 nm thick Al
0.8
Ga
0.2
As passivation layer. L4605 is a GaAs
nanowire with a 20 nm thick Al
0.8
Ga
0.2
As passivation layer. L4606 is a GaAs nanowire with 20 nm thick
Al
0.8
Ga
0.2
As and another 20 nm thick Al
0.9
Ga
0.1
As double passivation layers.

Four samples were studied: L4601 (bare GaAs nanowire), L4604 (GaAs
nanowire with 10 nm thick Al
0.8
Ga
0.2
As), L4605 (GaAs nanowire with 20 nm
thick Al
0.8
Ga
0.2
As), and L4606 (GaAs nanowire with 20 nm thick Al
0.8
Ga
0.2
As
and another 20 nm thick Al
0.9
Ga
0.1
As double passivation layers). PL
measurement results for these 4 samples are shown in Fig.5.4.6.
GaAs
L4606
Al
0.9
Ga
0.1
As
10nm
Al 0.8 Ga 0.2 As
10nm
GaAs
L4601
GaAs
L4605
20nm
Al
0.8
Ga
0.2
As
GaAs
L4604
10nm
Al
0.8
Ga
0.2
As
135

Fig. 5.4.6 PL results for GaAs nanowires on a (111) silicon substrate. The numbers after the sample
number denote different measurement spots. (a) PL results of sample L4601: a bare GaAs nanowire
structure. (b) PL results of sample L4604: a GaAs nanowire with a 10 nm Al
0.8
Ga
0.2
As layer. (c) PL
results of sample L4605: a GaAs nanowire with a 20 nm Al
0.8
Ga
0.2
As layer. (d) PL results of sample
L4606: a GaAs nanowire with double passivation layers.

Without an Al
x
Ga
1-x
As layer, sample L4601 showed the lowest photon
counts. The maximum photon count is approximately 600, as can be seen in
Fig. 5.4.6(a). After passivating the bare GaAs nanowire with a thin, 10 nm thick
Al
0.8
Ga
0.2
As layer, as shown in Fig.5.4.6(b), the number of emitted photons
increased. The maximum photon count was approximately 35,000, and the
minimum photon count is approximately 15,000. This is approximately 25
times greater then the bare GaAs nanowire. PL results for sample L4605, which
GaAs
L4601
800 900
0
300
600
L4601 (Photon counts)
Wavelength (nm)
L4601-1
L4601-2
L4601-3
(a)
GaAs
L4604
10nm
Al 0.8 Ga 0.2 As
800 900
0
5000
10000
15000
20000
25000
30000
35000
L4604 (Photon counts)
Wavelength (nm)
L4604-1
L4604-2
L4604-3
(b)
800 900
0
5000
10000
15000
20000
25000
30000
35000
L4605 (Photon counts)
Wavelength (nm)
L4605-1
L4605-2
L4605-3
GaAs
L4605
20nm
Al 0.8 Ga 0.2 As
(c)
800 900
0
5000
10000
15000
20000
25000
30000
35000
L4606 (Photon counts)
Wavelength (nm)
L4606-1
L4606-2
L4606-3 GaAs
L4606
Al 0.9 Ga 0.1 As
10nm
Al 0.8 Ga 0.2 As
10nm
(d)
136

has a thicker Al
x
Ga
1-x
As layer, are shown in Fig. 5.4.6(c). The maximum photon
count is near 35,000, and the minimum photon count is near 17,000, which is
similar to the thinner Al
x
Ga
1-x
As layer case. However, the average photon count
is higher in sample L4605 and in sample L4604, which means that the thicker
Al
x
Ga
1-x
As layer did result in better passivation than the thinner one. This is
the same as what we observed in the planar case. Fig. 5.4.6(d) shows the PL
results of the double passivation layer sample, L4606. The maximum,
minimum and average photon counts are similar to those of L4605. Unlike the
case of nanosheets and planar structure, it seems that double passivation layers
did not provide any improvement to PL emission for the nanowire case.
To estimate the effect of wet oxidization of the AlGaAs layer, PL
measurements were also performed on wet-oxidized L4606. There results are
shown in Fig. 5.4.7:

Fig. 5.4.7 PL results of sample L4606: double passivation layer structure after wet oxidization

The maximum photon count after wet oxidization is lowered to
approximately 25,000. However, the minimum photon count is increased to
800 900
0
5000
10000
15000
20000
25000
30000
35000
L4606 Oxidized (Photon counts)
Wavelength (nm)
L4606_oxidized_1
L4606_oxidized_2
L4606_oxidized_3
137

20,000, which implies that the uniformity improved after wet oxidization. A
similar trend is observed for the planar and nanosheet cases as well.

5.5 Dicussion
In this chapter, the passivation of an Al
x
Ga
1-x
As layer on planar and
nanostructures was examined. The PL intensity was measured as an indication of the
passivation results. The passivation effect is not only related to Al
x
Ga
1-x
As thickness
but also the passivation structure. Thicker Al
x
Ga
1-x
As layers provide better
passivation effects than thinner ones. However, the improvement is not obvious.
With the same Al
x
Ga
1-x
As thickness, double Al
x
Ga
1-x
As layers significantly
outperform single Al
x
Ga
1-x
As layer in PL intensity. It is believed that the double
Al
x
Ga
1-x
As layer structure introduces an additional energy barrier between the two
Al
x
Ga
1-x
As layers, thereby preventing carriers from occupying surface states.
After wet oxidization, on both planar and nano-structured substrates, the
uniformity of PL intensity improves. No obvious improvement was observed.
Instead, the PL intensity decreased after wet oxidization in the nanosheet and
nanowire cases. One postulation is that Al
x
Ga
1-x
As wet oxidization and arsenic
volatilization occurs at the same time. As
2
O
3
, the oxidation product formed during
oxidization, is then volatilized through the permeable oxide layer in the form of As or
AsH
3
. This implies that, at the oxidization front, there could be some residual As
2
O
3

which is not converted to As or AsH
3
to escape from Al
x
Ga
1-x
As layer. This residual
As
2
O
3
could re-pin the Fermi level at the middle of the bandgap. The reduced PL
intensity after wet oxidization may result from the residual As
2
O
3
.

138

5.6 Reference
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139

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140

Chapter 6 Future work
A newly invented nanostructure, the nanosheet, is proposed in previous chapters
discussing its growth mechanism, crystal-quality and optical properties. Compared to
nanowires, nanosheets have better crystal quality and exhibit better a passivation
effect with a double Al
x
Ga
1-x
As structure; these superiorities make nanosheets more
suitable than nanowires for many device applications. Therefore, as next step, it may
be worthy to improve device performance using a nanosheet structure in the following
application fields:

6.1 Tri-gate transistor
The Intel Ivy Bridge is the first CPU made by Si tri-gate
1–4
transistors. The
three-dimensional gate design shown in Fig.6.1 drives transistors at lower voltage
with lower leakage current and faster ON-OFF switching. Silicon fin structures are
first created by etching process and then gate oxide and gate material are deposited.
Due to three-dimensional structure of surrounding gates, silicon fins can be easily and
quickly depleted at lower voltage.
GaAs nanosheet
5
structure is similar to fin structure thus similar gate design can
be easily applied to nanosheets to form III-V three-dimensional transistor: gate oxide
and gate material can be deposited onto {110} facets of a nanosheet. The advantage of
using GaAs nanosheet as fin structure is: 1
st
: the as-grown {110} facets are
atomically-flat, thus it can avoid carrier scattering from rough surface due to etching
process. 2
nd
: the mobility of electron is higher in GaAs than that in Si therefore GaAs
tri-gates can provide better electrical performance over Si tri-gates.
141

(a)
(b)
Fig.6.1 (a) Schematic of silicon three-dimensional gate design. (b) Cross-section view of
three-dimensional gate

Fig.6.2 Cross-section view GaAs nanosheet (a) on silicon substrate and (b) coated with AlGaAs shell. (c)
AlGaAs shell oxidized after wet oxidization to form gate oxide. (d) Cross-section view of tri-gate
transistor made of GaAs nanosheet grown on silicon.

Fig.6.2 shows the procedure of III-V tri-gate transistor made of GaAs nanosheet
grown on silicon substrate. First GaAs nanosheet was grown on silicon substrate as
shown in Fig.6.2(a) and then AlGaAs was grown as the outer shell as shown in
SiNx SiNx
Silicon
GaAs nanosheet
(a)
SiNx SiNx
Silicon
GaAs nanosheet
Al x Ga 1-x As
(b)
SiNx SiNx
Silicon
GaAs nanosheet
Al 2 O 3
(c)
SiNx SiNx
Silicon
GaAs nanosheet
Gate material
(d)
142

Fig.6.2(b). In Fig.6.2(c) the AlGaAs shell was then wet oxidized in the furnace to
form Al
2
O
3
which can be served as gate oxide
6
material for GaAs nanosheet. Then
metal was deposited as shown in Fig.6.2.(d) to form GaAs tri-gate transistor. The
growth condition of AlGaAs shell and wet oxidization condition are already
developed in chapter 5, the main challenge of fabricating GaAs nanosheet tri-gate
transistor would be how to grow defect-free GaAs nanosheet on silicon substrate. In
chapter 4, many efforts were put to achieve defect-free GaAs nanosheet on
lattice-mismatched substrate, but there is no success; however as tri-gate transistor,
the thickness of fin structure is merely 10nm~20nm; with such thin nano-stripe
opening, the stress energy between GaAs and silicon can be greatly reduced and may
help to achieve defect-free GaAs nanosheet.

6.2 Nanostructured solar cell
The nanowire
7,8
is the commonly used structure in the nanostructured solar cell.
However, the reported photon-electron conversion efficiency is quite low and has a
huge gap between theoretic values; the inherent twin density and surface states are
considered main reasons for it. Twin defects within the nanowire could result in
energy barriers, which impedes carrier transportation; also from the defects, the
side-wall of the nanowire consists of micro (111)A and (111)B facets and make it
difficult to passivate as well. The reported highest efficiency of the nanostructured
solar cell is about 13% which is made of InP nanowires
9
. Unlike GaAs, InP doesn’t
have the serious surface state issue, thus passivation is not that important in the InP
nanowire solar cell. However, 13% is still much lower than its theoretical value. Since
the surface state is not a problem in InP, the possible issue of that could be twin
defects. The inherent twin-free feature of the nanosheet may be the solution for that:
without twin defects, carrier scattering effect is reduced
10–13
; moreover, the side-wall
143

facets of the nanosheet is atomically-flat, which can be perfectly passivated, and that
is the reason why the nanosheet structure shows better a passivation effect in chapter
5.

Fig.6.3 (a) Schematic design of nanosheet solar cell. (b) Simulated light absorption of GaAs nanosheet
solar cell.

Fig.6.3(a) shows the schematic design of nanosheet solar cell; as nanowire
structure, nanosheet solar cell is a 3D structure with larger surface area which can
help to increase light absorption by multiple reflections between nanosheets.
According to simulation result, maximum light absorption of nanosheet solar cell falls
at pitch equals 400nm (a = 400nm) with nanosheet thickness about 120nm (d =
120nm). The absorption spectrum of GaAs nanosheet (a = 400nm, d = 120nm, height
= 3um) is shown in Fig.6.3(b); the light absorption is about 85% however due to
asymmetric structure of GaAs nanosheet, light absorption rates vary with different
direction.

6.3 Thin film tandem solar cell
Nanosheets can not only serve as a building block for solar cells, the coalescence
of nanosheets can also form a continuous thin film with reduced defect density as
a
d
(a)
0.4 0.5 0.6 0.7 0.8 0.9
0
0.2
0.4
0.6
0.8
1
wavelength (μm)
Absorptance
a = 400 nm d/a = 0.3 h = 3μm

x polarized
y polarized
Average
(b)
144

shown in chapter 4 for thin film tandem solar cell purposes. The inherent twin-free
feature of the nanosheet results in atomically-flat facets on its side-walls; therefore it
avoids crystal defects within the coalescence of the thin films since each nanosheet is
within same twin domain. The small foot-print of the nanosheet also helps to reduce
strain energy between lattice-mismatched material to further increase the as-grown
thin film crystal quality. The as-grown III-V thin film can be used to integrate with Si
or other substrates to form thin-film tandem solar cells. Since surface states and twin
defects are not as serious as those in nanostructures, thin-film tandem solar cells may
result in better photon-electron conversion efficiency than nanostructured solar cells.
In chapter 4, GaAs thin film was grown on silicon substrates and defect density
of the as-grown thin film is greatly reduced with the help of nano-stripes. Not only
GaAs, other III-V materials maybe grown on lattice-mismatched substrates with same
method. For example, for two layer tandem solar cell, top cell with 1.7eV is required
when silicon is used as bottom cell. Possible candidate materials with 1.7eV are:
AlGaAs, GaAsP, InGaP and AlInAs Among these 4 materials, GaAsP has the smallest
lattice-mismatch constant to silicon substrate, and since the P content is about 22%
which makes it more like GaAs than GaP; therefore GaAsP may be potential
candidate material to form two layer tandem solar cell on silicon substrate using
nano-stripes pattern. Traditionally, graded buffer layer
14,15
is used to grown materials
on lattice-mismatched substrate to reduce strain energy; GaAsP with low defect
density may be achieved in the same way as shown in chapter 4. As shown in Fig.6.4:
during nanosheet growth, both As and P sources are supplied to form GaAsP
nanosheet structure, and then by intersecting nano-stripes or change growth condition
to enhance lateral growth rate as shown in Fig.6.4(b) to coalesce GaAsP nanosheet
into GaAsP thin film as shown in Fig.6.4(c). Though defects still exist within the
as-grown GaAs thin film in chapter 4; the smaller lattice-mismatch constant can help
145

to reduce strain energy between GaAsP/Si; also compared to As, P
16,17
is more easily
to passivate Si surface in order to get sufficient nucleation site at the first step.

Fig.6.4 (a) GaAsP nanosheet grown on silicon substrate. (b) Intersect nano-stripe patterns or change
growth condition to enhance lateral growth rate. (c) The as-grown GaAsP thin film on nano-stripe
pattern.

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Asset Metadata

Creator Chi, Chun-Yung (author)

Core Title Gallium arsenide nanosheets: study of stacking-fault-free nano-structure and its applications on semiconductor devices

Contributor Electronically uploaded by the author (provenance)

School Andrew and Erna Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 02/12/2015

Defense Date 12/02/2014

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag GaAs,MOCVD,nanosheet,OAI-PMH Harvest

Format application/pdf (imt)

Language English

Advisor Dapkus, Paul Daniel (committee chair)

Creator Email chunyung@gmail.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c3-533039

Unique identifier UC11297546

Identifier etd-ChiChunYun-3185.pdf (filename),usctheses-c3-533039 (legacy record id)

Legacy Identifier etd-ChiChunYun-3185.pdf

Dmrecord 533039

Document Type Dissertation

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Rights Chi, Chun-Yung

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

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Abstract (if available)

Abstract GaAs has superior optical and electrical performance over silicon