University of Southern California Dissertations and Theses

Silicon-based wideband & mm-wave power amplifier architectures and implementations

(USC Thesis Other)

Silicon-based wideband & mm-wave power amplifier architectures and implementations

PDF

Download

Open document

Flip pages

Download a page range

Download transcript

Copy asset link

Request this asset

Transcript (if available)

Content SILICON-BASED WIDEBAND & mm-WAVE
POWER AMPLIFIER ARCHITECTURES AND
IMPLEMENTATIONS
by
Jonathan D. Roderick
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulllment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2014
Copyright 2014 Jonathan D. Roderick
Dedication
To my Dad,
John Perry Roderick III.
ii
Acknowledgments
First, I would like to thank my parents, John and Linda Roderick, for their uncon-
ditional love and support. My success is a direct result of their sacrices and the
opportunities they provided for me.
I would like to thank my committee members Professor Hossein Hashemi, Pro-
fessor Martin Gundersen, and Professor Stephan Haas for their invaluable contribu-
tions towards my academic progress. Their knowledge, wisdom and insight has only
reenforced the University of Southern California's reputation as a premier research
institution.
During my time at USC, I have had the privilege to work closely under Professor
Hashemi and Professor John Choma Jr. Their dedication towards education has
resulted in my third degree from the University of Southern California. It is with
great sadness that Professor Choma passed away before the defense of my thesis.
He was a great mentor, educator, and friend during his service as my adviser for
my B.S. and M.S. degrees. He will truly be missed.
In addition I would like to thank all my group members at USC: Professor Harish
Krishnaswamy, Masashi Yamagata, Ken Newton, Dr. Ankush Goel, Prof. Ta-Shun
iii
Chu, Dr. Zahra Safarian, Prof. Firooz A
atouni, Alireza Imani, Tim Mercer, Kunal
Datta, Run Chen, Sushil Subramanian, Chenliang Du, Hooman Abediasl, Fatemeh
Rezaeifar. It was a privilege to work with such a talented group of individuals.
While credit has to be given to Prof. Hashemi for assembling such talented group,
everyone in the group has assisted my academic growth and maturity in one way
or another. I would not be able to complete this thesis without them.
Lastly, and most importantly, I thank my wife, Dr. Erin Roderick, for every-
thing. Without her full support none of this would have been possible.
iv
Table of Contents
Dedication ii
Acknowledgments iii
List Of Tables vii
List Of Figures viii
Abstract xv
Chapter 1: Introduction 1
1.1 Power Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 Linear Power Ampliers . . . . . . . . . . . . . . . . . . . . 6
1.1.1.1 Instantaneous Wideband Power Ampliers . . . . . 9
1.1.2 Switching Power Ampliers . . . . . . . . . . . . . . . . . . 14
1.1.3 Harmonic Manipulating Power Ampliers . . . . . . . . . . 16
1.1.4 Power Amplier Technologies . . . . . . . . . . . . . . . . . 18
1.1.5 Impedance Transformation & Power Combining . . . . . . . 20
1.2 Transmitters Architectures . . . . . . . . . . . . . . . . . . . . . . . 26
1.2.1 Transmitter Eciency Enhancement Techniques . . . . . . . 29
1.2.1.1 Doherty Amplier . . . . . . . . . . . . . . . . . . 30
1.2.1.2 Digital Polar Transmitter (DPT) . . . . . . . . . . 31
1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 2: Ultra-Wideband Power Ampliers 36
2.1 Tapered Distributed Amplication . . . . . . . . . . . . . . . . . . 38
2.1.1 Monolithic Tapered Transmission Line . . . . . . . . . . . . 44
2.2 Wideband Impedance Transformation . . . . . . . . . . . . . . . . . 44
2.2.1 Ruthro Transmission Line Transformer . . . . . . . . . . . 47
2.2.2 Guanella Transmission Line Transformer . . . . . . . . . . . 50
2.2.3 Silicon Implementation of TLTs . . . . . . . . . . . . . . . . 54
2.2.4 A 1:16 Silicon Wideband Impedance Transformer . . . . . . 59
2.3 Wideband Power Combining . . . . . . . . . . . . . . . . . . . . . . 62
v
2.4 A 20 dBm UWB Silicon Power Amplier . . . . . . . . . . . . . . . 65
2.4.1 Chip Results . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.5 An UWB Digital Pulse Generating Transmitter . . . . . . . . . . . 76
2.5.1 Chip Results . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 3: A Q-Band Digital Polar Transmitter (DPT) 86
3.1 HBT Switchmode Power Ampliers . . . . . . . . . . . . . . . . . . 87
3.1.1 Finite Inductance Class-E PA . . . . . . . . . . . . . . . . . 91
3.1.2 Millimeter-Wave Finite-Inductance Class-E PA . . . . . . . 95
3.1.3 Operating Beyond BV
CEO
. . . . . . . . . . . . . . . . . . . 106
3.2 Stacked Nonlinear Switching Class-E PA . . . . . . . . . . . . . . . 110
3.2.1 Multi-Input Multi-Stacked Switching PAs . . . . . . . . . . 112
3.3 A 23 dBm Stacked Q-Band Class-E PA . . . . . . . . . . . . . . . . 120
3.3.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . 124
3.3.2 Measurement Results Discussion . . . . . . . . . . . . . . . . 128
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 4: Future Work 131
4.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.2 Future Work: Watt Level Silicon PAs . . . . . . . . . . . . . . . . . 132
4.2.1 Watt-Level UWB PA . . . . . . . . . . . . . . . . . . . . . . 132
4.2.1.1 A 30 dBm UWB Silicon Power Amplier . . . . . . 133
4.2.1.2 Simulation Results . . . . . . . . . . . . . . . . . . 135
4.2.2 Watt-Level mm-Wave Switchmode PA . . . . . . . . . . . . 135
4.2.2.1 A 36 dBm Stacked Q-Band Class-E PA . . . . . . 135
4.2.2.2 Simulation Results . . . . . . . . . . . . . . . . . . 150
Chapter 5: Conclusions 152
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
References 154
Appendix A
Derivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
A.1 Transmission Line Transformer Theory . . . . . . . . . . . . . . . . 162
A.2 Finite Inductance Class-E Theory . . . . . . . . . . . . . . . . . . . 167
vi
List Of Tables
1.1 Properties of linear PAs . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Classication of nite inductance class-E ampliers. . . . . . . . . . 15
1.3 A summary of the physical properties of common PA technologies[59]. 20
2.1 A 20 dBm UWB PA Performance Summary . . . . . . . . . . . . . 77
3.1 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.1 A 30 dBm UWB PA Simulated Performance Summary . . . . . . . 137
4.2 Simulated performance summary of a watt-level Q-band class-E PA 151
vii
List Of Figures
1.1 A schematic diagram of a basic linear PA with output waveform
details for each linear class. . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Load lines for each linear amplier class. . . . . . . . . . . . . . . . 8
1.3 A schematic diagram of a CMOS distributed amplier. . . . . . . . 10
1.4 Class-A distributed amplier PAE versus technology unity gain fre-
quency for dierent bandwidth requirements. . . . . . . . . . . . . . 14
1.5 A schematic diagram and waveforms of a class-E and class-D
1
PA 15
1.6 The voltage and current waveforms for the four dierent categories
of nite inductance class-E PAs. . . . . . . . . . . . . . . . . . . . . 16
1.7 A schematic, waveforms, and load-line of a class-F amplier. . . . . 17
1.8 The output breakdown voltage vs. unity gain frequency (f
t
) of com-
mon PA technologies. Courtesy of Aitken-09[41]. . . . . . . . . . . . 19
1.9 A survey of the best performing output power and eciency handset
power ampliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.10 Ways to circumvent limited breakdown voltage: impedance trans-
forming and power combining. . . . . . . . . . . . . . . . . . . . . . 22
1.11 L-match impedance transformation:(a) Schematic of a PA with an
L-match passive network; (b) The L-match tuned circuit equivalent. 22
1.12 L-match performance versus transformation ratio and bandwidth for
a 2GHz center frequency. . . . . . . . . . . . . . . . . . . . . . . . . 25
viii
1.13 The peak-to-average ratios for common communication standards. . 27
1.14 The eciency vs peak-to-average power for linear PAs. . . . . . . . 28
1.15 A block diagram of a Doherty power amplier. . . . . . . . . . . . . 31
1.16 A block diagram of a digital polar transmitter . . . . . . . . . . . . 32
1.17 The theoretical drain eciency comparison between a Class-A, Class-
B, Doherty Amplier, and a 5-bit DPT . . . . . . . . . . . . . . . . 33
2.1 Spectrum allocation for UWB imaging applications and the one way
attenuation through concrete. . . . . . . . . . . . . . . . . . . . . . 37
2.2 Conceptual block diagram of transmitted UWB pulse through (a)
linear amplication and (b) generation. . . . . . . . . . . . . . . . . 38
2.3 A tapered distributed amplier: (a) schematic and (b) an illustration
of tapered micro-strip line implementation. . . . . . . . . . . . . . . 39
2.4 2-Stage Transmission Line Transformers (TLT): (a) Ruthro and (b)
Guanella implementation. . . . . . . . . . . . . . . . . . . . . . . . 45
2.5 The frequency performance of ideal Ruthro TLT with various trans-
mission line lengths (1, 2, 4, and 8 mm). . . . . . . . . . . . . . . . 49
2.6 The frequency performance of ideal Guanella TLT with various trans-
mission line lengths (1, 2, 4, and 8 mm). . . . . . . . . . . . . . . . 54
2.7 Available layout of coupled lines for a monolithic process: (a) copla-
nar strip lines and (b) broadside coupled strip lines. . . . . . . . . . 56
2.8 Design examples of coupled lines in IBM 8RF-LM (a) coplanar strip
lines and (b) broadside coupled strip lines. . . . . . . . . . . . . . . 56
2.9 The frequency performance of an = 2 Guanella versusK
e
for various
lengths of transmission line . . . . . . . . . . . . . . . . . . . . . . . 57
2.10 The simulated frequency performance of a n = 2 Guanella imple-
mented in IBM8HP for various lengths of transmission line. The
TLT input impedance is designed to be 6.25
. . . . . . . . . . . . 58
ix
2.11 A 1:16 Transmission Line Transformers (TLT): (a) Schematic and
(b) Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.12 A 1:16 Transmission Line Transformers (TLT): (a) 3D layout and
(b) metal stack details. . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.13 The measured results of a 1:16 Transmission Line Transformers. The
designed input impedance transformed from a 50
load is 3.125
62
2.14 A schematic of two 1:4 TLTs being used as a power combiner. . . . 63
2.15 Schematic of a UWB CMOS power amplier . . . . . . . . . . . . . 66
2.16 The load line for a 0.13m NMOS . . . . . . . . . . . . . . . . . . . 67
2.17 The eciency degradation due to nite output impedance and knee
voltage of a single 0.13m device. . . . . . . . . . . . . . . . . . . . 68
2.18 The eciency degradation as a function of load resistance and device
size of 0.13m device. . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.19 The eciency degradation as a function of load resistance and device
size for a cascode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.20 The output power and PAE versus biasing and device size for a 7-
section TDPA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.21 Details of the CPS designs used in the output tapered line. . . . . . 72
2.22 Schematic of a UWB CMOS power amplier . . . . . . . . . . . . . 73
2.23 Measured output power versus input power . . . . . . . . . . . . . . 74
2.24 Measured linear (-1 dB compression point) and saturated output
power vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.25 Time domain measurement with an UWB mono-cycle pulse genera-
tor. The output waveforms includes a 20 dB attenuator. . . . . . . 76
2.26 A schematic block diagram of a 1-bit UWB pulse generator . . . . . 77
2.27 A 5-stage example of the 1-bit UWB pulse generator . . . . . . . . 79
x
2.28 A 5-stage example of the 1-bit UWB pulse generator with minimum
pulse width settings. . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.29 A 5-stage example of the 1-bit UWB pulse generator with 2X mini-
mum pulse width settings. . . . . . . . . . . . . . . . . . . . . . . . 82
2.30 The delay performance of each the delay line element versus process
corner for a 0.13m CMOS technology. . . . . . . . . . . . . . . . . 83
2.31 The measurement of the 1-bit UWB pulse generator: (a) time do-
main measurement and (b) the frequency domain measurement of the
420ps pulses; (c) time domain measurement and (d) the frequency
domain measurement of the 150ps pulses. . . . . . . . . . . . . . . . 85
3.1 A schematic of a class-E amplier and the associated waveforms. . . 87
3.2 8HPr
on
characterization and the maximum allowable r
o
n for a 90%
ecient class-E PA vs Supply voltage. . . . . . . . . . . . . . . . . 89
3.3 A loadline vs. HBT I-V characteristics and the HBT input power
loss mechanism associated with entering saturation. . . . . . . . . . 90
3.4 A 3-D plot of an HBT I-V characteristics with a superimposed class-
E loadline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.5 A schematic of a nite inductance class-E PA. . . . . . . . . . . . . 92
3.6 Output power and
XL
versus X for a 45 GHz PA. . . . . . . . . . 93
3.7 Output power versus X and RL for a nite-inductance class-E 45
GHz PA with a 1.5 V supply. . . . . . . . . . . . . . . . . . . . . . 94
3.8 The vaues of C
1
and L
1
as a function of X. . . . . . . . . . . . . . . 96
3.9 The required device size for a 130nm SiGe HBT as a function of C
1
and I
switch
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.10 The required device size as a function of C
1
and I
switch
. . . . . . . . 99
3.11 The dynamics associated with the eective output capacitance of an
HBT during class-E operation. . . . . . . . . . . . . . . . . . . . . . 100
xi
3.12 Equivalent HBT input parasitics and the impact on class-E conduc-
tion angle for C

C
b
. . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.13 Impact of conduction angle variation on a nite-inductance class-E
amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.14 Output Power and PAE versus R
L
for dierent emitter lengths, E
L
. 105
3.15 IBM8HP current Density vs collector-emitter voltage and base ter-
mination. Courtesy of IBM. . . . . . . . . . . . . . . . . . . . . . . 107
3.16 Waveforms of a 45 GHz Class-E PA with a 1.5 V supply and 12.5

load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.17 TheBV
CER
versusV
be
performance of a high f
t
0.130m HBT. The
loadlines of Class-E PA with a supply voltage of 1.5 V and 3 V are
superimposed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.18 A schematic of a stacked class-E amplier with a mid mode resonator
and the associated simulated waveforms. . . . . . . . . . . . . . . . 113
3.19 A unique method of switching a stacked (n=2) multi-port class-E
power amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.20 Simulated results of a proposed n=2 and n=4 stacked multi-port
class-E power amplier architecture. . . . . . . . . . . . . . . . . . 116
3.21 The theoretical output power and drain eciency vs. the number
of stacked devices and the comparison of stacked drain eciency
compared to a single device with impedance transformation for com-
parable output powers. . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.22 The maximum mid-node voltage to maximum collector voltage ratio
vs. phase-shift for a n = 2 PA. . . . . . . . . . . . . . . . . . . . . . 119
3.23 A schematic diagram and associated waveforms of a 23 dBm Q-band
Class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.24 A microphotograph and block diagram of the fabricated a 23 dBm
Q-band Class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . . 122
xii
3.25 A mm-wave parasitic modeling of device connection parasitics using
Momentum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.26 A mm-wave modeling Metal-Insulator-Metal (MIM) capacitors using
Mentor's IE3D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.27 Measured P
out
,
c
, and PAE vs. P
in
for a 23 dBm Q-band Class-E
PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.28 Measured P
sat
,
c
, and PAE vs. frequency . . . . . . . . . . . . . . 126
3.29 S
11
and S
21
for the Q-band class-E PA when biased class-A. . . . . 126
3.30 Measured P
out
, and
c
, vs. phase-shift . . . . . . . . . . . . . . . . 127
3.31 Measured P
sat
,
c
, and PAE vs. frequency . . . . . . . . . . . . . . 130
4.1 A block diagram of a 30dBm UWB PA . . . . . . . . . . . . . . . . 134
4.2 Simulated output power versus frequency for linear (@ -1dB) and
saturated operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.3 The simulated output power versus input power for 4 and 5 GHz. . 136
4.4 Block diagram and microphotograph of a watt-level silicon class-E PA.138
4.5 The complete schematic diagram for a single channel used in a watt-
level silicon class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.6 The schematic diagram and simulated waveforms of the quasi-dierential
class-E PA core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.7 The simulated performance of resistive biasing with avalanche break-
down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.8 The schematic and simulated performance of the avalanche compen-
sation circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.9 The schematic and simulated performance of the avalanche compen-
sation circuitry for a two device stacked PA core. . . . . . . . . . . 144
xiii
4.10 The schematic diagram, 3-D EM simulation view, and circuit simu-
lation results of a class-E congured transformer. . . . . . . . . . . 146
4.11 The schematic diagram of Driver D1 (Class-E) with the simulated
collector voltage and current waveforms. . . . . . . . . . . . . . . . 148
4.12 The schematic diagram of Driver D2 (Class-E) with the simulated
collector voltage and current waveforms. . . . . . . . . . . . . . . . 148
4.13 The schematic diagram of Driver D3 (Class-E) with the simulated
collector voltage and current waveforms. . . . . . . . . . . . . . . . 149
4.14 The simulated S-parameter measurements of a Q-band watt-level
class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.15 Simualted output power, collector eciency, and PAE versus input
power of a Q-band watt-level class-E PA. . . . . . . . . . . . . . . . 151
A.1 The schematic of coupled transmission lines. . . . . . . . . . . . . . 162
A.2 A schematic of a nite inductance class-E PA. . . . . . . . . . . . . 168
A.3 Finite inductance class-E (a) output power and (b) required load
phase shift versus X. . . . . . . . . . . . . . . . . . . . . . . . . . . 173
A.4 Finite inductance class-E required (a) L
1
value and (b) C
1
value
versus X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
A.5 Finite inductance class-E required load (a) inductance and (b) ca-
pacitance versus X. . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
xiv
Abstract
Multi-functional communication and imaging applications have necessitated the
integration of many complex systems onto a single chip. Traditionally, multi-chip
modules or systems-in-a-package approaches have been utilized to perform com-
plex functions for state of the art architectures. Nanometer silicon processes have
the ability to integrate f
max
>100 GHz RF devices with CMOS digital devices to
achieve completely integrated system-on-a-chip solutions, where the performance
rivals traditional III-V solutions. Due to the requirements of advanced wireless sys-
tems, a silicon implementation is no longer solely determined by economics. The
ability to completely integrate an RF or millimeter-wave integrated circuit with a
mixed-signal application specic integrated circuit onto a single die, using nanome-
ter silicon processes, allows the emergence of novel and elegant solutions. This
thesis presents silicon-based Ultra WideBand (UWB) and millimeter-wave (mm-
wave) Power Amplier (PA) architectures and implementations for state of the art
wireless systems.
Silicon-based power ampliers rely on impedance transformation networks and
power combining to overcome the limited allowed supply voltage, which is governed
xv
by the modest breakdown voltages associated with high f
max
silicon devices. To
operate within breakdown limits, an impedance transformation is used to deliver
the desired power to the antenna. Traditionally, impedance transformations are
implemented with passives as L-, Tee-, or Pi-matching topologies. However, these
techniques are typically narrow band solutions.
UWB True-Time-Delay radar architectures require the transmission of pico-
second pulses for high resolution imaging. The amplication of UWB pulses requires
a power amplier that has the ability to amplify a time-limited pulse with little
amplitude and phase distortion. Wideband amplication has been traditionally
accomplished with a Distributed Amplier (DA) topology. A DA yields
at gain
and group delay over very wide bandwidths, yet DAs nd little utility as power
ampliers due to the loss associated with the reverse-wave termination found at
the output.
The rst part of this thesis presents two UWB prototype power ampliers suit-
able for UWB imaging. Both proposed topologies used Transmission-Line Trans-
formers (TLT) to circumvent the narrowband nature of typical impedance trans-
formation and power combining networks. In addition, each PA core is realized
with a distributed amplication approach which eliminates the reverse-wave termi-
nation using a tapered quasi-distributed line. The result is the realization of cost
xvi
eective integrated class-A ultra wideband CMOS power ampliers, which are com-
patible with existing true-time-delay systems for low GHz high-precision imaging
applications.
Alternatively, an UWB pulse can be generated and subsequently transmitted,
as opposed to amplied, using a class-A PA. A UWB pulse generator, with class-D
output drivers, has been proposed for short range imaging applications. This ap-
plication specic solution features 12 dBm of maximum output power with tunable
center frequency and bandwidth, which covers the UWB spectrum. The UWB
transmitter has zero static current consumption, which is ideal for a completely
integrated UWB radar.
The last part of this thesis proposes highly-ecient stacked nonlinear mm-wave
(Q-band) power ampliers tailored for use in a Digital Polar Transmitter (DPT).
The integration ability of silicon allows for the incorporation of linearization tech-
niques with nonlinear highly ecient power ampliers onto a single silicon die.
Thereby nding new utility for switching ampliers which have historically been
limited to applications with a constant envelope modulation scheme.
A multiple input drive stacked device class-E power amplier operating at 45
GHz is presented. Topology techniques that extend the device operation beyond
BV
CEO
and increase the usable supply voltage are proposed. The multiple input
drive switches the devices in a manner that equally distributes the output voltage
swing across each device, thus allowing the usable supply voltage to be increased by
xvii
a factor equal to the number of series stacked devices. The result is unprecedented
output power and eciency performance for integrated silicon power ampliers at
45 GHz.
xviii
Chapter 1
Introduction
Multi-functionality has necessitated the integration of many complex systems onto
a single chip. Traditionally, Multi-Chip Modules (MCM) or Systems-in-a-Package
(SiP) have been utilized to perform complex functions for state-of-the-art systems.
The ability of nanometer CMOS to integrated a System-on-a-Chip (SoC) with
billions of digital devices and RF devices with a unity-gain frequency (f
t
) and
maximum oscillation frequency (f
max
) of greater than 100 GHz gives silicon an
unmatched advantage for realizing unique solutions to improve the next generation
of wireless systems.
Cost is no longer the sole motivating factor for silicon implementation. For in-
stance, complex modulation schemes in high performance communication systems
yield high spectrum eciency at the cost of signicantly increasing the transceiver
hardware complexity, due to the high Peak-to-Average Power Ratios (PAPR). The
1
ability to integrate the entire modulation scheme and predistortion with a high ef-
ciency switching Power Amplier (PA) core allows designers to rethink the tradi-
tional prejudice against implementing power ampliers in silicon due to the limited
breakdown voltage.
This dissertation is organized as follows: In Chapter 1, an introduction into sil-
icon PA design and performance enhancement methods will be presented. Circuit
and system methods that increase overall PA eciency will be the focus. Tradi-
tionally in discrete or multiple module implementations, PA design and linearity
enhancement are carried out independently. However, the advanced integration
ability and high frequency performance of nanometer silicon processes allows the
realization of a complete transmitter on a single die. This unmatched integration
advantage allows the implementation of novel transmitter architectures targeted
towards complex communication standards and challenges the negative prejudice
of silicon PA utilization. Chapter 2 will present the theory, design and imple-
mentation of silicon Ultra-WideBand (UWB) power ampliers with giga-Hertz of
instantaneous bandwidth
1
. Power ampliers with the ability to transmit extreme
bandwidths can nd utility in anything from transmitting pico-second pulses
2
to
multi-carrier fast frequency hoping communication systems. Chapter 3 will shift
focus to the implementation of silicon PAs at millimeter-wave frequencies. The
1
This is opposed to frequency agile narrowband systems which can be tuned to cover a large
spectral bandwidth
2
Required in UWB imaging applications
2
theory, design and implementation of highly ecient Q-band switching power am-
pliers suitable for use in Digital Polar Transmitters (DPT) will be presented. A
summary of all research regarding UWB systems implemented in silicon, as well as
a few comments regarding future work will be presented in Chapter 4.
1.1 Power Ampliers
The sole purpose of a PA is to amplify a desired signal to a sucient level so it
is properly received. Whether it be through wireless or wire-line transmission, the
most important PA metric is eciency. There are many classes of power ampliers
and all have been developed with the sole intent of improving the eciency be-
yond what has been previously achieved. A schematic of a typical power amplier
is shown in Figure 1.1. The eciency of a power amplier is measured by how
eciently it converts DC power to AC power. The DC power, P
DC
, of the PA is
dened as
P
DC
=V
DD
I
DD
; (1.1)
whereV
DD
andI
DD
are the DC supply voltage and DC supply current, respectively.
The output power, P
out
, for a narrowband signal is dened as
3
P
out
=
V
2
o
2R
L
; (1.2)
where V
o
is the output voltage and R
L
is the load impedance. The eciency, , of
the device is
=
P
out
P
DC
: (1.3)
In Figure 1.1, the device eciency is often called the drain eciency,
D
, when the
active device is a Field Eect Transistor (FET). Likewise, the eciency is called
the collector eciency,
C
, when the PA is implemented in a bipolar technology.
Power ampliers are divided into various classes based on the device conduction
angle,
C
, and the associated device voltage and current waveforms. The opera-
tional dierences between each PA class results in a performance tradeo; typically
increased eciency at the expense of amplier linearity. Therefore, all PA classes
are not created equal, so there must be a performance metric which captures more
than the PA DC-to-RF eciency. As will be shown, some PA classes have lower
power gain, G
P
, which leads to a larger required input power, P
in
. A PA with a
lower power gain requires more output power and gain from the pre-ampliers (or
drivers) that precede it in the transmitter chain. This additional hardware may
4
Figure 1.1: A schematic diagram of a basic linear PA with output waveform details
for each linear class.
impact the overall transmitter eciency. To ensure that the eciency comparison
between each PA class is fair, an additional PA metric that measures the relative
eciency with respect to PA power gain was created. The Power Added Eciency
(PAE) is dened as
PAE =
P
out
P
in
P
DC
=

1
1
G
P

: (1.4)
In the limit that the PA has innite gain, the PA and PAE are equal. Ignoring
linearity, PAE has become the industry standard for comparing PA performance
because of the dependance on power gain.
5
1.1.1 Linear Power Ampliers
Historically, linear power ampliers (class-A, class-AB, class-B, class-C) are a class
of ampliers that encompass the vast majority of deployed power ampliers for
the wireless integrated circuit market. The term \linear" is used here to describe
a power amplier that is biased as a current source
3
and the output power is
unsaturated and proportional to the input power. Abiding by industry convention,
a \linear" power amplier does not suggest that the output is harmonic free or a
perfect high power replica of the input. A \linear" power amplier usually refers
to the PA class and is typically used to amplify non-constant envelope signals
and/or to ensure FCC spectral mask compliance by limiting spectral regrowth and
Adjacent Channel Power Ratio (ACPR)[90].
A schematic of a typical linear power amplier and the associated output wave-
forms for each class are shown in Figure 1.1. While the load impedance may dier,
the conduction angle,
c
, is the fundamental way to distinguish between each of
the linear power amplier classes. The conduction angle is dened as the angu-
lar period the device is conducting with respect to the input drive frequency. As
shown in Figure 1.1, the conduction angle is controlled by the gate bias. A class-A
amplier has conduction angle equal to 2, so the device is biased to ensure it is
always conducting: the input signal is always greater than the threshold voltage,
V
th
, of the device. A 2 conduction angle results in current and voltage overlap
3
It can also be thought of as a transconductor.
6
Table 1.1: Properties of linear PAs
Class Category Conduction Angle (
c
) Max. Eciency ()
A 2 50 %
AB <
c
< 2 50 % < < 78 %
B 78 %
C 0 <
c
< 78 % < < 100 %
through the device, as shown in Figure 1.1. The maximum achievable eciency of
a lossless class-A amplier is 50 % [27],[67]. This limited theoretical eciency has
spawned all other power amplier classes in an eort to save power.
Class-B and class-C amplier are reduced conduction angle linear power ampli-
ers. As shown in Figure 1.1, reduced conduction angle ampliers have less device
output voltage and current overlap. These ampliers sacrice amplier linearity
and gain for eciency by reducing the device conduction angle, which in turn re-
duces the current-voltage overlap through the lossy device. A load-line illustration
for each linear class amplier is shown in Figure 1.2. Neglecting any harmonic
termination requirements, the load-lines illustrate the low-frequency optimum load
resistance, R
opt
, required in to order realize proper operation in each class. The
value of the optimum resistance decreases as the slope of the load line increases, so
a class-C amplier would require a smaller load than a class-A amplier. To rst or-
der, the reduction in load resistance leads to a decrease in gain. Therefore, a higher
input power is needed to maintain an equivalent output power. A class-C amplier
requires much larger peak output current, I
D;max
to produce the equivalent output
7
Figure 1.2: Load lines for each linear amplier class.
8
power as a class-A. Here lies one basic trade-o between achieving higher eciency
through reducing the device conduction angle. A class-AB amplier is an amplier
that has a reduced conduction angle that lies somewhere between the conduction
angle of a class-A and class-B amplier. In theory, a class-C amplier can achieve
100 % eciency with a conduction angle of zero. The result would be zero output
power. Thus, class-C ampliers with very low conduction angles nd little utility
due to the low achievable output power levels. The basic linear PA properties are
summarized in Table 1.1.
1.1.1.1 Instantaneous Wideband Power Ampliers
An instantaneous wideband amplier demonstrates
at gain and group delay across
an ultra-wide bandwidth. Such ampliers are required when the waveform has a
large instantaneous bandwidth; an example is a time limited pico-second pulse used
in UWB imaging. A distributed amplier is the classic example for achieving large
bandwidths with frequency limited devices[36]. An example of a distributed ampli-
er is shown in Figure 1.3. The amplier trades delay for bandwidth enhancement.
The power gain of a class-A distributed amplier is [89]
G
P;DA
=
n
2
g
2
m
Z
oi
Z
oo
4
; (1.5)
9
Figure 1.3: A schematic diagram of a CMOS distributed amplier.
where n is the number of identical ampliers, g
m
is the transconductance of each
amplier, andZ
oi
andZ
oo
are the characteristic impedance of the input and output
line, respectively. As shown in the gure, the device input and output parasitic
capacitors are absorbed into the input and output quasi-distributed transmission
lines. The characteristic impedance of a quasi-distributed line is
Z
o
=
s
L
C
: (1.6)
For the purposes of this discussion, each device in the distributed amplier is mod-
eled as shown in Figure 1.3. In all likelihood, the design would absorb the input
parasitic capacitance of the device,C
gs
, into the capacitance required for the trans-
mission line, C. The same can be done for the output parasitic capacitance of
10
the device,C
ds
. Therefore, the quasi-distributed line cuto frequency
4
,f
c
, sets the
bandwidth of the distributed amplier and is dened as [53]
f
c
=
1

p
LC
=
1

q
LC
gs
: (1.7)
One signicant drawback to implementing a distributed amplier as a power
amplier is the loss associated with the reverse termination required in the output
line, as shown in Figure 1.3. This termination results in half of the output power
being lost, which reduces the maximum achievable eciency by half. Thus a lossless
class-A distributed amplier would have a maximum theoretical eciency of 25 %.
The implementation of a distributed power amplier is warranted when a large
instantaneous bandwidth is a high priority. The denition of power added eciency,
as dened in Equation 1.4, fails to give any insight on how a required bandwidth
performance aects amplier eciency. Assuming class-A operation, the PAE of a
distributed amplier is calculated to be
PAE =
P
out
P
in
P
DC
=

classA
2

1
1
G
P;DA
!
: (1.8)
Substituting the gain of a distributed amplier into Equation 1.8 yields
4
The cuto frequency of a quasi-distributed lines is dened as the frequency where the input
impedance of the line becomes purely imaginary, thus preventing the delivery of any real power.
11
PAE =

classA
2

1
4
n
2
g
2
m
Z
oi
Z
oo
!
: (1.9)
Next, combining Equations 1.6 and 1.7, the characteristic impedance of a quasi-
distributed transmission line can be rewritten as
Z
o
=
s
1
f
c
C
gs
: (1.10)
Typically, the load of a PA is transformed from a 50
standard to an optimal load
impedance based on the output power requirement. Therefore, the input impedance
and output impedance of a distributed PA are not necessary equal. The ratio of
output impedance to input impedance can be dened as Z
oi
= K
Zo
Z
oo
. Using
Equations 1.7, 1.9, and 1.10, the PAE of a class-A distributed amplier can be
calculated as
PAE =

classA
2
0
@
1

4
2
K
Zo
n
2
!
f
c
f
t
!
2
1
A
; (1.11)
where f
t
is the technology unity gain frequency and is dened as
12
f
t
=
g
m
C
gs
: (1.12)
Equation 1.11 gives insight on the eciency implications of including bandwidth
as one of the distributed amplier design criteria. Figure 1.4 shows the calculated
PAE versus device unity gain frequency for dierent DPA bandwidth requirements
(5, 10, & 25 GHz). The graphs allows a designer to properly choose a technology
with an adequate f
t
given the PA bandwidth requirements. Equation 1.11 has
a very subtle, but important, dependance on the number of stages, n, and the
output impedance, which is a function of K
Zo
. Both directly aect the gain of
the distributed power amplier and therefor have a signicant impact on the PAE.
Two cases are plotted in Figure 1.4: Case 1 is a 7-stage distributed amplier with
K
Zo
=5, while case 2 is a 10-stage distributed amplier withK
Zo
=3. Case 1 requires
a technology with an f
t
greater than 50 GHz to achieve an eciency within 1
% of the theoretical maximum for a lossless class-A distributed amplier with a
bandwidth requirement of 5 GHz. Case 2 only requires an f
t
of around 25 GHz
due to the superior power gain performance. Therefore, the presented analysis can
be used to investigate the PAE performance of a distributed power amplier as
a function of number of stages, output impedance, bandwidth requirement, and
technology unity gain frequency.
13
Figure 1.4: Class-A distributed amplier PAE versus technology unity gain fre-
quency for dierent bandwidth requirements.
1.1.2 Switching Power Ampliers
Switching power ampliers (class-D, class-E) are the only power amplier topologies
with 100% theoretical eciency, [37], [46]. In these nonlinear ampliers, the
transistor acts like a switch and the passives are designed specically to prevent
voltage and current overlap through the transistor. The schematic and switching
waveforms of a class-E and class-D
1
are shown in Figure 1.5. The distinction
between a class-D and class-D
1
is voltage and current waveform role reversal. A
class-D amplier would have a square wave output voltage and a sinusoidal current.
The classication of class-E ampliers can be expanded based on designing L
1
to resonate at a specic frequency with C
1
. A design parameter,X, can be dened
as the ratio of the resonate frequency, !
L
1
C
1
,of L
1
and C
1
to the operating center
frequency of the power amplier, !
RF
,
14
Figure 1.5: A schematic diagram and waveforms of a class-E and class-D
1
PA
Table 1.2: Classication of nite inductance class-E ampliers.
Class-E PA Categories Inductance Resonant Frequency Ratio (X)
Classical 0
Sub-Harmonic 0 < x < 1
Parallel-Circuit 1.412
Even-Harmonic 2n (n=1,2,3...)
X =
!
L
1
C
1
!
RF
; where !
L
1
C
1
=
1
p
L
1
C
1
: (1.13)
Table 1.2 denes the subcategory nomenclature used throughout the literature
for class-E ampliers. A \classical" class-E amplier has an X = 0 and the in-
ductor, L
1
, is implemented with a RF choke. The other class-E ampliers uses a
nite inductance determined by the design parameter X and are known as nite
15
Figure 1.6: The voltage and current waveforms for the four dierent categories of
nite inductance class-E PAs.
inductance class-E ampliers. The associated voltage and waveforms of each are
shown in Figure 1.6. All classications of class-E ampliers listed in Table 1.2
have a 100% theoretical eciency. However, the nite passive Q and device loss
associated with a particular technology may result in a wide discrepancy between
the achievable eciency from each of the mentioned class-E amplier categories.
Unfortunately due to the nonlinear behavior, switching power ampliers have been
historically limited to communication standards with constant envelope signals.
1.1.3 Harmonic Manipulating Power Ampliers
Harmonic manipulating power ampliers (Class-F, Class-EF, Class-J) increase the
achievable eciency by designing the amplier load to have a specic impedance
(real and/or imaginary) at a specic frequency or set of frequencies [25]. Usually,
the load impedance is designed to have a certain eect (e.g. open, shorts, etc. ) at
specic frequencies; usually at the harmonics of the fundamental frequency. The
16
Figure 1.7: A schematic, waveforms, and load-line of a class-F amplier.
result is an increase in PA eciency by minimizing the voltage and current overlap
though the lossy device. Harmonic manipulation is accomplished either by using
a unique amplier class (Class-F) or by using a hybrid class approach (Class-EF)
[47].
An example of a harmonic manipulating PA is a class-F amplier (Figure 1.7)
[37]. This particular class-F uses a quarter wavelength line for harmonic frequency
termination. The device is biased as a class-B amplier, then the output voltage
is shaped using harmonic termination to resemble a square wave
5
. The shaping of
the square-wave drain voltage is accomplished by loading the device with an open
circuit load termination for all odd harmonics above the fundamental frequency
and a short circuit termination for all even harmonics using the quarter wavelength
line.
Class-F ampliers can also be realized using individual lters tuned at each
specic harmonic as opposed to using the quarter wavelength line. A perfect square
5
The device output current is shaped to resemble a square in an inverse class-F.
17
wave drain voltage which results in 100 % drain eciency is only achieve in the
limit of innite harmonic terminations. A major drawback to the class-F amplier
is the number of terminations required to achieve a high eciency [64], which can
result in diminishing return, due to nite-Q passive elements, as more and more
harmonic terminations are added[47].
The benets of harmonic tuning are not limited to the output of the PA. Proper
termination at the input can also be an eective means to increase amplier e-
ciency [37]. In addition, implementing harmonic tuning in other amplier classes
to create a hybrid amplier class results in one more degree of design freedom
when trying to maximize the eciency of a power amplier realized with non-ideal
components [27].
1.1.4 Power Amplier Technologies
The maximum achievable eciency of a power amplier is directly dependent on
the implemented technology. The wireless PA integrated circuit market has been
historically dominated by III-V semiconductor technologies due to the superior
breakdown voltage and frequency performance [66]. The breakdown performance
versus unity-gain frequency (f
t
) of commonly used technologies used to fabricated
power ampliers for mobile devices is shown in Figure 1.8.
In addition to breakdown voltage and unity-gain frequency, there are other key
properties of semiconductor technologies that play a pivotal role in determining the
18
Figure 1.8: The output breakdown voltage vs. unity gain frequency (f
t
) of common
PA technologies. Courtesy of Aitken-09[41].
overall performance of a power amplier. A table summarizing key performance
and physical properties of common PA technologies is found in Table 1.3. While
advanced silicon technologies lack the band gap voltage of III-V devices, the in-
creased thermal conductivity and the ability to incorporate high density digital
logic with high frequency devices gives nanometer silicon devices the advantage in
applications (or architectures) that require large scale integration. It is the high
integration advantage of silicon that transmitter designs can leverage to produce
unprecedented eciency performance.
In order for a silicon power amplier to be anything more than an academic
exercise and system integration challenge, then it must at least meet the perfor-
mance of linear millimeter wave III-V based power ampliers. A survey of the
best performing power ampliers was conducted and used to generate the graphs
in Figure 1.9. As shown, the breakdown voltage of III-V materials from Table 1.3
19
Table 1.3: A summary of the physical properties of common PA technologies[59].
Property Si SiC InP(InGaAs) GaAs GaN
Band-gap 1.11 3.02 1.35 1.43 3.39
Sat. Electron Velocity (x10
7
cm/sec) 1 2.7 2.5 2 2.7
Electron Mobility(cm
2
/Vs) @300K 1500 700 15000 (InGaAs) 8500 900
Breakdown Field (x10
5
V/cm) 3 25 7.5 6.5 33
Thermal Conductivity (W/cmK) 1.5 4.9 0.68 0.54 1.3
Available Metals Cu, AL Au Au Au Au
Integration High Low Low Low Low
has resulted in higher achievable output power and eciency at mm-waves. While
deep submicron silicon devices have f
t
sucient for mm-wave design, the higher
breakdown voltage of III-V materials allows for larger supply voltages and thus
eliminates the impedance transformation, and the loss associated with it, required
to achieve watt-level output power from a limited supply. To close the eciency
gap between silicon and III-V material, highly-ecient nonlinear switching mm-
wave silicon power ampliers must utilize the integration advantage of silicon to be
competitive with higher breakdown materials.
1.1.5 Impedance Transformation & Power Combining
The fundamental challenge in power amplier IC design arises when fabricating the
PA with a limited breakdown voltage. As shown in Figure 1.8, for RF and mm-
wave applications, a III-V device may have 4-to-6 times the breakdown voltage
of a frequency equivalent (equal f
t
) silicon process. For instance, the theoretical
maximum output power that can be delivered to a 50 ohm load from an ideal
20
Figure 1.9: A survey of the best performing output power and eciency handset
power ampliers.
class-A is 13.5 dBm: assuming a 1.5 V DC supply and ideal 50 % theoretical drain
eciency. However, the PA eciency is heavily in
uenced by factors such as device
knee-voltage, V
knee
, on-chip passive loss, and the loss associated with the silicon
substrate [27],[37],[47]. Therefore, the delivered power of a silicon PA with 1.5 V
DC supply and 50
is far less than 13.5dBm. The generation of power from a
breakdown limited device is accomplished through a variety of circuit techniques
that generally fall into one of two categories: impedance transformation and/or
power combining. Figure 1.10 highlights both methods and gives an example of
each method.
An impedance transformation is used to generate higher power levels while
operating within the device breakdown limits. Traditionally narrowband impedance
transformation can be carried out on- and/or o-chip using the traditional L-, Tee-
, or Pi-matching topologies [62],[53]. An impedance transformation using low-loss
21
Figure 1.10: Ways to circumvent limited breakdown voltage: impedance transform-
ing and power combining.
(a) (b)
Figure 1.11: L-match impedance transformation:(a) Schematic of a PA with an
L-match passive network; (b) The L-match tuned circuit equivalent.
22
passive components allows the device to generate a large power to an optimum load
resistance, R
opt
, while not violating any breakdown voltage limits. An example of
a PA with a low-pass L-match circuit is shown in Figure 1.11(a). The impedance
transformation ratio is measured by the transformation quality factor, Q and is
dened as
Q =
v
u
u
t

R
L
R
opt
!
1: (1.14)
Any passive loss has a direct aect on the output power and eciency of a PA
and must be considered when designing an L-match. The loss associated with an
inductor and capacitor can be dened by the passive quality factor. The inductor
quality factor, Q
L
, and capacitor quality factor Q
C
are dened as
Q
L
=
!L
R
; (1.15)
and
Q
C
=!CR: (1.16)
23
Assuming the passive network loss is dominated by the inductor, an L-match equiv-
alent circuit is substituted in the analysis [22],[51]. The loss associated with the
passives, R
LQ
, is related to the load impedance, R
L
, by
R
LQ
=

R
L
1 +Q
2
!
Q
Q
L
!
: (1.17)
Figure 1.11(b) shows the tuned equivalent circuit network, which is only valid
at the tuned frequency where
X
L
=X
C
Q
2
1 +Q
2
: (1.18)
Using the equivalent circuit shown in Figure1.11(b), the output power can be cal-
culated to be
P
out
=
(V
DD
V
knee
)
2
2R
opt

Q
L
Q
L
+Q
!
2
: (1.19)
Equation 1.19 highlights the achievable output power for a given impedance
transformation ratio and inductor Q. Figure 1.12 plots the achievable output power
vs transformation ratio assuming V
DD
= 1:5V and V
knee
= 0:4V . The gure also
24
Figure 1.12: L-match performance versus transformation ratio and bandwidth for
a 2GHz center frequency.
plots the eciency of the impedance transformation passive network versus the
impedance transformation ratio. The nite inductor quality factor drastically limits
the eciency of large transformation ratios. Thus the maximum achievable output
power of a power amplier is dictated by the technology breakdown voltage and
the passive quality factor. The impedance transformation ratio also determines the
minus three decibel bandwidth, BW
3dB
, of the system. The two are related by
BW
3dB
=
!
o
Q
: (1.20)
Figure 1.12 also shows output power versus achievable bandwidth
6
on the top axis
of the graph. As shown, an L-match circuit is typically a narrowband solution due
to limited bandwidth for large impedance transformation ratios.
6
Assuming a 2 GHz center frequency.
25
Figure 1.10 also illustrates power combining multiple devices as an ecient
way to generate larger output power from an integrated circuit with a limited
breakdown voltage. PA designs have implemented transmission line based power
combiners (e.g. Wilkinson) [87],[75] and transformer based designs which combine
both impedance transformation and power combining into one structure [7],[17].
As shown in Figure 1.10, a coupled transformer can provide impedance transfor-
mation and power combining by manipulating the turn ratio and coupling multiple
ampliers.
1.2 Transmitters Architectures
The increased demand for more integrated functionality and higher data rates into
current wireless devices has resulted in complex multi-carrier modulation schemes
and standards that push high data rates through limited slices of available spectrum
[52]. A summary of peak-to-average specications for common communication
standards is shown in Figure 1.13. Typically, a communication standard with a
high Peak-to-Average Power Ratio (PAPR) requires a linear amplier due to the
large dynamic output power requirement.
The cost associated with using a spectrally ecient high data rate communica-
tion system is transmitter eciency. The transmitted peak-to-average power ratio
requirements for advanced modulation schemes has resulted in the deployment of
linear (Class-A, Class-AB) gallium arsenide (GaAS) and gallium nitride (GaN)
26
Figure 1.13: The peak-to-average ratios for common communication standards.
power ampliers in the vast majority of high performance commercial and mili-
tary wireless handsets. In addition to the limited theoretical maximum eciency,
another disadvantage of a linear power amplier is that the maximum eciency is
only achieved at the peak output power, also know as Peak Envelope Power (PEP).
Therefore, communication standards with large PAPR specications will operate
the PA in the most ecient PEP operating region for only a fraction of the time.
Figure 1.14 shows the continuous wave (CW) theoretical average power eciency
versus PAPR for ideal linear PAs [10]. From gures 1.13 and 1.14, an ideal class-B
WiMAX PA has an average eciency of roughly 25 %, which is a drastic reduc-
tion from the 78 % theoretical maximum. The limited average eciency of linear
27
Figure 1.14: The eciency vs peak-to-average power for linear PAs.
amplier designs when used with modulation schemes that experience moderate-
to-high PAPR has created a huge demand for power ampliers that remain ecient
at reduced output powers.
In addition to eciency challenges dictated by the next generation modulation
schemes, the frequency agility of a power amplier has been drastically increased
due to the multi-carrier and large modulation bandwidths required by the advanced
modulation schemes. While the bandwidths of these carrier based modulation
schemes do not approach the frequency requirements of UWB imaging systems
discussed in the previous section, the challenges of switching power ampliers to
meet the 4G+ modulation bandwidths while maintaining a high eciency is not
trivial. LTE Single Carrier FDMA (SC-FDMA) demonstrate uplink data rates
up to 75 Mbit/s with 20 MHz of bandwidth [1], while WiMAX (IEEE 802.16e)
28
requires up to 56 Mbit/s with 20 MHz wide channels [2]. Therefore, a state of the
art transmitter must be power ecient and process large signal bandwidths, which
experience large PAPR.
The evolution of communication standards has resulted in a holistic transmitter
design approach. In order to meet the transmitter eciency demands of future
wireless devices, the PA must be designed in conjunction with the transmitter. In
order to increase the overall system power eciency, the growing trend in trans-
mitter development is the implementation of a more ecient and less linear power
amplier. Many transmitter topologies have been proposed and investigated to
increase the overall transmitter power eciency by utilizing circuit techniques to
either linearize a nonlinear PA or create a completely new, more ecient architec-
ture [9],[26],[30],[65],[68],[69],[70]. The proceeding sections provide an overview of
recent investigations into increasing the transmitter eciency transmitters through
architectural innovation.
1.2.1 Transmitter Eciency Enhancement Techniques
Transmitters that employ eciency enhancement are architectures where the e-
ciency is increased thorough the implementation of more ecient topologies. These
techniques dier from linearity enhancement because the topology is not using lin-
earity correction methods to achieve a certain performance out of a quasi-linear PA.
29
The techniques presented in this section use novel architectures to produce an over-
all more ecient transmitter. The overall transmitter eciency is still dictated by
the class of the implemented PA(s), which is typically a very high ecient switching
PA. Depending on the transmitter performance, the linearity enhancement meth-
ods, presented in the previews section, may be combined with an ecient architec-
ture to meet a specic communication standard. While there are many proposed
eciency enhancement methods, the high data rates and bandwidth requirements
of advanced communications systems favor a silicon implementation due to the
ability to completely integrate the entire system onto a single die.
1.2.1.1 Doherty Amplier
The Doherty power amplier architecture combines two moderately ecient am-
pliers to produce a highly ecient amplier while operating at large back-o
powers[31], [63]. A block diagram of the Doherty amplier is shown in Figure
1.15. The main amplier is usually quasi-linear (class-AB or class-B), while the
auxiliary amplier is usually a more ecient class-C. During low power operation,
the auxiliary amplier is cuto (inactive), thus the PA performance is dictated
solely by the performance of the main amplier. During higher output powers, the
main amplier saturates and the auxiliary amplier becomes active and is used to
boost (or peak) the total output power. This peaking from the auxiliary amplier
30
Figure 1.15: A block diagram of a Doherty power amplier.
allows the amplier to yield moderate-to-high back-o eciency performance. Do-
herty ampliers are the workhorse for high power cellular base stations that require
linear performance for modulation schemes that have high PAPR. Its popularity
is due to the simplicity of the architecture, which makes it more amenable for
III-V technologies. Unfortunately the peak eciency is limited to the maximum
theoretical eciency of a class-B power amplier (<80 %).
1.2.1.2 Digital Polar Transmitter (DPT)
A digital polar transmitter architecture (sub-set of EER) implemented with switch-
ing power ampliers (class-D or class-E) has a 100% theoretical eciency for all
output power levels. This is the only architecture that has a 100% theoretical e-
ciency for all output power levels. This is crucial due to the large PAPR of future
communication standards.
31
Figure 1.16: A block diagram of a digital polar transmitter
An example of a digital polar transmitter is featured in Figure 1.16. The trans-
mitter consists of a switching power amplier core, a phase modulation and dis-
tribution network, an amplitude modulation decoder, and a digital control unit.
It can be seen from Figure 1.16 that a digital polar transmitter is nothing more
than a high-power slightly altered Digital-to-Analog Converter (DAC). Amplitude
modulation is typically achieved by turning on the appropriate number of unit cells
in the power array using the decoder. The phase modulation is accomplished by
modulating the carrier frequency at the inputs of the unit cells. The unit cells are
1-bit highly ecient switching power ampliers. Therefore, when enabled, each
unit cell always operates at the peak output power and yields maximum eciency.
Due to the digital like nature of a DPT, it does have nite resolution and suers
from many of the challenges present in digital-to-analog converters[37], [56].
Figure 1.17 compares the theoretical eciency comparison vs back-o power
of a standalone class-B amplier, a Doherty power amplier, and a class-E ampli-
er. The maximum theoretical eciency of any transmitter topology is set by the
32
Figure 1.17: The theoretical drain eciency comparison between a Class-A, Class-
B, Doherty Amplier, and a 5-bit DPT
amplier class used in the design. Thus, a classical Doherty amplier has a maxi-
mum achievable eciency that is identical to a class-B amplier. It can be seen that
Doherty conguration increase the back-o eciency but not the maximum achiev-
able eciency. The maximum achievable eciency of a class-E amplier is 100%
and since a DPT transmitter only operates each unit cell at maximum eciency
(maximum power) the theoretical eciency is a constant 100%. Unlike the linear
Doherty amplier, a DPT only has discrete number of output levels. Therefore, a
nite element DPT trades o output power resolution for high eciency operation.
The amount of unit cells in the switching power array determines the output power
dynamic range and peak envelope power (PEP). For example, if a DPT is imple-
mented with 32 unit cells (5-bits), then the dynamic range of the transmitter is
33
15dB (10log(2
5
)). From Figure 1.17, the theoretical drain eciency of a classical
7
2-stage Doherty amplier drops by more than half at 15 dB back-o. If an appli-
cation can tolerate the discrete nature of the transmitted output power and the
spectral mask for a given communication standard can be met, then the ultimate
solution, in terms of achievable theoretical eciency, is a digital polar transmitter
implemented with high-ecient nonlinear switching power ampliers.
Additional linearization techniques or advanced modulation techniques (e.g.
sigma-delta) may be required to meet a given specic communication standard (e.g.
64-QAM). The circuitry required for the additional linearization and the switching
nature of class-D and class-E ampliers makes silicon an ideal candidate for the
realization of the next generation of mobile devices due to the high integration pos-
sibilities of digital CMOS. In order to realize an RF or millimeter wave digital polar
transmitter, a silicon process with highf
t
and digital CMOS integration capability
is required. The lack of integrated digital logic that enables advanced control and
calibration is a major obstacle towards the realization of highly complex nonlinear
amplier architectures in III-V technologies. The amplitude and phase modulation
required in a DPT (Figure 1.16) will require extensive digital logic for calibration
and control. In addition, even if a highly ecient millimeter-wave silicon power
amplier core can be realized, a deployable digital polar transmitter will more than
likely require additional linearization (e.g. digital predistortion) to meet the FCC
7
The auxiliary power amplier is designed to turn on at half PEP.
34
mask specication for a given standard, thus reinforcing the silicon implementation
requirement.
1.3 Summary
The complexity of the next generation of wireless systems presents a signicant
challenge to the way RF and millimeter wave systems are designed. The task of
processing pico-second pulse or wideband high peak-to-average power ratio modula-
tion schemes has reinvigorated the single chip module implementation. The choice
on silicon implementation is no longer solely determined by the economics. The
ability to completely integrate a millimeter-wave integrated circuit (MMIC) with
a mixed-signal application specic integrated circuit (ASIC) onto a single die us-
ing nanometer silicon devices allows the emergence of novel and elegant solutions.
While, III-V devices have dominated the wireless PA market due to high break down
voltages, insulating substrates and superior metal properties (i.e. gold), the high
integration aorded by silicon processes may produce increased performance or un-
realized functionality than what can be achieved using a traditional low integration
III-V PA technology. The increased functionality and performance requirements
by future wireless systems indicates that the integration of digital logic into the
transmitter core is no longer a luxury.
35
Chapter 2
Ultra-Wideband Power Ampliers
The increased interest in ultra wideband (UWB) pulsed based systems for high
resolution imaging applications [42] has created a demand for low-to-medium power
ampliers capable of transmitting such signals
1
. The complexity in the timing and
control circuity implemented in a UWB radar system [21] make the realization
of such a system more amenable to a fully integrated silicon solution. Therefore,
the delivery of an integrated CMOS power amplier with the ability to transmit
arbitrary instantaneous UWB (time-limited) waveforms has signicant value in
realizing a completely integrated silicon UWB imaging transceiver. UWB radar
and imaging systems which utilize waveforms that occupy the FCC-allocated lower
GHz frequency bands (960-3100 MHz) are attractive for wireless search-and-rescue
and see-through-the-wall sensing applications as well as within-the-wall imaging
due to the lower electromagnetic attenuation of most materials at these frequencies.
1
In Title 47 CFR Part 15, the FCC limits peak Equivalent Isotropic Radiated Power (EIRP)
to < 0 dBm per 50 MHz of bandwidth.
36
Figure 2.1: Spectrum allocation for UWB imaging applications and the one way
attenuation through concrete.
A plot of the FCC allocated UWB spectrum targeted for Through Wall Imaging
(TWI), Ground Penetrating Radar (GPR), and Medical Imaging (MI) is plotted
along with the one way attenuation through 4 inches of concrete versus frequency in
Figure 2.1 [35]. While the average Equivalent Isotropically Radiated Power (EIRP)
is governed by the FCC mask, the peak power of an UWB signal with 3 GHz of
bandwidth must have a peak EIRP less than 18 dBm. As demonstrated in Section
1.1.5, the generation of 18 dBm with 3 GHz bandwidth from a supply limited
technology is a signicant challenge.
There are two ways of transmitting UWB time-limited signals on silicon: either
a small signal pulse can be amplied linearly or a high power pulse can be generated
and subsequently transmitted, as shown in Figures 2.2(a) and (b) respectively. The
amplication of UWB pulses (Figures 2.2(a)) requires a power amplier that has the
37
Figure 2.2: Conceptual block diagram of transmitted UWB pulse through (a) linear
amplication and (b) generation.
ability to amplify a time-limited pulse with little to no amplitude or phase distortion
(little group delay variation), while adhering to technology breakdown limits. An
UWB waveform generator (Figures 2.2(b)) must produce pico-second pulse that
demonstrates high reliability in both pulse production and device lifetime (failures
due to device stress). This section presents the main contributions of research
accomplished at USC towards the realization of integrated UWB CMOS power
ampliers and an UWB digital transmitting waveform generator.
2.1 Tapered Distributed Amplication
The inability to tune out device parasitic capacitance, which can be substantial
due to the large device sizes implemented in power ampliers, in an ultra wideband
design adds a new degree of complexity to PA design. The distributed amplier
has been the quintessential solution for amplifying across large bandwidths that re-
quire
at gain and group delay performance. In principle, distributed amplication
techniques may be incorporated into the design of a PA. However, as discussed in
38
Figure 2.3: A tapered distributed amplier: (a) schematic and (b) an illustration
of tapered micro-strip line implementation.
section 1.1.1.1, the reverse termination reduces the theoretical maximum achievable
eciency by half (25 % for a class-A PA) when a traditional distributed amplier
architecture, shown in Figure 1.3, is used.
An alternative approach is to substitute a tapered transmission line for the
output quasi-distributed transmission line. Then-device Tapered Distributed Am-
plier (TDA), shown in Figure 2.3, eliminates the reverse-wave termination, and
hence, the power loss that is associated with it [36]. The tapered line distributed
amplier operation mimics the traditional distributed amplier except the output
transmission line is now realized with a tapered impedance structure, as opposed to
a constant impedance transmission line found in a traditional distributed amplier.
39
The tapered line architecture also provides an eective wideband impedance down
conversion. The increased eciency and inherent impedance down conversion make
a tapered distributed amplier attractive for implementation as a wideband power
amplier.
Figure 2.3(a) illustrates the current interaction between two devices at the N
th
taped line interface. DeviceM
N1
injects a current into the rst element of the ta-
pered structure (Z
o
). For proper operation, the re
ected current wave,
N
I
DN1
, at
theN
th
tapered line interface must be canceled by the reverse current,K
R
I
DN
, pro-
duced by theN
th
device (M
N
), while the forward currentK
F
I
DN
from each device
located at theN
th
impedance mismatch must add coherently with the transmitted
current from the device in the previous section, T
N
I
DN1
. It can be shown that
if the currents in the devices are equal and the tapered drain line characteristic
impedance are designed properly, the impedance of the N
th
-section is
Z
0
N
, then all
the reverse current will be canceled and the forward currents will add coherently
to produce a total output current that is equal to nI
D
. As with a traditional
distributed amplier, the signal delay through each section should allow coherent
signal addition in the output line. This is achieved by designing the delay through
each input transmission line section to compensate for the delay associated with
the active device and output transmission line section.
The frequency limitation of the amplier is set by the cuto frequency of the
quasi-distributed transmission lines, f
c
. As discussed in Section 1.1.1.1, the cuto
40
frequency of the quasi-distributed transmission lines is governed by the character-
istic impedance,Z
o
, and the transmission line capacitance,C
l
. The combination of
device input capacitance, C
in
, and any parasitics associated with on-chip passives
cannot exceed the transmission line capacitance. Therefore the required amplier
bandwidth and the input line characteristic impedance set the maximum allowable
active device size. In addition to the cuto frequency of the input line, another
limitation on device size is the the real part of the device output admittance. As-
suming a lossless device input, the real part of the output admittance associated
with a single NFET device is
Re (Y
out
) =
g
m
C
gd
(C
gs
+Cgd)
!
t
Cgd: (2.1)
Equation 2.1 predicts the parasitic gate-drain capacitance, C
gd
, feedback produces
a real part that lowers the output impedance as the device size is increased. If the
device output impedance is reduced enough, then the device will adversely load
the tapered line and reduce the achievable amplier eciency. The reduction in
PA eciency is attributed to the wasted power being consumed by the nite de-
vice output impedance. Ignoring nonlinearities, if a device is modeled as a Norton
equivalent circuit, then it is easy to visualize how the output power is self-consumed
if the real part of the output impedance, R
out
=
1
Yout
, is not much greater than the
eective impedance presented at the interface between two section of the taped
41
transmission line. Assuming the imaginary part of the output admittance is com-
pletely absorbed into the passives of the quasi-distributed transmission line, the
output current delivered to the tapered line, I
DN
, of the N
th
device is
I
DN
=

1
Y
22
1
Y
22
+R
LN
!
I
RF
=K
D
I
RF
; (2.2)
where I
RF
= g
m
V
gs
and R
LN
is the eective impedance of the output line at the
N
th
interface. The loss associated with the device loading eect on the transmission
line can be captured in the drain eciency
2
of each device and is shown to be

D
=
K
2
D
(1
K
)
2
; (2.3)
where
K
=
V
knee
V
DD
. Therefore, the maximum device size implemented in each section
of the tapered distributed amplier is determined by the cuto frequency of the
quasi-distributed lines and the max allowable eciency degradation due to device
loading eects.
As previously mentioned, the tapped transmission line provides an active impedance
transformation in addition to eliminating the reverse termination. An eective
impedance down conversion is achieved at the very output of the amplier thought
2
Assuming the device is biased in class-A operation.
42
the coherent addition of all the currents along the tapered line, while the voltage
along the line is kept constant. In a traditional single stage PA design, the optimum
class-A load resistance, R
opt
, is given by
R
opt
=
(V
DD
V
knee
)
I
DC
; (2.4)
whereV
DD
is the supply voltage ,V
knee
is the knee voltage, andI
DC
is the DC drain
current. As discussed in Section 1.1.1, the maximum power, linearity and eciency
are determined byR
opt
from the load line characterization. If a tapered distributed
amplier topology is used, then the optimum load impedance is
R
opt;TDA
=
(V
DD
V
knee
)
nI
DC
; (2.5)
where n is the number of stages implemented in the distributed amplier. This
new degree of freedom allows a designer to use the largest device, as allowed by
Equations 1.7 and 2.3, then choose the number of stages to achieve the desired
output power. While theoretically the number of stages can be increased with-
out bound, practically a limit exists due to nite passive Q components, resulting
in diminishing returns in output power and eciency as the number of stages is
increased[6],[89].
43
2.1.1 Monolithic Tapered Transmission Line
For monolithic realization, the passives in the tapered impedance output can be
realized through a variety of transmission lines [88]. An example using slow-wave
micro-strip lines with a patterned ground is shown in Figure 2.3(b). Slow-wave
micro-strip lines made with a patterned ground allows the capacitance of the line
to be altered with minimal inductance reduction using striped shielding lines un-
derneath the microstrip [18],[40],[55],[76]. The shielding strips used in slow wave
transmission lines can reduce any unwanted substrate coupling and associated eddy
current losses. The eective capacitance at each interface of the tapered line can
be controlled by the device size and the distance between the signal line and the
shielding strip, which can be varied by implementing the strips in dierent metal
layers. Implementation in a multi-metal silicon process allows a high degree of
freedom when trying to synthesize a specic capacitance. The length and width of
the microstrip are used to achieve a specic inductance. The inductance is used
together with the device and microstrip capacitance to achieve the required trans-
mission line impedance. The current handling capability of the metals sets the
minimum width of the lines.
2.2 Wideband Impedance Transformation
The fundamental challenge of designing a PA in a technology with a limited break-
down voltage is achieving the desired output power using a predened standard load
44
Figure 2.4: 2-Stage Transmission Line Transformers (TLT): (a) Ruthro and (b)
Guanella implementation.
impedance, which is usually 50
. As described in Section 1.1.5, impedance trans-
formations are implemented with passives using L-, Tee-, or Pi-matching topologies
to operate within the device limits and deliver the required power to the antenna.
However, these techniques are usually bandwidth limited. A constant wideband
impedance transformation is required in order to realize a PA with true instanta-
neous UWB performance in a technology with a limited breakdown voltage. Wide-
band impedance transformations are more complex than their narrow-band coun-
terpart and thus requires a dierent approach.
Two solutions for wideband impedance transformation employ Transmission
Line Transformers (TLT) [39],[74]. The Ruthro topology (aka the \Bootstrap
Eect" TLT) and the Guanella transformer (aka the \constant delay" TLT) both
45
achieve a wideband impedance transformation. Each structure provides a 1 : n
2
transformation ratio, wheren is the order of the TLT. The TLT order of a Ruthro
is dened as two times the number of transmission line pairs used in the design, since
it utilizes both the forward and reverse path in a transmission line. The order of
a Guanella is dened as the number of transmission line pairs. The fundamentals
developed by each approach can be creatively used to achieve a wide variety of
impedance transformation ratio beyond 1 : n
2
, which can provide a designer with
more degrees of freedom [58]. Examples of the Ruthro and Guanella transformers
featuring a 1:4 impedance transform ratio are shown in Figure 2.4(a) and (b),
respectively. Dierential Ruthro and Guanella transmission line transformers are
also possible. The operation of a dierential TLT structure is identical to a single
ended structure if a duplicate mirror image TLT structure replaces the ground ports
shown in Figure 2.4.
While the Ruthro and Guanella TLTs were originally envisioned as wire wound
transformer or coaxial cable structures, each can theoretically be implemented us-
ing transmission lines. In order to realize TLTs using transmission lines, a closer
inspection of transmission lines is required to study the eectiveness and limitation
of wideband TLTs.
The two-port ABCD parameters of a transmission line are
46
2
6
6
6
4
V
in
I
in
3
7
7
7
5
=
2
6
6
6
4
cosh
l Z
o
sinh
l
sinh
l
Zo
cosh
l
3
7
7
7
5
2
6
6
6
4
V
out
I
out
3
7
7
7
5
(2.6)
where
is the complex propagation constant,l is the length of the line, andZ
o
is the
characteristic impedance of the line. It is well know that if a low-loss transmission
line is terminated with a load equal to the line characteristic impedance, then the
input impedance of the line is Z
o
until the frequency limit of the line is reached.
However, TLTs using practical low loss transmission lines do not have the same
frequency independent behavior.
2.2.1 Ruthro Transmission Line Transformer
To rst order, a Ruthro TLT operation produces a \boot strap" eect which
essentially doubles the output voltage for a n = 2 topology, using the return path
of a transmission line. As shown in Figure 2.4(a), a voltage, V
s
is applied to the
upper line of a coupled transmission line pair input and also to the output of the
return path. Assuming a lossless line, the voltage propagating down the line, V
o
,
adds coherently with the voltage applied to the output of the return path, V
s
,
which results in V
L
= 2V
s
, since V
o
=V
s
. This voltage doubling is known as \boot
strapping", since the output voltage is doubled by coherently adding the input
voltage across the transmission line's forward and return paths. The input current,
47
I
s
, is divided between the upper line and the return path,I
o
=
Is
2
, therefore the load
current is half the input current,I
L
=
Is
2
. SinceI
o
=I
L
=
Is
2
andV
o
=V
s
=
V
L
2
, the
characteristic impedance of the line, Z
o
, is required to be half the load and double
the source impedance, Z
o
=
R
L
2
= 2Z
s
.
While the basic explanation above gives an intuitive operational understanding
of a Ruthro transformer, a comprehensive analysis is required to fully understand
the limitations of the topology. Using Equation 2.6, the input impedance of a
lossless (
l =jl) n=2 Ruthro TLT, featured in Figure 2.4(a), is
Z
in
=
R
L

cos(l) +j

Zo
R
L

sin(l)

(1 +cos(l))
2
sin
2
(l) +j

Zo
R
L

sin(l)cos(l)
: (2.7)
Equation 2.7 reduces toZ
in
=
R
L
4
ifl =n2, wheren = 0; 1; 2; 3;:::;1. Therefore
short lines (l << 1) and line lengths where l is a multiple of 2 produce a
wideband impedance transformation, where the bandwidth is limited by satisfying
l =n2. The analysis used to generate Equation 2.7 can be continued to realize
expressions for the n = 2 Ruthro TLT voltage , A
V
, and current, A
I
, transfer
functions, which are
A
V
=
1 +cos(l)
cos(l) +j

Zo
R
L

sin(l)
; and (2.8)
48
Figure 2.5: The frequency performance of ideal Ruthro TLT with various trans-
mission line lengths (1, 2, 4, and 8 mm).
A
I
=
1 +cos(l)
(1 +cos(l))
2
sin
2
(l) +j

R
L
Zo

sin(L)
: (2.9)
Equations 2.8 and 2.9 reduce to A
V
= 2 and A
I
=
1
2
if l = n2, where n =
0; 1; 2; 3;:::;1. Therefore, as with the input impedance, the maximum power trans-
fer for a Ruthro transmission line transformer is dependent on the value of l.
The frequency performance of Ruthro TLTs, implemented with ideal transmis-
sion lines, for various transmission line length are shown in Figure 2.5.
As shown in Figure 2.5, the Ruthro TLT is sensitive to the transmission line
length (l). As the length of the line is increased, the performance starts to dras-
tically deviate from the ideal case. If the l product is design properly, then the
Ruthro demonstrates a wideband impedance transformation. The low frequency
operating limit is set by the impedance through the transmission line return path
49
to ground. At low frequency, the path through the transmission line return path
shorts the input to ground. Thus, the transmission line transformer lower cut o
frequency is set by the transmission line length, which must be sucient to isolate
the input from the ground connection. This low frequency limit is not captured by
Figure 2.5 because the transmission line model (Equation 2.6) used in the simula-
tion does not support a common mode propagation; the currents through the line
are perfectly dierential. The upper frequency operation is set by satisfying the
l = n2 condition, where n = 0; 1; 2; 3;:::;1. Therefore, assuming the transmis-
sion line can be suciently modeled by the two-port model featured in Equation
2.6, the Ruthro produces a wideband impedance transformation suitable for UWB
PA applications.
2.2.2 Guanella Transmission Line Transformer
To rst order, the operation of a 1:4 Guanella transmission line transformer is
very similar to the Ruthro TLT. Referring to Figure 2.4(b), the input current,
I
s
is divided between the dierential inputs of the two transmission line pairs,
while the input voltage, V
s
, is applied to the inputs of both pairs. If the current
is divided equally through each transmission line pair
3
and the lines are low-loss,
then the current delivered to the load, I
L
, is half of that supplied by the source.
Similarly, the voltages propagating to the end of each low loss line add coherently
and deliver twice the voltage to the load, V
L
. For n = 2, where n is the TLT
3
A very critical assumption.
50
order and describes the number of transmission line pairs used in the structure, a
Guanella transformer delivers twice the voltage and half the current to the load and
therefore achieves a 1:4, orn
2
, impedance transformation. To satisfy these current
and voltage relationships the characteristic impedance, Z
o
, of the two coupled line
pairs must be equal to the load impedance divided by the TLT order, Z
o
=
R
L
n
=
nR
s
. In the example shown in Figure 2.4(b), the characteristic impedance must
equal half the load impedance. The main dierence between the Guanella and the
Ruthro transmission line transformer is the additional transmission line required.
A more comprehensive analysis is required to determine if the Guanella performance
justies this additional overhead.
Assuming modeling the transmission lines with Equation 2.6 is adequate
4
, the
input impedance,Z
in
, of an = 2 Guanella TLT, featured in Figure 2.4(b), is found
to be
Z
in
=
V
in
I
in
=Z
o
R
L
2
cosh(
l) +Z
o
sinh(
l)
R
L
sinh(
l) + 2Z
o
cosh(
l)
: (2.10)
If the characteristic impedance of the line is designed to be equal to half the load,
then Equation 2.10 reduces to
4
In order to be valid, this assumption requires symmetric dierential operation and complete
even-mode suppression in the transmission lines.
51
Z
in
=
V
in
I
in
=
Z
o
2
=
R
L
4
; (2.11)
and a frequency independent 1:4 impedance transformer is achieved. The addi-
tional line required in a Guanella has resulted in a frequency independent input
impedance. The input impedance insensitivity to frequency is a direct result from
the equal delay produced by the additional transmission line and has negated the
input impedance dependance on l, which plagues the Ruthro TLT. As with ev-
erything discussed thus far regarding a Ruthro TLT, an important assumption
made in the derivation of Equation 2.10 is that the forward and return currents
on the upper (forward path) and lower lines (return path), respectively, are equal
in magnitude and opposite in phase with respect to each other in each transmis-
sion line. In other words, the lines are lossless and only support the propagation
of odd-modes. Thus the even-modes must be suppressed by ideally making the
even-mode characteristic impedance innite at the frequencies of operation. The
even-mode suppression assumption was forced when a two-port representation for
the transmission lines (Equation 2.6) was used to derive Equation 2.10. Previous
TLT implementations have utilized ferrite material to assist with proper operation
[43],[73]. Standard silicon IC processes do not have access to on-chip ferrite materi-
als, so, as will be discussed shortly, additional methods must be exercised in order
to implement a monolithic IC transmission line transformer.
52
Continuing the assumption of even-mode suppression in the transmission lines,
the two-port ABCD model of a transmission line can be used to determine the
voltage and current transfer functions. For R
L
= 2Z
o
, the n = 2 Guanella TLT
voltage , A
V
, and current, A
I
, transfer functions are
A
V
=
2
cos(l) +jsin(l)
= 2e
jl
; and (2.12)
A
I
=
1
2cos(l) +j

R
L
Zo

sin(l)
=

1
2

e
jl
: (2.13)
The magnitude of the voltage and current transfer functions reduce to A
V
= 2
and A
I
=
1
2
and are independent of frequency for a n = 2 Guanella TLT. There-
fore, the maximum power transfer is also independent of frequency ifR
L
= 2Z
o
. As
shown in Figure 2.6, the Guanella TLT demonstrates a frequency independent wide-
band impedance transformation and unity power gain. While both the Ruthro and
Guanella wideband transformer topologies are very similar, the Guanella structure
is the focus of this thesis because of its superior frequency performance due to the
\equal delay" coherent wave combining produced by the additional transmission
line. All of the analysis for transmission line transformers thus far has assumed
53
Figure 2.6: The frequency performance of ideal Guanella TLT with various trans-
mission line lengths (1, 2, 4, and 8 mm).
even-mode suppression operation through lossless lines. In order to fully investi-
gate the potential for using transmission line transformers on a monolithic silicon
process, a closer inspection of coupled lines is required, specically the eects of
even-mode propagation.
2.2.3 Silicon Implementation of TLTs
Due to the nite and lossy ground planes, transmission lines realized in a monolithic
silicon process are more accurately modeled as coupled transmission lines than the
two-port ABCD-parameter representation in Equation 2.6. A complete transmis-
sion line model would account for the even- and odd-mode propagation in both the
forward and reverse paths. In order to investigate the eects of a nite even-mode
impedance on TLT, the even- and odd-mode characteristic impedance, Z
o;even
and
Z
o;odd
, respectively, can be solved from the wave equation derivation of two coupled
lines. They are found to be
54
Z
o;even
=

L +L
m
C
T
+C
m

1
2
and Z
o;odd
=

LL
m
C
T
C
m

1
2
: (2.14)
where L is the inductance , C is the capacitance, L
m
is the mutual coupled in-
ductance, C
m
is the mutual coupled capacitance of the two coupled lines and
C
T
= C + C
m
. The analysis presented thus far has assumed even-mode sup-
pression in the TLT transmission lines, which translates to Z
oeven
=1. From
Equation 2.14, it is evident that the coupling between the transmission lines may
be used to increase the even-mode characteristic impedance, while setting the odd-
mode impedance to the impedance required by the TLT impedance transformation
structure.
Ideally, the even-mode should be suppressed so the currents through the trans-
mission lines forward and reverse paths are dierentially symmetric. Two examples
of coupled lines are shown in Figure 2.7. Coplanar strips are commonly used as
coupled lines on a silicon process. While more symmetric with respect to the silicon
substrate, the coupling is not as high as what can be achieved using the more area
ecient broadside coupled lines.
Ideally, a higher coupling factor may be used to increase the even-mode impedance
while setting the odd-mode impedance to the characteristic impedance required by
the transmission line transformer. Figure 2.8 compares the dimensions of coplanar
and broadside coupled transmission lines with a dierential characteristic impedance
55
Figure 2.7: Available layout of coupled lines for a monolithic process: (a) coplanar
strip lines and (b) broadside coupled strip lines.
Figure 2.8: Design examples of coupled lines in IBM 8RF-LM (a) coplanar strip
lines and (b) broadside coupled strip lines.
56
Figure 2.9: The frequency performance of a n = 2 Guanella versus K
e
for various
lengths of transmission line .
of 25 ohms if implemented in a standard CMOS process
5
. The broadside coupled
lines have less loss and are more area ecient and thus more attractive for imple-
mentation as transmission line transformers. In addition, the lower characteristic
impedance required for high order transmission line transformer is easier to achieve
due to the better coupling through larger achievable C
m
and L
m
values.
A complete analysis of a n = 2 Guanella transmission line transformer using a
4x4 g-parameter model of each transmission line accurately accounts for all modes
of propagation. Depending on the available metal stack option, there exists a
nite range of odd-mode and even-mode characteristic impedances which can be
synthesized using monolithic coupled transmission lines; not only are the absolute
values limited but the ratio of the two is conned [62]. Using a 4x4 g-parameter
model for the transmission line, the input impedance,Z
in
, voltage transfer function,
A
V
, and current transfer function, A
I
, can be derived. The complete derivation of
5
The dimensions are indicative of an implementation in IBM 8RF-LM
57
Figure 2.10: The simulated frequency performance of a n = 2 Guanella imple-
mented in IBM8HP for various lengths of transmission line. The TLT input
impedance is designed to be 6.25
.
ann = 2 Guanella TLT, which includes the derivation of a 4x4 matrix for a coupled
transmission line model, is found in Section A.1 of the Appendix.
A plot of the frequency performance of a losslessn = 2 Guanella TLT for various
even-to-odd mode impedance ratios, K
e
=
Zo;even
Z
o;odd
, and transmission line lengths is
shown in Figure 2.9. This plot highlights the importance of designing TLT with
transmission lines that have the highest achievable even-mode impedance. Addi-
tionally, increasing the length of the line improves the lower frequency performance
of a xed even-to-odd mode impedance ratio. Therefore, the rst step when de-
signing a monolithic TLT is to maximize the achievable transmission line K
e
that
the metal stack option will allow. Then, the length of the line should be increased
to cover the lowest frequency of interest. Unfortunately, low frequency operation
will result in lower transformer eciency due to the increase in the series loss of
the long transmission lines.
58
An = 2 Guanella was designed in a 130nm SiGe technology (IBM 8HP), which
features an analog metal layer stack. The transmission lines where designed with
a odd-mode characteristic impedance of 12.5
. The simulated input resistance
and transformer eciency using an electromagnetic simulator (IE3D) are shown in
Figure 2.10. Neglecting loss from via interconnect, the Guanella TLT features 1:4
(Input resistance = 6.25
) wideband impedance transformation from a 25
load.
The plot also highlights the additional transmission line length required to cover
the lower gigahertz frequencies, which comes at the expense of additional series loss
and lower bandwidth. Figure 2.10 demonstrates that wideband monolithic silicon
transmission line transformers, suitable for UWB imaging applications, are possible.
The challenges of implementing TLT on silicon arise from the implementation of
nonideal transmission lines, which support even mode propagation due to the nite
and lossy ground plane, characteristic on a silicon chip.
2.2.4 A 1:16 Silicon Wideband Impedance Transformer
The implementation of a fully integrated 1:16 Transmission Line transformer on
silicon is accomplished using broadside coupled (or vertically coupled) strip lines.
The transformer was fabricated in a 0.13m CMOS technology with two 0.55 m
metal layers and six 0.35 m metal layers. A dierential 1:16 transformation ratio
is achieved by combing two single-ended 1:16 transformers in series to form one
dierential transformer.
59
Figure 2.11: A 1:16 Transmission Line Transformers (TLT): (a) Schematic and (b)
Layout.
The transformer schematic and layout details are shown in Figure 2.11. The
top two available metals are stacked and used to form the upper transmission line,
while the lowest three metals are stacked and used to form the lower line, as shown
in Figure 2.12. The connection to the transformer inner windings is made by rout-
ing two mid-level metal layers through the virtual ground plane between the upper
and lower transmission lines. For proper operation, the even-mode of propagation
must be suppressed over the entire operating bandwidth. Broadside-coupled strip
lines were selected to increase the even-mode characteristic impedance by exploit-
ing the inherently high coupling between the upper and lower transmission lines,
while setting the odd-mode impedance to the required value dictated by the trans-
formation ratio. The transmission line lengths are determined by the minimum
60
Figure 2.12: A 1:16 Transmission Line Transformers (TLT): (a) 3D layout and (b)
metal stack details.
even-mode suppression required at the lowest desired operating frequency, as de-
scribed in Section 2.2. In order to support lower frequencies, a longer length is
needed. Unfortunately, a longer length increases the series resistance and reduces
the transformer eciency and bandwidth. The two 1:4 dierential TLT are laid
out as two intertwined round spirals to achieve enough common mode suppression
at 1GHz in a compact area. The transformer was designed using coupled trans-
mission line theory and extensively modeled using Mentor's IE3D electromagnetic
simulation software.
A standalone dierential 1:16 UWB transformer was fabricated and the mea-
sured results are shown in Figure 2.13. The measured dierential equivalent impedance
of the transformer demonstrates approximately two ohms of variation around the
61
Figure 2.13: The measured results of a 1:16 Transmission Line Transformers. The
designed input impedance transformed from a 50
load is 3.125

designed value of 6.25
(singled ended) from 0.5 - 5 GHz. The maximum measured
eciency of the transformer is 29 %. It should be noted that the eciency and
bandwidth of the transformer can be dramatically increased in RFCMOS processes
that oer thicker metal layers (>0.55 m) which are a higher distance from the
silicon substrate.
2.3 Wideband Power Combining
In addition to wideband impedance transforming, transmission line transformers
can also be used to power combined PAs. The principle of power combining is
very similar to the impedance transformation operation. An example of two 1:4
Guanella TLT structures being used to power combine two PAs is shown in Figure
62
Figure 2.14: A schematic of two 1:4 TLTs being used as a power combiner.
2.14. The two TLTs leverage voltage combining at the very output to accomplish
power combining, which is essentially a voltage \boot strapping" eect. Thus,
power combining with TLTs is essentially a hybrid Guanella-Ruthro transmission
line transformer.
As shown in Figure 2.14, each PA delivers an output voltage, V
s
, and current,
I
s
, to each 1:4 Guanella transmission line transformer. If the PAs are identical,
the current delivered to the load is I
L
=
Is
2
while the voltage delivered to the
load is V
L
= 4V
s
. Assuming class-A operation, the power delivered to the load is
P
out
= 4V
s
Is
4
=V
s
I
s
, which is double the power supplied by each of the PAs. This
boot-strapping voltage combining technique can be used to power combine more
63
ampliers. The total output power
6
,P
out
, ofM power combined class-A ampliers
using this power combing technique is
P
out
=
Mn
2
V
2
DD
2R
L
; (2.15)
where n is the order of each TLT structure. The power combining network also
provides an eective impedance transformation to each PA. The load impedance,
R
L;PA
, presented to each individual amplier is
R
L;PA
=
R
L
n
2
M
: (2.16)
In order for the power combining TLT network to operate properly
7
, the odd-mode
characteristic impedance of each TLT line, Z
oo
, must equal
Z
oo
=
R
L
nM
: (2.17)
Theoretically, the number of PAs that are power combined using TLT networks has
no bound. However, Equation 2.17 has to be satised in order for the power combing
6
Assuming all the PAs and TLT structures are identical.
7
Assuming sucient common mode suppression.
64
network to operate properly. Even when ignoring loss, as previously discussed, there
exists a practical limitation due to the odd-mode characteristic impedance that can
be physical realized.
2.4 A 20 dBm UWB Silicon Power Amplier
An UWB CMOS Class-A power amplier was fabricated in a standard 0.13m
CMOS process
8
. The UWB PA is compatible with previously reported true-time-
delay-based beamforming systems for low-GHz high resolution imaging applications
[42]. A schematic of the PA is shown in Figure 2.15. A 0.13m CMOS process
(IBM 8RF-LM) was chosen due to availability and device frequency performance,
specically a f
t
=80 GHz. However, the 1.8 V breakdown voltage was a challenge.
A robust and reliable design adheres to the maximum peak voltage swing across
any drain-source requirement. Therefore, the dierential version of the UWB TLT,
featured in Figure 2.11, was implemented to achieve an output power that is greater
than 100 mW from the limited supply voltage.
An input distribution scheme is used to split the PA into two parts: Side A
and Side B as shown in Figure 2.15. Each side feeds the tapered output line
from the side. The PA was spit into two parts to increase the bandwidth and
improve the layout symmetry. The bandwidth is increased by distributing the total
input capacitance of the individual sections into two separate quasi-distributed
8
The process did not oer any metal layers thicker than 0.55m.
65
Figure 2.15: Schematic of a UWB CMOS power amplier
transmission lines using on-chip dierential spiral inductors. As with a traditional
distributed amplier, the signal delay from the input must be designed so coherent
signal addition occurs in the drain line. Therefore, additional lengths of dierential
transmission lines are used at the gate to compensate for the additional delay
from output sections with a large characteristic impedance. Unlike the output
line, the input line shown in Figure 2.15 is a quasi -distributed transmission line
with constant input impedance. The additional sections of dierential transmission
line used in the input lines for delay compensation are easily seen in the micro-
photograph shown in Figure 2.22.
66
Figure 2.16: The load line for a 0.13m NMOS
The core of the fabricated PA is implemented as a class-A 7-stage distributed
amplier with tapered drain-line characteristic impedance for simultaneous wide-
band distributed amplication and impedance down conversion. Each individual
amplier section is a quasi-dierential pair with a cascode. Following the theory
discussed in Section 2.1, the cascode increases the output impedance of each section
to reduce loading the tapered output line. The current source typically found in
dierential ampliers was eliminated to increase the available output voltage swing.
As previously discussed, the tapered distributed amplier eliminates the need for
reverse-wave termination, and hence, the power loss that is associated with it. The
impedance down conversion is achieved through the summation of currents along
the line, while the voltage along the line is kept constant. The sizing of the devices
was done within the guidelines that were established in Section 2.1.
67
Figure 2.17: The eciency degradation due to nite output impedance and knee
voltage of a single 0.13m device.
The load line performance of a single 8RF NMOS device with W=3m, L=0.12
m and NF=500 is shown in Figure 2.16. The load line performance is used to de-
termine the required impedance transformation ratio and device sizing for a desired
output power. From the load line simulation, a maximum drain eciency of 37.47
% is achieved with aV
knee
= 0.2 V and a maximum swing of 1.6 V across the drain
and source. To rst order, this best case drain eciency is dominated by the loss
associated with the device knee voltage. However, the ultra wideband operation
prohibits the use of an inductor to resonate out the imaginary part of the input
and output impedance. Thus, the device size is limited to the cuto frequency of
the quasi-distributed transmission lines and real part of the output impedance.
68
Figure 2.18: The eciency degradation as a function of load resistance and device
size of 0.13m device.
In addition to the loss associated with the knee voltage, the eciency degra-
dation due to the nite output impedance of the device was considered. Ignoring
nonlinear eects and following the theory discussed in Section 2.1, the impact of
the knee voltage factor,
K
, and the nite output impedance factor, K
D
, on the
drain eciency of a class-A biased NMOS, assuming a very optimistic V
knee
=0.2
V, is shown in Figure 2.18.
The results in Figure 2.18 highlight the signicant impact the device size and
load resistance have on the drain eciency for a class-A biased device. The graph
is generated using the theory discussed in Section 2.1 and the simulated output
impedance of a 0.13m NMOS device at 5 GHz. At best, the drain eciency
is 40 % due to the knee voltage. The nite output impedance of large devices
greatly reduces the maximum achievable drain eciency. It is easy to conclude
69
Figure 2.19: The eciency degradation as a function of load resistance and device
size for a cascode.
that a class-A PA fabricated with a 0.13m technology is very limited in terms of
both maximum device size and optimal load impedance. If the load impedance is
between 3 and 6
, then for large devices the drain eciency is reduced to the 25-30
% range without accounting for any reduction due to passive loss or other non-ideal
eects
9
. The inability to resonate out device parasitic capacitance in wideband PA
design is the root cause for the signicant reduction in PA eciency seen in Figure
2.18.
Fortunately, the device output impedance can be increased using a cascode
topology. Figure 2.19 illustrates the improvement of drain eciency using two
identical devices in a cascode topology. Ignoring any non-linear circuit eects, the
drain eciency improvement witnessed in Figure 2.19 is at least 10 to 15 % higher
9
Non-ideal eects include passive loss, nonlinearities, etc.
70
Figure 2.20: The output power and PAE versus biasing and device size for a 7-
section TDPA.
than achieved with a single device. The graph is generated using the theory dis-
cussed in Section 2.1 and the simulated output impedance of two cascode congured
identical 0.13m NMOS devices at 5 GHz. Another positive is that the cascode
performance is also less sensitive to the absolute value of the load resistance. While
the linearity and bandwidth requirements are ignored, the information gathered
from Figure 2.19 gives a starting point for device sizing. To nalize the device size,
a harmonic balance simulator was used to nd the optimal device size and biasing
for a 7-stage tapered distributed amplier at 3 GHz. Assuming a loss-less tapered
line, Figure 2.20 plots the output power and power added eciency for dierent
device sizes and gate-source bias voltages, V
gs
, where NF is the number of ngers
for a 3 m device width and 0.13m channel length. The simulated maximum
71
Figure 2.21: Details of the CPS designs used in the output tapered line.
eciency of the PA core (without the UWB TLT impedance transformation) is 28
% from 1 GHz to 8 GHz during linear Class-A operation.
The tapered impedance output lines use Co-Planar Strip-lines (CPS) in the top
two metals along with
oating strips underneath to reduce substrate coupling and
set the appropriate transmission line impedance. A detailed schematic diagram of
a dierential implementation of coupled CPS lines is shown in Figure 2.21. The
width of all shielded CPS are set to be large enough to reduce series loss, while
satisfying their current handling capability. The length of each CPS section is set to
achieve the appropriate inductance for a desired characteristic impedance. For each
CPS line, the
oating strips are implemented in an appropriate metal layer so that
72
Figure 2.22: Schematic of a UWB CMOS power amplier
the CPS capacitance together with the dierential pair device output capacitance
results in the desired transmission line impedance over the desired bandwidth.
2.4.1 Chip Results
The UWB PA was fabricated in a 0.13m CMOS technology with two 0.55 m
metal layers and six 0.35 m metal layers. A microphotograph for the fabricated
chip is shown in Figure 2.22). The PA uses a 1.5 V supply and occupies an area of 1.8
mm x 2.0 mm. The amplication of picosecond pulse requirement for the intended
imaging application limits the PA to linear Class-A operation. However, nothing in
principle limits the topology to operate exclusively as a Class-A power amplier. If
73
Figure 2.23: Measured output power versus input power
a certain amount of signal distortion can be tolerated, then the amplier conduction
angle can be reduced to improve eciency.
The PA has 20 dB of small-signal power gain over a bandwidth of 1 GHz while
maintaining an input return loss of at least 15dB. The output power versus input
power for a continuous signal source with frequencies of 1 GHz and 2 GHz are
shown in Figure 2.23.
As shown in Figure 2.24, the PA demonstrates a maximum linear (-1 dB com-
pression) output power of 17dBm and a maximum drain eciency of 6 %. The -3
dB bandwidth is roughly 0.6-2.8 GHz and is dominated by the frequency response
of the UWB impedance transformer. In addition to the intended linear operation,
the maximum class-A saturated output power is 21 dBm with a maximum drain
eciency of 16 %. The saturated -3 dB bandwidth is from 0.75-3.75 GHz. A time
74
Figure 2.24: Measured linear (-1 dB compression point) and saturated output power
vs. frequency
75
Figure 2.25: Time domain measurement with an UWB mono-cycle pulse generator.
The output waveforms includes a 20 dB attenuator.
domain measurement with an UWB mono-cycle pulse generator is shown in Figure
2.25. The output waveform includes a 20dB attenuator used in the test setup due
to the input power limitations of the 40 GSPS oscilloscope. A summary of the PA
performance is given in Table 2.1. The amplier clearly demonstrates the ability
to process UWB pulses required for UWB imaging applications [72].
2.5 An UWB Digital Pulse Generating Transmitter
An alternative method of transmitting an UWB waveform is to combine the am-
plier and waveform generation into a single topology. The resulting topology can
be thought of as a Power Digital-to-Analog Converter (PDAC). However, for many
wireless applications, a PDAC is not practical. In general, multi-bit DAC architec-
tures that produce pico-second pulses are not power ecient [8]. If an application
76
Table 2.1: A 20 dBm UWB PA Performance Summary
PA Operation Class-A
Linear -1 dB Bandwidth 0.8-1.8 GHz
Linear -3 dB Bandwidth 0.6-2.6 GHz
Max Linear Output Power (@ -1 dB) 17 dBm @ 1.3 GHz
Max Linear Power Gain (@ -1 dB) 20 dB
Max Linear PAE (@ -1 dB) 6 %
DC Power Consumption 500 mA (@1.5V)
Bandwidth -1 dB 0.8-1.8 GHz
Bandwidth -3 dB 0.6-2.6 GHz
Max Saturated Output Power 21 dBm @ 1.3 GHz
Max Saturated Power Gain 10 dB
Max Saturated PAE 16 %
Chip Area 1.8 mm X 2.0 mm
Technology 0.13m CMOS
Figure 2.26: A schematic block diagram of a 1-bit UWB pulse generator
77
does not require accurate amplitude resolution, then the DAC can be application
tailored and the power consumption can be dramatically reduced. This section
describes an UWB pulse generator where the power consumption is signicantly
reduced by using a delay line, a slow clock, and static CMOS logic to produce
a 1-bit amplitude resolution pico-second pulse generator with variable center fre-
quency and bandwidth. A block diagram of the implemented UWB transmitter
that employs these principles is shown in Figure 2.26.
The pulse generator and class-D drivers are constructed using static CMOS
elements and therefore consume no DC power. The maximum transmitted power is
determined by the antenna impedance (50
) since there is no on-chip impedance
transformation or power combining. The buers that drive the antenna are to
ensure the full swing (1.5 V power supply) across the 50
load. The parasitics of
the package (bond wire and chip and package capacitance) along with the high-pass
nature of an antenna will lter out the high frequencies and remove the DC oset in
the transmitted waveform. Therefore, the transmitter output signal will resemble
a pulsed-sinusoid.
The waveform generation principle is based on delaying a slow accurate clock
(10 MHz) through a digital variable delay line (VDL) with individual tunable delay
elements that produce very small amounts of delay (50-200 ps). Pico-second pulses
that occupy the UWB spectrum (1-10 GHz) can be formed by using the XOR logic
function on any two outputs of any delay element located along the delay line.
78
Figure 2.27: A 5-stage example of the 1-bit UWB pulse generator
A pulse produced through this process will have a center frequency (f
c
) that is
inversely related to the delay dierence between the two signals. If many of these
pulse are added together to form a pulse train, then the total amount of pulses in
one given period will set the bandwidth (BW ) of the pulse train. An example that
highlights the digital control details for a 5-stage delay line is featured in Figure
2.27.
The delay line consists of individual variable delay elements, where the delay,,
can be changed from 50 to 175 ps. Each delay element is a digitally programmed 4-
bit current starved inverter. The input of the delay line is a slow accurate clock. As
the clock propagates down the delay line, a shifted version of the clock is present
at each tap point along the delay line. As long as the rising and falling edges
(at the output of each delay section) are much smaller than the minimum pulse
width, or the center frequency of interest, then these dierent delays can be used
79
Figure 2.28: A 5-stage example of the 1-bit UWB pulse generator with minimum
pulse width settings.
to produce pulses that have a center frequency that is inversely proportional to the
the delay of each section. The shift-registers, along with AND gates, are used to
select the specic delay section output to produce a frequency and bandwidth agile
waveform generator. The programmable shift registers can be used to facilitate the
combination of the output of any even number of delay sections. A novel feature of
the 32-section edge-combiner design shown in Figure 2.26 is the ability to generate
pulses between any two arbitrary points along the delay line. This enables the
generation of pulse widths that are multiples of each individual delay element.
A simulation of the pulse generation principle using the delay line and XOR
combining technique is shown in Figure 2.28. For simplicity, a delay line with 8-
tapped points is shown. Each tap point along the delay line is routed to a digitally
80
controlled AND gate (numbered 1 through 8) and are a shifted version of the slow
clock. Each AND gate can be controlled using the circuitry highlighted in Figure
2.27. In this example, all 8 tap points are selected and pass the delayed clock to
the XOR combiner. The rst row of XOR combiners produce a pulse at points A
through D, where the pulse width is equal to the delay of a single delay element,,
because the XOR function was performed between two adjacent tap points along
the line. In addition to using the current starved inverters, the pulse width can be
increased if other combinations of tap points are combined in the XOR combiner.
Figure 2.29 illustrates the settings required to generate 2 width pulses. In this
setting, the edges of every other tap point are combined. The only dierence is
the pulses are formed in the second row of the XOR combiner, since the rst row
only passes a delayed version of the clock. The center frequency of the transmitted
waveform in Figure 2.28 is twice that of the signal generated from Figure 2.29
because the pulse widths are half as much.
The combiner can be used to generate a pulse width between any two tap points
along the line. The delay between the two tap points sets the center frequency of
the transmitted waveform. The bandwidth of the transmitted waveform is set by
the total number of pulses that are transmitted. Specically, the envelope of all
the transmitted pulse per clock cycle sets the bandwidth of the transmitted signal.
Thus, the signals from Figures 2.28 and Figures 2.29 should have the same band-
width, but dierent center frequencies. As shown in Figure 2.26, a 32-section delay
81
Figure 2.29: A 5-stage example of the 1-bit UWB pulse generator with 2X minimum
pulse width settings.
line allows the pulse generator to have up to 16 consecutive pulses with a pulse
width that is determined by the delay setting of the delay elements. The delay
line and XOR combiner essentially perform the exact same function as multiply-
ing a high frequency square wave (set by the pulse widths) with a low frequency
square wave (set by the number of total pulses). Therefore, a 1-bit UWB waveform
generator with frequency and bandwidth diversity can be constructed by correctly
delaying a slow clock to produce pico-second pulses and combining them to form a
pulse-train.
Depending on the application, the delay line may need calibration and the pulses
propagating through the XOR combiner may need realignment[14], [84], [85], [86].
82
Figure 2.30: The delay performance of each the delay line element versus process
corner for a 0.13m CMOS technology.
Neither were implemented in the fabricated transmitter prototype because the ap-
plication performance specication[21] did not warrant any corrective measures.
An accurate clock was sucient. The most signicant design constraint for the
intended application was power consumption. Therefore, the entire topology is
realized with static CMOS logic. A signicant drawback to this approach, as op-
posed to using common mode logic (CML), is that the minimum achievable delay
is process dependent. Thus process variation simulations must be performed to
ensure the implemented design provided sucient margin to meet the application
specications. The delay of each element used in the delay line is plotted versus
delay setting and process corner in Figure 2.30. With process corners, the mini-
mum achievable delay from each element can vary from 40 - 70 ps. Thus, the worst
83
case maximum center frequency for IBM 8RF using this topology is roughly 7 GHz,
which is sucient for the intended application[21].
2.5.1 Chip Results
Two measurements of the generated waveforms are shown in Figure 2.31. Figures
2.31(a) and (b) show the time and frequency domain measurement, respectively,
of a waveform with a center frequency of approximately 1.25 GHz and a -10 dB
bandwidth of roughly 1 GHz. This waveform was constructed by combining 6 delay
sections (three pulses) with roughly 420 ps of delay in each section. Figures 2.31(c)
and (d) shows the measurement of a waveform with a center frequency of 3.31 GHz
and a -10 dB bandwidth of roughly 2 GHz that was generated by combining 3
pulses with 150 ps delay resolution.
2.6 Summary
This section documents two fundamental ways to transmit UWB signals. The
rst method used distributed amplication techniques and wideband impedance
transformation and power combining to achieve watt-level performance over an
ultra wide bandwidth. The second method focused on generating and transmitting
UWB pulses while minimizing power consumption. All solutions were fabricated
in a 0.13m CMOS process and enable fully integrated silicon solutions for high
resolution imaging.
84
Figure 2.31: The measurement of the 1-bit UWB pulse generator: (a) time domain
measurement and (b) the frequency domain measurement of the 420ps pulses; (c)
time domain measurement and (d) the frequency domain measurement of the 150ps
pulses.
85
Chapter 3
A Q-Band Digital Polar Transmitter (DPT)
The aggressive scaling of silicon devices has produced nanometer silicon-germanium
(SiGe) heterojunction bipolar transistors (HBT) with f
t
> 200GHz and comple-
mentary metal oxide semiconductor (CMOS) devices at the expense of shrinking
breakdown voltages (Figure 1.8). Silicon based power ampliers have relied on
impedance transformation methods to deliver watt-level power to a 50
standard
load without exceeding the breakdown limits of the technology. Traditionally, the
breakdown voltage of the technology sets the maximum supply voltage, usually
around a volt or two for deep submicron silicon technologies. In addition, the
achievable passive quality factor (Q) of silicon is low due to the lossy silicon sub-
strate and limited metal options. Therefore, high impedance transformation ratios
result in signicant power loss for watt level power ampliers implemented with
nanometer silicon technologies due to the inherent low-Q nature associated with
on-chip passives. This chapter will explore methods of increasing millimeter-wave
(mm-wave) transmitter eciency by using nonlinear switch-mode power ampliers
86
Figure 3.1: A schematic of a class-E amplier and the associated waveforms.
and circuit techniques which extend the usable supply voltage beyond the standard
technology breakdown limits.
3.1 HBT Switchmode Power Ampliers
The foundation of a digital polar transmitter is the highly-ecient switchmode
power amplier. The achievable PA eciency sets the bar on how eective a trans-
mitter architecture is for a specic application. As discussed in Section 1.1.2, a
switchmode PA has a maximum theoretical eciency of 100 %, which is achieved
at the expense of linearity. The ability to completely integrate millimeter-wave inte-
grated circuits with mixed-signal CMOS integrated circuits onto a single die allows
for the emergence of novel and elegant linearization solutions for these traditionally
application limited highly ecient ampliers.
87
The traditional linear PA design methodology is to increase the device size just
enough to meet the output power requirement from a given supply voltage and load
impedance. As described in Section 1.1.1, increasing the device size beyond what
is required reduces the maximum achievable eciency due to the power lost from
the reduction in device output impedance. In contrast, the design methodology in
nonlinear switchmode PA design is to increase the devices size as much a possible.
A nonlinear switchmode PA is operated as a switch, thus the eciency is directly
dependent on lowering the device \on" resistance, which is inversely proportional
to device size. A traditional class-E PA schematic and waveforms are illustrated
in Figure 3.1. For a given supply voltage, V
cc
, and load impedance, R
L
, the power
loss associated with the switch on resistance, r
on
, in a class-E amplier is found to
be
P
ron
=

2
+ 28
2(
2
+ 4)
!

r
on
R
L

P
out
: (3.1)
Equation 3.1 shows the eciency of a class-E PA is directly proportional to the
ratio of the on resistance to load resistance,
ron
R
L
. Therefore, the rst priority in
class-E amplier design is to minimize the on resistance associated with the device
by increasing the size. Figure 3.2 plots the on-resistance of an IBM8HP device that
is operating in deep saturation. It also contains a plot of ther
on
required to achieve
90 % collector eciency for various supply voltages. As shown in Equation 3.1, the
88
Figure 3.2: 8HP r
on
characterization and the maximum allowable r
o
n for a 90%
ecient class-E PA vs Supply voltage.
loss of the switch is proportional to
ron
R
L
ratio. Therefore, as long as the breakdown
voltage limits of the technology are not violated, the ability to increase the supply
voltage relaxes the device size requirement due to the ability to use a larger load
impedance to generate an equivalent output power. The achievable IBM8HP high
f
t
HBT on-resistance shown is Figure 3.2 is actually quite optimistic because the
device has been driven into deep saturation. As will be shown, this allows for a
high drain eciency, but the power added eciency will be degraded due to the
input power required to switch an HBT in and out of the saturation region.
The vast majority of switch mode PAs are fabricated with a eld eect transistor
(FET) because a FET is an inherently better switch than a bipolar device. However,
the drain-source break down voltage of a silicon MOSFET is 5-to-6 times less
than what can be achieved in a frequency comparable (equivalent f
t
) SiGe HBT
[41]. Thus, the implementation and challenges associated with implementing a
switchmode power amplier with HBTs at millimeter wave frequencies will be the
89
Figure 3.3: A loadline vs. HBT I-V characteristics and the HBT input power loss
mechanism associated with entering saturation.
focus for the rest of this thesis. The superior breakdown voltage of BiCMOS HBTs
results in larger output power at millimeter-wave frequencies without relinquishing
the superior integration ability of silicon required to realize a fully integrated DPT.
One signicant drawback to an HBT switching power amplier is the consid-
erable input power consumption due to the device entering saturation. Figure 3.3
plots a class-E loadline versus a DC I-V characteristics of a 130nm SiGe HBT and
also highlights the physical loss mechanisms associated with driving an HBT into
saturation. The device is driven into deep saturation in order to maximize drain
eciency by decreasing V
CESAT
and minimizing the current-voltage overlap across
the device. Entering saturation causes the base-collector junction to become for-
ward bias, which dramatically increases the base current and drastically reduces
the device switching speed. The exponential increase in base current results in a
signicant amount of input power consumption. A better visual of the base current
90
Figure 3.4: A 3-D plot of an HBT I-V characteristics with a superimposed class-E
loadline.
is found in Figure 3.4, where the DC I-V characteristic are plotted with a super-
imposed class-E loadline. Even at low frequencies, the loadline clearly highlights
the large power consumption of an HBT class-E amplier due to the base current
generated as the device enters saturation. This problem is only exasperated as the
frequency of operation is increased.
3.1.1 Finite Inductance Class-E PA
While other amplier classes either ignore or use techniques to negate the device
output capacitance, a class-E amplier utilizes this capacitance, along with other
passives, to minimize voltage and current overlap through the devices. This al-
lows the PA to achieve a high switching eciency in the presence of a previously
troublesome parasitic, which is very convenient for mm-wave operation. The term
\parasitic" is used to describe the capacitor because at mm-wave frequencies the
91
Figure 3.5: A schematic of a nite inductance class-E PA.
device parasitic, even for the most advanced silicon technologies, cannot be ignored
and must be incorporated into the design just like any standalone passive element.
The conception of the class-E amplier [33], [78] envisioned the implementation of
the amplier with a RF choke. The evolution of the class-E amplier has resulted in
a design which allows for a nite collector inductance [3], [4], [5], [37], which allows
the realization of a fully integrated silicon class-E power amplier necessary for a
DPT architecture. However, the demonstrated mm-wave class-E analysis[28] fails
to fully address key issues associated with operation at millimeter-wave frequencies.
Specically, the work fails to address when the technology frequency performance,
usually quantied by f
t
, f
max
or !
switch
= 1=(r
on
C
off
), is not sucient to meet all
class-E requirements for the frequency of operation.
A schematic of a nite class-E PA is shown in Figure 3.5. As brie
y discussed in
Section 1.1.2, the PA operation frequency,!
RF
, is related to the resonate frequency
of the passives, !
L
1
C
1
, and by the inductance resonant frequency ratio, X. The
92
Figure 3.6: Output power and
XL
versus X for a 45 GHz PA.
value ofX, Equation 1.13, determines the category of the nite inductance class-E
amplier. Theoretically each category can potentially achieve 100 % drain e-
ciency, but the performance of each, especially in the presence of nite-Q passives,
is far from equal. Figure 3.6 shows the output power and phase shift, , required
by X
L
as a function of X for a 45 GHz lossless PA with a supply voltage of 1.5 V,
a 50 % switching duty cycle
1
, and a load resistance of 12.5
.
As can be seen in Figure 3.6, the output power is a function of the inductance
resonant frequency ratio and is maximized at X=1.4142. In addition, =0 at
X=1.4142, so no additional phase shift is required to align the voltage and current
waveforms at the load. Therefore, X
L
and the loss associated with it are not
required for operation. This is very important due to the nite-Q passives available
on a monolithic silicon process at millimeter-wave frequencies. Assuming a passive
Q of 30 and an ideal switch, Figure 3.7 highlights the achievable power generated
from a nite-inductance class-E amplier as a function ofX. Therefore, this thesis
1
Unless specically noted, the duty cycle is always assumed to be 50 % in this section.
93
Figure 3.7: Output power versus X and RL for a nite-inductance class-E 45 GHz
PA with a 1.5 V supply.
will focus on \parallel-circuit"
2
millimeter-wave silicon nite-inductance class-E PA
design and implementation.
Since it has been established that a \parallel-circuit" class-E topology is the
best suited for silicon implementation, the next step is to determine the optimal
device size, or specically the emitter length, E
L
, for the design example featured
in Figure 3.5. Solving the class-E equations, the required class-E inductance and
capacitance are found to be
C
1
=
1
!
RF
R
L
X
2
K
L
; (3.2)
and
2
As dened in Section 1.1.2.
94
L
1
=
K
L
R
L
!
RF
; (3.3)
where
K
L
=
p

2p
+
2cos()

+sin()

: (3.4)
(3.5)
p, and are numerically found constants derived from the nite inductance class-E
analysis.
3
.
3.1.2 Millimeter-Wave Finite-Inductance Class-E PA
At millimeter-wave frequencies, the value of the device output capacitance becomes
signicant, so the practical realization of bothC
1
andL
1
becomes an issue because,
as shown in Equations 3.2 and 3.3, both are inversely proportional to frequency.
Assuming 45 GHz operation, a 1.5 V supply, and a 12.5
load, the required values
of C
1
and L
1
versus X are plotted in Figure 3.8.
From Figure 3.8, the device size can be determined by choosing the emitter
length of the device such that the complete value of C
1
is realized through the
3
The constants are solved for and plotted in the Appendix A.2.
95
Figure 3.8: The vaues of C
1
and L
1
as a function of X.
parasitic \o" output capacitance of the device. To rst order, the device output
capacitance during cut-o should be used to realizeC
1
because the eective device
output \on" capacitance is shorted out by the low device \on" resistance and it
is assumed to have little contribution to the switching dynamics. Therefore, the
required capacitance plot in Figure 3.8 can be modied to plot device size as a
function of X for 45 GHz operation. The required emitter length for a 0.13m
high f
t
NPN device as a function of the required class-E capacitance, E
L
=f(C
1
),
versus X is shown in Figure 3.9.
The device sizing as a function of class-E capacitance,EL =f(C
1
), curve shown
in Figure 3.9, satises the C
1
requirement, but it fails to account for the required
switch current, I
switch
, for proper class-E operation. The basis of all the nite-
inductance class-E derivations used thus far assumes the device acts like an ideal,
or low loss, switch and, as such, is able to support the required class-E switch
current. In this assumption, the switch current is solely determined by the supply
96
Figure 3.9: The required device size for a 130nm SiGe HBT as a function ofC
1
and
I
switch
.
voltage, load resistance, passive values, and the duty cycle of the class-E switching.
However, the current of a HBT is a function of the input drive. In order to minimize
the input power consumption, the input swing is limited to the boundary where the
device enters saturation. Thus, the device must be appropriately sized to supply
the required class-E current with a limited input drive magnitude. The required
class-E PA switch current is
I
switch
=

V
cc
R
L

2p
2
2K
3
L
!
!
RF
t
p
+sin ((!
RF
t +)sin)
!
: (3.6)
The required emitter size, for a 0.13m SiGe HBT, to supply the appropriate
class-E switch current, E
L
=f(I
switch
), is also plotted versusX in Figure 3.9. The
emitter length required by the switch current is almost twice the emitter length
97
governed by the output device capacitance limit. Thus, the amount of collector
current versus output \o" output capacitance is not sucient to meet all design
requirements for a 45 GHz nite-inductance class-E PA for a 0.13m SiGe HBT.
As the operating frequency and desired output power increase, state-of-the-art
technologies, such as IBM8HP, fail to satisfy all the class-E design criteria. Figure
3.9 suggests a tradeo exists for active device sizing as governed by the class-E
capacitance and current requirements. At the limits, the active devices of the PA
could be designed to meet the class-E capacitance requirement while limiting the
required switch current or it could be sized to support the required class-E current
while exceeding the class-E capacitance limitation. It is also possible that an opti-
mal solution exists between these two design limits. Figure 3.10 plots the eciency
degradation of an ideal 45 GHz \parallel-circuit" nite-inductance class-E PA due
to limiting the device current and exceeding the class-E capacitance requirement.
The capabilities of IBM 8HP are also superimposed on the graph. The plot clearly
suggest that limiting the current of the amplier is far more disadvantageous than
exceeding the class-E capacitance at 45 GHz. Therefore the device should always be
sized to support the required class-E current with a limited input drive. However,
even with ideal passives, technology limitations reduce the maximum achievable
eciency.
To complicate matters further, the HBT output capacitance value was assumed
to be constant and equal to the output capacitance when the device is in cuto.
98
Figure 3.10: The required device size as a function of C
1
and I
switch
.
The parasitic capacitors associated with an HBT are junction capacitors and their
value is heavily dependent on the voltage across them and any associated nonlinear
memory eects. Figure 3.11 plots the instantaneous output capacitance versus
class-E waveforms when driven with a continuous-wave source.
The eective output capacitance of the HBT drastically changes during op-
eration, which contradicts the constant output capacitance previously assumed.
However, if the device is suciently large and renders the device \on" resistance
much smaller than the output \on" capacitance at the operating frequency, then
implementing \o" output capacitance asC
1
has been seen to be sucient for mil-
limeter wave class-E design. However, Figure 3.11 displays a phase shift between
the output and input voltage of the amplier, which is due to the limited switching
speed of the device.
99
Figure 3.11: The dynamics associated with the eective output capacitance of an
HBT during class-E operation.
In addition to the operation limit imposed by the device output parasitics,
the input device parasitics will also impact the achievable class-E performance.
During class-E operation, the HBT will switch between the forward active and
cuto regions. An equivalent circuit model for both regions are found in Figure
3.12. The dierential equation relating the input voltage, V
!t
(!t), to the intrinsic
base voltage, V

(!t), is found to be
!
dV

(!t)
d!t
+V

(!t) =kV
in
(!t); (3.7)
100
where is the time constant associated with the device input andk is a constant as-
sociated with the attenuation at the input; both depend on the device operating re-
gion. When the device is switched into the forward active region,
FA
=

r
b
r
r
b
+r

C

and K
FA
=

r
r+r
b

. As opposed to when the devices are switched \o" and put
into the cuto region, then
CO
= r
b
C

and K
CO
= 1, as shown in Figure 3.12.
There are typically three distinct scenarios that can exist: 1. C

=C
b
, 2. C

>C
b
or 3. C

C
b
. The third criteria tends to predominately exist in power amplier
design due to the large actives and input drive levels required. The third criteria
results in
FA

CO
. As the operating frequency approaches the time constant
associated with the forward active region, the intrinsic base voltage can lag behind
the input voltage due to the large dierence between the forward active and cuto
time constants. Figure 3.12 highlights the high frequency conduction angle,
HFC
,
that can result due to the large dierence in operating region time constants for
!
FA
!t
= 0:25. The lag seen in V

results in an amplier high-frequency condition
angle that is greater than the 50 % duty cycle of the input. The exact amount of
increased conduction angle is directly dependent on the size of the device and the
frequency of operation.
A nite-inductance \parallel-circuit" class-E amplier can be designed to have
a conduction angle larger than 50 %, which, in theory, can produce more output
power while maintaining a 100 % theoretical eciency. However, it has been well
established that a 50 % duty cycle class-E design is more appealing due to the
101
Figure 3.12: Equivalent HBT input parasitics and the impact on class-E conduction
angle for C

C
b
.
resulting larger peak collector voltage and current required for larger conduction
angle implementations[4]. What has not been established is the impact of operating
a 50% duty cycle class-E design at a dierent conduction angle, which, as shown in
Figure 3.12, is an unintended consequence of incorrect device biasing, input signal
magnitude or increasing the amplier operating frequency to where it approaches
the time constant associated with the input of the transistor.
The output power and eciency performance versus conduction angle of a 50 %
duty cycle nite-inductance class-E power amplier is shown in Figure 3.13. The
conduction angle, , is dened as
= 2cos
1

V
th
V
dc
V
A

; (3.8)
102
Figure 3.13: Impact of conduction angle variation on a nite-inductance class-E
amplier.
where V
th
is the device threshold voltage, and the input signal is V
in
(!t) =V
DC
+
V
A
cos(!t). Figure 3.13 shows the output power increases with conduction angle,
but the eciency is drastically reduced as the conduction angle increases above 50
%. The results of Figure 3.13 suggest it is better to operate a mm-wave class-E
at a slightly lower conduction angle than 50 % due to any design uncertainties
(i.e. process variation). That way any intrinsic base lag will not result in a radical
degradation in amplier eciency at high frequencies. Therefore, after the size
of the devices has been determined by the required class-E switch current, the
amplitude and DC bias point of the input drive signal are used to ensure that the
high frequency amplier conduction angle does not result in a drastic eciency
reduction.
All of the factors discussed in this section thus far contribute to the complexity
of trying to determine the optimal device size for a millimeter-wave nite-inductor
103
class-E PA. It can be shown that the theoretical maximum collector voltage, V
c
,
swing of an ideal class-E amplier is roughly 3.562 times the supply voltage. How-
ever, experimentally, the collector swing of a class-E power amplier implemented
with 130nm HBTs and nite-Q passives is limited to around 2.5 times the supply
voltage. The reduction in collector voltage is due to the passive loss, nite device
switching time, high frequency conduction angle and nonlinear parasitic capacitance
associated with the device.
Properly understanding the design parameters and non-ideal integrated circuit
eects will aid the design optimization process. A few rules of thumb can be learned
from the discussion presented in this section. First, the amplier r
on
to R
L
ratio
must be minimized. If the device is too small, then the on-resistance will limit
the eciency for smaller values of load impedance. Second, the required class-E
capacitance is inversely proportional to the load resistance and operating frequency,
but the capacitance is not as critical of a design parameter as meeting the switch
current requirements. If the fabrication technology cannot satisfy all the class-E
design constraints, then a tradeo analysis must be performed to achieve the best
possible eciency.
Estimating a reasonable Q=30 for all passives, the output power and PAE ver-
sus load resistance for various HBT emitter lengths used in a 45 GHz class-E PA
are plotted in Figure 3.14. Assuming loss-less passives and conformity to break-
down voltage limits, a PAE=55 % is the best that can be achieved using a high
104
Figure 3.14: Output Power and PAE versus R
L
for dierent emitter lengths, E
L
.
f
t
0.13m NPN HBT. The information in Figure 3.14 is used to choose a load
resistance and emitter length for a given output power requirement. However, an
impedance transformation is required for a load other than 50
. Any impedance
transformation network will introduce additional loss and reduce the power ampli-
er performance reported in Figure 3.14 . As will be discussed in more detail in
the following section, any power amplier technique that eliminates the need for
an impedance transformation, while maintaining the delivered output power, will
be a more ecient design.
In low gigahertz frequency design, the design mentality for class-E design is to
use the largest possible device to minimize the on resistance, then choose a load
impedance based on a given supply voltage and output power requirement. At
millimeter-wave frequencies, the device parasitics can no longer be ignored and
must be taken into consideration during the design. At mm-wave frequencies, the
device size and load impedance must be chosen together based on the optimal
105
eciency for a given supply voltage, input drive, and output power requirement.
While the output power requirement is determined by the application, the supply
voltage is typically determined by the breakdown voltage limitations of the process.
3.1.3 Operating Beyond BV
CEO
Architecture or circuit innovations that increase the allowed power amplier supply
voltage without violating the technology breakdown limitations drastically increase
the output power and improves the amplier eciency. Increasing the supply volt-
age improves the class-E PA eciency by increasing the maximum collector voltage
swing with respect to the device \knee-voltage" and increasing the switch-mode am-
plier gain
4
, and by decreasing the impedance transformation ratio, which in turn
reduces the passive loss, for a given output power.
A circuit method of increasing the breakdown voltage in the forward active
region of bipolar devices is by terminating the base with a small resistance [44],
[45], [49], [50], [71], [82]. The maximum collector-emitter breakdown voltage for an
open base (BV
CE0
) is the standard method of determining the voltage limits for a
bipolar technology. However, if the base is terminated with a nite impedance, then
the breakdown voltage of the device can be signicantly increased. The voltage
increase is a function of base resistance and current density. The new resistive
loaded breakdown voltage (BV
CER
) can be 3-4 times BV
CE0
. Figure 3.15 plots the
4
The gain of a class-E amplier is dependent on V
cc
and R
L
106
Figure 3.15: IBM8HP current Density vs collector-emitter voltage and base termi-
nation. Courtesy of IBM.
maximum current density versus base resistance and collector-emitter voltage for
IBM8HP[80].
The BV
CER
of a silicon HBTs can be up to 6 times more than the breakdown
voltage of a CMOS device with comparable frequency response. The breakdown
voltage of an HBT is directly related to the current density in the device [24], and
the avalanche breakdown process, which, as discussed above, can be manipulated.
The breakdown in MOSFETs is due to the hot carrier eect, which is mostly
dependent on the electric eld across a \pinched-o" region [81]. The ability to
manipulate the breakdown limits of an HBT device is an advantage that a bipolar
power amplier has over a CMOS counterpart, which is not captured in Figure
1.8. The breakdown mechanism behavior for an HBT also favors switchmode PA
implementation. The maximum breakdown voltage of an HBT is achieved for low
107
Figure 3.16: Waveforms of a 45 GHz Class-E PA with a 1.5 V supply and 12.5

load.
current densities [16], [38]. This complements class-E operation, which is designed
to minimize voltage-current overlap through the device for eciency purposes.
The waveforms of a 45 GHz class-E amplier simulated using a high f
t
0.13m
HBT and ideal passives are shown in Figure 3.16. The waveform dier considerably
from the waveforms presented in Figure 3.1. The collector, or switch current, is
sinusoidal because it is impossible to separate switch current, I
switch
, from the C
1
current because C
1
is realized with the eective output capacitance of the device.
However, the collector voltage waveform prole is a little bit larger than half of the
duty cycle, which suggest that the eective class-E capacitance, C
1
, is too big [77],
but, as described in Section 3.1.2, this could be purposely conceived as the result
of a calculated tradeo. The discussion in Section 3.1.2 yielded the most ecient
device size and load resistance for a specied output power, but it neglected the
device breakdown limitations.
108
The load-line of a nonideal amplier must be compared to the breakdown lim-
itations in order to ensure the design is reliable. Figure 3.17 plots the BV
CER
of
a high f
t
f
t
0.13m HBT versus the base-emitter voltage, V
be
, for various base
resistance terminations, RB. The area under each base resistance curve represents
the HBT safe operating area (SOA). Nonideal amplier loadlines for a class-E am-
plier operating at 45 GHz with dierent supply voltages (1.5 and 3 V) using a
12.5
load are superimposed onto the graph. The loadlines plot the instantaneous
collector and base voltages through one complete switching cycle.
The loadlines featured in Figure 3.17 dier from the loadline presented in Figure
3.3 due to the loss associated with nite-Q passives and the phase-shift (or delay)
between the base and collector voltages due to operating at mm-wave frequencies
and the input time constant associated with the large power amplier device. As
shown, the device with the 1.5 V supply has a loadline which operates completely in
the safe area of operation. While the PA with the 3 V supply has a loadline which
falls outside the SOA during the \o"-to-\on" switching transition, and therefore
has a reliability issue. The design needs to be modied in order to completely
operate in the SOA. Figure 3.17 suggests there is too much input-output voltage lag,
since the violation of the SOA occurred during the switching transition. Therefore, a
new device size, supply voltage and/or load combination are required for operational
reliability if the loadline falls outside the SOA.
109
Figure 3.17: The BV
CER
versus V
be
performance of a high f
t
0.130m HBT. The
loadlines of Class-E PA with a supply voltage of 1.5 V and 3 V are superimposed.
3.2 Stacked Nonlinear Switching Class-E PA
One way of using a larger supply voltage is by stacking devices in a series cas-
code type conguration. Stacking devices in series allows the output voltage to be
shared between two or more devices, thus allowing for a larger supply voltage. The
eectiveness of the topology is judged by how eciently the supply voltage can
be increased. There are two distinct device stacking techniques for linear power
ampliers.
The rst method ties the base (or gate) of the top device(s) of the linear PA to
a xed AC ground (bias voltage), which mimics a cascode. The top device(s) are
implemented with a lower-f
t
higher-breakdown device oered in the process, which
are usually reserved for slow digital I/O [19], [48]. In a cascode conguration, the
higher breakdown voltage devices are used because the majority of output voltage
110
swing is forced across the upper device and its RF performance is not as critical
as the bottom device. This allows a larger supply voltage to be used and therefore
can increase the eciency of the PA even with the added series loss of the stacked
devices. The increase in output power and eciency are attributed to the lower
impedance transformation ratio required to achieve a given output power.
The second linear PA stacking method is the same as the rst, but the base
(or gate) of the top device(s) are terminated to a specic impedance which allows
the base of the upper transistor(s) to swing dynamically during PA operation[34],
[54], [57], [61], [79]. This method also increases the supply voltage by sharing the
voltage swing between the devices, but it uses either feedback or feed-forward along
with the nite base impedance to equally distribute the output voltage across the
stacked devices. This eliminates the high breakdown device requirement for the top
device.
This section explores the use of stacking transistors in millimeter-wave switch-
mode PAs with a specic impedance at the base of each transistor. The novelty of
the work presented here will expand stacked transistor topologies by allowing each
upper device to have a independent input drive, as opposed to relying on feedback
or feed-forward to drive the transistors. Specically, stacking multiple devices in
series and switching each of them in a manner that forces the output swing to be
equally distributed between the devices allows a larger supply voltage to be used
eciently. This will increase the achievable output power and drain eciency by
111
reducing the amount of loss associated with output passive networks by lowering
the required impedance transformation ratio for a given output power.
3.2.1 Multi-Input Multi-Stacked Switching PAs
A simplied schematic of a 45 GHz two stacked (n=2, where n is the number of
stacked devices) multi-input class-E amplier is shown in Figure 3.18. As shown,
the devices are modeled as switches with realistic parasitic capacitance and on-
resistance. The simulation results in Figure 3.18 are generated assuming ideal
passives (Q=30k) and identical input drives for both devices. Ideally, the middle
node (V
mid
) should be equal to half the output voltage (V
collector
) in order to equally
distribute the total output voltage equally across each device. If each device is
simply modeled as a resistor, then the equivalent circuit in both the \on" and "o
modes would be a simple voltage divider. If the devices are equal in size, then the
output voltage would be equally distributed across each transistor at all times.
However, the parasitic capacitance, which is signicant at mm-wave frequencies,
associated with the devices prevents the middle node from tracking with the output.
The simulation results in Figure 3.18 demonstrates that the middle node fails to
properly track the output even if the capacitance is resonated with an inductor. The
time constant associated with a high-Q resonator prevents the equal distribution
of voltage across each device.
112
Figure 3.18: A schematic of a stacked class-E amplier with a mid mode resonator
and the associated simulated waveforms.
To alleviate this limitation, the input drive of the devices can be modied in
order to force the devices to switch in a manner that results in the equal distribution
of the output voltage among the stacked devices. A \domino-switching" stacked
driving methodology is illustrated in Figures 3.19(a)-(d) for a two-device (n=2)
example. The middle node between the devices is loaded with a class-D
1
load
(parallel LC resonator). The rst mode of operation is when both devices are
switched on as shown in Figure 3.19(b). At this point, the devices can both be
modeled as two low impedance resistors. The input of the class-E load network
and the mid node class-D
1
are eectually shorted to ground and the operation is
identical to a single device class-E amplier.
113
Figure 3.19: A unique method of switching a stacked (n=2) multi-port class-E
power amplier.
114
Next, the bottom device is turned \o" causing the current to
ow into the D
1
load for a nite time (Figure 3.19(c)). If the \o" resistance of the bottom device is
sucient, then the injected current forces a class-D
1
operation at the middle node.
Finally, the top device is turned o causing all the current from L
1
to
ow into the
class-E load (Figure 3.19(d)). The output voltage characteristics (V
collector
) are
determined by class-E load and closely resemble normal class-E operation , while
the middle node voltage is determined by the D
1
load and the additional on-time
of the top transistor. The process is repeated in the reverse order (top most device
switches on rst) to turn the devices back on. Assuming ideal passives, the exact
timing of the domino switching shown in Figures 3.19(b)-(d) equally distributes the
mid node voltage across both devices.
Another advantage to having multiple independent input controls to achieve
domino switching is that the architecture is fully scalable. A multi-input stacked
PA core increases the achievable scaling eciency of stacked switched mode PA
at mm-wave frequencies beyond what can be achieved through feedback, which is
plagued by large device parasitics that are coupled with the feedback network[28].
Also, the switching delay of the devices, even for the most state-of-the-art silicon
technologies, are signicant at mm-wave frequencies. Any time constants associated
with nite device switching or inter-device connection parasitics can be compen-
sated by manipulating the switching time of each device through an additional
phase-shift between the independent inputs. This delay propagation through the
115
Figure 3.20: Simulated results of a proposed n=2 and n=4 stacked multi-port class-
E power amplier architecture.
devices is the sole limiting factor for the scalability with using nite base impedance
termination with feedback or feed-forward [15]. The collector waveforms of a two-
stacked (n=2) and a 4 stacked (n=4) multiple-input stacked switchmode power
ampliers are shown in Figure 3.20. The simulated results show the output voltage
can be equally distributed across each device with the proper input drive for each
transistor. In addition, the simulation results demonstrate that equal distribution
of the output voltage between all the stacked transistors can be achieved using
dierent drive waveforms that follow the basic \domino-switching" methodology.
The simulation result for the n=2 example was generated using square waves
with dierent duty cycles, while the n=4 results were archived using four sinusoid
116
signals with dierent DC oset. A practical trade-o exists due to the voltage-
current overlap across any stacked devices during the domino-switching process.
Any nite device \on" resistance will result in additional power loss as the number
of stacked devices is increased. Figure 3.21 plots the theoretical output power and
drain eciency versus the number of stacked devices. Ideally the output power
is increases by n
2
while the additional loss increase linearly with the addition of
each stacked device. Assuming the sole source of loss is r
on
, the penalty for adding
stacked transistors is roughly 3 % per device for the example shown in Figure
3.21
5
. The gure also compares the overall eciency of stacking devices versus
impedance transformation (Q=30) for comparable output powers. It can be see
that the additional loss due to stacking device is much less than the loss associated
with an impedance transformation.
The n = 4 example in Figure 3.20 was achieved by using dierent DC osets
for the input drive voltages to achieve the equal distribution of the output voltage
across each transistor. However, the realization of a multiple input stacked archi-
tecture with HBTs does not allow for a
exible range of DC voltages at the input.
In addition, the bottom transistor (sometimes referred to as the \master") sets
the bias point for all the upper transistors (sometimes referred to as the \slaves")
and, as discussed in Section 3.1.2, the DC bias point directly aects the conduction
angle of the class-E amplier. Therefore, to add an extra degree of design freedom,
the mid node voltage for implemented designs is mainly controlled by a phase shift
5
This assumes a device on-resistance that is featured in Figure 3.2
117
Figure 3.21: The theoretical output power and drain eciency vs. the number of
stacked devices and the comparison of stacked drain eciency compared to a single
device with impedance transformation for comparable output powers.
between the the upper and lower transistors. The dierential equation governing
the collector voltage, V
c
(!t), of a class-E amplier is found to be
!
2
C
1
L
1
d
2
V
c
(!t)
d!t
+V
c
(!t) =V
cc
(1 +pcos(!t +)); (3.9)
while the dierential equation governing the mid node voltage, V
m
(!t), is
!
2
C
1
L
1

1 +
C
m
C
1

d
2
V
m
(!t)
d!t
+

1 +
L
1
L
m

V
mid
(!t) =V
cc
(1 +pcos(!t +)): (3.10)
The mid-node inductor, L
m
, and capacitor, C
m
, must be sized accordingly in
order to minimize the loading of the mid-node on the class-E network at the output.
Equations 3.9 and 3.10 suggest that the design criteria of C
1
C
m
and L
m
L
1
118
Figure 3.22: The maximum mid-node voltage to maximum collector voltage ratio
vs. phase-shift for a n = 2 PA.
will minimize the mid-node loading on the class-E load dynamics at the collector.
Using the collector and mid-node voltage from Equations 3.9 and 3.10, the phase
shift between the input signal can be found in order to equally distribute the output
voltage across both transistors. Assuming ideal switches and a passive Q = 30,
Figure 3.22 plots the mid-node voltage versus the phase-shift between the upper
and lower transistor inputs. The phase shift between the inputs results in the
upper transistor staying on longer than the bottom transistor. The magnitude of
the mid-node voltage is directly dependent on the amount of extra time the top
transistor stays \on". The goal is to set the phase shift so that V
m
=
1
2
V
c
in order
to equally distribute the output voltage across both transistors in a n = 2 stacked
conguration.
119
Figure 3.23: A schematic diagram and associated waveforms of a 23 dBm Q-band
Class-E PA.
3.3 A 23 dBm Stacked Q-Band Class-E PA
The methodology presented in the previous section resulted in a prototype 2-device
(n=2) stacked multi-input Q-Band (45 GHz) class-E Power amplier, which was
fabricated in 0.13m BiCMOS HBT technology. The schematic diagram is shown in
Figure 3.23. The load of the amplier is class-E, while the mid-node voltage, V
mid
,
follows Class-D
1
operation. The parasitic capacitance at the mid-node requires
a 35 pH inductor to realized a Class-D
1
resonator. The loss associated with the
mid-node slab inductor and the DC blocking cap (20 pF) limits the maximum mid-
node voltage to 4V. The maximum collector-emitter voltage, V
CE
, of each device
is required to be under the base-terminated collector-emitter breakdown voltage;
BV
CER
=6V. Therefore the maximum voltage swing at the collector of the top
device, V
c
, is limited to 10V; as opposed to the 12 V goal.
120
The prototype uses the domino-switching method discussed in Section 3.2.1 to
distribute the voltage swing across both devices. The devices were sized according
to the guidelines outlined in Section 3.1. The PA incorporates coplanar waveguide
structures for all signal routing and passive inductance requirements. The devices
are biased with quarter-wavelength lines (=4), which also act as a low impedance
base termination to increase the device BV
CER
. The =4 lines yield an open cir-
cuit at the operating frequency, while providing a low-frequency short-circuit base
termination, increasing BV
CER
to 6 V. A series lter, 35 pH inductor and 350fF
capacitor, is connected in parallel with a 450
resistor to form a low-frequency
base-ballast for both inputs. Due to the switching nature of a class-E PA, a low fre-
quency instability at the half-harmonic of operation can occur due to a parametric
eect from the device input capacitance. Together, the base-ballast and =4 bias
lines provide proper termination for low-frequency and half-harmonic stability.
A micro-photograph and layout inspired block diagram are shown in Figure
3.24. All signal routing lines and required passive inductances are implemented as
coplanar waveguides. All passives and device connections where electromagnetically
(EM) veried using IE3D or Momentum. An example of modeling the parasitics
associated with connecting the devices to other devices and passives is shown in
Figure 3.25. Each S-parameter EM simulator result was tted to an equivalent
lumped model to assist with transient simulation convergence. While the IBM
\RF" model is relied on for active device modeling, each device was parasitic RC
121
Figure 3.24: A microphotograph and block diagram of the fabricated a 23 dBm
Q-band Class-E PA.
extracted to the last thin metal connection (M4 for IBM8HP) and the upper metals
and via (M5-AM for IBM8HP) parasitics captured using the EM simulator as shown
in Figure 3.25. A complete mm-wave parasitic aware lumped element model is the
result of combining these techniques, an example of which is also shown in Figure
3.25.
All capacitors, inductors and waveguides where modeled with Mentor's IE3D.
All mm-wave capacitance values where limited to under 375 fF due to the self-
resonant frequency of the available Metal-Insulator-Metal (MIM) capacitors (Figure
3.26). The mid-node, L
m
, and collector, L
c
, inductors are realized as a set of two
passive networks, as shown in Figure 3.24. This reduces the current crowding and
122
Figure 3.25: A mm-wave parasitic modeling of device connection parasitics using
Momentum.
123
Figure 3.26: A mm-wave modeling Metal-Insulator-Metal (MIM) capacitors using
Mentor's IE3D.
asymmetry that would be associated with a single passive network connection to
the large active device layout footprint, which results from four parallel connected
HBTs, each with an emitter length of 18m.
3.3.1 Measurement Results
The chip measurements were preformed with a probed chip-on-board setup. The
output power, collector eciency and PAE versus input power at 45 GHz are shown
in Figure 3.27. At 45 GHz, the chip produces 22.8 dBm of output power with a
collector eciency of 33.1 %. The gain of the structure is 5.5 dB which yields a
PAE of 24.4 %. The saturated output power versus frequency is plotted in Figure
3.28. The measurement data re
ects the usable bandwidth of the amplier, which
is determined by the Q of the mid-node class-D
1
resonator. While the amplier
demonstrates a much higher small-signal bandwidth, featured in Figure 3.29, the
Q of the class-D
1
resonator determines the bandwidth for which the maximum
124
Figure 3.27: Measured P
out
,
c
, and PAE vs. P
in
for a 23 dBm Q-band Class-E
PA
output voltage is equally distributed across each device. Any deviation from this
bandwidth during large-signal operation will result in damage to one or more of
the devices.
S-Parameter measurements, Figure 3.29, were done to verify the EM modeling.
In order to measure a positive S
21
, the devices were biased in class-A, the supply
was lowered to 2.5 V, and input number two was terminated with 50
. The S-
parameters show a slight down shift in frequency, which was found to be associated
with the IBM pad models. The error associated with the modeling of the RF pads
and the lower than expected Q of the mid-node passives are the primary cause for
the deviation between measurement and simulation.
The sensitivity to the top input phase shift is plotted in Figure 3.30. As demon-
strated by the measurement, the phase shift between the upper and lower input
125
Figure 3.28: Measured P
sat
,
c
, and PAE vs. frequency
Figure 3.29: S
11
and S
21
for the Q-band class-E PA when biased class-A.
126
Figure 3.30: Measured P
out
, and
c
, vs. phase-shift
drive is critical for power amplier operation. Figure 3.30 also demonstrates an
adequate window of operation which reduces the topology's sensitivity to process
uncertainty.
A summary of the 23 dBm Q-band class-E prototype performance and a compar-
ison with other Q-band HBT class-E ampliers is found in Table 3.1. The measured
output power and collector eciency performance is competitive with previously
published results and suggest that a watt-level digital polar architecture can be
achieved using a stacked multi-input class-E PA. The prototype chip was designed
to have a 50
input impedance at each input to facilitate measurement. In theory,
the PAE of the single-stage amplier can be enhanced by designing the upper tran-
sistor with a higher input impedance. The ability to integrate a multi-input PA
within a multi core DPT is facilitated by the ability to implement multi-winding
127
Table 3.1: Performance Summary
Freq. Stacked Amplier Combined Pout
c
PAE A
P
Area Ref
(GHz) Devices (n) Stages PAs (dBm) (%) (%) (dB) (mm
2
)
35 2 2 8 27.2 - 10.7 19.4 4.16 [11]
47 2 1 1 17.6 42.2 34.6 13 - [12]
47.5 4 1 1 20.3 23 19.4 12.8 - [12]
47 2 1 1 17.9 33.8 17.9 9.8 0.48 [13]
47.5 2 1 2 19.1 24.5 16 8.2 0.64 [13]
41 1 2 1 18.1 49.8 36 5.6 0.74 [28]
45 1 2 1 20.2 34.5 31.5 10.5 1.26 [28]
45 1 2 2 22.4 26.5 23 9.3 2.4 [28]
41 2 2 1 23.4 36 34.9 14.5 1.02 [28]
44 3 2 1 22.2 21 20.8 15.4 1.02 [28]
45 2 1 1 22.8 30.9 22.2 5.5 1.09 This work
45 2 1 1 22.3 34.2 24.7 5.55 1.09 This work
transformers on silicon at mm-wave frequencies at practically no additional foot-
print than what it takes to match each input to 50
.
Chakrabarti-12B
3.3.2 Measurement Results Discussion
The measured performance of the stacked class-E amplier featured in Figure 3.27
suggests the amplier has not been driven to reach the saturated output power, as
seen when compared to the simulation curves. The output power data featured in
Figure 3.27 is the maximum that can be obtained without breaking the amplier.
The performance is limited by the achievable mid-node voltage swing, which in turn
limits the distribution of the output voltage swing across the devices. This limited
voltage is the direct result of a lower than expect passive Q at the mid-node. The
128
DC blocking caps limited the Q of the mid-node slab inductor due to the more than
anticipated capacitor loss.
If the stacked-E design, presented in this section, is modied properly, then the
mid-node voltage can be increased using harmonic manipulation techniques that
have been implemented in the load of power ampliers that are voltage-limited[23].
A solution is shown in Figure 3.31. The dierential nature of the design eliminates
the lossy DC blocking capacitor. In addition, the new slab inductor, L
m2
, located
in the common-mode of the mid-node is used to align the rst and second harmonic
of the mid-node voltage. The coherent addition of these harmonics allows the mid-
node voltage to increase further. This simple proposed topology modication to
the multiple-input stacked-class-E amplier eliminates the low-Q mid-node passives
and allows the mid-node voltage to increase beyond 4V while equally distributing
the output voltage across the device.
The same harmonic manipulation technique may be implemented at the out-
put. By removing the impedance transformation network, usually associated with
generating large power from voltage limited devices, the 50
load is placed di-
rectly in series with the class-E series lter. The 50
load lowers the eective Q of
the series lter and erodes a very fundamental class-E assumption that the current
through the load is a single frequency sine-wave, as shown in A.19. Therefore, a
design with a limited-Q output series lter is \class-E like" in nature, but violates
129
Figure 3.31: Measured P
sat
,
c
, and PAE vs. frequency
a very fundamental class-E assumption. This limitation introduces additional fre-
quency harmonics at the load. By properly designing the load at specic harmonics,
the class-E output voltage may surpass the 2.5 times supply limit that has been
experimentally demonstrated.
3.4 Summary
Deep submicron silicon technologies must truly harness the power of large-scale
integration in order to compete with III-V technologies in watt level millimeter-wave
power amplier performance. The innovated contributions of this section leveraged
the integration advantage of silicon to realize switchmode power ampliers that are
suitable for integration into a digital polar transmitter.
130
Chapter 4
Future Work
4.1 Conclusions
In order to nd commercial acceptance, silicon technologies must truly harness
the power of large-scale integration in order to compete with III-V technologies in
watt-level millimeter-wave power amplier performance. The innovative research
contributions at USC presented in this thesis leveraged the integration advantage
of silicon to realize UWB and millimeter wave power ampliers. The prototype
UWB PA presented in Chapter 2 was tailored to meet the demands of ultra wide-
band imaging systems. The millimeter switched-mode power amplier presented in
Chapter 3 is suitable for integration into a Q-band digital polar transmitter.
131
4.2 Future Work: Watt Level Silicon PAs
The realization of watt-level UWB and mm-wave silicon power ampliers are re-
quired in order for completely integrated silicon transmitters to be more competitive
with system on a chip (SOC) solutions that feature III-V technologies. It is only
then that completely integrated silicon transmitters can be deployed in the vast
majority of UWB and mm-wave commercial applications.
4.2.1 Watt-Level UWB PA
The concepts demonstrated in Chapter 2 are derived mostly from an RFIC ap-
proach. With the aggressive scaling of CMOS devices, successful solutions for
future products will also need to be scalable. The techniques utilized in Chap-
ter 2 rely mostly on on-chip passives, which do not scale with technology. Future
commercially successful UWB PA solutions will be mostly digital with high power
eciency due to the complete system-on-a-chip solution required for future wire-
less integrated systems. Section 2.5 presented a 1-bit UWB pulse generator and
transmitter. The power and footprint savings realized by this design highlights the
power of deep submicron silicon technologies. Future silicon UWB PA transmitters
should more resemble a digital-to-analog converter (DAC) or digital polar transmit-
ter (DPT) than traditional class-A or Class-AB ampliers. While the 1-bit UWB
pulse generator and transmitter was sucient for human heart beat detection, a
132
multi-bit amplitude resolution UWB PA may be required for more high delity
imaging [21].
4.2.1.1 A 30 dBm UWB Silicon Power Amplier
A watt-level version of the 20 dBm CMOS UWB power amplier presented in Sec-
tion 2.4 can be fabricated in 0.13 m BiCMOS technology. A novel monolithic
transmission line transformer power combining scheme is proposed, which com-
bines 4 tapered CMOS distributed amplier cores that are identical to the previous
design using the techniques discussed in Section 2.3. A monolithic 4:1 UWB power
combining scheme using 1:4 dierential Guanella transmission line transformers is
proposed here that combines 4 tapered distributed amplier power ampliers to
achieve UWB watt level performance. In addition to the power combining, the
preamps, input distribution scheme and the impedance transformation ratios are
the only signicant modications from the 20 dBm design. The design of each
individual PA core is essentially unchanged from the design presented in Section
2.4 . A block diagram of the entire system is shown below in Figure 4.1.
As designed, each PA core uses a dierential 1:4 Guanella TLTs to simulta-
neously achieve impedance transformation and power combining through voltage
\boot strapping". The dierential TLTs are connected in series with each other
and achieve coherent voltage combining. If the voltage swing at the output of each
PA is V
o;PA
, then the output swing at the output of each dierential 1:4 TLT is
133
Figure 4.1: A block diagram of a 30dBm UWB PA
V
o;TLT
= 4V
o;PA
. Power combining 4 ampliers quadruples the voltage gain, so
the voltage swing at the load is V
o;RL
= 4V
o;TLT
= 16V
o;PA
. Therefore the hy-
brid impedance-transforming power-comining passive network produces a voltage
swing that is 16 times what is produced at the output of each individual core.
This type of passive network design is very amenable to IC fabrication because the
voltages are multiples and the currents are divided, thus mitigating any potential
electromigration problems associated with the IC metal process.
In addition to the novel output power combining passive network, the input
distribution scheme will present an additional challenge compared to the 20dBm
version. The watt-level UWB input distribution scheme has to provide an equally
delayed input signal to each PA core and allow for the input biasing of each PA
core. To facilitate multiple class operation (class-A, -AB, -B, or -C), the biasing
scheme will need
exibility.
134
4.2.1.2 Simulation Results
The simulated frequency performance of the 1W power amplier is presented in
Figures 4.2. The power amplier delivers a simulated maximum linear output
power of 26 dBm over a bandwidth from 3.5-5 GHz and yields a PAE of 5 % during
linear class-A operation (Pin=-6dBm) from a 1.5V supply. The maximum Class-A
saturated (Pin=4 dBm) output power is 30 dBm with a PAE of 19% while providing
very similar bandwidth performance. The output power versus input power for a 4
and 5 GHz continuous wave source is shown in Figure 4.3. The -3 dB bandwidth,
BW
3dB
, of the PA is from 2.5 to 6GHz. The PA is projected to occupy16 mm
2
of silicon area and consume 4.3 A of current from a 1.5 V supply during linear
class-A operation. A performance summary of the watt-level PA is located below
in Table 4.1. A prototype PA was fabricated in a 0.13m SiGe technology and the
microphotograph is shown in Figure 4.1. Unfortunately due to quasi-dierential
nature of the PA, it suered from a common-mode low frequency instability.
4.2.2 Watt-Level mm-Wave Switchmode PA
4.2.2.1 A 36 dBm Stacked Q-Band Class-E PA
A fully integrated watt-level Q-band silicon power amplier (PA) suitable for imple-
mentation in digital polar transmitters (DPT) requires at least a 0.13m BiCMOS
technology. The design leverages the unequaled integration ability of CMOS along
135
Figure 4.2: Simulated output power versus frequency for linear (@ -1dB) and sat-
urated operation.
Figure 4.3: The simulated output power versus input power for 4 and 5 GHz.
136
Table 4.1: A 30 dBm UWB PA Simulated Performance Summary
PA Operation Class-A
Linear -1 dB Bandwidth 3.5-5.5 GHz
Linear -3 dB Bandwidth 2.5-6.0 GHz
Max Linear Output Power (@ -1 dB) 25 dBm @ 4.5 GHz
Max Linear Power Gain (@ -1 dB) 33 dB
Max Linear PAE (@ -1 dB) 5 %
DC Current Consumption 4.3 A (@1.5V)
Saturated -1 dB Bandwidth 3.0-5.0 GHz
Saturated -3 dB Bandwidth 2.0-6.5 GHz
Max Saturated Output Power 30 dBm @ 4.5 GHz
Max Saturated Power Gain 25 dB
Max Saturated PAE 19 %
Chip Area 4.0 mm X 4.0 mm
Technology 0.13m CMOS
with the favorable unity gain frequency (f
t
>200 GHz) and collector-emitter break-
down voltage (BV
CEO
= 1.8 V) performance of a 0.13m SiGe HBTs to achieve a
fully-integrated watt-level Q-band power amplier in silicon.
A top-level block diagram of the proposed PA is shown in Figure 4.4. The ar-
chitecture power combines 8 PA channels using three 2-to-1 Wilkinson structures
congured in a binary tree combining fashion. Wilkinson power combiners were cho-
sen to help suppress erroneous inter-amplier odd-mode oscillations [20],[32],[83].
Each 2-to-1 Wilkinson has a measured eciency of 90 % [29].An identical 8-to-1
Wilkinson structure is used as a complementary power splitter at the input of each
power amplier chain.
Each amplier chain incorporates a PA core, which is preceded by three preamps
(or drivers D
1
, D
2
, D
3
). All the ampliers are dierential, so the implementation
137
Figure 4.4: Block diagram and microphotograph of a watt-level silicon class-E PA.
of on-chip balun transformers are used to convert the signal from singled-ended to
dierential, and vice versa. A schematic diagram of the complete mm-wave signal
path, neglecting complete digital control and biasing details, is shown in Figure
4.5. The PA amplier drivers, D
1
and D
2
, are quasi-dierential class-E ampliers,
while the rst driver in the chain, D
3
, is a dierential class-AB amplier.
The PA core implements a capacitive divider feedback (C
1
&C
2
) with nite base
termination to achieve equal distribution of the output voltage swing across each
device. A detailed schematic is shown in Figure 4.6. The choice of using feedback
as opposed to the multiple input technique, as described in Section 3.2.1, was solely
due to the layout footprint and overhead associated with the implementation of a
multiple input PA core in each chain.
The capacitive division ratio is determined by the base swing required to equally
distribute the total output voltage swing across both devices. The device sizing was
138
Figure 4.5: The complete schematic diagram for a single channel used in a watt-level
silicon class-E PA.
139
Figure 4.6: The schematic diagram and simulated waveforms of the quasi-
dierential class-E PA core.
done in accordance to the procedure outlined in Section 3.1. The design is quasi-
dierential, and essentially power combines two singled-ended structures using the
Class-E transformer load. The dierential operation is completely dependent on
the common-mode rejection of the preceding drivers. One side of the transformer
output is terminated to AC ground, so it also provides dierential to single-ended
conversion.
To facilitate the implementation of a 6V power supply, the core implements
avalanche compensation circuitry at the base of the core input transistors. The
compensation circuitry and the 400 pH center-tapped dierential inductor provide
a stable DC bias and low frequency (including the half-harmonic) gain suppression,
thus allowing stable operation with a 6 volt supply and up to 10 V single-ended
swing. Again, the loss associated with the capacitors (C
1
andC
2
) and inter-device
connection prevented the core from reaching the 12 V swing design goal.
140
The result is a two device stacked quasi-dierential class-E PA core that imple-
ments impact ionization compensation circuitry at the base to produce 26.3 dBm
of power from a technology which features a BVCEO of 1.8 V. While the proposed
PA is not implemented in a complete digital polar transmitter architecture, the
design does include the necessary supply modulation switches. As shown in Figure
4.6, the supply modulation switches and the associated level shifting circuitry are
included in the design for fair eciency comparison and are compatible with the
standard 2.5 V digital logic associated with nanometer silicon processes.
Compensation of the reverse base currents is critically important for maintain-
ing a stable DC bias quiescent-point and PA operational stability. The impact
ionization that leads to avalanche breakdown can also cause amplier instability
at the half harmonic due to the HBT nonlinear device input capacitance. A para-
metric oscillation can result when the switching capacitor is combined with the
negative base current, which is an eective negative impedance. Thus in order for
the compensation circuitry to be eective, it must dynamically maintain a constant
base-voltage for large collector swings. A schematic diagram and the simulation re-
sults of a HBT (Q
1
) with resistive biasing is shown in Figure 4.7.
As can be seen, the value of the resistive base termination extends the usable
collector voltage to roughly 3 V; BV
CER
is increased as the value of the resistors
are reduced [50]. In addition, Section 3.3 demonstrated that terminating the base
with a=4 line is also acceptable. It creates a DC short to a low impedance (supply
141
Figure 4.7: The simulated performance of resistive biasing with avalanche break-
down.
bias) and eectively sinks the reverse base current from the device. However, the
implementation of quarter-wavelength lines for every device in the PA cores is
not amenable for high integration, which is a requirement for integrating 8 PA
chains together onto a single chip, and the usable supply voltage for small base
terminations is limited to roughly 3 to 3.5 V.
To increase the usable supply voltage even further, an avalanche compensation
circuitry using feedback was created to dynamically sink the excess base current
from the device. The base compensation circuitry implemented in the PA core
(Figure 4.6) enables voltage swing across each device to reach a maximum BV
CER
=6 V, from a technology which features a device BV
CEO
=1.8 V. The biasing
circuity is designed to sink any negative base current produced by the avalanche
eect in the PA core, thus maximizing the usable BV
CER
.
142
Figure 4.8: The schematic and simulated performance of the avalanche compensa-
tion circuitry.
A schematic diagram of the base compensation circuitry is shown in Figure 4.8.
The compensation circuitry leverages the properties of a Wilson current mirror with
three current mirrors that replicate a reference current (I
REF
), which is generated
by a constant-g
m
biasing circuitry. The rst two reference currents are implemented
using two PMOS current mirrors (M
2
and M
3
), while the third current mirror is
implemented using a Wilson current mirror (Q
5
, Q
6
, and Q
7
). The PMOS current
mirrors (M
2
and M
3
) force the reference current through transistors Q
1
, Q
2
, Q
3
,
and Q
7
. Therefore, the base voltage of the PA core (Q
4
) is set by the reference
current and the voltage loop through the base-emitter junctions of Q
1
, Q
2
, Q
3
,
and Q
4
. In order to successfully compensate for avalanche eects, each device
in the compensation circuitry must not generate any excess carriers from impact
ionization [82]. Therefore, the avalanche compensation circuitry was designed so
that the base-collector voltage of each HBT (Q
1
throughQ
3
) in the voltage loop is
143
Figure 4.9: The schematic and simulated performance of the avalanche compensa-
tion circuitry for a two device stacked PA core.
zero. This prevents any bias changes due to impact ionization by eliminating the
reverse biased junction.
The feedback associated with the Wilson current source is used with transis-
tors Q
3
and Q
7
to compensate for any excess carriers generated in the base of
the PA core (Q
4
). The base compensation circuitry bootstraps the Wilson current
source feedback to dynamically adjust the amount of current pulled from the base
to account for large dynamic collector swings. The simulation of the compensa-
tion circuity implemented in the PA core is also shown in Figure 4.8. While the
performance of the resistive termination is shown in Figure 4.7, the compensation
circuity performance is compared to the performance of the PA when biased using
traditional current mirror techniques[60]. The compensation circuitry maintains a
constant base bias voltage for a collector voltage reaching 6 V.
144
Leveraging the high density potential of SiGe and CMOS devices allows for
the scalable implementation of avalanche compensation circuitry for stacked device
PA cores with minimal layout footprint overhead. The schematic diagram for an
avalanche compensation circuity tailored for a two device (n=2) stacked PA core
is shown in Figure 4.9. The topology is essentially identical to the compensation
circuitry for a single device PA core, shown in Figure 4.8. The only signicant
dierence is the additional Wilson current mirror used for compensating the base
current of the top device. The simulation results shown in Figure 4.9 demonstrates
that the compensation circuitry allows the supply voltage to scale with the number
of stacked devices.
Each PA chain drives a class-E transformer load. The transformer has been
implemented for dierential to single-ended conversion. Since the PA core is a
quasi-dierential design, the justication for using a transformer is only valid if its
ability to power combine meets or surpasses what can be achieved with a Wilkinson
power combiner. One logistical advantage of the transformer is the common-mode
center tap, which is a convenient place for the implementation of very large low loss
supply modulation switches. An elegant implementation solution is to congure
the transformer as a proper class-E load. This would achieve power combining
and reduce the number of required passives, and the associated loss, for class-E
operation.
145
Figure 4.10: The schematic diagram, 3-D EM simulation view, and circuit simula-
tion results of a class-E congured transformer.
A schematic diagram of a singled-ended class-E PA using a transformer load is
shown in Figure 4.10. Using the transformer equivalent T-model shown, a trans-
former can be designed to exactly mimic a class-E load if
L
1
=M =L
p
; (4.1)
L
s
=n
2
L
1
; (4.2)
k =
1
n
; (4.3)
M =k
q
L
p
L
s
(4.4)
146
where n is the number of transformer turns, and L
p
and L
s
are the inductance of
the primary and secondary winding, respectively. For Q-band operation, the class-
E capacitance, C
1
is realized exclusively with device parasitics. The center tapped
transformer can be tailored to exactly replicate a class-E load if the primary is equal
to the required class-E collector inductor (L
1
) and the secondary is equal to the
primary times (1=k)
2
, where k is the transformer coupling coecient. The resulting
secondary inductance can be used to realize the required class-E lter and phase
shifting network, L
fo
and L
x
. An ideal class-E amplier with an EM-simulated
transformer has a simulated eciency of 90 %, Figure 4.10, demonstrating that
the performance is comparable to an integrated Wilkinson power combiner. The
transformer layout footprint (200 x 75 ) is only a fraction of which is required
for a Wilkinson power combiner, therefore making it more preferable in a highly
integrated environment.
The 17 dBm input power required to properly drive the PA core only requires a
single stacked class-E design. Therefore, each of the rst two drivers which precede
the PA core (D1 and D2) are single device quasi-dierential class-E ampliers. The
only dierences between the two drivers are the input matching passive element
values and power supplies used.
Driver D1 drives the PA core, so it must provide 16.5 dBm of output power
to a 40 ohm dierential load. A supply voltage of 2 V is used with the schematic
featured in Figure 4.11 to achieve optimal switching in the PA core. The device
147
Figure 4.11: The schematic diagram of Driver D1 (Class-E) with the simulated
collector voltage and current waveforms.
Figure 4.12: The schematic diagram of Driver D2 (Class-E) with the simulated
collector voltage and current waveforms.
sizes where chosen by the standards outlined in Section 3.1. The PA achieves a 3
V swing at the output, with a conservative biasing of 745 mV from a 2V supply.
Driver D2 drives driver D1, so it must provide 12.5 dBm of output power to a 60
ohm dierential load. A supply voltage of 1.5 V is used with the schematic featured
in Figure 4.12. Once again, the device sizes where chosen by the standards outlined
in Section 3.1. The PA achieves a 2.5 V swing at the output, with a conservative
biasing of 745 mV from a 1.5 V supply. Both drivers D1 and D2 where designed for
a conservative performance. The main goal was to eciently achieve power gain,
148
Figure 4.13: The schematic diagram of Driver D3 (Class-E) with the simulated
collector voltage and current waveforms.
so the overall chip PAE would not suer. As such, the techniques required to push
the breakdown performance of the devices were not warranted.
The driver at the very input of the amplier chain, D3, was designed as a
dierential class-AB PA and is shown in Figure 4.13. The primary design criteria
for D3 was to convert a single ended input to a dierential output. In addition, the
input of each amplier chain requires a constant input impedance for the Wilkinson
power dividers to operate correctly. The amplier must also produce a decent gain
from a fairly low input-signal level, 0 -5 dBm. Therefore, a class-AB amplier was
implemented. The current source that was eliminated in the other quasi-dierential
ampliers is implemented for common-mode suppression. The input of the amplier
is a on-chip balun, which converts the single ended input to each amplier chain to
149
a dierential signal and provides the proper 50
input matching for the Wilkinson
power dividers.
4.2.2.2 Simulation Results
The PA was fabricated in a 0.13m BiCMOS technology that features high f
t
devices with a BVCEO of 1.8 V. The PA uses a 6V supply and occupies an area
of 4 mm x 4.5 mm. The small-signal s-parameter performance is shown in Figure
4.14. The large-signal output power, gain and PAE versus frequency is shown in
Figure 4.15. The PA demonstrates a minus 1 dB bandwidth of 3GHz. While
the PA is not operated as a digital polar transmitter, all results include the loss
associated with the switches from a supply modulation architecture. A table that
summarize the simulated PA performance is found in Table 4.2. A prototype PA
was fabricated in a 0.13m SiGe technology and the microphotograph is shown in
Figure 4.4. Unfortunately the drivers, D1-D3, were not implemented with half-
harmonic suppression at the inputs. The overall chip suered from instability in
the drivers.
150
Figure 4.14: The simulated S-parameter measurements of a Q-band watt-level class-
E PA.
Figure 4.15: Simualted output power, collector eciency, and PAE versus input
power of a Q-band watt-level class-E PA.
Table 4.2: Simulated performance summary of a watt-level Q-band class-E PA
PA Operation Class-E
PA Operating Frequency 45 GHz
Output Power 35.03 dBm
Power Gain 31.69 dB
Collector Eciency
c
19 %
PAE 18.31 %
Chip Area 4 mm x 4.5 mm
Technology 0.13 m BiCMOS HBT
151
Chapter 5
Conclusions
5.1 Conclusions
In order to nd commercial acceptance, silicon technologies must truly harness
the power of large-scale integration in order to compete with III-V technologies in
watt-level millimeter-wave power amplier performance. The innovative research
contributions at USC presented in this thesis leveraged the integration advantage
of silicon to realize UWB and millimeter wave power ampliers. The prototype
UWB PA presented in Chapter 2 was tailored to meet the demands of ultra wide-
band imaging systems. The millimeter switched-mode power amplier presented in
Chapter 3 is suitable for integration into a Q-band digital polar transmitter.
The ongoing research at USC (as well as other institutions such as USCD,
Columbia, Toronto, and Delft) continues the pursuit of a complete system-on-a-chip
152
solutions for advance communication standards. The ability to reliably harness suf-
cient power from silicon, is a key challenge towards the realization of commercially
qualied silicon only solutions.
153
References
[1] Evolved universal terrestrial radio access (E-UTRA); physical channels and
modulation, release 8. 3GPP TS 36.211 v8.7.0, 2009.
[2] IEEE draft standard for local and metropolitan area networks part 16: Air in-
terface for broadband wireless access systems. IEEE P802.16Rev3/D4, Febru-
ary 2012, pages 1{2612, Feb. 2012.
[3] M. Acar, A.J. Annema, and B. Nauta. Generalized design equations for class-
e power ampliers with nite dc feed inductance. In Microwave Conference,
2006. 36th European, pages 1308 {1311, Sept. 2006.
[4] M. Acar, A.J. Annema, and B. Nauta. Analytical design equations for class-e
power ampliers. Circuits and Systems I: Regular Papers, IEEE Transactions
on, 54(12):2706 {2717, Dec. 2007.
[5] M. Acar, A.J. Annema, and B. Nauta. Analytical design equations for class-e
power ampliers with nite dc-feed inductance and switch on-resistance. In
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on,
pages 2818 {2821, May 2007.
[6] R.E. Amaya, J. Aguirre, and C. Plett. Gain bandwidth considerations in
fully integrated distributed ampliers implemented in silicon. In Circuits and
Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium
on, volume 4, pages IV { 273{6 Vol.4, May 2004.
[7] I. Aoki, S.D. Kee, D.B. Rutledge, and A. Hajimiri. Distributed active
transformer-a new power-combining and impedance-transformation technique.
Microwave Theory and Techniques, IEEE Transactions on, 50(1):316 {331,
Jan. 2002.
[8] D. Baranauskas and D. Zelenin. A 0.36w 6b up to 20gs/s dac for uwb wave
formation. In Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of
Technical Papers. IEEE International, pages 2380 {2389, Feb. 2006.
[9] A. Bateman, D.M. Haines, and R.J. Wilkinson. Linear transceiver architec-
tures. In Vehicular Technology Conference, 1988, IEEE 38th, pages 478 {484,
June 1988.
154
[10] G. Baudoin, A. Diet, and M. Villegas. On the links between peak to average
power ratio for conventional rf power ampliers and peak to average duration
ratio for switching mode power ampliers. In General Assembly and Scientic
Symposium, 2011 XXXth URSI, pages 1 {4, Aug. 2011.
[11] R. Bhat, A Chakrabarti, and H. Krishnaswamy. Large-scale power-combining
and linearization in watt-class mmwave cmos power ampliers. In Radio Fre-
quency Integrated Circuits Symposium (RFIC), 2013 IEEE, pages 283{286,
June 2013.
[12] A Chakrabarti and H. Krishnaswamy. High power, high eciency stacked
mmwave class-e-like power ampliers in 45nm soi cmos. In Custom Integrated
Circuits Conference (CICC), 2012 IEEE, pages 1{4, Sept 2012.
[13] A Chakrabarti, J. Sharma, and H. Krishnaswamy. Dual-output stacked class-
ee power ampliers in 45nm soi cmos for q-band applications. In Compound
Semiconductor Integrated Circuit Symposium (CSICS), 2012 IEEE, pages 1{4,
Oct 2012.
[14] A.P. Chandrakasan, F.S. Lee, D.D. Wentzlo, V. Sze, B.P. Ginsburg, P.P.
Mercier, D.C. Daly, and R. Blazquez. Low-power impulse uwb architectures
and circuits. Proceedings of the IEEE, 97(2):332 {352, Feb. 2009.
[15] Jing-Hwa Chen, Sultan R. Helmi, Hossein Pajouhi, Yukeun Sim, and Saeed
Mohammadi. A 1.8ghz stacked power amplier in 45nm cmos soi technology
with substrate-transferred to aln. In Microwave Symposium Digest (MTT),
2012 IEEE MTT-S International, pages 1 {3, June 2012.
[16] Peng Cheng, C.M. Grens, and J.D. Cressler. Reliability of sige hbts for power
ampliers; part ii: Underlying physics and damage modeling. Device and
Materials Reliability, IEEE Transactions on, 9(3):440 {448, Sept. 2009.
[17] T.S.D. Cheung and J.R. Long. A 21-26-ghz sige bipolar power amplier mmic.
Solid-State Circuits, IEEE Journal of, 40(12):2583 { 2597, Dec. 2005.
[18] T.S.D. Cheung and J.R. Long. Shielded passive devices for silicon-based mono-
lithic microwave and millimeter-wave integrated circuits. Solid-State Circuits,
IEEE Journal of, 41(5):1183 { 1200, May 2006.
[19] D. Chowdhury, C.D. Hull, O.B. Degani, P. Goyal, Y. Wang, and A.M. Nikne-
jad. A single-chip highly linear 2.4ghz 30dbm power amplier in 90nm cmos.
In Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC
2009. IEEE International, pages 378 {379,379a, Feb. 2009.
155
[20] D. Chowdhury, P. Reynaert, and A.M. Niknejad. Transformer-coupled power
amplier stability and power back-o analysis. Circuits and Systems II: Ex-
press Briefs, IEEE Transactions on, 55(6):507 {511, June 2008.
[21] Ta-Shun Chu, J. Roderick, SangHyun Chang, T. Mercer, Chenliang Du, and
H. Hashemi. A short-range uwb impulse-radio cmos sensor for human fea-
ture detection. In Solid-State Circuits Conference Digest of Technical Papers
(ISSCC), 2011 IEEE International, pages 294 {296, Feb. 2011.
[22] Kenneth K. Clarke and Donald T. Hess. Communication Circuits: Analysis
and Design. Krieger Pub Co., 1994.
[23] P. Colantonio, F. Giannini, G. Leuzzi, and E. Limiti. Very high eciency
microwave amplier. the harmonic manipulation approach. In Microwaves,
Radar and Wireless Communications. 2000. MIKON-2000. 13th International
Conference on, volume 3, pages 33{46 vol.3, 2000.
[24] J.D. Cressler and G. Niu. Silicon-Germanium Heterojunction Bipolar Tran-
sistors. Artech House, 2003.
[25] S.C. Cripps, P.J. Tasker, A.L. Clarke, J. Lees, and J. Benedikt. On the con-
tinuity of high eciency modes in linear rf power ampliers. Microwave and
Wireless Components Letters, IEEE, 19(10):665 {667, Oct. 2009.
[26] Steve Cripps. Advanced Techniques in Rf Power Amplier Design. Artech
House Print, 2006.
[27] Steve Cripps. RF Power Ampliers for Wireless Communications, Second
Edition. Artech House Microwave Library, 2006.
[28] K. Datta and H. Hashemi. Performance limits, design, and implementation
of mm-wave sige hbe class-e and stacked class-e power ampliers. (accepted)
Solid-State Circuits, IEEE Journal of, 2014.
[29] K. Datta, J. Roderick, and H. Hashemi. A 22.4 dbm two-way wilkinson power-
combined q-band sige class-e power amplier with 23 In Compound Semicon-
ductor Integrated Circuit Symposium (CSICS), 2012 IEEE, pages 1 {4, Oct.
2012.
[30] J. Dawson. Power Amplier Linearization Techniques: An Overview. ISSCC
Workshop on RF Circuits for 2.5G and 3G Wireless Systems, February 2001.
[31] W.H. Doherty. A new high eciency power amplier for modulated waves.
Proceedings of the Institute of Radio Engineers, 24(9):1163 {1182, Sept. 1936.
156
[32] D. Elad, R. Shaulsky, and B. Mezhebovsky. A novel method for even odd
parametric oscillation stability analysis of a microwave power amplier. In
Microwave Symposium Digest, 2006. IEEE MTT-S International, pages 1850
{1854, June 2006.
[33] Gerald Ewing. High-eciency radio-frequency power ampliers. PhD thesis,
Oregon State University, 1964.
[34] A.K. Ezzeddine and H.C. Huang. The high voltage/high power fet (hivp). In
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE, pages
215 { 218, June 2003.
[35] L.M. Frazier. Mdr for law enforcement [motion detector radar]. Potentials,
IEEE, 16(5):23 {26, Jan. 1997.
[36] E.L. Ginzton, W.R. Hewlett, J.H. Jasberg, and J.D. Noe. Distributed ampli-
cation. Proceedings of the IRE, 36(8):956 { 969, Aug. 1948.
[37] Andrei Grebennikov and Nathan Sokal. Switchmode RF Power Ampliers.
Newnes, 2007.
[38] C.M. Grens, Peng Cheng, and J.D. Cressler. Reliability of sige hbts for power
ampliers; part i: Large-signal rf performance and operating limits. Device
and Materials Reliability, IEEE Transactions on, 9(3):431 {439, Sept. 2009.
[39] G. Guanella. New method of impedance matching in radio frequency circuits.
Brown-Broveri Review, 31:327{329, Sept. 1944.
[40] H. Guckel, P.A. Brennan, and I. Palocz. A parallel-plate waveguide approach
to microminiaturized, planar transmission lines for integrated circuits. Mi-
crowave Theory and Techniques, IEEE Transactions on, 15(8):468 {476, Aug
1967.
[41] A. Gutierrez-Aitken, C. Monier, P. Chang, E. Kaneshiro, D. Scott, B. Chan,
M. D'Amore, S. Lin, B. Oyama, K. Sato, A. Cavus, and A. Oki. Advanced
inp hbt technology at northrop grumman aerospace systems. In Compound
Semiconductor Integrated Circuit Symposium, 2009. CISC 2009. Annual IEEE,
pages 1 {4, Oct. 2009.
[42] H. Hashemi, Ta shun Chu, and J. Roderick. Integrated true-time-delay-based
ultra-wideband array processing. Communications Magazine, IEEE, 46(9):162
{172, Sept. 2008.
[43] J. Horn and G. Boeck. Ultra wideband balun for power applications. In
Microwave Conference, 2004. 34th European, volume 1, pages 369 {371, Oct.
2004.
157
[44] A. Inoue, S. Nakatsuka, R. Hattori, and Y. Matsuda. The maximum operating
region in sige hbts for rf power ampliers. In Microwave Symposium Digest,
2002 IEEE MTT-S International, volume 2, pages 1023 {1026, 2002.
[45] J.B. Johnson, A.J. Joseph, D.C. Sheridan, R.M. Maladi, P.-O. Brandt, J. Pers-
son, J. Andersson, A. Bjorneklett, U. Persson, F. Abasi, and L. Tilly. Silicon-
germanium bicmos hbt technology for wireless power amplier applications.
Solid-State Circuits, IEEE Journal of, 39(10):1605 { 1614, Oct. 2004.
[46] Marian K. Kazimierczuk. RF Power Ampliers. Wiley, 2008.
[47] Scott Kee. The Class E/F Family of Harmonic-Tuned Switching Power Am-
pliers. PhD thesis, California Institute of Technology, 2002.
[48] Shouhei Kousai and A. Hajimiri. An octave-range watt-level fully integrated
cmos switching power mixer array for linearization and back-o eciency im-
provement. In Solid-State Circuits Conference - Digest of Technical Papers,
2009. ISSCC 2009. IEEE International, pages 376 {377,377a, Feb. 2009.
[49] J. Kraft, D. Kraft, B. Loer, H. Jauk, and E. Wachmann. Usage of hbts
beyond bvceo. In Bipolar/BiCMOS Circuits and Technology Meeting, 2005.
Proceedings of the, pages 33 { 36, Oct. 2005.
[50] J. Kraft, B. Loer, N. Ribic, and E. Wachmann. Bvcer - increased operating
voltage for sige hbts. In Reliability Physics Symposium Proceedings, 2006. 44th
Annual., IEEE International, pages 507 {511, March 2006.
[51] Herbert L. Krauss, Charles W. Bostian, and Frederick H. Raab. Solid State
Radio Engineering. John Wiley and Sons, 1980.
[52] M. Lazarus. The great spectrum famine. Spectrum, IEEE, 47(10):26 {31,
October 2010.
[53] Thomas H. Lee. Planar Microwave Engineering: A Practical Guide to Theory,
Measurement, and Circuits. Cambridge University Press, 2004.
[54] S. Leuschner, S. Pinarello, U. Hodel, J.-E. Mueller, and H. Klar. A 31-dbm,
high ruggedness power amplier in 65-nm standard cmos with high-eciency
stacked-cascode stages. In Radio Frequency Integrated Circuits Symposium
(RFIC), 2010 IEEE, pages 395 {398, May 2010.
[55] R.D. Lutz, V.K. Tripathi, and A. Weisshaar. Enhanced transmission char-
acteristics of on-chip interconnects with orthogonal gridded shield. Advanced
Packaging, IEEE Transactions on, 24(3):288 {293, Aug. 2001.
[56] Franco Maloberti. Data Converters. Springer, 2007.
158
[57] S. Mandegaran and A. Hajimiri. A breakdown voltage multiplier for high
voltage swing drivers. Solid-State Circuits, IEEE Journal of, 42(2):302 {312,
Feb. 2007.
[58] M.A. Morrill, V.A. Caliskan, and C.Q. Lee. High-frequency planar power
transformers. Power Electronics, IEEE Transactions on, 7(3):607 {613, July
1992.
[59] S. Nakajima. Compound semiconductor ic's. In Indium Phosphide and Related
Materials, 2005. International Conference on, pages 603 {608, May 2005.
[60] Stephen H. Lewis Paul R. Gray, Paul J. Hurst and Robert G. Meyer. Analysis
and Design of Analog Integrated Circuits. Wiley, 2009.
[61] S. Pornpromlikit, Jinho Jeong, C.D. Presti, A. Scuderi, and P.M. Asbeck.
A watt-level stacked-fet linear power amplier in silicon-on-insulator cmos.
Microwave Theory and Techniques, IEEE Transactions on, 58(1):57 {64, Jan.
2010.
[62] David M. Pozar. Microwave Engineering. John Wiley and Sons, 1998.
[63] F.H. Raab. Eciency of doherty rf power-amplier systems. Broadcasting,
IEEE Transactions on, BC-33(3):77 {83, Sept. 1987.
[64] F.H. Raab. Maximum eciency and output of class-f power ampliers. Mi-
crowave Theory and Techniques, IEEE Transactions on, 49(6):1162 {1166,
June 2001.
[65] F.H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothecary,
J.F. Sevic, and N.O. Sokal. Power ampliers and transmitters for rf and mi-
crowave. Microwave Theory and Techniques, IEEE Transactions on, 50(3):814
{826, March 2002.
[66] F.H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothecary,
J.F. Sevic, and N.O. Sokal. Rf and microwave power amplier and transmitter
technologies - part 1. High Frequency Electronics, 2(3):22{36, May 2003.
[67] F.H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothecary,
J.F. Sevic, and N.O. Sokal. Rf and microwave power amplier and transmitter
technologies - part 2. High Frequency Electronics, 2(4):22{36, Aug. 2003.
[68] F.H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothecary,
J.F. Sevic, and N.O. Sokal. Rf and microwave power amplier and transmitter
technologies - part 3. High Frequency Electronics, 2(5):34{48, Sept. 2003.
159
[69] F.H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothecary,
J.F. Sevic, and N.O. Sokal. Rf and microwave power amplier and transmitter
technologies - part 4. High Frequency Electronics, 2(6):38{49, Nov. 2003.
[70] F.H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothecary,
J.F. Sevic, and N.O. Sokal. Rf and microwave power amplier and transmitter
technologies - part 5. High Frequency Electronics, 3(1):46{54, Nov. 2004.
[71] M. Rickelt, H.-M. Rein, and E. Rose. In
uence of impact-ionization-induced
instabilities on the maximum usable output voltage of si-bipolar transistors.
Electron Devices, IEEE Transactions on, 48(4):774 {783, April 2001.
[72] J. Roderick, H. Krishnaswamy, K. Newton, and H. Hashemi. Silicon-
based ultra-wideband beam-forming. Solid-State Circuits, IEEE Journal of,
41(8):1726 {1739, Aug. 2006.
[73] E. Rotholz. Transmission-line transformers. Microwave Theory and Tech-
niques, IEEE Transactions on, 29(4):327 { 331, April 1981.
[74] C.L. Ruthro. Some broad-band transformers. Proceedings of the IRE,
47(8):1337 {1342, Aug. 1959.
[75] A.A.M. Saleh. Planar electrically symmetric n-way hybrid power di-
viders/combiners. Microwave Theory and Techniques, IEEE Transactions on,
28(6):555 { 563, June 1980.
[76] A. Sayag, D. Ritter, and D. Goren. Compact modeling and comparative anal-
ysis of silicon-chip slow-wave transmission lines with slotted bottom metal
ground planes. Microwave Theory and Techniques, IEEE Transactions on,
57(4):840 {847, April 2009.
[77] N.O. Sokal. Class-e high-eciency rf/microwave power ampliers: Principles
of operation, design procedures, and experimental verication. Analog Circuit
Design, pages 269 { 301, 2002.
[78] N.O. Sokal and A.D. Sokal. Class e-a new class of high-eciency tuned
single-ended switching power ampliers. Solid-State Circuits, IEEE Journal
of, 10(3):168 { 176, June 1975.
[79] T. Sowlati and D.M.W. Leenaerts. A 2.4-ghz 0.18- mu;m cmos self-biased
cascode power amplier. Solid-State Circuits, IEEE Journal of, 38(8):1318 {
1324, Aug. 2003.
[80] IBM Systems and Technology Group. 8hp hbt safe operating area, reliability
limits and device self heating. IBM Microelectronics, june 2009.
160
[81] S. M. Sze. Semiconductor Devices, Physics and Technology. Wiley, 1985.
[82] H. Veenstra, G.A.M. Hurkx, D. van Goor, H. Brekelmans, and J.R. Long.
Analyses and design of bias circuits tolerating output voltages above bvceo.
Solid-State Circuits, IEEE Journal of, 40(10):2008 { 2018, Oct. 2005.
[83] R.J. Weber. Even mode versus odd mode stability [microwave networks]. In
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on,
volume 1, pages 607 {610 vol.1, Aug. 1997.
[84] D.D. Wentzlo, R. Blazquez, F.S. Lee, B.P. Ginsburg, J. Powell, and A.P.
Chandrakasan. System design considerations for ultra-wideband communica-
tion. Communications Magazine, IEEE, 43(8):114 { 121, Aug. 2005.
[85] D.D. Wentzlo and A.P. Chandrakasan. A 47pj/pulse 3.1-to-5ghz all-digital
uwb transmitter in 90nm cmos. In Solid-State Circuits Conference, 2007.
ISSCC 2007. Digest of Technical Papers. IEEE International, pages 118 {591,
Feb. 2007.
[86] D.D. Wentzlo and A.P. Chandrakasan. Delay-based bpsk for pulsed-uwb
communication. In Acoustics, Speech and Signal Processing, 2007. ICASSP
2007. IEEE International Conference on, volume 3, pages III{561 {III{564,
April 2007.
[87] E.J. Wilkinson. An n-way hybrid power divider. Microwave Theory and Tech-
niques, IRE Transactions on, 8(1):116 {118, Jan. 1960.
[88] Ingo Wol. Coplanar Microwave Integrated Circuits. Wiley-Interscience, 2006.
[89] Thomas T. Y. Wong. Fundamentals of Distributed Amplication. Artech
House, 1993.
[90] G.T. Zhou and J.S. Kenney. Predicting spectral regrowth of nonlinear power
ampliers. Communications, IEEE Transactions on, 50(5):718 {722, May
2002.
161
Appendix A
Derivations
A.1 Transmission Line Transformer Theory
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
I
1
V
2
I
3
V
4
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5
=
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
g
11
g
12
g
13
g
14
g
21
g
22
g
23
g
24
g
31
g
32
g
33
g
34
g
41
g
42
g
43
g
44
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5

2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
V
1
I
2
V
3
I
4
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5
(A.1)
Figure A.1: The schematic of coupled transmission lines.
162
In order to fully investigate the performance of a n = 2 Guanella TLT, a full
4x4 g-parameter model, Equation A.1, of two lossless coupled lines is derived. A
schematic of two coupled lines is shown in Figure A.1. The current and voltage
along line #1 are dened as
V
Line1
(z) =V
+
e
e
jez
+V

e
e
jez
+V
+
o
e
joz
+V

o
e
joz
; (A.2)
I
Line1
(z) =I
+
e
e
jez
+I

e
e
jez
+I
+
o
e
joz
+I

o
e
joz
; (A.3)
where
e
and
o
are the even- and odd-mode phase constants, respectively. The
amplitude of each voltage and current has a subscript which denote the propagation
mode (e for even and o for odd) and a superscript which denote the wave direction
of travel (\+" denotes a forward traveling wave, while \-" denotes a backwards
traveling wave). The even-mode is dened as the mode of propagation when the
voltage applied to line #1 and #2 are the same (V
+
1e
= V
+
2e
and V

1e
= V

2e
), while
the odd-mode of propagation is dened as when the voltage at port 1 and 3 are 180
degrees out of phase (V
+
1e
=V
+
2e
and V

1e
=V

2e
). Using the conditions for even-
and odd-modes, similar equations for voltage and current along line #2 are found
to be
163
V
Line2
(z) =V
+
e
e
jez
+V

e
e
jez
V
+
o
e
joz
V

o
e
joz
; (A.4)
I
Line2
(z) =I
+
e
e
jez
+I

e
e
jez
I
+
o
e
joz
I

o
e
joz
: (A.5)
Using Equation A.2-A.5, two 4 x 4 matrices that represent the voltage and cur-
rents with respect to the forwards and reverse current amplitudes can be generated
and are
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
V
1
I
2
V
3
I
4
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5
=
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
Z
oe
Z
oo
Z
oe
Z
oo
e
jeL
e
joL
e
jeL
e
joL
Z
oe
Z
oo
Z
oe
Z
oo
e
jeL
e
joL
e
jeL
e
joL
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5

2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
I
+
e
I
+
o
I

e
I

o
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5
(A.6)
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
I
1
V
2
I
3
V
4
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5
=
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
1 1 1 1
Z
oe
e
jeL
Z
oo
e
joL
Z
oe
e
jeL
Z
oo
e
joL
1 1 1 1
Z
oe
e
jeL
Z
oo
e
joL
Z
oe
e
jeL
Z
oo
e
joL
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5

2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
I
+
e
I
+
o
I

e
I

o
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5
(A.7)
164
where Z
oo
and Z
oe
are the odd-mode and even-mode characteristic impedance,
respectively, and L is the length of the lines. Setting I
2
,V
3
, andI
4
equal to zero in
Equation A.6, the the following g-parameters can be solved:
g
11
=j
Z
oo
+Z
oe
2Z
oe
Z
oo
tan() (A.8)
g
21
=sec() (A.9)
g
31
=j
Z
oo
Z
oe
2Z
oe
Z
oo
tan() (A.10)
g
41
= 0 (A.11)
SettingV
1
,V
3
, andI
4
equal to zero in Equation A.6, the following g-parameters
can be solved:
165
g
12
=sec() (A.12)
g
22
=j
Z
oo
+Z
oe
2
tan() (A.13)
g
32
= 0 (A.14)
g
42
=j
Z
oo
Z
oe
2
tan() (A.15)
Columns 3 and 4 of Equation A.1 can be solved for in a similar manner. How-
ever due to the symmetry of the passive coupled transmission lines, the following-
parameter can be solved for by inspection: g
33
=g
11
,g
34
=g
12
,g
43
=g
21
,g
44
=g
22
,
g
31
=g
32
, g
31
=g
14
, g
41
=g
23
, and g
42
=g
24
.
Using the derivations above and the fact that a n = 2 Guanella is simply a
parallel-series connection of two coupled line pairs, the 4x4 g-parameters model of
166
a Guanella TLT is simply the addition of two transmission line 4x4 g-parameter
matrices. Therefore the complete 4x4 g-parameter matrix of a n = 2 Guanella is
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
j
K
1
K
3
tan() 2sec() j
K
2
K
3
tan() 0
2sec() jK
1
tan() 0 jK
2
tan()
j
K
2
K
3
tan() 0 j
K
1
K
3
tan() 2sec()
0 jK
2
tan() 2sec() jK
1
tan()
3
7
7
7
7
7
7
7
7
7
7
7
7
7
5
(A.16)
where K
1
=Z
oo
+Z
oe
, K
2
=Z
oo
Z
oe
, and K
3
=Z
oe
Z
oo
. Most of the derivations
in Chapter 2 assume even-mode suppression (Z
oe
= inf)through the transmission
line transformer. Realistically, this is not possible because the ratio between the
even- and odd-mode impedance is low for silicon processes, which do not possess
ferrite materials. Equation A.16 give a designer the ability to simulate and see the
eect of a nite even-mode impedance on the TLT performance. Once the even to
odd mode impedance ratio has been maximized, then the transmission line length
can be increased to meet the desired low frequency corner.
A.2 Finite Inductance Class-E Theory
A schematic diagram of a nite inductance class-E amplier is shown in Figure A.2.
The amplier has two distinct regions of operation: when the switch is closed and
when the switch is open. The analysis below will start with analyzing each region
167
Figure A.2: A schematic of a nite inductance class-E PA.
separately, then use the boundary conditions between the two states to derive the
nal solution.
When the switch is \on" or closed during the duration 0 !t , then the
switch current, I
switch
(!t), and inductor current, I
L1
(!t) are
I
switch
(!t) =I
L1
(!t) +I
RL
(!t); (A.17)
I
L1
(!t) =
1
!L
Z
!t
0
V
cc
V
c
()d; (A.18)
whereV
c
is the switch voltage and I
RL
(!t) is the load current and is dened as
I
RL
(!t) =I
RL
sin(!t +); (A.19)
168
where is dened as the load current phase shift with respect to the load voltage.
When the switch is closed, the switch voltage is equal to zero (V
c
= 0) and the
inductor current is
I
L1
(!t) =
V
cc
!t
!L
+I
L1
(0) =
V
cc
!t
!L
I
RL
sin(): (A.20)
The boundary condition I
L1
(0) =I
RL
(0) was used to generate Equation A.20.
Using Equations A.17 and A.20, the switch current is found to be
I
switch
(!t) =
8
>
>
>
<
>
>
>
:
Vcc!t
!L
+I
RL
(sin(!t +)sin()) 0!t
0 !t 2
(A.21)
When the switch is \o" or open during the duration !t 2 , then the
capacitor current, I
C1
(!t), is
I
C1
(!t) =
8
>
>
>
<
>
>
>
:
0 0!t
1
!L
R
!t

(V
cc
V ())d +I
L1
() +I
RL
sin(!t +) !t 2
(A.22)
In addition, the class-E amplier must satisfy the zero voltage switching (ZVS)
condition and the currents through the inductor, switch, and load must be con-
tinuous. Therefore at !t = , the boundary conditions V
C
() = 0 and I
L
() =
169
I
switch
()+I
RL
() must be satised. The voltage and current through the capacitor,
C
1
, are related by
I
C1
(!t) =!C
dV
C1
(!t)
d!t
: (A.23)
Using Equations A.22 and A.23, along with the boundary conditions, the voltage
across the switch can be written as a dierential equation and is
V
C
(!t) =
8
>
>
>
<
>
>
>
:
0 0!t
!
2
L
1
C
1
d
2
Vc(!t)
d!t
+V
c
(!t) =V
cc
+!L
1
I
RL
cos(!t +) !t 2
(A.24)
Solving the dierential equation in Equation A.24 using the mentioned bondary
condition yields the following general solution
V
C
(!t) =C
1
cos(X!t) +C
2
sin(X!t) +V
cc

X
2
1X
2
I
RL
!L
1
cos(!t +); (A.25)
where
C
1
=V
cc

X
2
p
1X
2
cos(2X)cos() +
X
2
p
1X
2
sin(2X)sin()cos(2X)
!
(A.26)
170
C
2
=V
cc

X
2
p
1X
2
sin(2X)cos()
X
2
p
1X
2
sin(2X)cos()sin(2X)
!
(A.27)
wherep =
!LI
RL
Vcc
andX =
!
L1C1
!
. X is dened as the ratio of the resonant frequency
of L
1
and C
1
, !
L1C1
=
1
p
L
1
C
1
to the PA switching frequency, !. The DC supply
current,I
DC
, can be solved for by taking the average current through the inductor,
L
1
, and is
I
DC
=
I
RL
2

2
2p
+ 2cos()sin()
!
(A.28)
A class-E amplier is specically designed to eliminate any voltage and current
over lap through the switch using the ZVS condition, therefore it has a theoretical
eciency of 100%. The class-E eciency dictates thatP
out
=
V
2
RL
2R
L
=P
DC
=I
DC
V
cc
.
Therefore the load voltage,V
RL
, and current amplitude,I
RL
, can be solved for and
can be shown to be
V
RL
=
I
RL
R
L
=
V
cc

2
2p
+ 2cos()sin()
!
: (A.29)
171
A nite inductance class-E amplier utilizes a nite inductance value for L
1
as
opposed to a RF choke that is implemented in a classical class-E amplier. The
cost of using a nite value of inductor is a phase shift between the load current
and voltage. A phase shift is required in order to align the current and voltage and
deliver real power to the load. Therefore, the value of X
L
is required. Using the
fact that the voltage drop, V
XL
, across X
L
and voltage drop across the load, V
RL
,
are related by
X
L
R
L
=
V
XL
V
RL
.
Using the analysis above, equations for the output power, P
out
, required phase
shift, , inductance value, L
1
, capacitance value, C
1
, and load reactance, X
L
, can
be solved:
L
1
=

R
L
!
RF

0
@
p

2
2p
+ 2cos()sin()

1
A
(A.30)
C
1
=

1
X
2

0
@

2
2p
+ 2cos()sin()

p
1
A
(A.31)
P
out
=

p
2
2
!
0
@

2
2p
+ 2cos()sin()

p
1
A
2
(A.32)
172
Figure A.3: Finite inductance class-E (a) output power and (b) required load phase
shift versus X.
The value of the load reactance is a function of X. IfX < 1:4142 then the required
reactance is inductive. If X > 1:4142 then a capacitor is required to achieve the
proper phase shift. No additional passive is required if X = 1:4142, since the load
voltage and current are already in phase. The required load inductance, L
XL
, or
capacitance, C
XL
are
X
L
=
8
>
>
>
<
>
>
>
:
L
XL
=
K
XL
R
L
!
X < 1:4142
C
XL
=
1
K
XL
R
L
!
X > 1:4142
(A.33)
Plots of output power, required load phase shift, L
1
inductance value, C
1
ca-
pacitance value, load inductance, and load capacitance versus the tuning frequency
X are shown in Figures A.3 - A.5.
173
Figure A.4: Finite inductance class-E required (a)L
1
value and (b)C
1
value versus
X.
Figure A.5: Finite inductance class-E required load (a) inductance and (b) capaci-
tance versus X.
174
From Figures A.3-A.5, a design with X=1.4142 will be the most ecient for the
lossy on-chip passive associated with a silicon process. The implementation of a
class-E PA with X=1.4142 will maximize the allowedC
1
capacitance and therefore
maximize the allowed device size at mm-wave frequencies. It will also minimize
the inductance value required for L
1
, which minimizes loss for nite-Q passives.
In addition, a \parallel-circuit" class-E PA eliminates the additional passive, and
associated loss, required for the load phase shift.
175

Abstract (if available)

Abstract Multi-functional communication and imaging applications have necessitated the integration of many complex systems onto a single chip. Traditionally, multi-chip modules or systems-in-a-package approaches have been utilized to perform complex functions for state of the art architectures. Nanometer silicon processes have the ability to integrate ƒmax >100 GHz RF devices with CMOS digital devices to achieve completely integrated system-on-a-chip solutions, where the performance rivals traditional III-V solutions. Due to the requirements of advanced wireless systems, a silicon implementation is no longer solely determined by economics. The ability to completely integrate an RF or millimeter-wave integrated circuit with a mixed-signal application specific integrated circuit onto a single die, using nanometer silicon processes, allows the emergence of novel and elegant solutions. This thesis presents silicon-based Ultra WideBand (UWB) and millimeter-wave (mm-wave) Power Amplifier (PA) architectures and implementations for state of the art wireless systems. ❧ Silicon-based power amplifiers rely on impedance transformation networks and power combining to overcome the limited allowed supply voltage, which is governed by the modest breakdown voltages associated with high ƒmax silicon devices. To operate within breakdown limits, an impedance transformation is used to deliver the desired power to the antenna. Traditionally, impedance transformations are implemented with passives as L-, Tee-, or Pi-matching topologies. However, these techniques are typically narrow band solutions. ❧ UWB True-Time-Delay radar architectures require the transmission of pico-second pulses for high resolution imaging. The amplification of UWB pulses requires a power amplifier that has the ability to amplify a time-limited pulse with little amplitude and phase distortion. Wideband amplification has been traditionally accomplished with a Distributed Amplifier (DA) topology. A DA yields flat gain and group delay over very wide bandwidths, yet DAs find little utility as power amplifiers due to the loss associated with the reverse-wave termination found at the output. ❧ This thesis presents two UWB prototype power amplifier suitable for UWB imaging. Both proposed topologies used Transmission-Line Transformers (TLT) to circumvent the narrowband nature of typical impedance transformation and power combining networks. In addition, each PA core is realized with a distributed amplification approach which eliminates the reverse-wave termination using a tapered quasi-distributed line. The result is the realization of a cost effective integrated class-A ultra wideband CMOS power amplifier, which is compatible with existing true-time-delay systems for low GHz high-precision imaging applications. ❧ Alternatively, an UWB pulse can be generated and subsequently transmitted, as opposed to amplified, using a class-A PA. A UWB pulse generator, with class-D output drivers, has been proposed for short range imaging applications. This application specific solution features 12 dBm of maximum output power with tunable center frequency and bandwidth, which covers the UWB spectrum. The UWB transmitter has zero static current consumption, which is ideal for a completely integrated UWB radar. ❧ The last part of this thesis proposes highly-efficient stacked nonlinear mm-wave(Q-band) power amplifier tailored for use in a Digital Polar Transmitter (DPT). The integration ability of silicon allows for the incorporation of linearization techniques with nonlinear highly efficient power amplifier onto a single silicon die. Thereby finding new utility for switching amplifiers which have historically been limited to applications with a constant envelope modulation scheme. ❧ A multiple input drive stacked device class-E power amplifier operating at 45 GHz is presented. Topology techniques that extend the device operation beyond BVCEO and increase the usable supply voltage are proposed. The multiple input drive switches the devices in a manner that equally distributes the output voltage swing across each device, thus allowing the usable supply voltage to be increased by a factor equal to the number of series stacked devices. The result is unprecedented output power and efficiency performance for integrated silicon power amplifiers at 45 GHz.

Linked assets

University of Southern California Dissertations and Theses

Conceptually similar

PDF

High power, highly efficient millimeter-wave switching power amplifiers for watt-level high-speed silicon transmitters

PDF

Architectures and integrated circuits for RF and mm-wave multiple-antenna systems on silicon

PDF

RF and mm-wave blocker-tolerant reconfigurable receiver front-ends

PDF

CMOS mixed-signal charge-metering stimulus amplifier for biomimetic microelectronic systems

PDF

Wideband low phase-noise RF and mm-wave frequency generation

PDF

Silicon-based RF/mm-wave power amplifiers and transmitters for future energy efficient communication systems

PDF

Improving the speed-power-accuracy trade-off in low-power analog circuits by reverse back-body biasing

PDF

Real-time channel sounder designs for millimeter-wave and ultra-wideband communications

PDF

Integrated multi-band and wideband reconfigurable wireless receivers

PDF

Silicon photonics integrated circuits for analog and digital optical signal processing

PDF

Elements of next-generation wireless video systems: millimeter-wave and device-to-device algorithms

PDF

Low-power, dual sampling-rate, shared-architecture ADC for implantable biomedical systems

PDF

Charge-mode analog IC design: a scalable, energy-efficient approach for designing analog circuits in ultra-deep sub-µm all-digital CMOS technologies

PDF

An asynchronous resilient circuit template and automated design flow

PDF

Theory and design of magnetic induction-based wireless underground sensor networks

PDF

Integrated wireless piezoelectric ultrasonic transducer system for biomedical applications

PDF

Demand based techniques to improve the energy efficiency of the execution units and the register file in general purpose graphics processing units

PDF

A logic partitioning framework and implementation optimizations for 3-dimensional integrated circuits

Asset Metadata

Creator Roderick, Jonathan David (author)

Core Title Silicon-based wideband & mm-wave power amplifier architectures and implementations

School Andrew and Erna Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 10/21/2014

Defense Date 09/11/2014

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag CMOS,millimeter wave integrated circuit,OAI-PMH Harvest,power amplifier,SiGe,ultra wideband

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Hashemi, Hossein (committee chair), Gundersen, Martin A. (committee member), Haas, Stephan W. (committee member)

Creator Email jonathan.d.roderick@gmail.com,roderick@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c3-509150

Unique identifier UC11297794

Identifier etd-RoderickJo-3025.pdf (filename),usctheses-c3-509150 (legacy record id)

Legacy Identifier etd-RoderickJo-3025.pdf

Dmrecord 509150

Document Type Dissertation

Format application/pdf (imt)

Rights Roderick, Jonathan David

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA