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Architectures and algorithms of charge management and thermal control for energy storage systems and mobile devices

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Architectures and algorithms of charge management and thermal control for energy storage systems and mobile devices

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Architectures and Algorithms of Charge Management
and Thermal Control for Energy Storage Systems and
Mobile Devices

by

Qing Xie

______________________________________________________________

A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)

December 2014

Copyright 2014 Qing Xie

In the loving memory of my grandmother
Xiuyun Zhu
(1923-2008)

ii

ACKNOWLEDGEMENTS
First and foremost, I give my deepest gratitude to my PhD advisor, Prof. Massoud
Pedram, for being a constant source of guidance, assistance, expertise, and inspiration
during the past five years. Prof. Pedram introduced me to a complete new world. My
major was physics before I met Prof. Pedram, and he offered me an opportunity to work
in his group. I joined his group and it turned out to be one of the wisest decisions I have
ever made. He has taught me, both consciously and unconsciously, how good research is
done throughout my graduate studies. Prof. Pedram guided me through every step to do
meaningful research, even spending time to correct my writings. When I felt ready to
venture into research on my own and branch out into new research topics, Prof. Pedram
gave me the freedom to do whatever I wanted, at the same time continuing to contribute
valuable feedback, advice, and encouragement. His unbounded passion for research and
dedication in making technical contributions has been and will always be an inspiration
to me. In addition, as I started my family during the course of pursing my PhD, I am also
grateful for his understanding and help.
Next, I would like to thank other members of my defense and qualifying exam
committee: Prof. Sandeep Gupta, Prof. Ramesh Govindan, Prof. Murali Annavaram, Prof.
Paul Bogdan, and Prof. Sri R. Narayan, for providing valuable feedback to my research
and pushing me to think deeper. Special thanks to Prof. Gupta for his excellent teaching
in VLSI design course, from which I gained solid knowledge in circuits. Also thank Prof.
Annavaram for our inspirational discussions on the near-threshold project, which is not
included in this dissertation.
iii

I would also like to thank the many excellent researchers that I am fortunate to work
with over the years, including Prof. Naehyuck Chang, Prof. Shahin Nazarian, and Prof.
Massimo Poncino. A special thank goes to Prof. Chang for our long-time, unbreakable,
and fruitful collaboration. His energy and dedication in engineering always impress and
inspire me. I am fortunate to have Prof. Chang’s advices in every possible way, from
theoretical demonstrations to practical implementations, from understanding significance
to improving English, from picking cars to building muscles. I especially enjoy the
moments that you were sharing your experiences with us and I will always appreciate of
that. Also thank Prof. Nazarian for his excellent teaching, insightful technical discussions,
valuable comments while I am mentoring students, and kind understandings when there
are conflicts between course projects and paper deadlines.
My sincere thanks also go out to my collaborators, inside and outside of the USC.
They include Yanzhi Wang, Mohammad Javad Dousti, Tiansong Cui, Xue Lin, Woojoo
Lee, Di Zhu, Alireza Shaefei, Shuang Chen, Majid Ghasemi, and Ji Li at USC;
Younghyun Kim, Donghwa Shin, Sangyoung Park, Jaehyun Park, Jaemin Kim, and Kitae
Kim at Seoul National University, Donkyu Baek at KAIST University; and Mehdi Kamal
at University of Tehran. Without them I could not accomplish what I have done. Special
thanks to Yanzhi Wang for contributing in most of my work. His endless ideas and
unbeatable passion always encourages others. A special thank also goes to Mohammad
Javad Dousti for his extraordinary programming skills and a responsible attitude.
During my time at USC, I enjoy myself very much as a member of the large SPORT
family. I appreciate the time shared with all SPORT members during my PhD career. I
iv

also appreciate the help I received from alumni members of the SPORT group, including
Amir H. Salek, Ehsan Pakbaznia, Mohammad Ghasemazar, and Hadi Goudarzi. I would
like to thank my colleagues and friends who have in many ways contributed to the
success of my academic endeavors. Special thanks to Da Cheng for teaching me scripting
in Perl, and to Jizhe Zhang, Jianwei Zhang, and Fangzhou Wang for our carpools travels
between Los Angeles and the Bay Area.
Finally, I would like to thank my family for all their love and encouragement. In
particular, I gratefully thank my parents for always supporting me with unconditional
love and encouragement, and my in-laws for coming over to the US to help take care of
Dylan. I dedicate this thesis to the memory of my grandmother Xiuyun Zhu, whose role
in my life was, and remains, immense. This last word of acknowledgment I have saved is
for my dear wife Rong Yang. Our friendship began when we entered high school in
September 2000. We immediately became friends and have remained so ever since. Out
of similar goals in the career path, our close friendship evolved into a deep loving
relationship in 2007 and since then I have been happier, calmer, and more content. We
got married in 2011 and had our lovely son Dylan in 2013, who brings us even more
happiness, as well as some tough times of course. With Rong by my side, together with
her love, patience, support, and unwavering belief in me, I have been able to complete
this long PhD journey. Thank you with all my heart and soul.
v

TABLE OF CONTENTS

ACKNOWLEDGEMENTS ........................................................................................................ III
LIST OF TABLES .................................................................................................................. XI
LIST OF FIGURES ............................................................................................................... XIII
ABSTRACT ........................................................................................................................ XIX
SECTION I INTRODUCTION, RELATED WORK, AND COMPONENT MODELS 1
CHAPTER 1 INTRODUCTION ...............................................................................................1
1.1 Contributions in Energy Storage Systems ...........................................................1
1.2 Contributions in Mobile Devices .........................................................................5
1.3 Organization .........................................................................................................8
CHAPTER 2 REVIEW OF THE STATE-OF-THE-ART ............................................................10
2.1 Hybrid Use of Distinct EES Elements ...............................................................10
2.2 Battery Characterization, Modeling and Management ......................................11
2.2.1 Battery State-of-Charge ......................................................................... 11
2.2.2 Battery State-of-Health ......................................................................... 12
2.2.3 Battery Thermal Management ............................................................... 13
2.3 Thermal Modeling and Design in Mobile Devices ............................................15
2.4 Dynamic Thermal Management .........................................................................16

vi

CHAPTER 3 COMPONENT MODELS ..................................................................................18
3.1 Batteries .............................................................................................................19
3.1.1 Battery Capacity Model ........................................................................ 19
3.1.2 Battery Aging Model ............................................................................. 22
3.1.3 Battery Thermal Model ......................................................................... 25
3.2 Supercapacitors ..................................................................................................28
3.3 Power Converters ...............................................................................................29
SECTION II HYBRID ELECTRICAL ENERGY STORAGE SYSTEMS ..................32
CHAPTER 4 INTRODUCTION TO HYBRID ELECTRICAL ENERGY STORAGE SYSTEMS ........32
4.1 HEES System Architecture ................................................................................34
4.2 Design Challenges in HEES Systems ................................................................37
4.2.1 Hardware ............................................................................................... 37
4.2.2 Software ................................................................................................ 39
4.3 Basic Operations in HEES Systems ...................................................................40
4.3.1 Charge allocation ................................................................................... 40
4.3.2 Charge replacement ............................................................................... 41
4.3.3 Charge migration ................................................................................... 43
4.3.4 EES bank reconfiguration ..................................................................... 46
4.4 A HEES Prototype .............................................................................................47
4.4.1 Prototype overview ............................................................................... 48
4.4.2 Prototype Design Specifications ........................................................... 49
4.4.3 Prototype Characterization .................................................................... 52
4.4.4 Experimental Results based on the HEES Prototype ............................ 54
CHAPTER 5 CHARGE ALLOCATION OPTIMIZATION .........................................................63
5.1 Charge Allocation Problem Statement ...............................................................65
5.2 Charge Allocation Optimization Problem Formulation .....................................68
5.3 Near-optimal Charge Allocation Control Algorithm .........................................69
vii

5.3.1 Solar irradiance level prediction ........................................................... 70
5.3.2 Instantaneous charge allocation solver .................................................. 72
5.3.3 Power limit derivation ........................................................................... 77
5.3.4 Global charge allocation solver ............................................................. 80
5.3.5 Temperature, aging, and malfunction handling..................................... 82
5.4 Experimental Results .........................................................................................83
5.4.1 Solar irradiance level prediction ........................................................... 85
5.4.2 Power limit derivation ........................................................................... 86
5.4.3 Global charge allocation problem ......................................................... 88
CHAPTER 6 CHARGE REPLACEMENT OPTIMIZATION .......................................................94
6.1 Charge Replacement Problem Statement ...........................................................95
6.2 Charge Replacement Optimization Problem Formulation .................................97
6.3 Near-optimal Charge Replacement Control Algorithm .....................................98
6.3.1 Instantaneous charge replacement ......................................................... 98
6.3.2 Global charge replacement .................................................................. 101
6.4 Experimental Results .......................................................................................107
6.4.3 Instantaneous charge replacement ....................................................... 108
6.4.1 Global charge replacement .................................................................. 109
CHAPTER 7 CHARGE MIGRATION OPTIMIZATION .........................................................111
7.1 Charge Migration Scheduling Problem Statement ...........................................113
7.2 Charge Migration Scheduling Optimization Problem Formulation .................118
7.3 Near-Optimal Charge Migration Scheduling Algorithm .................................119
7.3.1 Example ............................................................................................... 121
7.3.2 Scheduling algorithm .......................................................................... 122
7.4 Experimental Results .......................................................................................130

viii

CHAPTER 8 STATE-OF-HEALTH-AWARE CHARGE MANAGEMENT ................................133
8.1 SoH-aware Charge Management Problem .......................................................134
8.2 Charge Management Problem Formulation .....................................................136
8.3 SoH-aware Charge Management Algorithm ....................................................137
8.3.1 Optimal operating condition search .................................................... 137
8.3.2 Near-optimal charge management algorithm ...................................... 138
8.4 Experimental Results .......................................................................................143
CHAPTER 9 JOINT THERMAL AND CHARGE MANAGEMENT ...........................................146
9.1 The Joint Thermal and Charge Management Problem ....................................148
9.1.1 DTMB Problem Setup ......................................................................... 148
9.1.2 DTMB Optimization Problem Formulation ........................................ 150
9.2 Optimization Method .......................................................................................153
9.2.3 Reinforcement Learning Method ........................................................ 153
9.2.4 Deriving the Pareto Tradeoff Curve .................................................... 155
9.2.5 Maximizing Cumulative Workload Completion ................................. 158
9.3 Experimental Results .......................................................................................161
9.3.6 Simulation Setups ................................................................................ 161
9.3.7 Pareto Tradeoff Curve ......................................................................... 162
9.3.8 Battery Array Lifespan Extension ....................................................... 165
9.3.9 Cumulative Workload Completion ..................................................... 166
SECTION III MOBILE DEVICES .............................................................................168
CHAPTER 10 GENERATING TEMPERATURE MAPS IN MOBILE DEVICES .........................168
10.1 Therminator Overview .....................................................................................170
10.2 Compact Thermal Modeling ............................................................................172
10.3 Therminator Implementation ...........................................................................175
10.4 Therminator Evaluation ...................................................................................176
10.4.1 Validation of the Therminator Results ................................................ 176
ix

10.4.2 Convergence of the Therminator Results ............................................ 181
10.5 Case Study ........................................................................................................182
CHAPTER 11 DYNAMIC THERMAL MANAGEMENT IN MOBILE DEVICES ...........................188
11.1 Problem Statement ...........................................................................................189
11.1.1 Power and Thermal Models ................................................................ 189
11.1.2 RC-circuit Thermal Model of Thermal Coupling ............................... 190
11.1.3 Effect of the Thermal Coupling .......................................................... 192
11.1.4 Problem Formulation ........................................................................... 193
11.2 Methodology ....................................................................................................194
11.2.1 Parameter Extraction of the RC-Circuit Thermal Model .................... 194
11.2.2 Dynamic Thermal Management .......................................................... 197
11.3 Experimental Results .......................................................................................201
11.3.1 Battery Thermal Modeling .................................................................. 201
11.3.2 Battery-AP Thermal Interaction Modeling ......................................... 202
11.3.3 AP Thermal Modeling ......................................................................... 203
11.3.4 Simulations of Proposed DTM Method .............................................. 204
CHAPTER 12 CONCLUSION AND FUTURE WORK ...........................................................207
REFERENCES .....................................................................................................................210

x

LIST OF TABLES

Table 1.1. Properties of typical EES elements. .............................................................. 2
Table 3.1. Notation used in Chapter 3. ......................................................................... 18
Table 4.1. Notation used in Chapter 6. ........................................................................ 33
Table 4.2. EES bank specifications in the HEES prototype. ........................................ 49
Table 4.3. Comparisons of the GCR efficiencies obtained by the proposed policy and
baseline policies at different levels of the load demand. ............................. 56
Table 4.4. Comparisons of the GCR efficiencies obtained using the proposed policy
and baseline policies for flat load profiles. ................................................. 58
Table 4.5. Comparisons of the GCR efficiencies obtained using the proposed policy
and baseline policies for pulsed load profiles. ............................................ 58
Table 4.6. Comparisons of the GCR efficiencies obtained using the proposed policy
and baseline policies for random-generated load profiles. .......................... 60
Table 5.1. Notation used in Chapter 5.3. ...................................................................... 70
Table 5.2. Comparison of normalized GCA results after a 12 hours charge allocation
process for the 4-bank HEES system for UB policy.. ................................. 88
Table 5.3. Comparison of normalized GCA results after a 12 hours charge allocation
process for the 4-bank HEES system for SBF policy. ................................ 88
Table 5.4. Comparison of normalized GCA results after a 12 hours charge allocation
process for the 4-bank HEES system for BBF policy. ................................ 89
Table 5.5. Comparison of normalized GCA results after a 12 hours charge allocation
process for the 8-bank HEES system for UB policy. .................................. 89
Table 5.6. Comparison of normalized GCA results after a 12 hours charge allocation
process for the 8-bank HEES system for SBF policy. ................................ 90
Table 5.7. Comparison of normalized GCA results after a 12 hours charge allocation
process for the 8-bank HEES system for BBF policy. ................................ 90
xi

Table 7.1. Notation used in Chapter 7. The notations are more complicated than the
charge allocation and charge replacement problem. ................................. 113
Table 10.1. Temperatures obtained from the thermocouple measurement (TCM),
Autodesk Simulation CFD, and Therminator. Note the AP junction
temperature is read from temperature register (Reg) instead of
measurement. The ambient temperature is 23.0˚C. ................................... 179
Table 10.2. Skin temperature and AP junction temperature obtained by thermocouple
measurement (TCM) and Therminator at different AP power consumption
levels. ......................................................................................................... 183
Table 11.1. Extracted parameters for the proposed RC-circuit thermal model. ........... 201
Table 11.2. Tasks having thermal violation as a percentage of all tasks in TS1. ......... 204
Table 11.3. Tasks having thermal violation as a percentage of all tasks in TS2. ......... 204

xii

LIST OF FIGURES

Figure 1.1. Concept diagram of HEES systems .............................................................. 4
Figure 3.1. Li-ion battery model used in our work based on [43]. ................................ 20
Figure 3.2. Validation of circuit model in [43] by comparing simulation results with the
measured battery terminal voltage of two serial-connected 350 mAh Li-ion
batteries. ...................................................................................................... 20
Figure 3.3. The battery terminal voltage changes as the discharging time (SoC
decreases). Data is taken by discharging a 350 mAh 2-cell series lithium-ion
GP1051L35 [85]. ......................................................................................... 21
Figure 3.4. SoH degradation versus SoC swing (at different average SoC levels) and
average SoC (at different SoC swings). ...................................................... 24
Figure 3.5. Simulated SoH degradation versus cycle numbers at different battery
temperatures with environment temperature of 25°C. ................................ 25
Figure 3.6. Simulated battery temperatures at different discharge rates during
continuous discharge process in the condition of natural convection. ........ 26
Figure 3.7. Thermal resistance and power consumptions of the 4-cell battery pack
(22650M LiMnNi battery) with a 70mm fan at different fan speeds. ......... 27
Figure 3.8. Circuit-based model of the boost-buck model. ........................................... 29
Figure 3.9. Validation of converter model (16)(17) with measured LTM4607 data. .... 30
Figure 3.10. Converter efficiency at different input voltage, output voltage, and output
current. ......................................................................................................... 31
Figure 4.1. Architecture of the proposed HEES system. ............................................... 34
Figure 4.2. Conceptual drawing of the charge allocation process. ................................ 41
Figure 4.3. Conceptual drawing of the charge replacement process. ............................ 42
Figure 4.4. Conceptual drawing of the charge migration process. ................................ 43
Figure 4.5. EES bamk reconfiuration example. ............................................................. 46
Figure 4.6. Front and rear view of the HEES prototype. ............................................... 47
xiii

Figure 4.7. Screenshot of the LabVIEW user interface. ................................................ 51
Figure 4.8. Characterization of the lead-acid battery bank (top panel), and curve fitting
of the rated capacities with respect to the discharging currents (bottom
panel) to find the Peukert constant. ............................................................. 53
Figure 4.9. Changes of the terminal voltage of the supercapacitor bank over the
replacement process for the proposed policy and the baseline policies (left
axis), and the optimal CTI voltage setting achieved by the proposed CTI
voltage control (right axis). ......................................................................... 54
Figure 4.10. Comparisons of the instantaneous charge replacement efficiency between
the proposed policy and the baseline policies during the discharging
process. ........................................................................................................ 55
Figure 4.11. Energy assignments by the proposed GCR policy (a), BP4 (b), BP5 (c) for
the 15-min load profiles in [98]. Light and dark gray areas denote amounts
of energy drawn from the supercapacitor bank and the lead-acid battery
bank, respectively. ....................................................................................... 61
Figure 4.12. Comparisons of the normalized remaining energy in the supercapacitor
bank (a) and the instantaneous charge replacement efficiencies (b) obtained
by the proposed GCR policy and baseline policies, for the 15-min load
profiles in [98]. ............................................................................................ 62
Figure 5.1. Schematic of the charge allocation process in a HEES system. .................. 66
Figure 5.2. Comparison of ICA efficiency at different CTI voltages obtained by the
proposed method (solid curve) and Monte Carlo simulation (cross marks).
..................................................................................................................... 75
Figure 5.3. Results of the proposed solar irradiance level predictor at 8 AM, 10 AM,
and 12 AM. The four groups from top to bottom are the average solar
irradiance levels for Apr., Jul., Sep. and Dec. ............................................. 84
Figure 5.4. Comparisons of the GCA with the proposed solar prediction method and
Oracle system for the 4-bank HEES system (a) and the 8-bank HEES
system (b). ................................................................................................... 85
xiv

Figure 5.5. Power limit for supercapacitor banks (SBs) that is derived from the
proposed heuristic. The data is generated using the 8-bank HEES system
with the 4X6 PV module. Simulated results are obtained using solar data in
Los Angeles in July. .................................................................................... 86
Figure 5.6. Comparison of total power gain (a), average array charging current of
supercapacitor banks (b) and battery banks (c), in the 8-bank HEES system
with the 4X6 PV module. Simulated using solar data in Los Angeles in July.
..................................................................................................................... 93
Figure 6.1. Schematic of the charge replacement problem in HEES systems. .............. 95
Figure 6.2. Line (a) and (b) show the discharging power bounds. The shadow area and
white area under Pload(t) curve denote the Eeff
BB
and Eeff
SB
, respectively. . 105
Figure 6.3. Comparison of ICR efficiencies on eight-bank (a) and four-bank (b) HEES
systems with high, median and low power demand. ................................. 108
Figure 6.4. Comparison of GCR efficiencies on eight-bank (a) and four-bank (b) HEES
systems with load Profile 1 and 2, at long and short operation time. ........ 109
Figure 7.1. Schematic of the charge migration scheduling problem. .......................... 115
Figure 7.2. Charge migration efficiency versus charging current (left) and converter
efficiency versus output voltage (right). ................................................... 120
Figure 7.3. Three scheduling schemes: all merged (A), one at a time (B) and near-
optimal scheduling (presented). ................................................................ 122
Figure 7.4. Charge migration efficiencies comparison in 20-bank HEES system (a) and
40-bank HEES system (b). ........................................................................ 131
Figure 7.5. Presented task scheduling solutions for a 20-bank HEES system (a) a 40-
bank HEES system (b). ............................................................................. 131
Figure 8.1. Conceptual diagram of charge management problem. .............................. 135
Figure 8.2. Schematic of optimal operation condition search ..................................... 137
Figure 8.3. SoC swing and average SoC of battery-only EES system and HEES system
vs. duration of pulse load profile per cycle. .............................................. 144
xv

Figure 8.4. Normalized cycle life gain (bars) and cycle efficiency improvement
(curves) of a HEES system with different source and loads profile (upper -
pulse, lower - sinusoidal wave). ................................................................ 145
Figure 9.1. Block diagram of an portable system using dynamic battery thermal
management. ............................................................................................. 148
Figure 9.2. Tradeoff curve achieved by presented algorithm with a hybrid power source
(dot marks) and a battery-only power source (triangle marks). Cross and
circle marks show results of using fixed fan speed (F0, F1, F2 from left to
right) with the hybrid power source. ......................................................... 163
Figure 9.3. Normalized one-cycle workload completion of different tradeoff options in
RL-Hy and RL-Bat tradeoff curve. ........................................................... 164
Figure 9.4. Battery temperature traces in one cycle when applying F0-Hy (0%) and RL-
Hy tradeoff options with different efan....................................................... 164
Figure 9.5. Maximal lifespan of the battery array when ΔSLEOL is 20%. .................... 165
Figure 9.6. Cumulative workload completion versus the desired system lifetime of all
baseline setups and the presented RL-Hy. ................................................ 166
Figure 10.1. Overview of Therminator. ......................................................................... 171
Figure 10.2. A cross-section view of the thermal resistance network in a simple
smartphone model. .................................................................................... 173
Figure 10.3. Comparison of runtime of sequential and parallel methods for different sub-
component counts. ..................................................................................... 176
Figure 10.4. (a) Teardown of MSM8660 MDP device and temperature measurement kits
(circle marks are temperature measurement points. Note for the PCB,
thermocouple is attached onto the other side), (b) CFD drawing, and (c)
Therminator 3-D visualization. ................................................................. 177
Figure 10.5. Temperature maps produced by Autodesk Simulation CFD (a1, b1, c1) and
by Therminator (a2, b2, c2) for the screen protector (a), rear case (b), and
PCB (c) for the StabilityTest use case. ...................................................... 180
xvi

Figure 10.6. Therminator results convergence and runtime versus sub-component counts
for the StabilityTest use case. .................................................................... 181
Figure 10.7. 3D layout for Samsung Galaxy S4. Sub-components are not shown. ....... 182
Figure 10.8. AP power consumption and junction temperature versus various skin
temperature setpoints. ................................................................................ 185
Figure 10.9. Skin and AP junction temperature versus rear case material (a) and thermal
pad material (b) for PAP=2.2W. ................................................................. 186
Figure 11.1. Temperature profile of the battery and application processor during the 1C
battery discharging in Nexus S. The phone is turned off. ......................... 188
Figure 11.2. Conceptual diagram of thermal resistors in mobile devices. .................... 191
Figure 11.3. Comparison of RC-thermal circuit models: a) conventional thermal model;
b) thermal model considering the thermal coupling effect. ...................... 191
Figure 11.4. The effect of the elevated ambient temperature on the chip power
consumption due to the thermal coupling in mobile devices. ................... 192
Figure 11.5. The flowchart of the proposed DTM method. ........................................... 196
Figure 11.6. Comparison of temperature prediction with and without considering the
thermal coupling effect. The scaling factor is the ratio between the actual
operating frequency and the maximal frequency. ..................................... 199
Figure 11.7. Experiment setup used to characterize the thermal coupling effect in a
Nexus smartphone. .................................................................................... 200
Figure 11.8. Measured and simulated battery thermal behaviors for a 1C discharging
process. ...................................................................................................... 201
Figure 11.9. Measured and simulated battery and AP thermal behaviors by applying a
controllable constant heating power. ......................................................... 202
Figure 11.10. Measured and simulated AP temperature trace during the cooling down of
the AP. ....................................................................................................... 203
Figure 11.11. Verification of AP thermal behaviors on Nexus S during the temperature
rising while running the StabilityTest v2.7 benchmark [120]. .................. 203
xvii

Figure 11.12. Thermal violations caused by baseline DTM without considering thermal
coupling effect. Simulation for TS1 with critical temperature of 45C. ..... 205
Figure 11.13. Violated tasks and dropped tasks as a percentage of all tasks in Task Set 1
versus different battery temperature. ......................................................... 205

xviii

ABSTRACT
This dissertation is dedicated to address several thermal-related problems in a multiple
systems, including energy storage systems and mobile devices.
The first part of this dissertation introduces hybrid electrical energy storage (HEES)
systems by explaining the motivation, proposing basic architectures, defining key HEES
operations, and presenting the near-optimal charge management policies. Key HEES
operations, including the charge allocation, charge replacement, charge migration, and
state-of-health-aware charge management are all formulated as mathematical
optimization problems. Near-optimal charge management control algorithms based on
certain approximations and iterative solving convex optimization problems are also
presented separately for each key HEES operation. Simulation results show significant
improvements in energy efficiency and battery lifespan. A HEES prototype is built and
implemented with the presented charge management policies to further demonstrate the
energy efficiency improvements brought by the hybrid use of different types of energy
storage elements and the efficacy of presented policies. In addition, this dissertation also
points out that elevated battery temperature can significantly speed up the aging process
of batteries, which necessitates a proper thermal management policy for the HEES. This
thesis later formulates a joint thermal and charge management problem for batteries in
the HEES with a forced air-convection cooling technique and presents a hierarchical
algorithm that combines reinforcement learning method and dynamic programming
method to derive the optimal joint management policy, which determines
charging/discharging profiles of the power source and settings of the cooling device.
xix

Simulation results show that presented policy significant improves the battery lifespan,
resulting in completion of much more workload before the battery expires.
The second part of the dissertation focuses on mobile devices. The dissertation points
out that maintaining the skin temperature (surface temperature on the exterior case of
mobile devices) at an appropriate level is a new design challenge in mobile devices
because most of them are directly touched by users. A compact thermal modeling-based
approach is presented and implemented as Therminator, which is capable of producing
temperature maps of all important components, from the application processor (AP) to
the skin of the device itself, in an accurate and efficient manner. Therminator have been
validated against the practical temperature measurements and commercial computational
fluid dynamics simulation tools. A case study on the thermal path design and skin
temperature management policy is carried out for a state-of-art smartphone by using
Therminator. Next, it is observed in smartphones that there exists a thermal coupling
effect, which is referring to the phenomenon that the major heat generation components,
such as the AP and the battery, thermally affect each other. Theoretical analysis show that
ignoring this thermal coupling effect results in an underestimation of the chip
temperature. Practical experiments are presented to quantitatively characterize and model
this effect. A thermal coupling-aware dynamic thermal management policy based on an
accurate RC-thermal model considering the thermal coupling effect is presented to reduce
the maximal temperature violations in mobile devices.

xx

SECTION I INTRODUCTION, RELATED
WORK, AND COMPONENT MODELS

CHAPTER 1
INTRODUCTION
Operating electronic devices at appropriate temperature levels is extremely important
because a lot of other performance metrics are temperature-related, e.g., leakage power,
failure rate, system lifespan. Thus, designing proper thermal management policies is one
of the major design challenges in various systems, such as integrated circuits (ICs),
portable systems, energy storage systems, vehicles, and so on. To derive a thermal
management policy, accurately modeling the thermal behaviors receives the highest
priority as it provides a good starting point. Moreover, thermal management is an
important issue, but not the only one, that shall be concerned in a system. This
dissertation is dedicated to address a series of thermal-related problems, from modeling
temperature distributions to deriving a joint thermal and charge management policy, in
multiple systems.
1.1 Contributions in Energy Storage Systems
Electrical energy is being world-widely used in every aspect in the modern society.
Reliable supply of electric energy is among the top concerns of the electrical energy
1

generation. On the other side, electrical energy consumption in a system changes over
time due to changes in the power requirements of load devices as well as the users’
behaviors. Therefore, electrical energy generation and consumption rates are typically not
matched with each other. Electrical energy storage (EES) systems mitigate this mismatch
by storing the excessive energy produced at certain times of the day and providing the
stored energy during the peak load times as needed. When properly designed and
controlled, EES systems [1, 2, 3] increase the availability of the electrical energy,
mitigate the supply-demand mismatches, and reduce the power generation capacity
required to meet the peak power demand.
Conventional EES systems are mainly homogeneous, which only consist of a single
type of EES elements. Unfortunately, no available EES element can fulfill all desired
performance metrics of an ideal storage means (e.g., high power/energy density, low
Table 1.1. Properties of typical EES elements.
Metrics
Batteries
Supercapacitor
Li-ion NiMH Lead-acid NiCd
Power capacity (W/kg) high high high high ultra high
Energy density (Wh/L) very high medium low low very low
Leakage (%) low low low low high
Lifespan (cycles) medium short short medium very long
Cycle efficiency (%) high low low high very high
Cost () high medium very low low very high

2

cost/weight per unit capacity, high round-trip efficiency, and long cycle life.) For
example, although supercapacitors have superior power capacity and lifespan, their
energy density is way too low and they are too expensive. In contrast, lead-acid batteries
are cheap but have relatively low power capacity and short lifespan. Table 1.1
summarizes properties of some typical EES elements. An obvious shortcoming of a
homogeneous EES system is that key figures of merit (normalized with respect to
capacity) of the system cannot be any better than those of its constituent EES elements.
We seek for a system-level design methodology based on current energy storage
technologies to enhance storage system performance and lifetime of the EES system. We
propose hybrid EES (HEES) systems [4, 5] to overcome the shortcoming mentioned
above. HEES systems are EES systems that comprise of two or more types of EES
elements, where each type has its unique strengths and weaknesses. Figure 1.1 depicts the
conceptual diagram of the HEES system. Yet, the HEES system can be designed so that it
offers characteristics of an ideal storage, in much the same way that a hybrid memory
hierarchy system in today's computer systems provides low access delay, high density,
and low cost all at the same time. Based on characteristics of the HEES system and
power demand profiles of load devices (or power sources), charge management policies
aiming to achieve near-optimal HEES system performance must be developed. The
appropriate charge management policies to control HEES operations such as charge
migration, charge allocation, charge replacement, and SoH-aware charge management,
can exploit strengths of each type of EES element and achieve performance metrics that
3

are superior to those of any of its individual EES elements [6, 7, 8, 9, 10, 11, 12, 13, 14,
15].
Apart from the charge management policy, we see a strong motivation to develop a
thermal management policy for EES systems. Batteries age during the cycling. The
lifespan of a battery is defined as the number of cycles before its state of health (SoH)
drops below an end-of-life (EOL) threshold. The SoH is a figure of merit that
indicates the state of battery between the beginning of its life and end of its life in
percentage. It captures the general status of the battery and its ability to store and deliver
energy compared to its ideal condition (a brand new battery of the same kind). ). A fresh
new battery has SoH of 100% and the typical end-of-life threshold is considered as 80%

Figure 1.1. Concept diagram of HEES systems
4

[16]. The SoH of a battery generally degrades during the usage while many factors could
affect the degradation rate, e.g., depth of discharge (DoD), cycling rate, and battery
temperature. Elevated temperature speeds up the SoH degradation of the battery
dramatically [17, 18]. For example, the SoH degradation rate at 45° 𝐶𝐶 is twice as fast as
that at 35° 𝐶𝐶 [19]. Unfortunately, many research results show that the battery temperature
could easily rise up (>60° 𝐶𝐶 ) at a high charge or discharge rate [20, 21]. Thus, a key issue
is how to extend the lifespan of a given EES system such that it can power the service
provider for a longer time. The SoH-aware charge management has been presented in
[22]. However, a joint thermal and charge management can further improve the lifespan
of an EES system. We present to use a forced convection cooling mechanism, such as a
cooling fan, and develop a corresponding thermal management policy [23]. The thermal
management policy maintains the battery temperature at a proper level during the
cycling, and thereby improves lifespan of batteries.
1.2 Contributions in Mobile Devices
Mobile devices, such as smartphones and tablets, continue to grow in popularity thanks to
their computational ability and mobility. Some of the state-of-art mobile processors are
considered to be as functional as typical processors in many existing computer systems.
Meanwhile, the high-end mobile processor design is concerned with many of the same
problems that conventional processors face, including performance, energy efficiency,
thermal issues, and reliability concerns, although generally performance takes the back
seat to energy efficiency and thermal considerations.
5

It is well known that the elevated chip temperature is one major contributor to lower
device reliability (i.e., accelerated aging) and higher leakage power consumption [24].
The negative bias temperature instability (NBTI) and hot carrier injection (HCI) cause the
performance degradation [25] as circuits operating at high temperature. In addition,
failure mechanisms such as electromigration, stress migration, and dielectric breakdown
are exponentially dependent on temperature as well [26]. More importantly, the leakage
power consumption is known to be exponentially dependent on the temperature of the
application processor (AP). Higher temperature results in greater power consumption,
and this effect in turn increases the AP temperature even more. Therefore, developing an
effective thermal management policy for AP, which is concerned about energy savings
and reliability, is crucial for mobile device.
Dynamic thermal management (DTM) has been proposed as an effective technique to
control the over-heating of the chip and maintain the chip temperature below a critical
temperature, 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 , above which the microprocessor chip could be damaged. The
typical DTM response mechanisms (control knobs) include fetch-toggling, dynamic
thread migration, frequency throttling and dynamic voltage and frequency scaling
(DVFS) [27]. Practical run-time DTM methods require either distributed temperature
sensors or a compact thermal model of the chip (such as HotSpot [28]) that would relate
the chip temperatures to the chip-package-heat sink interface characteristics and power
density values. Conventional DTM methods work well for computer systems where the
CPU is assumed to be thermally independent of other components. Unfortunately, due to
the sharing of the rather small physical space, thermal behaviors of different components
6

in mobile devices may interact with each other. This thermal coupling effect results in a
design challenge to derive a proper thermal management policy for chips in mobile
device.
In addition, a new degree of thermal constraint appears to be extremely important in
mobile devices because most are designed to be hand-held. The skin (surface)
temperatures are defined as temperatures at the surface of the exterior case of mobile
devices. High skin temperatures can cause first or even second degree burns on device
users, with obvious and immediate adverse user reactions. According to [29, 30], most
people experience a sensation of heat pain when they touch an object hotter than 45˚C.
Therefore, how to maintaining the skin temperature at an appropriate level has become
another design challenge in mobile devices. This constraint refers to the fact that the
temperature at the device skin must not exceed a certain upper threshold.
To address the thermal challenges aforementioned, two important factors should be
accounted properly. First, we need to consider the thermal coupling effect between the
major heat generation components in enclosures of mobile devices, e.g., AP and battery.
In the following text, we present our work that points out the strong thermal coupling
between the AP and battery in a mobile device enclosure, and provides a quantitative
characterization of this effect. In particular, we build a compact thermal model (using
RC-circuits) to account for this effect and extract corresponding parameters through
practical experiments. We also present a DTM method combining the thermal sensor
readouts, look-up tables (LUTs), and the compact thermal modeling. Second, it is
necessary to generate temperature map (temperature at different locations) for different
7

components in the smartphone, starting from the AP and other key device components,
extending to the skin of the device itself, in an accurate and efficient manner. Knowing
the detailed temperature map on the device skin at the design time is helpful in selecting
the right material to build the device and designing the heat flow path. Moreover, derive
the optimal thermal management policy also depends the temperature maps of particular
components, such as the AP and the device skin. In the following text, we present
Therminator, a CTM-based component-level thermal simulator targeting small form-
factor mobile devices (such as smartphones and tablets).
1.3 Organization
The rest of this dissertation is organized as follows. Chapter 2 reviews the previous
research efforts that are related to thermal management, thermal modeling, studies of
properties of EES elements, and EES system design. The system models that we adopted
for our simulations are presented in Chapter 3. Chapter 4 introduces the HEES system in
details, explaining how the HEES system functions, presenting system models for each
component, and elaborating key HEES system operations. In addition, a HEES prototype
is also shown to demonstrate the HEES concept and efficacy of control algorithms.
Chapter 5, Chapter 6, Chapter 7, and Chapter 8 discuss each key operation separately,
and present a near-optimal algorithm to derive the charge management policy. Chapter 9
presents a joint optimization of thermal and charge management to extend the lifespan of
batteries in a HEES and, in turn, results in more total workload completion. Chapter 10
presents a compact thermal modeling-based approach that provides accurate temperature
8

maps for various components, including AP, battery, print-circuit board (PCB), display
screen and so on, in a smartphone within a fast runtime. Chapter 11 presents practical
experimental results that discover the thermal coupling effect between the AP and model
this effect by using a RC thermal model. A thermal-coupling-aware thermal management
policy is presented as well to reduce the number of thermal violations. Finally, Chapter
12 concludes this dissertation and discusses some possible future research topics.

9

CHAPTER 2
REVIEW OF THE STATE-OF-THE-ART
2.1 Hybrid Use of Distinct EES Elements
The concept of hybrid power sources (energy storage systems) was first introduced in
[31]. Considerable efforts have been invested in exploring the optimal architecture of the
HEES systems. A direct-parallel connection of the battery and supercapacitor [32, 33] is
simple but has major weaknesses because the shared terminal voltage of both sources
must be kept same, which limits the capacity utilization of the supercapacitor and
disables the active current distribution control. A cascade DC-DC converters between the
battery and supercapacitor [34] can isolate the power sources and allow higher
supercapacitor utilization. However, this design is targeted to a predefined charge
management scenario whereby the supercapacitor is used as a battery buffer all the time.
A more general architecture is a DC-bus with distributed converters [35, 36]. However,
the previous DC-bus architectures do not change the DC-bus voltage, which prevents
them from achieving higher system efficiency. The proposed HEES system resembles the
DC-bus topology, but employs optimal control of the DC-bus voltage and does proper
current distribution to each bank at run time.
Proper charge management on top of the hybrid EES architecture will be crucial if the
architecture has some degree of freedom both at design and run times. A circuit model
helps derive a desirable capacity ratio between the battery and supercapacitor, based on
the peak power [37]. Different supercapacitor configurations and changing duty ratios
10

and pulse frequency of the load profile were considered in optimizing HEES performance
in [38]. However, none of the previous work has introduced a general HEES management
because the previous HEES architectures are mostly dedicated to particular operation
scenarios.
2.2 Battery Characterization, Modeling and Management
Tons of efforts have been invested to build and improve the modeling of battery
behaviors, including the relationship between battery voltage and state-of-charge (SoC),
aging effect, and heat generation.
2.2.1 Battery State-of-Charge
Knowing the amount of energy left in a battery compared with the energy it had when it
was full gives the user an indication of how much longer a battery will continue to
perform before it needs recharging. The state-of-charge (SoC) is defined as a percentage
number from 0 to 100% to indicate how much charge remains in the battery, like the
analogy of a fuel tank in a car.
Measuring state-of-charge by voltage is the simplest method, but it can be inaccurate.
Cell types have dissimilar chemical compositions that deliver varied voltage profiles.
Temperature also plays a role. Higher temperature raises the open-circuit voltage, a lower
temperature lowers it, and this phenomenon applies to all chemistries in varying degrees.
We use Li-ion batteries in our HEES system as they have high-energy density, high
efficiency, long cycle life, no memory effect, and low self-discharge rate. Authors in [39,
40] took a theoretical electrochemical way to estimate the SoC and state-of-health of
11

batteries for system management. A dual extended Kalman filter is used to
simultaneously estimate the SoC and capacity from the open-circuit voltage [41]. A
lithium-ion battery model introduced in [42] employs the method of electrochemical
impedance spectroscopy. Authors in [43] presented a circuit-based runtime model. We
adopt this model as it provides enough accuracy and does not involve too many details
from electrochemistry.
2.2.2 Battery State-of-Health
Among the performance metrics aforementioned for EES systems, the cycle life, also
known as the lifespan, of EES elements is one of the crucial metrics that should be
considered by system designers. The cycle life is directly related to the state of health
(SoH), which is defined as the ratio of full charge capacity (FCC) of a cycle-aged EES
element to its designed capacity (DC). A fresh battery has SoH value of one. Typically, a
battery is considered to be completely aged when SoH drops below 0.8.
The SoH of the batteries is hard to estimate because the capacity fading effect (i.e.,
SoH degradation) is a result of long-term electrochemical reaction. The capacity fading is
related with carrier concentration loss and internal impedance growth in the batteries.
These effects strongly depends on the operating condition of the battery such as charging
and discharging current, number of cycles, SoC swing, average SoC and operation
temperature [44, 45, 46]. The characterization of the battery cell requires time consuming
experiments. Thus, mathematical models help us to reduce the time complexity in
estimating the SoH degradation. Electrochemistry-based models [18, 39, 47] are
12

generally accurate but not easy to implement. The SoH degradation model in [16], which
has a good match with real data in [46] is suitable for HEES systems.
Appropriate control of charging and discharging process is a representative way to
enhance the cycle life of the batteries. Typical Li-ion batteries are usually charged
through two continuous steps, constant-current step (CC) and constant-voltage step (CV).
Each step has an effect on the charging time and battery lifetime. An appropriate
charging protocol needs to achieve a balance between charging time and cycle life.
Several techniques have been introduced such as current decay charging [48], dynamic
pulse charging [49], constant-power (CP) charging [50], and multistage CC charging [51].
These works, although effective, are all focused on the single type of EES elements or
homogeneous EES system.
2.2.3 Battery Thermal Management
Batteries generate non-negligible amount of heat during usage. The general thermal
model of a lithium battery is very complex due to the non-uniform internal temperature
distribution. The total heat generation of a lithium battery generally has three components:
entropy change heat, Ohmic heat and chemical reaction heat [52]. Considerable efforts
have been invested to model the thermal behaviors of batteries [53, 54, 55, 21, 56, 57].
Previous research revealed that elevated temperature affects battery performance such as
power capability during charging and discharging [58]. Especially, the aging mechanism
speeds up the battery health degradation significantly [17, 18, 59]. The fast battery health
degradation results in a reduction of the lifespan, which becomes a primary concern for
13

systems such as electrical vehicles (EVs) or hybrid electrical vehicles (HEVs) that rely on
the battery performance [58, 60, 61, 62].
Therefore, an appropriate thermal management for batteries is an effective method to
extend the battery cycle life, and in turn the lifespan of the entire systems. Thermal
management systems for batteries using forced convection cooling have been proposed in
[63, 64]. Simulation results for lead-acid batteries in electrical vehicles (EVs) showed
that thermal management systems of this kind cooling might improve battery
performance by 30–40% [56]. However, the cooling effect for the large size lithium
batteries (for EVs) is limited by the heat transfer from the battery inside to the battery
outside due to high thermal resistance of the electrolyte and the plastic cell housing. In
contrast, for small size lithium batteries, authors in [21] observed negligible temperature
difference between the battery surface and inside.
The thermal management work for battery systems can be generally classified into
two categories: passive cooling and active cooling. Passive cooling methods use some
special materials, such as phase change materials, to absorb heat generated in the battery
systems and transfer the heat outside the battery pack [65, 66, 67]. Active cooling
methods adopt air cooling [68] or liquid cooling [69]. Cooling fan is the most widely
used forced convection cooling devices [70] due to its properties of small size, easy
installation and control and low cost.
14

2.3 Thermal Modeling and Design in Mobile Devices
HotSpot [28] is a successful early-stage CTM methodology targeting thermal analysis of
the silicon die and its packaging which are cooled with a heat sink and possibly a fan. It
generates accurate temperature maps quickly. Temptor [71] is a tool based on HotSpot
which allows the temperature prediction using performance counters instead of
components’ power trace. Meng et al. [72] improved HotSpot by adding the 3-D chip
simulation support. Teculator [73] instruments HotSpot to support thermoelectric coolers.
3D-ICE [74] is another thermal simulator targeting 3-D ICs equipped with liquid cooling.
However, neither HotSpot nor 3D-ICE can be modified or extended to analyze small
form-factor devices as they target a single IC package along with its cooling equipment.
In fact, modeling smartphone is much more complicated due to: 1) multiple heat
generators, including battery, display, and a number of IC chips; 2) complex 3-D layout
where each component may be in vertical and horizontal contact with several other
components; and 3) necessity of considering the internal air in the device. Comparing to
those tools, Therminator focuses on component-level thermal modeling, in which the
architecture-level details inside a single chip package are ignored.
Several researches have been conducted in studying the thermal design for
smartphones and tablets [75, 76, 77]. Luo et al. established a simple thermal resistance
network to analyze the whole mobile phone system [75]. However, the thermal resistance
network built in [75] is oversimplified as each component is modeled as one block with a
single uniform temperature value. Gurrum et al. modeled the smartphone in CFD tools
and analyzed the thermal effect of using materials with different thermal conductivities
15

through CFD simulation [76]. Rajmond and Fodor [77] used CFD tools to show that
attaching thermal pad on top of the AP significantly reduces the AP temperature. To the
best of our knowledge, Therminator is the first tool targeting smartphones that
automatically builds a compact thermal model from the device specifications, and solves
for temperature maps of all components accurately with a fast runtime.
2.4 Dynamic Thermal Management
Many research works have been conducted on the dynamic thermal management for
conventional computer systems. In the architecture level, Brooks et al. [27] described a
couple of micro-architectural and scaling techniques to cool-down the temperature of the
microprocessors. Skadron et al. [28] adopted a feedback control theory to evoke the DTM
and used the fetch-toggling as the response mechanism. The work aforementioned are
mainly reactive DTM techniques, which have respond time limitation that prevents the
use of dynamic voltage scaling (DVS) due to its high invocation overhead [78]. The
authors in [79] proposed a predictive DTM method and combined the architectural
adaption and DVS for multimedia applications. The authors in [80] proposed proactive
thread migration, DVFS and temperature balancing to minimize impact of thermal
hotspots and temperature gradients. For real-time systems, Lee et al [81] proposed DTM
for MPEG-2 decoding, which processes tasks at the minimum frequency meeting
deadline constraints and sacrifices the video quality if there is a thermal violation. The
authors in [82] derived the DTM policy using reinforcement learning technique: defining
16

the processor temperatures and workload levels as the environment states and the
available operating frequencies as the action set.
As the feature size scales down, the proportion of the leakage energy consumption in
the total energy keeps increasing due to the lower threshold voltage, smaller channel
length and gate oxide thickness. The authors in [83] improved the model for leakage
current and showed that it has an exponentially relationship with the die temperature. In
[84], Shin et al. considered the cooling mechanism for the CPU, accounted for the
cooling energy consumption, and solved for the energy-optimal DTM policy. They
jointly optimized the cooling fan usage and operating frequency selection to minimize the
total energy consumption, including both of computing and cooling. Authors in [23]
proposed the thermal management policy to extend the service life of the batteries in
portable devices. None of the aforementioned work targets the mobile devices and
considers the thermal coupling between the AP and battery.

17

CHAPTER 3
COMPONENT MODELS
We adopt circuit-based models to describe and simulate the electrical behaviors of
batteries, supercapacitors, and power converters. In addition, for batteries, we also
account for thermal behaviors and aging mechanism. We present the models that are used
in our work in this chapter. The notations are summarized in Table 3.1.
Table 3.1. Notation used in Chapter 3.
Symbol Definition
𝐶𝐶 𝑏𝑏 , 𝑓𝑓 𝑓𝑓 𝑐𝑐𝑐𝑐
Total charge of battery when it is fully charged
𝐶𝐶 _ 𝑏𝑏 Remaining charge of a battery
𝛾𝛾 𝑐𝑐 Peukert constant of the batter for charging process
𝛾𝛾 𝑑𝑑 Peukert constant of the batter for discharging process
𝑅𝑅 𝑠𝑠 , 𝑅𝑅 𝑐𝑐 𝑠𝑠 , 𝑅𝑅 𝑐𝑐 𝑐𝑐 Internal resistance in the battery circuit model in Figure 3.1
𝐶𝐶 𝑐𝑐 𝑠𝑠 , 𝐶𝐶 𝑐𝑐 𝑐𝑐 Internal capacitance in the battery circuit model in Figure 3.1
𝑅𝑅 𝑠𝑠 𝑠𝑠 𝑐𝑐 𝑐𝑐 𝑠𝑠𝑠𝑠
Internal resistance in the supercapacitor
𝐶𝐶 𝑐𝑐𝑐𝑐𝑐𝑐
Capacitance of supercapacitor banks
𝜏𝜏 𝑠𝑠 𝑑𝑑 Self-discharge time constant of the supercapacitor bank
𝑥𝑥 𝑐𝑐 Binary indicator of the charger status (on/off)
𝑃𝑃 𝑐𝑐 Power loss rate in the converter
𝑃𝑃 𝑐𝑐 𝑑𝑑 𝑐𝑐𝑐𝑐
, 𝑃𝑃 𝑠𝑠𝑠𝑠
, 𝑃𝑃 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐
Conduction, switching, and controller power loss rate in the
converter
𝐷𝐷 Duty ratio of the converter
𝑅𝑅 𝐿𝐿 , 𝑅𝑅 𝐶𝐶 Series resistances of the inductor and capacitor in the converter
𝑅𝑅 𝑠𝑠𝑠𝑠 𝑐𝑐 , 𝑄𝑄 𝑠𝑠𝑠𝑠 𝑐𝑐 Turn-on resistance and gate charge of the 𝑖𝑖 -th MOSFET
𝑉𝑉 𝑂𝑂 𝐶𝐶 Open-circuit voltage
𝑉𝑉 𝐶𝐶𝐶𝐶 Closed-circuit voltage
𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎
Array charging or discharging current, seen at the output of battery
and supercapacitor arrays
𝐼𝐼 𝑠𝑠 𝑒𝑒
Equivalent charging or discharging current, considering the rate
capacity effect

18

3.1 Batteries
Batteries have advantages of high energy capacity and low self-discharge, and thereby,
they are suitable for long-term storage purpose. The presented the thermal and charge
management framework and optimization techniques are general and can be applied to
any type of battery banks so far as we have accurate battery models.
3.1.1 Battery Capacity Model
We rely on an accurate circuit-based battery model in [43] to relate the battery SoC to its
open-circuit voltage and other important parameters such as the internal resistance and
capacitance. Figure 3.1 shows a charging process of a Li-ion battery, with a runtime-
based model on the left, and a circuit-based model on the right for accurately capturing of
the battery service life and the I-V characteristics. In this model, the SoC is given by,
𝑆𝑆𝑆𝑆 𝐶𝐶 =
𝐶𝐶 𝑏𝑏 𝐶𝐶 𝑏𝑏 , 𝑓𝑓 𝑓𝑓 𝑐𝑐𝑐𝑐
(1)
In practice, ignoring the battery aging, we derive 𝐶𝐶 𝑏𝑏 , 𝑓𝑓 𝑓𝑓 𝑐𝑐𝑐𝑐
from the nominal capacity
(usually characterized in units of 𝐴𝐴 ⋅ ℎ) of the battery. The battery OCV is modeled as a
function depending on SoC. Other parameters, such as the internal resistance and
capacitance, are functions of SoC as well. The functions are non-linear and involve some
empirical parameters 𝑏𝑏 𝑐𝑐 𝑖𝑖 in [85],
19

𝑉𝑉 𝑂𝑂 𝐶𝐶 = 𝑏𝑏 1 1
𝑒𝑒 𝑏𝑏 1 2
⋅𝑆𝑆 𝑆𝑆 𝐶𝐶 + 𝑏𝑏 1 3
( 𝑆𝑆𝑆𝑆 𝐶𝐶 )^3 + 𝑏𝑏 1 4
( 𝑆𝑆𝑆𝑆 𝐶𝐶 )^2 + 𝑏𝑏 1 5
𝑆𝑆𝑆𝑆 𝐶𝐶 + 𝑏𝑏 1 6

𝑅𝑅 𝑠𝑠 = 𝑏𝑏 2 1
𝑒𝑒 𝑏𝑏 2 2
⋅𝑆𝑆 𝑆𝑆 𝐶𝐶 + 𝑏𝑏 2 3

𝑅𝑅 𝑐𝑐 𝑠𝑠 = 𝑏𝑏 3 1
𝑒𝑒 𝑏𝑏 3 2
⋅𝑆𝑆 𝑆𝑆 𝐶𝐶 + 𝑏𝑏 3 3
, 𝐶𝐶 𝑐𝑐 𝑠𝑠 = 𝑏𝑏 4 1
𝑒𝑒 𝑏𝑏 4 2
⋅ 𝑆𝑆 𝑆𝑆 𝐶𝐶 + 𝑏𝑏 4 3

𝑅𝑅 𝑐𝑐 𝑐𝑐 = 𝑏𝑏 5 1
𝑒𝑒 𝑏𝑏 5 2
⋅ 𝑆𝑆 𝑆𝑆 𝐶𝐶 + 𝑏𝑏 5 3
, 𝐶𝐶 𝑐𝑐 𝑐𝑐 = 𝑏𝑏 6 1
𝑒𝑒 𝑏𝑏 6 2
⋅𝑆𝑆 𝑆𝑆 𝐶𝐶 + 𝑏𝑏 6 3

(2)
The OCV and CCV of a battery are generally not equal to each other. Figure 3.1
shows that the difference between them is the voltage drop on internal resistances 𝑅𝑅 𝑠𝑠 ,
𝑅𝑅 𝑐𝑐 𝑠𝑠 , and 𝑅𝑅 𝑐𝑐 𝑐𝑐 ,

𝑉𝑉 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) = 𝑉𝑉 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) + 𝑉𝑉 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) + 𝑉𝑉 𝑐𝑐 𝑠𝑠 ( 𝑡𝑡 ) + 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 ( 𝑡𝑡 ) ⋅ 𝑅𝑅 𝑠𝑠 , charging
𝑉𝑉 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) = 𝑉𝑉 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) − 𝑉𝑉 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) − 𝑉𝑉 𝑐𝑐 𝑠𝑠 ( 𝑡𝑡 ) − 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 ( 𝑡𝑡 ) ⋅ 𝑅𝑅 𝑠𝑠 , discharging
(3)
We justify this model by comparing simulation results to realistic measurements on

Figure 3.1. Li-ion battery model used in our work based on [43].

Figure 3.2. Validation of circuit model in [43] by comparing simulation results with the measured
battery terminal voltage of two serial-connected 350 mAh Li-ion batteries.
0.2 0.4 0.6 0.8 1
7
7.5
8
8.5
9
SoC
V
CC
(V)

Measurement
Simulation
20

Li-ion battery, as shown in Figure 3.2. Lead-acid batteries are modeled with a same
circuit-model but with different sets of parameters.
The rate capacity effect of batteries describes how the available charge in a battery
relates to the magnitude of the discharging current [86]. The Peukert’s Law is an
empirical relation that accurately relates the discharging time and discharging current to
the change of the battery charge. This law is described as Δ 𝐶𝐶 𝑏𝑏 = � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 �
𝛾𝛾 𝑑𝑑 ⋅ 𝑡𝑡 , where 𝑡𝑡 is
the discharging time, and 𝛾𝛾 𝑑𝑑 is the Peukert constant (1.05 and 1.3 depending on the
battery type). A similar relationship can be approximately used for the charging process
except that Peukert constant for charging, 𝛾𝛾 𝑐𝑐 is less than 1. Thus we have,

𝐼𝐼 𝑠𝑠 𝑒𝑒 = � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 �
𝛾𝛾 𝑐𝑐 or 𝐼𝐼 𝑠𝑠 𝑒𝑒 = � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 �
𝛾𝛾 𝑑𝑑
𝑆𝑆𝑆𝑆 𝐶𝐶 ( 𝑡𝑡 ) = 𝑆𝑆𝑆𝑆 𝐶𝐶 (0) + �
𝐼𝐼 𝑠𝑠 𝑒𝑒 ( 𝜏𝜏 ) − 𝐼𝐼 𝑠𝑠 𝑑𝑑 ( 𝜏𝜏 )
𝐶𝐶 𝑏𝑏 , 𝑓𝑓 𝑓𝑓 𝑐𝑐𝑐𝑐
⋅
𝑐𝑐 0
𝑑𝑑𝜏𝜏
(4)
where 𝐼𝐼 𝑠𝑠 𝑒𝑒 in (4) is the equivalent charging current inside the EES array, considering the
rate capacity effect. The 𝐼𝐼 𝑠𝑠 𝑒𝑒 reflects the rate that a battery sends or receives charge. (4)
shows that 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 is a convex function of 𝐼𝐼 𝑠𝑠 𝑒𝑒 . Typically, 𝐼𝐼 𝑠𝑠 𝑑𝑑 is very small in batteries.
Figure 3.3 shows the rate capacity effect in a Li-ion battery. One can see that the

Figure 3.3. The battery terminal voltage changes as the discharging time (SoC decreases). Data is
taken by discharging a 350 mAh 2-cell series lithium-ion GP1051L35 [85].
21

available capacity of the GP1051L35 battery decreases when the discharging rate
increases.
3.1.2 Battery Aging Model
According to the model in [16], the rate of SoH degradation depends on the average SoC
level and SoC swing. We consider a time interval of [0, 𝜏𝜏 ] and calculate the average and
standard deviation of SoC as,

𝑆𝑆𝑆𝑆 𝐶𝐶 𝑐𝑐 𝑎𝑎𝑎𝑎 = � 𝑆𝑆𝑆𝑆 𝐶𝐶 ( 𝑡𝑡 )
𝑑𝑑𝑡𝑡 𝜏𝜏 𝜏𝜏 0

𝑆𝑆𝑆𝑆 𝐶𝐶 𝑑𝑑 𝑠𝑠 𝑎𝑎 = 2 � 3 � � 𝑆𝑆𝑆𝑆 𝐶𝐶 ( 𝑡𝑡 ) − 𝑆𝑆𝑆𝑆 𝐶𝐶 𝑐𝑐 𝑎𝑎𝑎𝑎 �
2
𝜏𝜏 0
𝑑𝑑𝑡𝑡 𝜏𝜏
(5)
𝑆𝑆𝑆𝑆 𝐶𝐶 𝑑𝑑 𝑠𝑠 𝑎𝑎 is normalized to have the value of 1.0 for the full 100% depth of discharge cycle,
i.e. SoC ranges from 1.0 down to 0 and back to 1.0. 𝑆𝑆𝑆𝑆 𝐶𝐶 𝑑𝑑 𝑠𝑠 𝑎𝑎 can be used to approximately
describe the SoC swing if the battery SoC increases and decreases steadily. The battery
may have multiple charges and discharges due to the different magnitude of operation
current during the time interval 𝜏𝜏 . Thus we compute the effective throughput number of
cycle 𝑁𝑁 as follows,
𝑁𝑁 = �
| 𝐼𝐼 ( 𝑡𝑡 )| 𝑑𝑑 𝑡𝑡 2 𝑄𝑄 𝑛𝑛 𝜏𝜏 0
(6)
where 𝐼𝐼 ( 𝑡𝑡 ) is the charging/discharging current of the battery, which is 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝐵𝐵 ( 𝑡𝑡 ) in (3)(4),
𝑄𝑄 𝑛𝑛 is the nominal charge capacity of the battery. The SoH degradation during this time
interval, accounting the average SoC level and SoC swing, is given by,
𝐿𝐿 1
= 𝐾𝐾 𝑐𝑐 𝑆𝑆 ⋅ 𝑁𝑁 ⋅ exp �
( 𝑆𝑆𝑆𝑆 𝐶𝐶 𝑑𝑑 𝑠𝑠 𝑎𝑎 − 1) 𝑇𝑇 𝑐𝑐 𝑠𝑠𝑓𝑓
𝐾𝐾 𝑠𝑠 𝑒𝑒 𝑇𝑇 𝐵𝐵 � + 0.2
𝜏𝜏 𝜏𝜏 𝑐𝑐 𝑐𝑐 𝑓𝑓 𝑠𝑠 (7)
22

𝐿𝐿 2
= 𝐿𝐿 1
⋅ exp[4( 𝑆𝑆𝑆𝑆 𝐶𝐶 𝑑𝑑 𝑠𝑠 𝑎𝑎 − 0.5) 𝐾𝐾 𝑆𝑆 𝑆𝑆 𝐶𝐶 ] ⋅ (1 − 𝐿𝐿 )
𝐿𝐿 3
= 𝐿𝐿 2
⋅ exp � 𝐾𝐾 𝑇𝑇 � 𝑇𝑇 𝐵𝐵 − 𝑇𝑇 𝑐𝑐𝑠𝑠 𝑓𝑓 � 𝑇𝑇 𝑐𝑐𝑠𝑠 𝑓𝑓 𝑇𝑇 𝐵𝐵 �
where the empirical constants 𝐾𝐾 𝑐𝑐 𝑆𝑆 , 𝐾𝐾 𝑠𝑠 𝑒𝑒 , 𝐾𝐾 𝑆𝑆 𝑆𝑆 𝐶𝐶 and 𝐾𝐾 𝑇𝑇 are battery specific [19], 𝑇𝑇 𝑐𝑐𝑠𝑠 𝑓𝑓 and
𝑇𝑇 𝐵𝐵 is the reference battery temperature and operation battery temperature, respectively,
and 𝜏𝜏 𝑐𝑐 𝑐𝑐 𝑓𝑓 𝑠𝑠 is the calendar life to 80% SoH. If the 𝑛𝑛 -th full cycle of contains 𝑀𝑀 time
intervals, the SoH degradation is calculated as,

𝛥𝛥 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑓𝑓 𝑐𝑐 ( 𝑛𝑛 , 𝑇𝑇 𝑏𝑏 ) = � 𝐿𝐿 3
( 𝑚𝑚 )
𝑀𝑀 𝑚𝑚 = 1

𝑆𝑆𝑆𝑆 𝐻𝐻 ( 𝑛𝑛 + 1) = 𝑆𝑆𝑆𝑆 𝐻𝐻 ( 𝑛𝑛 ) − 𝛥𝛥 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑓𝑓 𝑐𝑐 ( 𝑛𝑛 , 𝑇𝑇 𝑏𝑏 )
(8)
In (8), the normalized SoH degradation L will change over the life of battery from 0
(brand new) to 1.0 (no capacity left). Typically, the value of L=0.2, giving nominally
80% charge capacity, can be used as a measure of end of useful life. The relations of SoH
degradation versus SoC swing and average SoC level is shown in Figure 3.4. A cycle is
defined as a charging process and a discharging process right after it (i.e., SoC ramps up
then back to original value). We can vary the duration of a cycle to achieve different
average SoC levels and SoC swings. We repeat such charging and discharging cycle until
the battery reaches L=0.2 and record the total number of cycles at that time. The results
are shown in Figure 3.4. There are three important observations from Figure 3.4: more
severe SoH degradation is caused by 1) bigger SoC swing and 2) larger average SoC
level in each cycle. 3) The improvement of cycle life has a super linear relation with
respect to the reduction of SoC swing and average SoC.
23

It is known that battery ages much faster at elevated temperatures. Figure 3.5 shows
the simulated SoH degradation process. The battery ages much faster at higher
temperature. The model we adopt only captures the SoH degradation based on how many
cycles that the Li-ion battery has been used. However, a detailed model is required to
study the SoH degradation within one cycle since temperatures are different from time to
time. To address this issue, we break one cycle into a number of short, consecutive time
slots and assume the SoH degradation in each time slot is proportional to the amount of
battery SoC loss during that time slot. We calculate the temperature correction for SoH
degradation according to the actual battery temperature during that time slot. In this way,
we are able to evaluate the SoH degradation at different cycling rates and temperatures.

Figure 3.4. SoH degradation versus SoC swing (at different average SoC levels) and average SoC (at
different SoC swings).
0.2 0.3 0.4 0.5 0.6 0.7
0
2
4
x 10
4
SoC swing
Number of cycles

30%
40%
50%
60%
70%
0.3 0.4 0.5 0.6
0
1
2
x 10
4
average SoC
Number of cycles

40%
45%
50%
55%
60%
24

3.1.3 Battery Thermal Model
The general thermal model of a Li-ion battery is very complex due to the non-uniform
internal temperature distribution. Since we target the small size Li-ion batteries, and the
temperature variation inside the battery is negligible [21], we use the temperature at the
battery surface as the battery temperature. The charge and discharge reactions for Li-ion
secondary battery are endothermic and exothermic, respectively. The thermal behaviors
of the Li-ion batteries have been extensively studied [52, 55, 87]. At the system level, we
assume the chemical reaction is reversible so that the total heat generation has two
components: entropy heat change 𝑄𝑄 ̇ 𝑠𝑠 and ohmic heat change 𝑄𝑄 ̇ 𝑐𝑐 [21],

𝑄𝑄 ̇ 𝑠𝑠 = −| 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 | 𝑇𝑇 𝑏𝑏 𝜕𝜕 𝑉𝑉 𝑂𝑂 𝐶𝐶 𝜕𝜕 𝑇𝑇 𝑏𝑏
𝑄𝑄 ̇ 𝑐𝑐 = 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 2
⋅ 𝑅𝑅 𝑐𝑐 𝑛𝑛𝑐𝑐
= 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 2
⋅ ( 𝑅𝑅 𝑠𝑠 + 𝑅𝑅 𝑐𝑐 𝑐𝑐 + 𝑅𝑅 𝑐𝑐 𝑠𝑠 )
(9)
where 𝑅𝑅 𝑐𝑐 𝑛𝑛𝑐𝑐
is the total internal resistance of the Li-ion battery and 𝑇𝑇 𝑏𝑏 is the battery
temperature. The reaction directions for charge and discharge are opposite to each other,
i.e., 𝜕𝜕 𝑉𝑉 𝑂𝑂 𝐶𝐶 /𝜕𝜕 𝑇𝑇 𝑏𝑏 > 0 for charge and 𝜕𝜕 𝑉𝑉 𝑂𝑂 𝐶𝐶 /𝜕𝜕 𝑇𝑇 𝑏𝑏 < 0 for discharge. The 𝑅𝑅 𝑐𝑐 𝑛𝑛𝑐𝑐
in (9) is not
fixed but increases as SoC decreases during the discharge [21].

Figure 3.5. Simulated SoH degradation versus cycle numbers at different battery temperatures with
environment temperature of 25°C.
0 500 1000 1500 2000
0
20
40
60
Number of Cycles
SoH Degradation %

25 °C
35 °C
45 °C
55 °C
25

The battery temperature change rate is related to the heat generation and diffusion at
the battery surface as follows,

𝑚𝑚 𝑏𝑏 𝐶𝐶 𝑐𝑐 𝑑𝑑𝑇𝑇 𝑑𝑑𝑡𝑡 = − ℎ 𝐴𝐴 𝑠𝑠 𝑓𝑓𝑓𝑓
( 𝑇𝑇 𝑏𝑏 − 𝑇𝑇 𝑐𝑐 ) + 𝑄𝑄 ̇ 𝑠𝑠 + 𝑄𝑄 ̇ 𝑐𝑐
(10)
where the 𝑚𝑚 𝑏𝑏 is battery mass, 𝐶𝐶 𝑐𝑐 is the specific heat capacity ( 𝐽𝐽𝐽𝐽 𝑔𝑔 − 1
𝐾𝐾 − 1
) of the Li-ion
battery, 𝐴𝐴 𝑠𝑠 𝑓𝑓𝑓𝑓
is the effective surface area of the Li-ion battery, ℎ is the heat transfer
coefficient ( 𝑊𝑊 𝑚𝑚 − 2
𝐾𝐾 − 1
) between the battery surface and air, and 𝑇𝑇 𝑐𝑐 is the ambient
temperature. The accepted value of h for small size Li-ion battery is about 5~10
𝑊𝑊 𝑚𝑚 − 2
𝐾𝐾 − 1
[21, 54]. The first term in RHS of (10) shows the heat diffusion in the
condition of natural convection. We simulate the thermal behaviors of a small size Li-ion
battery during discharge at different discharge rates and show the results in Figure 3.6.

Figure 3.6. Simulated battery temperatures at different discharge rates during continuous discharge
process in the condition of natural convection.
0 0.2 0.4 0.6 0.8 1
20
40
60
80
State of Charge
Temperature / °C

0.2C
0.5C
1C
2C
26

Using a forced convection cooling mechanism significant helps the heat diffusion of
the battery. We derive our thermal diffusion model based on the two-term thermal
resistance model for heat sinks [70]. In this model, the total thermal resistance consists of
two thermal resistors in series: i) the resistor relates to heat transfer between the prime
material and the finned heat sink, and ii) the resistor relates to the forced-convection. In
this work, we modify the original two-term thermal resistance model and assume two
thermal resistors connected in parallel: one natural convection resistor (relates to the
bottom surface) and one forced convection resistor (relates to the fan). Thus, (10),

𝑚𝑚 𝑏𝑏 𝐶𝐶 𝑐𝑐 𝑑𝑑𝑇𝑇 𝑑𝑑𝑡𝑡 = −
( 𝑇𝑇 𝑏𝑏 − 𝑇𝑇 𝑐𝑐 )
𝑅𝑅 𝑐𝑐 ℎ
+ 𝑄𝑄 ̇ 𝑠𝑠 + 𝑄𝑄 ̇ 𝑐𝑐
𝑅𝑅 𝑐𝑐 ℎ
=
1
ℎ 𝐴𝐴 𝑠𝑠 𝑓𝑓𝑓𝑓
||
1
2 𝑚𝑚 ̇ 𝑐𝑐 𝑐𝑐𝑐𝑐
,
(11)
where 𝑐𝑐 𝑐𝑐𝑐𝑐
is the specific heat capacity of the air and 𝑚𝑚 ̇ is the mass flow rate of the air,
which depends on the fan speed and the shape of air channel. The energy consumed by
the fan has a super-linear relation with respect to the fan speed [84]. Figure 3.7 shows the

Figure 3.7. Thermal resistance and power consumptions of the 4-cell battery pack (22650M LiMnNi
battery) with a 70mm fan at different fan speeds.
0
3
6
9
12
15
18
Rotations per Minute
Thermal resistance / KW
-1

0 500 1000 1500 2000 2500 3000
0
1
2
3
4
5
6
Power / W
Thermal Resistance
Power Consumption
27

simulated battery thermal resistance and cooling fan power consumptions at different fan
speeds.
3.2 Supercapacitors
The supercapacitor is another representative EES element that has relatively lower energy
density, but superior cycle efficiency and much longer cycle life compared to batteries.
Thus, the supercapacitor banks are commonly used to deal with the peak power demand
or supply. The rate capacity effect is negligible in supercapacitor and we have 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 ≈
𝐼𝐼 𝑠𝑠 𝑒𝑒 . The electrical circuit model for the supercapacitor used in this paper contains a low
series resistance ( 𝑅𝑅 𝑠𝑠 𝑠𝑠 𝑐𝑐 𝑐𝑐 𝑠𝑠𝑠𝑠
~25m Ω in [85]). Therefore, the following relation between
𝑉𝑉 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) and 𝑉𝑉 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) holds for the supercapacitors,

𝑉𝑉 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) = 𝑉𝑉 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) + 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 ( 𝑡𝑡 ) ⋅ 𝑅𝑅 𝑠𝑠 𝑠𝑠 𝑐𝑐 𝑐𝑐 𝑠𝑠𝑠𝑠
, charging
𝑉𝑉 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) = 𝑉𝑉 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) − 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 ( 𝑡𝑡 ) ⋅ 𝑅𝑅 𝑠𝑠 𝑠𝑠 𝑐𝑐 𝑐𝑐 𝑠𝑠𝑠𝑠
, discharging
(12)
A fundamental disadvantage of the supercapacitor is the high self-discharge rate
compared with other EES elements. A supercapacitor typically loses more than 20% of
its stored energy per day due to self-discharge [88]. The voltage decay of a
supercapacitor for a short time interval 𝛥𝛥 𝑡𝑡 is given by:

𝑉𝑉 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 + Δ 𝑡𝑡 ) = 𝑉𝑉 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝑒𝑒 −
Δ 𝑐𝑐 𝜏𝜏 𝑠𝑠 𝑑𝑑
(13)
where 𝜏𝜏 𝑠𝑠 𝑑𝑑 is self-discharge time constant. Using Taylor Expansion, the power loss rate
due to self-discharge is given by:
𝑃𝑃 𝑠𝑠 𝑑𝑑 ( 𝑡𝑡 ) = 𝐶𝐶 𝑐𝑐𝑐𝑐𝑐𝑐
( 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ))
2
𝜏𝜏 𝑠𝑠 𝑑𝑑 (14)

28

3.3 Power Converters
We use a pulse width modulation (PWM) buck-boost converter model as the charger
model. The input voltage, input current, output voltage and output current of the charger
are denoted by 𝑉𝑉 𝑐𝑐 𝑛𝑛 , 𝐼𝐼 𝑐𝑐 𝑛𝑛 , 𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
, and 𝐼𝐼 𝑆𝑆 𝑓𝑓𝑐𝑐
, respectively. A charger has two working modes:
buck mode (if 𝑉𝑉 𝑐𝑐 𝑛𝑛 > 𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
) and boost mode otherwise. When the charger is turned on, the
power loss 𝑃𝑃 𝑐𝑐 of the charger consists of three components: conduction loss 𝑃𝑃 𝑐𝑐 𝑑𝑑 𝑐𝑐𝑐𝑐
,
switching loss 𝑃𝑃 𝑠𝑠𝑠𝑠
, and controller loss 𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 . The power loss of the charger is zero when
the charger is turned off. Note that 𝑃𝑃 𝑠𝑠𝑠𝑠
and 𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 are non-zero and not proportional to the
output power. We adopt a binary indication variable 𝑥𝑥 𝑐𝑐 such that 𝑥𝑥 𝑐𝑐 = 1 if the charger is
turned on, and 𝑥𝑥 𝑐𝑐 = 0 otherwise. Thus 𝑃𝑃 𝑐𝑐 is given by:

𝑃𝑃 𝑐𝑐 = 𝑃𝑃 𝑐𝑐 𝑆𝑆 𝑛𝑛 ⋅ 𝑥𝑥 𝑐𝑐 = ( 𝑃𝑃 𝑐𝑐 𝑑𝑑 𝑐𝑐𝑐𝑐
+ 𝑃𝑃 𝑠𝑠𝑠𝑠
+ 𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 ) ⋅ 𝑥𝑥 𝑐𝑐
(15)
Figure 3.8 shows a schematic of a PWM buck-boost converter. It consists of four
switching MOSFETs whose ON-OFF states determine the operation mode of the
converter. The power loss components are mainly determined by the PWM duty ratio 𝐷𝐷
(less than 1), the maximum current ripple Δ 𝐼𝐼 , the switching frequency 𝑓𝑓 𝑠𝑠 , the controller
current 𝐼𝐼 𝑐𝑐 𝑆𝑆 𝑛𝑛 𝑐𝑐 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑠𝑠 𝑐𝑐 , the equivalent series resistances 𝑅𝑅 𝐿𝐿 and 𝑅𝑅 𝐶𝐶 , and the turn-on resistance

Figure 3.8. Circuit-based model of the boost-buck model.
29

and gate charge of the 𝑖𝑖 -th MOSFET switch, 𝑅𝑅 𝑠𝑠𝑠𝑠 𝑐𝑐 and 𝑄𝑄 𝑠𝑠𝑠𝑠 𝑐𝑐 . In the buck mode, we adopt
the power loss model in [89] as follows,

𝐷𝐷 =
𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
𝑉𝑉 𝑐𝑐 𝑛𝑛 , Δ 𝐼𝐼 =
𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
( 1 − 𝐷𝐷 )
𝐿𝐿 𝑓𝑓 ⋅ 𝑓𝑓 𝑠𝑠
𝑃𝑃 𝑐𝑐 𝑑𝑑 𝑐𝑐𝑐𝑐
= ( 𝐼𝐼 𝑆𝑆 𝑓𝑓𝑐𝑐
)
2
⋅ ( 𝑅𝑅 𝐿𝐿 + 𝐷𝐷 ⋅ 𝑅𝑅 𝑠𝑠𝑠𝑠 1
+ (1 − 𝐷𝐷 ) ⋅ 𝑅𝑅 𝑠𝑠𝑠𝑠 2
+ 𝑅𝑅 𝑠𝑠𝑠𝑠 4
)
+
( Δ 𝐼𝐼 )
2
12
⋅ ( 𝑅𝑅 𝐿𝐿 + 𝐷𝐷 ⋅ 𝑅𝑅 𝑠𝑠𝑠𝑠 1
+ (1 − 𝐷𝐷 ) ⋅ 𝑅𝑅 𝑠𝑠𝑠𝑠 2
+ 𝑅𝑅 𝑠𝑠𝑠𝑠 4
+ 𝑅𝑅 𝐶𝐶 ),
𝑃𝑃 𝑠𝑠𝑠𝑠
= 𝑉𝑉 𝑐𝑐 𝑛𝑛 ⋅ 𝑓𝑓 𝑠𝑠 ⋅ ( 𝑄𝑄 𝑠𝑠𝑠𝑠 1
+ 𝑄𝑄 𝑠𝑠𝑠𝑠 2
),
𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 = 𝑉𝑉 𝑐𝑐 𝑛𝑛 ⋅ 𝐼𝐼 𝑐𝑐 𝑆𝑆 𝑛𝑛 𝑐𝑐 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑠𝑠 𝑐𝑐 .
(16)
Note that in (16), the switching loss 𝑃𝑃 𝑠𝑠𝑠𝑠
and controller loss 𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 are independent of 𝐼𝐼 𝑆𝑆 𝑓𝑓𝑐𝑐
.
We derive the power loss in boost mode based on the power loss in buck mode:

𝐷𝐷 = 1 −
𝑉𝑉 𝑐𝑐 𝑛𝑛 𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
, Δ 𝐼𝐼 =
𝑉𝑉 𝑐𝑐 𝑛𝑛 𝐷𝐷 𝐿𝐿 𝑓𝑓 ⋅ 𝑓𝑓 𝑠𝑠
𝑃𝑃 𝑐𝑐 𝑑𝑑 𝑐𝑐𝑐𝑐
= �
𝐼𝐼 𝑆𝑆 𝑓𝑓𝑐𝑐
1 − 𝐷𝐷 �
2
⋅ ( 𝑅𝑅 𝐿𝐿 + 𝐷𝐷 𝑅𝑅 𝑠𝑠𝑠𝑠 3
+ (1 − 𝐷𝐷 ) 𝑅𝑅 𝑠𝑠𝑠𝑠 4
+ 𝑅𝑅 𝑠𝑠𝑠𝑠 1
+ 𝐷𝐷 (1 − 𝐷𝐷 ) 𝑅𝑅 𝐶𝐶 )
+
( Δ 𝐼𝐼 )
2
12
⋅ ( 𝑅𝑅 𝐿𝐿 + 𝐷𝐷 ⋅ 𝑅𝑅 𝑠𝑠𝑠𝑠 3
) + (1 − 𝐷𝐷 ) ⋅ 𝑅𝑅 𝑠𝑠𝑠𝑠 4
+ 𝑅𝑅 𝑠𝑠𝑠𝑠 1
+ (1 − 𝐷𝐷 ) ⋅ 𝑅𝑅 𝐶𝐶 ),
𝑃𝑃 𝑠𝑠𝑠𝑠
= 𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
⋅ 𝑓𝑓 𝑠𝑠 ⋅ ( 𝑄𝑄 𝑠𝑠𝑠𝑠 3
+ 𝑄𝑄 𝑠𝑠𝑠𝑠 4
), 𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 = 𝑉𝑉 𝑐𝑐 𝑛𝑛 ⋅ 𝐼𝐼 𝑐𝑐 𝑆𝑆 𝑛𝑛 𝑐𝑐 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑠𝑠 𝑐𝑐 .
(17)

Figure 3.9. Validation of converter model (16)(17) with measured LTM4607 data.
0.01 0.1 1 3
20
40
60
80
100
I
out
(A)
Charger Efficiency (%)

Simulation
Measurement
30

We extract the model parameters based on LTM4607 converter [90] and compare the
simulated and measured conversion efficiency in Figure 3.9.
Figure 3.10 shows the efficiency of a DC-DC converter at different 𝑉𝑉 𝑐𝑐 𝑛𝑛 , 𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
, and
𝐼𝐼 𝑆𝑆 𝑓𝑓𝑐𝑐
. One can see that the effeminacy increases with the output current when 𝐼𝐼 𝑆𝑆 𝑓𝑓𝑐𝑐
is low,
and saturates for large 𝐼𝐼 𝑆𝑆 𝑓𝑓𝑐𝑐
. Highest efficiency occurs when 𝑉𝑉 𝑐𝑐 𝑛𝑛 is close to 𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
.

Figure 3.10. Converter efficiency at different input voltage, output voltage, and output current.
0
2
4
6
8
0
2
4
6
8
0.4
0.5
0.6
0.7
0.8
0.9
1
V
i
DC-DC Converter Efficiency
V
o
0.5A
1A
2A
31

SECTION II HYBRID ELECTRICAL
ENERGY STORAGE SYSTEMS

CHAPTER 4
INTRODUCTION TO HYBRID ELECTRICAL ENERGY
STORAGE SYSTEMS
Conventional EES systems only consist of a single type of EES element. Unfortunately,
no available EES element can fulfill all the desired performance metrics of an ideal
storage means, e.g., high power/energy density, low cost/weight per unit capacity, high
round-trip efficiency, and long cycle life. An obvious shortcoming of a homogeneous
EES system is that the key figures of merit (normalized with respect to capacity) of the
system cannot be any better than those of its constituent EES element.
An HEES system is consisting of different types of EES elements (e.g., batteries and
supercapacitors), where each type has its unique strengths and weaknesses. The HEES
system can exploit the strength of each type of EES element and achieve a combination
of performance metrics that is superior to that of any of its individual EES components.
Based on the properties of the HEES system and characteristics of power sources (or load
devices), we developed charge management policies (such as charge allocation, charge
replacement, charge migration and bank re-configuration) to operate HEES system
properly to achieve a near-optimal performance.
32

The chapter introduces the HEES system in details. The Chapter 4 shows a single-bus
architecture of the HEES system. Chapter 4.2 presents the design challenges in the HEES
systems, from both software and hardware sides. The basic operations in a HEES system
is presented in Chapter 4.3. Chapter 4.4 shows a HEES prototype that we built to
demonstrate benefits in energy efficiency brought by the hybrid concept and our
management policies. Notation used in this chapter are summarized in Table 4.1.
Table 4.1. Notation used in Chapter 6.
Symbol Definition
𝑆𝑆 Full set of all EES banks in HEES system
𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ) Selection set among all EES banks in HEES system
𝑆𝑆𝑆𝑆 𝐶𝐶 𝑘𝑘 ( 𝑡𝑡 ) State of charge of the 𝐽𝐽 -th EES array
𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) Open circuit voltage (OCV) of the 𝐽𝐽 -th EES array
𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) Closed circuit voltage (CCV) of the 𝐽𝐽 -th EES array
𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) Voltage level on the charge transfer interconnect
𝑉𝑉 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) Output voltage at the terminal of the power source
𝑃𝑃 𝑑𝑑 , 𝑠𝑠 𝑖𝑖 ( 𝑡𝑡 ) Power loss in 𝑗𝑗 -th source-to-CTI converter
𝑃𝑃 𝑑𝑑 , 𝑐𝑐 𝑖𝑖 ( 𝑡𝑡 ) Power loss in 𝑗𝑗 -th CTI-to-load converter
𝑃𝑃 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 ) Power loss in charging control charger in the 𝐽𝐽 -th EES bank
𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑘𝑘 ( 𝑡𝑡 ) Power loss due to the self-discharge in the 𝐽𝐽 -th EES bank
𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ) Bank charging current of the 𝐽𝐽 -th bank, seen at the input of charger
𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 )
Array charging current of the 𝐽𝐽 -th bank, seen at the output of
charger

33

4.1 HEES System Architecture
Figure 4.1 shows the system architecture of the proposed HEES system. The system
contains 𝑁𝑁 heterogeneous EES banks. Each EES bank is connected to each other via the
CTI. An EES bank includes a set of homogeneous EES elements and a bidirectional
converter since a typical EES element has a low voltage rating and a small energy
capacity. These EES elements are organized in an appropriately constructed two-
dimensional array using reconfigurable series and/or parallel connections. The
bidirectional converters control the voltage and current when charging or discharging the
EES array since there is generally a voltage difference between the CTI and the EES
array. The bidirectional converters support the following two operation modes: 1) voltage
regulation mode, the bidirectional converter generates a desirable output voltage
Bidirectional
Converter
Bidirectional
Converter
AC-DC
Rectifier
Unidirectional
Converter
Unidirectional
Converter
DC-DC
Converter
DC-AC
Inverter
Charge Transfer Interconnect (CTI)
Power Grid
DC Sources DC Loads AC Loads
I
array,1
EES Bank 1 EES Bank 2
I
array,2
I
bank,1
I
bank,2
V
CTI
P
SRC,1
V
SRC,1
P
SRC,2
V
SRC,2
V
CC
array,2
V
CC
array,1
V
OC
array,1
V
OC
array,2
P
sd,2
P
load,1
V
load,1 P
load,2
V
load,2
P
c,2
P
c,s1
P
c,l1
P
c,s1
P
c,l2
C
CTI
Energy Flow
Control
Signal
Contro-
ller
...
Charge
Management
Policies

Figure 4.1. Architecture of the proposed HEES system.
34

regardless of the variation of the input power; and 2) current regulation mode, the
bidirectional converter generates a desirable output current regardless of the variation of
the input power. We refer to it as a charger if the converter is in this mode. The DC and
AC power sources are connected to the HEES system using the unidirectional converters
that only allow current flows onto the CTI. We use DC-DC converters and DC-AC
inverters for the load devices to maintain the compatibility of the voltage-levels between
the CTI and load devices.
In our problem setup, the HEES system is comprised of 𝑁𝑁 inhomogeneous EES
banks, denoted by a set 𝑆𝑆 = {1, 2, . . . , 𝑁𝑁 }. The charging or discharging process starts at
time 𝑡𝑡 = 𝑇𝑇 𝑠𝑠 and ends at time 𝑡𝑡 = 𝑇𝑇 𝑠𝑠 . At any time instance, a subset of all EES banks
𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ) ∈ 𝑆𝑆 is turned on and provides power to CTI through their chargers. We use
𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) and 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) to denote the open circuit terminal voltage (OCV) and the
closed circuit terminal voltage (CCV) of EES element array in the 𝐽𝐽 -th bank,
respectively. Because of the internal resistance of the EES array, these two voltages are
generally not equal. The SoC of each EES array is denoted by 𝑆𝑆𝑆𝑆 𝐶𝐶 𝑘𝑘 ( 𝑡𝑡 ). We denote he
voltage level settings of the CTI by 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ( 𝑡𝑡 ). The power supply (load demand) and voltage
of the 𝑗𝑗 -th source (load devices) are denoted by 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 , 𝑖𝑖 ( 𝑡𝑡 ) �𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) � and 𝑉𝑉 𝑠𝑠 𝑐𝑐 𝑐𝑐 , 𝑖𝑖 ( 𝑡𝑡 )
�𝑉𝑉 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) �.
The charging/discharging rate of each EES array is controlled by the charger in that
bank. The upstream and downstream of a charger are the CTI and the EES array during
the bank charging, respectively, and reversely during the bank discharging. Each charger
35

sets its downstream current to the desired level determined by the charge replacement
policy. We name the current between the 𝐽𝐽 -th charger and the CTI as bank
charging/discharging current, denoted by 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ), as it flows between the EES bank to
the CTI. Meanwhile, the current between the 𝐽𝐽 -th charger and its EES array is named as
array charging/discharging current, denoted by 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 . We account for the self-
discharge power loss, 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑘𝑘 ( 𝑡𝑡 ), in the 𝐽𝐽 -th supercapacitor bank, conversion power loss in
the 𝐽𝐽 -th charger, 𝑃𝑃 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 ), the converter power loss for the 𝑗𝑗 -th load device 𝑃𝑃 𝑑𝑑 , 𝑐𝑐 𝑖𝑖 ( 𝑡𝑡 ), the
converter power loss for the 𝑗𝑗 -th source supply 𝑃𝑃 𝑑𝑑 , 𝑠𝑠 𝑖𝑖 ( 𝑡𝑡 ).
The charge management policies control the EES bank reconfiguration, CTI
connection, CTI voltage and charging currents/discharging current of each EES bank at
each time instance in order to achieve the best HEES system performance. We control
both the CTI voltage and charging/discharging current of EES arrays using the following
method. We operate one converter in the voltage regulation mode to determine the
desirable CTI voltage and all other converters in the current regulation mode. The output
current for the voltage regulation converter is automatically determined since the total
current flowing into CTI equals the total current flowing outward. This control scheme
ensures the stability of CTI voltage and bank currents while we generate the software-
level real-time tasks to implement the high-level charge management policies.
Ideally, the CTI voltage is determined by the power balance between the loads and
the banks. The incoming currents from the banks to CTI and the outgoing currents from
CTI to the load devices are perfectly balanced. Thus we can control the bank discharging
36

currents (array charging currents) through chargers to achieve both the load (source)
power match as well as the CTI voltage control. However, in practice, the incoming and
outgoing currents of the CTI may have discrepancy, especially during the transient period
whenever the load current changes. In such a case, the currents mismatch is accumulated
in the CTI capacitance 𝐶𝐶 𝐶𝐶 𝑇𝑇 𝐶𝐶 (mostly the input capacitors of the DC-DC converter and the
output capacitors of the chargers) and increases or decreases the CTI voltage. Thus, we
utilize the grid to maintain the CTI voltage through an AC-DC rectifier.
4.2 Design Challenges in HEES Systems
The challenges of designing a HEES system and corresponding charge management
policies to achieve desired performance metrics come from both hardware and software
sides.
4.2.1 Hardware
In the hardware side, the main challenges include,
1) How to design the HEES system so that we have the flexibility in determining the
charging or discharging current for each EES bank individually?
2) How to maintain the stability of currents and voltage settings in the HEES system
at our desired values?
3) How to determine the capacity of each EES bank considering the energy usage
patterns, system lifespan, amortized cost, and return on investment?
A well-designed system allows us to control variables of interest to our desired levels.
We address the first issue by proposing a general HEES system architecture so that each
37

EES bank is connected to a charge transfer interconnect (CTI) through its own power
converters (chargers), as shown in Figure 4.1. This architecture provides great control
flexibility because the charging/discharging current of each bank can be set
independently. The second issue is an implementation challenge. The chargers have
feedback circuits to maintain stable current settings. For the CTI voltage stability, we
connect the CTI to the grid in our prototype. The grid maintains a stable CTI voltage
through an AC-DC rectifier. To diminish the temporary voltage fluctuation when load
demands or source supplies change, we connect a large capacitor with value of
132,000uF to the CTI.
Designing a HEES system requires careful consideration of properties of EES
elements and usage profiles. Cost is first concern in designing HEES system. High
efficiency elements such as supercapacitors and Li-ion batteries are more expensive than
some elements with relative low efficiency, like lead-acid battery. The lifespan is another
important performance metric for the HEES system. How long a HEES system can last
depends on the usage of EES elements. Using large EES bank can reduce the depth of
discharge (DoD) per cycle of EES elements, which results in longer lifespan. Beside
issues of cost and lifespan, some other factors such as volume, mass, and power and
energy capability, also play important roles in designing HEES systems. Near-optimal
HEES system design strategies for households are presented in [12, 13].
38

4.2.2 Software
The software issue is how to design charge management policies to operate the system
given the HEES system specifications. The nonlinearities of the energy loss in the HEES
system is the primary reason that causes design challenges in the charge management
policies. The nonlinear energy loss terms include,
1) The available capacity for a battery decreases when they are discharged at higher
rates. This phenomenon is also known as the rate capacity effect [85, 86].
2) The conversion energy loss in power converters depends on input voltage, output
voltage, and output current. There is also a fixed non-zero amount of energy loss
in the converter when it is turned on [6, 89].
3) The rate of self-leakage energy in supercapacitor banks is proportional to the
energy stored in supercapacitors.
We divide the general operations of HEES systems into some key operations such as
charge allocation [11], charge replacement [8], and charge migration [6, 9], and provide
systematic solution method separately for each of them. For each operation, we account
for these complicated energy loss terms in our optimization framework and apply certain
approximations so that we can utilize standard convex optimization tools such that [91].
In addition to these complicated energy loss terms, the load demand and power supply
profiles are typically unknown and may even vary in a big range. Therefore, we also
include ‘power limits’ in our charge management policies, in order to globally consider
the whole process and avoid the greedy approach.
39

Designing charge management policies for HEES systems is a multi-objective
optimization problem. Besides the energy efficiency, the lifespan of a HEES system is of
the same importance. State-of-health (SoH) is a metric of measuring the aging effect of
EES elements. It is known that deep charging and discharging cycles significantly
degrade the battery health [16]. In addition, elevated temperature, which is caused by
thermal generation in batteries, speeds up the battery aging [17, 18]. Therefore,
appropriate charge management policies should account for aging and thermal effects.
4.3 Basic Operations in HEES Systems
HEES systems are used to store the excessive energy produced at certain times of the day
and provide the energy during the peak load times as needed. The general HEES system
operations are complicated because both charging and discharging processes are involved.
In order to derive the near-optimal charge management policy for the entire usage
process, we identify several key operations in the HEES system and provide systematic
solution methods for them. These key operations, though they are discussed and
optimized separately, shall be considered and performed jointly in practice.
4.3.1 Charge allocation
Global charge allocation (GCA) problem for an HEES system considers how to
distribute the given power supplies to some selected EES destination banks in the HEES
system so that the GCA efficiency is maximized [11]. The GCA efficiency is defined as,
𝜂𝜂 𝐺𝐺 𝐶𝐶 𝐺𝐺 =
𝑡𝑡 𝑆𝑆 𝑡𝑡 𝑡𝑡 𝑡𝑡 𝑒𝑒 𝑛𝑛 𝑒𝑒𝑒𝑒 𝑔𝑔 𝑒𝑒 𝑠𝑠 𝑡𝑡 𝑆𝑆 𝑒𝑒𝑒𝑒𝑑𝑑 𝑖𝑖 𝑛𝑛𝑡𝑡 𝑆𝑆 𝑡𝑡𝑡𝑡 𝑡𝑡 𝐸𝐸 𝐸𝐸 𝑆𝑆 𝑏𝑏 𝑡𝑡 𝑛𝑛𝐽𝐽 𝑠𝑠 𝑡𝑡 𝑆𝑆 𝑡𝑡 𝑡𝑡 𝑡𝑡 𝑒𝑒 𝑛𝑛 𝑒𝑒𝑒𝑒 𝑔𝑔 𝑒𝑒 𝑝𝑝 𝑒𝑒𝑆𝑆 𝑝𝑝 𝑖𝑖 𝑑𝑑𝑒𝑒𝑑𝑑 𝑏𝑏 𝑒𝑒 𝑝𝑝 𝑆𝑆 𝑝𝑝 𝑒𝑒 𝑒𝑒 𝑠𝑠 𝑠𝑠 𝑝𝑝𝑝𝑝𝑡𝑡 𝑖𝑖 𝑒𝑒 𝑠𝑠 (18)
40

This GCA efficiency is determined by properties of selected EES banks, magnitudes of
charging currents, and the states of charge’s (SoCs) of EES banks. Figure 4.2 shows a
charge allocation process, which receives energy from solar cells and stores to a two-
bank HEES system.
We consider the energy conservation and charge conservation during the charge
allocation process. In addition to the energy stored into all EES banks, we also account
for the power dissipation on internal resistances of battery banks and supercapacitor
banks, the power loss on chargers during the power conversion process, the rate capacity
effect in batteries, and the self-discharge in supercapacitors.
4.3.2 Charge replacement
Charge replacement is similar to the charge allocation problem as it is a reverse process
of the charge allocation process. The global charge replacement (GCR) problem in the

Figure 4.2. Conceptual drawing of the charge allocation process.
41

HEES system refers adaptively selecting EES banks and determining discharging
currents, from zero to a maximum limit, and voltage level settings on the CTI so that the
given load demand is met and the charge replacement efficiency is maximized [8]. Figure
4.3 shows an example of charge replacement process. Note that the global charge
replacement efficiency denotes the ratio between the energy requested by load devices
and the energy retrieved from the HEES system.
𝜂𝜂 𝐺𝐺 𝐶𝐶 𝐺𝐺 =
𝑡𝑡 𝑆𝑆 𝑡𝑡 𝑡𝑡 𝑡𝑡 𝑒𝑒 𝑛𝑛 𝑒𝑒𝑒𝑒 𝑔𝑔 𝑒𝑒 𝑒𝑒𝑒𝑒 𝑟𝑟 𝑠𝑠 𝑒𝑒𝑠𝑠𝑡𝑡 𝑒𝑒𝑑𝑑 𝑏𝑏 𝑒𝑒 𝑡𝑡 𝑆𝑆𝑡𝑡 𝑑𝑑 𝑑𝑑𝑒𝑒 𝑝𝑝 𝑖𝑖 𝑐𝑐𝑒𝑒 𝑠𝑠 𝑡𝑡 𝑆𝑆 𝑡𝑡 𝑡𝑡 𝑡𝑡 𝑒𝑒 𝑛𝑛 𝑒𝑒𝑒𝑒 𝑔𝑔 𝑒𝑒 𝑑𝑑𝑒𝑒 𝑡𝑡 𝑝𝑝 𝑛𝑛 𝑓𝑓 𝑒𝑒 𝑆𝑆𝑚𝑚 𝑡𝑡𝑡𝑡 𝑡𝑡 𝐸𝐸 𝐸𝐸 𝑆𝑆 𝑏𝑏 𝑡𝑡 𝑛𝑛𝐽𝐽 𝑠𝑠 (19)
We provide a mathematical formulation for the GCR problem and propose an
efficient algorithm to solve it near-optimally. Precisely, the GCR problem is formulated
as an optimization problem where the objective function is the GCR efficiency and
constraints are derived from laws of energy and charge conservation. We account for the
energy loss due to the internal resistance of batteries, the power conversion energy loss,
the rate capacity effect of batteries, and the self-discharge of supercapacitors. We solve

Figure 4.3. Conceptual drawing of the charge replacement process.
42

the GCR problem using convex optimization methods while imposing an output power
bound on battery banks in order to avoid discharging supercapacitor banks too quickly
(which could in turn degrade the charge replacement efficiency).
4.3.3 Charge migration
Charge migration migrates electrical energy in the HEES system internally, from one
EES bank to another. Figure 4.4 shows an example of the charge migration process, in
which the energy is moved from one EES bank to another. We see strong motivations to
perform charge migration to enhance the EES system performance. First, it alleviates the
self-discharge loss by moving stored energy to less leaky EES banks. Second, it ensures
the (energy) availability of the EES banks by controlling the SoC of various EES banks.
Finally, it improves the efficiency of the subsequent charge allocation or replacement
processes in the HEES system by pre-charging or pre-discharging appropriately selected

Figure 4.4. Conceptual drawing of the charge migration process.
43

EES banks so as to efficiently meet the dynamic power generation and load demand. The
figure of merit for the charge migration task is the charge migration efficiency, which is
defined as the ratio of the total target energy migrated to destination EES banks to the
total energy drawn from the source EES banks,
𝜂𝜂 𝐶𝐶 𝑀𝑀 =
𝑡𝑡 𝑆𝑆 𝑡𝑡 𝑡𝑡 𝑡𝑡 𝑒𝑒 𝑛𝑛 𝑒𝑒𝑒𝑒 𝑔𝑔 𝑒𝑒 𝑒𝑒𝑒𝑒𝑐𝑐𝑒𝑒 𝑖𝑖 𝑝𝑝 𝑒𝑒𝑑𝑑 𝑏𝑏 𝑒𝑒 𝑑𝑑 𝑒𝑒 𝑠𝑠 𝑡𝑡 𝑖𝑖 𝑛𝑛𝑡𝑡 𝑡𝑡 𝑖𝑖 𝑆𝑆 𝑛𝑛 𝐸𝐸 𝐸𝐸 𝑆𝑆 𝑏𝑏 𝑡𝑡 𝑛𝑛𝐽𝐽 𝑠𝑠 𝑡𝑡 𝑆𝑆 𝑡𝑡 𝑡𝑡 𝑡𝑡 𝑒𝑒 𝑛𝑛 𝑒𝑒𝑒𝑒 𝑔𝑔 𝑒𝑒 𝑑𝑑𝑒𝑒 𝑡𝑡 𝑝𝑝 𝑛𝑛 𝑓𝑓 𝑒𝑒 𝑆𝑆𝑚𝑚 𝑠𝑠 𝑆𝑆 𝑠𝑠 𝑒𝑒 𝑐𝑐𝑒𝑒 𝐸𝐸 𝐸𝐸 𝑆𝑆 𝑏𝑏 𝑡𝑡 𝑛𝑛𝐽𝐽 𝑠𝑠 (20)
There are different problem setups for the charge migration problem, depending on
the number of EES banks and CTIs involved. Single-source, single-destination (SSSD)
charge migration utilizes a single CTI during the whole migration process and does not
deal with multiple simultaneous migrations. Exhaustive search can efficiently converge
to the near-optimal solution [6]. Multiple source, multiple destination (MSMD) charge
migration moves energy to multiple destination EES banks through a (fixed) number of
(typically greater than one) CTIs, which may be overlapping in time. The MSMD
migration can significantly speed up the whole migration process and can improve the
overall charge migration efficiency [9]. The catch is that all migration tasks start at the
same time and share the same set of CTIs (thus they are bounded to use the same CTI
voltages), which can cause migration efficiency degradation if charge migration tasks are
not scheduled and assigned to various CTIs prudently. The most general situation is the
charge migration scheduling (CMS) problem, which in turn enables a number of
concurrent MSMD charge migrations through a fixed number of CTIs while meeting a
global deadline constraint [7].
44

In the CMS problem, we have a number of MSMD migration tasks, where each task
is defined as delivering a fixed amount of energy from a given set of source EES banks to
another set of destination EES banks within a deadline. The objective is to maximize the
overall charge migration efficiency. The solution to the CMS problem requires solving
the following sub-problems. First, we must determine the optimal CTI voltage and
charging current profile for each MSMD migration task. This also depends on the
duration the migration process. Second, we must decide whether two MSMD migration
tasks should be merged. Merging two migration tasks will force both of them to utilize
the same CTI, and thus, adopt the same CTI voltage during the migration process. To
ensure that the overall charge migration efficiency for the merged task is higher than
those of the individual (non-merged) migration tasks, we only allow merges between
tasks that have similar optimum CTI voltage levels. Third, we assign a CTI to the
migration task among the available CTI’s and calculate the CTI usage time, defined as
the duration the migration process. Notice that merging two migration tasks into one
reduces the resource overhead (i.e., the number of CTI’s used is reduced to one), but the
optimum realization of the merged migration task may also result in an increase in the
usage time of the shared CTI. In case of a deadline overflow, the CTI usage time for the
merged task must be reduced to the given deadline at the expense of a sub-optimal
realization of the merged migration task. Unfortunately, the optimal solutions of the three
sub-problems are not independent, but coupled with each other.
To solve the CMS problem, we start from the time-unconstrained migration problem
for each migration task and calculate the optimal migration time. Next, we reduce the
45

CTI usage time while minimizing the increase of the total energy drawn from the sources
at each step until the deadline constraint is met. During the usage time reduction, we
derive the optimal CTI voltage and charging current profile over time by using non-linear
fractional programming. We will merge multiple migration tasks if the merged migration
task yields higher migration efficiency than those of the separate ones. We converge to
the final solution for the CMS problem when all the migration tasks are scheduled to
complete by the given deadline, and no further merging can improve the charge migration
efficiency.
4.3.4 EES bank reconfiguration
The EES bank reconfiguration dynamically change the number of series- and parallel-
connected EES bank to achieve a higher charge replacement or charge allocation

Figure 4.5. EES bamk reconfiuration example.
46

efficiency, as well as improve storage capacity utilization with minimum the EES system
cost [10]. We aim to minimize the energy loss in power converters, which is primarily
due to the imbalance between the CTI voltage and the EES bank terminal voltage. To
enable the dynamic reconfiguration, we present general balanced reconfiguration
architecture for an EES bank and analyze the properties of the balanced configurations, as
shown in Figure 4.5. We also present a dynamic reconfiguration method for the proposed
reconfigurable EES banks.
4.4 A HEES Prototype
We build a HEES prototype based on our HEES architecture and implement presented
charge management policies. The photo of the prototype is shown in Figure 4.6. The

Figure 4.6. Front and rear view of the HEES prototype.
47

hardware part of the HEES prototype is comprised of three types of module: the EES
bank module, the CTI module, and the converter module. The HEES prototype provides a
high degree of freedom to transfer energy between power grid, load devices, and EES
banks. We control the CTI voltage and current of each bank individually. For the
software part, the user interface (UI) is designed using the LabVIEW and charge
management policies are implemented using the Mathscript module [92]. The UI
interface allows multiple working modes, including manual mode, in which user can
specify the current and voltage settings, and automatic mode, in which the optimal
current and voltage is determined by the implemented charge management policy.
4.4.1 Prototype overview
There are three EES bank modules, including a 6.5Wh supercapacitor [93], a 115Wh
lithium-ion battery [94], and a 163Wh lead-acid battery banks [95]. The converter
modules contains a AC-DC rectifier [96], which allows us to use AC power to charge
EES banks and maintain the CTI voltage at the desired level. A DC-AC inverter [97] is
also installed so that the EES banks can be used to support AC load. These modules are
connected through a shared-bus CTI in the CTI module. A PC running LabVIEW is
responsible for determining EES bank current and CTI voltage. The LabVIEW monitors
and system status and communicates with the bank controllers through control area
network (CAN) interface. Experiments based on the prototype demonstrate the energy
efficiency enhancements brought by the hybrid use of EES elements and effectiveness of
our charge management policies.
48

4.4.2 Prototype Design Specifications
4.4.2.1 The hardware part
Our prototype contains three types of module.
1) EES bank module: the EES bank modules are the electrical energy is stored. We
install three representative EES bank modules: one supercapacitor bank, one Li-
ion battery bank, and one lead-acid battery bank. The meters on the front panel
display the voltage and current of each EES bank. We select these three types of
EES elements as they have very distinct characteristics [4]. Supercapacitor has
superior power capacity, but high leakage rate, very low energy capacity and it is
very expensive. Li-ion battery is less expensive, but has good power capacity, low
leakage rate and ultra-high energy capacity. Lead-acid battery is even cheaper than
the Li-ion battery, while its other characteristics are inferior to those of the Li-ion
battery. Due to its high expense, the energy capacity of the supercapacitor bank is
much smaller compared to the Li-ion battery bank and lead-acid battery bank.
The specifications of the HEE banks in the prototype are listed in Table 4.2. We
Table 4.2. EES bank specifications in the HEES prototype.

49

use 14-series connected Maxwell BCAP0650 supercapacitor [93] and each of it
has capacitance of 650F. We use Samsung 18650 Li-ion battery (2,600mAh for
each cell) [94] and Panasonic LC-R123R4P lead-acid battery (3,400mAh for each
cell) [95].
2) CTI module: the CTI module is the path for charge transfer between the power
sources, load devices and EES banks. The voltage level setting in CTI affects the
power conversion efficiency of chargers and power converters. Thus, it is very
important to maintain the CTI voltage at a stable and appropriate level. We have
used an AC/DC rectifier and unidirectional power converter in our prototype
system to keep the CTI voltage stable by using the AC power source (i.e., the
Grid). In addition, we also connect a large capacitance of 132,000uF to the CTI to
keep the CTI voltage stable even in case of a rapid increase in the load demand.
We select this CTI capacitance value since it can provide stable power when the
load demand changes from 0W to 300W.
3) Converter module: This module contains an AC-DC rectifier for the grid power
input, which are used to charge EES banks and maintain stable CTI voltage. It also
contains a DC-AC inverter to support AC loads. DC/DC conversion can also be
included into the system to provide ability for DC inputs and outputs. In the HEES
prototype, we use a Mean Well SE-600-36 AC-DC rectifier [96] and a Samlex
PST-100S-24A DC-AC inverter [97].

50

4.4.2.2 The software part
The user interface is designed by using the LabVIEW. Figure 4.7 is a screenshot of the
user interface. The LabVIEW UI monitors the runtime status of the HEES prototype,
including the CTI voltage, voltage and input/output current for each EES bank, and
calculates the instantaneous charging or discharging efficiencies using these information.
The LabVIEW is also responsible for the top-level power management between the
HEES prototype and the external power sources or load devices. Currently, the power
management policies are implemented using the LabVIEW MathScript on a PC, which is
connected to the HEES prototype through the CAN bus.
The red rectangles in Figure 4.7 highlight the interactive parts where we can manually
specify the CTI voltage, charging/discharging current or charging/discharging power for

Figure 4.7. Screenshot of the LabVIEW user interface.
51

each bank. The Auto Simulation switch allows us to switch between two modes: 1)
manual mode, in which CTI voltage is set manually, and 2) auto model, in which CTI
voltage is determined using presented methods. The blue rectangles in Figure 4.7
highlight indicators that report the status of the CTI voltage, total CTI input and output
current, and terminal voltage and current for each EES bank.
4.4.3 Prototype Characterization
We perform a characterization process to obtain characteristics of each component in the
prototype. The characterization process mainly includes finding the internal resistance of
each EES bank, calculating the Peukert constant for battery banks, and obtaining
conversion efficiencies of chargers at different input and output conditions. We find that
internal resistances are roughly 0.15 𝛺𝛺 , 0.5 𝛺𝛺 , and 0.7 𝛺𝛺 for the supercapacitor bank, Li-
ion battery bank, and lead-acid battery bank, respectively. We find that the internal
resistance is quite stable except for a rapid increase when the battery SoC approaches 0 or
1. However, it only lasts for a very small range of the battery SoC. Therefore, we
approximately use fixed internal resistance values for the EES banks for the simplicity in
policy implementation. We measure the conversion efficiency of the charger at different
conditions using a NI-DAQ.
To calculate the rate capacity effect, we fully charge the Li-ion battery bank and lead-
acid battery bank, and discharge them at different rates. Due to the limitation of the
current rating of our charger boards, we do not observe significant rate capacity effect in
the Li-ion battery bank. For the lead-acid battery bank, according to the datasheet [93],
52

we charge the lead-acid bank up to 26.2V with 0.5A current, and then completely
discharge it at five different rates (0.46A, 0.59A, 0.95A, 1.14A, and 1.42A). We record
the discharging current and time before the terminal voltage reaches a stopping value,
which depends on the discharging rate, e.g., 20.4V for 0.8A. Top panel in Figure 4.8
shows the terminal voltage of the lead-acid battery decreases with time at different
discharging rates. We perform curve fitting to relate the rated capacities, which are
obtained by integrating the array discharging current over the discharging time. We
calculate the Peukert constant using (4) and obtain 𝛾𝛾 𝑐𝑐𝑠𝑠𝑐𝑐 𝑑𝑑 − 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑑𝑑 = 1.19. The fitting results
are shown in the bottom panel in Figure 4.8.

Figure 4.8. Characterization of the lead-acid battery bank (top panel), and curve fitting of the rated
capacities with respect to the discharging currents (bottom panel) to find the Peukert constant.
53

4.4.4 Experimental Results based on the HEES Prototype
4.4.4.1 Optimal CTI voltage setting
We derive the charge replacement policy, which is explained in details in Chapter 6. We
take the voltage reading, array/bank current reading, and the discharging power bound for
each EES bank as inputs, together with the pre-characterized data of charger conversion
efficiency, to determine CTI voltage, as well as the output current of each charger. To
show the effect of the optimal CTI voltage setting, we perform the discharging process
for the supercapacitor bank only and turn-off other banks. This is because that typically
the terminal voltage of the supercapacitor bank varies in a great range thus we may
expect obvious change of the optimal CTI voltage. The supercapacitor bank is charged to
36 V, then discharge for 15 minutes using a constant load demand profile. We perform
the multiple discharging processes using the proposed policy with optimal CTI voltage
setting and some baselines with fixed CTI voltages.

Figure 4.9. Changes of the terminal voltage of the supercapacitor bank over the replacement process
for the proposed policy and the baseline policies (left axis), and the optimal CTI voltage setting
achieved by the proposed CTI voltage control (right axis).
54

Figure 4.9 shows the changes of the supercapacitor voltage using the proposed policy
and baselines. One can observe that, starting from same conditions, to deliver the same
amount of energy, the remaining energy of the supercapacitor bank operated by the
proposed policy is more than the others, i.e., the solid curve is above the others three lines
that are corresponded to baseline policies. Figure 4.9 shows that the optimal CTI voltage
setting changes over the complete discharging process, depending on the terminal voltage
of the supercapacitor bank. The optimal CTI voltage curve is discontinuous since the
characterization of the charger is discrete and the charger efficiencies at some cases
input-output voltage are very close. Therefore, as the supercapacitor voltage changes, the
optimal CTI voltage may vary greatly.
Figure 4.10 compares ICR efficiencies 𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 obtained by the proposed policy and
baseline policies over the discharging process. The proposed policy consistently
outperforms the baselines during the complete discharging process. From Figure 4.10 we
see that no single fixed CTI voltage does the perfect job in maximizing the 𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 . In

Figure 4.10. Comparisons of the instantaneous charge replacement efficiency between the proposed
policy and the baseline policies during the discharging process.
55

contrast, the proposed policy achieves the optimal 𝜂𝜂 𝐶𝐶 𝐶𝐶 𝐺𝐺 through adaptively setting the
CTI voltage. Table 4.3 lists the GCR efficiency 𝜂𝜂 𝐺𝐺 𝐶𝐶 𝐺𝐺 obtained by operating the optimal
CTI voltage control policy and baseline policies at different levels of the load demand.
BP1, BP2 and BP3 in the Table 4.3 stand for the baseline policy with fixed CTI voltage
of 25V, 20V, and 15V, respectively. One can observe that maintaining CTI voltage at
optimal value achieves up to 5.9% 𝜂𝜂 𝐺𝐺 𝐶𝐶 𝐺𝐺 improvement.
4.4.4.2 Hybrid use of EES banks
We perform charge replacement for multiple EES banks in this section. To demonstrate
the concept and benefits of hybrid EES, we use supercapacitor and lead-acid battery
banks as these two EES technologies exhibit very different characteristics even at low
current levels. In contrast, the Li-ion battery does not show distinct characteristics
compared to the supercapacitor due to the relatively low value of maximum discharging
current, which is supported in the board used in our experiments (this limit is 3A). We
use it to shave the peaks of the power demand profile, in order to reduce the energy loss
Table 4.3. Comparisons of the GCR efficiencies obtained by the proposed policy and baseline policies
at different levels of the load demand.

56

due to rate capacity effect in the lead-acid battery. We derive discharging power bounds,
and assign the power demand accordingly to the supercapacitor bank and the lead-acid
bank, respectively, as explained in Chapter 6. Note that in Chapter 6 we present a general
method of deriving power bounds with the consideration of the self-discharge of the
supercapacitor bank. However, in practice, the supercapacitor bank in our prototype has a
relatively small energy capacity, and thereby we limit the discharging processes less than
one hour in our experiments. The self-discharge of the supercapacitor bank can be safely
ignored for such short discharging processes.
We explore the GCR efficiency improvements offered by the proposed policy for
various load demand profiles. A constant load profile is used to compare the performance
of the proposed method against that of baseline setups for cases in which power demands
remains fixed for long periods of time. Note that in Table 4.4, we report our results for
the constant load demand profile under different windows of time. The pulsed load
profiles are traces taken from real power demands generated by a military radio as
reported in [98]. The profile consists of periodic alternate peak (when transmitting
signals) and off-peak (when receiving signals) power demand levels. The duty ratios of
the peak power demand are 50% for the (50W, 20W) entry and 40% for the (70W, 5W)
entry in Table 4.5. Randomly generated load profiles are obtained by mixing random
Gaussian-distributed power demands to some fixed average load demand levels. We use
this kind of load profiles to mimic realistic load demand profiles typically have some
fluctuations in the power demand.
57

Table 4.4 and Table 4.5 compare the GCR efficiencies obtained by using the
proposed policy and three other baseline policies for constant and pulsed load profiles,
respectively. The baseline policy BP4 discharges the supercapacitor bank first and
switches to battery bank only when the supercapacitor bank is completely depleted. The
Table 4.4. Comparisons of the GCR efficiencies obtained using the proposed policy and baseline
policies for flat load profiles.

Table 4.5. Comparisons of the GCR efficiencies obtained using the proposed policy and baseline
policies for pulsed load profiles.

58

baseline policy BP5 discharges all available EES banks with the same amount of current.
The other baseline method, BP6, uses lead-acid battery bank only. BP6 is designed to
explore the benefits of HEES system against the homogeneous EES system. All the
baseline policies maintain constant CTI voltage levels over the discharging processes,
which are shown in the tables. One can observe from the Table 4.4 and Table 4.5 that the
proposed GCR policy consistently outperforms the baseline policies. The maximum GCR
efficiency improvement ranges from 2.8% to 11.1% for the HEES baselines, and from
11.6% to 24.7% for homogeneous EES baseline, respectively, depending on load profiles.
For short-duration load profiles, the BP4 achieves better GCR efficiency among all
baseline policies, as it fully utilizes the energy stored in the supercapacitor bank, i.e., the
supercapacitor bank has higher charge replacement efficiency due to the small internal
resistance and negligible rate capacity effect. However, for long-duration load profiles,
BP5 performs better than BP4, because BP4 has to draw the energy from the lead-acid
battery bank only after the supercapacitor bank is depleted, which is inefficient and
significantly reduces the overall GCR efficiency. In general, the GCR efficiency
decreases at higher load demand, due to higher energy loss on the internal resistance and
the rate capacity effect.
We show results of the proposed GCR policy for randomly generated load profiles,
together with the average power levels and durations in the Figure 4.11. We derive the
GCR policy using the average power demand of the randomly generated load profile. We
obtain similar GCR efficiency compared to the case based on the perfect knowledge of
the load profile. This is because that the load demand profiles last for a short period of
59

time, and therefore, the self-discharge of supercapacitor banks is negligible (cf. Figure
4.11 (a), the discharging power bound is nearly a flat line). The proposed policy improves
the GCR efficiency by up to 4.5% and 6.8% against the HEES baseline policies BP4 and
BP5 for the two load profiles. In addition, it improves the GCR efficiency by up to 10.3%
and 19.4% against the homogeneous EES baseline BP6 for the two load profiles.
Figure 4.11 shows energy assignments among the supercapacitor bank and the lead-
acid bank for the proposed GCR policy, baseline policies BP4, and BP5 for the 15-min
random load profile. The light gray areas correspond to the energy drawn from the
supercapacitor bank and the dark gray areas amount of energy are drawn from the lead-
acid battery bank. According to Chapter 6, the proposed GCR policy shaves peaks of the
load demand and discharges the lead-acid bank using a relatively low rate over the
complete discharging process. In contrast, the BP4 policy draws the energy from the
supercapacitor bank first, and thereby the light gray part ends very quickly. The BP5
policy equally distributes the power demand between the two banks before the
supercapacitor bank is depleted.
Table 4.6. Comparisons of the GCR efficiencies obtained using the proposed policy and baseline
policies for random-generated load profiles.

60

Figure 4.12 shows the corresponding remaining energy in the supercapacitor bank
and the ICR efficiency over the discharging process. The energy stored in supercapacitor
banks decreases from 100% to 0% for proposed policy, BP4, and BP5. The BP6 only
uses the battery bank, and thereby the remaining energy stays at 100%. The ICR
efficiencies fluctuate since they are dependent on load power demands. One can observe
that the BP4 drains the energy stored in the supercapacitor very fast. It achieves very high
ICR efficiency (>80%) for the first eight minutes. After that the ICR efficiency drops
significantly as it has to switch to lead-acid battery bank only. BP5 policy makes better
balance between the short-term and long-term efficiency by simultaneously discharging
both battery and supercapacitor banks. However, the energy assignment of BP5 is not
optimal among these two banks. The proposed policy properly discharges the
supercapacitor bank with a global consideration of the complete discharging process. It
fully utilizes the energy stored in the supercapacitor bank to minimize the energy loss due

Figure 4.11. Energy assignments by the proposed GCR policy (a), BP4 (b), BP5 (c) for the 15-min
load profiles in [98]. Light and dark gray areas denote amounts of energy drawn from the
supercapacitor bank and the lead-acid battery bank, respectively.
61

to the rate capacity effect in the lead-acid battery bank, through peak shaving over the
complete discharging process.

Figure 4.12. Comparisons of the normalized remaining energy in the supercapacitor bank (a) and the
instantaneous charge replacement efficiencies (b) obtained by the proposed GCR policy and baseline
policies, for the 15-min load profiles in [98].
62

CHAPTER 5
CHARGE ALLOCATION OPTIMIZATION
Charge allocation is a problem that is concerned with how to allocate given amount of
incoming energy to EES banks so that the total energy received by the HEES system is
maximized, considering the energy loss in power converters and EES banks (e.g., self-
discharge, rate capacity effect, internal resistance). We present the problem statement,
optimization problem formulation, solution method, and experimental results of charge
allocation problem in this chapter.
We start by introducing a generalized HEES architecture comprised of two
representative types of EES elements (batteries and supercapacitors) connected by a
charge transfer interconnect (CTI) and then build the corresponding electrical circuit
models for power converters, and battery and supercapacitor banks. Next we introduce
the global charge allocation (GCA) problem for a HEES system, i.e., how to distribute
the given source power supply to some selected EES destination banks in the HEES
system so that the global charge allocation efficiency is maximized. This efficiency is
determined by the characteristics of the selected banks and the magnitudes of the
charging currents, and the states of charge (SoCs) of the banks. We consider the energy
conservation and charge conservation during the charge allocation process. In addition to
the energy pushed into all EES banks, we also take into account the power dissipation on
the internal resistances of battery banks and supercapacitor banks, the power loss on
63

chargers during the power conversion process, the rate capacity effect in batteries, and
the self-discharge in supercapacitors.
The GCA problem may be decomposed into three sub-problems: i) what is the
optimal voltage level setting for the CTI? ii) which EES bank(s) should be selected
among all the destination EES banks? and iii) how to assign the charging current for each
of the selected destination EES banks? The GCA efficiency depends on the profile of the
power source, magnitude of charging currents, and SoCs of each EES banks. Since SoCs
of EES banks and the amount of source (input) power vary over time, and solutions to
these three questions are inter-dependent, our method is an online, iterative approach.
The charge allocation efficiency also depends on detailed characteristics of the external
power source. We adopt a photovoltaic (PV) cell array as the incoming power source. An
accurate forecast of the PV power is extremely important for us to develop for the GCA
policy. We predict the solar radiation level based on the history of solar irradiance levels
and the current observation.
We formulate the GCA problem as a mixed-integer non-linear programming
(MINLP) problem, which unfortunately cannot be optimally solved in polynomial time.
We, therefore, break the whole charge allocation process into a series of time slots and at
every decision epoch (which denotes the boundary between consecutive time slots), we
solve an instantaneous charge allocation (ICA) problem, which seeks to optimize the
charge allocation efficiency at a specific instance of time. The ICA problem is still a
MINLP problem. However, we can simplify the ICA problem, and subsequently, develop
an effective way of solving the ICA problem in an iterative manner, where in each
64

iteration the optimization problem is convex. We incorporate appropriate charging power
limits for the high-charging-efficiency EES banks to the problem formulation to ensure
that the charge allocation manager considers the future energy generation profile, and
thus, avoid greedy decisions that can result in significant future efficiency degradation.
The charging power limits are derived using the Lagrange multiplier method to minimize
the energy loss due to the rate capacity effect and self-discharge. The near-optimal
solution of the original GCA problem is obtained by solving the ICA problem with
charging power upper limit for high-charging-efficiency banks at every decision epoch
throughout the charge allocation process. We record the ICA solutions to obtain the GCA
solutions. Simulation results show that the percentage improvement of energy harvesting
ability from various baseline setups ranges from 5% to 25% in general.
5.1 Charge Allocation Problem Statement
Figure 5.1 shows the diagram of the system. We target the charge allocation problem of a
HEES system with an energy harvesting system, e.g., a PV module. The PV module
collects the solar energy and delivers the energy to the HEES system. The charge
allocation process starts at time 𝑡𝑡 = 0 and ends at time 𝑡𝑡 = 𝑇𝑇 𝑐𝑐 . From the initial SoCs of
all EES banks, we determine the OCV of EES arrays 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 (0) for all EES banks. We
observe the solar radiation levels in the target area and based on this predict the power
generation profile of the PV module over the charge allocation process.
The charge allocation process is managed by three sets of control variables that
should be optimally determined for the highest global efficiency. The first one is CTI
65

voltage 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ), which is maintained by the source-to-CTI charger. The second one is the
set of selected EES banks, 𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ) ∈ 𝑆𝑆 . The third set of variables is 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ), 𝐽𝐽 ∈ 𝑆𝑆 of
all the EES banks, which are tuned by the EES bank chargers. Note that an array charging
current can be set to 0, i.e. we turn off the charger if we decide not to charge that EES
bank. The solution of the charge allocation problem consists of three parts: 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ),
𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ), and 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ), 𝐽𝐽 ∈ 𝑆𝑆 , 𝑡𝑡 ∈ [0, 𝑇𝑇 𝑐𝑐 ]. We formulate the GCA as a mathematical
programming problem while the objective function is the global charge allocation
efficiency and variables are the three variables aforesaid.
We derive the constraints in the mathematical programming problem based on the
law of energy conservation. Electrical energy is generated by PV and delivered to the
CTI through the source-to-CTI charger, where it is further distributed by selected

Figure 5.1. Schematic of the charge allocation process in a HEES system.
66

chargers to their corresponding destination EES banks. Based on the law of energy
conservation, the power supplied by the power source, 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ), consists of 𝑃𝑃 𝑐𝑐 , 𝑠𝑠 ( 𝑡𝑡 ) ,
𝑃𝑃 𝑠𝑠𝑐𝑐𝑠𝑠𝑐𝑐 𝑠𝑠 ( 𝑡𝑡 ) and the power delivered to CTI, 𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ), thus the energy conservation for the
CTI is given by,

𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 )& = 𝑉𝑉 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) = 𝑃𝑃 𝑐𝑐 , 𝑠𝑠 ( 𝑡𝑡 ) + 𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) + 𝑃𝑃 𝑠𝑠𝑐𝑐𝑠𝑠𝑐𝑐 𝑠𝑠 ( 𝑡𝑡 )
= 𝑃𝑃 𝑐𝑐 , 𝑠𝑠 ( 𝑡𝑡 ) + 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) � 𝐼𝐼 _( 𝑏𝑏 𝑡𝑡 𝑛𝑛𝐽𝐽 , 𝐽𝐽 )( 𝑡𝑡 )
𝑁𝑁 𝑘𝑘 = 1

(21)
For the 𝐽𝐽 -th charger, the output power equals the input power minus the power loss
during the conversion. Thus, the energy conservation for the charger is given by,

𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ) = 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) + 𝑃𝑃 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 )
= 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 ( 𝑡𝑡 ) ⋅ � 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 ( 𝑡𝑡 ) �
1
𝛾𝛾 𝑐𝑐 + 𝑃𝑃 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 )
(22)
𝑃𝑃 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 ) and 𝑃𝑃 𝑐𝑐 , 𝑠𝑠 ( 𝑡𝑡 ) in (21) and (22) can be derived using (15), (16) and (17) but with
different sets of parameters.
We define the objective function as the global charge allocation efficiency, or
equivalently, the total energy gain in all EES banks after the charge allocation process,
i.e., the integration of the power pushed into all EES banks minus the leakage power as in
(14). Continuing the previous analysis, the energy increase rate in the k-th EES bank,
denoted by 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑘𝑘 ( 𝑡𝑡 ), is given by,

𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑘𝑘 ( 𝑡𝑡 ) = 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 ( 𝑡𝑡 ) − 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑘𝑘 ( 𝑡𝑡 ),
𝑑𝑑 𝑑𝑑𝑡𝑡 𝐸𝐸 𝐻𝐻𝐻𝐻𝐻𝐻 𝑆𝑆 ( 𝑡𝑡 ) = � 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑘𝑘 ( 𝑡𝑡 )
𝑁𝑁 𝑘𝑘 = 1

(23)
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where 𝐸𝐸 𝐻𝐻𝐻𝐻𝐻𝐻 𝑆𝑆 ( 𝑡𝑡 ) is the total energy stored in all HEES banks. Note that the first term at
RHS in (23) corresponds to the power that is pushed into the 𝐽𝐽 -th EES bank. Compared
to the first term at RHS in (22), we exclude the power dissipation on the internal
resistance of the EES banks and the power loss due to the rate capacity effect from the
output power of the 𝐽𝐽 -th charger.
5.2 Charge Allocation Optimization Problem Formulation
We have described the GCA problem in Chapter 5.1. We formulate the GCA
optimization problem as follows.
Given: Initial SoCs of all destination EES banks, 𝑆𝑆𝑆𝑆 𝐶𝐶 ( 𝑡𝑡 )|
𝑐𝑐 = 0
, ∀ 𝐽𝐽 ∈ 𝑆𝑆 ; (historic)
profile of the solar radiation; specifications of the HEES system and the PV module; and
duration of the charge allocation process [0, 𝑇𝑇 𝑐𝑐 ].
Find: 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ), 𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ), and 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ), ∀ 𝐽𝐽 ∈ 𝑆𝑆 and ∀ 𝑡𝑡 ∈ [0, 𝑇𝑇 𝑐𝑐 ].
Maximize: the global charge allocation efficiency, 𝜂𝜂 𝐺𝐺 𝐶𝐶 𝐺𝐺 , which is given by:
𝜂𝜂 𝐺𝐺 𝐶𝐶 𝐺𝐺 =
∑
∫ 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑘𝑘 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑇𝑇 𝑎𝑎 0
𝑁𝑁 𝑘𝑘 = 1
∫ 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑇𝑇 𝑎𝑎 0
(24)
or equivalently, maximize the total energy increment in all the destination EES banks at
time 𝑇𝑇 𝑐𝑐 , given by the nominator term in (24), since the denominator term in (24) is fixed.
Subject to:
1) Lower and upper bound of the array charging currents,
0 ≤ 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 ( 𝑡𝑡 ) ≤ 𝐼𝐼 𝑚𝑚 𝑐𝑐𝑒𝑒 , 𝑘𝑘 , ∀ 𝑡𝑡 ∈ [0, 𝑇𝑇 𝑐𝑐 ], ∀ ∈ 𝑆𝑆 (25)
2) Maximum energy storage constraint,
68

𝐸𝐸 𝑘𝑘 ( 0)
+ � 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑘𝑘 𝑐𝑐 0
( 𝜏𝜏 ) 𝑑𝑑𝜏𝜏 ≤ 𝐸𝐸 𝑚𝑚 𝑐𝑐𝑒𝑒 , 𝑘𝑘 , ∀ 𝑡𝑡 ∈ [0, 𝑇𝑇 𝑐𝑐 ] (26)
where 𝐸𝐸 𝑘𝑘 (0) stands for the initial energy stored in the 𝐽𝐽 -th bank at the beginning of the
charge allocation process.
3) The conservation of energy given by (21)(22).
4) The conservation of charge given by (4).
Although { 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 )} is the set of variables that we can control using the chargers,
we use { 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 ( 𝑡𝑡 )} as the optimization variables instead in the formulation because of the
convenience in solving the optimization problem. We determine { 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 )} from
solved { 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 ( 𝑡𝑡 )} according to (4). In addition, the GCA optimization problem is a mixed-
integer nonlinear programming (MINLP) problem due to the existence of binary variable
set { 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 )}. Therefore, the GCA optimization problem is NP-complete and cannot be
optimally solved in polynomial time. We provide an approximation algorithm to obtain
the near-optimal solution of the GCA problem.
5.3 Near-optimal Charge Allocation Control Algorithm
Before solving the GCA problem, we first consider the instantaneous charge allocation
(ICA) problem, which aims to optimize the charge allocation efficiency at a specific time
instance. We present an algorithm to solve the ICA problem and derive a near-optimal
solution. Subsequently, we break the whole charge allocation process into a series of time
slots and solve one ICA problem at each decision epoch. However, a simple combination
of the ICA solutions at each decision epoch is a greedy decision, which may not achieve
the global optima due to the lack of consideration of SoC changes in the EES banks,
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especially those banks that have small energy capacity and high-charging-efficiency. We
classify all EES banks into two groups: high-charging-efficiency banks (e.g.,
supercapacitor banks) and low-charging-efficiency banks (e.g., battery banks) according
to their properties. To overcome this issue, we incorporate an upper bound on the total
charging power of the high-charging-efficiency banks.
5.3.1 Solar irradiance level prediction
Accurate online solar irradiance forecast, which provides the clue of future power
generation, is extremely important in developing the GCA algorithm since the optimal
GCA policy depends on the power generation profile. We break the daily observation of
solar irradiance level into 𝑀𝑀 time slots (0, 𝑡𝑡 _1, 𝑡𝑡 _2, . . . , 𝑡𝑡 𝑀𝑀 ). We consider two factors in
order to accurately predict the solar irradiance: clear sky solar irradiance level,
𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) (i.e., solar irradiance in a sunny day), which stands for the maximum solar
irradiance level without any decay due to the climate conditions, and climate condition
Table 5.1. Notation used in Chapter 5.3.
Symbol Definition
𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 At the 𝑡𝑡 𝑚𝑚 -th time slot in the 𝑑𝑑 𝑛𝑛 -th day
𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) Clear sky solar irradiance level ( 𝑊𝑊 /𝑚𝑚 2
)
𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) Observed solar irradiance level ( 𝑊𝑊 /𝑚𝑚 2
)
𝜉𝜉 𝑐𝑐 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) Climate condition factor, typically less than 1
𝑃𝑃 𝑑𝑑 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) Predicted solar irradiance level ( 𝑊𝑊 /𝑚𝑚 2
)
𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) Upper limit for the charging power of all supercapacitor banks
𝐸𝐸 𝑆𝑆 𝐵𝐵 the energy stored in all supercapacitor banks
𝐸𝐸 𝐵𝐵𝐵𝐵
the energy stored in all battery banks

70

factor 𝜉𝜉 𝑐𝑐 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ), which takes into account the decay factor caused by climate conditions,
such as rain, cloud, and so on. We set each time slot to be 10~15 minutes so that the solar
irradiance level and climate conditions are approximately unchanged within a time slot.
We consider that the climate conditions have an approximately linear decaying effect
on the solar irradiance levels. To obtain the predicted solar irradiance level 𝑃𝑃 𝑑𝑑 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ),
we multiply the climate condition factor at previous time instance 𝜉𝜉 𝑐𝑐 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 − 1
) to
𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ). At the end of the 𝑡𝑡 𝑚𝑚 -th time instance, we observe the solar irradiance level
𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) and calculate 𝜉𝜉 𝑐𝑐 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) as relative ratio between 𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) and 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ).

𝑃𝑃 𝑑𝑑 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) = 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) ⋅ 𝜉𝜉 𝑐𝑐 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 − 1
)
𝜉𝜉 𝑐𝑐 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) =
𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 )
𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚
(27)
Although 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) varies with the location on the earth and the time of the year, it
is predictable based on the observation history of solar irradiance levels [99]. We adopt
exponential smoothing, which is a powerful technique that is applied to sequential data to
make forecasts by assigning exponentially decreasing weights over time [100]. This
weighting method makes exponential smoothing particularly effective in our problem
since 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) is more related to the solar irradiance in recent past rather than earlier
past. We observe 𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) and update 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) using a smoothing factor \alpha,
which ranges between 0 and 1. The 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) is given by,

𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 1
, 𝑡𝑡 𝑚𝑚 ) = 0
𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 + 1
, 𝑡𝑡 𝑚𝑚 ) = 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ), if 𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) < 𝜆𝜆 ( 𝑡𝑡 𝑚𝑚 ) 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 )
𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 + 1
, 𝑡𝑡 𝑚𝑚 ) = 𝛼𝛼 ⋅ 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) + (1 − 𝛼𝛼 ) ⋅ 𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ), otherwise
(28)
71

Since 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) denotes the clear sky solar irradiance level, we use 𝜆𝜆 ( 𝑡𝑡 𝑚𝑚 ) as a
screening factor to prune the solar irradiance data that severely degrades due to the
climate conditions in (28) and only update 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) using those data that is collected in
sunny days. More precisely, if 𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) < 𝜆𝜆 ( 𝑡𝑡 𝑚𝑚 ) ⋅ 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ), we consider it to be not
under clear sky condition, and thereby directly carry 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) to the next time instance.
We determine 𝜆𝜆 ( 𝑡𝑡 𝑚𝑚 ) based on a online learning approach, where the state set is defined
as the set of time slots { 𝑡𝑡 𝑚𝑚 }, the action set is defined as a set of different reasonable
screening factors ( 𝜆𝜆 1
, 𝜆𝜆 2
, . . . , 𝜆𝜆 𝐾𝐾 )(i.e., 0.7~1). Selecting different 𝜆𝜆 𝑘𝑘 ends up with
different 𝐶𝐶 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 + 1
, 𝑡𝑡 𝑚𝑚 ) and in turn affects the predictions later on. The prediction error is
captured by the penalty function 𝐸𝐸 𝑒𝑒𝑒𝑒𝑆𝑆 𝑒𝑒 𝑚𝑚 . We adopt Q-learning and update the state-
action pair 𝑄𝑄 ( 𝑡𝑡 𝑚𝑚 , 𝜆𝜆 𝑘𝑘 ) using a learning rate 𝛽𝛽 ,

𝐸𝐸 𝑒𝑒𝑒𝑒𝑆𝑆 𝑒𝑒 𝑚𝑚 = | 𝑃𝑃 𝑑𝑑 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 ) − 𝑅𝑅 𝑠𝑠 ( 𝑑𝑑 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 )|
𝑄𝑄 ( 𝑡𝑡 𝑚𝑚 , 𝜆𝜆 𝑘𝑘 ) ← (1 − 𝛽𝛽 ) ⋅ 𝑄𝑄 ( 𝑡𝑡 𝑚𝑚 , 𝜆𝜆 𝑘𝑘 ) + 𝛽𝛽 ⋅ 𝐸𝐸 𝑒𝑒𝑒𝑒𝑆𝑆 𝑒𝑒 𝑚𝑚
(29)
We pick the screening factor 𝜆𝜆 𝑘𝑘 according to the probability of
𝑠𝑠 𝑒𝑒 𝑐𝑐 − 𝑄𝑄 � 𝑡𝑡 𝑚𝑚 , 𝜆𝜆 𝑘𝑘 �
∑ 𝑠𝑠 𝑒𝑒 𝑐𝑐
− 𝑄𝑄 � 𝑡𝑡 𝑚𝑚 , 𝜆𝜆 𝑘𝑘 �

𝐾𝐾 𝑘𝑘 = 1
.
5.3.2 Instantaneous charge allocation solver
The ICA optimization problem maximizes the total power that is pushed into all EES
banks at a specific time instance. The ICA problem is a special case of the GCA problem
when 𝑇𝑇 𝑐𝑐 → 0. The control variables to be solved in the ICA problem are similar to GCA
problem, except that they are only for one time instance. Thus we omit t for simplicity in
writing. We define the objective function instantaneous charge allocation efficiency 𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 ,
72

𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 =
1
𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 � 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑘𝑘 𝑁𝑁 𝑘𝑘 = 1
(30)
where 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 is a fixed value and do not affect the optimization. We apply similar
constraints (21)(22) to the ICA problem. Therefore, the ICA optimization problem is
again an MINLP problem. We utilize three facts to simplify the original ICA problem to
optimal charging current determination (OCCD) problem, which is a convex
optimization problem. The three facts are:
1) The optimal ICA efficiency 𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 is approximately a unimodal function with respect
to the CTI voltage 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 . Therefore, we perform a ternary search
1
in the feasible
region of 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 as the outer loop. Inside the outer loop, we consider the CTI voltage
𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 as a fixed value and solve the OCCD problem. More precisely, we do not treat
𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 as a variable in OCCD problem, otherwise solving { 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 } becomes impractical
because the power loss in the charger (15)(16)(17) is a function of both { 𝐼𝐼 𝑠𝑠 𝑒𝑒, 𝑘𝑘 } and
the CTI voltage.
2) It will be beneficial to turn off some EES banks if their optimal { 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 } are smaller
than a threshold value 𝐼𝐼 𝑐𝑐 ℎ
. The charger power loss contains a fixed part and a part
proportional to the output charging current. It is not worthwhile to keep the charger
on when the output charging current is small. The binary indicators { 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 } that
1
A ternary search is a divide and conquer-based algorithm that determines either that
the minimum or maximum cannot be in the first third of the domain or that it cannot be in
the last third of the domain, then repeats on the remaining two-thirds.
73

denote the charger statuses lead to the discontinuity in optimization problem. To
overcome this issue, we maintain a selection set 𝑆𝑆 𝑆𝑆 𝑛𝑛 , which is a subset of 𝑆𝑆 , and only
consider 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 , 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 in the OCCD problem, i.e., 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 = 1, 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 . For other EES
banks that are not in S', we set 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 = 0, 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 = 0, 𝐽𝐽 ∉ 𝑆𝑆 𝑆𝑆 𝑛𝑛 . In this way the OCCD
problem becomes a continuous mathematical programming problem. For each fixed
𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 , we first initialize S' to be the full set of all EES banks and remove those EES
banks whose 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 is smaller than 𝐼𝐼 𝑐𝑐 ℎ
. We repeat solving the OCCD problem until the
selection set 𝑆𝑆 𝑆𝑆 𝑛𝑛 converge.
3) In general, the CCVs are not very different from OCVs since the internal resistances
are not large, according to (3)(12). The objective function is a complicated non-
linear function of � 𝐼𝐼 𝑠𝑠 𝑒𝑒, 𝑘𝑘 � since both CCVs and { 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 } are involved in the charger's
power loss. To address this issue, we use fixed CCVs { 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 } in the OCCD
problem instead of functions of { 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 }. After solving the OCCD, we obtain
� 𝐼𝐼 𝑠𝑠 𝑒𝑒, 𝑘𝑘 � and update { 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 } using (4)(3)(12). We repeat solving the OCCD
problem until � 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 � , ∀ 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 converge.
The proposed ICAS algorithm is summarized in Algorithm 5.1. We do ternary search
of 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 in the outer loop, while in the inner loop we solve the OCCD problem repeatedly
at a fixed 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 and update the selection set S' as well as the CCV voltages { 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 }. The
OCCD problem has a concave objective function (30) to be maximized, subjecting to
linear inequality constraints (16) and convex inequality constraints (21)(22). Thus the
OCCD problem is a convex optimization problem and can be solved optimally in
74

polynomial time using the standard convex optimization technique. We carefully set the
threshold current 𝐼𝐼 𝑐𝑐 ℎ
such that turning off the charger when the 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 < 𝐼𝐼 𝑐𝑐 ℎ
always
improves the charge allocation efficiency. Figure 3.9 shows that when 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑘𝑘 < 0.05 𝐴𝐴 , the
conversion efficiency of the charger becomes unacceptably low. Thus we set 𝐼𝐼 𝑐𝑐 ℎ
to be
0.05A. The inner loop in Algorithm 5.1 is terminated when 𝑆𝑆 𝑆𝑆 𝑛𝑛 and { 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 } converge,
where the optimal 𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 at a specific 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 is achieved. We search the 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 domain and
repeat the inner loop subroutine for different 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 until a termination condition is met, i.e.,
the difference between the upper and lower bounds of the 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 domain falls within a pre-
defined threshold Δ 𝑉𝑉 𝑐𝑐 ℎ
.
Figure 5.2 shows 𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 versus the 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 for a 4-bank HEES system. The solid curve
shows that 𝜂𝜂 𝐶𝐶 𝐶𝐶𝐺𝐺 solved at each fixed 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 is a unimodal function of 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 . Thus we
converge to the near-optimal solution (displayed as a circle) by ternary searching the 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐
domain. The empty space in Figure 5.2 below the solid curved is caused by the

Figure 5.2. Comparison of ICA efficiency at different CTI voltages obtained by the proposed method
(solid curve) and Monte Carlo simulation (cross marks).
75

discontinuity of the { 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 }. The Monte Carlo simulation results (displayed as cross marks)
shows that the proposed method always achieves better solutions than the MC simulation.

Algorithm 5.1. The ICA solver (ICAS).

76

5.3.3 Power limit derivation
The ICAS algorithm presented in Chapter 5.3.2 solves the ICA problems near-optimally
and returns the corresponding EES bank selection, CTI voltage, and EES array charging
currents. A straightforward way to solve the GCA problem is to follow a greedy approach,
i.e., breaking the whole charge allocation process into a series of consecutive time slots
(0, 𝑡𝑡 1
, 𝑡𝑡 2
, . . . , 𝑡𝑡 𝑀𝑀 ) and solving an ICA problem at the beginning of each time slot, with the
approximation that the SoC stays unchanged over the time slot. However, such a greedy
approach does not consider the EES bank capacity, and thereby may not lead to the
optimal results, e.g., simply assigning a large amount of power to high-charging-
efficiency banks. As shown in Figure 1.1, supercapacitor banks usually have high
charging efficiency thanks to their high power-capacity and small internal resistance,
while their energy capacity is very limited. Therefore, the greedy GCA approach may
fully charge the supercapacitor banks very quickly and then assign all power to battery
banks during the rest of the charge allocation process. In such a case, the global charge
allocation efficiency may be unacceptably low due to the following two reasons.
1) The power loss due to the rate capacity effect in the battery banks increases super-
linearly as the array charging current increases, according to the Peukert's law. The
greedy approach may charge the battery banks with high rates after all
supercapacitor banks are full. Thus the HEES system suffers a significant power
loss that prevents it from reaching the global optimality.
2) The other reason that makes the greedy approach even worse is the self-discharge
of the supercapacitor banks. The self-discharge power rate grows quadratically as
77

the OCV of the supercapacitor bank increases, according to (14). Thus, the high
leakage rate degrades the GCA efficiency if we charge the supercapacitor banks
quickly and leave them at high SoC state for the rest of charge allocation process.
Due to these reasons, we modify the original ICAS to make it `aware of the future
energy generation'. More precisely, we impose an upper limit for the total charging power
of all the supercapacitor banks, 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ), to prevent rapid charging of supercapacitor
banks, leaving some capacity for the remaining charge allocation process to combat the
rate capacity effect and alleviate the power loss due to the self-discharge. A low power
limit may under-charge the supercapacitor banks and result in low GCA efficiency, since
the supercapacitor banks typically have high charging efficiency. Furthermore, the power
limit should also consider the power generation. For example, the power limit should be
relatively high during the peak period of the power supply in order to allow more power
to be assigned to the supercapacitor banks. An effective heuristic of setting the
appropriate power limits to achieve the near-optimal GCA efficiency is to charge the
supercapacitor banks such that they are fully charged at the end of the charge allocation
process.
Since supercapacitor banks typically have higher charging efficiency, the ICAS
intends to assign full 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) amount of power to them. Therefore, the energy assigned
to all supercapacitor banks (denoted by 𝐸𝐸 𝑆𝑆 𝐵𝐵 ) and battery banks (denoted by 𝐸𝐸 𝐵𝐵𝐵𝐵
) over the
whole charge allocation process are approximately given by,
78

𝐸𝐸 𝑆𝑆 𝐵𝐵 = � � 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) 𝑑𝑑𝑡𝑡 𝑐𝑐 𝑚𝑚 𝑐𝑐 𝑚𝑚 − 1
𝑀𝑀 𝑚𝑚 = 1

𝐸𝐸 _( 𝐵𝐵𝐵𝐵 ) = � � � 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 𝑚𝑚 ) − 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) � 𝑑𝑑𝑡𝑡 𝑐𝑐 𝑚𝑚 𝑐𝑐 𝑚𝑚 − 1
𝑀𝑀 𝑚𝑚 = 1

(31)
According to (13) and (14), we conclude that the ratio between energy loss due to
self-discharge and the total energy is fixed and given by 𝜇𝜇 𝑠𝑠 𝑑𝑑 = 𝐸𝐸 𝑆𝑆 𝐵𝐵 ( 𝑡𝑡 + Δ 𝑡𝑡 )/𝐸𝐸 𝑆𝑆 𝐵𝐵 ( 𝑡𝑡 ) =
𝑒𝑒 −
2 Δ 𝑡𝑡 𝜏𝜏 , where Δ 𝑡𝑡 is the duration of a time slot and 𝜇𝜇 𝑠𝑠 𝑑𝑑 < 1 is the ratio of remaining energy
after one time slot. Therefore, the total energy loss due to the self-discharge 𝐸𝐸 𝑠𝑠 𝑑𝑑 , is
approximately given by,
𝐸𝐸 _( 𝑠𝑠 𝑑𝑑 ) = 𝐸𝐸 _( 𝑆𝑆 𝐵𝐵 ) − � � (1 − 𝜇𝜇 𝑠𝑠 𝑑𝑑 )
( 𝑀𝑀 − 𝑚𝑚 + 1)
𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) 𝑑𝑑𝑡𝑡 𝑐𝑐 𝑚𝑚 𝑐𝑐 𝑚𝑚 − 1
𝑀𝑀 𝑚𝑚 = 1
(32)
We denote the part of the energy assigned to all the battery banks but wasted due to
the rate capacity effect by 𝐸𝐸 𝑐𝑐𝑏𝑏
. For derivation simplicity, we approximately treat all
battery banks as a big equivalent battery with an equivalent Peukert constant 𝛾𝛾 𝑠𝑠 𝑒𝑒 <1. Thus
𝐸𝐸 𝑐𝑐𝑏𝑏
is given by,
𝐸𝐸 𝑐𝑐𝑏𝑏
= 𝐸𝐸 _( 𝐵𝐵𝐵𝐵 ) − � � � 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 𝑚𝑚 ) − 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) �
𝛾𝛾 𝑒𝑒𝑒𝑒
𝑑𝑑𝑡𝑡 𝑐𝑐 𝑚𝑚 𝑐𝑐 𝑚𝑚 − 1
𝑀𝑀 𝑚𝑚 = 1
(33)
We determine the parameter 𝛾𝛾 𝑠𝑠 𝑒𝑒 in (33) by fitting the energy loss due to rate capacity
effect of all battery banks. The power limit is constrained by the energy capacity of all
the supercapacitor banks. This helps us to express the energy loss due to the self-
discharge and rate capacity effect as convex functions of � 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) � . The derivation of
power limit becomes an optimization problem as follows:
79

Minimize:
𝐸𝐸 𝑐𝑐𝑏𝑏
+ 𝐸𝐸 𝑠𝑠 𝑑𝑑 (34)
Subject to: maximum energy constraint for SB
� � 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) 𝑑𝑑𝑡𝑡 𝑐𝑐 𝑚𝑚 𝑐𝑐 𝑚𝑚 − 1
𝑀𝑀 𝑚𝑚 = 1
≤
1
2
� 𝐶𝐶 𝑐𝑐𝑐𝑐𝑐𝑐 , 𝑘𝑘 ⋅ � 𝑉𝑉 𝑚𝑚 𝑐𝑐𝑒𝑒 , 𝑘𝑘 2
− � 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 �
2
�
𝑘𝑘 ∈ 𝑆𝑆 𝐵𝐵 (35)
where 𝑉𝑉 𝑚𝑚 𝑐𝑐𝑒𝑒 , 𝑘𝑘 is the maximum voltage of the supercapacitor bank and 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 is the
current OCVs. (34) is a convex function and (35) is a linear constraint. Thus we solve the
optimization problem (34) using Lagrange multiplier and achieve the optimal set of
� 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ) � over all time slots. The source power information that is required in (31)~(34)
comes from the solar irradiance level prediction in Section 5.3.1. The power upper limit
may change due to the variation of the climate condition. We determine this limit at every
time slot according to the latest information of climate conditions and remaining capacity
of the supercapacitor banks.
5.3.4 Global charge allocation solver
In this section, we present the GCA solver with charging power limits (SCPL) for the
GCA problem, integrating solar irradiance level prediction, power limits derivation, and
modified ICAS alternately. The original ICAS finds the near-optimal solution of the ICA
problem by iteratively solving OCCD problem and updating the CCVs and EES banks
selection set. We modify the original ICA problem to constrained ICA problem by
introducing a new constraint for the supercapacitor banks as follows:

𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) ⋅ � 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 )
𝑘𝑘 ∈ 𝑆𝑆 𝐵𝐵 ≤ 𝑃𝑃 𝑆𝑆 𝐵𝐵 𝑓𝑓𝑐𝑐
( 𝑡𝑡 𝑚𝑚 ), ∀ 𝑡𝑡 ∈ [ 𝑡𝑡 𝑚𝑚 − 1
, 𝑡𝑡 𝑚𝑚 ].
(36)
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Since (36) is a convex inequality constraint, the OCCD in constrained ICA problem is
still a convex optimization problem. We propose the SCPL algorithm as follows. We first
break the whole charge allocation process into a series of short time slots
(0, 𝑡𝑡 1
, 𝑡𝑡 2
, . . . , 𝑡𝑡 𝑀𝑀 ). For each time slot, we observe the current solar irradiance level, make
prediction of the solar irradiance level over the rest time of the day, derive the power
upper limits for the supercapacitor banks, and solve the constrained ICA problem. The
SCPL algorithm is summarized as Algorithm 5.2. The SCPL algorithm solves the GCA
problems and derives the CTI voltage setting 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ), selected set of the EES banks
𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ), and the array charging currents � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) � for the selected EES banks over the

Algorithm 5.2. Global charge allocation solver with charging power limits (SCPL).
81

whole charge allocation process. Our claim that the proposed algorithm returns a near-
optimal solution of the GCA problem is based on the above flow in which each sub-
problem is solved near-optimally.
5.3.5 Temperature, aging, and malfunction handling
The optimal management policy of the HEES should account for the effect of
temperature. Intensive research has been conducted to study the battery behaviors at
various temperatures. It turns that the cycling capacity, i.e., battery charge 𝐶𝐶 𝑏𝑏 , 𝑓𝑓 𝑓𝑓 𝑐𝑐𝑐𝑐
, only
varies slightly (less than 5%) from 25
∘
𝐶𝐶 to 60
∘
𝐶𝐶 [101, 102]. The internal resistance of
the battery does not vary much (~10%) either with the temperature rising [101].
Therefore, we ignore the temperature effect in the proposed SCPL algorithm. The GCA
problem only solves the allocation problem for one charging process and does not
involve cycling.
The batteries age as the HEES system is being operated, which causes capacity fading
and the increase of internal resistance. Some known factors, such as the DOD and
average SoC significantly affect the battery aging. Thus, we perform Coulomb counting
for each EES bank, calculate the SoH degradation, and update model parameters
according to the SoH degradation. In fact, a high temperature significantly speeds up the
battery aging. We record the battery temperature so that we can accurately update the
characteristics of the aged battery including the battery capacity and internal resistances
[16, 59].
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In practice, a part of EES elements may have malfunction during runtime. We address
this issue at the bank level and system level. A more elaborated dynamic bank
reconfiguration [10] improves fine-granularity fault-tolerance of the EES bank, which is a
bank-level method. We simply exclude the unavailable banks from the set of available
EES banks at the system level. We update bank set 𝑆𝑆 at the beginning of each decision
epoch and perform the proposed method because the GCA problem is solved in a discrete
time manner.
5.4 Experimental Results
We consider two different HEES systems: one consists of four EES banks (two
supercapacitor banks and two battery banks), and the other consists of eight EES banks
(four supercapacitor banks and four battery banks.) We use the solar irradiance level data
that is collected in Los Angeles for year 2011 [103] and use PV modules with MPTT
technique [104] as the power source. We consider the charge allocation process lasting
for 12 hours and solve corresponding GCA problems using the proposed GCA algorithm
for both HEES systems. We extract the model parameters of chargers, Li-ion batteries,
and supercapacitors through real measurements based on the Linear Technology
LTM4607 converter [90], the GP1051L35 Li-ion battery cells [105] and the Maxwell
BCAP P270 series supercapacitor [93].
The baseline setups in the simulation include: i) unbiased bank charging (UB), the
input power is uniformly allocated into all EES banks; ii) battery banks first policy
(BBF), the input power is allocated into all battery banks; and iii) supercapacitor banks
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first scheme (SBF), the input power is allocated into all supercapacitor banks. The BBF
policy ignores the supercapacitor banks and is used to mimic the homogeneous battery-
only EES systems. Note that the SBF policy switches to BBF if all supercapacitor banks
are fully charged. We use a constant CTI voltage for the baseline setups during the whole
charge allocation process. We operate the baseline systems at several representative CTI
voltage values and compare the results with that of the proposed SCPL algorithm. We
investigate different solar irradiance levels in a year (April, July, September, and
December) and PV module configurations
2
(4 × 2, 2 × 4, 4 × 4, 4 × 6 for 4-bank HEES
system and 4 × 2, 4 × 4, 4 × 6, 6 × 6 for 8-bank HEES system), with 16 test cases in
total for each HEES system.
2
For a PV module with configuration of 𝑛𝑛 × 𝑚𝑚 , 𝑛𝑛 and 𝑚𝑚 denote the number of series
and parallel-connected PV cells, respectively.

Figure 5.3. Results of the proposed solar irradiance level predictor at 8 AM, 10 AM, and 12 AM. The
four groups from top to bottom are the average solar irradiance levels for Apr., Jul., Sep. and Dec.
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5.4.1 Solar irradiance level prediction
Figure 5.4 shows the monthly average solar irradiance level prediction using the
proposed online prediction method at three time instances: 8 AM, 10 AM, and 12 AM in
April, July, September, and December. We predict the solar irradiance level for the
remaining charge allocation process at each time instance. The average error of the
proposed prediction heuristic is less than 10%.
Figure 5.4 compares the total energy gain in HEES systems for all the 16 test cases
between the SCPL algorithm using proposed solar irradiance prediction and the SCPL

Figure 5.4. Comparisons of the GCA with the proposed solar prediction method and Oracle system
for the 4-bank HEES system (a) and the 8-bank HEES system (b).
85

algorithm using Oracle system
3
. Results shown in Figure 5.4 show that the performance
degradation of the proposed SCPL algorithm due to the misprediction is within 2%.
5.4.2 Power limit derivation
Figure 5.5 shows the power limit that is derived from the proposed heuristic for the 8-
bank HEES system and 4 × 6 PV module, using solar irradiance data in July. The line
with circle marks is the power limits of the supercapacitor banks and the line with cross
marks is the power that is allocated to the battery banks. We use the supercapacitor banks
to shave the peak of the power generation profile in order to alleviate the energy loss due
to rate capacity effect. Although the average duration with effective solar irradiance is
about 12 hours, we only use the supercapacitor banks from about 8 AM to 4 PM,
depending on the predicted solar irradiance level and when the power generation peak
3
The Oracle system has the perfect knowledge of the solar irradiance over the
remaining charge allocation process.

Figure 5.5. Power limit for supercapacitor banks (SBs) that is derived from the proposed heuristic.
The data is generated using the 8-bank HEES system with the 4X6 PV module. Simulated results are
obtained using solar data in Los Angeles in July.
86

happens. Since the self-discharge rate is larger when the supercapacitor banks have
higher SoCs, the proposed heuristic tends to assign more energy to supercapacitor banks
in later part of the charge allocation process. Therefore, the line with cross mark has
negative slope as shown in Figure 5.5. The value of power limit depends on the relative
magnitude between power generation rate, capacities of battery and supercapacitor banks.

87

5.4.3 Global charge allocation problem
Table 5.2. Comparison of normalized GCA results after a 12 hours charge allocation process for the
4-bank HEES system for UB policy..

Table 5.3. Comparison of normalized GCA results after a 12 hours charge allocation process for the
4-bank HEES system for SBF policy.

88

Table 5.4. Comparison of normalized GCA results after a 12 hours charge allocation process for the
4-bank HEES system for BBF policy.

Table 5.5. Comparison of normalized GCA results after a 12 hours charge allocation process for the
8-bank HEES system for UB policy.

89

Table 5.6. Comparison of normalized GCA results after a 12 hours charge allocation process for the
8-bank HEES system for SBF policy.

Table 5.7. Comparison of normalized GCA results after a 12 hours charge allocation process for the
8-bank HEES system for BBF policy.

90

We set the initial OCVs of battery banks and supercapacitor banks as 7.4V and 3.0V,
respectively, for the 4-bank HEES system. The 8-bank HEES system has the initial
OCVs of battery banks of 7.4V, 7.4V, 3.7V, and 3.7V, respectively, and 3.0V initial
OCVs for all the supercapacitor banks. The battery banks have large enough capacity to
accommodate all the energy generated from the PV modules while the supercapacitor
banks do not. Although the PV configuration is known, the power generated in PV
module is not fixed but depending on 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 in our problem setup since we apply MPTT.
Therefore, to have fair comparisons, we use total energy gain after the charge allocation
process as the measure of solution quality, i.e., the nominator in (24). We normalize the
total energy gain of the baseline systems to the results of the proposed SCPL algorithm in
Table 5.2 ~ Table 5.7.
Table 5.2, Table 5.3, and Table 5.3 summarize the GCA results of the proposed SCPL
algorithm and the selected baseline systems. The proposed SCPL algorithm consistently
outperforms the baseline systems by approximately 5% to 25% in general. Most
importantly, the HEES system using the proposed SCPL algorithm improves the energy
harvesting ability by up to 48% compared to the BBF policy, which ignores the
supercapacitor banks. This explains the poor performance of a homogeneous EES system
of the same battery banks.
Table 5.5, Table 5.6, and Table 5.7 show that the SBF policy generally performs well
with a smaller number of PV modules, e.g., configuration of 4 × 2 or 2 × 4, or lower
solar irradiance level, e.g., in December. In this case, the supercapacitor banks have
enough capacity to accommodate all energy generated by the PV modules. Hence, the
91

SBF policy takes the advantage of the high charging efficiency of the supercapacitor
banks. However, SBF policy suffers from serious performance degradation later on after
the supercapacitor banks are fully charged, as shown in the test cases for April and July
with 4 × 6 or 6 × 6 PV modules. In contrast, UB policy achieves good results for those
test cases with large amount of energy generation because it unbiasedly allocates
generated energy to all EES banks. The performance of UB policy is quite close to the
proposed SCPL algorithm in some corner cases because even the best energy allocation
does not help much when the energy generation rate is too high. However, in general, the
proposed SCPL algorithm outperforms UB policy by fully utilizing the high-efficiency
EES banks.
Since the optimal 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 depends on the energy generation profile, charge allocation
policy, SoCs and properties of EES banks, there is no way to determine a generally
optimal 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 . We observe a fluctuation of the total energy gain up to 20.7% in case of the
different 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 settings in Table 5.2 ~ Table 5.7. Hence, it is not surprising that an
inappropriate 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 can be often used in practice unless the proposed concept is widely
accepted. In contrast, the proposed SCPL algorithm searches and converges rapidly to the
optimal 𝑉𝑉 𝑐𝑐 𝑐𝑐 𝑐𝑐 .
Figure 5.6(a) shows the total instantaneous power gain of all the EES banks in the 8-
bank HEES system during the 12 hours charge allocation process. The SBF policy
performs well at the beginning but suffers from huge performance degradation after all
supercapacitor banks are fully charged. Figure 5.6(b) and (c) show that the average array
charging currents of supercapacitor banks drop to zero and the currents of battery banks
92

jump high at 1 PM. The SBF policy harvests less energy than BBF policy does afterwards
due to higher self-discharge from the fully charged supercapacitor banks. The UB and
BBF policies allocate charging power uniformly to all the EES banks. The proposed
SCPL algorithm activates the supercapacitor banks at 7 AM according to the solar
irradiance level and fully charges the supercapacitor banks at 4 PM. Figure 5.6 (a) shows
that SCPL algorithm outperforms the other baseline systems by properly allocating
charging power and determining the CTI voltage.

Figure 5.6. Comparison of total power gain (a), average array charging current of supercapacitor
banks (b) and battery banks (c), in the 8-bank HEES system with the 4X6 PV module. Simulated
using solar data in Los Angeles in July.
93

CHAPTER 6
CHARGE REPLACEMENT OPTIMIZATION
The charge replacement problem in the HEES system is to adaptively select EES banks
and determine discharging currents, from zero to a maximum limit, and voltage level
settings on a charge transfer interconnect (CTI) so that the given load demand is met and
the charge replacement efficiency is maximized. Note that the charge replacement
efficiency denotes the ratio between the energy requested by load devices and the energy
retrieved from the HEES system. In this chapter, we provide a mathematical formulation
for the global charge replacement (GCR) problem and propose an efficient algorithm to
solve it near-optimally. Precisely, the GCR problem is formulated as an optimization
problem where the objective function is the GCR efficiency and constraints are derived
from laws of energy and charge conservations. We account for the energy loss due to the
internal resistance of batteries, the power conversion energy loss, the rate capacity effect
of batteries, and the self-discharge of supercapacitors. We solve the GCR problem using
convex optimization methods while imposing an output power bound on battery banks in
order to avoid discharging supercapacitor banks too quickly (which could in turn degrade
the charge replacement efficiency).
We build a prototype HEES system with the purpose of exploring energy benefits
brought by the HEES system and validating the efficacy of the proposed GCR policy.
The prototype consists of three EES banks: one supercapacitor bank, one Li-ion battery
bank, and one lead-acid battery bank. We connect them to the CTI, which also connects
94

input sources and output loads through appropriate power converters. We first perform a
characterization process to obtain characteristics of EES banks and power converters, and
then derive the GCR policy based on the characterized information and load demand
profiles. We implement the GCR policy to automatically control charging currents and
voltage level settings for the CTI. We apply various types of representative load profiles
with different durations to test the functionality of implementation and the performance
of the proposed charge replacement algorithm. Experiments based on the realistic
prototype system show improvements up to 11.1% and 24.7% in terms of the GCR
efficiency against other HEES baselines and homogeneous EES baseline, respectively.
6.1 Charge Replacement Problem Statement
Figure 6.1 shows a schematic of the charge replacement process. The charge replacement
problem is constrained by laws of energy conservation. Let us consider a discharging
process starting from 𝑇𝑇 𝑠𝑠 and ending at 𝑇𝑇 𝑠𝑠 . As illustrated in Figure 6.1, the power

Figure 6.1. Schematic of the charge replacement problem in HEES systems.
95

delivered to the CTI is used to drive all load devices and corresponding DC-DC
converters. For 𝑡𝑡 ∈ [ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ], we have,
𝑃𝑃 𝐶𝐶 𝑇𝑇 𝐶𝐶 ( 𝑡𝑡 ) = 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ( 𝑡𝑡 ) � 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 )
𝑁𝑁 𝑘𝑘 = 1
= � � 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) + 𝑃𝑃 𝑐𝑐 , 𝑐𝑐 𝑖𝑖 ( 𝑡𝑡 ) �
𝑀𝑀 𝑖𝑖 = 1
, (37)
where 𝑁𝑁 and 𝑀𝑀 stand for the total number of EES banks and load devices, respectively.
The power provided by the 𝐽𝐽 -th EES array consists of two parts: the power delivered to
the CTI and the power loss in the charger. Thus, we have,

𝑃𝑃 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) = 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) = 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ) + 𝑃𝑃 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 )
= 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ) + 𝑃𝑃 𝑐𝑐 , 𝑘𝑘 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ) ⋅ 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 ( 𝑡𝑡 )
(38)
The initial EES element array OCVs 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 )|
𝑐𝑐 = 0
, ∀ 𝐽𝐽 ∈ 𝑆𝑆 are known based on the
initial SoCs of EES arrays, using the battery model [43]. We assume that the statistical
information of load profile, i.e., 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) and 𝑉𝑉 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) for 𝑡𝑡 ∈ [ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ], is given or
predictable. We make this assumption to simplify the presentation. Perfect knowledge of
load profiles is indeed neither possible nor necessary. In practice, the proposed algorithm
can take the statistics of the load profiles (e.g., average value and standard deviation of
the power demand and its duration) as inputs and determine discharging power bounds.
At each decision epoch, the proposed algorithm is applied to determine the discharging
currents from the actual power demand at that time and the corresponding discharging
power bound.

96

6.2 Charge Replacement Optimization Problem Formulation
We have described the GCR problem in Chapter 6.1. The GCR optimization problem can
be formulated as follows.
Given: 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 )|
𝑐𝑐 = 0
, ∀ 𝐽𝐽 ∈ 𝑆𝑆 , 𝑉𝑉 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) and 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) for 1 ≤ 𝑗𝑗 ≤ 𝑀𝑀 and 𝑡𝑡 ∈
[ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ].
Find: 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ( 𝑡𝑡 ), 𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ), and 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ), for ∀ 𝐽𝐽 ∈ 𝑆𝑆 and 𝑡𝑡 ∈ [ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ].
Maximize: the GCR efficiency, defined as:
𝜂𝜂 _( 𝐺𝐺𝐶𝐶 𝑅𝑅 ) =
∫
∑ 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 )
𝑀𝑀 𝑖𝑖 = 1
𝑇𝑇 𝑒𝑒 𝑇𝑇 𝑠𝑠 ∫
∑ 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑘𝑘 ( 𝑡𝑡 )
𝑁𝑁 𝑘𝑘 = 1
𝑇𝑇 𝑒𝑒 𝑇𝑇 𝑠𝑠 𝑑𝑑𝑡𝑡 (39)
The nominator in (39) is the integral of the load demand over the discharging process,
and therefore, is fixed. Thus, maximizing 𝜂𝜂 𝐺𝐺 𝐶𝐶 𝐺𝐺 is equivalent to minimizing
∫
∑ 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑘𝑘 ( 𝑡𝑡 )
𝑁𝑁 𝑘𝑘 = 1
𝑇𝑇 𝑒𝑒 𝑇𝑇 𝑠𝑠 𝑑𝑑𝑡𝑡
Subject to:
i) Energy conservation: (37), (38) are satisfied.
ii) Charge conservation: (4) is satisfied.
iii) The OCV-SoC and OCV-CCV relations for battery (4)(3) and supercapacitor (12).
iv) The bank discharging current is no less than zero, and the array discharging
current is no more than a maximum value,

𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ) ≥ 0, 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) ≤ 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑚𝑚 𝑐𝑐𝑒𝑒
, ∀ 𝑡𝑡 ∈ [0, 𝑇𝑇 ], ∀ 𝐽𝐽 ∈ 𝑆𝑆 .
(40)
If 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 ) = 0, the charger is turned off, i.e. 𝐽𝐽 ∉ 𝑆𝑆 𝑆𝑆 𝑛𝑛 ( 𝑡𝑡 ).
97

6.3 Near-optimal Charge Replacement Control Algorithm
We solve the GCR optimization problem in three steps. First, we present an efficient
heuristic for the instantaneous charge replacement (ICR) problem obtained by letting
𝑇𝑇 𝑠𝑠 → 𝑇𝑇 𝑠𝑠 in the GCR problem formulation. Second, we globally consider the complete
discharging process and derive discharging power bounds for battery banks to avoid
greedy results. Finally, we solve the GCR problem in a discrete time space by solving an
ICR problem at the beginning of each time slot with additional constraint of discharging
power bound.
6.3.1 Instantaneous charge replacement
As the ICR problem implies that 𝑇𝑇 𝑠𝑠 → 𝑇𝑇 𝑠𝑠 , we omit the time index 𝑡𝑡 in the GCR problem
formulation for simplicity in writing. We have EES array OCVs 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 , ∀ 𝐽𝐽 ∈ 𝑆𝑆 derived
from their SoCs, and the load profile 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 and 𝑉𝑉 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 for 1 ≤ 𝑗𝑗 ≤ 𝑀𝑀 . Optimization
variables are 𝑆𝑆 𝑆𝑆 𝑛𝑛 (or 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 , ∀ 𝐽𝐽 ∈ 𝑆𝑆 ), 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 and 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 , ∀ 𝐽𝐽 ∈ 𝑆𝑆 . We let 𝑇𝑇 𝑠𝑠 → 𝑇𝑇 𝑠𝑠 in (39). The
cost function for ICR as,

𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 = � 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑘𝑘 𝑁𝑁 𝑘𝑘 = 1
= � 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ⋅ � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 �
𝛾𝛾 𝑘𝑘 𝑁𝑁 𝑘𝑘 = 1
+ 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑘𝑘
(41)
We derive the constraints from (37), (38) and (40). The ICR optimization is a mixed-
integer non-linear programming problem due to the existence of binary variables 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 in
(38). Thus, optimally solving the ICR problem is an NP-Complete problem.
We first consider the optimal discharging current determination (ODCD) problem,
that is, finding the optimal 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 , ∀ 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 to minimize 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 , under the condition that
98

the selection set 𝑆𝑆 𝑆𝑆 𝑛𝑛 , CTI voltage 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , and 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 are given. In the ODCD problem, the
charger power loss 𝑃𝑃 𝑐𝑐 , 𝑘𝑘 is a quadratic function of 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 according to (15)~(17), and 𝑥𝑥 𝑐𝑐 , 𝑘𝑘
is always one for 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 . Thus the array discharging current 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 becomes a convex
function of 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 according to (38). In addition, 𝛾𝛾 𝑘𝑘 is greater than (for battery arrays) or
equal to (for supercapacitor arrays) one. Therefore, the cost function (41) becomes a
convex function of 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 , ∀ 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 as well, due to the rules of convexity of composite
functions [91]. Moreover, the inequality constraint (40) is convex, and the equality
constraint (37) is affine over the control variables of 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 , ∀ 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 . The constraint
(38) is already integrated into the objective function. Due to the above properties of the
cost function and constrains, the ODCD problem is a convex optimization problem and
can be solved using standard convex optimization tools in polynomial time. We propose
the following three heuristics, together with repeatedly solving the ODCD problem, to
determine 𝑆𝑆 𝑆𝑆 𝑛𝑛 , 𝑉𝑉 𝐶𝐶𝑇𝑇 𝐶𝐶 and 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 , ∀ 𝐽𝐽 ∈ 𝑆𝑆 for the ICR problem.
Heuristic 1: We assume that the optimal objective function 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 is a quasi-convex
function with respect to 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 . We first solve the ODCD problem with a fixed 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 value
and obtain the minimal value of 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ). Next we efficiently search the feasible
region of 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 to get the optimal 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 value that has the minimal 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 3F
4
. Simulation
4
We perform ternary search which converges to the optimal value for uni-model
function within log-time complexity. A ternary search is a divide and conquer-based
algorithm that determines either that the minimum or maximum cannot be in the first
99

results validate the assumption of quasi-convexity and prove the efficiency of searching
for the best-suited 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 value.
Heuristic 2: We initialize 𝑆𝑆 𝑆𝑆 𝑛𝑛 = 𝑆𝑆 and solve for proper 𝑆𝑆 𝑆𝑆 𝑛𝑛 in an iterative manner. In
each iteration, we only consider the banks 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 in ODCD problem, and thus 𝑥𝑥 𝑐𝑐 , 𝑘𝑘 is
always one. We update 𝑆𝑆 𝑆𝑆 𝑛𝑛 by excluding those banks whose discharging current 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘
is smaller than the threshold value at the end of that iteration. We repeat this process until
𝑆𝑆 𝑆𝑆 𝑛𝑛 converges.
Heuristic 3: We start from the initial condition that 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 = 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 . In each
iteration, we solve ODCD problem with fixed 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 and update 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 using (3)(12)
after the iteration. We repeat this process until all 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 converge.
In summary, these heuristics solve ICR problem in an iterative manner. We search the
𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 in the outer loop and use a fixed 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 in the ODCD problem in the inner loop. We
repeatedly solve ODCD problem and update 𝑆𝑆 𝑆𝑆 𝑛𝑛 and 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝐶𝐶𝐶𝐶 in the inner loop until they
converge. We obtain 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 𝑆𝑆 𝑐𝑐 𝑐𝑐 , 𝐽𝐽 ∈ 𝑆𝑆 𝑆𝑆 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 and the minimal value of 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ) at the fixed
third of the domain or that it cannot be in the last third of the domain. The procedure is
then repeated for the remaining two-third of the domain. For example, to minimize a uni-
modal function 𝑓𝑓 ( 𝑥𝑥 ) in interval [ 𝑥𝑥 1
, 𝑥𝑥 2
], we choose two points 𝑚𝑚 1
and 𝑚𝑚 2
so that 𝑚𝑚 1
=
𝑥𝑥 1
+
𝑒𝑒 2
− 𝑒𝑒 1
3
, 𝑚𝑚 2
= 𝑥𝑥 2
−
𝑒𝑒 2
− 𝑒𝑒 1
3
. We update the boundary of the interval as 𝑥𝑥 2
= 𝑚𝑚 2
if
𝑓𝑓 ( 𝑚𝑚 1
) < 𝑓𝑓 ( 𝑚𝑚 2
), and 𝑥𝑥 1
= 𝑚𝑚 1
otherwise. We repeat this process and find the minimal
point when this method converges.
100

𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 . We finally pick the 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 value that gives the minimal 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 value. The complete
algorithm is given in Algorithm 6.1. This algorithm converges because 1) ternary search
always converges; and 2) the number of EES banks in selection set 𝑆𝑆 𝑆𝑆 𝑛𝑛 does not increase.
No convergence issue is experienced when performing this algorithm.

Algorithm 6.1. The ICR solver (ICRS).
6.3.2 Global charge replacement
The GCR problem considers the optimization problem to maximize the GCR efficiency
for the complete discharging process. We break the discharging process into a series of
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time slots and solve the GCR in a discrete time space. The time slot is short enough so
that the SoC of EES banks are approximately unchanged during that time slot. Thus we
solve an ICR problem during each time slot and update SoCs of EES banks afterwards. A
simple method may solve a series of ICR problems one at a time slot to tackle the GCR
problem, which may fail to achieve the global optimality due to its greedy nature. In fact,
the proposed ICR solver prefers to retrieve more energy from the supercapacitor banks
because of the higher cycle efficiency. Thus, it is highly likely that all supercapacitor
banks may be fully discharged at very early stage. The consequence is that we have to
discharge the battery banks at higher rates for the rest of the discharging process, which
causes more energy loss due to the rate capacity effect and in turn hurts the GCR
efficiency. Therefore, it is necessary to "globally consider the complete discharging
process" and properly assign energy demands to different types of EES banks.
6.3.2.1 Estimation of discharging power sounds
We start from the fact that battery banks are generally less efficient compared to
supercapacitor banks in supplying higher load demands, due to their relatively large
internal resistances and the rate capacity effect. Thus, we can achieve high GCR
efficiency by limiting discharge currents of the battery banks in relatively low levels
while using the supercapacitor banks to shave the peak power demands. Inspired by this
idea, we classify all EES banks into two main categories without loss of generality:
supercapacitor banks and battery banks, due to their distinct characteristics.
We introduce discharging power bounds, denoted by 𝑃𝑃 ∗
( 𝑡𝑡 ), and define it as the lower
bound of power provided by all battery banks. We define effective energy of a category as
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the energy delivered to load devices from all banks in that category, excluding the energy
loss due to internal resistance, rate capacity effect, and power conversion. We denote
effective energy provided by the supercapacitor and battery banks by 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝑆𝑆 𝐵𝐵 and 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝐵𝐵𝐵𝐵
, and
have,

𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝐵𝐵𝐵𝐵
≤ � 𝑚𝑚 𝑖𝑖 𝑛𝑛 � � 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 )
𝑀𝑀 𝑖𝑖 = 1
, 𝑃𝑃 ∗
( 𝑡𝑡 ) �
𝑇𝑇 𝑒𝑒 𝑇𝑇 𝑠𝑠 𝑑𝑑𝑡𝑡 ,
𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝑆𝑆 𝐵𝐵 = � � 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑖𝑖 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑀𝑀 𝑖𝑖 = 1
𝑇𝑇 𝑒𝑒 𝑇𝑇 𝑠𝑠 − 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝐵𝐵𝐵𝐵
= 𝐸𝐸 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
− 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝐵𝐵𝐵𝐵

(42)
where 𝐸𝐸 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
is the total energy requested by all load devices. According to (42), deriving
𝑃𝑃 ∗
( 𝑡𝑡 ) depends on the load demand profiles and 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝑆𝑆 𝐵𝐵 . We estimate 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝑆𝑆 𝐵𝐵 in the way that
we want to fully utilize the energy stored in supercapacitor banks during the discharging
process. We may typically set 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝑆𝑆 𝐵𝐵 to be 80%~90% of total energy available in all
supercapacitor banks, denoted by 𝐸𝐸 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑆𝑆 𝐵𝐵 , to leave some margin for the energy loss due to
power conversion and self-discharge.
Discharging power bounds 𝑃𝑃 ∗
( 𝑡𝑡 ) set a lower bound for the discharging power of all
battery banks, which in turns becomes an upper bound for the discharging power of all
supercapacitor banks, and thereby prevents completely discharging all supercapacitor
banks at very early stage. To present the heuristic to determine the 𝑃𝑃 ∗
( 𝑡𝑡 ), we first start
from a proposition.
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Proposition. A constant 𝑃𝑃 ∗
( 𝑡𝑡 ) during the discharging process [ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ] yields the
minimal amount of energy drawn from battery banks, when the self-discharge of
supercapacitor banks and dependence of battery OCV on SoC are ignored.
The total energy drawn from battery banks is

𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝐵𝐵𝐵𝐵
= � � 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝛾𝛾 𝑘𝑘 ( 𝑡𝑡 )
𝑘𝑘 ∈ 𝐵𝐵𝐵𝐵
𝑇𝑇 𝑒𝑒 𝑇𝑇 𝑠𝑠 𝑑𝑑𝑡𝑡
(43)
We let 𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝑆𝑆 𝐵𝐵 to be 90% of 𝐸𝐸 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑆𝑆 𝐵𝐵 in (42), thus we have

𝐸𝐸 𝑠𝑠 𝑓𝑓𝑓𝑓
𝐵𝐵𝐵𝐵
= 𝜂𝜂 0
� � 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑘𝑘 ∈ 𝐵𝐵𝐵𝐵
𝑇𝑇 𝑒𝑒 𝑇𝑇 𝑠𝑠 = 𝐸𝐸 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
− 0.9 𝐸𝐸 𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑆𝑆 𝐵𝐵
(44)
where 𝜂𝜂 0
accounts for the conversion efficiency. Note that the RHS in (44) is a fixed
value and (43) is a convex function of discharging currents. Therefore, ignoring the VOC
changes with respect to SoCs, a fixed 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) during [ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ] results in minimal
𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝐵𝐵𝐵𝐵
. Note that if there exists 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 1
) and 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 2
) such that 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 1
) ≠
𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 2
), we can always find better solution which is 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ′
= �𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 1
) +
𝐼𝐼 𝑐𝑐 𝑐𝑐𝑐𝑐𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 2
) � /2 at time instance 𝑡𝑡 1
and 𝑡𝑡 2
. This is because that �𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 1
) �
𝛾𝛾 𝑘𝑘 +
�𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 2
) �
𝛾𝛾 𝑘𝑘 > 2 � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ′
�
𝛾𝛾 𝑘𝑘 for 𝛾𝛾 𝑘𝑘 > 1. ■
Based on this proposition, we determine a constant discharging power bound 𝑃𝑃 ∗
( 𝑡𝑡 ) =
𝑃𝑃 0
∗
for 𝑡𝑡 ∈ [ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ], which is shown as Line (a) in Figure 6.2. The value of 𝑃𝑃 0
∗
is
determined using binary search.
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We account for the self-discharge of supercapacitor banks and the dependence of
battery OCVs on SoCs after we obtain 𝑃𝑃 ∗
( 𝑡𝑡 ) = 𝑃𝑃 0
∗
for 𝑡𝑡 ∈ [ 𝑇𝑇 𝑠𝑠 , 𝑇𝑇 𝑠𝑠 ]. According to (14), the
self-discharge rate is proportional to the remaining energy in a supercapacitor array.
Therefore, a straight line 𝑃𝑃 ∗
( 𝑡𝑡 ) = 𝜌𝜌 ⋅ 𝑡𝑡 + 𝑃𝑃 ∗
(0) with positive slope 𝜌𝜌 , shown as Line (b)
in Figure 6.2, reduces the total self-discharge energy loss by allowing more energy to be
retrieved from supercapacitor banks at the early stage. We use the flat 𝑃𝑃 0
∗
line as a
reference and construct the slope curve with the same integral area.
The value of slope 𝜌𝜌 determines the tradeoff between the energy loss due to rate
capacity effect in battery banks and the energy loss due to self-discharge in
supercapacitor banks. The greater slope 𝜌𝜌 , on the one hand, consumes more energy in
battery banks due to the rate capacity effect. This is because that 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝐵𝐵𝐵𝐵
is a super-linear
function of 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑘𝑘 ( 𝑡𝑡 ) for every battery bank, according to (43). On the other hand, 𝜌𝜌 =
0 results in slow discharging supercapacitor banks at the early stage, which causes a high
self-discharge energy loss in supercapacitor banks. Therefore, the total energy drawn

Figure 6.2. Line (a) and (b) show the discharging power bounds. The shadow area and white area
under Pload(t) curve denote the Eeff
BB
and Eeff
SB
, respectively.
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from the HEES system, including the energy loss due to both the rate capacity effect and
self-discharge, is a unimodal function with respect to the slope.
We perform ternary search to efficiently search in a proper interval of 𝜌𝜌 , from zero to
reasonable upper limit, to determine the appropriate slope 𝜌𝜌 . We pick two slopes, 𝜌𝜌 1
and
𝜌𝜌 2
, that correspond to one-third and two-third points of the current interval [𝜌𝜌 𝑚𝑚 𝑐𝑐𝑛𝑛 , 𝜌𝜌 𝑚𝑚 𝑐𝑐𝑒𝑒
]
in each iteration. We construct the discharging power bound curves, 𝑃𝑃 1
∗
( 𝑡𝑡 ) and 𝑃𝑃 2
∗
( 𝑡𝑡 ),
with 𝜌𝜌 1
and 𝜌𝜌 2
, respectively, and let them have the same integral area with the flat 𝑃𝑃 0
∗
line.
Then we calculate the total energy drawn 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 1
𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 and 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 2
𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 accordingly, considering
the rate capacity effect and change of VOCs with respect to SoCs in battery banks, and
self-discharge in supercapacitor banks. We drop the left third of the if 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 1
𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 >
𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 2
𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 and right third otherwise. We repeat this procedure until the optimal slope 𝜌𝜌 𝑆𝑆 𝑐𝑐 𝑐𝑐
is found. A more rigorous (but also computationally more expensive) method to derive
the power bound is presented in [11], in which an optimization problem is formulated and
solved using the method of Lagrange multiplier. To reduce the computational overhead,
we use the method presented above to implement the control policy in the HEES
prototype.
6.3.2.2 Solving the GCR problem
We solve the GCR problem hierarchically. At the top level, we globally consider the
complete discharging process before discharge begins and find the optimal discharging
power bounds 𝑃𝑃 ∗
( 𝑡𝑡 ) over the discharging process. At the bottom level, we break the
discharging process into a series of time slots and solve a series of ICR problems,
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accounting for all kinds of energy loss in detail. At the beginning of a time slot, we solve
an ICR problem using the ICRS in Algorithm 6.1 with an additional constraint given by:

𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ( 𝑡𝑡 ) � 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑘𝑘 ( 𝑡𝑡 )
𝑘𝑘 ∈ 𝐵𝐵𝐵𝐵
≥ 𝑚𝑚 𝑖𝑖 𝑛𝑛 � 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
𝑐𝑐 𝑆𝑆 𝑐𝑐 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ), 𝑃𝑃 ∗
( 𝑡𝑡 ) �
(45)
Since (37) is an affine inequality constraint, the constrained ODCD problem can still
be solved optimally in polynomial time. Therefore, the GCR solution is obtained by
solving ICR problem for each time slot and combining the solutions together. To improve
the GCR solutions, we may refine the estimation of discharging power bounds 𝑃𝑃 ∗
( 𝑡𝑡 )
according to the actual remaining energy in supercapacitor arrays over the discharging
process.
We solve the convex optimization problem by using Matlab (recall that convex
programs can be solved efficiently). The average time needed to determine the
discharging currents at the beginning of each decision epoch is 2.4 seconds for an 8-bank
HEES system. The configuration of the host machine is an Intel Duo Core 2.4GHz and
4G memory. This runtime is negligible compared to the duration of each decision epoch,
which is typically set to 10~15 minutes.
6.4 Experimental Results
We compare our near-optimal charge replacement control policy (NCR) derived from the
previous section, with three baseline setups: equal current discharging (ECD, i.e., all
banks are discharged at the same current), the most efficient bank tracking (MEBT, i.e.,
keep allocating power demand to the currently most efficient and not fully utilized bank
until the load demand is satisfied), and the supercapacitor banks first (SBF, i.e., start
107

with discharging all supercapacitor banks with the same current and discharge battery
banks after the supercapacitor banks are fully discharged.)
6.4.3 Instantaneous charge replacement
We compare our near-optimal charge replacement policy with the baseline setups
applying the above representative instantaneous discharge processes with a high (100 W),
a medium (50W) and a low (10W) power demand to two different HEES systems. One
consists of eight EES banks with four supercapacitor banks and four battery banks. We
set the OCVs of the eight EES banks to 16V, 16V, 4V, 4V, 6V, 6V, 12V, 12V,
respectively. The other HEES system consists of four EES banks with two supercapacitor
banks and two battery banks. We set the OCVs of the four EES banks to 16V, 4V, 6V,
12V, respectively. Figure 6.3 shows up to 30% improvement in terms of charge
replacement efficiency with our policy. We notice that the efficiencies of the baseline
setups are strongly dependent on the environmental factor (e.g., load power) and the
HEES system configuration (e.g., number of banks.) Thus no baseline setup consistently
outperforms other baseline setups. Lacking of knowledge of the optimal CTI voltage, the

Figure 6.3. Comparison of ICR efficiencies on eight-bank (a) and four-bank (b) HEES systems with
high, median and low power demand.
108

efficiencies of baseline setups are not stable but typically fluctuate in a range of 5% along
with the load power demand.
6.4.1 Global charge replacement
We use power profiles from military radio receivers [98] as the load profiles, which
consist of periodic power demand levels of 10W, 100W, and 5W for Profile 1, and 5W,
and 70W for Profile 2 with a period of 10 minutes. We test our policy on Profile 1 and 2
with two different operating time cases: a long case for 8 hours and a short case for 4
hours. We assume all EES arrays are fully charged before discharge begins. Figure 6.4
shows that our near-optimal charge replacement policy consistently outperforms all
baseline setups. The GCR efficiency improvements range up to 28% in eight banks
HEES system (a) and 24% in four banks HEES system (b).
Comparing our policy with the baseline setups, we find that the aggressive baseline
systems, such as MEBT and SBF, may perform well if the energy stored in the
supercapacitor banks is capable of supporting the load demands in short operation time
cases (Figure 6.4(a) 2S.) However, our policy still outperforms these aggressive baseline

Figure 6.4. Comparison of GCR efficiencies on eight-bank (a) and four-bank (b) HEES systems with
load Profile 1 and 2, at long and short operation time.
109

setups due to better discharge control among different supercapacitor banks. Furthermore,
significant GCR efficiency improvements against MEBT and SBF are observed in the
long operation time cases because supercapacitor banks do not have enough energy while
our policy exhibits near-optimal utilization of the energy from both the battery and
supercapacitor banks. The conservative policy such as ECD leads to steady performance
in all cases, but our policy still outperforms it by the near-optimal setting of the bank
discharging currents, selective turning off the low efficiency banks to avoid constant
controller power loss in the chargers and full utilization of energy in the high efficiency
EES banks.

110

CHAPTER 7
CHARGE MIGRATION OPTIMIZATION
This chapter introduces the charge migration scheduling (CMS) problem in HEES
systems, which in turn enables a number of concurrent MSMD charge migrations through
a fixed number of CTIs while meeting a global deadline constraint. In the CMS problem,
we have a number of MSMD migration tasks, where each task is defined as delivering a
fixed amount of energy from a given set of source EES banks to another set of destination
EES banks within a deadline. The objective is to maximize the overall charge migration
efficiency (by minimizing the charge that is extracted from the source banks since the
charge that is delivered to the destinations banks is specified as part of the problem
statement.)
The solution to the CMS problem requires solving the following sub-problems. First,
we must determine the optimal CTI voltage and charging current profile for each MSMD
migration task. This also depends on the duration the migration process. Second, we must
decide whether two MSMD migration tasks should be merged. Merging two migration
tasks will force both of them to utilize the same CTI, and thus, adopt the same CTI
voltage during the migration process. To ensure that the overall charge migration
efficiency for the merged task is higher than those of the individual (non-merged)
migration tasks, we only allow merges between tasks that have similar optimum CTI
voltage levels. Third, we assign a CTI to the migration task among the available CTIs and
calculate the CTI usage time, defined as the duration the migration process. Notice that
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merging two migration tasks into one reduces the resource overhead (i.e., the number of
CTIs used is reduced), but the optimum realization of the merged migration task may also
result in an increase in the usage time of the shared CTI. In case of a deadline violation,
the CTI usage time for the merged task must be reduced to the given deadline at the
expense of a sub-optimal realization of the merged migration task. Unfortunately, the
optimal solutions of the three sub-problems are not independent but coupled to each
other.
We formulate the CMS problem as an optimization problem and solve it in an
iterative manner since the three sub-problems mentioned above are coupled. More
precisely, we start from the time-unconstrained migration of each migration task and
calculate the optimal migration time. Next we reduce the CTI usage time while
minimizing the increase of the total energy drawn from the sources at each step until the
deadline constraint is met. During the usage time reduction, we derive the optimal CTI
voltage and charging current profile over time by using non-linear fractional
programming. We will merge multiple migration tasks if the merged migration task
yields higher migration efficiency than those of the separate ones. We converge to the
final solution for the CMS problem when all the migration tasks are scheduled to
complete by the given deadline, and no further merging can improve the charge migration
efficiency. Experimental results demonstrate significant charge migration efficiency
improvements of up to 32.2% compared to baseline setups in example HEES systems.
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7.1 Charge Migration Scheduling Problem Statement
Table 7.1. Notation used in Chapter 7. The notations are more complicated than the charge
allocation and charge replacement problem.
Symbol Definition
The following notation relates to the 𝑖𝑖 -th EES bank in the 𝑛𝑛 -th migration task
𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑑𝑑 𝑠𝑠𝑐𝑐 ), 𝑂𝑂 𝐶𝐶 ( 𝐶𝐶𝐶𝐶 )
Open (closed) circuit voltage of the EES array
𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑑𝑑 𝑠𝑠𝑐𝑐 )

Current between the source (destination) EES array and its
discharging (charging) control charger
𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑑𝑑 𝑠𝑠𝑐𝑐 )
Current between the EES bank and its CTI
𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑑𝑑 𝑠𝑠𝑐𝑐 )

Equivalent current inside the EES array, considering the rate
capacity effect
𝑃𝑃 𝑐𝑐 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑑𝑑 𝑠𝑠𝑐𝑐 )
Power conversion loss in chargers of the EES bank
𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑑𝑑 𝑠𝑠𝑐𝑐 )
Self-discharge power loss of the EES array
𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 Power drawn from the source EES bank
𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
Power pushed into the destination EES bank
The following notation relates to the 𝑛𝑛 -th migration task:
{ 𝑆𝑆 𝑒𝑒 𝑐𝑐 }
𝑛𝑛 , { 𝐷𝐷 𝑠𝑠𝑡𝑡 }
𝑛𝑛 Set of source or destination EES banks
𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 Voltage setting of the CTI
𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 Total energy drawn from all the source EES banks
𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐

Target amount of energy to be pushed into the destination EES
bank after the migration process
𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 CTI usage time that is assigned to the migration task
𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗

Global optimal CTI usage time as determined by the time-
unconstrained MSMD solution (cf. Section 4.2)
𝑇𝑇 𝐺𝐺 , 𝑇𝑇 𝐷𝐷 Arrival time and deadline of the migration process
113

The notations are slightly more complicated than previous several problem setups
because migration task id becomes another index. We skip the SSSD migration and
MSMD migration, and focus on the more general charge migration problem – charge
migration scheduling (CMS) problem. The SSSD and MSMD can be solved using our
CMS framework. CMS problem in HEES systems enables a number of concurrent
MSMD charge migrations through a fixed number of CTI’s while meeting a global
deadline constraint. The 𝜂𝜂 𝐶𝐶 𝑀𝑀 depends on the properties and SoC’s of the source and
destination EES banks, charging current, CTI voltage, amount of energy to be migrated,
and deadline constraint. We denote the amount of energy to be migrated by target energy.
We define a migration task as: 𝑇𝑇 ({ 𝑆𝑆 𝑒𝑒𝑐𝑐 }, � 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
� , 𝑇𝑇 𝐺𝐺 , 𝑇𝑇 𝐷𝐷 ), where { 𝑆𝑆 𝑒𝑒 𝑐𝑐 } is the set
of source EES banks, { 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
} is the set of destination EES banks and target energy
for each destination EES bank, 𝑇𝑇 𝐺𝐺 is the arrival time, and 𝑇𝑇 𝐷𝐷 is the deadline for this
migration task. The target energy 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
is defined as the energy to be stored into the
destination EES bank after the migration process, which is generally less than the energy
drawn from source EES bank due to the energy loss during the migration process.
We make two assumptions without loss of generality while making the description
succinct. First, each migration task is a set of mutual exclusive SSSD migrations, i.e., all
source banks and destination banks are one-to-one paired up in one migration task. For
all the SSSD migrations in one task, they must share one CTI and start migration
simultaneously. Second, all migration tasks arrive at the beginning of the whole
migration process and have the same deadline constraint. However, they may not finish at
114

the same time, since one SSSD migration can disconnect its source bank and destination
bank from CTI once target energy 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
is received by the destination bank. Based on
two assumptions, we can merge multiple migration tasks to form a new migration task:

𝑇𝑇 ′
= 𝑇𝑇 1
∪ 𝑇𝑇 2
∪ … ∪ 𝑇𝑇 𝑛𝑛 = 𝑇𝑇 � { 𝑆𝑆 𝑒𝑒 𝑐𝑐 }
1
∪ { 𝑆𝑆 𝑒𝑒 𝑐𝑐 }
2
∪ … ∪ { 𝑆𝑆 𝑒𝑒 𝑐𝑐 }
𝑛𝑛 , � 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
�
1
∪ � 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
�
2
∪ … ∪ � 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
�
𝑛𝑛 , 𝑇𝑇 𝐺𝐺 , 𝑇𝑇 𝐷𝐷 � .
(46)
Figure 7.1 presents a schematic of the CMS problem. We place the source banks and
destination banks on left hand side and right hand side for visualization purpose. We have
𝑁𝑁 charge migration tasks where each of them contains 𝑚𝑚 𝑛𝑛 ( 𝑛𝑛 ∈ {1,2, … , 𝑁𝑁 }) source EES
banks destination EES banks. We denote the i-th ( 𝑖𝑖 ∈ {1, 2, … , 𝑚𝑚 𝑛𝑛 }) source EES banks in

Figure 7.1. Schematic of the charge migration scheduling problem.
115

the n-th( 𝑛𝑛 ∈ {1, 2, … , 𝑁𝑁 }) migration task by 𝑆𝑆 𝑒𝑒 𝑐𝑐 ( 𝑛𝑛 , 𝑖𝑖 ), and a similar notation is applied to
the destination bank 𝐷𝐷 𝑠𝑠𝑡𝑡 ( 𝑛𝑛 , 𝑖𝑖 ).
We have 𝑆𝑆 number of CTI’s. Each EES bank is connected to all the CTI’s through 𝑆𝑆
on/off switches, denoted as blank dot in Figure 7.1. No more than one switch among
these 𝑆𝑆 switches can be turned on for each EES bank at a time. If we decide to use s-th
( 𝑠𝑠 ∈ {1, 2, … , 𝑆𝑆 }) CTI for n-th migration task, we turn on the s-th switch of all the source
and destination banks involved in n-th migration task. The voltage level setting of n-th
migration task is denoted by 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ). In this case, the s-th CTI is occupied by the n-th
migration task and not available for any other migration tasks, assuming that all
migration tasks that want to share s-th CTI have been merged into n-th migration task.
We only consider very limited number of CTI’s (no more than four) considering the cost
of the switches.

𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) = 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 , 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) + 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 )
= 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 , 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) �
𝛾𝛾 𝑛𝑛, 𝑖𝑖 + 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ),
(47)
where 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) is the equivalent current inside the source bank 𝑆𝑆 𝑒𝑒 𝑐𝑐 ( 𝑛𝑛 , 𝑖𝑖 ). The Peukert
constant γ
n, i
is greater than one if the source bank 𝑆𝑆 𝑒𝑒 𝑐𝑐 ( 𝑛𝑛 , 𝑖𝑖 ) is a battery bank and equal to
one for a supercapacitor bank. The discharging control charger of the source bank
𝑆𝑆 𝑒𝑒 𝑐𝑐 ( 𝑖𝑖 , 𝑗𝑗 ) has a conversion power loss of 𝑃𝑃 𝑐𝑐 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 , given by (15)(16)(17). Thus the power
contribution by 𝑆𝑆 𝑒𝑒 𝑐𝑐 ( 𝑛𝑛 , 𝑖𝑖 ) to its connected CTI is given by:
𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 , 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) = 𝑃𝑃 𝑐𝑐 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) + 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) (48)
116

At the destination side, the power provided to the destination bank 𝐷𝐷 𝑠𝑠𝑡𝑡 ( 𝑛𝑛 , 𝑖𝑖 ) is the
power retrieved by its charging control charger from the CTI, excluding the conversion
power loss 𝑃𝑃 𝑐𝑐 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), which is:
𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) = 𝑃𝑃 𝑐𝑐 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) + 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐 , 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) (49)
Again, the power stored into destination bank 𝐷𝐷 𝑠𝑠𝑡𝑡 ( 𝑛𝑛 , 𝑖𝑖 ) is less than the powering
delivered to it due to the rate capacity effect:

𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) = 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐 , 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) − 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 )
= 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐 , 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) ⋅ � 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) �
𝛽𝛽 𝑛𝑛, 𝑖𝑖 − 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠 𝑐𝑐 ( 𝑡𝑡 )
(50)
where the constant 𝛽𝛽 𝑛𝑛 , 𝑐𝑐 is less than one if the destination bank 𝐷𝐷 𝑠𝑠𝑡𝑡 ( 𝑛𝑛 , 𝑖𝑖 ) is a battery bank
and equal to one if it is a supercapacitor bank, and 𝑃𝑃 𝑠𝑠 𝑑𝑑 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) is the self-discharge of the
EES array, given by (14). Since each migration task is a set of many SSSD migrations,
for each SSSD migration, we have:
𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) = 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ) ⋅ 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) (51)
We apply a reasonable setting of the outputs of the discharging control charger of
𝑆𝑆 𝑒𝑒 𝑐𝑐 ( 𝑛𝑛 , 𝑖𝑖 ) and the charging control charger of 𝐷𝐷 𝑠𝑠𝑡𝑡 ( 𝑛𝑛 , 𝑖𝑖 ) such that generally the
contribution of the source bank matches the consumption of the destination bank for the
SSSD pair ( 𝑛𝑛 , 𝑖𝑖 ).

117

7.2 Charge Migration Scheduling Optimization Problem Formulation
We formulate the CMS problem as following.
Given:
(i) all the initial migration tasks 𝑇𝑇 𝑛𝑛 = ({ 𝑆𝑆 𝑒𝑒𝑐𝑐 }
𝑛𝑛 , � 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
�
𝑛𝑛 , 0, 𝑇𝑇 𝐷𝐷 ), 𝑛𝑛 ∈
{1,2, … 𝑁𝑁 }at time 𝑡𝑡 = 0, each initial task is a SSSD migration;
(ii) The SoC’s of all the source and destination EES banks, 𝑆𝑆𝑆𝑆 𝐶𝐶 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 )|
𝑐𝑐 = 0
,
𝑆𝑆𝑆𝑆 𝐶𝐶 𝑘𝑘 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 )|
𝑐𝑐 = 0
, 𝑖𝑖 ∈ {1,2, … , 𝑚𝑚 𝑛𝑛 }, 𝑛𝑛 ∈ {1,2, … 𝑁𝑁 };
(iii) 𝑆𝑆 number of available CTI’s during the time period (0, 𝑇𝑇 𝐷𝐷 ).
Find:
(i) Merged migration tasks 𝑇𝑇 𝑛𝑛 ′
′
= � { 𝑆𝑆 𝑒𝑒 𝑐𝑐 }
𝑛𝑛 ′, � 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
�
𝑛𝑛 ′
, 0, 𝑇𝑇 𝐷𝐷 � , 𝑛𝑛 ′
∈
{1,2, … , 𝑁𝑁 ′ } and 𝑁𝑁 ′
≤ 𝑁𝑁 ;
(ii) CTI usage time of each migration task, 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ′
𝑆𝑆 𝑐𝑐 𝑐𝑐 , 𝑛𝑛 ′
∈ {1,2, … , 𝑁𝑁 ′
};
(iii) Charging current profile and CTI voltage for each destination bank,
𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 ′
, 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ′( 𝑡𝑡 ), 𝑖𝑖 ∈ {1,2, … , 𝑚𝑚 𝑛𝑛 ′}, 𝑛𝑛 ′
∈ {1,2, … 𝑁𝑁 ′
}, 𝑡𝑡 ∈ (0, 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ′
𝑆𝑆 𝑐𝑐 𝑐𝑐 ), for
𝑛𝑛 ′
𝑐𝑐 ℎ
task.
Maximize: charge migration efficiency, defined as
𝜂𝜂 𝑀𝑀 𝑆𝑆 𝑀𝑀 𝐷𝐷 =
∑
∫
∑ 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 ′
, 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑚𝑚 𝑛𝑛 ′
𝑐𝑐 = 1
𝑐𝑐 𝐶𝐶𝐶𝐶𝐶𝐶 , 𝑛𝑛 ′
0
𝑁𝑁 ′
𝑛𝑛 ′
= 1
∑
∫
∑ 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 ′
, 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑚𝑚 𝑛𝑛 ′
𝑐𝑐 = 1
𝑐𝑐 𝐶𝐶𝐶𝐶𝐶𝐶 , 𝑛𝑛 ′
0
𝑁𝑁 ′
𝑛𝑛 ′
= 1
(52)
Subject to:
(i) Target energy constraint: 𝐷𝐷 𝑠𝑠𝑡𝑡 ( 𝑛𝑛 ′
, 𝑖𝑖 ) receives:
118

� 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 ′
, 𝑐𝑐 𝑑𝑑 𝑠𝑠 𝑐𝑐 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑐𝑐 𝐶𝐶𝐶𝐶𝐶𝐶 , 𝑛𝑛 ′
0
= 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 ′
, 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐
(53)
for all 𝑖𝑖 ∈ {1,2, … , 𝑚𝑚 𝑛𝑛 ′}, 𝑛𝑛 ′
∈ {1,2, … , 𝑁𝑁 ′ };
(ii) Deadline constraint:

𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ′ ≤ 𝑇𝑇 𝐷𝐷 , ∀ 𝑛𝑛 ′
∈ {1,2, … , 𝑁𝑁 ′ }
� 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ′
𝑁𝑁 ′
𝑛𝑛 ′
= 1
≤ 𝑆𝑆 ⋅ 𝑇𝑇 𝐷𝐷
(54)
Note that due to the characteristics of charge migration task, we can break the
CTI usage time 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ′ of a migration task into many short time periods and
finish them separately. Therefore, if the CTI usage time of each migration task
is shorter than 𝑇𝑇 𝐷𝐷 , there is always a scheduling to arrange all migration tasks
without violating deadline constraint.
(iii) Energy conservation: (47) ~(51) are satisfied;
(iv) EES array charge conservation: (4) is satisfied.
7.3 Near-Optimal Charge Migration Scheduling Algorithm
Two important factors affect 𝜂𝜂 𝐶𝐶 𝑀𝑀 according to our theoretic model.
First, there exists the optimal charging/discharging current for each SSSD migration.
On one hand, we have to charge/discharge the EES banks using larger currents than this
optimal value when the target energy is large and/or deadline is relatively tight.
According to (4), the energy drawn from (stored into) the source (destination) EES
bank(s) increases super-linearly (sub-linearly) with respect to the discharging (charging)
current. In other words, more energy is wasted due to the rate capacity effect. On the
other hand, if we use a smaller charging/discharging current than the optimal value, the
119

charge migration process becomes slower so that more energy will be wasted due to the
switching loss and controller loss, which are independent of operation current. An
example result of charge migration efficiency versus charging current for a typical
migration process is shown in Figure 7.2 left panel.
Second, the power converters achieve the maximum conversion efficiency, defined as
the ratio of output power and input power, when the mismatch of input and output
voltage, i.e., | 𝑉𝑉 𝑐𝑐 𝑛𝑛 − 𝑉𝑉 𝑆𝑆 𝑓𝑓𝑐𝑐
|, is minimized. According to (15), (16) and (17), the conduction
power loss decreases as the voltage mismatch is reduced. Figure 7.2 right panel shows the
conversion efficiency of power converter versus the ratio of output and input voltage for
a typical migration process.
The two important factors above guide our CMS algorithm. The migration tasks
typically have the different optimal CTI voltages due to the different SoC’s of the EES
banks. Merging two or more migration tasks allows the scheduler to assign a longer CTI
usage time so that it can improve the migration efficiency. However, merged migration

Figure 7.2. Charge migration efficiency versus charging current (left) and converter efficiency versus
output voltage (right).
0.5 1 1.5
0.75
0.8
0.85
Charging Current (A)
Migration Efficiency

V
cti
=10V
V
cti
=12V
V
cti
=14V
0.5 1 1.5
0.85
0.9
0.95
V
out
/ V
in
Conversion Efficiency

I
in
=0.75A
I
in
=1.25A
120

tasks have to use the same CTI voltage, which causes migration efficiency degradation if
their optimal CTI voltages do not quite match with each other. Thus, the optimal CMS
algorithm selectively merges those migration tasks when their optimal CTI voltages are
close enough. Those merged tasks sharing the same CTI start migrate simultaneously.
Our algorithm converges to a static scheduling that achieves near-optimal charge
migration efficiency.
7.3.1 Example
We consider an example of three SSSD migration tasks with the target energy of (1000J,
1000J, 750J) and a deadline constraint of 300 sec. There is only one CTI available. The
source and destination EES banks OCVs are (15V, 15V, 6V) and (12V, 12V, 6V),
respectively. A bank OCV and SoC have strong correlation, and we use SoC to estimate
OCV. Figure 7.3 compares three scheduling schemes: all the migrations tasks are merged
and performed simultaneously, one migration task at a time with the CTI usage time of
(80s, 80s, 140s) and our near-optimal scheduling. In this example, we merge Task1 and
Task2 because they have the same optimal CTI voltage. A longer CTI usage time is
assigned to Task 3 to avoid a large charging current since it has a low destination EES
bank OCV. The cumulative height of the three bars indicates the charge migration
efficiency. When the tasks are merged, the ratio of their areas indicates the energy
received by the destination EES banks.
121

7.3.2 Scheduling algorithm
In this section, we introduce the proposed scheduling algorithm that contains three sub-
algorithms: i) finding the near-optimal charging current profiles and CTI voltage for one
migration task; ii) determining the appropriate CTI usage time for each migration task
under the deadline constraint; and iii) merging the migration tasks so that the merged
tasks have longer CTI usage time while the overall CTI usage time of all migration tasks
is reduced. We will present each sub-algorithm individually and integrate them together
to form the proposed scheduling algorithm.
7.3.2.1 Solving the MSMD migration
A lookup table based solution effectively solves the SSSD migration problem [6].
However, the lookup table is EES bank specific, and thus it is not applicable to large-
scale HEES systems. We propose a new approach based on the non-linear fractional
programming to solve the near-optimal charging current profiles and CTI voltage for one
migration task, which is a MSMD migration.

Figure 7.3. Three scheduling schemes: all merged (A), one at a time (B) and near-optimal scheduling
(presented).
0 100 200 300
1,2,3
1 2 3
1,2 3
A
B
Ours
Time (sec)
0.5
0.6
0.7
0.8
0.9
Ours B A
Migration Efficiency
122

In a MSMD migrations problem, we are given a migration task 𝑇𝑇 𝑛𝑛 , which has a set of
source EES banks { 𝑆𝑆 𝑒𝑒 𝑐𝑐 }
𝑛𝑛 , and a set of destination EES banks and their corresponding
target energy � 𝐷𝐷 𝑠𝑠𝑡𝑡 , 𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
�
𝑛𝑛 . The CTI usage time 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 of this task is also given by the
scheduler. The objective function to be maximized is the overall charge migration
efficiency of all migrations, which is similar to (52) but the summation over all migration
tasks is removed:
𝜂𝜂 𝑀𝑀 𝑆𝑆 𝑀𝑀 𝐷𝐷 � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 � =
𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 𝑐𝑐 𝑐𝑐𝑐𝑐
𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 =
∫
∑ 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑚𝑚 𝑛𝑛 𝑐𝑐 = 1
𝑐𝑐 𝐶𝐶𝐶𝐶𝐶𝐶 , 𝑛𝑛 0
∫
∑ 𝑃𝑃 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝑚𝑚 𝑛𝑛 𝑐𝑐 = 1
𝑐𝑐 𝐶𝐶𝐶𝐶𝐶𝐶 , 𝑛𝑛 0
(55)
We apply the constraint (iii) and (iv) of the CMS problem to the MSMD problem. The
optimization variables are the equivalent current values of destination banks 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), 𝑖𝑖 ∈
{1,2, … , 𝑚𝑚 𝑛𝑛 }. Hence we rewrite constraint (i) as:

𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) ≥
𝐸𝐸 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐
− ∫ 𝑃𝑃 𝑎𝑎𝑐𝑐 𝑐𝑐 𝑛𝑛 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝜏𝜏 ) 𝑑𝑑𝜏𝜏 𝑐𝑐 0
𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 − 𝑡𝑡
(56)
The minimum current constraint (9) assures that the i-th destination EES bank receives
target amount of energy by the end of 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 . The charging currents of destination banks,
𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), can be derived from (47) and (50).
We break the whole migration process into many timeslots and solve the multiple
migrations optimization problem in an iterative manner for each timeslot. We also apply
heuristics, which are elaborated in Appendix. C, to simplify (55) into the form of:

𝜂𝜂 𝑀𝑀 𝑆𝑆 𝑀𝑀 𝐷𝐷 =
𝐹𝐹 ( 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 1
𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 2
𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), … , 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑚𝑚 𝑛𝑛 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ) )
𝐺𝐺 ( 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 1
𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 2
𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), … , 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑚𝑚 𝑛𝑛 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ), 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ) )

(57)
123

where 𝐺𝐺 is a positive quasi-convex function and F is a linear function with respect to
equivalent currents at the fixed CTI voltage level. Hence maximizing (57) is a fractional
programming problem that can be solved in polynomial time [91]. We perform a binary
search in the feasible range of 𝛼𝛼 (0 < 𝛼𝛼 < 1) to find the maximum value of α such that
𝜂𝜂 𝑀𝑀 𝑆𝑆 𝑀𝑀 𝐷𝐷 ≥ 𝛼𝛼 . The optimization variables 𝐼𝐼 𝑠𝑠 𝑒𝑒 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐
( 𝑡𝑡 ) are determined accordingly. We
determine the CTI voltage 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ( 𝑡𝑡 ) through a ternary search in the feasible range of CTI
voltage since 𝜂𝜂 𝑀𝑀 𝑆𝑆 𝑀𝑀 𝐷𝐷 is also a quasi-convex function of the CTI voltage. In this way, we
find the near-optimal migration efficiency for the n-th CTI usage time constrained
migration task, the corresponding charging current profiles and CTI voltage. We
summarize the inputs and outputs of this algorithm, MSMDSolver, in the form of:

� 𝜂𝜂 𝑀𝑀 𝑆𝑆 𝑀𝑀 𝐷𝐷 𝑆𝑆 𝑐𝑐 𝑐𝑐 � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 � , 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 � , { 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝑛𝑛 , 𝑐𝑐 𝑑𝑑 𝑠𝑠𝑐𝑐 , 𝑆𝑆 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 )}, 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) �
= 𝑀𝑀 𝑆𝑆 𝑀𝑀 𝐷𝐷 𝑆𝑆 𝑆𝑆 𝑡𝑡 𝑝𝑝 𝑒𝑒 𝑒𝑒 � 𝑇𝑇 𝑛𝑛 , 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 �
(58)
where 𝑖𝑖 ∈ {1,2, … , 𝑚𝑚 𝑛𝑛 }, 𝑡𝑡 ∈ � 0, 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 � , and 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ) is the total amount of
energy drawn from all source banks in task 𝑇𝑇 𝑛𝑛 applying the near-optimal operating
conditions. The details of this algorithm are described in [9].
7.3.2.2 Determining CTI usage time
In this section, we introduce our algorithm to determine the CTI usage time for each
migration task such that all migration tasks are completed without violating the deadline
constraint. Our algorithm is based on two propositions.
Proposition 1: There exists the global optimal CTI usage time 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
, such that for
each charge migration task 𝑛𝑛 , ∀ 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 > 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
, 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 � = 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
).
124

Proof: As we explain in Section III. B, there exists the optimal charging current for
each SSSD migration and in turn the corresponding optimal CTI usage time. We denote
the optimal CTI usage time of i-th SSSD migration in n-th task by 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 , 𝑐𝑐 ∗
. We define the
global optimal CTI usage time for a migration task as 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
= max { 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 , 𝑐𝑐 ∗
, 𝑖𝑖 ∈
{1,2, … , 𝑚𝑚 𝑛𝑛 }, which corresponds to the highest charge migration efficiency can be
achieved. The 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
is solved by global MSMDSolver algorithm, i.e., removing the
minimum current constraint (54). Therefore, increasing 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 beyond 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
is not helpful
in improving charge migration efficiency since it is equivalent of not having constraint
(54). The migration efficiency decreases progressively as 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 goes below 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
.
Although it is possible to achieve the highest migration efficiency by using 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
, we
typically have ∑ 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗ 𝑁𝑁 𝑛𝑛 = 1
> 𝑆𝑆 ⋅ 𝑇𝑇 𝐷𝐷 so that we cannot assign 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
to each task directly.
Here we call the set of CTI usage time that can achieve the optimal charge migration
efficiency under the deadline constraint (ii) as constrained optimal CTI usage time set,
denoted by { 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 1
𝑆𝑆 𝑐𝑐 𝑐𝑐 , 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 2
𝑆𝑆 𝑐𝑐 𝑐𝑐 , … , 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑁𝑁 𝑆𝑆 𝑐𝑐 𝑐𝑐 }.
Proposition 2: For a constrained optimal CTI usage time set { 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 1
𝑆𝑆 𝑐𝑐 𝑐𝑐 , 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 2
𝑆𝑆 𝑐𝑐 𝑐𝑐 , … , 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑁𝑁 𝑆𝑆 𝑐𝑐 𝑐𝑐 },
there must be 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 ≤ 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
, ∀ 𝑛𝑛 ∈ {1,2, … 𝑁𝑁 }.
Proof: If there exists such an optimal usage time 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 > 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
, we can always safely
reduce it to 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
without any sacrifice in charge migration efficiency according to
Proposition 1, and assign this slack time to other migration tasks to further improve the
charge migration efficiency. Thus the new time set becomes the constrained optimal CTI
usage time set.
125

The energy loss due to rate capacity effect dominates when 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 < 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
. Smaller
𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 causes larger charging/discharging current, which in turn increases
𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 � significantly. According to Proposition 2, we are only interested in the
left side of 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
, where 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 � < 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 − Δ 𝑡𝑡 � . We propose the UTR
algorithm in Algorithm 7.1 to determine CTI usage time.
The idea of UTR algorithm in Algorithm 7.1 is based on the local search. We use
𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 as the cost function and start from the global optimal solution set � 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
� , 𝑛𝑛 ∈
{1,2, … , 𝑁𝑁 }. If the global optimal solution set satisfy the deadline constraint (ii), we can
simply return to the optimal solution set. Otherwise, we iteratively search all neighbor
solution sets and move to the one that brings us the least amount of extra cost. The
algorithm is terminated when we move to a solution set that satisfies deadline constraint
(ii). Furthermore, the gradient of 𝐸𝐸 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 , 𝑛𝑛 𝑆𝑆 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ) versus 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 is always negative when

Algorithm 7.1. CTI usage time reduction (UTR).
126

𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 < 𝑡𝑡 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑛𝑛 ∗
, since the energy loss due to rate capacity effect dominates. Therefore, the
cost function does not have local minima in this region. The solution set where we
terminate our algorithm is the optimal solution set subject to the deadline constraint (ii).
The complexity of this algorithm depends the dimension of problem (i.e., number of
migration tasks) and the step length of each move Δ 𝑡𝑡 . Using smaller Δ 𝑡𝑡 in Algorithm 7.1
can achieve better at the expense of longer runtime. We consider a migration scheduling
problem with a typical deadline of hundreds of seconds, and we thereby use a time step
length of 10 ~30 s considering both the runtime and accuracy.
7.3.2.3 Merging tasks
Merging tasks allows us to assign a longer CTI usage time for each migration task, which
is helpful in saving energy loss from severe rate capacity effect and meeting the deadline
constraint. However, we should not merge two tasks if the energy loss due to the non-
optimal CTI voltage setting is greater than the energy saved. Therefore, we propose the
TM algorithm in Algorithm 7.2 based on the optimal CTI voltage difference between
tasks.
We do not have to merge any task if the total number of tasks is equal to or less than
the number of available CTI’s. In this case, we simply assign one CTI to each migration
task, and it will achieve the optimal migration efficiency since each task uses its optimal
CTI voltage, neglecting the overhead of using more CTI’s. Otherwise, in Algorithm 7.2,
we check the 𝐾𝐾 pairs of migration tasks that have the closest optimal CTI voltage settings
and merge the pair that brings us the largest improvement. The experimental results show
127

that generally merging the pair of tasks that have the closest optimal CTI voltage yields
highest improvement. Therefore, we set 𝐾𝐾 ≤ 5 in practice to avoid high complexity of
merging algorithm.
7.3.2.4 Scheduling algorithm
We propose scheduling algorithm to find the near-optimal scheduling of charge migration
tasks in an iterative manner. In each iteration, we start to reduce from the global optimal
CTI usage time, which can be calculated using MSMDSolver by replacing CTI usage
time by ∞. The deadline constraint is guaranteed to be met by using Algorithm 7.1. Then
we use the constrained optimal CTI usage time set as the baseline and check whether we
can improve the charge migration efficiency through tasks merging. If merging is
performed, the number of migration tasks decrease by one and we start next iteration. We

Algorithm 7.2. Tasks merging (TM).
128

converge to the near-optimal scheduling when deadline constraint is met and no further
merging can improve the charge migration efficiency. The integrated CMScheduling
algorithm is shown in Algorithm 7.3.
The CMScheduling algorithm returns the constrained optimal CTI usage time set that
satisfies deadline constraint (ii). We still need an arrangement with definite starting time,
ending time and CTI number for each migration task. In practice, the energy overhead
due to the CTI voltage regulation is negligible compared to energy loss during migration.
Therefore, the different arrangements of the migration tasks on the CTI’s do not affect
the overall charge migration efficiency. We arrange the migration tasks with longer CTI

Algorithm 7.3. Charge migration tasks scheduling (CMScheduling).
129

usage time first, and then move to those with shorter CTI usage time and break them if
necessary.
7.4 Experimental Results
We compare the proposed CMS algorithm in two example HEES systems, with various
baseline setups. The baseline setups basically follow two different scheduling schemes: A)
merging based, i.e., merge all the initial migration tasks into 𝑆𝑆 number of tasks and assign
one task to each CTI, where the CTI usage time for each task is the global deadline 𝑇𝑇 𝐷𝐷 ;
and B) clustering based, i.e., cluster all initial migration tasks into 𝑆𝑆 number of groups,
assign each group to one CTI and perform the migration tasks in a group one at a time
while the CTI usage time is determined based on the ratio of target amount of energy
transfers of all migration tasks in that group. During the migration process, the OCVs of
the battery banks change only slightly while the OCVs of the supercapacitor banks vary
by a large amount due to their small energy capacity and strong SoC-OCV dependency.
Hence it is difficult for the baseline schemes to predict the OCV in following time
instances. The baselines setups use constant CTI voltage during the entire migration
process. For each baseline scheduling scheme, we try different merging methods: A.1
(merge tasks that have similar initial OCVs), A.2 (merge tasks so that the total target
energy for each merged task is nearly the same) and A.3 (randomly pick the initial tasks
and merge them, we did 100 runs and report the average efficiency) and clustering
methods: B.1 (cluster tasks that have similar initial OCVs), B.2 (cluster tasks so that the
130

total target energy of each group is nearly the same) and B.3 (randomly pick the initial
tasks and cluster them, we did 100 runs and report the average efficiency.)
Figure 7.4 compares the charge migration efficiencies of the proposed scheduling
algorithm and various baselines. According to the results in Figure 7.4, performance in
charge migration efficiency of these two baseline scheduling schemes depend on the
problem setup e.g., the number of migration tasks, amount of target energy to be
delivered, and the deadline constraint. In addition, the performance fluctuates by about 5%

Figure 7.4. Charge migration efficiencies comparison in 20-bank HEES system (a) and 40-bank
HEES system (b).

Figure 7.5. Presented task scheduling solutions for a 20-bank HEES system (a) a 40-bank HEES
system (b).
0.4
0.5
0.6
0.7
0.8
0.9
Migration Efficiency
Ours A.1 A.2 A.3 B.1 B.2 B.3
0.4
0.5
0.6
0.7
0.8
0.9
Migration Efficiency
Ours A.1 A.2 A.3 B.1 B.2 B.3
11 13 15 17
1
2
3
4
1 11~14
2,3 7,8 18,19
4~6 20
9,10 15~17
1
9,10
Time in a day
CTI Number
11 13 15 17
1
2
1,2 3~5 10
10 6~9
Time in a day
CTI Number
131

when trying different merging and grouping combinations. As shown in Figure 7.4, the
proposed algorithm for solving the CMS problem consistently outperforms the baseline
systems with charge migration efficiency improvement ranging from 11.4% to 32.2%.
Figure 7.5 shows the scheduling of the migration tasks in these two HEES systems.
The numbers inside the block denotes the initial migration task IDs. Multiple initial
migration tasks have been merged when multiple numbers appear in one block, as shown
in Figure 7.5. To maximize the overall efficiency and finish all migration tasks by the
deadline, we sometimes break one migration task into some smaller subtasks, depicted in
gray color in Figure 7.5, so that we can perform them separately and meet the global
deadline.

132

CHAPTER 8
STATE-OF-HEALTH-AWARE CHARGE
MANAGEMENT
The cycle life of the EES elements is one of the most important metrics that should be
considered by the designers of the EES system. It is usually described by state of health
(SoH), which is defined as the ratio of full charge capacity (FCC) of a cycle-aged EES
element to its designed capacity (DC). It reflects the general condition of the EES
elements and their ability to store and deliver energy compared to its initial state (i.e.,
compared to a fresh new EES element). Some researchers have worked on extending the
lifetime of EES elements [48, 49, 50, 51]. However, they only focus on either a single
EES element or a homogeneous EES system, which consists of a single type EES
element array.
Unlike a single element or a homogeneous EES system, the cycle life of the EES
elements in a HEES system is largely dependent on the HEES charge management
policy. This chapter introduces the cycle life of EES elements in a HEES system and
develops systematic charge allocation, replacement and migration policies that prolong
the cycle life of EES elements. We deal with extending cycle life of the HEES system as
well as improving cycle efficiency. In this chapter, we first introduce a generalized
architecture of the HEES system and build the corresponding electrical circuit models for
power converters, battery elements and supercapacitor elements. We adopt the cycle life
model in [16] and determine the SoH degradation rate with respect to different average
133

state of charges (SoCs, defined as available capacity remaining in the battery, expressed
as a percentage of the rated capacity) and SoC swings (defined as SoC change during a
charging or discharging cycle). We consider the cycle efficiency, taking into account the
power dissipation on internal resistance of EES elements, power loss due to power
converters and rate capacity effect of the batteries elements.
We simplified the target HEES system with a two-bank architecture in this chapter to
focus on the idea of SoH-aware charge management, that is, using supercapacitor banks
as buffer to shave the spiky portion of the source or load profiles so that battery banks
can steadily receive energy from the power sources or provide energy to the load devices.
During the charging/discharging process, we achieve high cycle efficiency by
determining the optimal CTI voltage and subsequently the charging or discharging
currents for battery and supercapacitor banks through a ternary search. Besides improving
the cycle efficiency, we also reduce the SoC swing and average SoC of battery arrays,
which leads to SoH enhancement. We implement our algorithm on a HEES system and
compare with a typical homogeneous EES system. The experimental results demonstrate
significant improvement up to 21.9% and 4.82x in terms of cycle efficiency and cycle
life, respectively.
8.1 SoH-aware Charge Management Problem
State of health-aware charge management problem is kind of joint charge management
problem that including all three types of basic HEES operations. SoH-aware charge
management problem in HEES systems is to find charging/discharging current profiles
134

for all EES banks and CTI voltage, for a given HEES system, aiming to improve both the
cycle life of the EES arrays (mainly battery arrays) and overall cycle efficiency of the
entire system. In HEES systems, battery arrays have higher energy capacity but relatively
lower cycle life and cycle efficiency. Thus we determine the appropriate charging and
discharging rate at which we charge or discharge the battery arrays continuously and
steadily, considering the battery properties and load/source characteristics. We use the
supercapacitor arrays as buffer of battery arrays because it has strengths of high power
capacity, superior cycle efficiency and long cycle life but weakness of low energy
capacity. We maintain the desired charging current of the battery banks in charging
process, allowing the supercapacitor banks to accept the extra power from CTI or supply
power to battery banks. Similar strategy is also taken during the discharging process, we
let the supercapacitor banks compensate power shortage caused by high load demand and
get charged from battery banks to maintain their SoC when the load demand is low.

Figure 8.1. Conceptual diagram of charge management problem.
135

Figure 8.1 shows a simplified SoH-aware charge management problem in the HEES
system. The charge management problem in HEES system is constrained by energy
conservations. For the charging process, the input power follows:
,
,
() () () () ( () ) ,
src src src c s
CTI CTI S
Pt V t t P t tI t IV   
(59)
where the current through CTI, 𝐼𝐼 𝐶𝐶 𝑇𝑇 𝐶𝐶 , 𝑆𝑆 ( 𝑡𝑡 ), consists of two parts:
, ,,
() () ().
CTI S bank C bank B
tt I I It 
(60)
In (60), 𝐼𝐼 𝑏𝑏 𝑐𝑐𝑛𝑛𝑘𝑘 , 𝐶𝐶 ( 𝑡𝑡 ) can be positive (from CTI to supercapacitor banks) or negative (from
supercapacitor banks to CTI), depending on whether supercapacitor banks is used to store
excessive energy from source or provide energy to battery banks. For battery banks and
supercapacitor banks, we also have:

, ,, ,
, ,, ,
() () () (),
() () () ().
CC
CTI c C array C array C bank C
CC
c B array B array B CTI bank B
V I t P t V tI t
V I t P t V tI t
 
  


(61)
Besides, the relations of OCV and CCV and rate capacity effect are given in (4). Similar
relations also hold for discharging process. The overall cycle efficiency of HEES system
has two components (charging efficiency and discharging efficiency), given by:

, ,
,,
() ()] () ,
() () ()]
[
[,
cc
dd
c gain B gain C
d drawn
src
loa C drawn d B
PP t t dt t dt
td
P
tt P t PP dt










(62)
and the cycle efficiency is the product of these two, i.e., 𝜂𝜂 = 𝜂𝜂 𝑐𝑐 𝜂𝜂 𝑑𝑑 .
8.2 Charge Management Problem Formulation
The SoH-aware charge management problem is formulated as follows:
Given: a HEES system, and statistical knowledge about the power sources and load
devices.
136

Find: operation current profiles 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐶𝐶 ( 𝑡𝑡 ) for supercapacitor banks and 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 ( 𝑡𝑡 )
for battery banks
Minimize: SoH degradation given by (8) for battery after a large number of cycles
Subject to:
1) Energy conservation in HEES system: (59)~(62);
2) Charge conversation in EES banks (4)
3) Discharging power of the HEES system meets the load demand.
Note that the supercapacitor array typically has very long cycle life so its SoH
degradation is not considered in our work.
8.3 SoH-aware Charge Management Algorithm
8.3.1 Optimal operating condition search
At time 𝑡𝑡 , the source voltage and current, 𝑉𝑉 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) and 𝐼𝐼 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ), and SoC of the EES array,
which is used to determine 𝑉𝑉 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 𝑂𝑂 𝐶𝐶 ( 𝑡𝑡 ) using (2), are given for a charging process. We omit
the time 𝑡𝑡 in following text for convenience. In Figure 8.2, given 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , we can calculate
CTI current 𝐼𝐼 𝐶𝐶 𝑇𝑇 𝐶𝐶 from (59), and further determine array charging current 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 and
equivalent current inside EES array 𝐼𝐼 𝑠𝑠 𝑒𝑒 from (4)(61). The instantaneous charging
efficiency is a function of 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , given by:

Figure 8.2. Schematic of optimal operation condition search
137

() ()
src gain CTI C I ic T
V PV P  
(63)
Assuming 𝜂𝜂 𝑐𝑐 𝑐𝑐 ( 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 ) in (63) is a quasi-concave function of 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 , we perform a ternary
search within the feasible region of CTI voltage to find 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 𝑆𝑆 𝑐𝑐 𝑐𝑐 and subsequently 𝐼𝐼 𝐶𝐶 𝑇𝑇 𝐶𝐶 𝑆𝑆 𝑐𝑐 𝑐𝑐 and
𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 𝑆𝑆 𝑐𝑐 𝑐𝑐 , such that 𝜂𝜂 𝑐𝑐 𝑐𝑐 ( 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 𝑆𝑆 𝑐𝑐 𝑐𝑐 ) achieves its maximum value [6]. The search algorithm
converges in a logarithmic time with respect to 𝑉𝑉 𝐶𝐶 𝑇𝑇 𝐶𝐶 precision. The simulation results
validate the quasi-concavity assumption. By the similar way, one can easily solve the
discharging process.
This proposed online optimal operation condition search (OOCS) algorithm guides us
in determining the charging (discharging) current and CTI voltage according to the
source (load) characteristics and SoC of the EES arrays. Since the cycle efficiency of
battery bank can vary from 50% to 70% (depending on the charging or discharging
current), operating the battery bank near the optimal operation condition can significantly
improve the cycle efficiency, which in turn benefits the cycle life.
The proposed OOCS algorithm can be applied to the HEES system with multiple EES
banks. We can still finish this search in polynomial time and converge to a near-optimal
operation condition with some proper charge allocation and replacement algorithms.
Without loss of generality, we perform OOCS algorithm to one battery bank and one
supercapacitor bank HEES system in our work.
8.3.2 Near-optimal charge management algorithm
Here we elaborate our near-optimal charge management algorithm to determine the near-
optimal operation condition for the HEES system, with the purpose of extending battery
138

array cycle life as well as improving the overall cycle efficiency. The operation condition
consists of the CTI voltage and battery array charging or discharging current.
8.3.2.1 Target optimal operating condition
We can find a target optimal operation condition for the battery banks in our HEES
system, based on the low frequency components of the source power profile obtained
through the crossover filter. We assume the EES array in Figure 8.2 be the battery array
and apply the OOCS algorithm:

, ,
ˆ ˆ
(), ()] (), (), ()
ˆ
[ )
ˆ
(
tar tar OC
sr array B c src array B CTI
t I t OOCS t I t V V t V 
(64)
The target optimal operation condition is the desired operation condition for battery
banks, maximizing the cycle efficiency but ignoring incoming and outgoing power
fluctuations. The HEES system can operate battery banks at near-optimal operation
condition for most of the time with the help of the supercapacitor bank.
8.3.2.2 Instantaneous optimal operation condition
At time 𝑡𝑡 , we perform the OOCS algorithm to the instantaneous source power as well and
get the optimal operation condition as:

, ,
(), ()] (), (), () [ ) (
ins ins OC
sr arr c src array B CTI ay B
t I t OOCS t I t V V t V 
(65)
The instantaneous optimal operation condition is to maximize the instantaneous
charging efficiency when the power source charges battery bank only. It is affected by
the source power fluctuations and does not reflect the overall optimal operation condition
for the entire HEES system since the supercapacitor bank is not involved when we
applying the OOCS algorithm.
139

8.3.2.3 Near-optimal charge management algorithm
The key idea of the algorithm is to use supercapacitor bank as the buffer of the battery
bank, as we mentioned before. When charging the battery bank, we allocate part of the
incoming power to the supercapacitor bank as well if the incoming power is very high, in
order to mitigate the loss caused by rate capacity effect. However, the supercapacitor
bank typically has limited energy capacity. It may result in undesirable situation since the
supercapacitor bank may be fully charged very quickly and fail to get charged from the
power source any more. We overcome this problem by performing charge migration from
the supercapacitor bank to the battery bank when the instantaneous charging current is
lower than the target charging current and the SoC of the supercapacitor array is high
enough. Similarly, we avoid fully discharging the supercapacitor bank by charging it at
the beginning of the charging process.
Based on this key idea, we propose the following near-optimal operation algorithm.
We first charge the supercapacitor bank until the supercapacitor array has a certain level
of SoC, which is HEES system and source (load) specific and can be determined by their
statistical information. We determine the two sets of the optimal operation conditions for
battery bank at time 𝑡𝑡 : the target and instantaneous operation conditions. We compare
𝐼𝐼 ̂
𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) − 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑛𝑛𝑠𝑠
( 𝑡𝑡 ) with a positive threshold value 𝜀𝜀 , and perform appropriate
actions such that:
1) 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑛𝑛𝑠𝑠
( 𝑡𝑡 ) − 𝐼𝐼 ̂
𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) > 𝜀𝜀 , i.e., the instantaneous optimal battery array charging
current is higher than the target optimal battery array charging current. It is usually
caused by high incoming power. In this case, we charge the battery with the target
140

array charging current 𝐼𝐼 ̂
𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) and store the excessive power from power source
to supercapacitor bank.
2) 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑛𝑛𝑠𝑠
( 𝑡𝑡 ) − 𝐼𝐼 ̂
𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) < − 𝜀𝜀 , i.e., the instantaneous optimal battery array charging
current is lower than the target optimal battery array charging current, which is
typically due to the low incoming power. In this case, both of power source and
supercapacitor bank are charging the battery bank, maintaining the value of battery
array charging current to be 𝐼𝐼 ̂
𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ).
3) | 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑛𝑛𝑠𝑠
( 𝑡𝑡 ) − 𝐼𝐼 ̂
𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑐𝑐𝑐𝑐
( 𝑡𝑡 )| < 𝜀𝜀 , the two optimal battery array charging current match
within the threshold value. We can simply charge battery bank with instantaneous
optimal array charging current 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑎𝑎 , 𝐵𝐵 𝑐𝑐 𝑛𝑛𝑠𝑠
( 𝑡𝑡 ).

Algorithm 8.1. Near-optimal SoH-aware charge management algorithm.
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The above policy is summarized as an algorithm in Algorithm 8.1. The proposed
algorithm for HEES system has two distinct advantages. First, we have a supercapacitor
bank in the HEES systems that can store the excessive energy from power source or
provide extra energy to the load devices. Thus the SoC swing and average SoC level of
the battery array can be reduced naturally. Second, a HEES system is superior to a
homogeneous EES system when supporting the same load devices and the same
minimum SoC requirement for future load demand. The HEES system with the proposed
algorithm can achieve higher overall cycle efficiency than that of the homogeneous EES
system because of the near-optimal choice of CTI voltage, charging/discharging current
and high cycle efficiency of the supercapacitor bank. In other words, the HEES system
needs less input energy to support the same load demand and thereby further reduce the
SoC swing and average SoC level of the battery array.
Recall the observations we made from Figure 3.4, the cycle life of the battery array
can be extended if we reduce the SoC swing and the of the battery array. There is super-
linear relation between the cycle life improvement with respect to reduction of SoC
swing and the average SoC level. Thus the proposed algorithm can further boost up the
cycle life of the battery array.
Discharging process is similar to the charging process, but the charge is moving from
the EES banks to load devices. We also set a target optimal battery array discharging
current and try to maintain it as much as we can during the whole discharging process.
We discharge the supercapacitor bank to compensate the power shortage if the load
devices require larger current than the target battery discharging current. However, we
142

need to maintain the SoC of the supercapacitor array since it has small energy capacity
and may be fully discharged very quickly. We charge the supercapacitor array using the
excessive current when the target battery discharging current is greater than the current
required by the load devices to maintain the SoC of the supercapacitor array.
The capacity of the supercapacitor array affects the improvement of the battery array
cycle life and the HEES system cycle efficiency. A larger supercapacitor array can
enhance both of the two metrics with expense of high capital cost. Thus, we should
determine the optimal capacity of supercapacitor array based on the statistical
information of the source/load profiles.
8.4 Experimental Results
We implement our near-optimal SoH-aware charge management algorithm on a typical
HEES system consisting of a 1 Ah Li-ion battery, of which the OCV varies from 2.9 V to
4.2 V, depending on the SoC level, and a 100 F supercapacitor. We compare the cycle
life and overall cycle efficiency of our HEES system with the baseline system, which is a
battery-only EES system using the same battery. We test our proposed algorithm with
two sets of source and load profiles. In the first set, we use a pulse source profile (duty
ratio of 30%, average power of 2.7 W) and a pulse load profile (duty ratio of 25%,
average power of 2 W). We use a sinusoidal wave source profile (average power of 4.5
W) and a sinusoidal wave load (average power of 4 W) profile in the second set. A cycle
starts from a charging process, in which the two systems are charged by the source, and
then has a discharging process to supply power to the load. Hence the battery SoC,
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starting from the initial value, will first ramp up and then down to this value. We test
various different durations of the discharging process (i.e., different load energy
demands) for each set of experiments so that we can achieve different battery SoC swings
and average SoC levels. We guarantee fairness by letting the HEES system have the same
minimum SoC requirement for battery and the same duration of discharging process per
cycle as those of the baseline system. However, the corresponding charging process for
HEES system may be shorter than that of the baseline system due to higher cycle
efficiency of HEES system.
Figure 8.3 shows that our proposed algorithm can effectively reduce the SoC swing
(a) and average SoC level (b) in HEES system with the pulse source and load profile. We
repeat simulation for tens of thousands of cycles until the battery SoH degradation, given
by (8), reaches 0.2, which is a measure of the end of life of the battery. The results of the
normalized cycle life gain and overall cycle efficiency are shown in Figure 8.4.

Figure 8.3. SoC swing and average SoC of battery-only EES system and HEES system vs. duration of
pulse load profile per cycle.
144

We demonstrate significantly normalized cycle life enhancement and overall cycle
efficiency improvement in Figure 8.4. For the pulse source and load profile, the cycle life
of HEES system is extended by a factor from 2.29x to 4.82x and the overall cycle
efficiency is improved from 11.9% to 21.9%, compared to the battery-only system. The
cycle life enhancement factor varies from 1.76x to 3.66x, and cycle efficiency
improvement varies from 5.0% to 12.9%.

Figure 8.4. Normalized cycle life gain (bars) and cycle efficiency improvement (curves) of a HEES
system with different source and loads profile (upper - pulse, lower - sinusoidal wave).
1
2
3
4
5
Cycle life gain

EES HEES
1000 2000 3000 4000
0.4
0.6
0.8
Cycle efficiency

1
2
3
4
T
Load
per cycle (sec)
Cycle life gain

EES HEES
500 1000 1500 2000
0.4
0.6
0.8
Cycle efficiency

145

CHAPTER 9
JOINT THERMAL AND CHARGE MANAGEMENT
We formulate the dynamic thermal management problem for batteries (DTMB) in
portable systems with forced convection cooling. We introduced how to derive the
dynamic thermal management policy that maximizes the cumulative workload
completion (CWC) defined as the cumulative amount of energy that the battery delivers
to the load devices over the designed system lifetime of portable systems. The
contributions in this work are threefold. First, we introduce a hybrid power source to
replace the previous battery-only power source. The hybrid power source consists of a
battery array and a supercapacitor arrays. Each of arrays again consists of multiple
identical cells. Second, we present a new dimension of the optimization problem, namely,
how to leverage the supercapacitor to alleviate the battery aging, and combine it with the
previous thermal management policy. Finally, new simulation results demonstrate the
effectiveness of the hybrid power source over the battery-only power source.
The DTMB policy determines two things. First, we manage the charging and
discharging power among the battery array and the supercapacitor array properly so that
the supercapacitor array effectively shaves peaks of load power demand. This makes it
possible to achieve less energy waste in the battery because the rate capacity energy loss
is super-linearly proportional to the battery discharging current [86]. Another benefit is
that less amount of heat is generated in the battery array because the Ohmic heat is also
proportional to the square the discharging current. Second, we dynamically control the
146

fan speed to tradeoff the cooling energy investment and the lifespan extension. The
optimal fan speed control is crucial because the fan is also powered by the same hybrid
power sources. We may achieve zero or very little performance loss but also end up with
significant battery SoH degrades if we turn off the fan or use a very low fan speed due to
excessive battery temperature rise. On the other hand, a higher fan speed can effectively
remove the heat from the battery surface by reducing the thermal resistance, and, in turn,
mitigate the SoH degradation at the expense of higher energy consumption and
performance degradation. A globally optimal thermal management strategy should be
determined based on the designed lifetime of portable systems.
To address the above-mentioned challenges, we develop a hierarchical algorithm to
derive the DTMB policy combining reinforcement learning (RL) method at the lower
level and dynamic programming (DP) method at the upper level. We first obtain the
tradeoff curve between the normalized fan usage and SoH degradation using the RL
method, considering the battery temperature, supercapacitor SoC, and load demand
intensity. We apply the DP method to determine the global tradeoff strategy for each
cycle so that the cumulative workload completion is maximized the system lifetime.
Simulation results show that presented system and algorithm achieve up to 2.02X and
78.7% improvements in terms of battery lifespan and cumulative workload completion,
respectively.
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9.1 The Joint Thermal and Charge Management Problem
In this section, we introduce the DTMB problem setup by showing a conceptual diagram
of the system and explaining how the system works and formulate it as an optimization
problem.
9.1.1 DTMB Problem Setup
Figure 9.1 shows a block diagram of the proposed DTMB problem setup. The entire
system contains a service provider, a hybrid power source consisting of a battery array
and a supercapacitor array, a cooling fan that is also powered by the same power source,
and three converters. Converters control the charging and discharging currents of the
battery array and the supercapacitor array, and maintain voltage compatibility between
the hybrid power source and the service provider. Converters in Figure 9.1 have two
operation modes: voltage regulation mode and current regulation mode, in which it sets
output voltage and current to a desired level, respectively. Once the output voltage

Figure 9.1. Block diagram of an portable system using dynamic battery thermal management.
148

(current) has been set, the output current (voltage) is determined automatically based on
the input power and converter efficiency. The cooling fan has multiple levels of fan speed
with different power consumption values. A controller determines the state of switches,
desired charging and discharging currents of the battery array and the supercapacitor
array, as well as the fan speed, according to the thermal management policy.
The hybrid power source has four working modes, depending on the relative
magnitude between the output power of the battery array and the total load demand
(including both the cooling fan and the service provider). These four working modes are
realized by changing the switch state ( 𝑆𝑆 1
, 𝑆𝑆 2
, 𝑆𝑆 3
).
• Working Mode 𝑀𝑀 0
� ( 𝑆𝑆 1
, 𝑆𝑆 2
, 𝑆𝑆 3
) = (0,0,0) � : all switches are left opened and the
system is turned off.
• Working Mode 𝑀𝑀 1
� ( 𝑆𝑆 1
, 𝑆𝑆 2
, 𝑆𝑆 3
) = (1,0,0) � : the desired battery output power is very
close to the total load demand. In this working mode, 𝑆𝑆 1
directly connects the battery
array to the service provider and the cooling fan, and thus only the battery array
discharges to support the system. Converter1 is working as a voltage regulator in this
working mode.
• Working mode 𝑀𝑀 2
� ( 𝑆𝑆 1
, 𝑆𝑆 2
, 𝑆𝑆 3
) = (1,1,0) � : the desired battery output power is greater
than the total load demand. In this mode, the battery array is used to support the
service provider, the cooling fan, and, in addition, to charge the supercapacitor array.
We normally operate the system in this working mode when the service provider
demands a small amount of power. Charging the supercapacitor allows us to use the
149

supercapacitor to shave peaks of power demand in the future. Converter1 works as a
voltage regulator to maintain the voltage compatibility, while Converter2 works as a
current regulator to set the charging current for the supercapacitor array.
• Working mode 𝑀𝑀 3
� ( 𝑆𝑆 1
, 𝑆𝑆 2
, 𝑆𝑆 3
) = (1,0,1) � : the desired battery output power is
smaller than the total load demand. In this mode, we discharge both the battery and
the supercapacitor array to supply the service provider and the cooling fan, when the
service provider demands a large amount of power (i.e., power demand is greater than
desired battery output power). We use Converter2 to regulate the voltage and
Converter1 to set the discharging current of the battery array (the discharging current
of supercapacitor array is set automatically through the feedback control of
converters). The reason that we use Converter2 as the voltage regulator is that it is
preferred to maintain a stable output current of the battery array.
Note that the converter efficiency normal depends on the input and output voltage and
currents. We approximately consider constant converter efficiencies due to a relatively
small range of the voltage (tens of volts) and current (a few Amps) settings.
9.1.2 DTMB Optimization Problem Formulation
There are mainly two factors that affect the thermal behaviors of the battery array. First,
the battery temperature directly relates to the SoH degradation. A high fan speed should
be used if the battery is at high temperature. Second, load demand determines the
discharging current of the battery, which in turn affects the ohmic heat generation of the
battery array. We set a hard constraint for the thermal management policy in this work,
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that is, the sum of the fan power and load demand cannot exceed the maximum power
capability of the battery array. The policy makes the fan slow down or turn off if this is
the case. We should avoid using high fan speed in the condition of high load demand
because the heat generation in (9) is proportional to the square of the discharging current.
Therefore, we receive both power and thermal benefits from peak shaving in power
demand profile.
The expected system lifetime plays an important role in deriving the global tradeoff
strategy between the investment of cooling energy and extension of battery lifespan. For
relatively short lifetime, the system policy may discharge batteries aggressively, i.e.,
without investing too much energy in cooling. This significantly degrades the lifespan of
batteries but results in a higher short-term performance. In contrast, we would better
invest more energy in cooling for a relatively long designed lifetime, i.e., a higher fan
speed, because it mitigates the SoH degradation of batteries and extends its lifespan.
We define the workload completion as the energy requested by the service provider at
downstream of converters. We use cumulative workload completion over the designed
system lifetime 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 as the metric function, which captures both the short-term
performance and long term lifespan. The system lifetime, 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 , could vary from
hundreds to thousands of cycles, depending on the design specifications. The internal
resistance increases and charge capacity decreases as SoH degrades. We assume the
batteries reach their end of lives once the SoH degradation increases above the EOL
threshold value, Δ 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 . A well accepted value of Δ 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 is 20%. Thus, we denote the
CWC by 𝑊𝑊 ( 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 , Δ 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 ) and formulate the DTMB problem as follows.
151

Given:
1. battery array specifications: 𝑉𝑉 𝑂𝑂 𝐶𝐶 - 𝑆𝑆𝑆𝑆 𝐶𝐶 relation, 𝑅𝑅 𝑐𝑐 𝑛𝑛𝑐𝑐
- ( 𝑆𝑆𝑆𝑆 𝐶𝐶 ) relation, nominal
capacity 𝐶𝐶 𝑏𝑏 , geometric dimensions, heat transfer coefficient ℎ;
2. supercapacitor array specifications: capacitance 𝐶𝐶 𝑐𝑐𝑐𝑐𝑐𝑐
, internal resistance 𝑅𝑅 𝑐𝑐𝑐𝑐𝑐𝑐
,
self-discharge constant 𝜏𝜏 ;
3. fan specification: speed levels { 𝐹𝐹 } = [𝐹𝐹 0
, 𝐹𝐹 1
, … ], where 𝐹𝐹 0
is the off-state of the
fan, power consumption of different levels [𝑃𝑃 𝐹𝐹 0
, 𝑃𝑃 𝐹𝐹 1
, … ], geometric dimensions;
4. converter efficiency 𝜂𝜂 1
, 𝜂𝜂 2
, 𝜂𝜂 3
.
Find:
1. fan speed over the time, 𝐹𝐹 ( 𝑡𝑡 ) ∈ [𝐹𝐹 0
, 𝐹𝐹 1
, … ], 𝑡𝑡 ∈ [0, 𝜏𝜏 𝑛𝑛 ], 𝑛𝑛 ∈ [1, … , 𝑁𝑁 ], 𝜏𝜏 𝑛𝑛 is the
stopping time for 𝑛𝑛 -th discharge process;
2. operating point of the hybrid power source over the time, 𝑃𝑃 𝑏𝑏 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) and
corresponding 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) , 𝑡𝑡 ∈ [0, 𝜏𝜏 𝑛𝑛 ], where 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) and 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) are discharging
power seen at the output of the battery and supercapacitor array, respectively.
Maximize CWC:
𝑊𝑊 ( 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 , Δ 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 ) = � � 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
( 𝑡𝑡 ) 𝑑𝑑𝑡𝑡 𝜏𝜏 𝑛𝑛 𝑐𝑐 = 0
𝑁𝑁 𝑛𝑛 = 1
(66)
Subject to:
1. If the hybrid power source is at working mode:
𝑀𝑀 1
:
𝑀𝑀 2
:
𝜂𝜂 1
𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) ≥ 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
( 𝑡𝑡 ) + 𝑃𝑃 𝐹𝐹 ( 𝑐𝑐 )

𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) ≥ ( 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
( 𝑡𝑡 ) + 𝑃𝑃 𝐹𝐹 ( 𝑐𝑐 )
)/𝜂𝜂 1
+ 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 )/ 𝜂𝜂 2

(67)
152

𝑀𝑀 3
: 𝜂𝜂 1
𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) + 𝜂𝜂 3
𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) ≥ 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
( 𝑡𝑡 ) + 𝑃𝑃 𝐹𝐹 ( 𝑐𝑐 )

where 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 < 0 (supercapacitor array is being charging) in 𝑀𝑀 2
.
2. ∑ Δ 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑓𝑓 𝑐𝑐 ( 𝑛𝑛 , 𝑇𝑇 )
𝑁𝑁 𝑛𝑛 = 1
≤ Δ 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 , the subscription 𝑓𝑓𝑐𝑐 stands for full cycle SoH
degradation;
3. 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
( 𝑡𝑡 ) + 𝑃𝑃 𝐹𝐹 ( 𝑡𝑡 ) ≤ 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 𝑚𝑚 𝑐𝑐𝑒𝑒
, 𝑡𝑡 ∈ [0, 𝜏𝜏 𝑛𝑛 ], 𝑛𝑛 ∈ [1, … , 𝑁𝑁 ], where 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 𝑚𝑚 𝑐𝑐𝑒𝑒
is the
battery power capability.
9.2 Optimization Method
We formulate the DTMB problem for portable systems as an optimization problem.
However, this problem is generally non-convex and thereby cannot be optimally solved
by analytic methods. Thus, we propose an RL-based optimization algorithm to derive the
DTMB policy hierarchically. We focus on minimizing the SoH degradation with given
amount of cooling energy investment at the lower level. We apply Q-learning to derive
tradeoff curves between the cooling energy investment and SoH degradation. The state-
action pairs at different tradeoff options are recorded in look-up tables (LUTs). At the
upper level, we implement the Dynamic Programming (DP) method to derive the optimal
tradeoff strategy by properly selecting the tradeoff options for each single cycle, aiming
to maximize 𝑊𝑊 ( 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 , Δ 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 ).
9.2.3 Reinforcement Learning Method
Reinforcement learning is a machine learning technique that is concerned with how an
agent ought to take actions in an environment so as to maximize some notion of
cumulative reward. RL is widely used when the problem is essentially to exploit the
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interaction between a goal-oriented agent and an uncertain environment [106]. The
learner and decision-maker are called the agent. The thing it interacts with, comprising
everything outside the agent, is called the environment. These interact continually, the
agent selecting actions and the environment responding to those actions and presenting
new situations to the agent. The environment also gives rise to rewards, special numerical
values that the agent tries to maximize over time. Compared to reactive control policy
used in [107], RL method is more powerful because the agent is able to keep improving
his performance by observing the reward and updating his knowledge base.
The basic RL model consists of the following components: i) a finite set of
environment states; ii) a set of available actions; iii) a state transition mechanism; and iv)
a reward or penalty function. The environment is typically formulated as a Markov
decision process (MDP) and thus modeled as a finite state machine 𝑆𝑆 . At each state, there
are multiple available actions we can take, denoted by 𝐴𝐴 . The agent and environment
interact at each decision epoch. For example, at decision epoch 𝑡𝑡 𝑐𝑐 , the system is in state
𝑠𝑠 𝑐𝑐 ∈ 𝑆𝑆 . The agent selects an action 𝑡𝑡 𝑐𝑐 ∈ 𝐴𝐴 ( 𝑠𝑠 𝑐𝑐 ) according to a certain action selection
policy. One epoch later, in part as a consequence of its action, the agent receives a
numerical reward 𝑅𝑅 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ), and finds itself in a new state 𝑠𝑠 𝑐𝑐 + 1
. The action select policy,
denoted by 𝜋𝜋 ( 𝑠𝑠 , 𝑡𝑡 ), gives a mapping from states to probabilities of selecting each
possible action. Reinforcement learning methods specify how the agent changes its policy
as a result of its experience. The agent's goal, roughly speaking, is to maximize the total
amount of reward it receives over the long run. Note that we use a penalty function in this
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work, instead of a reward function, to minimize a weighted sum of normalized SoH
degradation and energy drawn from the battery array.
The key part of the RL method is to find an optimal policy that minimizes the
cumulative penalty over a potentially infinite time span. Q-learning is a widely used RL
method that associates a Q value to each state-action pair ( 𝑠𝑠 , 𝑡𝑡 ). The state-action pair
𝑄𝑄 ( 𝑠𝑠 , 𝑡𝑡 )provides an expected cumulative penalty of taking action 𝑡𝑡 at state 𝑠𝑠 . More
precisely, at state 𝑠𝑠 𝑐𝑐 , we take the action 𝑡𝑡 𝑐𝑐 that has the minimal value of 𝑄𝑄 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ). After a
penalty 𝑅𝑅 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ) is received, we move to state 𝑠𝑠 𝑐𝑐 + 1
. The 𝑄𝑄 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ) is updated as follows,
𝑄𝑄 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ) ← 𝑄𝑄 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ) + 𝛼𝛼 � 𝑅𝑅 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ) + 𝛽𝛽 𝑀𝑀 𝑖𝑖 𝑛𝑛 𝑐𝑐 𝑖𝑖 + 1
� 𝑄𝑄 ( 𝑠𝑠 𝑐𝑐 + 1
, 𝑡𝑡 𝑐𝑐 + 1
) � − 𝑄𝑄 ( 𝑠𝑠 𝑐𝑐 , 𝑡𝑡 𝑐𝑐 ) � (68)
where 𝛼𝛼 is the learning rate and 𝛽𝛽 is the discount factor. The 𝑀𝑀 𝑖𝑖 𝑛𝑛 function is applied
since we are interested in minimizing the penalty. RL involves finding a balance between
exploration of uncharted territory and exploitation of current knowledge. One such
method is 𝜖𝜖 -greedy. We choose the action that we believe has the minimum penalty with
probability 1 − 𝜖𝜖 , otherwise an action uniformly at random. Here, 𝜖𝜖 ∈ [0,1] is a tuning
parameter, which is reduced to zero gradually as the learning process continues.
9.2.4 Deriving the Pareto Tradeoff Curve
RL is a very versatile method that can solve many different problems with a proper setup.
We use RL to solve the DTMB problem at the lower level. However, the entire setup is
differentiated from that in [23] such that the environment of DTMB problem includes the
battery temperature and the load demand when mapping the RL method to the problem
setup. In addition, we take the SoC of the supercapacitor array into account to determine
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whether or not and how much we should charge to and discharge from the supercapacitor
array. For example, there is no need to charge it anymore even if the load demands is
very low and the supercapacitor is already full.
We define the state set S as a combination of the battery temperature, the load
demand, and the SoC level of the supercapacitor array, i.e., 𝑆𝑆 = { 𝑇𝑇 } × { 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑
} ×
{ 𝑆𝑆𝑆𝑆 𝐶𝐶 𝑠𝑠 𝑐𝑐 𝑐𝑐 }. Although the SoC of battery array also affects the solution quality ( 𝑅𝑅 𝑐𝑐 𝑛𝑛𝑐𝑐
and
𝑉𝑉 𝑂𝑂 𝐶𝐶 ), we do not consider it in the state set 𝑆𝑆 because these parameters are stable for
typical batteries. Significant changes of 𝑅𝑅 𝑐𝑐 𝑛𝑛𝑐𝑐
only occur when battery is almost fully
charged or nearly depleted. The state set defined above has Markovian properties.
We define the action set as a combination of fan speed levels and battery discharging
power. To obtain a finite action set, we consider a number of discrete levels of available
battery discharging power such that { 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
} = { 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 0
, 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 1
, … }. We selection one from
𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ) ∈ { 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
} and 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 ( 𝑡𝑡 ) is calculated from (67) at each decision epoch. Therefore,
the action set is defined as 𝐴𝐴 = { 𝐹𝐹 } × { 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
}. The state transition is calculated by using
(3)~(9).
We consider a large number of cycles, i.e., the portable system gets charged and then
discharged. We primarily focus on the discharge process in this chapter because devices
are generally charged from a constant and stable power sources such as an AC outlet. A
discharge process [0, 𝜏𝜏 𝑛𝑛 ] is broken into a series of short decision epochs with time
instances { 𝑡𝑡 0
, 𝑡𝑡 1
, 𝑡𝑡 2
, … , 𝑡𝑡 𝑀𝑀 }, where 𝑡𝑡 0
= 0, 𝑡𝑡 𝑀𝑀 = 𝜏𝜏 𝑛𝑛 , in order to apply the discrete RL
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method. We consider the power demand of service provider, 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑚𝑚 , is approximately
unchanged during this 𝑚𝑚 -th decision epoch.
The penalty function should account for both the short-term cooling energy
investment and the long-term benefit of extension of battery lifespan. At the beginning of
𝑚𝑚 -th decision epoch in 𝑛𝑛 -th cycle, we observe the state 𝑠𝑠 𝑚𝑚 𝑛𝑛 , pick the proper action 𝑡𝑡 𝑚𝑚 𝑛𝑛 =
( 𝐹𝐹 𝑚𝑚 , 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 𝑚𝑚 ) according to cumulative state-action pairs values { 𝑄𝑄 ( 𝑠𝑠 , 𝑡𝑡 )}. The total load
power 𝑃𝑃 𝑐𝑐𝑆𝑆 𝑐𝑐𝑑𝑑 , 𝑚𝑚 + 𝑃𝑃 𝐹𝐹 𝑚𝑚 is determined once an action ( 𝐹𝐹 𝑚𝑚 , 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 𝑚𝑚 ) is selected. The working
mode of the hybrid power source and charging or discharging power of supercapacitor
array 𝑃𝑃 𝑠𝑠 𝑐𝑐 𝑐𝑐 , 𝑚𝑚 is in turn determined according to (67). We calculate the total power drawn
from battery 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 𝑚𝑚 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 from (3)(4) considering the rate capacity effect for a given 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 𝑚𝑚 . In
addition, taking action 𝑡𝑡 𝑚𝑚 𝑛𝑛 leads to battery temperature 𝑇𝑇 𝑏𝑏 , 𝑚𝑚 , which in turn results in
𝛥𝛥 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑚𝑚 � 𝑛𝑛 , 𝑇𝑇 𝑏𝑏 , 𝑚𝑚 � amount of SoH degradation during the 𝑚𝑚 -th decision epoch. We
calculate the penalty function as follows,
𝑅𝑅 ( 𝑠𝑠 𝑚𝑚 𝑛𝑛 , 𝑡𝑡 𝑚𝑚 𝑛𝑛 ) = 𝜆𝜆 �
𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐 , 𝑚𝑚 𝑑𝑑 𝑐𝑐 𝑐𝑐𝑠𝑠𝑛𝑛 𝐸𝐸 𝑐𝑐 𝑆𝑆 𝑐𝑐 ( 𝑛𝑛 )
𝑑𝑑𝑡𝑡 𝑐𝑐 𝑚𝑚 𝑐𝑐 𝑚𝑚 − 1
+ (1 − 𝜆𝜆 )
𝛥𝛥 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑚𝑚 � 𝑛𝑛 , 𝑇𝑇 𝑏𝑏 , 𝑚𝑚 �
𝛥𝛥 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑓𝑓 𝑐𝑐 � 𝑛𝑛 , 𝑇𝑇 𝑐𝑐𝑠𝑠 𝑓𝑓 �
(69)
where the 𝐸𝐸 𝑐𝑐 𝑆𝑆 𝑐𝑐 ( 𝑛𝑛 ) is total energy capacity of the battery pack in 𝑛𝑛 -th cycle,
𝛥𝛥 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑓𝑓 𝑐𝑐 ( 𝑛𝑛 , 𝑇𝑇 𝑐𝑐𝑠𝑠 𝑓𝑓 ) is the SoH degradation over 𝑛𝑛 -th full cycle at reference temperature
(25° 𝐶𝐶 ). We use the penalty function in (69) to update { 𝑄𝑄 ( 𝑠𝑠 , 𝑡𝑡 )} by using (68). According
to (67), the first term in (69) account for effects of two operations on the energy drawn
from the battery array: i) the fan speed setting; and ii) the charge management of the
hybrid power source. The first term increases when higher fan speed is used or the battery
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array is used to charge the supercapacitor array. Note that the latter operation stores
energy into the supercapacitor array, which is used to shave power demand peaks, i.e.,
reduce the first term in (69), in following decision epochs. Therefore, we learn the
optimal fan speed setting policy and charge management policy by using (69).
𝜆𝜆 in (69) is a weighting factor that adjusts the relative weight between the SoH
degradation and total energy drawn from the battery in the penalty function. We obtain a
tradeoff curve between SoH degradation and cooling energy investment by varying 𝜆𝜆 .
Each tradeoff point in this curve is a Pareto optimal point because it is not possible to
achieve less SoH degradation without investing more energy in cooling, and vice versa.
The Q-learning method requires to maintain a state-action pairs set matrix { 𝑄𝑄 ( 𝑠𝑠 , 𝑡𝑡 )}.
We divide the battery temperature, load demand, and SoC level of supercapacitor into 15,
10, and five discrete levels in this work, which gives a total number of 750 states. We
consider 10 discrete levels of battery discharging power and three fan speed levels (off,
low, and high), which gives a total 30 actions. The problem setup above gives about
22,500 state-action pairs. In practice, we achieve a quick convergence after 1,000 training
cycles, while we divide each cycle into a few hundreds of decision epochs. Note that this
training process is offline and only carried out once.
9.2.5 Maximizing Cumulative Workload Completion
With the Pareto tradeoff curve, the problem at the upper level is how to determine the
optimal tradeoff strategy to meet the desired system lifetime as well as maximize the
CWC. More precisely, we solve a sub-problem of how to select a tradeoff option from
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RL results for each cycle by properly balancing the energy investment in cooling and the
energy used by service provider to complete workloads.
We start from a general problem, that is, how to maximize the CWC over 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿
number of cycles with a constraint that the SoH loss is no more than 𝛥𝛥 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 . We
construct a matrix of which the rows relate to the cycle index (1,2, … , 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 ) while the
columns relate to quantized SoH loss levels ( 𝛥𝛥 𝑆𝑆𝐿𝐿 , 2 𝛥𝛥 𝑆𝑆𝐿𝐿 , … , 𝑀𝑀 ⋅ 𝛥𝛥 𝑆𝑆𝐿𝐿 , where 𝑀𝑀 ⋅ 𝛥𝛥 𝑆𝑆𝐿𝐿 =
𝛥𝛥 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 ). Each element in this matrix, 𝑊𝑊 ( 𝑛𝑛 , 𝑚𝑚 ), implies the maximum workload that the
system can provide over all 𝑛𝑛 cycles with the SoH loss of 𝑚𝑚 ⋅ 𝛥𝛥 𝑆𝑆𝐿𝐿 . We derive 𝑊𝑊 ( 𝑛𝑛 , 𝑚𝑚 ′ )
from 𝑊𝑊 ( 𝑛𝑛 − 1, 𝑚𝑚 ), where 𝑚𝑚 ′
> 𝑚𝑚 , and the tradeoff options. Recursively optimizing sub-
problems implies that a dynamic programming method is applicable, while 𝑊𝑊 ( 𝑛𝑛 , 𝑚𝑚 ) is
the memory matrix. We implement a bottom-up DP algorithm to solve this problem.
An important issue for the DP algorithm is to control the time complexity and the
memory complexity. Let us denote the lower level RL gives 𝑍𝑍 number of tradeoff options
as follows,
𝑇𝑇 𝑒𝑒 𝑡𝑡 𝑑𝑑𝑒𝑒 𝑆𝑆 𝑓𝑓𝑓𝑓 = � � 𝑒𝑒 𝑓𝑓 𝑐𝑐𝑛𝑛 , 𝑧𝑧 , Δ 𝑠𝑠 𝑆𝑆 ℎ
𝑧𝑧 � , 𝑧𝑧 ∈ {1, 2, … , 𝑍𝑍 } � (70)
where 𝑒𝑒 𝑓𝑓 𝑐𝑐𝑛𝑛 , 𝑧𝑧 and Δ 𝑠𝑠 𝑆𝑆 ℎ
𝑧𝑧 in (70) are the cooling energy investment normalized to total
battery energy and SoH degradation normalized to SoH at that time of 𝑧𝑧 -th tradeoff
option, respectively,
𝑒𝑒 𝑓𝑓 𝑐𝑐𝑛𝑛 , 𝑧𝑧 =
∑
∫ 𝑃𝑃 𝐹𝐹 𝑚𝑚 𝑐𝑐 𝑚𝑚 𝑐𝑐 𝑚𝑚 − 1
𝑑𝑑𝑡𝑡 𝑀𝑀 𝑚𝑚 = 0
𝐸𝐸 𝑐𝑐 𝑆𝑆 𝑐𝑐 ( 𝑛𝑛 )
× 100%
(71)
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Δ 𝑠𝑠 𝑆𝑆 ℎ
𝑧𝑧 =
∑ 𝛥𝛥 𝑆𝑆𝑆𝑆 𝐻𝐻 𝑚𝑚 ( 𝑛𝑛 , 𝑇𝑇 𝑚𝑚 )
𝑀𝑀 𝑚𝑚 = 0
𝑆𝑆𝑆𝑆 𝐻𝐻 ( 𝑛𝑛 )
× 100%
Note that the parameter 𝑛𝑛 in the RHS of (71) disappears after the normalization because
the total energy and SoH degradation are all linearly related to SoH.
The DP algorithm is described in Algorithm 9.1. 𝑃𝑃𝑡𝑡 𝑡𝑡 ℎ matrix and 𝑂𝑂 𝑝𝑝𝑡𝑡 𝑖𝑖 𝑆𝑆 𝑛𝑛 matrix
record the SoH and select tradeoff options from the previous cycle. We trace back and
find the optimal tradeoff strategy by using the information in 𝑃𝑃𝑡𝑡 𝑡𝑡 ℎ and 𝑂𝑂 𝑝𝑝𝑡𝑡 𝑖𝑖 𝑆𝑆 𝑛𝑛 matrix.
Function 𝐼𝐼 𝑛𝑛𝑑𝑑𝑒𝑒 𝑥𝑥 discretizes the continuous SoH degradation to index the matrices.
Function 𝐶𝐶 𝑡𝑡 𝑡𝑡 𝑐𝑐𝑊𝑊𝐿𝐿 calculates the workload that the portable system completes by
selecting a particular tradeoff option. DP method finds the optimal tradeoff strategy to

Algorithm 9.1. DP method to determine the tradeoff strategy.
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maximize 𝑊𝑊 ( 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 , 𝑀𝑀 ), taking the tradeoff options obtained from the lower level RL.
Note that 𝐶𝐶 𝑡𝑡 𝑡𝑡 𝑐𝑐𝑊𝑊𝐿𝐿 adopts an approximation in calculating the workload. This
approximation, considering the workload completion to be proportional to the battery
energy that is not used for cooling, provides a fast and accurate estimation of real
workload completion. We demonstrate the efficacy of the presented algorithm in Chapter
9.3, while the workload completion is calculated through cycle accurate simulation.
In Algorithm 9.1, we need to try at most 𝑍𝑍 tradeoff options to new elements from
each 𝑊𝑊 ( 𝑛𝑛 , 𝑚𝑚 ) that is already known. Hence, the total time complexity of Algorithm 9.1
is 𝑂𝑂 ( 𝑀𝑀 𝑁𝑁𝑍𝑍 ) and the memory complexity is 𝑂𝑂 ( 𝑀𝑀 𝑁𝑁 ). The SoH degradation is a continuous
process so that we round it to the closest quantized SoH level. We quantize 1% SoH
degradation into 2000 levels during our simulation, considering both the computation
precision and time complexity.
9.3 Experimental Results
We present the simulation results in this section. We first show that better tradeoff
options are achieved by using RL-based method at the lower level and hybrid power
source. Then we show that the presented DP method is able to complete more workload.
9.3.6 Simulation Setups
We use four LiMnNi 22650M cylinder lithium battery cells as the battery array and a 50
F supercapacitor. A single battery cell has height of 65 mm, diameter of 22 mm, weight
of 60 gram, and nominal capacity of 2 𝐴𝐴 ℎ. The total energy capacity of the battery pack is
30.4 𝑊𝑊ℎ , close to a typical commercial laptop battery. The capacitance of the
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supercapacitor is 50 𝐹𝐹 . We target the portable system as a laptop and simulate the load
demands profile as a continuous profile while the magnitude of the power demand
follows a normal distribution, based on the power measurement in [108]. The average
power of the load demand is about 20 𝑊𝑊 . The typical specific heat capacity of the lithium
battery is around 0.8~0.9 𝐽𝐽 ( 𝑔𝑔 𝐾𝐾 )
− 1
. We borrow the relation of internal resistance and
activation energy versus battery SoC [21]. A 70 mm fan is used in the simulation. We
adopt a modified fan model based on [84] and assume that the fan has an off state and
two speed options: 𝐹𝐹 0
(0 RPM), 𝐹𝐹 1
(1000 RPM), and 𝐹𝐹 2
(2000 RPM). Fixed fan speed
baseline setups using 𝐹𝐹 0
are used to produce results of the same system without using any
cooling device.
We design three baseline setups to compare with the presented ATBM system. RL-
Bat baseline adopts the algorithm presented in [23], which uses a RL-based method and a
batter-only power source. Fx-Hy ( 𝑥𝑥 = 0, 1, or 2) adopts fixed fan speed ( 𝐹𝐹 0
, 𝐹𝐹 1
, and 𝐹𝐹 2
)
policy with the hybrid power source. Similarly, Fx-Bat uses fixed fan speed ( 𝐹𝐹 0
, 𝐹𝐹 1
, and
𝐹𝐹 2
) with the batter-only power source. We name the presented ATBM system as RL-Hy
in the following text as it contains the hybrid power source and uses RL-based method to
derive Pareto optimal tradeoff options.
9.3.7 Pareto Tradeoff Curve
We apply the RL-based method and adjust the weighting factor 𝜆𝜆 to produce a continuous
tradeoff between the cooling energy investment and the SoH degradation. For the
baseline setups with fixed fan speed policy, no tradeoff option is available but only the
162

cooling energy investment and the SoH degradation at that fan speed. Figure 9.2 presents
the simulation results.
Figure 9.3 compares the amount of workload completed by RL-Hy and RL-Bat in one
charging-discharging cycle. We select a few tradeoff options whose Δ 𝑠𝑠 𝑆𝑆 ℎ values are
listed in x-axis of Figure 9.3. The workload completions are normalized to a maximal
value – the workload completed in one cycle by F0-Hy baseline (it utilizes hybrid power
source to shave power demand peaks and no energy is spent on cooling). One can
observe from Figure 9.3 that the presented algorithm is able to improve the workload
completion in one cycle by up to 11.8% with the help of hybrid power source. Note that
we do not include results of fixed fan speed baselines in Figure 9.3 because it does not
have tradeoff options that have similar Δ 𝑠𝑠 𝑆𝑆 ℎ values to offer fair comparisons. But their
results are no better because the RL method gives no worse results when that particular
fan speed is a subset of its action set.

Figure 9.2. Tradeoff curve achieved by presented algorithm with a hybrid power source (dot marks)
and a battery-only power source (triangle marks). Cross and circle marks show results of using fixed
fan speed (F0, F1, F2 from left to right) with the hybrid power source.
0
0.01
0.02
0.03
0.04
0% 5% 10% 15%
Δsoh (%)
e
fan
(%)
RL-Hy trade-off options
RL-Bat trade-off options
Fx-Hy
Fx-Bat
163

Figure 9.4 shows the battery temperature traces within one cycle when applying
different RL-Hy tradeoff options. The solid line denotes the temperature trace with fan-
off status, which is F0-Hy baseline. The other three line correspond to normalized
cooling energy investment of 1.40%, 4.10%, and 7.50%, respectively. One can see that
the more energy spent on cooling, the lower temperature that the battery array is
maintained at. Lower battery temperature ensures less SoH degradation.

Figure 9.3. Normalized one-cycle workload completion of different tradeoff options in RL-Hy and
RL-Bat tradeoff curve.

Figure 9.4. Battery temperature traces in one cycle when applying F0-Hy (0%) and RL-Hy tradeoff
options with different efan.
0
0.2
0.4
0.6
0.8
1
0.013 0.015 0.018 0.02
Normalized Workload
Δsoh (%)
RL-Hy trade-off options RL-Bat trade-off options
20
40
60
0 1000 2000 3000
Temperature (˚C)
Time (sec)
0% 1.40% 4.10% 7.50%
164

9.3.8 Battery Array Lifespan Extension
We set Δ 𝑆𝑆 𝐿𝐿 𝐻𝐻𝑂𝑂 𝐿𝐿 to be 20% in our problem setup. Figure 9.5 shows the maximal number of
cycles before the battery array reaches its EOL point in all baseline setups and the
presented RL-Hy. One can see that the presented thermal management policy
significantly extends the battery lifespan. The other two baseline setups that use constant
fan speed of 𝐹𝐹 1
and 𝐹𝐹 2
extend the battery lifespan by 1.40X and 1.87X against the fan-off
option in the battery-only system, and 1.40X and 2.02X against the fan-off option in the
hybrid power source system, respectively. Spending energy in cooling degrades the short-
term performance because the energy that was spent on cooling could have been used to
power the service provider. However, in the long-term, the battery lifespan (as well as the
system lifetime) is extended significantly. Therefore, we achieve higher CWC in systems
using cooling devices. Again, the RL method gives no worse results than those of the fan

Figure 9.5. Maximal lifespan of the battery array when ΔSLEOL is 20%.
0
500
1000
1500
2000
F0-Bat F1-Bat F2-Bat RL-Bat F0-Hy F1-Hy F2-Hy RL-Hy
Cycles
165

speed in its action set. The presented algorithm achieves same battery lifespan when the
penalty function focuses on the SoH degradation, i.e., setting 𝜆𝜆 in (69) to be 0.
9.3.9 Cumulative Workload Completion
Figure 9.6 shows the CWC versus different requirements of the system lifetime. The
solid line in Figure 9.6 shows that RL-Hy achieves the highest CWC over all 𝑁𝑁 𝑑𝑑 𝑠𝑠𝑐𝑐
’s. RL-
Hy improves the CWC at the maximal lifespan by 31.6% against RL-Bat (dash-dotted
line). The difference between RL-Hy and RL-Bat comes from the contribution of the
hybrid power source. The supercapacitor array shaves peaks of the power demand
requested by the service provider through an appropriate charge management. It helps the
battery array in two aspects such that: i) less amount of energy is wasted on the rate
capacity effect and; ii) less heat is generated in the battery array. Therefore, we observe a
longer battery lifespan as well as a higher workload completion in RL-Hy.
Figure 9.6 also shows that both RL-Hy and RL-Bat outperform their corresponding
fixed fan speed counterparts, Fx-Hy (dashed line) and Fx-Bat (dotted line), respectively.

Figure 9.6. Cumulative workload completion versus the desired system lifetime of all baseline setups
and the presented RL-Hy.
0.0
1.0
2.0
0 500 1000 1500 2000
Normalized CWC
N
dsl
RL-Bat RL-Hy Fx-Bat Fx-Hyb
F1-Bat F2-Bat F1-Hyb F2-Hyb
F
0
F
2
F
1
166

The three dashed lines and dotted lines, from left to right in Figure 9.6, are corresponding
to CWC with fixed fan speeds 𝐹𝐹 0
, 𝐹𝐹 1
, and 𝐹𝐹 2
, respectively. On the one side, although
fixed fan speed policies with 𝐹𝐹 0
and 𝐹𝐹 1
achieves good short-term performance, their fail
to maintain the battery array at a good condition if the required system lifetime 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 is
long. RL-Hy improves CWC against F0-Hy and F1-Hy by 78.7% and 40.6%, and RL-Bat
improves CWC against F0-Bat and F1-Bat by 53.0% and 18.6%, respectively. On the
other side, although using fan speed 𝐹𝐹 2
results in a long system lifetime, the presented
algorithm achieves higher CWC for all shorter 𝑁𝑁 𝐷𝐷 𝑆𝑆 𝐿𝐿 because always using highest fan
speed level is over-conservative. Finally, the presented algorithm achieves larger
improvement against the fixed fan speed baseline setups in systems with hybrid power
sources than the method in [23] does in systems with battery-only power sources. This is
because that using a hybrid power source provides an extra dimension of optimization –
charge management between the battery array and the supercapacitor array in the hybrid
power source.

167

SECTION III MOBILE DEVICES

CHAPTER 10
GENERATING TEMPERATURE MAPS IN MOBILE
DEVICES
Thermal design and management of smartphones are also concerned a skin temperature
constraint. This constraint refers to the fact that the temperature at the device skin must
not exceed a certain upper threshold. Ideally speaking, distributing the heat uniformly
onto the device skin results in the most effective heat dissipation. However, in practice,
majority of the heat flows in vertical direction from the AP die, and thus hot spots are
formed on the device skin above the AP location [109]. It is reported that the hottest spot
on iPad 3 can reach as high as 47˚C while playing graphic intensive games [110].
Usually, a skin temperature thermal governor is implemented to maintain the skin
temperature at a desired setpoint by using a control feedback.
To properly design the thermal path and develop a thermal management policy, it is
necessary to model the temperature map (temperature at different locations) for the
smartphone in an accurate and efficient manner. Knowing the detailed temperature map
on the device skin at the design time is helpful in the device implementation. For
example, using materials with high thermal conductivity in the thermal path enhances
heat removal from the AP and in turn causes high skin temperature, whereas using low
168

thermal conductivity materials cannot remove the heat from the AP fast enough and
hence the die temperature goes up. Moreover, knowing how the temperature of a
particular component depends on use cases helps to derive the optimal thermal
management policy for that component. For instance, setting CPU frequency throttling
levels is affected by how skin temperature depends on the CPU frequency.
Analyzing temperature maps at the early stage of the design flow can significantly
reduce the design time. Even though computational fluid dynamics (CFD) tools generate
accurate temperature maps, they are expensive and not compatible with other
performance/power simulators. Compact thermal modeling (CTM) method has been
proposed for thermal analysis with reasonable accuracy and low computational
complexity [28, 111]. This method builds an RC thermal network based on the well-
known duality between the thermal and the electrical phenomena, and solves for
temperatures in the network in a similar way to finding voltage values in an electrical
circuit.
In this chapter, we present Therminator, a CTM-based component-level thermal
simulator targeting small form-factor mobile devices (such as smartphones and tablets).
Major contributions of this work are the following:
1) Therminator is the first thermal simulator targeting at smartphones. It produces
temperature maps for all components, including the AP, battery, display, and other
key device components, as well as the skin of the device, with high accuracy and fast
runtime. Therminator results have been validated against thermocouple measurements
169

on a Qualcomm Mobile Developer Platform (MDP) [112] and simulation results
generated by Autodesk Simulation CFD [113].
2) Therminator is very versatile in handling different device specifications and
component usage information, which allows a user to explore impacts of different
thermal designs and thermal management policies. New devices can be simply
described through an input specification file (in XML format).
3) Therminator supports parallel processing, allowing users to employ GPU to reduce
the runtime by more than two orders of magnitude for high-resolution temperature
maps.
4) A detailed case study has been conducted for Samsung Galaxy S4 by using
Therminator. The temperature results relate the device performance to the device skin
temperature, as well as the impact of the thermal path design.
10.1 Therminator Overview
Figure 10.1 depicts the overview of Therminator. Therminator takes two input files
provided by users. The specs.xml file describes the smartphone design, including
components of interest and their geometric dimensions (length, width, and thickness) and
relative positions. Therminator has a built-in library storing properties of common
materials (i.e., thermal conductivity, density, and specific heat) that are used to
manufacture smartphones. In addition, users can override these properties or specify new
materials through the specs.xml file. The power.trace file provides the usage
information (power consumption) of those components that consume power and generate
170

heat, e.g., ICs, battery, and display. The power.trace can be obtained through real
measurements or other power estimation tools/methods such as [114, 115]. power.trace
is a separate file so that one can easily interface a performance-power simulator with
Therminator.
Therminator has three main modules. A parser module parses input files, updates the
material library, and makes a set of components specified by the input file. Parser
performs multiple sanity checks after it finishes parsing to detect inappropriately
specified components, e.g., the positions of two components are set such that they
overlap in space. A CTM module takes the valid components set from the parser, divides
them into fine-grained sub-components, and stores them into a spatial database. Next, the
CTM module detects physical contacts among sub-components and builds a compact
thermal model. Finally, the compact thermal model is given to a Solver module. The
solver uses the thermal model along with the power trace coming from the parser to
CTM
Solver
Temperature
.maps
Therminator
Power
measurements
or power
estimation tools
Parallel
Method
power.trace
Parser
specs.xml
Spatial
Database
Material
Library

Figure 10.1. Overview of Therminator.
171

compute temperature maps of all components. The Solver applies a parallel method using
GPUs to solve for temperature results more quickly when GPU hardware is available.
10.2 Compact Thermal Modeling
There is a well-known duality between the thermal and electrical phenomena [116]. The
compact thermal modeling methods build an equivalent RC circuit based on the original
thermal system. In this chapter, we focus on generating the steady-state temperature maps
for components inside a smartphone because the objective of thermal design and
management is to ensure that the device can run continuously without exceeding a given
temperature threshold. Therefore, the device is modeled by using a thermal resistance
network only.
To build a compact thermal model, Therminator divides specified components into
sub-components with smaller dimensions and checks for physical contacts among sub-
components. Finer granularity of sub-component division helps to produce more accurate
temperature maps at the cost of increased runtime and memory usage. Each sub-
component is modeled as a node in the thermal resistance network and has a single
temperature value. A thermal resistance is calculated for every contacted sub-component
pairs, based on their material properties, dimensions, and relative positions.
172

Figure 10.2 shows a small part of thermal resistance network for the Qualcomm
MSM8660 Mobile Developer Platform (MDP) [112]. The components in Figure 10.2,
from top to bottom, include screen protector, display module, PCB and IC chips, battery,
and rear case. Terminator breaks various components into non-equal number of sub-
components according to their importance and requirements of solution quality. For two
adjacent sub-components 𝑖𝑖 and 𝑗𝑗 , the thermal resistance is calculated by serially
connecting two thermal resistors from their centers to the shared surface,
𝑒𝑒 ( 𝑗𝑗 , 𝑖𝑖 ) = 𝑒𝑒 ( 𝑖𝑖 , 𝑗𝑗 ) = 𝑒𝑒 𝑐𝑐 + 𝑒𝑒 𝑖𝑖 =
1
𝐴𝐴 �
𝑡𝑡 𝑐𝑐 𝐽𝐽 𝑐𝑐 +
𝑡𝑡 𝑖𝑖 𝐽𝐽 𝑖𝑖 � (72)
where 𝐴𝐴 is the common area between these two contacted sub-components, 𝐽𝐽 𝑐𝑐 and 𝐽𝐽 𝑖𝑖 are
the thermal conductivity, and 𝑡𝑡 𝑐𝑐 and 𝑡𝑡 𝑖𝑖 are the perpendicular distances from the center of
sub-components to the shared surface, respectively. Note that adjacencies between sub-

Figure 10.2. A cross-section view of the thermal resistance network in a simple smartphone model.
Display
+Air
Chip
PCB
Chassis
C
1
C
2
D
1
D
2 D
3
P
1
P
2
Screen
Protector
C
3
Battery
Rear
Case
B
1
B
2
R
1
R
2
R
3
S
1
S
2
S
3
z
y
Ambient
Ambient
Ambient
x
173

components are detected in a 3D space and thereby, we account for orthotropism in the
material thermal conductivity.
At the boundary of the device, heat diffuses to the ambient environment (air). Thus,
the boundary thermal resistance between the 𝑖𝑖 -th sub-component and the ambient air is
calculated as,
𝑒𝑒 ( 𝑖𝑖 , 𝑡𝑡 𝑚𝑚𝑏𝑏 ) = 𝑒𝑒 𝑐𝑐 + 𝑒𝑒 𝑐𝑐𝑚𝑚𝑏𝑏
=
1
𝐴𝐴 �
𝑡𝑡 𝑐𝑐 𝐽𝐽 𝑐𝑐 +
1
ℎ
𝑐𝑐𝑐𝑐𝑐𝑐 � (73)
where ℎ
𝑐𝑐𝑐𝑐𝑐𝑐 is the air heat transfer coefficient. In the natural convection condition, ℎ
𝑐𝑐𝑐𝑐𝑐𝑐
has the value of 5~25 𝑊𝑊 /( 𝑚𝑚 2
𝐾𝐾 ) [117].
Note that empty spaces, shown as orange areas in Figure 10.2, are left in the design
specifications. Ignoring these empty spaces, i.e., not calculating the thermal resistance
between them and adjacent components will completely disable the heat flow through
them and subsequently result in temperatures over-estimation. Thus, to avoid this issue,
Therminator does VoidFill – i.e., it automatically identifies these empty spaces and fills
them with air, as shown in Figure 10.2. Note that it is not practical to model the internal
air using compact modeling of fluids in our problem, due to the lack of specific air
circulation channels in smartphones. Therefore, in the steady-state, the air flow is ignored
and the air is modeled like other sub-components. We apply a correction factor to the
thermal conductivity of the air to account for this simplification.
Having built the resistance network, we obtain heat flow equations for all sub-
components in a matrix format as follows,
𝑮𝑮 𝑻𝑻 � � ⃗
= 𝑷𝑷 � � ⃗

(74)
174

where 𝑻𝑻 � � ⃗
is the vector of all sub-component temperatures, 𝑮𝑮 is the conductance matrix
derived from the thermal resistance network, and 𝑷𝑷 � � ⃗
is the heat generation vector, which
includes the heat generation of sub-components and heat diffusion from the device to the
ambient environment. Therminator adopts the LUP decomposition method to decompose
𝑮𝑮 into a lower and upper triangular matrices, and then applies forward and backward
substitution to solve for 𝑻𝑻 � � ⃗
. Advanced matrix solver libraries enabling GPU-acceleration
are also included to reduce the runtime for fine-grained temperature maps.
10.3 Therminator Implementation
Therminator is implemented using C++ and compiled by GCC 4.7. The parser adopts
PugiXML [118], an open source, light-weight, and fast C++ XML processing library. The
built-in material library is a class called Materials which holds default material
properties and its data are updated by the parser. All components and sub-components are
instances of Component and Subcomponent classes, respectively. A Device class keeps
track of sub-components objects using a spatial database. Another class called Model takes
the device object and builds the thermal model based on (72) and (73). Several geometric
utility methods are implemented in order to perform basic spatial queries on sub-
components, e.g., checking the physical contact between every two sub-components,
determining if they have overlap in space, and calculating their common area. Moreover,
the Model class calls another parser to read the power.trace file which contains the
power consumption of each component.
175

Matrix solving techniques, namely, the LUP decomposition method followed by the
forward and backward substitution method, are implemented using the sequential method
(which utilizes the CPU) and the parallel method (which utilizes the GPU), respectively.
For the parallel method, Therminator adopts CULA Dense [119], which is a set of GPU-
accelerated linear algebra libraries utilizing the NVIDIA CUDA parallel computing
platform. One can observe that the parallel method speeds up Therminator by more than
two orders of magnitude against the sequential method, as shown in Figure 10.3. Runtime
results of both methods are measured on a server with 4×Intel Xeon E7-8837 CPUs,
64GB of memory, and an NVIDIA Quadro K5000 GPU.
10.4 Therminator Evaluation
10.4.1 Validation of the Therminator Results
We use a Qualcomm MSM8660 MDP [112] as the target system to validate Therminator
results. The MSM8660 MDP has a dual-core 1.5GHz CPU, Adreno 220 GPU, 1GB
LPDDR2 RAM, 3.61-inch touch screen, and a 1,300mAh Li-ion battery. A smartphone

Figure 10.3. Comparison of runtime of sequential and parallel methods for different sub-component
counts.
1
10
100
1,000
10,000
0 2 4 6 8 10 12 14 16 18 20
Runtime (s)
Sub-component Count (×1000)
Sequential
Parallel
120x
172x
176

consists of a large number of small components with irregular geometric shapes and
complicated material compositions. In this work, we try our best to identify the major
components in the MSM8660 MDP and obtain the thermal properties of these
components. Figure 10.4(a) shows a teardown of the MSM8660 MDP. We create a model
for MSM8660 MDP device by identifying major components that have thermal impact to
the entire device and measure their dimensions and relative positions.
Components identified include rear case, chassis, battery, PCB, display, screen
protector, and some ICs, such as AP, DRAM, eMMC, GPS and WiFi. We draw the

Figure 10.4. (a) Teardown of MSM8660 MDP device and temperature measurement kits (circle
marks are temperature measurement points. Note for the PCB, thermocouple is attached onto the
other side), (b) CFD drawing, and (c) Therminator 3-D visualization.
AP
Battery
PCB
LCD Display
Screen Protector
Chassis
Rear Case
(a) (b)
AP
LCD
Display
Chassis
Battery
Rear
Case
PCB
Thermocouples
Screen
Protector
Temperature measurement point
Thermometer
AP
Battery
PCB
LCD Display
Screen Protector
Chassis
Rear Case
(c)
177

MSM8660 MDP model in Autodesk software, as shown in Figure 10.4 (b), and perform
CFD thermal analysis. We treat CFD results as golden results and compare Therminator
results with them. Thus, a similar MDP device model, including the aforesaid
components, their dimensions, relative positions and material properties, is specified in
the specs.xml file for Therminator. Figure 10.4 (c) visualizes the 3-D layout model that
Therminator creates from the input file. Note that Therminator applies different
granularity to different components.
We run a few representative use cases that utilize different components and consume
various amounts of power. Use cases tested in this work are StabilityTest (an app that
heavily stresses CPU and GPU [120]), casual gaming (Candy Crush), YouTube video
streaming, camcorder (video recording), and a local video playback. We adopt Trepn
Profiler [121] to record the per component power consumption breakdown of this device,
and provide as inputs for both CFD simulation software and Therminator. Note that we
assign the total power consumption of some small components (interconnects, sensors,
etc.) to the PCB uniformly because we have no access to the schematic diagram of the
MSM8660 MDP to precisely locate them.
We use thermocouples to measure temperatures at three locations in MSM8660 MDP,
shown as red circles in Figure 10.4 (a). We measure 1) hot spot on the screen right above
the AP; 2) hot spot on the rear case below the battery (because there is a big air gap
between PCB and rear case, the hot spot on the rear case is located below the battery);
and 3) the PCB (the opposite side of the board shown in Figure 10.4 (a).) The ambient
temperature is measured as 23.0˚C during the experiments. We access Sysfs of the MDP
178

device through the Android Debug Bridge interface and obtain the AP junction
temperature by reading the temperature register in
/sys/class/thermal/thermal_zone2 directory. Note that the temperature register only
has the accuracy of ±1˚C.
Table 10.1 compares temperature of aforementioned regions obtained through
thermocouple measurements, CFD simulations, and Therminator. We first compare
thermocouple measurement results and CFD simulation results. One can see that CFD
simulation produces accurate results for all tested use cases and all regions. The
maximum and average temperature error are 2.4˚C and 0.7˚C (11.0% and 4.7%),
respectively. The error mainly comes from simplifications in modeling the real device
and inaccuracies in determining component material properties. Note that the largest error
Table 10.1. Temperatures obtained from the thermocouple measurement (TCM), Autodesk
Simulation CFD, and Therminator. Note the AP junction temperature is read from temperature
register (Reg) instead of measurement. The ambient temperature is 23.0˚C.
Use
Case
Tscreen hot spot (˚C) Trear case hot spot (˚C) TPCB (˚C) T AP junction (˚C)
TCM CFD
Therm
-inator
TCM CFD
Therm
-inator
TCM CFD
Therm
-inator
Reg CFD
Therm
-inator
Stability
Test
38.1 38.4 38.5 38.4 39.1 38.7 44.9 44.5 44.4 60 58.6 59.3
Candy
Crush
37.2 37.8 37.7 38.4 39.2 38.9 46.2 44.6 44.8 59 59.0 59.5
You
Tube
35.8 37.0 36.7 34.6 34.4 34.2 39.3 38.4 38.3 43 45.2 45.4
Cam
corder
31.7 32.2 32.1 33.3 32.6 32.4 36.9 36.2 36.2 42 42.7 43.3
Video
playback
30.2 30.8 30.7 30.5 30.8 30.7 33.3 33.4 33.4 39 39.4 40.0

179

(2.4˚C) comes from the AP junction temperature in YouTube use case. A potential reason
might be the inaccuracy of the temperature register (i.e., ±1˚C).

Figure 10.5. Temperature maps produced by Autodesk Simulation CFD (a1, b1, c1) and by
Therminator (a2, b2, c2) for the screen protector (a), rear case (b), and PCB (c) for the StabilityTest
use case.
180

Next, CFD results are used as golden results and we compare Therminator results with
them. We divide specified components into 7,336 sub-components in total in
Therminator. Table 10.1 shows that for all use cases and temperature points, the
maximum and average errors of Therminator are only 0.7˚C and 0.25˚C (3.65% and
1.42%), respectively, compared to CFD results. Figure 10.5 shows more detailed
comparisons of temperature maps, produced by CFD simulation and Therminator, of
front screen, rear case, and PCB. One can see that Therminator is able to accurately
capture not only the temperature of a particular hot spot, but also temperature maps of the
entire smartphone device. Therefore, Therminator matches very well with the commercial
CFD tool, given the same input models.
10.4.2 Convergence of the Therminator Results
Therminator can generate more detailed temperature maps at higher resolution with
longer runtime. We study the convergence of temperature versus total the number of sub-
components created by Therminator for MSM8660 MDP in Figure 10.6. We calculate
convergence errors at different resolutions by comparing temperature results obtained at

Figure 10.6. Therminator results convergence and runtime versus sub-component counts for the
StabilityTest use case.
0 5 10 15 20
0
2
4
6
8
Sub-component Counts ( ×1000)
Error in percent (%)

T
AP,junc
T
screen
T
rear case
T
PCB
181

a particular resolution to those obtained at the highest resolution that we have tested
(18,109 sub-components in total). One can see that the convergence errors of all four
temperature points drop below 1% when the total sub-components number is above
7,000. According to results reported in Chapter 10.4.1, the difference of Therminator
results compared to CFD results is only 1.42% for 7,500 sub-components. The runtime of
Therminator at that resolution is less than seven seconds.
10.5 Case Study
Therminator is versatile in handling different form-factor devices as long as input files
are provided properly. In this section, we provide a case study targeted at Samsung
Galaxy S4. Samsung Galaxy S4 is a flagship commercial smartphone released in 2013.
Unlike the MSM8660 MDP device, Samsung Galaxy S4 does not provide power
consumption due to some commercial reasons. Thus, the power consumption for major
components, i.e., AP (CPU and GPU) and display, are estimated by measuring the total
power consumption of Galaxy S4 at the battery output terminals and scaling them to the
power breakdown ratio as reported in [122]. A simplified model of Galaxy S4 is also

Figure 10.7. 3D layout for Samsung Galaxy S4. Sub-components are not shown.
eMM
C
PCB Battery
Chassis
Chassis
Rear Case
WiFi
AP 4G LTE
Audio
Codec
Screen Protector
OLED Display
Thin Metal Plate Thick Metal Plate
Chassis
Thermal Pad
182

created, as shown in Figure 10.7. An AP floorplan describing locations of CPU and GPU
is specified in the specs.xml file for better estimation accuracy.
We notice that in Galaxy S4, the thermal governor throttles the CPU, GPU, and
memory operating frequency such that the skin temperature will not exceed 45˚C, i.e., the
skin thermal governor has the temperature setpoint of 45˚C. The critical temperature of
AP junction is usually quite high, say 85˚C, and thereby the frequency throttling we have
observed is triggered by the skin thermal governor. We validate Therminator results for
the maximum skin temperature located on the front screen (denoted as 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐 𝑛𝑛 ) and the AP
Table 10.2. Skin temperature and AP junction temperature obtained by thermocouple measurement
(TCM) and Therminator at different AP power consumption levels.
Method
Temperature (˚C) Power (W)
𝑻𝑻 𝑨𝑨𝑷𝑷 , 𝒋𝒋 𝒋𝒋 𝒋𝒋𝒋𝒋
𝑻𝑻 𝒔𝒔 𝒔𝒔𝒔𝒔 𝒋𝒋 𝑷𝑷 𝑨𝑨𝑷𝑷 * 𝑷𝑷 𝑨𝑨𝑷𝑷 , 𝒍𝒍𝒍𝒍𝒍𝒍 𝒔𝒔 𝑷𝑷 𝑨𝑨𝑷𝑷 , 𝒅𝒅 𝒅𝒅 𝒋𝒋
TCM 62.5 44.8 2.20 0.15 2.05
Therminator
68.0 47.7 2.64 0.18 2.46
66.5 47.1 2.53 0.17 2.36
65.1 46.5 2.42 0.16 2.26
63.7 45.9 2.31 0.15 2.16
62.3 45.3 2.20 0.15 2.05
60.9 44.7 2.09 0.15 1.94
59.4 44.1 1.98 0.13 1.85
58.0 43.5 1.87 0.13 1.74
56.1 42.9 1.76 0.12 1.64
55.2 42.4 1.65 0.12 1.53
53.8 41.8 1.54 0.11 1.43
52.3 41.2 1.43 0.11 1.32
50.9 40.6 1.32 0.11 1.21
49.5 40.0 1.21 0.10 1.11
48.1 39.4 1.10 0.10 1.00

183

junction temperature ( 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑖𝑖 𝑓𝑓𝑛𝑛𝑐𝑐
) against the thermocouple measurement results. The
measurements results and Therminator results in the same condition of power
consumption are underlined in Table 10.2. One can see that the temperature error
produced by Therminator is within 0.5˚C (2%).
To simulate the effect of frequency throttling utilized by the thermal governor, we
scale the total power consumption to produce different steady-state skin temperatures.
Table 10.2 reports the corresponding 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 and 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑖𝑖 𝑓𝑓𝑛𝑛𝑐𝑐
values for different AP power
consumption values. To better study the effect of skin temperature on the device
performance, we obtain the dynamic power consumption by subtracting the leakage
power consumption, estimated by using McPAT [123], from the total AP power
consumption values. Note that we use average AP temperature to estimate leakage power
consumption values. Each row in Table 10.2 indicates a dynamic power consumption
level when that specific skin temperature is met. In other words, when the skin thermal
governor sets the target 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 as the values listed in the third column of Table 10.2, the
approximated AP’s dynamic power consumption allotment are shown in the fifth column.
Figure 10.8 plots the AP’s dynamic power consumption allotment, denoted by 𝑃𝑃 𝐺𝐺𝐴𝐴 , 𝑐𝑐𝑐𝑐𝑐𝑐 ,
versus the skin temperature setpoint, denoted by 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 , 𝑠𝑠𝑠𝑠 𝑐𝑐 , as the latter is a typical variable
in various thermal management policies. The blue dots indicates that 𝑃𝑃 𝐺𝐺𝐴𝐴 , 𝑐𝑐𝑐𝑐𝑐𝑐 (which is
proportional to the device operating frequency and therefore, the device performance) has
a linear relationship with the setpoint value of skin temperature. From the data presented
in Figure 10.8, we capture this relationship as,
184

𝑃𝑃 𝐺𝐺𝐴𝐴 , 𝑐𝑐𝑐𝑐𝑐𝑐 = 𝛼𝛼 ⋅ 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 , 𝑠𝑠𝑠𝑠 𝑐𝑐 − 𝛽𝛽 (75)
where 𝛼𝛼 = 0.18W/K and 𝛽𝛽 = 5.92W. Since the device performance highly depends on
𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 , 𝑠𝑠𝑠𝑠 𝑐𝑐 , allowing high skin temperature results in significant performance improvement.
For instance, increasing 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 , 𝑠𝑠𝑠𝑠 𝑐𝑐 from 45˚C to 48˚C results in 15.5% increase of 𝑃𝑃 𝐺𝐺𝐴𝐴 , 𝑐𝑐𝑐𝑐𝑐𝑐 ,
i.e., an increase from 1.93W to 2.23W. On the other hand, decreasing 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 , 𝑠𝑠𝑠𝑠 𝑐𝑐 from 45˚C
to 42˚C results a decrease from 1.93W to 1.63W. In addition, one can also observe from
Figure 10.8 that the AP’s junction temperature also linearly depends on the skin
temperature setpoint (red crosses).
Clearly, modifying the thermal path design for a device affects its peak performance
level. We study the thermal impact of thermal properties of the device exterior case by
exploring its thermal conductivity from very low value (insulation material) to a high
value (conductive material). Figure 10.9 (a) shows that both of 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 and 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑖𝑖 𝑓𝑓𝑛𝑛𝑐𝑐

decrease when using higher thermal conductivity materials for the exterior case of the

Figure 10.8. AP power consumption and junction temperature versus various skin temperature
setpoints.
0.5
1
1.5
2
2.5
AP power allotment (W)
Skin temperature setpoint ( ° C)

P
AP,dyn
= α ⋅T
skin,set
- β
38 40 42 44 46 48
50
60
70
T
AP, junc
( ° C)
P
AP,dyn
T
AP,junc
185

device. More precisely, adopting aluminum as the device case results in 2~3˚C lower
𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 and 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑖𝑖 𝑓𝑓𝑛𝑛𝑐𝑐
, comparing with using pure plastic as the device case. This temperature
reduction is helpful in improving the device performance. In practice, device
manufacturers may also account for other factors such as the manufacturing cost.
We also investigate the impact of the material composition of the thermal pad, which
is attached on top of the AP, and report the results in Figure 10.9 (b). A clear trade-off
can be observed between 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 and 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑖𝑖 𝑓𝑓𝑛𝑛𝑐𝑐
at various types of materials. This
observation complies with results reported by a group of researchers at Texas Instrument
[76]. The optimal thermal path design should touch the AP junction temperature
constraint and skin temperature constraint at the same time. According to our study, from
the thermal path design perspective, adopting a thermal pad with lower thermal

Figure 10.9. Skin and AP junction temperature versus rear case material (a) and thermal pad
material (b) for PAP=2.2W.
40
45
50
T
skin
( ° C)
Thermal pad material's conductivity (Wm
-1
K
-1
)

10
-1
10
0
10
1
10
2
60
65
70
T
AP, junc
( ° C)
T
skin
T
AP,junc
40
45
50
T
skin
( ° C)
Case material's conductivity (Wm
-1
K
-1
)

10
-1
10
0
10
1
10
2
58
63
68
T
AP, junc
( ° C)
T
skin
T
AP,junc
Plastic
Aluminum
186

conductivity on top of the AP achieves better performance. This is because 𝑇𝑇 𝑠𝑠 𝑘𝑘𝑐𝑐𝑛𝑛 is
usually more critical in smartphones and a low thermal conductivity material hinders the
heat flow to the device skin. However, in practice, some other factors (such as
accelerated aging of AP and high leakage power at high temperatures) may prevent the
use of low thermal conductivity material.

187

CHAPTER 11
DYNAMIC THERMAL MANAGEMENT IN MOBILE
DEVICES
Conventional DTM methods work well for computer systems where the CPU is assumed
to be thermally independent of other components. However, due to the sharing of the
rather small physical space, thermal behaviors of different components in mobile devices
may interact with each other. Therefore, conventional DTM approaches, which only
focus on processors, should be modified to consider the thermal coupling effect between
the major heat generation components in enclosures of mobile devices, e.g., AP and
battery. Although typical system-on-chip designs avoid direct abutment of the battery and
AP, thermal coupling between these two components exists. For example, we clearly
observe that the AP temperature rises, when we turn off the AP and discharge the
smartphone battery separately. Figure 11.1 shows how the AP temperature increases as
the battery temperature.

Figure 11.1. Temperature profile of the battery and application processor during the 1C battery
discharging in Nexus S. The phone is turned off.
188

This chapter points out the strong thermal coupling between the AP and battery in a
mobile device enclosure, and provides a quantitative characterization of this effect. In
particular, we build the thermal RC-circuit model to account for this effect and extract
corresponding parameters through practical experiments. We also present a DTM method
combining the thermal sensor readouts, look-up tables (LUTs), and the RC-circuit
thermal modeling. For each task, we calculate the minimum frequency that guarantees to
meet deadline constraints and lookup the maximum frequency that avoids thermal
violations from pre-characterized tables. The DTM policy is based on the relationship
between these two frequencies. In case of a thermal violation is predicted, a DTM
response mechanism is activated, e.g., reducing the operating frequency or dropping the
task, to avoid the potential violation of the critical temperature. Simulations targeting real
smartphone platforms show significant reduction of the number of thermal violations by
considering the thermal coupling effect.
11.1 Problem Statement
11.1.1 Power and Thermal Models
We adopt the output power and thermal model of batteries that are presented in Chapter 3.
The power consumption of the AP has two components: dynamic part and static (leakage)
part. It is known that the leakage power has a strong dependence on the die temperature.
Accurately modeling the power consumption of the AP is quite complicated since it
contains many parts working at different frequency and voltage levels. We derive the
approximated total power consumption versus voltage, frequency, and temperature based
189

on our own measurements. The thermal behaviors of the application processor is more
straightforward than batteries. According to [28], thermal resistance is proportional to the
package thickness and inverse of the interface area between the AP package and ambient
environment. The thermal capacitance is proportional to the thickness and area of the AP
package. The heat generation is proportional to the power consumption of the AP.
11.1.2 RC-circuit Thermal Model of Thermal Coupling
Figure 11.2 shows a conceptual diagram of the mobile devices. Differ from previous
work, we include a thermal resistor between the AP and the battery to reflect the thermal
coupling effect. Figure 11.3(b) models Figure 11.2 using a RC-circuit manner. The
thermal model includes elements as follows: 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
and 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
denote temperatures of
the AP, battery, and ambient environment; 𝐶𝐶 𝐺𝐺𝐴𝐴 and 𝐶𝐶 𝑏𝑏 𝑐𝑐𝑐𝑐
denote thermal capacitances of
the AP and battery; 𝑃𝑃 𝐺𝐺𝐴𝐴 and 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
are the heat generated by the AP and battery; and
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
and 𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
are thermal resistors between the ambient environment and the
AP and battery, respectively. Compare to conventional RC-circuit thermal models like
Figure 11.3(a) in [28, 84], a thermal resistor that corresponds to the thermal coupling
between the AP and battery is considered. Note that in Figure 11.3 (b), the heat
generation of the battery is described as a dependent source since it is determined by the
total current demand of the AP and other components, as shown in (3)(4)(9).
We write the Kirchhoff equations for the proposed RC-circuit thermal model shown
in Figure 11.3 (b) as follows,

𝐶𝐶 𝐺𝐺𝐴𝐴 𝑑𝑑 𝑇𝑇 𝐺𝐺𝐴𝐴 𝑑𝑑𝑡𝑡 = 𝑃𝑃 𝐺𝐺𝐴𝐴 −
𝑇𝑇 𝐺𝐺𝐴𝐴 − 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
−
𝑇𝑇 𝐺𝐺𝐴𝐴 − 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
,
(76)
190

𝐶𝐶 𝑏𝑏 𝑐𝑐𝑐𝑐
𝑑𝑑 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
𝑑𝑑𝑡𝑡 = 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
−
𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
− 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
−
𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
− 𝑇𝑇 𝐺𝐺𝐴𝐴 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐

It is worthy to point out that the conventional RC-circuit thermal model in Figure
11.3 (a) is a special case of the proposed model: one can obtain the conventional model
by disconnecting the battery heat source and short the 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
to 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
. In that case, the AP
has two parallel-connected thermal resistors between 𝑇𝑇 𝐺𝐺𝐴𝐴 and 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
.

Figure 11.2. Conceptual diagram of thermal resistors in mobile devices.

Figure 11.3. Comparison of RC-thermal circuit models: a) conventional thermal model; b) thermal
model considering the thermal coupling effect.
191

11.1.3 Effect of the Thermal Coupling
At the steady-state, equations set (76) has closed-form solutions as follows,

𝑇𝑇 𝐺𝐺𝐴𝐴 = 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
+
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
⋅ 𝑃𝑃 𝐺𝐺𝐴𝐴 +
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
⋅ 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
,
𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
= 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
+
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐 𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
⋅ 𝑃𝑃 𝐺𝐺𝐴𝐴 +
𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
𝑅𝑅 𝑏𝑏 𝑐𝑐 𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
+ 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
⋅ 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
.
(77)
We solve the 𝑇𝑇 𝐺𝐺𝐴𝐴 by plotting both left and right hand sides in (77) and finding the
cross-point, as shown in Figure 11.4. In Figure 11.4, the line 1 denotes the temperature-
dependent 𝑃𝑃 𝐺𝐺𝐴𝐴 at a fixed operating frequency, i.e., fixed dynamic power consumption. The
leakage power consumption increases super-linearly with respect to the AP temperature.
Line 1 stands for solutions without considering the thermal coupling and line 2 stands for
closed-form solutions of (77). In general, the intercept of line 2, denoted by 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
∗
, does

Figure 11.4. The effect of the elevated ambient temperature on the chip power consumption due to
the thermal coupling in mobile devices.
192

not equal to 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
because the last term in (77) is generally non-zero. The slope of line 2
is smaller than line 1 because high 𝑃𝑃 𝐺𝐺𝐴𝐴 causes elevated 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
, which plays a negative role
in heat dissipation of the AP. Figure 11.4 shows that ignoring the thermal coupling
between the battery and AP could result in underestimation of 𝑇𝑇 𝐺𝐺𝐴𝐴 and 𝑃𝑃 𝐺𝐺𝐴𝐴 .
11.1.4 Problem Formulation
Application processors typically have accurate temperature sensors embedded inside the
package or on the printed circuit board [124], and thereby we can utilize these thermal
sensors in the DTM methods. Although thermal sensors may suffer from noise issue, it is
beyond the scope of this work. Although the temperature distribution inside the AP
package is generally uneven among the junctions, we approximately focus on the
temperature of the entire AP package at the system-level. We propose the DTM method
combining the accurate temperature predictions using the proposed RC-circuit thermal
model with the thermal sensors and pre-characterized LUTs.
We consider stationary periodic soft real-time system and describe a task 𝑇𝑇 𝑐𝑐 by
( 𝑡𝑡 𝑐𝑐 , 𝑊𝑊 𝑐𝑐 , 𝑑𝑑 𝑐𝑐 ), where 𝑡𝑡 𝑐𝑐 , 𝑊𝑊 𝑐𝑐 and 𝑑𝑑 𝑐𝑐 denote the arrival time, workload and deadline for 𝑖𝑖 -th
task, respectively. The typical magnitude 𝑑𝑑 𝑐𝑐 are set to be in the order of tens to hundreds
of milliseconds. We adopt a common assumption in the real-time system that the next
task arrives no sooner than the deadline of the current task, 𝑡𝑡 𝑐𝑐 + 𝑑𝑑 𝑐𝑐 ≤ 𝑡𝑡 𝑐𝑐 + 1
. We consider
discrete operating frequency levels in the AP. The supply voltage, denoted by 𝑉𝑉 𝑑𝑑𝑑𝑑 , 𝑘𝑘 , is set
as the minimum voltage that can support the AP running at operating frequency 𝑓𝑓 𝑘𝑘 . We
193

consider 𝐾𝐾 number of discrete operating frequency levels ( 𝑓𝑓 1
, 𝑓𝑓 2
, … , 𝑓𝑓 𝐾𝐾 ) for practical use
and thereby 𝐾𝐾 number of voltage levels ( 𝑉𝑉 𝑑𝑑𝑑𝑑 , 1
, 𝑉𝑉 𝑑𝑑𝑑𝑑 , 2
, … , 𝑉𝑉 𝑑𝑑𝑑𝑑 , 𝐾𝐾 ).
We aim to maximize the performance of the application processor subject to thermal
constraints. The AP performance is defined as the percentage of tasks that are finished by
their deadlines. Previous work in [125] revealed that keeping the die temperature at the
maximal allowable value results in the maximum throughput. Therefore, we let the AP
running at the temperature level close to the 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 . We first qualitatively characterize
the thermal coupling between the AP and battery through a series of experiments. Then
we utilize the characterized thermal model to provide accurate predictions of the AP
temperature, given the current temperature readings. In case that a thermal violation is
predicted, we first try to avoid it by reducing the operating frequency which may violate
the deadline constraint but still finish the task before the arrival time of the next task. It
causes a relatively small amount of quality of service (QoS) degradation. However, we
have to drop the task if no thermally safe operating frequency can be selected to finish the
task by next arrival time, which causes a large amount of QoS degradation.
11.2 Methodology
11.2.1 Parameter Extraction of the RC-Circuit Thermal Model
We setup the following experiments to extract the parameters of the proposed thermal
model in Figure 11.3(b).
194

11.2.1.1 Characterizing the battery
We first setup an experiment to characterize 𝑒𝑒 𝑐𝑐 𝑛𝑛𝑐𝑐
, 𝜕𝜕 𝑉𝑉 𝑂𝑂 𝐶𝐶 /𝜕𝜕 𝑇𝑇 , 𝑅𝑅 𝑏𝑏 𝑐𝑐𝑐𝑐 − 𝑐𝑐𝑚𝑚𝑏𝑏
, and 𝐶𝐶 𝑏𝑏 𝑐𝑐𝑐𝑐
. We take
the battery out from the smartphone, connect the battery terminals to a programmable
active load device and place it in a constant-temperature chamber which maintains
constant ambient temperature. We discharge the battery with various constant C-rating
currents and derive 𝑒𝑒 𝑐𝑐 𝑛𝑛𝑐𝑐
based on the voltage differences at different current ratings. We
calculate the SoC of the battery by Coulomb counting and determine parameters 𝑏𝑏 's
according to (2). After separating thermal contributions made by ohmic heat and entropy
change heat, we extract other parameters using curve fittings.
11.2.1.2 Characterizing the battery-AP thermal coupling
We derive 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
and 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚 𝑏𝑏 in this experiment. The idea is to heat up only the
battery and then measure the AP temperature change, while the AP is turned off.
However, direct discharging battery using an active load has two issues: 1) it is
impossible to precisely control the heat generation rate of the battery, given the complex
battery thermal model in (9); and 2) the heating-up process is limited by the battery
capacity. Therefore, we heat up the battery with a heater that wraps around the battery.
The battery heater enables us to emulate a controllable constant-power heating such that
both of the battery and AP reach their thermal equilibriums, i.e., the steady-states. We
measure the steady-state temperatures and solve for 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
and 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
, by letting
𝑃𝑃 𝐺𝐺𝐴𝐴 = 0 and 𝑃𝑃 𝑏𝑏 𝑐𝑐𝑐𝑐
to be the heat generation rate set in the experiment in (77).
195

11.2.1.3 Characterizing the AP
We derive the thermal capacitance of the AP, 𝐶𝐶 𝐺𝐺𝐴𝐴 , in this experiment. Note that we
cannot determine 𝐶𝐶 𝐺𝐺𝐴𝐴 in Chapter 11.2.1.2 because the steady-state temperature is
independent of the thermal capacitance. There are generally two ways to derive the RC
thermal time constant of the AP: heating-up or cooling-down. We use the latter method
because accurately measuring the AP power dissipation is rather complicated. Therefore,
we heat up the entire smartphone using the chamber, then place it to room environment
and record the cooling-down temperature profile of the AP. The 𝐶𝐶 𝐺𝐺𝐴𝐴 is derived using the
measured RC time constant and previously determined 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
.

Figure 11.5. The flowchart of the proposed DTM method.
Readings from the thermal
sensors, T
AP
(t), T
bat
(t)
Task knowledge (a, W, d)
f
dl,i
, te
i
, f
safe,i
, T
AP
(t+te
i
)
Characterize the RC-circuit
thermal model
Characterize thermally safe
frequency look-up table F
Offline Characterization Part
Drop the task
Run the task at
f=f
dl,i
Run the task at
f=f
safe,i
f
dl,i
≤ f
safe,i
? T
AP
(t+te
i
)

≤ T
cr
? W
i
/f
safe,i
≤ a
i+1
-a
i
?
No No
Yes
Yes
No
Yes
Online Management Part
196

11.2.2 Dynamic Thermal Management
In this section, we present our DTM method, which consists of an offline
characterization part and an online management part. Figure 11.5 shows the flowchart of
the proposed DTM method. We first characterize the proposed RC-circuit thermal model,
which allows us to accurately predict the AP thermal behaviors. Then we define a
thermally safe frequency 𝑓𝑓 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 as the maximum frequency that we can keep the AP
running without causing the thermal violation after a time interval Δ 𝑡𝑡 , which is given by,

𝑓𝑓 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 ( 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
, Δ 𝑡𝑡 )
= max{( 𝑓𝑓 𝑘𝑘 | 𝑇𝑇 𝐺𝐺𝐴𝐴 ( 𝑡𝑡 + Δ 𝑡𝑡 ) ≤ 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑐𝑐 , 𝑓𝑓 𝑘𝑘 ∈ ( 𝑓𝑓 1
, 𝑓𝑓 2
, … , 𝑓𝑓 𝐾𝐾 )}
(78)
Since the thermally safe frequency in (78) is independent of the task, we pre-
characterize all 𝑓𝑓 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 at different conditions and store them into a LUT, denoted by
𝐹𝐹 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 ( 𝑇𝑇 𝐺𝐺𝐴𝐴 , 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
, Δ 𝑡𝑡 ), using the proposed thermal model and the relationship between the
power consumption and operating frequency.
The online parts focus on maximizing the performance subject to the thermal
constraint. We consider the stationary periodic soft real-time task set in this work. Thus,
for a task ( 𝑡𝑡 𝑐𝑐 , 𝑊𝑊 𝑐𝑐 , 𝑑𝑑 𝑐𝑐 ), we define a deadline frequency 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 as the minimum operating
frequency that can finish the task while meeting the deadline constraint. The
corresponding execution time 𝑡𝑡 𝑒𝑒 𝑐𝑐 is defined as the time to finish the task using 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 .

𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 = 𝑚𝑚 𝑖𝑖 𝑛𝑛 ( 𝑓𝑓 𝑘𝑘 |
𝑊𝑊 𝑖𝑖 𝑓𝑓 𝑘𝑘 ≤ 𝑑𝑑 𝑐𝑐 and 𝑓𝑓 𝑘𝑘 ∈ ( 𝑓𝑓 1
, 𝑓𝑓 2
, … , 𝑓𝑓 𝐾𝐾 ) ,
𝑡𝑡 𝑒𝑒 𝑐𝑐 =
𝑊𝑊 𝑐𝑐 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐
(79)
197

Operating the AP at the frequency lower than 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 results in deadline violations.
However, running the AP at frequency higher than 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 is wasteful from the energy
perspective, which also causes unnecessary higher AP temperature. We access the
thermal sensors and determine the thermally safe frequency for Task 𝑖𝑖 using the
knowledge of the task set and the pre-characterized LUT,

𝑓𝑓 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 , 𝑐𝑐 = 𝐹𝐹 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 ( 𝑇𝑇 𝐺𝐺𝐴𝐴 ( 𝑡𝑡 ), 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
( 𝑡𝑡 ), 𝑡𝑡 𝑐𝑐 + 1
− 𝑡𝑡 𝑐𝑐 )
(80)
At the time instance of 𝑡𝑡 𝑐𝑐 , we apply the following DTM policy to determine whether
to execute this task the operating frequency.
1) 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 ≤ 𝑓𝑓 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 , 𝑐𝑐 : we commit to run Task 𝑖𝑖 at 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 as it is thermally safe and
guarantees to finish by the deadline.
2) 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 > 𝑓𝑓 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 , 𝑐𝑐 : it is not necessary to cause thermal violations since in general 𝑡𝑡 𝑐𝑐 +
𝑑𝑑 𝑐𝑐 ≤ 𝑡𝑡 𝑐𝑐 + 1
. Thus we solve the differential equation (76) for 𝑇𝑇 𝐺𝐺𝐴𝐴 ( 𝑡𝑡 + 𝑡𝑡 𝑒𝑒 𝑐𝑐 ) and if,
a. 𝑇𝑇 𝐺𝐺𝐴𝐴 ( 𝑡𝑡 + 𝑡𝑡 𝑒𝑒 𝑐𝑐 ) ≤ 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑐𝑐 : we commit to run Task 𝑖𝑖 at 𝑓𝑓 𝑑𝑑 𝑐𝑐 , 𝑐𝑐 as it is thermally
safe.
b. 𝑇𝑇 𝐺𝐺𝐴𝐴 ( 𝑡𝑡 + 𝑡𝑡 𝑒𝑒 𝑐𝑐 ) > 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑐𝑐 : there is a thermal violation. We try to resolve it
with QoS degradation and if,
i.
𝑊𝑊 𝑖𝑖 𝑓𝑓 𝑠𝑠 𝑎𝑎 𝑠𝑠 𝑒𝑒 , 𝑖𝑖 ≤ 𝑡𝑡 𝑐𝑐 + 1
− 𝑡𝑡 𝑐𝑐 : we commit to run Task 𝑖𝑖 at 𝑓𝑓 𝑠𝑠 𝑐𝑐𝑓𝑓 𝑠𝑠 , 𝑐𝑐 . It is
thermally safe but causes a small QoS degradation.
198

ii.
𝑊𝑊 𝑖𝑖 𝑓𝑓 𝑠𝑠 𝑎𝑎 𝑠𝑠 𝑒𝑒 , 𝑖𝑖 > 𝑡𝑡 𝑐𝑐 + 1
− 𝑡𝑡 𝑐𝑐 : we have to drop Task 𝑖𝑖 as there is no way to
finish it before the arrival time of next task and meet the thermal
constraint. It causes a large QoS degradation.
Figure 11.6 compares the AP temperature predictions with and without considering
the thermal coupling effect conceptually. In the presence of thermal coupling, since the
battery temperature is typically higher than the ambient environment, ignoring the
thermal coupling effect underestimates the AP temperature. As the battery discharges,
𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
increases and the underestimation of the AP temperature increases as well. Since we
keep the AP temperature close to the maximum allowable value for the sake of
performance, underestimations potentially cause thermal violations. Thus, considering
the thermal coupling in temperature prediction is crucial for the DTM method.

Figure 11.6. Comparison of temperature prediction with and without considering the thermal
coupling effect. The scaling factor is the ratio between the actual operating frequency and the
maximal frequency.
199

We briefly discuss the hardware and software overhead for the proposed DTM
method. Temperature sensors are widely used in the mobile devices for the thermal
management purpose. We pre-characterize the RC-circuit thermal model and the lookup
table that contains thermally stable frequency of AP for each type of device, thereby the
online computation cost is negligible. Since the battery typical has much larger thermal
capacitance, we ignore the battery temperature variation during the task processing period
and only focus on AP temperature. Compare to reactive DTM method, the proposed
DTM method is armed with accurate thermal model to capture the AP thermal behaviors,
and thereby accesses thermal sensors in a relatively low rate, which reduces the data-
collection overhead. The overhead of DVFS (50~200 μs according to [78]) is also
negligible compared to the duration of the task (tens to hundreds of milliseconds.)

Figure 11.7. Experiment setup used to characterize the thermal coupling effect in a Nexus
smartphone.
200

11.3 Experimental Results
We characterize the RC-circuit thermal model for a Google Nexus S smartphone
[126], which has 1500 mAh battery and 1.0 GHz single core ARM Cortex-A8 processor.
We dissemble the phone and attach TC1047AVNB thermal sensors [127] onto the center
of battery back side, and the center of AP package. We reassemble the smartphone and
securely close the battery door so that we keep the original operating condition. The
temperature data are logged using NI-DAQ. The experimental setup is shown in Figure
11.7.
11.3.1 Battery Thermal Modeling
We take the battery from the smartphone, connect the battery terminals to the Kikusui
Table 11.1. Extracted parameters for the proposed RC-circuit thermal model.

Figure 11.8. Measured and simulated battery thermal behaviors for a 1C discharging process.
201

PLZ334W programmable active load device [128]. The system is placed in a constant-
temperature chamber to keep the ambient temperature constant. We perform the constant-
current discharging (0.5C, 1C, and 1.5C) for the battery using the active load and log
temperature profiles of the battery. We extract the 𝐶𝐶 𝑏𝑏 𝑐𝑐𝑐𝑐
, thermal resistance, 𝑒𝑒 𝑐𝑐 𝑛𝑛𝑐𝑐
and
𝜕𝜕 𝑉𝑉 𝑂𝑂 𝐶𝐶 /𝜕𝜕 𝑇𝑇 using the method discussed in Chapter 11.2.1.1. The parameters are
summarized in Table 11.1. The battery thermal model are validated by comparing
simulated results to the measured data, as shown in Figure 11.8. Simulated thermal
behaviors of 1C discharging case show 0.2% error on average.
11.3.2 Battery-AP Thermal Interaction Modeling
We wrap Nichrome wire onto the battery to produce controllable constant heating power.
We apply 1.5V voltage across the Nichrome wire and 0.770A current, which gives a
heating power of 1.125W. We wait for sufficiently long time to let the system reach the
thermal steady-state ( 𝑇𝑇 𝐺𝐺𝐴𝐴 = 31
∘
𝐶𝐶 , 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
= 33.5
∘
𝐶𝐶 , 𝑇𝑇 𝑐𝑐𝑚𝑚𝑏𝑏
= 25.5
∘
𝐶𝐶 ). We derive 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏

and 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑏𝑏 𝑐𝑐𝑐𝑐
using the method discussed in Chapter 11.2.1.2. The results are summarized

Figure 11.9. Measured and simulated battery and AP thermal behaviors by applying a controllable
constant heating power.
202

in Table 11.1. Simulated results of 𝑇𝑇 𝑏𝑏 𝑐𝑐𝑐𝑐
and 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑓𝑓 using extracted parameters match
measured data well with an average error of 0.8% and 0.5%, as shown in Figure 11.9.
11.3.3 AP Thermal Modeling
We place the smartphone in a constant-temperature chamber, heat it up to 50
∘
𝐶𝐶 , and then
move it to the room temperature of 25
∘
𝐶𝐶 . We record the AP temperature decrease curve
and obtain 𝐶𝐶 𝐺𝐺𝐴𝐴 using the 𝑅𝑅 𝐺𝐺𝐴𝐴 − 𝑐𝑐𝑚𝑚𝑏𝑏
in Table 11.1. Figure 11.10 shows that the simulated
cooling down curve matches well with the measured curve, with an average error of
0.85%.

Figure 11.10. Measured and simulated AP temperature trace during the cooling down of the AP.

Figure 11.11. Verification of AP thermal behaviors on Nexus S during the temperature rising while
running the StabilityTest v2.7 benchmark [120].
203

11.3.4 Simulations of Proposed DTM Method
We compare the simulated the temperature rising of the Nexus S using the proposed RC
thermal model and extracted parameters, with the measured temperature profile obtained
by running the StabilityTest v2.7 benchmark [120]. Simulation results in Figure 11.11
show that our system models matches well with measured data at an average error of
1.46%. We carry out following simulations based on our system models.
We setup two periodic task sets: TS1 and TS2. TS2 has relatively shorter interval
between task arrival times and the workload of tasks are heavier than the TS1. We
assume six available operating frequency levels (389, 503, 655, 760, 950, and 1000) MHz.
The power consumption at different frequency levels are derived based on our
measurements. According to our measurements by running benchmarks on the Nexus S,
the critical temperature that invokes the internal DTM is around 40
∘
𝐶𝐶 . Considering that
Table 11.2. Tasks having thermal violation as a percentage of all tasks in TS1.

Table 11.3. Tasks having thermal violation as a percentage of all tasks in TS2.

204

modern smartphones typically have multiple processors and thus produce more heat, we
set the critical temperature in our simulation slightly higher to be 45
∘
𝐶𝐶 and 50
∘
𝐶𝐶 ,
respectively. While the AP is idle, we assume it is power gated with 95% efficiency. The
temperature of the ambient environment is set to be 25
∘
𝐶𝐶 . We compare the proposed
DTM method with a baseline setup: the same DTM method except that the thermal
coupling effect is ignored.
Table 11.2 and Table 11.3 show the number of tasks causing thermal violation, i.e.,

Figure 11.12. Thermal violations caused by baseline DTM without considering thermal coupling
effect. Simulation for TS1 with critical temperature of 45C.

Figure 11.13. Violated tasks and dropped tasks as a percentage of all tasks in Task Set 1 versus
different battery temperature.
205

𝑇𝑇 𝐺𝐺𝐴𝐴 > 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑐𝑐 , as a percentage of all tasks at given different critical temperatures. Since
ignoring the thermal coupling typically underestimates the AP temperature, the baseline
setup results in thermal violations much more frequently. The proposed method avoids
thermal coupling most of the time, thanks to its accurate temperature prediction. The
simulation for TS2 shows more thermal violations than the TS1 because TS2 is heavier.
Among each table, less thermal violations are observed at higher 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑐𝑐 because the
DTM is more relaxed if the allowable temperature is higher. Figure 11.12 shows a clip of
the simulation result. One can see that the AP temperature of the baseline setup rises
above the 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑐𝑐 several times.
Figure 11.13 shows the relationship between the battery temperature and dropped
tasks as a percentage of the all tasks for TS1. High battery temperature brings more
difficulties to heat dissipation of the AP. Therefore, we have to drop more tasks to avoid
thermal violations. On the other hand, maintaining the AP at a lower 𝑇𝑇 𝑐𝑐𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐 𝑐𝑐𝑐𝑐 𝑐𝑐 temperature
results in larger QoS degradation, i.e., more tasks are dropped. Similar trend is observed
for tasks having deadline violations.

206

CHAPTER 12
CONCLUSION AND FUTURE WORK
This dissertation is dedicated to solve several system-level power and thermal-related
problems in energy storage systems and mobile devices. The contributions of this
dissertation include designing the architecture and charge management policies for the
hybrid electrical energy storage (HEES) systems as well as improving thermal modeling
and management policies for mobile devices.
For the energy storage systems, we introduced the fundamental concept of the HEES
systems that are designed to exploit strengths of different EES elements and avoid their
shortcomings. We designed a single-bus HEES system architecture that allows us to
control each EES bank individually, defined key operations by dividing HEES functions
into a few key steps, and presented algorithms to derive the near-optimal control policy
for each key operation. We built a HEES prototype with the purpose of validating the
energy benefits brought by the HEES concept and the efficacy our management policies.
Practical experimental results based on the HEES prototype demonstrated energy
efficiency improvements.
To derive the he near-optimal control policies, we formulated global charge allocation
(GCA) problem, global charge replacement (GCR) problem, and charge migration
scheduling (CMS) problem as mixed-integer non-linear optimization problem (MINLP).
Certain approximations were applied to reduce original MINLP problems to convex
optimization problems. We presented algorithms based on solving convex optimization
207

problem efficiently and iteratively. Meanwhile, to approach to the global optimality, we
incorporated power bounds to shave the peaks in power profiles by using the high-
efficiency, but low energy-density storage banks. Simulation results demonstrated
significant energy efficiency improvement against baseline policies.
Besides the energy efficiency, the lifespan of energy storage systems is also an crucial
performance metric. We introduced the state-of-health (SoH)-aware charge management
problem for HEES systems and combined it with charge management problems. We
designed a forced air-convection cooling mechanism for batteries in portable systems
with a hybrid power source. A hierarchical algorithm that combines a reinforcement
learning method and a dynamic programming method is presented to derive the optimal
management policy. Simulation results showed that the presented joint management
policy and corresponding system setup achieve up to 2X improvements of the battery
lifespan, results in completion of 80% more workload before the batteries expire.
Our work in the HEES can be extended in a few ways. First, the current works in
HEES are mainly based on the single-bus architecture. A sophisticated architecture, such
as the networked CTI, can be used to further improve the availability of EES banks and
enable more system functions at a time. Next, we have found near-optimal solutions for
general charge management problems. However, since the energy storage systems are
widely used in many areas, more detailed, application-specific optimizations of system
design and management can be made to HEES systems.
To address the thermal issues in mobile devices, we started from building an accurate
thermal simulation framework. We presented a component-level compact-thermal-
208

modeling-based approach, targeting at small form-factor devices such as smartphones,
and implemented it as Therminator. Therminator is capable of producing accurate steady-
state temperature maps of all components (ICs, boards, screens, cases, etc.) in a
smartphone with a fast runtime. We validated Therminator results against real
temperature measurements and simulations results from a commercial computational-
fluid-dynamics tool. We carried out a case study of thermal design of the state-of-the-art
Samsung Galaxy by using the Therminator. An extension of this work will be adding
thermal capacitances to the thermal model to allow Therminator to generate transient
temperature results, which enables optimizations of the thermal management policy by
using Therminator.
Next, a thermal coupling effect observed in mobile devices through practical
experiments showed that heat generation components are thermally interacting each
other. We proposed an RC-circuit thermal model to account for the thermal coupling
effect and qualitatively characterized the RC-circuit model. A dynamic thermal
management (DTM) method was presented, combining the proposed thermal model with
the temperature sensors and the pre-characterized LUT, to maximize the smartphone
performance subject to the thermal constraint. We showed that the presented DTM
method that accounts for the thermal coupling effect can significantly reduce thermal
violations. The future research work could extend the thermal coupling-aware dynamic
thermal management policy by incorporating adaptive chip temperature feedback control,
while the temperature setpoint and step-size depend on the battery temperature.

209

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Abstract (if available)

Abstract This dissertation is dedicated to address several thermal-related problems in a multiple systems, including energy storage systems and mobile devices. ❧ The first part of this dissertation introduces hybrid electrical energy storage (HEES) systems by explaining the motivation, proposing basic architectures, defining key HEES operations, and presenting the near-optimal charge management policies. Key HEES operations, including the charge allocation, charge replacement, charge migration, and state-of-health-aware charge management are all formulated as mathematical optimization problems. Near-optimal charge management control algorithms based on certain approximations and iterative solving convex optimization problems are also presented separately for each key HEES operation. Simulation results show significant improvements in energy efficiency and battery lifespan. A HEES prototype is built and implemented with the presented charge management policies to further demonstrate the energy efficiency improvements brought by the hybrid use of different types of energy storage elements and the efficacy of presented policies. In addition, this dissertation also points out that elevated battery temperature can significantly speed up the aging process of batteries, which necessitates a proper thermal management policy for the HEES. This thesis later formulates a joint thermal and charge management problem for batteries in the HEES with a forced air-convection cooling technique and presents a hierarchical algorithm that combines reinforcement learning method and dynamic programming method to derive the optimal joint management policy, which determines charging/discharging profiles of the power source and settings of the cooling device. Simulation results show that presented policy significant improves the battery lifespan, resulting in completion of much more workload before the battery expires. ❧ The second part of the dissertation focuses on mobile devices. The dissertation points out that maintaining the skin temperature (surface temperature on the exterior case of mobile devices) at an appropriate level is a new design challenge in mobile devices because most of them are directly touched by users. A compact thermal modeling-based approach is presented and implemented as Therminator, which is capable of producing temperature maps of all important components, from the application processor (AP) to the skin of the device itself, in an accurate and efficient manner. Therminator have been validated against the practical temperature measurements and commercial computational fluid dynamics simulation tools. A case study on the thermal path design and skin temperature management policy is carried out for a state-of-art smartphone by using Therminator. Next, it is observed in smartphones that there exists a thermal coupling effect, which is referring to the phenomenon that the major heat generation components, such as the AP and the battery, thermally affect each other. Theoretical analysis show that ignoring this thermal coupling effect results in an underestimation of the chip temperature. Practical experiments are presented to quantitatively characterize and model this effect. A thermal coupling-aware dynamic thermal management policy based on an accurate RC-thermal model considering the thermal coupling effect is presented to reduce the maximal temperature violations in mobile devices.

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Asset Metadata

Creator Xie, Qing (author)

Core Title Architectures and algorithms of charge management and thermal control for energy storage systems and mobile devices

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 11/11/2014

Defense Date 11/11/2014

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag algorithms,architectures,charge management,energy storage systems,mobile devices,OAI-PMH Harvest,thermal management,thermal modeling

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Pedram, Massoud (committee chair), Govindan, Ramesh (committee member), Gupta, Sandeep K. (committee member)

Creator Email qing86.xie@gmail.com,xqing@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c3-517731

Unique identifier UC11298277

Identifier etd-XieQing-3081.pdf (filename),usctheses-c3-517731 (legacy record id)

Legacy Identifier etd-XieQing-3081.pdf

Dmrecord 517731

Document Type Dissertation

Format application/pdf (imt)

Rights Xie, Qing

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA