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Photodetector: devices for optical data communication
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Photodetector: devices for optical data communication
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Content
PHOTODETECTOR:
Devices for Optical Data Communication
BY
MIR-ASHKAN SEYEDI
A DISSERTATION PRESENTED TO THE
FACULTY OF THE
UNIVERSITY OF SOUTHERN CALIFORNIA
GRADUATE SCHOOL
IN PARTIAL FULFILLMENT OF THE
REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
IN
ELECTRICAL ENGINEERING
Co-advised by:
John O’Brien
&
P. Daniel Dapkus
Committee:
Anupam Madhukar
Aluizio Prata Jr.
Aiichiro Nakano
May 2015
ii
I wish to dedicate this work to my
parents who migrated with the
sole purpose of a better life for
their children, as enabled by
higher education.
iii
ACKNOWLEDGMENTS
A leap of faith is required by a professor to accept a new student into their research group. Faith
that this student will adopt, embody, and further enhance the academic integrity and technical
ability that has been fostered by generations past. I’d like to first thank Prof. John O’Brien for
having this faith in my abilities and for giving me access to the vast wealth of knowledge that
existed in Micro-Photonics Device Group. His philosophy of “Here’s the lab, go do something
interesting” has always stayed with me throughout the years as I strove to practice science that
was on par with the rich pedigree of work that existed before me. I also have a deep level of
appreciation towards Prof. Dan Dapkus for adopting me into Compound Semiconductors Labs and
allowing me to further enrich my scientific skills by working on cutting-edge problems.
Throughout our many conversations – technical or personal – I have learned many critical lessons
from his long and prestigious career. Thank you to Dr. S. Y. Wang of UC-Santa Cruz and formerly
HP Labs for sponsoring the nanowire detector project and for many fruitful discussion. I also owe
many thanks to Drs. Stephen Farrell, Mahmood Bagheri, Ling Lu, Raymond Sarkissian, Larry
Stewart and Ting-Wei Yeh for the countless hours of help in the cleanroom and labs, teaching me
the very complex steps of device fabrication and testing; collaborations with my CSL colleagues
Yenting Lin, Maoqing Yao, Chunyung Chi and Yoshitake Nakajima were some of the best I have
had. And without the help of Jaime Zelada, Eliza Aceves, Kim Reid, and especially Jenny Lin,
progress on my research would have been very difficult. I also would like to extend my gratitude
to the members of my committee for their time and comments.
As a student at USC and a member of MPDG and CSL, I have been afforded many rare
opportunities to improve and invest in myself. It is my hope that through my scientific work, I will
have left the school and these research groups better than I found them.
iv
TABLE OF CONTENTS
Acknowledgments.......................................................................................................................... iii
List of Figures ............................................................................................................................... vii
List of Tables .................................................................................................................................. x
Abstract .......................................................................................................................................... xi
1 Introduction ............................................................................................................................. 1
1.1 Medium and Long Haul Optical Data Communication ................................................... 1
1.1.1 Current State of Technology ..................................................................................... 1
1.1.2 Optical vs. Electrical Data Links .............................................................................. 2
1.1.3 VCSEL-Based Optical Data Links ........................................................................... 3
1.1.4 Hybrid Silicon and III-V Optical Data Links ........................................................... 4
1.1.5 Photodetectors in Optical Data Links ....................................................................... 5
1.2 On-chip optical data communication ............................................................................. 10
1.2.1 Current State of On-Chip Data Communication ..................................................... 10
1.2.2 Research of Optical Networks-on-Chip .................................................................. 11
1.3 Proposed devices ............................................................................................................ 11
1.3.1 Nanowire Photodetector.......................................................................................... 11
1.3.2 Photonic Crystal Photodetector............................................................................... 13
2 Nanowire Photodetector........................................................................................................ 15
2.1 Nanowire Materials ........................................................................................................ 15
2.1.1 Growth Techniques ................................................................................................. 15
2.2 Nanowire Devices .......................................................................................................... 22
2.2.1 Solar Cells ............................................................................................................... 22
2.2.2 Light Emitting Diodes............................................................................................. 24
2.2.3 Optoelectronic Devices ........................................................................................... 25
2.3 Proposed Device ............................................................................................................. 32
2.3.1 Conceptual Device Design ...................................................................................... 32
2.3.2 Optical Absorption Optimization ............................................................................ 33
2.3.3 Nanowire Surface.................................................................................................... 36
2.3.4 Nanowire Growth.................................................................................................... 41
2.3.5 Polymer Infiltration ................................................................................................. 43
2.3.6 Indium-Tin-Oxide Deposition ................................................................................ 45
v
2.3.7 High-Speed Device Fabrication and Packaging ..................................................... 47
2.4 Experimental setups ....................................................................................................... 49
2.4.1 Responsivity Measurement Experimental Setup .................................................... 49
2.4.2 Bandwidth Measurement Experimental Setup........................................................ 50
2.5 Experimental Results...................................................................................................... 51
2.5.1 Junction Analysis .................................................................................................... 51
2.5.2 Device Current-Voltage .......................................................................................... 54
2.5.3 Responsivity ............................................................................................................ 58
2.5.4 Modulation Bandwidth ........................................................................................... 61
2.6 Future Work ................................................................................................................... 71
2.6.1 Data Modulation ..................................................................................................... 72
2.6.2 Harmonic Generation .............................................................................................. 75
2.6.3 Improved High-Speed Packaging ........................................................................... 77
3 Photonic Crystal Photodetector............................................................................................. 78
3.1 Optical Characteristics of Photonic Crystals .................................................................. 78
3.1.1 Optical Properties of Photonic Crystal Lattices ...................................................... 78
3.1.2 Optical Properties of Photonic Crystal Membranes, Cavities, and Waveguides .... 80
3.2 Photonic Crystal Optical Data Link Components .......................................................... 84
3.2.1 Photonic Crystal Cavity Lasers ............................................................................... 84
3.2.2 Quantum Well Intermixing ..................................................................................... 86
3.2.3 Photonic Crystal Integrated Circuit Components ................................................... 91
3.3 Proposed Device ............................................................................................................. 94
3.3.1 Conceptual Device Integration Scheme .................................................................. 94
3.3.2 Device Design ......................................................................................................... 96
3.4 Processing and Experimental Results .......................................................................... 100
3.4.1 Key Aspects of Device Fabrication ...................................................................... 100
3.4.2 Preliminary Results ............................................................................................... 108
3.5 Future Work ................................................................................................................. 114
3.5.1 Responsivity Measurement ................................................................................... 114
4 References ........................................................................................................................... 117
5 Bibliography ....................................................................................................................... 135
6 Appendix ............................................................................................................................. 155
vi
6.1 Nanowire detector processing details ........................................................................... 155
6.2 Photonic crystal Photodetector processing details ....................................................... 156
vii
LIST OF FIGURES
Figure 1 Performances of reported PD devices of various architecture.[35] .................................. 5
Figure 2 Schematic of a waveguide photodetector design.............................................................. 8
Figure 3 Schematic view of InGaAsP WGPD with external coupling view optical fiber.[39] ...... 8
Figure 4 MBE-grown GaAs nanowires using Au nanoparticle catalysts.[59] .............................. 16
Figure 5 GaAs nanowires grown via Au-catalyst VLS in an MBE system on (1 1 1)B GaAs
substrate.[61] ................................................................................................................................. 17
Figure 6 SEM image of a) MBE grown nanowire array, b) up-close view of autocatalytic GaAs
nanowire. c) top-down view of dielectric mask patterend for SAG.[62]...................................... 18
Figure 7 Schematic of radial P-N junction with surface passivation.[67] .................................... 20
Figure 8 Axial P-i-N junction in nanowire solar cells.[1] ............................................................ 20
Figure 9 NW growth on polycrystalline Si. a) NW growth on islands of poly-Si b) Magnification
showing vertical GaAs NW (false color) c) Cross-sectional view of vertical and tilted NWs.[68]
....................................................................................................................................................... 21
Figure 10 GaAs NW array grown by autocatalysis in an MBE chamber, as patterned by NIL.[69]
....................................................................................................................................................... 22
Figure 11 Schematic and SEM of nanowire positioned between two electrodes and the excitation
spot. SEM image on right show excitation spot (1) and observed output at opposite end (2).[4] 26
Figure 12 Observed excitation wavelength from NW laser. Dotted line represents output with no
applied electric field and blue line is observed output with applied electric field.[4] .................. 26
Figure 13 Observed emission from 3 different nanowire orientations with respect to the
underlying grating.[76] ................................................................................................................. 27
Figure 14 Image of GaN NWs on Si substrate with a) as-grown NWs b) 45° tilt view of NW
array and c) schematic of device.[79] ........................................................................................... 29
Figure 15 Schematic (a,b) and SEM images (c,d) of the CPW nanowire device.[80] ................. 30
Figure 16 Schematic (a) and SEM images (d-b) of NWs intersection from two ends of CPW.[80]
....................................................................................................................................................... 30
Figure 17 Photocurrent response of NWs on CPW from a 1ps wide laser pulse.[80] .................. 31
Figure 18 3D schematic of proposed nanowire photodetector device. ......................................... 32
Figure 19 a) schematic of simulated nanowires and associated dimensions. b) simulated
absorptance of nanowire array at 850 nm.[82] ............................................................................. 35
Figure 20 Absorption of 850 nm light for a square array of GaAs nanowire array infiltrated with
a polymer. ..................................................................................................................................... 36
Figure 21 Nanowire cross section schematic and parameter definitions for simulation.[84] ....... 38
Figure 22 Contour plot showing various cases as a function of a and a p. Different values of
surface state density D it are shown for N=N A=N D with critical core radius and shell thickness
shown for each plot.[84] ............................................................................................................... 39
Figure 23 TRPL signal of a passivated and unpassivated GaAs nanowire.[6] ............................. 41
Figure 24 SEM images of passivated nanowire array post-growth. ............................................. 42
Figure 25 Selective etch of GaAs nanowire versus AlGaAs passivation layer. ........................... 43
Figure 26 3D schematic of reduced-dimension device for RF bandwidth testing. ....................... 48
Figure 27 SEM of a reduced dimension device for high-speed testing. ....................................... 48
viii
Figure 28 Cross section of package schematic showing wirebond to ground plane. ................... 49
Figure 29 Schematic of optical portion for responsivity measurement setup. .............................. 50
Figure 30 Schematic of experimental setup for high-speed bandwidth measurement. ................ 51
Figure 31 Metal-Semiconductor Schottky junction energy diagram.[83] .................................... 52
Figure 32 IPS data showing barrier height of ~0.8 eV. ................................................................ 54
Figure 33 Photocurrent of nanowire detector under various powers of illumination. .................. 55
Figure 34 Plot of Eqn. (2.17) as derived above from experimental device I-V data. ................... 57
Figure 35 Plot of Eqn. (2.19) as derived above from experimental device I-V data. ................... 57
Figure 36 Responsivity at various optical intensities and reverse bias values. ............................ 59
Figure 37 Responsivity of an unpassivated nanowire detector. .................................................... 61
Figure 38 Capacitance area density versus applied reverse bias for a passivated nanowire
detector. ......................................................................................................................................... 62
Figure 39 Simulated and experimental complex reflection impedance of a packaged nanowire
detector for high speed operation. ................................................................................................. 63
Figure 40 Modulation bandwidth at several applied reverse bias values for a fixed optical
intensity. ........................................................................................................................................ 64
Figure 41 3dB modulation bandwidth frequency at various reverse bias values and optical
intensities. ..................................................................................................................................... 65
Figure 42 Small-signal circuit used for transmission and carrier velocity modeling. .................. 67
Figure 43 Extracted average carrier velocity for various applied reverse biases. ........................ 67
Figure 44 Simulated GaAs crystal with and without twin boundaries, where red and yellow
spheres represent Ga and As atoms, respectively.[109] ............................................................... 69
Figure 45 The calculated twin-scattering contribution to electron mobility as functino of
temperature for three lengths of twin segments.[109] .................................................................. 70
Figure 46 TEM image showing twin defect planes in GaAs nanowires....................................... 71
Figure 47 TEM image showing twin defect planes in GaAs nanowires....................................... 71
Figure 48 Typical eye diagram.[112]............................................................................................ 72
Figure 49 Eye diagram of electrical data at 1 GHz. ...................................................................... 73
Figure 50 Eye diagram of data from VCSEL onto a commercial photodetector.......................... 74
Figure 51 Eye diagram of data from VCSEL onto a nanowire photodetector.............................. 75
Figure 52 Harmonics of planar p-i-n photodetector.[101] ............................................................ 76
Figure 53 Harmonic generation for a nanowire photodetector. .................................................... 77
Figure 54 Possible package solution for reduced inductance for device parasitics. ..................... 77
Figure 55 (a) Real space and (b) reciprocal space unit vectors for triangular lattice of holes in a
photonic crystal lattice formation.[113] ........................................................................................ 78
Figure 56 Photonic band diagram of TE z modes for a 2-D triangular photonic crystal lattice.[113]
....................................................................................................................................................... 80
Figure 57 Photonic band structure for a suspended membrane photonic crystal.[113] ................ 81
Figure 58 Schematic of a double heterostructure cavity formed in a photonic crystal lattice.[116]
....................................................................................................................................................... 82
Figure 59 Finite-Element Method band structure calculation of a photonic crystal waveguide.[17]
....................................................................................................................................................... 83
ix
Figure 60 Band diagram of modes and transmission for a photonic crystal defect
waveguide.[114]............................................................................................................................ 84
Figure 61 SEM image of a defect cavity placed a few periods away from a single defect
waveguide in a photonic crystal lattice.[119] ............................................................................... 85
Figure 62 SEM of a photonic crystal double hetero-structure cavity.[120] ................................. 86
Figure 63 Photoluminescence of the Quantum Wells from before and after the intermixing
process.[123] ................................................................................................................................. 88
Figure 64 Quantum well intermixed sample with a double hetero-structure laser cavity for
optically pumped lasers.[123] ....................................................................................................... 89
Figure 65 Light-in Light-Out curve of photonic crystal double hetero-structure cavities with and
without quantum well intermixing.[123] ...................................................................................... 90
Figure 66 Schematic of a double hetero-sctructure cavity laser coupled to a passive intermixed
waveguide.[124]............................................................................................................................ 91
Figure 67 SEM image of an asymmetric MZI in silicon with a photonic crystal lattice.[17] ...... 92
Figure 68 Fourier transform of the optical output of the MZI[17]. .............................................. 92
Figure 69 Schematic of a photonic crystal phase shifter in an asymmetric MZI.[126] ................ 94
Figure 70 Optical eye diagram of a 10 Gb/s data pattern on a photonic crystal-based
modulator.[126] ............................................................................................................................ 94
Figure 71 Top view schematic of an integrated optical circuit in photonic crystal lattice
architecture. ................................................................................................................................... 96
Figure 72 Transmission spectrum for an air-suspended photonic crystal waveguide. ................. 97
Figure 73 Cross section of proposed photonic crystal photodetector device................................ 98
Figure 74 3D schematic of the proposed device with electrical contacts. .................................... 98
Figure 75 Top down schematic showing four boundaries for the p-type diffusion region......... 100
Figure 76 Zn 3P 2 diffusion depth profile for a fixed temperature at given time values.[129] ..... 101
Figure 77 Peak zinc concentration as a function of film thickness for a spin-on dopant
source.[131] ................................................................................................................................ 103
Figure 78 Typical temperature vs. time profile for an RTA process. ......................................... 103
Figure 79 SEM of a diffusion region interface on an InP sample. ............................................. 105
Figure 80 InGaAsP suspended photonic crystal cavity with planar metal contacts. .................. 107
Figure 81 Close view of the input facet of the suspended membrane cavity. ............................ 108
Figure 82 Schematic of c-TLM devices used for extraction of material resistance versus
distance.[138] .............................................................................................................................. 109
Figure 83 SEM image of fabricated c-TLM devices on InP. ...................................................... 109
Figure 84 Resistance versus contact spacing for c-TLM devices on n-type InP. ....................... 110
Figure 85 Resistance versus contact spacing for c-TLM devices on p-type diffused InP .......... 111
Figure 86 Reverse bias current for PN junction in planar III-V material. .................................. 112
Figure 87 Current-Voltage behavior of diode with photonic crystal p-i-n junction. .................. 113
Figure 88 Schematic of a fiber aligned to a photonic crystal defect waveguide. ....................... 115
Figure 89 Schematic of coupling scheme to a photonic crystal cavity.[142] ............................. 115
Figure 90 Transmission loss to photonic crystal cavities of varying lengths.[142].................... 116
x
LIST OF TABLES
Table 1 Summary of various results of Zinc diffusion in InP. .................................................... 102
Table 2 Summary of target and experimental doping concentration for n-type and p-type InP. 111
Table 3 Process parameters for Nanowire Photodetector fabrication. ........................................ 155
Table 4 Diffusion process steps for photonic crystal photodetector. .......................................... 156
xi
ABSTRACT
Nanowire material geometry offers unique advantages as compared to planar semiconductor
geometry due to its large height to diameter aspect ratio and, as a result, has grown popular in
energy conversion[1, 2], lighting[3], and optoelectronic device applications[4, 5]. A variety of
nanowire growth techniques have also emerged with inherent advantages which may be exploited
by various applications. For example, vapor-liquid-solid, a large volume growth technique, has
been used to grow long (> 10 𝜇𝑚 ) , tapered nanowires that are unique for material
characterization[6]. Other popular techniques such as molecular beam epitaxy[7], metal organic
vapor phase epitaxy[8] and metal organic chemical vapor deposition have been widely used for
device applications and material characterization. In the last decade, metal organic chemical vapor
deposition, in conjunction with selective area growth, has been used in Compound Semiconductor
Lab (CSL) at USC as a source of high quality III-V nanowire materials[9] for solar cell[10] and
lighting[11] device applications. In these works, extensive knowledge has been built to yield
appropriate materials of accurate atomic content and crystallographic orientation needed for
various applications. The theses of Drs. Chu[12] and Yeh[13] outline in-depth analyses of InP
nanowire growth and GaN nanowire light emitting diode devices, respectively.
The first part of this thesis extends this nanowire technology and proposes a device for optical data
communication. This device is a GaAs nanowire photodetector for operation at 850 𝑛𝑚
wavelength to be used in conjunction with existing Vertical Cavity Surface Emitting Laser
technology. A Schottky-like junction between Indium-Tin-Oxide and the GaAs nanowires serves
as the photo-collecting junction, which eliminates the need for complicated doping process steps
required to form a PN junction. The key advantage of the nanowire design as compared to planar
xii
Schottky junction GaAs detectors is reduced junction capacitance density enabled by its large
surface to volume ratio. We are also afforded the advantage of being able to engineering the optical
absorption characteristics of nanowire arrays for a given range of incident wavelengths. With a
spatial fill factor on the order of 10 − 15%, these devices can demonstrate bulk-like absorption of
the incoming optical signal[14]. The crucial impact of the reduced fill factor is on the modulation
bandwidth of the detector. By distributing the junction capacitance over a large optical active area,
operation in the tens of Gigahertz range with active area on the order of 50 𝜇𝑚 × 50 𝜇𝑚 is
achievable. Furthermore, a large optical active area maintains a reasonable current signal value
which can reduce the power consumption of subsequent amplification components, such as trans-
impedance amplifiers, that are used in system integration. Finally, a large optical active area can
reduce packaging costs by less strict fiber alignment dimensions.
Section 2.3 outlines the schematic of the device design and the basic working principles of the
junction. Simulations done to optimize the absorption of the nanowires at 850 𝑛𝑚 wavelength as
a function of nanowire pitch and diameter and experimental surface passivation techniques to
reduce surface recombination velocity follow this section. Details of the device fabrication steps
for polymer infiltration of the nanowire array and the Indium-Tin-Oxide (ITO) deposition
technique and characteristics are contained in §2.3.5 and §2.3.6, respectively. The experimental
setups and techniques used to characterize these devices are outlined in §2.4. Key findings for this
device in both its responsivity and modulation bandwidth measurements are outlined in §2.5. For
surface-passivated nanowires of 3 𝜇𝑚 height and optimized pitch and diameter for absorption at
850 𝑛𝑚 , a responsivity of 0.65 𝐴 /𝑊 was demonstrated. This value is 94% of the 0.69 𝐴 /𝑊
theoretical limit of photon absorption in GaAs at 850 𝑛𝑚 . This finding confirms that bulk-like
responsivity can indeed be experimentally achieved in nanowires through proper dimensions and
xiii
surface passivation techniques. Similar devices with reduced active areas were fabricated and
packaged for high-speed operation and demonstrated a 9.2 𝐺𝐻𝑧 3dB modulation bandwidth.
Using this data, a small-signal model of the device is developed and used to extract average carrier
velocity of ~2 × 10
6
𝑐𝑚 /𝑠 . To date, this is the first device-level extraction of carrier velocity in
a nanowire material system. Furthermore, this model implies the bandwidth limit is largely due to
packaging parasitics and not due to an inherent limit of the average carrier velocity in the nanowire
material system. These two key findings of high efficiency responsivity of the nanowire detector
and a large active area with modulation bandwidth in the Gigahertz range serves as building blocks
of possible nanowire device implementation for optical data links.
As computer processor speeds keep up with Moore’s Law, ever smaller process nodes are
developed. However, with the adaptation of the 9 𝑛𝑚 process node, materials are being pushed to
a fundamental limit. To circumvent these limitations, multi-core processors have been developed
to maintain high processing speeds in parallel operation. As a result, electronic data
communication between cores accounts for 50% of the dynamic power consumption[15],
generates significant amount of heat, and suffers from signal latency. Another advantage of smaller
processing nodes in CMOS fabrication facilities is the possibility of large volume fabrication of
optical devices that can be integrated into process flows to replace electrical data links.
The second part of this thesis proposes a device for on-chip optical data communication. In Micro
Photonics Device Group (MPDG) at USC, photonic crystal devices have been explored to serve
as the optical platform for on-chip data communication. In-depth simulations by FDTD techniques
have been used[16] in the group to investigate the optical characteristics of photonic crystal lattices
and cavities. Such devices have also been fabricated in both silicon and III-V material systems in
building both passive and active devices. In building an integrated optical link, passive components
xiv
such as low-loss Y-branches and asymmetric Mach-Zehnder Interferometers[17] have been
simulated and fabricated. Photonic circuits in III-V material systems enable integrated lasers,
which have been demonstrated in the group by optically pumping photonic crystal cavities[18].
To enable low loss propagation of the signal, quantum well intermixing process was
developed[19], whose impacts on the laser were also explored.
The goal of the device proposed in this thesis is to build on these existing component technologies
and to integrate a waveguide photodetector in the photonic crystal platform using a transverse P-
i-N junction formed by an in-house diffusion technique. This device is key in demonstrating a fully
integrated photonic circuit in photonic crystal architecture for adaptation into on-chip optical data
links. Section 3.1 contains the basic working principles of photonic crystal lattices,
waveguides/cavities, and key takeaways from previously developed components and §3.2 outlines
key design aspects of this waveguide photodetector. In §3.3, the proposed device schematic is
outlined for design, integration, and processing steps for junction formation by diffusion. The
formation of a lateral P-i-N junction by diffusion is low damage, cost effective, and compatible
with large volume manufacturing which is important in demonstration of possible device
commercialization. The details of the diffusion theory, processing steps, and characterization of
the doped material are the main findings in this thesis and their experimental results are outlined.
The final section of this chapter discusses the future work in responsivity measurements and
discusses integrated approaches for low-loss coupling schemes to photonic crystal lattices.
1 INTRODUCTION
1.1 MEDIUM AND LONG HAUL OPTICAL DATA COMMUNICATION
1.1.1 Current State of Technology
The optical communication age began in 1988 when a consortium of companies led by AT&T laid
the TAT-8, a pair of fiber optic cables at the bottom of the Atlantic Ocean.[20] The cables carried
40,000 simultaneous calls between USA and Europe at England and France. Data was modulated
at a rate of 295 𝑀𝑏 /𝑠 and repeated every 40 𝑘𝑚 . This defined the so-called Wide Area Network
scheme that dominates the communication between cities and countries. However, we have come
a long way since the days of the TAT-8. Current projects are being planned for trans-Atlantic
cables carrying 4 × 10 𝑇𝑏 /𝑠 between the US and Europe.
In the last decade, we have also seen a tremendous growth of both internet data content and device
connectivity, according to a study by Cisco[21]. This same study claims we are now establishing
the Zettabyte era and by 2017, there will be an average of 2.5 internet connected devices per
individual, globally. These numbers are not surprising as services like Netflix, Hulu, YouTube,
Facebook, etc. are creating more content for which users require immediate, constant connectivity.
However, this only accounts for about 17% of the global internet traffic, according to the same
study. Of the remaining internet traffic, about 13% is between data centers and 75% is within the
same data center, i.e. rack to rack. These statistics highlight the immediate need for increased
bandwidth in the range of several hundred meters to facilitate intra-data center traffic.
To address these high data rate demands, the IEEE set standard speed requirements to be developed
for data links. In 2002, the IEEE 802.3ae defined an Ethernet connection at 10 𝐺𝑏 /𝑠 , achievable
2
with either electrical or optical platforms. However, the electrical connections required high-grade
copper and were limited to distances of 10 − 20 𝑚 , thus were not able to fully serve this
benchmark. The invention of the Vertical Cavity Surface Emitting Laser (VCSEL)[22] opened up
a new realm of possibility for medium (0.1 − 1 𝑘𝑚 ) and long range (0.1 − 1 𝑘𝑚 ) optical
communication by providing a technology platform that could deliver fast data rates (up to several
Gb/s) for relatively cheap power and processing costs. Due to their long range reach, VCSELs
were successfully commercialized to serve this speed benchmark. The next speed standard was
defined in 2008 as the IEEE 802.3 for 100 𝐺𝑏 /𝑠 , implemented on an optical platform with 4
channels of 25 𝐺𝑏 /𝑠 each. To achieve this benchmark, different approaches are used by
companies developing optical links based on both VCSELs and hybrid silicon/III-V integrated
systems. These various approaches offer unique advantages and disadvantages which make them
preferable depending on the applications.
1.1.2 Optical vs. Electrical Data Links
As mentioned in the previous section, high data rates are needed to keep up with the fast growth
of internet traffic. These speeds and distances are difficult to practically attain by electronics and
optics can serve as a viable solution. However, speed is not the only category in which optics must
dominate in order to overtake electronic solutions. As processing node dimensions decrease in
limit, optical devices can be defined on an ever decreasing dimension. This reduces signal latency
and increases bandwidth density. Research done at Cornell outlined the point at which optics
becomes advantageous over electrical interconnects.[23] Their findings show that, with
Wavelength Division Multiplexing, optical links can rival electrical data links as the 22 𝑛𝑚
process node is developed. In this study, they have also assumed a 4 𝜇𝑚 pitch for the optical
waveguides, which is typical for rib waveguide structures. In order to integrate optics successfully,
3
the waveguides will require space-efficient bends, low propagation loss and small footprint. Bends
are on the order of 100’s of square microns[24] for rib structures, making them very inefficient in
usage of space. Another key requirement for optical data links is power consumption. Current data
links are around 5 𝑝𝐽 /𝑏𝑖𝑡 [25] and are targeting < 1 𝑝𝐽 /𝑏𝑖𝑡 for future applications. These links
use at minimum a 5 𝑉 drive voltage for the high-speed electronics and lasers. For the adaptation
of optics to on-chip applications, links would have to use low drive voltages, typically around 1 𝑉
for the high-speed circuitry, as well as lasers and photodetectors.
1.1.3 VCSEL-Based Optical Data Links
For the IEEE 802.3ae standard, VCSELs were the eventual leading platform as they enabled longer
reach than electrical connections. Recently, 10 𝐺𝑏 /𝑠 operation up to 26 𝑘𝑚 of a VCSEL was
demonstrated.[26] This lab demonstration is a basis for many commercial products today such as
what has been commercialized into 4 or 12-channel arrays, able to achieve up to 120 𝐺𝑏 /𝑠
aggregate data rates.[27] VCSEL technology has been the main driving force of optics integration
into high-end server/data center networks as well. IBM has employed this technology in its
supercomputers for the last decade. Their latest implementation is a 24-channel array of VCSELs
and photodetectors that can achieve an aggregate data rate of 450 𝐺𝑏 /𝑠 using a 20 𝐺𝑏 /𝑠
VCSEL.[25] To achieve the IEEE 802.3 benchmark, VCSEL operation was pushed further to
25 𝐺𝑏 /𝑠 per channel[28], and most recently, error free operation at 64 𝐺𝑏 /𝑠 for 100 𝑚 multi-
mode fiber on a single channel VCSEL link was demonstrated.[29] However, the short length of
these links opens up a new area of research for single-mode operation in O-band or C-band, which
enables reach extending into the kilometer range at speeds in excess of 25 𝐺𝑏 /𝑠 .
4
1.1.4 Hybrid Silicon and III-V Optical Data Links
To realize an optical data link in the same material system would simplify processing and make
optical integration a more viable option for companies as costs are reduced. Silicon is the obvious
choice, however lasers in silicon are impractical as they are difficult to fabricate and poor in
performance. Intel’s research group developed a convincing solution with a Raman laser in silicon,
but this solution is not viable for optical links due to high power requirements. For operation at
1.31 𝜇𝑚 wavelength, a typical example is Intel’s approach via a bonded InAlGaAs/InAlAs gain
material evanescently coupled to a silicon waveguide, as developed by research groups at
University of California – Santa Barbara[30]. Another technique aimed at improving yield and
enabling Wavelength Division Multiplexing is a butt-coupled mechanism of an external cavity
InGaAsP laser for operation at 1.55 𝜇𝑚 , as used by Kotura.[31]
External hybrid lasers (bonded or butt-coupled) typically have long gain regions (1 𝑚𝑚 ) and have
low heat dissipation which does not allow for fast direct modulation and thus need an external
modulator for data transmission. One popular approach is the use of a Mach-Zehnder
interferometer in a silicon rib waveguide architecture. This approach is not space efficient, but
offers an advantage of being compatible with existing CMOS technology and is the approach
favored by companies such as Intel. They were able to demonstrate 25 𝐺𝑏 /𝑠 operation per channel
with a hybrid bonded III-V laser.[32] Modulators based on ring device architecture have been also
used in silicon and shown single channel data rates of 10 𝐺𝑏 /𝑠 by Luxtera [33] and 25 𝐺𝑏 /𝑠 by
Oracle[34]. Ring modulators require smaller footprint, but have higher temperature sensitivity,
thus requiring temperature control circuitry. Modulators based on absorption band edge are also
favored due to their short lengths, as used by Kotura and Infinera. However, this approach
increases cost due to further integration of non-silicon based materials.
5
1.1.5 Photodetectors in Optical Data Links
The previous section outlined the necessary components for on-chip data communication such as
lasers and modulators. These components make up the transmission modules often used in optical
data link systems. The key component of the receiving module is the photodetector, responsible
for converting optical signals into electrical signals. This section will outline various photodetector
designs and describe their advantages based upon their applications. The two key parameters of
distinction for a photodetector are its responsivity (efficiency) and modulation bandwidth. These
two parameters are often combined in the so-called bandwidth-efficiency product, used to make
direct comparison between photodetectors of different architectures and material composition.
Many device architectures exist for on-chip photodetectors (PD) such as vertically-illuminated
photodetectors (VPD), traveling-wave photodetectors (TWPD), waveguide photodetectors
(WGPD), resonant-cavity enhanced photodetectors (RCE-PD), refracting-facet photodetectors
(RFPD), and avalanche photodiodes (APD). Figure 1 describes typical values of efficiency and
bandwidth values for these device designs.
Figure 1 Performances of reported PD devices of various architecture.[35]
6
The 3𝑑𝐵 electrical bandwidth limited by carrier transit time for an absorption region thickness 𝐷
can be defined by an empirical equation[36] such that
𝑓 𝑡 ≅
3.5𝑣 𝑎𝑣𝑔 2𝜋𝑑
⁄
(1.1)
where 𝑣 𝑎𝑣𝑔 is an average of both electron and hole saturation velocities. For example, if we assume
𝑣 𝑎𝑣𝑔 ~5 × 10
6
𝑐𝑚 /𝑠 for a GaAs material system and 𝑑 ~0.1 𝜇𝑚 , the 3dB bandwidth is
𝑓 𝑡 ~300 𝐺𝐻𝑧 . For optical signals coupled to a photodetector such as VPDs, the light is subject to
reflection and travels with an exponential decay, the internal efficiency can be expressed as[35]
𝜂 𝑖𝑛𝑡 = (1 + 𝑟 𝑒 −𝛼𝑑
)(1 − 𝑒 −𝛼𝑑
) ≈ (1 + 𝑟 )𝛼 (1.2)
where 𝑟 , 𝛼 and 𝑑 are reflection due to the top transparent electrode, absorption coefficient of the
material and the absorption region thickness, respectively. The first term in the above equation is
due to the double-pass scheme, where efficiency is attempted to be improved by reflection of the
incident light by the rear electrode. Here, the optical absorption in the transparent electrode is
ignored. By combining Eqns. (1.1) and (1.2), we can state the bandwidth-efficiency product as
𝑓 𝑡 ∙ 𝜂 𝑖𝑛𝑡 ≅
3.5𝑣 𝑎𝑣𝑔 (1 + 𝑟 )𝛼 2𝜋
(1.3)
From the above equation, for a GaAs material system, and a reflection coefficient between 0-1,
the bandwidth-efficiency product is in the rage of 30 − 60 𝐺𝐻𝑧 for 850 𝑛𝑚 incident wavelength.
These equations can then be used to estimate limits for other material compositions for various
wavelengths.
Vertically illuminated detectors have been under investigation for more than twenty years [37] and
offer advantages for use with VCSELs given relatively low-cost multi-mode fiber alignment with
7
active areas on the order of tens of microns. These devices are often designed with absorption
region thicknesses in the range of 0.1 − 0.3 𝜇𝑚 to facilitate operations in the several tens of
Gigahertz [35], as this minimizes carrier transit times. However, such short absorption regions
limit the amount of signal, even with high responsivity, which increases power requirements for
any subsequent amplification of the signal by on-chip Trans-Impedance Amplifiers (TIA). State
of the art planar detectors used in the aforementioned VCSEL links use active areas with 15 −
20 𝜇𝑚 diameter for operation up to 28 𝐺𝑏 /𝑠 .[38] As data rates increase, the active area must
decrease to reduce device parasitics due to junction capacitance, which will further increase device
costs due to more stringent fiber alignment dimensions.
A key restriction of VPDs is that carriers are generated in the same direction of collection of the
photo-generated carriers. Therefore, to have large responsivity, longer absorption material is
needed, limiting bandwidth due to increased transit time, as shown previously. A solution to this
approach is to decouple absorption and collection by incorporating a waveguide in the detector
design, as in the case of a WGPD. This design comprises of a free-space optical beam focused
onto an input facet of a semiconductor material with a waveguide inside that is formed by index
contrast of the surrounding materials. This waveguide region serves as the active region of a
photodetector junction and the direction of optical propagation is perpendicular to the internal
electric field, thus decoupling the carrier generation and extraction direction. This design is shown
schematically in Figure 2.
8
Figure 2 Schematic of a waveguide photodetector design.
The orthogonal orientation of the optical and intern electric field can serve to greatly improve the
bandwidth-efficiency factor. However, a main drawback of this design is the efficient coupling of
light into the waveguide cavity due to poor spatial overlap of the optical mode and waveguide
core. Another limiting factor for WGPD designs is their RC parasitics as determined by the device
geometry due to capacitance of the contacts due to their length and resistance of the cladding
materials. In an InGaAs WGPD, for example, a 100 𝐺𝐻𝑧 bandwidth would require 0.3 𝜇𝑚 core
thickness, resulting in ~30 𝑓𝐹 capacitance for this WGPD design. The material resistance for such
a device is ~40 Ω. When used with a 50 Ω system for high speed modulation, the overall
resistance is 90 Ω and the bandwidth is thus limited to 60 𝐺𝐻𝑧 .[39] This device is shown
schematically in Figure 3, where it is important to note the dimension of the waveguide cavity of
4 𝜇𝑚 width and 12 𝜇𝑚 length. From these values, we can see these compact devices enable high
bandwidth with reasonable efficiency.
Figure 3 Schematic view of InGaAsP WGPD with external coupling view optical fiber.[39]
9
The transmission line characteristics of WGPDs is treated like a lumped element model comprised
of RLC components. As the optical signal propagates down the length of the WGPD, the
microwave electrical signal generated in the contacts will move at a velocity determined by the
characteristic impedance of the transmission line. These are defined as
𝑉 𝑒 =
1
√ 𝐿𝐶
, 𝑍 0
= √
𝐿 𝐶 ⁄ (1.4)
where the inductance and capacitance are given in terms of per unit length. This velocity is slower
than the optical group velocity and thus causes a phase mismatch between the two signals, leading
to signal degradation. Also, there will be electronic signal reflections in the transmission line that
will further degrade the signal. One solution then is the distributed photodetector design often
called TWPD where photo-absorption occurs in many diodes along the optical path length. This
design was initially proposed in 1990[40], followed by a successful demonstration in 1991[41].
The key advantage of TWPD as compared to WGPD design is that by distribution of the photo-
absorption regions, the bandwidth-efficiency of the device is independent of the overall length.
For example, for operation at 830 𝑛𝑚 , a TWPD with dimension of 1 𝜇𝑚 wide, 7 𝜇𝑚 long GaAs
with a P-i-N junction achieved 172 𝐺𝐻𝑧 bandwidth with 40 % efficiency.[42] By comparison, a
TWPD designed in InGaAsP with a length of 1 𝑚𝑚 achieved a 40 𝐺𝐻𝑧 bandwidth[43], showing
that a properly designed transmission line can overcome RC limitations and maximize absorption
by enabling long cavity lengths.
10
1.2 ON-CHIP OPTICAL DATA COMMUNICATION
1.2.1 Current State of On-Chip Data Communication
During the last 40 years, Moore’s Law has been very successful in determining the number of
integrated transistors on a chip as fabrication capabilities and tools have improved dramatically.
These fabrication tools, combined with advanced circuit designs, have improved microprocessor
speeds to levels that were never initially imagined. However, as fabrication processes reach a
fundamental physical limit, other techniques have been used to stay ahead of performance
demands. One such technique is the use of multiple processor cores in parallel to divide the work
of a single processor chip, as done previously. This development was driven largely in part due to
the power dissipation limits for a single processor. Multi-core processors optimize power
dissipation by operation in parallel rather than serially, usually at lower clock speeds. As the
number of cores per chip increases, this places a critical challenge on the efficiency, latency and
power usage of interconnects between various microprocessors on-chip. Traditional copper
electrical connections suffer from heating, latency, and significantly increase the overall power
dissipation of the processor chip. It is due to these reasons that integrated optics on to processor
chips can provide a solution to this challenge. The inter-core communication network on a
processor chip is often referred to as network-on-chip (NoC).
In order for optical devices to replace traditional copper wiring in NoCs, they must be compact,
able to achieve low power consumption, and be placed in close proximity to electrical drivers on
the processor chip. Another advantage to optical interconnects is that they are relatively immune
to electromagnetic interferences and offer high bandwidth throughput for a unit area on the chip.
Thus far, electrically enabled NoCs have been able to serve most interconnect needs, however they
account for 50% of the dynamic power in some high-performance chips.[15] Some companies are
11
investing in the adaptation of an optical NoC, as used by Xilinx, in their Virtex-7 FPGA module.
This module uses an off-chip, fiber-coupled laser to excite an on-chip optical modulator. This
modulator then is driven by the FPGA, and the optical signal is taken off-chip via another fiber.
From nascent examples such as this, it is clear that in the future, optics will be able to serve as a
viable solution to relieve the power requirements of today’s electrical on-chip interconnects.
1.2.2 Research of Optical Networks-on-Chip
As mentioned before, optical circuits have been demonstrated to achieve modulation response in
the few Gigahertz range with dimensions that would make them a competitive choice for optical
interconnects for on-chip applications.[44] However, these are silicon based devices and suffer the
same drawbacks as the long-reach optical data links of not having a native laser. Other approaches
have shown integrated lasers onto silicon passive components with a small footprint, but are also
nascent in their application.[45] Research groups have shown an integrated laser diode onto
passive silicon waveguides with SiGe traveling-wave photodetectors.[46, 47] These devices show
operation at 12.5 𝐺𝑏𝑠 with low bit error rates. These works highlight some of the latest research
efforts in improving on-chip optical data interconnects. However, the costs associated with
alignment of external lasers, large area required by traditional silicon rib waveguides, and the need
of SiGe for the photodetector serve as obstacles for easy adaptation of this technology into existing
processors chip designs
1.3 PROPOSED DEVICES
1.3.1 Nanowire Photodetector
The growth of semiconductor materials like GaAs or InP in arrayed nanowires via techniques such
as metal organic chemical vapor deposition (MOCVD) using patterned selective area growth [9,
12
48] offers an opportunity to investigate new classes of devices that exploit the unique properties
of nanowires. In device applications based on optical absorption, this material geometry offers
unique advantages and challenges as compared to planar geometry due to its large surface area to
volume ratio. As mentioned previously, optical data links based on VCSELs play an important
role in the communication infrastructure. Vertically illuminated photodetectors used in
conjunction with VCSELs operating at 25 𝐺𝑏 /𝑠 are limited in their bandwidth and signal value by
the active area diameter, typically 15 − 20 𝜇𝑚 , and absorption thickness, typically 0.1 −
0.3 𝜇𝑚 .[35, 38] Interlaced contacts are also often used to eliminate parasitic effects at the expense
of reduced responsivity [49]. Furthermore, as aggregate channel numbers grow,[28] accurate
alignment of fibers to the small active area also increases packaging costs.
The first proposed device in this thesis builds on the existing knowledge of nanowire materials
growth and device fabrication in Compound Semiconductor Labs. The device is based on a
periodic array of ordered GaAs nanowires as enabled by large area electron-beam lithography
(EBL) and selective area growth (SAG) by MOCVD. Optical absorption for the solar spectrum
was simulated and optimized for nanowire solar cell devices in the past.[14] These simulations
were repeated to optimize optical absorption at 850 𝑛𝑚 for this device specifically as a means to
determine optimal physical dimensions of nanowires. Furthermore, in-situ surface passivation
during MOCVD growth was also carried out to decrease surface recombination effects. The photo-
collecting junction of this device is a Schottky-like junction between ITO and the GaAs nanowire,
eliminating the need for complex doping steps for the formation of a PN junction. Section 2.3
outlines the details of the device design.
This device then exploits the low spatial fill factor of the nanowire geometry to both maintain
responsivity similar to that of bulk GaAs, while having a reduced junction capacitance. This
13
enables operation in the Gigahertz range and serves as a platform to circumvent issues currently
faced by conventional planar GaAs photodetectors in their parasitic limitations, overall signal
level, and packaging costs. Experimentation techniques and results are presented in §2.4 and §2.5,
respectively.
1.3.2 Photonic Crystal Photodetector
Given the system requirements of space on the wafer and power usage discussed in §1.2, devices
based in photonic crystals offer a very viable solution, especially due to their high device packing
density. Photonic crystal waveguides with a pitch of 1 𝜇𝑚 showed less than −30𝑑𝐵 optical cross-
talk.[50] Bends have also been demonstrated using this architecture with ~0.1𝑑𝐵 optical loss and
have a footprint of less than 20 𝜇𝑚
2
.[51] Active components such as a laser have also been
fabricated. By forming a two dimensional photonic crystal lattice on a III-V membrane,
electrically-injected lasers with less than 300 𝑛𝐴 threshold current were experimentally
demonstrated.[52]
The device proposed in this thesis for on-chip optical data communication is an extension of the
work done in Micro Photonics Device Group in building an integrated photonic circuit in a
photonic crystal platform. As mentioned, Y-branches and asymmetric Mach-Zehnder
Interferometer (MZI) components were simulated and experimentally measured in the group.[17]
Furthermore, optically pumped lasers in photonic crystal cavities with intermixed transparent
waveguides were also demonstrated.[19] The device for this thesis proposes the formation of a
lateral P-i-N junction by solvent diffusion techniques and uses a waveguide photodetector device
architecture all in the photonic crystal platform. This geometry is suitable for on-chip optical data
communication as it does not require external optical coupling to the detector, and the waveguide
photodetector design allows for optimal design for both responsivity and bandwidth.
14
To set the stage for this technology, on-chip optical data components and their key principles were
discussed in §1.1.5. A brief introduction to photonic crystal lattices, cavities, waveguides and
photonic circuit components previously developed in the group are given in §3.1. The proposed
device is to be integrated with an optically pumped photonic crystal cavity laser with an
intermixed, transparent waveguide used to direct the light. In §3.3, the proposed device is
discussed in detail of dimensions, the optical bandwidth as defined by intermixing for transparent
waveguides, the details of the III-V material, lattice design and junction formation by diffusion.
This chapter concludes with experimental results on the doping levels of the p-type and n-type
material, preliminary device data of the PN junction, and projected future work on characterization
of the photonic crystal detector.
15
2 NANOWIRE PHOTODETECTOR
2.1 NANOWIRE MATERIALS
2.1.1 Growth Techniques
The field of nanowire growth has evolved into very complex and highly customizable techniques
that are advantageous depending on the experiments and device applications. One of the older
growth approaches of vapor-liquid-solid (VLS), initially proposed in 1964[53], has been
investigated in academic research due to its fast growth rates and potential large volume
throughput. Crystal growth by gas phase adsorption is typically slow, 200 − 300 𝑛𝑚 /ℎ𝑟 .
However, in VLS growth, this process rate is enhanced by using a catalyst that forms a liquid at
the catalyst-semiconductor interface. The catalyst is a metallic nanoparticle, typically gold, with
diameter on the order of a few hundred nanometers and is dispersed or patterned on the substrate
by various techniques. During growth, the temperature is just above the eutectic temperature to
form the liquid alloy, enhancing the adsorption rate of the vapor source material by maintaining
supersaturation for the metal alloy. Therefore, if cost effective approaches of nanoparticle
formation can be developed, VLS can be a possible approach to deliver large volume arrays of
uniform nanowires.
The nanoparticles can be defined by electron beam lithography (EBL)[54], which is slow and
therefore costly for large volume fabrication. Other approaches of nanoparticle patterning include
soft-photolithography[55], mask lithography[56], and nanoparticle self-assembly[57]. The latter
approach of self-assembly has been shown to yield large area nanowires, however growth direction
and heights are not uniform. In another work, also based on self-assembly[58], vertically aligned
16
ZnO nanowire arrays on a GaN substrate are experimentally shown. In this work, the truly vertical
and uniform in height nanowires are attributed to the similar bandgap of GaN and ZnO, wurtzite
crystal symmetry, and a small lattice constant mismatch. These concerns highlight some of the
factors that directly impact nanowire growth.
The enhanced growth rate of VLS can lead to impurity incorporation into the nanowires. A main
source of this impurity comes from the catalyst particle, which introduces impurities at the
catalyst/semiconductor interface. A high-purity nanowire growth technique has been developed in
molecular beam epitaxy (MBE) systems, since such systems can achieve ultra-high vacuum levels
on the order of 10
-8
Pa and does not need a catalyst particle. It is possible to use the catalyst
approach of VLS in an MBE chamber[59] where high-purity wurtzite GaAs nanowires have been
grown. In this work, a (100) crystal orientation Si substrate is patterned with Au nanoparticles and
GaAs nanowires grown in the <111> preferential direction, as shown in Figure 4.
Figure 4 MBE-grown GaAs nanowires using Au nanoparticle catalysts.[59]
Due to the kinetics of crystal growth, nanowires grow in the direction of minimum free energy,
which is largely determined by the surface energy between the metal catalyst and the underlying
semiconductor. In a review of various growth conditions, substrates and substrate orientations[60],
17
it has been summarized that for diamond and zinc-blend crystals, the catalyst-semiconductor
interface forms a lowest energy surface in the (111) plane, thus leading to growth in the <1 1 1>
direction. The same study also reports other low index growth directions for specific growth
conditions and substrates. One such study is the growth of wurtzite GaAs nanowires by Au-catalyst
VLS growth mechanism in an MBE system[61]. The substrate used is GaAs in the (111)B
direction, which yields vertical nanowires, as shown in Figure 5. These nanowires can be seen to
have a tapered shape, which is characteristic of VLS growth mechanism. This shape has an
important implication of materials analysis and will be discussed in subsequent sections.
Figure 5 GaAs nanowires grown via Au-catalyst VLS in an MBE system on (1 1 1)B GaAs substrate.[61]
18
It can also be noted from Figure 5 that the nanowires are not very uniform in spacing or orientation.
One approach to ensure a more uniform array is by selective area growth (SAG). This technique
creates regions of preferential growth by a patterned dielectric mask. A thin (10 − 20 𝑛𝑚 ) layer
of a dielectric mask, typically SiN or another similar dielectric material, is deposited on the
substrate. This dielectric layer is then patterned by such techniques as EBL, photolithography, or
soft-lithography, to open regions of desired nanowire growth. High-resolution lithography such as
EBL allows for openings on the order of 80 − 100 𝑛𝑚 with pitch spacing of similar order of
distance.
Growth of nanowires with SAG in MBE has also been demonstrated.[62] In this work, a SiO 2
mask is patterned by EBL on a (111) Si substrate. Growth of GaAs nanowires was investigated as
a function of opening diameter, 40 − 120 𝑛𝑚 , and pitch, 0.25 − 3 𝜇𝑚 . Figure 6 shows the
nanowire growth and mask opening from this work.
Figure 6 SEM image of a) MBE grown nanowire array, b) up-close view of autocatalytic GaAs nanowire. c) top-down view of
dielectric mask patterend for SAG.[62]
MBE growth of nanowires with SAG relies on self-catalyzed mechanisms of growth, and in the
case of GaAs, the growth is initiated by the autocatalytic Ga droplet formed in the mask
opening.[63] A key conclusion of this work is that the nanowire diameter is independent of mask
19
opening, which confirms the autocatalytic growth mechanism in MBE. It is summarized in this
work that the diameter depends on the Ga droplet condensation and the As/Ga flux ratio. This is
in contrast to non-catalytic GaAs where mask opening strongly determines final diameter.
The nanowires proposed for this thesis are grown by metalorganic chemical vapor deposition
(MOCVD) using SAG. MOCVD is a non-catalytic growth technique, and as previously
mentioned, relies strongly on the mask opening and pitch to ensure uniform nanowires. The
elimination of a metal catalyst also reduces impurities introduced to the nanowire from the metal-
semiconductor interface and leaves the nanowire tips exposed, which can be contacted for device
fabrication. The approach of MOCVD growth, initially developed at Rockwell by Manasevit[64],
involves pyrolysis reaction of vapors of a volatile organometallic and a gaseous hydride.[65] For
the growth of GaAs materials, (CH 3) 3Ga and AsH 3 precursor are used. The carrier gases are used
to transport the compounds of interest, Ga or As, to the reaction chamber where elevated
temperatures cause chemical reactions at the wafer. Crystal growth occurs by chemical reaction
and is different than MBE, for example, where crystal growth happens by physical deposition of
atomic layers.
MOCVD growth of nanowires has been an active area of research for device fabrication. Catalyst-
free growth of GaAs nanowires using SAG with diameters down to 50 𝑛𝑚 has been
experimentally demonstrated.[66] Given the accurate control over material composition and
growth direction of MOCVD, unique junctions have been formed in nanowire materials for device
applications as well. An example is the formation of a PN junction in a shell/core radial junction,
as shown in Figure 7.[67] In this schematic, a passivation layer of InGaP has also been used to
reduce surface recombination velocity to improve device efficiency.
20
Figure 7 Schematic of radial P-N junction with surface passivation.[67]
Another junction type is an axial P-i-N junction, shown schematically in Figure 8.[1] In this device
geometry, a short intrinsic region is used to improve the device efficiency. From this schematic, a
typical approach at device fabrication can also be seen where a polymer has infiltrated the
nanowire array and a transparent conductive material such as ITO is used to form contacts to the
tips of the nanowires.
Figure 8 Axial P-i-N junction in nanowire solar cells.[1]
To move towards the goal of cost-effective and scalable manufacturability of nanowires, several
approaches have been pursued in literature. One approach is the use of polycrystalline Si on an
21
amorphous substrate.[68] This technique relies on metal-induced crystallization of Si when put in
contact with a metal layer. Wafers used were (001) Si, covered with a thin thermal oxide layer.
Using magnetron sputtering, thin layers of Al and Si were deposited, anneal, and the upper Al
layer was selectively etched. After anneal, XRD measurements showed no presence of Al atoms.
After substrate preparation, the GaAs nanowires were grown by the previously mentioned
technique of self-catalyzed VLS in an MBE chamber. Figure 9 shows SEM images of the
nanowires.
Figure 9 NW growth on polycrystalline Si. a) NW growth on islands of poly-Si b) Magnification showing vertical GaAs NW (false
color) c) Cross-sectional view of vertical and tilted NWs.[68]
This approach, though scalable, does not render uniform arrays of nanowires. An inexpensive
method of defining growth regions in an oxide, as mentioned, is nanoimprint lithography (NIL).
This approach has been undertaken in a study which also uses autocatalysis in MBE.[69] This
process begins with a 2 inch (111) Si wafer covered with a thermal oxide. NIL and wet etching are
used to transfer a hole pattern of 75 𝑛𝑚 diameter and 1 𝜇𝑚 pitch into the thermal oxide.
22
Subsequently, these wafers are loaded into an MBE chamber for nanowire growth. This technique
renders a uniform array of nanowires, shown in Figure 10, with a low cost, high throughput
approach.
Figure 10 GaAs NW array grown by autocatalysis in an MBE chamber, as patterned by NIL.[69]
The growth of uniform arrays of GaAs nanowires with SAG by MOCVD on a silicon substrate
has also been investigated by other groups, with similar results as reported above.[70] At USC,
Maoqing Yao and Chun Yung Chi were able to experimentally demonstrate GaAs nanowires on a
Si substrate. This was done as a building block to successfully demonstrate a tandem junction solar
cell for increased efficiency. At the time of this writing, this work is unpublished.
2.2 NANOWIRE DEVICES
2.2.1 Solar Cells
As mentioned previously, a major focus of research for nanowire devices is the area of solar cells.
This is motivated by the possibility of improving device efficiency by the optical absorption
enhancement due to the nanowire geometry. To achieve this, nanowire solar cell devices are under
investigation in various material systems and junction designs. Nanowire PN junctions are
23
typically either a radial junction where the core is doped with the opposite species than the
surrounding shell, or an axial junction where one portion of the nanowire is grown p-type and
another is n-type, along the height. Theoretical studies predicted that axial junctions are more
sensitive to surface states but can provide larger open circuit voltages and are easier to customize
for junction structure dimensions and thus lend themselves well to integration with a multi-junction
solar cell.[71]
A nanowire solar cell based on a radial junction, schematically shown in Figure 7, was able to
achieve 6.63 % efficiency. This device also features a surface passivation layer, the effects of
which will be discussed in subsequent section. An example is of an axial P-i-N junction is a solar
cell with InP nanowires[72], grown on an InP substrate by Au-catalyzed MBE technique. To form
a contact to the nanowires, a conformal coating of a transparent conducting oxide is used. In order
to prevent shorts to the base region of the nanowire, a dielectric coating is used for the nanowires.
Simulations were carried out to optimize nanowire diameter and pitch, resulting in 13.8 %
efficiency for these devices. In the CSL group, GaAs nanowires with axial P-N junctions have also
been experimentally demonstrated and used for solar cell devices.[1] These nanowires, grown by
MOCVD with SAG, however, differ from the previous example in contact formation. These
nanowire arrays were infiltrated by a transparent, non-conduction polymer, which planarized the
sample, exposing only the nanowire tips. This study finds that a shallow junction is crucial for
good device performance, resulting in 7.8 % efficiency. To make a tandem solar cell, a Si substrate
with a planar PN junction as the growth platform for GaAs nanowires can be used. This device
can have improved efficiency compared to the single junction nanowire device due to the different
absorption regions of the two material systems. This is a presently active research area for
nanowire solar cells.
24
2.2.2 Light Emitting Diodes
Light emitting diodes (LEDs) in the visible range can be made from compounds such as
InGaN/GaN, grown by the aforementioned techniques. Conventional planar visible LEDs with
InGaN quantum wells suffer from a reduced output efficiency above a threshold input current bias;
a phenomenon referred to as efficiency droop. There are many theoretical propositions for the
source of this droop such as the presence of piezo-electric fields in the polar planes of GaN, Auger
recombination, and current leakage outside the quantum wells. A review paper by Piprek[73]
outlines these effects thoroughly and is a recommended introductory paper to the field of efficiency
droop research. To build up on these proposed sources of droop, research done at USC by Dr.
Sarkissian also suggests that photon quenching in the III-V material can also be accountable for
contributing to droop.[74] This work provides experimental evidence of photon quenching and
from it develops an equilibrium rate equation model, showing that photon quenching can be
difficult to distinguish from Auger recombination as it has similar magnitude and carrier density
dependence.
As a means to investigate the effects of efficiency droop due to the piezo-electric fields, devices
with quantum wells on both the polar and non-plar (c-plane and m-plane, respectively) can be
fabricated and tested. However, non-polar GaN substrates are both small and very expensive. A
cost-effective approach to access non-polar planes on a polar GaN substrate is by MOCVD of
nanostructures by SAG. Such work has been done at USC[3], where vertical GaN nanorods were
grown on c-plane GaN substrates, exposing the m-planes on their sidewalls. Due to the control
afforded by MOCVD growth, InGaN quantum wells were then grown on the sidewalls, allowing
for preferential injection into the m-plane. LEDs designed in this fashion have been published[7],
and are the subject of research in CSL.
25
Extraction efficiency of photons also contributes to the overall device efficiency of LEDs. Much
like optical absorption can be enhanced by proper dimensions of a nanowire array, so too could
light extraction. Finite-difference time-domain simulations done at USC[75] study both the light
extraction and far field emissions of a square GaN nanorod array by variations in its height,
diameter and pitch. For a narrow optical bandwidth in the visible range, the overall brightness of
nanorod LEDs was found to be enhanced by a factor of ~10 for optimized array dimensions.
2.2.3 Optoelectronic Devices
Nanowire devices are also being investigated for optoelectronic devices applications such as single
frequency light sources, waveguides, and modulators. One example of an optically pumped
nanowire laser with an electro-optic modulator is work done at Harvard[4] where a single CdS
nanowire is isolated for experimentation. These nanowires are grown via MOCVD and have 100
nm diameter and are 10 𝜇𝑚 long. To demonstrate waveguide and modulation properties, this
nanowire was positioned vertically between two electrodes with one end of the nanowire excited
by an optical source with a ~5 𝜇𝑚 spot size at the band-edge wavelength, done at 4.2 𝐾 . This
arrangement is shown in Figure 11. The output, observed at the opposite facet of the nanowire, is
shown in Figure 12. The observed peak at 489 𝑛𝑚 is associated with the exciton line and the
514 𝑛𝑚 feature is from the free electron-bound hole population. The modulation here is attributed
to absorption modulation of the nanowire itself, with the physical process being similar to the
Franz-Keldysh absorption mechanism.
26
Figure 11 Schematic and SEM of nanowire positioned between two electrodes and the excitation spot. SEM image on right show
excitation spot (1) and observed output at opposite end (2).[4]
Figure 12 Observed excitation wavelength from NW laser. Dotted line represents output with no applied electric field and blue
line is observed output with applied electric field.[4]
An inherent difficulty faced by nanowire lasers is the challenge of modal control due to their sub-
wavelength dimension. One proposed solution is the integration of single nanowires on top of a
grating, as a means to externally control the emitted wavelength.[76] A 5 𝜇𝑚 planar layer of GaN
was grown by MOCVD and nanowires were etched by a top-down technique using Inductively-
Coupled Plasma (ICP) dry etch and a KOH wet etch, with a final diameter of ~200 𝑛𝑚 . The
grating was fabricated into a 200 𝑛𝑚 thick layer of SiN on a Si substrate with a 90 𝑛𝑚 period and
50 % duty cycle. The nanowires were isolated and carefully positioned by micro-manipulation in
an SEM chamber and oriented at 0°, 45°, and 90° with respect to the grating to vary the effect of
the grating from maximum to minimum, respectively. The nanowires were optically pumped by a
Nd:YAG laser with the output observed in-plane, from the sides of the nanowires. Output spectra
27
and associated orientations are shown in Figure 13. The modes of these nanowires were simulated
for both air suspended and on substrate with the effects of the grating taken into account.
According to these simulations, an emission peak of 369 𝑛𝑚 is expected. The 0° orientation shows
a strong emission near this wavelength with the maximum modal side suppression ratio, indicating
that a lasing line within the gain spectrum can be controlled by external techniques.
Figure 13 Observed emission from 3 different nanowire orientations with respect to the underlying grating.[76]
28
Photodetectors (PDs) based on nanowires have also been investigated, motivated by similar
reasons as for solar cell research. Furthermore, integration with low cost substrates is a desirable
feature for possible commercialization. Various combinations of materials for both the nanowires
and substrates have been investigated for this application. For example, by using catalyst-free
MOCVD growth techniques, n-type InAs NWs were grown on a Si substrate to serve as material
for both photodiode and photovoltaic device applications.[77] Silicon nanowires were grown by
using Au nanoparticles uniformly arrayed on a Si substrate, where these nanowires were grown
vertically by Plasma-Enhanced Chemical Vapor Deposition (PECVD), which is a similar growth
mechanism to VLS.[78] This array was then infiltrated by a polymer and nanowire tips were
contacted by a transparent electrode, demonstrating a Schottky-like junction. However, junction
analysis is complicated due to the presence of the Au nanoparticle at the nanowire tips. As
mentioned in 2.1.1, autocatalysis in an MBE chamber can leave the nanowire tips exposed for
electrical contact formation. This technique was used to grow GaN nanowires with an axial P-i-N
junction on a Si substrate.[79] This array was then infiltrated and contacted by Au/Ti/ITO and
tested for photodetection for Ultra-Violet wavelengths. Figure 14 shows a schematic and SEM
image of this device.
29
Figure 14 Image of GaN NWs on Si substrate with a) as-grown NWs b) 45° tilt view of NW array and c) schematic of device.[79]
These devices show promising integration of III-V onto Si substrates, as well as fabrication
procedures for devices that can take advantage of the optical absorption enhancements of nanowire
geometry. They also demonstrate photodetection for the DC regime within their intended optical
bandwidths. However, for PDs to be used in optoelectronics applications, characterization of their
modulation bandwidth must be also taken into account. In a recent work[80], nanowires were
grown on a coplanar waveguide (CPW) designed for high-speed operation. Using PECVD, an n-
type region of Si was grown on the metal CPW to serve as the anode of the junction, as well as the
region for nanowire growth. A suspension of Au nanoparticles coated the sample and
30
subsequently, InP nanowires were grown by low pressure MOCVD. The nanowires grew in
random orientation, but due to the close proximity of the CPW ends, a region of nanowires grew
together, forming an electrically continuous nanowire. This device is schematically shown in
Figure 15. A closer view of the regions of intersection of the nanowires forming a connection is
shown in Figure 16.
Figure 15 Schematic (a,b) and SEM images (c,d) of the CPW nanowire device.[80]
Figure 16 Schematic (a) and SEM images (d-b) of NWs intersection from two ends of CPW.[80]
31
To carry out high-speed photodetector measurements, a pulsed 780 𝑛𝑚 mode locked laser with a
pulse width of 1 𝑝𝑠 was coupled to the active region using a single-mode lensed fiber. The active
area of the device is 10 𝜇𝑚 long and 2 𝜇𝑚 wide, and the fiber was aligned by a translational stage.
Figure 17 shows the measured high-speed photocurrent from the above device, in response to a
1 𝑝𝑠 pulse with applied reverse bias of 1 𝑉 , as measured from a 40 𝐺𝐻𝑧 oscilloscope. The full-
width half maximum (FWHM) of 18 𝑝𝑠 is a result of the laser pulse width and oscilloscope
response, resulting in a 14 𝑝𝑠 FWHM contributed by the device itself. This experiment shows that
with a properly designed high-speed package, modulation in the several tens of Gigahertz range is
possible. However, a drawback of this technique is the random orientation of the nanowires,
eliminating the key advantage of optical absorption enhancement due to the periodic geometry of
a uniformly ordered array.
Figure 17 Photocurrent response of NWs on CPW from a 1ps wide laser pulse.[80]
32
2.3 PROPOSED DEVICE
2.3.1 Conceptual Device Design
The proposed device is designed to exploit the advantages afforded by nanowire geometry for both
enhanced optical absorption and distributed junction capacitance. By using the previously
mentioned simulation techniques, the details of which are discussed in §2.3.2, absorption for a
uniform array of nanowires within a narrow optical bandwidth can be optimized and enhanced as
compared to planar material. This geometry typically has a low spatial fill factor, on the order of
10 − 15%, which consequently distributes the junction area as well. Theoretically, this allows for
a low parasitic junction capacitance with a large active area, enabling modulation bandwidth in the
Gigahertz range. For example, a junction on a nanowire array with a 10 % spatial fill factor will
have 10 times the active area of a conventional, planar junction with the same net junction
capacitance. Figure 18 shows a schematic of the proposed device.
Figure 18 3D schematic of proposed nanowire photodetector device.
33
This schematic shows an array of nanowires with a GaAs core and an AlGaAs passivating shell,
infiltrated by a polymer. A schematic layer of ITO is shown to cover a portion of the nanowire
array, demonstrating where the Schottky-like junction will be formed at the nanowire tips. This
device intends to build on the learning demonstrated in previous nanowire photodetectors that were
highlighted in §2.2.3. The uniform array will be able to exploit the enhanced optical absorption,
while using a high-speed packaging scheme to enable high-speed modulation bandwidth. The
simulations done to optimize the device, growth and fabrication, and experimental techniques and
results follow in the subsequent sections of this chapter.
2.3.2 Optical Absorption Optimization
An array of nanowire material has a complicated optical absorption response which is due to the
periodicity of the uniform nanowire array and the associated dielectric contrast seen by the incident
optical wave. These effects have been simulated and investigated for solar cell applications as a
means to improve device efficiency.[71, 81] In these studies, it was found that optical absorption
within a spectral range can be greatly enhanced as compared to planar material. The dependence
of optical absorption enhancement for a particular value or a range of wavelength is on the diameter
and pitch of the nanowires. An important metric of nanowire materials is their spatial fill factor
which relates their diameter 𝐷 and pitch 𝑝 as
𝑓 =
𝜋 (
𝐷 2
)
2
𝑝 2
⁄
(2.1)
A study on the theoretical enhancement of nanowire optical absorption[82] considers an InP
nanowire array to be optimized for operation at 850 𝑛𝑚 . In the regime where 𝐷 ≫ 𝜆 , we can
expect the absorption to behave very similarly to that of a bulk, planar material. Incident plane
34
waves interact predominantly with the top surface of the nanowire, and the reflection from these
surfaces is defined as
𝑅 𝑏𝑢𝑙𝑘 =
|𝑛 𝐼𝑛𝑃 − 𝑛 𝑎𝑖𝑟 |
2
|𝑛 𝐼𝑛𝑃 + 𝑛 𝑎𝑖𝑟 |
2
= 0.3 (2.2)
The optical waves inside the InP nanowires decay as they would in bulk material, with the
absorption coefficient 𝛼 𝑏𝑢𝑙𝑘 = (4𝜋 Im(𝑛 𝐼𝑛𝑃 ) 𝜆 ⁄). In this so-called geometrical limit, then, the
absorptance 𝐴 for nanowires with length 𝐿 is then defined by
𝐴 𝑔𝑒𝑜𝑚 = 𝑓 (1 − 𝑅 𝑏𝑢𝑙𝑘 )[1 − 𝑒 −𝛼 𝑏𝑢𝑙𝑘 𝐿 ] (2.3)
In the opposite extreme, where 𝐷 ≪ 𝜆 , the spatial fill factor is 𝑓 ≪ 1 and the electric field is
screened from the nanowires and remains constant in the region between the nanowires. A
screening factor 𝛽 𝑠𝑐𝑟 can be defined as
𝐸 𝑁𝑊
(𝑧 ) = |
2𝑛 𝑎𝑖𝑟 2
𝑛 𝑎𝑖𝑟 2
+ 𝑛 𝐼𝑛𝑃 2
| 𝐸 𝑒𝑥𝑡 (𝑧 ) ≡ 𝛽 𝑠𝑐𝑟 𝐸 𝑒𝑥𝑡 (𝑧 ) (2.4)
which relates the external field between nanowires to the magnitude inside of the semiconductor
material. By considering the power flow in the vertical direction, and the field screening factor,
the absorption coefficient in this electrostatic regime as
𝛼 𝑒𝑠𝑡𝑎𝑡 = 𝑓𝜂 𝛼 𝑏𝑢𝑙𝑘 (2.5)
where
𝜂 = 𝑅𝑒 (𝑛 𝐼𝑛𝑃 )𝛽 𝑠𝑐𝑟 2
(2.6)
This factor reduces the nanowire absorption as compared to bulk by a value of 1/𝜂 . In this limiting
case, the reflection at the nanowire surfaces is negligible and the reflection at the substrate is as
defined in eqn. (2.2). Therefore the absorptance in this regime is
35
𝐴 𝑒𝑠𝑡𝑎𝑡 = [1 − exp (−𝛼 𝑒𝑠𝑡𝑎𝑡 𝐿 )][1 + 𝑅 𝑏𝑢𝑙𝑘 exp (−𝛼 𝑒𝑠𝑡𝑎𝑡 𝐿 )] (2.7)
where a majority of the light can be absorbed, given the proper length of nanowire.
To investigate the regime of nanowire absorption enhancement, diameters in the range of 10 nm –
10 µm were simulated. The fill factor 𝑓 = 0.055 with a fixed relationship of 𝑝 = 3.78𝐷 for
nanowires with 1 𝜇𝑚 length. Figure 19 shows the geometry definitions and the resulting
absorptance values for the simulated range of diameters.
Figure 19 a) schematic of simulated nanowires and associated dimensions. b) simulated absorptance of nanowire array at 850
nm.[82]
As mentioned, the fill factor is a fixed value with a fixed relationship between pitch and diameter.
Therefore, the volume of semiconductor material is constant for this simulation. The right plot of
Figure 19 also shows the absorption of a planar thin film with the same volume of material as a
point of reference. We can see that at 𝐷 = 177 𝑛𝑚 , there is a strong resonance, yielding 97 %
absorptance at 850 𝑛𝑚 .
Similar work has been at USC in Dr. Povinelli’s Nanophotonics Laboratory to study enhancement
of absorption for solar cells.[14, 71] These calculations follow the methodology outlined above
and were repeated by Nanophotonics Laboratory group member Ningfeng Huang for the proposed
devices in this thesis. The simulations were done for GaAs nanowires infiltrated with polymer for
operation at 850 𝑛𝑚 wavelength. The absorption length of 850 𝑛𝑚 in GaAs is ~1 𝜇𝑚 , therefore
36
the height of nanowires in these simulations is fixed at 3 𝜇𝑚 , to ensure maximum light absorption.
The results are shown in Figure 20. The simulation space in the upper left and lower right portions
of the figure were not simulated as a means to reduce simulation time. Two regions showing strong
absorption trends can be seen in the figure. When determining the optimum point for lattice
constant, technological issues of polymer infiltration and possible bending/cracking damage to the
nanowire must be considered. For these reasons, and motived by the simulation results, a lattice
constant of 600 𝑛𝑚 with a 0.28 d/a ratio was chosen for these devices, which has a simulated
absorption of 94.3 % for 850 𝑛𝑚 wavelength.
Figure 20 Absorption of 850 nm light for a square array of GaAs nanowire array infiltrated with a polymer.
2.3.3 Nanowire Surface
As a nano-structure, the surface of a nanowire plays a key role in material characteristics. As a
result, the effects of surface states on carrier lifetime and mobility has been under intense research.
The surface of a semiconductor material is an example of a perturbation to the otherwise infinite,
periodic crystal structure. A few consequences of this perturbation are unpassivated bonds for the
37
lattice atoms at the surface and relaxed interatomic spacing for the few monolayers beneath the
surface.[83] These two effects play a major role in nanowires, given that typical diameters are on
the order of ~2000 Å, III-V lattice constants range from 3 − 5 Å, resulting in a structure that is
400-600 atomic sites in width.
The unpassivated surface states create a radially depleted layer whose penetration depth depends
on the quality of the surface and any possible core/shell doping of the nanowire. These were
simulated theoretically for a p-type core/n-type shell nanowire for a solar cell application.[84] In
this work, various combinations of doping concentrations for each species, as well as different
concentration values of surface states, were simulated as a means to understand the depth of the
radial depletion. A summary of their approach and results follow and the reader is encouraged to
reference the study for a more in-depth understanding.
Figure 21 shows a schematic of the nanowire cross section and the associated parameter definitions
used for this simulation. In this simulation, the surface state density is represented energetically by
the 𝜓 𝐶𝑁𝐿 parameter. This parameter represents the Fermi energy at the surface due to the
unpassivated bonds. The parameters 𝜓 𝑝 0/𝑛 0
represent the energy separation of the Fermi level to
the valence/conduction band as a consequence of the doping concentration for the core and shell.
The simulation uses the Poisson equation in radial coordinates to solve for the electric field and
energy as a function of radius. This equation is defined as
𝑑 2
𝜓 𝑑 𝑟 2
+
1
𝑟 𝑑𝜓
𝑑𝑟
= −
𝜌 𝘀 = −
𝑑𝐸
𝑑𝑟
−
𝐸 𝑟
(2.8)
In radial coordinates, the solution for the electric field and potential are of the form
𝜓 (𝑟 ) = −
𝜌 4𝘀 𝑟 2
+ 𝐶 1
ln(𝑟 ) + 𝐶 2
(2.9)
38
𝐸 (𝑟 ) = −
𝑑𝜓
𝑑𝑟
=
𝜌 2𝘀 𝑟 −
𝐶 1
𝑟
(2.10)
The equations (2.9) and (2.10) are subject to boundary conditions that rely on various doping
combinations and whether or not they are at the doping interface or the surface of a nanowire. For
example, for a partially depleted p-core, the Neumann boundary condition implies that
𝐸 (𝑟 = 𝑟 𝑝 ) = 0 due to charge neutrality. Similarly, the Dirichlet boundary can be used to define
𝜓 (0 < 𝑟 < 𝑟 𝑝 ) = 𝜓 𝑝 0
as defined by the doping concentration.
Figure 21 Nanowire cross section schematic and parameter definitions for simulation.[84]
Similar mathematical approaches were taken for situations and the key finding is shown below in
Figure 22. For brevity, the species doping have been held equal, implying 𝑁 ≡ 𝑁 𝐴 = 𝑁 𝐷 , and three
levels of surface state densities have been simulated. These values loosely represent the range of
39
possible densities for poor nanowires (𝐷 𝑖𝑡
= 10
13
𝑐𝑚
−2
𝑒 𝑉 −1
) to a passivated nanowire surface
(𝐷 𝑖𝑡
= 10
11
𝑐𝑚
−2
𝑒 𝑉 −1
). For a fixed row (𝐷 𝑖𝑡
) and fixed radius of nanowire (𝑎 ), it can be noted
that as doping concentration is increased, the critical thickness, represented by the yellow region,
grows smaller. These results give a sense of dimensions involved for the radial depletion thickness
as a function of realistic doping concentrations and surface state densities for nanowires that are
used in device applications. The optimized combination is then a highly doped nanowire with a
passivated surface to minimize the surface density of states.
Figure 22 Contour plot showing various cases as a function of a and a p. Different values of surface state density Dit are shown
for N=NA=ND with critical core radius and shell thickness shown for each plot.[84]
40
There have also been experimental techniques used to show the effects of surfaces on nanowire
material characteristics. Using Terahertz Time-Domain Spectroscopy (THz-TDS)[85, 86],
lifetimes and mobilities of GaAs nanowires have been experimentally quantified. An advantage of
THz-TDS is that it does not require electrical contacts and can be done in room temperature. These
advantages simplify the nanowire sample preparation and enable extraction of material parameters
at temperatures at which they will be used. In these studies, it was found that GaAs nanowires
grown by Au-catalyst MOCVD technique with a zinc-blend crystal structure have a mobility of
1000 𝑐𝑚
2
𝑉 −1
𝑠 −1
, almost a factor of 6 less than bulk GaAs. It should be noted that these nanowires
were not passivated. Another contactless experimental technique is time-resolved
photoluminescence (TRPL) used to quantify carrier lifetimes.[6, 87] The study done by Demichel,
et al.[6] compares the TRPL signal of an unpassivated GaAs nanowire to one that is passivated
with a thin AlGaAs layer. The nanowires used in this experiment were grown by Au-catalyst VLS
technique in an MBE chamber with a zinc-blend crystal structure, are ~15 𝜇𝑚 in length and have
a taper in the diameter. This shape allows for an experimental measure of the TRPL signal for
various diameter values. The optical signal is from a 780 𝑛𝑚 laser and are done at liquid helium
temperatures. The results of this experiment are shown in Figure 23. The black curve for the
unpassivated sample shows a sharp decrease in signal once the nanowire diameter reaches
~110 𝑛𝑚 . For a similarly grown nanowire with a 4 𝑛𝑚 thick layer of Al 0.4Ga 0.6As passivation
layer, the TRPL signal remains in the same order of magnitude for the length of the nanowire, as
shown by the red curve. These results highlight the importance of the surface on nanowire material
parameters and the necessity of surface passivation. In order to optimize device performance,
surface passivation steps were incorporated into the growth recipe for the devices used in this
thesis.
41
Figure 23 TRPL signal of a passivated and unpassivated GaAs nanowire.[6]
2.3.4 Nanowire Growth
The preparation and growth of samples used for this work were done by CSL alumni Maoqing
Yao. The substrates used were GaAs (111)B and degenerately doped n-type to ~1 × 10
18
𝑐𝑚
−3
.
These substrates were cleaned and covered with a 20 𝑛𝑚 thick layer of SiN dielectric hard mask.
A layer of photoresist was then spun on and exposed by a Raith e-Line EBL system for a 1 𝑚𝑚 ×
1 𝑚𝑚 square array of circular holes with a pitch of 600 𝑛𝑚 and a diameter of 100 𝑛𝑚 and
developed using conventional lithography techniques. This pattern was etched into the underlying
SiN using a Fluorine-based Reactive Ion Etch (RIE) recipe and subsequently stripped.
The samples were then loaded in a Thomas Swan MOCVD chamber for nanowire growth via
SAG. Trimethylgallium (TMG), trimethylaluminum (TMAl), and arsine are used as the precursors
for Ga, Al, and As at 0.1 atm pressure. The total flow rate of carrier gas is 7 SLM and partial
pressure for TMG and arsine are 7.5 × 10
−7
𝑎𝑡𝑚 , 2.4 × 10
−4
𝑎𝑡𝑚 , respectively, during the
growth of the nanowire core. During the growth of the AlGaAs passivation layer, arsine partial
pressure was increased to 1.01 × 10
−3
𝑎𝑡𝑚 and partial pressures of TMG and TMAl were kept
at 3.7 × 10
−7
𝑎𝑡𝑚 and 1.51 × 10
−7
𝑎𝑡𝑚 , respectively. Temperature was fixed at 760 °𝐶 for
42
the growth of both nanowire core and passivation layer. After 90 minutes, nanowires with ~3 𝜇𝑚
height and ~220 𝑛𝑚 diameter were grown, as shown in Figure 24. From the figure, can we see a
hexagonal shape to the nanowires, the cause of which is not specifically known. The white flakes
seen on the substrate is due to the lower selectivity of the Al species, which deposits on the
dielectric mask, as well as the nanowire sidewalls. It also appears that this passivation layer did
not grow on the upper nanowire surface. To confirm this observation, a known selective dry etch
technique[88] that has high 200:1 selectivity between GaAs and AlGaAs was used.
Figure 24 SEM images of passivated nanowire array post-growth.
It was hypothesized that if there is minimal or no thickness of AlGaAs at the nanowire tip, a
selective dry etch should form a crater-like depression in the nanowire core. Using a BCl 3 gas etch
recipe in an ICP etch tool, these as-grown samples were infiltrated to expose the nanowire tips and
etched for various times. The resultant SEM image is shown in Figure 25 where, as expected, a
depression is seen to form in the GaAs core. There is also pitting in the infiltration polymer as a
result of this etch as well. The details of this polymer are outlined in §2.3.5. This evidence, and
43
the SEM images of the grown wires, suggests a very thin, < 1 𝑛𝑚 , layer of AlGaAs on the
nanowire tips, if at all.
Figure 25 Selective etch of GaAs nanowire versus AlGaAs passivation layer.
Immediately following the growth of the nanowire array, an Ohmic contract to the back of the
substrate is formed. This is done to avoid the exposure of the sample to the high temperature anneal
used for this Ohmic contact as it can adversely affect the polymer and eliminate the rectifying
junction at the ITO/GaAs interface. The Ohmic contact material is 100 𝑛𝑚 /10 𝑛𝑚 /100 𝑛𝑚 layer
of AuGe/Ni/Au is deposited on the back of the substrate by metal electron-beam (e-beam)
evaporation and annealed up to 450 °𝐶 using a Rapid Thermal Anneal (RTA) oven.
2.3.5 Polymer Infiltration
The ideal polymer used for nanowire infiltration must be transparent at the operating wavelength
of 850 𝑛𝑚 , electrically insulating, mechanically stable, have thermal expansion/contraction
characteristics similar to that of GaAs, and be chemically stable over time from exposure to air.
Furthermore, it must be low enough in viscosity to ensure infiltration all the way down to the
44
substrate, but yet be viscous enough so that a uniform layer of the polymer that is thick enough
can be built up to cover all of the nanowire height. Furthermore, the coverage of the polymer is a
function of nanowire height/pitch, as well as the spin speed/time used. To ensure chemical stability
and to prevent deterioration or oxidation over time, polymers are cured with a bake at temperatures
in the range of 200 − 250 °𝐶 . Therefore, it is important that the polymer used has a thermal
expansion coefficient that is similar as the nanowires during heating/cooling. This is crucial to
ensure that once cooled to room temperature, the polymer does not pull away from the nanowires,
exposing the sidewalls and causing electrical shorts and leakages once contacts are formed.
To achieve this task, polymers such as Polymethyl methacrylate (PMMA), AZ 5214-E,
Benzocyclobutane (BCB) and Hydrogen Silsesquioxane (HSQ) were used. In previous device
fabrication applications[1, 10], BCB was used successfully to infiltrate nanowires of ~3 𝜇𝑚
height with a 600 𝑛𝑚 pitch. However, due to the high viscosity of this material and the nanowire
dimensions, 3 𝜇𝑚 seemed to be the minimum thickness achievable by BCB as nanowire samples
were often over-infiltrated, covering the nanowire tips. Subsequent CF 4 dry etch of BCB in RIE
tools can be used to expose the nanowire tips, however this should be avoided to prevent damage
to the GaAs material underneath. Various concentrations of PMMA at 2%, 5%, and 9% were used
as infiltration polymers as well. The lighter concentrations of 2% and 5% proved to be too low in
viscosity or possibly surface tension, making it very difficult to infiltrate a 3 𝜇𝑚 tall nanowires.
One possible solution to this problem is using multiple spin-on steps accumulate the material.
However this approach is complicated, as the effective nanowire height is reduced with each
subsequent spin-on, requiring the spin speed/time be adjusted as well.
Using HSQ as an infiltration polymer proved to be the most repeatable and successful approach.
This material was initially developed by Dow-Corning as a high-resolution EBL polymer. On
45
planar materials, it can achieve a thickness of ~10 𝑛𝑚 routinely, therefore, it is very low in
viscosity. This is advantageous as it can seep down to the substrate during infiltration. For an array
with a pitch of 600 𝑛𝑚 and samples with various heights in the range of 1 − 3 𝜇𝑚 , it can achieve
a uniform coverage of the entire array with ~50 𝑛𝑚 of exposed nanowire tip at a spin speed of
1000 𝑟𝑝𝑚 for 60 seconds. This is most likely due to higher surface tension for HSQ as compared
to a similarly low viscous material such as 2 % PMMA, which promotes adhesion to the
nanowires. After the infiltration step, the nanowires were exposed to a 30 second Oxygen plasma
ash at 200 𝑚𝑇 pressure and 100 𝑊 power. This is to remove HSQ residue from the exposed
nanowire tips and to ensure a clean surface. Previous studies in literature have also found this
Oxygen plasma can enhance the Schottky barrier height at the ITO/GaAs interface.[89] It was
possible to achieve a uniform, planar infiltrated layer with HSQ by only one spin-on step.
Therefore, no dry etch of the material was needed to expose nanowires tips, minimizing surface
damage to the GaAs nanowires.
Another key advantage of HSQ is that once baked and cured at 225 °𝐶 , it will turn into an Oxide
dielectric. This advantage ensures chemical stability once the sample is processed and exposed to
regular atmosphere. To achieve this cure, the samples were put on a hot plate with an isolation
chamber. This chamber was purged with a 10 sccm flow of Nitrogen as the temperature was
ramped from 25 °𝐶 to 225 °𝐶 and baked for 15 minutes. The ramp up/down rate used was 1 °𝐶 /𝑠
with a programmable temperature control module.
2.3.6 Indium-Tin-Oxide Deposition
Indium-Tin-Oxide is the contact material of choice in many device applications as it is both
optically transparent and highly conductive. In2O3 has a cubic crystal structure as deposited.
Studies have been done with X-ray Diffraction measurements done on samples and show no peaks
46
that can be assigned to Sn, SnO or SnO2, implying totally miscibility of Sn and In atoms within
the lattice.[90] In the lattice, Sn is tetravalent, with each Sn atom substituting an In atom, donating
a free electron for increased conductivity. The optical transmission and conductivity of the overall
material, therefore, have an inverse relationship. It is possible to achieve ~90 % optical
transmission at visible/infrared wavelengths with conductivity on the order of ~10 Ω ∎ ⁄ with
ITO films of 100 − 300 𝑛 𝑚 thick by both e-beam evaporation and sputtering deposition
techniques.[90]
For e-beam evaporation of ITO, source material of 90% In
2
O
3
and 10% SnO
2
ceramic targets from
American Elements was used in a Sloan dielectric evaporation chamber. This chamber allows for
accurate control of the optical transmission and conductivity characteristics by allowing oxygen
(99.99% purity) flow into the chamber during the deposition process. Tungsten lamps within the
chamber that heat the sample up to ~275 °𝐶 , which allows for control of the Oxygen species
incorporation into the sample. After the nanowires are infiltrated and the polymer is cured, the
sample is loaded for ITO e-beam evaporation. Previous studies of ITO Schottky barriers found
that, prior to deposition, a high-temperature outgas improved barrier heights.[91] This was
attributed to the impurities on the surface being driven and resulting in a clean surface. Following
this procedure, once the sample is loaded, it is out-gassed at 275 °𝐶 prior to deposition. This step
also helps reduce the background deposition pressure of the chamber to the order of 1 ×
10
−6
𝑇𝑜𝑟𝑟 . A 150 𝑛𝑚 thick layer of ITO is then deposited at a rate of 0.2 𝑛𝑚 /𝑠 at 225 °𝐶 with
an Oxygen flow rate of 8 𝑠𝑐𝑐𝑚 . A low deposition rate was chosen as it has shown higher barrier
height and minimal surface damaged compared to higher rates.[92] This yields a film with 85 −
90 % optical transmission for 850 𝑛𝑚 with a sheet resistance of 30 − 40 Ω ∎ ⁄ corresponding to
~1 × 10
21
𝑐𝑚
−3
n-type carrier concentration.[93]
47
Since the e-beam evaporation is a high temperature process, patterning of ITO by conventional
lift-off technique involving polymers is not possible. Therefore, sputtered ITO was also deposited
and patterned via lift-off techniques to reduce active area detectors for high-speed operation.
Sputtered ITO for contacting III-V materials for solar cells has been studied in the past.[94] For
these devices, similar recipe as used for nanowire solar cells was used.[1] Optical transmission
and conductivity of sputtered ITO using an ULVAC J-Sputter system was very close to values
obtained by e-beam deposited ITO. To increase optical transmission, 0.5 𝑠𝑐𝑐𝑚 oxygen was
admitted into the chamber. The details of the ITO lift-off process is discussed in the next section
for high speed device fabrication and packaging.
2.3.7 High-Speed Device Fabrication and Packaging
To exploit the dispersed junction capacitance of nanowires for high-speed operation, the active
area dimension as contacted by the ITO requires careful control by lithography and lift-off
techniques. Sputtered ITO is appropriate for this purpose as it is a room temperature process that
allows lift-off of the photoresist. Using optical lithography, a square active area with an area of
50 𝜇𝑚 × 50 𝜇𝑚 was defined on the perimeter of the nanowire array. This region extended to a
30 𝜇𝑚 × 30 𝜇𝑚 square pad off of the nanowire array active area to allow stable probing. Image
reversal lithography was used to ensure a negative slope for the polymer sidewall, improving ITO
lift-off and with smoother edges. A 50 𝑛𝑚 layer of Au/Ti was subsequently deposited on the
probing region of the ITO to allow for repeatable, low resistance probing of the device. A
schematic and SEM image of a typical device is shown in Figure 26 and Figure 27, respectively.
The metal pad on the ITO allows for probing with a high-speed RF probe and therefore requires a
ground pad on the top surface of the sample. The Au/Ti ground plane is deposited away the
nanowire array on top of the HSQ, which planarizes the sample. This ground pad is shorted to the
48
backside ground contact via wirebonds, as shown schematically in Figure 28. The parasitics and
possible improvements for this packaging scheme are proposed in §2.6.3.
Figure 26 3D schematic of reduced-dimension device for RF bandwidth testing.
Figure 27 SEM of a reduced dimension device for high-speed testing.
49
Figure 28 Cross section of package schematic showing wirebond to ground plane.
2.4 EXPERIMENTAL SETUPS
2.4.1 Responsivity Measurement Experimental Setup
To achieve a high signal value as a means to accurately measure photocurrent responsivity, a large
active area nanowire device was used. The 1 𝑚𝑚 × 1 𝑚𝑚 nanowire array size necessitates the
use of optical fibers in lieu of free-space optical beams to achieve a spot size diameter on the order
of millimeters. The laser source is a continuous-wave diode laser at 850 𝑛𝑚 (Power Technology,
IQ1H85/5557) with 40 𝑚𝑊 maximum output power and an elliptical output beam with a diameter
on the order of centimeters. An optical isolator in front of the laser prevents back-reflections into
the laser cavity, followed by two optical lenses (5 𝑐𝑚 diameter) used to collimate the optical beam.
The output is attenuated by a large-area gradient neutral density filter wheel and is split by a 50/50
beamsplitter to actively monitor beam power via a commercial photodetector with known
responsivity. The through beam is then coupled to a multimode 62.5 𝜇𝑚 fiber using an objective
lens with ~1.5 𝑑𝐵 coupling loss. The fiber has a cleaved output facet with NA of 0.275, and is
able to achieve 2.6 𝑚𝑚 diameter spot size at 7 𝑚𝑚 working distance, resulting in 75 % overlap
with the active area. To accurately align the fiber, a 4-axis translation/rotation stage was used to
ensure an optimally aligned, normal incidence input beam. Optical losses due to various
components, and the area overlap of the spot size with the active area, must be taken into account
accurately to calculate the responsivity. Figure 29 shows a schematic of the experimental setup.
50
To carry out current-voltage (I-V) measurements, a semiconductor parameter analyzer (HP 4145B)
with 1 𝑝𝐴 noise floor was used. The device under test (DUT) was mounted to a circuit board with
a signal trace that was connected to an RF terminal. The ITO layer was wirebonded to the signal
pad for I-V measurements. This technique maintained a low noise floor and enabled the device to
mechanically fit under the fiber assembly due to height clearance issues.
Figure 29 Schematic of optical portion for responsivity measurement setup.
2.4.2 Bandwidth Measurement Experimental Setup
To experimentally measure the modulation bandwidth of nanowires devices, a VCSEL emitting at
850 𝑛𝑚 with a 3dB modulation bandwidth of 10 𝐺𝐻𝑧 bandwidth was used as the optical source.
The VCSEL has a 1 𝑚𝐴 threshold current, external efficiency of 𝜂 = 0.2 𝑊 /𝐴 , and a max bias
value of ~12 𝑚𝐴 . The VCSEL was DC-biased at quadrature of 6 𝑚𝐴 by a current source and
modulated sinusoidally by port 1 of a network analyzer (HP 8510). Using a commercial high-speed
detector with a 25 𝐺𝐻𝑧 bandwidth, the modulation depth of the VCSEL was measured at 𝑚 =
0.94 for the aforementioned conditions. The optical output was coupled to a spherically lensed
fiber (LaseOptics) with a 45° facet designed for normal incidence which can achieve ~100 𝜇𝑚
diameter spot size at ~1 𝑚𝑚 working distance. The device was probed with 150 𝜇𝑚 pitch high-
speed probes (Cascade Microtech) and its current output was input to a bias-t used to apply various
51
values of reverse bias. The AC current output was electrically amplified (HP 83050A), which
places a lower frequency limit of 2 𝐺𝐻 z owing to the gain spectrum of the amplifier. The
frequency response was then measured at increasing values of reverse bias and optical intensities.
The entire setup is shown schematically in Figure 30.
Figure 30 Schematic of experimental setup for high-speed bandwidth measurement.
2.5 EXPERIMENTAL RESULTS
2.5.1 Junction Analysis
Photodetectors based on a Schottky junctions have shown high RF bandwidth[95], and offer
advantages such as simplification in fabrication as they require no additional doping of the
semiconductor. Furthermore, current is based on electron majority carriers and can be engineered
by a proper understanding of the intricate physics regarding band alignment of the two materials.
The energy band diagram for a typical metal to semiconductor junction is shown in Figure 31.
52
Figure 31 Metal-Semiconductor Schottky junction energy diagram.[83]
The barrier height B is lowered due to the mirror-charge image force and the effective barrier
height Bn plays a key role in determining the current behavior in reverse bias. This barrier height
is paramount in reducing leakage current in reverse bias to maintain good signal to noise ratio, as
well as to avoid breakdown of the junction with applied reverse bias. As previously mentioned,
fabrication steps can be taken to enhance the barrier height by ensuring a clean surface of the
semiconductor material.[89]
The reverse bias saturation current density can be theoretically predicted by the thermionic
emission model and summarized as
𝐽 𝑠 = 𝐴 ∗
𝑇 2
𝑒𝑥𝑝 (
−𝑞 𝜙 𝐵𝑛
𝑘𝑇
) (2.11)
where
𝐴 ∗
=
4𝜋𝑞 𝑚 ∗
𝑘 2
ℎ
3
(2.12)
Here, A is referred to as the Richardson constant with value 120 (A/cm
2
/°K
2
) for electron emission
into a vacuum. The effective mass of the semiconductor will reduce this value. From Eqn. (2.11),
the barrier height effects on the magnitude of leakage current is obvious in the exponential.
53
An experimental technique exists that allows for direct measurement of the barrier height of the
junction. Referred to as Internal Photoemission Spectroscopy (IPS), it has been used successfully
in the past for accurate measurement of Schottky barrier heights in III-V material systems.[96, 97]
The experiment is such that a tunable laser light that is below the bandgap of the semiconductor
impinges on the metal layer. As the wavelength (photon energy) is decreased (increased) towards
a ‘turn on’ wavelength (energy), excited electrons in the metallic layer of the Schottky junction
will have enough energy to surmount the barrier and therefore increase leakage current, which can
be experimentally measured.[83] Careful calibration of the optical power and high current
sensitivity are required for this measurement. Theory predicts[96] the photoresponse per absorbed
photon (PR) to photon energy as
√ 𝑃𝑅 ≅ ℎ𝜐 − 𝜙 𝐵𝑛
(2.13)
IPS was conducted on nanowire devices to directly measure the barrier height. A tunable laser
within the range of 1400-1480 nm wavelength was used. The data is plotted in Figure 32, which
shows a measured barrier height of ~0.8 eV which is within 5 % of calculated values of barrier for
an ITO/GaAs interface. GaAs has a room temperature work function and bandgap of 4.1 𝑒𝑉 and
1.4 𝑒𝑉 , respectively. However, the work function of ITO is dependent on deposition technique,
parameters, and conditions and therefore varies greatly in the range of 4.7 − 5.5 𝑒𝑉 [93].
54
Figure 32 IPS data showing barrier height of ~0.8 eV.
2.5.2 Device Current-Voltage
Figure 33 shows I-V behavior of this device with 2.7 − 3 𝜇𝑚 tall passivated nanowires in the dark
and at various powers of illumination. The reverse bias portion of the curve shows increase in
photocurrent with an increase in optical illumination. Beyond 4 𝑉 reverse bias, we see the junction
tending towards breakdown and current collected becomes independent of illumination power.
55
Figure 33 Photocurrent of nanowire detector under various powers of illumination.
In another method to extract barrier height, among other relevant parameters, the forward bias
portion of the dark I-V curve is used, as outlined in Cheung et al.[98] Here, the Schottky current
equation takes into account deviations from theoretical behavior by including an ideality factor 𝑛 ,
in the denominator of the exponential of Eqn. (2.11). The diode resistance is also modeled by a
series resistor 𝑅 , which decreases the voltage across the junction. The resultant equation is
𝐽 = 𝐽 𝑠 𝑒𝑥𝑝 [
𝑞 (𝑉 − 𝐼𝑅 )
𝑛𝑘𝑇 ⁄ ] (2.14)
Another method to extract the series resistance, ideality factor, and barrier height has been
developed by Norde[99], but is rather complex in that it requires experimental current behavior at
two temperatures. The method developed by Cheung et al.[98] simplifies this one measurement
by a mathematical treatment. Solving Eqn. (2.14) for applied voltage results in
𝑉 = 𝑅 𝐴 𝑒𝑓𝑓 𝐽 + 𝑛 𝜙 𝐵𝑛
+ (
𝑛 𝛽 ⁄
) 𝑙𝑛 (
𝐽 𝐴 ∗∗
𝑇 2
⁄ ) (2.15)
56
where 𝐴 𝑒𝑓𝑓 is the junction effective area and
𝛽 =
𝑞 𝑘𝑇
⁄ (2.16)
Differentiation of Eqn. (2.15) with respect to ln (𝐽 ) results in
𝑑 (𝑉 )
𝑑 (ln 𝐽 )
= 𝑅 𝐴 𝑒𝑓𝑓 𝐽 +
𝑛 𝛽 (2.17)
Thus a plot of 𝑑 (𝑉 ) 𝑑 (ln 𝐽 ) ⁄ vs. 𝐽 will give 𝑅 𝐴 𝑒𝑓𝑓 as the slope and 𝑛 𝛽 ⁄ as the y-axis intercept. To
calculate the barrier height, we can define a function
𝐻 (𝐽 ) ≡ 𝑉 − (
𝑛 𝛽 ⁄
) ln (
𝐽 𝐴 ∗∗
𝑇 2
⁄ ) (2.18)
This equation is also of the form
𝐻 (𝐽 ) = 𝑅 𝐴 𝑒𝑓𝑓 𝐽 + 𝑛 𝜙 𝐵𝑛
(2.19)
A plot of Eqn. (2.19) will give a similar slope to that of Eqn. (2.17), which can be used to track the
consistency of this approach. The calculated ideality factor from Eqn. (2.17) can then be used to
find the barrier height given the y-axis intercept from Eqn. (2.19), which will result in a linear plot.
These equations are shown in Figure 34 and Figure 35.
57
Figure 34 Plot of Eqn. (2.17) as derived above from experimental device I-V data.
Figure 35 Plot of Eqn. (2.19) as derived above from experimental device I-V data.
58
From the device I-V data, the turn-on voltage is extracted to be 𝑉 𝑏𝑖
= 0.65 𝑉 . The analysis of Eqns.
(2.17) and (2.19) resulted in a barrier height of 0.75 𝑒𝑉 , which is close to the measured value from
IPS reported above. ITO that is deposited via e-beam evaporation or sputtering has carrier
concentration in the range of ~1 × 10
20
𝑐𝑚
−3
for electrons[100] and thus forms an n+/n junction
at the ITO/GaAs interface. This can be treated as a one-side junction, where the depletion region
width is estimated as
𝑊 𝐷 =
√
2 𝜖 𝑟 𝜖 𝑉 𝑏𝑖
𝑞 𝑁 𝑑
(2.20)
With the barrier height experimentally measured and calculated, and built-in voltage
experimentally known, one can calculate the potential difference, 𝑉 𝑛 , as defined in Figure 31. This
potential is the difference between the conduction band and Fermi level, which is a function of the
semiconductor material’s density of states and doping concentration. Given the experimental
values for the barrier height and 0.65 𝑉 for 𝑉 𝑏𝑖
, we can estimate 𝑉 𝑛 to be 0.1 − 0.15 𝑉 . Using
Fermi statistics, and the known conduction band density of states for GaAs, we can estimate the
nanowire carrier concentration to be ~3 × 10
15
𝑐𝑚
−3
. Using Eqn. (2.20), the depletion region is
calculated to be on the order of ~1 𝜇𝑚 deep into the nanowires for this junction at zero bias. It
should be noted that the total depletion region in a nanowire has both height and radial dependence
to the surface states mentioned previously.
2.5.3 Responsivity
The device behavior shown in Figure 33 demonstrates an increase in open circuit voltage and short
circuit current with an increase in optical power, implying the presence of a Schottky-like photo-
collecting junction at the ITO/GaAs interface. This junction was analyzed both experimentally and
theoretically for its relevant parameters of barrier height and turn-on voltage. The next step is to
59
analyze the responsivity of this junction as a means to quantify its efficiency and to learn more
about the behavior of the device.
For GaAs-based photodetector with absorption at 850 𝑛𝑚 , the theoretical responsivity limit is
0.69 𝐴 /𝑊 for a device operating with 100 % internal and external efficiency. At an applied
reverse bias of 4 𝑉 and optical intensity on the order of 100 𝜇𝑊 /𝑐𝑚
2
, the nanowire device
presented in this thesis achieves a peak responsivity of 0.65 𝐴 /𝑊 . The responsivity of a passivated
nanowire device at various applied reverse bias values is plotted below.
Figure 36 Responsivity at various optical intensities and reverse bias values.
The zero bias responsivity decreases strongly with increased intensity. This behavior is believed
to be primarily due to carrier screening which reduces or even eliminates internal electric field[101,
102] and collapses the depletion region. As a result, the carrier velocity is reduced below saturation
velocity[103] and photo-generated carriers recombine before being collected at the top of the
60
nanowire, drastically reducing responsivity. This effect was simulated and proven experimentally
for planar P-i-N photodetectors based in III-V materials in other studies[102, 103]. The studied
planar devices had much higher internal electric fields as compared to our nanowire devices given
their higher doping and much smaller absorption region thickness. Therefore, the onset of
screening occurred at much higher intensities than is observed for our nanowire devices. Carrier
screening of the internal field can be overcome with an applied field, as can be seen from the
reduced slope of the curves with increasing applied reverse bias in Figure 36. As the magnitude of
the applied field is increased up to 20 𝑘𝑉 /𝑐𝑚 at 4 𝑉 reverse bias, the carrier velocity increases to
its saturation value[104]. This applied field magnitude is large enough that, for the given range of
optical intensities, the internal field is not greatly screened, as is the case for lower reverse bias
values. Therefore, we can see the effect of screening is reduced and a flat response of 0.65 𝐴 /𝑊
across the given intensity values is observed.
As a means of comparison, unpassivated nanowires were tested for responsivity in the same
intensity and bias ranges and the results are plotted in Figure 37. At zero bias, the responsivity was
slightly lower than that of the passivated nanowire device. However, it improved marginally and
did not show the drastic improvement seen for the passivated device with an increase in applied
reverse bias. This observation can be attributed to the unpassivated surfaces of the nanowire which
decrease carrier lifetimes due to high surface recombination velocities. And as mentioned
previously, unpassivated nanowires were found to have surface recombination velocity on the
order of saturation velocity for GaAs. For the unpassivated nanowire device, we can conclude that
surface recombination velocity is not overcome by the applied electric field, and therefore
responsivity remains low. We were also unable to increase reverse bias beyond 1 𝑉 due to high
leakage current. We believe this to be due to the surface states that may also contribute to increased
61
surface current which leads to Ohmic conduction, increasing the leakage current and drastically
decreasing the Signal-to-Noise ratio needed for accurate photo-response measurements.
Figure 37 Responsivity of an unpassivated nanowire detector.
2.5.4 Modulation Bandwidth
The phenomenon of reduced carrier velocity with increasing optical power observed in the
previous section manifests itself in the device’s AC behavior as well by reduction of modulation
bandwidth. To test what range of modulation speeds are attainable, junction capacitance must first
be measured. The large active area devices used for responsivity measurements were also ideal for
measurement of junction capacitance. The capacitance as a function of applied reverse bias was
measured at 1 𝑀𝐻𝑧 and is plotted in Figure 38. Up to 2 𝑉 applied reverse bias, the capacitance
shows almost no change, which is a characteristic of a fully depleted material. The peak
62
capacitance value of < 2.12 𝑛𝐹 /𝑐𝑚
2
theoretically enables modulation bandwidth limit for this
device in the Gigahertz range with proper active area design and device packaging.
Figure 38 Capacitance area density versus applied reverse bias for a passivated nanowire detector.
The two primary mechanisms that limit modulation bandwidth of photodetectors are device
parasitics and carrier transit time. In a packaged device, parasitics are a static function of the device
geometry, electrical pads and probing methodologies. The transit time, however, depends on
applied reverse bias and optical intensity which can result in average carrier velocity reduction, as
hypothesized in the previous section.
Motivated by the observed low capacitance density to measure modulation bandwidth, devices
with reduced active areas were fabricated and packaged as outlined §2.3.7. To first confirm device
quality, the responsivity of the studied devices was measured and found to match the results seen
previously[105]. In order to accurately measure modulation bandwidth as a means to observe
63
material characteristics, circuit parasitics must be de-embedded. To quantify the maximum
modulation frequency due to parasitics, reflection impedance, S 22, measurements at 0 V applied
bias with no optical excitation were carried out. These results were matched with a simulation of
an effective small-signal circuit[106], and found to have a 3𝑑𝐵 roll-off frequency of 9.1 𝐺𝐻𝑧 . The
simulated and measured reflection impedance curves are shown in Figure 39.
Figure 39 Simulated and experimental complex reflection impedance of a packaged nanowire detector for high speed operation.
With the device packaging parasitics known, the modulation bandwidth at various optical
intensities and applied reverse biases was measured with the experimental setup described in
§2.4.2. Figure 40 shows the normalized frequency response for a typical device at three values of
reverse bias for a fixed optical intensity. It is expected that at no applied bias, screening of the
internal electric field due to photo-generated carriers greatly reduces average carrier velocity, thus
reducing the 3𝑑𝐵 roll-off frequency. The simulated transmission curve due to device parasitics is
also drawn as a reference. It should be noted that this simulated curve uses no applied reverse bias.
The experimental curve for zero applied bias has a 3𝑑𝐵 bandwidth that is ~5 𝐺𝐻𝑧 below the
64
simulated zero applied bias condition. Of the two mechanisms stated previously that limit
modulation bandwidth, therefore, it is the transit time that is limiting the 3𝑑𝐵 bandwidth in this
case. To ameliorate this effect, an increased reverse bias may be applied. As applied reverse bias
is increased, a clear increase in the 3𝑑𝐵 roll-off frequency is observed. This behavior is expected
to result from the elimination of photo-generated carrier screening effect by the applied electrical
field which leads to an increase of the average carrier velocity. As an applied reverse bias of 7 𝑉 ,
the modulation bandwidth approaches the parasitic limitation, as expected.
Figure 40 Modulation bandwidth at several applied reverse bias values for a fixed optical intensity.
Another way to approach the issue of carrier velocity reduction is to measure modulation
bandwidth at a fixed reverse bias for various optical intensities. Such a measurement was done and
the results are shown in Figure 41. It is expected that at lower intensities, the 3𝑑𝐵 bandwidth
should be higher for the same applied reverse bias since the effects of screening on carrier transit
time are less at lower optical intensities. For example, the 3𝑑𝐵 bandwidth for both 5 𝑉 and 6 𝑉
applied reverse biases increase as the optical intensity is reduced. At the lowest measured optical
65
intensity, it can be seen that 6 𝑉 reverse bias is very close to the parasitic bandwidth of the device
package.
Figure 41 3dB modulation bandwidth frequency at various reverse bias values and optical intensities.
As a means to quantify average carrier velocities and to gain insight into material characteristics,
we can use theory developed previously[107]. In this treatment, an electron/hole traverses the
depletion region of width 𝑊 𝐷 with an average transit time of 𝜏 𝑒 /ℎ
which includes effects of various
scattering mechanisms. This results in an average electron/hole velocity 𝑣 𝑒 /ℎ
= 𝑊 𝐷 𝜏 𝑒 /ℎ
⁄ . With
the modulated optical excitation varying as e
jω(t−𝑡 0
)
, the electron/hole contribution to the current
generated is defined by
𝑁 [1 −
(𝑡 − 𝑡 0
)
𝜏 𝑒 /ℎ
⁄ ]
𝑞 𝜏 𝑒 /ℎ
⁄ 𝑒 jω(t−𝑡 0
)
(2.21)
66
where 𝑞 is the elementary charge value. We can integrate Eqn. (2.21) for electrons/holes existing
for time after 𝑡 − 𝜏 𝑒 /ℎ
and normalize to find a resultant transfer function of the frequency
dependent current output. Accordingly, the transit time bandwidth of this transfer function can be
estimated with
𝑓 𝑡 ≅
3.5𝑣 𝑎𝑣𝑔 2𝜋 𝑊 𝐷 ⁄
=
1
2𝜋 𝑅 𝑡 𝐶 𝑡 ⁄
(2.22)
where 𝑅 𝑡 is assumed to be 50 Ω for impedance matching.[108] The average velocity which is a
combined result of both electrons and holes is defined as[36]
1
𝑣 𝑎𝑣𝑔 4 ⁄
=
1
2
⁄ (
1
𝑣 𝑒 4
⁄ +
1
𝑣 ℎ
4 ⁄
) (2.23)
In this model, the nanowire detector is abstracted as a perfect AC sinusoidal current source whose
transmission is then measured through two components. The first of those components is a shunt
RC element that is to abstractly represent the carrier transit dynamics of the model developed
above. The second component is the RLC network that represents the device parasitics, as
measured previously by the reflection impedance. The overall circuit is shown in Figure 42. With
the addition of this extra RC component to abstractly represent the carrier dynamic effects,
transmission simulations were done again and a C t value resulting in best fit was extracted. With
the use of Eqn. (2.22), the average velocity at various values of applied reverse bias is plotted
Figure 43.
67
Figure 42 Small-signal circuit used for transmission and carrier velocity modeling.
Figure 43 Extracted average carrier velocity for various applied reverse biases.
An increase in average carrier velocity with increased applied reverse bias is evident and is
expected due to elimination of the screening effect. The peak value of ~2 × 10
6
𝑐𝑚 𝑠 ⁄ is a factor
of three less than carrier velocities observed in high purity GaAs bulk crystal. This can be partly
attributed to scattering planes existing in the nanowire due to twin defects. These effects were
68
simulated by an atomic model developed at USC.[109] In this work, an atomic level quantum
mechanical model is developed to study the effects of twin defects on carrier lifetimes and
mobility. The nanowires for this work have zinc blende (ZB) crystal orientation with alternating
monolayers of Ga and As atoms. In this work, a twin defect plane is defined as[109]:
“The [111]-oriented ZB crystalline GaAs is a stack of alternating Ga and As
monolayers (MLs), where each ML is a two-dimensional triangular lattice of
either Ga or As atoms. According to the lateral positions occupied by the
atoms, the triangular lattices are classified into three types: “A,” “B,” and “C.”
Let the stacking sequence of the top three As MLs below a (111) plane be
ABC, where C is the topmost ML. Then, the next bilayer above the (111) plane
consists of a Ga ML in the C triangular lattice followed by an As ML in two
possible triangular lattices. Namely, As adatoms without twin defect occupy
the A triangular lattice and continue ZB stacking, i.e., ABC|ABC. On the other
hand, As atoms with a twin-boundary plane occupy the B triangular lattice
and continue to grow as ABC|BAC.”
To study the effects of twin defect planes on carrier mobility, an electron scattering potential for
conditions of with and without twin defect planes are develop by analysis of the Kohn-Sham
potential.[110] The calculation was performed for a crystal size of 1.385 𝑛𝑚 × 1.2 𝑛𝑚 ×
7.833 𝑛𝑚 in the 𝑥 , 𝑦 , 𝑧 directions, respectively, with periodic boundary conditions for all axes. A
schematic of the atomic layers is shown in Figure 44.
In defining this crystal and the respective scattering potentials, it was found that the scattering
potential was strongest on the (111) plane in the middle of the Ga and As monolayers. The vertical
dimension only was considered for mobility calculations and it was calculated for three different
average lengths between twin defect planes. This result is shown in Figure 45.
69
Figure 44 Simulated GaAs crystal with and without twin boundaries, where red and yellow spheres represent Ga and As atoms,
respectively.[109]
Using terahertz spectroscopy, carrier mobility for nanowires with and without twin defects was
experimentally measured as well. In this work, it was observed that mobility of GaAs nanowire
with ~50 𝑛𝑚 diameter was enhanced from 1200 𝑡𝑜 2250 𝑐𝑚
2
𝑉 ∙ 𝑠 ⁄ by the elimination of twin
70
defects.[111] This was done by changing growth conditions to reduce mechanisms believed to
cause twin defects, among other crystal impurities. These results agree with the above simulations.
Figure 45 The calculated twin-scattering contribution to electron mobility as functino of temperature for three lengths of twin
segments.[109]
To study the presence of twin defects on nanowires grown for devices used in this thesis,
transmission electron microscopy (TEM) images were taken by Maoqing Yao. From the figures
shown below, twin defect planes separated by lengths on the order of 3 − 5 𝑛𝑚 can be observed.
Therefore, the approximate factor of three velocity reduction observed in the high speed data is in
agreement with the simulated reduction in carrier mobility, given the observed twin lengths from
TEM images. Improvement of growth conditions to reduce and eliminate twin defects can then
serve to enhance material properties and increase modulation bandwidth of high-speed nanowire
detectors.
71
Figure 46 TEM image showing twin defect planes in GaAs nanowires.
Figure 47 TEM image showing twin defect planes in GaAs nanowires.
2.6 FUTURE WORK
In this section, work that was done to extend this project but has remained unfinished is presented.
These experiments were done as a means to further understand the material and device
characteristic of nanowires. For a photodetector, another key metric is its response to data
modulation at various data rates and reverse bias values. Also, for photodetectors experimentally
showing the effects of carrier screening, models were developed to analyze harmonic frequency
generation due to carrier velocity non-linearity. Preliminary measurements of these types were
done on the nanowire based devices and their results are presented below.
72
In doing the high speed parasitic analysis, it was found that the packaging scheme of the nanowire
device contributed significantly to the bandwidth limit observed. It is conceivable that high-quality
GaAs nanowires have carrier velocities that enable modulation above 10 𝐺𝐻𝑧 . Therefore, a
packaging scheme can be developed to enable those measurements. A proposal for such a scheme
is given in this section as a means to observe higher modulation bandwidth in the future.
2.6.1 Data Modulation
The response of a photodetector to a data pattern modulated on to the optical signal is a key metric
as it defines the usage of the detector in real life systems. This response depends ultimately on the
impulse response of the detector and differs from the sinusoidal modulation bandwidth presented
earlier. The main difference in data modulation bandwidth to sinusoidal bandwidth is the transition
time of the detector going from an ON state to OFF state (fall time) and vice versa (rise time).
These two values are often different since they rely on different physical mechanisms and are
subject to different device parasitics. Figure 48 shows a typical eye diagram.
Figure 48 Typical eye diagram.[112]
The data modulated here is non-return to zero (NRZ) format where a high (positive) pulse
represents a logic one and a low pulse (negative) represents a logic zero. This is important to note
73
as it keeps the DC bias of the signal to near zero and allows the data to be both AC or DC coupled.
The amplitude of the eye shown above is the voltage level for the two logic values and ideally, the
eye height should match it. However, signal imperfections such as noise and leakage current can
decrease eye height, causing eye closure. Eye crossing percentage is an indication of duty cycle
distortion or asymmetry in data pulses in the channel. The eye width is the time value between the
two statistical means of crossing points and should ideally equal the pulse width for the associated
data rate that is being modulated. Jitter, or the variation in the statistical mean of the data crossing
point, can cause a decrease in eye width, and is often caused by time deviations of the rise/fall
times.
To experimentally measure such an eye diagram for nanowire devices, a setup very similar to that
shown in Figure 30 was used. However, rather than a network analyzer, a Pseudo-Random Bit
Source (PRBS) data generator (HP 80000) was used for a data rate of 1 𝐺𝐻𝑧 . To characterize the
electrical signal eye diagram, the signal was amplified by RF amplifiers and analyzed by an HP
54750A Digital Circuit Analyzer (DCA). The eye diagram of the data generator signal was
analyzed, as shown in Figure 49, showing 945 𝑝𝑠 eye width.
Figure 49 Eye diagram of electrical data at 1 GHz.
74
Next, the VCSEL data signal was benchmarked by a 25 𝐺𝐻𝑧 commercial photodetector, shown in
Figure 50 with 659 𝑝𝑠 eye width. The reduction of eye width and capacitive features of the rise/fall
curves were experimentally verified to be from the electrical amplifiers used.
Figure 50 Eye diagram of data from VCSEL onto a commercial photodetector.
The nanowires were then tested for their eye diagram response, as shown in Figure 51. The eye is
noisier, and this is a consequence of the leakage current at higher reverse bias values for these
devices. Reduction of the leakage current will enhance the quality of the eye diagram. As a
consequence of noise, the algorithm of the DCA cannot accurately measure the eye width. Manual
measurements show ~660 𝑝𝑠 eye width and it should be noted all the diagrams are with the same
horizontal time scale.
75
Figure 51 Eye diagram of data from VCSEL onto a nanowire photodetector.
2.6.2 Harmonic Generation
In studying planar photodiodes for the effects of photo-generated carrier screening of the internal
electric field, various models were developed. In one such model, described by Dentan et al.[101],
the dependence of carrier velocity on the internal electric field is modeled for a planar, P-i-N,
normal-incidence photodetector. This model is self-consistent, developed for calculating the
internal electric field as a function of photo-generated carriers via the varied optical intensity. This
field value is then used to calculate carrier velocities based on empirical equations that are
developed for GaAs, where carrier mobility values are assumed for bulk InGaAs absorption region.
Finally, the temporal photocurrent response of the device is modeled for a single-frequency,
sinusoidal optical input for a range of optical powers. The nonlinearity of a detector is investigated
and harmonic generation is seen via this model. Figure 52 shows the electrical power as a function
of optical input power. The upper curve, H 1, shows the current response due to the fundamental
frequency of the optical signal. Above −5 𝑑𝐵𝑚 optical input power, 2
nd
and 3
rd
order harmonics
are generated in the current signal, which are caused by the intermodulation terms.
76
Figure 52 Harmonics of planar p-i-n photodetector.[101]
A similar measurement was done on the nanowire devices as a means to see if they too demonstrate
this nonlinear behavior. A sinusoidal optical input of 1 𝐺𝐻𝑧 illuminated the device within a range
of optical powers. An electronic spectrum analyzer was used to monitor the output electrical
current at the fundamental frequency, as well as 2
nd
and 3
rd
order harmonic values. The resulting
plot is shown in Figure 53. A similar model as mentioned above can be developed that takes into
account the field-dependence of the carrier velocities as a means to simulate this experimental
behavior. The ratio, or magnitude difference, of the fundamental frequency and harmonics are of
key dependence on the magnitude of nonlinearity seen by the device. This model could then in
turn be used to extract carrier mobility for nanowires as another method of material
characterization.
77
Figure 53 Harmonic generation for a nanowire photodetector.
2.6.3 Improved High-Speed Packaging
The device parasitics for the packaged nanowire detectors show a large inductive parasitic
component at high frequency, as shown by the s-parameter measurements of Figure 39. This is
believed to be in large part due to the wirebond that connects the ground plane on the back of the
sample to the contact pad on the top surface of the sample. This was done to enable probing for
high-speed measurements. However, if this wirebond can be shortened, or even eliminated,
bandwidth limitations due to packaging parasitics can be removed. Figure 54 shows a schematic
of a proposed packaging scheme that can shorten the length of this wirebond. By using a sample
stage with a step that equals the sample height, a short wirebond can be used to connect two ground
planes. The sample stage, trace length and width, and step height should be carefully simulated
and designed to ensure decreased packaging parasitics.
Figure 54 Possible package solution for reduced inductance for device parasitics.
78
3 PHOTONIC CRYSTAL PHOTODETECTOR
3.1 OPTICAL CHARACTERISTICS OF PHOTONIC CRYSTALS
3.1.1 Optical Properties of Photonic Crystal Lattices
Photonic crystal device architecture relies on similar principles to that of Bragg reflectors to
confine optical intensity and to control the direction of propagation. An example of a 1-D photonic
crystal device is a grating or a series of alternating dielectric layers used for high-reflectivity
mirrors in laser cavity designs. 2-D photonic crystals, as studied in this thesis, are formed by
periodic perturbations to the dielectric material of interest for optical propagation by the formation
of cylindrical holes in a triangular lattice orientation. Figure 55 shows a schematic of such an
orientation with two primary axes a 1 and a 2 for real space and b 1 and b 2 for reciprocal space lattices.
Figure 55 (a) Real space and (b) reciprocal space unit vectors for triangular lattice of holes in a photonic crystal lattice
formation.[113]
To get an understanding of the optical properties of such a lattice, we begin with Maxwell’s
equations below for a source-free medium. These equations assume that the material is isotropic
and therefore 𝘀 and 𝜇 are scalars. Furthermore, it is also assumed that the field intensities are small
79
enough that material oscillator response is linear and non-dispersive, ignoring frequency
dependence of permittivity and permeability.
𝛻 × 𝐸 (𝑟 ) = −𝑖𝜔 𝘀 0
𝐻 (𝑟 ) (3.1)
𝛻 × 𝐻 (𝑟 ) = −𝑖𝜔 𝜇 0
𝐻 (𝑟 ) (3.2)
𝛻 ∙ [𝘀 (𝑟 ) 𝐸 (𝑟 )] = 0 (3.3)
𝛻 ∙ 𝐻 (𝑟 ) = 0 (3.4)
An eigenvalue equation can be derived from these time-harmonic equations and results in
1
𝘀 (𝑟 )
𝛻 × [𝛻 × 𝐸 (𝑟 )] =
𝜔 2
𝑐 2
𝐸 (𝑟 ) (3.5)
𝛻 × [
1
𝘀 (𝑟 )
𝛻 × 𝐻 (𝑟 )] =
𝜔 2
𝑐 2
𝐻 (𝑟 )
(3.6)
The periodicity of the dielectric material caused by the formation of the holes implies that
translation by a primitive lattice vector 𝑹 only results in the accumulation of phase and that the
permittivity is simply 𝘀 (𝑟 + 𝑹 ) = 𝘀 (𝑟 ). This allows the introduction of Bloch functions to define
the electromagnetic fields and can be solved by the eigenvalue equations shown above. Numerical
methods such as finite-difference time domain have been developed to solve these complex
equations.[113, 114] A convention of expressing photonic crystal lattice dimensions is the ratio of
the inter-hole spacing of the lattice, 𝑎 , and the radius of holes, 𝑟 . The plot shown in Figure 56 is
for the TE z-polarized modes of a 2-D triangular lattice of holes, showing frequency as a function
of propagation constant along the directions of symmetry, as defined in Figure 55. The photonic
bandgap can be seen between the first two bands for normalized frequency in the range of 0.28 −
0.31. It should be noted that this is for a 2-D cavity that extends indefinitely in the third dimension.
80
Figure 56 Photonic band diagram of TEz modes for a 2-D triangular photonic crystal lattice.[113]
3.1.2 Optical Properties of Photonic Crystal Membranes, Cavities, and Waveguides
In experimental practice, photonic crystal lattices are formed in a membrane of semiconductor
material that is on the order of 200 − 300 𝑛𝑚 thick for operation in the 1.5 𝜇𝑚 wavelength range.
This alters the band diagram previously derived since, in this condition, light is vertically confined
to the semiconductor by total internal reflection due to index contrast. Although the general trends
of the band diagram do not change, modes will leak into the radiated modes of the lower index
substrate, thus limiting the frequency of guided modes. In order to prevent this leakage, a
membrane of semiconductor material can be formed by selectively etching the material
above/below to allow for vertical air confinement for maximal index contrast. An example of this
approach is for a 225 𝑛𝑚 silicon layer on top of a buried oxide. Once the lattice holes are formed,
selective wet etch removes the oxide underneath the silicon layer, leaving an air-suspended silicon
membrane. The band structure for such a device is shown in Figure 57 where the shaded regions
indicated radiation due to vertical index contrast. This plot also compares the results as obtained
by FDTD and Finite-Element Method approach.
81
Figure 57 Photonic band structure for a suspended membrane photonic crystal.[113]
As seen, the photonic crystal lattice has a high reflection for a range of frequencies in the bandgap,
as determined by the physical dimensions of the holes. The 2-D lattice can be perturbed as well by
the removal of holes to form cavities that can be sub-wavelength in dimension. This is of great
interest as it lends itself very well for cavity formation in applications for lasers and can be
extended to making defect waveguides in photonic crystal lattices with unique characteristics.
Derivations of the electromagnetic states and bandstructures of photonic crystal lattice waveguides
have been done previously by numerous texts and publications, and for continuity of work, this
thesis follows the convention done in the thesis of MPDG alumni Dr. Wan Kuang.[115] Of
particular interest to the work presented in this thesis is the formation of a cavity referred to as a
double hetero-structure. These cavities are formed by first removing a row of holes in the lattice.
Then for a specific region, the remaining holes are perturbed, either in diameter, lattice position,
or both. This alters the photonic band structure for that region, allowing for high intensity local
fields to build due to reflections. A schematic is shown in Figure 58. For a narrow range of
frequency, only region II supports modes and the lattice in region I acts as high reflection mirrors
82
for the Γ − 𝐽 direction, with the lattice holes providing reflection along Γ − Χ. This technique has
demonstrated experimental Q-factor on the order of 6 × 10
5
for such a cavity.[116].
Figure 58 Schematic of a double heterostructure cavity formed in a photonic crystal lattice.[116]
By removing a row of holes in the lattice, a waveguide can be created where the light is confined
vertically by index contrast between air/semiconductor (for a suspended membrane) and confined
in-plane by the photonic crystal holes. The band structure of such a waveguide has been calculated
by Finite Element Method[17] and is shown in Figure 59 where the solid lines represent the
waveguide modes. The light line is also shown by a dashed line.
83
Figure 59 Finite-Element Method band structure calculation of a photonic crystal waveguide.[17]
A unique advantage of photonic crystal waveguides is the ability to customize the dispersion
relationship of the waveguide mode. From the above figure, we can note that for wavevectors
approaching the zone edge (near 0.5), the dispersion relationship becomes very flat, a region that
is often referred to as slow light. This is in reference to the group velocity of such modes, as defined
by 𝑣 𝑔 = 𝑐 𝑛 𝑔 = 𝑐 ∙ (𝜕𝜔 𝜕𝛽 ⁄ ) ⁄ . These modes have unique applications for phase modulation due
to such low group velocities which enhance phase accumulation as compared to conventional rib
waveguides. However, as these modes approach the photonic bandgap, reflection from the facets
and lattice become quite high, increasing the cavity Q-factor. Therefore, transmission for these
modes is very low, making it an engineering challenge to effectively couple to/from these modes.
Figure 60 shows a calculated transmission diagram with the associated band diagram of a photonic
crystal waveguide.[114]
84
Figure 60 Band diagram of modes and transmission for a photonic crystal defect waveguide.[114]
3.2 PHOTONIC CRYSTAL OPTICAL DATA LINK COMPONENTS
3.2.1 Photonic Crystal Cavity Lasers
For truly successful industry adaptation of photonic crystal-based devices, an efficient laser
component is fundamentally necessary. On-chip optical sources must be compact in device area
and have both high internal and external efficiency to ensure high output power (> 100 𝜇𝑊 ) with
a low threshold for operation in the several Gigahertz range. Lasers based in photonic crystal
architecture offer small footprints and have demonstrated electrical injection[117] and CW
operation at room temperatures for an optically pumped cavity.[118] The main challenge in
photonic crystal lasers, as in any high-Q laser cavity, is efficient out-coupling of the lasing modes
that maintain a low threshold. As shown previously, photonic crystals can have very low in-plane
loss as compared to the vertical direction. By intentionally increasing the in-plane loss by design
of the lattice holes, one can favor radiation of the lasing modes to one direction to maximize output.
85
One such technique involves the formation of a single-hole cavity in a photonic crystal lattice.[119]
This cavity is then placed a few lattice periods away from a single row defect waveguide. The
lasing modes will couple to this waveguide and the magnitude of the field in the waveguide region
is a function of the distance between the defect and the waveguide. This is shown in Figure 61.
Figure 61 SEM image of a defect cavity placed a few periods away from a single defect waveguide in a photonic crystal
lattice.[119]
Another approach to tailoring the in-plane loss to favor a desired direction is by the use of hetero-
structure lattices described previously, as done at USC by MPDG alumni Tian Yang[120]. The
photonic crystal lattice was made in a GaAs substrate and incorporate InAs quantum dots as the
active material. By using a single line defect and varying the lattice spacing, two regions were
created. Shown in Figure 62, the ‘cavity’ and ‘output waveguide’ region have the same lattice
spacing and as do the two mirror regions. Using FDTD calculations, this cavity has a passive Q-
factor on the order of 10
5
. By optically pumping the quantum dots in the cavity region, lasing
modes preferentially leaked into the output waveguide region. This was designed by the number
of periods used in the mirrors and calculated that 80% of the total laser power emitted from the
facet of the shorter mirror.
86
Figure 62 SEM of a photonic crystal double hetero-structure cavity.[120]
These lasers, while demonstrating the ability to design in-plane loss for preferential directional
coupling, have complex fabrication processes that will present a challenge for incorporation into
a photonic integrated circuit. The main challenge comes from absorption of the lasing wavelength
by the surrounding semiconductor material. In the approach presented in Figure 61, this was
circumvented this by the butt-joint regrowth method. This method involves the growth of one
material type for the III-V quantum wells (InGaAsP in this case), followed by removal of a
dielectric mask and regrowth of another material (InAs). This complex process ensures that light
coupled to the waveguide material is below its bandgap and therefore not absorbed. The results
shown for the device in Figure 62 don’t suffer this issue since they use InAs quantum dots who
emit below the bandgap of the GaAs photonic crystal semiconductor. However, a present challenge
for quantum dot lasers is their electrical injection for continuous operation.
3.2.2 Quantum Well Intermixing
Another method to solve the absorption issue is by quantum well intermixing.[121] This was
worked out by MPDG alumni Dr. Ling Lu, similar to studies done in the past [122], and the key
87
results are highlighted. Quantum well intermixing relies on disordering of quantum wells by three
main approaches of 1) ion implantation, 2) dielectric capping, and 3) laser-induced intermixing.
Details and results for ion implantation are presented here and the reader is directed to the thesis
of Dr. Ling Lu for further details on the other two approaches.[123]
Ion implantation, as the name suggests, relies on the bombardment of the III-V lattice with high-
energy ions which disorder the lattice by creating point defects. By using a thick (> 150𝑛𝑚 )
dielectric capping layer, areas where intermixing occurs can be controlled to only regions of
interest. The quantum wells/barriers used in these experiments were formed by varying
concentration of phosphorous species in the InGaAsP material. This is a key detail in determining
the ion species to use for intermixing. As a result, P
+
ions were used and incident at 7° with respect
to normal. It’s important to tilt the sample slightly for otherwise, the ion species will find channels
and penetrate the lattice without causing disordering. The ion energy, 10 𝑘𝑉 in this case,
determines the penetration depth of the ions and is a function of the thickness of the capping layer
on the quantum wells. Figure 63 shows photoluminescence spectra of the sample from before and
after the intermixing process. Two key parameters of note are the spectral bandwidth afforded by
the intermixing process, as well as the spatial resolution. The upper portion of Figure 63 shows the
peak wavelength of the as-grown sample at ~1.5 𝜇𝑚 . Following the implantation step, a rapid
thermal anneal is performed on both an as-grown sample and the intermixed sample for a direct
comparison. From the difference of the ion-free (non-implanted) and ion-implanted sample, we
see ~80 𝑛𝑚 blue shift in the peak absorption of the quantum wells. This shift is an important
factor as it represents the bandwidth of such a technique for enabling multiple lasers at varying
wavelengths near 1.5 𝜇𝑚 for wavelength-division multiplexing applications.
88
Figure 63 Photoluminescence of the Quantum Wells from before and after the intermixing process.[123]
To determine the spatial resolution of this technique, regions of the quantum wells were masked
by a SiN dielectric mask with stripes of varying width. The bottom portion of Figure 63 shows the
photoluminescence spectra of samples post implantation and thermal anneal for stripes of 1 −
4 𝜇𝑚 wide after the dielectric is removed. The sample is optically excited at the interface of the
stripe-defined boundary and we can see as the stripe width decreases, the longer wavelength peak
begins to drop relative to the short wavelength peak. This is attributed to lateral diffusion of
implanted ion species which causes disordering in the region masked by the stripe. This experiment
then determines that the spatial resolution for this technique to a minimum in the range of 2 −
3 𝜇𝑚 .
89
Quantum well intermixing was then incorporated into the fabrication process of a double hetero-
structure, optically pumped lasers with the intention of improving slope efficiency and optical
power extraction. Figure 64 shows a schematic of the double hetero-structure lattice which has a
passive Q-factor of 2.65 × 10
5
as calculated by FDTD. Devices with the same structure design
were previously fabricated without quantum well intermixing and showed a peak output power of
500 µW.
Figure 64 Quantum well intermixed sample with a double hetero-structure laser cavity for optically pumped lasers.[123]
Figure 65 shows the results of the two different lasers with and without intermixing. An
improvement by a factor of 2.37 on the slope efficiency is observed and is attributed to the reduced
absorption of the mirror cladding in the device. Quantum well intermixing is not only important
for improving laser performance, but it also enables the integration of active and passive
components onto one material layer. By shifting the absorption peak of the quantum wells,
generated laser light can propagated with drastically lowered absorption loss into other
components for modulation and opto-electronic detection. Development of quantum well
intermixing is a key step to enable on-chip photonic integrated circuits using III-V materials in
photonic crystal device architecture.
90
Figure 65 Light-in Light-Out curve of photonic crystal double hetero-structure cavities with and without quantum well
intermixing.[123]
The results presented above for quantum well intermixing were extended by Dr. Ling Lu[124] to
a proposed scheme of a double-hetero-structure laser cavity coupled to an intermixed waveguide
for high-efficiency coupling, while maintaining a high cavity Q factor. The design schematic is
shown in Figure 66 where an optically pumped laser cavity is placed in close proximity to a
waveguide extending to an intermixed passive region. The output of this waveguide is then
designed to optimize the free-space coupling of the guided mode to microscope objective lenses.
The lattice constant of the laser cavity, 𝑎 ′, differs from the rest of the lattice to form the double
hetero-structure design. The waveguide defect width, 𝑤 as shown in the figure, is a degree of
freedom to optimize the coupling efficiency of the cavity to the waveguide by tuning the
waveguide dispersion for a fixed frequency of light emission. The placement of the waveguide
relative to the double hetero-structure cavity is another design factor, optimized by 3D FDTD
simulation. The starting point of the waveguide presents a trade-off between cavity Q and coupling
91
efficiency. For the proposed design, coupling efficiency of 93% was achieved while maintaining
a cavity Q of > 10
3
. This design also introduces a taper at the waveguide termination to improve
the far field emission directionality for optimal collection by a lens.
Figure 66 Schematic of a double hetero-sctructure cavity laser coupled to a passive intermixed waveguide.[124]
3.2.3 Photonic Crystal Integrated Circuit Components
Passive components in photonic crystal architecture have also been developed for use as building
blocks of photonic integrated circuits. In MPDG, FDTD simulation was used to design a y-branch
using a photonic crystal lattice.[17] This is a critical component for building interferometers and
for otherwise channeling light on-chip. These components were subsequently fabricated and
experimentally demonstrated 95 % splitting efficiency for the intended design bandwidth. They
were used as a component in building an asymmetric MZI in a photonic crystal lattice. Figure 67
is an SEM image of such an MZI and Figure 68 shows the Fourier transform of the observed
transmission spectrum of the device. This device was built with a path length difference of 75 𝜇𝑚 ,
and the resonance peak of 502 𝜇𝑚 in the Fourier transform corresponds to a group index of 6.7,
as determined by the band structure of the photonic crystal lattice.
92
Figure 67 SEM image of an asymmetric MZI in silicon with a photonic crystal lattice.[17]
Figure 68 Fourier transform of the optical output of the MZI[17].
Silicon modulators based MZI device architecture with rib waveguides have been used
successfully for optical modulation up to 60 𝐺𝑏 /𝑠 .[125] The development of such a device within
photonic crystal lattice structure is a promising step for the future of this technology. As mentioned
before, photonic crystal waveguides offer a unique advantage of dispersion tailoring and allow the
propagation of modes with group indices greater than 10, which can be advantageous for phase
modulation schemes. Modulation by interferometry (like an MZI, for example) rely on a plasma
interaction mechanism to induce a phase difference between the two arms by interaction of the
93
electromagnetic wave with the free carriers. This can be done by inserting a PN junction in one or
both of the paths of the MZI and by biasing them in either reverse or forward bias to alter the
electron/hole population in the semiconductor material. When operated in reverse bias, or
depletion mode, the index of refraction of silicon is modulated by the variation in the depletion
width as the diode ranges from 0 𝑉 to 1 𝑉 reverse bias. For typical applications, the index of
refraction difference, Δ𝑛 is on the order of 1 × 10
−4
. For a given electromagnetic wave with
components in the (x,y) plane, propagating in the z-direction with 𝑒 𝑖 2𝜋𝑘𝑧 𝑛𝜆 ⁄
, the phase difference
is determine by
𝛿𝜙 = 𝐿 ∙ 𝛿𝑘 ≅ 𝐿 ∙
𝛿𝜔
𝑑𝜔
𝑑𝑘
⁄
≈
𝐿𝜔𝜎𝛿𝑛 𝑛 𝜈 𝑔
(3.7)
Here, 𝜎 represents the mode overlap with the region of index change. From Eqn. (3.7), we can
solve for length at a given value of index change, represented by 𝛿𝑛 , and arrive at
𝐿 𝜆 𝑎𝑖𝑟 ≈
1
2𝜎 (
𝑛 𝛿𝑛
) (
𝜈 𝑔 𝑐 ) (3.8)
From Eqn. (3.8), we can see that the length scales linearly with group velocity for a fixed index
change. It is typical to achieve a group velocity that is a factor of 10-15 less than the speed of light
in photonic crystal waveguides. Using the aforementioned value of index change, lengths of only
100 − 200 𝜇𝑚 are necessary for a full 360° of phase accumulation necessary for deconstructive
interference in an MZI. This is in stark contrast to 2.5 − 3 𝑚𝑚 needed in a rib waveguide with the
same diode structure. Indeed, this has been exploited and a high-speed, compact asymmetric MZI
modulator based on a photonic crystal phase shifter region has been demonstrated.[126] This
device uses a conventional rib waveguides as the input/output and y-branches and couples to a
photonic crystal lattice for the phase shifter region. The device is shown in Figure 69. They are
94
able to taper the rib waveguide to couple into modes with group indices in the range of 15-20, and
have done high speed modulation for varying lengths of phase shifter regions. The results of the
optical eye diagram for the three longest lengths are shown in Figure 70 for modulation at
10 𝐺𝑏 /𝑠 .
Figure 69 Schematic of a photonic crystal phase shifter in an asymmetric MZI.[126]
Figure 70 Optical eye diagram of a 10 Gb/s data pattern on a photonic crystal-based modulator.[126]
3.3 PROPOSED DEVICE
3.3.1 Conceptual Device Integration Scheme
The device proposed in this thesis extends the knowledge built in MPDG of photonic crystal-based
devices by attempting to combine the components to build a photonic integrated circuit. As was
previously described, components such as integrated light sources, transparent waveguides, Y-
branches, asymmetric MZI, and even modulators have been demonstrated in photonic crystal
device architecture. What remains is the ability to integrate a photodetector to complete the data
95
link. In §1.1.5, various designs of photodetectors that are used in conventional optical data links
were outlined. These PDs can be classified as normal incidence or in-plane incidence cavities, each
with respective advantageous based on their application. The bandwidth-efficiency of in-plane
geometries such as waveguide photodetectors (WGPD) was explained to be higher than normal
incidence detectors since the direction of optical carrier generation and collection were orthogonal.
These devices, however, suffer from overall inefficiency since the optical signal is incident into
the cavity from an external source, resulting in poor spatial overlap of the optical mode and
waveguide. For an application such as an on-chip optical data link, the optical signal never leaves
the semiconductor chip, circumventing this obstacle. Therefore, a properly designed input
waveguide for the photodetector is expected to have minimal insertion loss.
Figure 71 shows a top view schematic of the proposed integration of a WGPD in a photonic crystal
device architecture. The semiconductor material is an InP substrate with four compressively
strained quantum wells (QW) of In 0.74Ga 0.26As 0.75P 0.25 and barriers of In 0.75Ga 0.25As 0.54P 0.46 which
are capped with a 60 𝑛𝑚 layer of n-type doped InP. The QWs are designed for emission at
1.55 𝜇𝑚 wavelength. The envisioned integration scheme is one where an electrically injected laser
with a transverse junction is used to generate light that is preferentially coupled into a region of
the semiconductor that has been intermixed by ion implantation to shift the absorption peak. This
region is indicated schematically in Figure 71 by the red rectangle. Within this intermixed region,
various passive and active components can be inserted to create directional couplers and/or y-
branches to form MZIs which can be used for modulate, or to otherwise manipulate, the optical
signal. This signal is then routed to a non-intermixed region where carriers are generated within
the QW region. These carriers are then swept out of the active region by a reverse biased transverse
P-i-N junction comprising of the photodetector. An immediately apparent advantage of such a
96
scheme is the elimination of external coupling of the optical signal to the active region of the
WGPD. This decreases the optical signal loss, relieving power output requirements that would
otherwise be placed on the laser light source.
Figure 71 Top view schematic of an integrated optical circuit in photonic crystal lattice architecture.
3.3.2 Device Design
The photonic crystal lattice used for the proposed devices has the same dimensions as the lattice
used for work done previously in MPDG to ensure compatibility and continuity. The target
wavelength is 1.55 𝜇𝑚 with a lattice that has a ratio 𝑟 𝑎 ⁄ = 0.3 with 𝑟 = 150 𝑛𝑚 and a lattice
spacing 𝑎 = 450𝑛𝑚 . The combined thickness of the four InGaAsP quantum wells and barriers is
a total of 220 𝑛𝑚 . To ensure proper cavity design, the transmission spectrum of an air-suspended
membrane, single-defect waveguide was simulated using Lumerical’s FDTD software package,
and is plotted in Figure 72. It should be noted that this transmission spectrum was calculated by
placing a dipole source inside the cavity and therefore does not include coupling effects to the
photonic crystal waveguide facet. It can be noted that the target wavelength is below the cut-off
frequency of the photonic crystal band structure, as intended.
97
Figure 72 Transmission spectrum for an air-suspended photonic crystal waveguide.
As mentioned, the III-V substrate has a 60 𝑛𝑚 cap layer that is grown to be n-type, designed to
serve as the anode of the lateral P-i-N junction. In the past, a semi-lateral junction has been
attempted by first growing a p-type InP buffer beneath the quantum wells and capping them with
an n-type layer.[127] In this device design, we propose to compensate the n-type cap layer by Zinc
diffusion from a spin-on dopant source to create the p-type region. A schematic of the proposed
device cross section is shown in Figure 73. It is important that the diffusion region extend into the
quantum wells to ensure efficient extraction of photogenerated carriers from the active region.
Therefore, the target depth of the diffusion is < 300 𝑛𝑚 given the combined thickness of the
capping layer and the quantum wells which comprise the suspended membrane. The triangular
shape in Figure 73 is due to the etch-stop planes in InP due to a selective wet etch with HCl used
to create the suspended membrane. It is also denoted that the diffusion source will compensate the
n-type cap layer to a p-type material, as has been shown experimentally in the past.[128]
98
Figure 73 Cross section of proposed photonic crystal photodetector device.
Aside from careful formation of the junction depth and concentration, the dimensions and positions
of electrical contacts must be carefully considered. The 3D schematic of the proposed device is
shown in Figure 74. As previously described in §1.1.5, similar designs of a waveguide
photodetectors were able to achieve high bandwidth-efficiency factors with device lengths on the
order of 7 𝜇𝑚 in similar material systems. The optical absorption coefficient for 1.55 𝜇𝑚
wavelength light in InGaAsP is ~2 × 10
4
𝑐𝑚
−1
, which corresponds to a 1 𝑒 ⁄ absorption length of
< 1 𝜇𝑚 . Therefore, for a devices on the order of microns in length, majority of the light coupled
to the waveguide photodetector will be collected while enabling high modulation bandwidth.
Figure 74 3D schematic of the proposed device with electrical contacts.
The lateral position of the electrical contacts relative to the waveguide defect is another point of
careful design. In order to prevent interference with the optical mode due to the contact metals, a
99
minimum distance should be maintained. From FDTD simulations done via Lumerical software,
it was calculated that the electric field of the propagating mode is below 1 % intensity after 10
periods of the lattice holes. Given the lattice dimension previously mentioned, this corresponds to
a distance of ~7 𝜇𝑚 from the center of the waveguide defect cavity, setting a contact separation
of 14 𝜇𝑚 . As carriers are generated within the waveguide defect and swept laterally due to the
applied reverse bias, it is hypothesized that surface recombination at the regions where the
photonic crystal holes are formed can lower the extraction efficiency of the device. Therefore,
devices with varying contact separation from the defect waveguide are planned for experiment to
quantify this effect. As shown previously, optically pumped photonic crystal lasers in the same
material system demonstrated ~500 𝜇𝑊 of edge-emitted output power. If in a demonstration of
the integration scheme where such a laser is coupled to a transparent waveguide and directed into
the WGPD resulted in an estimated −10𝑑𝐵 loss, the power in the cavity would be 𝑃 = 50 𝜇𝑊 .
Assuming the optical absorption coefficient of 𝛼 = 2 × 10
4
𝑐𝑚
−1
, the estimated photocurrent at
𝜆 = 1.55 𝜇𝑚 would be
𝐼 𝑝 ℎ
=
𝛼𝑃𝜆𝑞 ℎ𝜈 ≅ 200 𝜇𝐴
(3.9)
where 𝑞 is the elementary charge of an electron. This sets an estimated range of expected current
assuming ideal internal and external efficiency, and this value is above the noise floor of
experimental tools used for current measurement.
The position of the diffusion region for the p-type dopant source relative to the waveguide defect
is also another factor to be considered for this device design. This interface, as measured from the
defect, determines the average distance of drift for generated holes in the intrinsic QW region
before being swept away as majority carriers in the p-region, which can also impact both
100
bandwidth and responsivity of the photodetector. Assuming a contact separation of 14 𝜇𝑚 as
mentioned above, four positions for the position of the diffusion interface are experimentally
planned for device fabrication, as shown in Figure 75. The electrical contacts are shown on the
outside of the lattice holes, in gold. Four vertical lines designate a distance from the waveguide
defect center with one at the center, follow by a separation of 2 𝜇𝑚 ,4 𝜇𝑚 and 6 𝜇𝑚 away.
Figure 75 Top down schematic showing four boundaries for the p-type diffusion region.
3.4 PROCESSING AND EXPERIMENTAL RESULTS
3.4.1 Key Aspects of Device Fabrication
To form the transverse junction, Zinc was chosen as the species of diffusion for the p-type region,
which has also been reported to compensate the n-type InP, as is the case with the cap layer for
these devices.[128] Zinc diffusion in InP is comprised of two mechanisms i) the Fair vacancy
model and ii) the Frank-Turnbull, or substitution-interstitial (S-I), model of diffusion.[129] In the
Fair vacancy process[130], the Zn atom is trapped/releases by a group III atom vacancy on the
lattice. The S-I process is one where the Zn atom is trapped/released between the lattice sites.
101
These two mechanisms yield unique characteristics of the Zn dopant profile versus depth. Such a
plot is shown in Figure 76, where Zn 3P 2 is diffused into semi-insulating InP in a closed ampoule
as heated in a furnace. The two arrows indicate the key features of a plateau region, typically a few
hundred nanometers in depth, followed by a sharp exponential drop. The source solubility,
diffusion temperature, and time determine the magnitude and depth of the plateau region. The rate
at which this concentration drops off, and the overall junction depth, is also determined by the
background doping type and concentration of the semiconductor material.
Figure 76 Zn3P2 diffusion depth profile for a fixed temperature at given time values.[129]
A consequence of the complex diffusion mechanism of Zinc in InP is that a theoretically calculated
diffusion constant would not give correct results. Therefore, experiments done with techniques of
various dopant sources and diffusion methods have been conducted to quantify an empirical value
for Zinc diffusion constant. Table 1 shows the results from some of these works. The dopant source
102
is either a spin-on solution that is hardened by a bake before the diffusion process or a film
containing Zinc that is deposited via sputtering or electron-beam evaporation. The diffusion
processed was then either carried out in a furnace, sealed ampoule with in furnace, in a rapid
thermal anneal (RTA) furnace, or by using a stripe heater.
Table 1 Summary of various results of Zinc diffusion in InP.
Depth
(𝒏𝒎 )
Temp
(°𝑪 )
Time
(𝒔 )
Diffusivity
(𝒄𝒎
𝟐 𝒔 ⁄)
Source
Type
Diffusion
Method
Ref.
250 650 30 2 × 10
−11
Spin-on Furnace [131]
800 670 100 8 × 10
−11
Spin-on Furnace & RTA [132]
700 650 15 8 × 10
−11
Spin-on Ampoule [133]
500 560 45 1 × 10
−10
Deposit RTA [129]
1000 700 10 1 × 10
−9
Spin-on Stripe Heater [134]
The work done in ref. [132] gave detailed process steps for the experiments done and used a
commercially available Zinc Silica (Emulsitone Company) solution as the dopant source.
Therefore, their experimental techniques were chosen as a basis for diffusion experiments for the
proposed device. A spin-on source can act as an inexhaustible source of dopant material up to
temperatures of 700 °𝐶 , where the peak concentration at the surface of the material is dependent
on the initial film thickness, as plotted in Figure 77[131] The film thickness also has technological
implications for fabrication processes. Due to thermal coefficient mismatch between the two
materials, if too thick a layer is used, there will be severe cracking and peeling during the anneal
process, resulting in damage underlying III-V material. For the experiments done, it was found
that film thicknesses in the range of 50 𝑛𝑚 were able to withstand the slow ramp up/down steps
of the anneal process and showed no cracking afterwards. The details of the process are discussed
in the appendix.
103
Figure 77 Peak zinc concentration as a function of film thickness for a spin-on dopant source.[131]
To estimate the diffusion depth as a function of temperature and time, we can use the reported
diffusivity value for Zinc in InP. It is also reported that Zinc diffusion process has a temperature
threshold of ~400 °𝐶 , below which there is no significant amount of penetration of the Zinc
dopant source into the material.[129] A typical temperature versus time profile of an RTA process
is shown in Figure 78 where 𝑇 𝑖 is the initial temperature, often room temperature, and 𝑇 𝐴 is the
annealing temperature. The process is represented by three phases: 1) ramp up 2) anneal and 3)
cool down, represented in time by 𝑡 1
, 𝑡 𝐴 and 𝑡 3
, respectively.
Figure 78 Typical temperature vs. time profile for an RTA process.
104
To prevent damage to the material, the lowest allowable ramp up/down rates for the RTA machine
were used, at 1 °𝐶 /𝑠 , which determined the slope of the lines shown in region 1 and 2 of Figure
78. We can use an effective diffusion time 𝑡 𝑒𝑓𝑓 , which is the time the sample spends above 400 °𝐶 ,
to theoretically calculate the overall diffusion depth. The final junction depth can be estimated
using the equation below
𝐷 𝑡 𝑒𝑞
= ∫ 𝐷 0
𝑒 −𝐸𝑔
𝑘𝑇 (𝑡 )
𝑑𝑡
𝑡 𝑒𝑓𝑓 0
(3.10)
where 𝐷 0
is the experimental diffusivity value, 𝑇 (𝑡 ) is the temperature as a function of time, and
𝐸 𝑔 is the activation energy of dopants in III-V material, reported to be 1.44 𝑒𝑉 ± 0.22 𝑒𝑉 .[132]
Using the slow ramp rate and diffusivity value mentioned, for 𝑇 𝐴 = 600 °𝐶 , and for 𝑡 𝐴 = 0 to
understand minimum depths attainable, Eqn. (3.10) results in a final depth on the range of
~300 𝑛𝑚 . Since the photonic crystal membrane that is intended for this device is 260 𝑛𝑚 thick,
this junction depth is sufficient.
To mask regions where diffusion is not wanted, 150 𝑛𝑚 thick layer of SiN deposited by CVD is
used. Lithography is used to pattern PMMA and that pattern is transferred to the SiN by an RIE
dry etch. The zinc silica source is spun on at 6500 𝑟𝑝𝑚 for 35 𝑠 and hard-baked on a hot plate at
200 °𝐶 . The sample is then annealed in an RTA using the above temperature/time profile. The
sample is then dipped into Hydoflouric Acid (HF) to remove both the hard mask and spin-on
diffusion source. Figure 79 shows an SEM of a diffusion region interface. The lower right region
is where the mask was opened for diffusion. The grainy texture is a result of surface damage during
the anneal and can be attributed to out-gassing of phosphorous species from the InP material.[135]
The upper left portion of this figure was masked during the anneal process and shows no such
105
surface damage. It must also be noted that the damage due to the diffusion is in the InP cap layer
only and does not impact the InGaAsP active region where the optical mode will be focused.
Figure 79 SEM of a diffusion region interface on an InP sample.
Following the formation of the junction by diffusion, the photonic crystal lattice is fabricated. This
process begins by a deposition of a second SiN hard mask followed by PMMA spin-on for e-beam
lithography. The photonic crystal hole pattern is written in the PMMA, developed and the PMMA
film is then re-exposed to harden the material. This re-exposure is a crucial step in maintaining
vertical sidewalls during subsequent etching of the photonic crystal hole pattern by preventing
mask erosion. The pattern is then transferred into the SiN layer via an RIE dry etch and the PMMA
is removed with an Acetone wash. To etch the holes into the underlying III-V layer, an ICP etch
recipe based on BCl 3 carrier gas is used, at a stage temperature of 165 °𝐶 . This temperature was
found to be crucial for a clean InP etch and is a threshold to prevent surface passivation due to the
etch by-product compound In xCl y. At lower etch temperatures, this compound re-deposits on the
InP surface after initial etching has begun, passivating the surface, and preventing further etching.
Above a temperature of ~160 °𝐶 , enough thermal energy is maintained, preventing these
106
passivation atoms from binding to the surface of the InP material, which greatly decreases the etch
rate. An advantage of using an ICP tool versus an RIE etch tool is the independent control of the
power levels for the platens and the magnetic coils that surround the chamber. The specific etch
mechanisms of ICP are outlined in literature[136] and should be read for a full understanding.
Specifically, the platens, which vertically surround the etch chamber, control the etch rate by
increasing population of reactive etch ions with increased RF power. This comes at the expense of
decrease anisotropy. The magnetic coils surrounding the etch chamber, in turn, control the
directionality of the reactive ions and improve both anisotropy and etch rates. These parameters
were experimentally optimized for the ICP tool in the USC cleanroom and should always be
calibrated as they are subject to etch chamber conditions.
For the proposed device, it is paramount to maintain as anisotropic of an etch possible to prevent
increasing hole diameter since the final 𝑟 𝑎 ⁄ ratio determines the optical characteristics of the
photonic crystal waveguide. An expansion of the photonic crystal hole diameter throughout both
the SiN hard mask etch and the III-V etch, however, is inevitable. The precise etch recipe
parameters outlined in the appendix are for process steps that have been fully characterized, and
thus have a predictable increase in 𝑟 𝑎 ⁄ ratio. Therefore, the initial photonic crystal hole pattern
written by the e-beam lithography step accounts for this bias by writing holes at a smaller ratio
than desired. The target etch depth is ~1 𝜇𝑚 , as this was the depth that experimentally showed the
best undercut wet etch result, which will be discussed in the subsequent paragraphs.
After the ICP etch, traditional lithography and lift-off techniques were followed to deposited metal
contacts for the p-type and n-type region with Ti/Pt/Au and AuGe/Ni/Au, respectively. In order to
form the suspended membrane, a selective wet etch between InP and InGaAsP with Hydrochloric
(HCl) acid at 0 °𝐶 is used.[137] However, the Titanium metal used for the p-type contact is
107
attacked by this acid, and therefore, a PMMA layer is spun on prior to the wet etch to encapsulate
and protect the metal. This PMMA layer also protects the InP cap layer underneath both of the
metal contacts. The wet etch that undercuts the InGaAsP membrane works best when there are
open box regions at the end of the photonic crystal cavity that have been etch down ~1 𝜇𝑚 . The
photonic crystal holes also allow the acid to penetrate into the underlying InP material. There are
etch-stop planes in InP that prevent a complete undercut of the membrane. To overcome this, the
triangular lattice photonic crystal hole pattern should be oriented along the <01-1> direction,
perpendicular to the etch-stop planes. Details of this chemical wet etch implemented in the USC
cleanroom were experimentally characterized in detail in the thesis of MPDG alumni Dr. J.R. Cao,
and should be referenced for further detail.[127] Figure 80 shows SEM images of the suspended
membrane photonic crystal cavity with metal contacts on either side. The v-groove underneath the
membrane is a consequence of the previously mentioned etch-stop planes in the InP substrate.
Figure 81 is an SEM image showing the input facet of this cavity. The vertical sidewalls are a
consequence of the fine-tuned ICP dry etch.
Figure 80 InGaAsP suspended photonic crystal cavity with planar metal contacts.
108
Figure 81 Close view of the input facet of the suspended membrane cavity.
3.4.2 Preliminary Results
In order to fully characterize the PN junction formed during the diffusion process, the doping
concentration of the p-type diffused layer must be experimentally verified. There are various
methods to do this, such as secondary-ion mass spectroscopy, scanning resistance probing, and
transmission line method (TLM), and Hall measurements. The first two of these require specific
equipment not available within the USC facilities. TLM devices are relatively easy to fabricate
and can be used to extract resistance of a material as a function of distance between two metal
contacts. However, an added process step necessary for traditional TLM devices is the formation
of a mesa to restrict the current flow to a predetermined region, necessary for accurate calculations
of resistance. The contact spacing must also be far enough apart to prevent errors in calculation
due to fringing electric fields. Another type of TLM device that circumvents these effects is the
circular-TLM (C-TLM) device.[138] This device comprises of concentric, circular metal contacts
at specific gaps that are used to measure resistance as a function of distance. The concentric
orientation of the circular contacts eliminates the error effects of fringing fields and the formation
of a mesa. There is a conversion factor to account for this circular shape to give true values of
109
resistance versus distance, as outlined in the reference. The device schematic is shown in Figure
82 with an SEM of the fabricated devices in Figure 83.
Figure 82 Schematic of c-TLM devices used for extraction of material resistance versus distance.[138]
Figure 83 SEM image of fabricated c-TLM devices on InP.
The III-V material used for the proposed device was grown by MOCVD by students in Dr. Dapkus’
CSL group, and therefore, have a target doping concentration of 1 − 3 × 10
18
𝑐𝑚
−3
for the n-
type cap layer. This was used to initially verify the approach of c-TLM devices by testing for the
material resistance of the InP cap layer. This, in turn, will yield sheet resistance, which can be
related to doping levels from experimental results cited in literature.
110
To form the contacts, AuGe/Ni/Au contacts were deposited and annealed at 400 °𝐶 for 60 seconds.
A plot of the resistance versus distance is shown in Figure 84. Using the theory developed in
ref.[138], the slope of this plot yields a sheet resistance of 𝑅 𝑠 = 40 Ω ∎ ⁄ , corresponding to a
doping concentration of ~2 × 10
18
𝑐𝑚
−3
[139], which is well within the expected range. The
contact resistance per metal pad to the substrate is approximately 60 Ω.
Figure 84 Resistance versus contact spacing for c-TLM devices on n-type InP.
With this approach verified, and experimental errors known, it was extended to calculation of the
doping concentration for the p-type diffused region. A square area of 100 𝜇𝑚 × 100 𝜇𝑚 was
etched in the SiN hard mask for diffusion of the Zinc Silica film. After the anneal step for diffusion,
c-TLM pads were deposited with Ti/Pt/Au and annealed for an Ohmic contact formation to the p-
type region. Similar tests as done for the n-type cap region were carried and the resulting plot of
resistance versus pad distance is shown in Figure 85.
111
Figure 85 Resistance versus contact spacing for c-TLM devices on p-type diffused InP
From the slope, we extract a sheet resistance of 250 Ω ∎ ⁄ , corresponding to a donor density of
~8 × 10
17
𝑐𝑚
−3
.[139] This is within the expected range given the 50 nm thick film of Zinc Silica,
as shown in Figure 77. The contact resistance for the metal pads to the p-type InP is on the order
of 150 Ω. To confirm the numbers derived for doping concentration of this material, Hall
measurements were also conducted with the help of CSL alumni Dr. TW Yeh. These results, as
well as those from the c-TLM devices, are summarized in
Table 2 Summary of target and experimental doping concentration for n-type and p-type InP.
Species Target c-TLM Hall meas.
n-type (𝑐𝑚
−3
) 1 − 3 × 10
18
𝑐𝑚
−3
2 × 10
18
𝑐𝑚
−3
3 × 10
18
𝑐𝑚
−3
p-type (𝑐𝑚
−3
) 1 − 5 × 10
18
𝑐𝑚
−3
8 × 10
17
𝑐𝑚
−3
2 × 10
18
𝑐𝑚
−3
After the doping concentrations were confirmed, a lateral PN junction test structures were formed
in the planar material. This device comprised of bulk InP with a region diffused for p-type InP.
112
The respective p-type and n-type layers were then contacted by the recipes mentioned above and
annealed for Ohmic contact formation. The formation of a photonic crystal cavity was not done
for these devices. To test whether the junction demonstrated photo-detection, an 850 𝑛𝑚
wavelength laser with a spot size of 3 𝜇𝑚 diameter was incident normal on the sample between
the two metal contacts, spaced 15 𝜇𝑚 apart, to simulate the distance for the final device. This laser
was chosen due to its availability and high optical power to ensure signal detection for carriers
generated in the waveguide region. The reverse bias portion of the I-V tests done is shown in
Figure 86. From this figure, we can see an increase in current with an increase in optical power,
indicative of a rectifying, photo-collecting junction.
Figure 86 Reverse bias current for PN junction in planar III-V material.
Initial, preliminary tests for the current-voltage relationship of the junction were done and shown
in Figure 87. The turn-on voltage is ~0.95 𝑉 , and is within the expected range for the given doping
113
concentration values and should be noted that for biases above 1.6 𝑉 , the current is above the
compliance value and therefore clipped. It can also be noted that with in the 0 − 2 𝑉 reverse bias
range, the dark current is below the noise floor of the testing instrument, and much lower than the
dark current observed for the planar junction. This is expected to be primarily due to a reduced
current cross sectional area as comprised by the suspended membrane compared to the planar
diodes tested previously. The devices, when tested in the forward bias regime were irreversibly
damaged and showed resistive, linear current conduction when subsequently retested. This is
estimated to be due to break down of the junction as a result of resistive joule heating of the
membrane where, after turn-on, current density on the order of 5 × 10
2
𝐴 𝑐𝑚
2
⁄ flows. From this
data, we see rectification due to the presence of a P-i-N junction. Motivated by the photo-collection
demonstrated by a planar PN junction, future experiments are proposed to characterize this
photodiode for responsivity and modulation.
Figure 87 Current-Voltage behavior of diode with photonic crystal p-i-n junction.
114
3.5 FUTURE WORK
3.5.1 Responsivity Measurement
To test the true responsivity of the proposed photonic crystal membrane photodetector, an
experimental setup must be able to accurately couple light into the cavity with a known insertion
loss. This can be done via traditional methods of cleaving or dicing the sample near the end of the
photonic crystal cavity to expose the facet and use a free-space optical beam incident on the input
facet. However, this technique suffers from high optical insertion loss due to the low spatial
overlap between the optical beam, often 2 𝜇𝑚 in diameter, which is much larger than the
dimension of the input facet which has a low aspect ratio, with dimension on the order of
250 𝑛𝑚 × 750 𝑛𝑚 in height and width, respectively. Furthermore, it is often easy to excite
radiative modes in the underlying substrate with this technique. For coupling to non-absorbing
waveguides in silicon for example, accurate modal excitation can be verified by imaging the output
facet of the photonic crystal waveguide cavity. However, such an approach is not viable for these
absorbing material of the InGaAsP photodetector.
Previously in MPDG, other approaches of coupling light into photonic crystal cavities using
tapered fibers aligned with the cavity defect have yielded optical coupling efficiency greater than
90 %.[140] Figure 88 shows a schematic of such an approach, where a photonic crystal defect
waveguide is formed with fewer cladding periods formed on one side. This enables the light to
evanescently couple into the cavity by bringing an optical fiber within close proximity to the
defect. The photonic crystal lattice holes serve as a grating and couple the light counter-
directionally within the waveguide.[140] A similar approach was worked out by MPDG alumni
Dr. Sarkissian by tapering a fiber that physically rested on top of the defect, yielding optical
efficiency of > 90 %.[141]
115
Figure 88 Schematic of a fiber aligned to a photonic crystal defect waveguide.
A different approach using integrated optical components was developed by IBM where passive
components were used to couple light into the photonic crystal cavity.[142] This approach is
schematically shown in Figure 89. The region denoted as ‘F-S coupler’ is a polymer material that
is a multi-mode waveguide region with micron dimensions that captures free-space or light from
a lensed fiber. This region has a taper which converts adiabatically to single mode from the
polymer to an underlying, similarly tapered Si strip waveguide, denoted by the ‘strip wg’ region.
This strip waveguide has a width dimension of ~400 𝑛𝑚 and must be tapered to a wider region
for coupling to the photonic crystal defect that has a dimensions almost twice as wide; this is
denoted in the ‘S-PhC coupler’ region. The ratio and alignment of the strip waveguide width (W rib)
to the defect width (W phc) is a factor that determines overall coupling loss.[142]
Figure 89 Schematic of coupling scheme to a photonic crystal cavity.[142]
116
To quantify the loss due to the strip/photonic crystal waveguide interface, a similar device as
shown in Figure 89 was fabricated but without a photonic crystal cavity. This was done to measure
relative loss as compared. These results are shown in Figure 90 for cavities of increasing length.
As cavity length is increased, the effects of the photonic crystal bandgap become more pronounced
as non-guided modes are radiated out of the waveguide. For the shorter cavity lengths, coupling
loss of 3 − 4 𝑑𝐵 is expected from experimental measurements.
Figure 90 Transmission loss to photonic crystal cavities of varying lengths.[142]
These coupling schemes can be incorporated to the proposed device of this thesis to accurately
quantify the optical intensity within the photonic crystal cavity. This will then enable to accurate
measurement device responsivity as a function of reverse bias and optical power.
117
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6 APPENDIX
6.1 NANOWIRE DETECTOR PROCESSING DETAILS
Table 3 Process parameters for Nanowire Photodetector fabrication.
Step Tool Parameter Value Unit
Ohmic contact Metal evaporator AuGe thickness 100 nm
Ni thickness 20 nm
Au thickness 100 nm
Ohmic anneal RTA Temperature 400 C
Time 60 sec
Rate 8 C/s
HSQ Infiltration Spinner Spin speed 3000 rpm
Spin time 60 sec
Oxygen Ash Asher RF Power 100 W
Time 15 sec
HSQ Bake Vacuum hot plate Temperature 240 C
Time 30 min
Large Area device fabrication
E-beam ITO Dielectric evap. Temperature 225 C
Rate 0.5 A/s
Oxygen flow 9 sccm
ITO Lift-off
Photoresist spin Spinner Speed 2000 rpm
Time 60 sec
Hot Plate Temperature 100 C
Time 90 sec
Mask exposure Optical aligner Exposure Dose 120 mJ
Image-reverse bake Hot Plate Temperature 120 C
Time 120 sec
Develop 4:1 AZ400K Time 120 sec
Oxygen Ash Asher RF Power 100 W
Time 15 sec
ITO Sputter Sputter tool RF Power 200 W
Time 30 min
Lift-off Acetone Time 20 min
156
The detailed process parameters for fabrication of the nanowire photodetector are given below in
6.2. The first five steps are what comprise of forming the Ohmic contact to the substrate and
infiltration of the nanowire array. The polymer that gave best results for infiltration was HSQ,
purchased from Dow-Corning. This material dries up rather quickly and should be stored in cool
temperatures in an air tight container. The large area of the NW array was contacted with e-beam
evaporated ITO and did not require lift-off. The deposition rate for this step is paramount to ensure
a good quality ITO with a smooth surface. The crucible should be at least 50% full and the
temperature and oxygen flow should stabilize for about 10 minutes before process is started.
Because the e-beam ITO is done at high temperature, lift-off via photoresist is difficult since most
photoresist harden at these temperatures. To circumvent this issue, a sputtered ITO can be used
which is done at temperatures in the range of 30-50°C. To ensure a clean lift-off, image reversal
of the pattern is used on AZ 5214-E photoresist that results in negatively sloped sidewalls of the
photoresist after development. Since sputtered material is conformal, this step is necessary to give
a clean lift-off with sharp edges of the ITO contact pad.
6.2 PHOTONIC CRYSTAL PHOTODETECTOR PROCESSING DETAILS
Table 4 Diffusion process steps for photonic crystal photodetector.
Step Tool Parameter Value Unit
P-type region formation
SiN dry mask CVD RF Power 30 W
Time 15 min
Temperature 275 C
Photoresist spin Spinner Speed 4000 rpm
1 min
Photoresist bake Hot plate Temperature 100 C
Time 90 sec
Diffusion box litho E-beam Fill skip 58
Write speed 70,000
157
Write current 25 pA
Development Wet bench 2:1 IPA:MIBK 60 sec
Zinc silica spin on Spinner Speed 6500 rpm
Time 35 sec
Zinc silica bake Vacuum hot plate Temperature 100 C
Time 10 min
Temperature 150 C
Time 10 min
Temperature 200 C
Time 10 min
Zinc silica diffuse RTA Temperature 550 C
Time 1 sec
Rate 1 C/s
Mask removal Wet bench HF acid dip 30 sec
Table 4 outlines the detailed steps that were developed for diffusion of the Zinc silica source. This
material was purchased from Emulsitone Company. The steps for lithography of lattice holes, their
etch recipes and the formation of metal contacts have been developed elsewhere and were adopted
for the devices mentioned above. It should be noted that the Zinc silica source material dries up
very quickly and should be stored under 25°C.
Abstract (if available)
Abstract
This thesis presents experimental results on a photodetector based on an Indium-Tin-Oxide Schottky-like heterojunction using GaAs nanowire device geometry. By distributing the active detecting area over an array of nanowires, it’s possible to achieve large area detection with low capacitance. Devices with bare GaAs and passivated AlGaAs/GaAs nanowires are also fabricated to compare the responsivity with and without surface passivation. We are able to achieve responsivity of >0.5 A/W and Signal-Noise-Ratio in excess of 7 dB for 2 V applied reverse bias with passivated nanowire devices. Capacitance-voltage measurement yields an overall capacitance of <5 nF/cm², which shows a strong possibility for high-speed applications with a broad area device. To exploit this advantage for operation in the gigahertz range, efficient, low capacitance density GaAs/Indium-Tin-Oxide Schottky-like junction photodetectors with a 50 μm ×50 μm active area are fabricated. Modulation bandwidth is experimentally measured up to 10 GHz at various applied reverse biases and optical intensities to explore the effects of photo-generated carrier screening on modulation bandwidth. Lastly, the bandwidth dependence on applied reverse bias and optical intensity is simulated as a means to quantify average carrier velocities in nanowire material systems. These experiments resulted in a 3 dB modulation bandwidth of 9.1 GHz for 7 V applied reverse bias, corresponding to an average carrier velocity of ~2 × 10⁶ cm⁄s for GaAs nanowires. ❧ An integrated design of a waveguide photodetector using a lateral P-i-N junction in a photonic crystal architecture with previously developed components such as Y-branches and optically pumped lasers is also presented. Fabrication steps are detailed for p-type region formation via an in-house diffusion technique and experimental characterization of the junction shows a p-type peak concentration of 8 × 10¹⁷ cm⁻³ from transmission line method device. Initial experiments also show photo-detection from the resulting junction, motivating future work on this photodetector.
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Seyedi, Mir-Ashkan
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Photodetector: devices for optical data communication
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