University of Southern California Dissertations and Theses

Nanomaterials for macroelectronics and energy storage device

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Nanomaterials for macroelectronics and energy storage device

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Content NANOMATERIALS FOR MACROELECTRONICS AND ENERGY STORAGE DEVICE By Haitian Chen A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2014 Copyright 2014 Haitian Chen ii Abstract In this dissertation, I present my development of an innovative approach to utilize the advantage of the stable semiconducting properties of two materials, carbon nanotube thin films and indium gallium zinc oxide thin film to form circuits operating in complementary. The approach has resolved the following issues. Firstly, carbon nanotube (CNT) thin film transistors (TFTs) behave as p-type transistors in ambient with high work function metal electrodes, such as palladium. And CNT TFTs exhibits desirable transistor behavior showing device mobility and on-current density suitable for macroelectronic applications, which is superior to the commercially available amorphous silicon TFTs. However, in order to operate circuits with low steady-state power dissipation, it is more desirable to have complementary circuits, meaning circuits consist of both p-type and n-type transistors. CNT TFTs can be converted into n-type, however, there has not been a method to realize n-type CNT TFTs with long term stability. On the other hand, oxide semiconductor TFTs have been a well-known high performance n-type TFTs. However, researchers have also struggled to obtain stable and high performance p-type oxide semiconductor TFTs. I demonstrate using CNT TFT, the stable p-type device, and indium gallium zinc oxide (IGZO) TFT, an outstanding n-type device to realize integrated circuits operating in complementary mode with good stability in ambient. I have demonstrated for the first time a large-scale integration of CNT/IGZO hybrid circuits, a 501stage ring oscillator comprised of over 1000 TFTs, showing the high yield of both of the p-type and n-type devices and their stability in ambient environment. This hybrid complementary design enables circuits to operate with low static power consumption, and allows the output of the circuit to reach rail-to-rail voltage. In addition, in order to further improve the stability of the device, I introduce a method to reduce the hysteresis in CNT TFTs, but encapsulating the devices with a layer of photoresist. Further, I was able to demonstrate this is a generic approach. iii In addition to carbon nanotubes, I also present my study in the controlled synthesis of silicon nanowires, another promising nanomaterial that can be used for energy storage device. I demonstrated the bulk synthesis method to increase the throughput for the nanowire growth. High throughput of silicon nanowire is desirable for applications such as Li-ion battery. My dissertation is divided in five chapters. Firstly, the Introduction chapter gives a brief explanation on the electrical properties of carbon nanotube thin film transistors; then it discusses macroelectronics, an important technology for modern consumer electronics, and it explains how CNT TFT can play an important role in the development of macroelectronics, hence the motive for intensive research in the field of CNT thin films. Secondly, the idea and the development of the large-scale hybrid integrated CNT/IGZO TFTs for macroelectronic applications are discussed in chapter 2. Thirdly, a systematic study on the method to improve the stability of CNT TFTs is presented in Chapter 3. The hysteresis of CNT TFTs can be controlled with appropriate passivation of the CNT TFTs. In the 4 th chapter, a novel method to improve the yield of silicon is introduced. And a lithium ion battery half-cell was realized using the as-grown silicon nanowires with this bulk synthesis scheme. Finally, I conclude my dissertation and also present my idea for the future development of the CNT-based macroelectronics. The idea is to use CNT TFT for fully transparent touch screen applications. iv To my grandma, my mother, my father, my love Natalie, and the SGI v Acknowledgement Firstly, I would like to express my gratitude to my adviser Prof. Chongwu Zhou. He has given me the opportunity to pursue my passion in research. With his guidance I have been able to obtain a skill that is crucial for the future development of my professional career, which is the problem solving skill. And he has taught me the way to brain storm and create ideas based on accumulative knowledge. Working with Prof. Zhou in the nanotechnology research allows me to experience the excitement of this ever-changing field, and it reminds me of the importance to always maintain a seeking spirit, and never become stagnant in the path of learning. Most importantly, I have learned to always adapt the change. Secondly, I would also like express my gratitude to my dissertation committee members, Prof. Steven Cronin, Prof. Edward Goo, and Prof. Wei Wu for their help with my dissertation defense process. I am also grateful for Prof. Ellis Parker who served as a member of my qualification exam committee. Thirdly, I would like to thank my former colleague Dr. Jialu Zhang who had given me much guidance and encouragement during the beginning of my research in the hybrid circuit study.. Also I would like to thank Dr. Po-chiang Chen who served as my mentor at the beginning of my PhD program. And I wish to thank Yu Cao for his contribution to my CNT/IGZO hybrid circuit study. I would like to give special thanks to Dr. Donghai Zhu for his help the equipment in the USC cleanroom. I would like to express my gratitude to the staffs at UCLA Nanolab cleanroom, Mr. Hoc Ngo, Mr. Wilson Lin and Mr. Max Ho for their help with the facilities there. I would like to thank Mr. John Curulli for his help with the SEM in USC CEMMA. In addition, Mr. vi Douglas Hauser and Mr. Ernesto Barron have provided me help with the TEM at the USC Health Science campus. I would like to thank Dr. Ashkan Seyedi and Yoshitake Nakajima for their help with the Hitachi FESEM. In addition, I would like to express my gratitude to my current colleagues, Dr. Chun-chung Chen, Shelley Wang, Noppadol Aroonyadet, Mingyuan Ge, Jiepeng Rong, Luyao Zhang, Xin Fang, Hui Gui, Liang Chen, Anyi Zhang, Sen Cong, Dr. Bilu Liu, Ahmad Abbas, Yuqiang Ma, Xuan Cao, Fanqi Wu, Yihang Liu, Chenfei Shen, Yilin Huang, Qingzhou Liu, Mohammad Abou-Saba, Christian Lau, and Xiaofei Gu. And I would like to express my gratitude to my former colleagues, Dr. Koungmin Ryu, Dr. Fumiaki Ishikawa, Dr. Lewis Gomez, Dr. Akshay Kumar, Prof. Chuan Wang, Dr. Alexandar Badmaev, Dr. Hsiao-Kang Chang, Dr. Anuj Madaria and Dr. Yi Zhang, Dr. Yuchi Che, Dr. Maoqing Yao, Dr. Jia Liu, Yue Fu, Xue Lin, Zhen Li, Jing Xu, Jing Qiu, Shermin Arab, Pyojae Kim, Younghyun Na, Rebecca Lee, Kuan-The Li, Ning Yang Pattaramon Vuttipittayamongkol, Dr. Gang Liu, and Dr. Yung-Chen Lin, Dr. Jesse Theiss, Rohan Dhall, and Shun-Wen Chang. They have given me support and encouragement during my study. Moreover, I would like to thank our collaborator Dr. Ming Zheng from National Institute of Standards and Technology for his valuable insight in research matters. And I would not have come this far without the unconditional care, support and love from my grandma, my mom, my dad and my girlfriend. They have always been there through the ups and downs in my life. I can never repay my debt of gratitude to them. Finally, I would like to express my gratitude to the Soka Gakai International (SGI) and all the members. They have given me tremendous support and encouragement through this experience. vii Table of Contents Abstract ...................................................................................................................................... ii Acknowledgement ...................................................................................................................... v List of Figures ......................................................................................................................... viii 1 Introduction ........................................................................................................................ 1 1.1 Introduction of carbon nanotubes ................................................................................ 1 1.1.1 Structure of carbon nanotubes .............................................................................. 1 1.1.2 Electrical transport mechanism of CNT field effect transistors ........................... 3 1.2 The role of carbon nanotube in macroelectronics ....................................................... 6 1.3 Introduction of nanowires .......................................................................................... 11 1.3.1 Vapor-liquid-solid growth mechanism of nanowires ......................................... 12 2 Large-scale integrated (LSI) complementary circuits based on carbon nanotubes and indium gallium zinc oxide for rigid and flexible electronics ................................................... 16 2.1 Introduction ............................................................................................................... 16 2.2 Hybrid complementary CNT and IGZO TFTs and circuits ...................................... 17 2.3 Hybrid complementary CNT/IGZO inverter, NAND and NOR gates ...................... 22 2.4 Hybrid complementary CNT/IGZO integrated ring oscillators with 1004 transistors 25 2.5 Hybrid CNT/IGZO dynamic circuits ......................................................................... 28 2.6 Summary .................................................................................................................... 30 2.7 References ................................................................................................................. 32 3 Improving device performance to achieve high performance and low hysteresis carbon nanotube thin film transistors. .................................................................................................. 35 3.1 Introduction ............................................................................................................... 35 3.2 Carbon nanotube comparison based on 99.9%, 99% semiconducting enriched and 1R Raymor carbon nanotubes .................................................................................................... 37 3.3 Abatement of hysteresis in both p-type and n-type carbon nanotube TFTs in ambient 46 3.4 Summary .................................................................................................................... 52 3.5 References ................................................................................................................. 53 4 Bulk Synthesis of Crystalline and Crystalline-Core/Amorphous-Shell Silicon Nanowires and Their Application for Energy Storage ............................................................................... 56 4.1 Introduction ............................................................................................................... 56 4.2 Bulk synthesis of silicon nanowires .......................................................................... 57 4.3 Crystalline-core/amorphous-shell silicon nanowires ................................................. 60 4.4 Single crystalline silicon nanowires .......................................................................... 63 4.5 Electrochemical characteristic of crystalline-core/amorphous-shell silicon nanowires 65 4.6 Summary .................................................................................................................... 70 4.7 References ................................................................................................................. 71 5 Conclusions and future direction on CNT macroelectronics ........................................... 74 5.1 Conclusions ............................................................................................................... 74 5.2 Future research: Fully transparent hybrid carbon nanotube/IGZO TFT-based control circuitry for transparent CNT resistive touch screen ........................................................... 76 5.2.1 Introduction ........................................................................................................ 76 5.2.2 Touch screen structure and operating mechanism ............................................. 77 5.2.3 Fully transparent carbon nanotube-based 4-wire resistive touch screen with CNT/IGZO hybrid integrated complementary multiplexer control circuitry ................... 80 5.3 References ................................................................................................................. 86 Bibliography ............................................................................................................................. 89 viii List of Figures Figure 1.1: (a) The unrolled hexagonal honeycomb lattice of a carbon nanotube. a1 and a2 are base vectors in the vector Ch. By connecting point O with A, and point B with B‘ a carbon nanotube nanotube can be formed. The nanotube structure is defined by n = 4, and m = 2 in the schematic diagram. (b) (4,2) carbon nanotube with the translation vector T. (Figure adopted from ref. 4 ) ................................................................................................ 3 Figure 1.2: (a) Energy band diagram of a carbon nanotube field effect transistor in the off state of the device. (b) Energy band diagram of the CNT FET in on-state. (Figure adopted from ref. 11 ) .......................................................................................................................... 4 Figure 1.3 (a) Energy band diagram of p-type CNT FET at negative and positive gate bias. (b) Energy band diagram of n-type CNT FET at negative and positive gate bias (figure adopted from ref. 8 ). ............................................................................................................ 5 Figure 1.4: International technology roadmap for semiconductors (ITRS) prediction on microprocessor unit (MPU) and high performance application-specific integrated circuits (ASIC) half-pitch and gate length trends. (Figure adapted from ref. 26 ) .............................. 7 Figure 1.5: Examples of macroelectronics including mobile device, flexible OLEDs, flexible display, OLED TV, flexible RFID, wearable display, X-ray imager, conformal electronics. (Figure adapted from ref. 27,28,30-32 ). ..................................................................................... 9 Figure 1.6: Revenue of different technologies in the global market in year 2012. (Figure adapted from ref. 33 ) ............................................................................................................. 9 Figure 1.7: Forecast of OLED revenue in global market for the ten years period in different consumer electronics. (Figure adapted from ref. 34 ). ......................................................... 10 Figure 2-1: Illustration, optical micrographs, scanning electron microscopic images, and device characteristics of hybrid CNT/IGZO complementary integrated circuits. a, Three dimensional schematic diagram of a CNT/IGZO complementary mode inverter on rigid substrate (left) and same circuit on flexible substrate (right). b, schematic diagram conceptually showing the interface between the Ti/Pd electrode and the CNT network. c, SEM image of CNT network in the channel of a p-type TFT; the scale bar in the low magnification SEM image is 10 μm and the scale bar in the high magnification SEM image is 2 μm. d, SEM image of IGZO in an n-type TFT; the scale bar is 5 μm. e, Optical micrograph of the hybrid CNT/IGZO ring oscillators, inverters, individual p-type, and n- type transistors fabricated on a rigid Si/SiO2 substrate. The inset shows a 501-stage ring oscillator on the rigid substrate. The scale bar in the rigid circuit chip is 500 μm. The scale bar in the 501-stage ring oscillator image is 600 μm. f, Optical photographic image of the hybrid CNT/IGZO ring oscillators, inverters, and individual transistors on a flexible polyimide substrate laminated on a polydimethylsiloxane (PDMS) film. The scale bar in flexible circuit is 2 cm. g, Transfer characteristic in linear and log scale and transconductance of a CNT TFT with gate bias varied from -5 to 5V. Lch = 20 μm, Wch = 100 μm, VDS = 1V. h, Output characteristic of the CNT TFT with VDS varied from -5 to 0V. i, Transfer characteristic in linear and log scale and transconductance of a IGZO TFT with gate bias varied from -5 to 5V. Lch = 4 μm, Wch = 12 μm, VDS = 1V. g, Output characteristic of the IGZO TFT with VDS varied from 0 to 5V. ........................................ 20 Figure 2-2: Structure and characteristic of a hybrid CNT/IGZO complimentary inverter, a NAND gate, and a NOR gate. a, Schematic diagram and an optical micrograph of a hybrid CNT/IGZO inverter. The scale bar is 200 μm. b, Output voltage and current characteristic of the hybrid inverter. c, Voltage gain of the inverter. d, Output characteristic of 20 hybrid CNT/IGZO inverters fabricated on a polyimide flexible substrate. e, Schematic diagram and an optical micrograph of a hybrid CNT/IGZO NAND gate. The scale bar is 200 μm. f, Output characteristic of a hybrid CNT/IGZO NAND gate. g, schematic diagram and an optical micrograph of a hybrid CNT/IGZO NOR gate. The scale bar is 200 μm. h, Output characteristic of a hybrid CNT/IGZO NOR gate. ................................................................................................................................... 24 Figure 2-3: Structure and output characteristic of 51-stage, 101-stage, 251-stage and 501-stage ring oscillators. a, Optical micrograph and schematic diagram of a 51-stage ring oscillator. Scale bar is 400 μm, b, Output characteristic of a 51-stage ring oscillator. c,d, Optical micrograph of a 101-stage ring oscillator and its output characteristic, respectively. Scale ix bar is 400 μm. e,f, Optical micrograph of a 251-stage ring oscillator and its output characteristic, respectively. Scale bar is 600 μm. g,h, Optical micrograph of a 501-stage ring oscillator and its output characteristic, respectively. Scale bar is 600 μm. i, Frequency of the output signals of the 51-stage, 101-stage, 251-stage, and 501-stage ring oscillators with respect to the number of stages. j, Comparison of level of integration of CNT-based integrated circuits from 19 published articles and our work. The star circled by red ink corresponds to our work. .................................................................................. 26 Figure 2-4: Structure and output characteristic of dynamic inverter, NAND and NOR gate. a,b, Schematic and optical micrograph of a dynamic inverter based on the hybrid CNT/IGZO complementary scheme. Scale bar is 200 μm. c, Output characteristic of the dynamic inverter with a clock signal supplied at 500 Hz and a VDD of 3V. d,e, Schematic and optical micrograph of a dynamic NAND gate. Scale bar is 200 μm. f, Output characteristic of the dynamic NAND gate with a clock signal supplied at 500 Hz and a VDD of 3V. g,h, Schematic and optical micrograph of a dynamic NOR gate. Scale bar is 200 μm. i, Output characteristic of the dynamic NOR gate with a clock signal supplied at 500 Hz and a VDD of 3V. ................................................................................................... 30 Figure 3.1: SEM images of 99.9%, 99% and 1R Raymor carbon nanotubes. (a) SEM image of 99.9% semiconducting enriched CNT thin film at 20x magnification. (b) SEM image of 99% CNT thin film at 20x magnificatoin. (c) SEM image of 1R Raymor CNT thin film at 20x magnification. ............................................................................................................. 40 Figure 3.2: Electrical properties of back-gated TFTs based on the 99.9%, 99% and 1R Raymor CNT thin films. (a-c) Normalized transfer characteristic (ID/W Vs. Gate Voltage) of CNT TFTs based on 99.9% CNTs (a), 99% CNTs (b), and 1R Raymor CNTs (c) with channel length variation (L = 4 μm, 10 μm, 20 μm, 50 μm, and 100 μm) and with channel width, W = 400 μm. The graph is delineated in logarithmic scale. (d-e) Transfer characteristics (black: linear; blue: logarithmic scale) and gm Vs. Gate Voltage characteristics (red) of typical CNT TFTs based on 99.9% CNTs (d), 99% CNTs (e), and 1R Raymor CNTs (f) with a device geometry of L = 4 μm and W = 400 μm. ................. 42 Figure 3.3: Output characteristic (Drain Current versus Drain Voltage) of CNT TFT fabrcated from 99.9% CNT thin film (a), 99% CNT thin film (b), and 1R Raymor CNT thin film (c). ........................................................................................................................................... 43 Figure 3.4: Statistical study and comparison of electrical performance metrics between CNT TFTs comprised of 99.9% CNT thin films, 99% CNT thin films, and 1R Raymor thin films. (a) Average CNT TFT mobility measured at different channel length for the TFTs with the 99.9% CNT thin films, the 99% CNT thin films, and the1R Raymor thin films. (b) Average current on/off ratio (Ion/Ioff) measured at different channel length for the same CNT TFTs. (c) Average current density (Ion/W) versus the inversed of the channel length. (d) Drain current of CNT TFTs based on the three types of CNT thin films with channel length of 10 μm versus different channel width. ................................................. 46 Figure 3.5: Schematic diagram and transfer characteristic of p-type CNT TFT with and without passivation. (a) Cross-sectional schematic diagram of a p-type common back- gate CNT TFT with SPR 3612 positive photoresist passivation. (b) Transfer characteristic of a CNT TFT common back-gate device before (black) and after (red) passivation of the device with SPR 3612 photoresist. (c) The transfer characteristic of the device in logarithmic scale. .............................................................................................................. 48 Figure 3.6: Statistical study of the hysteresis (a), subthreshold voltage swing (b), mobility (c), and threshold voltage (d) of 18 CNT TFTs with L = 4, W = 200 μm before and after S3612 passivation. The red bars correspond to CNT TFTs with passivation, and the black bars correspond to the CNT TFTs without passivation. ................................................... 50 Figure 3.7: Transfer characteristic of p-type CNT TFT, converted n-type CNT TFT of the same device before and after SPR3612 passivation. (a) Transfer characteristic of a p-type CNT TFT (black), converted n-type CNT TFT from the same device (red), and converted n-type CNT TFT with passivation (blue). (b) Transfer characteristic plotted in logarithmic scale. .............................................................................................................. 52 Figure 4-1: Schematic diagram of the growth set-up, and the growth mechanism, and SEM and photographic images of the as-grown Si NW on Al2O3 subtrates (a) Schematic diagram illustrating a nanowire synthesis system comprised of a furnace and a quartz reaction chamber. A quartz boat loaded with Au-coated Al2O3 spheres were placed at the center of the chamber. (b) Schematic diagram showing a pristine Al2O3 sphere, an Al2O3 sphere decorated with Au particles after annealing, and Si nanowires synthesized on x Al2O3 spheres via the VLS mechanism. (c) Photographic image of Al2O3 spheres before (top) and after (bottom) nanowire synthesis. (d) Photographic image of 80 mg of free- standing silicon nanowires in a vial. (e) SEM image of crystalline-core/amorphous-shell Si nanowires synthesized on a millimeter scale Al2O3 sphere. (f) Al2O3 spheres stacked in a vertical quartz reaction chamber (left). Photographic image and SEM image (inset) of Al2O3 spheres with Si nanowires synthesized with the vertical chamber configuration (right). The scale bar is 400 μ m. ...................................................................................... 63 Figure 4-2: SEM and TEM characterization of the core/shell silicon NWs. (a) FESEM image of crystalline-core/amorphous-shell Si nanowires grown on an Al2O3 sphere. Inset: SEM image of a c-a core/shell Si nanowire with a Au catalytic particle at its tip. Scale bar is 100 nm. (b) TEM image of a c-core/a-shell Si nanowire. (c) HRTEM image of crystalline-core/amorphous-shell interface of a Si nanowire. (d) Diameter distribution of the c-core/a-shell Si nanowires. ........................................................................................ 63 Figure 4-3: SEM and the TEM characterization of the as-grown Si NWs (a) FESEM image of single crystalline Si nanowires grown Al2O3 sphere. Inset: crystalline Silicon nanowire with a Au particle at its tip. The scale bar is 100 nm. (b) TEM image of a single crystalline Si nanowire having the growth axis in the <111> direction. (c) HRTEM image showing the lattice fringes of the nanowire. Inset: electron diffraction pattern from the silicon nanowire. (d) Diameter distribution of the single crystalline nanowires. ............. 65 Figure 4-4: Performance oft the bulk sythesized Si NW used in the anodel of Li-ion battery half cell. (a) Cyclic voltammogram for Si nanowires from 0.01V to 3.0V. The first three cycles are shown. (b) Voltage profile for first 40 cycles of the Si nanowire electrode at the C/30 rate. (c) Capacity versus cycle number for the Si nanowire electrode at the C/30 (red) rate and the C/10 (black) rate. (d) Coulombic efficiency versus cycle number for the Si nanowire electrode at the C/30 (red) rate and the C/10 (black) rate. ............................ 68 Figure 5.1: A cross-sectional schematic diagram of a 4-wire touch screen (Figure adapted from ref. 22 ). ........................................................................................................................ 78 Figure 5.2: Schematic diagram of a four wire resistive touch screen and the conceptual diagram of its operation. (a) Schematic diagram of a four wire resistive touch screen with its top and bottom electrodes. (b) Conceptual diagram of the operating mechanism of the touch screen, when a voltage is applied across Y+ and Y- in the bottom electrodes, and the point of contact is measured at X+ in the top electrode, hence the y-coordinate of the point is detected. (c) When a voltage applied across the X+ and X- in the top electrodes, the point of contact is measured at Y+ in the bottom electrode, hence the x-coordinate of the point is detected. (Figure adapted from ref. 37 ). ........................................................... 79 Figure 5.3: Schematic diagram and photographic images of Unidym CNT thin films used as top electrodes for touch screen. (Figure adapted from ref. 33 ). (a) Schematic diagram of the structure of a commercially available 4-wire resistive touch screen (top) and a touch screen using CNT thin film as the top electrode. (b) Photographic image of a Unidym CNT thin film touch screen. (c) Photographic image of a Unidym CNT touch screen integrated with a commercial LCD monitor. .................................................................... 81 Figure 5.4: Schematic diagram, optical micrograph, and output characteristics of CNT/IGZO hybrid XOR gate and D-Latch. (a) (b) Schematic diagram and optical micrograph of CNT/IGZO hybrid complementary XOR gate, respectively. (c) Output characteristic of the XOR gate at VDD of 5 V. (d) (e) Schematic diagram and optical micrograph of CNT/IGZO hybrid complementary D-Latch, respectively. (f) Output characteristic of the D-Latch at VDD of 5V. ....................................................................................................... 83 Figure 5.5: Conceptual schematic diagram of the electronic interface between the CNT-based 4-wire resistive touch screen and the CNT/IGZO hybrid complementary multiplexer. (Figure adapted from ref. 37 ) .............................................................................................. 84 Figure 5.6: Schematic diagram of an all-CNT-based TFT, using high density CNT (metallic) grown CNT thin film as the gate, drain and source electrodes; using low density CVD grown CNT thin film as the channel of the TFT.( Figure adapted from ref. 40 ). ............... 85 Figure 5.7: Schematic diagram of fabrication of TFTs using graphene as the electrodes, CNT thin film as the channel material, and wrinkled Al2O3 as the dielectric material. (Figure adapted from ref. 43 ). .......................................................................................................... 85 1 1 Introduction 1.1 Introduction of carbon nanotubes Carbon nanotube has captivated much research interest for the past two decades since its first discovery in 1991 by Sumio Iijima as an interesting one-dimensional (1D) material exhibiting large aspect ratio; having diameter in the order of a nanometer, and with length in the order of micrometers 1-3 . The electrical conductivity of carbon nanotubes can exhibit either metallic or semiconducting behavior depending on the chirality of the atomic structure of the nanotubes 2- 4 . Energy band-gap of carbon nanotubes is inversely proportional to the diameter of the nanotubes 2,3 . The diameter and chirality dependence of the electrical properties of carbon nanotubes have captured much research effort to exploit these properties for the future development of electronics 3 . Field effect transistor comprised of an individual single wall carbon nanotube (SWNT) has been characterized to exhibit mobility greater than 10000 cm 2 /Vs 5-7 . This extraordinary mobility of CNT FET can be attributed to the one- dimensionality of CNT, in which the carrier scattering is limited due to carrier confinement 2,3 . Its superior electrical property has made CNT a desirable material for research in devices. 1.1.1 Structure of carbon nanotubes Carbon nanotube can be considered as a seamless cylindrical tube formed by rolling up a single layer of graphitic sheet, or graphene. Nanotubes can be described by a chiral vector Ch, which is given by:  m n m n C h , a a 2 1    (1) 2 The structure of the carbon nanotube can be defined by a pair of integer   m n, . The unit cell base vectors in the hexagonal honeycomb lattice are represented by a1 and a2. Hence na1 and ma2 denote the number of unit vectors in the hexagonal lattice within the vector Ch 4 . Figure 1 illustrates the vector Ch and the unit vector a1 and a2. A chiral angle, θ is created in the honeycomb lattice by the chiral vector Ch. Carbon nanotubes can be classified into three types based on its chiral angle. If θ = 0˚, then the nanotube is considered to be zigzag nanotube; if θ = 30˚, then it is classified as an armchair nanotube; and if the chiral angle is between 0˚ and 30˚, then it can be considered as a chiral nanotube. The nanotube diameter can be given by the expression:    2 1 2 2 3 n mn m a C d CC h t     (2) where aCC is the nearest distance between two adjacent carbon atoms, which is a constant of 1.421 Å. Ch is the length of the chiral vector Ch. And θ is given by:    n m m 2 / 3 tan 1     (3) The translation vector, T as can be seen in Figure 1_1 is given by the following expression:  2 1 2 2 1 1 , T t t a t a t    (4) where the coefficients t1 and t2 can be given as:   R R d m n t d n m      2 2 , 2 t1 (5) where dR is the largest value of the common divisor of (2n+m, 2m+n), in which dR is given by the expression:         d m n d d m n d d R 3 of multiple if 3 3 of multiple if (6) where d is the largest value of the common divisor of (n,m). The magnitude of the translation vector, T is given by R h d C 3 T  . 3 Figure 1.1: (a) The unrolled hexagonal honeycomb lattice of a carbon nanotube. a 1 and a 2 are base vectors in the vector C h. By connecting point O with A, and point B with B‘ a carbon nanotube nanotube can be formed. The nanotube structure is defined by n = 4, and m = 2 in the schematic diagram. (b) (4,2) carbon nanotube with the translation vector T. (Figure adopted from ref. 4 ) 1.1.2 Electrical transport mechanism of CNT field effect transistors Carbon nanotube-based field effect transistor (FET) is inherently a p-type transistor in atmosphere due to the adsorption of oxygen molecules and the high work metal electrodes used in the transistors 3,8,9 . When a negative bias is applied to the gate of the transistor, an accumulation of holes is generated in the channel of the transistor and an increase in conductance can be expected 10 . The electrical transport mechanism of CNT FET is significantly influenced by the Schottky barrier created between the carbon nanotube channel and the drain and source metal electrodes, which is a result of the difference in work function between the metal used for the electrodes and the carbon nanotube channel 11 . In the condition where a CNT FET is placed in air, the valence band of the carbon nanotube is near the Fermi energy level of the metal electrode at the metal-nanotube junction, more prominently demonstrated when high work function metal, such as palladium is used 12-14 . The Schottky 4 barrier width at the metal-nanotube junction can be decreased by applying a gate bias greater than the threshold voltage of device, hence holes can tunnel through the barrier, resulting in transport of carriers from the source to the drain of the device. The transport of the carriers is based on tunneling of the Schottky barrier by the holes, and the probability of tunneling increases with reduction in the barrier width 11 . The aforementioned transport behavior of carriers in CNT FET is summarized in the energy band diagram in Figure 2. In figure 2a, there is no conduction of carriers in the channel of the transistor, when there is no voltage applied to the gate of the transistor, and the barrier width is large. In figure 2b, the holes can tunnel through the Schottky barrier at the metal-nanotube junction, when a negative bias is applied to the gate electrode of the device. Figure 1.2: (a) Energy band diagram of a carbon nanotube field effect transistor in the off state of the device. (b) Energy band diagram of the CNT FET in on-state. (Figure adopted from ref. 11 ) In addition to the p-type conducting behavior exhibited by the CNT FET in air, carbon nanotubes can be modified to exhibit n-type and ambipolar behavior 15,16 . By annealing the carbon nanotube FET in vacuum can effectively remove the adsorbed oxygen molecule, hence directly modify the band bending at the metal-nanotube junction in the device. The removal of oxygen molecules results in the Fermi energy level of the metal electrode lining up with the conduction band of the carbon nanotube, hence lowering the barrier for the electrons in the channel. The realignment of the energy band also creates higher barrier for holes, which 5 hinders the transport of holes, resulting in a n-type conducing behavior 8 . As it is illustrated in Figure 3 (a) and (b), the removal of oxygen molecule enhances the transport of electron in the transistor. In Figure 1.3 (a) the Fermi energy level of the metal electrode is closer to the valence band of the CNT than it is to the conduction band, therefore hole conduction can be enbaled at a negative gate bias. For n-type conduction, it is illustrated in Figure 3(b) that, the conduction band of the CNT is situated closer to the Femi level of the metal electrode. However, an ambipolar behavior of the CNT FET can be observed, when the Fermi energy level of the metal electrode situates at near the middle of the bandgap of the CNT, hence resutling in similar barrier for both electron and hole transport in the device 15 . Figure 1.3 (a) Energy band diagram of p-type CNT FET at negative and positive gate bias. (b) Energy band diagram of n-type CNT FET at negative and positive gate bias (figure adopted from ref. 8 ). 6 1.2 The role of carbon nanotube in macroelectronics In the previous section it was discussed that CNT can exhibit either semiconducting or metallic conductivity depending on the chirality, hence the diameter of the CNTs. During the synthesis of carbon nanotubes, generally 1/3 of the as-grown nanotubes are metallic and 2/3 are semiconducting nanotubes 17,18 . Much research effort has been dedicated in the extraction of semiconducting enriched nanotubes for the development of carbon nanotube thin film transistors (TFTs) as an emerging TFT technology for macroelectronics 19-22 . TFTs have been a driving force for macroelectronics, which has advanced in a direction different from the silicon-based complementary metal oxide semiconductor (CMOS) microelectronics technology 23,24 . Engineers have pushed for transistors with smaller and smaller channel length to improve the speed and to minimize the size of transistors in microprocessor units (MPU) and in memories in order to follow the Moore’s law 25 . The prediction of the half pitch and gate channel length of transistors by the International Technology Roadmap of Semiconductors (ITRS) is shown in Figure 1.4 26 . The channel length and the half-pitch will be scaled down to below 10 nm. 7 Figure 1.4: International technology roadmap for semiconductors (ITRS) prediction on microprocessor unit (MPU) and high performance application-specific integrated circuits (ASIC) half-pitch and gate length trends. (Figure adapted from ref. 26 ) However, the development of macroelectronics is moving in a different direction. Macroelectronics are electronics required to cover a large area, for instance active matrix flat panel displays, and the thin film transistors are utilized to control a pixel as large as 1 mm 2 in size 23 , therefore the transistor size needs not to be as small as that used in transistors used in microelectronics. Since many of the TFTs are expended in the pixel driving circuitry for display applications, the requirement on speed, hence the requirement on mobility of the transistors can be relaxed 23 . Macroelectronics have become a crucial element in the modern consumer electronics, some of these devices are illustrated in Figure 1.5, including mobile device, flexible organic light emitting diodes (OLEDs), flexible display, OLED TV, flexible radio frequency identification tag (RFID), wearable display, X-ray imager, conformal electronics 27-32 . Correspondingly, the utilization of macroelectronics in consumer electronics can be translated into revenues in the global market. In Figure 1.6, it depicts the share of 8 revenue based on different technologies in the global market in the year 2012. In particular, smart phone, TV and LCD represent a total of $417 billion industry 33 . And thin film transistors can be used in all of these technologies. In addition, due to the recent development in active matrix OLED (AMOLED), and the advantages exhibited by OLEDs, including wide viewing angle (up to 180 ˚), fast response time, higher contrast ratio, relatively low power consumption, companies have expanded production in AMOLED displays 33,34 . It has been predicted that the revenues based on OLED display technology rise to $35 billion in comparison to its $4 billion revenue in 2011 as shown in Figure 1.7 34,35 . TFT is the backbone for pixel driver circuitry in AMOLED displays, hence the market prediction for AMOLEDs also presents enormous opportunity for TFTs. In the current TFT technology, polycrystalline silicon, amorphous silicon (a-Si:H), and oxide semiconductor have been the commercialized materials used as the channel material for TFTs 36 . The development of organic materials based TFTs has also gained momentum in the past decade 36 . However, each of the aforementioned materials exhibits shortcomings in terms of performance for macroelectronics. And CNT TFT has been demonstrated with many advantages, proven to be a potential candidate for the development of the next generation of macroelectronics 17,18,37-40 . 9 1) Macroelectronics and Flexible Macroelectronics – cover large area (>1 m 2 ) 2) Transistor dimension – 1 to 10 μm feature size 3) Sensing and control of large area Light weight display Conformal electronics for sensors X-ray imager Flexible OLED and control Flexible display OLED TV Flexible RFID Wearable OLED display Figure 1.5: Examples of macroelectronics including mobile device, flexible OLEDs, flexible display, OLED TV, flexible RFID, wearable display, X-ray imager, conformal electronics. (Figure adapted from ref. 27,28,30-32 ). Figure 1.6: Revenue of different technologies in the global market in year 2012. (Figure adapted from ref. 33 ) In the past decade, many researchers have demonstrated the excellent electrical performance of CNT thin films as a channel material for TFTs 17,38,40 . CNT thin film-based transistors exhibit p-type electrical behavior as it was explained earlier, and it shows effective mobility between 10 and 164 cm 2 V -1 s -1 which is higher than the existing amorphous silicon (a-Si:H) 10 technology currently being used in active matrix liquid crystal display (AMLCD) 17,36,38,41 . However, for applications such AMOLED displays, a current driven system, high on-current density is required, hence high device mobility is critical. In which case, amorphous silicon can no longer match with the criteria. In addition, CNT thin films exhibit excellent transparency (~90%) and operational stability, which are more advantageous than organic TFTs for macroelectronic applications 42,43 . Moreover, CNT thin films are highly flexible, and they can be processed at room temperature, which are important properties for the development of flexible and wearable electronics 37,44 . The aforementioned advantages of CNT TFTs, and the merits and drawbacks of other TFT technologies are summarized in Table 1-1. The table shows a comparison of CNT TFTs, amorphous silicon (a-Si:H) TFTs, oxide semiconductor TFTs, organic TFTs, and polycrystalline silicon (Poly-Si) TFTs in terms of their mobility, uniformity, stability, scalability, process temperature, cost and availability 34 . The metrics listed in the table further demonstrate CNT TFTs as a unparallel platform for the development of macroelectronics. Figure 1.7: Forecast of OLED revenue in global market for the ten years period in different consumer electronics. (Figure adapted from ref. 34 ). 11 Table 1-1: Comparison of CNT TFTs, amorphous silicon (a-Si:H) TFTs, oxide semiconductor TFTs, organic TFTs, and polycrystalline silicon (Poly-Si) TFTs. (Figure adapted from ref. 34 ). Characteristic CNT TFT a‐Si:H Oxide TFT Organic TFT Low Temp Poly‐Si Mobility Good, 10 ‐ 164 cm 2 /Vs Poor, 0.5 ‐ 1 cm 2 /Vs Good, 1 ‐ 40 cm 2 /Vs Typical ≤ 1 cm 2 /Vs, max. 46 cm2/Vs Excellent, 10 ‐ 500 cm 2 /Vs Uniformity Good Excellent Good with amorphous type, poor with crystalline type Good Poor Stability Good Poor Poor Poor Excellent Scalability Good, currently 4'' Excellent, >100'' Potential to 100'' Good, currently 4'' Limited to < 40'' Process Temperature room temperature Typical ~300 ˚C, some low temp. process can be ~150˚C Typical ~200 ˚C, but some need anneal at 350 ̊CTypical < 100 ˚CHigh, > 400 ˚C Cost Low Low Medium Low High Availability Research stage Yes Yes Research stage Yes Challenges Hysteresis Poor mobility; poor stability Threshold voltage unstable Poor operational stability Uniformity, cost, stability 1.3 Introduction of nanowires Nanowires are intriguing materials which have been investigated for many applications including digital circuits, energy storage applications, transparent and flexible electronics, driver circuits for displays, chemical sensors and biosensors etc 45-51 . The electrical conductivity of nanowires can be facilely controlled by the chemical composition of the precursor or the bulk material used to synthesize the nanowires. The versatility of the material choice for nanowires results in the wide variety of applications which can be implemented with nanwires of different electrical conductivity. Semiconducting nanowires, such as silicon nanowires, InAs nanowires, germanium nanowires, Ge/Si core/shell nanowires and In2O3 nanowires etc. exhibit excellent electrical properties 45,52-57 . InAs nanowire-based filed effect transistor has been reported to exhibit electron mobility as high as 6580 cm 2 /Vs 58 . The desirable mobility of NW based FETs makes it an attractive candidate for electronics. Silicon nanowires have been studied extensively for its applications in circuits and also in energy storage devices, especially in lithium ion batteries 59,60 . Silicon has been considered as an candidate for the anodes of Li-ion batteries due to its superior capacity, namely 4200 mAh/g 59 . Zinc oxide piezoelectric properties which enable them to expended in energy harvesting 12 applications 61 . Metallic nanowires such as silver and copper nanowires have been used in transparent conductive electrodes (TCE) with sheet resistance as low as 10 Ω/sq 62,63 . These Ag and Cu nanowire TCEs exhibit desirably low sheet resistance, excellent transparency and flexibility, which have been considered as possible candidates for next generation of flexible and transparent TCE for the development of flexible electronics 62,64 . 1.3.1 Vapor ‐liquid ‐solid growth mechanism of nanowires Vapor-liquid-solid is one common growth mechanism in many nanowires synthesis. The mechanism was first discovered by R. S. Wagner and W. C. Ellis. In brief, for the mechanism, a catalyst, for instance, Au particles are heated on a Si wafer forming droplets of Au-Si alloy. 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Lett. 4, 89 (1964). 16 2 Large ‐scale integrated (LSI) complementary circuits based on carbon nanotubes and indium gallium zinc oxide for rigid and flexible electronics 2.1 Introduction Carbon nanotube network-based transistors have been utilized in demonstrations of integrated circuits for digital circuits, computers, displays and flexible electronics 1-15 . They have been proven to exhibit the potential to be utilized in integrated circuits and OLED pixel driving circuitry for active-matrix flat-panel display (FPD) 2,8 . CNT network thin film transistors (TFTs) exhibit the merits of high transparency, high flexibility, low process cost, low processing temperature, and high scalability, which can surpass that of the TFTs based on amorphous silicon and polysilicon thin films 3,6,16-23 . Their electrical performance is tantamount of those exhibited by amorphous silicon 24 . With the growing interest in transparent and flexible electronics, such as driver circuitry for FPDs, radio frequency tags, sensors, and memories, CNT network TFTs can be used as an essential building block for the applications. Large scale integration of CNT network TFTs is a necessity for the realization of more complicated functionality in the aforementioned applications, for instance in flexible memories or circuits with computational functions. Circuits operating in complementary mode are essential to reduce the static power consumption for LSI circuits, and the complementary configuration enables full output voltage swing for the ICs. CNTs are inherently doped to be p-type semiconducting material in atmosphere due to adsorption of oxygen 25-27 . ICs fabricated based on unipolar CNT TFTs are subject to significant steady-state power dissipation. Some groups, including our own, have dedicated effort in the development of CNT-based complementary ICs 5,28-30 . Some groups introduced doping of CNTs as means to 17 convert the material into n-type; however, the long term stability of the methodology has not yet been thoroughly investigated 30 . Here we report a quantum leap of using hybrid integration of p-type CNT and n-type IGZO thin-film transistors to reliably achieve large scale integration (>1000 transistors) of complementary circuits on rigid substrates, and demonstrate the feasibility to fabricate and correctly operate the circuits on flexible substrates. This novel approach of hybrid integration is reliable and scalable, and exhibits ultra low steady-state power consumption due to the complementary configuration. Full output voltage swing is achieved by our hybrid CNT/IGZO design allowing for wide noise margin which are illustrated in our hybrid CNT/IGZO inverters, NAND and NOR gates, and ring oscillators. Utilizing CNT network for the channel material of the p-type TFTs enables the performance of the transistors to be less susceptible to defects, such as metallic nanotubes in the thin film. The enrichment of semiconducting CNT solution has been drastically improved due to the advancement in CNT separation methodology 16 . IGZO was selected to be expended as the channel material for the n-type transistors in the integrated circuits, due to the fact that IGZO is one of the most promising members in the category of amorphous oxide semiconductors. It has been exploited for active matrix organic light emitting diode (AMOLED) displays due its excellent uniformity of device mobility which is tantamount to the current polycrystalline silicon thin film devices 31-34 . The deposition of both CNT and IGZO thin films is a scalable process, and in the future the hybrid circuit scheme can be incorporated into printed electronics. 2.2 Hybrid complementary CNT and IGZO TFTs and circuits Schematic diagram in Figure 2-1 (a) illustrates our proposed scheme of a hybrid integration of CNT network and IGZO thin film transistors in an inverter, which can be fabricated on both 18 of a rigid Si/SiO2 and a flexible polyimide substrate. We have adopted an individual back-gate design for all of the circuits fabricated in this study. Briefly, individual back-gate Ti/Au electrodes were patterned and deposited on a Si/SiO2 substrate. The process was followed by deposition of dielectric material (40 nm of Al2O3 and 5 nm of SiOx), and then a 98% semiconducting CNT network solution was uniformly spread across the sample after functionalizing the SiOx surface. Metallization of Ti/Pd was carried out after patterning the CNT thin film for the specific channel geometry of the p-type TFTs. Then a layer of IGZO thin film was deposited as the channel material for the n-type devices by DC magnetron sputtering. Finally the circuit was completed by conducting standard photolithography and metallization of Ti/Au for the n-type TFTs. The schematic diagram in Figure 2-1 (b) conceptually illustrates the interface between the CNT random network and the Ti/Pd electrode. Figure 2-1 (c) (d) are scanning electron microscopic (SEM) images illustrating the CNT network and IGZO thin film in the channel of p-type and n-type transistors respectively. Figure 2-1 (e) (f) show optical images of our hybrid integrated CNT/IGZO complementary circuits on a rigid and a flexible substrate, including 501-stage ring oscillators, 251-stage ring oscillators, 101-stage ring oscillators, 51-stage ring oscillators, inverters and individual n-type and p-type devices. In addition to fabrication of the circuits on a rigid silicon/silicon oxide substrate, we successfully incorporated the integrated circuits onto a flexible polyimide membrane (HD MircroSystems, Inc. PI-2525). The result has provided evidence for the applicability of large scale integration of flexible electronics using CNT TFTs. Individual bottom-gate electrodes were patterned by photolithography on a highly doped p-Si substrate with a layer of thermally grown oxide (300 nm). E-beam evaporation was used to deposit Ti/Au (5 nm/50 nm) to form the electrodes. A layer of 40 nm of Al2O3 was deposited on the electrodes by atomic layer deposition (ALD) at 250 ˚C, which was then followed by deposition of 5 nm of SiOx by E-beam evaporation to form the dielectric layer for the circuits. In order to deposit carbon nanotube onto the dielectric material, the sample was 19 functionalized by poly-L-lysine (0.1% wt in water from Sigma Aldrich) to form amine terminated surface. The surface of the dielectric material was covered with poly-L-lysine by drop casting of the solution, and the surface was incubated in the solution for 6 minutes. Then the sample was cleansed by deionized (DI) water to remove the solution. Next, the surface of the functionalized sample was coated with commercially available 0.01 mg/mL 98% semiconducting carbon nanotube solution (NanoIntegris Inc.) for 10 minutes, followed by deionized water rinsing and drying with N2 gun. CNT channels were then defined by photolithography and followed by O2 plasma etching at 100 W/150 mTorr for 1 minute and 15 seconds. Vias or interconnects between devices and probing window on testing pads for gate electrodes were patterned by photolithography and the dielectric material at the vias and on the testing pads was etched by buffered oxide etchant (buffered HF 7:1) for 1 minute and 20 a bc d e f 20 012 345 0 10 20 30 40 50 60 70 80 90 100 V GS = 10 V V GS = -5 to 10 V 1.5 V step Drain Current ( A) V DS (V) -4 -2 024 0 1 2 3 4 5 6 7 8 9 Gate Voltage (V) Drain Current ( A) 10 -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 Drain Current (A) V DS = 1V 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 Transconductance ( S) -4 -2 0 2 4 0 1 2 3 4 5 6 Gate Voltage (V) Drain Current ( A) 10 -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 Drain Current (A) 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Transconductance ( S) V DS = 1V -5 -4 -3 -2 -1 0 -35 -30 -25 -20 -15 -10 -5 0 V GS = -10 V V GS = -10 to 5 V 1 V step Drain Current ( A) V DS (V) e g f d Figure 2-1: Illustration, optical micrographs, scanning electron microscopic images, and device characteristics of hybrid CNT/IGZO complementary integrated circuits. a, Three dimensional schematic diagram of a CNT/IGZO complementary mode inverter on rigid substrate (left) and same circuit on flexible substrate (right). b, schematic diagram conceptually showing the interface between the Ti/Pd electrode and the CNT network. c, SEM image of CNT network in the channel of a p-type TFT; the scale bar in the low magnification SEM image is 10 μm and the scale bar in the high magnification SEM image is 2 μm. d, SEM image of IGZO in an n-type TFT; the scale bar is 5 μm. e, Optical micrograph of the hybrid CNT/IGZO ring oscillators, inverters, individual p-type, and n-type transistors fabricated on a rigid Si/SiO 2 substrate. The inset shows a 501-stage ring oscillator on the rigid substrate. The scale bar in the rigid circuit chip is 500 μm. The scale bar in the 501-stage ring oscillator image is 600 μm. f, Optical photographic image of the hybrid CNT/IGZO ring oscillators, inverters, and individual transistors on a flexible polyimide substrate laminated on a polydimethylsiloxane (PDMS) film. The scale bar in flexible circuit is 2 cm. g, Transfer characteristic in linear and log scale and transconductance of a CNT TFT with gate bias varied from -5 to 5V. L ch = 20 μm, W ch = 100 μm, V DS = 1V. h, Output characteristic of the CNT TFT with V DS varied from -5 to 0V. i, Transfer characteristic in linear and log scale and transconductance of a IGZO TFT with gate bias varied from -5 to 5V. L ch = 4 μm, W ch = 12 μm, V DS = 1V. g, Output characteristic of the IGZO TFT with V DS varied from 0 to 5V. seconds. Then electrodes for the p-type CNT TFTs were defined by photolithography and then formed by E-beam evaporation with Ti/Pd (1 nm/50 nm). The IGZO channels were defined by standard photolithography. Then 50 nm of IGZO thin film was deposited by DC magnetron sputtering at 180 W. Finally the circuits were completed by patterning the electrodes for the n-type IGZO TFTs and metallization of Ti/Au (1 nm/50 nm) with E-beam evaporator. 21 The fabrication of the CNT/IGZO hybrid complementary circuits can be conducted on flexible polyimide substrate with the procedure similar to the aforementioned steps. The only difference is that, initially a layer of polyimide (HD MicroSystems, Inc. PI-2525) was spun on the silicon supporting wafer at a speed of 2000 rpm for 30 seconds. Then it was soft baked at 120 ˚C for 30 seconds, and then at 150 ˚C for 30 seconds. The second layer of polyimide (PI) was spun onto the sample and baked at the same conditions. Then the sample was cured in argon gas at a temperature of 200 ˚C for 30 minutes with a ramping rate of 4 ˚C/min.. Then the temperature was raised to 300 ˚C at a ramping rate of 2.5 ˚C/min., and the temperature was sustained at the same level for 60 minutes. The thickness of the final PI film is approximately 24 μm. The circuits were then fabricated onto the polyimide substrate based on the procedure described in the previous paragraph. The fully fabricated circuits along with the polyimide film was delaminated from the Si/SiO2 substrate, and was then laminated onto a polydimethylsiloxane (PDMS) substrate as a support to form a flexible IC chip. Based on the SEM image of the CNTs in the device channel (Figure 2-1 (c)), it illustrates a uniform network of CNTs. The metrics of performance of the p-type devices can be readily controlled by varying the density of the CNTs in the channel through modification of the CNT incubation time 3 . Figure 2-1 (g) (h) delineate the electrical performance of an individual p- type CNT TFT. The CNT TFT, as expected, exhibits a p-type transistor behavior as shown in the transfer characteristic curve (black curve) of Figure 2-1 (g). The device exhibits a desirable p-type transistor behavior, the typical device on/off ratio (Ion/off) and mobility are ~1 × 10 6 and 8 - 16 cm 2 /Vs respectively. In this device and the devices utilized in the more complicated integrated circuits in our study, the channel length and width of the p-type transistors are 20 μm and 100 μm respectively. The mobility was calculated based on the formula,    GS DS DS ch ch dV dI V C W L   1  , where C was the gate capacitance estimated with the network model 28 . The transistor can be fully saturated as depicted in Figure 2-1 (h). 22 Figure 2-1 (i) (j) illustrate the transfer and output characteristic of an individual n-type IGZO TFT with a channel length of 4 μm and a channel width of 12 μm. The typical Ion/off and mobility of an n-type device are ~4 × 10 6 and ~7 cm 2 /Vs respectively. Based on the results presented in Figure 2-1 (g) and (i), the p-type and n-type devices turn on approximately at -2V and 1.8V, respectively. Circuits operating in complementary mode can be actualized with the desirable p-type and n-type behavior of these TFTs. CNT and IGZO TFT are an ideal pair of materials for complementary integrated circuits. The fabrication process of the devices based on the two materials can be conducted at room temperature, which is compatible with the current flat-panel display manufacturing processes, and it is also desirable for flexible electronics. The mobility of the CNT and IGZO TFTs exceed that of amorphous silicon and organic TFTs 3,33 . 2.3 Hybrid complementary CNT/IGZO inverter, NAND and NOR gates Figure 2-2 (a) illustrates a schematic diagram and an optical micrograph of a hybrid complementary inverter. The supply voltage (VDD) and the ground (GND) of the inverter were connected to 5V and 0V during the characterization. The inverter exhibits an ideal rail-to-rail output voltage behavior as can be seen in Figure 2-2 (b), and the inverter threshold voltage is measured to be at 2.4V, which is nearly half of the VDD. The inverter current was nearly zero when the input bias was below 1.5V or above 3.5V, hence demonstrating the low steady-state power dissipation advantage of having this hybrid complementary TFT structure. The inverter exhibits a voltage gain of 15 as shown in Figure 2-2 (c). Figure 2-2 (d) illustrates the uniformity of the performance of 20 hybrid CNT/IGZO inverters fabricated on flexible polyimide substrate. The 20 inverters were measured in the same region of the chip, and the yield of the circuits is 100%. This demonstrates the reliability and practicality of implementing this hybrid circuit scheme for both rigid and flexible circuit applications. Figure 23 2-2 (e) (h) illustrate the performance of a two input NAND gate and a two input NOR gate fabricated based on the CNT/IGZO hybrid design on rigid substrates. Both of the NAND gate and NOR gate demonstrate a rail-to-rail voltage swing from 0V to 5V at a supply voltage of 5V. This can be attributed to the reliable complementary mode of operation of the CNT/IGZO hybrid design. Figure 2-2 (f) shows the output of the NAND gate returning correctly an output of “0” only when both of the inputs are “1”. In that logic configuration, both of the p-type CNT transistors are turned off. Figure 2-2 (h) illustrates the output of the NOR gate returning correctly an output of “1” only at the condition when both of the inputs are set to “0”. This logic corresponds to both of the n-type IGZO transistors are turned off. The circuits return correct output signal based on the corresponding input logics. NAND and NOR gates are some of the basic building blocks in modern digital integrated circuits. This enables us to further explore the possibility of more complex digital circuits with the hybrid circuit design. 24 0 12345 0 1 2 3 4 5 V IN (V) V OUT (V) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 I DD ( A) 01 2 345 0 2 4 6 8 10 12 14 16 Inverter Gain Input Voltage (V) b c d e f 01 23 45 6 0 1 2 3 4 5 6 V OUT (V) V IN (V) 0 1 2 3 4 5 NAND V DD = 5V Logic "0" = 0 V Logic "1" = 5 V Gate A 0 0 1 1 Output VotlageV  Gate B 0 1 0 1 0 1 2 3 4 5 NOR V DD = 5V Logic "0" = 0 V Logic "1" = 5 V Gate A 0 0 1 1 Output Votlage V  Gate B 0 1 0 1 g h V DD GND V A V OUT V B V A V B V DD V OUT GND V IN V DD V OUT GND a Figure 2-2: Structure and characteristic of a hybrid CNT/IGZO complimentary inverter, a NAND gate, and a NOR gate. a, Schematic diagram and an optical micrograph of a hybrid CNT/IGZO inverter. The scale bar is 200 μm. b, Output voltage and current characteristic of the hybrid inverter. c, Voltage gain of the inverter. d, Output characteristic of 20 hybrid CNT/IGZO inverters fabricated on a polyimide flexible substrate. e, Schematic diagram and an optical micrograph of a hybrid CNT/IGZO NAND gate. The scale bar is 200 μm. f, Output characteristic of a hybrid CNT/IGZO NAND gate. g, schematic diagram and an 25 optical micrograph of a hybrid CNT/IGZO NOR gate. The scale bar is 200 μm. h, Output characteristic of a hybrid CNT/IGZO NOR gate. 2.4 Hybrid complementary CNT/IGZO integrated ring oscillators with 1004 transistors With the ideal inverter behavior manifested by the hybrid CNT/IGZO integrated circuit, the hybrid design enables implementation of 51-stage, 101-stage, 251-stage and 501-stage ring oscillators, and they all generated output signals with rail-to-rail output voltage swing from 0 to 6V. The optical micrographs and output signals of the oscillators are depicted in Figure 2-3 (a) to (h). The schematic diagram in Figure 2-3 (a), illustrates the circuit connection of a 51- stage ring oscillator. In the oscillator, 51 hybrid CNT/IGZO complementary inverters are connected in series with an additional inverter connected at the output of the oscillator functioning as a buffer stage. The circuit configuration is adopted for all of the oscillators presented in this work. The oscillation frequency of ring oscillators decreases with increase in number of stages due to the effect of stage delay. This effect is depicted in Figure 2-3 (i), showing the oscillation frequencies at 1.96 kHz, 1.13 kHz, 648 Hz and 460 Hz for 51-stage, 101-stage, 251-stage and 501-stage ring oscillator, respectively. All of the results were obtained from the circuits fabricated on one single chip, which underscores the reliability of hybrid CNT/IGZO design. The stage delay of the 51- 26 a c e g V OUT i 0 1234 5 0 1 2 3 4 5 6 Voltage (V) Time (ms) 012 345 0 1 2 3 4 5 6 Voltage (V) Time (ms) 0 5 10 15 20 0 1 2 3 4 5 6 Voltage (V) Time (ms) d 0 5 10 15 20 0 1 2 3 4 5 6 Voltage (V) Time (ms) f h 0 100 200 300 400 500 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Frequency (kHz) Ring Oscillator Stages b V DD V OUT GND V DD V OUT GND j 2005 2007 2009 2011 2013 10 100 1000 32 10 33 36 1 37 3 11 12 4 35 38 31 34 13 5 6 14 2 This Work Transistor Count Year Figure 2-3: Structure and output characteristic of 51-stage, 101-stage, 251-stage and 501-stage ring oscillators. a, Optical micrograph and schematic diagram of a 51-stage ring oscillator. Scale bar is 400 μm, b, Output characteristic of a 51-stage ring oscillator. c,d, Optical micrograph of a 101-stage ring oscillator and its output characteristic, respectively. Scale bar is 400 μm. e,f, Optical micrograph of a 251-stage ring 27 oscillator and its output characteristic, respectively. Scale bar is 600 μm. g,h, Optical micrograph of a 501- stage ring oscillator and its output characteristic, respectively. Scale bar is 600 μm. i, Frequency of the output signals of the 51-stage, 101-stage, 251-stage, and 501-stage ring oscillators with respect to the number of stages. j, Comparison of level of integration of CNT-based integrated circuits from 19 published articles and our work. The star circled by red ink corresponds to our work. stage ring oscillator can be calculated with nf 2 1 , n being the number of stages in an oscillator, and f being the oscillation frequency. The stage delay is found to be 5 μs, which is consistent for all the oscillators studied in this report. We note that our ring oscillator performance compares favorably with previously published work 6 . For instance, all of our ring oscillators exhibited rail-to-rail switching between VDD and ground. In comparison, previous work based on p-type-only inverters showed oscillation that reached neither VDD nor ground 6 . We were able to demonstrate the largest integration of CNT-based circuit with a 501-stage ring oscillator which was comprised of 1004 transistors as illustrated in the optical image in Figure 2-3 (g). This LSI circuit is consisted of 501 inverters and a buffer stage. The VDD of the circuit is 6V, and as can be observed in Figure 2-3 (h), the output of the oscillator is showing a rail-to-rail voltage swing. The oscillation frequency of the circuit can reach 460 Hz, which is a result of combination of the stage delay across the circuit. The CNT/IGZO hybrid circuit platform provides a reliable foundation for the integration with such unprecedented level of integration. Figure 2-3 (j) delineates the progress of the level of integration of carbon nanotube based circuits since the Year 2006 including the result from our study and data reported by other research teams 1-6,10-14,35-42 . A general trend of increment in the level of integration can be observed on the graph, and we have realized the first demonstration of large scale integrated circuits, with over 1000 CNT-based transistors. 28 2.5 Hybrid CNT/IGZO dynamic circuits In addition to the static logic gates and ring oscillators, we also demonstrate the implementation of dynamic logic circuits with the CNT/IGZO hybrid scheme. Figure 2-4 (a)- (c) illustrate the performance of a dynamic inverter. In a dynamic inverter, a clock signal is sent into the circuit. When the clock signal is low, M1 is turned on to precharge the output parasitic capacitance to the level of VDD, and M2 is off during this cycle of operation, and hence the input can not affect the output when the clock signal is low. When the clock signal is changed to high, M1 is turned off and now M2 is on, at which the output is determined by the input signal, and this is the evaluating stage. Dynamic gate further reduces static power dissipation and increases the overall switching speed of the circuit. To the best of our knowledge, our report is the first demonstration of using CNT in a dynamic gate integrated circuit. The VDD of the inverter was held at 3V in the middle panel of Figure 2-4 (c), and the clock signal was set at 500 Hz as depicted in the upper panel of the same figure. The middle panel and the lower panel of Figure 2-4 (c) illustrate the output signal versus time for the input signal of “0” and “1”, respectively. As we can see from both of the panels, when clock is low, the output is “1” (near VDD) regardless of the input. When the clock is high, the output is an inverted signal of the input, as expected. Equivalently, the output of the inverter was observed to be near VDD when the input was “0” (Figure 2-4 (c) middle panel), and the output resulted in an inverted signal of the clock when the input was set at “1” (3V) (in the lower panel of the figure). Figure 2-4 (d)-(f) show the circuit and output characteristic of a dynamic NAND gate with a 3V VDD. It generates correct output corresponding to the specific input signals, as illustrated in Figure 2-4 (f), the output is held near the VDD while the input signals are “00”, “01” and “10”. The output returns an inverted signal of the clock when the input equals “11”. A dynamic NOR gate and its output characteristic are exemplified in Figure 2-4 (g)-(i). The 29 correct output signal close to VDD was generated by the dynamic gate when “00” was supplied to the input (Figure 2-4 (i)). The output resulted 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 5 10 15 20 0 1 2 3 Clock (V) "00" "01" "10" "11" OUT (V) OUT (V) OUT (V) OUT (V) Time (ms) 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 5 10 15 20 0 1 2 3 Clock (V) "00" "01" "10" "11" OUT (V) OUT (V) OUT (V) OUT (V) Time (ms) 0 1 2 3 0 1 2 3 0 5 10 15 20 0 1 2 3 Clock (V) IN="0" IN="1" OUT (V) OUT (V) Time (ms) a b c fi de g h M1 M2 30 Figure 2-4: Structure and output characteristic of dynamic inverter, NAND and NOR gate. a,b, Schematic and optical micrograph of a dynamic inverter based on the hybrid CNT/IGZO complementary scheme. Scale bar is 200 μm. c, Output characteristic of the dynamic inverter with a clock signal supplied at 500 Hz and a V DD of 3V. d,e, Schematic and optical micrograph of a dynamic NAND gate. Scale bar is 200 μm. f, Output characteristic of the dynamic NAND gate with a clock signal supplied at 500 Hz and a V DD of 3V. g,h, Schematic and optical micrograph of a dynamic NOR gate. Scale bar is 200 μm. i, Output characteristic of the dynamic NOR gate with a clock signal supplied at 500 Hz and a V DD of 3V. in an inverted signal of the clock when “01”, “10”, and “11” were supplied to the input of the NOR gate. This is the first demonstration of CNT based dynamic inverter, NAND, and NOR gates. It provides evidence that our hybrid circuit scheme can enable the integration of more complicated circuits with the dynamic circuit building blocks. We have demonstrated with our experimental results that the carbon nanotube and IGZO hybrid complementary TFTs can be used as building blocks to realize reliable large scale integrated digital circuits with more than one thousand transistors. Having the circuits operated in complementary mode can minimize the static state power dissipation in the circuits. The p-type CNT TFT transistors are based on semiconducting enriched CNT solution, the performance of the transistors can be further improved by utilizing CNT solution with higher semiconducting purity. We have also demonstrated the operation of the circuits on a flexible polyimide substrate and the reliability of the devices on the substrate. This demonstration allows further development in the implementation of the hybrid CNT/IGZO circuit scheme for flexible electronics. Currently the IGZO thin film employed in our circuits were fabricated with the sputtering technique, however the material can also be printed during the fabrication procedure 43 . CNT thin film has also been demonstrated to exhibit desirable printability and performance for printed electronics 44 . For future development, the hybrid CNT/IGZO complementary circuit configuration can be investigated for large-scale, low cost and reliable printed electronics applications. This hybrid CNT/IGZO complementary circuit scheme enables the advancement toward integration of more sophisticated circuits with higher level of computing functionality. 2.6 Summary There have been demonstrations of small to medium scaled carbon nanotube (CNT) based integrated circuits (ICs) for applications in digital circuits, flat-panel display, transparent and flexible electronics, and CNT computer. The next milestone would be large-scale integrated (LSI) circuits, defined as an integration of at least 1000 transistors, however, has yet been 31 realized. In order to aggrandize the level of integration, a reliable, scalable and low static power consumption circuit scheme must be explored. Here we demonstrate the largest integration of CNT-based complementary circuit, with 1004 transistors integrated in a 501- stage ring oscillator. In this LSI circuit, CNT and indium gallium zinc oxide (IGZO) thin film are used as the channel materials in the p-type and n-type transistors, respectively. We also demonstrated complementary inverter, NAND and NOR gates, dynamic logic gates, and ring oscillators with different stages. The hybrid circuits have also been fabricated on flexible substrates for flexible electronics. 32 2.7 References 1 Cao, Q. et al. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature 454, 495-500 (2008). 2 Shulaker, M. M. et al. Carbon nanotube computer. Nature 501, 526-530 (2013). 3 Wang, C., Zhang, J. & Zhou, C. Macroelectronic Integrated Circuits Using High- Performance Separated Carbon Nanotube Thin-Film Transistors. ACS Nano 4, 7123- 7132 (2010). 4 Sun, D.-m. et al. Flexible high-performance carbon nanotube integrated circuits. Nat Nano 6, 156-161 (2011). 5 Gao, P., Zou, J., Li, H., Zhang, K. & Zhang, Q. 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Nano Letters 13, 954-960 (2013). 35 3 Improving device performance to achieve high performance and low hysteresis carbon nanotube thin film transistors. 3.1 Introduction Separated semiconducting enriched single-walled carbon nanotube (SWCNT) random network thin films have been proven to be an excellent semiconducting material providing high electrical performance for thin film transistors (TFTs), which can be utilized in the development of macroelectronics and flexible macroelectronics 1-13 . Organic materials have also been investigated for TFTs used in flexible or printable macroelectronics due to its desirable inherent flexibility and its compatibility with solution-based processing 14-18 . Organic thin film transistors (OTFTs) had been subjected to low device mobility 14, 17, 19 . Researchers have recently made significant improvement on the mobility of OTFTs in the past few decades 14, 17, 18, 20 . However, in order to actualize OTFT in commercial applications, the issues of operational stability and environmental stability associated with OTFTs are yet to be addressed 14, 17 . Hydrogenated Amorphous silicon (a-Si:H) TFTs have been widely used as the pixel driving circuitry for flat panel active matrix liquid crystal display (AMLCD) 21 , which is voltage driven. However, the low mobility of a-Si:H TFTs, thus low current density limits its implementation in pixel driver circuits for active matrix organic light emitting diode (AMOLED) display, a current driven system 22, 23 . Although polycrystalline silicon has been demonstrated to be an excellent TFT material with high device mobility 21, 24 , but its lack of flexibility inhibits it from being utilized in flexible macroelectronics. 36 On the other hand, CNT TFT has been manifested to show great potential for macroelectronics and flexible macroelectronics 1, 2, 4, 6, 7, 11, 25-30 . CNT TFT exhibits relatively high mobility which enables it to be used in the pixel driver circuits for flat panel AMOLED display, and an OLED pixel requires approximately 10 μA of current to drive a 300 × 300 μm monochrome pixel 22 . CNT solution can be processed in room temperature to be fabricated into TFTs, and CNT exhibits excellent flexibility and transparency, hence it can be a potential candidate for high performance flexible and transparent macroelectronics 5, 28, 29, 31, 32 . In addition, CNT is printable which paves way for its utilization in the development of low-cost printable electronics 11, 26, 30, 33-35 . Separated semiconducting enriched CNT has been used in many applications for macroelectronics as mentioned earlier. In an earlier chapter of my dissertation, I even reported the first demonstration of large-scale integrated hybrid complementary macroeletronic circuit using CNT and IGZO thin film transistors 1 . However, there is room for improvement for the CNT TFTs employed in the previous work in terms of their mobility and current density. Researchers have demonstrated that the electrical properties of CNT thin films can be ameliorated by using CNTs with higher semiconducting purity 12, 36-38 . In addition, the CNT TFTs still exhibit hysteresis window greater than 1 V in the previous work, which is deleterious for circuit operations due to the inconsistent threshold voltage. Methods of encapsulation of CNT TFTs with different polymers and dielectric materials have been proposed to reduce hysteresis of CNT TFTs in ambient 37, 39-41 . Here, I report a comparison of three types of extracted carbon nanotubes, namely 99.9%, 99%, and 1R Raymor tubes with different semiconducting purity and different length in terms of their electrical properties in TFTs. The results of the comparison demonstrate that the 99.9% 37 CNT-based TFTs exhibit the highest mobility (> 30 cm 2 /Vs) and the highest on-current density (> 1 μA/ μm) amongst the TFTs comprised from these three types of CNTs. The 99.9% CNT can be used in the future development of flexible and printable electronics. The hysteresis issue of the CNT TFTs in ambient is alleviated by encapsulating the CNT TFTs with a layer of SPR3612 photoresist in this study. The photoresist can reduce the level of O2 and water molecules on the surface of CNTs, hence abating the effect of hysteresis. I have demonstrated the passivation scheme can reduce the hysteresis window of the CNT TFTs by half. And it has also been proven that this scheme is a generic method to reduce hysteresis, as shown by applying the passivation method on converted n-type CNT TFTs. This provides opportunities for the exploration of high performance, low hysteresis complementary circuits based on p-type and n-type CNT TFTs. 3.2 Carbon nanotube comparison based on 99.9%, 99% semiconducting enriched and 1R Raymor carbon nanotubes The length and semiconducting enrichment are two important factors in selection of CNT solution for TFT applications 10, 12, 13 . CNTs with longer length can contribute the reduction in tube-tube junctions in the channel in a CNT TFT, hence improving the mobility of the TFTs. On the other hand, semiconducting enrichment or purity of CNTs can result in TFTs with improved gate control and better current on/off ratio (Ion/Ioff) of the devices. In my previous work of large-scale complementary hybrid CNT and indium gallium zinc oxide (IGZO) circuits 1 , 98% semiconducting enriched CNT thin film was used as the channel for p-type CNT TFTs. Based on the aforementioned factors, the performance of the hybrid circuits can be drastically improved with longer and highly semiconducting enriched CNTs. Three types of carbon nanotubes have been selected for this study on improving CNT TFT electrical performance, which are the 99.9% semiconducting enriched CNT (Nanointegris 38 Technologies, Inc.), 99% semiconducting enriched CNT (Nanointegris Technologies, Inc.), and 1R Raymor. The 99.9% and 99% CNT solution was used for this study as purchased from Nanointegris. The 1R Raymor CNT solution was provided by my colleague Hui Gui, who carried out Raymor CNT dispersion, extraction and length sorting processes to obtain high purity and long semiconducting 1R Raymor CNT solution. The three types of CNT solution was deposited onto Si/SiO2 substrates (50 nm thermally grown oxide, p-type, 0.005 Ωcm) for morphological characterization. The 99.9% CNT is in xylene solution, and in order to form a thin film of the CNT, it was firstly deposited to cover the entire surface a piece of Si/SiO2 (50 nm thermal oxide) substrate with pipette by drop-casting. Following the drop-casting, the incubation of the solution on the substrate was carried out for 15 minutes. Then the sample was immersed in toluene for removal of organic residue, and followed by N2 drying. Following the cleaning step, the sample was baked on hotplate in ambient at 200 ˚C for 1 hour 38 . For the 99% CNT solution, the deposition procedure is described by the following. Firstly, the surface of the Si/SiO2 is functionalized with poly-L-lysine (poly-L-lysine (0.1% wt in water from Ted Pella) by drop-casting to form amine-terminated surface. The surface of the sample is then exposed in the solution environment for 6 minutes. Then, the sample is cleansed with deionized (DI) water thoroughly, and followed by N2 drying. Secondly, the 1R Raymor CNT solution is dispersed onto the surface of the functionalized sample, and the sample is incubated in the solution for 14 hours and 38 minutes. After completion of the incubation, the sample is thoroughly cleansed with DI water, followed by N2 drying. Finally, the sample is baked on hotplate at 120 ˚C for 1 minute. The 99% CNT solution was deposited onto a Si/SiO2 (50 nm thermal oxide) following the similar procedure as that employed for the 99% CNT, but the only exception is that the CNT incubation time for the 1R Raymor CNT solution was shortened to 5 hours. The purity of the 1R Raymor CNTs was estimated to be 99% based on the absorption spectrum and the comparison with reported results 42 . 39 In Figure 3.1a-c, they illustrate the scanning electron microscopic images of the 99.9%, 99%, and 1R Raymor CNT thin films, respectively. Thin films of percolation network of randomly oriented CNTs are formed for all three types of CNTs based on the SEM images. The nanotube length of 99.9% CNT is estimated to fall between 1 and 2 μm; the length of 99% CNT is approximately to be less than 1 μm; and the length of 1R Raymor CNT is around 1 μm. It is shown by the SEM images that 99.9% CNTs exhibit the longest length among the three types of nanotubes. From the aforementioned discussion, this is advantageous for the formation of CNT thin films with smaller number of tube-tube junctions, hence can result in improved CNT TFT mobility. Thin film transistors with common back-gate structure based on the three types of CNTs were fabricated, in order to evaluate the electrical characteristics of the three types of CNTs. The fabrication procedure of the TFTs is given by the following. Firstly, photolithography was conducted to transfer drain and source (D/S) electrode patterns from a photomask onto the three types of CNT samples, and the samples were prepared by the CNT deposition method mentioned in earlier sections of the article. Then it was followed by metallization using electron beam evaporation to deposit Ti (1nm) and Pd (50 nm) for the devices, and then lift- off process was carried out to define the electrodes. Secondly, a second photolithography process was conducted to transfer a pattern from a mask to the samples to define the CNT channel geometry of the devices. Finally, the samples were placed in an oxygen plasma asher to etch the CNTs outside of the channel of the devices’. The CNT etching step was in place to define the channel length and channel width of the devices, hence allowing for more accurate estimation of the effective device mobility. 40 2 μm 2 μm 2 μm a) b) c) Figure 3.1: SEM images of 99.9%, 99% and 1R Raymor carbon nanotubes. (a) SEM image of 99.9% semiconducting enriched CNT thin film at 20x magnification. (b) SEM image of 99% CNT thin film at 20x magnificatoin. (c) SEM image of 1R Raymor CNT thin film at 20x magnification. Following the aforementioned fabrication procedure of CNT TFTs, devices with channel length (L) of 4, 10, 20, 50, and 100 μm, and channel width (W) of 200, 400, 800, 1200, and 1600 μm were fabricated for characterization of the electrical performance of the 99.9%, 99% and 1R Raymor CNTs, and the results are delineated in Figure 3.2. Figure 3.2 (a-c) illustrate the normalized transfer characteristic of 99.9% CNTs (Figure 3.2a), 99% CNTs (Figure 3.2b), and 1R Raymor CNTs (Figure 3.2c) with a variation of channel length of L = 4, 10, 20, 50, 41 and 100 μm. The drain current values are normalized with W = 400 μm and plotted in logarithmic scale. The measurements were conducted under drain source voltage (VDS) of 1 V. All of the TFTs exhibit p-type transistor behavior as illustrated in Figure 3.2 (a-c). The three figures also illustrate that the Ion/Ioff increases as the channel length of the devices increase, while the on-current decreases with increase channel length. The Ion of 99.9% and 1R Raymor CNT TFTs is higher than that of 99% CNT devices. The transfer characteristic of 99.9%, 99% and 1R Raymor CNT TFTs with the geometry of L = 4 μm and W = 400 μm is delineated in Figure 3.2 (d-f). The graph illustrates the Drain Current versus the Gate Voltage (VG) in both linear (black) and logarithmic scale (blue) and the Transconductance versus Gate Voltage (red). A Drain voltage of 1 V was used in all measurements for the data delineated in the three plots. The on-current density (Ion/W) at VG = -5 V for the 99.9% CNT TFT is extracted from the curve and it is 0.8 μA/ μm, the Ion/Ioff = 1.5 × 10 5 , and the transconductance (gm) of the device is 107 μS as extracted fromFigure 3.2 (d). For the 99% CNT device, the current density is 0.6 μA/ μm, the Ion/Ioff is 1.4 × 10 5 , and the gm is 70 μS as extracted from Figure 3.2 (e). For the 1R Raymor CNT TFTs, the current density is 0.58 μA/ μm, the Ion/Ioff is 1.9 × 10 5 , and the gm is 105 μS Figure 3.2 (f). These data demonstrate that the CNT TFT comprised of both 99.9% and 1R Raymor CNT thin films exhibit higher current density and transconductance than the 99%-based CNT TFT. In terms of the on-current density, these results agree with those shown in Figure 3.2 (a-c). This primarily can be attributed to the length of the carbon nanotubes. As it was mentioned earlier, 99.9% and 1R Raymor CNTs exhibited longer length than 99% CNTs, hence reduces the tube-tube junctions in a CNT network, which as a result enhances the on-current density and transconductance of the devices. The output characteristics, Drain Current versus Drain Voltage measured from the 99.9% CNT TFT, the 99% CNT TFT, and the 1R Raymor CNT 42 TFT are shown in Figure 3.3 (a-c). The linear and saturation regions can be observed in the output characteristics, resembling the ideal output characteristic of silicon transistors. -4 -2 024 10 -9 10 -7 10 -5 10 -3 10 -1 10 1 L = 4 m L = 10 m L = 20 m L = 50 m L = 100 m I D /W ( A/ m) Gate Voltage (V) V DS = 1 V 99.9% CNT -4 -2 0 2 4 0 50 100 150 200 250 300 350 Gate Voltage (V) Drain Current ( A) 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 Drain Current (A) V DS = 1V 99.9% CNT -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Transconductance ( S) -4 -2 0 2 4 0 50 100 150 200 250 Gate Voltage (V) Drain Current ( A) 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 Drain Current (A) V DS = 1V 99% CNT -10 0 10 20 30 40 50 60 70 80 Transconductance ( S) -4 -2 0 2 4 10 -10 10 -8 10 -6 10 -4 10 -2 10 0 L = 4 m L = 10 m L = 20 m L = 50 m L = 100 m I D /W ( A/ m) Gate Voltage (V) V DS = 1 V 99% CNT -4 -2 024 10 -10 10 -8 10 -6 10 -4 10 -2 10 0 L = 4 m L = 10 m L = 20 m L = 50 m L = 100 m I D /W ( A/ m) Gate Voltage (V) V DS = 1 V 1R Raymore -4 -2 0 2 4 0 50 100 150 200 250 Gate Voltage (V) Drain Current ( A) 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 Drain Current (A) V DS = 1V -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Transconductance ( S) 1R Raymore a) b) c) d) e) f) Figure 3.2: Electrical properties of back-gated TFTs based on the 99.9%, 99% and 1R Raymor CNT thin films. (a-c) Normalized transfer characteristic (I D/W Vs. Gate Voltage) of CNT TFTs based on 99.9% CNTs (a), 99% CNTs (b), and 1R Raymor CNTs (c) with channel length variation (L = 4 μm, 10 μm, 20 μm, 50 μm, and 100 μm) and with channel width, W = 400 μm. The graph is delineated in logarithmic scale. (d-e) Transfer characteristics (black: linear; blue: logarithmic scale) and g m Vs. Gate Voltage characteristics (red) of typical CNT TFTs based on 99.9% CNTs (d), 99% CNTs (e), and 1R Raymor CNTs (f) with a device geometry of L = 4 μm and W = 400 μm. 43 -5 -4 -3 -2 -1 0 -1600 -1400 -1200 -1000 -800 -600 -400 -200 0 200 V GS = -5 V Drain Current ( A) Drain Voltage (V) V GS = -5 to 5 V 1 V step 99.9% CNT -5 -4 -3 -2 -1 0 -1000 -800 -600 -400 -200 0 V GS = -5 V Drain Current ( A) Drain Voltage (V) V GS = -5 to 5 V 1 V step 99% CNT -5 -4 -3 -2 -1 0 -1200 -1000 -800 -600 -400 -200 0 Drain Current ( A) Drain Voltage (V) V GS = -5 to 5 V 1 V step V GS = -5 V 1R Raymor a) b) c) Figure 3.3: Output characteristic (Drain Current versus Drain Voltage) of CNT TFT fabrcated from 99.9% CNT thin film (a), 99% CNT thin film (b), and 1R Raymor CNT thin film (c). In order to thoroughly study and evaluate the CNT TFTs based on the 99.9%, 99%, and 1R Raymor CNTs, the data of several important performance metrics, such as the device mobility, current on/off ratio, current density was collected.Figure 3.4(a) illustrates the change in the average mobility of the CNT TFTs based on the three types of CNTs at different channel 44 length. Twenty devices were measured for each kind of the three CNT thin films with channel width of W = 200, 400, 800, 1200, 1600 μm, and with channel length of L = 4, 10, 20, 50, and 100 μm. The mobility was calculated based on this model, W g C V L m ox D effect    , where effect  is the effective device mobility, L and W are the channel length and channel width of the device, respectively; VD is the drain voltage, gm is the transconductance and Cox is the oxide capacitance of the device. The Cox is given by an analytical model in the mobility calculation based on equation (3-1). CQ is the quantum capacitance of the nanotubes with a value of 4 × 10 -12 F/cm. Λ0 -1 is the carbon nanotube density measured by tubes/ μm; tox is the thickness the dielectric material which is the 50 nm oxide in this case; R is the radius of the nanotubes; ε0 and εox are the permittivity of free-space and the dielectric constant of the insulator material, respectively 2 . (3-1)  1 0 1 0 0 0 1 2 sinh ln 2 1                         ox ox Q ox t R C C As it can be observed in Figure 3.4(a), the average mobility of the TFTs comprised of 99.9% CNT and 1R Raymor CNT is in average almost a factor higher than that exhibited by the TFTs based on 99% CNTs. As it was discussed in an earlier section, this again can be attributed to the length of the CNTs. Both 99.9% and 1R Raymor CNTs exhibit longer length than 99% CNTs, hence less tube-tube junctions are formed in the CNT thin film channels of the TFTs, resulting in higher mobility. The CNT TFTs comprised of 99.9% CNTs exhibit average mobility of greater than 30 cm 2 /Vs. In Figure 3.4 (b), it shows the average Ion/Ioff versus various channel length for devices based on the three types of CNTs. The current- on/off ratio increases as the channel length of the devices increases from 4 μm to 10 μm as shown in the figure. This can be ascribed to the decrease in probably of formation of percolation network of metallic CNT path in longer channels. The TFTs fabricated from the 45 99.9%, 99%, and 1R Raymor CNTs all exhibit Ion/Ioff of greater than 10 6 when the device channel length is greater than 4 μm. This can be associated with the high percentage of semiconducting CNT enriched in the three types of CNT solution ( ≥ 99% semiconducting enriched). There is a noticeable drop in the Ion/Ioff for CNT TFTs with channel length longer than 20 μm. This phenomenon can be associated with the limitation of equipment (Agilent 4156B Semiconducting Parameter Analyzer) used for the electrical property characterization 12 . As the channel length of the devices increases, both of the Ion and Ioff should reduce accordingly. However, the noise level of the analyzer is 1 pA, and as the Ioff decreases below that level, the analyzer can no longer capture the true Ioff exhibited the devices. Figure 3.4 (c) depicts the relationship between the average normalized on-current density (Ion/W) and the inversed channel length (1/L). It can be observed that the Ion/W increases with decreased channel length for all of the TFTs comprised of the three types of CNTs. However, TFTs based on the 99.9% CNTs exhibits the highest overall Ion/W in comparison with the TFTs fabricated based on the other two types of CNTs. This result is consistent with the result shown in Figure 3.2 (a), which can be ascribed to the longer CNT length in the 99.9% tubes. Figure 3.4 (d) demonstrates the relationship between the Drain Current passing through the CNT thin film channels of the TFTs and the channel width. As expected the Drain current increases with the channel width due to the increase in the number percolation network conduction path in the channel of the TFTs. Based on the data illustrated in Figure 3.2 and Figure 3.4, the 99.9% CNT is a better nanotube for thin transistors in terms of its mobility, on-current density and current on/off ratio in comparison with the 99% and 1R Raymor CNTs. 46 99.9% CNT 99% CNT 1R Raymor 0 2040 6080 100 1 10 100 Mobility (cm 2 /Vs) Channel Length ( m) 99.9% CNT 99% 1R Raymor 0 20406080 100 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 I on /I off Channel Length ( m) 99.9% CNT 99% CNT 1R Raymor 0.00 0.05 0.10 0.15 0.20 0.25 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 I on /W ( A/ m) 1/L ( m -1 ) a) b) c) d) 0 500 1000 1500 10 -6 10 -5 10 -4 10 -3 Drain Current ( A) Channel Width ( m) L = 10 m 99.9% CNT 99% CNT 1R Raymor Figure 3.4: Statistical study and comparison of electrical performance metrics between CNT TFTs comprised of 99.9% CNT thin films, 99% CNT thin films, and 1R Raymor thin films. (a) Average CNT TFT mobility measured at different channel length for the TFTs with the 99.9% CNT thin films, the 99% CNT thin films, and the1R Raymor thin films. (b) Average current on/off ratio (I on/I off) measured at different channel length for the same CNT TFTs. (c) Average current density (I on/W) versus the inversed of the channel length. (d) Drain current of CNT TFTs based on the three types of CNT thin films with channel length of 10 μm versus different channel width. 3.3 Abatement of hysteresis in both p ‐type and n ‐type carbon nanotube TFTs in ambient In the previous section, a thorough comparison was conducted for three types of CNTs, namely, the 99.9%, 99%, and the 1R Raymor CNTs on their electrical properties. The 99.9% CNT was selected based on the results as a viable channel material that provides high electrical performance for thin film transistors. Another congenital issue related to CNT-TFTs operating in ambient is the large hysteresis, which is detrimental to circuit operations due to the inconsistent threshold voltage for the devices 37, 39-41 . Figure 3.5 (a) illustrates a schematic 47 diagram of a passivation scheme to reduce hysteresis in CNT TFTs in ambient environment. The schematic diagram shows a cross-sectional diagram of a common back-gate CNT TFT with its channel area covered with a bi-layer photoresist overlaying structure, and with the entire device encapsulated by a layer of SPR3612 photoresist. The fabrication process of the aforementioned device was described in an earlier section in this chapter, and photolithography process employed for the fabrication is based on a bi-layer process. The bi-layer photoresist process is a common process used in lift-off lithography, and the detail description of the process procedure is given by the following. Firstly, a layer of approximately 200 nm of a sacrificial lift-off layer, LOL2000 (MicroChem, Corp.) is spun onto the specimen by a spinner at 3000 rpm for 30 seconds, and it is followed by soft baking of the specimen on hotplate at 170 ˚C for 10 minutes. Secondly, a layer of approximately 1 μm of positive photoresist SPR3612 (MicroChem, Corp.) is spun onto the sample at 5500 rpm for 30 seconds, and it is followed by soft baking of the sample on hotplate at 90 ˚C for 1 minute. Thirdly, an alignment and exposure process is carried to transfer patterns on a photomask onto the photoresist, and the dose of the exposure is 24 mJ/cm 2 . Finally, the specimen can be developed in a developer, MF-26A (MicroChem, Corp.) for 1 minute to release the pattern. The LOL2000 is not a photosensitive material, however, it is developed at a faster rate than the SPR3612, thus leaving an overhang of the photoresist layer. After the last procedure of the CNT TFT fabrication, the O2 plasma etching of CNTs outside of TFT channels, there remains the bi-layer photoresist layer, and it was discovered in this study that the hysteresis of the as-fabricated CNT TFT can be abated by encapsulating the surface of the sample with SPR3612 after the abovementioned process. The encapsulation is carried out by spin coating a layer of approximately 1 μm of SPR3612 at 5500 rpm for 30 seconds on the surface of the specimen, and it is followed by softbaking of the sample on hotplate at 90˚C for 1 minute. The transfer characteristic of a CNT TFT device before and after photoresist, 48 SPR3612 encapsulation is shown in Figure 3.5 (b) and (c) in linear and in logarithmic scale, respectively. The device geometry is L = 4 μm, and W = 200 μm, and 99.9% CNT is used as the channel material for the device. In addition, the device was characterized under the VDS of -1 V. The CNT TFT exhibits p-type transistor behavior before and after the photoresist passivation as shown in the figure. The hysteresis window measured at the widest point on the transfer characteristic for the CNT TFT without passivation is 1.7 V and the hysteresis for the device after passivation is 0.52 V. This demonstrates an abatement of 1.18 V corresponds to a reduction of more than half of the original hysteresis window. And it can also be observed from Figure 3.5 (b) that the device maintains its p-type enhancement mode behavior after the passivation. Oxygen and water molecule have known to be one of the causes of hysteresis in CNT TFTs measured in ambient 43, 44 . The reduction in hysteresis of the CNT TFT device can be attributed to the removal of oxygen and water molecule during the encapsulation process. -5-4-3-2-1 0 1 2345 -25 -20 -15 -10 -5 0 CNT CNT + Passivation Drain Current ( A) Gate Voltage (V) V DS = -1 V -4 -2 0 2 4 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 CNT CNT + Passivation V DS = -1 V Drain Current ( A) Gate Voltage (V) b) c) a) Si SiO 2 Ti/Pd SPR 3612 CNT Figure 3.5: Schematic diagram and transfer characteristic of p-type CNT TFT with and without passivation. (a) Cross-sectional schematic diagram of a p-type common back-gate CNT TFT with SPR 3612 positive photoresist passivation. (b) Transfer characteristic of a CNT TFT common back-gate device before (black) and after (red) passivation of the device with SPR 3612 photoresist. (c) The transfer characteristic of the device in logarithmic scale. 49 In graphs shown in Figure 3.6 delineate statistical study of the electrical properties of 18 CNT TFTs before and after the S3612 passivation. Figure 3.6 (a) illustrates the hysteresis window measured from 18 CNT TFTs before and after S3612 passivation, and the red bars correspond to results obtained from devices after passivation, and the black bars correspond to results obtained before passivation. The results conspicuously show that the majority (13/18 devices) of the CNT TFTs with passivation exhibit hysteresis window half of that exhibited by the same devices before passivation. It is clear that the SPR3612 has exerted positive effect on the reduction of hysteresis in all of the measured devices. The majority of the passivated CNT TFTs exhibit hysteresis window between 0.4 and 0.6 V, and on the other hand, the non- passivated devices show hysteresis window between 1 and 1.2 V, and 1.4 and 1.6 V. In terms of subthreshold voltage swing (SS), the SPR3612 layer does not vary the SS significantly for the devices. Figure 3.6 (c) illustrates that the device mobility of the majority of the devices with passivation is lower than exhibited by the devices without passivation. Fifteen out of eighteen of the passivated devices exhibit mobility between 8 and 12 cm 2 /Vs. On the other hand, 16/18 un-passivated devices evince mobility between 12 and 20 cm 2 /Vs. In Figure 3.6 (d), it shows the threshold voltage of the 18 devices before and after passivation. There is no significant change in the Vth after the devices were passivated. It was introduced in Chapter 3 of my dissertation that an innovative method to integrate p- type CNT TFT and n-type IGZO TFT to form circuits operating in complementary mode 1 . However, it has also been demonstrated that p-type CNT TFT can be converted into transistors with n-type behavior by passivation using ALD HfO2 45, 46 . During the ALD process, the O2 molecule is removed from the surface of CNTs, and they are passivated by HfO2. Hafnium oxide dielectric layer contains positive fixed charge due to the reaction between HfO2 and moisture, which induces negative charge on the surface of metal electrodes 50 and CNT interfaces, hence causing the energy bands in the CNT channel to bend downward resulting in a narrower Schottky barrier width for the conduction band (EC) of the CNT; by apply a positive bias to the gate of the CNT TFT, the energy band of the CNT is bent farther down, thus further narrowing the barrier width between the metal and the CNT. The aforementioned phenomenon can result in conduction of electron through the CNT channel in the CNT TFT, hence a conversion of the CNT TFT from a p-type behavior to an n-type behavior in ambient 45, 46 . However, hysteresis can be still observed in the transfer characteristic measured from the n-type CNT TFTs manifested with this method. 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2 4 6 8 10 12 14 16 CNT + S3612 CNT Number of Devices Hysteresis (V) 0.0 0.1 0.2 0.3 0.4 0 2 4 6 8 10 CNT + S3612 CNT Number of Devices Subthreshold Swing (V/decade) -1.6 -1.2 -0.8 -0.4 0.0 0 2 4 6 8 CNT + S3612 CNT Number of Devices Threshold Voltage (V) 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 CNT + S3612 CNT Number of Devices Mobility (cm 2 V -1 s -1 ) a) b) c) d) Figure 3.6: Statistical study of the hysteresis (a), subthreshold voltage swing (b), mobility (c), and threshold voltage (d) of 18 CNT TFTs with L = 4, W = 200 μm before and after S3612 passivation. The red bars correspond to CNT TFTs with passivation, and the black bars correspond to the CNT TFTs without passivation. 51 In order to demonstrate that the aforementioned SPR3612 encapsulation is a generic method for the abatement of hysteresis in CNT-based TFTs, it was also applied on n-type ALD converted CNT TFTs. The fabrication process for the converted n-type CNT TFTs is briefly given by the following. Firstly, a p-type CNT TFT is fabricated based on the procedure mentioned in earlier part of the chapter. Then it is followed by the removal of the SPR3612 and LOL2000 covering the channel area of the TFTs with acetone and developer consecutively. Secondly, a layer of approximately 40 nm of Al2O3 dielectric material was deposited on top of the devices by atomic layer deposition (ALD, Fiji model, by Ultratech/CambridgeNanoTech) at 200˚C. Then the devices can be characterized and showing n-type behavior. The transfer characteristic of a CNT TFT with a channel geometry of L = 20 and W = 200 μm before the ALD Al2O3 deposition is delineated as the black curve shown in Figure 3.7 (a). It can be observed that the transistor exhibits p-type behavior with an Ion of 4.5 μA and Ion/Ioff of 1.2 × 10 5 with a hysteresis window of 1.25 V. Then after the Al2O3 was deposited onto the device, it was converted into a TFT with n-type behavior shown as the red curve in the same figure. The Ion is 1.5 μA and the Ion/Ioff is now 1.6 × 10 4 with a hysteresis window of 3.4 V. The decrease of the Ion after ALD deposition can be attributed to the coating of the dielectric material around CNTs can introduce additional sites for trap charges at the interface between the CNTs and the top dielectric material, hence reducing the current of the devices. In order to reduce the hysteresis of the converted n-type CNT TFT, the aforementioned SPR3612 passivation scheme was applied to the device, and the transfer characteristic of the passivated device is depicted as the blue curve in Figure 3.7 (a). To lucidly demonstrate the change in hysteresis of the device before and after SPR3612 encapsulation, the transfer characteristic of the device under ambient condition (black curve), with ALD conversion (red curve), and with SPR3612 passivation (blue curve) is plotted in logarithmic scale. The hysteresis window of 52 the passivated n-type device is extracted to be 0.15 V, which demonstrates the SPR3612 can effective reduce the hysteresis in the device. -4 -2 0 2 4 0 1 2 3 4 5 w/o ALD with ALD with ALD + PR Drain Current ( A) Gate Voltage (V) V DS = 1 V -4 -2 0 2 4 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 V DS = 1 V w/o ALD with ALD with ALD + PR Drain Current ( A) Gate Voltage (V) a) b) Figure 3.7: Transfer characteristic of p-type CNT TFT, converted n-type CNT TFT of the same device before and after SPR3612 passivation. (a) Transfer characteristic of a p-type CNT TFT (black), converted n-type CNT TFT from the same device (red), and converted n-type CNT TFT with passivation (blue). (b) Transfer characteristic plotted in logarithmic scale. 3.4 Summary In conclusions, I have compared the electrical properties of CNT TFTs based on three types of carbon nanotubes, namely the 99.9% CNT, 99% CNT, and the 1R Raymor CNT. The results of the comparison the CNT TFTs comprised of the 99.9% CNT exhibit more superior electrical performance than the other two types of CNTs in terms of the devices’ mobility and on-current density. This can be attributed to the higher semiconducting purity and the longer length of the CNT. These properties give rise to the highest average mobility of greater than 30 cm2/Vs, and on-current density of greater than 1 μA/ μm for the 99.9% CNT TFTs. Secondly, I have demonstrated an effective method to reduce the hysteresis of CNT TFTs in ambient, which is to encapsulate the devices in a positive photoresist, SPR3612. The method has proven to have reduced the hysteresis window of the TFTs by half, approximately from 1 V to 0.5 V. This has also been verified to a generic method. The hysteresis exhibited in ALD Al2O3 converted n-type CNT TFTs was also suppressed by the encapsulation method. 53 3.5 References 1. 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Nanotechnology 2010, 21, 165201. 56 4 Bulk Synthesis of Crystalline and Crystalline ‐ Core/Amorphous ‐Shell Silicon Nanowires and Their Application for Energy Storage 4.1 Introduction Silicon micro- and nano-structures have captivated much attention since 1964 due to the interest in studying of the effect of diminution of size and dimension on its physical properties. 1-5 Silicon nanowire has been exploited for its application as a building block in bottom-up nanoelectronics, 6, 7 photovoltaics, 8-10 biosensors, 11 and energy storage devices. 12 Having the ability to synthesize high quality and large quantity of Si nanowires is an important factor in the process to investigate the electrical, optical and electrochemical properties of the material and in realization of the aforementioned applications. In many of the studies, crystalline and crystalline-core/amorphous-shell (c-core/a-shell) Si nanowires were synthesized via the vapor-liquid-solid (VLS) mechanism, 1, 13 however, very often in small quantity. Si nanowires have been synthesized on many different substrates. For instance, vertically grown Si whiskers were synthesized on Si (111) wafer first reported by R. S. Wagner and he conducted thorough fundamental study on the growth mechanism of this nanomaterial. 1 Y. Cui et al. conducted investigation in the relationship between the size of the catalyst and the diameter of the resulting Si nanowires on Si/SiO2 wafers. 14 C. K. Chan et al. underwent study of the electrochemical properties of Si nanowires on stainless steel as an anode material for Li-ion batteries. 12 These syntheses can be defined as growth on two dimensional (2-D) planar substrates, and often relatively small quantity of nanowires is grown with this method. The ability to synthesize bulk quantity of Si nanowires is advantageous in many of the aforementioned applications. Different mechanisms for achieving growth of bulk quantity of nanowires have been actively studied. 5, 15-19 In particular D. Wang et al. explored the concept of synthesis of high quantity of germanium nanowires on irregular silica particles. 57 In his experiments, he had proven that higher quantity nanowires can be produced by replacing the 2-D substrates with three dimensional (3-D) substrates. 17, 18 One of the many important applications of Si nanowires in bulk quantity is the study of expending Si nanowires as the active material in the anode of Li-ion batteries. In a traditional slurry electrode fabrication process, which is used for commercialized batteries, a current collector is coated with a layer of slurry of amalgamation formed by active materials, composite of ionic conduction, and binder. 20 Tens of milligrams of the active material are required in the processing of traditional slurry electrodes. Synthesis of silicon nanowire in bulk quantity can enable the material to be adopted in the commercially compatible slurry electrode fabrication process. In this paper, we report a scalable methodology for synthesis of Si nanowires via the vapor-liquid-solid (VLS) mechanism. The nanowires were synthesized three-dimensionally (3D) on aluminum oxide (Al2O3) millimeter spheres decorated with gold (Au) nanoclusters. Both single crystalline and crystalline-core/amorphous-shell (c-core/a-shell) Si nanowires were obtained with this method by varying the growth recipe. The crystallography of the nanowires was characterized by high resolution transmission electron microscopy (HRTEM) and electron diffraction patterns. The c-core/a-shell Si nanowires were utilized as the active anode material in Li-ion battery half-cells to demonstrate an application of the Si nanowires grown with this scalable method. The specific capacity of the half cells was sustained at 1100 mAh/g after 60 cycles as measured in the galvanostatic charge-discharge experiment. 4.2 Bulk synthesis of silicon nanowires In order to achieve synthesis of Si nanowires in a scalable manner, Al2O3 spheres with diameters of ranging from 0.79 to 1.18 mm (GlenMills, Inc.) were used as the supporting substrate for the synthesis. In this study, the Si nanowires were synthesized in a low-pressure 58 chemical-vapor-deposition (LPCVD) system as illustrated in Figure 4-1 (a). To form the catalytic Au nanoclusters for the growth, Au film of 2 nm was deposited on the surface of the spheres by e-beam evaporation. Thermal annealing of the sphere covered in Au film was performed at 530 C  under 20 Torr of pressure with constant flow of 100 standard cubic centimeter per minute (sccm) of H2 for 30 minutes. At elevated temperature, Au nanoclusters were formed during the annealing process as shown in Figure 4-1 (b). Our method works as a simple and reliable way to achieve gold nanoclusters with narrow diameter distribution, which is sufficient for producing silicon nanowires for certain applications such as anode for Li ion battery. The Al2O3 spheres decorated with Au nanoclusters were contained in a quartz boat, and it was loaded and positioned at the center of a horizontally oriented quartz growth chamber inside the furnace as shown in Figure 4-1 (a). During the synthesis, the temperature of the growth chamber was raised to 450 – 530 C  depending on the requirement of crystallinity on the resulting nanowires. The pressure in the chamber was controlled at 100 Torr while supplying a constant flow of silane (SiH4, 2% silane in argon) and hydrogen (H2, ultra-high-purity hydrogen) at 111 sccm and 20 sccm respectively. The Au nanoclusters served as catalytic sites for Si nucleation during the VLS process of the synthesis. The diameter of the nanoclusters is proportional to the thickness of the Au film, and varies within certain range. More accurate control over the nanocluster and resulting nanowire diameter can be obtained by deposition of pre-synthesized gold nanoclusters of desired diameters onto the spherical substrates, 21 or by using the aqueous impregnation method, 22 or surface functionalization of the subtrates. 17 Si nanowires have been reported to be synthesized via the VLS mechanism in various substrates including Si wafers, 2 Si/SiO2 wafers, 14 and stainless steel foil. 12, 23 In all these reports, the nanowires were synthesized on a two dimensional planar substrate. Three- dimensional growth substrates had been proven in contribution to the higher quantity of nanowire synthesis due to their large surface areas. 17, 18 In order to achieve bulk synthesis of 59 Si nanowires, we conducted studies in silicon nanowire growth on 3-D substrate, namely on Al2O3 spheres. The spherical Al2O3 substrates provided large surface area for the nanowire growth, hence resulted in high nanowire quantity. To the best of our knowledge this is the first report of Si nanowires synthesized on Al2O3 spheres via the VLS mechanism. The surface of the liquid Au-Si alloy droplets formed during the VLS growth process has large accommodation coefficient, which gives rise to the preferential deposition of Si atoms onto the liquid droplet as explained by R. S. Wagner. 2 The advantageous characteristic allows Si nanowires to be synthesized on any substrate, hence allowing the Al2O3 sphere to be a valid choice for the growth substrate of the synthesis. The two photographic images in Figure 4-1 (c) show the difference in external appearance of the Al2O3 spheres before and after the synthesis. There is an apparent change in color of the spheres, from white to brown. A typical SEM image of Si nanowires synthesized on a single Al2O3 sphere is illustrated in Figure 4-1 (e). The sphere is clearly covered with high density of nanowires grown in random directions, which demonstrates the validity of three-dimensional synthesis. Nanowires were not only grown on Al2O3 spheres situated on the surface of the sphere stack, but also can be observed on the surface of the spheres buried underneath. Due to the large diameter of the spheres, the precursor (SiH4) can diffuse through the interstices between the spheres situated on the surface, and can reach the buried spheres during the synthesis. 24 The property mentioned above can enable the spheres to be stacked in multiple layers, results in enhancement of loading during each round of the synthesis, and gives rise to synthesis of Si nanowires in bulk quantity. The Si nanowires can be easily removed from the surface of the spheres by applying ultrasonication on spheres in solvent (i.e. Isopropyl Alcohol) or by simply exerting vibration on the spheres in solvent. In order to extract nanowires from the solution, the solution was dispersed onto a piece of microscope slide, and at elevated temperature (80 C  ) the solvent was evaporated leaving behind a layer of nanowire film. After removing the nanowire film from the microscope slide, the nanowires appeared as black materials being contained in a 60 glass vial, and the total weight of the nanowires in the vial is 80 mg as depicted in Figure 4-1 (d). To further increase the yield of the synthesis method, the growth chamber along with the furnace can be oriented in the vertical direction as demonstrated in Figure 4-1 (f). The aforementioned configuration of the growth chamber enables higher quantity of Al2O3 spheres to be loaded, hence leading to higher yield of the Si nanowires. Photographic images of the Al2O3 spheres before and after synthesis are shown in Figure 4-1 (f). The SEM image of an Al2O3 sphere with as-grown Si nanowires in the inset of Figure 4-1 (f) demonstrates the validity of the scheme. 4.3 Crystalline ‐core/amorphous ‐shell silicon nanowires Both single crystalline and crystalline-core/amorphous-shell Si nanowires were successfully synthesized by the nanowire-on-sphere methodology. The two types of Si nanowires have been found in applications reported in literature including energy storage devices, 12 transistors, 6 and photovoltaics. 10, 25 Having the ability to produce both single crystalline and c-core/a-shell Si nanowires in bulk quantity provides a source for scaling up the aforementioned nanowire-related applications, and one example is the anode for Li-ion battery. Figure 4-2 (a) shows a typical SEM image of the as-grown crystalline- core/amorphous-shell Si nanowires on Al2O3 spheres, which were synthesized under a constant flow rate of SiH4 and H2 at 111 sccm and 20 sccm, respectively. The growth temperature was elevated to 530 C  and was under 100 Torr of pressure. For synthesis of crystalline-core/amorphous-shell Si nanowires, the millimeter scale Al2O3 spheres decorated with Au nanoclusters were placed in a quartz boat, which was placed at the center of a growth chamber inside a horizontal tube furnace. The chamber was evacuated to 20 Torr and was purged with ultra-high-purity hydrogen gas for 10 minutes to remove oxygen in the chamber. The temperature of the chamber was raised from room temperature to 530 C  in 10 minutes. 61 At 530 C  SiH4 was introduced into the chamber at 111 sccm and the H2 flow rate was controlled at 20 sccm. The pressure inside the chamber was maintained at approximately 100 Torr during the growth, and the growth time was 25 minutes. At the end of the growth, SiH4 gas was turned off and the flow rate of H2 was adjusted to 100 sccm, while the chamber was cooled to room temperature. The procedure for the synthesis of single crystalline Si nanowires is almost the same as the one for synthesis of crystalline-core/amorphous-shell nanowires, except the growth temperature was maintained at 455 C  . The nanowires are between 40 – 100 μm in length, and the density is approximately 6 nanowires per 2 μm(NWs/ 2 μm). From the inset of Figure 4-2 (a), a Au particle can be clearly observed on the tip of a single nanowire, giving evidence to the fact that the nanowire growth was based on the VLS mechanism. Figure 4-2 (b) is a typical TEM image showing the core/shell morphology of the nanowire. The clear contrast reveals the conspicuous boundary between the core and the shell. To illustrate the c-core/a-shell structure of the nanowires, a high resolution transmission electron microscopic (HRTEM) image is presented in Figure 4-2 (c). The periodic planes in the crystalline core give rise to constructive interference of the deflected electron waves in the TEM and resulting in lattice fringes, as shown in the figure. There is a clear boundary between the fringes resulting from crystalline lattice of the core and the amorphous shell of the Si nanowire in Figure 4-2 (c). The spacing between contiguous planes in the Si nanowire was measured to be 3.32 Å based on the lattice fringe depicted in Figure 4-2 (c). The plane spacing corresponds to the <200> direction as the preferential growth direction of the nanowire. The majority of the nanowires synthesized at the aforementioned growth condition exhibit diameters range between 151 to 200 nm, as illustrated in Figure 4-2 (d). A Gaussian fit of nanowire diameter distribution yields a mean value of 149 nm and a standard deviation value of 40 nm. The variation in diameter of the nanowires can be ascribed to the property of lateral diffusion of the Au droplets during the annealing process and during the growth. 26 Study has shown that the Au droplet might migrate during the growth from smaller Au 62 droplets to large ones, hence resulting in variation of diameter of the nanowires. 26 The amorphous shell of the nanowires can be attributed to the simultaneous deposition of Si via the vapor-solid (VS) mechanism during the growth. 27 The VS deposition increases with temperature, and later in this paper it will be shown that the amorphous layer can be eliminated by conducting the synthesis at a lower temperature. The crystalline- core/amorphous-shell silicon nanowires can be a highly desirable candidate working as the active anode material in Li-ion batteris, as reported previously by Y. Cui et al. 23 FURNACE SiH 4 and H 2 Quartz Chamber (a) (b) (c) (d) dates of the images are included in the presentation file titled “100810_work_to_d o_HC_3” 4 mm (e) (f) 300 µm 63 Figure 4-1: Schematic diagram of the growth set-up, and the growth mechanism, and SEM and photographic images of the as-grown Si NW on Al 2O 3 subtrates (a) Schematic diagram illustrating a nanowire synthesis system comprised of a furnace and a quartz reaction chamber. A quartz boat loaded with Au-coated Al 2O 3 spheres were placed at the center of the chamber. (b) Schematic diagram showing a pristine Al 2O 3 sphere, an Al 2O 3 sphere decorated with Au particles after annealing, and Si nanowires synthesized on Al 2O 3 spheres via the VLS mechanism. (c) Photographic image of Al 2O 3 spheres before (top) and after (bottom) nanowire synthesis. (d) Photographic image of 80 mg of free-standing silicon nanowires in a vial. (e) SEM image of crystalline- core/amorphous-shell Si nanowires synthesized on a millimeter scale Al 2O 3 sphere. (f) Al 2O 3 spheres stacked in a vertical quartz reaction chamber (left). Photographic image and SEM image (inset) of Al 2O 3 spheres with Si nanowires synthesized with the vertical chamber configuration (right). The scale bar is 400 μ m. Aug. 30, 2010 September 22, 2010 September 22, 2010 October 04, 2010 October 04, 2010 (a) (c) (d) 30 µm (b) 250 nm 10 nm 3.32Å <200> 20 18 16 14 12 10 8 6 4 2 0 Number of Nanowires 1‐50 51‐100 101‐150 151‐200 201‐250 Nanowire Diameter (nm) Figure 4-2: SEM and TEM characterization of the core/shell silicon NWs. (a) FESEM image of crystalline- core/amorphous-shell Si nanowires grown on an Al 2O 3 sphere. Inset: SEM image of a c-a core/shell Si nanowire with a Au catalytic particle at its tip. Scale bar is 100 nm. (b) TEM image of a c-core/a-shell Si nanowire. (c) HRTEM image of crystalline-core/amorphous-shell interface of a Si nanowire. (d) Diameter distribution of the c- core/a-shell Si nanowires. 4.4 Single crystalline silicon nanowires Single crystalline Si nanowires had also been synthesized on the Al2O3 spheres with a similar reaction recipe. The process of the synthesis was almost the same as the procedure mentioned in the previous section of this paper except for the growth temperature, which was 64 controlled at 455 C  in order to attain the single crystalline nanowires (detail description of the synthesis can be found in the Methods section). The volume of the Si-Au alloy can be controlled by the temperature during the VLS process, 28 and J. Westwater illustrated that Si nanowires with smaller diameter can be obtained at lower temperature than that at higher temperature. 3 An SEM image of the as-grown nanowires on sphere is shown in Figure 4-3 (a). The average length of the nanowires is estimated to be 10 μm as shown in the figure which is at least four times shorter than that of the crystalline-core/amorphous-shell nanowires. The density of the nanowires is approximately 10 NWs/ 2 μm . The inset in Figure 4-3 (a) shows the Au particle tip formed at one end of a Si nanowire, and that reveals the nature of the growth was based on the VLS mechanism. A typical TEM image of the Si nanowire is illustrated in Figure 4-3 (b). The diameter of the nanowire is 48 nm in the image, which is three times smaller than the diameter of the c-core/a-shell Si nanowires. The spacing between contiguous planes in the Si nanowire was measured to be 3.32 Å based on the lattice fringe illustrated in Figure 4-3 c. The plane spacing corresponds to the <200> direction as the preferential growth direction of the nanowire. The diameter of the nanowires synthesized under the aforementioned condition varies from 10 to 70 nm, having the majority of the diameter of the nanowires lies between 30 to 60 nm as illustrated in Figure 4-3 (d). A Gaussian fit of nanowire diameter distribution yields a mean value of 44 nm and a standard deviation value of 11 nm. As it was shown by the results, crystalline Si nanowires can be synthesized on the Al2O3 spheres by varying the growth temperature in the reaction chamber. These crystalline nanowires with smaller diameter can be used for study of their electronic transport properties. The electrical properties of the Si nanowires can be improved by incorporating n-type or p- type dopant atoms into the nanowires with this scheme. Gaseous phase dopants, such as phosphine (PH3) or diborane (B2H6) can be introduced into the reaction chamber during the synthesis to achieve doping of the nanowires. 6, 29 65 September 10, 2010 (a) (b) (c) (d) 3 µm 5 nm 3.32Å <200> 50 nm 14 12 10 8 6 4 2 0 Number of Nanowires 10‐20 21‐30 31‐40 41‐50 51‐60 61 ‐ 70 Nanowire Diameter (nm) Figure 4-3: SEM and the TEM characterization of the as-grown Si NWs (a) FESEM image of single crystalline Si nanowires grown Al 2O 3 sphere. Inset: crystalline Silicon nanowire with a Au particle at its tip. The scale bar is 100 nm. (b) TEM image of a single crystalline Si nanowire having the growth axis in the <111> direction. (c) HRTEM image showing the lattice fringes of the nanowire. Inset: electron diffraction pattern from the silicon nanowire. (d) Diameter distribution of the single crystalline nanowires. 4.5 Electrochemical characteristic of crystalline ‐core/amorphous ‐shell silicon nanowires As it was mentioned in the earlier part of this report, crystalline-core/amorphous-shell Si NWs have been demonstrated to be a desirable anode material for Li-ion battery. 23 In order to demonstrate one of the many applications of our Si nanowires obtained by the bulk synthesis scheme, we conducted a series of studies in the electrochemical properties of the crystalline-core/amorphous-shell Si nanowires. The c-core/a-shell Si nanowires were mixed with ion conducting composite and binder to form a layer of uniform slurry. Anode is formed by dispersion of the slurry on a copper sheet, as the current collecting layer. The anode is 66 assembled into a coin cell in conjunction with electrolyte and lithium counter electrode. The electrodes were made by mixing the Si nanowires with SuperP conductive carbon black, and sodium carboxymethylcellulose (CMC) (MW90,000, Aldrich) in water (10% weight) to form a uniform slurry, and then spread onto a copper foil using a stainless steel blade. The electrode was dried at 50 overnight in air and was maintained at room temperature in Ar for two hours just prior to cell assembly to remove any residual water vapor. The loading density of our Si nanowires was estimated to be 1 mg/cm 2 . Then CR2032 coin cells were assembled in an Ar-filled glove box using the as-prepared Si nanowires anodes as working electrodes and lithium metal foils as counter electrodes. The electrolyte was 1M LiClO4 dissolved in a 1:1 (weight ration) mixture of ethylene carbonate (EC) and diethyl carbonate (DEC). The nanowires were utilized as active materials in the electrode of electrochemical cells. The cyclic voltametery (CV) profile of the Si nanowire electrodes was obtained by a potentiostat (Gamry, Reference 600) using a potential window of 0.01 volt to 3.0 volt for three cycles. The result of the CV measurement is depicted in Figure 4-4 (a) with scan rate of 0.05mV/sec. When the potential was incremented from 3.0V to 0.01V during the first discharging cycles, the Si nanowires exhibited typical crystalline-core/amorphous-shell features. First, there is an apparent peak at around 250 mV due to lithiation of the amorphous Si shell, which agreed with the previous thin film study conducted by Maranchi et.al. 30 Second, the small peak near 130 mV is attributed to the amorphorization of crystalline Si during first lithiation process 12, 31 . Furthermore, further discharging results in the formation of a new phase, Li15Si4, from amorphous Li-Si alloy at the peak potential around 55 mV, which was suggested by a previous study on Si powder and films 32 . Upon charging process, the peak at 390 mV indicates a transformation by means of coexistence of two phases of both crystalline and amorphous Li-Si alloy. 32 After the first cycle of discharge and charge between 3.0-0.01 V, the peak for crystalline Si was drastically diminished, demonstrating the crystalline- core/amorphous-shell structure was completely transformed into the amorphous phase. The 67 second and the third cycles match relatively well, which implies the system had reached a steady state. Figure 4-4 (b) and (c) illustrate the Galvanostatic (GV) charging and discharging measurements, carried out by a battery testing system (MSTAT, Arbin), determining the specific capacity (Csp) and the Coulombic efficiency of the devices in a two-electrode configuration. Computation of different current rates was based on the capacity in the first discharging process. Figure 4-4 (b) is the charging-discharging performance of the Si nanowire electrodes for 40 cycles with a current rate of C/30. The slow cycling current reveals much electrochemical information relating to the electrode structure. In the initial state, the potential dropped to 200 mV and maintained at a prolonged flat plateau at around 100 mV, then gradually decreased to zero. This plateau is resulted from coexistence of partially lithiated amorphous Si shell accompanied by amorphorization of crystalline Si core. The capacity in the first discharging cycle reached up to 3500 mAh/g, very close to the theoretical capacity of silicon. 33 For the following cycles, the plateau is stable at 240 mV, which is consistent with the conclusion from Figure 4-4 (a), that after the first cycle, almost all the crystalline-core/amorphous-shell nanowires had transformed into the amorphous phase. Furthermore, we can still observe the small plateau at about 50 mV because of the emergence of the new phase, which was also explained in the earlier discussion for Figure 4-4 (a). To further investigate the GV behavior of the Si nanowires from bulk synthesis, we cycled the electrode with two different current rates, C/30 and C/10. The relationship between discharging specific capacity and cycle number is illustrated in Figure 4-4 (c). As it can be observed in the figure, the Si nanowire electrodes display relatively high capacity value at both current rates for 60 cycles, which are more than two factors of the specific capacity value exhibited by the commercially available graphite anodes. The high specific capacity can be attributed to the small dimension of the nanowires, which enables better ion accommodation, and the one-dimensional electronic pathway gives rise to improved charge transport. The Si 68 nanowire electrode exhibits relatively small irreversible capacity of 10%. The retention of C/10 current rate is higher than that of the C/30 rate. That may be attributed to different degrees of Si involvement in the lithiation/delithiation process. For C/30, the small current allows the electrode materials to react more thoroughly; therefore more Si nanowires can participate in lithiation, resulting in higher specific capacity but at the same time larger volume expansion. The large volume expansion could damage the intact electrode structure, thereby having a negative effect on capacity retention. (c) (d) (b) (a) Figure 4-4: Performance oft the bulk sythesized Si NW used in the anodel of Li-ion battery half cell. (a) Cyclic voltammogram for Si nanowires from 0.01V to 3.0V. The first three cycles are shown. (b) Voltage profile for first 40 cycles of the Si nanowire electrode at the C/30 rate. (c) Capacity versus cycle number for the Si nanowire electrode at the C/30 (red) rate and the C/10 (black) rate. (d) Coulombic efficiency versus cycle number for the Si nanowire electrode at the C/30 (red) rate and the C/10 (black) rate. Moreover, the Coulombic efficiency of our devices was calculated and plotted in Figure 4-4 (d), which further demonstrates the excellent battery performance of the Si nanowires obtained from the bulk synthesis method. In the second cycle, the efficiency at 69 both of the C/30 and C/10 current rate was increased to 90% and in the cycles following that, the efficiency sustained at around 98% to 99%. The efficiency is comparable to the efficiency of the anodes in commercial Li-ion batteries. The only difference in Coulombic efficiency for the two current rates is that the charging-discharging experiment conducted under the higher current rate required few more cycles to reach 99% Coulombic efficiency value. That is caused by the fact that with larger current, more cycles of repeated lithiation are required to transform all crystalline-core/amorphous-shell structure into the amorphous phase. By now the bulk synthesis of silicon nanowires and their application for Li-ion battery has been elucidated. We note that our bulk synthesis approach can be applied to produce many other nanowire materials, for instance, indium oxide NWs, 34 tin oxide NWs, 35 zinc oxide NWs, 36, 37 gallium nitride NWs, 21 Ge/Si core-shell nanowires, 38 via LPCVD and III-V nanowires with MOCVD. 39 These nanowires can be expended for a wide variety of applications that may require bulk quantity, for instance, nanowires in thin film transistors for display applications 40, 41 and electronic skins. 42 We further note that bulk synthesis of nanowires can also be potentially achieved by utilization of other techniques such as fluidized-bed synthesis, 43 which is currently being investigated in our group. The scheme of incorporating millimeter size Al2O3 substrates as the support for VLS growth of Si nanowires was successfully demonstrated. Bulk quantity of Si nanowires was obtained through stacking large number of the spheres in the reaction chamber during the synthesis. Both crystalline and crystalline-core/amorphous-shell Si nanowires were synthesized on the spheres by variation in temperature of the growth recipe. The as- synthesized crystalline-core/amorphous-shell Si nanowires were used as the active material and were processed using the slurry method to form half-cells for electrochemical study. Galvanostatic measurement demonstrated the maximum power capacity achievable by the electrodes was 3500 mAh/g and capacity sustained at 1100 mAh/g after 60 cycles of charging 70 and discharging. The results demonstrated one of the viable applications of the Si nanowires synthesized with the proposed scheme. 4.6 Summary Silicon nanowires (NWs) have stimulated significant interest and found numerous applications; however, many applications will require bulk quantity of nanowires synthesized in a reliable way. In this paper, we report the bulk synthesis of silicon nanowires on millimeter scale Al2O3 spheres with a thermal chemical vapor deposition system (CVD) via the vapor-liquid-solid (VLS) growth mechanism. The spherical substrates enable the realization of Si nanowire synthesis on three dimensional surfaces in comparison with the synthesis on a planar, two dimensional wafer substrate. By modifying temperature in the recipe of synthesis, both single crystalline and crystalline-core/amorphous-shell Si nanowires were obtained with this nanowire-on-spherical-support method. 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Circuits operating in complementary mode are essential to ensure low steady-state power dissipation and enabling circuits to achieve rail-to-rail output signal. I have proven that the hybrid CNT/IGZO circuit scheme provides a reliable path to realize complementary circuits due to the high device yield and lower device-to-device variation in ambient environment. I was able to realize integrated circuit blocks, such as inverter, NAND and NOR gates with the hybrid circuit scheme. And due to the reliable yield and stability of the CNT and IGZO TFTs in ambient, I was able to realize the first demonstration of a large scale integrated circuit based on the CNT/IGZO TFTs manifested in a 501-stage ring oscillators with over 1000 transistors. In addition to the aforementioned static logic gates, dynamic logic circuits including inverter, NAND and NOR gates were also demonstrated in my study. In order to improve the performance of CNT-based TFTs, I conducted systematic study of TFTs based on 99.9% CNT, 99%, CNT, and 1R Raymor CNTs, which are extracted semiconducting enriched CNTs with different length. And it was shown in the my study that 99.9% purity CNT is a more preferable CNT channel material in comparison to the other two types of CNTs in terms of its effective device mobility and on- current density which are important metrics especially in AMOLED display applications. I have also proposed and realized a generic and effective method to reduce hysteresis in both p- type and converted n-type CNT TFTs in ambient environment, which is the encapsulation of 75 the CNT devices with photoresist. And the results have shown that the hysteresis in the CNT TFTs can reduced by half of its original value of devices measured before encapsulation. In addition to carbon nanotube, I have demonstrated my study in the synthesis and characterization of another nanomaterial, silicon nanowires. I proposed and realized a synthesis method to produce bulk quantity of silicon nanwires, and this was accomplished by using millimeter size Al2O3 as supporting substrate for the silicon nanowire growth. This method increases the surface area for growth, hence resulting in high throughput during each round of synthesis. And I also demonstrated that the crystallinity of the nanowires can be controlled through the growth temperature. And as a proof of concept, the silicon nanowires synthesized with this method were successfully employed as the anode material in a Li-ion battery half-cell. 76 5.2 Future research: Fully transparent hybrid carbon nanotube/IGZO TFT ‐based control circuitry for transparent CNT resistive touch screen 5.2.1 Introduction As it was demonstrated in earlier chapters of my dissertation, and also demonstrated by fellow researchers that carbon nanotube thin film transistors hold great potential for macroelectronics and flexible macroelectronics 1-4 . Digital circuits such as decoders, flip-flops, inverters, NAND, NOR, ring oscillators, sensors, memories, radio-frequency ID tags, pixel driving circuitry for active matrix organic light emitting diode (AMOLED) display, electronic skins, radio frequency electronics have been realized using CNT TFTs 5-19 . The success in these applications by using CNT TFTs can be attributed to their relatively high performance, excellent flexibility, compatibility with room temperature processing, high stability in air, high yield and low processing cost, which makes them more superb in comparison with other thin film technologies such as hydrogenated amorphous silicon (a-Si:H) and organic TFTs 20-26 . In addition to the aforementioned merits of CNT thin films, they also exhibit excellent transparency, with an optical transmission of as high as 90% at a sheet resistance of 60 Ohm/square 27-30 . It has been demonstrated that CNT TFTs can be utilized in the pixel driving circuitry for AMOLEDs as transparent display 4,9 . Another important application of the macroelectronics is touch screen, and it has been massively employed in modern electronics, such as mobile phones, tablets, laptops etc., and CNT thin film is a desirable candidate for next generation of touch-screens. 77 5.2.2 Touch screen structure and operating mechanism In the current touch screen technologies, they can be categorized into four types based on their sensing mechanism, including resistive, capacitive, optical and acoustic sensing 22 . Among the four sensing mechanisms, resistive and capacitive sensing touch screens are most commonly used in consumer electronics 22 . A cross-sectional diagram of a 4-wire resistive touch screen is shown in Figure 5.1 22 . It can be observed in Figure 5.1 that the touch screen is consisted of one transparent bottom layer comprised of a piece of glass substrate coated with a transparent electrodes, indium-tin-oxide (ITO); a top layer is made of a polymer, usually a film of polyethylene terephthalate (PET) coated with ITO electrodes; and some insulating separator dots are intercalated between the top and bottom layers. The separator dots are in place to separate the top and bottom electrodes with a minimum distance of 0.2 mm to prevent contact between the top and bottom electrodes at no external pressure 22 . The operating mechanism of a touch screen is illustrated in Figure 5.2 31 . In Figure 5.2 (a), it depicts a set of electrodes, X+ and X-, and Y+ and Y-, are coated on the top and bottom layers of the touch screen, respectively. When pressure is applied to the top screen by a finger or a stylus, the area of contact on the top is deflected and it comes into contact with the bottom layer. When a voltage is applied across to the bottom electrodes, Y+ and Y- as shown in Figure 5.2 (b), a voltage divider is formed and an output voltage can be detected at X+. The ratio between the voltage measured at X+ (VX+) and the voltage applied across Y+ and Y- (VYsupply) equals to the y-coordinate the height (hscreen) of the touch screen which can be defined by the following expression (5-1) screen ply Y X h V V y    sup 78 Based on equation (5-1), the coordinate of the point of contact can be detected. Similarly, in order to detect the x-coordinate of the point of contact, a voltage is required to be supplied across the X+ and X- top electrodes, and the voltage is read from the Y+ bottom electrode as the output of the voltage divider as depicted in Figure 5.2 (b). Then similarly the ratio between the voltage measured at Y+ (VY+) electrode and the voltage applied across X+ and X- (VXsupply) equals to the ratio of the x-coordinate to the touch screen width (wscreen). The expression is defined by the following (5-2) screen ply Y w V V x    sup Figure 5.1: A cross-sectional schematic diagram of a 4-wire touch screen (Figure adapted from ref. 22 ). As it was illustrated in Figure 5.1, that ITO is the transparent electrode material used in the 4- wire resistive touch screen, which is also true in other types of resistive and capacitive touch screen technologies 22 . ITO is an excellent transparent conductive material with low resistivity (~10 Ω/square) and outstanding optical transmittance (~90%), and it has been the most preferable material to be used in touch screen and in display applications. However, the 79 composition of ITO contains 90% of indium oxide (In2O3), which is a scarce material with limited supply, and its price has doubled in the past ten years 27 . On the other hand, carbon nanotube is comprised of one of the most abundant material on this planet, carbon, and as it was mentioned earlier, CNT thin films exhibit desirable transparency and conductivity, therefore it has the potential to serve as the replacement of ITO in touch screen applications 29,30,32,33 . In addition, CNT TFTs have been proven to be excellent devices for transparent electronics 4,15,34-36 . a) b) c) Figure 5.2: Schematic diagram of a four wire resistive touch screen and the conceptual diagram of its operation. (a) Schematic diagram of a four wire resistive touch screen with its top and bottom electrodes. (b) Conceptual diagram of the operating mechanism of the touch screen, when a voltage is applied across Y+ and Y- in the bottom electrodes, and the point of contact is measured at X+ in the top electrode, hence the y-coordinate of the point is detected. (c) When a voltage applied across the X+ and X- in the top electrodes, the point of contact is measured at Y+ in the bottom electrode, hence the x-coordinate of the point is detected. (Figure adapted from ref. 37 ). 80 5.2.3 Fully transparent carbon nanotube ‐based 4 ‐wire resistive touch screen with CNT/IGZO hybrid integrated complementary multiplexer control circuitry Here, I proposed a fully transparent carbon nanotube-based touch screen and transparent CNT TFT control circuitry. A 4-wire resistive touch screen system will be adopted for this study due to its simplicity for this demonstration as a proof of concept 22 . Multiwall carbon tubes (MWCNT) will be used as the material for the screen on both the top and bottom layers of the touch screen, in replacement of the ITO as shown in Figure 5.1. It has demonstrated that MWCNT is a ideal material for touch screen, as its sheet resistance can reach 450 Ω/square and its transmittance can reach 90%, which exceed the requirement for touch applications (transmittance > 85% and sheet resistance < 500 Ω/square) 27 . For the control circuitry, a multiplexer is stacked to the bottom of the touch screen, which is expended to select between the X+ and X- top electrodes and the Y+ and Y- bottom electrodes for supplying voltage and for signal measurement as explained in an earlier section 31 . The multiplexer is consisted of fully transparent p-type CNT TFTs and n-type IGZO TFTs, allowing the circuits to operate in complementary mode 6 . The CNT and IGZO TFTs are encapsulated with Teflon AF for abatement of hysteresis in the p-type CNT devices, and to alleviate the effect of oxygen molecules on electron density in the IGZO TFTs 38,39 . In order to actualize fully transparent touch screen and control circuitry, two types of transparent electrodes could be selected for the CNT and IGZO TFTs. One option is to use metallic CNT thin films as the contact electrodes for both of the CNT and IGZO TFTs 40 . The other option is use graphene as the transparent electrodes for the CNT and IGZO TFTs 41-43 . 81 b) c) a) Figure 5.3: Schematic diagram and photographic images of Unidym CNT thin films used as top electrodes for touch screen. (Figure adapted from ref. 33 ). (a) Schematic diagram of the structure of a commercially available 4- wire resistive touch screen (top) and a touch screen using CNT thin film as the top electrode. (b) Photographic image of a Unidym CNT thin film touch screen. (c) Photographic image of a Unidym CNT touch screen integrated with a commercial LCD monitor. Carbon nanotube thin films have been implemented in touch screen technology 27,33 . In Figure 5.3, it illustrates a 4-wire resistive touch screen technology demonstrated by Unidym 33 . Figure 5.3 (a) compares the structure of the resistive touch screen between the commercial product using ITO as the top and bottom electrodes, and the technology demonstrated by using CNT thin film as the top electrodes. Figure 5.3 (b) and (c) show photographic images of the CNT thin film based touch screen and its integration with a commercial LCD monitor, respectively. As it was demonstrated in Chapter 2 of my dissertation, I successfully realized hybrid integrated complementary circuits using CNT and IGZO TFTs. The hybrid CNT/IGZO circuit scheme has been proven to be a high yield, reliable configuration for static logic gates (inverter, NAND and NOR gates), ring oscillators (51-stage, 101-stage, 251-stage and 501- 82 stage ring oscillators, and dynamic logic circuits (dynamic inverter, dynamic NAND and NOR gates) 6 . In addition to some of the hybrid CNT/IGZO logic building blocks I demonstrated in Chapter 2, in Figure 5.4 I have demonstrated XOR gate and D-Latch utilizing expending the CNT/IGZO hybrid complementary circuit configuration. Especially for the D- Latch, this is first demonstration of a sequential complementary circuit with a hybrid CNT/IGZO TFTs. It can be observed in Figure 5.4 (c) that the circuit returns the correct logic for the XOR gate, namely, the output is only high (logic “1”) when input A is different from input B. The power supply (VDD) of the circuit is 5 V. For the D-Latch circuit shown in Figure 5.4 (f), the output (Q) follows the input (D) when the clock signal (CLOCK) is high (logic “1”); the Q returns the D signal in the previous clock cycle when the CLOCK is low (logic “0”). With the successful demonstration of sophisticated complementary combinational logic gates and sequential circuit using the CNT/IGZO, the CNT/IGZO devices can be further integrated to form a multiplexer (MUX) for selecting electrodes for voltage supply and selecting electrodes for measurement in a 4-wire resistive touch screen system. The conceptual schematic diagram of the electronic interface of the CNT-based 4-wire resistive touch screen and the CNT/IGZO hybrid complementary multiplexer is shown in Figure 5.5. The multiplexer is used to select between the X+ and X-, and Y+ and Y- electrodes in the touch screen, as explained in the earlier sections, to either supply voltage across the electrodes, or to take measurement of the contact point potential of the touch screen. Based on the results I have obtained through the study I presented in Chapter 3, 99.9% CNT thin films can be used to improve the mobility and on-current density of the CNT TFTs and the CNT devices can be encapsulated with a layer of photoresist or Teflon AF 38,44-46 . 83 0 1 2 3 4 5 XOR V DD = 5V Logic "0" = 0 V Logic "1" = 5 V Gate A 0 0 1 1 Output VotlageV  Gate B 0 1 0 1 D 02468 10 -4 -2 0 2 0 1 2 3 4 5 0 1 2 3 4 5 Q Time (ms) D CLOCK B GND OUT A V DD GND V DD Q D CLK a) c) b) d) e) f) A NA B NB NA NB AB A B NA NB XOR VDD CK NCK NCK CK D NCK CLK D VDD Q NQ Figure 5.4: Schematic diagram, optical micrograph, and output characteristics of CNT/IGZO hybrid XOR gate and D-Latch. (a) (b) Schematic diagram and optical micrograph of CNT/IGZO hybrid complementary XOR gate, respectively. (c) Output characteristic of the XOR gate at V DD of 5 V. (d) (e) Schematic diagram and optical micrograph of CNT/IGZO hybrid complementary D-Latch, respectively. (f) Output characteristic of the D-Latch at V DD of 5V. 84 Touch Screen Driver Interface MUX X+ X- Y+ Y- Figure 5.5: Conceptual schematic diagram of the electronic interface between the CNT-based 4-wire resistive touch screen and the CNT/IGZO hybrid complementary multiplexer. (Figure adapted from ref. 37 ) The CNT and IGZO channels for the CNT/IGZO TFTs are transparent, as both of these two materials exhibit excellent transparency 4,15,47-51 . In order to implement a fully transparent touch screen and driver circuitry, the electrodes for the CNT and IGZO devices must be transparent as well 29,32,52 . In Fan., S.’s article, the research group demonstrated an all CNT- based TFT using CVD grown CNT with different density and used direct transfer method to form the electrodes and channels of CNT TFTs with CNT thin films 40 . The schematic diagram of the device is shown in Figure 5.6. As it shown in the figure that the gate, drain and source electrodes are formed with CVD grown CNT thin films with high density, hence more metallic. The TFT channel is formed with a layer of sparse CVD grown CNT, exhibiting more semiconducting property 40 . In my study, commercially available metallic CNT solution (from Nanointegris Technologies, Inc.) can be used as the electrodes for both of the CNT and IGZO TFTs 29 . And alternative to the CNT thin film transparent electrode is using graphene as the electrode for both of the CNT and IGZO TFTs 42,43 . In Figure 5.7, it illustrates the implementation of graphene as the electrodes for a CNT TFT. CNT thin films are used as the channel material in the device 43 . 85 Figure 5.6: Schematic diagram of an all-CNT-based TFT, using high density CNT (metallic) grown CNT thin film as the gate, drain and source electrodes; using low density CVD grown CNT thin film as the channel of the TFT.( Figure adapted from ref. 40 ). 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Abstract (if available)

Abstract In this dissertation, I present my development of an innovative approach to utilize the advantage of the stable semiconducting properties of two materials, carbon nanotube thin films and indium gallium zinc oxide thin film to form circuits operating in complementary mode. The approach has resolved the following issues. Firstly, carbon nanotube (CNT) thin film transistors (TFTs) behave as p-type transistors in ambient with high work function metal electrodes, such as palladium. And CNT TFTs exhibit desirable transistor behavior showing device mobility and on-current density suitable for macroelectronic applications, which is superior to the commercially available amorphous silicon TFTs. However, in order to operate circuits with low steady-state power dissipation, it is more desirable to have complementary circuits, meaning circuits consisted of both p-type and n-type transistors. CNT TFTs can be converted into n-type, however, there has not been a method to realize n-type CNT TFTs with long term stability. On the other hand, oxide semiconductor TFTs have been a well-known for high performance n-type TFTs. However, researchers have also struggled to obtain stable and high performance p-type oxide semiconductor TFTs. I demonstrate using CNT TFT, the stable p-type device, and indium gallium zinc oxide (IGZO) TFT, an outstanding n-type device to realize integrated circuits operating in complementary mode with good stability in ambient. I have demonstrated for the first time a large-scale integration of CNT/IGZO hybrid circuits, a 501-stage ring oscillator comprised of over 1000 TFTs, showing the high yield of both of the p-type and n-type devices and their stability in ambient environment. This hybrid complementary design enables circuits to operate with low static power consumption, and allows the output of the circuits to reach rail-to-rail voltage. In addition, in order to further improve the stability of the device, I introduce a method to reduce the hysteresis in CNT TFTs, by encapsulating the devices with a layer of photoresist. Further, I was able to demonstrate that this is a generic approach. ❧ In addition to carbon nanotubes, I also present my study in the controlled synthesis of silicon nanowires, another promising nanomaterial that can be used for energy storage device. I demonstrated the bulk synthesis method to increase the throughput for the nanowire growth. High throughput of silicon nanowire is desirable for applications such as Li-ion battery. ❧ My dissertation is divided into five chapters. Firstly, the Introduction chapter gives a brief explanation on the electrical properties of carbon nanotube thin film transistors

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Asset Metadata

Creator Chen, Haitian (author)

Core Title Nanomaterials for macroelectronics and energy storage device

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 10/30/2014

Defense Date 10/20/2014

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag carbon nanotube,flexible electronics,IGZO,macroelectronics,OAI-PMH Harvest,silicon nanowires

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Zhou, Chongwu (committee chair), Cronin, Stephen B. (committee member), Goo, Edward K. (committee member), Wu, Wei (committee member)

Creator Email haitianc@usc.edu,hytenbatulu@yahoo.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c3-511196

Unique identifier UC11298513

Identifier etd-ChenHaitia-3046.pdf (filename),usctheses-c3-511196 (legacy record id)

Legacy Identifier etd-ChenHaitia-3046.pdf

Dmrecord 511196

Document Type Dissertation

Format application/pdf (imt)

Rights Chen, Haitian

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

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