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Gyrator-based synthesis of active inductances and their applications in radio -frequency integrated circuits

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Gyrator-based synthesis of active inductances and their applications in radio -frequency integrated circuits

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Content GYRATOR-BASED SYNTHESIS OF ACTIVE INDUCTANCES AND THEIR APPLICATIONS IN RADIO-FREQUENCY INTEGRATED CIRCUITS Copyright 2006 by Timothy Wade Bakken A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2006 Timothy Wade Bakken Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. UM I Number: 3233818 Copyright 2006 by Bakken, Timothy Wade All rights reserved. INFORMATION TO USERS The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleed-through, substandard margins, and improper alignment can adversely affect reproduction. In the unlikely event that the author did not send a complete manuscript and there are missing pages, these will be noted. Also, if unauthorized copyright material had to be removed, a note will indicate the deletion. ® UMI UMI Microform 3233818 Copyright 2006 by ProQuest Information and Learning Company. All rights reserved. This microform edition is protected against unauthorized copying under Title 17, United States Code. ProQuest Information and Learning Company 300 North Zeeb Road P.O. Box 1346 Ann Arbor, Ml 48106-1346 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Epigraph “If it were easy, it wouldn’t be research.” - Dr. John Choma, Jr. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Dedication I would like to dedicate this work to my family, for without them I would have accomplished nothing. First, to my parents, who have been my champions my entire life. Their encouragement and love gave me the confidence to establish high goals, and their unwavering support has helped me to achieve my academic goal of a doctorate in electrical engineering. I thank them for an extraordinary childhood, for teaching me kindness, compassion, and humility, and for introducing me to so much of the world. To my brother, Chris, for punching me, flicking my nose, and pestering me throughout our childhood. He taught me perseverance, self-reliance, and gave me the gift of concentration, without which this research would have been impossible. He also gave me love, encouragement, and camaraderie that brothers do not often share. I appreciate his wit and sincerity, and I am grateful for our continued bond. To my wonderful children, Cole, Danica, and Annalise, for decorating my office with beautiful artwork, for giving me hugs when I need them most, and for reminding me that there is so much more to life than equations and computer simulations. I thank them for brightening my study breaks with their smiles and laughter, for their Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. imaginative games of dragons, kitties, and explorer bunnies, and for the way each of them adds depth, joy, and purpose to my life. Lastly, to my wife, Kath, for demonstrating infinite patience and boundless confidence. I am grateful for her love, her understanding, and all she has done for our family. While caring for me and raising our children, she has completed her own graduate studies, earned her black belt in karate, and managed our entire household. I thank her dearly for supporting my pursuit of this very time-consuming endeavor. She is truly remarkable, and I give her all of my love and gratitude. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Acknowledgements This work would not have been possible without the assistance of many people from the University o f Southern California. I give my deepest thanks to my advisor and friend, Dr. John Choma, Jr., whose inspiration and support have been invaluable since I began graduate studies so many years ago. I thank John for encouraging me to pursue graduate work, for providing teaching and research opportunities, and for guiding my research through its many ups and downs. I feel privileged to have worked with him, and am deeply honored to have earned his friendship. I would also like to extend my sincerest thanks to the other members of my doctoral committee, Profs. Hossein Hashemi, Eun Sok Kim, James Moore II, and Alan Willner, for their time, attention to detail, and for offering many helpful suggestions over the past two years. Special thanks also goes to Dr. Hashemi for assisting in the fabrication of one of my final designs. His generosity helps to substantiate my work thus far and create opportunities for future research. Ramona Gordon and Ericka Lieberknecht of the Electrical Engineering/Electrophysics Department deserve special recognition as well. I am grateful to Mona for her patience, her humor, and for the endless paperwork that she processed during my teaching assistant days. I thank Ericka for repeatedly weaving me into Dr. Choma’s Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. busy schedule, for her assistance during my defense presentation, and for her personal submission o f this dissertation on my behalf. Finally, I thank two former doctoral students, Wendell Beale and Chris Grossman, for their mentoring during my preparation for the Ph.D. entrance examination. Our review sessions in El Porto were the best means to prepare for any exam, and will always be remembered with a smile. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Contents Epigraph...................................................................................................................................... ii Dedication..................................................................................................................................iii Acknowledgements....................................................................................................................v List of Tables..............................................................................................................................x List of Figures........................................................................................................................... xi Abstract................................................................................................................................... xvii C hapter 1: In troduction ........................................................................................................ 1 C hapter 2: Research O bjectives..........................................................................................4 2.1 Evaluate Integrated Inductance Architectures........................................................4 2.2 Analyze the Preferred Architecture and Offer Improvements............................ 4 2.3 Establish Performance Specifications for Final D esigns..................................... 4 2.3.1 High-Frequency Operation............................................................................5 2.3.2 Stable Inductance V alues..............................................................................5 2.3.3 High Q s ........................................................................................................... 5 2.3.4 Tunable Inductance Values.......................................................................... 5 2.3.5 Very Small Die A rea..................................................................................... 5 2.3.6 Low Voltage Operation.................................................................................6 2.3.7 Low Power Consumption..............................................................................6 C hapter 3: An Evaluation of Integrated Inductance A rchitectures.......................... 7 3.1 Planar Spiral Inductors.............................................................................................. 7 3.1.1 Printed Circuit Planar Spirals........................................................................ 7 3.1.2 Thin-Film Planar Spirals................................................................................9 3.1.3 ^-Enhanced Planar Spirals.......................................................................... 21 3.2 Out-of-Plane Micro-Inductors................................................................................22 3.2.1 Three-Dimensional Out-of-Plane Spirals.................................................22 3.2.2 Three-Dimensional Out-of-Plane C oils................................................... 24 3.3 Bond Wire Inductors............................................................................................. 25 3.4 Non-Gyrator Active Inductors...............................................................................28 3.4.1 Semiconductor Junction Active Inductors................................................ 28 3.4.2 Other Non-Gyrator Active Inductors.........................................................29 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.5 Gyrator-Based Active Inductors............................................................................30 3.5.1 Ideal Gyrators................................................................................................ 30 3.5.2 Gyrators With Non-Zero Input and Output Conductances.....................32 3.5.3 Gyrators With Frequency-Dependent Gyration Conductances.............. 35 3.5.4 Passive Realizations of Gyrators.................................................................37 3.5.5 Active Realizations of Gyrators and Gyrator-Based Inductances 38 3.6 Conclusions.............................................................................................................. 49 C hapter 4: Analysis of a G yrator Inductor Using Transconductance A m plifiers......................................................................................................... 51 4.1 A General Transconductor Model......................................................................... 52 4.2 Analysis o f a Gyrator-Based Inductor Using the General Transconductor M odel............................................................................................55 4.3 Design Constraints and Guidelines....................................................................... 62 4.4 Design Exam ple.......................................................................................................66 4.5 Conclusions...............................................................................................................73 C hapter 5: Evaluation and Analysis of Transistorized G y ra to rs............................ 76 5.1 Transistorized Gyrator Topologies....................................................................... 77 5.1.1 Gyrator A: Common-Source (NMOS)/Common-Drain (NM OS).......78 5.1.2 Gyrator B: Common-Source (PMOS)/Common-Drain (PMOS)........ 79 5.1.3 Gyrator C: Common-Source (NMOS)/Common-Drain (PM OS)....... 80 5.1.4 Gyrator D : Common-Source (PMOS)/Common-Drain (NMOS)........81 5.1.5 Gyrator E: Common-Gate (NMOS)/Common-Source (NM OS) 82 5.1.6 Gyrator F: Common-Gate (PMOS)/Common-Source (PMOS)........... 83 5.1.7 Gyrator G: Common-Gate (NMOS)/Common-Source (PM O S) 84 5.1.8 Gyrator H: Common-Gate (PMOS)/Common-Source (N M O S) 84 5.2 Comparison of Transistorized Gyrator Topologies............................................. 85 5.3 Stability Analysis of a Transistorized Gyrator.....................................................87 5.3.1 Small-Signal Model for Each Transistor....................................................88 5.3.2 Analysis o f a Transistorized Gyrator Using the Small-Signal Model... 89 5.3.3 Design Constraints and Guidelines for a Transistorized G yrator 97 5.4 Equivalent Circuit of Transistorized Gyrators...................................................102 5.5 Design Exam ple.....................................................................................................104 5.6 Accuracy of Design Example Results.................................................................110 5.7 Quality Factor Limitations of Transistorized Gyrators................................... 111 C hapter 6: Analysis of a Cascode G yrator Inductor..................................................115 6.1 A Cascode Gyrator Inductor Overview...............................................................115 6.2 Small-Signal Model of a Cascode G yrator........................................................ 118 6.3 Analysis o f the Cascode Gyrator Small-Signal M odel.....................................121 6.4 Design Constraints and Guidelines..................................................................... 127 6.5 Conclusions.............................................................................................................131 viii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 7: Designing Cascode Gyrator Inductors.....................................................133 7.1 Validating the Design Equations and Guidelines.............................................. 133 7.2 Comparing Performance Results with Research Objectives............................136 7.3 Tuning the Inductance of the Cascode Gyrator..................................................137 7.4 A Suite of Six Tunable Cascode Gyrator Inductors.......................................... 142 7.4.1 Design One: A Cascode Gyrator Inductor Tunable from 10.4-18.2 nH........................................................................................144 7.4.2 Design Two: A Cascode Gyrator Inductor Tunable from 7.25-11.4 nH........................................................................................148 7.4.3 Design Three: A Cascode Gyrator Inductor Tunable from 4.75-8.15 nH........................................................................................154 7.4.4 Design Four: A Cascode Gyrator Inductor Tunable from 2.90-5.43 nH........................................................................................158 7.4.5 Design Five: A Cascode Gyrator Inductor Tunable from 1.57-3.30 nH........................................................................................163 7.4.6 Design Six: A Cascode Gyrator Inductor Tunable from 0.88-1.70 nH........................................................................................168 7.5 Inductor Suite Performance Summary................................................................173 Chapter 8: Nonlinear Effects on Phase, Distortion, and Dynamic Range............ 176 8.1 Linearity Measurement Methodology.................................................................177 8.2 Phase Error..............................................................................................................180 8.3 Total Harmonic Distortion and Dynamic Range................................................182 Chapter 9: Applications of Tunable Cascode Gyrator Inductors...........................185 9.1 RL High-Pass Filter Application..........................................................................185 9.2 LC Tank Oscillator Application...........................................................................190 Chapter 10: Conclusion.....................................................................................................194 References............................................................................................................................... 199 Bibliography...........................................................................................................................241 ix Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. List of Tables Table 1. Summary o f Performance Characteristics for Transistorized Gyrators...........86 Table 2. Performance Summary for Design One. The Inductance is Tunable from 10.4 to 18.2 nH, with Ln o m = 14.3 nH........................................................ 148 Table 3. Performance Summary for Design Two. The Inductance is Tunable from 7.25 to 11.4 nH, with Ln o m = 9.30 nH........................................................ 153 Table 4. Performance Summary for Design Three. The Inductance is Tunable from 4.75 to 8.15 nH, with Ln o m = 6.45 nH........................................................ 158 Table 5. Performance Summary for Design Four. The Inductance is Tunable from 2.90 to 5.43 nH, with Ln o m = 4.16 nH........................................................ 163 Table 6. Performance Summary for Design Five. The Inductance is Tunable from 1.57 to 3.30 nH, withZ„o m = 2.43 nH........................................................ 167 Table 7. Performance Summary for Design Six. The Inductance is Tunable from 0.88 to 1.70 nH, with Ln o m - 1.29 nH........................................................ 172 Table 8. Combined Performance Summary of the Suite o f Six Inductors....................174 Table 9. Linearity Summary of Design Three in Fig. 67.................................................184 x Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. List of Figures Fig. 1. Rectangular Thin-Film Planar Spiral Inductor................................................... 10 Fig. 2. Cross Section of a Spiral Inductor in Silicon......................................................14 Fig. 3. Lumped Physical Model of a Spiral Inductor in Silicon................................... 14 Fig. 4. Lumped Model of a Spiral Inductor in Silicon with the Substrate and One Port Grounded...........................................................................................16 Fig. 5. Equivalent Model to that in Fig. 4, with the Combined Impedance of Cox, Csi, and Rst Replaced with Rp and Cp...................................................... 17 Fig. 6. Symbolic Representation of an Ideal Gyrator.................................................... 31 Fig. 7. Ideal Gyrator Terminated at Its Output Port in a Capacitance, C....................32 Fig. 8. Capacitively-Terminated Nonideal Gyrator with Non-Zero Input and Output Conductances, gij and g22.................................................................. 33 Fig. 9. Equivalent Circuit of the Nonideal Gyrator in Fig. 8........................................34 Fig. 10. Negative Resistance Compensation of the Nonideal Gyrator in Fig. 8..........35 Fig. 11. Symbolic Representation of an Ideal Negative Impedance Converter (NIC).......................................................................................................39 Fig. 12. Ideal NIC Terminated at Its Output Port in Impedance, Zp..............................41 Fig. 13. An Ideal NIC-Based Gyrator................................................................................41 Fig. 14. Transconductor Implementation of an Ideal Gyrator........................................45 Fig. 15. Ideal Transconductor Gyrator Terminated at Its Output Port in a Capacitance, C..........................................................................................................45 Fig. 16. Symbolic and Equivalent Circuit Representations of an Ideal Transconductor.........................................................................................................52 Fig. 17. Ideal Transconductor Realization of a Capacitively-Terminated Gyrator 53 xi Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 18. Equivalent Circuit Representation of the Ideal Transconductor Gyrator Depicted in Fig. 17....................................................................................53 Fig. 19. High-Frequency General Transconductor Model Used for Stability Analysis.....................................................................................................54 Fig. 20. Complete Gyrator-Based Active Inductor Using the General Transconductor Model Given in Fig. 19.............................................................56 Fig. 21. Two-Port Equivalent Circuit of the Complete Gyrator-Based Active Inductor Using the General Transconductor Model........................................... 57 Fig. 22. Gyrator Active Inductor Realization for the Design Example in Section 4.4................................................................................................................ 70 Fig. 23. Simulated Frequency Response of the Inductance for the Gyrator in Fig. 22. The Inductance Value at Low Signal Frequencies is 24.91 nH and is Maintained to Within 15% of this Value Through 2.1 GHz..................................................................................................... 71 Fig. 24. Simulated Frequency Response of the Real and Imaginary Components of the Driving-Point Input Impedance for the Gyrator in Fig. 22. At Low Signal Frequencies, the Real Part of the Impedance is 1.14 Q and Remains Less Than 50 Q for Frequencies Through 1.12 GHz...................................................................................................72 Fig. 25. The Simulated Quality Factor of the Inductance for the Gyrator in Fig. 22. The Maximum Q of 11.77 Occurs at a Frequency of 170.6 MHz........................................................................................................... 73 Fig. 26. Gyrator A: Common-Source (NMOS)/Common-Drain (NM OS)................ 78 Fig. 27. Gyrator B: Common-Source (PMOS)/Common-Drain (PMOS)..................... 80 Fig. 28. Gyrator C: Common-Source (NMOS)/Common-Drain (PM OS).................... 80 Fig. 29. Gyrator D: Common-Source (PMOS)/Common-Drain (NM OS)................. 81 Fig. 30. Gyrator E: Common-Gate (NMOS)/Common-Source (NM OS)..................... 82 Fig. 31. Gyrator F: Common-Gate (PMOS)/Common-Source (PMOS).......................83 Fig. 32. Gyrator G: Common-Gate (NMOS)/Common-Source (PMOS)....................84 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 33. Gyrator H: Common-Gate (PMOS)/Common-Source (NMOS).....................85 Fig. 34. Small-Signal Model of a MOS Transistor in Saturation................................... 88 Fig. 35. Complete Model of Gyrator A Using the Small-Signal Transistor Model of Fig. 34....................................................................................88 Fig. 36. Equivalent Model of Gyrator A Using the Small-Signal Transistor Model Given in Fig. 34........................................................................ 89 Fig. 37. Revised General Transconductor Model with Reference Designators Corresponding to the Topology of Gyrator A ............................... 90 Fig. 38. Parallel RLC Circuit with Zj„(s) Equivalent to (106)........................................102 Fig. 39. Transistorized Gyrator Realization for the Design Example in Section 5.5.......................................................................................................... 107 Fig. 40. Simulated Frequency Response of the Inductance for the Gyrator in Fig. 39. The Inductance Value at Low Signal Frequencies is 22.37 nH and is Maintained to Within 15% of this Value Through 2.5 GHz................................................................................................... 108 Fig. 41. Simulated Frequency Response of the Real and Imaginary Components o f the Driving-Point Input Impedance for the Gyrator in Fig. 39. The Imaginary Component is Zero at 5.72 GHz........................... 109 Fig. 42. The Simulated Quality Factor of the Inductance for the Gyrator in Fig. 39. The Maximum Q of 2.03 Occurs at a Frequency of 1.03 GHz.............................................................................................................110 Fig. 43. A Cascode Gyrator Inductor................................................................................116 Fig. 44. A Cascode Gyrator Inductor with Non-Ideal Current Sources.......................118 Fig. 45. Small-Signal Model of the Cascode Gyrator Given in Fig. 44..................... 119 Fig. 46. Equivalent Model to the Cascode Gyrator Model in Fig. 45..........................120 Fig. 47. Simplified Yet Accurate Model of the Cascode Gyrator in Fig. 44. Elements C/o, C23, and R21 Have Been Omitted................................ 122 Fig. 48. Frequency Responses for the Simplified Yet Accurate Model of Fig. 47................................................................................................................. 123 xiii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 49. A Cascode Gyrator for Design Guideline Validation...................................... 134 Fig. 50. Frequency Responses for the Gyrator in Fig. 49.............................................. 135 Fig. 51. A Complete Tunable Cascode Gyrator Inductor.............................................. 138 Fig. 52. Small-Signal Model of the Tunable Cascode Gyrator Given in Fig. 51................................................................................................................. 139 Fig. 53. Equivalent Model to the Tunable Cascode Gyrator Model Given in Fig. 52......................................................................................................140 Fig. 54. Design One: A Cascode Gyrator Inductor Tunable from 10.4-18.2 nH................................................................................................. 144 Fig. 55. Frequency Responses of Le and Q for Design One with Different Values of V g t u n e • The Nominal Inductance is Tunable from 10.4-18.2 nH and Q > 10 for Signal Frequencies Between 800 MHz and 2 GHz..............................................................................................146 Fig. 56. Design Two: A Cascode Gyrator Inductor Tunable from 7.25-11.4 nH................................................................................................. 149 Fig. 57. Frequency Responses of Le and Q for Design Two with Different Values of V g t u n e • The Nominal Inductance is Tunable from 7.25-11.4 nH and Q > 10 for Signal Frequencies Between 800 MHz and 2 GHz..............................................................................................151 Fig. 58. Design Three: A Cascode Gyrator Inductor Tunable from 4.75-8.15 nH................................................................................................. 154 Fig. 59. Frequency Responses of Le and Q for Design Three with Different Values o f V g t u n e• The Nominal Inductance is Tunable from 4.75-8.15 nH and Q > 10 for Signal Frequencies Between 800 MHz and 2 GHz..............................................................................................156 Fig. 60. Design Four: A Cascode Gyrator Inductor Tunable from 2.90-5.43 nH..................................................................................................159 Fig. 61. Frequency Responses of Le and Q for Design Four with Different Values of V g t u n e■ The Nominal Inductance is Tunable from 2.90-5.43 nH and Q > 10 for Signal Frequencies Between 800 MHz and 2 GHz..............................................................................................161 xiv Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 62. Design Five: A Cascode Gyrator Inductor Tunable from 1.57-3.30 nH................................................................................................. 164 Fig. 63. Frequency Responses of Le and Q for Design Five with Different Values of V g t u n e ■ The Nominal Inductance is Tunable from 1.57-3.30 nH and Q > 10 for Signal Frequencies Between 800 MHz and 2 GHz..............................................................................................165 Fig. 64. Design Six: A Cascode Gyrator Inductor Tunable from 0.88-1.70 nH..................................................................................................168 Fig. 65. Frequency Responses of Le and Q for Design Six with Different Values of V g t u n e• The Nominal Inductance is Tunable from 0.88-1.70 nH and Q > 10 for Signal Frequencies Between 800 MHz and 2 GHz..............................................................................................170 Fig. 66. Inductor Tuning Ranges for Designs One Through Six. For Each Design, the Minimum, Maximum, and Nominal Inductances are Given Numerically, and the Tuning Range is Represented by a Vertical Bar 175 Fig. 67. Linearity Measurement Schematic Diagram..................................................... 177 Fig. 68. Ideal and Synthesized Voltage Responses of Design Three in Fig. 67 for a 1 GHz Sine Wave Input Current with 100 pA Amplitude ..................................................................................................... 179 Fig. 69. Voltage Responses of Design Three in Fig. 67 for a 1 GHz Sine Wave Input Current with Amplitudes from 100 pA to 1 mA..........................180 Fig. 70. Phase Errors for the Voltage Responses in Fig. 69.......................................... 181 Fig. 71. FFT o f the Voltage Waveform in Fig. 69 for Is with an Amplitude of 100 pA ............................................................................................ 182 Fig. 72. FFT o f the Voltage Waveform in Fig. 69 for Is with an Amplitude of 630 pA ............................................................................................ 183 Fig. 73. FFT o f the Voltage Waveform in Fig. 69 for Is with an Amplitude of 1 mA................................................................................................183 Fig. 74. RL High-Pass Filter Application.........................................................................186 Fig. 75. RL High-Pass Filter Responses Using Ideal and Synthesized Inductors 187 xv Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 76. RL High-Pass Filter Responses Using Ideal (with Parasitics) and Synthesized Inductors.................................................................................... 188 Fig. 77. LC Tank Oscillator Application......................................................................... 190 Fig. 78. LC Tank Oscillator Using Ideal and Synthesized Inductors...........................191 Fig. 79. LC Tank Oscillator Using Ideal (with Re = 0.74 Q) and Synthesized Inductors................................................................................... 192 xvi Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Abstract The unavailability of high-quality integrable inductors that are small, stable, tunable, and inexpensive, is a fundamental limitation of today’s monolithic fabrication processes. Planar spirals of metallization are commonly used to synthesize on-chip inductances, but these structures offer low quality factors (or “(3”s) and are neither small nor implicitly tunable. Compared to passive inductors, active realizations consume much less die area, have inductance values that can be easily tuned, and are capable of producing extremely high Qs. Active topologies based on the gyrator and implemented with transconductance amplifiers perform the best at high frequencies, but can suffer from instability for designs that require both high Q and high-frequency operation. To better understand the inherent design trade-offs between circuit stability, frequency response, Q, and the frequency at which Q is maximum, a detailed stability analysis of gyrator-based active inductors using transconductance amplifiers is performed. Design equations and operating constraints are derived to control the circuit damping and produce inductance values that are nearly independent of frequency over the required operational frequency range. The results of the stability analyses are used to design a suite of six cascode gyrator inductors with nominal inductance values from 1.3-14.3 nH and tuning ranges from ± 22% to ± 35%. The wide tuning ranges enable the suite o f inductors to produce any xvii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. inductance between 0.88-18.2 nH. Quality factors range from 10-60,000 and inductances are within ± 7-8% of their respective nominal values for signal frequencies between 800 MHz and 2 GHz using SPICE transistor parameters for a standard silicon CMOS process. Power consumption ranges from 1.7-18.6 mW using a single 2.5 V supply, and die areas vary from 16 to 543 times smaller than those required of comparable spiral inductors. Though the synthesized inductances use transistor models from a 0.13 pm CMOS process, the shortest channel length used in any design is 0.28 pm. All designs, therefore, can easily be ported to less expensive processes. One inductor from the suite is used in two signal processing applications with excellent results, illustrating the practicality of the final designs. xviii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 1: Introduction The explosive growth in wireless communications over the past decade has fueled an increased demand for radio-frequency (RF) circuits operating well into the gigahertz range. This growth has also increased the demand for system-on-chip (SoC) designs, in which all components of an electronic circuit are integrated on a single wafer. Although active components such as transistors and diodes can be reliably integrated using modem semiconductor processing techniques, not all passive components that meet the high-performance requirements of modem RF circuit designs can be easily fabricated on-chip. These monolithic passive resistors, capacitors, and inductors are used to match or modify impedances, filter out unwanted signals, and cancel transistor parasitics to provide high gain at high frequencies. Resistors and capacitors have been integrated on-chip since the invention of the integrated circuit in 1958 [1], and, like transistors and diodes, their present-day performance is adequate to satisfy most requirements of modem RF circuits. However, the difficulties of manufacturing high-quality integrated inductors have plagued circuit designers for decades. There have been many approaches attempting to fabricate on-chip inductors, but few o f these approaches have produced inductors with the performance characteristics demanded of state-of-the-art RF circuit designs. Despite the many significant advances in semiconductor processing over the past 50 years, the lack of small, stable, tunable, inexpensive, high- 1 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. quality integrable inductors remains a conspicuous shortcoming of today’s monolithic fabrication processes [2], The goal of this research is to greatly improve the performance and features of integrated inductors operating in modem RF circuits. The steps required to reach this goal are outlined in Chapter 2, along with target performance specifications for the final inductor designs. To gain insight into the history of inductance synthesis, Chapter 3 reviews the many techniques that have been proposed to produce on-chip inductors since the 1950s. Each technique is investigated to determine its strengths and weaknesses, and the state-of-the-art performance of modem implementations is assessed. It is determined in Chapter 3 that active integrated inductors based on the gyrator and implemented with transconductance amplifiers perform the best at high frequencies, and offer the most promising topology to meet the research objectives outlined in Chapter 2. Chapter 4 offers a detailed stability analysis of gyrator-based active inductors using transconductance amplifiers. Design equations are derived using a practical high- frequency model of each transconductor, and the circuit damping factor is extracted and analyzed to reveal the relative stability of the synthesized inductor. Operating constraints are then provided to mitigate the effects of parasitics and to ensure optimal frequency response and stability. 2 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapters 5 and 6 expand the stability analysis of Chapter 4 to include transistorized gyrators (those using only two transistors) and cascode gyrator topologies, respectively. The equations and design guidelines derived in Chapter 6 are then used in Chapter 7 to design a suite of six tunable cascode gyrator integrated inductors. Chapter 8 investigates the linearity of one inductor from the suite, and favorable values are obtained for the phase error, distortion, and dynamic range. Chapter 9 uses the same inductor from Chapter 8 to implement a tunable RL high-pass filter and a tunable LC tank oscillator, yielding excellent results for both. Finally, Chapter 10 provides a summary of the contributions of this work, and offers potential design projects for future research. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 2: Research Objectives As indicated earlier, the goal of this research is to greatly improve the performance and features of integrated inductors operating in modem RF circuits. The objectives necessary to accomplish this goal are outlined below. 2.1 Evaluate Integrated Inductance Architectures The first step to improving the performance of integrated inductors is to determine the strengths and weaknesses of state-of-the-art inductance architectures, and then select the architecture that offers the greatest promise of satisfying the performance specifications outlined in Section 2.3. The evaluation of inductance architectures is completed in Chapter 3 and summarized in Section 3.6. 2.2 Analyze the Preferred Architecture and Offer Improvements The next step is to improve the performance of the most promising inductor topology. To accomplish this task, the limitations of the selected inductor will be thoroughly examined, and design guidelines and circuit modifications will be developed to mitigate these limitations and improve overall performance. This analysis is performed in Chapters 4 through 6, with final designs presented in Chapter 7. 2.3 Establish Performance Specifications for Final Designs The performance goals for the completed designs are established in Sections 2.3.1 through 2.3.7, and the actual results of the final designs are summarized in Section 7.5. 4 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2.3.1 High-Frequency Operation This research will provide transistor-level designs of integrable inductors that operate at signal frequencies between 800 MHz and 2 GHz using a standard silicon CMOS process. 2.3.2 Stable Inductance Values Achievable inductance values will be between 1 nH and 15 nH, and will be independent of frequency to within ± 15% of their nominal value over the operational frequency range. 2.3.3 High Qs Achievable Q values will be no less than 10 over the entire signal frequency range of 800 MHz to 2 GHz. 2.3.4 Tunable Inductance Values The inductance values will be tunable from ± 20% of the nominal values, with Q remaining no less than 10 over the entire tunable range. 2.3.5 Very Small Die Area The die area consumed by each complete design, including biasing and tuning circuitry, will be at least 10 times smaller than that required of a comparable planar spiral inductor. 5 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2.3.6 Low Voltage Operation All circuitry will be powered from a single voltage supply between 1.2 V and 2.5 V. 2.3.7 Low Power Consumption The power consumption of the final inductance circuits, including biasing and tuning circuitry, will be no more than 10 mW. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 3: An Evaluation of Integrated Inductance Architectures To gain insight into the most promising topology for inductance synthesis, this chapter reviews the many architectures that have been proposed to produce on-chip inductors. Passive implementations are discussed first, with spirals in Section 3.1, out-of-plane micro-inductors in Section 3.2, and bond wire inductors in Section 3.3. Active inductors are reviewed next, with non-gyrator designs in Section 3.4, and architectures based on gyrators in Section 3.5. A brief summary is offered in Section 3.6. 3.1 Planar Spiral Inductors Planar spiral inductors, also called planar spirals or single-layer spirals, differ from traditional wound coils in that planar spirals are flat coils in which the conductor winds within itself in a single plane. Although these spirals may be circular, rectangular, square, or even octagonal, square spirals are the most common since many layout tools do not support angles other than 90 degrees. 3.1.1 Printed Circuit Planar Spirals Single-layer spirals were first manufactured as printed circuits, in which the spiral was formed on the surface of a printed wire board along with conductive traces that connected the discrete components together [3-5]. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. In 1903, Hanson filed for a printed wire patent that describes a method to produce conductive metal patterns on a dielectric by cutting or stamping copper or brass foil patterns, and adhesively bonding them to paraffin paper. He also stated that conductors could be formed in situ by electro-deposition or by applying metal powder in a suitable medium [5]. Many more patents were granted between 1923 to 1939 describing different methods o f making circuit connections on an insulating base, but their connections replaced only wires, not the components themselves [4]. In the 1940’s, the U.S. National Bureau of Standards and the Army Ordnance Department developed a miniaturized proximity switch for trench mortar shells that included printed resistors and capacitors in addition to their connective traces. The first known design to include printed spiral inductors, however, was not completed until 1947, when Sargrove described his fabrication technique to produce printed circuit panels for radio receivers [4, 6]. Although over 80 printed circuit patents were issued in the decade following Sargrove’s work, planar spirals began to show their drawbacks soon after their discovery [7]. Classical inductance equations derived for wound coils produced errors as high as 100%, and new equations were needed to more accurately predict performance. A precise estimate of the Q of the inductor, however, could not be determined, forcing designers to rely on experience rather than calculations [3, 4, 8]. In addition, inductance values were limited to a few microhenries and the spirals consumed large amounts of area. A 1 pH circular printed inductor could have Q = 100 8 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. at 25 MHz, but could easily have a diameter larger than 1 cm. These limitations of printed circuit spirals all contributed to severely limit their use [3, 4, 9]. 3.1.2 Thin-Film Planar Spirals Planar spirals were later manufactured using thin-film techniques in which conductive, resistive, and/or insulating films are deposited or sputtered on an insulating substrate. The term “thin-film” is descriptive in that the deposited films are only a few microns in thickness, compared to 10 to 50 microns for thick-films [10]. Thin-film spirals date back to the invention of the integrated circuit, when in 1958, Kilby connected together a transistor, capacitor, and three resistors to form an oscillator on a single body of germanium [11]. Although this first design did not include an inductor, Kilby described in his patent application of 1959 how inductors could be fabricated with a single-layer circular spiral of semiconducting material [12]. Although not originally integrated with other active devices, early thin-film inductances consumed much less area than their printed circuit predecessors. For example, a compact 1 pH printed circuit inductor in 1955 may have had a diameter of approximately 1 cm [3], while in 1964, a thin-film inductor with the same inductance may have had a diameter 10 times smaller [13]. The improved fabrication process of thin-films allowed for smaller spiral widths and a greater number of turns in the same area. Though smaller in size, thin-film inductors still suffered from low inductance, low Q, and undesirable coupling effects. The coupling could be reduced and the 9 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. inductance increased by using coils with magnetic core material (having relative permeability n > 1) [14, 15], but these advantages were offset by fabrication problems, limited frequency response, increased losses that further lowered Q, and possible nonlinear effects [13]. Eventually, attempts were made to integrate thin-film spirals on-chip, creating a complete integrated circuit. Fig. 1 depicts a rectangular thin-film planar spiral inductor with corresponding inductance, Ls, given in (1) where /jo is the permeability of free space in Henries/meter (/a> = 4n x 10'7 H/m), n is the number of turns, r is the outer radius in meters, and a is the mean radius in meters. For a 10-tum spiral with r = 100 pm and a = 50 pm, Ls - 7.85 nH [2]. 2r _ Fig. 1. Rectangular Thin-Film Planar Spiral Inductor. 2 2 31.5/J0n a s 22r — \4a (1) Although thin-film spirals are smaller than those made with printed circuit techniques, they are still much larger than the transistors, diodes, capacitors, and resistors that 10 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. comprise the rest o f the circuit’s components. The relatively large size required of planar spirals is due partially to the relationship between the physical dimensions of the spiral and its resulting Q. When a capacitor’s dimensions are reduced, its capacitance decreases proportionately but its Q remains constant at a given frequency. When an inductor’s dimensions are reduced, however, its Q decreases as the square of the scaling factor [16, 17]. Another contribution to low Q of early thin-film inductors was the high conductor resistivity of early monolithic processes. One can see from the simplified expression for Q in (2) that high resistive losses will lower Q. In (2), Q is defined as the reactance, coLs, divided by the conductor resistance, Rs, where co is the angular frequency and Ls is the inductance [18]. It was determined in the early 1960s that these resistive losses were the main barriers that prevented the practical use of miniaturized inductors [16]. From the 1960s through the 1980s, there were reports of inductors with higher Qs for monolithic microwave integrated circuits (MMICs) at frequencies from 1-20 GHz (note from equation (2) that higher frequencies will produce higher Qs), but these designs used exotic insulating or semi-insulating substrates such as gallium arsenide (GaAs) [18-28], sapphire [20, 29, 30], alumina [20, 31], and quartz [20]. The majority 11 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. of the circuits at that time were fabricated in silicon (Si), however, and operated at frequencies below a few hundred megahertz. These lower frequencies of operation, together with the lithographic limitations of Si processes and the conductivity of the Si substrate, prevented the use of planar spiral inductors with Si integrated circuits through the end o f the 1980s [32]. This situation changed in the early 1990s, however, when Nguyen and Meyer fabricated several Si integrated inductors and used them successfully in an LC filter [32], an RF bandpass amplifier [33], and a voltage-controlled oscillator [34]. Several process improvements contributed to the success of their designs: 1) metal width and pitch reached the low micrometer range which allowed for more inductor turns per unit area; 2) oxide-isolated processes allowed thick oxides to help isolate the inductor from the Si substrate and increase its frequency of self-resonance; and 3) the advent of 900 MHz communications and gigahertz-range satellite reception such as the Global Positioning System (GPS), and Direct Broadcast Satellite (DBS) pushed frequencies high enough to boost Qs to more reasonable values [32]. Although Nguyen and Meyer were successful in fabricating spiral inductors in Si, the Qs they achieved were still quite modest, with values ranging from 3 at 900 MHz to 8 at 4.1 GHz, and they still required an oxide-isolated process to minimize losses from the conductive Si substrate. To better understand the complex issues facing integrated spiral inductor design, a more thorough knowledge of planar spiral physics is required. 12 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. As mentioned in Section 3.1.1, early equations for traditional multi-layer wound coils [8], single-layer circular coils [3, 8, 14-16, 18, 29, 30, 35, 36], and single-layer square spirals [3, 13, 16, 29, 35, 36] were not sufficiently accurate for the smaller dimensions of newer planar square spirals, so new analyses were needed. In 1974, Greenhouse provided the most useful and accurate expressions of the day, updating earlier research to reflect the smaller dimensions of square and rectangular spirals in the 1970s [37]. Although many subsequent spirals have been designed using Greenhouse’s models, the need for more accurate and more user-friendly models for the ever-changing state-of- the-art processes continues to this day, spawning a plethora of journal and conference papers with more intricate models and more detailed analyses each year [20-28, 31, 32, 38-100]. Why is modeling a seemingly simple spiral of metal so difficult? The useful design parameters of planar spirals, namely, Q, the inductance, and the frequency at which the inductor self-resonates, are complicated functions o f the spiral geometry and physical properties of the substrate, intermetal dielectric, and the metal itself that is used in the spiral’s construction. In addition, the underlying parasitic effects are far too difficult to predict analytically [46,47]. To illustrate the parasitics involved, a cross section of a planar spiral inductor in Si is depicted in Fig. 2, along with an overlay of its main parasitic elements. In the figure, Ls is the ideal inductance, Rs the conductor resistance, Cs the feed-through capacitance between the spiral and the center tap underpass, Cox the oxide capacitance, Rst the substrate loss, and Cs, the substrate capacitance. 13 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. A /W Oxide ox ox Substrate Fig. 2. Cross Section of a Spiral Inductor in Silicon. A lumped physical model of the spiral in Fig. 2 is given in Fig. 3. The elements in Fig. 3 contribute to three leading parasitic effects. These effects include losses in the metal spiral which lower Q, losses in the conductive substrate which lower both Q and the inductance, and coupling from the inductor to the substrate which lowers both the inductance and the self-resonant frequency. A /W Fig. 3. Lumped Physical Model of a Spiral Inductor in Silicon. 14 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. First, Q is decreased by losses in the metal spiral at low frequencies due to the series resistance, Rs, of the metal conductor. To increase Q, these resistive losses can be reduced by using thicker metal traces [44, 45, 47, 99, 101, 102], connecting several metal layers together in parallel [103], or using highly-conductive metals such as gold [101, 102, 104] or copper [81, 92, 95, 99, 100]. The series resistance is easily calculated at low frequencies, but the complex interaction of eddy currents and the skin effect at higher frequencies decreases Q further, thereby yielding errors between calculated and actual values [46]. Second, both Q and the inductance are decreased by the losses in the conductive substrate, modeled by i?s,. Most CMOS processes today use a heavily-doped Si substrate in which induced currents from the magnetic field of the inductor are free to flow. According to the law of Faraday-Lenz, an electric field is then magnetically induced in an imaginary spiral in the substrate under the inductor [46], This electric field causes an opposing image current to flow in the substrate, which manifests itself as an effective series resistance, lowering Q. For spirals with radii smaller than approximately 135 pm, the metal losses dominate and Q will be determined by the series resistance of the conductor. For larger spirals, the effective resistance due to induced substrate currents dominate and Q can be decreased by over 60%. The opposing substrate currents also lower the inductance by decreasing the total magnetic field of the inductor. Studies show a decrease in the inductance of 10% is possible 15 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. [46]. Although substrate losses can drastically altar the inductor’s performance, the magnitude of their effects on Q and the inductance is difficult to predict [47], Third, both the inductance and the self-resonant frequency are decreased due to the capacitance from the inductor to the substrate. This capacitance forms an LC tank with the desired inductor, creating a resonant frequency above which the spiral is no longer inductive [46]. A typical 10 nH inductor has a self-resonant frequency of 2.5 GHz [32]. This limits the maximum inductance at a certain frequency because increasing the inductance requires a larger spiral, which in turn, increases the substrate capacitance and lowers the self-resonant frequency. To clarify these parasitic losses further, assume the spiral in Fig. 3 has the substrate and one port connected to ground. The resulting lumped model is shown in Fig. 4 [50]. ox Fig. 4. Lumped Model of a Spiral Inductor in Silicon with the Substrate and One Port Grounded. 16 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. To simplify the following analysis, the combined impedance of Cox, Csi and Rs: replaced with Rp and Cp in Fig. 5, where R d = 1 _____ ! Rsi (Cox + CSi) ® Cox Rsi c , ox and C = C '- 'P '- ’OX \ + co (Cox + CS i )CSiRS i 1 + a>\Co x +CSi) 2 RSi2 (3) (4) Fig. 5. Equivalent Model to that in Fig. 4, with the Combined Impedance of Cox, Csi, and Rsi Replaced with RP and Cp. Inductor Q may be defined in terms of magnetic and electric energy as energy stored Q = 2 7 T = 2 n energy loss in one oscillation cycle peak magnetic energy - peak electric energy energy loss in one oscillation cycle (5) (6) where V 2L K o J peak magnetic 2[(<a£s )J + fls2] ’ (7) Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. V0\ C S + CP) J peak electric (8) and E loss in one oscillation cycle I n V 2 [ y o C O 2 l - + - R* RP (coLs ) + Rs Substituting (3), (4), (7), (8), and (9) into (6) yields coL. Q = R c [Substrate Loss Factor\Self-resonance Factor\, where Substrate Loss Factor = R t and Self-resonance Factor = Li c (9) (10) (11) ( 12) The first term in (10), coLs/Rs, is equal to the simplified Q given in (2) and represents the stored magnetic energy and the resistive loss in the metal spiral. This term accurately predicts Q to a few hundred megahertz in modem Si CMOS processes. The substrate loss factor accounts for the degradation of Q as the electric field from the inductor penetrates into the substrate at higher frequencies. The self-resonance factor accounts for the reduction in Q caused by the increase in peak electric energy with increasing frequency. It can be seen from (6) that as the peak electric energy increases from zero, Q is decreased. When the peak electric energy equals the peak magnetic 18 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. energy, Q = 0 and the inductor is in self-resonance. This self-resonant frequency can be determined by equating (12) to zero [50]. Various techniques have been employed to isolate the inductor from the Si substrate to reduce substrate loss and coupling, thereby increasing Q, the inductance, and the self resonant frequency. These include: 1) the use of special oxide-isolation [32-34] and silicon-on-insulator (SOI) processes [57, 82, 91, 105]; 2) removing the Si in areas directly beneath the inductor with special etching [92, 106] or micromachining [57, 73] techniques; 3) excluding lower level metal from the spiral to increase the spacing between the inductor and the substrate [47, 107]; and 4) adding a thick oxide layer [81, 104] or low-loss, low-k dielectric [92] between the inductor metal and the substrate. Though sometimes effective, these techniques either use special processes, or add extra non-standard steps to traditional processes that the industry is hesitant to adopt [46]. Patterned ground shields have also been used to isolate the inductor from the substrate [50, 78, 79, 88, 95, 100]. Note that from (11), the substrate loss factor can be made to approach unity as Rp approaches infinity. From (3), it can be seen that Rp will approach infinity as Rsi approaches either infinity or zero. Thus, Q can be increased by using either a high-impedance substrate (like those used in the special processes described in the preceding paragraph), or by using an extremely conductive substrate, such as a substrate shorted directly to ground. A shorted substrate can be simulated by placing a ground shield between the spiral and the actual substrate. This has the effect 19 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. of terminating the electric field at the ground plane before it reaches the substrate. However, the ground plane also allows the image current discussed earlier to flow more freely, decreasing the magnetic field and lowering the inductance. The image current can be reduced by creating slots in the ground plane that are perpendicular to the direction of the image current flow. These slotted planes are called patterned ground shields, and have been shown to improve Q in lightly doped Si substrates. They have not yet, however, been shown to be effective in the more common heavily- doped Si CMOS processes. In addition to the losses outlined above, integrated planar spirals have further weaknesses. They lack tuning ability and suffer from temperature dependencies that vary with frequency. Studies have shown that at frequencies below 2 GHz, Q decreases with increasing temperature, but at frequencies above 2 GHz, Q increases with increasing temperature [48]. And finally, even in modem deep submicron processes, planer spirals are still much larger than integrated resistors and capacitors. Attempts have made to reduce their chip area by using modified center-tapped spirals [39] and by using several metal layers connected together in series to form so-called “stacked” inductors [74, 75, 79, 84, 85, 95, 100, 107]. Modified center-tapped spirals have been shown to require only 63% of the area needed for traditional spirals and they can increase the self-resonant frequency by a factor of two, but they can be used only in balanced circuits in which the center 20 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. tap of the spiral is a virtual ground [39]. Creating “stacked” inductors by connecting several metal layers in series has similar limitations. Although the inductance per unit area can be increased nine times with only three metal layers and the resulting topology may have only half o f the resistive losses, the maximum Q occurs at lower frequencies and the self-resonant frequency is similarly reduced due to higher inter-wire capacitance [107]. Although many improvements have been made to the design and fabrication of planar spirals on Si substrates, they still suffer from many o f the same disadvantages that plagued early designs: low Q, large chip area, special processing requirements, and a lack of tunability. State-of-the-art spirals that can be fabricated in standard CMOS processes and that consume a chip area of approximately 300 pm x 300 pm include a 2 nH inductor with Q = 19 at 2.4 GHz and Q - 14 at 5.8 GHz, and a 6 nH inductor with Q = 9 at 2.4 GHz and Q = 1.5 at 5.8 GHz [108], 3.1.3 (^-Enhanced Planar Spirals To overcome the low Q offered by most planar spirals, several active ^-enhancement techniques are available. These techniques usually use simple negative resistance generators to compensate for losses in the inductor [109-116]. In some applications, an effective negative resistance is generated by adding a second spiral and exploiting the coupling between the two inductors [49, 59, 116-121]. In these designs, losses in the primary spiral are compensated by active magnetic feedback from the secondary spiral. 21 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Qs as high as 3000 have been reported for ^-enhanced coupled inductors at 2 GHz with inductances in the 10 nH range [121]. Not only is Q made higher, but the addition of active circuitry to the passive spiral usually allows for the Q to be tunable, and additional circuitry is often added to tune the center frequency of filters and amplifiers that employ spirals with ^-enhancement. Unfortunately, the additional circuitry required of ^-enhancement compensation schemes increases power dissipation, degrades noise figure, and limits dynamic range. Compensation circuitry is also sensitive to on-chip parasitics, requiring automatic on- chip tuning mechanisms which further increase power and degrade frequency response [122]. Perhaps the greatest drawback of ^-enhanced spirals is their physical size. Even if high-Q and tunability is achieved with additional circuitry, the spirals still consume large amounts o f die area. 3.2 Out-of-Plane Micro-Inductors Recently, three-dimensional out-of-plane inductors have been proposed which can be micromachined on a wafer surface. These include both out-of-plane spirals and out-of- plane coils. 3.2.1 Three-Dimensional Out-of-Plane Spirals In some out-of-plane inductor applications, planar spirals are formed on the surface of the wafer, and then the spirals are rotated 90 degrees from the wafer surface by either 22 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. plastic deformation magnetic assembly (PDMA) or solder surface tension self- assembly (SSTSA). With PDMA [123], a planar spiral is first fabricated on a flexible micro flap using a surface micromachining process. The flap is connected to the substrate on one side and left unconnected on the other three sides. After micromachining, the spiral lies in the same plane as the wafer, similar to a conventional spiral. However, when an external magnetic field is applied, the spiral lifts off of the substrate as the flexible flap bends at the side connected to the substrate. When the magnetic field magnitude reaches a threshold value, the bending will enter the plastic deformation region. Once plastic deformation is reached, the spiral will remain suspended off of the substrate - preferably perpendicular to the substrate - even after the magnetic field is removed. Out-of-plane inductors using SSTSA [124] also produce spirals that stand perpendicular to the substrate. As with PDMA, the spiral is first formed using micromachining techniques in a plane parallel to the substrate. The two ends of the spiral windings are then connected to solder pads located on either side of the spiral. The pads have solder on one of their sides, but no solder on the other three sides. When the wafer is heated, the solder on the pads melts, and the surface tension of the solder rotates the complete structure out of the substrate plane and perpendicular to the substrate surface. When the wafer is then cooled, the solder resolidifies to hold the pads and the spiral in place. 23 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The main advantage of perpendicular spiral inductors produced by PDMA and SSTSA manufacturing techniques is that substrate coupling is reduced, increasing Q. SSTSA inductors have produced Qs as high as 20 for frequencies between 500 MHz and 3 GHz for inductances of 1.5 to 2.5 nH and with a die area of 1.2 mm x 0.5 mm. The greatest drawbacks of these procedures, of course, are the special micromachining steps and the non-standard shape of the resulting die that must be encapsulated during packaging. In addition, these structures are even larger than traditional planar spirals. 3.2.2 Three-Dimensional Out-of-Plane Coils In other out-of-plane inductor techniques, thin molybdenum-chromium (MoCr) films are sputter-deposited with an engineered built-in stress gradient so that, when patterned and released from their substrate, they curl into circular springs [125, 126]. The springs self-assemble and interlock to form coil windings that are then electroplated with low-resistance metal, such as copper (Cu). The advantages of such structures are that both magnetic coupling to the substrate and resistive losses due to the skin effect are reduced. With the coil axis parallel to the substrate, coupling is reduced because the magnetic flux lies mainly above the substrate, instead o f penetrating into it. The skin effect is reduced for the following reason. As with a traditional planar spiral, the skin effect forces the current to the outer most regions of metal that form the inductor winding. For planar spirals, the outer most regions of metal are the outer edges of the flat metal spiral. Hence, making the metal wider than the skin depth of Cu 24 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. does not lower the resistive losses at a given frequency. To reduce the skin effect of planar spirals the metal traces need to be made thicker, which is more difficult than making them wider. The outer most regions of metal of a three-dimensional out-of- plane coil, however, correspond to the top and bottom of the metal traces that form the coils, which can easily be made wider to reduce resistive losses. With these benefits, out-of-plane spirals have produced Qs up to 85 at 1 GHz in lightly-doped Si, but the extra steps and materials required are far from standard. Moreover, even though Qs are higher than for planar spirals, out-of-plane coil inductors still consume large amounts of chip area. To produce an inductor of a few nanohenries with Q optimized at 1 GHz, six coiled springs are required at 200 pm wide each, with a pitch o f 230 pm and a 267 pm radius resulting in an enormous die area of 1.68 mm x 1.35 mm [126]. In addition, like both traditional planar spirals and out-of-plane spirals, neither the Q nor the inductance value is tunable. 3.3 Bond Wire Inductors The parasitic inductance o f a packaging bond wire can be considered another integrated inductor available to circuit designers. Bond wires are readily available in standard Si CMOS processes, and circuits which incorporate bond wire inductances into design parameters have been shown to work successfully [46, 63, 66, 71, 72, 104, 127-133], Standard bond wire inductors consume less area and have lower phase noise than planar spirals [66], and, because the wires are relatively far from the substrate surface, 25 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. t f20 ___ r In — 0.75 H — 5 I r ) e_ coupling to the substrate is negligible [128]. The bond wire inductance is a function of both the wire length and radius, and may be calculated as (13) where L is the inductance in nanohenries, I is the wire length in millimeters, and r is the radius of the wire cross section in millimeters [71]. For example, a 4 mm long bond wire with radius of 12.7 x 10' mm (1 mil diameter) produces an inductance, L = 4.6 nH. Unfortunately, an accurate prediction of the wire inductance can be made only if the wire length is tightly controlled, and this can only be done using pad-to-pad bonding on the same chip, rather than pad-to-bond finger or pad-to-lead frame bonding which is used during package assembly. Optimal inductance values often require pad- to-pad bonding too (because the desired inductance value may correspond to a wire length that is not suitable for standard bonding), but this special bonding process is not compatible with most automated bonding equipment [131]. The DC resistance of a bond wire is given by (14) where Rw ire is in ohms, p is the resistivity of the wire material in ohm-meters, i is the length of the wire in meters, and A is the area of the wire cross section in square meters [71]. For a 4 mm long gold wire {p = 2.35 x 10’8 Qm for Au) with a radius of 12.7 x 10'6 m, A = 5.07 x 10'1 0 m2 and Rw ire =185 mQ. Although this is a low resistance, the 26 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. skin effect will substantially increase the resistance of the bond wire at high frequencies [71]. The skin depth may be calculated as where 8 is in meters, p is the resistivity of the wire material in ohm-meters, po is the permeability of free space in Henries/meter (jjq = 4n x 10'7 H/m), and / i s the signal frequency in hertz. At a frequency of 1 GHz, the skin depth o f gold is 2.4 pm, so only the outer shell of the wire conducts. The area of this outer shell is approximately equal resistance of 490 mQ at 1 GHz, about 2.6 times greater than the DC resistance. This increase in resistance at high frequencies can limit bond wire inductor applications Standard bond wire inductances of a few nanohenries have produced Qs as high as 50 at 2 GHz [131]. More elaborate schemes that place several short bond wire loops next to each other to simulate a coil have also been proposed, but these techniques require special bonding machines with loop control capability, and the area consumed by the resulting coils is very large. Coils containing two, three, and four loops require chip areas of 160 pm x 770 pm, 250 pm x 770 pm, and 340 pm x 770 pm, respectively [129, 130]. Like other out-of-plane inductors, these dimensions are even larger than those of planar spirals. (15) in 9 to 2 7 1 r • 8 = 1.92 x 10' mm . Substituting this area back into (14) yields a series [71]- 27 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Other drawbacks of bond wire inductors include: 1) mutual coupling effects of adjacent wires require electromagnetic analysis [131]; 2) the spread of inductance values on a single chip can reach ± 20% which makes tuning out component variations difficult [66]; 3) yield and repeatability of the bonding process cannot be guaranteed by manufacturers; and 4) wire bonding is not compatible with flip-chip assembly techniques [134]. As a result, the semiconductor industry is hesitant to adopt bond wire inductors for mass production [46]. 3.4 Non-Gyrator Active Inductors An alternative to the passive inductors described above (planar spirals, out-of-plane micro-inductors, and bond wire inductors) is the active inductor. Although plagued by higher noise and higher power consumption than passive realizations, active inductors consume much less die area, have inductance values that can be easily tuned, and are capable of producing very high Qs [135]. Many of these circuits are based on the gyrator, described in Section 3.5, and many others use non-gyrator architectures briefly outlined here. 3.4.1 Semiconductor Junction Active Inductors Some of the earliest non-gyrator active inductors used the implicit inductive reactance of semiconductor junctions themselves. It was discovered in the early 1950s that point contact diodes, like their vacuum tube predecessors, could become inductive under certain conditions [136]. Similar inductive behavior was later found injunction diodes 28 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. and transistors, spawning several research efforts to fully understand the phenomenon and to use these elements as on-chip inductances [136-146], Inductive diodes were used as early as 1960 to implement the inductance in an LC resonant tank circuit [140] and a frequency rejection filter [141]. Unfortunately, early forward-biased junctions yielded inductances with Q less than unity. Compensation was possible with negative resistance devices, but these produced very high temperature dependencies and stability problems [144], Later, the inductive properties of emitter-follower and source-follower transistors were used to increase the bandwidth of broadband amplifiers using shunt-peaking techniques [147-150], Although successful in increasing amplifier bandwidth, the Qs attainable by these stages are typically no more than 3, and therefore tremendously limit the applications in which semiconductor junction inductors may be used. 3.4.2 Other Non-Gyrator Active Inductors After investigating the low Qs derived solely from the intrinsic inductance of semiconductor junctions, researchers began to design complete active circuits to provide simulated inductances yielding higher Qs. Inductor circuits have been designed using several active circuit building blocks including op-amps [151-164], current conveyors [165-182], negative impedance converters [151, 183, 184], positive impedance converters [185, 186], transconductance amplifiers [159, 160, 187, 188], switched capacitors [189-195], and others [196-204], Although some of these 29 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. topologies have been shown to produce reasonable results, synthesized inductance architectures based on the gyrator are widely recognized for their superior performance over non-gyrator topologies [135]. 3.5 Gyrator-Based Active Inductors O f the many architectures able to produce active inductances, those based on the gyrator are reported to be the best [205] and most popular [206]. A gyrator is a nonreciprocal two-port network first reported in 1948 by Tellegen [207], and patented in 1953 [208]. Intended to extend synthesis techniques to nonreciprocal circuits, the gyrator complemented the ideal transformer, inductor, capacitor, and resistor. Its network equations are similar to those of mechanical gyrostatic systems, and was named to describe the way in which the voltages at the ports are gyrated with the currents. A subset of a positive impedance inverter, a gyrator inverts an impedance into its reciprocal [209]. Thus, an ideal gyrator, when terminated at one port with a capacitance, produces an inductance at the other port [210]. 3.5.1 Ideal Gyrators The symbol for an ideal gyrator is shown in Fig. 6, which delineates the positive senses of the input and output voltages, Vi, and V2, respectively, and the input and output currents, Ij, and I2, respectively. 30 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 6. Symbolic Representation of an Ideal Gyrator. The terminal volt-ampere characteristics of an ideal gyrator are given by ’A" 0 gi" > r A r s 2 0 A The original definition o f an ideal gyrator requires that gi = g 2, forcing the input power to zero and yielding a passive network. For inductance simulation, however, this equality is not necessary, and the more general network in which gi is not necessarily equal to g2 is commonly called an active gyrator [210]. The arrow in the gyrator symbol shows the direction of the forward transmission path. The nonreciprocal nature of the gyrator allows no backward transmission [211]. If the gyrator in Fig. 6 is terminated at its output port in a capacitance, C, as shown in Fig. 7, the ideal conductance matrix in (16) produces a driving-point input impedance, Zm(s), which relates to capacitance, C, in accordance with Z J s ) = ^ - = ---------------- = — . (17) A (S) £l&2Zcapacitor § l § 2 31 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. z /„w •------ + u c Fig. 7. Ideal Gyrator Terminated at Its Output Port in a Capacitance, C. It is easily seen from (17) how an ideal gyrator performs impedance inversion, and how this property can be used to synthesize inductance from capacitance. The ideal gyrator in Fig. 7 simulates an ideal inductor with an effective inductance, Le, equal to C L. =■ 8 1 8 2 (18) 3.5.2 Gyrators With Non-Zero Input and Output Conductances Unfortunately, most practical inductors deviate from the ideal gyrator described above in two primary ways. First, elements on the principal diagonal of the conductance matrix may not be equal to zero. In this case, the nonideal conductance matrix is shown in (19). £11 8 i ~ § 2 8 2 2 where g n * 0 and g 22 * 0 (19) The matrix o f (19) may be decomposed into the sum of the ideal matrix of (16) and another matrix containing the nonideal principal diagonal elements, g n and g 22, as shown in (20). 32 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Expression (20) shows that the terms g n and g 2i represent parasitic input and output conductances, respectively, for the otherwise ideal gyrator. These parasitic conductances are manifested by loss in the gyrator and are modeled in the capacitively- terminated nonideal gyrator of Fig. 8. Fig. 8. Capacitively-Terminated Nonideal Gyrator with Non-Zero Input and Output Conductances, g// andg 22- The effect of non-zero input and output gyrator conductances on the resulting synthetic inductance can be derived by analyzing the equivalent circuit of Fig. 9. In the equivalent circuit, the synthetic inductor consists of the same inductance value given in (18) for the ideal gyrator, with the addition of a shunt resistance o f value 1 /gn, and a series resistance of value S 22 (21) 'series g \g 2 33 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 9. Equivalent Circuit of the Nonideal Gyrator in Fig. 8. The loss introduced by non-zero input and output conductances of the nonideal gyrator results in a finite Q of the resulting synthetic inductor and is given in (22). Q = -------------------- ^ S x S i C — ---------- ^ 8 x 8 2 8 2 2 ^ S 1 1 S 2 2 E \ \ C The maximum value o f Q is e „ „ = , + 1 , (23) A8ig2 + g n 8 2 2) \ SnS22 which occurs at frequency + (24) c \ 8 1 1 8 2 2 As indicated by (23), the input and output conductances, g n and g 22, should be much smaller than the gyration conductances, gj and g 2, if a large Q is desired [212]. One way to reduce non-zero g n and g 22 is to compensate both ports of the gyrator with negative conductances. It can be seen from Fig. 8 that, theoretically, shunting the input 34 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. port with a resistance of value - l/g n will compensate for non-zero input conductance, and similarly, shunting the output port with a resistance of value - \i g 22 will compensate for non-zero output conductance [211]. If such a compensated gyrator is to perform inductance simulation, the capacitor used for impedance inversion should be placed as shown in Fig. 10. Practical difficulties of this compensation technique are described in Section 3.5.5.1. Z. (s) m K ' U ) c V2 N egative R esistance C om pensation N egative R esistance C om pensation Fig. 10. Negative Resistance Compensation of the Nonideal Gyrator in Fig. 8. 3.5.3 Gyrators With Frequency-Dependent Gyration Conductances A second type o f nonideal behavior exhibited by practical gyrators is the frequency dependence o f the gyration conductances. This frequency dependence can be modeled by adding a small phase angle, < / > , to the gyration conductances [210]. The conductance matrix then becomes 0 ~ g 2e j< h .jfo (25) 35 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The resulting input impedance of a capacitively-terminated gyrator with gyration conductances described by (25) is Z in(j<o) = ^ e - J^ ) . (26) 8 1 8 2 For small phase shifts, the exponential in (26) may be replaced by the first two terms of its Taylor series given by 0 0 0 0 2 A+1 = V (_i)* J L _ + y V (_ i)* -2 .------ (27) to (2 k)\ J t (2 k + 1)! which produces an impedance of (28) 8 1 8 2 8 1 8 2 It can be seen from (28) that a synthetic inductor using a gyrator with frequency- dependent gyration conductances has an input impedance consisting of the same inductance value given in (18) for an ideal gyrator, in addition to a series resistance of value (29) 8 1 8 2 The series resistance o f (29) produces a finite Q of the resulting synthetic inductor and is given in (30). 36 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. (30) It can be seen from (29) and (30) that minimizing the phase shifts will minimize the series resistance, and maximize Q. Note that a negative effective phase shift ( < f> i + fa) of the gyration conductances yields a negative series resistance. If this negative resistance is greater than the positive series resistance caused by non-zero output conductances (21), Q will become negative and the circuit will be unstable. For a range of frequencies, a negative resistance in (29) can be designed to approximately cancel the positive series resistance caused by non-zero output conductance. Doing so requires that (31) be satisfied. 3.5.4 Passive Realizations of Gyrators Although Tellegen described detailed properties of the gyrator in his original paper, he did not offer practical implementations. The first realizations o f gyrators were accomplished in the early 1950s and were based on passive topologies using the Ferromagetic Faraday Effect which makes use of the Faraday rotation of ferrite placed in a waveguide [213-215]. Other passive implementations included gas-filled waveguides [216], a ferromagnetic body of coils [217], and lossy Hall generators based on the Hall Effect [218]. These implementations proved that gyrators could in fact be § 2 2 ~ + ^ 2) (31) 37 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. realized, but they were somewhat impractical and could not easily be connected to other electronic circuit elements. 3.5.5 Active Realizations of Gyrators and Gyrator-Based Inductances While theoretical studies o f gyrators and their uses in network synthesis continued through the 1970s [219-227], other researchers found ways to implement active gyrators using transistors and other circuit components. 3.5.5.1 Single-Transistor Gyrators Shekel described the first transistor-realizable gyrators in 1953 [228] and 1954 [229], by using the nonreciprocal nature of a transistor to implement the nonreciprocal property of a gyrator. He discovered that a gyrator consisting o f only a single transistor has unwanted non-zero principal diagonal terms in its conductance matrix, and proposed to reduce them by adding a negative conductance to each port of the gyrator (as explained in Section 3.5.2). Unfortunately, this results in difficult matching problems in which the added negative conductances must match the g n and g 22 values extremely closely. Other gyrators used similar designs in the 1960s and 1970s [230- 234], but suffered from the same limitations. To demonstrate this matching difficulty, refer again to Qm ax given in (23) and for simplicity let the gyration conductances be equal where gi = g 2 = G, and let the input and output conductances be equal where g n = g 22 = g- Qmax. can then be shown to be 38 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. It can be seen from (32) that for high Q, the input and output conductances, g, must be much smaller than the gyration conductances, G. For an uncompensated gyrator with g = G, Qm a > ( is only l A. To design for a Q of 50, g must equal G/100, and the negative conductances added for loss compensation must therefore match the input and output conductances to within 1%. This tolerance can be difficult to achieve, resulting in circuits that are very sensitive to element variations [210]. 3.5.5.2 Gyrators Using Negative Impedance Converters Similar matching problems exist for other gyrator implementations, including those based on negative impedance converters (NICs) introduced by Merrill in 1951 [235]. The symbol for an ideal NIC is shown in Fig. 11, which delineates the positive senses of the input and output voltages, Vi, and V2, respectively, and the input and output currents, //, and I2, respectively [236]. NIC Fig. 11. Symbolic Representation of an Ideal Negative Impedance Converter (NIC). 39 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The terminal volt-ampere characteristics of an ideal current-inversion NIC are given by " V '0 1" 7 . 1 0 J2. (33) and those of an ideal voltage-inversion NIC are given by ' V '0 - 1 " > r / a . - 1 0 h . (34) In fact, an ideal NIC can be implemented with many different values of the off- diagonal elements in the hybrid-G matrices of (33) and (34), as long as their product is unity. Through the 1960s, many papers were published that discussed the properties and implementations of negative resistances and NICs [235-254], but the purpose of a NIC is the same regardless of implementation - to create an impedance that is the negative of a reference impedance. Using (33) as an example, notice that /; = h and Vj = V2. Thus, the current-inversion NIC reverses the direction of h at the input port yet preserves the polarity of V2. If the ideal NIC in Fig. 11 is terminated at its output port in an impedance, Zi, as shown in Fig. 12, the driving-point input impedance, Z,„, is simply the negative of Zi as shown in (35). v Z in = 7 - = ■ * 1 (35) 40 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. z. U NIC Fig. 12. Ideal NIC Terminated at Its Output Port in Impedance, ZL. Like the single-transistor gyrator, the nonreciprocal nature of an appropriately loaded NIC can be used to make a gyrator. From the 1960s through the 1980s, several NIC- based gyrators were described using different topologies [157, 255-258], and an example of one such ideal NIC-based gyrator is given in Fig. 13 [210]. Z. (s) mx ' I, R, R3 I2 • > ^ A A t t j V W - * ► - + V, Fig. 13. An Ideal NIC-Based Gyrator. The “T” network formed by the three resistors, Ri, -R2, and R 3 has an impedance matrix described by — R 2 — ^2 - r 2 r 3 - r 2 (36) From Fig. 13 and from (33) it can be seen that the NIC reverses the current, I2, through the “T” network, which multiplies the elements in the right-hand column of (36) by -1, yielding the modified impedance matrix of 41 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. R{ R 2 - R , R 2 r 2 - R 3 (37) For the circuit in Fig. 13 to behave as a gyrator, the elements on the principal diagonal in (37) must be zero, forcing Rj = R 2 = R 3. Like the single transistor gyrator described in the preceding section, high Q can only be obtained if these resistances match each other very closely, making them sensitive to element variations and limiting their use [259]. 3.5.5.3 Gyrators Using Operational Amplifiers In an effort to find an improved gyrator building block, and one that could be easily and inexpensively implemented, several gyrator implementations were reported in the 1960s and 1970s that were based on operational amplifiers (op-amps). These can be classified mainly into two categories, 3-terminal gyrators in which both ports are grounded [260-265], and 4-terminal gyrators in which the output port is floating [266- 277]. In the 3-terminal circuits, non-zero conductances, g u and g 22, can be reduced to zero by cancellation schemes using negative resistances [259]. As explained in the preceding two sections, however, these lossless gyrators have large sensitivities to element variations, especially for high-Q designs. In 4-terminal op-amp gyrators, however, no negative resistances are used to cancel specific resistance values, so sensitivities can be low. In some cases, negative resistances can still be used [268], but the value of the negative resistance is not critical 42 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. (the only requirement is that it be negative), so no strict matching requirements exist. In other cases [267], g u and g 22 are reduced by closely matching voltages, not resistances. The voltages in question are applied to the two inputs of a differential op- amp and rely on the large op-amp gain to make the inputs nearly equal. Again, no specific matching is required, but the op-amp gain must remain large over all operational frequencies. Most 4-terminal gyrators still have large g u and g 22, however, and can therefore be regarded as lossy or nonideal. Unfortunately, these nonideal 4-terminal gyrators have several drawbacks. First, non-zero g u and g 22 will reduce Q, as predicted by (23) and (32). Second, many 4-terminal op-amp gyrators have only conditional stability, and may lock in either an unstable mode or a latch-up condition during power-up [259], In addition, many op-amp gyrators require capacitors at both ports to maintain stability. This is not an obstacle for some filters and oscillators (in which capacitors would be placed at both ports by default), but for pure inductance simulation, no external capacitance is allowed at the input port [274]. And finally, compared to other amplifier topologies, op-amps in general have inferior frequency responses. Despite these drawbacks, gyrators using op-amps during the 1960s and 1970s had a large advantage over other amplifier types because they could be easily produced using inexpensive discrete op-amp chips, while gyrators using other amplifier types required expensive full custom integration. Now that complete systems are being cost-effectively 43 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. integrated in digital CMOS processes, however, this one advantage of op-amp gyrators no longer exists, and their drawbacks are still numerous. 3.5.5.4 Gyrators Using Transconductance Amplifiers A review o f the preceding three sections indicates that high-ig gyrator-based inductances can be implemented only by avoiding the large input and output conductances of uncompensated lossy gyrators, and by escaping the matching difficulties o f gyrators that have been made lossless with negative resistance compensation. A preferred gyrator building block would therefore make negligible contributions to g n and g 22, yet deliver relatively large gyration conductances, g] and g 2. These characteristics can be found in gyrators implemented with ideal transconductors (voltage-controlled current sources). Notice that the ideal gyrator conductance matrix o f (16) can be decomposed as 0 8\ 'o 8i 0 O ' + _ 8 2 0 0 0 _ 8 2 0 where the two component matrices represent transconductors of opposite polarity and direction [210]. Fig. 14 shows how two ideal transconductors (with zero input and output conductances) can be connected in parallel, yet in opposite directions and with opposite polarity, to implement (38). 44 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 14. Transconductor Implementation of an Ideal Gyrator. If the gyrator in Fig. 14 is terminated at its output port in a capacitance, C, as shown in Fig. 15, the driving-point input impedance, Zin(s), becomes Vx{s) _ 1 _ sC W g ,g 2Z , capacitor g\gi (39) which is identical to the input impedance of the ideal gyrator depicted in Fig. 7 and described by (17). Z (s) m ' z S iV2Q ) C % Vj V 2 — C Fig. 15. Ideal Transconductor Gyrator Terminated at Its Output Port in a Capacitance, C. It is easily seen from (39) how the gyrator in Fig. 15 simulates an ideal inductor with an inductance given by (18). Because the gyrator modeled in Fig. 15 is ideal and therefore lossless, the Q o f the synthesized inductor is infinitely large. Gyrators have been implemented with transconductors since the 1950s. In 1955, Vallese suggested that lossless gyrators could be implemented with current sources 45 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. [278], and in 1957, Sharpe proposed the decomposition of the conductance matrix as shown in (38) and described a gyrator implementation using two voltage-controlled current sources (referred to as “transactors”) in parallel [279-280]. These early designs were based on vacuum tubes, but by the mid 1960s several papers offered discrete transistor implementations [281-291], many of which were used for inductance simulation. More analyses of gyrator realizations, gyrator-based inductors, and gyrator-inductor filters were completed through the 1970s [292-330] and beyond [331- 340], while discrete implementations of transconductor gyrators continued as well [341-354]. The first integrated gyrator using transconductors was described by Chua and Newcomb in 1967 [355], but a complete gyrator-based inductor integrated in a standard Si process (including the integration o f the gyration capacitance) wasn’t reported until 1978 [356, 357]. The gyrator described in [356] boasted a reasonable maximum Q of 20, but this maximum occurred at only 6 MHz. Thus, the limited frequency response of Si processes in the 1980s and 1990s forced high-frequency designs to take advantage of faster GaAs processes [358-370]. As channel lengths in Si CMOS processes reached submicron levels during the 1990s, integrated gyrator inductor designs slowly shifted from bipolar processes [205, 371-377] to BiCMOS processes [378-386], and finally to standard CMOS processes [377, 387-423]. 46 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. During this same time period in the 1990s, the implementation of the transconductors themselves also shifted. The first circuits [205, 361, 362, 369, 373-375, 377-379, 383, 387-390, 405, 424] used transconductors that consisted of several transistors, such as differential pairs with active loads. These inductor designs also used a relatively large gyration capacitance, such that the value of the capacitance was much larger than the parasitic capacitors of the transistors. The value of the simulated inductance could then be well controlled, according to (18). For low-voltage and low-power operation, however, the complex transconductors used in these traditional designs required too much headroom and consumed too much power. Thus, complex transconductors are now often replaced with much more simple topologies, many comprised of only a single transistor [364-366, 370, 414]. Gyrators using these simple transconductors are often referred to as “transistorized gyrators.” As operating frequencies push into the gigahertz range and closer to the unity-gain frequency, /r, of the transistors, the gyration capacitance can limit the frequency of maximum Q according to (24). As a result, many inductor designs eliminate the external gyration capacitance altogether, and rely solely on the intrinsic capacitances of the transistors themselves for impedance inversion [384, 385, 392, 394-396, 409, 410, 423], Although these intrinsic capacitances are not necessarily located across the output port, but rather between internal nodes, the resulting inductance still approximates that o f a traditional capacitively-terminated gyrator. Other transistorized 47 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. designs using resistive feedback and other topologies appear even less like classical gyrators, but their resulting design equations are often similar to those o f gyrator-based inductors [425-455]. The recent trend in SoC integrated circuits has been to increase operational frequencies while using lower voltages and consuming less power. To comply with this trend, most gyrator-based inductors published since 2000 use both transistorized gyrators and intrinsic gyration capacitances [372, 376, 380, 382, 386, 391, 393, 397-404, 406-408, 411-413, 415-422]. The advantages of such topologies are many, including low voltage requirements, low power consumption, high operating frequencies, and very small chip area usage. Their limitations, however, are also numerous, including 1) the gyrator must be grounded; 2) the gyrator performance is sensitive to fabrication variations; 3) tuning circuits are sometimes required to tune the operating point; and perhaps most importantly, 4) transconductors implemented with a single transistor are not the ideal amplifiers required to achieve the ideal conductance matrix of (38). Their non-zero output conductance contributes directly to non-zero terms on the principal diagonal, g u and g 22- Thus, although gyrator-based inductors implemented with single-transistor transconductors can operate at relatively high frequencies, their non zero output conductances will limit the Q of the resulting gyrator-based inductor. Many active inductance topologies have been suggested that improve some of the drawbacks mentioned above, but due to the many trade-offs inherent to active inductor 48 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. design, other limitations emerge. For example, adding transistors to a simple design may improve Q, but at the expense of increased voltage requirements, power consumption, noise, and the potential for instability. As 0 is made larger, either intentionally to satisfy design specifications or unintentionally by increased negative phase error, the potential for instability of the active inductor is greater. Even if outright instability is avoided, the frequency response o f the inductance value can vary wildly from the flat response predicted by ideal amplifiers. Thus, a well-designed high-frequency active inductor requires not only a clever topology that satisfies its voltage, power, noise, and dynamic range requirements, it must also produce a high 0 and an inductance value that is nearly independent of frequency over the operational frequency range o f the circuit in which the inductor is embedded. 3.6 Conclusions Planar spirals are commonly used to implement inductors on-chip, but these structures are not tunable, are limited by low 0 , have large die areas, and are difficult to parameterize reliably because their inductance values are mathematically intricate functions of geometry and the electrical properties o f the substrate on which they are fabricated, ^-enhancement circuitry may be added to increase Q to more useful levels, but the additional circuitry required of 0-enhancement compensation schemes increases power dissipation, degrades noise figure, and limits dynamic range. Compensation circuitry is also sensitive to on-chip parasitics, requiring automatic on- chip tuning mechanisms that further increase power and degrade frequency response. 49 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Other passive inductance implementations include out-of-plane micro-inductors and bond wire inductors. However, like passive spirals, these inductors have significant drawbacks including lack of tunability and large die area. In addition, micro-inductors require very specialized processing steps, and the yield, tolerance, and repeatability of bond wire inductors cannot be guaranteed by manufacturers for volume production. To satisfy the performance goals of tunability, high Q, small die area, and the use of a standard CMOS process, the limitations of passive inductors eliminate them from further consideration. Compared to passive inductors, active realizations consume more power, have higher noise and less dynamic range, but consume much less die area, are capable of producing extremely high Qs, and have inductance values that can be easily tuned. O f the many active topologies available, those based on the gyrator and implemented with transconductance amplifiers are the most popular and perform the best at high frequencies. These inductors are therefore considered to have the most promising topology to satisfy the performance specifications outlined in Section 2.3. Active gyrators can suffer from instability, however, especially for designs that require high Q and high frequency operation. Thus, a detailed stability analysis of a gyrator- based active inductor using transconductance amplifiers needs to be completed to understand inherent design trade-offs between Q, stability, and the frequency response of the synthesized inductance. 50 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 4: Analysis of a Gyrator Inductor Using Transconductance Amplifiers It is concluded in Chapter 3 that integrated inductors offering the best overall performance are active topologies implemented with transconductor-based gyrators. However, also noted in Chapter 3 is the potential instability of active inductors that require both high Q and high operating frequencies. Strategies must therefore be formulated to analyze the stability of the simulated inductance and offer insightful circuit modifications to ensure stability over the frequency range of interest. To guarantee accuracy of the stability analyses, the model used for the transconductors should be as realistic as possible. To this end, Section 4.1 offers a general transconductor model that can be used for both transistorized and more complex implementations. Section 4.2 uses the general model in a detailed stability analysis to extract and analyze the circuit damping factor and to reveal the relative stability of the synthesized inductor. Section 4.3 uses the results of Section 4.2 to formulate design constraints to mitigate the effects of parasitics and to ensure optimal frequency response and stability. Section 4.4 provides a design example using the constraints, and Section 4.5 summarizes the important concepts uncovered in this analysis and offers suggestions for successful active inductor designs that are tunable, stable, and offer high Q with inductance values that are nearly independent of frequency over the frequency range of interest. 51 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4.1 A General Transconductor Model Consider again the ideal gyrator conductance matrix decomposition of (38), repeated in (40) below. 0 g i -g i 0 0 g i 0 0 + 0 0 ~ & 2 0 (40) Expression (40) demonstrates that an ideal gyrator may be implemented by the parallel connection of two ideal transconductors of opposite polarity and direction. The symbol of such an ideal transconductor is given in Fig. 16, in which the input voltage, Vj, is differential, and the output voltage, V2, is referenced to ground. Fig. 16 shows that the ideal transconductor is simply an ideal voltage-controlled current source. Fig. 16. Symbolic and Equivalent Circuit Representations of an Ideal Transconductor. A synthesized inductance using a capacitively-terminated gyrator formed from (40) and using the symbol of Fig. 16 is shown in Fig. 17. 52 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. ■ C Fig. 17. Ideal Transconductor Realization of a Capacitively- Terminated Gyrator. The equivalent circuit representation of Fig. 17 is shown in Fig. 18, and the resulting input impedance is given in (41). Z M = F ,(s )= 1 _ sC (5) S lS lZ c a p a c ito r S l S l (41) ZJ S ) • W g ,v 2O Q !)g2v , v 2 Fig. 18. Equivalent Circuit Representation of the Ideal Transconductor Gyrator Depicted in Fig. 17. Note that the ideal input impedance of (41) is purely inductive, with an effective inductance, Le, equal to C L = g l§2 (42) 53 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Since Le is directly controlled by the transconductances of each amplifier, Le can be electronically tuned by adjusting gi and/or g 2 through the application of externally applied bias voltage or current (not shown in the diagram). This flexibility is far superior to the inductances produced by spirals and other passive implementations that lack tunability. As established in Section 3.5.5.4, the model of a realistic transconductor is not the lossless and memoryless structure depicted in Fig. 16. A more realistic model is needed. Most of the recently designed gyrator-based inductances use transistorized designs, so one may be tempted to use a simplified small-signal model of a MOS transistor. Many useful designs still use more complex topologies, however, especially those requiring high Q, so a more general model will be used in the forthcoming stability analysis. This model can be used for multi-stage transconductors like operational transconductance amplifiers (OTAs), and it can be simplified as necessary for transistorized designs. The high-frequency general transconductor model is given in Fig. 19 [135]. Fig. 19. High-Frequency General Transconductor Model Used for Stability Analysis. 54 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Many simplified transconductor models include only the ideal transconductance, gm , and the output resistance, R0. Although R 0 is the parasitic element that affects Q the greatest at low frequencies (with values in the range o f at least the high tens to several hundreds of thousands of ohms), more parasitic elements need to be included in the model for accurate stability analyses. The input resistance, is usually much larger than R0, but is included in the general model because even very large input resistance may have a measurable effect on the frequency response of the synthesized inductor. In submicron MOS technology circuits, the input capacitance, C„ derives largely from gate-source and gate-source overlap capacitances and has a value typically in the range of a few tens to the low hundreds of femptofarads. The output capacitance, C0, which is usually dominant in common-source MOS transistor circuit architectures, is determined primarily by drain-substrate capacitance and is generally of the order of the high tens to the few hundreds o f femptofarads. Finally, C/represents the net feedback capacitance between the input and output ports of the transconductor. Even for values of only a few femptofarads, as is the case with multistage OTAs, C/ establishes a right- half-plane zero that degrades phase margin. Larger values of C/ can cause significant underdamping or even outright instability in gyrators and other feedback networks [135]. 4.2 Analysis of a Gyrator-Based Inductor Using the General Transconductor Model The goal o f this section is to derive design equations that produce stable inductances with high Qs and inductance values that are nearly independent of frequency over the 55 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. frequency range of interest. To accomplish this, the characteristic equation of the input impedance of a complete gyrator-based active inductor using the general transconductor model is found, and the damping factor is extracted and analyzed to reveal the relative stability of the synthesized inductor. Replacing each ideal transconductor shown in the capacitively-terminated gyrator of Fig. 17 with the general model given in Fig. 19 results in the small-signal high-frequency electrical model for the complete synthetic inductor given in Fig. 20. K 7 'C 7 Fig. 20. Complete Gyrator-Based Active Inductor Using the General Transconductor Model Given in Fig. 19. It is evident from Fig. 20 that the parallel connection of the two transconductors causes their input and output parasitic elements to be similarly connected in parallel. Thus, the complete inductor of Fig. 20 can be simplified to that of Fig. 21, where C, = C„ + C„,, (43) 56 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. c = c ' - ' i l + C o 2 ’ (44) CF — Cj j + Cj- 2, (45) R i ~ R a " R o t , (46) R 0 ~ R i\ HRo2> (47) and represents the parallel connection of the two resistors in question. Z. (s) in' / U R ,< s f Q SS.O Roi co S 7 Fig. 21. Two-Port Equivalent Circuit of the Complete Gyrator-Based Active Inductor Using the General Transconductor Model. Note from (43-47) that if the transconductors in Fig. 21 are identical and no additional circuit elements are appended to either the input or output port of each transconductor, C/ = Co and Rj = R q- An analysis of Fig. 21 produces the driving-point input impedance of R„ + sL„ 1 + f S + / \ S I ® - ; { ®»J (48) where Re is the low-frequency resistance, R i „ 1 l + g lg 2RIR 0 g \g l R 0 for g ig 2R ,R 0 » 1, (49) 57 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Le is the low-frequency value of the effective input inductance, = R,R 0 (C0 + C + C ) a C0 + Cr + C & r R R > h (50) l + g ig iRi Ro § 182 (o „ is the undamped resonant frequency, and zeta, £ is the damping factor. Expressions for (o „ and C , are given in (51) and (52) below. With the additional constraint of C » (Co + C », the effective inductance in (50) collapses to the ideal effective inductance given in (42). This is expected because the complete circuit in Fig. 20 collapses to the ideal circuit in Fig. 17 for large Rj and Ro, and small Cj, Co, and Cp. Unfortunately, the complete circuit behaves less like the ideal circuit as operating frequencies increase. This can be seen from (48), which indicates an undamped resonance condition occurs at frequency, a > n , which can be shown to be co. = 1 1 q + CF(Co + C) CF + CQ + c for CF « Cj (51) The last term in the bracketed expression in the denominator on the right hand side of (51) is smaller than C/r, which is itself a small capacitance. Accordingly, (51) suggests that the inductance produced at the input port of the circuit in Fig. 21 effectively resonates with the net shunt input capacitance, C/. The amount o f resonance can be 58 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. controlled by changing the damping of the circuit, and the amount of damping can be measured by analyzing Q . For C , 1, the frequency response of Zjn(s^ is said to be overdamped and has poles that are real and unequal. For £= 1, Zin(s) is critically damped and has poles that are real and equal. In both cases, the poles lie in the left half of the complex frequency plane and Zi„(s) is unconditionally stable with magnitude less than or equal to unity. For 0 < C , < 1, Zin(s) is underdamped and has left-half-plane poles that are complex conjugates. For £= 0, the complex conjugate poles lie on the jco axis and Zin(s) is undamped and oscillates at frequency (O n predicted by (51). Finally, for C , < 0 the system is unstable with poles in the right half plane. Thus, C , can be used to assess the relative stability of Zin(s). The damping factor, £ may be derived from the coefficient o f the s term in (48) which is shown in (52) below. _ 1 ___Cj + C p______^ CF(g 2 —g i) co„Le Rj R0 (C0 +CF + C ) C0 +CF +C Note from (52) that for g 2 < gi and sufficiently large Cp, the damping factor can become negative and result in network instability. Fortunately, g 2 > gi precludes right- half-plane poles and therefore ensures asymptotically stable circuit responses. For g 2 ~ gi and large Ro, (52) delivers the approximate damping factor given in (53). 59 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. As expected, a progressively smaller input resistance, Rj, which appears directly in shunt with the resonant circuit composed of the effective inductance, L e, and the shunt input capacitance, C/, serves to increase the damping factor. The damping factor can therefore be made large enough to circumvent potential oscillations. As indicated earlier, one of the goals of this work is to produce inductances with high Qs and inductance values that are nearly independent of frequency. In addition to describing the relative stability of the synthesized inductor, the damping factor in (52) and (53) establishes the degree to which the generated series resistance, Re, and port inductance, Le, are rendered nominally constant over the frequency range of interest. To clarify this assertion, rewrite (48) in the form An examination o f (54) reveals that the equivalent resistance and inductance of the synthesized inductor will both be independent of frequency for F(s) = 1. Letting s = jco, it can be seen from (55) that F(jco) will equal unity at zero frequency. At higher (54) where (55) 60 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. frequencies, both the magnitude of F(ja>) and the bandwidth of \F(jco)\ are affected by £ The magnitude o f F(ja>) is given in (56) and the 3-dB bandwidth of \F(jco)\ is provided in (57) [456]. (56) (57) From (56), it can be shown that \F(jco)\ at DC is unity, and at c a n is (58) It may be tempting to let C , = 0.5 to force \F(jco)\ = 1 at co „ , but an analysis of (56) reveals that \F(jco)\ peaks above unity between 0 < cq < (o „ for Q less than the inverse of root 2. Although C , greater than the inverse of root 2 maintains \F(ja>)\ < 1, (57) indicates that C , greater than the inverse of root 2 decreases the 3-dB bandwidth of \F (j< x> )\ to less than a > n . The optimum design constraint appears to be Q equal to the inverse of root 2, shown in (59), which imposes a maximally-flat constraint on \F(jeo)\ such that C 0n = ai3d B - That is, \F(ja>)\ displays no peaking above unity and is constant to within three decibels of unity for all signal frequencies in the closed interval, 0 < co < Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. (O n [135]. 61 Using (59) and the expression for Q in (53), Ri can be shown to be (60) which is a reasonable constraint for ensuring nominally constant resistance and inductance over the widest possible passband. Imposing (59) ensures that \F(jco)\ is monotonic with \F(fco)\ = 1 at zero frequency and \F(j(o)\ = 0.707 at c o n, with the 3-dB bandwidth of \F(ja>)\ equal to (O n . 4.3 Design Constraints and Guidelines To formulate guidelines appropriate to a meaningful design of a gyrator-based active inductor, it is useful to introduce the frequency normalization, y, such that y = - = ^ r - (61) fn Under steady-state sinusoidal excitation conditions, (48) becomes Z,„ (jy) = Re[Z,„ 0 » ] + j Im [Zin ( ;» ] , (62) where ( l - y 2)2 + (24* . y f ( l - y 2)2 + ( 2 ^ ) 2 in which the approximation replaces Le with its approximation from (53), and 62 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. (64) in which the approximation also replaces C , in the numerator with its approximation from (53). The input impedance, Zin(jy), is inductive only for Im[Zin(jy)] > 0, but (64) indicates that a range o f frequencies exists for which Zin(jy) is actually capacitive with Im[Zj„(jy)\ < 0. Therefore, a normalized crossover frequency, y co, exists for which ZinOyco) is purely resistive with lm \Zin(jyC 0 )] = 0. This normalized crossover frequency is where the approximation reflects the fact that from (49), Re « Ri. In short, the electrical nature of the driving-point input impedance changes from inductive to capacitive at the resonant frequency of the gyrator circuit. Since the objective at hand is the realization o f inductance, it follows from the above discussions that the utility of the structure proposed in Fig. 20 is limited to signal frequencies that are smaller than the circuit resonance predicted by (51). Notice from (63) that unconditional circuit stability, in the sense o f a positive real input impedance, is assured for Re[Zin(jy)] > 0. The second term in the numerator of (63) is (65) 63 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. non-negative for all values o f C , andy, and the first term is positive fory < 1. Thus, the real component of the input impedance will remain positive for signal frequencies in the range 0 < a>< c o „ , the same range for which the input impedance is inductive. Using (63) and (64), the quality factor, Q(y), o f the actively synthesized inductor is given approximately by ( ° nLJ Q {y )= f f r r f ^ i— — -■ (66> [ ' « Oj7 ) ] ( l - y2 K + (2C y)2 R i Over the normalized frequency range, y < 1, where the input impedance is inductive and stable, (66) can be approximated as 2 0 ) » ----------------- . (67) R ,+ ( 2 ( y ? R , which displays a maximum at ® m ax f T i a x V S£o\ y m a x ~ ------ - —7 - 35------— • (68) co„ /„ ( o L , n J n n e Substituting (49) into (68) reveals that the frequency at which Q is maximized is f ~ _ L _ R i = 1 £ i ^ A (69) ■ '" " '2 x L , y g ,g 2R 0 24 C 0 + CF + C ) i R0 Replacing y in (67) with ym ax of (68) shows that the value of the maximum quality factor, g m ax , is G m ax = Q ^ y max ) * | • ( 7 0 ) 64 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. To review briefly, the shunt input resistance, Ri, is selected in (60) to establish a damping factor corresponding to maximally-flat inductance over the frequency passband. According to (70), the shunt output resistance, Ro, therefore determines the maximum Q of the synthesized inductor. Obviously, the largest possible value of Q is dictated by the ability to realize a transconductor characterized by very large shunt output resistance. The value of Qmm is therefore limited by the degree to which the output port of the transconductor emulates an ideal current source. The ratio,/nax/j2max, in (71) is a useful design figure of merit for it provides the value of the shunt output resistance that is necessary to produce a desired inductance value given the transconductances of the amplifiers. This ratio also helps to determine the feasibility of realizing the desired inductance specifications. f 1 i (71) Q m ax ^ L e S \ § 2 R 0 Solving (71) for Ro yields the additional useful design equation given in (72). Ro max 1 ^ e S l S l (72) For example, let the transconductors in Fig. 20 have g i= g 2 ~ 2 mS and let the desired inductance, Le, be 15 nH. If this inductance realization is to deliver a maximum quality factor, Qmax, o f 100 at frequency,/m ax = 400 MHz, (72) stipulates that Ro must be ~ 1.3 65 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. MQ. Such an output resistance is unrealistically large within the constraints imposed by low power transconductor design in state-of-the-art deep submicron CMOS technology. A more reasonable resistance value is Ro = 100 KQ. Then for Le - 15 nH and g i= g 2 = 2 m S ,fm a x/Qm a x = 53.05 MHz. Choosing Qm a x = 15 produces/m ax = 796 MHz according to (71), and assuming/nax < fn• Assuming Ro= 100 KQ, (69) yields Ri = 2.25 KQ, which requires that the input port of the gyrator-based active inductor be shunted by an appropriate resistance. Unfortunately, it is unlikely that this value of Rj equals that suggested by (60), which guarantees maximal inductance flatness over the circuit passband. Therefore, the damping factor in (53) corresponding to the net effective shunt input resistance must be checked to see if design compromises are mandated. If the damping factor is much larger than 1/V2, the magnitude of Le will decrease greatly over the frequency range 0 < / < f„. Conversely, if the damping factor is much smaller than 1/V2, severe peaking in the magnitude of Le may lead to instability. 4.4 Design Example To investigate the preceding analysis and resulting design constraints more thoroughly, a complete active inductor will be designed. For the following example, assume two identical transconductors having g i= g2 - 5 mS, C,7 = C,2 : 5 fF, C0i = Co2 = 20 fF, Cfi = Cp — 3 fF, Ru = Rq = 5 MQ, and R0i = R o2 =100 KQ are available. Let the specifications entail the realization of a 25 nH 66 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. inductor characterized by a Q of at least 15 at a frequency of 300 MHz. A plausible design procedure follows. 1. From (43-45), Q = 25 fF, Co = 25 fF, and C p = 6 fF. Using (46-47), Rj - Ro = 98.04 KQ. 2. Solving the approximation in (50) for the output port capacitance, C, yields (73). U ~ Leg \g 2 ~ Co ~ CF (73) Using the values of Co and C p from step 1, C may be calculated to be C = 594 fF. Because this capacitance value is about 19 times larger than the capacitance sum, Co + Up, the performance of the active inductor will be rendered nominally insensitive to energy storage uncertainties in the utilized transconductors. The disadvantage o f adding such a large capacitance to the circuit is the reduction of /max according to (69). 3. Recalling (51), the resonant frequency of the network is f„ = 5.72 GHz, which represents the upper bound of stable operating frequencies, and the upper bound for which the frequency response of the input port impedance is inductive. 4. From (60), the shunt input port resistance required for a maximally-flat inductance response is Ri = 635.6 Q. Since the default value of Rj for the chosen 67 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. transconductors is Ri = 98.04 KQ, a resistance of about 640 Q must be appended in parallel with the input port to reduce the input resistance to R; = 635.6 Q. 5. With Rj chosen for maximal flatness, the only remaining design parameter value to select is the output port shunt resistance, Ro. Note that Ro controls / m ax in (69) and Q m ax in (70), and selecting a single value for Ro that satisfies specifications for both /max and Qmax may not be possible. For these reasons, compromises in the design specifications may be necessary. To illustrate the possible design compromises revealed in step 5 above, (69) and (70) are solved for Ro in (74) and (75), respectively. R0 ~ --------- —-------- 7 (74) 4 Q 2 (75) g l § 2 R I For/nax = 300 MHz and maximum flatness ensured by Ri = 635.6 Q, Ro may be calculated from (74) to be Ro = 11.45 KQ. However, for Qm a x = 1 5 and the same Ri - 635.6 Q, Ro may be calculated from (75) to be Ro = 56.64 KQ. Clearly, the desired inductor specifications o f /nax = 300 MHz and Qm a x > 15 cannot be satisfied simultaneously while maintaining a maximally-flat frequency response. If maximal flatness and/nax = 300 MHz are absolute requirements, then Ro must be chosen from (74) to be Ro = 11.45 KQ and (70) gives a corresponding Qm a x of only 6.74. If some 68 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. peaking in the frequency response can be tolerated, a doubling of both Ri and Ro doubles Qm a x to just under the desired value of 15 without altering f m a x - The engineering price implicit to this alteration is diminished damping factor as predicted by (53). As discussed earlier, a damping factor smaller than 1/V2 degrades relative stability and incurs non-maximal flatness in the inductance frequency response. On the other hand, if maximal flatness and Qm a x > 15 are absolute requirements, then Ro must be chosen from (75) to be Ro - 56.64 KQ and (69) indicates that f m a x will only be/nax = 134.9 MHz. To move forward in the design, a compromise is needed. The compromise adopted must reflect consideration of all relevant circuit and system operating specifications. In this example, the strategy is to select Ro = 35 KQ, which is approximately the arithmetic mean of the two calculated output resistance extremes. Since the default value o f Ro for the chosen transconductors is Ro = 98.04 KQ, a resistance of 54.4 KQ must be appended in parallel with the output port to reduce the output resistance to Ro = 35 KQ. This resistance value yields/nax = 171.6 MHz from (69) and Qm ax - 11.79 from (70). The low-frequency resistance, Re, may be calculated from (49) to be Re = 1.14 Q. The complete active inductor is shown in Fig. 22, in which the general transconductor model of Fig. 19 is used for each OTA, and the values of the parameters shown in Fig. 19 are given in the design example above. 69 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 22. Gyrator Active Inductor Realization for the Design Example in Section 4.4. Simulation results of the complete circuit in Fig. 22 using Penzar Development TopSPICE™ (hereafter referred to simply as “SPICE”) are provided in Figs. 23-25. As the following overview confirms, excellent corroboration between the simulated and analytically deduced results is obtained. 70 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 23 displays the frequency response of the inductance for the active inductor in Fig. 22. The inductance has been calculated as the frequency derivative of the imaginary component o f the driving-point input impedance, Zin(f(o). The simulated low- frequency inductance is 24.91 nH, which is maintained to within 15% for signal frequencies through 2.1 GHz. 106 107 108 109 1010 F req u en cy (H z) Fig. 23. Simulated Frequency Response of the Inductance for the Gyrator in Fig. 22. The Inductance Value at Low Signal Frequencies is 24.91 nH and is Maintained to Within 15% of this Value Through 2.1 GHz. 71 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 24 depicts the frequency responses of both the real and imaginary components of the driving-point input impedance for the active inductor of Fig. 22. The simulated low-frequency resistance is 1.14 Q, and remains under 50 Q for signal frequencies through 1.12 GHz. The real part of the input impedance shows resonance at 5.75 GHz, while its imaginary counterpart is zero at 5.72 GHz. 800 I 600 -s; ^ 400 s; & 200 Real Part Imaginary Part ,8 ,9 10 ,6 ,7 10 10 10' F req u en cy (H z) Fig. 24. Simulated Frequency Response of the Real and Imaginary Components of the Driving-Point Input Impedance for the Gyrator in Fig. 22. At Low Signal Frequencies, the Real Part of the Impedance is 1.14 Q and Remains Less Than 50 Q for Frequencies Through 1.12 GHz. 72 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 25 provides the frequency response of Q for the active inductor of Fig. 22. A maximum Q o f 11.77 is observed at a frequency of 170.6 MHz. 12.5 Q = 11-77 ^m ax **•••. 7.5 5.0 / a n = 170.6 MHz 2.5 .6 7 .8 ,9 10 F req u en cy (H z) Fig. 25. The Simulated Quality Factor of the Inductance for the Gyrator in Fig. 22. The Maximum Q of 11.77 Occurs at a Frequency of 170.6 MHz. 4.5 Conclusions This work undertakes a detailed analysis of the gyrator-based inductance shown in Fig. 20. The fundamental conclusion drawn from this work is that the subject inductance network is a viable alternative to both traditional passive realizations and to non- gyrator active designs, particularly when relatively large Qs are required at high frequencies. Even though the gyrator approach to inductance synthesis comprises a viable engineering design alternative, its performance is far from the idealized behavior postulated in much o f the literature. Aside from the well-known shortfalls o f increased 73 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. power consumption, increased electrical noise, and constrained dynamic range, the gyrator approach embodies noteworthy small-signal operating constraints and issues that circuit designers must address. 1. It is essential that the two transconductors in Fig. 20 have sufficiently large transconductances. From (50) it can be seen that for a given desired inductance, Le, large transconductances imply the need for a large output port capacitance, C. In turn, large C will reduce the inductance sensitivity to parasitic transconductance capacitances. 2. Inductance values larger than the mid tens o f nanohenries are potentially counterproductive because the generated inductance effectively resonates with the parasitic capacitance of the input port. It is essential that this resonant frequency be placed outside the passband of the system in which the gyrator-based inductance is embedded. 3. From (53), the shunt input resistance, Rj, effectively sets the circuit damping factor, while (70) shows that the output resistance, Ro, controls the maximum attainable Q, and (69) shows the frequency at which this maximum Q is achieved. Very large Q demands that the output port of the transconductor closely emulate an ideal current source over the frequency range of interest. Unfortunately, larger Ro produces not only larger Q, but also smaller f m sK , the frequency at which Q is maximum. 74 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Increasing Ri can raise Q and restore / m a x to a higher frequency, but only at the expense o f decreased damping factor. Damping factors less than 0.707 give rise to diminished stability and an effective inductance that does not remain constant throughout the circuit passband. 4. It is essential that the transconductances, gi and g 2, in Fig. 20 satisfy the inequality, g2 > gi- Failure to satisfy this constraint can result in instability. 75 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 5: Evaluation and Analysis of Transistorized Gyrators It has been concluded in previous chapters that integrated inductors offering the greatest potential to satisfy the research objectives outlined in Chapter 2 are active topologies implemented with transconductor-based gyrators. The next step in satisfying the objectives is to determine the most promising transconductor topology that should be used in the final gyrator-based designs. The stability analysis performed in Chapter 4 will then be repeated for the selected gyrator to ensure stability and to provide inductance values that are nearly independent of frequency over the frequency range of interest. To minimize power consumption, noise, die area, and circuit complexity, transconductors implemented with a single transistor are considered first. As indicated in Section 3.5.5.4, these topologies are often referred to as transistorized gyrators, and are evaluated in this chapter according to their potential to produce high Qs at high frequencies, using low voltage supplies and minimal bias current. Additional transistors will be added to the initial designs only when necessary to meet performance goals. Another advantage o f transistorized gyrators over more complex topologies is that they contribute a minimal amount of capacitance to Co and Cf, maximizing / m a x in accordance with (69). To further increase no external capacitance, C, will be 76 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. added to the output port in the following analysis. Thus, the sum of intrinsic capacitances, Co and Cf, will serve as the gyration capacitance and will help establish the value of the synthesized inductance according to (50) with C = 0. An overview of eight different transistorized gyrator topologies is offered in Section 5.1, and a summary o f their attributes and shortcomings is given in Section 5.2. A stability analysis o f the preferred topology is undertaken in Section 5.3, using a similar methodology to the stability analysis performed in Chapter 4 using the general transconductor model. An equivalent circuit of the selected gyrator is derived in Section 5.4, and shown to be identical to that of a planar spiral inductor. Section 5.5 uses the chosen inductor in a design example, and Section 5.6 examines the accuracy of the results. Finally, Section 5.7 reveals the fundamental limitations from device physics that restrict the maximum attainable Q of transistorized gyrators, and suggests a circuit modification to improve Q enough to satisfy the research objectives. 5.1 Transistorized Gyrator Topologies Gyrators constructed with single-transistor transconductance amplifiers must have one transistor with a positive transconductance and the other transistor with a negative transconductance, according to the conductance matrix of (38). Because common- source amplifier stages produce negative transconductances, and both common-gate and common-drain stages produce positive transconductances, transistorized gyrators can be implemented with both common-source/common-drain and common- 77 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. gate/common-source topologies. Using NMOS and/or PMOS transistors, a total of eight gyrator implementations are possible and are described below [421]. 5.1.1 Gyrator A: Common-Source (NMOS)/Common-Drain (NMOS) The first transistorized gyrator to be analyzed is shown in Fig. 26, and is comprised of two NMOS transistors connected in a common-source/common-drain configuration. In this topology, Mi and M 2 form back-to-back transconductors while the gyration capacitance is implemented by the sum of the intrinsic output and feedback capacitances. In this case, the output capacitance, Co, is the effective capacitance from the output node (gate of M 2) to ground, and the feedback capacitance, Cf, is the effective capacitance from the output node to the input node (source of M2). Fig. 26. Gyrator A: Common-Source (NMOS)/ Common-Drain (NMOS) Two drawbacks of this design are noted. First, two current sources are required to bias the circuit, which may not be optimal to minimize power consumption. In addition, V dd * M 2 ■ 7 M, 78 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. this design requires a larger supply voltage, Vdd, than other topologies. If current source, //, is implemented with a single transistor, then the minimum drain-source voltage required to keep this transistor in saturation may be defined as Vdsatn ^ Vgsii - Vtj]. It then follows that the minimum value of Vdd to keep My and M2 also in saturation can be found to be Vdd ^ Vgsl + V gs2 + Vdsatn- A significant benefit o f this design, however, is that only NMOS transistors are used, allowing this circuit to operate at higher frequencies than circuits using PMOS transistors. This concept is made clear by analyzing (76), and noting that the unity- gain frequency, c o t , of a MOS transistor is directly proportional to the mobility, /jq, of the majority carriers. Standard Si CMOS processes can have electron mobility 3-5 times higher than hole mobility, allowing NMOS circuits to operate at higher frequencies than similar PMOS circuits. - 3 (V - V ) 1 , , , _ ' g s t > r dsat 2 i} ~ 2 i} 5.1.2 Gyrator B: Common-Source (PMOS)/Common-Drain (PMOS) The gyrator in Fig. 26 can also be implemented with PMOS transistors as shown in Fig. 27. The PMOS configuration of Fig. 27 shares the limitations of Fig. 26 (two required current sources and non-minimal Vdd) while adding the additional drawback of an inferior frequency response due to the exclusive use o f PMOS transistors. Therefore, gyrator A should be preferred to gyrator B for high-frequency operation. 79 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. dd Z J s) Fig. 27. Gyrator B: Common-Source (PMOS)/ Common-Drain (PMOS) 5.1.3 Gyrator C: Common-Source (NMOS)/Common-Drain (PMOS) Using an NMOS common-source and a PMOS common-drain topology results in the gyrator of Fig. 28. M 1 £ dd Z J s) M, Fig. 28. Gyrator C: Common-Source (NMOS)/ Common-Drain (PMOS) Gyrator C requires that Vdd be only Vdd ^ V gsj + Vdsatn, making this design better than gyrators A and B for low-voltage operation. However, this design has its shortfalls, 80 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. too. First, as with gyrators A and B, two current sources are required. Second, and more importantly, the frequency response of this topology will be severely limited because Vd sat2 is restricted to only V dsat2 < \ Vthi\ - IKh2\ [421]. With Vthi and Vth 2 being perhaps only 50 mV apart, this topology will have a poor frequency response since cot is directly related to V dsat as shown in (76). The frequency response of gyrator C will be further hampered by the inferior frequency response of the PMOS transistor, M2. 5.1.4 Gyrator D: Common-Source (PMOS)/Common-Drain (NMOS) The gyrator of Fig. 29 is similar to that of Fig. 28, except the common-source transistor is now PMOS, and the common-drain transistor is now NMOS. M, ; , Q dd m 7 Z. (s) in' ' Fig. 29. Gyrator D: Common-Source (PMOS)/ Common-Drain (NMOS) As a result, the benefits and drawbacks of this design are very similar to those of gyrator C: Vdd is minimized with Vdd > Vgsi + Vd sa tn, but two biasing current sources are required and the frequency response will be limited by the PMOS transistor and the restricted V dsa,2 of Vd sat 2 <\Vthi\ - \Vth 2\- 81 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 5.1.5 Gyrator E: Common-Gate (NMOS)/Common-Source (NMOS) As indicated earlier, gyrators can also be formed with common-gate/common-source configurations. The NMOS version of this topology is provided in Fig. 30. An obvious advantage of gyrator E over gyrators A-D is that gyrator E requires only one current source, a benefit to low-power operation. Gyrator E is also a potentially good choice for low voltage operation, as Vdd is required to be only Vdd ^ Vgs 2 + Vdsatii- V gS2 cannot be made too small, however, as it must satisfy V gS2 > Vdsati + Vdsat2- This configuration uses no PMOS transistors, so at first glance it appears to offer high- frequency capabilities. A more detailed look, however, reveals its frequency response may have limitations. Fig. 30. Gyrator E: Common-Gate (NMOS)/ Common-Source (NMOS) The feedback loop from Vdi to V g2 confines Vg sJ to Vg sJ < Vthi + Vth2. A small Vgs/ will limit the frequency response o f Mj according to (76). This limitation is not as great as V dd 82 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. that imposed on gyrators C and D by the even smaller maximum values of V dsa t2, but it must be taken into account when biasing the circuit. In addition, Mi and M2 must also share the same current, which limits the options for biasing and tuning. 5.1.6 Gyrator F: Common-Gate (PMOS)/Common-Source (PMOS) The PMOS version of the gyrator depicted in Fig. 30 is shown in Fig. 31. This design shares the same low-power and low-voltage advantages of gyrator E, using only one current source and requiring a relatively small supply voltage of Vdd ^ V gS2 + Vdsatii- However, gyrator F has all of the biasing and frequency limitations as gyrator E, in addition to using only PMOS transistors that will further degrade the frequency performance. V •_ Bias M, Z J s) Fig. 31. Gyrator F: Common-Gate (PMOS)/ Common-Source (PMOS) 83 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 5.1.7 Gyrator G: Common-Gate (NMOS)/Common-Source (PMOS) Using an NMOS common-gate and a PMOS common-source topology results in the gyrator of Fig. 32. As with gyrators A-D, two current sources are required, rendering this design non-ideal for low power applications. The PMOS transistor, M 2, will also limit the frequency response. However, only a modest supply voltage of Vdd > V gS2 + Vdsati + Vdsatn is required, which makes this design better than gyrators A or B for low- voltage operation, but not as good as gyrators C-F. 5.1.8 Gyrator H: Common-Gate (PMOS)/Common-Source (NMOS) The gyrator of Fig. 33 is similar to that of Fig. 32, except the common-gate transistor is now PMOS, and the common-source transistor is now NMOS. V dd Fig. 32. Gyrator G: Common-Gate (NMOS)/ Common-Source (PMOS) 84 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. dd v •—I Bias I Z J s) Fig. 33. Gyrator H: Common-Gate (PMOS)/ Common-Source (NMOS) As a result, the strengths and weaknesses of this design are very similar to those of gyrator G: Vdd is modest with Vdd ^ V gS2 + Vdsati + Vdsatii, but two biasing current sources are required and the frequency response will be limited by the PMOS transistor, Mi. 5.2 Comparison of Transistorized Gyrator Topologies A small-signal analysis o f the eight gyrator topologies in Section 5.1 reveals that each gyrator produces nearly the same input impedance, Zin(s). More details of this analysis are given in Sections 5.3 and 5.4. Since each gyrator synthesizes approximately the same input impedance, the topology that should be analyzed further is the one offering the greatest potential for low-power, 85 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. low-voltage, and high-frequency operation. To facilitate the comparison of the eight transistorized gyrator designs, a summary of their performance characteristics is offered in Table 1. G yrator fr^OjieiKLy Considerations A 2 Vgs + Vdsat 2 Superior NMOS B 2 V es + Vdsat 2 Inferior PMOS C VgS " F Vdsat 2 Inferior PMOS & small Vdsat D Vgs " F Vdsat 2 Inferior PMOS & small Vdsal E Vgs ” F Vdsat 1 Superior NMOS but small Ves F Vgs " F Vdsat 1 Inferior PMOS & small Vss G VgS + 2 Vdsat 2 Inferior PMOS H Vgs+ 2 Vdsat 2 Inferior PMOS Table 1. Summary of Performance Characteristics for Transistorized Gyrators. A review of Table 1 shows that there is no gyrator topology that is clearly better than the rest in all areas of interest. Thus, trade-offs need to be made when choosing a design for implementation. Although gyrators C and D require minimal Vdd, they offer poor frequency performance because of their severely limited V dsat2 and will not be considered further. Similarly, though gyrators B and F share the benefits of A and E (respectively), B and F use PMOS transistors instead of NMOS and will not perform as well at high frequencies as their NMOS counterparts. Consequently, gyrators B and F will likewise not be considered further. Four designs remain under consideration: A, E, G and H. Although gyrators G and H require smaller Vdd than A and E, G and H contain PMOS transistors while A and E use 86 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. only NMOS. It is likely that meeting the frequency range specification of 800 MHz to 2 GHz will prove to be the most difficult requirement o f those outlined in Chapter 2, so designs using only NMOS transistors will be preferred. This decision leaves only gyrators A and E as possible contenders. Gyrator E uses less power and requires a smaller Vdd, but its Vgsi is somewhat restricted (limiting its frequency response), and the single current source will likely cause tuning difficulties. The two current sources of gyrator A will consume more power, but they afford more freedom to independently tune the inductance without changing other parameters such as Qm ax,fmax and /. Thus, gyrator A, depicted in Fig. 26, is selected as the most promising transistorized topology to satisfy the research objectives. 5.3 Stability Analysis of a Transistorized Gyrator Satisfying all performance goals will require design equations for Qm ax, /m a x , C ( t 0 establish a maximally-flat frequency response), and (O n (to determine the maximum operating frequency for which Zin(s) is inductive). It would be convenient to simply use the equations from Chapter 4 rather than perform another complete analysis, but as will be shown in the following section, the equations for the general transconductor model derived in Chapter 4 do not completely apply to the transistorized topologies of gyrators A-H. Consequently, a new small-signal model and a fresh analysis are required. 87 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 5.3.1 Small-Signal Model for Each Transistor To begin the detailed analysis of gyrator A, a high-frequency, small-signal model of each transistor is chosen and depicted in Fig. 34. Note that the bulk is tied to the source in the model, so that the body effect is eliminated with gm bVbS = 0. Connecting the bulk to the source also eliminates the source-bulk capacitance, C Sb , places the gate- bulk capacitance, C g b , in parallel with C g s, and places the drain-bulk capacitance, C d b , effectively from the drain to the source. In the model o f Fig. 34, the parallel combination o f C gs and C g b is represented by C gs alone. + Drain Source Fig. 34. Small-Signal Model of a MOS Transistor in Saturation Replacing each transistor in gyrator A (depicted in Fig. 26) with the model given in Fig. 34 results in the high-frequency small-signal electrical model for the complete synthetic inductor shown in Fig. 35. Fig. 35. Complete Model of Gyrator A Using the Small-Signal Transistor Model of Fig. 34. 88 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. An inspection of Fig. 35 reveals that several model elements are connected in parallel. Thus, the complete inductor of Fig. 35 can be simplified to that of Fig. 36, where and C/ — Cgsl + Cd h 2 , (77) C o = Cd b [ + Cgd2, (78) c = c + c F g dl T gs2» (79) Ri = rn llro 2 > (80) R 0 = rol’ (81) RF = riZ ■ (82) Fig. 36. Equivalent Model of Gyrator A Using the Small-Signal Transistor Model Given in Fig. 34. 5.3.2 Analysis of a Transistorized Gyrator Using the Small-Signal Model The goal is to extract Qm ax, f m ax, and c o n from Zin(s) of Fig. 36, so it may be useful to compare this model to that generated from the general transconductor model shown in Fig. 21 from Chapter 4. If the models are identical, the design equations from Chapter 4 may simply be applied to the model in Fig. 36. 89 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The reference designators of the general transconductor model must first be swapped to match the topology o f gyrator A. The revised general transconductor model is given in There are three differences between the transistorized model of Fig. 36 and the general model of Fig. 37. Two of these differences are minor, but the third ensures that the design equations derived in Chapter 4 cannot be directly applied to the transistorized gyrator A. One obvious difference is that Fig. 36 uses R f to represent the feedback resistance between the input and output ports, while this resistance is assumed infinite in Fig. 37. According to (82), large R f corresponds to large rt2, which is a reasonable assumption for MOS devices. Thus, this difference will have little effect on the final input impedance of each model. A second difference is the reversed direction of gm \ and gm2 between Figs. 36 and 37. This will actually have no effect on the final transfer function of Zin(s). As long as the Fig. 37. Fig. 37. Revised General Transconductor Model with Reference Designators Corresponding to the Topology of Gyrator A. 90 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. current generators within a given model are positioned in opposite directions, a positive input impedance will be produced at the input port. The last difference concerns the location of the controlling voltage, V2, for gm 2. In Fig. 37, V 2 is located across the output port. In Fig. 36, however, V2 is not from the output node to ground, but between the input and output nodes. This difference renders the design equations from Chapter 4 unusable in the present case, and a completely new analysis of Fig. 36 must be undertaken. An analysis o f Fig. 36 (with Rf open) produces the familiar driving-point input impedance of R , + s L 1 + r \ 2 ’ (83) s + where Re is the low-frequency resistance (for gmiRo >> 1), Ri _ 1 R = 1 Sm\Sm2RIR 0 Sm\Sm2R 0 for g m ig m 2R , R 0 » 1, (84) L e is the low-frequency value of the effective input inductance (for gm iRo » 1), RiRo{c o +Cf) L e = ' ^ Sm\Sm2RIR 0 Sm\Sm2 for g m X g mlR ,R 0 » 1 > (85) a > „ is the undamped resonant frequency, and zeta, £ is the damping factor. Expressions for (O n and £ are given in (86) and (87). 91 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. It should be noted that if an external gyration capacitance, C, were added from the drain of M/ to ground in Fig. 26, it would appear in parallel with Co, and would therefore be added to the numerator of the approximation in (85). The new expression for Le would then be identical to that of the general transconductor case shown in (50). As noted previously, however, any capacitance at this node appears in the denominator of the expression for / m ax . To maximize f m ax, no external capacitance will be added in this analysis and the gyration capacitance will consist of only Co + Cf. As shown earlier, the complete circuit behaves less like the ideal circuit as operating frequencies increase. This can be seen from (86), which indicates an undamped resonance condition occurs at frequency, o)n, which can be shown to be In the general transconductor analysis, the approximation in the c o n expression o f (51) requires that Cf be small. This is a reasonable assumption because Cf is comprised of the two feedback capacitances of the transconductance amplifiers (which are small), while Ci and Co are both comprised of an input capacitance (~ Cgs) and an output capacitance (~ Cdb), which will be much larger than Cf. The relatively large external capacitance, C, also helps to make the approximation more accurate. c o . n 1 l for CF « C j. (86) 92 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Comparatively, the approximation of (86) will not be as accurate as that of (51) because C f and Co of the transistorized inductor have new values that tend to invalidate the assumption that C f is small. The new feedback capacitance, C f = Cgdi + Cg S 2, is larger than in the general case, and the new output capacitance, Co = Cdbi + Cgd 2> is smaller. In addition, the external capacitance, C, is not used in the transistorized implementations, rendering the approximation o f (86) even less accurate. Taking these questionable assumptions into account, the approximation in (86) still suggests that the inductance produced at the input port o f the circuit in Fig. 35 effectively resonates with the shunt input capacitance, C/, connected in parallel with the series connection of Cf and Co- As with the general case, the amount of resonance can be controlled by changing the damping of the circuit, and the amount of damping can be measured by analyzing £ The damping factor, £ may be derived from the coefficient of the s term in (83) which is shown in (87) below. Note again that the reference designators are swapped when comparing (87) with the similar expression for the general case in (52). — = 8 .2 + C / + C r + C f ^ ’ ' ~ s ’ 2 ' 1 (87) a>.L. S "2 R 0 (C „+ C F) C0 +Cf An inspection of (87) reveals that for gm j < g m2 and sufficiently large Cf, the damping factor can become negative and result in network instability. This is more of an issue 93 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. for the transistorized topology than for the general transconductor model for two reasons. First, as indicated earlier, C f is larger for gyrator A than for the general model. Second, the general model has a large external capacitance, C, located in the denominator of the last term in (52), which helps to minimize the effects of this term for unequal transconductances. This large capacitance is not present in the transistorized expression of (87), which increases the effect o f the last term for unequal gm i and gm 2- Fortunately, gm j > g m2 precludes right-half-plane poles and therefore ensures asymptotically stable circuit responses. For gm i ~ g m2 and large Ro, (87) delivers an approximate damping factor of Note that the input impedance, Ri, does not appear in (88). Clearly, the frequency response of the input impedance cannot be completely independent of the input resistance. In fact, the similar expression for C , in the general model analysis (53) indicates that £ is indeed a function of Rj. The surprising result in (88) is due to approximations made in the analysis. The approximations used in the design equations for the general case (49-53) include the requirement that RiRogmigm2 » 1. In contrast, the approximations used in the design equations for the transistorized topology (84-88) include the more stringent requirements of Rjgm2 » 1 and Rogmi » 1. If Ri is large enough such that Rigm2 » 1, then Rj does not appear in (88) and C , is rendered nearly independent of Ri. For a nominal transconductance of g m2 = 5 mS, R; must be much (88) 94 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. larger than 200 Q for (88) to remain valid. An inspection of (80) reveals that Ri is approximately equal to the output resistance of M2, r02. Output resistances of modem CMOS devices are at least a few tens of thousands of ohms, so (88) should remain valid. In the general case, Ri is an independent design parameter and is used to control the circuit damping. Similarly, the external capacitance, C, is another independent design parameter and is used to establish the desired inductance. Neither Rj nor C is available in the transistorized gyrator topology, however, so gm i and g m2 must be used to establish both the damping and the desired inductance together. Because each transconductance affects both C , and Le, care must be taken to select gm i and g m2 appropriately. Having lost i?/ and C as independent parameters, meeting all design specifications o f the transistorized topology is more difficult to achieve than for the general case. It is interesting to note that the approximated damping factors of the general model in (53) and the transistorized model in (88) will be equal for g m2 = 1/i?/. Substituting the approximation of (85) for Le in (88) provides an expression for C , in terms of gm j. The result is offered in (89). (89) 95 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Solving (88) for g m2 and solving (89) for gm i yields (90) and (91), respectively. These expressions provide values for g m2 and gm i that yield both the desired damping and the desired inductance. (»«) co L n e g , i - '° - (C^ + C f) (91) It is demonstrated in Chapter 4 that maintaining a damping factor equal to the inverse of root 2, as shown in (59), will impose a maximally-flat constraint on the frequency response of Zin(s). Substituting (59) for C in (90) and (91) results in (92) and (93), respectively. These design equations provide values for g m2 and gm j that yield both the desired inductance and a maximally-flat frequency response. (92) co L n e ( « ) It should be stressed that the approximations in (88-93) are valid for gm i « g m2 such that the last term in (87) is much less than gm 2. This allows (87) to be simplified to (88). As the difference between gmt and g m2 increases, the approximations in (88-93) become less valid. This phenomenon is addressed in more detail in the example of Section 5.5. 96 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 5.3.3 Design Constraints and Guidelines for a Transistorized Gyrator The frequency normalization parameter, y, is again used to facilitate the derivation of equations for Qm a x and f m ax. y = — = 4 - (94) fn Under steady-state sinusoidal excitation conditions, the input impedance of (83) becomes Z J J y ) = Re[z,.„(.,»]+ y lm [z ,„ 0 » ], (95) where R e [z ,,0 > )K / 7» \ ' “ — t— T 5 r 2 -’ ( 9 6 ) ( l - / ) +(2 Zyf ( l - / ) +(2 Qyf in which the approximation replaces Le with its approximation from (88), and Im [ Z ,.0 » ] - - f ) , (97) ( l - y 2) +(2 £ y ) 2 (l - / ) + (2 £ y ) 2 in which the approximation also replaces C , in the numerator with its approximation from (88). As in the general transconductor case, the input impedance, Zin(jy), is only inductive for Im[Zin(jy)] > 0. The imaginary component of Zin(jy) for the transistorized topology given in (97), however, indicates that a range of frequencies exists for which Zi„(jy) is actually capacitive with Im[Zin(jy)] < 0. Therefore, a normalized crossover frequency, 97 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. y co, exists for which Zin(jyc o ) is purely resistive with Im[Zin(jyc o )] = 0. This normalized crossover frequency is ? » = — = 4 s - - V 1- •» .* « * ’> > w fn where the approximation reflects the fact that the product, Regm2, is much less than unity. This is evident for the realistic values of Re and g m2 presented earlier. As in the general transconductor analysis of Chapter 4, the electrical nature of the driving-point input impedance changes from inductive to capacitive at the resonant frequency of the gyrator circuit. Since the objective at hand is the realization o f inductance, it follows from the above discussions that the utility of the transistorized gyrator inductor in Fig. 26 is limited to signal frequencies that are smaller than the circuit resonance predicted by (86). Notice from (96) that unconditional circuit stability, in the sense of a positive real input impedance, is assured for Re[Zin(jy)\ > 0. The second term in the numerator of (96) is non-negative for all values of C , and y, and the first term is positive for y < 1. Thus, the real component of the input impedance will remain positive for signal frequencies in the range 0 < co < c o „ , the same range for which the input impedance is inductive. Using (96) and (97), the quality factor, Q(y), of the actively synthesized inductor is given approximately by 98 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. = 1 M Z jS jy )} „ G > nLey ^ - Reg m 2- y 2) (99) Re[z« 0 > ) ] V / k + ( 2 ^ ' Over the normalized frequency range, y < 1, where the input impedance is inductive and stable, (99) can be approximated as eoo*— a " L ’ y , . (io o ) R, + (2 £ y ) 2 — o m2 which displays a maximum at y ~ = — = 4 a- » - !r J — ■ ( 101> Substituting (84) into (101) reveals that the frequency at which Q is maximized is f « ------------- - _ = ----------:---------= ----------1 g ”L (102) 7 " “ 2nL,g„2J J ^ MCo+Cr)TjR,, ' Replacing y in (100) with ym a x of (101) shows that the value o f the maximum quality factor, g m ax, is Sm ax = 2 0 m a x ) ~ ^ g miR 0 • ( 1 0 3 ) Comparing (102) and (103) o f the transistorized gyrator to (69) and (70) of the general transconductor model reveals significant differences between the two topologies. The most notable difference is that Qm a x for the general case is a function of the input resistance, Rj, the output resistance, Ro, and both transconductances, g/, and g2- The 99 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. maximum Q for the transistorized design, however, is a function o f only Ro and gm j. Rj and g m2 do not affect Qm ax, at least to a first order approximation. In summary, the general model uses the default transconductance values and establishes the desired inductance by appending an external capacitance, C, to the output port, according to (50). The desired damping factor is then chosen with the appropriate selection of an appended input resistance such that the parallel combination of this additional resistance and the default value of i?/ will provide the desired value of Ri from (60). Similarly, an appended output resistance is used to establish an appropriate Ro to satisfy both / m a x (69) and Qm sK (70). Performance trade-offs may need to be made to simultaneously satisfy specifications for the inductance value and the amount of damping, along with f m ax, and Qm ax. In contrast, the transistorized topology may not use an external capacitance to establish the inductance, and because the input resistance does not appear in any design equation, it cannot be used to establish the circuit damping. Therefore, the transconductance values themselves must be used to establish Le and Q according to (90) and (91). As in the general case, the output resistance, Ro, determines f m a x (102) and Q m ax (103) of the synthesized inductor. Trade-offs will also likely be necessary to simultaneously satisfy specifications for Le, £ / m a x and Qm ax. 100 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Again, the largest possible value of Q is dictated by the ability to realize a transconductor characterized by very large shunt output resistance. Note that from (81), Ro depends on only r0i. The value of < 2 m ax is therefore limited by the degree to which the output port of Mi emulates an ideal current source. The figure o f merit ratio used for the general case can also be employed for the transistorized gyrator. This ratio, given in (104), provides the value of the shunt output resistance that is necessary to produce a desired inductance value, given the transconductances o f the amplifiers. f J m 1 Q m a x ^ ~ 'e S m \S m 2 ^ '0 Solving (104) for Ro yields the more useful design equation given in (105). (104) R r ( Q 1 i ^ m a x f 1 } f \ J m a x J (105) If the desired output resistance from (105) is lower than the output resistance of Mi, an additional resistance can be appended to the output port such that the parallel combination o f this additional resistance and rQ i will provide the desired value of Ro- 101 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. It should be noted that the design figure of merit for the transistorized gyrator shown in (104) is identical to that of the general case defined in (71), and the design equations for Ro given in (72) and (105) are equal as well. 5.4 Equivalent Circuit of Transistorized Gyrators A small-signal analysis of each transistorized gyrator presented in Section 5.1 indicates that all topologies have an input impedance, Zin(s), that can be modeled by a parallel RLC equivalent circuit [457]. This equivalent circuit, given in Fig. 38, is identical to that of planar spiral inductors depicted in Fig. 5 (for Ct = Cp+ Cs). Thus, the analysis of Q and the self-resonant frequency derived for spiral inductors may be applied to transistorized gyrators as well. Z. (s) in' ' Fig. 38. Parallel RLC Circuit with Z/„(s) Equivalent to (106). The input impedance, Zj„(s), of Fig. 38 is approximately for Rs « Rp. (106) 102 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. For the transistorized inductor in Fig. 26, values of the circuit elements in (106) can be related to the small-signal transistor model parameters o f Fig. 35 by equating like terms in (106) and (83). Doing so yields 1 1 RS = K S m \ S m 2 ^ 0 8 m \ S m 2 r o\ I = l ~ C Q + Cf _ CM + C gd2 + Cgd\ + Cgs2 and 8 m \ 8 m2 CT — C, — Cg sl + Cdb2, 8 m \8 m 2 8 m2 (107) (108) (109) ( 110) Since the equivalent circuits of the transistorized gyrators and planar spirals are equal, the effects of Re, Ci, and g m2 on Q and the self-resonant frequency of the model in Fig. 38 can be analyzed using the same equations derived for spirals in Section 3.1.2. First, (10-12) are modified in (111-113) using the parameter substitutions in (107-110). Q = coLe R „ \L o s s Factor][SeIf-resonanceFactor], where Loss Factor = and Self-resonance Factor = — - ^ 2LeC, (111) (112) (113) 103 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. From (111), it can be seen that Re directly decreases Q, as expected. From (112), it is evident that both Re and gm2 contribute to decrease Q further, however, the loss factor can be made unity if either Re = 0, or g m2 = 0. The self-resonance factor o f (113) shows how Le, Re, and C/ combine to establish the self-resonant frequency. As indicated in Section 3.1.2, the self-resonant frequency may be found by setting (113) to zero and solving for co . Doing so yields ^SRF ~ Le f g2C/ . (114) L /C , Not only does Re lower Q, but it also reduces the self-resonant frequency according to (114). Only for Re = 0 does the self-resonant frequency have the familiar form of ® SR F ~ ' > (H 5) which is equivalent to the resonant frequency in (86) derived earlier. 5.5 Design Example To verify the equations derived in Section 5.3 and to illustrate a plausible transistorized design methodology, an inductor will be designed using the topology of gyrator A in Fig. 26. Each transistor in gyrator A is assumed to have a small-signal model equal to that in Fig. 34. 104 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. For the following example, assume two identical NMOS transistors are available with § m l § m 2 5 mS, Cgsl 5 fF, Cdbl ~ Cdb2 20 fF, Cgdl C' gd 2 3 fF, Fjl fQ ~ 5 MQ, and rQ i - r02 = 100 KQ. These are the same parameter values used in the example of Section 4.4. Let the specifications entail the realization o f a critically-damped, 25 nH inductor characterized by a Q of at least 15 at a frequency o f 1 GHz. Replacing each transistor in Fig. 26 with the small-signal model o f Fig. 34 produces the equivalent circuit shown in Fig. 36. 1. From (77-79), Q = 25 fF, C0 = 23 fF, and CF = 8 fF. Using (80-82), = 98.04 KQ, Ro - 100 KQ, and RF = 5 MQ. 2. For gm i = g m2 = 5 mS, the value of the default inductance can be calculated from (85) to be Le = 1.24 nH. Similarly, the default damping factor from (88) yields Q= 0.5, producing an over-damped response. Clearly, the default values of gm i and g m2 need to be altered to achieve critical damping and the desired inductance of 25 nH. Equations (92) and (93) provide the appropriate values of g m2 and gm i, respectively, but the resonant frequency must be known first. 3. From (86), the resonant frequency of the network is found to be f , = 5.72 GHz, which represents the upper bound of stable operating frequencies, and the upper bound for which the frequency response o f the input port impedance is inductive. 105 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4. Proper values for gm i and g m2 to simultaneously provide the desired inductance and a critically-damped frequency response can be obtained from (93) and (92), respectively. Evaluating these expressions yields gm i = 788 pS and g m2 =1.57 mS. 5. The only remaining design parameter value to select is the output port shunt resistance, Ro- Note that Ro controls f m a x in (102) and Qm ax in (103), and selecting a single value for Ro that satisfies specifications for bothy^ax and Qm a K may not be possible. For these reasons, compromises in the design specifications may be necessary. To illustrate the possible design compromises revealed in step 5 above, (102) and (103) are solved for Ro in (116) and (117), respectively. R0 ~ ------------ r (116) g m x Q n f m n g m l L . ) 4 0 2 R0 ~ — — (117) Sm\ For 0 m ax = 15, the desired Ro may be calculated from (117) to be Ro = 1.142 MQ. Unfortunately, this is more than 10 times larger than the default value of Ro - 100 KQ. Appending a resistance to the output port to control 0 m ax will only decrease the effective output resistance - not increase it - and reduce Qm a x even further. Thus, the specification for Qm a x cannot be satisfied using the given model parameters. 106 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. To achieve/m ax = 1 GHz, R 0 may be calculated from (116) to be Ro = 20.87 KQ. Since the default value of Ro for the chosen transistors is Ro - 100 KQ, a resistance of 26.37 KQ must be appended in parallel with the output port to reduce the output resistance to Ro = 20.87 KQ. This resistance yields the desired/nax, but the resulting maximum Q is reduced to £?m ax = 2.03 from (103). The low-frequency series resistance, Re, may be calculated from (84) to be Re = 38.7 Q. The complete inductor (without biasing) is shown in Fig. 39, in which the small-signal model of Fig. 34 is used for each transistor, and the values of the model elements are given in the design example above. Fig. 39. Transistorized Gyrator Realization for the Design Example in Section 5.5. SPICE simulations of the inductor in Fig. 39 are provided in Figs. 40-42. As the following overview confirms, excellent corroboration between the simulated and analytically deduced results is obtained. V 107 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 40 displays the frequency response of the inductance for the active inductor in Fig. 39. As in Chapter 4, the inductance has been calculated as the frequency derivative of the imaginary component of the driving-point input impedance, Zin(jco). The simulated low-frequency inductance is 22.37 nH, which is maintained to within 15% for signal frequencies through 2.5 GHz. The frequency response is critically damped, with (88) predicting a damping factor of C , = 0.705, nearly equal to the ideal value of 0.707. 25n Le = 22.37 nH ^ 15n s 10n G 5n ,9 3 1 .8 10 10 F req u en cy (H z) Fig. 40. Simulated Frequency Response of the Inductance for the Gyrator in Fig. 39. The Inductance Value at Low Signal Frequencies is 22.37 nH and is Maintained to Within 15% of this Value Through 2.5 GHz. 108 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 41 depicts the frequency responses of both the real and imaginary components of the driving-point input impedance for the active inductor of Fig. 39. The simulated low-frequency resistance, Re, is 36.7 Q, which is very close to the calculated resistance of 38.7 Q. The real part of the input impedance shows resonance at 5.75 GHz, while its imaginary counterpart is zero at 5.72 GHz. Again, excellent corroboration exists between these simulated values and the calculated value oif„ = 5.72 GHz. -r R & 1 Retil Part / t i / 1 / -A --- fmnainnrx} Pinrt > 7 \ 1 / 1 \ 4- --- — ' 1(f 107 108 10 F req u en cy (H z) 9 10 10 Fig. 41. Simulated Frequency Response of the Real and Imaginary Components of the Driving-Point Input Impedance for the Gyrator in Fig. 39. The Imaginary Component is Zero at 5.72 GHz. 109 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 42 provides the frequency response of Q for the active inductor of Fig. 39. A maximum Q o f 2.03 is observed at a frequency o f 1.03 GHz. Theoretical values agree exactly with g m ax = 2.03 an d /m a x = 1.0 GHz. 2.5 ‘ m a x Oi 2.0 £ & ... a O ) 0.5 = 1 .0 3 G H z m a x ,6 ,9 .7 ,8 10 F re q u e n c y (H z) Fig. 42. The Simulated Quality Factor of the Inductance for the Gyrator in Fig. 39. The Maximum Q of 2.03 Occurs at a Frequency of 1.03 GHz. 5.6 Accuracy of Design Example Results The simulation results of Section 5.5 confirm that the equations derived in Section 5.3 can be used successfully to design transistorized inductors. However, the assumptions used to simplify the analysis must be taken into account when considering the accuracy of the final equations. 110 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. In the recent example, the simulated value of the inductance is 22.37 nH, while the theoretical inductance is 25 nH. This slight discrepancy is caused by the relatively small values of gm i and Ro, undermining the assumption, gm jRo » 1 • Using the larger default value of Ro — 100 KQ (instead of the smaller value of 20.87 KQ to satisfy the fnax specification) produces a simulated inductance of 24.5 nH, which is much closer to the theoretical 25 nH. Similarly, using (90-93) to select gmi and g m2 for the desired inductance and circuit damping may result in less accurate Le and C , values as the difference between gm i and g m2 increases. The simplified equations containing C , assume that the last two terms of (87) are much less than gm 2. As the last term in (87) demonstrates, this assumption is less valid as the difference between gm \ and g m2 increases. Finally, it must be remembered that altering gm i and gm2 to satisfy the Le and C , requirements will also change the capacitances in the small-signal model of Fig. 34. Capacitances Cgs and Cgd are functions of gate area, while Q* is a function of both gate area and the bias voltage, Vm, from drain to bulk. An iterative design process may therefore be necessary to satisfy both Le and C , specifications. 5.7 Quality Factor Limitations of Transistorized Gyrators The example of Section 5.5 suggests that achieving high Qs is difficult with transistorized gyrators. This is true because high Q requires a larger Ro than can be 111 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. achieved with the transistorized gyrators of Section 5.1. Equation (117) can be used to explain why this is so. For Qm a x - 15 and gm i = 5 mS, (117) indicates that Ro must be equal to 180 KQ. However, if Q is desired to be equal to or greater than 15 over a range o f frequencies, then Qmax should be increased to account for smaller Q at frequencies less than and greater than / m ax. Selecting a larger Qm a x of 20 forces Ro to increase from 180 KQ to 320 KQ. The analysis in Section 5.3 assumes that the current sources in Fig. 39 are ideal, and therefore have infinite output resistances. When implemented with transistors, however, current sources 7/ and h will have finite output resistances, r0 u and r0n, respectively. Because Ro is the effective resistance at the output node, Ro will not simply equal r0i as (81) suggests, but will equal the parallel combination o f rQ i and r0n. To counter the effect of roU and achieve the desired Ro, r0i must be very large. Assuming for simplicity that r0 u and r0i are equal, they each must be twice the desired value of Ro so that their parallel combination will yield the correct Ro o f 320 KQ. Unfortunately, the large gm j necessary for the desired Le and Q requires a large drain current, Idi, and therefore a small r0j. The relationships between g m, Id, and r0 are provided in (118) and (119). For a given transconductance, (118) provides the 112 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. corresponding Id for a MOS transistor operating in saturation (neglecting the contribution of the drain-source voltage, V ds). / „ = - % r (118) 2 k '— L Assuming reasonable values for gm = 5 mS, k1 = 250 pA/V2, and W/L = 40, the drain current may be calculated to be Id - 1.25 mA. The channel length modulation parameter, X, describes the relationship between the drain current and output resistance and is defined in (119). l = - t - (119) r,Jd For Idi = 1.25 mA and r0i = 640 KQ, X must be approximately 0.001. This is 100 times smaller than typical values of X for deep submicron NMOS transistors. A more realistic value o f X is 0.12, reducing r0i to ~ 6.7 KQ. Assuming a similar resistance for r0ii, Ro will equal the parallel combination of r0j and ra u resulting in Ro ~ 3.3 KQ. Applying (103) again with gm i = 5 mS and R o - 3.3 KQ produces Qmax ~ 2. This low value of Q is also verified by SPICE simulations. All eight of the transistorized gyrators in Section 5.1 (using current sources implemented with actual transistors), have been simulated in SPICE using BSIM3v3.2 transistor parameters from a standard 0.13 pm CMOS process. In all cases Qs were no more than 2-3. 113 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. To increase Q to more useful levels, Ro must be increased without a corresponding decrease in gm j. A cascode topology achieves this desired result, and is analyzed in detail in the following chapter. 114 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 6: Analysis of a Cascode Gyrator Inductor Section 5.7 concludes that the transistorized inductors depicted in Figs. 26-33 have a maximum Q of only 2-3. This limited Q is caused by the inverse relationship between Id and r0 shown in (119), making large drain current and large output resistance difficult to achieve simultaneously with a single transistor. A circuit topology is therefore needed that increases the effective output resistance without causing a corresponding decrease in bias current. Such performance can be found in the cascode gyrator presented in Section 6.1. An accurate small-signal model of the cascode gyrator is developed in Section 6.2, and an analysis of this model is offered in Section 6.3. Finally, guidelines for the design of stable cascode gyrator inductors are outlined in Section 6.4 and summarized in Section 6.5. 6.1 A Cascode Gyrator Inductor Overview One technique to increase the output resistance o f Mi in gyrator A is to add a third transistor, M3, between the drain of Mi and the gate of M2. This new cascode inductor is shown in Fig. 43 [458]. 115 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. dd G3 Fig. 43. A Cascode Gyrator Inductor. The circled numbers in Fig. 43 represent node numbers that will be referenced in the remainder o f this document. The input port is node 1, the output port is node 2, and the intermediate node between the cascoded transistors of Mj and Mj is node 3. In the cascode gyrator, M3 buffers Mj from variations in voltage at the output node. The addition o f M 3 increases the output resistance from rQ i (for the two-transistor topology of Fig. 26) to r03(\+gm 3ro!) for the cascode topology in Fig. 43. Because the cascode gyrator produces this large output resistance without reducing drain current, Q is increased and gm i can remain large enough to deliver inductances in the low nanohenry range. 116 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Replacing R 0 in (84) with the appropriate small-signal output resistance reveals the simplified series resistance (assuming ideal 7/ and I2) for the original transistorized gyrator A in Fig. 26 to be Re* ------ , ( 120) § m \& m T ^ o X and for the cascode gyrator of Fig. 43 to be * . « ! . (121) S m l S m 2 S m3r o i r o3 The cascode inductor reduces Re by approximately the gain of M3, gm 3ro3, and increases Q by the same amount. As in previous analyses, design equations are desired for Le, Re, c o n, £ Qm a x and f m ax, and deriving these equations requires a complete small-signal equivalent circuit. In past analyses, circuitry implementing the current sources, 7/ and I2, have been omitted in the small-signal analysis. This circuitry will be included in this chapter, however, because the finite output resistances of the current sources have a profound effect on the performance of the synthesized inductor. Fig. 44 depicts the inductor of Fig. 43 with the ideal current sources, 7; and I2, replaced by transistors, Mia and M2 a, respectively. 117 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. dd G1A 2A / Fig. 44. A Cascode Gyrator Inductor with Non-Ideal Current Sources. 6.2 Small-Signal Model of a Cascode Gyrator Replacing each transistor in Fig. 44 with the small-signal model given in Fig. 34 produces the high-frequency small-signal electrical model shown in Fig. 45. 118 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Current Source M. 1A ’ dlA ilA gslA olA dblA db3 db2 gdl Z (s) in '* / Current Source M, ; d2A db2A 1 2A Fig. 45. Small-Signal Model of the Cascode Gyrator Given in Fig. 44. An inspection o f Fig. 45 reveals that several model elements are connected in parallel. Other elements are connected to ground at both terminals, effectively eliminating them from the model. These shorted elements are ruA, CgsiA, rt2A, and Cg S 2A - In addition, Vg siA and Vg S 2A are both equal to zero, enabling the removal o f current sources gm iAVgsiA and gm 2A Vgs2A - The complete circuit of Fig. 45 can therefore be simplified to the model 119 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. given in Fig. 46, where the values of the circuit elements are provided in equations (122-132). 30 © ^ 2 0 > R 20 Q ^ 8 m 3 V g s3 23 R 21 V* 2 T C» C^S/nl^gs! C^JSm 2^gs2 V gsI - CI0 © ;o Fig. 46. Equivalent Model to the Cascode Gyrator Model in Fig. 45. ©o — Cgs\ + Cd b 2 + Cgd2A + Cd b 2 A ^20 ~ ~ Cgd2 + Cgds + Cgd\A + Cd b X A c =c +c 3 0 dbl T ' - ' g s 3 ^ 2 1 ~ Cgs2 c = c 2 3 W f > 3 Q l ~ Cgd\ * 1 0 = r iX l l r o2 11 r o2A R = r 2 0 f o \A R3o = ro l Hrn (122) (123) (124) (125) (126) (127) (128) (129) (130) 120 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. R2X= r i2 (131) *23=^3 (132) 6.3 Analysis of the Cascode Gyrator Small-Signal Model In previous analyses of gyrators using the general transconductor model and the transistorized inductor topology, an expression for the input impedance, Zin(s), was found from the simplified small-signal model. The input impedance was then cast in the form given in (48) and (83), and simplified expressions were extracted for Le, Re, C 0 „ , £ 0max ^m d^/niax- Unfortunately, the model in Fig. 46 cannot easily be simplified to a 2n d -order circuit, and a 2n d -order circuit is required to derive expressions for the damping factor and the resonant frequency as performed in earlier analyses. Even if a simplified small-signal model is used for each transistor (one containing only Cgs, r0, and the current generator, gm ), a 3rd-order circuit is still produced. In an effort to simplify the model in Fig. 46 as much as possible without reducing the model’s accuracy, an empirical approach was adopted. The cascode gyrator inductor in Fig. 44 was first implemented using SPICE transistor models from a standard 0.13 |am CMOS process, and biased such that reasonable values were obtained for gm i, gm 2, and gm 3. The values o f the remaining elements defined in (122-132) were then extracted from an operating point analysis of the complete circuit. The model o f Fig. 46 was 121 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. simulated in SPICE (using the extracted element values), and the performance of the small-signal model was compared to that of the “real” circuit implemented with transistors. Finally, to determine which elements in the model can be omitted without seriously affecting its accuracy, each element in Fig. 46 was removed one-at-a-time and the resulting performance of Le, Q, and R e was compared to the lull model. It was determined that elements Cio, C 23, and R 21 and can all be removed from the model simultaneously without sacrificing simulation accuracy. The simplified model is shown in Fig. 47 with the frequency responses for Le, Q, and R e given in Fig. 48. © Fig. 47. Simplified Yet Accurate Model of the Cascode Gyrator in Fig. 44. Elements Cio, C23, and R21 Have Been Omitted. 122 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. *4 20n 16n 12n 8n 4n 0 800 MHz-2 GHz Real Complete Simplified -s; - 800M H z-2 i 0 50 40 30 20 10 0 Real Complete Simplified Real Complete Simplified 10' 10” 10° 10 F req u en cy (H z) 10 10 11 Fig. 48. Frequency Responses for the Simplified Yet Accurate Model of Fig. 47. In Fig. 48, traces labeled “Real” represent those from the actual inductor in Fig. 44 implemented with SPICE transistor models from a standard 0.13 pm CMOS process. Traces labeled “Complete” were generated from the complete model in Fig. 46, and traces labeled “Simplified” were generated from the simplified model in Fig. 47. Fig. 48 indicates that the complete model predicts the performance o f the real inductor very well, and the simplified model is still reasonably accurate for signal frequencies up to a few gigahertz. 123 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Unfortunately, the simplified model in Fig. 47 still contains four capacitors. The capacitive loop of nodes 0-2-1-3-0 will reduce the circuit’s response to a 3rd-order instead of the usual 4th-order, but even a 3rd -order response will preclude the extraction of C , and c o „ that was performed in earlier analyses. O f the four remaining capacitors, only Cn might possibly be eliminated. In some self aligning processes (typically with minimum channel lengths of 0.18 pm and larger), all gate-drain capacitances may be neglected. In accordance with (127), Cj/ may then be removed from the model. Once again, however, a 3rd -order circuit remains, and both hand calculations and SPICE simulations demonstrate that a response of at least 3rd- order is necessary to retain accuracy of the model. Even with C31 = 0, expressions for Q xnax and f m sK become too complex to afford any assistance in designing practical inductors. Even though useful yet accurate expressions for £ < % , Qm ax and f m a x cannot be obtained, low-frequency values of Le and Re can be derived from the model, and a thorough understanding of the cascode gyrator inductor operation can still lead to an intelligent methodology for its design. There are two techniques that can be used to derive expressions for Le and Re of the full model given in Fig. 46. The first is to find the complete expression for Zin(s) given in (48) and (83), and then equate terms in the numerator such that Re is set equal to the 124 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. real component and Le is set equal to the imaginary component. The second approach is to use the expressions for Re and Le derived for the transistorized topology in (84) and (85), respectively, with effective values for Ro, Co, and Cf that are appropriate to the cascode topology in Figs. 44 and 46. The second approach provides more insight into the operation o f the cascode gyrator and is outlined below. A simplified expression for Re has already been provided in (121) for the cascode gyrator o f Fig. 43, but this expression assumes current sources // and h are ideal and have infinite output impedances. A more accurate expression for Re is needed that reflects the inclusion of non-ideal current sources, Mia and M2 a- Figs. 44 and 46 reveal that the inclusion of Mia and M2 a produce the output resistance provided in (133). R0 ~ R20 H ^ 2 3 ( l S m 3 -^ 3 o )= ro \A ^^o3 + Sm^ol) ( 1 3 3 ) Substituting (133) for Ro in (84) produces the series resistance given in (134) of the cascode gyrator depicted in Fig. 44. gmlgmlRo g m lg m 2 VoU " ^ 3 0 + gn,Sol )] The inductance of the transistorized gyrator of Fig. 26 is given in (85) in terms of the effective output capacitance, Co, and the effective feedback capacitance, C>. These capacitances are provided in (78) and (79), respectively. The inductance o f the cascode gyrator inductor in Fig. 44 can still be derived using (85), however, provided that 125 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. appropriate values for Co and CF are used. An analysis of Figs. 44 and 46 shows that the effective output capacitance from node 2 to ground and the effective feedback capacitance from node 2 to node 1 can be defined as in (135) and (136), respectively. (135) CF — C2 1 + (136) Substituting (135) and (136) for Co and CF in (85) produces the inductance shown in (137) for the cascode gyrator in Fig. 44. As indicated earlier, useful yet accurate expressions for £ c o n, Qmax, and / m a x cannot be obtained. However, an intelligent methodology for designing cascode gyrator inductances can still be devised. This methodology is based on expressions (133-137) and on the previous stability analyses of gyrators using the general transconductor model in Chapter 4 and the transistorized inductor topology o f Chapter 5. The equations derived in Chapters 4 and 5 will not be exact for the cascode topology, but will be qualitatively accurate enough to draw some general conclusions. S m \ S m2 & m \ S m2 126 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 6.4 Design Constraints and Guidelines As with most designs, many trade-offs exist when developing cascode gyrator inductors to satisfy a multitude of specifications. Listed below are five principal trade offs regarding critical parameters and the equations from which they are derived. Following each trade-off, guidelines are provided to help reconcile the conflicting choices and offer biasing and other design suggestions. 1. The capacitance sum, C o + Cf, should be large to maximize C , (88-89), but should be made small to maximize T^ax (102) and c o „ (86) and to keep Le in the 1-15 nH range (137). A compromise should therefore be adopted in which Co + C f is made just small enough to satisfy the specifications fo r/m a x and < y „ and to keep Le between 1-15 nH. Making C o + C f smaller than necessary will reduce the circuit damping, causing peaking in the frequency response of the inductance. According to (135) and (136), Co + C f can be made small by using small geometry devices for Mia, M2, and M3. 2. The output impedance, R o , should be large to minimize R e (133-134) and maximize Qm a x (103), but should be small to maximize /max (102). A compromise must again be adopted in which Ro is made just large enough to satisfy the specifications for Q m ax- Making R 0 larger than needed will reduce / m a x 127 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. unnecessarily. According to (133), Ro can be made large by biasing the circuit to obtain large r0i, r0iA, ro3, and gm 3 - A conflict arises, however, because (119) stipulates that large r0 requires small Id, and small Id yields small transconductances. Therefore, obtaining both large ro 3 and large gm 3 is difficult to achieve. Similarly, obtaining both large roi and large gm j (needed in #3 below) is difficult to achieve. One method to increase rQ while keeping Id constant is to increase the channel length of the subject transistor. This decreases X, and (119) indicates that smaller X will yield larger r0 for a given Id- However, according to (76), increasing the channel length in a transistor through which the signal travels will decrease that transistor’s unity-gain frequency. Thus, increasing the channel length of Mi will hamper the frequency performance of the inductor. Luckily, r0i, r0 3, and gm 3 need not be enormous, because the cascode topology multiplies them together to generate a relatively large resistance at the drain of M3. This attribute of the cascode arrangement of Mj and M3 underscores why the cascode topology has been selected to yield high-g inductors. With a very large resistance o f ~ gm 3r0ir03 seen when “looking into” the drain of M3, the effective output resistance at node 2 will be approximately equal to the resistance seen when “looking into” the drain of Mia- Unfortunately, M u is not arranged in a cascode structure, so the output resistance at its drain is simply r0u- Since M !A is acting as a current source, no signal flows through it. Thus, its output 128 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. resistance can be increased by increasing its channel length and decreasing X without reducing the frequency response of the inductor. To review the trade-offs for Ro, the bias current through M u, M 3, and Mi should be just large enough to achieve moderate values for g m3 and gm i, and the relatively small output resistances, r0i and r03, will get multiplied together with g m3 to create a large resistance at the drain of M3. M u will have the same current as Mi and M 3 (producing relatively small r0u), but rau can be increased by using a larger channel length and decreasing X according to (119). In Chapters 4 and 5, the default Ro was made larger than necessary, and then reduced to satisfy the / m ax or f?m ax specification by appending an external resistance to the output node. This is not the most efficient way to satisfy these specifications, because making the default Ro larger than necessary will require that M u be larger than necessary. Larger M u will increase Co + Cf, decreasing 0^ and f m ax, and possibly increasing Le out of the desired range. Thus, Ro should be made only as large as necessary to satisfy the specification for Q m ax- No external resistance will be appended from the output node to ground. 3. The transconductance of M ;, gm }, should be large to maximize Qmax (103), f m a x (102), and c o n (86), and to minimize Re (134) and Le (137), but should be small to maximize £ (88-89). 129 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. A third compromise must be made in which gm i is just large enough to satisfy the specifications for Q max, fm ax, &>n, Re, and Le. Making g mi larger than necessary will lower the damping, causing peaking in the frequency response of the inductance. As discussed in #2 above, gm i is limited by the bias current requirements needed to create a large output resistance to satisfy the (7m ax specification. However, as will be shown in #4 below, g m2 can be made much larger than the moderate value of gm i to help satisfy the specifications for < x > „ , Q , Re, and Le. 4. The transconductance of M2, gm 2, should be large to maximize a > n (86) and C , (88- 89) and to minimize Re (134) and Le (137). At first glance it appears that g m2 should be as large as possible, but making g m2 larger than necessary has disadvantages. Large gm2 will require either large devices (which will increase Co + C f and decrease 6)n and /m a x ), or will require a large bias current which will consume unnecessary power. Given the limited value of gm ;, g m2 should be made as large as necessary (larger than gm i), to establish the desired Le, 0^ , Re, and £ ,, without using excessively large devices or consuming extra power. 130 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 5. The input capacitance, C/, should be small to maximize a > „ (86) and £ (88-89). The input capacitance, C/, in (86), (88), and (89) is represented by Cio in Fig. 46. Minimizing Cw is accomplished by using small devices for Mi, M 2, and M}a- 6.5 Conclusions In summary, all five transistors in Fig. 44 should be implemented with small geometry devices. Current sources M u and M2A may use larger channel lengths to increase their output resistances, but if possible, the channel lengths for Mi, M2, and M3 should be kept small to maximize their unity-gain frequency, cor. If either r0i or r03 needs to be increased to satisfy the Qm a x specification, then increasing r03 (by using a larger channel length for M3) is preferred to increasing r0j. Gate widths and gate-source voltages should be selected to establish the appropriate values for gm i and gm 2- Given that Co + C f will be in the tens of femptofarads for modem deep submicron CMOS processes, gm i and g m2 will need to be in the millisiemen range to produce inductances between 1-15 nH according to (137). Producing small inductance values is difficult, because small Le requires small Co + CF yet large gm j and gm2* Creating a large transconductance without using a large device requires large Vgs (which also increases cor), but the topology o f the cascode gyrator 131 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. does not allow all transistors to have large Vgs and remain in saturation. Since gm ; will be smaller than gm 2, Vgsi should be less than Vg S 2- To maintain large Q, a large output port resistance is more important than a large input port resistance. Therefore, a large output resistance for Mi is more important than a large output resistance for M2, so Mi should be biased with less current than M2. This smaller current will limit gm j, but g m2 can be made larger to satisfy Le. The smaller r02 that is developed from the larger /<# will not appreciably lower Q because r02 appears across the input port. 132 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 7: Designing Cascode Gyrator Inductors To investigate the preceding analysis and resulting design equations more thoroughly, a cascode gyrator inductor is designed in this chapter using SPICE transistor parameters (BSIM3v3.2) for a standard 0.13 pm CMOS process. This process offers channel lengths as small as 0.13 pm for 1.2 V transistors, but requires channel lengths of as least 0.28 pm for 2.5 V transistors. Because drain-source voltages in this design exceed 1.2 V, the 2.5 V transistors are employed. As a benefit, all transistors in the design have channel lengths o f at least 0.28 pm, enabling the design to be ported to more mature and less expensive processes. SPICE simulations using transistor parameters from a standard 0.25 pm CMOS process yield similar results to those presented here. 7.1 Validating the Design Equations and Guidelines Using the design constraints and guidelines from Chapter 6, a complete cascode gyrator inductor is designed and depicted in Fig. 49, with the frequency responses for Le, Re, and Q (extracted from Zin(s) at the input port), given in Fig. 50. The numbers next to each transistor in Fig. 49 represent the size (W/L) of the gate width and channel length in microns. The bias voltages, V g 3, V g ia , and V q 2a are implemented with ideal DC voltage sources. 133 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. r Ad. 1A 0.56 G1A r 3 0.56 — M 0.28 1 — M 0.56 2A Fig. 49. A Cascode Gyrator for Design Guideline Validation. The gyrator in Fig. 49 uses a single supply voltage o f 2.5 V, and is biased to produce gmi = 1 mS and g m2 = 2 mS. As suggested in the design guidelines, the channel lengths for Mi and M 2 are minimized to 0.28 pm. The channel length o f M 3, however, is increased to 0.56 pm to increase the output resistance and satisfy the specification for Q. To minimize the gate width of M 3 (minimizing Co + Cf and therefore keeping Le less than 15 nH), V gS3 is made relatively large. This enables M 3 to accommodate the current required of Mj without making the capacitances of M 3 larger than necessary. In the final design, node 1 is 0.7 V, node 2 is 1.6 V, and node 3 is 1.2 V. The bias currents are Idi = 123 pA and U2 = 554 pA, producing a power consumption of only 1.7 mW. 134 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 60n 50n ® 40n ^ 3 0 n 20n 10n 50 40 800 MHz-2 GHz 60 800 MHz-2 GHz O 30 .9 10 > 8 10’ 10' 10 F req u en cy (H z) Fig. 50. Frequency Responses for the Gyrator in Fig. 49. A SPICE operating point analysis was used to extract parameter values and test the validity of equations (133-137). Using these extracted parameter values, the output resistance from (133) is found to be 92.4 KQ, and the series resistance from (134) is found to be 5.34 Q. Simulations from SPICE report a low-frequency series resistance of 5.53 Q, producing an error of only 3.6%. From (135), the effective output capacitance is calculated to be 8.3 fF, and from (136) the effective feedback capacitance is calculated to be 10.1 fF. Using these values in (137) yields an 135 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. inductance of 9.2 nH. Simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance of 9.4 nH for an error of only 2.2%. 7.2 Comparing Performance Results with Research Objectives The graph of Le in Fig. 50 shows that the inductance rises from 9.4 nH at low frequencies to 54 nH at 6 GHz. The frequency range of interest for this research, however, is from 800 MHz to 2 GHz, and Fig. 50 shows that Le is fairly constant within this range. The inductance is 9.6 nH at 800 MHz and 10.9 nH at 2 GHz, giving a nominal inductance o f 10.25 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies only ±6.3% . Although the frequency response o f Le is not maximally-flat, the specification in Section 2.3.2 requiring the inductance to be independent of frequency to within ±15% (over the operational frequency range) is satisfied. Simulations also report that Q is 17 at 800 MHz, peaks to 15,000 at 1.15 GHz, and decreases to 12 at 2 GHz. Thus, Q is greater than 10 over the frequency range of interest and satisfies the high-Q specification in Section 2.3.3. The specifications outlined in Sections 2.3.1, 2.3.5, 2.3.6 and 2.3.7 are also satisfied with the design in Fig. 49. The gyrator-based inductor operates correctly over the required frequency range using a standard Si CMOS process as specified in Section 2.3.1. The transistors are very small, resulting in a die area much less than that required of a spiral inductor of the same value and quality as specified in Section 2.3.5. Proof of this will be given later in Section 7.4. The supply voltage of 2.5 V satisfies 136 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. the requirement in Section 2.3.6 and the power consumption of 1.7 mW is much less than the maximum power of 10 mW specified in Section 2.3.7. The only remaining specification left unsatisfied is described in Section 2.3.4. The inductance value is to be tunable from ± 20% of the nominal value, with Q remaining no less than 10 over the entire tunable inductance range. Adding tunability to the cascode gyrator o f Fig. 49 is described in the following section. 7.3 Tuning the Inductance of the Cascode Gyrator A quick glance at (137) reveals that the inductance of the cascode gyrator can be tuned by varying either gm i or gm 2. A simple yet effective technique to tune gm \ is shown in Fig. 51. The tuning scheme involves using M t u n e to progressively steer more and more current away from Mi and into M t u n e • With V g t u n e = 0 V, M T u n e is in cutoff and conducts no current. Thus, all current from the source of M3 enters Mi and establishes gmi at its default value of 1 mS. As V g t u n e is increased beyond the threshold voltage of M t u n e , some of the current from the source of M3 enters M t u n e instead of My. Reducing Idi reduces g mj and increases L e in accordance with (137). The tuning transistor, M t u n e , is sized such that when V g t u n e = 1.5 V, it conducts the maximum amount of current away from Mi while still allowing the inductor to meet the specification for Q over the required range of frequencies. 137 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. IA 0.56 G1A r « 3 0.56 r M l TUNE 1.2 — M 0.28 m l \7 — M 0.56 1 1 2 =1 V G2A Fig. 51. A Complete Tunable Cascode Gyrator Inductor. A new small-signal model that includes the effects of M t u n e is needed to calculate new values of Re and Le. This complete model is shown in Fig. 52, and like the model in Fig. 45, has many elements that are either shorted to ground or connected in parallel with other elements. 138 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Current Source M, >dlA 'dblA ilA gslA olA gd3 gd2 db3 db2 gs3 gdTUNE iTUNE' 'gsTUNE gsTUNE oTUNE dbTUNE gsTUNE gdl Z (s) dbl Current Source M, 12A db2A i2A gs2A o2A Fig. 52. Small-Signal Model of the Tunable Cascode Gyrator Given in Fig. 51. The tunable model in Fig. 52 can therefore be simplified to the model in Fig. 53. The topology of the simplified model in Fig. 53 is identical to that in Fig. 46, but the values 139 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. of some of the circuit elements are different than those given in (122-132). The circuit element values applicable to the tunable model of Fig. 53 are provided in (138-148). Fig. 53. Equivalent Model to the Tunable Cascode Gyrator Model Given in Fig. 52. C,o — Cg sl + Cd b 2 + Cg d 2 A + Cd b 2 A ^ 2 0 - C g d 2 + C g d l + C g d \A + C d b \A c =c +c +c +c 3 0 dbl T ' - / g s 3 T gdTUNE T dbTUNE c = c ' - ' 2 1 gs2 ^ 2 3 — C db3 c = c 3 1 ^ g d 1 * 1 0 = r il H r o2 11 r o2 A * 2 0 — r o\A (138) (139) (140) (141) (142) (143) (144) (145) 140 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. ■^30 — r o\ H r i3 H r oTUNE (146) R2X= r i2 (147) * * = r * (148) The addition of M t u n e changes the value of the output resistance, Ro, to R o * ^ 2 0 H R 23 (l + 8 m 3R 30 ) = Vo\A ^ To3 [l + 8 m 3 i r ol N r oTUNE )]• (149) Substituting (149) for Ro in (84) produces the series resistance given in (150) of the tunable cascode gyrator depicted in Fig. 51. Re ~ ----- = ----------- j J ------ t------------- m (150) 8 m l 8 m 2 R 0 8 m \ 8 m 2 V o lA 11 Yo2 [1 + 8 m 3 « r oTUNE j j j The addition o f the small-signal model elements of M T u n e has little effect on Ro or Re. The output resistance, r0ruNE, is much larger than r0j, yielding an effective output resistance and series resistance very similar to that for the gyrator in Fig. 44. The additional model elements of M t u n e have even less effect on the critical capacitances, Co and Cp. The effective output and feedback capacitances given in (151) and (152) for the tunable gyrator are identical to those o f the standard gyrator of Fig. 44. c 0 = C 20 = Cgd2 + Cg < /3 + CgdlA + CdbX A (151) 141 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. CF — C2 1 + c c 2 3 3 1 ( c c ^ ^ , db3 gd\ gs2 c +c (152) Consequently, the expression for the inductance of the tunable gyrator in (153) is the same as for the standard gyrator in Fig. 44. It may be concluded, then, that the tuning scheme offered in Fig. 51 is an effective technique to tune the inductance via gm i without altering the existing expressions or design guidelines. 7.4 A Suite of Six Tunable Cascode Gyrator Inductors Section 2.3 specifies that gyrator-based inductors must be designed with inductance values between 1-15 nH and with Q no less than 10 over the frequency range of 800 MHz to 2 GHz. In addition, the inductors must be tunable, with a minimum tuning range of ± 20% of the nominal value. To satisfy these requirements, six tunable cascode gyrator inductors have been designed and are discussed in detail in Sections 7.4.1 through 7.4.6. Each inductor has been designed such that its tunable inductance range overlaps with those of other & m \S m 2 S m \ S m 2 (153) 142 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. designs. In this way, the suite of six inductors has a combined tuning range of greater than 17 nH, capable o f producing any stable inductance from 0.88 nH to 18.2 nH. Each of the six designs can be modeled by the complete small-signal model depicted in Fig. 52 and simplified in Fig. 53, with values for the simplified elements given in (138- 148). Expressions for Ro, Re, Co, Cf, and Le are offered in (149-153), respectively. In addition, all designs operate from a single 2.5 V supply and are simulated in SPICE using 2.5 V transistor parameters (BSIM3v3.2) from a standard 0.13 pm Si CMOS process. Section 2.3 also specifies that the die area of each design must be at least 10 times smaller than that of a comparable spiral inductor. The die areas of the gyrator inductors are estimated based on the gate area of each transistor. For transistors with aspect ratios (W/L) less than or equal to 10, the source and drain areas are each assumed to be twice the area of the gate. For aspect ratios greater than 10, the source and drain areas are each assumed to be 1.5 times the area of the gate. The total area is then increased an additional 25% to account for interconnects. The resulting gyrator die areas are then compared to the areas o f comparable planar spiral inductors. The die areas of spiral inductors are calculated from (1), using inductance values equal to the nominal inductances of the six tunable gyrator inductors. 143 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 7.4.1 Design One: A Cascode Gyrator Inductor Tunable from 10.4-18.2 nH. The first cascode gyrator inductor to meet all performance specifications is the gyrator already discussed in Section 7.3 and depicted again in Fig. 54. As indicated earlier, this gyrator is designed with gm \ = 1 mS and g m2 = 2 mS. Bias currents are Idi =123 pA and U2 - 554 pA, generating node voltages of 0.7 V, 1.6 V, and 1.2 V for nodes 1, 2, and 3, respectively. r 1A 0.56 G1A M — 1V12 0.28 r 1 1 TUNE 1.2 — M 0.28 1 — M 0.56 m 2 Fig. 54. Design One: A Cascode Gyrator Inductor Tunable from 10.4-18.2 nH. With V g t u n e = 0 V, a SPICE operating point analysis was used to extract parameter values and calculate theoretical values for Ro, Re, Co, Cf, and Le from equations (149- 153). Using these extracted parameter values, the output resistance from (149) is found to be 92.4 KQ, and the series resistance from (150) is found to be 5.3 Q. Simulations 144 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. from SPICE report a low-frequency series resistance of 5.5 Q, producing an error of only 3.8%. From (151), the effective output capacitance is calculated to be 8.3 fF, and from (152) the effective feedback capacitance is calculated to be 10.1 fF. Using these values in (153) yields an inductance of 9.1 nH. Again, simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance of 9.4 nH for an error of only 3.3%. The frequency responses o f Le and Q for Design One are shown in Fig. 55 for several values of V g t u n e • With V g t u n e = 0 V, the inductance is 9.7 nH at 800 MHz and 11 nH at 2 GHz, giving a nominal inductance, L„om , of 10.35 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies only ± 6.3%. Simulations also report that Q is 20 at 800 MHz, is a maximum of ~ 11,000 at 1.1 GHz, and decreases to 10 at 2 GHz. 145 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 60n § 50n ^ 40n I 30n 800 MHz-2 GHz / / 5 20n 10n 0 50 ITT ' If T I 40 30 20 $00 MHz -2 GHz 10 0 V =1 5 V GTUNE J V =1 4 V Y GTUNE V =/ 3 V GTUNE V =1 I V Y GTUNE V = o o v V GTUNE '• V =1 5 V GTUNE V =1 4 V Y GTUNE ' V =1 3 V Y GTUNE Y V =1 1 V r GTUNE ■ V = o o v r GTUNE u -u 10° Fig. 55. 10* F requency (Hz) 10 10 Frequency Responses of Le and Q for Design One with Different Values of V g t u n e • The Nominal Inductance is Tunable from 10.4-18.2 nH and Q ^ 10 for Signal Frequencies Between 800 MHz and 2 GHz. With the inductor tuned to its maximum value using V g t u n e = 1.5 V, I c i t u n e becomes 73 (iA, and Idi is reduced from 123 pA to 50 pA. This reduces gm i from 1.0 mS to 0.62 mS, increasing Le. An operating point analysis was used again to extract relevant parameter values. Using these newly extracted parameter values, Ro from (149) is found to be 88.0 K fi, and Re from (150) is found to be 9.1 Q. Simulations from SPICE report a low-frequency series resistance of 8.7 Q, producing an error of 4.4%. From 146 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. (151), Co is calculated to be 8.5 fF, and from (152) O is calculated to be 10.1 fF. Using these values in (153) yields an inductance of 14.9 nH. Again, simulations match theoretical calculations reasonably well as SPICE predicts a low-frequency inductance of 16.2 nH for an error of 8.7%. It should be noted that as V g t u n e is varied from 0 to 1.5 V, both g m 2 and the capacitance sum, Co + C>, change less than 1%. The sole cause of the variable inductance, therefore, is due to gm i changing from 1.0 mS to 0.6 mS, as designed. For V g t u n e = 1.5 V, Le increases to 16.7 nH at 800 MHz and 19.7 nH at 2 GHz, giving a nominal inductance of 18.2 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies only ± 8.2%. Simulations also reveal that Q is 10 at 800 MHz, is a maximum of 22 at 1.7 GHz, and decreases to 20 at 2 GHz. The nominal inductance can be tuned to any value between 10.4 and 18.2 nH, but once established, remains within ± 8.2% of the chosen inductance for frequencies between 800 MHz and 2 GHz. Selecting a nominal inductance of Ln o m = 14.3 nH (in the middle of the tuning range), gives a tunable range of ±27% . Thus, the tuning range specification of at least + 20% is satisfied. The power consumption for all values of V g t u n e is only 1.7 mW, far less than the specified maximum of 10 mW. 147 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 2 summarizes the performance of Design One and compares simulated results to the research objectives established in Section 2.3. In the table, the die area of a comparable planar spiral inductor is calculated from (1) with n = 12, r = 125 pm, and a = 63 pm. This gives a spiral inductance of Ls = 14.4 nH, very close to the nominal gyrator inductance o f Ln o m =14.3 nH. Frequency Range 800 MHz- 2 GHz 800 MHz- 2 GHz Pass Stable Inductance Within + 15% of Ln o m ± 8.2% of Lnom Pass Q > 10 10-11,000 Pass Tunable Inductance At least ± 20% of Ln o m ± 27% of L„o m Pass Supply Voltage 1.2 V -2 .5 V 2.5 V Pass Power Consumption < 10 mW 1.7 mW Pass Die Area Less than 1/10* the Area of a Comparable Spiral * 17543t h the Area. See Below ** Pass * Spiral Area (Ls = 14.4 nH) is 250 pm x 250 pm = 62.5 nm2 ** Gyrator Area (L n o m = 14.3 nH) is 10.7 pm x 10.7 pm = 0.115 nm2 Table 2. Performance Summary for Design One. The Inductance is Tunable from 10.4 to 18.2 nH, with L„o m = 14.3 nH. In summary, Design One satisfies all specifications outlined in Sections 2.3.1 through 2.3.7. 7.4.2 Design Two: A Cascode Gyrator Inductor Tunable from 7.25-11.4 nH. Design Two uses larger values of gm i and g m2 to provide a lower inductance range than Design One. The complete inductor, with gm i = 1 .6 mS and g m2 = 2.6 mS, is shown in Fig. 56. To achieve larger transconductances, bias currents are increased to Idi =193 148 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. pA and I& = 700 pA, yet node voltages of 0.7 V, 1.6 V, and 1.2 V for nodes 1, 2, and 3, respectively, remain unchanged. 1A 0.56 G1A M — J I 2 0.28 3 0.56 r 1A TUNE 1.2 — M 0.28 1 — M 0.56 W12 Fig. 56. Design Two: A Cascode Gyrator Inductor Tunable from 7.25-11.4 nH. With V g t u n e = 0 V, a SPICE operating point analysis was used to extract parameter values and calculate theoretical values for Ro, Re, Co, Cf, and Le from equations (149- 153). Using these extracted parameter values, the output resistance from (149) is found to be 55.6 KQ, and the series resistance from (150) is found to be 4.2 Q. Simulations from SPICE report a low-frequency series resistance of 4.2 Q, producing 0% error. From (151), the effective output capacitance is calculated to be 13.1 fF, and from (152) the effective feedback capacitance is calculated to be 13.8 fF. Using these values in (153) yields an inductance of 6.2 nH. Again, simulations match theoretical 149 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. calculations very well as SPICE predicts a low-frequency inductance of 6.6 nH for an error of 6.5%. The frequency responses o f Le and Q for Design Two are shown in Fig. 57 for several values of V g t u n e • With V g t u n e = 0 V, the inductance is 6.8 nH at 800 MHz and 7.7 nH at 2 GHz, giving a nominal inductance, Ln o m , of 7.25 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies only + 6.2%. Simulations also report that Q is 17 at 800 MHz, is a maximum of ~ 60,000 at 1.1 GHz, and decreases to 10 at 2 GHz. 150 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 40n 30n 800 MHz -2 GHz M 20n V =1 5 V y GTUNE V =14 V y GTUNE l ' ^ y V =1 3 V y GTUNE V =1 1 V y GTUNE 1 V =0 0 V y GTUNE Ol c S o £ Q a Q) 50 40 30 20 10 0 ! i ! ! l ! ! 1 :i\r \ l i ! i i i ; ! 1 ! ' / : \ ■ i ) ■ ■ i i i | 1 f ' j l \ v 1 ' ; i • 2 1 i ' V r ' i ; • i » : I i i / • ' / \.y I i • 1 • 1 i i , i t / / f t / / \ • . / \ % \ l l t i ■ i 1 800 MHz-:1 sjttz '/* / / \ N \ \ , < 1 ! I & \ - \ f . , v \ S \ \ V =1 5 V y GTUNE V =1 4 V y GTUNE 1^t y V =1 3 V r GTUNE V =11 V y GTUNE 1 1 y V =0 0 V y GTUNE U U y 10c 10s F requency (Hz) 10 10 Fig. 57. Frequency Responses of Le and Q for Design Two with Different Values of V g t u n e • The Nominal Inductance is Tunable from 7.25-11.4 nH and Q>. 10 for Signal Frequencies Between 800 MHz and 2 GHz. With the inductor tuned to its maximum value using V g t u n e = 1.5 V, I < itu n e becomes 93 pA, and Idi is reduced from 193 pA to 100 pA. This reduces gmi from 1.6 mS to 1.2 mS, increasing L e. An operating point analysis was used again to extract relevant parameter values. Using these newly extracted parameter values, Ro from (149) is found to be 48.8 KQ, and Re from (150) is found to be 6.7 Q. Simulations from SPICE report a low-frequency series resistance of 6.2 Q, producing an error of 7.5%. From 151 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. (151), Co is calculated to be 13.6 fF, and from (152) Cf is calculated to be 13.8 fF. Using these values in (153) yields an inductance o f 8.9 nH. Simulations match theoretical calculations fairly well as SPICE predicts a low-frequency inductance of 10.2 nH for an error of 14%. It should be noted again that as V g t u n e is varied from 0 to 1.5 V, g m 2 changes less than 1%, and the capacitance sum, Co + Cf, changes only 1.5%. The principal cause of the variable inductance, therefore, is due to gm i changing from 1.6 mS to 1.2 mS, as designed. For Vg t u n e = 1.5 V, L e increases to 10.5 nH at 800 MHz and 12.2 nH at 2 GHz, giving a nominal inductance of 11.35 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies only ± 7.5%. Simulations also reveal that Q is 10 at 800 MHz, is a maximum of 28 at 1.9 GHz, and decreases to 27 at 2 GHz. The nominal inductance can be tuned to any value between 7.25 and 11.35 nH, but once established, remains within ± 7.5% of the chosen inductance for frequencies between 800 MHz and 2 GHz. Selecting a nominal inductance of L nom = 9.30 nH (in the middle of the tuning range), gives a tunable range of ± 22%. Thus, the tuning range specification of at least ± 20% is satisfied. 152 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The power consumption for all values of V g t u n e is just 2.2 mW, far less than the specified maximum of 10 mW. Table 3 summarizes the performance of Design Two and compares simulated results to the research objectives established in Section 2.3. In the table, the die area of a comparable planar spiral inductor is calculated from (1) with n = 11, r= 115 pm, and a = 54 pm. This gives a spiral inductance of Ls = 9.37 nH, very close to the nominal gyrator inductance of Ln o m = 9.30 nH. a ft? " * “ t'd . ’ • .Phss&aifc? Frequency Range 800 MHz- 2 GHz 800 MHz- 2 GHz Pass Stable Inductance Within ± 15% of Ln o m + 7.5% of Ln o m Pass Q > 10 10-60,000 Pass Tunable Inductance At least ± 20% of L n o m ± 22% of L „o m Pass Supply Voltage 1.2 V -2 .5 V 2.5 V Pass Power Consumption < 10 mW 2.2 mW Pass Die Area Less than 1/10* the Area of a Comparable Spiral * 1/333* the Area. See Below ** Pass * Spiral Area (Ls = 9.37 nH) is 230 pm x 230 pm = 52.9 nm2 ** Gyrator Area (Ln o m = 9.30 nH) is 12.6 pm x 12.6 pm = 0.159 nm Table 3. Performance Summary for Design Two. The Inductance is Tunable from 7.25 to 11.4 nH, with L nom = 9.30 nH. Like Design One, Design Two satisfies all specifications outlined in Sections 2.3.1 through 2.3.7. 153 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 7.4.3 Design Three: A Cascode Gyrator Inductor Tunable from 4.75-8.15 nH. Design Three generates the next lower inductance range using gm j = 2 mS and g m2 = 4 mS, and is shown in Fig. 58. Bias currents are increased again to Idi = 251 pA and = 1.41 mA, yet node voltages o f 0.7 V, 1.6 V, and 1.2 V for nodes 1, 2, and 3, respectively, again remain unchanged. 1A 0.56 G1A r A i 3 0.56 r L L TUNE 0.56 — M 0.28 1 — M 0.56 2 =1.2 V G2A Fig. 58. Design Three: A Cascode Gyrator Inductor Tunable from 4.75-8.15 nH. With V g t u n e = 0 V, a SPICE operating point analysis was used to extract parameter values and calculate theoretical values for R o, R e, Co, Cf, and Le from equations (149- 153). Using these extracted parameter values, the output resistance from (149) is found to be 45.2 KQ, and the series resistance from (150) is found to be 2.6 Q. Simulations from SPICE report a low-frequency series resistance of 2.7 Q, producing an error of 154 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.8%. From (151), the effective output capacitance is calculated to be 16.8 fF, and from (152) the effective feedback capacitance is calculated to be 20.1 fF. Using these values in (153) yields an inductance of 4.3 nH. Again, simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance o f 4.4 nH for an error of just 2.3%. The frequency responses of Le and Q for Design Three are shown in Fig. 59 for several values of V g t u n e - With V g t u n e = 0 V, the inductance is 4.5 nH at 800 MHz and 5.0 nH at 2 GHz, giving a nominal inductance, L„om , of 4.75 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies only ± 5.3%. Simulations also report that Q is 17 at 800 MHz, is a maximum o f ~ 14,000 at 1.1 GHz, and decreases to 11 at 2 GHz. 155 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 25n 800 MHz-2 GHz 50 40 30 O) C £ 20 a s O) 10 0 10' , / li 1 1 1 1 h'\\r li i * • i 1 1 i ; c < 1 \ \ i \ li :: 1 l ! p \ i i • 1 1 h i /■ \ \ I - 1 : j 1 » t 7 / ' \ N . \ l; i l 1 1 / ' \ '' A- 1 1 ! 1 1 800MHz- 2 GHI V \ \ , y 1 / » \i\ 1 \ \ ' \ \ ; \ \v V o * c s ,8 10s F requency (Hz) 10 10 V =1 5 V y GTUNE 1 J r V =1 4 V r GTUNE — • V. GTUNE =1.3 V V =1 1 V v GTUNE . . . . v GTUNE =0.0 V V =1 5 V r GTUNE V = 14 V r GTUNE V =1 3 V r GTUNE J V =1 1 V r GTUNE 1 1 V = o o v r GTUNE Fig. 59. Frequency Responses of L e and Q for Design Three with Different Values of V g t u n e • The Nominal Inductance is Tunable from 4.75-8.15 nH and Q ^ 10 for Signal Frequencies Between 800 MHz and 2 GHz. With the inductor tuned to its maximum value using V g t u n e = 1.5 V, U t u n e becomes 153 (j,A, and Idi is reduced from 251 (iA to 100 (jA. This reduces gm i from 2 mS to 1.2 mS, increasing Le. An operating point analysis was used again to extract relevant parameter values. Using these newly extracted parameter values, Ro from (149) is found to be 49.4 KQ, and Re from (150) is found to be 3.9 Q. Simulations from SPICE report a low-frequency series resistance of 3.9 Q, producing 0% error. From (151), Co 156 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. is calculated to be 16.9 fF, and from (152) CF is calculated to be 20.1 fF. Using these values in (153) yields an inductance of 7.1 nH. Simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance of 7.3 nH for an error of just 2.8%. Like Design One, as V g t u n e is varied from 0 to 1.5 V, both g m2 and the capacitance sum, Co + Cp, change less than 1%. The principal cause of the variable inductance, therefore, is due to gm j changing from 2 mS to 1.2 mS, as designed. For V g t u n e = 1.5 V, Le increases to 7.5 nH at 800 MHz and 8.8 nH at 2 GHz, giving a nominal inductance o f 8.15 nH at 1.5 GHz. Over the frequency range o f 800 MHz to 2 GHz, this nominal inductance varies only ± 8%. Simulations also reveal that Q is 12 at 800 MHz, is a maximum o f 42 at 1.9 GHz, and decreases to 41 at 2 GHz. The nominal inductance can be tuned to any value between 4.75 and 8.15 nH, but once established, remains within ± 8% of the chosen inductance for frequencies between 800 MHz and 2 GHz. Selecting a nominal inductance of L„o m - 6.45 nH (in the middle of the tuning range), gives a tunable range of ± 26%. Thus, the tuning range specification of at least + 20% is satisfied. The power consumption with V g t u n e = 0 V is 4.2 mW, and decreases slightly to 4.1 mW for V g t u n e = 1.5 V. 157 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 4 summarizes the performance of Design Three and compares simulated results to the research objectives established in Section 2.3. In the table, the die area of a comparable planar spiral inductor is calculated from (1) with n = 9, r - 100 pm, and a = 50 pm. This gives a spiral inductance of Ls = 6.36 nH, close to the nominal gyrator inductance of L„o m - 6.45 nH. Frequency Range 800 MHz- 2 GHz 800 MHz- 2 GHz Pass Stable Inductance Within ± 15% of Ln o m ± 8.0% of L„o m Pass Q > 10 11-14,000 Pass Tunable Inductance At least ± 20% of Ln o m ± 26% of Ln o m Pass Supply Voltage 1.2 V-2.5 V 2.5 V Pass Power Consumption < 10 mW 4.2 mW Pass Die Area Less than 1/10* the Area of a Comparable Spiral * 17237t h the Area. See Below ** Pass * Spiral Area (Ls = 6.36 nH) is 200 pm x 200 pm = 40.0 nm2 ** Gyrator Area (L „o m = 6.45 nH) is 13.0 pm x 13.0 pm = 0.169 nm2 Table 4. Performance Summary for Design Three. The Inductance is Tunable from 4.75 to 8.15 nH, with Ln o m = 6.45 nH. Like the previous designs, Design Three satisfies all specifications outlined in Sections 2.3.1 through 2.3.7. 7.4.4 Design Four: A Cascode Gyrator Inductor Tunable from 2.90-5.43 nH. Design Four delivers the next lower inductance range using gm i = 2.5 mS and gm2 = 10 mS, and is shown in Fig. 60. As recommended in the design guidelines of Section 6.4, g m2 is increased much more than gm i to synthesize smaller inductances. Increasing gm i by increasing Idi will reduce rQ \ and lower Q, but increasing g m2 with larger I& has little 158 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. effect on Q . Thus, I d i is increased only slightly to 312 pA, while I d 2 is more than doubled to 3.00 mA. The node and bias voltages are also changed to accommodate the larger currents. The gate-source voltage o f Mia, Vgsu , is increased from 1.2 V to 1.4 V to help minimize the gate width of M u- To accomplish this, Vqia is reduced from 1.3 V to 1.1 V. Likewise, Vg2a (and hence, Vg S 2A), is increased from 1.2 V to 1.4 V. In addition, the drain-source voltage of M3, Vds3, is increased from 0.4 V to 0.6 V to increase ro3. Keeping V gs3 at 1 V, Vg3 is reduced from 2.2 V to 2.0 V, and node 3 is reduced from 1.2 V to 1 V. Nodes 1 and 2 remain unchanged at 0.7 V and 1.6 V, respectively. !A 0.56 G1A 2 0.28 V„=2 V 3 0.56 r UL TUNE 0.56 — M 0.28 1 Z. (s) W ' ' — M 0.56 2A G2A Fig. 60. Design Four: A Cascode Gyrator Inductor Tunable from 2.90-5.43 nH. 159 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. With V g t u n e — 0 V, & SPICE operating point analysis was used to extract parameter values and calculate theoretical values for Ro, Re, Co, Cf, and Le from equations (149- 153). Using these extracted parameter values, the output resistance from (149) is found to be 33.8 KQ, and the series resistance from (150) is found to be 1.15 Q. Simulations from SPICE report a low-frequency series resistance of 1.21 Q, producing an error of 5.2%. From (151), the effective output capacitance is calculated to be 21.5 fF, and from (152) the effective feedback capacitance is calculated to be 47.5 fF. Using these values in (153) yields an inductance of 2.67 nH. Again, simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance of 2.68 nH for an error of only 0.4%. The frequency responses of Le and Q for Design Four are shown in Fig. 61 for several values of V g t u n e • With V g t u n e = 0 V, the inductance is 2.7 nH at 800 MHz and 3.1 nH at 2 GHz, giving a nominal inductance, L„o m , of 2.90 nH at 1.5 GHz. Over the frequency range o f 800 MHz to 2 GHz, this nominal inductance varies ± 6.9%. Simulations also report that Q is 30 at 800 MHz, is a maximum of ~ 18,000 at 1 GHz, and decreases to 12 at 2 GHz. 160 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. O) c s o t§ a a Ol 50 40 30 20 10 0 10n 800 MHz-2 GHz O K a V =7 5 V GTUNE V =1 4 V Y GTUNE V =1 3 V GTUNE V =1 1 V GTUNE V = o o v v GTUNE v u y / . i ' 1 / i ; i ( c > i . | : ! ( 1 / i * \ r 1 t . / I I ; 1 i i l l I / 1 / “ \ \ \ 1 , i 1 : 1 1 1 i i / \ \ I \ , i !- 1 1 1 ’ •1 1 1 / \ \ V \ \ \ •1 i / > t / \ 1 / \ ft 800 MHz -2 GHz y , V s \ A \ \ \ S . ' \ N V =1 5 V V GTUNE 1 " J Y V =7 4 V GTUNE ^GTUNE V V =1 1 V Y GTUNE 1 1 V -0 0 V V GTUNE 10 Fig. 61. 109 F requency (Hz) 10 10 Frequency Responses of Le and Q for Design Four with Different Values of V g t u n e • The Nominal Inductance is Tunable from 2.90-5.43 nH and Q > 10 for Signal Frequencies Between 800 MHz and 2 GHz. With the inductor tuned to its maximum value using V g t u n e = 1.5 V, F t u n e becomes 211 (J.A, and Idi is reduced from 312 \xA to 104 pA. This reduces gm i from 2.5 mS to 1.4 mS, increasing Le. An operating point analysis was used again to extract relevant parameter values. Using these newly extracted parameter values, Ro from (149) is found to be 42.7 KQ, and Re from (150) is found to be 1.69 Q. Simulations from SPICE report a low-frequency series resistance of 1.72 Q, producing an error of only 161 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1.8%. From (151), Co is calculated to be 21.5 fF, and from (152) Cf is calculated to be 47.4 fF. Using these values in (153) yields an inductance o f 4.96 nH. Simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance of 4.82 nH for an error of only 2.8%. Like in previous designs, as V g t u n e is varied from 0 to 1.5 V, both g m2 and the capacitance sum, Co + Cf, change less than 1%. The principal cause of the variable inductance, therefore, is due to gm i changing from 2.5 mS to 1.4 mS, as designed. For V g t u n e = 1.5 V, Le increases to 5.0 nH at 800 MHz and 5.85 nH at 2 GHz, giving a nominal inductance of 5.43 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies only ± 7.8%. Simulations also reveal that Q is 14 at 800 MHz, is a maximum of 19 at 1.4 GHz, and decreases to 13 at 2 GHz. The nominal inductance can be tuned to any value between 2.90 and 5.43 nH, but once established, remains within ± 7.8% of the chosen inductance for frequencies between 800 MHz and 2 GHz. Selecting a nominal inductance of Ln o m = 4.16 nH (in the middle of the tuning range), gives a tunable range of ± 30%. Thus, the tuning range specification of at least ± 20% is satisfied. The power consumption with V g t u n e = 0 V is 8.3 mW, and decreases slightly to 8.1 mW for V g t u n e = 1.5 V. 162 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 5 summarizes the performance of Design Four and compares simulated results to the research objectives established in Section 2.3. In the table, the die area o f a comparable planar spiral inductor is calculated from (1) with n = 8, r = 80 pm, and a = 41 nm. This gives a spiral inductance of Ls = 4.28 nH, near the nominal gyrator inductance of Ln o m = 4.16 nH. P u n s t e r .' ‘ - - I .- Pass/Fail? Frequency Range 800 MHz- 2 GHz 800 MHz- 2 GHz Pass Stable Inductance Within ± 15% of L„o m ± 7.8% ofL„o m Pass Q > 10 12-18,000 Pass Tunable Inductance At least ± 20% of Ln o m ± 30% of Ln o m Pass Supply Voltage 1.2 V - 2.5 V 2.5 V Pass Power Consumption < 10 mW 8.3 mW Pass Die Area Less than 1710th the Area of a Comparable Spiral * 1/114th the Area. See Below ** Pass * Spiral Area {Ls = 4.28 nH) is 160 pm x 160 pm = 25.6 nm2 ** Gyrator Area (L„o m = 4.16 nH) is 15.0 pm x 15.0 pm = 0.225 nm2 Table 5. Performance Summary for Design Four. The Inductance is Tunable from 2.90 to 5.43 nH, with Ln o m = 4.16 nH. Like the previous three designs, Design Four satisfies all specifications outlined in Sections 2.3.1 through 2.3.7. 7.4.5 Design Five: A Cascode Gyrator Inductor Tunable from 1.57-3.30 nH. Design Five produces the next lower inductance range using gm j = 5 mS and g m2 = 15 mS, and is shown in Fig. 62. Bias currents are increased once more to I< ti = 665 pA and Id2 = 4.51 mA, with node and bias voltages identical to those o f Design Four. 163 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1A 0.56 G1A 3 0.56 r JJ- TUNE 0.56 — M 0.28 1V11 Fig. 62. Design Five: A Cascode Gyrator Inductor Tunable from 1.57-3.30 nH. With V g t u n e = 0 V , a SPICE operating point analysis was used to extract parameter values and calculate theoretical values for Ro, Re, Co, C f, and Le from equations (149- 153). Using these extracted parameter values, the output resistance from (149) is found to be 15.9 KQ, and the series resistance from (150) is found to be 842 mQ. Simulations from SPICE report a low-frequency series resistance of 890 mQ, producing an error of 6%. From (151), the effective output capacitance is calculated to be 38.1 fF, and from (152) the effective feedback capacitance is calculated to be 70.5 fF. Using these values in (153) yields an inductance of 1.45 nH. Again, simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance of 1.47 nH for an error o f just 1.4%. 164 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The frequency responses of Le and Q for Design Five are shown in Fig. 63 for several values of Vgtune• With Vgtune = 0 V, the inductance is 1.49 nH at 800 MHz and 1.65 nH at 2 GHz, giving a nominal inductance, L„om , of 1.57 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies ±5.1% . Simulations also report that Q is 17 at 800 MHz, is a maximum of ~ 10,000 at 1.2 GHz, and decreases to 12 at 2 GHz. o T o R a -S ^3 O) a £ 50 40 30 20 <3 3 O) 10 0 10' 6n 800 MHz-2 GHz 5n 4n 3n 2n 1n 0 t • 1 I ! ■pr ■ i h ! \ 1 ■ 1 , I »i j i I ■ i i ' > 1 • i 11 E i / i / y . \ / i [ i [ i ii \ a i 1 1 1 t r \ » , i i 1 1 1 8 0 0 A{ H z - 2 < JH, h ' \ \ \ \ \ 3 * 1 < 1 * - v '• 1 \ M i . - v V I 1 \ . \ ----- -------- \ ,8 109 F requency (Hz) 10 10 V =1 5 V r GTUNE V =7 4 V y GTUNE ^ y V =7 3 V y GTUNE V =1 1 V r GTUNE 1 1 r V =0 0 V GTUNE 1 V =1 5 V y GTUNE V = 14 V y GTUNE V =1 3 V y GTUNE V =1 1 V y GTUNE . . . . y GTUNE --o.ov Fig. 63. Frequency Responses of Le and Q for Design Five with Different Values of V g t u n e • The Nominal Inductance is Tunable from 1.57-3.30 nH and Q ^ 10 for Signal Frequencies Between 800 MHz and 2 GHz. 165 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. With the inductor tuned to its maximum value using V g t u n e - 1.5 V, U t u n e becomes 494 (J.A, and Idi is reduced from 665 pA to 178 pA. This reduces gm \ from 5 mS to 2.4 mS, increasing Le. An operating point analysis was used again to extract relevant parameter values. Using these newly extracted parameter values, Ro from (149) is found to be 21.0 KQ, and Re from (150) is found to be 1.33 Q. Simulations from SPICE report a low-frequency series resistance of 1.34 Q, producing an error of just 0.8%. From (151), Co is calculated to be 38.1 fF, and from (152) C f is calculated to be 70.7 fF. Using these values in (153) yields an inductance of 3.04 nH. Simulations match theoretical calculations well as SPICE predicts a low-frequency inductance of 2.94 nH for an error o f 3.3%. Once again, as V g t u n e is varied from 0 to 1.5 V, both g m2 and the capacitance sum, C o + Cf, change less than 1%. The principal cause of the variable inductance, therefore, is due to gmi changing from 5 mS to 2.4 mS, as designed. For V g t u n e = 1.5 V, Le increases to 3.04 nH at 800 MHz and 3.55 nH at 2 GHz, giving a nominal inductance of 3.30 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies just ± 7.7%. Simulations also reveal that Q is 11 at 800 MHz, is a maximum of 14 at 1.4 GHz, and decreases to 11 at 2 GHz. The nominal inductance can be tuned to any value between 1.57 and 3.30 nH, but once established, remains within ± 7.7% of the chosen inductance for frequencies between 166 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 800 MHz and 2 GHz. Selecting a nominal inductance of L„o m = 2.43 nH (in the middle of the tuning range), gives a tunable range of ± 35%. Thus, the tuning range specification o f at least ± 20% is easily satisfied. The power consumption with V g t u n e = 0 V is 12.9 mW, and decreases slightly to 12.6 mW for V g t u n e = 1.5 V. Both values exceed the maximum power specification of 10 mW. Table 6 summarizes the performance of Design Five and compares simulated results to the research objectives established in Section 2.3. In the table, the die area of a comparable planar spiral inductor is calculated from (1) with n = 7, r = 60 pm, and a = 30 pm. This gives a spiral inductance of Ls = 2.31 nH, very close to the nominal gyrator inductance o f L„o m = 2.43 nH. Frequency Range 800 MHz- 2 GHz 800 MHz- 2 GHz Pass Stable Inductance Within ± 15% of L„o m + 7.7% O f Lnom Pass Q > 10 11-10,000 Pass Tunable Inductance At least ± 20% of L„o m ± 35% of Ln o m Pass Supply Voltage 1.2 V - 2.5 V 2.5 V Pass Power Consumption < 10 mW 12.9 mW Fail Die Area Less than 1/10t h the Area of a Comparable Spiral * 1/38* the Area. See Below ** Pass * Spiral Area (Ls = 2.31 nH) is 120 pm x 120 pm = 14.4 nm2 ** Gyrator Area (L„om = 2.43 nH) is 19.5 pm x 19.5 pm = 0.380 nm2 Table 6. Performance Summary for Design Five. The Inductance is Tunable from 1.57 to 3.30 nH, with Ln o m = 2.43 nH. 167 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Thus, Design Five satisfies all specifications outlined in Section 2.3, with the exception of the power consumption specified in Section 2.3.7. 7.4.6 Design Six: A Cascode Gyrator Inductor Tunable from 0.88-1.70 nH. Design Six generates the smallest inductance range with gm i = 1 0 mS and g m2 = 20 mS, and is shown in Fig. 64. This design has the largest bias currents of Idi = 1 .4 mA and Id2 = 6.0 mA, with node and bias voltages identical to those of Designs Four and Five. 1A 0.56 G1A 2 0.28 3 0.56 TUNE 0.56 — M 0.28 1 h* V G 2A = '-4 v 0.56 Fig. 64. Design Six: A Cascode Gyrator Inductor Tunable from 0.88-1.70 nH. With V g t u n e = 0 V, a SPICE operating point analysis was used to extract parameter values and calculate theoretical values for Ro, Re, Co, Cf, and Le from equations (149- 153). Using these extracted parameter values, the output resistance from (149) is found 168 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. to be 7.6 KQ, and the series resistance from (150) is found to be 651 mQ. Simulations from SPICE report a low-frequency series resistance of 689 mQ, producing an error of 5.8%. From (151), the effective output capacitance is calculated to be 67.8 fF, and from (152) the effective feedback capacitance is calculated to be 97.2 fF. Using these values in (153) yields an inductance of 816 pH. Again, simulations match theoretical calculations very well as SPICE predicts a low-frequency inductance of 821 pH for an error of only 0.6%. The frequency responses of Le and Q for Design Six are shown in Fig. 65 for several values of V g t u n e • With V g t u n e = 0 V, the inductance is 836 pH at 800 MHz and 920 pH at 2 GHz, giving a nominal inductance, L„o m , of 878 pH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies ± 4.8%. Simulations also report that Q is 10 at 800 MHz, is a maximum o f ~ 10,000 at 1.3 GHz, and decreases to 11 at 2 GHz. 169 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4n 800 MHz-2 GHz K 5 O) c S £ a 3 O) 50 40 30 20 10 I i i i 1 i i :• ii !• 1 > 1 i ' ;; i| » n / \ 'i . • / * 1 I | i • • 1 !>' : jl S ' ! 1 i i 'I ; 11 k x V 1 i ! 1 S t ) ! / t \ j h ~ / ~ -------V - T i \\ 1 — R a n M H * - ? c * n a - i n ' t V / N / v*. A ---------\ i 1; i V > ' s . \ . \ 4 - V ' V - V ■ > 1 • i ' rs ?4* V =1 5 V Y GTUNE V =7 4 V Y GTUNE V =1 3 V Y GTUNE Y V =1 1 V Y GTUNE V =0 0 V V GTUNE u u Y V =7 5 V Y GTUNE V =7 4 V Y GTUNE V =1 3 V Y GTUNE V =11 V Y GTUNE 1 1 Y V = o o v V GTUNE u u Y 10° Fig. 65. 10s F requency (Hz) 10 10 Frequency Responses of L e and Q for Design Six with Different Values of V g t u n e • The Nominal Inductance is Tunable from 0.88-1.70 nH and Q ^ 10 for Signal Frequencies Between 800 MHz and 2 GHz. With the inductor tuned to its maximum value using V g t u n e = 1.5 V, U t u n e becomes 1.0 mA, and Ui is reduced from 1.4 mA to 418 pA. This reduces gmi from 10 mS to 5.3 mS, increasing Le. An operating point analysis was used again to extract relevant parameter values. Using these newly extracted parameter values, Ro from (149) is found to be 10.0 KQ, and Re from (150) is found to be 951 mQ. Simulations from SPICE report a low-frequency series resistance of 965 mQ, producing an error of just 170 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1.5%. From (151), Co is calculated to be 67.8 fF, and from (152) Cf is calculated to be 96.8 fF. Using these values in (153) yields an inductance of 1.56 nH. Simulations match theoretical calculations well as SPICE predicts a low-frequency inductance of 1.53 nH for an error of only 1.9%. Once again, as V g t u n e is varied from 0 to 1.5 V, both g m2 and the capacitance sum, C o + Cf, change less than 1%. The principal cause of the variable inductance, therefore, is due to gm i changing from 10 mS to 5.3 mS, as designed. For V g t u n e = 1.5 V, Le increases to 1.57 nH at 800 MHz and 1.82 nH at 2 GHz, giving a nominal inductance o f 1.70 nH at 1.5 GHz. Over the frequency range of 800 MHz to 2 GHz, this nominal inductance varies just + 7.4%. Simulations also reveal that Q is 10 at 800 MHz and is a maximum of 42 at 2 GHz. The nominal inductance can be tuned to any value between 0.88 nH and 1.70 nH, but once established, remains within ± 7.4% of the chosen inductance for frequencies between 800 MHz and 2 GHz. Selecting a nominal inductance of Lnom = 1 -29 nH (in the middle of the tuning range), gives a tunable range of ± 32%. Thus, the tuning range specification of at least ± 20% is easily satisfied. 171 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The power consumption with V g t u n e = 0 V is 18.6 mW, and decreases slightly to 18.1 mW for V g t u n e = 1.5 V. Both values exceed the maximum power specification of 10 mW. Table 7 summarizes the performance of Design Six and compares simulated results to the research objectives established in Section 2.3. In the table, the die area of a comparable planar spiral inductor is calculated from (1) with n = 6, r = 50 pm, and a = 24 pm. This gives a spiral inductance of Ls - 1.28 nH, very close to the nominal gyrator inductance o f Ln o m = 1.29 nH. Frequency Range 800 MHz- 2 GHz 800 MHz- 2 GHz Pass Stable Inductance Within ± 15% of Ln o m ± 7.4% of L„o m Pass Q > 10 10-10,000 Pass Tunable Inductance At least ± 20% of L„o m ± 32% O iLnom Pass Supply Voltage 1.2 V -2 .5 V 2.5 V Pass Power Consumption < 10 mW 18.6 mW Fail Die Area Less than 1/10th the Area of a Comparable Spiral * 1/16th the Area. See Below ** Pass * Spiral Area (Ls = 1.28 nH) is 100 pm x 100 pm = 10.0 nm2 ** Gyrator Area (Ln o m = 1.29 nH) is 25.1 pm x 25.1 pm = 0.630 nm2 Table 7. Performance Summary for Design Six. The Inductance is Tunable from 0.88 to 1.70 nH, with Ln o m = 1.29 nH. Like Design Five, Design Six satisfies all specifications outlined in Section 2.3, with the exception of the power consumption specified in Section 2.3.7. 172 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 7.5 Inductor Suite Performance Summary Tables 2-7 reveal that the six cascode gyrator designs discussed in the preceding sections satisfy all performance specifications except one. The power consumption goal of no more than 10 mW is exceeded by Designs Five (with 12.9 mW) and Six (with 18.6 mW). It may seem counter-intuitive that the gyrators producing the smallest inductances consume the most power, but a review of (153) helps to explain why this is so. According to (153), small Le requires small Co + C f and large gm i and gm 2. Unfortunately, large transconductances require large currents as demonstrated in (118). Thus, the larger bias currents required to synthesize smaller inductances consume more power. All other specifications are satisfied by the six designs, and in most cases, satisfied by a very large margin. Overall, the inductances are twice as stable as specified, varying with frequency by only ± 7-8%, compared to the specification of ± 15%. Similarly, the average tuning range is ± 29%, much greater than the specified ± 20%. In addition, the die areas of the gyrator-based inductors are extremely small, between 16 and 543 times smaller than comparable planar spirals, while the specification is only 10 times smaller. And finally, although the specification of Q > 10 is satisfied for all inductance values over the wide frequency range of 800 MHz to 2 GHz, extremely large Qs can be generated for specific inductances or over smaller frequency ranges. For example, Design Four (with V g t u n e = 1.3 V and Ln o m = 3.9 nH) produces Q > 20 from 750 MHz 173 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. to 3.5 GHz; generates Q > 35 from 920 MHz to 3.3 GHz; and delivers Q > 100 from 1.1 GHz to 1.4 GHz. Similarly, Design Two (with Vgtune = 1.4 V and L nom = 1 0 nH) produces Q > 10 from 750 MHz to 3.8 GHz; generates Q > 40 from 1.3 GHz to 3.2 GHz; and delivers Q > 100 from 1.5 GHz to 3.0 GHz. The combined performance of the entire suite of six inductors is summarized and compared to the research objectives in Table 8. \ ' flil& ifS fn S lB r . ■ _ | ' P a ssJ -tfa lK ? Process Standard Si CMOS 0.13 pm Si CMOS Pass Frequency Range 800 MHz- 2 GHz 800 MHz- 2 GHz Pass Inductance Range 1 nHto 15 nH 0.88 nHto 18.2 nH Pass Tunable Inductance At least ± 20% of L „ o m ± 22-35% of L n o m Pass Stable Inductance Within + 15% of L n o m ± 7-8% of L n o m Pass Large Q > 10 10-60,000 Pass Supply Voltage 1.2 V - 2.5 V 2.5 V Pass Power < 10 mW One-Four: 1.7-8.3 mW One-Four: Pass Consumption Five-Six: 12.9-18.6 mW Five-Six: Fail Die Area Less than 1/10t h the Area of a Comparable Spiral 1/16* to 1/543* the Area Pass Table 8. Combined Performance Summary of the Suite of Six Inductors. As discussed earlier, each inductor has been designed such that its tunable inductance range overlaps with those of other designs. In this way, the suite o f six inductors has a combined tuning range of over 17 nH, capable of producing any stable inductance from 0.88 nH to 18.2 nH. Thus, the overall tuning range specification of 1-15 nH is satisfied. Fig. 66 displays the tuning range for each design, and graphically shows how the tuning ranges o f adjacent designs overlap to create a seamless range of available 174 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. inductances from 0.88 nH to 18.2 nH. The minimum, maximum, and nominal inductance values are given for each design in the figure. 20 — - 1 8 . 2 0 - 1 4 . 2 8 1 1 . 3 5 - 9 . 3 0 8 . 1 5 6 . 4 5 FT 5 4 3 - 4 . 1 6 3 . 3 0 2 . 4 3 1 . 5 7 1 . 7 0 E E 1 . 2 9 0.88 Design Design Design Design Design Design One Two Three Four Five Six Fig. 66. Inductor Tuning Ranges for Designs One Through Six. For Each Design, the Minimum, Maximum, and Nominal Inductances are Given Numerically, and the Tuning Range is Represented by a Vertical Bar. 175 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 8: Nonlinear Effects on Phase, Distortion, and Dynamic Range An inductor is ideally a linear device, producing a voltage, vl(0, between its two terminals that is proportional to the derivative of the current, ii(t), flowing through it. The proportionality constant is simply the inductance, L, as shown in (154). = (154) For sufficiently small sinusoidal signals, Designs One through Six produce inductances whose volt-ampere characteristics are described very nearly by the ideal relationship given in (154). For larger signals, however, the nonlinear behavior of transistors comprising the active inductors introduces non-ideal effects including phase errors between the terminal voltage and current, distortion in the output waveforms, and limited dynamic range. Although not specified in the research objectives of Chapter 2, these nonlinear effects should be measured and understood before a comprehensive analysis of the final designs can be considered complete. The methodology used to measure these effects is discussed in Section 8.1. The phase error is then measured in Section 8.2, followed by the total harmonic distortion (THD) and dynamic range in Section 8.3. It should be noted that the phase error discussion in Section 8.2 is not a standard metric of the performance of an inductor, and the phase error measurements were only taken 176 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. as an intermediate step while performing the FFT analysis required in Section 8.3. Although not a standard metric, the phase error analysis still provides a quantifiable assessment of the non-ideal phase relationship between large input currents and distorted output voltages. 8.1 Linearity Measurement Methodology Design Three is chosen to represent a typical inductor from the suite, producing inductances from 4.75-8.15 nH. To measure the phase error, distortion, and dynamic range, Design Three is first tuned to produce a nominal inductance of 5 nH at 1 GHz with V g t u n e = 1.05 V. A 1 GHz sine wave current source, Is, is then applied to node 1, and the resulting voltage from node 1 to ground is measured. A schematic diagram showing the circuit under test is given in Fig. 67. G1A 1A 0.56 M — 2 0.28 f M . 3 0.56 r J A . TUNE 0.56 iL(t) — M 0.28 1 0.56 2A Fig. 67. Linearity Measurement Schematic Diagram. 177 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. For a sine wave input current in the form o f = sin(atf), (155) the inductor should ideally produce a cosine wave output voltage in the form of in accordance with (154). For a current amplitude o f Im = 100 pA at 1 GHz, the resulting voltage amplitude with L = 5 nH is ideally Vm = 3.14 mV. Fig. 68 displays both the ideal and synthesized voltage responses for a 1 GHz sine wave input current with 100 pA amplitude. The DC voltage of node 1 (approximately 670 mV) has been subtracted from the synthesized signal displayed in Fig. 68. vi (0 = ^cos(©0. (156) where (157) 178 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 6m Synthesized 4m Ideal -2m -4m 0 0.25n 0.50n 0.75n 1.00n 1.25n 1.50n 1.75n 2.00n Time (s) Fig. 68. Ideal and Synthesized Voltage Responses of Design Three in Fig. 67 for a 1 GHz Sine Wave Input Current with 100 pA Amplitude. Fig. 68 indicates that the output voltage, vi(t), has an overshoot o f 86%, and then settles to a nearly perfect cosine wave in approximately 650 ps. After the transient has decayed, the amplitude of the steady-state output voltage is 3.14 mV, matching the ideal amplitude exactly. To determine the effects of larger input signals, the input amplitude is increased and the resulting nonlinear effects are measured in the following sections. 179 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 8.2 Phase Error To measure the phase error, the test circuit of Fig. 67 is used again with Design Three biased to produce L nom = 5 nH at 1 GHz. The amplitude of Is is now varied from 100 pA to 1 mA (in 100 pA steps), and the voltage at node 1 is measured for each value of Is. Voltage amplitudes (minus the DC component) range from ~ 3 mV (for Is = 100 pA), to ~ 30 mV (for Is = 1 mA). The steady-state voltage responses are shown in Fig. 69. The output waveforms are analyzed from 1.75-2.75 ns after the input is applied to exclude the effects o f the decaying transient. 30m 15m • / / .,/ - ••y. / /, -30m -45m 2.50n 2.75n 1.75n 2.00n 2.25n 1 mA - IM = 900 pA - IM = 800 pA - IM = 700 pA ^ = 6 ° ° p A - Iu = 500 pA - 7 M = 400pA - IM= 300 pA Iu = 200 pA - IM = 100 pA Time (s) Fig. 69. Voltage Responses of Design Three in Fig. 67 for a 1 GHz Sine Wave Input Current with Amplitudes from 100 pA to 1 mA. 180 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 69 shows that small current amplitudes produce small voltage amplitudes that are similar to ideal responses. For current inputs greater than 630 jiA (corresponding to voltage amplitudes greater than 20 mV), the sinusoidal output waves begin to differ substantially from ideal waves, especially for negative amplitudes. The phase of each voltage waveform in Fig. 69 is compared to the corresponding ideal waveform at the peak of the positive amplitude, and the resulting phase errors are plotted in Fig. 70. if £ a -C r a O 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Phase Error (Degrees) Fig. 70. Phase Errors for the Voltage Responses in Fig. 69. 181 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Fig. 70 indicates that voltage amplitudes of less than 20 mV produce phase errors of less than 9 degrees. 8.3 Total Harmonic Distortion and Dynamic Range The fast Fourier transform (FFT) is taken of each waveform in Fig. 69 (including the first eight harmonics), and the total harmonic distortion (THD) and dynamic range are measured for each output voltage. Three FFT responses are shown below in Figs. 71- 73 for input current amplitudes of 100 pA, 630 pA (corresponding to the maximum reasonably undistorted output voltage of 20 mV), and 1 mA, respectively. 4m Co ■ t-S 3m ■ K R 0 1 2 "f- <3 £ 1m l 3 1G 2G 3G 4G 5G 6G Frequency (Hz) 7G 8G 9G Fig. 71. FFT of the Voltage Waveform in Fig. 69 for Is with an Amplitude of 100 pA. 182 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 25m r c r , 2 0 m f - K i K K O 15mt ST ro O 10m- 5-. C O * h»A S k 3 5 m - £ 1G 2G 3G 4G 5G 6G 7G 8G 9G Frequency (Hz) Fig. 72. FFT of the Voltage Waveform in Fig. 69 for Is with an Amplitude of 630 pA. 40m ' 20m »3 I S 30m R C O R 0 1 <3 !< " »»»» . „ ^ 10m a £ 0 1G 2G 3G 4G 5G 6G 7G 8G 9G Frequency (Hz) Fig. 73. FFT of the Voltage Waveform in Fig. 69 for Is with an Amplitude of 1 mA. 183 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. A summary o f the output voltage, phase error, THD, and dynamic range for each value of input current amplitude is given in Table 9. 100 3.2 2.7 1.2 39 200 6.3 3.8 2.4 32 300 9.5 4.9 3.8 29 400 1 3 5.9 5.3 26 500 16 7.2 7.1 23 600 19 8.2 9.2 21 630 20 9.1 9.9 21 700 23 9.6 12 19 800 27 1 1 15 18 900 30 12 18 16 1000 35 1 3 23 14 * Including H arm onics Table 9. Linearity Summary of Design Three in Fig. 67. A review of Figs. 71-73 and Table 9 shows that for current amplitudes up to 630 pA, the fundamental signal and first harmonic contain most of the frequency content of the output voltage waveforms. At 630 pA, the THD is 9.9%, the output voltage amplitude is 20 mV, and the dynamic range is 21 dB. Thus, Design Three can process voltage swings up to 40 mV peak-to-peak, while maintaining THD less than 10%. 184 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 9: Applications of Tunable Cascode Gyrator Inductors The frequency response curves given in Chapter 7 for Designs One through Six show that even though the inductances are relatively constant between 800 MHz and 2 GHz, Le peaks sharply near 5 GHz. The damping can be increased to reduce this peaking, but Q suffers dramatically if done so. To determine if this high frequency peaking will impair the performance of the inductors in their operational frequency range of 800 MHz to 2 GHz, Design Three is used in two applications that operate at 1 GHz. An RL high-pass filter is implemented in Section 9.1, and an LC tank oscillator is implemented in Section 9.2. 9.1 RL High-Pass Filter Application Design Three is first tuned to produce a nominal inductance o f 5 nH at 1 GHz with V g t u n e = 1-05 V. It is then connected to an external series resistor, Rx, and a voltage source, Vs, to form the RL high-pass filter shown in Fig. 74 in which the output is taken at node 1. 185 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. ^ g t u n e Q J ) M — \ TUNE 0.56 — M 0.28 1 O R v + ^ A A n — M 0.56 2A / 'VG 2A =1-2V Fig. 74. /?L High-Pass Filter Application. With Le = 5 nH and i?* = 31.42 Q, the ideal cut-off frequency, f^B , is 1 GHz. An AC SPICE analysis of Fig. 74 produces - 1.017 GHz, for an error of only 1.7%. The normalized (Vj/Vs) ideal and synthesized frequency responses are shown in Fig. 75. 186 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1.25 1.00 Ideal, fm = 1.000 GHz SP0.75 Synthesizedf3 d B -1.017 GHz a 0.50 £ 0.25 — Synthesized •— Ideal Frequency (Hz) Fig. 75. RL High-Pass Filter Responses Using Ideal and Synthesized Inductors. If an input capacitance and series resistance are added to the ideal inductor, the ideal and synthesized responses are much more closely matched at high frequencies. The input capacitance, C„ can be calculated from Cio in (138) to be 38.3 fF, and forces the ideal response to drop to zero at high frequencies. The series resistance can be calculated from Re in (150) to be 2.8 Q, and causes the ideal response to increase slightly at low frequencies as a result of the voltage divider formed by Re and Rx- 187 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The values of these parasitics are quite low compared to parasitics of traditional planar spiral inductors. It is reported in [50] that a typical 7.5 nH spiral inductor has an input capacitance of 126 fF, and a series resistance of 8.2 Q. Thus, the gyrator-based inductor of Design Three will perform more similarly to an ideal inductor in this application than will a comparable planar spiral. The new ideal (including C; and Re) and synthesized frequency responses are shown in Fig. 76. 1.25 Synthesized Ideal 0.50 0.25 103 1 04 1 05 106 1 07 108 109 1 010 1011 1012 1 013 Frequency (Hz) Fig. 76. RL High-Pass Filter Responses Using Ideal (with Parasitics) and Synthesized Inductors. 188 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The cut-off frequency can be tuned by adjusting V g t u n e to any value between 0 and 1.5 V. Thus, fzdB can be as low as 730 MHz (for V g t u n e = 1.5 V and Ln o m = 8.15 nH) and as high as 1.096 GHz (for V g t u n e = 0 V and L„o m = 4.75 nH). Compared to an ideal inductor without any parasitics, the /mb error for L„o m = 8.15 nH is 16% (with actual /mb - 730 MHz and ideal /mb = 614 MHz), and the error for Lno m = 4.75 nH is 4% (with actual f 3d B = 1.096 GHz and ideal /mb - 1.052 GHz). If the parasitic elements, C, and Re, are added to the ideal inductor, the fidB error for Ln o m = 8.15 nH reduces to 9.6% (with actual /mb = 730 MHz and ideal f 3d B increasing to 660 MHz) and the error for Lnom = 4.75 nH is reduced to 3.1% (with actual f 3d B = 1.096 GHz and ideal increasing to 1.130 GHz). It should be noted that the high-pass filter presented in this section represents the worst-case filter application for the suite of gyrator inductors, in the sense that the high-pass function will pass any high-frequency peaking of the synthesized inductance. In conclusion, the gyrator-based inductor o f Design Three performs very well in the RL high-pass filter of Fig. 74 and offers a cut-off frequency that is tunable between 730 MHz and 1.096 GHz. In addition, because the parasitic input capacitance and series resistance of Design Three are smaller than those of a comparable spiral inductor, Design Three will perform more similarly to an ideal inductor in this application than will a comparable planar spiral. 189 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 9.2 LC Tank Oscillator Application Design Three is again tuned to produce a nominal inductance of 5 nH at 1 GHz with V g t u n e = 1 05 V. It is then connected to an external shunt capacitor, Cx, to form the LC tank oscillator shown in Fig. 77, in which the output is again taken at node 1. The current source, Is, is used in SPICE as an impulse function to excite oscillations. 1A 0.56 G1A r M - 3 0.56 r 1£ TUNE 0.56 — M 0.28 I 0.56 M 2A / I 1 * V G2A Fig. 77. LC Tank Oscillator Application. With Le= 5 nH and Cx= 5 pF, the ideal oscillation frequency,/,, is 1 GHz. A transient SPICE analysis o f Fig. 77 produces f a = 1.009 GHz, for an error of only 0.9%. The ideal and synthesized transient responses are shown in Fig. 78. 190 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 673.00rr S ' 672.80m ^3 ' K k Q 672.60m 5 * > £ • < » » a w * q> 672.40m 672.20m 4n Time (s) — Synthesized — Ideal Fig. 78. LC Tank Oscillator Using Ideal and Synthesized Inductors. If a series resistance is added to the ideal inductor (as in the RL high-pass filter), the ideal and synthesized responses are much more closely matched. At 1 GHz, the series resistance is found from SPICE to be only 0.74 Q. This small resistance introduces enough loss in the ideal circuit to reduce the amplitude of successive oscillations. The comparative results are given in Fig. 79. 191 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 673.00m Synthesized Ideal 672.80m 672.60m £ 'K k w * O 672.40m 672.20m 2n 6n 0 4n 8n Time (s) Fig. 79. LC Tank Oscillator Using Ideal (with Re = 0.74 Q) and Synthesized Inductors Like the cut-off frequency for the RL filter, the oscillation frequency can be tuned by adjusting V g t u n e to any value between 0 and 1.5 V. T hus,/, can be as low as 814 MHz (for V g t u n e = 1.5 V and Ln o m = 8.15 nH) and as high as 1.057 GHz (for V g t u n e = 0 V and Ln o m = 4.75 nH). Compared to an ideal inductor with Re = 0.74 Q, the / , error for Lnom = 8.15 nH is just 3.2% (with actual / = 814 MHz and id eal/, =788 MHz), and the error for L„o m = 4.75 nH is only 2.4% (with actual/ = 1.057 GHz and ideal/ , = 1.032 GHz). 192 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Again, the gyrator-based inductor of Design Three performs very well in the LC tank oscillator and offers an oscillation frequency that is tunable between 814 MHz and 1.057 GHz. 193 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 10: Conclusion The goal of this research is to greatly improve the performance and features of integrated inductors required in modem RF circuits. Such inductors must be small, tunable, inexpensive, and offer high Q with inductances that are nearly independent of frequency over a wide frequency range. Planar spirals are commonly used to implement inductors on-chip, but these structures are not tunable, are limited by low Q, have large die areas, and are difficult to parameterize reliably because their inductance values are mathematically intricate functions of geometry and the electrical properties of the substrate on which they are fabricated. Other passive inductance implementations include out-of-plane micro inductors and bond wire inductors. Although some passive inductors provide higher Q than planar spirals, they have significant drawbacks including lack of tunability and large die area. In addition, micro-inductors require very specialized processing steps, and the yield, tolerance, and repeatability of bond wire inductors cannot be guaranteed by manufacturers for volume production. Compared to passive inductors, active realizations consume much less die area, have inductance values that can be easily tuned, and are capable of producing extremely high Qs. As Q s are pushed higher, however, these circuits become less stable and can result in wildly varying inductance values with poor frequency responses over the frequency range of interest. 194 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. To improve the performance of active inductors, several inductance architectures are evaluated and a detailed stability analysis is performed on the most promising topology to offer tunable, high-Q, high-frequency, inductance synthesis: gyrator-based active inductors using transconductance amplifiers. Design equations are derived and the circuit damping factor is extracted and analyzed to reveal the relative stability of the active circuit, and to understand the trade-offs between Q, stability, and the frequency response o f the synthesized inductance. Operating constraints and biasing guidelines are provided to help satisfy performance specifications while ensuring optimal frequency response and stability. In particular, the synthesized inductors are optimized to produce high Qs and flat inductive frequency responses over the required operational frequency range. The thorough analysis presented in this research enables the insightful design of a suite of six tunable cascode gyrator inductors with high Q, wide tuning ranges, and inductances that are nearly independent of frequency over the specified frequency range. Simulation results using SPICE transistor parameters for a standard 0.13 pm Si CMOS process show that the complete suite of inductors performs extremely well against performance goals. The only objective not completely satisfied is the maximum power consumption specification of 10 mW. Four of the six designs meet this goal, but two exceed it with power consumption values of 12.9 mW and 18.6 mW. 195 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The remaining research objectives are satisfied by the final suite of inductors, and in most cases are satisfied by a large margin. The inductances are twice as stable as required, varying with frequency by only + 7-8% over the operational frequency range of 800 MHz to 2 GHz, compared to the specified maximum variation of + 15%. Similarly, the tuning ranges vary from ± 22% to ± 35%, considerably greater than the specified minimum range of ± 20%. The wide tuning ranges enable the suite of inductors to produce any inductance from 0.88 nH to 18.2 nH, satisfying the minimum inductance range of 1-15 nH. The die areas of the gyrator-based inductors are much smaller than the specified maximum o f 1/10 the size of comparable spirals, with total areas (including biasing and tuning circuitry) between 16 and 543 times smaller than comparable spiral inductors. The parasitic input capacitance and series resistance are shown to be three times smaller than those o f spiral inductors as well. The specification that Q be no less than 10 is satisfied for all inductance values over the wide frequency range of 800 MHz to 2 GHz, and much larger Qs can be generated for specific inductances or over smaller frequency ranges. For frequency ranges of several hundred megahertz, Qs of at least 100 are easily achievable. Although not specified in the original objectives, the linearity of one inductor from the suite is simulated and yields favorable results. The inductor is capable of processing 196 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. voltage swings up to 40 mV peak-to-peak while maintaining a total harmonic distortion of less than 10%. To confirm the performance of the final designs in realistic applications, a tunable RL high-pass filter and a tunable LC tank oscillator are implemented using an inductor from the final suite. The synthesized inductor performs remarkably well in both applications, offering performance very similar to that of an ideal inductor. Although the synthesized inductances use SPICE models from a standard 0.13 pm Si CMOS process, the shortest transistor channel length used in any design is 0.28 pm. All designs, therefore, can be easily ported to more mature and less expensive processes. SPICE simulations using transistor parameters from a 0.25 pm CMOS process yield similar results to those presented here. In short, the active inductors designed in this research circumvent the major drawbacks of planar spirals and other passive architectures (low Q, large die area, lack of tunability, and special processing requirements), and improve the stability and frequency responses o f existing active inductor designs. Their successful implementation in common RF applications illustrates not only their exceptional performance, but their real-world practicality as well. 197 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. To more completely measure the performance of the synthesized inductors presented in this work, at least one design from the suite will be fabricated in a standard 0.18 pm CMOS process. Additional future research includes using folded cascode architectures to reduce the supply voltage, creating coupled inductors in which the coupling coefficient is made tunable, and converting the single-ended inductors o f Designs One through Six to fully differential topologies. The differential designs will increase noise rejection and dynamic range, and will allow the inductors to be used in applications in which neither terminal o f the inductor is allowed to be connected ground. Applications using such “floating” inductors include bandpass amplifiers, filters, and lossless constant-resistance networks for use in the intermediate stages of communication systems. All future work will employ the analyses and biasing guidelines derived and proven in this research, with the expectation that the superb stability and frequency responses exhibited in current designs will be present in the new designs as well. 198 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. References [1] R. N. Noyce, “Semiconductor Device-and-Lead Structure,” U.S. Patent 2 981 877, Apr. 25, 1961. [2] T. H. Lee, The Design o f CMOS Radio-Frequency Integrated Circuits. Cambridge, UK: Cambridge University Press, 1998, pp. 34-61. [3] H. E. Bryan, “Printed Inductors and Capacitors,” Tele-Tech & Electronic Industries, vol. 14, no. 12, pp. 68-120, Dec. 1955. [4] J. M. C. Dukes, Printed Circuits, Their Design and Application. London: Macdonald & Co., Ltd., 1961, pp. v-viii, 1-18, 119-152. [5] K. Gilleo, “The History of the Printed Circuit,” Printed Circuit Fabrication, vol. 22, no. 1, pp. 18-21, Jan. 1999. [6] J. A. Sargrove, “New Methods of Radio Production,” Journal o f The British Institution o f Radio Engineers, vol. 7, no. 1, pp. 2-33, Jan.-Feb. 1947. [7] A. E. Stones, “Pro & Con on Seven Different Methods of Printed Wiring,” Electronic Industries & Tele-Tech, vol. 16, no. 3, pp. 64-158, Mar. 1957. [8] H. A. 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Creator Bakken, Timothy Wade (author)

Core Title Gyrator-based synthesis of active inductances and their applications in radio -frequency integrated circuits

School Graduate School

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag engineering, electronics and electrical,OAI-PMH Harvest

Language English

Contributor Digitized by ProQuest (provenance)

Advisor Choma, John (committee chair), Hashemi, Hossein (committee member), Kim, Eun Sok (committee member), Moore, James E. (committee member), Willner, Alan E. (committee member)

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c16-428488

Unique identifier UC11342054

Identifier 3233818.pdf (filename),usctheses-c16-428488 (legacy record id)

Legacy Identifier 3233818.pdf

Dmrecord 428488

Document Type Dissertation

Rights Bakken, Timothy Wade

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the au...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus, Los Angeles, California 90089, USA