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A passive RLC notch filter design using spiral inductors and a broadband amplifier design for RF integrated circuits

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A passive RLC notch filter design using spiral inductors and a broadband amplifier design for RF integrated circuits

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Content A PASSIVE RLC NOTCH FILTER DESIGN
USING SPIRAL INDUCTORS
AND A BROADBAND AMPLIFIER DESIGN
FOR RF INTEGRATED CIRCUITS
by
Jun-Hee Lim
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree of
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
August 2005
Copyright 2005 Jun-Hee Lim
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UMI Number: 3196844
Copyright 2005 by
Lim, Jun-Hee
All rights reserved.
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Dedication
To My Wife Hyunjeong Lim, My Son Andy Jaehoon Lim
And
My Lovely Families In My Korea
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Acknowledgements
I am extremely grateful to Professor John Choma, my advisor, for his deep
insight and sincere guide to research throughout the course of my Ph. D studies. His
standards were best in the field and his insights were always correct. I hope I will
become a highly effective engineer and a better person because I have gained the
knowledge and experience working with him.
I also thank Professor Hossein Hashemi, Won Namgoong, Eun S. Kim and
James E. Moore II, my committee members including qualifying exam, for their
generous availability and kind patience.
I would like to express sincere appreciation to Mr. Byungcheon Min, Mr.
Steve Son and Mr. Sam Lee. I believe that they always hope my family’s well being
and soothe the homesick of my family.
I extend wholeheartedly thank to Dr. Younghyun Jun, Vice-president Sooin
Cho, Dr. Duheon Song, Sangki Koh in Samsung Electronics and Dr. Yoonjong Huh
for continuous cheering me up.
Through this space, I would like to wholeheartedly thank to Professor
Young-June Park in Seoul Nat’l University, Professor Sangheon Song in Dongguk
University, Dr. Kyungho Lee and Dr. Hee-Gook Lee in LG Electronics to help
prepare for studying.
I would like to sincerely thank to Mr. Kigak Hong, Mr. Byungtae Cheong in
Hynix Electronics for their guide to better engineer aspect.
iii
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Thanks to my sibling and immediate friends who are close by and elsewhere,
Jungho Kim, Jungjune Park, Daegyu Kim, Insoo Yoon, and Dr. Keongu Moh with
their continued interest and some healthy pressure to keep me going.
My heartfelt appreciation goes to Father who taught me valuable principles
in life and to beloved Mother who had taught me to read a newspaper wherewith to
open a new world. Also my heartfelt gratitude goes to my father-in-law who always
makes me think why I am here and taught me absolute principles in life by the
example of his overwhelming joy and deepest appreciation for daily living. I would
like to give deepest thanks to my mother-in-law for her unconditional love not to be
expressed by words as well.
Full and complete credit is due to my son Andy Jaehoon, who is and will be
happiness and joy itself in my life, and my wife Hyunjeong, who is my peer and
companion to share my joys and sorrows. She is my partner in everything, and this
dissertation is no exception.
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Table o f Contents
Dedication............................................................................................................................. ii
Acknowledgements........................................................................................................... iii
List of Tables.................................................................................................................... viii
List of Figures..................................................................................................................... ix
Abstract............................................................................................................................... xv
Chapter 1. Introduction..................................................................... 1
Chapter 2. A Passive RLC Notch Filter Design Using Spiral Inductors......................2
2.1 Introduction........................................................................................................... 2
2.2 Research Objectives............................................................................................. 7
2.2.1 Overview of Comparing Passive Filters with Active Filters........... 7
2.2.2 Attenuation at the Notch Frequency................................................... 9
2.2.3 Tuning of the Notch Frequency.........................................................12
2.2.4 Quality Factor of -3 dB and Symmetrical Frequency Response.... 15
2.2.5 Other Considerations..........................................................................17
2.3. Evaluation of Notch Filter Architectures....................................................... 18
2.3.1 Approaches Using Input Impedance Function.................................18
2.3.1.1 Input Impedance of LC Circuit...........................................19
2.3.1.2 Input Impedance of Active LC Circuit............................ 21
2.3.1.3 Input Impedance of Active Circuit without Inductor...23
2.3.2 Approaches Using Transfer Voltage-gain Function.......................25
2.3.2.1 Source Degenerated Amplifier Structure.......................... 25
2.3.2.2 Notch Filtering Using Gm-sources and LC Circuit.........26
2.3.3 Impedance Matched Passive RLC Notch Filter.............................. 27
2.3.4 Conclusions......................................................................................... 28
2.4. Impact of Research...........................................................................................30
2.4.1 Benefits...............................................................................................30
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2.4.2 Applications..........................................................................................31
2.5. Design Background..........................................................................................32
2.5.1 Theory....................................................................................................32
2.5.2 Prototype of the Proposed Passive Notch Filter...............................34
2.5.3 Equivalent Circuit Models of Integrated Inductors......................... 41
2.5.3.1 Bonding Wire Inductors.......................................................42
2.5.3.2 Planar Spiral On-Chip Inductors.........................................44
2.6 Design and Simulation Results......................................................................... 50
2.6.1 Prototype Design Using Spiral Inductors.........................................50
2.6.2 Method of Pole-Zero Cancellation.................................................... 53
2.6.3 Design Example...................................................................................58
2.7 Noise Considerations......................................................................................... 66
2.8 Application to Heterodyne Receiver Front-end.............................................. 71
2.8.1 Evaluations of Inductors.....................................................................72
2.8.2 Simulation Results.............................................................................. 77
2.9 Conclusions......................................................................................................... 81
2.10 References......................................................................................................... 83
Chapter 3. A Broadband Amplifier Design................................................................... 86
3.1 Introduction......................................................................................................... 86
3.2 Design Background............................................................................................ 88
3.2.1 Shunt Peaking......................................................................................88
3.2.2 Shunt-series Peaking...........................................................................89
3.3 Design and Analysis..........................................................................................95
3.4 Conclusions.......................................................................................................101
3.5 References......................................................................................................... 102
Chapter 4. Conclusions.................................................................................................. 104
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Bibliography...................................................................................................................... 105
Appendices........................................................................................................................109
Appendix A: Normalization of the Transfer Function (Chapter 2.5.2)........... 109
Appendix B: Normalization of the Transfer Function (Chapter 2.6.2)........... 110
Appendix C: Induction of pole and zero frequencies.........................................112
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List of Tables
Table 1. Summary of the elements values of Figure 17 and the simulation results. ..41
Table 2. Examples of circuit parameters of Figure 25.................................................. 65
Table 3. Simulation results of the circuit in Figure 25...................................................65
Table 4. Components of the inductors in Figure 19 from TSMC 0.25 pm process. ..72
Table 5. Combination of inductor and capacitor in LC tank load................................75
Table 6. Combination of inductor and capacitor in notch filter................................... 76
Table 7. Comparison of the simulated signal-path performances...............................80
Table 8. Comparison of pole and zero frequencies, (a) Co effect in Figure 46,
(b) Only Cx effect in Figure 50, (c) Only L0 effect in Figure 50,
(d) Cx and Lo effects in Figure 50................................................................... 98
Table 9. Response variations due to component deviations of ±15 % .................... 100
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List of Figures
Figure 1. Block diagram of simple heterodyne receiver for down conversion, fc
and/v means the carrier frequency of the signal and the image frequency,
respectively. The intermediate frequency,^, is the difference between fc
and fosc for down conversion............................................................................10
Figure 2. Illustration of the effects o f image signal. The image signal atfy
introduces an unwanted signal at the mixer output through IF filter.............11
Figure 3. (a) Dependency of depletion capacitance on reverse biased voltage
assuming Vbi = 0.8 V. (b) Notch frequency dependency according to (a)
andf y oc(1/LC)!'2. Solid line: m = 1/2 for an abrupt junction,
Dotted line: m = 1/3 for a linearly graded junction........................................13
Figure 4. Switched capacitor array proposed for frequency tuning [7],
Needs a binary logic circuitry for the bias Vto, L /, and Vh4.........................14
Figure 5. A typical frequency response of a notch filter. DC and the infinity
high frequency transfer gain of the notch filter is OdB and BWmb is
determined by two 3-dB roll-off frequencies, y ^ a n d y/ow .......................... 15
Figure 6. (a) Schematic diagram of LNA with the notch filter proposed in the
heterodyne receiver application, (b) Input impedance magnitude of ZN
with 1 = 4 nH, Qm = coNL/Rin ( i = 9.4 andfy = 1530 MHz............................ 20
Figure 7. Schematic diagram of the notch filter using a negative impedance
circuit................................................................................................................... 21
Figure 8. Input impedance function using a transistor and LC circuit........................22
Figure 9. Input impedance function of an active circuit without monolithic
inductor................................................................................................................24
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Figure 10. Simplified amplifier circuit with source degeneration...............................25
Figure 11. Notch filter diagram using Gm sources and LC circuit..............................27
Figure 12. Input impedance matched notch filter whose quality factor of poles is
Qp, the notch frequency is co ,y and the output load is Rs..............................28
Figure 13. A proposed notch filter structure. The configuration has an input port,
an open-output port, a linear two-port network of the dotted box, which
can be represented by Z-parameters, and a base branch element, ZB........34
Figure 14. A proposed notch filter circuit. The elements in the dotted box are
composed of a re-match network with LC and a resistor RB is a base
branch element. Rind is the series resistance due to inherent Qind of
inductor L .......................................................................................................... 35
Figure 15. Frequency response of Z2I of the re-match network in Figure 14.
(a) Phase angle characteristic: The phase angle is varying from -90° to
-270° near the resonance frequency and the cross point with frequency-
axis reads thefy = 1530 MHz. Its slope would relate the -3 dB quality
factor of the notch filter, (b) Magnitude characteristic: The magnitude
at the resonance frequency determines the value of RB...............................36
Figure 16. Plots off(y) in (2-4-9). The two points of intercept off(y) with
f(y) = 0 are yh,gh and yio w by which Qid B of the notch filter can be
calculated. Thick solid line: Cr = 1, Dotted line: Cr = 0.1,
Thin solid line: Cr = 0.01 (a) Qind = 5, (b) Qin d = 20, (c) Qm d = 5 0 ............39
Figure 17. Transfer voltage-gain characteristics of the circuit in Figure 14.
Thick solid line: fy = 860 MHz, Dotted line:fy = 1210 MHz,
Thin solid line: fy = 1560 MHz...................................................................... 40
Figure 18. Cross-section view of a bonding wire inductor and its equivalent
circuit. L is self-inductance and Rm d is series resistance due to loss
including skin effect. C junction is added to reduce the effect of Cpad.
H is the height of a wire above the substrate and h is the vertical
bending in the bonding wire...........................................................................43
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Figure 19. Perspective view of a square spiral inductor and its equivalent circuit.
L is self-inductance and Rm d is series resistance due to loss including
skin effect. C, is due to lower metal cross-under and Co x results from
oxide below the top-level metal. CS U b and Rsub are functions of the Si-
substrate doping................................................................................................ 46
Figure 20. The quality factor of the inductor having L = 8 nH from the previous
work [13]. Solid line is for Q m d_actuah and the dotted line represents
Qind = oil/Rj„d. At the 1.8 GHz, Q m d_actuai is about 7.5 and decreases
drastically due to substrate parasitic at high frequencies............................ 48
Figure 21. (a) A prototype notch filter with an on-chip spiral inductor.
(b) Frequency response showed the unsymmetrical characteristic and
a peaking............................................................................................................51
Figure 22. (a) Virtual configuration to ensure the load effects, (b) The frequency
response had a symmetrical characteristic like Figure 17.......................... 52
Figure 23. Illustration of the load effect of ZL at the output port on the filter........... 54
!
Figure 24. Plots off(y) in (2-5-9) with Qm d = 5. The two points of intersection '
off(y) with f(y) = 0 are yh,gh and yio w by which Qmb can be calculated.
Thick solid line: Lr = 1, Thin solid line: Lr = 2, Dotted line: Lr = 4.
(a) Cr- \ (b) Cr = 0.1...................................................................................... 57
Figure 25. Complete schematic of the proposed notch filter with the load, which
is the parallel combination of a spiral inductor and a capacitor, Cadd........59
Figure 26. (a) Frequency response of the proposed notch filter showed symmetrical
notch characteristic and no peaking. The gain in the passband was
-6.02 dB. (b) The magnified plot o f (a) near the notch frequency.
Thick solid line: With the load + 6.02 dB, Thin solid line: Without the
load, Dotted line: Virtual configuration....................................................... 60
Figure 27. (a) Dependence of the attenuation on Rb-
(b) Dependence of the notch frequency on Rb..............................................60
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Figure 28. Dependence of the frequency response on Ca dd■ Thick solid line:
Ca dd = 9.7 fF, Thin solid line: Ca dd = 97 fF, Dotted line: Ca dd = 970 fF 61
Figure 29. (a) Magnitude of the input impedance of the notch filter.
(b) Phase angle of the input impedance of the notch filter.
Thick solid line: f s = 2362 MFlz, Thin solid line: fy= 1530 MHz.............62
Figure 30. Magnitude of the Z/;V of the notch filter according to different Cr for
f N= 2362 MHz. Thick solid line: C/ = 758 fF, C2 = 2 pF,
Thin solid line:C/ = 2 pF, C2 = 758 fF...........................................................63
Figure 31. (a) Magnitude of the output impedance of the notch filter.
(b) Phase angle of the output impedance of the notch filter.
Thick solid line:fy = 2362 MHz, Thin solid line:/v = 1530 MHz............. 64
Figure 32. Equivalent noise circuit model of the notch filter...................................... 66
Figure 33. Equivalent circuit to calculate the noise current Iouti................................68
Figure 34. Noise Calculation according to (2-7-8) with L = 8 nH, Qin d = 11.2,
Rb =312 Q, Rin d = 8.56 Q, Rs = 50 Q, Cx = 100 fF,
Thick line: C} = 2 pF, C2 = 758 fF, Thin line: Cj = 758 fF, C2 = 2 pF 69
Figure 35. Schematic of a front-end heterodyne receiver.
Biasing circuitry was not shown.................................................................... 71
Figure 36. Impedances of the inductors from TSMC process.
(a) Real part, (b) Magnitude..........................................................................73
Figure 37. Impedances of the inductors from TSMC process.
(a) Imaginary part/2ir/, (b) Phase angle...................................................... 74
Figure 38. Impedances of the parallel L-C tanks (a) Magnitude (b) Phase angle....74
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Figure 39. (a) Magnitudes of impedances at the noded) in Figure 34,
(b) Noise figure calculations according to (2-7-8).
# of turns: Thick line = 6.5, Thin line = 5.5, Dot = 4.5, Circle = 3.5....76
Figure 40. Comparison of the frequency Responses.
Thick line: LNA/Notch filter, Thin line: Only LNA................................... 77
Figure 41. Comparison of the noise figures.
Thick line: LNA/Notch filter, Thin line: Only LNA...................................78
Figure 42. Two-tone IP3 simulation results. •: fundamental term of (LNA/Notch
filter), o: fundamental term o f only LNA, ▲ : IM3 term of (LNA/Notch
filter), A: IM3 term of only LNA....................................................................79
Figure 43. Schematic diagram of a shunt peaking.........................................................88
Figure 44. Frequency responses at node OC. Thin line: m = go,
Dot: m = 3.10 (MFD), Thick line: m = 2.41(MFM), A: m = 1.41...............89
Figure 45. Schematic diagram of an amplifier with a shunt-series peaking.............. 90
Figure 46. Schematic diagram of an amplifier with T-coil.......................................... 91
Figure 47. Frequency responses at node OC.
Thin line: m = oo, Dot: m = 2.41 (MFM), Thick line: Kc = 1/3................92
Figure 48. Frequency responses at each node in Figure 46 of (a) normalized v(/C),
(b) normalized v(OC), (c) normalized v{LC).
Thick line: With Co- Thin line: Without Co.................................................93
Figure 49. Transient responses with step input at 100 ps. Thick line: Without Co-
Thin line: With Co- (a) normalized v(/C), (b) normalized v(OC)................94
Figure 50. Schematic diagram of the proposed broadband amplifier......................... 95
xiii
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Figure 51. Frequency responses of the proposed circuit with Cx = 32 fF,
Lo = 0.5 nH. Thick line: With Co, Cx and Lq. Thin line: Only with Co-
(a) normalized v(IC), (b) normalized v(OC), (c) normalized v(LC) 96
Figure 52. Poles and zeroes in s-domain of v(/C) response.
(a) Co effect in Figure 46, (b) Only Cx effect in Figure 50,
(c) Only L0 effect in Figure 50, (d) Cx and Lo effects in Figure 50.........97
Figure 53. Transient response with step input at 100 ps.
Thick line: With Co, Cx and Lo- Thin line: Only with Co-
(a) normalized v(IC), (b) normalized v(OC)................................................. 99
Figure 54. Response variations due to (a) 67, deviation, (b) Cx deviation.
Thick line: 0 %, Thin line: -15%, Dotted line: +15 % ...............................100
xiv
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Abstract
The extensive use of wireless personal communication systems has
engendered considerable research interest. The current market demands low power
devices, whence a need to pay attention to the passive networks within
communication systems arises. In this work, notch filter designs and the broadband
amplifier designs using passive circuits are analyzed and assessed.
The role of a notch filter is band-rejection to diminish the unwanted signal in
the communication systems. Especially, the notch filter followed by the mixer for
the image signal rejection is widely used in the front-end heterodyne receivers.
Recently, passive filters have grown in importance because the active RC filters
have such problems as finite gain-bandwidth product, higher electrical noise,
increased power dissipation, inherent dynamic range limitations, and difficulty
operating at low voltages. In this work, a new approach to realize a passive RLC
notch filter using the open-circuit impedance parameters (Z-parameters) is
introduced and its third order transfer voltage-gain function is analyzed to predict
the performance, such as the attenuation at the notch frequency and the tuning of the
notch frequency. The feasibility for on-chip implementation using planar on-chip
spiral inductors is demonstrated. The controllability of the symmetrical notch
characteristic is obtained by providing the method of pole-zero cancellation to
reduce the parasitics of the spiral inductor. A design example of front-end
heterodyne receiver is shown and it is compared with that of only a low noise
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amplifier (LNA). HSPICE simulations that confirm the propriety of the adopted
design methodology are provided.
One way to improve amplifier bandwidth entails a shunt-series peaking
methodology. A broadband amplifier with the previous T-coil configuration for
bandwidth extension has peaking in its frequency response due to parasitic
capacitances. The peaking affects the nonlinear operation of the system and results
in non-monotonic step responses. To reduce these effects, a modified T-coil
configuration is proposed and is analyzed by tracing the poles and zeros in the
transfer function. The effects of the component deviations are examined for the
design guidelines as well.
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Chapter 1. Introduction
The countless use of worldwide wireless communication systems opens
ubiquitous era. Current market needs the technology development for low power and
low cost radio system. Interest in the low power devices causes strong attention to
design methodologies using passive networks. In addition, necessarily for low cost
devices, integration technology to establish inductors and transformers on a chip
makes another momentum to the re-interest in the passive network, even though the
impedance of practical inductor deviates from its ideal value owing to inherent
resistance associated with its realization.
This paper consists of two parts, where one is for designs of passive RLC
notch filters using spiral inductors and another is about a modified T-coil
configuration for broadband amplifier design. The first part shows the notch filter,
which is widely used for receiver applications, with full attenuation at the notch
frequency only by resistor although the low quality inductor such as planar spiral
on-chip inductor is used. To the end, an approach to a third-order passive RLC notch
filter implementation by using open-circuit impedance parameters (Z-parameters)
representation is presented. The second part deals one of techniques of bandwidth
extension, shunt-series peaking. For the closer poles and zeros, a modified T-coil
configuration realized only by passive components is proposed and analyzed.
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Chapter 2. A Passive RLC Notch Filter Design Using Spiral
Inductors
2.1 Introduction
A filter in electronic systems is a signal processor that transmits signals in
some frequency bands and rejects or attenuates signals in other bands. Filters are
used extensively in electronics to separate, pass, or suppress signals of certain
frequencies within the group of signals present in electronic circuits and systems and
used in modem audio systems, control systems, biomedical systems, signal
processing systems, and communication systems [1]. The fundamental filter
configurations by the band selection include low pass, high pass, band pass, notch
filters, and so on.
With the rapid increasing demands of wireless personal communication
market, low cost and low power receivers are needed. To this end, modem RF filters
required for band selection and image rejection can be achieved by integration of the
required elements as much as possible, therefore minimizing the number of off-chip
components. Currently, off-chip passive filters, such as ceramic filters, surface
acoustic wave (SAW) filters or discrete LC filters for signal filtering processing
have severe restrictions to implement monolithically with other receiver elements
[2], [3]. Its process and the assembly are not compatible with the current commercial
IC technologies since the impedance matching network and the parasitic elements
associated with additional I/O pins and semiconductor packaging degrade system
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performance. In consequence of the incompatibility, the increase of the cost and the
bulky volume cause not to be suitable for current market demands.
Electromechanical filters use mechanical resonance to accomplish the filtering of
electric signal. In spite of the quality factor of more than thousands and the recent
technology developments, the difficulty of integration makes still out o f application
in current commercial receiver systems.
The on-chip filter implementation can be categorized as active and passive
design. Active filters composed of resistors, capacitors, and active devices such as
op-amps and operational transconductor amplifiers (OTAs) are widely used in audio,
video, and other types of relatively low frequency signal processors. Active filters
can be very effective, even when quite simple, however, active filters place a limit
on the systems operating in RF range because of the finite gain-bandwidth product,
inadequate phase response, and delay characteristics afforded by the active elements.
Furthermore the electrical noise, increased power dissipation to be required for
biasing, inherent dynamic range limitations, and low voltage operation in current
technology trends should be considered in the active filter design.
Passive filters composed of resistors, inductors, and capacitors have certain
problems due to the use of inductors. The impedance of practical inductor deviates
from its ideal value owing to inherent resistance associated with its realization. In
contrast to active filters, passive filters do not have such an upper frequency
limitation, however, the limitation at the relatively high frequency is due to the
parasitic associated with the passive elements, especially inductors. Although the
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poor quality factor and the parasitic o f monolithic inductors had made on-chip
implementation of passive filters impractical, the recent works showed the
feasibility of on-chip passive filter design [4-6]. And passive filters are less affected
by component drift due to manufacturing or environmental changes and have a
design freedom in terms of noise, non-linearity, voltage headroom and dissipated
power consumption, etc [1-3].
The objective of the notch filters, which are commonly used for receiver
applications, is to eliminate several known but undesirable input signals that may
vary in frequency. A notch filter for image rejection at the front end of receivers is
used to attenuate greatly the image signal prior to mixing and this image signal
frequency is located twice the IF away from the desired frequency [5]. The research
was conducted to determine a possible solution for eliminating many narrow bands
of frequencies by incorporating an automatic self-locking self-tuning scheme. The
use of tunable notch filters imbedded in several self-tuning sub-systems allows
phase lock loop systems to adjust the center frequency of various notch filters [6].
An analog comb filter, which is another application of notch filters in
communication systems, is an electronic system to attenuate several undesirable
frequency bands while passing signals whose frequencies lie within the signal
processing frequency range. This analog comb filter can be designed by cascading
more than one notch filter. For instance, the notch filters could be chosen to
attenuate an analog cell phone frequency (-860 MHz), a digital cell phone
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frequency (-1100 MHz), and a Global Positioning Satellite (GPS) frequency (-1530
MHz).
The overall goal of the research described in this chapter is to implement
passive notch filters on a chip operating in modem RF circuits. The state-of-the-art
previous works had tried to cancel out the resistive loss of monolithic inductor by
using the negative resistance active circuit. In this proposal, although the low quality
inductor such as planar spiral on-chip inductor is used, the full attenuation at the
notch frequency can be accomplished only by resistive load. And the parasitic
capacitance of the inductor can be compensated by introducing the pole-zero
cancellation method. The proposed notch filter is applied to a heterodyne receiver
front-end and the performances are compared to those of a LNA configuration
without the notch filter. By adoption of the notch filter, there is no additional power
consumption and the image rejection can be obtained. The acceptable performances
such as the gain, the noise figure and the non-linearity are achieved.
To this end, Chapter 2.2 reviews considerations that are required in the notch
filter design and the state-of-the-art notch filters are shown in Chapter 2.3 as reviews
of previous works. Chapter 2.4 demonstrates the impact of the research proposed in
Chapter 2.5 and 2.6. In Chapter 2.5, a new approach to a third-order passive RLC
notch filter implementation by using open-circuit impedance parameters
representation is presented and the equivalent circuit modeling for the spiral on-chip
inductor implementation is reviewed. Chapter 2.6 shows the proposed passive notch
filter design introduced the pole-zero cancellation method and demonstrates the
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simulation results with discussions to show the feasible realization of filters by
applying the theoretical aspects developed in Chapter 2.5. Chapter 2.7 provides the
noise analysis of the proposed notch filter circuit and Chapter 2.8 shows an
application example of the proposed notch filter to the front-end heterodyne receiver
design through HSPICE simulations. Chapter 2.9 as a conclusion, is a collection of
the all the important results and interpretations, which are summarized to offer the
reader a conclusion to the information that is covered in the body of the proposal.
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2.2 Research Objectives
In this chapter, first, the advantages of active RC filters and passive filters
are briefly reviewed, respectively, and the previous works will be briefly discussed.
And then the required considerations, such as the attenuation at the notch frequency,
the tuning capability of the notch frequency, the quality factor of the notch filter, and
the symmetrical feature of frequency response, in the notch filter design will be
described.
2.2.1 Overview of Comparing Passive Filters with Active Filters
Active RC filters overcome the difficulty of integration with high quality
inductors, which are bulky and expensive as discrete components. In addition, the
integrated active RC filters provide the following advantages [1 ]-[3]:
• A reduction in size and weight.
• Increased circuit reliability, because all the automated manufacturing steps
can be integrated on a wafer.
• Much lower cost of an integrated circuit than its discrete equivalent passive
filters by mass manufacturing.
• A reduction in the parasitic because of small size.
• Analog active filters and digital circuitry can be integrated on the same
silicon chip.
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• Simpler design process than that for passive filters.
• Provision of voltage gains in contrast to voltage loss of passive filters.
• Often simpler tuning processes than that for passive filters.
• Realization of high Q active filters without the use of inductors.
The economic and performance advantages of active RC realization far
outweigh the its disadvantages, which described in the followings, in voice data
communication systems, especially.
The use of negative resistance using the LC circuit through a bipolar
transistor [4], and the use of negative resistance circuit using the cross-connected
differential pair o f transistors had been proposed to compensate the resistive loss of
inductor [5], [7], [8]. The Gm cell used to control the zero frequency to implement
notch characteristics [6] and the active filter based on a gyrator had presented [9],
[10], In these designs of the active filters, the parameters such as noise figure, non-
linearity, power dissipation, and stability issue due to feedback should be considered.
The recent IC technology development of on-chip inductor implementation
and the market needs of personal communication system such as low voltage
application make the regime of on-chip passive filter design refocused [11], [12].
The passive filters have several advantages over active filters as follows [l]-[3].
• No upper frequency limitation afforded by the active elements.
• Less sensitivity under manufacturing or environmental changes.
• No requirement of power supplies and no needs to consider low supply
voltage operation in the need of current technology.
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• Higher dynamic range, less distortion and less noise than active filters.
• No power dissipation to be required for bias circuitry.
Although passive filters do not have as much of an upper frequency
limitation as active filters have in the relatively low frequency range, but the
relatively high frequency capability is also limited by the parasitic associated with
the passive elements. Especially, in the use of spiral on-chip inductors, the quality
factor of inductor is aggregated by induced electric field coupled to the substrate at
RE range [11]-[15], In the passive filter design, the tuning of frequency is typically
accomplished by on-chip varactor and the input impedance matching of the filter
could be required with the driving of the preceding stage if necessary.
In this research proposal, a new approach to implement a passive RLC notch
filter on a chip operating in RF frequency range is described. And the pole-zero
cancellation method is introduced to compensate the parasitic in spiral inductor
realization as will be described in Chapter 2.5. Hence, the design has a degree of
freedom not to consider the disadvantages of any active filter circuit.
2.2.2 Attenuation at the Notch Frequency
In most state-of-the-art monolithic receivers, the superheterodyne receivers
in which have image frequency problems are widely used. To reject the image signal
is to pass the desired signal and not to pass the image signal. However, to realize a
9
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low power tunable monolithic band-pass filter with high selectivity in giga-hertz
range is extremely challenging due to stability and linearity considerations [4].
A superheterodyne receiver consists of a low noise amplifier (LNA), a notch
filter for image rejection, a mixer for down conversion and an intermediate
frequency (IF) filter, as shown in Figure 1. The down conversion helps signal
processing after the front-end electronics. The receiver needs to provide the image
rejection of the notch filter to suppress the image signal, which is located at the
twice IF frequency away from the desired signal before the mixing [16], [17].
LNA
IF
fosc
IF
Filter
Notch
Filter
Local
Oscillator
Figure 1. Block diagram of simple heterodyne receiver for down conversion. f c and f N
means the carrier frequency of the signal and the image frequency,
respectively. The intermediate frequency,///,, is the difference between/ and
fosc for down conversion.
The mixer translates the desired input carrier frequency, fc, to the IF
frequency, ///,. Without the notch filter, the unwanted image frequency,// =fc ± 'Ifif,
where the sign depends on the choice of local oscillator frequency, will produce
another unwanted IF signal at the IF output as shown in Figure 2. In other words, if
we are attempting to receive a signal having carrier frequency fc, we can also
receive a signal at f N =fc+ I f if if the local oscillator frequency is fosc = fc+ / if or a
10
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signal at f N = fc -2 fiF if fosc = fc - fiF■ There is only one image frequency, and it is
always separated from the desired frequency by 2ff. Figure 2 shows the desired
signal and the image signal for a local oscillator having the frequency
fosc = fc +fiF (2-2-1)
Desired
Signal
Local
Oscillator
Signal
at Mixer
Output
Image
Signal
Image
at Mixer
Output
fiF
1
f c
\fIF |
Pass band
o f IF filter
A
fosc
f c +fc osc
/ n
f s +fosc
*f
* f
*f
*f
* f
Figure 2. Illustration of the effects of image signal. The image signal at f N introduces
an unwanted signal at the mixer output through IF filter.
The image signal can be eliminated by the notch filter, which placed before
the mixer. The attenuation at the notch frequency,/^, is the most important parameter,
in other word, the notch filter should be designed to have a relatively small loss in
the desired band and a large attenuation in the image band. It is accomplished by a
sufficiently large l-fo or a large attenuation at the notch frequency, fy. A large f f
11
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makes practical IF filters unfeasible, so a large attenuation at the notch frequency fy
is required. Although the infinite image rejection at the notch frequency is desirable,
the image attenuation is required from 60 to 90 dB depending on the application [4],
2.2.3 Tuning of the Notch Frequency
The tuning ability is essential for operation over a range of frequencies, and
also to accommodate manufacturing or environmental changes. Wider range of
tuning is preferred, however, the notch frequency is determined by LC resonance in
passive filter designs. The tunable capability comes from the on-chip varactor such
as a form of the reverse biased diode. A depletion capacitance of the reverse biased
diode, C, is expressed in terms of electrical parameters as follows,
C 1
— = t-------- ------- — (2-2-2)
c o (l + Vc:m/¥ „ )"
where Co is the depletion capacitance at Vcon = 0 V, Vcon is the applied reverse
biased voltage, Vbi is the built-in potential of the PN junction and m is grading
coefficient. For the abrupt junction, m = 1/2, and for the linearly graded junction, m
= 1/3 [18]. Figure 3 shows the PN diode capacitance dependence upon the applied
reverse biased voltage and the notch frequency variation associated with capacitance
I/O »
variation based on the relation of /\ (1/LC) . With the reverse biased voltage of 3
V, the capacitance C varies ~ 43 % and /v varies ~ 150 % with respect to Co and f m
12
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of Vcon = 0 V, respectively, for the abrupt junction (m = 1/2) as an approximation for
many integrated circuits.
2.5
o
O
O
0.5
3 1 2 0 1
1.6
1.4
1.2
J
0.8
0.6
0.4
1 0 1 2 3
V con 0 0 Vcon 00
(a) (b)
Figure 3. (a) Dependency of depletion capacitance on reverse biased voltage assuming
V m = 0.8 V . (b) Notch frequency dependency according to (a) and fy °c
(1/LC) 12 . Solid line: m = 1/2 for an abrupt junction, Dotted line: m= 1/3 for
a linearly graded junction.
The high well resistivity of standard PN junction diodes typically degrades Q
to undesirably low levels [12]. The use of the gate capacitance of a standard
enhancement-mode MOSFET is another option, which has the change in
capacitance as the gate bias varies from well below threshold to well above
threshold. A modification to the standard MOSFET varactor results in substantial
improvements. By using a PMOSFET with the n+ source/drain diffusions, or vice
versa, a MOS capacitor that may be operated in the accumulation mode can be
constructed. Only a design rule adjustment is required for this device and, typically
achievable capacitance tuning range approaches 2:1. Operation in the accumulation
mode can be advantageous because of the lowered channel resistance in operations.
13
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As a result, large frequency products (e.g., > 1 0 0 GHz) are achievable with current
processes, and continue to improve as technology scales [12].
A switched capacitor array is another way to tune the center frequency of a
notch filter as shown in Figure 4 [7]. Cdo, Cdi, and are the drain junction
capacitors of each transistor and the transistors Mo, M i, and M4 control the
equivalent capacitance of Ceq. The capacitance connected in parallel (Co, Ci, and C4 )
is a part of the equivalent capacitance o f Ceq when the transistor turns on and is
removed by series combination with Cm, Cdi, and Cd4 when the transistor is off.
According to the described results, the noise contribution from the switched
capacitor array is negligible, the linearity is good and it consumes no dc power [7],
however, the binary logic circuitry for the bias Vw, VbJ, and V/,4 is necessary.
_ L c,
“ t c,.
cd i
t J K = t lb
M,
b l
Mj
Figure 4. Switched capacitor array proposed for frequency tuning [7], Needs a binary
logic circuitry for the bias V h 0 , Vhh and V b 4 .
In the works as will be described in Chapter 2.5 and 2.6, the tuning
capability will be examined with the varactor of a reverse biased diode.
14
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2.2.4 Quality Factor of -3 dB and Symmetrical Frequency Response
Typical frequency response of a notch filter is shown in Figure 5. One of the
critical parameters of a notch filter is the quality factor of Q3dB , which is a measure
of band selectivity of a filter. Therefore, higher Qmb is desirable. In Figure 5, the
normalized center frequency is defined at /y = 1 and the quality factor of Qmb is
defined as the center frequency fy divided by the 3dB bandwidth, BWmb- which
represents the stop band, {/high - flow)- In other words,
n _ fN _ f N 1
^ 3 dB ~
(2-2-3)
fh ig h flo w y high T low
where fh,gh andf o w are high- and low-, respectively, stop band frequencies to produce
3dB roll-off with respect to the DC and infinity high frequency transfer gain of the
notch filter, yh ig h and yio w are the corresponding normalized frequencies with f N.
-3 dB
S' -1 0
S .2 0
-30
Ylow
, ^
Yhigh
-40
0.5 1.0 1.5
Normalized Frequency
Figure 5. A typical frequency response of a notch filter. DC and the infinity high
frequency transfer gain of the notch filter is OdB and BW3 d B is determined by
two 3dB roll-off frequencies, y;„g ;, and yhw .
15
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For a second order passive notch filter, the transfer voltage-gain function,
H(s), is
H (S\ = lourOO = _____ 1 + (s /^ z )--------- (2-2-4)
VIN (s) 1 + s/ (QP (op ) + (5/ coP )2
where co p = con = ' 1 -k/n is the angular pole frequency, coz is the angular zero
frequency, and Qp is the pole-0. In this equation, the Qz of the zero-0 is infinity.
If co z » (op, (2-2-4) represents a low pass characteristic with a notch in the
stop band and the transfer voltage-gain at low frequencies is seen to be greater than
that at high frequencies. Such a filter characteristic is referred to as the low-pass-
notch (LPN). Meanwhile, if coz « c o p, the obtained transfer function has the high-
pass-notch (HPN) characteristic [3].
By ordinary, Qp is approximately Qmb of the notch filter when Qp » 1 [20],
and Qp is typically affected by the quality factor of inductor in the passive RLC
circuits. The effects of induced electric fields, which couple to the substrate, limit
the quality factor of the spiral on-chip inductors for integrated circuits. This will be
in detail discussed in Chapter 2.5.
The symmetrical frequency response means that the transfer voltage-gain at
frequencies below a notch is to be identical to that at frequencies above a notch. The
preferred design, whether symmetrical frequency response or not, depends on the
application. The general design of the notch filter is necessary to have symmetrical
frequency response because the transfer voltage-gain reduction of the frequencies
can cause to use another amplifier to compensate the reduced gain. Occasionally, the
16
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unsymmetrical response, such as low pass notch (LPN) filters or high pass notch
(HPN) filters, is considered to help the system performance such as in the image
rejection operation. In other words, when the signal frequency is located at the
peaking frequency, the relative attenuation at the image frequency can be increased
with respect to the gain at the signal frequency. This will be explained with the
simulation results in Chapter 2.6.
The proposed notch filter design shows the control capability to have
symmetrical or unsymmetrical features of frequency response by using the pole zero
cancellation concepts for any application. The methodology and the design will be
described in Chapter 2.6.
2.2.5 Other Considerations
For RF circuits, it is important to achieve maximum power transfer between
signal ports and output ports on signal driver. To achieve maximum power transfer,
the load impedance must equal the complex conjugate of the source impedance [2].
This is referred to as an impedance matching. The impedance matching
considerations of the proposed design will be postponed until the future work to
consider the use in the system, if necessary.
Noise and linear operation associated with large input signal are design
considerations as well. The simulation results to show them will be provided in
Chapter 2.8.
17
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2.3 Evaluation of Notch Filter Architectures
In this chapter, the state-of-the-art integrated notch filter architectures
proposed in the previous works are reviewed to get the insight into the most
promising topology for notch filter design. To acquire the notch characteristic, one
approach is to use the input impedance function of notch response with a constant
current source [5], [7], [8], and another is to derive transfer voltage-gain function
directly. The architecture with a source-degenerated amplifier was presented [21]
and the combination of Gm-sources and LC-tank was proposed to realize the notch
characteristic [6]. Another category is a passive notch filter associated with
impedance matching consideration [9].
2.3.1 Approaches Using Input Impedance Function
Conceptually, a voltage function is expressed as the product of a current
function and an impedance function. Among most previous works, the notch
filtering for the heterodyne receiver is necessary for the image rejection and a low-
noise amplifier (LNA) offers the current source function. And the shunt path to the
impedance load of Zn, which performs the notch filtering, is placed at the midway of
the signal path to the output. This impedance load had appeared as the forms of an
LC circuit, an LC circuit with the active circuit to cancel the resistive loss of
inductor, or the gyrator type active circuit without passive monolithic inductor.
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2.3.1.1 Input Impedance of LC circuit
An LC circuit with impedance of ZN modifies the transfer voltage-gain
function of a cascode LNA topology with inductive degeneration as shown in Figure
6-a. The path to the LC circuit, which consists of the series combination of a
capacitor, Cs, with the parallel combination of an inductor, L, and a varactor C,
shunts the signal path to the output through the transistor, M 2. Conceptually, at the
notch frequency, the impedance of the parallel LC combination is inductive to
cancel the impedance of the capacitor, Cs. The parallel combination of L and C has
input impedance of band-pass characteristic [5], [7].
The LC circuit has low impedance at the image frequency and high
impedance at the signal frequency. The input impedance of the LC circuit can be
expressed as
L-(C + Cs)s 2 +1
CCSL • + C s • 5
ZN(*)= „ „ r 3 ~ (2-3-1)
The zero of impedance function is located at a> z = [L(C+CS ) \ :, and the pole
is located at o)p = (LC)J /' 2 . For frequencies close to a> z, the LC circuit has impedance
lower than l/g m2 where gm2 is the transconductance of transistor M 2, and steals the ac
current away from M2, thus reducing the LNA gain. At frequencies close to a> p , the
magnitude of impedance is larger than l/g m2 and the LNA gain is high. Flence, the
resultant transfer function has the image rejection at oj y = & > z.
19
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1E+3
M
IN
1E+1
1E+09
Frequency (Hz)
1E+10
(a) (b)
Figure 6. (a) Schematic diagram of LNA with the notch filter proposed in the
heterodyne receiver application, (b) Input impedance magnitude of ZN with
L = 4 nH, Qm d = mN L/Rm d = 9.4 and f N = 1530 MHz.
The attenuation at the notch frequency is degraded by the loss of the on-chip
inductor, especially is remarkably aggravated by a planar spiral inductor as will be
explained in Chapter 2.5.3.2. Figure 6-b shows the magnitude o f Zv in case that L =
4 nH, C = Cs = l.35 pF for fy = 1530 MHz, and Qm d (=coN L/Rm d) at the notch
frequency was 9.42, which is typical value for spiral on-chip inductor. At the notch
frequency, the magnitude of ZN was -16 Q, not much lower than l/g m 2, so the
sufficient attenuation could not be obtained. To compensate the inherent low quality
factor of integrated inductors, negative resistance circuit using the cross-connected
differential pair of Ms and M 4 in Figure 7 could be introduced.
The depth of the notch in the frequency response depends on the negative
resistance of -l/g m3 or - l/g m 4, which can be adjusted by choosing a correct tail
current through Mb. Since the LNA/filter using the circuit of Figure 7 becomes
unstable when the net negative impedance of Zi V becomes comparable to l/gm 2,
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which is the impedance looking into the source of M2, in the Figure 6, the design to
concern the stability is required [5], [7]. And the disadvantage of active filters such
as the power consumption, the noise issue, the non-linearity, and so on should be
considered.
M ,
'N2 ’ N1
Figure 7. Schematic diagram of the notch filter using a negative impedance circuit.
2.3.1.2 Input Impedance of Active LC Circuit
The proposed input impedance function shown in Figure 8 consists of an LC
circuit and a transistor. It has input impedance function as
L C - s 2 +C.
ZN(s) = -
R +
gn, 3
S' C^Cj
•5 + 1
c.
(2-3-2)
where Cs is the series combination of C and CK 3, which is the capacitance between
the emitter and the base of the bipolar transistor, Q$. R represents the sum of the
21
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resistive loss of inductor of L and the base resistance of Q3, and gm3 is the
transconductance of the Q3 [4],
To make ‘s' term in numerator of (2-3-2) deleted, that is for the infinite Q of
zeros, R term can be completely cancelled by adjusting g m3 of the transistor tuned
with the bias current If,ias. And the notch frequency is determined as a)3; = coz = (LCS J
/!
OUT
bias
Figure 8. Input impedance function using a transistor and LC circuit.
Similar to the circuit of Figure 6 with Figure 7, the circuit becomes unstable
when the net negative impedance of ZN becomes comparable to l/g m 2, which is the
impedance looking into the emitter of Q2. Hence, the stability concern should be
needed in the design. And the disadvantages of active filters described in Chapter
2.2.1 should be considered in the design.
22
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2.3.1.3 Input Impedance of Active Circuit without Inductor
The parallel combination of L and C with band-pass characteristic in Figure
6 can be replaced with an active circuit without realization of the monolithic
inductor [9], [10]. The active circuit contains gyrator type inductor, which is realized
with trans-conductance devices and capacitors. In the circuit of Figure 9, the input
impedance of Z,„(s) is found to be
C2, Cs, and C4 are the capacitance between node® and Ground, the capacitance
between node® and node®, the capacitance between node® and Ground, and the
capacitance between node® and Ground, respectively. And g* is the admittance
looking into node®.
The transconductance devices of M6 , M 7 and Ms act as the feedback path for
a gyrator and M 7, M8 and Mu are used for high impedance looking into the node®.
Through the analysis of the input impedance of Zv(s), which is series
combination of Cs and Z,„(s), the zero frequency and its Q are expressed by
(2-3-3)
where A = , C 2 = C ,C 2 +C 2C3 +C ,C 3 and Cu
(2-3-4)
23
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& =
g»,V(Ci +C.(C; +C,)) + g„tg.7
§ m & ( . 8 m l ^ l 8 8ds^~'s') 8 m ( s 8 m l ^ 4
(2-3-5)
5
Figure 9. Input impedance function of an active circuit without monolithic inductor.
From (2-3-4), the notch frequency is determined as « v = coz and it is tuned
by varying gm6 or gm 7. As a result, it has wider range tuning capability compared
with the case using varactor as shown in the LC resonance circuit. Furthermore, by
adjusting Cq, thereby changing C4 , the Qz can be independently tuned without
altering the notch frequency according to (2-3-5) [9].
Although the proposed circuit in Figure 9 overcomes the shortfall of passive
monolithic inductor, which results in large chip area, the resistive loss and the
capacitive coupling to the substrate, it is necessary to consider power consumption,
the stability concern due to the feedback, the linearity issue, the noise concern, and
so on.
24
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2.3.2 Approaches Using Transfer Voltage-Gain Function
To realize the notch characteristic, the transfer voltage-gain function can be
derived directly. The source degenerated amplifier topology and the structure using
Gm sources with LC circuit were proposed.
2.3.2.1 Source Degenerated Amplifier Structure
In the circuit of the source degenerated amplifier structure as displayed in
Figure 10, the transfer voltage-gain function H(s) can be expressed as
H(s) =
Ux/rU) Sm^L
V/N(s) 1 + gmZA
(2-3-6)
where gm is the transconductance of the transistor, and Z/. and Z; y represent the loads
at the drain side and source side of the transistor, respectively.
OUT
i n O
Figure 10. Simplified amplifier circuit with source degeneration.
25
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At the resonance of LC circuit, ZN becomes the maximum, hence the gain
H(s) get minimized accordingly. To maximize the image rejection, it is necessary to
have much larger ZN compared with ZL. As a result, the gain at the notch frequency
decrease to zero, and the notch characteristic can be acquired [8], [21].
To suppress the noise contribution owing to the notch filter, the filter can be
placed at the second stage after LNA with high gain. The function of ZN is to
improve the linearity by trading off the voltage gain [21]. Similar to Figure 6-b, the
depth of the notch is influenced by the inherent low finite quality factor of inductor.
To cancel the losses in the LC resonator, the way to use the negative Gm cell shown
in Figure 7, with the transformer was proposed [8].
2.3.2.2 Notch Filtering using Gm-sources and LC Circuit
As shown in Figure 11, the notch filtering can be achieved in the feed
forward system [6]. The output current via the load of Z/, can be obtained by
subtracting the band-pass filtered input signal current through the gm z from the
current through the gm/.
The transfer voltage-gain can be found to be
H M = = s - w ■ ■ LC ' ° 2 \ c ^ + r Lc + ! 1 ~ R“ G) < 2 ' 3 _ 7 )
V,N(s) LC-s +RmdC-s + 1
where G = (gm 2 / gmfrgmz ■
26
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Sm2 mz
ind
O v O U T
Sml
Figure 11. Notch filter diagram using Gm sources and LC circuit.
The quality factor of poles is equal to the inherent quality factor o f inductor.
And, for the perfectly matched transconductances (gmi= gm i), the Q of zeros can be
made infinite if the coefficient of the V term in the numerator in (2-3-6) disappears
by setting G (= gm z) to Rm dC/L. The notch frequency is coN =coz = [(1- gm zR,„d)/LC]/2 .
As in many active filters depicted in Chapter 2.2.1, the noise, linearity
degradation, and power consumption should be considered.
2.3.3 Impedance Matched Passive RLC Notch Filter
Figure 12 shows an example of a second-order notch filter whose input
impedance is matched to the signal source resistance of Rs for the maximum power
transfer, in case that the source resistance is equal to the load resistance [20].
The transfer voltage-gain function H(s) is written as
H(s) = = - • r (2-3-8)
V q u t (^) _ ^
Vm(s) 2 s2 +(aN !Qp)-s + c o n
27
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where Qp is the Q of poles and cdn is the notch frequency. Although the filter is
capable of an input impedance match to the signal source resistance over the entire
signal frequency range of interest, the circuit has a shortfall in terms of tuning
capability. According to the equations for components values in Figure 12, the
inductances are the function of the notch frequency, however, the inductance cannot
be tunable in passive element. And the resistive loss of inductor of L2 has influence
on the attenuation at the notch frequency. Especially, the sufficient attenuation could
not be obtained in case of using on-chip spiral inductors.
OUT
IN
Figure 12. Input impedance matched notch filter whose quality factor of poles is Qp,
the notch frequency is coN and the output load is Rs.
2.3.4 Conclusions
In this chapter, the state-of-the-art topologies to realize the integrated notch
filters were demonstrated through reviewing the previous works. The way of filter
design to obtain the notch characteristic can be categorized into using the input
impedance function and using the transfer voltage-gain function. Another is to
approach in terms of the input impedance matching for maximum power transfer.
28
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The input impedance function, which is realized with LC circuit, is suffered
from the resistive loss of inductor. To overcome the inherent low quality factor of
inductor, the negative resistance circuit or the LC circuit combined with a transistor,
which are so-called Q-tuning circuit, should be introduced in the applications. Also,
an active gyrator circuit without monolithic inductor, which has huge merit in terms
of chip area, was presented. And the way to use the source degenerated amplifier
topology and the LC circuit with the Gm-sources to derive transfer voltage-gain
function directly was proposed for Q of zeros to make infinity. To implement the
filters in a system, however, the concerns about active filter design such as power
consumption, noise figure, non-linearity, stability, and so on are required.
Although a commonly used passive RLC filter is for the application
considered the impedance matching, it has the limitation to tuning capability and the
attenuation at the notch frequency is poor due to the loss of inductors as well.
To overcome the above shortfalls in the previous works, a new approach to
realize notch filter with passive RLC circuit will be proposed in the next chapter.
Through the analysis using the open-circuit impedance parameters, full attenuation
would be acquired only by adjusting the value of the resistive load rather than by
introducing the active circuit as proposed in the previous works.
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2.4 Impact of Research
The availability of the notch filters that meet all or most of the design
objectives outlined in Chapter 2.2 will greatly make the design of their applications
in RF circuits easy. In this chapter, the benefits and applications of the notch filters
proposed in this research are delineated.
2.4.1 Benefits
The passive RLC notch filters proposed in this research circumvent the
major drawbacks of active RC filters and other passive filters, which need the active
circuit to cancel the inherent low quality of integrated inductors.
The notch filters proposed in this research are superior to the state-of-the-art
active and other passive notch filters in the following ways:
• Full attenuation at the notch frequency only by adjusting the resistance.
• Controllability of the symmetrical notch frequency response.
• Larger Qmb than the inherent Qm a ctual of the integrated inductors.
• Availability into the following stages with the gate of MOSFET’s.
30
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2.4.2 Applications
The proposed notch filter can be applied for the following systems. For these
applications the impedance matching considerations could be needed, if necessary:
• Band rejection filtering function block.
• Analog comb filters.
• Heterodyne receivers in front-end electronics.
In this proposal, the new methodologies to design the notch filters are
provided as followings:
• An approach to make the notch characteristic by using Z-parameters.
• Introduction of a third-order transfer voltage-gain function.
• The pole-zero cancellation to reduce the parasitic capacitance effect of
passive on-chip inductors at the output port.
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2.5 Design Background
In this chapter, the fundamental background to implement notch filters in this
proposal will be described. By using the input-to-output transfer voltage-gain
function represented by the open-circuit impedance parameters, the characteristic of
a third order passive RLC notch filter can be obtained. A prototype of the proposed
notch filter configuration will be showed and the simulation results will be
demonstrated to ensure its operation. To realize the on-chip notch filter as will be
explained in Chapter 2.6, the equivalent circuit modeling of the integrated inductors
from the previous works will be introduced.
2.5.1 Theory
The notch characteristic can be acquired to consider an input-to-output
transfer function. In this proposal, the transfer voltage-gain function is directly used
to realize the notch filter.
Figure 13 illustrates a proposed notch filter structure, which has an input port,
an open-output port, a linear two-port network of the dotted box, and a base branch
element, Z b ( s ) . The linear two-port network in the dotted box can be represented by
Z-parameters, open-circuit impedance parameters [22], and the input-to-output
transfer voltage-gain function, H(s), of this configuration can be expressed as
32
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fj(s) — ^r ° U T ^ — ^ 2 1 ^ B ^
VlN{s) ~ Zn {s) + ZB{s)
(2-5-1)
For a notch characteristic at the angular notch frequency, con = 2iifN, the
numerator of H(s) should be zero while the denominator of H(s) should not be zero.
That is the output port should be shorted to the Ground at the notch frequency while
the input port should not be. As mathematical expressions,
Hence, the relations of the magnitudes and the phase angles between the
element in the box and the branch element are as followings,
In other words, the transmission zeros of the transfer voltage-gain function of
the given notch structure can be achieved by setting the value of the branch elements,
Zb(s), to the value satisfied with the conditions as (2-5-2). From this relations, if the
impedance Z2/(s) has the phase angle of -180°, i.e. the negative resistance of Z2i, at
the notch frequency, then Zb(s) can be set only to a resistor for notch filtering.
In the configuration with the following stage of the notch filter, if the input
impedance of the connected with the open-output port of the notch filter is much
higher than the impedance looking into the output port of the notch filter, the
situation of the open-output port is not a severe limitation. In the heterodyne receiver
system as Figure 1, the notch filter is followed by the mixer with the input to the
^ 2 1 O '® J V ) ^ B ( j ® N ) — ®
Z 21 O'® A i) = - Z B (jto N ) = Zb(Jcd n ) • e x p (-;l 80°)
\zB 0'®jv ) |_ 1^21 (y®jv )|
Z Z B (Ja> N) = Z Z 2 1 (j 0)N ) +180°
(2-5-2)
33
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gate of MOSFET and the input impedance looking into the gate of MOSFET is
typically higher than the output impedance of the proposed notch filter.
OUT IN
Figure 13. A proposed notch filter structure. The configuration has an input port, an
open-output port, a linear two-port network of the dotted box, which
can be represented by Z-parameters, and a base branch element, ZB.
2.5.2 Prototype of the Proposed Passive Notch Filter
A circuit of a proposed notch filter is shown in Figure 14. The elements in
the dotted box are composed of a 7i-match network with L, Cj and C2. A resistor R B
is the base branch element. For simplicity, the on-chip inductor is modeled as an
ideal inductor of L with a series resistance, Rin d, representing its loss, which is
represented by the inherent quality factor, Qin d, of inductor.
The open-circuit forward trans-impedance, Z2i(s), of the 71-match network of
the dotted box in Figure 14 is expressed in (2-5-3).
34
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z 2 i (X) =
l 1
(2-5-3)
5 [(Cj +C2) + s 2LCx C 2 + sRin d C\C2]
At the angular resonance frequency, < x > n , the phase angle of Z2i(jo),\) is -180°
(i.e. Z21(s) has only a 1/s2 term in (2-5-3)) and the transmission zeroes can be
achieved by setting the value of RB to the magnitude of Z2i(jmN ) as follows,
< ° N =
c,+c2
1 l c \ c 2
(2-5-4)
~ 1 ^ 2 1 UO>N)\ —
o > N2Rin d C,C 2 ^ ( C , + C 2)
(2-5-5)
IN
o >-
ind
C,
i , = o
-O ^ OUT
Figure 14. A proposed notch filter circuit. The elements in the dotted box are
composed of a 7i-match network with LC and a resistor RB is a base branch
element. Rjndis the series resistance due to inherent Qin d of inductor L.
Figure 15 demonstrated one example of the frequency response of Z2i of the
7t-match network, which has the calculatedfy of 1530 MHz with L = 8nH, C\ = 4.9
pF, C2 = 1.87 pF, and Rm c i = 8.16 Q. In Figure 15-a, the phase angle of Z2i is varying
from -90° to -270° near the resonance frequency and the curve passed -180° point at
f y — 1530 MHz. Its slope of the transition region from an inductive to capacitive
35
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impedance would relate the -3 dB quality factor of the notch filter. The magnitude of
Z21 at the resonance frequency determines the value of i?gas (2-5-5), which reads as
-145 Q in Figure 15-b.
u r
a >
a >
a
" O
N
o
0 >
c
< B
•c
a.
-90
-180
-270
1E+10 1E+09
E
-e
.0
N
O
■ §
3
E
O )
( 0
250
200
150
100
50
0
1E+08
Frequency (Hz)
1E+09
Frequency (Hz)
1E+10
(a) (b)
Figure 15. Frequency response of Z2 I of the 7c-match network in Figure 14. (a) Phase
angle characteristic: The phase angle is varying from -90° to -270° near
the resonance frequency and the cross point with frequency-axis reads the
f N= 1530 MHz. Its slope would relate the -3 dB quality factor of the notch
filter, (b) Magnitude characteristic: The magnitude at the ^determines the
value of Rb.
It is noticed that the complete transmission zeros can be achieved only by
resistance. As mentioned in Chapter 2.3, the active circuits could be used for
cancellation of the resistive loss of the inductor in the previous works, however, only
the resistive load can act for it in this approach.
Meanwhile, the open-circuit input impedance, Z j i ( s ) , is
1 1 + s 2 LC-, + sRin iiC2
Z u (s)
s [(C, + C 2) + 5'2I C ]C2 + si?^ C 1 C2]
(2-5-6)
36
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From the (2-5-1) with (2-5-3) and (2-5-6) for the notch filter circuit of Figure
14, the transfer voltage-gain function, H(s), can be represented by (2-5-7) and can be
simplified as (2-5-8) using the normalized frequency, y, with (2-5-4), and (2-5-5)
[Appendix A].
H (s) =
________ 1 + s 2RBRm d Cx C 2 + sRB (C, + C2) + s 3LRBCx C 2________
1 + s \ L C 2 + RBRm dC,C2) + s[Rm dC 2 + Rb (Q + C2)] + s 3LRBCx C2
(2-5-7)
H(jy)
i-y2 +jyQindQ--y2 )
1 - a y 2 + jyQ md( b - y 2)
(2-5-8)
where
y = co/(oN
Q i n d ~ R i n d
a = l + C 2 IC x
o
Q , irtd
To obtain the -3 dB quality factor (Qmb) of the notch filter, an equation
\H(jy)\J=l/2 is used [23]. The equation can be deduced to a 3rd degree equation o fy
as
f(y) = (y 2y + A ( y y + B ( y ' ) + C = 0
2x2
(2-5-9)
where
A s _ ^ Cr(Cr+ 2>
Q , in d
/
B = 1
Q , in d
Cr +1
o 2
\ in d J
C = 1 / qJ
Cr s C 2/C,
37
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As described in (2-5-9), the coefficients of the equation are the functions of
Cr, the capacitance ratio, and the inherent Qin ( i of inductor. Hence, the roots of the
equation, f(y)= 0 , are related to these two parameters.
To explain the relations between the roots and the parameters, the plots of
fly) are shown in Figure 16 of the cases of Qm ( i = 5, 20, and 50, which represent the
examples of a spiral on-chip inductor, a discrete inductor and a bonding wire
inductor, respectively. Q ^ b of the notch filter can be calculated by
e * » = — z — < 2-5- 10)
y M g h y i o w
where yhig h and yio w (yhigh> yiow) are two roots of (2-5-7) around y = 1 (normalized
notch frequency) as shown in Figure 16. For Cr = 0.1 and Qm (i = 5, Qmi is computed
as 4.7 because yhigh - 1.122 and yio w = 0.9007.
With the larger Qin d or smaller Cr = C2/C 1, the notch filters have the larger
QsdB and the more symmetrical notch characteristics, which means an identical gain
at frequencies below notch to the gain at frequencies above a notch.
When C2/C 1 « 1, Q3dB of notch filter approaches to Qm d of the inductor. In
particular, the notch frequency can be controlled by only C2 and RB is almost
constant with fixed C/. This feature results in the better attenuation at the notch
frequency of a tunable notch filter with tunable capacitor of C2.
As an example, Figure 17 is the HSPICE simulation results to show the
feasible tuning capability of the notch filter over from 860 MHz to 1560 MHz range.
The circuit for the simulations is shown in Figure 14 and the ideal inductor with a
38
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
series resistance representing its loss was used. The values of elements were L - 175
nH, R m = 47 Q, Rb = 365 Q, C/ = 10 pF and various Q = 200 fF, 100 fF, and 60 fF.
0.01 0.2 0.02
i 0
> c r
- 0.02
- 0.01 - 0.2
1.0 1.1 0.9
1.2 0.95 1 1.05 0.8 1
y = w /w N y = w /w N y = w /w N
(a) (b) (c)
Figure 16. Plots off(y) in (2-5-9). The two points of intercept off(y) with f(y) = 0 are
yhig h and yi„w by which Q3 d B of the notch filter can be calculated. Thick Solid
Line: Cr= 1, Dotted Line: Cr = 0.1, Thin Solid Line: Cr = 0.01 (a) Qim i = 5
(b) Qm d = 20 (c) Qm d =50
When C2 was 200 fF (C /C / = 0.02), the notch characteristics are fy = 860
MHz, Qub was almost 20 and the attenuation at the notch frequency was about 50
dB. As C2 became smaller, the notch frequency became larger and better Qmh was
obtained due to the fixed R in d (i.e. higher Qm d) in the simulations. The worse
attenuations at the higher notch frequencies, for instance, 36 dB from the curve for
/n = 1560 MHz, resulted from the mismatched i?^to each circuit in the work, which
is explained with (2-5-5).
When the notch frequency is tuned, the fixed Rb makes the attenuation at the
notch frequency worse in the circuit of Figure 14. The attenuation dependency on
39
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the Rb will be explained in Chapter 2.6. This problem can be solved by realization of
Rb as a variable resistor with a MOSFET operating in the linear region. With a
suitable gate-to-source voltage, Vos, the incremental resistance between drain-to-
source, r*, of a long channel MOSFET in the linear region is from the first-order
approximation as
W
(2-5-11)
$ -10
S. -20
-30
-40
-50
1.5E+9 1.0E+9
Frequency (Hz)
Figure 17. Transfer voltage gain characteristics of the circuit in Figure 14. Thick Solid
Line: f N= 860 MHz, Dotted Line: f N = 1210 MHz, Thin Solid Line: f N =
1560 MHz.
In this work as shown in Figure 17 and Table 1, the values of elements are
not feasible to implement the notch filter on a chip. The inductance was too large to
realize with the current IC technology, and the Q,„d is rather suitable for a discrete
40
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component. For the realistic on-chip inductors, their equivalent circuit models will
be described in the following chapter.
Table 1. Summary of the elements values of Figure 17 and the simulation results
I n
860 MHz 1210 MHz 1560 MHz
L 175 nH 175 nH 175 nH
Rind
47 Q 47 Q 47 Q
Qind
20.1 28.3 36.5
Cj 10 pF 10 pF 10 pF
c 2
200 fF 100 fF 60 fF
I I
0.02 0.01 0.006
Rb
365 Q 365 Q 365 Q
Attenuation 49.6 dB 39.6 dB 35.6 dB
Qmb
19.7 27.8 36.2
2.5.3 Equivalent Circuit Models of On-chip Inductors
In the RF circuits, the poor inductor is by far the most severe shortcoming of
standard IC process. Although active circuits can sometimes synthesize the
equivalent of an inductor such as gyrator type device, higher noise, distortion and
power consumption than real on-chip passive inductors are serious limitations. In the
following chapters, as on-chip inductors, bonding wire inductors and planar spiral
inductors are described.
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2.5.3.1 Bonding Wire Inductors
The automatic bonding machines used in the wafer manufacturing allow not
only bonding wires from on-chip pads to package pins, but also a bonding wire from
on-chip pad to another.
The Gold bonding wire inductor offers the advantages of its low intrinsic
series resistance, which allows the realization of inductors to have high quality
factor. Also, the parasitic capacitance to the substrate is limited by the capacitances
of both of two bonding pads.
The cross-section view of a bonding wire inductor and its equivalent circuit
model are depicted in Figure 18. The first-order formula to compute the inductance
of L in nH is found to be [25]
/
In
I
1
~ r
L = — -0.75 + -
5 \ r ) /
where / is the length of wire in mm and r is the radius of the cross-section in mm. As
an example, L = 4.57 nH for / = 4 mm and r = 12.5 pm.
The manufacturing process of bonding is not perfectly reproducible and the
shape of the wire could vary from chip to chip. This cause an uncertainty in the final
inductance obtained, which must be incorporated in the total tuning range of the
system. Typically, the height above the substrate of H = 150 ± 50 pm results in 2 %
variation in its inductance and the vertical bending in the bonding wire of h = 75 ±75
42
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pm does less than 0.5 % variation. And the 10 % variation of radius o f wire leads to
3 % variation of the inductance [26].
C d Oxide
Substrate
I C
| junction
C-
junction
Figure 18. Cross-section view of a bonding wire inductor and its equivalent circuit. L
is self-inductance and Rin d is series resistance due to loss including skin
effect. CjU n c t i Q n is added to reduce the effect of Cp a d . H is the height of a wire
above the substrate and h is the vertical bending in the bonding wire.
The series resistance of inductor, Rir u j, to be express the resistive loss of the
inductor is estimated as the following equation,
Ri n n = l -V7 l - r v t eff\ X = /•
2 ft -rcr ■ 8 -(\-e /s ) (2-5-13)
where a is the conductivity of the wire metal, te g is the effective thickness of
metalization, and t is the physical thickness of the interconnect. And the skin depth,
S, which describes the degree of penetration by the electric current and magnetic
flux into the surface of a conductor at high frequencies, is given for by
8 =
I — S
ft-o-Ho • /
(2-5-14)
43
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w here/is the signal frequency and ji0 is permeability (47I-E-7 H/m) of free space. As
the skin depth, 5, decreases with frequency, Rind increases. At 1 GHz, the skin depth
of Gold wire (o = 2.35 pQ cm ) is 2.4 pm and Rm d per length is 0.125 Q/mm. For a
Gold wire of 4 mm length, a possible quality factor, Qin d (=o)L/Rin d ), at 1 GHz can be
computed as 57.4. However, at 2 GHz, Rin d per length is 0.175 Q/mm. This could
certainly limit the possibilities of use of bonding wire inductors.
The capacitance, Cpad, between the pad and the substrate depends on the
bonding pad structure used in the specific technology. By the placing a floating PN
junction underneath the bonding pad, the total capacitance is alleviated. For instance,
for Apad = 100x100 pm2, /0 J C = 2 pm and a typical N-well/P-sub, each parasitic
capacitance of the pads, Ctot, is computed as -150 fF.
f-'to/ — ^ p a d H ^ ju n c tio n ~ ^ pad ’ ox A o x ) ^ ^ j u n c t i o n ( A ' 5 1 5 )
where eo x is a dielectric permittivity of oxide and C Ju n ctlo n is the junction capacitance
of N-well/P-sub with the same area as the pad.
2.5.3.2 Planar Spiral On-chip Inductors
The widely used on-chip inductor is the planar spiral, a square version of
whose perspective view and equivalent circuit are shown in Figure 19. The spiral
inductor is preferred over bonding wire inductor because of its smaller area, a better
accuracy and more confident reproducibility. The bulk of the spiral is implemented
in the top-level metal, and the center of the spiral is connected to a lower level of
44
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metal through a via-contact. Although the actual spirals are not symmetrical, the
model is symmetrical and the error introduced is negligible in most instances [24].
Although the inductance, L, of such a spiral type is a complicated function of
geometry, and accurate computations require the use of field solvers of
Greenhouse’s method, a zeroth-order estimate for hand-calculations is,
where ju 0 is permeability (47:-E-7 H/m) of free space, n is the number of top-level
metal turns and r is the radius of outer dimension of a spiral inductor. This equation
is semi empirical and has accuracy to about ± 30 %.
By removing a few of the innermost turns, the hollow square spiral inductor
has an improvement over its traditional square spiral due to diminished series
resistance and, hence, higher Qin c j. Monolithic inductor consumes large area, for
example, required diameter 220 pm for L = 30 nH. In general, practical on-chip
inductances are in the neighborhood of 10 nH or less.
Rin ij is estimated as the following equation,
where a is the conductivity of the top level metal, te jj is the effective thickness of
metalization, I is the total length of the winding, W and t are the width and the
physical thickness of the interconnect. And the skin depth, S, is given by (2-5-14).
At 1 GHz, the skin depth of Aluminum with t - 3 pm is 2.8 pm and its te jf is 1.8 pm.
The shunt capacitance, Cs, across the inductor that is modeled as the plate
capacitor with the lower level metal is
L ~ /i0'n2-r (2-5-16)
(2-5-17)
45
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^ind
o x _
sub'.
sub sub sub
Figure 19. Perspective view of a square spiral inductor and its equivalent circuit. L is
self-inductance and Ri n c i is series resistance due to loss including skin effect.
Cs is due to lower metal cross-under and Co x results from oxide below the
top-level metal. CS U b and RS U b are functions of the silicon substrate doping.
Cs =n-W 2 -(sox/toxm) (2-5-18)
where n is the number of overlap, W is the width of spiral line, eo x is a dielectric
permittivity of oxide, and to x m is the oxide thickness between the spiral and the
under pass.
As parameters to represent the substrate parasitic, Cox, Csu b, and Rsub are the
oxide capacitance, the silicon substrate capacitance and resistance, respectively.
C „, =(1/2 \ I W - C ,
2
' si sub
R-sub ~
I -W ■ G„. „
(2-5-19)
(2-5-20)
(2-5-21)
si sub
46
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where to x is the oxide thickness between the top metal and the substrate and C s i s u b,
G Si_sub are the fitting parameters and the functions of the silicon substrate doping.
•2 9 9
C Si_ su h has a typical range between 10' and 10' fF/pm , and a typical value of G si sub
is about 10'7 S/pm2.
With the above parameters, the actual quality factor o f an inductor is
calculated by the following equations [13],
Energy Stored
Q ind a c tu a l ~ '^7l' “ 7 r i 7] 7] . f 7~ (2-5-22)
Energy Loss in une Oscillation Cycle
Peak Magnetic Energy - Peak Electrical Energy
= 2 n -------------------------------------------------------------------
Energy Loss in One Oscillation Cycle
= Qm d ■ (Substrate loss factor) ■ (Self resonance factor)
co-L R
p
Rind Rp + [(® • L/Rind) 2 + 1 ] ' Rind
R l d ( C s + C „ )
L
a L ( C S + C )
where
n 1 R sub (G q x + C suh )
P v 2C 2 0 X-Rsuh C
= l + a> 2 (Co x + Csub) ■ Csu h R 2 s u h
p m 1 + o 2(C0X+Csuh) 2 -Rlh
Figure 20 shows the extracted quality factor of the inductor from the
previous work [13]. The test structure to extract the parameters is following as; the
top Aluminum metal with resistivity of 12 mQ/sq has W= 15 pm, line space = 5 pm,
t = 2 pm, n = l turns, r =150 pm, and / = 6440 pm. The oxide thickness between top
metal and pattemed-shield-ground (PSG), which reduce the capacitive coupling and
47
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noise coupling from the substrate, was tox = 5.2 pm and 10-20 Q cm bulk silicon
substrate was used.
From the measured S-parameters, the characteristic impedance and the
complex propagation constant were computed. From the computed numbers, the
extracted parameters were; 1 = 8 nFl, Cs = 18 fF, Co x //Cmb ~ 270 fF, and Rsub was
almost infinity. With these parameters, the calculated Qin d a ctu a l using (2-5-22) is
shown in Figure 20.
10
8
6
4
2
0
1E+10 1EH)9
Frequency (Hz)
Figure 20. The quality factor of the inductor having L = 8 nH from the previous work
[13]. Solid line is for Qin d a c ,u a i, and the dotted Line represents Qin d =
coL/Rm d . At the 1.8 GHz, Qm d a c tu a l is about 7.5 and decreases drastically due
to substrate parasitic at high frequencies.
The Qmd a ctu a l increases to about 7.5 until the frequency increase to 1.8 GHz,
and above it, drastically decreases by the self-resonance effect. The substrate loss
factor in (2-5-22) can be ignored because the infinite Rsub is assumed in the work.
Meanwhile, the Qind defined as coL/Rin d increases with frequency.
48
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To ensure the operation o f the proposed notch filter as will be shown Chapter
2.6, the equivalent circuit model in Figure 19 and the extracted parameters in Figure
20 will be used. It is interesting for the compensated substrate parasitic by the pole-
zero cancellation method to result in larger Qmb of the notch fdter than the Qmd actm i
of the inductors. This will be explained in detail in the next chapter.
49
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2.6 Design And Simulation Results
In this chapter, the proposed notch filter incorporated with the on-chip spiral
inductors displayed in Chapter 2.5.3.2 was examined. The parasitic of spiral
inductors caused unsymmetrical notch characteristic and, to reduce this effects, the
concept of the pole-zero cancellation was introduced. To this end, the additional load
was introduced at the output port of the notch filter. The HSPICE simulations of the
final configuration were provided.
2.6.1 Prototype Design Using Spiral Inductors
The prototype of the proposed notch filter in Figure 14 is again depicted with
the planar spiral inductor as shown in Figure 21-a. The values of the elements of a
planar inductor, which were measured in the previous work [13] or calculated
according to (2-5-19), were 1 = 8 nH, C, = 18 fF, Coxi= Cox2= 320 fF, Csubi = Csu b 2
= 1728 fF, and Rsubi = RS u b 2 = 10 MQ. In the simulations, Rm ( j was emulated with
frequency dependent feature as shown in (2-5-17). For the arbitrary selected notch
frequency of 2400 MHz, Cy = 2 pF, C2 = 758 fF and Rb = 312 Q were used. The
simulation results as displayed in Figure 21-b reveal that the notch frequency was
2362 MHz, the transfer voltage-gain at 2362 MHz was -70.9 dB, and the frequency
response was unsymmetrical. The transfer voltage-gain at higher frequencies than
50
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the notch frequency was 3.5 dB smaller than that at lower frequencies and the
peaking in the lower band appeared (+9.6 dB at 1910 MHz).
This unsymmetrical characteristic was offered by the right-hand sided parasitic part
of the spiral inductor displayed in Figure 21-a. Because the resonance frequency of
L-Cs tank was computed as about 13.3 GHz, this was not due to the effect of Cs. In
fact, the elements of C0X 2, Csub 2 and Rsub 2 acted as a load of the filter in the structure.
To ensure the load effects, the simulation for the virtual configuration without the
parasitic branch at the output port as shown in Figure 22-a was performed. The
result in Figure 22-b showed the symmetrical frequency response and non-peaking
as expected. And the notch frequency was not varied. On the analogy of this result,
the added capacitance at the output port on purpose could produce a gain at the
peaking frequency.
On-Chip Spiral Inductor
x
10
0
-10
(3 -20
S -30
5 -40
•I
g -50
I- -60
-70
1E+10
Frequency (Hz)
(a) (b)
Figure 21. (a) A prototype notch filter with an on-chip spiral inductor, (b) Its
frequency response showed the unsymmetrical characteristic and a peaking.
51
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10
' IN
o—
C
C.
R .„
R..
OUT
-O
( 0
C 9 -20
0 )
S ’ -30
> -40
1E+08 1E-HJ9
Frequency (Hz)
1E+10
(a) (b)
Figure 22. (a) Virtual configuration to ensure the load effects, (b) The frequency
response had a symmetrical characteristic like Figure 17.
The preferred frequency response, whether the symmetrical is or not, is
dependent on the application of the filter. When the notch filter is used as an all-pass
filter except the notch region, the symmetrical feature is necessary. If the notch
filters in the heterodyne receivers have certain gain at the signal frequency, then the
relatively lower attenuation at the image signal frequency compared with the gain at
the signal frequency can be acquired. For instance, from Figure 21-b, the peaking of
9.6 dB at 1910 MHz occurred and the notch appeared -70.9 dB at 2362 MHz. In the
case that IF frequency was (2362-1910)/2 = 226 MHz and the signal frequency was
1910 MHz, then the relative attenuation at the notch frequency was obtained by 80.5
dB. The problem appearing in Figure 21-b was that the unsymmetrical frequency
response could not be diminished only by the added capacitor at the output port.
Furthermore, in the circuit of Figure 21-a, the peaking frequency could not be
reduced to less than 1910 MHz by the added capacitance. To mitigate this shortfall,
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the way to control the symmetry and to have arbitrary peaking frequency will be
demonstrated in the following chapter.
2.6.2 Method of Pole-Zero Cancellation
When the circuit in Figure 23 is compared with that in Figure 14, the load,
Zl(s), is added at the output port. In fact, ZL(s) includes the right-hand sided branch
of inductor in Figure 21. At this juncture, the transfer voltage gain function, H(s), is
found to be
H{s) = Yo u M =-----------------(Z 2 1 + Z B) • zL ----------------- (2 _ 6 _ 1 }
Kn(s) (ZU+ Z B)-ZL+ Z HZ22- Z 21 + (Zn + Z22- 2 Z 2])-ZB
By the load of ZL(s) term, the numerator and denominator of H(s) with
respect to (2-5-1) is modified. In other word, the load produces another poles and
zeros in the transfer function.
By a tacit inspection, setting the ZL(s) term to make \ZuZ 22-Z21 +(Zu+Z22-
2 Z2i)-Zb\ term as the product of ZL renders the zeros of the transfer voltage-gain
function determined only by (Z2i(s) + ZB (s)) like in (2-5-1). As a result, the
additional zeroes due to the load can be removed and the poles become modified
with respect to (2-5-1).
The open-circuit output impedance, Z22(s), of the 71-match network of the
dotted box in Figure 14 is expressed in (2-6-2).
53
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z (A = i 1 + s 2LCx + sRindCx
llK s [(C,+C2) + 52I C 1 C2 + ^ w C1 C2]
(2-6-2)
OUT
Figure 23. Illustration of the load effect of ZL at the output port on the filter.
By using (2-5-3), (2-5-6) and (2-6-2), the term of \ZuZ 22-Z21 +{Zu+Z22
2 Z2i)-ZB \ is shown to be
1
ZnZ 22 Z2 1 +(Zn +Z 21 2 Z 2l)-ZB —
________Rjnd + SL________
, 2 LCx C2 Rm Cx C2
1 + 5 ------- -— -— 1 “ 5 -
5 ( C , + C 2)
- + Zo
Cj + c2 c, + c2
(2-6-3)
According to (2-6-3), there can be two choices for Zi/s). However,
[l/s(Ci+C2) + ZB ] term, which is the series combination of (C7+C 2) and ZB , can not
express the capacitance between the output node and Ground node like the parasitic
one of the inductor, and the resultant transfer function has a low-pass-notch
characteristic. Hence, for the pole-zero cancellation, ZL should be considered as the
parallel combination of a spiral inductor, Ll, and a capacitor, C/.. For the simple
54
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analysis, the spiral inductor can be modeled as an ideal inductor with a series
resistance, Rin d L, representing its loss;
Z ,0 ) =
R in dL +S^L
1 + s L lCl + sRin d L CL
(2-6-4)
where Cl contains the parasitic capacitances of the inductors, L and Ll , at the output
node.
Setting toN2 = 1/ (Ll Cl ) and assuming Qm d = con Ll / Rindl = coNL/ Rin d , hence,
the relation between [ZiiZ22-Z2i2+(Zii+Z22-2 Z2i)-Zb\ and Z/,is by using (2-6-3) and
(2-6-4),
ZHZ2 2 Z 2 1 +(ZU+ Z 2 2 2Z2])-Z b -
L_
IT
i
5(C1+C2)
■+zB z, (2-6-5)
As a result, the new transfer function is
H(s)
^2\ +
Z\\ + Z R +
1
s(C,+C2)
+ z.
(2-6-6)
where the term of the parasitic capacitances of inductors cannot be found and the
zeros of the transfer function are determined only by (Z2/ + Zg) as expected.
By using (2-5-3), (2-5-6), (2-6-2) and Zg - Rg in Figure 14, the transfer
function is of the form
H(s)
\ + s 2RBRin d C,C2 +sRB(Cx+C2) + s iLRBCx C 2
(1 + Lr) + s 2[U] + j[F] + 53(1 + Lr)LRB C,C2
(2-6-7)
where
L , ‘ L/L,=R,„JR
indL
55
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U = LC 2 + Lr • iC|C! +(1 + Lr)JI„Rm ,C ,C 2
c, + c 2
V = RindC2 +Lr ■ ^ ^ + (l + I ,) « <(C ,+C 2)
'“ 'I 2
With the normalization factor in Chapter 2.5, the normalized transfer
voltage-gain function, H(jy), is [Appendix B]
H(jy) = f 1 ^
i - y 2 +jyQm d( i - y 2) _
f 1 1
Q + Lr )
1 - a y 2 +jyQmd( b - y 2)
J + Lr;
•H N(jy) (2-6-8)
where
Q ind ~ ®nLI Rm d ~ I Rin d l,
a = l + m
2
6 = 1 + m f
m = 1 +
in d
c2 /c, '
I + i / i ,
From (2-6-8), the symmetrical notch characteristic can be found by
observing that the gain at DC is identical to that at infinity high frequency. And, for
the special case without the load in Chapter 2.5.2 (i.e. L « Li), the transfer function
in (2-6-8) approaches to (2-5-8) as expected.
To figure out the relation between the Qmb of the notch filter and the
electrical parameters, the equation \H\{jy)\2=l/2 can be considered. As a similar
2 t
fashion like an analysis in Chapter 2.5.2, an equation \H^(jy)\ =1/2 instead of
\H(jy) ' \ = ] / 2 should be used to obtain the Qmb- The equation can be deduced to a 3
rd
degree equation of y as
56
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f{y) = {y2f +A{y2) 2 +B{y2) + C = 0
where A = -2 + (1 - m 2 )/Qmd2 , B = \ - l / Q ind2 - (m/Qm / J , C =
o)^Lj
(2-6-9)
iIqJ ,
Q ind
R in d R i n d l .
m = 1 +
v
\ + L/L
L
As described in (2-6-9), the coefficients of the equation are the functions of
the capacitance ratio, Cr = C2 / C/, the inductance ratio, Lr = L / Ll , and the inherent
Qind of inductors. Hence, the roots of the equation, f(y)= 0, are related to these three
parameters.
0.1
0
- 0.1
1.0 1.2 0.8
0.1
0
- 0.1
1.0 1.2 0.8
y = w /w N
y = w /w N
(a) (b)
Figure 24. Plots off(y) in (2-6-9) with Qin d = 5. The two points of intersection off(y)
with f(y) = 0 are and y/o w by which Qua can be calculated. Thick solid
line: Lr = 1, Thin solid line: Lr = 2, Dotted line: Lr = 4. (a) Cr = 1 (b) Cr =
0.1
The plots of f(y) are shown in Figure 24, which explains the relations
between the roots and the parameters in the cases of Qin d = 5. The Qub of the notch
filter can be calculated by Q3d B= ( yhigh - yiow) '1 where y h ig h and y !fn v (yhigh> yiow) are
57
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two roots of (2-6-9) around y = 1 (normalized notch frequency) as shown in Figure
24.
For Cr = 0.1 and Lr = 1, yhigh = 1.105 and yum= 0.9065. So Qmb is computed
as 5.04. As mentioned in Chapter 2.5.2, the Qmb in the case of without the load is
4.7. With the load by the pole-zero cancellation, the Qmr of the notch filter slightly
exceeds the Qin d (=5) of inductors. Furthermore, it is interesting to observe that the
Qmb increases as the ratio of the inductors, Lr, increases in the case of Cr = 1.
Ftowever, this cannot be significantly found in the case of Cr = 0.1. Meanwhile, the
transfer gains at DC and the infinity high frequency decrease by the factor o f 1/(1+
Lr). For example, for Lr = 1 (i.e. L = Ll), the transfer voltage-gain in the pass band is
-6.02 dB.
2.6.3 Design Example
The complete schematic of the proposed notch filter is shown in Figure 25.
Compared with that of Chapter 2.5.1, another spiral inductor and additional
capacitor Ca dd appear at the output port. In the simulation work displayed in Figure
25, the spiral inductor as a load was identical to one in the notch filter block, i.e. L =
L l- The Cl in the previous chapter consists of Ca dd and the parasitic capacitances of
inductors. In other words,
CL = + (C„ 1 1 C,,„) + ( C ^ // C „„,) + C„ + (1 - Vm /VO IIT) ■ C, (2-6-10)
where Ca dd is the capacitance for the fitting of Cl. The term of (Co x //Cmb ) results
58
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from the right-hand sided branch o f the inductor, L, and the term of (Co xi //('sub/)
comes from the left-hand sided branch of the inductor o f the load, Li. The
coefficient o f Cs in (2-6-10) is due to the Miller’s effects, which is available only if
the voltage-gain of Vout/V/n is independent value [27]. Although the voltage gain in
all frequency range is not constant, as a crude approximation for simplicity, it could
be assumed as 1/2 (= -6.02 dB) in case of L = Ll . The parameters in Table 2 were
used in the simulations.
On-Chip Spiral Inductor O U T On-Chip Spiral Inductor
o
Figure 25. Complete schematic of the proposed notch filter with the load, which is the
parallel combination of a spiral inductor and a capacitor, Ca d d .
Figure 26-a shows the frequency response of the notch filter in Figure 25. As
expected, the symmetrical notch characteristic was obtained and the peaking did not
appear. The transfer voltage-gain in the pass band was -6.02 dB. The magnified
region near the notch frequency is displayed in Figure 26-b in which the response of
the proposed notch filter was added by 6.02 dB for easy comparison. The sharpness
o f the proposed notch filter slightly exceeded that of virtual configuration and the
59
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measured QsdB of the notch filter was about 11.1. It is noted that the Q,„u a ctu a l of
inductors at the notch frequency is 6.3 according to Figure 20.
10
o
-10
C D -20
-50
-70
1E+10
c
< 5
C D
«
S>
a
-10
2E+9 3E+9 4E+9
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 26. (a) Frequency response of the proposed notch filter showed the symmetrical
notch characteristic and no peaking. The gain in the pass band was -6.02 dB.
(b) The magnified plot of (a) near the notch frequency. Thick solid line: With
the load + 6.02 dB, Thin solid line: Without the load, Dotted line: Virtual
configuration.
-20
-80
320 340 300 280
2370
2350
280 300 320 340
R B (ohms) R B (ohms)
(a) (b)
Figure 27. (a) Dependence of the attenuation on RB . (b) Dependence of the notch
frequency on RB .
60
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The attenuation dependence due to the RB variation is shown in Figure 27-a.
It also shows a notch-like characteristic, which had 73 dB attenuation at RB = 311.4
Q. For the attenuation larger than 40 dB, the RB was needed within the range of
311.4 Q± 1.2 %. This means that the replacement with a MOSFET operating in the
linear region could be required for the realizations to compensate the fabrication
process variation. The notch frequency fluctuation due to RB variation of ±10 % was
less than 0.05 %, which can be negligible as shown in Figure 27-b.
-10
(3 -20
5 -30
5
> . 40
-50
-60
-70
Frequency (Hz)
Figure 28. Dependence of the frequency response on Ca d d - Thick solid line: Ca d d = 9.7
fF, Thin solid line: Ca d d = 97 fF, Dotted line: Ca d li = 970 fF.
Figure 28 displays the frequency response due to Cadd variation with RB =
312 Q. With the larger Ca dd than 9.7 fF, the peaking was shown up, the peaking
frequency moved down, and the gain at the higher frequencies than the notch
frequency decreased. The notch frequency due to Ca dd variation was not changed. If
the peaking occurs at the signal frequency in the heterodyne receiver application, it
renders more attenuation at the notch frequency. As an example, for Ca tjd = 970 fF in
61
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Figure 28, the peaking of 6.8 dB at 1713 MHz occurred and the notch appeared -
68.9 dB at 2362 MHz. In the case that IF frequency is (2362-1713)/2 = 325 MHz
and the signal frequency is 1713 MHz, then the relative attenuation at the notch
frequency could be obtained by 75.7 dB.
Figure 29 shows the simulation results of the input impedances of the notch
filters in the cases of /y = 2362 MHz and 1530 MHz, and the values of circuit
elements were displayed in Table 2. At the notch frequency, the magnitude of the
input impedance, Z/,y, was 209 Q for /y = 2362 MHz and Z/y = 171 Q forfy = 1530
MHz. From the plots of phase angle, the impedances at the notch frequencies were
capacitive.
400
300
o 200
100
0E+00 1E+09 2E+09 3E+09 4E-K>9
$
£
O )
H .
2
N
o
■ 2
" 5 >
c
< 0
-c
Q .
90
0
-90
Frequency (Hz)
O E+O O 1E+09 2E409 3E+09 4E+09
Frequency (Hz)
(a) (b)
Figure 29. (a) Magnitude of the Z /y of the notch filter, (b) Phase angle of the Zm of the
notch filter. Thick solid line: = 2362 MHz, Thin solid line: f N= 1530
MHz
The input impedance of the notch filter as a load of a common-source
configuration amplifier determines the gain of the amplifier. As shown in Figure 30,
62
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the notch filters with the exchanged C/ and Q for the same notch frequency have
the different input impedance. In a heterodyne receiver application, the symmetrical
frequency response is not critical and Cr = C2 / Cj larger than 1 could be adopted.
6 0 0
500
o 400
o 300
200
100
0E+00 1E+09 2E+09 3E+09 4E+09
Frequency (Hz)
Figure 30. Magnitude of the Z!N of the notch filter according to different Cr for f N =
2362 MHz. Thick solid line: C/ = 758 fF, C2 = 2 pF, Thin solid line: C/ = 2
pF, C2 = 758 fF.
Figure 31 demonstrates the output impedances of the notch filters in the
cases o f/v = 2362 MHz and 1530 MHz. In the simulation, the source resistance of
50 Q was added in the input port. The magnitude of the output impedance, Z o u t, has
a band pass-like characteristic and the maximum magnitude value of the output
impedance occurred at the notch frequency. The magnitudes of the output
impedance, Z o u t , were 659 Q for /y = 2362 MHz and Z o u t = 306 Q for /y = 1530
MHz and their phase angles were changing from inductive to capacitive. The level
of the output impedance was not severe in the application to the gate of the
following transistors, such as in a mixer or a buffer.
63
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S F
£
a
$
3
N
o
o
-9 0
OE+OO fE + 09 2E+09 3E +09 4E +09
700
600
v > v
I 5 0 0
O
K
§
N
H .
o
■ 8
a
< w
4 0 0
30 0
'£ 200
O )
( 0
s too
OE+OO IE +09 2E+09 3E+09 4E+09
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 31. (a) Magnitude of the Z o u t of the notch filter, (b) Phase Angle of the ZO U r of
the notch filter. Thick solid l i n e : 2362 MHz, Thin solid line: f N= 1530
MHz
Table 2 demonstrates the examples of various notch frequencies with the
fixed Cr (= C2/C 1) of 0.38. For the inductors, the same parameters in the previous
chapters were used. Table 3 shows the results of the simulation. The attenuation was
calculated by the difference between the gain in the pass band and that at the notch
frequency. The achieved <2Ws of the notch filter are interesting aspect. The Qmb^
were about 85 % of Qm (i (= con L / Rln d) of inductors and, with the data of Jm = 2362
MHz and 1530 MHz, the Qmbs exceeded the Q m a ctu a l s, which contain the effect of
the parasitic capacitance to the substrate. In other words, the quality factor of the
notch filter is limited by Qm c i rather than by Q m actu a l, and the parasitic effect due to
Co x and CS u b in the integrated inductors was compensated by the pole-zero
cancellation. The parasitic capacitances of an inductor cause the degradation of the
Q in d actual at high frequencies. However theses capacitances are absorbed to the
64
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intentionally added capacitor in the proposed notch filter circuit, so the quality factor
of the filter could exceed that of the inductor and Qmb with respect to frequency
follows Q ind instead of Q inci actual-
Table 2. Examples of circuit parameters of Figure 25.
In
862 MHz 1258 MHz 1530 MHz 2362MHz
ll
8nH 8 ni l 8nH 8nH
Q in d
5.9 8.1 9.4 13.2
Q in d actual
5.5 6.9 7.4 6.5
C l 16.50 pF 7.80 pF 4.85 pF 2.0 pF
c 2
5.71 pF 2.66 pF 1.84 pF 758 fF
Cr = C /C ; 0.38 0.38 0.38 0.38
C a d d
3.70 pF 1.44 pF 796 fF 9.7 fF
Rb
49.0 Q 96.5 Q 144.5 Q 312.0 Q
Table 3. Simulation results of the circuit in Figure 25.
I n
862 MHz 1258 MHz 1530 MHz 2362MHz
Attenuation 54 dB 59 dB 55 dB 56 dB
Qmb
5.0 6.9 7.9 11.1
Q id flfQ in d
84.6 % 85.6 % 83.9 % 84.0 %
Q id fC Q in d actual
90.9 % 100.3 % 106.9 % 172.0 %
65
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2.7 Noise Considerations
This chapter shows the noise analysis of the proposed notch filter to consider
the implementation of low noise heterodyne receiver front end. For simplicity, the Z-
parameters of the notch filter depicted in Chapter 2.5 were used.
An equivalent circuit for the noise calculation at the signal frequency is
displayed in Figure 32. All parasitic capacitance of the input node, as well as the
parasitic capacitance of the inductor and the parasitic capacitance at the output node
of the previous stage, are absorbed into Cx.
crr~
OUT
Figure 32. Equivalent noise circuit model of the notch filter.
The noise current due to the source resistor, Rs, and the noise contribution of
the resistive loss of the inductor L are
I] = 4kT -G s - A/
i] = 4kT-G , - A/
(2-7-1)
(2-7-2)
66
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where Gs = 1 /Rs and Gl = 1IRP ~ Qind Rind- For the analysis by using the Z-
parameters of the notch filter, the noise current model of the inductor was used.
And the noise contribution of the base resistor, Rb, is
V 2R B= 4 kT -R B -A f (2-7-3)
The total output noise current has three components, which are I o u t i due to
the source resistor Rs, I o u t 2 due to the resistive loss of the inductor and Iotm due to
the base resistance of Rb- In other words,
72 = / 2 + 72 + 72 12-7-41
1 OUT 1 OUT\ T 1 OUT2 ^ 1 OUT3 ' V
Figure 33 shows the equivalent circuit to calculate the noise current I o u t i
only due to the source (i.e. IL = Vrb = 0). The noiseless notch filter can be modeled
with its Z-parameters. As a result,
lo a n ~ I s
f z 1
f z
21
+
R b )
K Z + Zi„0 ,
7
V 22
+
Rb j
(2-7-5)
where
Z =
1 R <
(Rs IIsCx) 1 + sCxRs
^ino ~ (Zu + Rb)
(Z1 2 + Rb )(Z2 1 + Rh)
"12 '
Z2 2 + RB
The noise current Iout2 due to the resistive loss of the inductor can be
calculated by setting Is = Vrb = 0 in Figure 32. The circuit analysis results in the
form of
/
Z
I OUT 2 ~ I L
1
Z 2 1 + Rb
z + Z2 2 + R b j
(2-7-6)
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I, z n (s)
^ w -
Z 22(s) I 2 I o u t i
—W ------ <—
z i M h }2 2l(s)Il
Rn
Figure 33. Equivalent circuit to calculate the noise current I o u t i -
The noise current loun due to the base resistor Rg can be calculated by
setting Is = h = 0 in Figure 32. The circuit analysis results in the form of
I o u t , = V r b ------------------------^ ^ Z----------------------- (2-7-7)
oun m (Z2 1 + R b)(Z u + R b + Z ) - ( Z 2 1 + R b)(Z u + R b)
The noise figure is defined as the ratio of the total output noise power to the
output noise power only due to the source. Therefore the noise figure of the notch
filter configuration is shown to be
Noise Figure = 1 + ^oull + ^(nn 3 (2-7-8)
I 2 12
OUT\ OUT\
Noise calculations according to (2-7-8) with L = 8nH, Rb = 312 Q, Rind =
8.56 Q, Qind =11.2,R S = 50 Q, Cx = 100 fF and (C 7 = 2 pF, C2 = 758 fF) or (C, =
758 fF, C2 = 2 pF) were performed. Figure 34 shows the results of calculation
through MATLAB software. At the notch frequency of 2.4 GHz, the noise figure
goes to infinity because I o u t i i n (2-7-8) goes to zero due to ( Z 2 i + R b ) term. This
means the noise due to the source cannot be delivered to the output port at the notch
frequency.
68
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.110
15
1E+09 2E+09 3E+09
Frequency (Hz)
4E+09
Figure 34. Noise Calculation according to (2-7-8) with L = 8 nH, Qm d = 11.2, RB = 312
£2, Rjnj = 8.56 Q, Rg = 50 Q, Cx - 100 fF, Thick line: Ct = 2 pF, C2 = 758 fF,
Thin line: C, = 758 fF, C2 = 2 pF.
Friis equation for a system with m-stages is a form as
NFsys=NF]+ -
NF.' -1
- + • • + -
N F - 1
pi
A A
A p \ A p ( m - 1 )
(2-7-9)
where NFm is the noise figure of the m-th stage and Ap m is the power gain of the m-
th stage. It implies that the first few stages in a cascade system are the most critical
because the noise contributed by each stage decreases as the gain of the preceding
stage increases.
In case of the notch filter as a load of single common-source amplifier, the
gain of the preceding stage of the notch filter is determined by the input impedance
of the notch filter. Although the noise figure of (C/, C V ) = (758 fF, 2 pF) is about 2
dB larger than that of (C/, Ci) = (2 pF, 758fF) as shown in Figure 34, the input
impedance of (C/, Ci) = (758 fF, 2 pF) is about 4 dB larger than that of (C/, Ci) - (2
pF, 758fF) as shown in Figure 30. According to the Friis equation, in other words,
69
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the total system noise figure in case using the Cr (= C2 / C/) larger than 1 is better
than that using the Cr smaller than 1. In the next chapter, this result will be applied
to the design of a front-end heterodyne receiver where the symmetrical frequency
response is not important factor.
70
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2.8 Application to Heterodyne Receiver Front-end
This chapter shows the notch filter in a front-end heterodyne receiver. For
the comparison of its performance to an LNA without the notch filter, the circuit
component models from a vendor o f TSMC using 0.25 pm CMOS technology were
used the thickness of gate oxide was 5.4 nm. A DC power supply of 2.5 V was
used in simulations.
To design the receiver, the spiral inductors were evaluated at first for the
notch filter block and the load of LNA respectively. From the review of inductors,
the suitable value of the inductors could be determined.
'load load
O r OUT
B2
50 Q
r,„°-Vr
Figure 35. Schematic of a front-end heterodyne receiver. Biasing circuitry was not shown.
The simulation results of the front-end of heterodyne receiver show an
example of a DECT (Digital European Cordless Telecommunications) application.
71
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The signal frequency was 1.9 GHz and the image rejection frequency was 2.5 GHz
assumed the IF frequency of 300 MHz. Simply to show its performance, a cascode
LNA with single common-source configuration was used as shown in Figure 35.
The notch filter is located between cascoding transistor M 3 and the input transistor
Mi. The sizing of the transistors was accomplished only for low-power operation
and the optimizations for the input impedance matching, the low noise and the non-
linearity were not considered. Accordingly the comparison of the performances
with/without the notch filter could be focused in this work.
2.8.1 Evaluations of Inductors
The model of an inductor from TSMC 0.25 pm CMOS process was shown in
Figure 19 in Chapter 2.5. The outer dimension of the inductors was 60 pm and the
inductances depend on the number of turns. Table 4 shows the values of the
components according to its winding.
Table 4. Components of the inductors in Figure 19 from TSMC 0.25 pm CMOS process.
# of turns
L
(nH)
R-ind
(O)
C s
m
C o x l
m
Cqx2
(fF)
C su b
(fF)
R su b
(O)
2.5 2.2 3.2 16.7 123.6 133.6 37.4 441.9
3.5 3.7 4.7 20.8 134.6 144.3 49.5 423.1
4.5 5.9 6.2 24.9 145.5 155.0 61.5 404.3
5.5 8.7 7.7 29.0 156.4 165.7 73.6 385.5
6.5 12.1 9.3 33.2 167.3 176.4 85.6 366.6
72
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From the data of TSMC process, the skin effect was not considered in the
modeling of a series resistance of the inductor, Rin d, and the resultant quality factor
of Qind could be calculated by 8.1 to 15.6 at 1.9 GHz. The Csub and Rsub showed
dimension dependency as explained in Chapter 2.5.3.2. The difference between Coxj
and C0X2 could result from the unsymmetrical structure between both nodes of an
inductor, due to the connection though a bottom metal.
1) Inductor Itself
1000 1000
■ C
£
8
C
■ §
Q >
I
in '
S
■ § 100
o T
o
c
■ 8
# of tu rn s = 6.5
s .
O
■ §
a
0 )
I
# of tu rn s = 5.5 10
H — # of tu rn s = 4 .5
e
o >
< B
s
o c
# of tu rn s = 3.5
1E+09 3E+09 5E+09 7E+09 9E+09 2E+09
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 36. Impedances of the inductors from TSMC 0.25 pm process, (a) Real part,
(b) Magnitude.
Figure 36 and 37 show the evaluations of the inductors from TSMC 0.25 pm
CMOS process. According to the number of spiral turns of winding, the real and
imaginary parts of the inductor itself were plotted. As the number of turns increases,
the real impedance and the equivalent inductance increase as expected from Table 4.
73
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The self-resonance frequencies associated with the parasitic capacitances were
beyond about 4 GHz.
3E-08
§
§
3
O '
0 )
2E-08
&
*
o
c
■ §
4 )
f
'3
< o
E
1E-08
O E+O O
............ 1 1 1 1 , 1 ! ....... - ......... 1 1 1 1 1 1 1 1 1 .....*
||||||||||||||llllllllltt*tt‘
------- , ---------j --------- 1 ---------j --------- 1 ---------
1E+09 2E + 09 3E+09
Frequency (Hz)
4E+09 1E+09 3E+09 5E+09 7E+09 9E+09
Frequency (Hz)
(a) (b)
Figure 37. Impedances of the inductors from TSMC 0.25 pm process, (a) Imaginary
part/27if, (b) Phase angle.
2) Inductor in the Load of LNA
1000
w T
S
■ c
0 >
0
c
■ §
Q )
1
•§
a
800
600
400
* 5 200
© >
< 0
5
U of turns = 6 .5
# of turns = 5.5
# of turns = 4.5
- - -# of turns = 3.5
1E*09 2E+09 3E+09 4E+09
# of turns = 6.5
1
2
e >
3 1
0 )
o
c
•§
o
t
•# of turns = 5.5
• # of turns = 4.5
•# of turns = 3.5
O
■90
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 38. Impedances of the parallel L-C tanks (a) Magnitude (b) Phase angle.
74
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Table 5. Combination o f inductor and capacitor in LC tank load.
# o f turns 3.5 4.5 5.5 6.5
Chad (PF)
1.77 1.08 0.68 0.44
For the characterization of the load of LNA, the impedance of the parallel
LC tank, i.e. at the impedance at the node® in Figure 35, is displayed in Figure 38.
Each load capacitance was tuned to maximize the magnitude o f the impedance for
1.9 GHz operations as shown in Table 5. As the number of turns of an inductor
increases, the magnitude of the impedance increases. Although the number of turns
of 6.5 has the highest value of the impedance, the 5.5 turns of L/„a c j was chosen in the
LNA simulations. Because the load capacitance may contain the input capacitance of
the subsequent stage and the parasitic capacitance, the load capacitance should be
sufficiently large.
3) Inductor in Notch Filter
The impedance at the node® in Figure 35 determines the gain of the input
stage. To inspect the effect of the inductor LB in the notch filter block, Cbi, Cb2 and
Rb were tuned as shown in the following Table 6 for the image rejection at 2.5 GHz.
As shown in Figure 39-a, the magnitude of impedance increases as the inductance of
Lb increases.
Figure 39-b shows the results of the noise figure calculations according to (2-
7-8). Although the noise figure at the signal frequency 1.9 GHz increases as the
75
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number of turns of a the inductor increases, the increasing amount of the noise
figure is much less than the increasing amount of the input impedance i.e. the gain
of the amplifier. As a result, the number of the turns of 6.5 for the inductor L B was
chosen in the LNA simulations for the higher gain and lower noise.
Table 6. Combination of inductor and capacitor in notch filter
# o f turns { L io a d ) 5.5
C h a d (pF)
0.61
# o f turns (Lb) 3.5 4.5 5.5 6.5
Cbi (pF)
1.48 0.92 0.60 0.42
C B2 (pF)
3.90 2.40 1.62 1.07
R b ( p F)
142.5 275.0 474.0 790.0
v y
S
-c
Q >
0
c
1
I
■ §
a
£
O )
( 0
S
800
600
400
200
4E+09 2E+09
I
0)
k.
a
I
20
15
10
5
0 —
1E+09 3E+09
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 39. (a) Magnitudes of impedances at the node® in Figure 34, (b) Noise figure
calculations according to (2-7-8). # of turns : Thick line = 6.5, Thin line =
5.5, Dot = 4.5, Circle = 3.5
76
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2.8.2 Simulation Results
The LN A/notch filter combination circuit consumed 1.89 mW excluding
biasing circuitry from 2.5 V power supply, which was slightly smaller than the case
of only LNA. As mentioned earlier, the added passive notch filter didn’t consume
any additional power. Furthermore the slightly reduced power could be obtained due
to the resistive loss in the inductor Lb.
20
I
c
< 1 1
o
9)
U )
a
30
40
2E+09
Frequency (Hz)
Figure 40. Comparison of the frequency Responses. Thick line: LNA/Notch filter,
Thin line: Only LNA.
Figure 40 shows the frequency responses. The voltage gains of the
LNA/notch filter combination and only the LNA circuit at the signal frequency of
1.9 GHz were 12.9 dB and 14.8 dB, respectively, and that of the LNA/notch filter
combination at the image frequency of 2.5 GHz was -65.5 dB. Although the voltage
gain decreased by 1.9 dB due to the adoption of the notch filter, the image rejection
of 78 dB could be acquired. The reduction of the voltage gain of the LNA/notch
77
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filter combination compared with that of only LNA was due to the notch filter
transfer gain less than 1 resulted from the resistive load (= l/g m 3) at the output node
of the notch filter in Figure 35.
As shown in Figure 41, the noise figure o f the LNA/notch filter combination
at 1.9 GHz was degraded by 0.9 dB compared to that of only LNA circuit of 6.7 dB.
This increment resulted from the gain reduction as stated above.
Figure 42 shows the results of a two-tone third-order intercept point (IP3)
simulation performed on the signal path. Two in-band signals were applied to the
system at 1900 and 1910 MHz. In HSPICE simulation, the FFT analyses with
Kaiser-Bessel window were carried out after the transient analysis with sufficient
time duration. Kaiser-Bessel window, which gives sharp separation of the two tones,
was used for the reduction of spectral leakage in the FFT simulation [29].
18
16
14
12
10
8
6
4
Frequency (Hz)
Figure 41. Comparison of the noise figures. Thick line: LN A/Notch filter, Thin line:
Only LNA.
78
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0
E
I
4m
3
O
C L
-30 -20
Pin (dBm)
Figure 42. Two-tone IP3 simulation results. • : fundamental term of (LNA/Notch
filter), o : fundamental term of only LNA, ▲ : IM3 term of (LNA/Notch
filter), A : IM3 term of only LNA.
The simulated input-referred IP3 (IIP3) of the LNA/notch filter combination
and only the LNA circuit were -10 dBm and -12 dBm, respectively. The
improvement of 2 dBm of LNA/notch filter combination compared to the only LNA
circuit was due to the voltage gain reduction. The simulated input-referred 1 dB
compression point of the receiver was -22 dBm of both cases. The performances of
the system are summarized in Table 7.
To consider the cascaded nonlinear stages, let’s call transistor Mi, the notch
filter block and transistor M3 with the load as 1st, 2nd and 3rd stage, respectively.
For these three stages, the total IIP3 can be estimated with IIP3’s of each stage as
follows [30],
79
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where IIP3J, is the IIP3 of the n-th stage and A / and A 2 are the linear coefficients of
the voltage gains of the 1st and 2nd stages, respectively. If each stage in a cascade
has a gain greater than 1, the non-linearity of the latter stages becomes increasingly
more critical.
Table 7. Comparison of the simulated signal-path performances.
Only LNA LNA/Notch filter
Process TSMC 0.25 pm CMOS Technology
Supply Voltage DC 2.5 V
Power (excluding bias circuitry) 1.894 mW 1.892 mW
Consuming Current 0.7575 mA 0.7566 mA
(W/L)i 50 pm / 0.25 pm
gm l
7.16 m mho 7.15 m mho
ViHl
0.519V 0.519 V
Vgsi
0.669 V 0.669 V
(W/L)3
50 pm / 0.25 pm
gm 3
6.95 m mho 6.94 m mho
VlH3
0.533 V 0.533 V
VgS 3
0.692 V 0.692 V
Signal Frequency 1.9 GHz for DECT Application
Image Rejection Frequency - 2.5 GHz
Voltage Gain @1.9 GHz 14.8 dB 12.9 dB
Image Rejection @2.5 GHz - 78 dB
Noise Figure @1.9 GHz 6.7 dB 7.6 dB
ldB Compression Point -25.7 dBm -25.7 dBm
IIP3 -12 dBm -10 dBm
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
For the passive system, IIP3 is at infinity, i.e. the second term in the right
hand side of (2-8-1) could be ignored. From the results as shown in Figure 40, at the
signal frequency of 1.9 GHz,
(a 2A 2) < (a 2A 2) (2-8-2)
V 1 2 / I M I Notch ' 1 1 > Only LNA v 7
Therefore the resultant IIP3 of the LNA/notch filter combination could be improved
compared with that of the only LNA circuit.
2.9 Conclusions
Passive filters have several advantages to overcome the limitations of active
RC filters, which imply higher noise, non-linearity, power consumption and so on.
A passive RLC filter with a third-order transfer voltage-gain function has
been introduced through the approach to realize notch characteristic by using the
open-circuit impedance parameters. The analysis contains the term of the resistive
loss of inductor, thereby the attenuation at the notch frequency can be accomplished
only by use of the branch resistor, and the tuning capability of the filter comes from
the use of varactor. The parasitic capacitance effects of an integrated inductor, which
pose a serious reduction in the quality factor of the inductor, have been annihilated
with the proper output load by the method of the pole-zero cancellation. The passive
RLC notch filter using spiral on-chip inductors has been demonstrated as an
example, and its simulation results have been shown. The larger Q ^ b of the notch
filter than the quality factor of the realized inductor has been acquired.
81
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The simulations of a front-end heterodyne receiver were carried out to
compare the performances with/without the notch filter. By adoption of the notch
filter, the sufficient attenuation at an image frequency was obtained and the power
consumption was not degraded. The voltage gain and the noise figure at a signal
frequency decreased by few dB and the non-linearity feature was improved.
82
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2.10 References
[1] L. P. Huelsman, Active and passive analog filter design - An introduction.
McGraw-Hill Inc., 1993.
[2] W. K. Chen, Passive and active filters - Theory and implementations. John
Wiley & Sons, Inc., Chapter 5, 1986.
[3] G. Daryamani, Principle of active network synthesis and design. New York: John
Wiley Inc., Chapter 3,1976.
[4] J. Macedo, and M. A. Copeland, “A 1.9 GHz silicon receiver with monolithic
image reject filtering,” IEEE Journal of Solid-Stage Circuits, Vol. 33, No. 3, pp.
378-386, March 1998.
[5] H. Samavati, T. H. Rategh, and T. H. Lee, “ A 5 GHz CMOS wireless LAN
receiver front end,” IEEE Journal of Solid State Circuits, vol. 35, no. 5, pp. 765-
772, 2000.
[6] M. H. Koroglu and P. E. Allen, “A 1.9 GHz image-reject front-end with
automatic tuning in a 0.15 um CMOS technology,” ISSCC Digest o f Technical
Papers, pp. 1-10, Feb. 2003.
[7] C. Guo, N. L. Chan and H. C. Luong, “A Monolithic 2 V 950 MHz CMOS band
pass amplifier with a notch filter for wireless receivers,” IEEE Radio Frequency
Integrated Circuits Symposium, pp. 79-82, 2001.
[8] J. Rogers and C. Plett, “A 5 GHz radio front-end with automatically Q tuned
notch filter,” IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 69-
72, Sep. 2002.
[9] Y. Chang, J. Choma, Jr., and J. Wills, “An inductorless active notch filter for RF
image rejection,” Circuits and Systems, 42nd Midwest Symposium on, vol. 1, pp
166-169, Aug. 1999.
83
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[10] Y. Chang, J. Choma, Jr., and J. Wills, “A CMOS continuous-time active biquad
filter for gigahertz-band applications,” Proc. IEEE Int., Symp. on Circuits and
Systems, vol. 2, pp. 656-659, Jun. 1999.
[11] L. E. Larson, “Integrated circuit technology options for RF IC’s - Present and
future directions,” in Proc. IEEE Custom Integrated Circuit Conf., Session 9.1,
pp. 169-176, 1997.
[12] T. H. Lee and S. S. Wong, “CMOS RF integrated circuits at 5 GHz and
beyond,” Proc. IEEE, vol.88, pp 1560-1571, Oct. 2000.
[13] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground
shields for Si-based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, pp 743-752,
May 1998.
[14] A. Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and 1 to 2
transformers in CMOS technology,” Proc. 2000 Custom Integrated Circuits
Conf., May 2000.
[15] Y. Cao, R. A. Droves, X. Huang, N. D. Zamdmer, J, Plouchart, R. A. Wachnik,
T. King and C. Hu, “frequency independent equivalent circuit model for on-
chip spiral inductors,” IEEE J. Solid-State Circuits, vol. 38, pp 419-425, March
2003.
[16] T. H. Lee, The design o f CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 18, 1998.
[17] B. Razavi, RF Microelectronics. Prentice Hall, Inc., Chapter 5,1998.
[18] D. A. Johns and K. Martin, Analog integrated circuit design. John Wiley &
Sons, Inc., Chapter 1, 1997.
[19] H. Samavati, A. Hajimiri, A. R. Shahani, G. N. Nasserbakht, and T. H. Lee,
“Fractal capacitors,” IEEE J. Solid-State Circuits, vol. 33, pp 2035-2041, Dec.
1998.
84
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[20] J. Choma, “Passive filter characteristics and inter stage matching networks for
analog RF integrated circuits,” Univ. Southern California, Tech. Report. #1402-
001, Aug. 2002.
[21] A. Chan, C. Guo and H. Luong, “A IV 2.4 GHz CMOS LNA with source
degeneration as image rejection notch filter,” IEEE ISCAS, vol. 4, pp. 890-893,
May 2001.
[22] J. Choma, Electrical networks - Theory and analysis. John Wiley & Sons, Inc.,
Chapter 4, 1985.
[23] T. H. Lee, The design of CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 7, 1998.
[24] T. H. Lee, The design of CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 2, 1998.
[25] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,”
IEEE Trans. On Parts, Hybrid and Packaging, vol. PHP-10, no. 2, pp 1001-
1009, June, 1974.
[26] J. Craninckx and M. Steyaert, Wireless CMOS frequency synthesizer design.
Kluwer Academic Publishers, Chapter 4, 1998.
[27] J. Millman and A. Grabel, Microelectronics, 2n d Ed., McGraw-Hill Inc.,
Appendix- C, 1987.
[28] H. T. Friis, “Noise figure of radio receivers,” Proc. IRE, vol. 32, pp. 419-422,
July 1944.
[29] Star-Hspice Manual, Release 2003, Avant! Corporation, Chapter 28.
[30] B. Razavi, RF Microelectronics. Prentice Hall, Inc., Chapter 2, 1998.
85
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Chapter 3. A Broadband Amplifier Design
3.1 Introduction
The need for multi-standard tranceivers increases with the increasing number
of wireless standards, because each standard should be covered usually one.
Therefore, several standards such as WCDMA, WLAN (802.11a, b, d, e, f, g, h, i),
HIPERLAN and so on, have to be managed in a chip for future wireless
communication. It means that an RF front-end has to access a huge range of
different carrier frequencies for all these standards.
Such a front-end with either broadband LNAs, narrowband LNAs with
multiple passbands, or tunable LNAs were proposed in the realization of
broadband amplifiers. Narrowband LNAs with multiple passbands are only suitable
where the passbands are well separated and not more than two. Tunable LNAs are
attractive but hard to design with a large tuning range and low noise. The
development of scaling technology of CMOS devices and bandwidth extension
methodology make broadband LNAs feasible in giga-Hz operations [1],
Shunt peaking had used in television sets as bandwidth extension technique
since the 1930s at least up to the 1970s [2]. It is inductive peaking, which induces a
resonance with the parasitic capacitances to get broadband characteristics, and
introduces zeros and complex pole pairs into a transfer function. The method of the
86
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shunt peaking were widely proposed in applications such as current mode logic
structures [3], frequency dividers [4], transimpedance amplifiers [5], preamplifiers
[6], and so on.
The improved way to extend the bandwidth is a shunt-series peaking and T-
coil configuration had used for the realization [2]. The parasitic capacitances in on-
chip T-coil configuration cause the non-linearity of the system and bounces in
transient response. To solve the problems, the T-coil circuit was modified and the
analysis by tracing the moved poles and zeros was carried out. The poles and zeros
induced by the parasitic capacitance became closer one another in the proposed T-
coil circuit.
Chapter 3.2 reviews the design background and the problems of the previous
T-coil configuration and Chapter 3.3 shows the analyses and the simulation results
of the proposed circuit.
87
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3.2 Design Background
3.2.1 Shunt Peaking
A shunt peaking as shown Figure 43 originated to video amplifiers from the
1930s as a bandwidth extension method. An inserted inductor Lo, which needs not
high quality, into the branch of a resistor Ro creates a zero and makes a peaking in
frequency response. The inductor Lo impedes the current trough the resistor R0. So
the charging time of the capacitor Q goes faster and its bandwidth improves.
v(OC)
R ,
CD
'input
c,
Figure 43. Schematic diagram of a shunt peaking.
The input impedance Zin p u t at the node OC in Figure 43 is a form as
s(L0 / R0) + 1
Rr
S T + 1
^ i n p u t 7 t /~< t> r ' . 1 2 2 2 , . i
s L0C,+sR0Cj +1 s z m +srm + 1
(3-2-1)
where
D
t - L0 I Ra, m =
L (>
The bandwidth of the circuit is determined by the values of m and the
frequency response has maximum bandwidth, maximally flat magnitude response,
88
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and maximally fat delay response when m is 1.41, 2.41 and 3.10, respectively [2].
Although the case o f m of 1.41 results in the maximum bandwidth extension, the
peaking of 20 % in frequency response occurs. As shown in Figure 44, in the
maximally flat magnitude response, the 3-dB bandwidth increases by 72 %
compared with the case without the inductor.
> 0.5
1E+10
Frequency (Hz)
Figure 44. Frequency responses at node OC. Thin line: m - q o , Dot: m = 3.10(MFD),
Thick line: m = 2.41(MFM), A : m = 1.41.
3.2.2 Shunt-Series Peaking
More improved way to increase the bandwidth is a shunt-series peaking as
shown Figure 45. The configuration of an inductor L2 and a capacitor C). without an
inductor L3 is called as shunt peaking. The inductor L2 acts as an impedance
component that increase with frequency (i.e., it introduces a zero), which helps
offset the decreasing impedance of Cl, leaving a net impedance that remains roughly
constant over a broader frequency range than that of the RoCl network. When the
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step input is applied, the inductor L2 delays current flow through Rq, making more
current available for charging the capacitor C l , and reducing the rise time. A faster
transient time implies a larger bandwidth to the extent. Likewise an inductor Lj
reduces the charging time of the drain capacitance of the transistor. Rise time at the
drain decreases, which again means an improved bandwidth, and such a mechanism
is another shunt peaking. After the drain voltage has risen significantly, the voltage
across Cl begins to rise as current finally starts to flow through Lj, which is called as
series peaking. Hence, such a network charges the capacitance serially in time.
The price paid for the improved bandwidth is an increased delay [2],
v(LC)
o-
Figure 45. Schematic diagram of an amplifier with a shunt-series peaking.
The three inductors in Figure 45 can be replaced with a transformer, which is
so-called T-coil (according to drawing way of the schematic), shown in Figure 46.
The mutual inductance between Li and L2 produces the inductance like L3 in Figure
45 and Kq represents a coupling coefficient of the transformer. The resonance
created by the capacitor C/ and the inductors helps to push out bandwidth even
further. Stacked inductors [7] or monolithic configurations [8] [9] were proposed to
90
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implement an on-chip transformer. Although the die area can be saved in the stacked
inductor structure, the coupling coefficient Kc depends on the dielectric thickness
between metal layers. Meanwhile the monolithic transformer consumes larger area
but the Kc can be controlled with the spacing between metal lines.
v(LC) . v(OC)
L,=L/2
'input
Figure 46. Schematic diagram of an amplifier with T-coil.
The input impedance Zin p u t at the node IC in Figure 46 is a form as
Tn +sCf + To
Z input (,S ) 1
o ,, +sCf )2 ~(yu - s C f ) 2 + (yu +sCf )yi
fJ J' O
where
^ 1 , 2 LCI n
Tn(s) = — 0 —r^ + l)
A 2
1 2 K cLC l
Ti2^) = T ’^ o *)
y 0 < ,s) = s c 0 +
R,
(3-2-2)
A = sL( 1 + K c )
LC,
2
( l - K c) + \
91
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In the case of yo = Go = 1/Ro, that is Go - 0 in Figure 46, Zin p u t(s) = Rq if the
components satisfies the following conditions,
Cf =
(1+ K C)
L ( \ - K c) _ C l (1 - K c)
4 Rn 2 4 (1+ KC)
(3-2-3)
Meanwhile, the response of v(OC) is known as maximally flat magnitude
response if Kc = 1/3 and has maximally flat group delay if Kc = 1/2, respectively [2].
As shown in Figure 47, in case of the maximally flat magnitude response (Kc = 1/3),
the 3-dB bandwidth increases by 183 % compared with the unpeaked case of Figure
43 without the inductor.
o
o
■ 8
O
c
< 0
Q >
O )
45
§ 0.5
s
N
< 0
s
k.
o
2
1E+10
Frequency (Hz)
Figure 47. Frequency responses at node OC. Thin line: m - o o , Dot: m = 2.4l(MFM),
Thick line: K( = 1/3.
The parasitic capacitance Co, which results from the parasitic capacitance of
a spiral inductor or the input capacitance of a subsequent stage, makes fluctuation of
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v(IC) response as shown in Figure 48-a and the resultant bandwidth of v(LC)
becomes about 96 GHz. The frequency response of v(OC) was not changed
significantly with respect to the existence of the Co and the 3-dB bandwidth of about
4.7 GHz was shown in Figure 48-b. As reference, the 3-dB bandwidth from Rq-Cl
time constant was 1.7 GHz. The values of the components for the simulations were
Kc = 1/3, L = 11.84 nH, C /= 72.13 fF, RQ =165.4 Q, CL = 577 fF and CQ = 20 fF.
1.5
"8 0.5
1E+10 1E+11
Frequency (Hz)
(a )
1.5 1.5
S;
o
o
■ §
o
c
< B
0 >
O )
42
§
■ O 0.5
0 )
N
1 5
E
V .
O
2
■o 0 .5
1E+10 1E+11 1E+11 1E+10
Frequency (Hz) Frequency (Hz)
(b) (c)
Figure 48. Frequency responses at each node in Figure 46 of (a) normalized v(IC),
(b) normalized v(OC), (c) normalized v(LC). Thick Line: With C0. Thin
Line: Without Co-
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The fluctuation at the node IC could change the drain-bulk junction
capacitance of transistor, which makes the system nonlinear. And the poles and zeros
induced by the Co, which will be shown in the next chapter, cause bounces in
transient response. Figure 49 shows the transient response when a step input with a
rise time of 2 ps was applied at 100 ps. In the response of v(IC), a maximum peaking
of 35 % occurred and the 90 % settling time of v(IC) was 263 ps. Also the 90 %
settling time of v(OC) was degraded by 114 ps compared to that without Co, which
has the 90 % settling time of 91 ps.
1.1
o
o
■ §
o
c
9 i
c
o
8 -
Q >
K
■§ 0.9
N
0.8
400 0 200 600
1.4
O
■ §
g 1.2
3 i
c
o
f
0 )
o c
< D
t N
( Q
e
0.8
0.6
600 200 400 0
Time (ps) Time (ps)
(a) (b)
Figure 49. Transient responses with step input at 100 ps. Thick Line: Without C0. Thin
Line: With C(). (a) normalized v(IC), (b) normalized v(OC).
A methodology to improve the response of v(IC) will be shown in the next
chapter by tracing of movements of poles and zeros.
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3.4 Design and Analysis
Figure 50 shows the proposed broadband amplifier, where the transistor in
Figure 46 was replaced by a current source. Compared with Figure 46, a capacitor
Cx is added at input port and an inductor Lq is serially inserted into the branch of Rq.
Conceptually, the capacitor Cx can reduce the peaking in the high frequencies and a
shunt peaking circuit consists of the inductor Lq associated with the capacitor Co-
v(OC) v(LC) v(IC)
L/2
Figure 50. Schematic diagram of the proposed broadband amplifier.
The resultant frequency responses are shown in Figure 51. In the simulation,
Cx of 32 fF and Lo of 0.5 nH were used with the components in Figure 46. As
shown in Figure 51-a, about 20 % peaking of v(/C) due to the Co was diminished to
fluctuation less than 3 %. The response of v(OC) was not significantly changed and
the 3-dB bandwidth of v(LC) was reduced from ~ 96 GHz to ~53 GHz, which is still
in acceptable frequency range. In other words, the price paid for the reduction of the
peaking of v(7C) is the bandwidth reduction of v(LC).
95
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
To illustrate the improvement of v(/C) response, pole-zero analysis [10]
through HSPICE simulations was carried out. The poles and zeroes are plotted in s-
domain in Figure 52 for each case and the results of computed pole and zero
frequencies [Appendix C] are shown in Table 8.
1.5
o
■ §
o
c
<0
a >
o >
a
§
■ o
S 0.5
1E+11
Frequency (Hz)
(a)
1.5
O
O
o >
Q >
O )
a
1E+1 1E+10
• O
o
c
' W
a >
O )
a
§
N
" 5
E
o
2
1.5
1
0.5
1E+10 1 E + 1 1
Frequency (Hz) Frequency (Hz)
(b) (c)
Figure 51. Frequency responses of the proposed circuit with Cx = 32 fF, L() = 0.5 nH.
Thick Line: With C0, Cx and L0. Thin Line: Only with Ca. (a) normalized
v(/C), (b) normalized v(OC), (c) normalized v(LC).
96
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
LoglO(lmag) (Hz)
£
O i
C O
X Pole
O Zero
:*>o
0 .11.0
t-
0 1
o
~l
-10.5 - 10.0 -9.5
*>°
15
10
5
0
■ 9 1 0 .5
-10
-15
- LoglO(Real) (Hz)
(a )
x « o
- 11.0
—X-
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X « o
15
10
5
0
-9)0-5
-10
- 1 -15
£
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X
a*>
- 10.0 -9.5
■ Log10(Real) (Hz)
(b)
£
O i
Q
I
§ - 11.0 -10.5
X
- 10.0
- LoglO(Real) (Hz)
(C)
T 1 5
aso 10
5
— 0
-9.5 -9.0.5
0 * 0 -10
-15
15
10
5
0
-9 )9 .5
-10
-15
- LoglO(Real) (Hz)
(d)
Figure 52. Poles and zeroes in s-domain of v(/C) response, (a) Co effect in Figure 46,
(b) Only Cx effect in Figure 50, (c) Only L0 effect in Figure 50, (d) Cx and
L0 effects in Figure 50.
A constant v(/C) response in frequency domain means that its poles and
zeroes should be perfectly cancelled, which result in poles and zeros at infinity in s-
domain. Due to the parasitic capacitance of Co, the poles and zeros occurred in left
97
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
half plane of s-domain, which resulted in the fluctuation and about 20 % peaking in
the frequency response.
By the added capacitor Cx, the poles in the range of few GHz of the circuit in
Figure 46 moves toward the zeros and the pole at 96.2 GHz also moves to 29 GHz.
Although one zero and two poles in tens GHz range are generated by the inductor Lo,
the zeros in the range of few GHz o f the circuit in Figure 46 move closer to the poles.
The combination of these two effects results in the closer poles-zeros and the
fluctuation less than 3 % of v(IC) in frequency response. In Table 8, a pole-zero
cancellation means the ratio of pole frequency f p to zero frequency f z equals to 1.
The case of (d) has the closest (fp!fz) to 1 compared with other cases.
Table 8. Comparison of pole and zero frequencies, (a) C0 effect in Figure 46, (b) Only Cx
effect in Figure 50, (c) Only L0 effect in Figure 50, (d) Cx and L0 effects in Figure
50.
fp(GHz) 4.71 4.71 4.72 4.72 96.2 -
(a)
f (GHz) 3.23 3.23 6.10 6.10 - -
f p / f z
1.46 1.46 0.78 0.78 - -
fP (GHz) 4.35 4.35 5.34 5.34 29.0 -
(b)
f z (GHz) 3.23 3.23 6.10 6.10
f p / f z
1.35 1.35 0.88 0.88 - -
fp (GHz) 4.72 4.72 4.72 4.72 71.2 71.2
(c)
f z (GHz) 4.24 4.24 5.39 5.39 39.0
f p / f z
1.11 1.11 0.87 0.87 1.82 -
f p (GHz) 4.67 4.67 4.75 4.75 40.9 40.9
(d)
f(G H z) 4.24 4.24 5.39 5.39 39.0
fp /f
1.10 1.10 0.88 0.88 1.05 -
98
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Likewise the improvement of the frequency response, the transient response
significantly became better. The results nearly approached to the case of without Co
lt means that the poles and zeros became closer as previously stated. The responses
are shown in Figure 53. A peaking of about 6 % occurred in the response of v(/C)
and the 90 % settling time of v(OC) was degraded by about 3 ps compared to that
without C0.
1.1
o
o
T 3
O
C
< 0
8!
c
o
0 )
o :
$ 0.9
N
< 0
E
£
0.8 4 -
0 200 400 600
1.4
O
< B
■ o
o i o
c 1.2
IB
9 i
c
o
0 )
a:
■ Q
«
N
=- 0.8
0.6
600 200 400 0
Time (ps) Time (ps)
(a) (b)
Figure 53. Transient responses with step input at 100 ps. Thick Line: With CQ , Cx and
L (> . Thin Line: Only with Co- (a) normalized v(IC), (b) normalized v(OC).
The passive components could deviate from their nominal values due to the
initial tolerances associated with their manufacture. Therefore, the performance of
the built circuit would differ from the nominal design. To examine this difference,
the frequency responses were observed in the cases of ±15 % deviations of each
component, respectively, and the results are summarized in Table 9.
The nominal bandwidth of v(OC) response, that is in the case of 0 %
component deviation, was 4.68 GHz and had the maximum variation from -12.9 %
99
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to +16 % when Cl component varied. And the peaking didn’t occurred in the v(OC)
response. The case of Cl deviation is shown in Figure 54-a.
Table 9. Response variations due to component deviations of ±15 %.
v{OC) v (Z Q
BW3 d B(0%)=4.68 GHz BW3 d B (0%)=52.8 GHz Peaking(0%)=2.2 % GHz
BW3 d B
BW 3 d B Peaking
-1 5 % + 15% -1 5 % + 1 5 % -15 % + 1 5 %
Kc
-0.9 % +0.6 % -0.8 % +0.7 % 1.3% 3.1 %
Lj +5.7 % -5.6% +0.8 % -0.6 % 3.2 % 1.4%
l 2
-7.3 % +4.7 % +0.9 % -0.8 % 3.1 % 1.5%
Cf
+0.8 % -0.7 % -3.4 % +1.3 % 0.6 % 3.2 %
CL +16.0% -12.9% ~0 ~0 2.2 % 2.1 %
Cx
+0.1 % -0.1 % +10.0% -8.5 % 3.8 % 0.9 %
Co
+0.1 % ~0 +8.1 % -7.2 % 3.2 % 1.5%
Lo
+0.1 % -0.1 % -2.7 +1.5% - 5.5 %
o
® 1.0
* o
o
c
' W
< 0
0 )
O )
«
§ 0.5
$
N
< 0
E
I
0.0
1E+10 1E+11
4*
( B
Q >
O )
a
§ 0.5
■ o
a >
N
< S
0.0
1E+11 1E+10
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 54. Response variations due to (a) Q deviation, (b) Cx deviation. Thick Line:
0 %, Thin Line: -15 %, Dotted Line: +15 %.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The nominal v(LC) response had the 3-dB bandwidth of 52.8 GHz and
maximally varied from -8.5 % to +3.8 % in the Cx deviation . This result is shown
in Figure 54-b. The maximum peaking of 5.5 % occurred in the case of Lo deviation.
Chapter 3.4 Conclusions
A way to extend the bandwidth in broadband design is shunt peaking and T-
coil configuration had been used for the realization of shunt-series peaking. When it
is driven by the on-chip amplifier, the parasitic capacitances in the T-coil
configuration cause the non-linearity of the system and bounces in transient
response. To reduce these shortfall, the T-coil circuit was modified and the results
were shown. The tradeoff was the reduction of the peaking of v(/C) in charge for the
bandwidth reduction of v(LC). And the analysis by tracing the changed poles and
zeros was carried out. The poles and zeros induced by the parasitic capacitance
became closer one another in the proposed T-coil circuit. For the design guideline,
the variations of the responses due to the components deviations were observed.
101
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3.5 References
[1] S. Andersson, C. Svenson and O. Drugge, “Wideband LNA for a multistandard
wireless receiver in 0.18 /spl mu/m CMOS,” Proceedings of Solid-State Circuits
Conference, the 29th European, pp. 655-658, Sep. 2003.
[2] T. H. Lee, The design of CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 8,1998.
[3] M. M. Green, “CMOS design techniques for 10 Gb/s optical transceivers,”
International Symposium on VLSI Technology, Systems, and Applications, pp. 209-
212, 2003.
[4] H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 um CMOS frequency divider with
shunt-peaking locking-range enhancement,” IEEE International Solid-State Circuits
Conference, pp. 412-413, 471, Feb. 2001.
[5] C. Lee, C. Wu and S. Liu, “A 1.2V, 18mW, lOGb/s SiGe transimpedance amplifier,”
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 300-303,
Aug. 2004.
[6] S. H. Park, D. Y. Jung and C.S. Park, “Bandwidth extension in preamplifier design
maintaining low power consumption,” International Conference on Microwave and
Millimeter Wave Technology Proceedings, pp. 936-939, Aug. 2002.
102
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[7] A. Zolfaghari, A. Chan and B. Razavi, “Stacked Inductors and 1 to 2 Transformers in
CMOS Technology,” Proc. 2000 Custom Integrated Circuits Conf., May 2000.
[8] J. R. Long and M. A. Copeland, “The modeling, characterization, and design of
monolithic inductors for silicon RF ICs,” IEEE J. Solid-State Circuits, vol. 32, pp.
357-369, Mar 1997.
[9] J. J. Zhou and D. J. Allstot, “Monolithic transformers and their application in a
differential CMOS RF low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 33, no.
12, pp. 2020-2027, Dec 1998.
[10] Star-Hspice Manual, Release 2003, Avant! Corporation.
103
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Chapter 4. Conclusions
The designs of notch filters and modified series-shunt peaking circuit using
passive RLC networks were shown.
Although the low quality inductors such as planar spiral on-chip inductor
were used, the full attenuation at the notch frequency was obtained only by using
resistor. For the design, an approach to a third-order passive RLC notch filter
implementation by using Z parameters representation was proposed. A pole-zero
cancellation method was introduced to have the symmetric notch frequency response
and the performances of LNA/notch filter combination circuit were compared those
of only LNA circuit through HSPICE simulations.
A broadband amplifier with the previous T-coil configuration for bandwidth
extension has peaking problem due to its parasitics in frequency response, which
affects the nonlinear operation of system and results in bounces in step response. To
overcome the shortfall, i.e. to get closer poles and zeros in the transfer function, a
modified T-coil configuration was proposed. And the effects o f the components
deviation were examined for the design guideline.
104
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Bibliography
S. Andersson, C. Svenson and O. Drugge, “Wideband LNA for a multistandard
wireless receiver in 0.18 /spl mu/m CMOS,” Proceedings of Solid-State Circuits
Conference, the 29th European, pp. 655-658, Sep. 2003.
Y. Cao, R. A. Droves, X. Huang, N. D. Zamdmer, J. Plouchart, R. A. Wachnik, T.
King and C. Hu, “Frequency independent equivalent circuit model for on-chip spiral
inductors,” IEEE J. Solid-State Circuits, vol. 38, pp 419-425, March 2003.
A. Chan, C. Guo and H. Luong, “A IV 2.4 GHz CMOS LNA with source
degeneration as image rejection notch filter,” IEEE ISC AS, vol. 4, pp. 890-893, May
2001.
Y. Chang, J. Choma, Jr., and J. Wills, “A CMOS continuous-time active biquad filter
for gigahertz-band applications,” Proc. IEEE Int., Symp. on Circuits and Systems,
vol. 2, pp. 656-659, Jun. 1999.
Y. Chang, J. Choma, Jr., and J. Wills, “An inductorless active notch filter for RF
image rejection,” Circuits and Systems, 42nd Midwest Symposium on, vol. 1, pp
166-169, Aug. 1999.
W. K. Chen, Passive and active filters - Theory and implementations. John Wiley &
Sons, Inc., Chapter 5,1986.
J. Choma, Electrical networks - Theory and analysis. John Wiley & Sons, Inc.,
Chapter 4, 1985.
J. Choma, “Passive filter characteristics and inter stage matching networks for
analog RF integrated circuits,” Univ. Southern California, Tech. Report. #1402-001,
Aug. 2002.
J. Craninckx and M. Steyaert, Wireless CMOS frequency synthesizer design.
Kluwer Academic Publishers, Chapter 4, 1998.
105
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G. Daryamani, Principle of active network synthesis and design. New York: John
Wiley Inc., Chapter 3,1976.
H. T. Friis, “Noise figure of radio receivers,” Proc. IRE, vol. 32, pp. 419-422, July
1944.
M. M. Green, “CMOS design techniques for 10 Gb/s optical transceivers,”
International Symposium on VLSI Technology, Systems, and Applications, pp. 209-
212,2003.
H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE
Trans. On Parts, Hybrid and Packaging, vol. PHP-10, no. 2, pp 1001-1009, June,
1974.
C. Guo, N. L. Chan and H. C. Luong, “A Monolithic 2 V 950 MHz CMOS band
pass amplifier with a notch filter for wireless receivers,” IEEE Radio Frequency
Integrated Circuits Symposium, pp. 79-82, 2001.
L. P. Huelsman, Active and passive analog filter design - An introduction. McGraw-
Hill Inc., 1993.
D. A. Johns and K. Martin, Analog integrated circuit design. John Wiley & Sons,
Inc., Chapter 1,1997.
M. H. Koroglu and P. E. Allen, “A 1.9 GHz image-reject front-end with automatic
tuning in a 0.15 um CMOS technology,” ISSCC Digest of Technical Papers, pp. 1-
10, Feb. 2003.
L. E. Larson, “Integrated circuit technology options for RF IC’s - Present and future
directions,” in Proc. IEEE Custom Integrated Circuit Conf., Session 9.1, pp. 169-176,
1997.
C. Lee, C. Wu and S. Liu, “A 1.2V, 18mW, lOGb/s SiGe transimpedance
amplifier,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits,
pp. 300-303, Aug. 2004.
106
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
T. H. Lee and S. S. Wong, “CMOS rf integrated circuits at 5 GHz and beyond,” Proc.
IEEE, vol.88, pp 1560-1571, Oct. 2000.
T. H. Lee, The design of CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 2, 1998.
T. H. Lee, The design of CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 7,1998.
T. H. Lee, The design of CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 8,1998.
T. H. Lee, The design of CMOS radio frequency integrated circuits. Cambridge
University Press, Chapter 18, 1998.
J. R. Long and M. A. Copeland, “The modeling, characterization, and design of
monolithic inductors for silicon RF ICs,” IEEE J. Solid-State Circuits, vol. 32, pp.
357-369, Mar 1997.
J. Macedo, and M. A. Copeland, “A 1.9 GHz silicon receiver with monolithic image
reject filtering,” IEEE Journal of Solid-Stage Circuits, Vol. 33, No. 3, pp. 378-386,
March 1998.
J. Millman and A. Grabel, Microelectronics, 2n d Ed., McGraw-Hill Inc., Appendix-
C, 1987.
S. H. Park, D. Y. Jung and C.S. Park, “Bandwidth extension in preamplifier design
maintaining low power consumption,” International Conference on Microwave and
Millimeter Wave Technology Proceedings, pp. 936-939, Aug. 2002.
B. Razavi, RF Microelectronics. Prentice Hall, Inc., Chapter 2, 1998.
B. Razavi, RF Microelectronics. Prentice Hall, Inc., Chapter 5, 1998.
107
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J. Rogers and C. Plett, “A 5 GHz radio front-end with automatically q tuned notch
filter,” IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 69-72, Sep.
2002.
H. Samavati, A. Hajimiri, A. R. Shahani, G. N. Nasserbakht, and T. H. Lee, “Fractal
capacitors,” IEEE J. Solid-State Circuits, vol. 33, pp 2035-2041, Dec. 1998.
H. Samavati, T. H. Rategh and T. H. Lee, “A 5 GHz CMOS wireless LAN receiver
front end,” IEEE Journal of Solid State Circuits, vol. 35, no. 5, pp. 765-772,2000.
H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 um CMOS frequency divider with
shunt-peaking locking-range enhancement,” IEEE International Solid-State Circuits
Conference, pp. 412-413, 471, Feb. 2001.
C. R Yue and S. S. Wong, “On-Chip spiral inductors with patterned ground shields
for Si-Based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, pp 743-752, May 1998.
J.J. Zhou and D. J. Allstot, “Monolithic transformers and their application in a
differential CMOS RF low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 33, no.
12, pp. 2020-2027, Dec 1998.
A. Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and 1 to 2 transformers in
CMOS technology,” Proc. 2000 Custom Integrated Circuits Conf., May 2000.
Star-Hspice Manual, Release 2003, Avant! Corporation, Chapter 28.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendices
Appendix A. Normalization of the Transfer Function (Chapter 2.5.2)
H(s)
1 + s2RBRm dCx C2 +sRB(Cx +C2) + s3LRH ClC2
1 + s 2(LC2 +RBRmdCxC2) + s[RindC2 +RB(Cl + C 2)] + s3LRBCx C2
(A-l)
(A-2)
l c x c 2
Rb =
R in d (C \ + Q )
(A-3)
Q ind ~ 0 i N L I R-ind
(A-4)
From (A-2) and (A-3),
RBR^C,C, = — - (A-5)
B in d 1 2 2
co„
Rb(Cx+C2) =
Q ind
(0 „
(A-6)
I P C C — Q ‘ m l
0),
(A-7)
LC2 + RBRindCx C2 — ■
co,
2 + ^
c
(A-8)
Rin d C2 +RB(Ci + C2) =
Q ind
CO,
1+
a md
(A-9)
Put (A-5) ~ (A-9) to (A-l), and s = jco. And then,
H{jco) =
1 C O . CO _
1------- 7 + 7 ------
ry
< y
ft)
ry»
V J
1 -
. c,
A 2
CO . C O _
+ 7 S,w
/
1 + -
(1 + C2/C,) ry2
v
Q ind
CO
(A-10)
109
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Set y = c o / c o m , and the normalized transfer gain function, H(jy), is
(A-iD
1 - a y + jyQind( b - y )
where
a = 2 + C2 /C]
b = 1 +
(1+ C2/C,)
Q j
Appendix B. Normalization of the Transfer Function (Chapter 2.6.2)
H(s) =
1 + s 2RBRm dCx C2 + s R b (C, +C2) + s i LRbCx C2
(l + I,.) + 52 [£/] + s[V] + s \ l + Lr )LRhCx C2
(B-l)
where
Lr - L/Ll — Rm d / Rin d l
IC c
U = LC2 + Lr •— + (1 + Lr)RBRmdCxC2
c x+ c 2
V = Rm dC2 + Lr ■
R m dC \ C 2
c, +c,
+ ( 1 + 4 ) ^ ^ , +C2)
Using (B-2), (B-3) and (B-4),
g > n =
Q + C 2
' IC ,C 2
(B-2)
=
+c2 )
(B-3)
Q in d ~ Rind ~ ^ N A. ^ R ,indL
(B-4)
therefore,
ZC,
to
(B-5) RBRmdQ C 2 =— (B-6)
C 0 „
110
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n s~i Q ind ^
ind 2 ~
<°N Q u ind
r c A
1 + ^ -
c
\ i v
(B-7)
Rb(C]+C2) =
Q, ind
CO,
(B-8)
Q ind
l r , c 1c 2 = 3
co„
(B-9)
R,
C,C2 0,
ind
1
C j + C2 0
ind
Put (B-5) ~ (B-10) to (B-l), and s =jco. And then,
1 c o .co
1 2 + J Qind
C0N C0N
1 ~ ^
V J
C n 1 C O 2 C O _
U u Lr, c y _ c , i ^ Lr + J
1 + Lr -
2 (1 + £,.) + “ - 2 + 7 Qind
L c >-
coN 0)N
Qind C O N
(B-l 1)
Set_y = c o / c o n , and the normalized transfer gain function, H(jy), is
H{jy) =
( 1 ]
i - y 2 +jyQm dQ-y2) _
( 1 ^
1 - a y 2 +jyQlnd( b - y 2)
H N(jy)
(B-l 2)
where
Lr — L / Lj — R jn d / Rindl
Q ind ~ 0 i N L ! R ,nd ~ N ^ RjndL
a = 1 + m
b = \ + m/ Qt 2
m = 1 +
ind
r C2/C, '
V
1+ L L
'L
\ \ \
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix C. Induction of pole and zero frequencies.
For complex conjugate poles and zeroes
A = Retzi 1 + J Im[z, ], z2 = Re[z, ] - j Im[z, ]
P\ =Re[Pi] + yim[/71], p 2 = Re[/?, ] - j Im[/?, ] ’
a biquadradic transfer function H(s)
H(S) - K (J + ziXJ + z 2> _ K s 2 +(zl +z2)s + zlz2
(s + p l)(s + p 2) s 2 +(pl + p 2)s + p ip 2
can be rewritten as
H ( s ) = K .~ ' r r j: 2 • (C-2)
• s + 2 • Re[z, ].y + (Re[z, ]) +(Im [z,])
s2 +2- Re[p, ]s + (Refpj ])2 + (Im[p, ])2
Meanwhile H(s) with pole frequency wp, zero frequency wz, pole-Q of Qp
and zero-Q of Q: is a form of
tt, \ v s2 + (w JQ z)s + w 2
H(s) = K ■ —— - - . (C-3)
s +(.wp /Qp)s + wp
Therefore, from (C-2) and (C-3),
w
w
= j(R e[z,])2 + (Im[z,])2
= V(Re[^t])2 + (Im[^ ])2
Q = ■ - 3 - ■ (C-4)
2 • Rejz, ]
W n
QP= P
2-R e[p1 ]
112
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Asset Metadata

Creator Lim, Jun-Hee (author)

Core Title A passive RLC notch filter design using spiral inductors and a broadband amplifier design for RF integrated circuits

School Graduate School

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag engineering, electronics and electrical,OAI-PMH Harvest

Language English

Contributor Digitized by ProQuest (provenance)

Advisor Choma, John (committee chair), Hashemi, Hossein (committee member), Kim, Eun Sok (committee member), Moore, James E. (committee member), Namgoong, Won (committee member)

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c16-447126

Unique identifier UC11341023

Identifier 3196844.pdf (filename),usctheses-c16-447126 (legacy record id)

Legacy Identifier 3196844.pdf

Dmrecord 447126

Document Type Dissertation

Rights Lim, Jun-Hee

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the au...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus, Los Angeles, California 90089, USA