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On-chip tuning scheme for CMOS RF filters by implicit gain determination

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On-chip tuning scheme for CMOS RF filters by implicit gain determination

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Content ON-CHIP TUNING SCHEME FOR CMOS RF FILTERS
BY IMPLICIT GAIN DETERMINATION
Copyright 2003
by
Vijayaraghavan Srinivasan
A Thesis Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
MASTER OF SCIENCE
(ELECTRICAL ENGINEERING)
(December 2003)
Vijayaraghavan Srinivasan
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UMI Number: 1420402
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UNIVERSITY OF SOUTHERN CALIFORNIA
THE GRADUATE SCHOOL
UNIVERSITY PARK
LOS ANGELES, CALIFORNIA 900894695
This thesis, written by
Vi JA V a RACc I-I/WAM Sg.tfJ|VASA*J
under the direction o f h LA thesis committee, and
approved by all its members, has been presented to and
accepted by the Director o f Graduate and Professional
Programs, in partial fulfillment o f the requirements fo r the
degree o f
Director
Date Decem ber 1 7 , 2003
Thesis Committee
Z ^ f > w \ s
\ J / ] . f i / / 1 - / 7 7. ' Chair
l o A I i/ a
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ACKNOWLEDGEMENTS
This work was my first attempt at transistor level design for radio frequency
applications. I thoroughly enjoyed working on the topic and it has given me immense
satisfaction in gaining a better understanding of the subject. I would like to thank
Dr. Jack Wills, my principal advisor, for suggesting this interesting topic and for his
guidance throughout the course of this work. I would also like to thank my committee
members Dr. John Choma and Dr. Won Namgoong for their questions and suggestions.
At the student level, I would like to thank Dr. Yuyu Chang for the many
discussions I had with him while he was at ISI working on his doctoral dissertation and
Dr. Soonwook Hwang, with whom I shared the same office, for his company especially
on many of those long nights and weekends.
Finally, I would like to thank Mr. Jeff LaCoss at ISI under whom I work as a
research assistant, for his support throughout my Master’s program.
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TABLE OF CONTENTS
ACKNOWLEDGEMENTS.......................................................................ii
LIST OF T A B LES..................................................................................v
LIST OF FIGURES................................................................................vi
A B S T R A C T ..........................................................................................ix
CHAPTER 1: INTRODUCTION......................... ...1
1.1 Motivation .... 1
1.2 Research Goals........... ............2
1.3 Thesis Organization..... ...... 2
CHAPTER 2: SURVEY OF TECHNIQUES............................................... 4
2.1 Introduction. ...... 4
2.2 Receiver Architecture...........................................................................5
2.3 Tuning Schemes for RF Filters.................................................................6
CHAPTERS: VARIABLE GAIN A M P L IF IE R ............................................11
3.1 Introduction.............................................. ................... 11
3.2 VGA Architecture.............................................................................. 12
3.3 Simulation R e su lts..............................................................................17
CHAPTER 4: BANDPASS AMPLIFIER.....................................................1 9
4.1 Introduction......................................................................................1 9
4.2 Design Description and Analysis.............................................................2 0
4.2.1 Design Specifications. ...... ..24
4.2.2 Device Sizing. ...... 24
4.3 Simulation R e su lts..............................................................................28
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CHAPTER 5: THE TUNING S C H E M E ......................................................32
5.1 Introduction........................ .....................................3 2
5.2 Filter Transfer Function........................................................................3 3
5.3 Functional Description of the Timing Scheme. ......... .36
5.4 Circuit Level Design Description............................................................4 1
5.4.1 PMOS Varactor. ...... ...41
5.4.2 Active Q-Enhancement Circuit. ...............46
5.4.3 Peak Detector Circuit. ..... 50
5.4.4 Sample and Hold S ta g e ..................................................................51
5.4.5 The OTA Integrator...... ..................... .......54
5.4.6 The Overall Circuit Schematic.........................................................5 9
5.5 Simulation Results. ........ ...65
CHAPTER 6°. RESULTS AND CONCLUSIONS..........................................73
6.1 Introduction.................................................. ......73
6.2 Summary of Results for the Tuning Scheme. ..............73
6.3 Front-End Performance Measures. ..... .75
6.4 Conclusions.......................... 77
REFERENCES......................................................................................79
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LIST OF TABLES
Table 3.1 VGA Design P aram eters......................................................... 16
Table 3.2 VGA Performance Characteristics.............................................. 18
Table 4.1 Cascode BPF Design Parameters. ....... ....27
Table 4.2 BPF Input Impedance vs. Frequency. ........... ...................29
Table 5.1 Signal Nomenclature. ........... .................38
Table 5.2 PMOS Varactor Design Parameters and Characteristics........................44
Table 5.3 Negative Impedance Generator Design Parameters. ................ 49
Table 5.4 Summary of OTA Device Sizes and Bias Voltages. .....................59
Table 5.5 Component Values and DC Voltages for the Overall
Schematic. .......... ...61
Table 5.6 Integrator Loop Time Constants. ......... 63
Table 6.1 Summary of Tuning Loop Performance. .......... .74
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LIST OF FIGURES
Figure 2.1 Typical RF Front-end in Wireless Receivers....................................6
Figure 2.2 Direct Timing S c h e m e .............................................................8
Figure 2.3 Magnitude Lock Loop (M L L )............................................ .............9
Figure 2.4 Indirect Tuning Scheme. ........ .........................................1 0
Figure 3.1 Variable Gain Amplifier with Output Buffer. ............... 13
Figure 3.2 High frequency small signal model of Gain Control stage.................. 14
Figure 3.3 High frequency small signal model of Gain Control stage
With Miller Capacitances. ................ 14
Figure 3.4 High Frequency Small-signal model of Gain Amplification
S tage............................. .......................15
Figure 3.5 VGA Characteristic C urve..................... .....................................1 7
Figure 4.1 Cascode Bandpass Amplifier.... ....... ..................................2 0
Figure 4.2 High Frequency Small-signal model of the Cascode Amplifier
With Miller Capacitances. ......... ......21
Figure 4.3 Tank Impedance Zasa Parallel Combination of Various
Circuit Elements. ......... 22
Figure 4.4 Thevenin Representation of the Source Resistance of the BPF .............25
Figure 4.5 DC Bias Generator for Cascode BPF. ....... 27
Figure 4.6 Q-Tuning Characteristic Curve. ....... ..........................28
Figure4.7 Test Setup to measure ft........................ .....................30
Figure 4.8 Simulation Output for the ftTest Circuit. ....................................3 1
Figure 5.1 Tank Circuit with On-chip Passive Elements.................................3 3
Figure 5.2 Overall Block Diagram of the Tuning Scheme................................3 7
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Figure 5.3 Filter Characteristic Without Frequency Shift.................................38
Figure 5.4 Filter Characteristic With Center Frequency Shift. .........40
Figure 5.5 PMOS Varactor C haracteristic..................................................42
Figure 5.6 PMOS Varactor Circuit Configuration.........................................4 3
Figure 5.7 PMOS Varactor Characteristic Curve. ....... .45
Figure 5.8 LC Tank with Parallel Conductance ....46
Figure 5.9 Q-Enhancement Circuit. ........48
F igure 5.10 Small-signal Model of the Q-Enhancement Circuit..........................48
Figure 5.11 Peak Detector Circuit. ......................................................... ....50
Figure 5.12 Charge Injection in CMOS Switch.............................................5 2
Figure 5.13 Clock Feedthrough due to Overlap Capacitance Cov— ••••••••...... — 54
Figure 5.14 Folded Cascode O T A ....................... 56
Figure 5.15 Overall Circuit Schematic. ..............................................6 0
Figure 5.16 Basic OTA Cell.... ......... ..62
Figure 5.17 Amplitude at the Test Frequency vs. Q. ....... 64
Figure 5.18 Input Signals at 3-dB Frequencies. ....... .65
Figure 5.19 Variation in Q vs. Temperature.................................................6 6
Figure 5.20 BPF Output with Square Wave Modulation. ......67
Figure 5.21 Peak Detector and Sample-Hold Outputs......................................6 7
Figure 5.22 Frequency Control and Peak Detector Outputs. ...................68
Figure 5.23 BPF Output after Center Frequency Tuning...................................6 9
Figure 5.24 Frequency Domain Output before and after Tuning..........................69
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viii
Figure 5.25 BPF Output with Square Wave Modulation. .................................70
Figure5.26 Peak Detector and Sample-Hold Outputs......................................7 0
Figure 5.27 Q-Control Voltage and Peak Detector Output while Tuning................71
Figure 5.28 Frequency Control Voltage. .......... ...........................7 1
Figure 5.29 BPF Output after Frequency and Q Tuning....................................7 1
Figure 5.30 Frequency Domain Output before and after Tuning........................... 72
Figure 6.1 Noise Contributions of the Front-end Stages..................................7 5
Figure 6.2 Input-referred 3rd Order Intercept Point. ....... .........77
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ABSTRACT
An on-chip tuning scheme for CMOS radio frequency bandpass filters is
proposed. The scheme intends to compensate for variations in post-fabrication filter
bandwidth due to parasitics associated with on-chip passive components and variations in
temperature and process. The filter is tuned by amplitude comparison at two test
frequencies, input during idle periods of the receive chain. The bandpass filter is realized
as a CMOS tuned amplifier. The center frequency and Q tunability is rendered by a
PMOS varactor and a negative resistance generator respectively.
The circuit was simulated for process comer and temperature variations using
HSPICE level 49 models for 0.25pm CMOS technology. The results indicate a ± 10MHz
center frequency deviation and 15% variation in Q, around the nominal values of
900MHz and 30, for the worst case variation in process and temperature and 82mW
power dissipation under a 2.5V supply voltage.
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Chapter 1
i
INTRODUCTION
1.1 MOTIVATION
With the emergence of various global standards for wireless systems,
requirements on radio-frequency (RF) communication circuits have become stringent
with respect to bandwidth, power and overall system cost. To meet these demands, lot of
research effort has been focused on highly integrated, low-cost transceiver circuits in
CMOS technology with carrier frequencies ranging from 900MHz to 2.4 GHz.
A major challenge in the design of RF functional blocks in CMOS technology is
the non-availability of passive elements with high quality factor (Q). In addition the
parasitics associated with on-chip inductors and capacitors tend to degrade the
performance. In order to work around this problem techniques using active circuits, to
compensate for the low-Q, have been in use for sometime.
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However, to solve problems involving temperature and process issues requires
more complex methods, typically involving some form of tuning, to set the post-
fabrication performance within acceptable limits of the originally intended specifications.
1.2 RESEARCH GOALS
The primary focus of this research is to develop a simultaneous frequency and Q
tuning scheme, realized on-chip, to combat the deviation in filter bandwidth due to
temperature and process variations. The other important filter parameters such as Input-
referred Noise and third order Input-referred Intercept Point (IIP3) will be measured but
major design effort to obtain specific values would not be initiated.
The entire design is to be simulated using BSIM3V3.3 Level 49 HSPICE models
and comer parameters for TSMC 0.25pm process. The passive components used in the
LC tank of the bandpass filter are instances of an ideal inductor element and a PMOS
varactor for frequency tuning, respectively.
13 THESIS ORGANIZATION
The report is organized into six chapters as follows.
Chapter 2 provides a brief overview of a generic RF front-end architecture along with a
survey of existing frequency and Q tuning techniques.
Chapter 3 and Chapter 4 describe the circuit topology of the front-end, dealing with
variable gain amplifier (VGA) and bandpass amplifier (BPF) stages respectively. Chapter
5 gives a detailed description of the proposed tuning scheme with simulation
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results for test cases. A summary of the results for the overall scheme and conclusions
from this work are presented in Chapter 6.
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Chapter 2
4
SURVEY OF TECHNIQUES
2.1 INTRODUCTION
The RF front-end of a communications transceiver consists of two basic analog
functional blocks viz. Low Noise Amplifier (LNA) and Power Amplifier (PA) in the
receive and transmit paths respectively. In addition a mixer for modulation and
demodulation operations along with several other filters may be present based on the
topology of the transceiver. The RF front-end, owing to its very high power dissipation,
is the most difficult part to integrate in silicon. Consequently, the technology of choice
for integration of these blocks in silicon plays a major role and is decided by the topology
of the transceiver system, mostly defined by the modulation scheme of a particular
telecommunication standard such as DECT, CDMA etc.
A common approach for current transceiver designs is to employ different
technologies such as GaAs, Bipolar/BiCMOS or CMOS depending on the frequency of
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operation. This method dramatically increases the system cost due to the highly
specialized fabrication process necessary. However, at the low end of the frequency band
from 900 to 2400 MHz it is feasible to integrate a complete system using currently
available Si-based technologies. Further cost reductions are possible if techniques are
made available, mainly at the circuit level, for the implementation of transceivers in pure
digital CMOS processes thereby obtaining the highest level of integration. This is an
important objective of this research project.
The digital CMOS process provides an inferior alternative to a bipolar process for
transceiver implementations. This is because of the difficulty in meeting the fundamental
requirements of high gain, linearity and quality factor. Two methods of overcoming the
deficiencies of a MOS device can be identified:
1. Usage of submicron CMOS technologies like 0.25pm process to leverage the higher
device ft of those transistors and
2. Modifications in the transceiver architecture like direct conversion schemes.
22 RECEIVER ARCHITECTURE
A generic heterodyne receiver is shown in Figure 2.1. It consists of a bandpass
filter followed by a low-noise amplifier and a mixer for down-conversion. The major
function of the bandpass filter is to remove the out of band noise, which also contributes
to the rejection of the image frequency in dual conversion receivers. Usually the bandpass
function and amplification is combined into single block. Therefore the specifications of
the bandpass filter and the amplifier must be met together.
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The important specifications are the center frequency, quality factor (Q), gain, noise
figure, linearity and power consumption. This research project primarily targets the
center frequency, quality factor and gain of the amplifier.
BANDPASS AMPLIFIER
IMAGE
FILTER
V "
BPF LNA MIXER
i i
LO
Figure 2.1 Typical RF Front-end for Wireless Receivers.
Typical Bandpass Amplifier Specifications:
Center Frequency: 900 MHz
Bandwidth: 30 MHz
Quality factor (Q): ~30
Gain: 15dB
23 TUNING SCHEMES FOR IMF FILTERS
The frequency response of a bandpass amplifier like the one outlined in the
previous section is determined by the values of transconductances and passive
components such as inductance and capacitance. The absolute element values in an
integrated circuit can shift significantly from the nominal value due to temperature and
process variations. Thus to maintain an invariant filter characteristic, a system to correct
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7
for the deviations is necessary. Such correction schemes are referred to as automatic
tuning schemes. The accuracy of response determines the type and complexity of the
filter tuning scheme. The process of tuning involves the following:
1. Measurement of specific filter characteristics such as peak gain
2. Comparison of the measured value with a reference and
3. To generate and apply necessary correction.
The tuning schemes can be classified into two categories as described below.
1. Direct Tuning: The concept behind direct tuning is shown in Figure 2.2. In this
method the filter that processes the signal is tuned. This in turn is typically
accomplished in one of two ways depending on the filter usage mode as depicted
below.
Direct Tuning
i
Continuous or Adaptive Burst-mode Tuning
Tuning
The continuous mode involves inferring the filter parameter estimates from the
statistics of the input and output signals and hence the tuning process is complex.
On the other hand when the filter is operated in bursts, the filters in the receive
chain can be tuned in the idle time. This work corresponds to the latter mode of
tuning and involves the measurement of the gain of the filter for two selected
input frequencies which are offset from the center frequency. Thus the filter is
tuned by implicit gain determination.
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INPUT * ■ OUTPUT
TUNING
SCHEME
FILTER
Figure 2.2 Direct Tuning Scheme.
A specific case of direct tuning for frequency and Q employs a Vector Lock Loop
(VLL) also referred to as the Magnitude Lock Loop (MLL). This scheme utilizes the
phase difference between the input and output and output magnitude for frequency and Q
tuning respectively. The block diagram representation for this scheme is shown in
Figure 2.3 and the tuning process is described below:
Frequency Tuning: A sine wave at 3-dB frequency is input to the filter and a feedback
system measures the phase difference between the input and output and generates the
correction signal. In the case of a bandpass filter the transfer function is given by
s
= (2-1)
^ y + - ^ - + l
® 0 ® 0 Q
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9
A sine wave at the F+jde frequency which is the pole frequency for the low-pass slope in
the bandpass characteristic experiences a phase shift of 90°. This fact is used to tune the
center frequency ra0 .
Quality Factor Tunings The gain of the filter is measured by a feedback system,
compared with a reference and applies necessary correction.
BPF PEAK DETECT
REFERENCE INPUT
FREQUENCY
, f PHASE COMP.
LPF LPF
Figure 2.3 Magnitude Lock Loop (MLL).
2. Indirect Tuning: This method of tuning is also referred to as MASTER-SLAVE
tuning scheme as shown in Figure 2.3. The filter that processes the signal is tuned
by inferring its filter characteristics from a replica filter resident on the same chip.
Any non-idealities in the response of the replica filter would also exist on the
main filter and hence the corrections applied to the replica filter should tune the
main filter. The replica filter is the MASTER and the main filter is the SLAVE
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1 0
filter. A disadvantage of using this scheme is the doubling in area and power
dissipation. An alternative is to use a replica which is not identical to the main filter
but sufficient to model the main filter characteristics.
OUTPUT
SLAVE
FILTER
MASTER
FILTER
TUNING
SCHEME
Figure 2.4 Indirect Tuning Scheme.
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Chapter 3
11
VARIABLE GAIN AMPLIFIER
3.1 INTRODUCTION
In this scheme the variable gain amplifier (VGA) precedes the Bandpass amplifier
(BPF). The cascode amplifier, which is the principal circuit performing the bandpass
function, is accounted together with the preceding VGA as the Low Noise front-end
Amplifier (LNA) though the latter would degrade the noise performance. This definition
is necessary because in the scope of this report input to the BPF will be via the VGA. It is
also understood that the VGA stage could essentially be de-linked once the tuning is
complete, with bit more complexity added to the input switching circuitry, thereby
boosting the noise performance. With this flexibility in mind the VGA and BPF stages
are designed independently with regard to the input matching considerations and are
connected by inserting a buffer as detailed in the following design description.
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1 2
3.2 VGA ARCHITECTURE
The VGA is realized in two-stages with the first stage providing the gain control
and the second working as a wide-band amplification stage. This topology serves to meet
the bandwidth requirements while providing an overall gain that results in an acceptable
noise figure as well as providing sufficient amplitude to the BPF input after the
attenuation from the impedance match, which has a direct bearing on the signal amplitude
fed to the subsequent processing stages viz. peak detect and averaging.
The gain control is obtained from a simple common source (CS) amplifier with a PMOS
load biased in the triode region. The CS configuration has acceptable high frequency
performance with regard to gain and input-output impedances. The PMOS load is used to
obtain higher values of load resistance for a given control voltage. The on resistance of a
PMOS device in triode region is given by
r - on = w " ...................... -(3.1)
K p * { - r i V SD-V c -V th)
where, Vc is the gain control voltage and Kp is a process constant.
When compared with an NMOS load for the same purpose, PMOS devices offer
larger resistance values because with the process used, Kp is roughly 5.5 times smaller
than Kn. This implies that a given gain could be obtained with a smaller value of gm thus
lowering the power dissipation. Also a smaller device increases the bandwidth though
there is a trade-off with the bigger load resistance fighting against a smaller parasitic
drain capacitance.
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The gain control stage is shown in Figure 3,1 where MN1 is the CS driver
transistor and MP1 is the PMOS load. The high frequency small signal model is shown in
Figure 3.2. Owing to its small value, the parasitic drain capacitance associated with the
PMOS load is omitted in the analysis that follows.
Vdd
Vc
MP1
Rl
Vin
Rf
Cc
MM
MN3
MN2
V_b
Vo
MN4
X 7
Figure 3.1 Variable Gain Amplifier with Output Buffer.
The overall gain is the product of the gains for these two stages Ag c and AW b
respectively.
A = Ag c-Aw b-
(3.2)
The small signal model for the gain control stage shown is in Figure 3.2. The circuit can
be modified as shown in Figure 3.3 by adding the miller capacitances Cm i and Cm o , at the
input and output nodes respectively, in place of Cg a.
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14
Cgd
Vin Vo
gm V inW Cgs
Figure 3.2 High Frequency Small-signal Model of Gain Control Stage
l + Ag c
(3.3)
c = 8
m o |
1 + -
(3.4)
Vin Vo
Cmi Cgs Cmo
gmVin
\ 7
Figure 3.3 High Frequency Small-signal Model of Gain Control Stage
with Miller Capacitances.
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15
Summing the currents at the output node we get,
1 1 _
(- hsC„
T T
o n ,p ds
A
\ gc J
= - a V.
in
Upon simplification the expression for the gain is,
gj&on.p lk*) + ^ ( r 0 „! P 1 rc
[1 + sCg d (r 1 rds)]
•(3.5)
As is the case, for small values of Cg d and ro n jP the above gain expression reduces to
^ g c S m A o n ,p ) '
•(3.6)
The output of the gain control amplifier is AC coupled to the wideband amplification
stage. This is another CS amplifier with shunt feedback to enhance bandwidth and also
provides an easy way to keep the operating point fixed, making it easy to use a buffer
before the cascode BPF. The high frequency small signal model of this wideband
amplifier is shown in Figure 3.4 below.
R f
Vin Vo
A
rds
Cgs
Rl
in \
7
Figure 3.4 High Frequency Small-signal Model of Gain Amplification
Stage.
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The gain of this wideband stage AW b can be derived by applying superposition at
the output node.
Sn rds I I
V V
R,
sC
g a )
\Rl 1 +
(rds I I &L )
( r & I I Rl) +
Rf
1
sC
gd
The feed-forward term made up by the parallel combination of Rf and Cg d equals just Rf
for small values of Cg d . The drain-source resistance is typically much larger than Rf and
thus the above equation reduces to,
...........................................(3-7)
Rp + R -L
The output impedance of the wideband amplifier is approximately equal to the
load resistance which is 300 ohm. A common drain stage is added to present the required
low impedance close to 50 ohm at the input of the BPF. The component values and
device sizes of this VGA section is listed below in Table 3.1.
TABLE 3.1: VGA Design Parameters
PARAMETER VALUE
(W/L)i 30u/0.24u
(W/L)i 30u/0.24u
(W/L)i 10u/0.24u
(W/L)i 300u/0.5u
(W/L)i 300u/0.5u
Rf
10k
Rl
2k
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17
33 SIMULATION RESULTS
The VGA characteristic curve obtained from simulation is shown in Figure 3.5
below. An overall gain variation from 6dB to 17dB is obtained when the control voltage
is varied from 0 to 1.3v. The usage of control voltages in the neighborhood and beyond
1.3v is avoided as it causes the PMOS load to enter saturation region.
5.5
4JS-
4
5'
3 :
2.5
2:
1 .5
1
'VsnsfWeeaiii: Amplifier
0.2 0.4
- Control Vi
Amp Output
Buffer Output
: 1.2 1.4
Figure 3.5 VGA Characteristic Curve
The input-referred noise voltage is shown in Table 3.2. The noise performance
was analyzed using SPICE for different gain settings. The minimum gain setting gives
rise to maximum noise because the total output noise is divided by the gain. The major
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18
noise contribution comes from the load and feedback resistors Rf and RL of the shunt
feedback amplifier.
Bandwidth of interest: 880MHz - 920MHz.
TABLE 3.2: VGA Performance Characteristics
GAIN CONTROL
VOLTAGE (V)
GAIN
(dB)
INPUT-REFERRED
NOISE (pV)
0.1 6.38 20.72
0.3 6.97 19.63
0.5 7.71 18.52
0.7 8.7 17.17
0.9 10.0 15.6
1.1 12.4 13.7
1.3 17.4 11.31
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19
Chapter 4
BANDPASS AMPLIFIER
4.1 INTRODUCTION
The primary emphasis of this research project is on the tuning scheme, to control
the center frequency (Fc) and the Q-factor, of a bandpass amplifier. To simplify the
design process, a single-ended circuit configuration is used to implement the bandpass
function. The use of cascode stages for high frequency amplifier designs is well
understood for reasons such as high gain and better stability. In comparison with a CS
amplifier, higher values of gain are achieved with a cascode structure because of higher
output impedance and better stability through the inherent input-output isolation which
diminishes the miller effect on the parasitic drain capacitance to a large extent, increasing
the bandwidth of operation. The high output impedance also serves to achieve a given
gain with a smaller device resulting in lower power consumption. This chapter discusses
the design methodology for the tuned cascode amplifier.
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20
4.2 DESIGN DESCRIPTION AND ANALYSIS
The band pass amplifier is basically a generic tuned amplifier. The circuit, shown
in Figure 4.1, consists of a cascode stage driving an LC tank, which acts as a high
impedance load at the resonant frequency. Thus the gain at the resonant frequency is
boosted. A simplified small-signal model of the circuit is shown in Figure 4.2, where gm i
and gm2 are the transconductances of MOSFETs Ml and M2 respectively, Cto t is the total
capacitance at the output node including the parasitic capacitances of the MOSFET M2
and Gto t is the total conductance at the output node including the output conductance of
the cascode stage and the parallel conductance of the inductor L.
M2
Vin Ml
Figure 4.1 Cascode Bandpass Amplifier
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21
Tank Impedance
V i n
Figure 4.2 High Frequency Small- signal Model of Cascode Amplifier with
Miller Capacitances.
C t o t = C f ........ (4.1)
where, Cf is the frequency setting capacitance from the PMOS varactor and
Cp is the parasitic capacitance at the drain of M2.
C jni is the miller capacitance at the input of Ml
Cm o is the miller capacitance at the output of Ml.
The impedance of the tank circuit, Z, is the parallel combination of the on-chip
inductance, the total capacitance Cto t and the total effective parallel conductance Gto t.
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22
The effective parallel conductance Gto t by itself is a parallel combination of the
equivalent conductance of the inductor and the negative conductance supplied by the Q-
enhancement circuit as shown below in Figure 4.3.
E d s fLP
Figure 4.3 Tank impedance Z as Parallel Combination of
Circuit Elements
The series resistance of the on-chip inductance, which reduces the Q considerably, is
negated by the effective parallel conductance of the Q-enhancement circuit. The
transformation of the series resistance Rls to a parallel resistance (conductance Glp) is
valid in a narrow frequency range about the center frequency of operation. Thus the
effective parallel conductance or the conductance after enhancement is given by G e h h -
& E N H = ( & L P ~ S d s t f l ) ~
And for small g*,
^ENH ~ & L P ~ & Q ............................ ■ (4.2)
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23
The overall expression for Z can thus be written as:
1
Z - s L \
sC,r
R
enh
z = -
sLR
enh
S t o t R n h + $ L + R enh
z = -
c
\ lot
s2 +s
' 1 N
B
\ enh tot
(4.3)
+ -
LC.r
The following equations can now be derived from the sm a.1 1 signal model yielding the
gain for this stage:
Z r
O 2
Vo
~1 1 ‘
f 1 1
— +
---- —
8 m 2 ~ 8 mb2 + -----------
z
r o 2 „ < r o 2 ;
A ~ S m A i r ,
A - V ° -
v Jy 8 ml 8 m 2 8 m b 2
' o 2 J
Zr
o 2
Z + r
o2
A = ~ S n 8 m 2 8 mb2 roiro 2
1 + SiC m o + C gs 2 F o l
Z + r
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24
For large values of the drain-source resistance of M2, r0 2, the above expression for the
gain can be written as,
8 ml (.8m2 8mb2 \" ol
1
, (4.4)
where Z is given by equation (4.3).
4.2.1 DESIGN SPECIFICATIONS
Center Frequency
Gain
Q Factor
Noise Figure
Process Technology
900MHz
15dB
30
< 3dB
TSMC 0.25 micron
4.2.2 DEVICE SIZING
Noise performance and power consumption are two conflicting design parameters
in high frequency amplifier design. An expression for the width of the main device Ml in
the cascode structure, that takes both noise and power into consideration, is given in [1].
The optimum device width Wopt, is given by
1
W = -
° P ‘ 3a)LCR
(4.5)
where ra = 2flf = 5.625Grads/s L = Length of the transistor =0.25pm
4 2
C ox = — - = 6.05mF/m Rs = Source resistance =100 ohm.
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25
Substituting the above values, Wo p t turns out to be 390pm. The cascode transistor M2 is
arbitrarily chosen to be half the size as the driver. The required gain is obtained by
properly choosing the DC bias voltage of the main device which essentially sets the gm as
well as the device ft
The actual source resistance looking out from the bandpass input has two
components as shown in Figure 4.4. One is the low output impedance, R b«f, of the buffer
stage of the VGA which is close to 60 ohm and the other is the impedance of the DC
blocking capacitor, Cc, at the signal frequency. The value of this capacitor is carefully
chosen so as not to affect the bandwidth of the preceding stage and at the same time
presenting a low impedance path. At the operating frequency of 9Q0MHz a value of 5pF,
resulting in an impedance of 35 ohm in series with RtU f, was found to be an optimum
value.
RS= 6G
Cc=35
Ml
! ! V
Figure 4.4 Thevenin Representation of Source Resistance
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26
The source resistance value, as detailed in [1], refers to the standard 50 ohm input
match used in RF circuits. Here in this design the value used in the calculation is not the
standard 50 ohm and input impedance matching techniques such as inductive
degeneration are not employed. This is because the bandpass amplifier input stage is fed
by the VGA and hence 50 ohm matching is not necessary.
Without inductive degeneration, the input impedance of the cascode structure is
capacitive, as listed in Table 4.2 in the simulation results section, with a small real part
contributed by the shunt conductance of the gate. By ensuring the ft of the main device to
be at least four times the operating frequency, the value of shunt conductance can be
made negligible and thus the gate noise associated with it is reduced to a large extent. An
approximate expression for this shunt conductance [2] is
Sg
§ m
5
.(4.6)
The SPICE simulation results for the ft of the main device are plotted under the
simulation results section, for varying Vg s.
Finally the DC bias voltage for the main device Ml is generated using the diode
connected transistor M3 which is biased by a PMOS triode load M4 as shown in
Figure 4.5. The diode connected transistor, with its drain-source resistance being l/gm3,
forms a resistive voltage divider with the PMOS triode load. The input DC level
requirement, set by gm i and ft of the main device Ml, is of the order of 0.6 volts and thus
a low value of l/gms is necessary. This resistance also provides a resistive component, in
addition to the shunt conductance gg, to the impedance of the main input device of the
cascode BPF and contributes thermal noise at the input.
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27
?
4—
v 4 4
Vin dc
1 v !3
Figure 4.5 DC Bias Generator for Cascode BPF
The component values and device sizes are listed below in Table 4.1.
TABLE 4.1: Cascode BPF Design Parameters
PARAMETER VALUE
Ml 390u/0.5u
M2 19Qu/0.5u
M3 25u/0.72u
M4 70u/0.72u
Cc 5pF
L 4.25nH
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43 SIMULATION RESULTS
The Q-tuning characteristic curve obtained from simulation is shown in Figure 4.6
below. An overall Q variation from 3.8 to 220 is obtained when the control voltage is
varied from 0 to 2v. These values were obtained with the default temperature and process
parameter settings. For this setting, usage of control voltages in the neighborhood and
beyond 2v results in very high values of Q.
G-twing Characteristic Cusve
200
180
Q approaches infinity
in the vicinity of Vcq=2v.
1:60'
I
6T20'
/
.so- /
20
1.2 T.3 1.4 1 J 1.6 1.7
Q-Gontroi Voltage Vcq
1.8 1 J 2
Figure 4.6 Q-Tuning Characteristic Curve
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29
The input impedance as a function of frequency in the band 880MHz-920MHz is listed in
Table 4.2 below. As the phase entry indicates, the input impedance looking into the main
device is capacitive for this range of frequencies.
TABLE 4.2: Cascode BPF Input Impedance vs. Frequency
FREQUENCY (MHz) Zjn (MAG) Zin (PHASE)
880.00000 69.8014 -67.1128
882.02861 69.8464 -67.0155
884.06190 69.9320 -66.9027
886.09987 70.0692 -66.7713
888.14254 70.2704 -66.6183
890.18992 70.5491 -66.4408
892.24202 70.9180 -66.2374
894.29885 71.3861 -66.0061
896.36042 71.9541 -65.7590
898.42675 72.6091 -65.4976
900.49783 73.3210 -65.2390
902.57370 74.0426 -65.0011
904.65434 74.7164 -64.8018
906.73979 75.2874 -64.6542
908.83004 75.7165 -64.5636
910.92511 75.9877 -64.5267
913.02501 76.1076 -64.5344
915.12975 76.0985 -64.5745
917.23934 75.9895 -64.6353
919.35379 75.8096 -64.7069
921.47312 75.5839 -64.7820
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30
The ft of the main device was estimated using the approximate expression given in [2],
f ' =^ r ST r ...................................................(4'7) In Cffl + Lg d l
From hand calculation with the device width used for Ml and a current of 1mA, the
transconductance gm i is found to be of the order of 18mS. From the BSIM3V3-Level49
device model, the gate-source and gate-drain capacitance was found to be 1.173 IpF and
0.1652pF respectively, for the device width used. Substituting all these values into
equation 4.9 we obtain a value of 2.14GHz for ft.
This value of ft is 2.4 times the center frequency of the filter. The test setup shown
in Figure 4.7 below was used to verify the calculated value by simulation and the
simulation output is shown in Figure 4.8.
Yds
Vs
Vdc
Figure 4.7 Test Setup to Measure ft
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31
I
?
c
I
8
Figure 4.8 Simulation Output for the ftTest Circuit
From simulation the value of ft is found to be 1.91 GHz which is close to the theoretical
estimate of 2.14GHz.
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32
Chapter 5
THE TUNING SCHEME
5.1 INTRODUCTION
Frequency characteristics of continuous time filters realized using on-chip passive
elements are subject to fabrication tolerances, environmental changes and parasitics and
thus are inherently not tightly controlled. This work focuses on a radio frequency (RF)
filter that is implemented as a tuned amplifier with the inductance and capacitance of the
tank realized on-chip. The on-chip inductance, most commonly implemented as a spiral,
has low-Q factor because of the parasitic series resistance. This results in a low-Q overall
bandpass transfer function for the front-end filter, where it is assumed that the parasitics
associated with the variable capacitor of the tank can be neglected and thus is modeled as
ideal in the analysis. In order to compensate for the low-Q inductor, an active tunable Q
enhancement circuit is employed.
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33
As will be shown in detail, this tunable Q feature necessitates a center frequency tuning
circuitry to work in tandem. This chapter describes the circuit topology that accomplishes
this task of simultaneous frequency and Q toning including the method adopted for
generating the tuning control signals from the gain-frequency characteristic of the filter.
5.2 FILTER TRANSFER FUNCTION
The transfer function of the bandpass filter is essentially defined by the
impedance of the tank circuit. The tank circuit realized with on chip passive elements is
shown in Figure 5.1. The inductor is shown with its parasitic series resistance and the
capacitor, implemented as a PMOS varactor, is assumed ideal for analysis purposes. Also
shown is the variable negative conductance element which is supplied by the active Q
enhancement circuit.
R s
Cf
-Gr
Figure 5.1 Tank Circuit with On-chip Passive Elements
The impedance of the tank circuit, Z, determines the center frequency ©c and hence the Q
which is defined relative to the amplitude at the center frequency. The above circuit could
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34
be modified with the series resistance of the inductor transformed to parallel conductance
but it would not lend itself to the general case analysis as such a transformation would
only be valid for reasonably high-Q inductors. Thus a more general topology is used for
the following derivation of the impedance of the tank circuit.
From Figure 5.1 the impedance of the tank circuit is given by
z = sLs + Rs
l+(SCf -G Q fcL,+R,)
Z = SL, +Rs (51)
s%C,+s{CrR ,- L f i Q )+ \-R fia ................................
Adjusting the denominator to match the generic second order transfer function, we can
infer the following:
(O c —
-yl Rs^Q
~ W 7
a > c = a>„fi-R,Ge ....................................................................(5.2)
where ®0 and ® q are the actual center frequency of the tank and the resonance frequency
of the tank respectively.
The quality factor, Q, is given by
q =------® (5.3)
Cf R ,-L ,G e
The quality factor of the tank, Qo, without the negative conductance is just the quality
factor of the inductor given by
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Using (5.4) and recognizing that
, Chi? — L G0
1 - Q2 0GoRs = ' —£ ■
0 6 5 Cf Rs
Equation (5.3) can be rewritten as
O = ^ W 1 r *g q ( „
C } R l ^ - Q l R , G Q) ......................................................................
Thus Q can be made arbitrarily large for Gq values close to 1 /QqRs.
It can be inferred from equation (5.2) that varying G q also varies the center
frequency and thus the center frequency must also be tuned simultaneously to maintain
the filter characteristic invariant while Q tuning. It is also understood that this frequency
variation is in addition to the variation that is due to process and temperature and the
proposed tuning scheme Is intended to combat all of these variations.
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36
5.3 FUNCTIONAL DESCRIPTION OF THE TUNING
SCHEME
Transceiver architectures, in general, employ switching between transmit and
receive modes. This implies that the receiver functional units remain idle during
transmission and thus this period of time can be used to tune the front-end filters in the
receive chain. The tuning circuitry has its test inputs as two pure sinusoids symmetrically
placed in frequency about the center frequency of the bandpass filter. The two
frequencies coincide with the one-sided 3-dB bandwidth that would be obtained with a Q
of 30.
The quality factor (Q) is a measure of the frequency separation of the 3-dB points
on the transfer curve relative to the center frequency. A direct way to get an estimate of
the Q would be to identify the frequency at which the amplitude is 3-dB down from the
maximum. This method has practical difficulties, an obvious one being the requirement
for the filter input to be swept over a wide frequency range. On the contrary, the peak
gain being fixed a priori implies that for a given Q, the 3-dB points on the frequency
characteristic are fixed. The important requirement of keeping the gain constant at the
output of the bandpass amplifier is met by including a variable gain amplifier (VGA) in
the chain, before the BPF.
The overall block diagram for the tuning scheme is shown below in Figure 5.2.
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37
VSl
OKI VGA BPF PEAK DETECT
A /
A /
CK2
VSl
VoffJF
LPF OKI
DA
CK2
Voff_Q
LPF
DA
LPF
DA - Difference Amplifier with bias input.
DA
Voff_A
Figure 5.2 Overall Block Diagram of the Tuning Scheme
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38
The signal nomenclature used in Figure 5.2 is explained in Table 5.1 below.
TABLE 5.1: Signal Nomenclature
VS!,2 Input test signals at the 3-dB frequencies.
CKi,2 ignals used to switch the test inputs and sample the peak detector
Voff_A,F,Q Offset voltages, for setting the required amplitude, frequency
and Q, that are added to the difference amplifier output after the
current error is computed.
Vref_A,Q Reference voltage inputs to the difference amplifier, used to
compute the current error in amplitude and Q.
The offset and reference voltages are fixed DC voltages selected as the optimum value to
meet the variations due to temperature and process. Figure 5.2 shows three different
tuning loops - amplitude, frequency and Q, working in tandem. The functioning of the
three loops can be understood by taking an instantaneous snapshot of the system while it
is running and by considering two possible scenarios reflecting the state of the system.
CASE I: The frequency is perfectly tuned to the desired center frequency
In this case, the amplitude at the two test frequencies should be equal irrespective
of the current Q value. This state is depicted in Figure 5.3 below.
k
#
1 Amplitude
g
i
I
/ .........
%
......%
i
« * ■
f
g
t
*
\
s
* *
%
—— i — ----------------------------------------------------------— ►
Fc - 3dB Fc Fc +3dB Frequency
Figure 5.3 Filter Characteristic with no Frequency Shift
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By comparing the output of the peak detector at any of the test frequencies with
the amplitude/Q reference, we get an error signal that is proportional to the deviation in
amplitude and Q. The stability of the two loops is ensured by adjusting the time constant
of the integrators appropriately. Specifically, the time constant lAof the amplitude control
loop is set smaller that than the time constant tq of the Q control loop. This can be
intuitively understood by looking at extremely high or low Q cases that could arise,
where the amplitude loop would work faster in steering the bandpass amplifier output in a
direction opposite to that of the instantaneous direction forced by the Q enhancement
circuit, thus helping the loop to converge.
CASE II: The center frequency is not tuned to the correct center
This case represents the general state of the system at any given point in time as
the loops run simultaneously to ensure that on an average, the frequency characteristics
remain invariant most of the time. This implies instantaneous departures from the desired
values are expected. Two possible states for this case are depicted in Figure 5.4. Here the
peak detector output is different for the two test inputs which are the 3-dB frequencies
relative to the current center frequency. The sign of the difference of the amplitudes for
the two test frequencies gives the direction of the shift in center frequency, above or
below, in relation to the desired center frequency. The magnitude of the difference is the
estimate of the instantaneous error relative to the center frequency. This difference
magnitude is scaled and added to an offset to correct for the shift. The offset corresponds
to the zero error input, corresponding to the correct center frequency, to the variable
capacitor included in the LC tank load of the bandpass amplifier.
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40
A p c -3 d B > A p c + 3 d B Apc-3 d B < A F c+ 3 d B
7
Fc-3dB Fc Fc+3dB Fc-3dB Fc Fc+3dB
Figure 5.4 Filter Characteristic with Center Frequency Shift
The variable capacitor realized using PMOS transistors in accumulation mode
shows an increase in capacitance with a decrease in control voltage and vice versa. Thus
the resonance frequency decreases with decrease in control voltage and vice versa. This
characteristic is used in deciding the order of inputs to the difference amplifier.
Specifically, if the current frequency error is positive then the amplitude of the peak
detector at Fc + 3d B is greater than the output at Fc - 3ds and thus a negative correction, to the
zero error offset, is to be added to drive the tank circuit in the direction towards the
desired center frequency. This implies that the Afc+3< ! b signal is to be applied to the
positive terminal of the difference amplifier since the feedback configuration of the
amplifier is inverting. The circuit configuration is explained in detail in the following
sections.
Since the amplitude and the Q control loops require the current center frequency
to be closer to the correct center and because the sensitivity of the varactor is high, the
variations in the tuning voltage to the varactor need to be slow. This requires a longer
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41
time constant for the frequency control loop and hence ip is the largest. This ensures that
the current center frequency moves in the appropriate direction towards the correct center
even as the other two loops work simultaneously.
5.4 CIRCUIT LEVEL DESIGN DESCRIPTION
In this section the design of various circuit blocks used in the implementation of
the three tuning loops are each explained in detail. At the core of this design is the circuit
topology that generates the control signals used in the tuning process. Also of
considerable importance is the integration of these circuit blocks.
5.4.1 PMOS VARACTOR
A MOS transistor with its drain, source and bulk terminals connected together
forms a capacitor with the resulting capacitance being a function of the voltage Vbg
between the bulk and the gate. In the case of a PMOS capacitor, an inversion channel
with mobile holes builds up for Vbg > |Vtp|, where |VT p j is the threshold voltage of the
transistor. When Vbg is very much greater than Vtp, then the MOS capacitor works in the
strong inversion region. For some voltage Vg>Vb, the MOS device enters the
accumulation region, where the voltage at the interface between the gate oxide and the
bulk is positive and high enough to allow electrons to move freely. Thus, in both strong
inversion and accumulation regions the value of the MOS capacitance is equal to the
oxide capacitance Co x . For intermediate values of Vbg the MOS device progressively
goes through moderate inversion, weak inversion and finally into depletion. In these
regions there are fewer and fewer mobile charge carriers at the gate oxide interface which
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42
causes the effective capacitance Cm o s of the MOS device to decrease. The capacitance
versus tuning voltage characteristic is shown in Figure 5.5.
Cox Cmos Cox
VBG
Accumulation Depletion Weak Moderate Strong
Inversion Inversion Inversion
Figure 5.5 PMOS Varactor Characteristic
In this design a PMOS device is used to implement the capacitor since the tank
circuit configuration easily allows the capacitor to be biased in the accumulation region.
The tank circuit is connected between VDD and the drain of the cascode transistor of the
bandpass amplifier. Due to the presence of the inductor the drain of the cascode transistor
is also at VDD and thus two drain, source and bulk tied PMOS capacitors can be
connected as shown in Figure 5.6. The varactor moves progressively into depletion, weak
inversion and moderate inversion as the frequency control voltage increases and thus the
effective capacitance connected to the tank decreases as the tuning voltage increases.
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43
MV1
-Gq
MV2
MC
Figure 5.6 PMOS Varactor Configuration
The size of the required capacitance is determined by the frequency of operation.
In this design, the parasitic drain capacitance of the cascode transistor modified by miller
effect adds to the effective tank capacitance Ce ff.
^eff = + Cy a r ,
where Cm o is the miller capacitance due to drain-gate capacitance Cg d of the cascode
transistor and Cv a r is the capacitance supplied by the varactor. From simulation, a value of
2.2pF was estimated for the nominal capacitance of the PMOS varactor. Nominal value
refers to the capacitance required for resonance at the desired center frequency when
simulated at room temperature with Nominal-Vt device model. The varactor design
parameters and characteristics are listed in Table 5.2 and the characteristic curve is
plotted in Figure 5.7.
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The Q of the varactor is decided by the parasitic resistance which in turn depends
on the region of operation. It is understood from the analysis in [2], [3], [4] that the
parasitic resistance in the strong inversion region is dominated by the device on
resistance, Ron, and decreases going towards depletion owing to electrons becoming the
majority carriers, which have higher mobility.
TABLE 5.2: PMOS Varactor Design Parameters and Characteristics
Number of Varactors 2, connected in series
Transistor Size 300|im/5jim
Tuning Voltage Range 1.5v to 2.5v
Capacitance Timing Range - 1.5pF to 3.1pF
Q
-4 5
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M O S CAPACITANCE v s TUNING. VOLTAGE
45
©
c s s
< 0
CM
Figure 5.7 PMOS Varactor Characteristic Curve.
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T U N IN G VO LTAGE (V)
46
5A2 ACTIVE Q-ENHANCEMENT CIRCUIT
The LC tank realized with on-chip inductor and varactor capacitance has a low-Q
characteristic due to the parasitic resistance associated with these elements as shown in
Figure 5.8. The overall Q is influenced more by the inferior quality inductor than by the
varactor and thus the varactor series resistance in ignored in the analysis.
The basic principle of the Q-enhancement technique is to add a negative conductance to
the LC tank so that the inductor resistive losses can be compensated. With a negative
conductance -G q connected in parallel with the tank circuit, the modified total
conductance at the output node is
Gtof=GL- Gq. .............. (5.6)
where, Gl is the parallel conductance of the inductor, taken to be 7mmho at 900 MHz
obtained by assuming a series resistance of 60 and aQ of 5 from [5].
-LS
Figure 5.8 The LC Tank with Parallel Conductance.
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47
Gto t is decreased by the negative conductance and hence the Q value of the circuit is
increased and this helps in achieving the required gain from the cascode bandpass
amplifier with a smaller gm .
The negative conductance is generated from a circuit consisting of source-
follower and common-gate stages by employing positive feedback as shown in Figure
5.9. Feedback, in general, modifies the input and output impedances by a factor equal to
one plus the loop gain. Thus, if the loop gain is made sufficiently negative by having
sufficient positive feedback, negative resistance is achieved. The equivalent small signal
model neglecting channel length modulation is shown in Figure 5.10. From the small
signal model we have
U = - i r „ U - U ) .............................................................. (5.7)
where Vy is some voltage maintained by the current source M3.
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48
-'IN
M2
Ml
M3
Figure 5.9 Q-Enhancement Circuit.
Ix
V y
Figure 5.10 Small-signal Model of Q-Enhancement Circuit.
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49
V r ( g m l + g m 2 ) = - g m l V X
VY =-
f \
8 m l
v 8 m l ” * * * 8 m 2
= ~ 8 m 2 ^ Y =
f \
8 ml 8 m2
gml+gm2
(5.8)
Thus the effective negative conductance is given by
gq =~
8 m l8m 2
8 m l + 8 m 2
(5.9)
The values of the contributing transconductances are controlled by the current source M3
and thus the effective negative conductance is tunable by varying V ^ . The required
sizes of the transistors are listed in Table 5.3.
TABLE 53: Negative Impedance Generator Design Parameters
PARAMETER VALUE
(W/L)i 138{i/0.5q
(W/L)2 544jj/0.5p
(W/L)3 31fj/0.5|i
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'50
5.43 PEAK DETECTOR CIRCUIT
The amplitude of the bandpass filter output, at the two input frequencies, when
compared with a reference ^ provides the error information pertaining to the center
frequency and Q of the filter. The peak amplitude of the waveform is detected by a
simple source follower with a capacitive load. In the source follower of Figure 5.11, the
load resistor could either be a simple resistor or a current source.
' b p f
MP1
MP2
R ip f
C c H
C c
- d p f
R f
R l
MP3
Figure 5.11 Peak Detector Circuit.
In general, the drain current of the transistor M l is heavily dependent on the input dc
level. Here, since the input to the source follower is the output of the tuned amplifier, the
DC level is always VDD. Hence, any variation in VDD would lead to a variation in the
V gs of Ml which in turn introduces non-linearity at the output.
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51
Also, since the source follower - capacitive load combination is intended to
behave as an envelope detector, the resistor value required at the source of Ml would be
quite large. This is so because the capacitor charges quickly to the peak value of the
900MHz waveform, via Rout of the source follower which is essentially l/gm i. To
prevent discharging the capacitor, the resistive load at the source of Ml which is the only
path to ground, must be rather large to provide a substantial decay time compared to the
signal period. To avoid the above mentioned problems a current source load is employed.
This would lead to a constant current biasing for transistor MP1 as well as a large resistor
for the envelope detector function.
The output of the bandpass filter is modulated by the switching signal which is a
square wave. It is of interest to preserve the switching characteristic at the output of the
source follower while attenuating the high frequency test input. This is accomplished by a
simple RC low-pass filter, with the time constant carefully chosen to meet the objective.
The resulting signal is amplified for further processing by the integrator section.
5.4.4 SAMPLE AND HOLD STAGE
The sample and hold stage updates the input to the integrators with the current
peak detector output magnitude corresponding to each of the two test frequencies. It is
implemented as a simple CMOS switch followed by a charging capacitor as shown in
Figure 5.12. The dominant error factors arising out of this sampling scheme are those due
to charge injection and clock feedthrough [6].
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52
Charge Injection: In the worst case, all of the charge that made up the channel under the
gate oxide exits through the terminal connected to the sampling capacitor Ch.
The channel charge is given by,
The error voltage due to this quantity of charge depends on the size of the sampling
capacitor Ch and is given by,
WLCox(Vc k - v in -V tk J
AV = ■
(5.H)
-//
Also, the error voltage is positive (negative) for a PMOS (NMOS) device because the
channel is formed by holes (electrons). Therefore, by employing both PMOS and NMOS
devices together to form a CMOS switch, opposite charge packets introduced by each
type of device tend to cancel out each other and this lowers the error due to charge
injection.
CK
in
K 7
r CK
Figure 5.12 Charge Injection in CMOS Switch.
C
H
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53
Aqt = W pLpC oxtV « -\V t , p\)
(yCK— - v^x)
K = ^ ................................................................... (5.12)
L -h
................................................................... (5.13)
l h
Vo=Vin+(Vh-V e) ........................................ (5.14)
It can be inferred from the above set of equations that the error voltage due to charge
injection can be reduced by choosing small device width, W, for the switch and by
increasing the size of Ch-
Clock Feedthrough: The CMOS switch also couples the gate transitions to the sampling
capacitor Ch through the gate-source overlap capacitance as shown below in Figure 5.13.
The total charge flowing through the series combination of the overlap capacitance per
unit width, Cov, and Ch is given by,
w r c ............. (5.15)
The change in output voltage due to transitions of Vck is given by,
AF ~ ^ is L = YfO 'Q Z (0±F )
° w co r+ cH ck)
* y° =±v“ J i t r * - ........................................................ (516)
v rK yO V
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54
OF OV
V ^
¥ CK
Figure 5.13 Clock Feedthrough due to Overlap Capacitance C q v
The sign of the expression is positive for high to low transition. This error can be reduced
to a large extent by using a dummy switch. When the dummy switch is designed to have
one-half the width of the main switch, the total error reduces to zero.
This configuration was chosen, for the frequency correction loop would involve a
difference computation and hence any errors like charge injection while sampling would
appear as common mode input.
5A5 THE OTA INTEGRATOR
The Operational Transconductance Amplifier (OTA) is implemented as a folded-
cascode differential-input single-ended output amplifier, as shown in Figure 5.14.The
OTA is preferred because, with the primary application being an integrator, the high
output impedance that it offers would be ideal to drive capacitive loads [7]. The folded-
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55
cascode configuration is chosen over a telescopic op-amp because it allows wider output
swings. The current mirror consisting of transistors MN2-5 is a wide-swing cascode
current mirror configuration. The four transistors are biased at the edge of saturation thus
allowing the output to swing closer to the ground rail. The transistors MN2 and MN4 act
as a single diode-connected transistor ensuring that the current in the two arms are
matched more closely by keeping the drain-source voltages nearly equal. This enhances
the output impedance and reduces the input referred offset.
The choice of input devices, MA and MB, is generally governed by performance
measures such as noise and DC gain. For this application, in addition to the above
criteria, the input DC level plays a major role.
Thermal Noise: The input-referred thermal noise of a transistor is given by
r i = * K T .\.— 6 f ..................................................................... (5 .1 7 )
3 g m
The input referred thermal noise of the amplifier shown in Figure 5.14 is contributed
mainly by the input and load devices. The noise of the cascode devices MN2, MN3,
MP3, and MP5 are negligible at low frequencies. The potentially significant sources are
MA, MB, MP1, MP2, MN4 and MN5. The input-referred thermal noise is obtained by
normalizing the output referred noise of the device pairs MP1-2, MN4-5 with square of
the gain of the input devices and adding it to the noise contribution of MA,B.
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56
VB2
MP1 MP2
VB3
MP3 MP4
MNA MNB
VO
Vin
VB4
MN2 MN3
VB!
MN4 MN5
x z
Figure 5.14 Folded Cascode OTA
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57
R out is the open loop output resistance of the OTA.
V 2 I =2
V n,out IUP1,2 ^
AKT.-
3 g,
' 8 mMPl, 2^-,
2
out
mMPl,2
A/, (5.18)
n,out IMN4,5
= 2 4 KT.-
3 g
2 2 R 2
o mMN 4,5 out
mMN4,S
A /, (5.19)
where the factor of 2 signifies the uncorrelated nature of the noise sources.
The total thermal noise at the input after adding the contributions of MA-B, we get
V =2
v ntjot ^
4K T .I- 1
| ^ 8 mMPl,2 | SmMN4,5
Sm M A,B 8m M A.B y
A/ (5.20)
Flicker Noise: The flicker noise of a transistor is given by
K
F 2 = •
CoxWL
A /, (5.21)
where K is a process dependent constant and its value is lower for PMOS devices.
The total input-referred flicker noise power is given by
V2 =2
n f,tot
K
N
S mMN4,5
+ ■
K t
8 mMPl,2
Cox{WL)A,Bf ^ OX ( ^ ' ) m V 4 , 5 f 8 mMA,B ^ OX MP\,2 f 8m M A,B
A f ..(5.22)
The above expression for the total noise represents a trade off with respect to the
transconductances g mMPU2 m ^ 8 m m 4,5 • Since the wide swing cascode configuration is
used, the overdrive voltage is kept to a minimum in order to increase the output swing.
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58
However lower overdrive voltage results in higher transconductance for a given current
as implied by
........................................................... (5.23)
D,sai
This essentially increases the transconductance ratios occurring in the above noise
expressions. However, with regard to the output swing necessary to generate the control
voltages for the frequency, Q and VGA control loops, which range from 0.4v to 2.2v
under varying temperature and process conditions, noise reduction in this design is
obtained only by increasing the width of the input devices.
DC Gain: The low frequency DC gain of the OTA is given by
A v — §mMA,B^oul ........ ........ ...(5.24)
The output resistance R out of the folded-cascode structure is given by
^ out ~ tr* ,A W 3 (l + 8mMN3rdstfN5 )J I I lr& ^ V P 4 + §m M > 4rdsMP\ ) J (5.25)
where r^i is the incremental output resistance of the transistors.
The transconductance of NMOS device is higher for a given drain current because of
higher mobility of electrons. This allows higher values of gain to be achieved for less
power using NMOS devices.
Input DC Level: The input DC level is fixed by the output of the peak detector stage.
This signal has a nominal value of Iv DC which is also the nominal DC level of the
sample-hold stage. This signal exhibits shifts in the DC level reflecting shifts in center
frequency and Q of the BPF. For this value of input DC, it would be impossible to bias a
PMOS input stage for maximum output swing as the gate source voltage would be very
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high to have a wide active region of operation with a 2.5V supply rail. Thus NMOS
transistors are used as the input devices though the noise performance would be
degraded. The device sizes for the OTA are listed below in Table 5.4.
TABLE 5.4: Summary of OTA Device Sizes and Bias Voltages
PARAMETER VALUE
MNA 350u/0.72u
MNB 350u/0.72u
MN1 100u/0.48u
MN2 63u/0.72u
MN3 63u/0.72u
MN4 63u/0.72u
MN5 63u/0.72u
MP1 216u/0.72u
MP2 216u/0.72u
MP3 132u/0.72u
MP4 132u/0.72u
VB1 0.7v
VB2 1.6v
VB3 1.4v
VB4 l.Ov
5.4.6 THE OVERALL CIRCUIT SCHEMATIC
The overall circuit schematic for the three tuning loops is as shown in Figure 5.15.
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60
on
012
BUF
BUF
021
RN12 jj Cl
VofLF
RN11
RP32 0A1
RP31
RP1I
RP12
V refF
F - Section
OA3
RP22
RP21
RN31
RN32 || C3
OA2
RN21
RN221| C2 VofLQ
RP42
RP41
0A4 C Q
Q - St
RN41
RN42 || C4
RN52 || C5
RN51
OA5
RP51
RP52
VoflLA
Figure 5.15 Overall Circuit Schematic.
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61
TABLE 5*5" COMPONENT VALUES AND DC VOLTAGES FOR THE
OVERALL SCHEMATIC
PARAMETER VALUE
R N lljR Pll 15k
RN12,RP12 30k
RN21,RP21 15k
RN22,RP22 30k
RN31,RP31 5k
RN32,RP32 25k
RN41,RP41 4.5k
RN42,RP42 20k
RN51,RP51 4k
RN52,RP52 20k
C1,C2,C3 30pF
C4 25pF
C5 20pF
Vref_F lv
Vref_A,Q 0.9v
Voff_F 1.95v
VofLQ
1.4v
Voff_A 0.5v
The buffered outputs of the sample-held stages are the inputs to the integrator
sections generating the F, Q and A control voltages. The OTA OAi shown in Figure 5.16
along with the circuit elements RNil, RNi2, RPil, RPi2 and Ci is representative of the
basic integrator cell used extensively in the overall schematic. The DC voltages
Vref_F,A,Q is the amplitude reference to which the current output of the sample-hold
stage is compared with. Voff_F,A,Q is the control voltage, required by the PMOS
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62
varactor, the VGA and the negative resistance generator of the Q-enhancement circuit,
under nominal conditions of temperature and process. The nominal conditions would
correspond to 25 degrees C and nominal Vt device process comer.
RNi2 8 Ci
RNil
SIG
OA!
REF
RPil
RPi2
Figure 5.16 Basic OTA Cell
An expression for th e output of the integrator stage can be derived as follows [8]:
Applying superposition we obtain,
f mu') i
v = v
v OUT r SIG
RNil
+ V,
(l + sCiRNil)
RNil
REF
RNil + RNil
1 +
RNi2
(l + sCiRNil)RNil _
+ V,
OFF
RNil
RNil + RNil
1 +
RNil
(l + sCiRNil)RNil
.(5.26)
Upon simplifying we get,
^OUT ~ ^OFF + REF ^SIG )■
RNil
RNil
1 sCiRNil
'(l + sGRNi2)+
•(5.27)
(l + sCiRNil)
Recognizing that the signal term V Sig is the output of the sample-hold stage and
that it is a constant value for each switching period, the third term of the above equation
becomes negligible (when computed close to DC).
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63
The reduced expression is then,
^ (5.28)
It can be inferred from the above equation that the nominal control voltage gets
updated with the average error voltage supplied by the integrating operation. The time
constant of the integration operation from equation 5.28 is the product QRM2. The
individual loop time constants for the tuning circuit shown in Figure 5.15 are listed in
Table 5.6 below.
TABLE 5.6: INTEGRATOR LOOP TIME CONSTANTS
LOOP COMPONENTS TIME CONSTANT
Amplitude RN52, C5 0.4psec
Q
RN42, C4 O.Spsec
Frequency RN32, C3 0.75psec
The F-section generates the frequency control voltage and consists of integrators
OA1-3. The buffered inputs, each corresponding to a 3-dB test frequency about the
expected center frequency, are first smoothened by OAl,2 to attenuate the variations
caused by sampling before being fed to the high gain integrator stage OA3. The third
integrator OA3 averages the difference in the DC levels of these two signals and the
output corresponds to the average magnitude of the frequency error. The gain resistors
provide the necessary scaling factor to be applied to the error voltage before adding it to
an offset that corresponds to the nominal center frequency.
The Q and VGA sections work in an exact similar manner. The variation in Q
over the temperature range and process comers considered, was found to be such that for
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64
increasing Q, the amplitude of the BPF output (and hence the DC level of the peak
detector output) increases at the two 3-dB test frequencies. It is to be noted that on the
contrary for extremely high values of Q, the 3-dB bandwidth would be so small that the
amplitude at the two 3-dB test frequencies could actually be less than those obtained for
much lower values of Q. The two scenarios are depicted in Figure 5.17.
Amplitude
Figure 5.17 Amplitude at the Test Frequencies vs.Q.
With this observation, an estimate of Q can be arrived at by comparing the
magnitude of the peak detector output to a reference. This error voltage after scaling is
added to an offset, which corresponds to the nominal Q value, in order to generate the Q-
tuning control voltage. In this case the peak detector output for the lower 3-dB frequency
is used for the comparison, to be in agreement with the above observation, as simulation
shows a frequency shift towards right accompanied by decrease in Q for increasing
temperature which makes the amplitude-Q relationship less distinct.
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65
5.5 SIMULATION RESULTS
Two sample cases that offer step by step elucidation of the functioning of the automatic
tuning of center frequency and Q are presented below. The two cases correspond to
temperature and process variations respectively. The input signals, sinusoids at the 3-dB
frequencies with respect to the 900MHz center frequency and when Q is 30, for the two
sample cases are identical. The two sinusoids are switched with a 2MHz square wave and
the output of the input switching operation is shown in Figure 5.18.
720m -il J . . dr— ...................................................-d— -
|' n " T T T * {'T T ’" n " T '*l l " l 'I | ~t fl'l 'l 1 > | I ' 'i "I i I l f I I" } ' m T T *T'"1 »"T"| a I " r T T T y i 'T ' H T r T T T ^ T T > ' T Hf “f T " p " " |
248n zm zm 251 ti 25Zn Z53n 254n . 25%
Tm© i$m ) (TIM E)
Figure 5.18 Input Signals at 3-dB Frequencies.
CASE I: Tuning for Temperature Variations
Changes Observed In Filter Characteristics:
1. Center Frequency increases with increase in temperature
2. Q decreases with increase with increase in temperature
Test parameters: Temp: 50°C
Process: TSMC 025 Logic - Nominal VT
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66
The filter transfer function plotted in Figure 5.19 shows the variations in Q when the
temperature is swept from 0°C to 100°C in steps of 25°C. These curves were obtained
under open loop condition with the frequency and Q control voltages set at nominal
values that result in the center frequency and Q being close to 900MHz and 30
respectively at T=25°C.
so -
45 ~
40 -
35 -
§ , 30 -
I 2 5 -
| 20 -
5 -
IS -
10 -
-s _
T T T T
Frequency (fin) (HERTZ)
Figure 5.19 Variations in Q with Temperature.
The waveform shown in Figure 5.18 is input to the variable gain amplifier (VGA). The
VGA feeds the bandpass amplifier (BPF) and the shift in frequency resulting from the
increase in temperature is shown in Figure 5.19. This results in the square wave
modulation observed in the amplitude envelope of the BPF output as shown in Figure
5.20.
The amplitude levels at the two phases of the input switching signal are captured
by the peak detector for further processing in the comparator/integrator stages. Due to the
fact that the center frequency shift is to the right, the output amplitude for the P+ 3d B signal
is greater that for the F.3< ib signal. The amplitude level corresponding to the two switching
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67
phases are separated by the two sample-bold arms. The output of the peak detector and
the sample-bold arms are shown in Figure 5.21.
z j :
H ' T T T T 'j- T 1 1 't r r T r j T n r r , i n j n n T i - r r r j T T T T T 'r n 1 v {"i i n i l i n 1 1 r - r n - r r r f n n n i n p m i n 1 1 i t ( t t n i 1 1 r r f r n 'T T r r r T
9 2 in « 5 a i i a 1s 12u 1.4l 1j6u 1Ju Z
Tin® (in ) (TIME)
Figure 5.20 BPF Output with Square Wave Modulation.
1 -
i--
_r *
= & jr* \ --------- ‘
■ r -
} r " T " T i 'i ■ )■ ■ ■ (■ ■ t t » v 'i""| 11" i" i r r " t " » - i "T " |“ T - Y - T ' ,,r 'T " r ,,'v,"ii i i - i ' “ f T T T - r r ~r T | ~ T ) v - v - r v i i " r f f t t v i i i i
lit IJy 2 m Z M 3u
Tins (Si) (T IM E )
Figure 5.21 Peak Detector and Sample-Hold Outputs.
3.5u
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68
It is to be noted that the peak detector consists of two stages - a common drain stage with
capacitive load acting as an envelope detector followed by an amplification stage. The
amplification stage introduces an inversion in the captured square wave modulation
envelope. Thus the first stage captures the top-side envelope of the BPF output while the
overall output of the peak detector stage resembles the lower envelope of the BPF output.
This flip in the envelope is accounted for in the following comparator/integrator section.
The sample-hold outputs are fed to the F, Q and VGA control sections and under
closed loop condition converge to generate the required correction control voltages. The
frequency control signal and the peak detector output signals are shown below in Figure
5.22 and the bandpass filter output corrected for the frequency shift is shown in Figure
5.?3.
2 1
11
p r 'i - r ,i“ r-r~ rT ‘p r r T T “r r -t- i~ T -fT " rT { .. f t V i i y T ^ 'T H '-T - i^ -rn -’ -p rr-'rT -'
4ti Gu §y m
I f ( ! [ i 1 i i
IZ tt
M I I | 1 1 t 1 1 1 1 ! 1
14a
T m (ii) (TM)
r T r n -T n T T p '. r T T T T n ' T ' i ' i ' n i i r i i1 f— p T 'T 'T'T i n i r-j T T T T T - r - n i pt t t t h — i r i t ") i i i i i i i i
* G » ftl 1 0 U 1Z M 1*1
I n * fin) fTIME)
Figure 5.22 Frequency Control and Peak Detect Outputs.
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69
lUkkkihi y u y kiiiiiauiUA i yyyiu u u - L L iiL L tuiLmjiiJ u j j U L l
w
»T-rT i- i- r TT -i r 'i T T r r r i -TT T -rT -i-i-T-rj'T T-TT-n n i | i m m i l y r t r n t r r r p - t r r r r r r r p i i n v i » i | n m ' m , | [ i i m i r r r T - r T-r r n r r r
Sii 8u 10U 1 2 a I4u ISu lOu Z 2 a 24u
T i ' . - w * rrjMC’ f e
Figure 5.23 BPF Output After Center Frequency Correction.
The frequency domain output before and after tuning is shown below in Figure 5.24.
itMJSifMt -
itMBIM
I "
2 5
1 5
10
0
Rifncy(h)pnz)
Figure 5.24 Frequency Domain Output Before and After Tuning.
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70
CASE II: Tuning for Process Variations
Test parameters: Temp: 25°C
Process: TSMC025 Logic - Medium V j - FF
(FF - Fast NMOS-Fast PMOS)
As in the previous case the waveforms below offer snapshots into the various stages of
frequency and Q tuning.
j i i i vi i 1 n - i t 'i i"i i i ] i i i i i i ; t i ; ; i i i I . i I i | ^ i i ^ i . i ■ : | < j r- i-i rt i'i i i t i i !TTT 7 ’ f n lL lr : i i | , iTTT-rrr-r p ’ -nTT- f T T r r r r r i 1 mm r ’ t i n \
0 Z O ftri 400n 60tm ® 00m In 1211 tAu 1£u IJ u Zu
T iro (fc) (TIME)
Figure 5.25 BPF Output with Square Wave Modulation.
300m
mm
Figure 5.26 Peak Detector and Sample-Hold Outputs.
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71
1 i
wrtfwwffltvni> ■JftfWMWirfMVfl' wffiwH wrnfw-
I ‘VI '< t I I I 1 i I > 'rTTTTTT|TT"TT" T ’n ,l rT,rr"i r I l r. . r,T . " T .- 1 .,p . j — rT.,|r. . rT .1 ..T ..t , r r. T -;-., . , .,r-. r...p ..r. . T -. r.,— y -j , , I I J I I I
1043 15u 20n 25n 3ms 35w 4§u
Time (Bn) (TIME)
Figure 5.27 Q-Controi Voltage and Peak Detector Output while Tuning.
n " » i— t-I — i— r I t ) i i i i i t i « ' i " | - » t t t t t t t i ( i i i t i i i i i r m r v vv-T-T-1-y-r r <>11 r r q - T rT i i t t \ i
15as 2ms 25ii 3t!si 35ss
-rime m \ m i iE i
Figure 5.28 Frequency Control Voltage.
v*:,
ZA -
111'' f r
I
18u
~ i — j — i — i — i — ] — j — j — r ~
35u
Figure 5.29 BPF Output After Frequency and Q Correction.
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f r K j u e n c y (fc) (HERTZ)
Figure 5.30 Frequency domain output before and after tuning
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7400
73
Chapter 6
RESULTS AND CONCLUSIONS
6.1 INTRODUCTION
This chapter summarizes the results of the tuning scheme for the RF bandpass filter. The
SPICE simulation results on performance measures such as power dissipation, input-
referred noise and third order input-referred intercept point (IIP3) are also provided.
6.2 SUMMARY OF RESULTS FOR THE TUNING
SCHEME
The tuning scheme, as described in Chapter 2, renders the BPF tunable and generates the
frequency and Q correction voltages to combat deviations in these two parameters of
interest. The overall design was tested for temperature variations from 0°C to 100°C and
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74
for different process comers of the TSMC 0.25 digital CMOS process. A summary of the
simulation outputs are tabulated below in Table 6.1.
'TABLE 6.1: SUMMARY OF TUNING LOOP PERFORMANCE
OPERATING CONDITIONS CONTROL VOLTAGE PARAMETER
PROCESS* TEMP. (°C) VF VQ F
Q
CL025 _ TT
0 1.94 1.4 906 37.3
50 1.89 1.95 895 26
100 1.87 2.15 896 16.6
CL025 _ TT
25
1.925 1.73 895 31.9
CL025 _ FF 1.91 1.45 890 31.5
CM025
Medium Vx_FF
1.85 1.3 890 23.4
CM025
Zero V j_FF
1.83 1.22 892 19.4
* Process Comer Nomenclature:
CL025 - TSMC 0.25um CMOS Logic
CM025 - TSMC 0.25um CMOS Mixed Signal
TT - NMOS - Typical, PMOS Typical
FF - NMOS - Fast, PMOS Fast
SS - NMOS - Slow, PMOS Slow
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75
63 FRONT-END PERFORMANCE MEASURES
The front-end consists of the input switch, the variable gain amplifier (VGA) and the
bandpass amplifier (BPF) as shown in Figure 6.1. The input-referred noise voltage and
the third-order input intercept point were obtained from SPICE AC and transient analyses
respectively. These two parameters impose the lower and upper limits of the input signal
level and thus define the input dynamic range of the filter.
Input-referred Noise Voltage: The input-referred noise defines the sensitivity of the
front-end by quantifying the minimum-detectable signal level at the input.
The measurements were carried out at nominal temperature for the CLG25_TT process
comer. The overall input-referred noise calculated at the input of VGA is 26.45|iVa /Hz.
Input Switch VGA BPF
Total output noise: Total output noise: Total output noise:
Vn,switch = 5.7pV/VHz V u ,v g a = 23.36pV/VHz Vn,switch = 111.1 pV/VHz
Gain = 1.41 Gain = 4.2
Figure 6.1 Noise Contributions of the front-end stages
Input-Intercept Point (IIP3): The inter-modulation performance of the filter quantifies
the effect of non-linearity on the input dynamic range.
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76
Measurement setup:
Temp: 25°C
Process Comer: CL025_TT
Input signal frequencies: Fl=875MHz and F2=895MHz.
Inter-modulation component Frequencies: 2Fi-F2=855MHz and 2F2-Fi=9 15MHz.
The following equation representing the slopes of the fundamental and the inter
modulation components relation can be derived. Since the third order components have a
slope that is three times the slope of the fundamental,
The intercept point is computed using the above equation for each set of input and inter
modulation component powers as the input amplitude is swept from 2mV to 42mV. The
extrapolated plot of the fundamental and the third-order component is shown in Figure
Power Dissipation:
The breakdown of DC power dissipation of the various stages is given below.
VGA: 13.3mW
BPF: 15.8mW
Timing Loop: 53mW
Total power dissipation: 82.1mW.
3(IP-Pl) = IP -P 3
2IP = 3/j - P 3
(6.1)
6.2.
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77
100
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10
Figure 6.2 Input-referred 3rd Order Intercept Point.
6A CONCLUSIONS
An automatic tuning scheme for the center frequency and Q of a RF front-end amplifier
was targeted. The tuning scheme, analogous to an Automatic Gain Control (AGC) loop,
works by inferring the gain of the filter at the 3-dB frequencies and generating the error
signal by comparing with a known reference voltage. The various circuit blocks include a
variable gain amplifier, PMOS varactor, active Q-enhancement circuit, peak detector and
a OP-AMP based integrator as an averaging circuit.
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78
The various functional units listed above were individually simulated and verified for
their operation subject to the requirements on the gain and bandwidth as per the
specifications. The blocks were integrated with a LC tank based bandpass amplifier and
subsequently the closed loop performance was studied for various temperature and
process comers.
The overall scheme was found to correct for deviations in frequency and Q due to
temperature variations from 0°C to 100°C and for the Typical (TT) and Fast (FF) process
comers of the TSMC 0.25um process.
This design could not correct for the deviations due to the Slow (SS) process comer
primarily because of higher threshold voltages of the transistors which resulted in
conflicts with the various DC bias voltages and reference voltages used.
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79
REFERENCES
[2] Pietro Andreani and Sven Mattisson, “On the Use of MOS Varactors in RF
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[9] EE533a, EE533b Class Notes, University of Southern California
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Creator Srinivasan, Vijayaraghavan (author)

Core Title On-chip tuning scheme for CMOS RF filters by implicit gain determination

Contributor Digitized by ProQuest (provenance)

Degree Master of Science

Degree Program Electrical Engineering

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Permanent Link (DOI) https://doi.org/10.25549/usctheses-c16-313540

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