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Functional testing of constrained and unconstrained memory using march tests

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Functional testing of constrained and unconstrained memory using march tests

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Content INFORMATION TO USERS This manuscript has been reproduced from the microfilm master. UM I films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bteedthrough, substandard margins, and improper alignment can adversely affect reproduction. In the unlikely event that the author did not send UM I a complete manuscript and there are missing pages, these w ill be noted. Also, if unauthorized copyright material had to be removed, a note will indicate the deletion. Oversize materials (e.g., maps, drawings, charts) are reproduced by sectioning the original, beginning at the upper left-hand comer and continuing from left to right in equal sections with small overlaps. Photographs included in the original manuscript have been reproduced xerographically in this copy. Higher quality 6” x 9” black and white photographic prints are available for any photographs or illustrations appearing in this copy for an additional charge. Contact UMI directly to order. ProQuest Information and Learning 300 North Zeeb Road. Ann Arbor, M l 48106-1346 USA 800-521-0600 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. FUNCTIONAL TESTING OF CONSTRAINED AND UNCONSTRAINED MEMORY USING MARCH TESTS Copyright 2001 by Sultan M. AI-Harbi A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (COMPUTER ENGINEERING) August 2001 Sultan M. Al-Harbi Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. U M I Number. 3054703 Copyright 2001 by Al-Harbi, Sultan M . R. F. All rights reserved. _ ___ _( § ) UMI UM I Microform 3054703 Copyright 2002 by ProQuest Information and Learning Company. All rights reserved. This microform edition is protected against unauthorized copying under Title 17, United States Code. ProQuest Information and Learning Company 300 North Zeeb Road P.O. Box 1346 Ann Arbor, M l 48106-1346 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. UNIVERSITY OF SOUTHERN CALIFORNIA T he Graduate School U niversity Park LOS ANGELES, CALIFORNIA 90089-1695 This dissertation , w ritten b y U nder th e direction o f h lk .. D issertation Com m ittee, an d approved b y a il its m em bers, has been p resen ted to and accepted b y The G raduate School, in p a rtia l fulfillm ent o f requirem ents fo r th e degree o f DOCTOR OF PHILOSOPHY 1 o f G raduate S tu d ies D ate August 7 , 2001_______ DISSERTATION COMMITTEE Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Acknowledgments This dissertation would not have existed without the guidance and unlimited assistance of my advisor, Professor Sandeep Gupta. I would like to thank him for being more than an advisor, since his effect went beyond my academic life, much deeper, to my social life. Our discussions were keys that always opened new avenues of thinking and gates of knowledge. Now, I believe, as he believes, that every human-made product can be improved since humans are imperfect. This fact made me challenge every given solution to research problems and produce better solutions that others thought did not exist. This is the research spirit that Professor Gupta has instilled in me. I am very grateful for that. I would like to also thank Professor Shariffa Carlo for reading and proofreading the final version of the dissertation. My thanks also to the members of the Guidance Committee. Their feedback was very helpful in enriching my research. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Contents Acknowledgments.......................................................................................................ii List of Tables................................................................................................................v List of Figures..............................................................................................................vi Abstract.................................................................................................................... viii Chapter 1: Introduction................................................................................................. 1 LI Fault Model.................................................................................................... 2 1.1.1 Classical Fault Models............................................................................. 2 1.1.2 Extended Fault Model.............................................................................. 5 1.1.3 General Fault Model................................................................................. 6 1.2 Interacting Faults............................................................................................. 6 1.3 March Tests......................................................................................................8 1.3.1 Properties of March Tests......................................................................... 8 1.3.2 Known March Tests............................................................................... 11 1.4 Motivation......................................................................................................12 1.5 Problem Definition.........................................................................................14 1.6 Dissertation Overview................................................................................... 15 Chapter 2: Condition Generation for Fault Detection................................................... 17 2.1 Fault Representation...................................................................................... 18 2.2 Requirements for Fault Detection................................................................. 20 2.3 The Procedure for Generating Conditions for Unlinked Faults’ Detection. 26 2.3.1 The Procedure........................................................................................ 26 2.3.2 Special Cases..........................................................................................29 2.3.3 Analysis of Resulting Conditions...........................................................31 2.4 Interacting Unlinked Faults........................................................................... 34 2.5 Linked Faults................................................................................................. 35 2.5.1 Properties of Linked Faults....................................................................38 2.5.2 Single cell faults.................................................................................... 39 2.5.3 Address decoder faults.......................................................................... 41 2.5.4 Inversion coupling faults....................................................................... 42 2.5.5 CFid linked with CFid........................................................................... 44 2.5.6 CFid linked with CFin........................................................................... 48 2.5.7 CFst and CFds faults linked with other faults........................................55 2.6 Summary.......................................................................................................56 Chapter 3: March Test Generation............................................................................. 57 3.1 March Tests’ Search Space Reduction..........................................................57 3.2 First Stage: Filtration of Conditions............................................................. 60 iii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.3 Second Stage: Building the Tree Structure..................................................... 61 3.4 The Test Generation Algorithm......................................................................62 3.5 Analysis of the Algorithm...............................................................................63 3.6 Illustration of The Algorithm..........................................................................64 3.7 Generated Tests...............................................................................................65 3.7.1 March tests for unlinked faults................................................................ 6 6 3.7.2 March tests for linked faults.................................................................... 69 3.8 Constrained Memory Testing..........................................................................70 3.8.1 Unidirectional Memories......................................................................... 71 3.8.2 Queues.....................................................................................................74 3.8.3 Stacks....................................................................................................... 80 3.8.4 Embedded Memories...............................................................................81 3.9 Comparison With Previous Work...................................................................83 3.10 Summary.........................................................................................................8 8 Chapter 4: Cache Testing............................................................................................. 89 4.1 Previous Work.................................................................................................89 4.2 Cache Model.................................................................................................. 91 4.3 Efficiency Considerations For Tag Testing....................................................93 4.4 Tag Test Transformation Framework............................................................ 94 4.5 The Transformation Methodology..................................................................96 4.5.1 The Transformation Steps.......................................................................96 4.5.2 Fault Detection Capabilities of Transformed Tests.................................99 4.6 Transformation Examples.............................................................................121 4.7 Comparison of Tests Complexities............................................................. 122 4.7.1 Complexity of the Proposed March B Test........................................... 123 4.7.2 Comparison With the Previous Work.................................................... 124 4.8 Summary.......................................................................................................125 Chapter 5: Conclusions and Future Research..............................................................126 5.1 Conclusions...................................................................................................126 5.1.1 Condition Generation for Fault Detection............................................126 5.1.2 March Test Generation..........................................................................127 5.1.3 Cache Testing........................................................................................ 128 5.2 Future Research.............................................................................................129 5.2.1 March Test Generation..........................................................................129 5.2.2 Memory Structures................................................................................130 5.2.3 Cache Testing........................................................................................ 130 5.2.4 BIST Design.......................................................................................... 131 References..................................................................................................................132 iv Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. List of Tables Table 2.1: DFRs for SA, SOF, DRF, TF, CFin and CFid Faults................................19 Table 2.2: DFRs forCFst, CFds and AD Faults.........................................................19 Table 2.3: Possible Usage of M l and M2 from Figure 2.1 for Fault Detection........ 25 Table 2.4: Conditions for Detection of Unlinked Faults Generated by the Procedure Described in Section 2.3.........................................................32 Table 2.5: Some Linked CFid Faults With All Their Necessary and Sufficient Conditions................................................................................................46 Table 2.6: Possible CFid Faults and Their Detecting Conditions.............................47 Table 2.7: Sufficient Conditions for Linked CFst Faults..........................................55 Table 3.1: Generated March Tests for Unlinked Faults............................................ 6 8 Table 3.2: Fault Coverage of Generated Tests.......................................................... 6 8 Table 3.3: Conditions for Unlinked Fault Detection in Unidirectional Memories 73 Table 3.4: Generated March Tests for Unidirectional Memories.............................. 75 Table 3.5: Fault Coverage of Tests Generated for Unidirectional Memories........... 75 Table 3.6: Conditions for Fault Detection in Queues................................................76 Table 3.7: Generated March Tests for Queues.......................................................... 79 Table 3.8: Fault Coverage of Tests Generated for Queues....................................... 79 Table 3.9: Conditions for fault detection in stacks...................................................81 Table 3.10: Generated March Tests for Stacks......................................................... 81 Table 3.11: The Representation of a Two-cell Fault-Free Memory.......................... 83 Table 3.12: A Two-cell Memory with <T; I>y CFin Fault....................................... 83 Table 3.13: Drawbacks of Goor’s and Kamran’s Methodologies............................. 87 V Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. List of Figures Figure 1.1: Address Decoder Faults.............................................................................3 Figure 1.2: Interacting Faults...................................................................................... 7 Figure 1.3: Linked CFin Faults................................................................................... 7 Figure 1.4: A March Test...........................................................................................10 Figure 1.5: Fault/Not Detectable by March Tests.....................................................10 Figure 1.6: March C and March C- Tests for Unlinked Classical Faults................... 11 Figure 1.7: March B and March M Tests for Linked Faults......................................12 Figure 1.8: A March Test Wrongly Generated for Detecting CFin Faults................. 12 Figure 1.9: A March Test that Detects CFid but not <T, |> CFin Faults................... 12 Figure 2.1: Possible Directions for Ml and M2.........................................................25 Figure 2.2: Interaction Unlinked Types......................................................................34 Figure 2.3: Linked Faults.......................................................................................... 36 Figure 2.4: The U and D2 faults................................................................................. 37 Figure 2.5: Equivalence of AF4 fault to the U fault.................................................. 41 Figure 2.6: Equivalent linked CFin faults discussed in Lemma 2.3...........................42 Figure 2.7: Equivalent linked CFin faults discussed in Lemma 2.4...........................42 Figure 2.8: The Model for Linked CFin Faults......................................................... 44 Figure 2.9: Instance of Linked CFin Faults and All its Necessary and Sufficient Conditions.............................................................................................. 44 Figure 2.10: All Possible Linked and Unlinked CFid Faults Combinations..............45 Figure 2.11: Linked CFid Faults and Necessary and Sufficient Condition for Their Detection......................................................................................45 Figure 2.12: Example of a U element with the corresponding dominated class of faults ..50 Figure 2.13: Two of six undetectable U elements..................................................... 51 Figure 2.14: The D class and the D2 class that dominates it..................................... 51 Figure 2.15: Example of a D2 element with the corresponding dominated class of faults..................................................................................................... 51 Figure 2.16: Fully undetectable classes of faults....................................................... 51 Figure 2.17: An element and a subclass of the Ni class............................................ 52 Figure 2.18: The N2 and N3 classes........................................................................... 53 Figure 2.19: The intersection of N| and N2 classes (the Ni, 2 class)...........................53 Figure 3.1: Test Generation Tree for CFst Faults......................................................... 65 Figure 3.2: March Test for All Linked Classical and Extended Fault Models...........70 Figure 3.3: March Test for Linked Faults in Unidirectional Memories.....................74 Figure 3.4: Empty, Half-full and Full Circular Queues............................................. 76 Figure 3.5: Empty, Half-full and Full Stacks.............................................................81 Figure 3.6: A March Test Wrongly Generated for Detecting CFin Faults.................84 vi Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. List of Figures (Cont.) Figure 3.7: A March Test that Detects CFid but not <T, t> CFin Faults.................. 84 Figure 3.8: Possible Transitions for Detecting CFin Faults.......................................85 Figure 3.9: March M Test.......................................................................................... 85 Figure 4.1: Direct Mapped Cache............................................................................. 91 Figure 4.2: Two-Way Set Associative Cache............................................................ 93 Figure 4.3: Uncovered Address Decoder Fault........................................................120 1 vii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Abstract Memory systems exist in every computer system, making it important to test them in order to ensure the correct functionality of computer systems. Memories are used in different forms such as caches, main memories, buffers and unidirectional memories. Memories are used in different environments, where each environment imposes different constraints on the manner in which memory can be accessed. Every implementation and every environment requires different techniques to test the memory due to the nature of these constraints. March tests are commonly used for testing memories. They are well known for their high fault coverage and low time complexity. We present new methodologies to generate optimal march tests. Optimality of march tests can be defined in terms of their length and uniformity. Such features in march tests are desirable to lower test time and the complexity of the design of built-in self-test (BIST) circuitry. We have developed a methodology for a number of common fault models and we have generated optimal march tests for those fault models. The methodology depends on generating necessary and sufficient conditions for fault detection, and using the properties of march tests to generate the optimal tests using a branch-and-bound search tree. Constrained memories are tested using a subset of the detection conditions that do not violate the memory constraints. viii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. We also present a new methodology for testing cache memories. Our new methodology provides a 60.6% reduction in time complexity compared with previously published methodologies. We have developed a transformation that benefits from the cache design features in order to lower the time complexity. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 1 1 Introduction Memory systems exist in every computer system, making it important to test them in order to ensure the correct functionality of computer systems. Memories are used in different forms such as caches, main memories, buffers, and unidirectional memories. Memories are used in different environments, where each environment may impose different constraints on the manner in which these locations may be accessed. For example, in a multiple core system, memory modules can not be directly accessed from chip I/O, making it necessary to access the memory through other cores or via scan chains [9,19,28]. March tests are one type of memory tests [42]. They have specific structure, and are proven to be efficient since they provide high fault coverage and have low time complexity. Different march tests have been published [6 , 20, 23, 35,41,45,46]. The main objective in generating march tests is to generate more effective ones for the desired fault coverage. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1.1 Fault Model Technically, it is impossible to coverall types of faults [6 ]. However, there are common faults that are frequently found in defective memories. Such faults are represented using a fault model. The fault models that we will be discussing fall in three categories: classical fault models, extended fault models and open fault models. 1.1.1 Classical Fault Models Classical fault models include faults that are commonly considered. Nearly all march tests are designed to cover some subsets of these faults. Experiments have shown the validity of these fault models, meaning that they are found in real memory modules [61. 1. Stuck-at faults'. A memory cell i has a value 0 (SA-0) or 1 (SA-1) that never changes. 2. Transition faults: A memory cell i accepts a transition in one direction but not in the other, unless the transition is caused by a coupling fault with another cell and not by a write operation at cell i. It can be of the following types. a. T transition fault - the memory cell changes from 1 to 0 but not from 0 to 1 . b. 1 transition fault ~ the memory cell changes from 0 to 1 but not from 1 to 0 . 2 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3. Coupling faults [23,41]: A transition due to a write operation in one memory cell (coupling cell), affects the value of another memory cell (coupled cell). For simplicity, we denote a coupling cell by i and a coupled cell by j in the rest of this dissertation. Coupling faults are of two types: a. Inversion coupling faults (CFin): A transition in one memory cell inverts the value of another memory cell. For example, <T, £> denotes a coupling fault where a high transition in the coupling cell i inverts the value of the coupled cell j. The fault < i, t> can be defined in a similar manner. b. Idempotent coupling faults (CFid): A transition in one memory cell forces another memory cell to have a certain value. For example, <T, 0 > denotes a fault where a high transition in cell i forces the value of cell j to 0. Faults, < i, 0>, <T,1>, and <1,1> can be defined similarly. 4. Address decoder faults [23, 35,41]: The decoder used to select a memory cell has a fault that causes it to malfunction. We consider four types of address decoder (AD) faults shown in Figure 1.1. a — 1 1 — Ca AF1 AF2 AF3 AF4 Figure 1.1: Address Decoder Faults 3 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. In this figure, — ► indicates that the address points to the particular location, —I indicates that the address does not point to any location and I — indicates that no address points to the location. When an address does not point to any location, then accessing that address causes a fixed value, which could be either 0 or 1, to be returned. When an address { 3 points to two locations, then the returned value is unknown; in some cases, the returned value may be the result of the ORing or ANDing of the data in the two locations. In the following, we will not rely on the observation of such returned values for fault detection. We call the cell that excites a fault, the excitation cell, and the one that receives the fault’s effect as the observation cell or the victim cell. We also categorize faults as single cell faults, where only one cell is involved, and multiple cell faults, where multiple cells are involved. S A faults are examples of the single cell faults, while coupling faults are multiple cell faults. In the case of the single cell faults, the excitation cell is same as the observation cell, while the excitation and the observation cells are called the coupling and coupled cells, respectively, in case of coupling faults. Address decoder faults AF1 and AF2 are equivalent to SA faults, meaning that they behave like SA faults and can be detected by any test that detects SA faults. Hence, AF1 and AF2 can be viewed as single cell faults. In contrast, AF3 and AF4 are viewed as multiple cell faults since they act like coupling faults where the value written at cell (3 also appears at cell a. 4 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1.1.2 Extended Fault Model We also consider the following less frequently studied faults. 1. Stuck-open fault (SOF) [42]: It denotes a fault where a memory cell i is inaccessible due to an open word line. In this case, the returned value is same as the last value read in the corresponding bit column. 2. Data retention fault (DRF) [42,46]: It denotes a fault where a cell i fails to retain its logic value after some period of time. 3. State coupling faults (CFst) [6 ]: A coupled cell j is forced to a value v (0 or 1 ) only if a coupling cell i has a certain value (0 or 1). For example, <0, 1> means that the coupled cell j is forced to 1 when the coupling cell i has 0 . <0 , 0 >, <1, 0 > and < 1, 1> are defined in a similar fashion. 4. Disturb coupling fault (CFds) [46]: It is a coupling fault where the coupled cell is disturbed (makes a transition) due to a read or a write operation at the coupling cell. It could be CFds-r which include <ri), 0>, <r0,1>, <rl, 0> and <rl, l>, or CFds-w which include <w0,0>, <w0,1>, <wl, 0> and <wl, 1>. An example for this fault is <w0 , 1>, meaning that a write with value 0 at coupling cell i forces a 1 at coupled cell j. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1.13 General Fault Model March tests are capable of detecting all the faults discussed above as well as many other types of faults. However, we concentrate upon the aforementioned faults since they are considered common. It is possible, however, that other fault models will be considered in the future. Due to their structure, march tests cannot detect some types of faults. The following is the list of faults they can not detect. 1. Faults that involve more than one exciting cell, meaning that they can not be excited by a single cell, and require different values at the exciting cells. (This is different than interacting cells that we will discuss shortly.) 2. Faults that cancel the effect of each other due to the properties of march tests, as will discussed in the linked faults section. This general fault model goes beyond all faults mentioned in the above subsections to include all faults that can possibly be detected by march tests. This fault model is a target for future research and beyond the scope of this dissertation. 1.2 Interacting Faults A set of faults are said to be independent if no subset of faults affects the excitation and the observation of one of the other faults in the set. In contrast, faults may interact 6 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. through their exciting and observing cells. Figure 1.2 shows some possible ways for fault interaction. When faults interact through the observing cells, they are called linked faults [43,44], otherwise they are called unlinkedfaults. Linked faults need special care since they may mask each other, meaning that one of them may remove the effect of the other. Figure 1.3 shows a scenario where two CFin faults mask each other. They mask each other because cell a is visited causing inversion at cell y, but when cell P is visited, it inverts the value of cell y for a second time, causing cell y to contain the correct value. It is proven in [41] that an even number of the same type of linked CFin faults with coupling cells located at one side of the coupled cell, where all coupling cells are located on the left or the right of the coupled cell, can not be detected using march tests. This is an example of the second type of faults mentioned in the general fault model that cannot be detected using march tests. <T; 0> <?; 0> a P ' Ca" Cy----- <T; 1> i p V t iL <T;1>I i i <T; 1> a P y a P y (a) AF4 linked with <T; 1> (b) <T; 1> linked with <T; 0> (c) <T; l> interacting with <T ; 0> Figure 1.2: Interacting Faults < t:t> I . f <T; t > 1 a P y Figure 1.3: Linked CFin Faults Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Interacting faults that are not linked cannot mask each other; at least one of them is always not masked. In Figure 1.2(c), we see that <T; 1> is not affected by other faults since no other fault affects its exciting or observing cells. More details on this issue will be presented in Chapter 2. 1.3 March Tests March tests are proven to be efficient since they have high fault coverage and low time complexity [42]. In this section, we will discuss the structure and properties of march tests [25,48]. After that, we will discuss some of the published march tests. 1.3.1 Properties of March Tests Notation: • w O is used to denote write 0 to the memory cell under test, wl can be similarly defined. • wd is used to denote wO or wl. wd! is writing the complement o f d. • rO is used to denote read data from the cell under test, expect the value 0. rl can be similarly defined. • A march element is a set of consecutive operations that are performed on one memory cell before moving to the next one, such as 1t(i0, wl). In all tests, we will Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. name the march elements as M O, Ml, M2, and so on. A read-only march element consists of a single read operation like ft(rO) or ft(rl). • ft is the direction of a march element and indicates some arbitrary but fixed order of traversing all memory cells exactly once, ft indicates a traversal of all memory cells in an order that is opposite of that for ft. < = > indicates a traversal of all memory cells in either of the above two orders. A march test is a finite sequence of march elements [35]. A march test is said to be redundant for a desired fault coverage if a test obtained by removing one or more operations from the test also provides the desired fault coverage. A march test is said to be uniform if each of its march elements has the same number of operations. The following are march tests properties when considering the classical and extended fault models: PI. March elements are applied on memory cells in order. This makes it impossible to visit a cell twice during the application of a single march element. (Note that when a cell a is visited, multiple operations may be applied at a. However, a is visited only once by a march element). P2. A read has the same value as the preceding write operation. P3. Inverting every data value in a march test produces a test whose fault coverage is identical to the original test. Such tests are said to be equivalent [41]. P4. Inverting the direction of every march element produces an equivalent march test [41]. 9 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1t(wl, wO); tt(rO, w l); li(rl); U -(w O ); < = *(rO ) M O M l M2 M3 M4 Figure 1.4: A March Test I \ a P Y a = P when y is visited No way to have a = 0 and P = I (fault requirement) / can not be excited Figure 1.5: Fault/N ot Detectable by March Tests Based on the above notations and properties, Figure 1.4 shows a possible march test. March tests starting with a march element that contains more than one operation are not commonly considered. We will see later that ignoring such tests has prevented development of some optimal and many uniform tests. The fact that a march test visits memory cells in order and the same sequence of operations is applied to all memory cells prevents it from being able to detect faults with multiple exciting cells that are discussed in the general fault model. For example, consider a fault/defined in the following way: a 0 at cell a and 1 at cell P forces the value of cell y to be 1. Such a fault could exist among any three cells in the memory, and detecting it requires different values at cells a and P, as illustrated in Figure 1.5. Such a fault can be detected only if y is located between cells a and P, in Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. the order in which the ceils are accessed. Since there is a constraint on the test order, a march test can be used but should be applied several times with different orders. Such faults are beyond the scope of this research, since we are focusing on march tests of order 0(N), where N is the number of memory locations. 1.3.2 Known March Tests Based on the needed fault coverage, several march tests have been developed. The most powerful march test for unlinked faults is named March C-. It covers all unlinked (or simple) classical faults. March C- is a reduced version of March C. March C and March C- are shown in Figure 1.6. Many other tests have been developed to cover different combinations of linked faults. The most popular one is the March B test Another test, which was claimed to provide higher fault coverage with lower time complexity, is the March M test [22]. Both tests are shown in Figure 1.7. Other tests with different fault coverages are also published. As we have mentioned, almost all published tests start with a single-operation march element M O . «=*(w 0 ); T T (rO , wl); I T (rl, wO); < = > (rO ); Ji(iO, wl); Ti(rl, w O ); Ji(rO) M O Ml M2 M3 M4 M5 M6 (a) March C Test «= > (w 0 ); T T (rO , wl); I T (rl, wO); -U (rO , wl); U(rl, wO); < = > (r 0 ) M O Ml M2 M3 M4 M5 (b) March C- Test Figure 1.6: March C and March C- Tests for Unlinked Classical Faults Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. < = > (w O ); lt(iO, wl, rl, wO, iO, wl); 1 1 (rl, wO, wl); U(iO, wl, wO, wl); li(rl, wO, wl) M O Ml M2 M3 M4 March B Test < = > (w O ); 1t(rO , wl, rl, w O ); < = > (rO ); T T ( r O , wl); « (rl); T T (rl, w O , rO , wl); « (rl); -U(rl, w O ) MO Ml M2 M3 M4 M5 M6 M7 March M Test Figure 1.7: March B and March M Tests for Linked Faults 1.4 Motivation As we have seen in the previous section, several march tests have been developed to cover different combinations of faults. However, there are many other combinations of faults for which no customized test exists. For example, the shortest available test for testing CFst faults is March C-, which is a ION test that is capable of detecting many other faults. It is quiet possible that a shorter test can be developed if CFst faults are the only target faults. <=>(w 0); lT (rO , wl, wO, w l, wO); < = *(rO ), MO Ml M2 Figure 1.8: A March Test Wrongly Generated for Detecting CFin Faults <=>(w0); 1t(iO, w l, wO, w l); 1t(rl, wO, w l, wO, w l, wO); tT (rO , w l, wO, w l), M O Ml M2 M3 Figure 1.9: A March Test that Detects CFid but not <T, t> CFin Faults 12 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The currently used march tests are not proven to be optimal, making it possible to discover other more efficient alternatives. Finding more efficient tests is the main goal for every researcher in memory testing since they reduce the cost of manufacturing memories, and hence increase the profit. Proving the optimality of tests is important since it eliminates the need for searching for more efficient alternatives. Earlier methodologies to generate optimal march tests have major flaws. The methodology published in [51] and [52] generates incomplete tests. Figure 1.8 shows a test that was generated to detect CFin faults while it actually fails to detect any of them. The other methodology presented in [58] claimed that detecting CFid faults guarantees the detection of CFin faults. Figure 1.9 shows a test that is capable of detecting CFid faults but not CFin faults. Some of the older tests have been proven to be incomplete and/or redundant, such as March C, which has been recently proven to be redundant [41]. Since it is not feasible to manually prove the completeness of march tests, three main methodologies for automatic test verification were published [29,38, 56]. The methodology presented in [38] wrongly passed incomplete tests, such as the tests presented in [52] for CFin faults. Other two methodologies presented in [56] and [29] use the approach of memory simulation with high time complexity of 0(N3 ), where N is the size of the simulated memory. All published methodologies for Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. automatic test verification were implemented for unlinked faults only, leaving the important tests that deal with linked faults unverified. 1.5 Problem Definition One objective of this research is to automatically generate optimal march tests for unconstrained and some types of constrained memories for any given set of target faults. Recall that constrained memories place restrictions on the way in which their locations can be accessed, such as only accessing their locations in a certain order. Optimal tests are tests that give us the most benefit in terms of a specific feature. An optimal test is the shortest test that covers specific faults with lowest time complexity when an external tester is used, since the main cost in such tests is the time required to test the memory. However, an optimal test for built-in self-test (BIST) designs is a uniform test even if it is not optimal in terms of time complexity. A uniform test reduces the hardware overhead required for decoding the number of operations in each march element. Our research goes beyond traditional constrained memories to cover embedded and cache memories. Embedded memories are unique in the sense that they can be accessed only through scan chains. Caches differ from other constrained memories in the sense that march tests must be transformed in order to apply them to the tag and data parts of a cache. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Another objective is to present a methodology that automatically determines whether a given test is complete and irredundant. Such a methodology should not be limited to unlinked faults, and its time complexity should be reasonable in order to produce results for linked faults. 1.6 Dissertation Overview Our research will cover both classical and extended fault models as single and linked faults. Our new approach for generating and verifying march tests will serve as a starting point for handling future fault models, and ultimately the general fault model. We will discuss the necessary and sufficient conditions for detecting unlinked and linked memory faults in Chapter 2. Memory faults are analyzed and a theorem and a procedure are presented for generating the required conditions for unlinked faults. Other theorems that use fault dominance are used to generate the conditions for linked faults. These conditions constitute the key representation behind our approach. They have the same format as march tests. They are used to generate march tests as well as for test verification. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 3 presents procedures for test generation. It covers unlinked faults in the extended fault model and linked faults in the classical fault model. We prove the optimality of some known march tests for the first time. We also generate optimal tests that are more powerful than the known tests. In addition, this chapter discusses several constrained memory structures, including unidirectional memories, stacks, queues and embedded memories. Techniques for overcoming the constraints in the procedure for accessing the contents of these memories are also discussed. Based on the constraints, different versions of the necessary and sufficient conditions are generated. Optimal march tests are then generated for these types of memories. In Chapter 4, we present a methodology to transform march tests for testing caches. The main problem in testing caches is applying memory tests on cache tags, which are not accessible directly. The transformation transforms original tests to new tests that are capable of testing cache tags with the same fault coverage as the original tests. The transformation benefits from the cache structure to reduce the time complexity of transformed tests. The transformation is proven to be much more powerful than previously published transformations. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 2 2 Condition Generation for Fault Detection Our methodology for generating march tests starts by generating the necessary and sufficient conditions for detection of each type of faults. We have developed a representation for unlinked memory faults, techniques to identify the conditions for their detection, and efficient ways to represent the conditions. The conditions are developed to take advantage of the properties of march tests. A different approach is used for linked faults. In this chapter, we first describe our approach to generate conditions for detection of unlinked faults. After that, we present a different approach to that successfully deals with linked faults. The results of this chapter are sets of conditions for detecting unlinked and linked faults. These conditions are used as input for the test generation algorithm, which will be presented in the next chapter. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2.1 Fault Representation In order to generate necessary and sufficient conditions for detecting memory faults, we need a representation for the faults. A detailed fault representation (DFR) is generated for every fault based on its properties, such as the faulty value, which is the value forced by the fault that differs from the correct value, and the excitation requirements. Two DFRs are used to represent faults with two faulty values. For example, < T, t> has two faulty values 0 and 1, hence we consider a DFR for each faulty value. The DFRs are used to generate conditions for fault detection. In the case of faults with two DFRs, conditions generated for the two DFRs are combined, since detecting the fault through any of the two representations is sufficient. A fault is represented by its properties in a DFR as follows: - Type of the fault: Single or multiple cell fault. - Faulty value associated with the fault: 0 or 1. - Excitation method: setting the value of a memory location to 0 (C = 0), setting it to I (C = 1), T transition, 1 transition, a read operation rt), rl, a write operation wO, wl or delay. - Other DFRs, if any. • If a multiple cell fault is excited by a transition, then whether the number of transitions is relevant or not. If relevant, the procedure for generating conditions must ensure satisfaction of the required condition. 18 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 2.1: DFRs for SA, SOF, DRF, TF, CFin and CFid Faults. Fault Detailed Fault Representation (DFR) Type Faulty Value Other DFRs Excitation Constraint on # of transitions SA-0 Single cell 0 None C = l — SA-I Single cell 1 None n n o — SOF Multiple cell 0 Next row o I I 0 — SOF Multiple cell I Previous row G = 1 — DR-0 Single cell 0 None Delay — DR-1 Single cell 1 None Delay — T t f Single cell 0 None C = T ---- 4 TF Single cell I None C = 4 — <T.!> Multiple cell 0 Next row C = T Odd <T.I> Multiple cell 1 Previous row C = T Odd <4. t> Multiple cell 0 Next row r . = 4 Odd <4. t> Multiple cell 1 Previous row G = 4 Odd <T. o> Multiple cell 0 None g = t None <T, i> Multiple cell 1 None g = t None < 4,0> Multiple cell 0 None G = 4 None <4. i> Multiple cell 1 None G = 4 None Table 2.2: DFRs for CFst, CFds and AD Faults. Fault Detailed Fault Retncsentation (DFR) Type Faulty Value Other DFRs Excitation Constraint on # o f Transitions <0,0> Multiple cell 0 None C, = 0 --- <0.l> Multiple ceil I None C. = 0 --- <I.0> Multiple cell 0 None C, = 1 --- < I,l> Multiple cell 1 None G = 1 --- <r0,0> Multiple cell 0 None C, = rO --- <rO,I> Multiple cell 1 None G = tO ---- <rl.O> Multiple cell 0 None G = rl --- < rl.l> Multiple cell I None G = rl --- <w0,0> Multiple cell 0 None G = wO --- <wO.I> Multiple cell 1 None G = wO --- <wl,0> Multiple cell 0 None G = w l --- < w l,l> Multiple cell 1 None C. = wl --- — A S — AF1 Single cell ------- 8------- 1 Previous row C - l -------- c = o --- — AF2 AF2 -Multiple cell Multiple cell ---------- 8---------- 1 — Next ton— Previous row ----- e = - i ------ c = o ---- <AF3> -Multiple cell Multiple cell ---------- 8---------- 1 — Next row Previous row — e r = « ----- C, = 1 --- <AF4> Multiple cell Multiple cell ---------- 8---------- 1 — Next row Previous row — er=-®— G = 1 --- Tables 2.1 and 2.2 show all the DFRs generated for the classical and extended fault models. In the tables, we use the following notations: Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. • The letter i, in Q, refers to the coupling cell. • C = d means that set the value o f a cell to d. • C = T means make a high transition at the memory cell. C = i can be defined in a similar manner. Our representation depends on representing the behavior of memory cells. Faults in other parts of the memory are represented by their effect on the behavior of memory cells. In SOF, a read operation at the victim cell returns the last value read from any other cell in the same column as the victim cell. Hence, its appearance is like a multiple cell fault where a read operation returning data value d in a coupling cell forces the value of the coupled cell to be stuck at the value d. AD faults are equivalent to <T, 1> linked with <1, 0> CFid faults. So both SAO and AD faults are considered multiple cell faults. 2.2 Requirements for Fault Detection When considering memory faults, we always use the following three main steps: Initialisation; Set the victim cell to a value that differs from a faulty value of the fault. Excitation: Excite the fault by satisfying the excitation condition. Observation: Read the victim cell. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. We present here two lemmas and a theorem that prove some properties of march tests and faults detection conditions. Theorem 2.1 shows that at most two consecutive march elements are necessary and sufficient for detecting any multiple cell fault. This justifies limiting our study to the behavior of only two consecutive march elements. Lemma 2.1: Adding read operations, including read-only march elements, does not reduce the fault coverage of march tests that target unlinked faults. Proof: The fault coverage is reduced if some faults mask each other. Since we are discussing unlinked faults, adding read operations may not mask faults not excited by read operations. So assume that we added a read operation that excites a CFds-r fault, which is the only type of faults excited by read operations. Such an operation would target a cell that is not a victim of any other fault. If there is already another read operation in the original test that excites the fault, then having two reads exciting it will not mask each other since the number of exciting reads is irrelevant when dealing with CFds-r faults. ■ Lemma 2.2: State coupling faults can be detected by one or two consecutive march elements. Any sequence of more than two march elements that detects a state coupling fault contains one march element or a subsequence of two consecutive Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. march elements that can detect the fault. (In general, the two march elements may be separated by one or more read-only march elements. However, these read-only elements can be removed without affecting the detection of the target fault.) Theorem 2.1: It is impossible for a single march element to detect a multiple cell fault, except CFst faults. Any sequence of more than two march elements that detects a multiple cell fault contains a subsequence of two consecutive march elements that can detect the fault, except CFst, which can be also detected by a single march element. (In general, the two march elements may be separated by one or more read only march elements. However, these elements can be removed without affecting the detection of the target fault.) Proof: Lemma 2.2 deals with the case of CFst faults. Hence, in this proof, we only consider the rest of faults. Due to the structure of march tests, a single march element can not satisfy the three requirements for fault detection since it can not operate on the coupled cell j, then the coupling cell i, then j again (Property PI in subsection 3.1). The exception of CFst is already discussed. This proves the first part of the theorem. Assume we have three march elements, Ml, M2 and M3, that are required to satisfy the three requirements for fault detection. First consider the case where M2 is not a read-only march element. Since initialization and observation for fault detection each Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. require one operation, namely a write operation for initialization and a read operation for observation, each of these operations can not be spread over more than a single march element. Hence, of the three march elements. Ml would be for initialization and M3 for observation. We have the following possible cases. 1. Excitation requires a write operation: Now we will demonstrate that the excitation cannot occur in a separate march element M2. First consider the case where, in M2, the coupled cell j is visited after the coupling cell i. Excitation requires a write operation at cell i. Due to the structure of march tests, the same write operation must also be applied at j before the end of M2. This would overwrite the fault effect created when the write operation was performed on cell i, before the end of M2. Hence, the read operation in M3, which is intended for observation, will not detect the fault. Next consider the only other possibility that cell j is visited before cell i. In this case the write operation that is to be performed on cell i for fault excitation will first be performed on cell j. This will overwrite any value written in cell j during the initialization march element Ml. 2. Excitation requires a read operation only: In this case, it is possible that M2 is a read-only march element. The other case, when M2 contains a write operation, is already covered above. If M2 contains a read operation that does not excite the fault, then M2 can be removed since it serves no purpose in detecting the fault. If M2 excites the fault, then it also observes with the condition that its direction is 23 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. changed such that it visits the coupling cell first then the coupled cell. Hence, M3 can be removed since M2 excites and observes the fault. From 1 and 2 above, we conclude that only two march elements are required and that excitation should be combined with either initialization or observation in one march element as follows: (a) Ml initializes and excites the fault effect, and M2 observes the fault effect; or, (b) Ml initializes, and M2 excites the fault effect and observes it. We can see that the above two ways are the only ways to satisfy the requirements for fault detection since they are the only ways to keep the required steps in order. The above proof can be extended to the case of a sequence of more than three march elements that detect a fault. In this case, there must be two march elements Ml and M2, possibly separated by read-only march elements, that detect the fault. ■ From this point onwards, to simplify the discussion, we will mainly discuss the case when the coupling cell i has an address less than the coupled cell j. Similar arguments can be applied to the case when i > j. Also, we will ignore the fact that read-only march elements can be added between M l and M2 that are required for detecting a certain fault. 24 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Ml M2 Ml M2 Ml M2 Ml M2 t i ♦ ♦ | | ! ♦ 1 1 1 1 ! ♦ 0 © t ; 0 © ♦ ♦ 1 1 ; : 0 0 : t 1 1 t ♦ 0 © 1 1 1 1 © 6 t i 6 6 ♦ ♦ i i 6 6 1 t 6 6 i i i i i i i * ♦ ! i i ♦ ♦ Case 1 Case 2 Case 3 Case 4 Figure 2.1: Possible Directions for M l and M2 Table 23: Possible Usage of M l and M2 from Figure 2.1 for Fault Detection Initialization Excitation Observation Notes Case 1 Ml M2 None Useless for fault detection since no way to observe the fault effect. Case 2 Ml M2 M2 No other choice, since i is visited only once (in M2) between the two visits to j. Case 3 Ml M2 M2 Two choices, since i is visited twice (in Ml and M2) between the two visits to j. We have the choice of using either the first or the second visit to i for excitation. Ml Ml M2 Case 4 Ml Ml M2 No other choice, since i is visited only once (in Ml) between the two visits to j. The directions of two consecutive march elements, Ml and M2, can take one of four possible combinations as shown in Figure 2.1. In Table 2.3, we list the ways in which we can use Ml and M2 for detecting a multiple cell fault, when two march elements are needed. The four cases shown in Figure 2.1 are discussed. The cases when only one march element is sufficient for detecting a fault are relatively simple, and hence directly dealt with in the procedure presented in the next section. Notice that a single march element is sufficient only for some types of CFst faults. 25 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2.3 The Procedure for Generating Conditions for Unlinked Faults’ Detection Using the above three steps required for fault detection, along with the aforementioned properties of march tests and faults, the task of generating the conditions is done by the following procedure. The procedure uses as input the DFR representation discussed in the previous section. It generates all possible conditions for detection of each DFR, and thus for each fault. Notice that in multiple cell faults, excitation consists of all operations that change the value of the coupling cell I, after visiting j for initialization and before observation. Also, a march element that starts with a write operation does not guarantee the number of transitions occurring at the coupling cell, since the value of a cell before applying a march element on it is considered unknown since a fault could have altered it. 2.3.1 The Procedure 1 . If the DFR represents a single cell fault, then the condition consists of write operations that satisfy the excitation requirement, followed by a read operation to observe the fault effect. Example: T transition fault will be detected by w O , wl, rl. 2. If the DFR represents a multiple cell fault, then we need to study the four possible combinations of Ml and M2 discussed in Table 2.3. We have the following possibilities: 26 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. a. Ml and M2 have the direction shown in Case 2 in Figure 2.1. This requires the following steps: i. Make Ml end with wd (d=0 or 1), where d is the desired value for initializing j. ii. Set the first read in M2 to expected value d. iii. Write the rest of the march element M2 to satisfy the excitation requirements. b. Ml and M2 have the direction shown in Case 3 in Figure 2.1. First consider the scenario where Ml satisfies the conditions for initialization while M2 satisfies the conditions for excitation and observation. This requires the following steps: i. Make Ml end with wd (d = 0 or 1), where d is the desired value for initializing j. ii. Set the first read in M2 to expected value d. iii. Write the rest of the march element M2 to satisfy the excitation requirements. iv. Make sure that the operation of Ml on cell i does not invalidate the excitation accomplished in M2. If Ml starts with a write operation, then the number of transitions it makes at cell i is unknown. c. Ml and M2 have the direction shown in Case 3 in Figure 2.1. This time consider the other scenario where M l covers the initialization and excitation while M2 covers the observation only. This requires the following steps: i. Write Ml such that it satisfies the excitation requirements. If Ml starts with a write operation, then the number of transitions it makes on cell i is unknown. ii. Make Ml end with wd (d = 0 or 1), where d is the desired value for initializing j. Note: If it is impossible to satisfy either of the above conditions, then it is impossible to use this combination for detecting the fault 27 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. iii.Set the first read in M2 to expect value d, with no restriction to the rest of M2. iv.Make sure that the operation of M2 on cell i does not invalidate the excitation accomplished in Ml. d. Ml and M2 have the direction shown in Case 4 in Figure 2.1. We have Ml covering the initialization and excitation while M2 covers the observation only. This requires the following steps: i. Write Ml such that it satisfies the excitation requirements. If Ml starts with a write operation, then the number of transitions it makes on cell i is unknown. ii. Make Ml end with wd (d = 0 or 1), where d is the desired value for initializing j. Note: If it is impossible to satisfy both of the above steps, then it is impossible to use this combination for detecting the fault iii.Set the first read in M2 to the expected value d, with no restriction to the rest of it. 3. For CFst, generate single march elements that are capable of detecting these faults by: i. The march element should end with the exciting value. ii. It should contain rx where x is the faulty value. iii. It should visit i then j. 4. Combine the conditions of all DFRs used to represent a single fault in one set. For example, assume we are targeting <T , 0>jj coupling fault. Based on the above procedure, we should be able to generate four conditions for fault detection. By 28 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. applying part 2(a) of the above procedure, we get f f ( w l); ft(rl, wO, wl,...). Part 2(b) of the above procedure gives l i ( wl); 1T(rl, w O , wl,...); part 2(c) of the above procedure gives Ji(..., opO, wl); lt(rl,...); and part 2(d) of the above procedure gives li(..., opO, w l); U(rl,...). These four conditions can be combined in two conditions as shown in Table 2.4. Note that in the resulting conditions, read operations can be added between any two consecutive operations. Also, any number of read-only march elements can be added between the march elements. 2.3.2 Special Cases Among the cases discussed in Table 2.3, the above procedure automatically deals successfully with the following special cases. Spl. Case 3 involves two march elements applied to the coupling cell for excitation. In 2(b) and 2(c) above, the procedure ensures that the operations on the coupling cell i, applied during Ml and M2, still constitute valid excitation. Example: When we are dealing with CFin, the case of Ml and M2 having odd number of transitions is avoided in 2(b) and 2(c), since in that case the fault would not be excited. Sp2. Part 2(d) above deals with the case when Ml cannot be used for initialization and excitation due to a conflict in their requirements. 29 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Example: In some faults, initialization requires that Ml ends with wd, while the excitation requires that Ml ends with wd!. This is the case with AD faults AF3 and AF4. Sp3. A march element that starts with a write operation does not detect any multiple cell fault, and transitions resulting from the first operation are not guaranteed since the value of a cell is unknown due to a possibly faulty value. Example: When dealing with <T, t> CFin, the number of T transitions in li(w l,..., wl) is unknown since a cell could contain 0 or 1 before the application of the march element. Table 2.4 shows the conditions for detection of each fault generated by applying the above procedure on SA, TF, SOF, DRF, AD, CFid, CFin, CFst and CFds faults. In the table, we see the two different ways in which conditions are represented: (a) without parentheses, which indicates that the operations could fall in one or more march elements; and (b) with parentheses, which indicates that the operations should be in one or more march elements as specified by the parentheses. We also used the following notations: • The letters i and j next to a coupling fault denote the coupling cell i and coupled cell j, where ij means i is visited before j when the direction of a march element is 1 t, and vise versa. • U(!wl,...) means that the march element is not starting with wl. 30 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. • opO means rO or wO, and opl means rl or wl. • <AF3> y denotes AF3 fault where i corresponds to fJ and j corresponds to a in Figure 1.1. Recall that any number of read operations can be added between the operations in these conditions. Also, read-only march elements can be added between any two march elements. That comes from the fact that we are dealing with unlinked faults at this point, so adding more read operations does not cause fault masking. 2.3.3 Analysis of Resulting Conditions In Table 2.4, we do not see the different DFRs for faults with multiple DFRs since they are combined at Step 4 of the above procedure. We notice that AF3 and AF4 faults (rows 48 and 49) have only one method of detection. This is due to the fact that Ml could not be used for initialization and excitation due to conflict in their requirements. Such conditions fall in the special case category, Sp 2, above. The proposed methodology generates all alternative conditions for detecting each fault since it studies all possible ways for fault detection. Theorem 2.1 helps limit the analysis to only two consecutive march elements and helps reduce the number of alternative scenarios that are considered to obtain these conditions. The fact that all alternative conditions are covered guarantees the generation of all march tests needed 31 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 2.4: Conditions for Detection of Unlinked Faults Generated by the Procedure Described in Section 23 fau lt Type Conditions I SA-0 w l.rl 2 SA-l wO. tO 3 SOF <=»(.... tO....... r l . ...) OR r l ....... tO ....) 4 DR-0 « f . .. o o l) Delay « f r l_ _ ) 5 DR-1 «=»(.... ooO) Delay <=>(t0....) 6 t TF wO. w l. rl 7 i TF w l, wO. tO 8 <T. !>„ If (.... wd) T T (r d ,.... w l....) odd# o f wl in M2 OR lt(!wl......w l....... wd) Ik rd ,...) odd # o f wl in M l OR U (!w l...... wd); 1f(rd....) o d d # o fw l in (M l +M2) 9 <T, J>„ ll( .... wd) 8(rd...... w l ,...) odd # o f wl in M2 OR 1t(!wl......w l....... wd) ft(rd,...) o d d # o fw l in M l OR 1f(!wl......wd): Ikrd,...) odd# o f wl in (M l + M2) 10 < i. I>,, II (.... wd) U (r d ,.... wO,...) odd # o f wO in M2 OR Jk!wO,.... wO,.... wd) Ik rd ....) odd # o f wO in M l OR II (!w 0,.... wd); ft(rd,...) o d d # o fw O in (M I +M2) 1 1 Ik — > wd) U (rd..... wO,...) odd # o f wO in M2 OR tt(!wO......wO....... wd) 1t(rd,...) odd # o f wO in M l OR 1t(!w0,.... wd); ll(rd,...) odd # o f wO in (M 1 + M2) 12 <T, o>u <=»(.... w l) If(rl, wO, wl,...) OR Ik.... ooO. w l ) ; » ( r l_) 13 <T.o>,, «=»(..., w l) fk rl, wO, wl,...) OR ff(.... opO, w l ) ; « (rl....) 14 < f. l >,, <=»(.... wO) lf(iO, w l , ...) OR Ik.... ouO. w l. wO); <=»(i0,...) 15 <1', I s , <=»(.... wO) 8(10, w l ,...) OR Ik.... opO. w l. wO): <=>(t0....) 16 < i. o>„ <=»(.... w l) lk rl, wO,...) OR 8(.... o o l. wO. w l) ; ee(rl....) 17 < 1 ,0>p c » (.... w l) 8 (rl, wO,...) OR Ik.... o p l. wO. w l) ; <=>(rl....) 18 < i, 1>,, <=>(.... wO) U(tO, w l, wO,...) OR U(..„ o p l. wO): «=»(i0....) 19 < i. 1>, <=>(..., wO) 8(r0. w l, wO,...) OR Ik.... o o l. wO); <=»(i0,...) 20 < 0 ,0>,, H(...,opO.......wl)<=Krl,...) OR <=»(..., w l) ft(rl.......wO....) OR <=»(..., wO) U(iO.......w l, r l , ...) OR <=»(...) 1t(.... r l .......wO) 21 < o.o> , lf( -.o p O ....... w l) <=»(rl,...) OR « (..., w l)U (rl.......wO....) OR » (..., wO) ft(rO..... wl, r l , ...) OR «=»(...) Ik.... r l .......wO) 22 <0. 1>,, <=K. .. wO) <=KrO,...) OR « (...) U(..., tO.......wO) OR « (...) 1t(.... wO. tO) 23 <0. 1>, «=>(.... w O ),p(rO ,...) OR <=>(...) I k - . rO.......wO) OR «=>(...) I k - . w0.i0) 24 <1. o>„ «=»(.... w l) «=>(rl....) OR « (...) U(.... r l .......wl) OR e»(...)1t(.... w l.rl) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 fault Type < 1 .0 > » <1. !>., < 1 . I> j, Conditions « ( ..., w l)e*(rl....) OR <=»(...) Il(..., rl. ...,w l) OR <=*(...) Il(.... w l.rl) U(.... opl wO) <=H iO . — ) OR « (.... wO) 1t(rO.......w l....) OR « (..., wl) U (rl.......wO. tO,...) OR < =»(...) tO w l)________ <aO. 0>,, <i0,0>,, < i O , 1 > i, < i0 . l> » <rl. 0>,, < rl. l>„ <rl, l>r <w0,0 > i , <w0,0>p <w0, 1>,, <w0, l>f <wl, 0>i, <wl, 0>j, <wl, l>,. AF1 tf(.... opl wO) <=»(r0,...) OR <=>(.... wO) U(iO.......w l,...) OR <=»(..., wl) lf(rl.......wO, tO,...) ORes(...) Ik-. tO w l)_______ <=>(..., w l)tt(rl tO,...) OR H(— . tO w l) ; cXrl....) >(.... wl) U(rl f0 ....) OR I k - . rO w l) : <=»(rl.-) <=>(.... wO) ff(iO,...) OR fl(- tO. ....wO): < = X r O . . . . ) « ( .... wO) ■U(r0....) OR lt(— tO wO): t=>(tO....) cK .... wl) tT(rl....) OR Ik... r l w l) :<=Xrl..„) <=»(.... w l) U (rl,...) OR tk — r l w l):« = K rl.-) « ( .... wO) 1t(iO r l . ...) OR ll(.... r l wO): < = > (iO .— ) <=K.... wO) Il(r0,.... r l , ...) OR Ik -. r l wO): < = > (tO —) «=*(.... wl); 1f(rl wO,...) OR ■ U (.... w O wl): <=»(rl,...) « ( .... wl); 8 (rl wO,...) OR Ik— wO........wl): <=>(rl—) <=>(.... wO); 1f(rO wO,...) OR U(.... wO): < = »(rO — .) <=>(.... wO); 8(rO wO....) OR Ik— wO); <=>(iO....) <= K wl); 1t(rl w l....) OR <k-.wl);<=>(rl..~) «=>(.... wl); il<rl w l,...) OR wl); <=»(rl.— ) <=>(.... wO); 1f(r0 w l,...) OR lt(— . w l wO): <=>(tO ....) «=»(..., wO); U(iO w l,...) OR w l wO): <=»(t0,...) AF2 <AF3>„ <AF3>« <AF4>m <AF4>. wO.tOand w l. rl wO. tO and wl. rl <=>(.... wd) 1t(id wd!) OR <=>(.... wd) U(rd wd!) « = * ( .... wd) ff(rd wd!) OR <=>(.... wd) Ikrd wd!) »(.... wd) ff(rd wd!) e » (.... wd) li(rd wd!) 32 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. for detecting certain faults. Consequently, no desired test would be out of the search domain for march tests. The condition generation methodology works for the complete set of faults presented in the classical fault model or any subset thereof. For instance, when a manufacturer chooses a subset of the faults, the methodology can be used to produce conditionsrequired for detecting only that subset. This enables generation of custom tests that provide the desired coverage at minimal test cost. From studying the necessary and sufficient conditions presented in Table 2.4, we find that the structure of useful march elements, i.e., which could possibly satisfy at least one condition for excitation and/or observation, has the following properties. These properties are used to limit the search space for march tests, as we will see in the next chapter. MP1. Reads can be added to march elements shown in the above conditions without invalidating them. MP2. One of two read operations with the same data value in the same march element can be removed without affecting fault coverage. MP3. Internal reads in a march element, i.e., reads that are not at its beginning, should not be added unless SOF, CFst or CFds-r are not covered yet, since they are the only faults that include internal reads in the conditions for their detection. 33 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. MP4. If a march element contains two write operations with the same value, each one of them should cause a transition in a fault free memory, otherwise the one that does not cause a transition can be removed without affecting the fault coverage. MPS. Two consecutive march elements should not start with write operations. 2.4 Interacting Unlinked Faults Up to this point, we have successfully handled the case of independent faults. It is time now to consider interacting faults. As we mentioned in Chapter 1, there are two ways for faults to interact: through the coupling cell or the coupled cell. Linked faults are faults that interact through the coupled cell. Faults interacting through coupling cells are unlinked faults. Figure 2.2 shows two possible ways for unlinked faults to interact: open and cyclic interaction. J L A . a p y a P (a) Open interaction (b) Cyclic interaction Figure 2.2: Interaction Unlinked Types 34 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Theorem 2.2: Interacting unlinked faults do not mask each other. Proof: Interacting faults occur in one of the two forms shown in Figure 2.2. If the faults take the open interaction form, then one of them is independent since no other fault affects its excitation or observation cells. In Figure 2.2(a), we see that the fault// is independent. The second type of unlinked faults is the cyclic one, as shown in Figure 2.2(b). Let us consider the fault// in the figure. It is obvious that the observing cell fJ is not affected by any other fault. Hence, it is initialized correctly and it reflects the fault effect if cell a experiences the excitation requirements. The fault f 2 affects cell a, but it does not prevent it from experiencing the excitation effect. This is true since the excitation effect is a sequence of operations that cannot be masked by the fault/2, and it does not depend on the initial value of clH 2.5 Linked Faults In the previous sections, we covered unlinked faults. In this section we deal with linked classical and extended fault models using different approaches. Figure 2.3 shows the notation used for linked faults. In Figure 2.3, the coupling cell a/ affects the victim cell v with fault//, and so on. Any number of fault free cells may exist between any two memory cells shown in Figure 2.3. We do not show the 35 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. memory cells that are not involved in any fault since they are irrelevant to our discussion. We denote two linked faults// and fz byft # / . As we can see, the coupling cells for faults // to f m are located on the left side of the victim cell while the coupling cells for faults f m + i to ft are located on the right side of the victim cell. In the figure, the closest coupling cell with a CFid fault that is located on the left side is am .i. In order to excite that fault we need a march element that causes a 1 transition. For the fault to be detected after exciting the closest CFid on the left side, the excitation requirement for the closest CFid fault on the left side should be satisfied, and, at the time of excitation, the victim cell should have initial value that is different from the faulty value written to v as a result of the linked coupling faults. For example, the march element 1t(rl, wO) will detect the fault after exciting the closest CFid in the left side since it visits memory cells from left to right (ft direction), it excites the CFid fault (causes a I transition) and detects the fault (value 1 is expected at the victim cell while the fault causes the value to change to 0). In Figure 2.3, the coupling cells a/ and a„ are called the outer boundary coupling cells. We will be dealing with two types of coupling faults named the U and D2 faults. The U fault is a fault that occurs in an outer boundary coupling cell and is of the form <T, L> & < 1 ,0>, meaning that a T transition at the boundary cell sets the ft /»./= <A, 0> fm = <t*Z> fm + t fm • • • • • • 1 ----- 1 ------------I-----------JL ------1 - - - - 1 ------! — ► at O z < * ■ * • / °m < *«♦/ am Figure 2.3: Linked Faults 36 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. victim cell to 1 and a 1 transition at the boundary sets the victim cell to 0. It is not only the type of the coupling faults but also the location of the coupling cells that characterizes the U fault. Figure 2.4(a) shows a U fault linked with another fault. It can be shown that when a u cell is the last coupling cell visited after visiting the victim cell by a march element that causes one or more transitions, the victim cell v will have the fault-free value due to the U fault, assuming that the victim cell does not have SA fault. The D fault is a fault that occurs in the two closest coupling cells to the victim cell in a certain direction, where the further coupling cell (bom the victim cell) of the two has <T, 1> & <>l, 0> faults and the closer one has <1, t> coupling fault. The D2 fault has two D faults surrounding the victim cell. Figure 2.4(b) shows a victim cell with a D2 fault. In the presence of the D2 fault, any march element containing a write operation (causing a transition) that visits the victim cell observes the fault-free value (assuming that the victim cell does not have a S A fault). Hence, the only way to observe a faulty value at a victim cell is by having read-only march elements. u <4.0> & <t, i> <1. I> <4.0>&<t. 1 > <t. t> D (a) A U fault linked with a CFin fault Figure 2.4: The U and D2 faults dl d 2 (b) The D2 fault 37 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2.5.1 Properties of Linked Faults In this section we handle the different combinations of linked faults. Our strategy is to show that any combination of linked faults that contains single cell faults, SAFs and TFs, can be detected by detecting the single cell fault. Address decoder faults are implicitly considered in this strategy, since they are dominated by S A and CFid faults. Then we handle the case when only Oinked) CFin faults are present, followed by the case when only (linked) CFid faults are present. And Anally we present the dominating set for the case when at least one CFid fault is present linked with one or more CFin faults. Before we go into details, we present the following theorem, which shows that it is sufAcient to consider only two consecutive march elements when dealing with the classical multiple cell faults. The following theorem is a variation of Theorem 2.1. It deals with linked classical faults only, and its proof is similar to the proof for Theorem 2.1 when CFst faults are not considered. Theorem 2.3: It is impossible for a single march element to detect a (linked) classical multiple cell fault. Any sequence of more than two march elements that detects a (linked) classical multiple cell fault contains a subsequence of two consecutive march elements, Ml and M2, that can detect the fault. (In general, the two march elements may be separated by one or more read-only march elements. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. However, these elements can be removed without affecting the detection of the fault.) Notice that when the U fault is present on each side of the coupled cell where coupling cells exist, Ml can be used for initialization only. Hence, M2 must excite the fault and observe the faulty value. In such a case, we study M2 only, and M l can be any march element ending with the same data value that M2 starts with. 2.5.2 Single cell faults We present here four theorems that deals with stuck-at faults, transition faults, stuck- open faults and data retention faults. Theorem 2.4: Any march test that detects unlinked SA faults also detects any set of linked faults that includes one or more SA faults. Proof: This follows from the definition of SA faults, where the value of a cell is not changed even when the fault is linked with others. ■ It is possible that a memory cell suffers from a transition fault while it is also a target for a combination of undetectable classical coupling faults, which will be discussed 39 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. in Section 2.5.6. In this case, the linked faults can be detected by detecting the transition fault using internal reads with the condition that the internal reads follow a write operation that causes a definite transition. Note that a write operation causes a definite transition only if it follows an operation, read or write, with data value that differs from its value. Based on this discussion we reach the following theorem. Theorem 2.5: All sets of linked classical faults that include one or more transition faults are detected if and only if a march test contains one or more march elements that contain one or more internal rO and internal rl operations following a write operation causing a definite transition. In the case of SOFs, the returned value for a read operation is supplied from the read latch, not from the target memory cell. Hence, even if the victim cell is a target for other faults, they do not affect the SOF detection. Another point is the fact that the returned value in the case of a SOF is fixed and hence the mentioned conditions in the next theorem are sufficient for detecting it. Same conditions are mentioned in [46]. Theorem 2.6: A test detects SOF linked with any other fault if it has two march elements of the form: (a) (..., rx ,..., rx!,...) (b) (..., rx! rx ,...) 40 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Theorem 2.7: Data retention faults linked with all other faults, except CFds-r faults, are detected by any test that contains {delay; < = > (r 0 )} and {delay; <=>(rl)}. Theorems 2.4 and 2.5 present the necessary and sufficient conditions for detecting any combination of linked faults that include SA and transitions faults. Theorems 2.6 and 2.7 present sufficient conditions for detecting SO and DR faults. From this point we consider only combinations of linked faults that do not include any single cell faults. 2.5.3 Address decoder faults Theorem 2.8: Address decoder faults are equivalent or dominated by other faults as follows: - AF1 and AF2 are equivalent to SA faults. - AF3 is dominated by AF4. - AF4 is equivalent to CFid faults as shown in Figure 2.5. From this point onward, we will not consider AD faults since Theorem 2.8 has already shown that it is sufficient to consider SA and CFid faults. c is equivalent to ^1 < 1 .0> & <T. 1> Figure 2.5: Equivalence of AF4 fault to the U fault 41 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2.5.4 Inversion coupling faults In this section, we consider the case where we have inversion coupling faults only. The excitation requirement of a coupling fault is the transition required to excite the fault. Lemma 2.3: When visited by a march element that starts with a read operation, two linked CFin faults of opposite excitation requirements caused by two coupling cells in the same side of the victim cell are equivalent to one cell coupling the victim cell on both excitation requirements. Lemma 2.4: When visited by a march element that starts with a read operation, a set of linked CFin faults on one interval ]a, b[ that are located at one side of the victim cell, and with no coupling cell for CFid fault, are equivalent to CFin faults caused by one coupling cell located on the same direction of the victim cell. <i. :> <r. :> <1, !> & <T, t> is equivalent to Figure 2.6: Equivalent linked CFin faults discussed in Lemma 2.3 X CFin .CFin Y X CFin Cl...Cn y is equivalent to Figure 2.7: Equivalent linked CFin faults discussed in Lemma 2.4 42 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Figures 2.6 and 2.7 show the meaning of Lemmas 2.3 and 2.4, respectively. Lemma 2.3 follows from the fact that the total number of transitions applied on cells a and b is equal to the total number of transitions on cell e, regardless of the total number of operations in the applied march element. The condition in Lemma 2.3 that the applied march element starts with a read operation ensures that both cells a and b have the correct and identical initial values. Lemma 2.4 follows from the fact that having an odd number of coupling cells with <1, t> or <?, t> fault on one side of the victim cell is equivalent to having one coupling cell with the same coupling fault. If we have odd number of both types, then they are equivalent to one coupling cell with both coupling faults (similar to Figure 2.6). Theorem 2.9: When only CFin faults are targeting a victim cell, all possible cases are dominated by all possible combinations of faults in the form of the three-cell model shown in Figure 2.8, given that applied march elements start with read operations. Figure 2.8 shows 16 possible combinations, one of which represents the fault free memory, and other 4 of which represent unlinked faults (The notation <£,!> is a short form for the fault <T, t> & < i , t>). In the scope of linked faults, we have studied all the remaining 1 1 combinations, which represent linked faults and 43 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. considered all their necessary and sufficient conditions. Figure 2.9 shows one of these combinations of faults and a complete list of necessary and sufficient conditions that consist of march elements starting with read operations, and hence validating the previously mentioned Lemmas 2.3 and 2.4 and Theorem 2.9. ■ £ E u l CFin e (0. <T, !> . <4. I>. <J,t>( Figure 2.8: The Model for Linked CFin Faults < T ,t> <T, I> ~ T ~ 1 Condition for detection is to have one of the following pairs o f march elements: Tt(rd wd); ft (rd ....) odd # o f wI in Ml or M2 but not both OR lt(rd....... wd); ft(rd....) odd # o f wl in (Ml + M2) OR 1 1 (rd....... wd): ft(rd,...) odd # o f wl in (Ml + M2) OR ikrd........ wd); ll(rd....) odd # o f wl in Ml o r M2 but not both Figure 2.9: Instance of Linked CFin Faults and All its Necessary and Sufficient Conditions 2.5.5 CFid linked with CFid In this section we discuss the case when only linked CFid faults are present. Our objective is to list the necessary and sufficient conditions for their detection. The number of possible combinations of CFid#CFid faults is huge making it difficult to study all possible cases. Instead, we show that if each of the 16 CFid faults shown in Figure 2.10 are detected after exciting the closest CFid fault in the same march element, then all combinations of CFid#CFid faults are detected. Then we present a 44 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. set of eight specific CFid#CFid faults and necessary and sufficient conditions for their detection. Clearly it is necessary that a test detects the eight linked faults, otherwise it does not detect all CFid#CFid faults. We then show that satisfying the conditions for detecting those eight faults guarantees the excitation and detection of the closest CFid faults in the desired manner, for each of the 16 cases shown in Figure 2.10. Hence, detecting the eight faults is not only necessary but also sufficient for detecting all possible combinations of CFid#CFid faults. The excitation of a CFid fault requires a march element that causes the exciting transition for the fault, while the detection requires having an initial value at the victim ceil that differs from the value enforced by the fault. If we have a test that excites the fault caused by closest CFid coupling cell, covering all possible cases of CM a v v b C F id e {< T . 0>, <t, 1>, <i, 0>. <1. 1> . <T , 0>&<i. 0 > , < T , 0>&<i, I> , < T , 0>,<T, !>} Figure 2.10: All Possible Linked and Unlinked CFid Faults Combinations March Element (M2) Detection U = <i, 0> & <t, 1 > <i, l> <T . 0> 1f(r0, w l,...) X ' “ 1 1t(ri, w O ) X ' « f c n V lt(rl. w O , w l,...) V Figure 2.11: Linked CFid Faults and Necessary and Sufficient Condition for Their Detection 45 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. coupling shown in Figure 2.10, and detects it in one march element, M2, then the test is capable of detecting all CFid#CFid combinations. This is true since no masking may happen to the fault excited by the closest coupling cell to the victim cell due to the fact that CFid faults set the victim cell to a new faulty value regardless of its current value. Table 2.5 shows eight CFid#CFid faults with their necessary and sufficient conditions. These conditions are obtained by studying all possible values for M2 and keeping only those that are capable of detecting the corresponding faults. Figure 2.11 shows an example fault and how its necessary and sufficient conditions are generated. Notice that if a fault has more than one necessary and sufficient condition, then it is necessary and sufficient to satisfy at least one of them. The dots in a condition mean that the rest of the condition can be any combination of operations as long as the first part, which is specified, is satisfied. Read operations can be added between any two operations in every condition. Table 2.5: Some Linked CFid Faults With All Their Necessary and Sufficient C o n d i t i o n s Fault C ondition F ault C on d itio n u < i, l> < t.o> C l: lt(rl, wO , w l,...) < t. 0> <1. 1> y C5: tl(rl. wO, w l,. .) J 1 " 1 . < J t ___________1 ___ ._____1 -----!_► ^ u b a v - ^ v a b u 11 <T, o> < i. i> C2: T f(rO . wl, wO,...) <1, I> < t,0 > 1 1 C6: U(iO, w l, wO....) | U T - x _ ------- L _ — 1 — L * . ^ u b a V - ^ v a b u II <1. I>& <T,0> , 1 1 .......................i * C3: tt(iO.......wO) or lt(rl.......wl) < i. 1>&<T.0> ti i f t % h ^ u a v " V a u u = < i. o> & <T. i> - “ 1 C 4 :1t(i0.......wl) or It(rl.......w O ) U = < 4 .0> & < t, I> « ^ C8: U(iO.......wl) or U(rl.......wO) * u V ► ' V u ' 46 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Theorem 2.10: A test detects all possible combinations of CFid#CFid faults if and only if it satisfies the necessary and sufficient conditions for faults shown in Table 2.5. Proof: To prove the theorem, we need to prove the following two parts: 1. If a test detects all combinations of CFid#CFid faults, then it satisfies all the necessary and sufficient conditions shown in Table 2.5. 2. If a test satisfies all the necessary and sufficient conditions shown in Table 2.5, then it detects all combinations of CFid#CFid faults. Assume that a test detects all combinations of CFid#CFid faults and yet it does not satisfy one of the necessary and sufficient conditions shown in Table 2.5. Hence, there is a sufficient condition for detecting one of the eight faults that is not listed in Table 2.5. However, that contradicts with the fact that all the necessary and sufficient Table 2.6: Possible CFid Faults and Their Detecting Conditions CFid: a and v Detecting Condition CFid: b and v Detecting Condition <T,o> Cl <T , 0> C5 <t, l> C2 < T , i> C6 <1,0> Cl <4.0> Cl <1, l> C2 <4. l> C l <T , 0>&<l, o> Cl <f, 0>&<4.0> Cl <f, 0>& <4, l> C3 <T , o>& <4. I> C7 <T, l>& <4, o> C4 <T . i>&<4.0> C8 <T , i>& <4, i> C2 <t. i>&<4, l> C l Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. conditions for those faults are listed in Table 2.5, which are found by enumerating every possible M2 for every one of the eight faults in the manner shown in Figure 2.11. Hence the assumption is invalid and the first part of the theorem is proven by contradiction. Now assume that the necessary and sufficient conditions for faults shown in Table 2.5 are satisfied. We need to prove that they are sufficient for detecting all combinations of CFid faults. Assume we have any combination of linked CFid faults, and name it X. Figure 2.10 shows all possible combinations of CFid faults, including X. Notice that Table 2.6 shows how every case is detected by one of the eight conditions (C1-C8) given in Table 2.5. In the given conditions, the fault is excited and detected in one march element M2, and since it is the closest to the victim cell, the fault can not be masked due to the presence of other faults. Hence, the combination X is detected by one of the eight conditions (C1-C8). Hence, satisfying the conditions given in Table 2.5 is sufficient for detecting any combination of CFid#CFid faults. ■ 2.5.6 CFid linked with CFin By this point, we have discussed all possible (linked) faults, except those combinations of linked CFin and CFid faults that contain at least one CFid and at least one or more CFin faults. This is a generalization of the case discussed in the Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. previous section. Again, we identify sets of detectable faults that dominate the set of all possible detectable faults. We then demonstrate that the satisfaction of conditions for their detection is not only necessary but also sufficient for detecting all detectable CFid#CFin. (A significant amount of detail is presented in the next few pages. These details serve the purpose of providing intuitive proofs for Theorems 2.11 and 2.12 and may be skipped.) Definition: • The set S is the set of all combinations of linked CFin and CFid faults. • A class of faults is a subset of S that is denoted using a partially defined fault notation. The undefined part of this notation can be replaced by any combination of linked faults. • An element in a set of linked faults is a particular completely defined combination of linked faults. We have identified U set that contains 96 elements, where each element is a combination of linked CFid and CFin faults. Figure 2.12 shows one of these elements. The elements in the U set are selected such that detecting one of them leads to detecting a class of faults in the set of all combinations of linked faults, S. A main property of the U set is that the condition(s) for detecting an element in the set requires the excitation of the CFid fault excited by the memory cell a. For example, Figure 2.12(a) shows an element in the U set and Figure 2.12(b) shows the condition 49 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. u <1. o> & < T . i> < ■ ! . . t> <t. o > (a) a U element (b) The condition for detection o f the U element in (a) <T,0> Y :zn (c) Class of faults dominated by the U element in (a) and guaranteed to be detected by any march test that satisfies the condition in (b). Figure 2.12: Example of a U dement with the corresponding dominated class of faults required to detect it. If we have a test that detects all detectable linked faults, then it must detect the fault shown in Figure 2.12(a) and hence must satisfy the shown condition. Figure 2.12(c) shows a class of faults that is detected if the corresponding U element is detected. In a similar manner, a set of 96 elements, collectively called the U set, dominate all combinations of linked faults (the set S), meaning that detecting all elements in the U set guarantees detecting all elements in the S set. However, there are 6 elements in the U set that are undetectable, two of which are shown in Figure 2.13. Figure 2.13(a) shows an undetectable U element that corresponds to the D class. Some elements in the D class are detectable while others are not. D2 class is a subset of the D class that contains faults that collectively dominate all faults in the D class. 50 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. u < T , i> & <4. o> <1, t> D Y d, d2 v " * d v y (a) Undetectable U element with the cotresponding class o f linked faults (the D class) U <1. I> <T . I>&<1. t> < 1. t> X < T . 1> & <1. t> <t. t> Y (b) Undetectable U element with the corresponding class o f linked faults (the Ni class) Figure 2.13: Two of six undetectable U elements D Y v y d v di d, Figure 2.14: The D class and the D2 class that dominates it < t, 0> D <T,0> X > opO, wl) <=>(rl) (a) A D* element (b) The condition for detection of the D2 element in (a) (b) A fault class dominated by the D2 fault in (a) Figure 2.15: Example of a D element with the corresponding dominated class of faults U X D P D D X U u x d v d d v d x u U X D D Y U d v d y u Figure 2.16: Fully undetectable classes of faults 51 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. There is a set of 96 elements in the D2 class that collectively dominate all of its elements. We call the set of these 96 elements the D2 set. In a similar manner to the U set, the D2 set dominates the S set. Figure 2. IS shows an element of the D2 set, the condition required to detect it, and the class of faults that is dominated by the element of the D2 set. Similar to the U set, the D2 set contains 6 undetectable members. Two of the undetectable members belong to the intersection with the U set, and dominate classes of faults shown in Figure 2.16, each of whose elements are undetectable. We are left now with four members in the U set and four members in the D2 set that are undetectable. These eight members dominate N classes. Figure 2.13(b) shows an undetectable U element that corresponds to a class, we call the N| class, that contains elements that are detectable. We will analyze the example shown in Figure 2.13(b); the other seven elements in U and D2 that dominate the rest of the N classes can be treated in a similar manner. When dealing with the elements of the Ni class, we ignore any combination of linked faults falling to the right of the victim cell v, since they are irrelevant. Figure 2.17(a) shows a fault that can not be detected but by the march element MNi = TT(rl, w O). Hence, for a test to cover all detectable elements in S, it must contain MN|. Also, if a march element contains wl ■ * - u x a b v (b) A subclass of the Ni class (a) An element in the Nidass Figure 2.17: An element and a subclass o f the Ni class 52 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. <t. :> & < i. o > x (a) The N: class (b) The Nj class Figure 2.18: The N2 and N3 classes <t. i> & < ■ ! ■ . t> <T, i> & <i, !> <1, t> Figure 2.19: The intersection of N| and ty classes (the Ni, 2 class) (causing a transition) and has an IT direction, then it does not detect any member in the Ni class. Hence, among all march elements with 1 T direction, only MNi can be used. That leads to the conclusion that any member in the class of faults shown in Figure 2.17(b) is undetectable if it can not be detected by MNi, since the faults in this class can not be detected by a march element with the II direction due to the presence of the U fault at the left most coupling cell. Now consider the case when a member in the Ni class is also a member in one of the classes shown in Figure 2.18. These two classes, N2 and N3, are two of four N classes dominated by undetectable members in the D2 set. We will study the intersection of the classes Ni and N2; and the intersection of Ni and N3 can be treated in a similar manner. The result of the intersection of the Ni and N2 classes is shown as a new class in Figure 2.19, namely the N|, 2 class. Faults in the Ni, 2 class can be detected only by MNi and MN2, where MN2 = Ji(rl, wO) < = > (r0). Now, the only possibility for an N[ element is to be in the Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. intersection of the Ni and a class dominated by a detectable D2 element. Such elements are detectable by satisfying the conditions for detecting the detectable elements in the D2 set. As a result, a test must contain MNi, MN2 and MN3 in order to detect all detectable elements in the Ni class. By studying the N2 to Ng classes in a similar manner, we reached the conclusion that for a test to detect all detectable faults in the N classes, it must contain the following pairs of march elements: ft(rO, wl) <=>(rl), TT(rl, w O ) <=*(r0), ^(rO, wl) <=>(rl), and JJ(rl, wO) «=>(r0). By covering the detectable members in the U and D2 sets, along with the detectable members in the N classes, we cover a set that dominates all detectable combinations of linked faults. That follows from the fact that any detectable fault either dominated by a detectable member in the U set, a detectable member in the D2 set, or it is one of the detectable members in the eight N classes. Based on the above discussion, we obtain the following results. Theorem 2.11: All combinations of linked CFin and CFid faults are detected if all detectable faults in the sets U and D2 and N are detected. Theorem 2.12: The set of undetectable linked faults are the following: a. All faults that are dominated by the UnD2 set (shown in Figure 15), and b. Faults in the eight N classes that can not be detected by any of the four pairs of 54 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. the march elements: 1t(iO, wl) <=>(rl), 1t(rl, wO) < = > (iO ), li(rO, wl) <=>(rl), and Ji(rl, wO) »(rO). 2.5.7 CFst and CFds faults linked with other faults Theorem 2.13: A march test detects CFst faults linked with other faults if it detects CFid#CFin faults. The above theorem follows from the fact that the detection of CFid#CFin faults requires the satisfaction of a set of conditions that are also sufficient for detecting CFst faults. The CFst fault has a unique property since it forces the victim cell to a certain value that is not changeable by any other linked fault. It is like forcing the victim cell to a temporary SA fault. With this property in mind, conditions in Table 2.7 can be shown to be sufficient for detecting CFst faults linked with any other faults. Table 2.7: Sufficient Conditions for Linked CFst Faults <0.0>ij: ft(rl,.... wO) < 0,0>jj: U(rl, ... wO) <0,l>ij: tt(rO,. ., wO) or <=>(rO ) <0,l>jj: IkiO ,. ., wO) or <=>(iO ) <1,0>y: 1t(rl,.... wl) or<=>(rl) < 1,0>jj: U(rl, ... wl)or<=>(rl) <1. l>jj: fT(rO,.... wl) <1, !>*: U(rO, ...w l) Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Theorem 2.14: A march test detects CFds-w if it detects CFid faults. The above theorem follows from the fact that detecting CFid faults requires causing transitions for excitation, which requires write operations. Hence, detecting CFid faults guarantees detecting CFds-w faults. 2.6 Summary In this chapter we presented a procedure to generate all necessary and sufficient conditions for detecting unlinked classical and extended fault models. We also provided a study that covers linked classical faults and provides their necessary and sufficient conditions. We have identified the set of undetectable linked classical faults. The sufficient conditions for the linked extended fault models are also provided. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 3 3 March Test Generation We discussed the sufficient and necessary conditions for fault detection in Chapter 2. In this chapter, we present a new algorithm that generates tests using the given conditions. Since all conditions for classical fault detection are given, the generated tests are optimal. We will consider constrained and unconstrained memories. We will also compare our work with the published methodologies [51,52, 58] that try to achieve the same goal. 3.1 March Tests’ Search Space Reduction Given a set of faults in a fault list (FL) along with conditions for their detection, we present a methodology for generating optimal march tests. The methodology exploits the properties of march tests to avoid generation of equivalent march tests. The methodology is a branch-and-bound framework in which march elements are incrementally added to a partial test. In each step, the conditions that a march element must satisfy are used to reduce the number of alternative march elements considered. The number of march elements considered is further reduced by 57 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. eliminating those march elements that do not facilitate the detection of any of the desired faults not already detected by the partial test. Also, a weight function is used to order the candidate march elements to be added to a partial test and serves as a branching condition. In generating march tests, we use the properties discussed in Chapter 1, along with the properties of combinations of march elements MP1-MP5 presented in Chapter 2, to limit the march elements considered at any step. To further limit the space searched while generating march tests, and hence to speed up the process of generating tests, we present the following lemmas. Lemma 3.1 shows that, under some conditions, we can delete an intermediate march element that consists of a read operation only when dealing with unlinked faults, and hence we do not study tests where such a march element is present. Lemma 3.2 shows that it is unnecessary to consider tests that have two or more consecutive march elements starting with write operations. Lemma 3.1: When only unlinked faults are considered, an intermediate march element that consists of only one read operation can be removed or combined with the march element following it, unless it is between march elements with different directions and each causes an odd number of transitions of the same direction. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Proof: CFin faults are masked when the coupling cell experiences even number of transitions. For this reason, we handle this special case at the end of our proof. For other cases, assume we have Ml, M2 and M3 where M2 is a march element consisting of a read operation only. There are two possible cases: M3 starts with a read operation, or it starts with a write operation. In the first case, M3 would start with a read operation with the same expected value as the read in M2. Hence, it will detect any fault which is detected by M2. Therefore, M2 can be detected. In the second case, the third march element starts with a write operation. The last two march elements in this case can be combined into <M2, M3> with the same direction as M3. If M3 starts with a write operation that has data which is the same as the read in M2, then that write operation can be removed. The resulting march element <M2, M3> has the same detection capability as M2 since it starts with a read, and it has the same excitation capability as M3 since it contains the operations of and has the same direction as M3. The special case is having Ml and M3 with different directions (similar to Case 3 in Figure 2.1), making it possible to visit the coupling cell during Ml and M3 before visiting the coupled cell in the case of removing M2 or combining it with M3. If Ml has an odd number of transitions, then M2 may detect a CFin fault. However, if we delete M2 or combine it with M3 as above, the fault may escape since the total 5 9 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. number of transitions on the coupling cell i may become even. We limit this special case with the following conditions: - The number of transitions should be known. Resulting transitions from the first write operation in a march test are unknown due to the unknown state of the memory before the test. - The direction of Ml and M3 should be different. - The total number of transitions in Ml and M3 must be even. ■ Lemma 3.2: When classical or extended faults are considered, consecutive march elements starting with write operations can be combined with direction same as the direction of the last one. Proof: Assume we have Ml and M2 of the form: (wv,..., wx) (wy,...) (no direction is mentioned since it is irrelevant). In this case, no multiple cell fault is detected since such a fault requires a march element starting with a read. Hence, we can combine Ml and M2 with the same direction as M2 to keep any fault excited by M2 excited by (wv,..., wx, wy, ...).■ 3.2 First Stage: Filtration of Conditions Some faults can be removed from the list of faults due to fault dominance. Assume we have two faults X and Y in our fault list. If detecting Y guarantees detecting X, then we Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. remove X from our list of faults. X is said to be dominated by Y. That would be the case when the conditions for detecting Y satisfy at least one of the conditions for detecting X. For example: any set of conditions for detecting CFid, satisfies the conditions for SA faults. This stage helps in narrowing the domain of search for march tests. 3.3 Second Stage: Building the Tree Structure Before we build the tree, we initialize two lists: Uncovered faults (UFL), and Covered faults (CFL). Initially, all faults are in UFL, and CFL is empty. Also, we have a global variable T that stores the value corresponding to the best test found at any stage of search based on a certain desired criteria, such as symmetry. For example, we make our target to be finding the shortest test (lowest time complexity), hence T is defined to be time complexity of the generated tests. Initially T is infinity. Also, we have a stack S for nodes. It is initially empty. Every node in the tree is a march element with the following information: - A list of uncovered faults (UFL) by the partial test denoted by the path proceeding the node but not including it. - A list of covered faults (CFL) by the path proceeding the node but not including it. - A list of detected faults (LDF) from the UFL by the node: all conditions covered by adding this node. Initially 0. - A list of initialized faults (LIF) from the UFL: beginning o f a condition for single 61 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. cell faults or Ml for multiple cell faults. Initially 0. - The weight of the node ‘W ’: For generating shortest test, we use: W = Size of LDF. When two march elements have the same W, then the one with fewer operations is taken. Initially - Tn is the number of operations from the first node till the node n. It is the length of the march test when the node n is a leaf. 3.4 The Test Generation Algorithm 1. The starting point is the root node, which is a partial test that does not contain any march element. 2. Create new nodes consisting of march elements starting with read and write operations. If none of the undetected faults benefit from an internal read operation, then add write operations only, one at a time, to generate new nodes with different sizes. If some undetected faults can be detected by an internal read, then add one operation at a time, that can be read or write, with maximum one read for each data value (property MP3), to generate new nodes. Possible next nodes are the ones that: • Follow the properties of march tests (P1-P5) and march elements (MPI-5). • Have non-empty LDF or LIF. • If the node is M O (initialization march element), then it should start with w O . • All Ml nodes should have the same direction. 62 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. • Does not contain only a read operation, unless it is the last march element in the test (UFL = 4>) or belongs to the special case discussed in Lemma 3.1. • Is not a march element that starts with a write operation if the current node starts with a write operation. • Is not a superset of other branches unless it has a different LDF or L1F, or ends with a write operation having different data than the other march elements at the same level. Note: Stop creating new nodes when two consecutive new nodes are rejected in each direction, with different starting operations. 3. Give weight to every new node, and set its Tn value to its size plus the Tn of the parent node. 4. Choose the node with highest W as the next node. Push on the stack the other nodes in a descending order of their W values. Remove LDF of the chosen node from UFL and add it to CFL. 5. Go to 2 until UFL is empty. 6. If the number of operations in the generated path (Tn) is less than T, then set T = Tn. 7. Pop the stack S until we get a node with Tn < T. 8. Go to 2 until the stack S is empty. 3.5 Analysis of the Algorithm Conditions, mentioned in step 2 of the above procedure, for creating new nodes in the test generation tree are used to speedup the process. We analyze them in order as follows: 63 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1. No need to study the case when MO is <=>(wl,...) since it would lead to equivalent march tests as the ones generated above (property P3 in Chapter 1, Section 1.3.1). 2. Considering only those nodes that satisfy march test properties eliminates any path that does not match those properties. 3. If a node does not contribute by either initializing or detecting a fault, then its branch is not taken since it would be redundant. 4. Since M O has no condition as per the direction of application, march tests generated from paths with nodes at Ml level that differ only by the direction would be redundant (property P4 in Chapter 1, Section 1.3.1). 5. Lemma 3.2 handles the case when consecutive march elements start with a write operation. 6. If a node is a superset of another node that share the same parent, then it should add more power to the test otherwise only the smaller node with same power is considered to avoid redundancy. 3.6 Illustration of The Algorithm As an example, assume that we are considering state coupling faults only. Table 2.4 contains all conditions for their detection. Figure 3.1 shows the test generation tree and how the first march test is generated. The search sets the bound, T, to 8 after finding the first complete test. The generated 8N test is not optimal so the search tree grows until an optimal test is found. As we will see in the next section, an optimal test for CFst faults is of length 6. 64 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. V o ) | T n = l.W = 0 | i(wu. rO) Tn = 8, W = 2 LDF={4,6) Stop. All faults covered. T = Tn = 8 tt(rl. wO. rO ) j T n = 4 .W = 2 F={5,7] Tn = 7. W = 4 ; |L D I^{ 1 .2 .3 .8 | I I (wu, lO, w l. rl. *<^*tt(wO. tO. w l. r l. wO) ^T n = S. W = 2 j Stop this way and reject this node Contained by the third node C ft(wO, tO, w l, r l. wO. wl) < ^lf(w O . rO. w l. r l, wO. w l, wO)] Stop this way and reject this node. ' — ' Contained by the fourth node above. Stop generating children since two nodes rejected. Figure 3.1: Test Generation Tree for CFst Faults 3.7 Generated Tests One of the most important properties in march tests is to have the shortest length possible. Shorter march tests require less time and consume less power. A second desired property in march tests is to be uniform, which is having the same number of operations in every march element. Uniform tests can be implemented in BIST using simpler hardware since they eliminate the need for complicated logic required to deal with different lengths of march elements. A third desired property in march tests is to have small number of march elements. Having fewer march elements reduces the number of times the memory is traversed and the addresses are changed leading to lower power consumption and heat dissipation. 65 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. We implemented the presented test generation algorithm in such a manner that it can generate tests for any given combination of types of faults discussed in Chapter 2. The test generator uses the set of conditions presented in that chapter. The following two sections present the generated tests by applying the algorithm with the conditions for detection of unlinked and linked faults. 3.7.1 March tests for unlinked faults We used the detection conditions for unlinked faults, shown in Table 2.4, as input for the test generation algorithm. By applying the algorithm for test generation with different fault coverages, we get march tests shown in Table 3.1 and their fault coverages shown in Table 3.2. The results demonstrate the optimality of some of the published tests for the first time, such as March X and March C-. Twelve new tests for different combinations of fault types are generated. Some of the new tests provide shorter march tests for some combinations of faults than the known tests. MT-2 is the shortest test that is capable of detecting CFst faults. We notice that MT-2 has low time complexity of 6 N. So if CFst fault is the only targeted fault, then there is no need to use March C- (ION test), which previously was the shortest known test that covers this fault. This is also the case for CFin fault that is covered by MT-1 (5N) and March X (6 N). If both CFin and CFst are desired, then MT-4 is still a better option than March C-, since it is shorter. 66 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. The new tests include three uniform tests that cover different combinations of faults. MT-3 has the same number of operations and the same fault coverage as March X. However, unlike March X, MT-3 is uniform. This makes MT-3 a better option than March X for BIST design. MT-7 and MT- 8 are uniform and have the same fault coverage as March C-, with the exception of CFds-r. Since CFds-r do not occur in SRAMs [46], for SRAMs, MT-7 and MT- 8 have the same fault coverage as March C-. Due to the uniformity of MT-7 and MT-8 , they are more suitable for BIST than March C-. Several new tests contain fewer march elements than known tests, with comparable fault coverage. MT-3 has fewer march elements than March X. The new tests MT-5 to MT- 8 have the same fault coverage as March C-, except CFds-r, making them a better option for SRAM testing than March C-. The new tests MT-9 to MT-12 have the same fault coverage as March C-SOF and they have fewer march elements, making them a better option than March C-SOF regardless of the memory type. We notice that March C- is the shortest test that covers all faults except SOF. However, when a read operation is added to it in order to cover SOF, then the tests MT-9 to MT-12 become better options. When CFds-r and SOF are not desired, then tests MT-7 and MT- 8 become more attractive since they are uniform and have fewer number of march elements than March C-. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 3.1: Generated March Tests for Unlinked Faults Test Name Test MATS’ < = > fw O , rO, wl, rl) MATS-DRF <=»fw O ); <=»frO,wl); <=>(rl) MATS+" <=> fw O ); 1ifr0, wl); lifrl, wO) MT-1 < = > fw O ); tifrO, wl, wO); < = > ( r 0 ) MT-2 < = *fw O ); lifrO.wl); lifrl.wO); <=>(r0) MATS++’ «fwO): lifrO, wl); lifrl. wO, rO ) March X’ «(w0): tifrO, wl); lifrl. wO); < = > (rO ) MT-3 lifwO, wl); lifrl, wO); T T frO , wl) MT-4 < = »(w O ); lifrO.wl); fi(rl.wO); lifrO.wl) MT-5 ofwO); H'(rO,wl,wO,wl); lifrl.wO); lifrO.wl); <=>(rl) MT-6 <=>(w0); lifrO.wl); lifrl.wO); IlfrO.wl.wO.wl); <=>frl) March C-* ofwO); 1t(r0, wl); tlfrl, wO); lifrO, wl); lifrl, wO); < = *frO ) MT-7 ITfw O , wl); lifrl, wO); lifrO, wl); TTfrl, wO); ttfrO, wl) MT-8 fifwO, wl); TTfrl, wO); IlftO, wl); lifrl, wO); T T frO , wl) MT-9 »fwO); 1ffr0,wl,rl,w0,wl); lifrl.wO); lifrO.wl); <=>frl) MT-10 «(w 0); fffrO.wl); lifrl.wO); lifrO.wl,rl.wO.wl); « f r l) March C-SOF <=>fw O ); tffrO,wl,rl); ITfrl.wO); lifrO.wl); lifrl.wO); < = > frO ) MT-U tlfwO.wl); U(rl,wO,rO); lifrO.wl); lifrl.wO); lifrO.wl) MT-12 iifwO.wI); lifrl.wO); lifrO.wl); Iifrl.w0.r0); iifrO.wl) * test proven to be optimal for the first time. Table 3.2: Fault Coverage of Generated Tests Test SAF SOF DRF** TF ADF CFin CFid CFst CFds OfN) MATS’ • • 4N MATS-DRF • • 4N MATS+’ • • • 5N MT-1 • 5N MT-2 • • • 6N MATS++’ • • • • • 6N March X’ • • • • • 6N MT-3 • • • • • 6N MT-4 • • • • • • 7N MT-5 • • • • • • • ION MT-6 • • • • • • • ION March C-’ • • • • • • • • ION MT-7 • • • • • • • ION MT-8 • • • • • • • r ion MT-9 • • • • • • • • • r i i n MT-10 • • • • • • • • • ii n March C-SOF • • • • • • • • • ii n MT-11 • • • • • * • • • ii n MT-12 • • • • • • • • • ii n * test proven to be optimal for the first time. **D R Fs are considered to be coveted when a test detects them by adding two delays between march elem ents. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. As described in the previous sections, the test generation algorithm works in a branch-and-bound manner, making it branch repeatedly to reach a march test, and uses the length of that generated march test as an upper bound for the rest of the search. Due to Theorem 1, the algorithm is limited to a maximum bound of a march test with a number of march elements equal to twice the number of faults. By using the weight function described in Section 3.3, for several set of faults the first test generated was optimal! For generating optimal ION march tests without using a weight function, the tree grows to 41,413 nodes. Using the weight function reduces the number of generated nodes to 22,503, providing a 50% improvement. 3.7.2 March tests for linked faults We used the test generator to generate the shortest test possible that satisfies the necessary and sufficient conditions for all detectable faults in the U, D2 and N sets presented in Chapter 2. We have presented an example for the necessary and sufficient conditions for a U element in Figure 2.12. An example that deals with a D2 element was presented in Figure 2.15. Theorem 2.12 presented all conditions for detecting all detectable elements in the N classes. A number of march tests of length 43N were obtained. By eliminating those tests that do not satisfy the sufficient conditions for detecting CFin faults, we obtained a subset of march tests that detect all linked classical faults. Figure 3.2 shows one of the newly generated tests. Notice 69 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. that we have 10 read-only march elements. All of them are required to ensure the detection of all detectable members in the D2 set. Due to the structure of the members in the D2 set, every member requires M2 to be a read-only march element in order for a sequence of march elements, {Ml; M2}, to detect it. The test shown in Figure 3.2 is capable of detecting all detectable linked faults, except CFds-r. If a subset of linked faults is desired, then only the conditions of the corresponding members in the U, D2 and N sets are input to the test generator. For example, we targeted linked CFid faults and linked CFin faults, but not CFid linked with CFin faults. We used the conditions shown in Table 2.5 and demonstrated that March A was an optimal test for that subset of linked faults. When considering the same subset with TF linked to both CFin and CFid faults, we found out that March B is an optimal test for this set of faults. <=> (w 0); 1T(r0,wl, rl, w0,wl); <=>(rl); 1t(rl,w0,wl,w0); «(i0); ft(i0,wl); « (rl); ft(rl,w0); «=>(i0); 1t(i0,wl,w0); < = > (i0); U(r0,wl,w0, iO , wl); <=>(rl); U(rl,w0,wl,w0); <=K rO ); ii(ri),wl); <=>(rl); Ii(rl,w0); < = > (r0); U(i0,wl,w0); < = > (i0 ) Figure 3.2: March Test for All Linked Classical and Extended Fault Models 3.8 Constrained Memory Testing In the previous sections, we discussed unconstrained memories. However, memories are used in different forms such as caches, buffers, unidirectional memories, etc. 70 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Memories are used in different environments, like cores in multiple core systems, with different constraints on how they can be accessed, especially during testing. Every implementation and every environment necessitates different techniques. For example, in a multiple core system, memory modules can not be directly accessed from chip I/O, making it necessary to access the memory through other cores or through scan chains [9,19,28]. In our study, we assume that constrained memories such as stacks and queues consist of a RAM module and additional control logic. In this section, we will discuss in detail some memory structures that constrain the access to the memory. We will discuss testing unidirectional memories, queues, stacks and embedded memories. Cache memories will be discussed in the next chapter since they present several major challenges. All faults listed in Chapter 1 can occur in constrained memories. However, the constraints on accessibility may make it impossible to detect some types of faults since the conditions for their detection require some sequence of operations that can not be performed due to the constraints. 3.8.1 Unidirectional Memories Unidirectional memories are memory modules that can be accessed in one direction only making it impossible to test them using march tests generated in the previous 71 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. chapter. Such memories are used for different applications. For example, they are very useful for digital answering machines since a message is stored and retrieved as data in a single order. For such applications, a FIFO can not be used since the data for such applications is retrieved several times while a FIFO allows retrieving it only once through pop operations. 3.8.1.1 Fault Detection Conditions The required conditions for detecting unidirectional memory faults are a subset of the conditions mentioned in Table 2.4. We consider only those conditions that do not conflict with the constraint, meaning that they do not require traversing the memory in two different directions. Table 3.3 shows the conditions for detecting unlinked faults in unidirectional memories. 3.8.1.2 March Test Generation for Unidirectional Memories By applying the algorithm for test generation with different fault coverages, we get march tests shown in Table 3.5 and their fault coverages shown in Table 3.6. All tests shown in Tables 3.5 and 3.6, except MATS and SOA-March C— , are presented for the first time. Each test presented in these tables is optimal in terms of test length for the corresponding set of target faults. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 3.3: Conditions for Unlinked Fault Detection in Unidirectional Memories Fault Type Conditions 25 < I.0 > B 1t( .... w l); lt(rl,...) 26 <1. 1>„ 1t(.... wO); ftfrO.......w l . ...) or 1t(...): tt(..., lO.......w l) 27 <1. l>ji t t( .... o p l.......wO); 1t(iO,...) or 1t(.... w l); 1f(rl......wO, tO ....) 28 «r0.0>„ I t( .... w l) ftfrl.......i0....) 29 <t0,0>„ 1t(.... iO.......wl); ft(rl....) 30 <r0,1>„ l t( .... wO) ft(iO,...) 31 <a0.1>„ It(... iO.......wO); 1t(iO,...) 32 <rl, 0>„ ft(.... w l); ftfrl....) 33 <rl, 0>„ ft(... r l .......wl); ftfrl....) 34 <rl. l>i, l t( .... wO); ftCrO..... r l . ...) 35 < rl. I>» 1f(.... r l .......wO); tt(iO....) 36 <w0.0>„ 1t(.... w l); 1t(rl.......wO....) 37 <w0.0>» 1t(.... wO.......wl); «=>(rl....) 38 <w0. I>ii 1f( .... wO); tt(iO.......wO....) 39 <w0,1>B Iff.... wO); 1t(i0,...) 40 <wl. 0>i, 1t(.... w l); ftfrl.......w l....) 41 <wl,0>» 1t(.... w l); ftfrl....) 42 <wl, 1>„ 1t(.... wO); IttiO......w l,...) 43 <wl, 1>„ 1t(..., w l.......wO); ftfrO,...) 44 AF1 wO. rOand w l.rl 45 AF2 wO. rO and wl. rl 46 <AF3>i, tf(.... wd) ft(rd.....wd!) 47 <AF3>, 1t(.... wd) 1t(rd..... wd!) 48 <AF4>,, tt( .... wd) 1t(rd.....wd!) 49 <AF4>j, Untestable Fault Type Conditions I SA-0 W l.rl 2 SA-1 WO.iO 3 SOF It(—. iO.......r l , ...) D rft(...,rl.......iO ....) 4 DR-0 It(.... o pl) Delay ftfrl_ _ ) 5 DR-1 IT (_ opO) Delay ft(iO,...) 6 T t f WO. w l. rl 7 i TF WI.wO.iO 8 < t. t>„ It (.... wd) 1t (rd ..... w l. ...)o d d # o f wl in M2 9 <T. t>„ lt(!wl......w l....... wd) 1t(rd....) odd# of wl in Ml 10 < 1 . l> „ It (.... wd) It (rd......wO....) odd # of wO in M2 II <A.t>. It(!w0......wO....... wd) lt(rd,...) odd # of wO in Ml 12 <T. 0>„ ff(.... w l) 1t(rl. wO. wl,...) 13 <T.0>„ It(.... opO, w l ) ; 1t(rl....) 14 <T. !>,, It(.... wO) tt(iO, w l . ...) 15 <T. 1>H tt(..„ opO, w l, wO); lt(iO,...) 16 < i. 0 > j , It(.... w l) Itfrl, wO....) 17 < i.o>„ It(.... o p l. wO. wl); fffrl....) 18 <1. i>„ lt(.... wO) ttfrO. w l. wO....) 19 < i. l>. It(..., o p l. wO); ff(iO....) 2 0 < 0 .0>,, It(..„ w l)1t(rl.......wO,...) or It(...) tt(.... r l..... wO) 21 < 0 ,0>, lt(.... opO..... w l); tt( r l,...) ortt(.... wO) 1t(i0..... w l. r l . ...) 22 <0. 1>,, [f(.... wO); 1t(iO,...) or 1t(...): 1t(..., iO..... wO) or tt(_ ); 1t(.... wO. iO) 23 <0. I>„ 1t(.... wO); 1t(r0,...) 24 <1.0>„ tt( .... w l); ftfrl,...) or ft(...) ft(..., r l .......w l) orft(...) 1t(..., w l. rl) CFds-r faults never occur in SRAMs [46], hence the best test for single-order addressed memory that contains static cells is SOA-IO3 since it has the fewest march elements possible leading to lowest power dissipation. In [40] a 7N test, called SOA-CFst, was presented to cover CFst faults. We report two tests, SOA-6 1 and SOA-6 2 , each of complexity 6 N that cover CFst faults. Furthermore, SOA- 6 2 is uniform. Hence, generated tests are not only shorter but are more suitable for BIST implementation. Also in [40], a 13N test, called SOA-March 73 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. C-, is presented that covers the same set of faults as the newly generated SOA-12i and SOA-122- Again, these tests are shorter than their previously known counterparts and proven optimal. For linked faults, we can apply the test shown in Figure 3.3. The shown test is capable of covering all detectable linked faults dominated by the U, D2 and N sets. That contains only 50% of the detectable faults in unconstrained memory. The limited coverage is due to the constraint in accessing unidirectional memories. 3.8.2 Queues Queues are used in many applications such as write-back buffers in single-processor systems [4], buffers for tasks in shared memory multiprocessor systems [5,26], computer networks [32,37], wireless networks [10], etc. Different queue structures with testing procedures for them are presented in [2,49,50,54, 55,61]. We will be considering Ring RAM-type queue, shown in Figure 3.4, since it nicely illustrates the problems related with testing queues and is widely used. The queue consists of a memory, two counters for generating read (Front) and write (Rear) addresses, a flag that is set when the queue is full (FF), and a flag that is set when the queue is empty (EF). When a write operation occurs in the queue, it targets the location addressed ft(wO); 1t(r0,wl, rl, w0,wl); tT(rl); 1t(rl,w0,wl,w0); ItfrO); ft(rf),wl); tt(rl); ff(rl,w0); T f(rO ); 1t(r0,wl,w0); tf(rO ) Figure 33: March Test for Linked Faults in Unidirectional Memories 74 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 3.4: Generated March Tests for Unidirectional Memories Test Name Test SOA-3 ft(wO); ftfrO. wl) MATS ft(wO); ftfrO); fT(wI); ftfrl) SOA-4 ft(wO); ftfrO, wl); ftfrl) SOA-5, ft(wO, wl); ftfrl, wO); T T frO ) SOA-52 ft(wO); tT (rO , wl, wO); ft(iO) SOA-61 ft(wO); ftfrO. wl); ftfrl, wO); ftfrO) SOA-62 ft(wO, wl); ftfrl, wO); ft(rO, wl) SOA-March C~ ft(wO); ftfrO, wl, wO); ft(rO, wl); ftfrl, wO, wl); ftfrl) SOA-lOz ft(wO); ftfrO, wl, wO, wl); ftfrl, wO, w l, wO); ft(rO) SOA-IO3 ft(wO, wl, w O ); ft(iO, wl, w O , wl); ftfrl, wO, wl) SOA-I2i ft(wO); ftfrO, wl, rl, wO); ft(rO, wl); ftfrl, wO, rO, wl); ftfrl) SOA-122 ft(wO); ftfrO, wl, rl, w O , wl); ftfrl, wO, rO, wl, wO); ft(tO) Table 3.5: Fault Coverage of Tests Generated for Unidirectional Memories Test SAF DRF* TF ADF CFin CFid CFst CFds-w CFds-r Test Complexity SOA-3 • 3N MATS • • 4N SOA-4 • • • 4N SOA-5, • • • • 5N SOA-52 • 5N SOA-6, • • • • • • 6N SOA-62 • • • • • • 6N SOA-March C - • • • • • • • • ION SOA-lOj • • • • • • • • ION SOA-IO3 • • • • • • • • ION SOA-12, • • • • • • • • • 12N SOA-122 • • • • • • • • • 12N *DRFs arc considered to be covered when a test detects them by adding two delays between march elements. by Front index then the index is incremented. A read operation returns the value stored at the location pointed to by the Rear index. After a read, the value of the Rear index is incremented. The queue is full when the Front and Rear indexes become the same following a write operation, and it is empty when the two indexes match following a read operation. 75 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.8.2.1 Fault Detection Conditions The mechanism to access the memory imposes constraints on the fault detection conditions that can be satisfied. The constraints with their effects are the following. Notice that a write operation puts data at the Rear address while reads get the data from the Front address. 1. The memory can be accessed in one direction since the indices for front and rear of the queue are always incremented making them move in one direction, as shown in Figure 3.4. FF = 0 EF = I FF = 0 EF = 0 FF= I EF = 0 ■Rear Front Figure 3.4: Empty, Half-full and Full Circular Queues Table 3.6: Conditions for Fault Detection in Queues Fault Type Conditions 12 < t, 1>« Impossible 13 < i. o>„ 1T(.... w l) ftfrl. wO) 14 <i,0>j, Impossible 15 < i. 1>.. Impossible 16 <1, 1>„ ftfrl, wO); ft(tO....) 17 AF1 wO. rO and w l. rl 18 AF2 wO. iO and w l.rl 19 <AF3>„ ft(.... wd) ftfrd. wd!) 20 <AF3>, ft( .... wd) ftfrd. wd!) 21 <AF4>„ ft( .... wd) ftfrd, wd!) 22 <AF4>„ Impossible Fault Type Conditions 1 SA-0 WO.iO 2 SA-1 W l.r l 3 T t f WO. w l.r l 4 1 T F W l, wO. iO 5 < T . ft (.... wO) ft(iO, w l) 6 < T . t>„ ftfrO. w l) f tf r l,...) 7 < 4 -. J > „ ft (.... w l) ft (rl, wO) 8 ftfrl. wO) ftfrO,...) 9 < T . o > „ Impossible 10 <T .0>„ ftfrO. w l ) ; ftfrl....) 11 <t. l>i, ft(.... wO) ft(i0, w l) Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2. The length of a march element can not be longer than two operations with the following possibilities: - Write operation only, after which the Front address in incremented. • Read operation only, after which the Rear address is incremented. - Read followed by write, where both operations occur at the same location only when the queue is full, since the Front and Rear addresses are the same. - Write followed by read, where both operations occur at the same location only when the queue is empty, since the Front and Rear addresses are the same. - Every two consecutive read operations are separated by a write, and every two consecutive write operations are separated by reads. Violating this constraint leads to an attempt to read firom an empty queue or an attempt to write to a full one. With the above constraints, Table 3.6 shows the possible set of conditions that can be satisfied by tests that may be applied to queues. We notice that some faults can not be detected due to the constraints in accessing the memory. Notice also that CFin and CFid faults have the same conditions for covering them. CFid faults also dominate SA, DR, TF and AD faults. So, whenever CFid faults are considered, conditions for dominated faults need not be included. Hence, the test generation process takes less time due to fault dominance. (Notice that Table 3.6 indicates that SOFs can not be detected in queues. However, by alternating the data value of a march test, tests become capable of detecting SOFs. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Examples of such tests can be found in [49] and [55]. This trick for detecting SOFs can be used in other march tests that test constrained and unconstrained memories, possibly saving one read operation. However, there is trade off between reducing the number of operations and more complicated test structure. Systematic exploration of such approaches is beyond the scope of this dissertation.) 3.8.2.2 Test Generation for Queues Using the set of conditions shown in the previous subsection, we are able to generate tests that are shown in Table 3.7 and their fault coverages are shown in Table 3.8. Due to implications of the memory constraints on conditions and test structure, we were able to significantly reduce the complexity of the test generation algorithm. For example, we did not consider any march element that contains more than two operations. Before applying any of these tests, the queue has to be emptied by applying as many read operations as necessary. From the generated tests, we see that our choices are very limited due to the constraints on accessing the memory. The best test we generated is ION test and it covers all the testable faults. Of course many faults cannot be detected as shown in Table 3.6. Notice that new type of march elements that were never used before were helpful in generating optimal march tests. That includes tt(rl, wl) and tt(iO, wO). We included these march elements since they excite some CFds-w faults which do not require a transition for excitation. 78 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 3.7: Generated March Tests for Queues Test Name Test QMT3 ft(wO); ff(rO, wl) QMT4 ff(wO); T T (rO ); ff(wl); tT(rl) MATS ft(wO); tt(iO, wl); ff(rl) SAO-MATS++ fl(wO); 1t(r0, wl); t!(rl, wO); Tt(iO ) QMT9 tl(wO); ft(K), wl); 1t(rl, wl); tt(rl, wO); t!(rO, w O) QMT10, ff(wO); ftfrO. wl); 1t(rl, wl); lT(rl, wO); 1 T (iO , wO); ft(rO) QMTIOz If(wO); 1t(r0. wO); 1 T (iO, wl); ftfrl, wl); ftfrl, wO); ftfrO) Table 3.8: Fault Coverage of Tests Generated for Queues Test SAF DRF* TF ADF CFin CFid CFst CFds-w CFds-r o m QMT3 • 4N QMT4 • • 4N MATS • • • 4N SAO-MATS++ 6N QMT9 • • • • • • • • 9N QMT10, • • • • • • • • • ION QMTIOz • • • • • • • • • ION * DRR; are considered to be covered when a test detects them by adding two delays between march elements. In Table 3.7, we present the shortest test for detecting AD faults. No test for unconstrained memory had such a short length due to the fact that in that case every detectable fault requires more than three operations. We see that QMT4 is easier to implement in BIST because it is uniform, while MATS has higher fault coverage and same time complexity. Our search has proven the optimality of SAO-MATS++, which was presented in [61]. We also report other three new tests, QMT9 that can be used for SRAMs, and QMTlOi and QMTIO2 that can detect all considered unlinked faults. We did not consider linked faults for queues since most linked faults require more than three operations in march elements in order for them to be detected. 79 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.8.3 Stacks It is common to use a part of the memory of a microprocessor or a microcontroller as a stack to store the necessary information, such as the contents of the Program Counter, when a procedure is called [17,31]. Stack based microprocessors rely extensively on stacks [16,24,27]. When a memory is used as a stack, it cannot be accessed but through the Top pointer, as shown in Figure 3.S. The Top index is incremented when a push operation occurs, and decremented when a pop operation occurs. In this structure, a write operation to the memory is equivalent to a push, and a read is equivalent to a pop. In this structure, we can have march elements that consist of only a single operation each, where no consecutive march elements are the same, and MO consists of a write operation (assuming testing starts with an empty stack). The direction of a march element that consists of a write operation is always up while the direction of the other march elements is down, since the Top index is incremented when write operations are applied and is decremented when read operations occur. Table 3.9 provides a list of faults that may be detectable in stacks. Table 3.10 provides two new tests: STK-4 covers all testable faults except TFs, and STK-6 covers all testable faults. Notice that the second march element in MT6 does not provide any fault coverage, however it is necessary due to the memory access constraint mentioned above. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. “Top Top -Top Figure 3.5: Empty, Half-full and Full Stacks Table 3.9: Conditions for fault detection in stacks Fault Type Conditions Fault Type Conditions 1 SA-0 w l.r l 9 < 1 . 0 > i , 1t(w l)tkrl) 2 SA-1 wO. iO 10 <1.0>. It w l)U (rl) 3 DR-0 It(wl) Delay % 1) 11 <i0.1># IT(wO) U(r0) 4 DR-t ff(wO) Delay ttfrO) 12 <rl, 0>„ 1t(wI)U(rl) 5 T t f wO, w l, rl 13 <w0.1>. 1t(w0); U(iO) 6 i T F w l. wO, (0 1 4 <w l.0>. ff(wl); U(rl) 7 <0. l>„ 1t(w0) IkiO) 1 5 AF1 wO. iO and wl.rl 8 < 0 .1>, 1t(wO) IkiO) 16 AF2 wO. iO and wl.rl Table 3.10: Generated March Tests for Stacks Test Name Test MT4 MT6 ft(wO); H (rO ); ft(wl); U(rl); ff(wO); Ji(rO) 3.8.4 Embedded Memories Systems on Chip (SoC) include many cores performing different functions in one chip. Some SoCs include hundreds of embedded memories. In such systems, there may be no direct access to the embedded memories making them difficult to test. It was believed that using the traditional methodology for testing embedded cores, which is scan testing, would not be practical since every step in a march element requires scanning in a new address [7,8]. The trend for testing embedded memories moved to using BIST techniques [1,7, 8,36,60]. However, BIST consumes 81 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 16460514 hardware overhead and applying it concurrently causes severe excessive heat dissipation [3,60]. In this section we describe methodologies that can be used to efficiently apply march tests to RAMs in SoCs. 3.8.4.1 Modified Scan Testing of Embedded memories The main problem with scan testing is the need to shift a new address every time a march element is applied to a particular location. Such application will require long test time. As mentioned in Chapter 1, any address order can be used as the ft direction for a march element, and its opposite order is the U direction. Since march tests do not impose any restriction on the order in which the addresses are traversed, we can use sequences generated by LFSRs. An LFSR with primitive feedback polynomial generates a new valid address per shift and covers the entire address range, except the all zero address. This methodology is described in [9] and [19]. It results in a significant reduction on test time since it shifts a new address per clock cycle. 3.8.4.2 Usage of Microprocessor for Testing the RAM In this methodology, the microprocessor, which is one of the cores in an SoC, is used to test the memory modules [28]. This methodology does not require extra overhead and tests the memory modules at speed. We have used this methodology in testing the internal cache as will be shown in the next chapter. One of the drawbacks of this methodology is the fact that it is applicable only to systems that have microprocessor core, which is always the case for cache memories. 82 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.9 Comparison With Previous Work Only two methodologies for automatic generation of march tests have been presented in the literature. The first methodology is Goor’ s methodology presented in [51] and [52]. The second one is Kamran ’ s methodology presented in [58]. Both methodologies use the same fault representation, which uses fault matrices that describe the behavior of the correct and faulty memory. Table 3.11 shows the representation of a fault-free memory. Table 3.12 shows the representation of <T; t>ij CFin fault. Such a fault representation does not give explicit information about faults. The matrix needs to be carefully processed in order to extract from it the necessary information about faults, such as their excitation requirements and the faulty values. For example, the matrix representation of CFin does not explicitly Table 3.11: The Representation of a Two-cell Fault-Free Memory State CiCj Next State Output W jO Wil W jO Wjl n fj 00 00 10 00 01 0 0 01 01 11 00 01 0 1 10 00 10 10 11 I 0 11 01 11 10 11 1 1 Table 3.12: A Two-cell Memory with <T; CFin Fault State CiCj Next State Output W jO Wjl W jO Wjl n T j 00 00 1 1 00 01 0 0 01 01 10 00 01 0 1 10 00 10 10 11 l 0 11 01 11 10 11 i 1 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. <=>(w O ); tt(iO, wl, wO, wl, wO); < =>(iO ), MO M l M2 Figure 3.6: A March Test Wrongly Generated for Detecting CFin Faults »(wO); ft(ri), wl, wO, wl); tt(rl, wO, wl, w O , wl, wO); 1t(rO, wl, wO, wl), MO Ml M2 M3 Figure 3.7: A March Test that Detects CFid but not <T, !> CFin Faults state the fact that even number transitions at the coupling cell removes the fault effect since it inverts the coupled cell for even number of times. Figure 3.6 shows a test generated using this methodology and published in [51] and [52] as a test for detecting CFin faults that actually fails to detect any CFin fault. On the other hand, Kamran’s methodology defines primitive faults, which are faults excited by a single write or read operations, and describes other faults using the primitive faults. This methodology also does not represent CFin faults correctly. It defines CFid faults as primitive faults then claimes that detecting CFid faults guarantees detecting CFin faults. However, the test shown in Figure 3.7 is actually capable of detecting CFid but not <T, |> CFin faults. The problem is that CFin faults have a special characteristic, as mentioned above, that make an even number of transitions at the coupling cell mask the fault. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. <?, I>ij: 00 — > 10 [rj] or 01 — > 11 [rj] <T, t>ji: 00 — > 01 [rj] or 10 — > 11 [rj] <1, I>ij: 10 — > 00 [rj] or 11 — > 01 [rj] < i, I>jj: 01 — > 00 [rj] or 11 — > 10 [rj] Figure 3.8: Possible Transitions for Detecting CFin Faults < = > (w 0 ); 1t(r0, wl, rl, w O ); < = > (rO ); 1t(iO , wl); «(rl); 1t(rl, w O , rO , wl); «(rl); -U-(rl, w O ) M O Ml M2 M3 M4 M5 M6 M7 Figure 3.9: March M Test Both methodologies depend on the transition sequence for detecting faults. Figure 3.8 shows the possible transitions for detecting CFin faults. The methods’ dependence on the transition sequence limits the types of faults that can be covered to those excited by transitions. This excludes many faults like AD, SOF, CFst and others. Goor’s methodology provides incomplete sets of conditions for detecting faults that are not excited by transitions. No systematic approach has been outlined even for the generation of these incomplete conditions. In fact, it seems that their conditions are not generated by using their fault representation but through the experience of the authors. Goor’s methodology has additional drawbacks. It does not cover the entire search space, which is necessary for proving optimality of march tests. It ignores tests that contain intermediate march elements consisting of a single read operation, despite Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. the fact that such march elements are part of powerful published tests, such as March M shown in Figure 3.9. Proving optimality of a march test requires studying march tests containing such march elements. Also it ignores tests that have intermediate march elements that start with a write operation without proving that an optimal march test could not contain such march elements. Furthermore, it assumes that every test starts with MO that consists of a single write operation. We have shown in Table 3.1 new superior march tests that start with march elements consisting of two write operations. This methodology for test generation could have found such superior tests if it extended its search space to include tests with multiple-operation march elements as MO. In addition, Goor’s methodology enumerates partial tests in a breadth-first manner and does not use any weight function as a branching criterion. This methodology cannot benefit from any branching or bounding criterion and can only prove optimality of a test by explicit enumeration! Also, in searching for tests, it expects the user to give an upper bound for the depth of the search tree. While the user may make a wrong decision in choosing an upper bound, such a bound is critical since some branches of the tree may grow to infinity. In addition, the size of the tree grows exponentially as the number of involved cells increases. By implementing this methodology, we found out that it requires 70,724 nodes in the search tree for generating the March C- test assuming that the user entered the correct test length (T=I0) for generating this test. The number of nodes grows exponentially as the user enters higher number for the maximum test length. On the 86 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table 3.13: Drawbacks of Goor’s and Kamran’s Methodologies Goor’s Methodology K am ran ’s Methodology • Does not detect CFin faults • Can not represent some faults • Does not generate all optimal tests • Does not cover the necessary search space for optimal tests • High time complexity • Search tree grows to infinity • Generates tests with redundant operations • Does not detect CFin faults • Can not represent some faults • High time complexity • Generates tests with redundant operations • Generates same test through different paths other hand, the new methodology does not depend on the user input and generates only 22,503 nodes. Kamran’s methodology is inefficient since it generates the same test several times. It does not have a mechanism to identify such duplication at early stages making it impossible to avoid paths that generate the same tests or equivalent tests. Table 3.13 summarizes the drawbacks of both Goor’s and Kamran’s methodologies. The methodology presented in this dissertation is able to avoid redundant nodes by maintaining the list of uncovered faults. By using the properties of march tests, it also avoids redundancy resulting from generating a test multiple times. It uses depth- first search in conjunction with a weight function to find an efficient test early in the search. Subsequently, it uses the length of the shortest test generated as the upper bound for the rest of the process. The efficiency of this approach is clearly demonstrated by its ability to generate new tests and to prove optimality of some of the old ones. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.10 Summary We have presented in this chapter a methodology for generating optimal march tests. We used the methodology to: (a) generate new optimal tests that are uniform, which are desired to simplify BIST architecture, (b) prove the optimality of some well- known tests such as March C-, and (c) generate a complete set of optimal march tests for different combinations of faults. We were able to successfully generate optimal march tests for all linked classical and extended fault models, except CFds-r which is not realistic when SRAMs are considered. We have also provided a set of march tests for constrained memories including unidirectional memories, queues and stacks. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 4 4 Cache Testing Today’ s typical system delivers performance partially by relying on a large capacity memory subsystem, which includes one or more levels of cache memories. Since the fault-free operation of the memory subsystem is crucial to the optimal operation of the system, periodic testing of the memory subsystem, say, during each system boot, is considered essential. While any of the large number of tests developed for off-line testing of memory chips [41] can be easily adapted for in-system testing of single level memory systems, considerable modifications are required before these tests can be used for in-system testing of caches. The objective of our research is to develop in-system tests for caches that (i) provide high fault coverage, (ii) have short test application times, and (iii) require little or no modification to the design of the memory subsystem. The targeted tests are transformed from the known off-line tests to make them work efficiently for caches. 4.1 Previous Work A large number of memory tests with varying test time complexities and fault coverages have been developed for off-line testing of memory chips [41]. In [S3], 89 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. one of these tests, namely the March B test, has been transformed into an in-system test of cache tags. In [34], a transformation methodology is proposed which when applied to the March B test results in the test given in [53]. It was assumed that the data part of the cache can be easily tested, as mentioned in [53] and [34]. Hence most effort was expended in adapting the March B to test the tag part of the cache. The difficulty arises due to the low observability of cache tags -- an incorrect tag value can only be observed indirectly - via a read that causes an unexpected cache miss and causes the memory subsystem to supply the data from the main memory. Any error in a tag value can only be observed if the data obtained in this manner is different from the data that would have been read from the cache if the tag value was error free. The method proposed in [53] adapts the March B test to test for address decoder, stuck-at, transition, and coupling faults in tags of a direct mapped cache, assuming that the cache hardware is modified so that the cache can be disabled to provide direct access to the main memory. The complexity of this test is 33NTM + 17NTc, where N is the number of block frames in the cache and Tm and Tc are respectively the main memory and the cache access times. Assuming that the data part is easy to test, we present an efficient methodology to test the tag part. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4.2 Cache Model The cache considered in this paper is write-back/read-through direct mapped or set associative cache [13]. Each block frame of a write-back cache has a modified bit that is set when a block is modified; if this bit is set, then the block is written back to the main memory when it has to be replaced. Note that, for the same address, the main memory and cache can have different data values before the modified data is replaced. The read-through feature enables the processor to obtain data directly from the main memory when a cache miss occurs. A direct mapped cache consists of tag and data parts, as shown in Figure 4.1. The least significant bits of the address are used to select a cache block frame, a, while the remaining bits are compared with the tag value of the selected block to identify a hit or miss. This addressing strategy maps consecutive N blocks of the main memory Block# Tag Tag Modified bit Data i r Comp. ) Hit/miss? Figure 4.1: Direct Mapped Cache 91 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. (where N is the number of block frames in the cache) with the same highest address bits (tags) to consecutive cache block frames. We call such blocks of data a cache page and refer to it by the unique tag field value, which will be denoted by A or B. (Note that the proposed approach can be directly used for cases where each cache block frame has multiple words.) Set associative cache designs are very popular in computer systems. A K-way set associative cache consists of K cache modules, each one of them is like a direct mapped cache containing N block frames. Figure 4.2 shows the structure of a two-way set associative cache. The fully associative cache design is a special case of the set associative one with K equals the total number of block frames in the cache, so we can choose any block frame as a target for replacement. In this type of caches, a block can be mapped to a set of block frames instead of a single block frame. It becomes important to have a replacement policy to decide which block frame in a set to replace. In our study, we will consider caches with a deterministic replacement algorithm, such as First-In-First-Out (FIFO), Least-Recently-Used (LRU) or Least Frequently Used (LFU) [15]. With such replacement algorithms, we can select the target block frame in the cache for replacement by satisfying the replacement algorithm’s conditions. In real systems, main memory does not occupy the whole address space due to the high cost of buying unnecessarily large memory. However, the cache design is supposed to function with the presence of different main memory sizes giving the Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Index Tag Value Module 2 Module 1 Tag2 Data2 Tagl Datal Tag2 Data2 Tagl Datal Tag2 Data2 Tagl Datal Hit/miss? Comp. Figure 4.2: Two-Way Set Associative Cache user the ability to add extra memory when needed. For this reason, it is possible that the highest bits of the tag field are not used. These bits are assumed to be zero during the tests discussed in this dissertation and consequently neglected. In our study, we consider the classical fault models in both linked and unlinked forms. 4.3 Efficiency Considerations For Tag Testing One of the important considerations in developing an efficient cache test is minimizing direct and indirect main memory accesses. A direct main memory access 93 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. occurs when a cache miss occurs during a read operation. This causes the processor to wait until it gets the data from the main memory, which increases the time complexity of the test. An indirect main memory access occurs during write misses that require moving the data in a modified block to the main memory. There is no way to eliminate the time penalty of direct main memory accesses but a write buffer can, to a limited extent, decrease the time penalty of indirect accesses. A good test must minimize both direct and indirect memory accesses. The test should also be designed to be applicable with minimal or no modification of the existing cache hardware while taking advantage of all its features. The need for hardware modifications may make the test inapplicable to memory systems that are already in use. Even in the case when a cache design can be modified, extra chip area is required to add the required hardware features which increases the memory cost. Restricting the tests to use only standard cache operations automatically eliminates any need for hardware modification. 4.4 Tag Test Transformation Framework Normal memory tests detect faults by writing a certain value to a location and then reading it, expecting to get the value that was written earlier. While this method can be applied to test the data part of a cache, it cannot be applied directly to test the tag part, since a tag can not be read from or written to directly. A value can be written to Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. the tag indirectly by accessing a certain memory location. For example, 001100 can be written to the tag field of a certain block frame a by accessing the memory location [001100, a]. Observing the tag Held of a cache is significantly more complicated. Since a cache miss occurs when the tag value stored in the cache does not match with the address of the location accessed by the processor, satisfying the following two conditions is sufficient for detecting a fault that must have altered, at the particular time, the value of a particular tag field: 1. The main memory location corresponding to a tag value should have a data value that differs horn the expected fault-fiee data value in the corresponding cache location. 2. A read operation should be performed to obtain the data from the cache location. If the tag value is erroneous, a cache miss will occur due to a mismatch between the correct and the erroneous tag, and the data will be fetched from the main memory location. Without loss of generality, assume that the main memory can store only one bit (0 or 1). The following is an example of a set of steps that satisfy the above conditions: • Initially, the main memory location contains an unknown value, x. A tag frame a has a SA-1 fault. • Write a 1 to the address [A, a] — this will be written in cache block frame with index a, where tag value will be A = 00...0 and data value will be 1 . • Read from address [A, a]. Since the tag part of block frame a has a SA-1 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. fault, that causes the tag value to be different from A, a cache miss will occur. • If currently, the data in memory location [A, a] is 0, then the fault will be detected, since zero will be read from the memory instead of 1 from the cache. (Since the initial state of the main memory is assumed x, appropriate steps must be taken to ensure that the value of this main memory location is 0 before this operation is performed.) • By repeating the above steps with data value 0, this fault can be detected in the case when the initial data in the memory location [A, a] is 1. 4.5 The Transformation Methodology 4.5.1 The Transformation Steps Notations: • A = aoa( ... a „ is a given binary tag value and B is the one’s complement of tag A. For simplicity, we assume A = 00.. .0 and B = 11... 1 . • In the following tests, w([A, a ] , 0) denotes write 0 to the address [A, a], where a is the index of the block frame under test. • r([A, a], 0) denotes read the address [A, a], expect the value 0. • Mdata[A, a] refers to the main memory contents at address [A, a], while $Data[A, a] refers to the cache contents at the same address. 96 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. • ME)ata[A, a] refers to the main memory initial contents at address [A, a]. • A march element is a set of consecutive operations performed at a block frame before moving to the next block frame, such as tt{w([A, a], 0), w([B, a], 0), w([A, a], 1), r([A, a], 1)}. In all tests, we will name the march elements as MO, M l, M2, and so on. • It is the direction of a march element and indicates that a traverses through all possible block frames in some order. It indicates a traversal of all block frames in an order that is opposite of tt. < = > indicates a traversal of all block frames in either of the two directions. Assumptions: 1 . The data part of the cache is fault free. This is easy to justify since the data part of a cache is easy to test and consequently can be assumed to have passed the tests. 2. 00...00 or 11... 11 is returned when a non-existing memory location is accessed due to a fault. 3. For simplicity, we assume that II traverses block frames in the order 1, 2,..., N. A normal test can be modified for in-system testing the tag part of a cache in the following manner. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. a. March tests usually start with the initialization step tt(wO). If this step exists in the original test, modify it to be 1t{w([A, a], 0), w([B, a], 0), w([A, a], 1)}, otherwise add this initialization march element. b. For the rest of the original march test, replace each: • w O by w([A, a], _ ) , • wl byw ([B ,a],_), • rO by r([A, a ] , ), and • rl byr([B, a ] ,__). c. Add appropriate data values to the above operations in such a way that two consecutive write operations to the same address have opposite data values and each read operation has the data corresponding to the last write to the same location. d. If transition faults linked with coupling faults are targeted, then select any two consecutive writes to address A and add following each of them corresponding reads such that each write with the corresponding read are in the same march element. Do the same to operations on address B. Example: March X algorithm [1] is 6N memory test given by: flX w O ); tt(rO, wl); li(rl, wO); U(r0), M O M l M2 M3 98 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Following the above steps, the test results in the following form. tl{w([A, a], 0), w([B, a], 0), r([B, a], 0), w([A, a], 1)}; M O tT{(r[A, a], 1), w([B, a], 1)}; li{(r[B, a], 1), w([A, a], 0)}; U{r([A, a], 0)}. M l M2 M3 We will show in the following section that the above transformation preserves the fault detection capability of the original memory tests. Step d. above is necessary to cover transition faults independent of the initial data in the main memory locations, which must be assumed to be unknown. 4.5.2 Fault Detection Capabilities of Transformed Tests We assume that the original march test to be transformed has the following properties. These assumptions are satisfied by all the commonly used march tests. Al. Every march element, except M0, starts with a read operation. A2. No two consecutive write operations use the same data value. A3. Every march test has at least two write operations, one of which may be replaced by the initialization march element, M0, proposed as a part of the transformation. A4. Adding read operations to a march test does not change its capability to excite a fault but may increase its fault coverage. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Also, we assume the presence of the following memory design feature. A5. In case of replacement with the presence of faults, the index part of replacement address comes from the address register, so only a location in the main memory with the correct index will be the target for replacement. Lemma 4.1: No two consecutive writes in a transformed march test use the same address. Proof: The transformation changes each wO in the original march test to w[A, x] and wl to w[B, x]. A2 states that no two consecutive write operations shall have the same data in the original tests. Together, the above facts cause alternation in the address value of the write operations in the transformed tests. ■ Lemma 4.2: Stuck-at (SA) faults in one or more bits of a cache tag prevent the changing of the initial value at the corresponding main memory locations in pages whose addresses have bit values opposite to the S A value at the faulty bit. Proof; Note that in a write-back cache data is written to a main memory location only via replacement. Without loss of generality, let bit i of the tag part of block frame a have a SA-1 fault. When a write operation is done to location [A, a], the faulty bit will Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. stay at 1 instead of 0. So, when the replacement occurs later, the data in the block frame a is written to the main memory location A* (where A‘ has 1 at bit i instead of 0) instead of location A. ■ Lemma 4.3: In a transformed test, there exists an operation with address [A, a] (read or write) preceding every write operation with address [B, a] in the same march element. Proof: A write operation to address [B, a] can not occur at the beginning of a march element due to Al. Therefore, it must follow an operation to address [A, a] since (a) it can not follow a write operation to the same address due to Lemma 4.1, and (b) it can not follow a read operation to the same address since that would be useless. ■ The above property is also true for write operations to address [A, a] except the w([A, a], 0) in M O. Lemma 4.4: In the absence of any fault, every read operation of the transformed test occurs while the cache location being accessed has a different data value than the corresponding main memory location, except if the read operation follows the first two write operations in M O . 101 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Proof: The correctness of the lemma follows from the following. 1. No two consecutive write operations are directed to the same address. 2. The structure of the transformed tests requires alternating the data part for consecutive writes to the same address. Each write operation causes a cache miss and a replacement since it has a different address than the proceeding write operation (from 1). Also, data that is different from that in the corresponding location of the main memory is written in the cache with each write operation (from 2). So, after each write operation, the main memory location has different data than the corresponding cache location. Consequently, read operations, which always occur after write operations, occur while the main memory location has different data than the corresponding cache location. ■ Example: Consider the sequence: w([A, a], 0), w([B, a], 0), w([A, a], 1), r([A, a], 1). The second write operation causes a cache miss making MData[A, a] = 0. The third write operation causes another cache miss and it sets $Data[A, a] = 1. Therefore, the read operation occurs while the corresponding cache and the main memory location have complimentary data. Lemma 4.5: In the absence of any fault, the transformed tests apply to the tag part of the cache the same sequence of transitions as the original tests apply to the main memory, with exception of the transitions in M O . 102 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Proof: The lemma follows from the fact that each w O in the original test is replaced by w([A, a], d), where A = 00...0, and wl is replaced by w([B, a], d), where B = 11... 1. ■ 4.5.2.1 Conditions of Stuck-at, Transition and Coupling Fault Detection A test must satisfy the following conditions to guarantee detection of certain faults. C l. The existence of the four combinations of writes using addresses A and B and data values 0 and 1 — along with the corresponding reads is sufficient to detect SA faults, even in the presence of all possible types of faults except address decoder faults. Proof: Consider the two possible faults, namely SA-0 and SA-1. 1. Assume bit i of tag frame a has a SA-0 fault while any other bit may have any type of faults except address decoder faults: • Case 1: Main memory initially has 0 at location [B, a], i.e., MIData[B, a] = 0. In this case, by Lemma 4.2, MIData[B, a] will never be changed. Con sequently, the fault will be detected by w([B, a], 1) followed by r([B, a], 1). • Case 2: MIData[B, a] = 1: As above, the fault will be detected by w([B, a], 0) followed by r([B, a], 0). 103 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 2. Assume bit i of tag frame a has a SA-1 fault while any other bit may have any type of faults except address decoder faults: Case 1: MIData[A, a] = 0: As above, the fault will be detected by w([A, a], 1) followed by r([A, a], 1). Case 2: MIData[A, a] = 1: As above, the fault will be detected by w([A, a], 0) followed by r([A, a], 0). ■ C2. Given that a transformed test starts with the initialization step, T T {w([A, a], 0), w([B, a], 0), w([A, a], 1)}, the existence of the four combinations of writes using addresses A and B and data values 0 and 1, along with the corresponding reads is sufficient to detect unlinked transition faults (TFs), even in the presence of all possible types of faults except SA faults and address decoder faults. Proof: Assume bit i of tag frame a has a transition fault: • t unlinked TF behaves exactly like a SA-0 fault since the test starts with w([A, a], 0). Consequently, it is detected even if other bits of the same tag have i or T unlinked TFs. • The only case that needs to be covered is 1 unlinked transition fault at bit i without the presence of T TF at any bit location. Two subcases can be considered. 104 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 1. Bit i is initially 1: Transition fault behaves like SA-1 fault and is detected as above. 2. Bit i is initially 0: w([A, a], 0) in the initialization march element will proceed correctly. w([B, a], 0) will then occur and 0 will be written to address [A, a] in the main memory due to replacement. Then the fault behaves like SA-1 with MIData[A, a] = 0 and is detected under the above conditions as proven in Cl. ■ C3. Assuming there are no SA faults or unlinked transition faults in the cache tags, transition faults linked with coupling faults (but not linked to address decoder faults) are detected by any test that contains the aforementioned four combinations of writes and corresponding reads that satisfy the following additional conditions. (1) Each read operation and the corresponding write operation should be in the same march element, and (2) Of the aforementioned four write operations, the two writes to an address should be consecutive, i.e., the above two writes to address A that have corresponding read operations should not have a third write operation to A between them. The same should also be true for the above writes to address B. Proof: The condition for address A can be satisfied in one of the following three ways: a. w([A, a], 1), r([A, a], 1), w([B, a], 1), w([A, a], 0), r([A, a], 0) 105 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. b. w([A, a], 0), r([A, a], 0), w([B, a], 0), w([A, a], 1), r([A, a], 1) but the sequence is not the beginning of the transformed march test. c. w([A, a], 0), r([A, a], 0), w([B, a], 0), w([A, a], 1), r([A, a], I) and the sequence is the beginning of the transformed march test. The condition for address B can be satisfied in one of the following two ways d. w([B, a], 0), r([B, a], 0), w([A, a], 1), w([B, a], 1), r([B, a], 1) e. w([B, a], 1), r([B, a], 1), w([A, a], 0), w([B, a], 0), r([B, a], 0) Since M0 starts with w([A, a], 0), the distinction between cases b and c becomes possible. This is not the case for B. Any two consecutive write operations of the above sequences can be in different march elements and the sequence may contain additional read operations, resulting with several complicated sequences. For example: The sequence in (a), namely w([A, a], 1), r([A, a], 1), w([B, a], 1), w([A, a], 0), r([A, a], 0), can take any of the following forms: • the entire sequence is contained in one march element ... { ..., w([A, a], 1), r([A,a], 1), w([B,a], 1), w([A, a], 0), r([A, a], 0 ) or 106 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. • the sequence is divided among three march elements ...{ ..., w([A, a], 1), r([A, a], 1)} {r([A, a], 1), w([B, a], 1), r([B, a], 1),} {r([B, a], 1), w([A, a], 0), r([A, a], 0),... } ..., or • four march elements ...{ ..., w([A, a], 1), r([A, a], 1)} {r([A, a], 1)} { r([A, a], 1), w([B, a], 1), r([B, a], 1),} {r([B, a], 1), w([A, a ],0), r([A, a], 0),... }..., and so on. Notice that the direction of the march elements is ignored since it is not of any importance in the following proof. Also notethat any number of read operations can be added. Definition: The faulty value of a bit with a transition fault is the value that the bit fails to change from. It is 1 for i TF and 0 for T TF. The detecting operation for a fault is the first read operation where unexpected value is obtained for a cache with the fault. Now, we will show that the presence of any of the abovementioned five basic sequences, (a) to (e), or any of their possible expansions will detect any bit i with a i TF linked with CFs. Notice that the three important points in testing this fault are: 1. the faulty bit of the tag should have a faulty value before the detecting operation is applied, 2. the main memory data for the address with the faulty value for the faulty bit Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. should not be changed from its value at the beginning of the basic sequence, and 3. operations in the same march element can not be affected by coupling faults since other locations are not changed while a march element is applied to a specific location. Detection of 1 transition faults: Assume bit i of tag frame a has a 1 transition fault linked with coupling faults and other bits may have SA, transition and coupling linked or unlinked faults but not address decoder faults. Notice that having a T transition fault in any bit will not invalidate the following proof since it only depends on the effect of I transition fault on write operations to address A while T transition fault has no effect on those operations. a) First basic sequence is w([A, a], 1), r([A, a], I), w([B, a], 1), w([A, a], 0), r([A, a], 0). Since this sequence of operations must be proceeded by at least MO, there exists an operation on address B which is in the same march element as w([A, a], 1) that proceeds this sequence and sets bit i to 1 (Lemma 4.3). The following two cases exist after applying w([A, a], 1): • MData[A, a] = 0: r([A, a], 1) will detect the fault. Note that C3 requires this read operation to be in the same march element as w([A, a], 1), and consequently no coupling fault will be excited. • MData[A, a] = 1: r([A, a], 0) will detect the fault. Note that MData[A, a] will 108 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. not be changed by the operations between w([A, a], 1) and r([A, a], 0) even if coupling faults existed, since the data value for those operations are the same as MData[A, a]; consequently replacement with a wrong address will not change MData[A, a]. Also, a coupling fault affects the sequence between the last two write operations only if they were in two different march elements. In this case, by Lemma 4.3, w([A, a], 0) follows an operation on B within the same march element. Consequently, bit i is guaranteed to be set to 1 before r([A, a], 0), which follows w([A, a], 0) in the same march element by C3, occurs leading to a cache miss. b. The second basic sequence w([A, a], 0), r([A, a], 0), w([B, a], 0), w([A, a], 1), r([A, a], 1) and its first operation is not the beginning of a transformed match test. This case is similar to the above. c. The third basic sequence w([A, a], 0), r([A, a], 0), w([B, a], 0), w([A, a], 1), r([A, a], 1) and its first operation is the beginning of a transformed test. Since this sequence represents M0 and falls in one march element, coupling faults have no effect. There are two initial cases for bit i and the other bits with a 1 TF fault: • All bits with a 4 TF fault are 0: The first write operation will write the address A and the data 0 in block frame c l The following read operation would be a cache hit and will not detect the fault. The second write operation will cause a replacement setting MData[A, a] to 0. The third write operation will occur 109 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. while MData[A, a] is 0 and bit i is set to 1, so bit i will not be set to 0 because of the fault and the last read operation will cause a cache miss and unexpected data from the main memory will return. The fault will be detected. • At least one of the bits with a i TF is initially 1 and MIData[A, a] = 0: The first write operation will not occur correctly and replacement resulting from the first read operation will occur to a wrong address A’ . The second write operation will cause a replacement to location A’ . However, the fault will be detected by the second read operation, just as in the above case. • At least one of the bits with a i TF is initially 1 and MIData[A, a] = 1 : r([A, a], 0) will detect the fault since a cache miss will occur and the main memory will supply the data as 1 while 0 is expected. Detection of T transition faults: Assume bit i of tag frame a has a T transition fault linked with coupling faults while no tag bit has a 1 transition fault. We will show that both the basic sequences (d) and (e) are able to detect it. d. Same as above, assume we have the sequence w([B, a], 0), r([B, a], 0), w([A, ot], I), w([B, a], 1), r([B, a], 1) in a march test such that the conditions mentioned in C3 are satisfied. The following two cases may exist. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Case 1: MData[B, a] = 0 after applying w([B, a], 0): • Replacement resulting from w([B, a], 0) sets MData[A, a] to 0, since the transformation ensures that the operation before it writes A in the address part, since no bit has a 1 TF, and 0 as data. We will see that this fact is important for detecting any possible coupling faults that may mask the transition fault. Notice that if address A in w([A, a], 1) is changed to B due to coupling faults, then a replacement will change MData[B, a] to 1 making the initial assumption, and consequently the remainder of the proof, invalid. • Replacement resulting from w([B, a], 0) and w([A, a], 1) will not change MData[B, a] or MData[A, a] since all replaced frames have the same data value as the main memory value at those locations, namely, 0. So, even if the first two write operations are in different march elements, the main memory contents at those two locations will not be changed. • If no coupling fault exists or the last two write operations are in the same march element, then replacement resulting from w([B, a], 1) will not change the 0 value in MData[B, a], since the replaced address is A due to the fact that no i TF is present. Also, w([B, a], 1) will write B’that differs from B due to the fault. Consequently, r([B, a], 1) will detect the fault, since it will cause a cache miss and the main memory will supply 0 from MData[B, a] while 1 is expected. • Assume the last two write operations are in different match elements. After w([A, a], 1), if A becomes A’due to coupling faults, this coupling fault will be in Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. detected by the second match element since, by A l, it certainly starts with r([A, a], 1) while MData[A, a] still has 0. Case 2: MData[B, a] = 1: r([B, a], 0) will detect the fault. e. Assume we have the sequence w([B, a], 1), r([B, a], 1), w([A, a], 0), w([B, a], 0), r([B, a], 0) in a march test. This is same as the above case, changing every 0 to 1 and every 1 to 0. ■ Lemma 4.6: The transformation preserves the coupling faults’detection capabilities of the original tests, assuming no stuck-at, transition and address decoder faults are present. Proof: Without loss of generality, consider a block frame a for detection of coupling faults. • Since we assume there is no stuck-at, transition and AD faults, the initialization is done successfully in terms of initializing the main memory. That is true because: 1. the coupling faults do not have an effect on the operations in the same march element, and 2. M0 starts with a write operation that masks prior effects of a coupling fault. • If applying M0 or M l to any other block frame changes a bit in block frame a after applying M0 on a, then the fault will be detected by the read operation in 112 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Ml when applied on a. This is true since MData[A, a] differs from $Data[A, a] (Lemma 4.4) and the effect of the coupling fault will lead to a cache miss. • If no fault was detected by the read operation in M l, then at the beginning of Ml, MData[A, a] and $Data[A, a] contain the expected data. • Applying Ml to block frame a has the same excitation effect as the original test’ s march element M l, by Lemma 4.S. ■ In general we have the following two facts: 1. Each march element in the transformed test has the same excitation power as the corresponding march element in the original test. 2. The march elements of the transformed test have the same detection capability as the original tests. This capability is due to the first read operation in the march element. We do not need to show detailed proof for the different types of coupling faults since the above proof shows that the original test and the transformed test have the same excitation and detection powers, regardless of the type of the coupling faults. 4.5.2.2 Conditions for Address Decoder Faults Detection We will handle two cases: Unlinked address decoder faults and linked address decoder faults. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. A. Unlinked address decoder faults C5. The detection of unlinked address decoder faults in a memory requires the satisfaction of the two conditions satisfied by the presence of two march elements with the following structure: MCO: 1T(rx,..., wx!). MCI: ii(rx!,..., wx). A test obtained by transforming a memory test that satisfies these conditions and has the aforementioned four write operations and the corresponding reads in the resulting test is guaranteed to detect the cache address decoder's faults. Proof: Since the original a test contains the above two march elements, the transformed test will contain the following: From MCO: ft{r([X, a, xl) w([X!, a], x2)} - MTO From MCI: U{r([X!, a], x3).......w([X, a], x4)} - MT1 where the data values xl, x2, x3 and x4 are as defined by the transformation. X = A or B. We handle X = A and X!=B; the proof for the second case is similar. So, the march elements MTO and MT1 have the following form: 114 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. MTO: tt{r([A, a], x l ) , w([B, a], x2)} MT1: U{r([B, a], x3),w([A, a], x4)} We will now show that these two inarch elements, along with the four reads and their corresponding writes, are sufficient for detecting unlinked address decoder faults. In unlinked address decoder faults, the tag frame a is a target for only one address decoder fault and no other fault affects it. However, it is possible to have other faults in other tag frames and tag bits. We pay attention to tag frame a since it is the key for address decoder fault detection. Faults AF1 and AF2 are the same as SA faults since we assume that a constant value returns from any invalid address (address [A, a] in this case). Consequently, they are guaranteed to be detected by a test that contains the aforementioned combinations of reads and writes. Now, we assume fault AF3 or AF4 is present in the cache tag part decoder. The following shows these faults will be detected, with the assumption that the location in the main memory corresponding to index a contains the fault-free value before applying M TO and MT1: Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. In MTO (P < a): • MTO will be applied to P first. • Based on the memory design feature (MDF), location [X, a] in the main memory will not be affected by replacements occurring because of applying MTO to block frame p. • When applied on block frame P, MTO will change the tag value of block frame a from A to B because of the existence of the fault. When MTO is applied on a, a cache miss will occur when the read operation takes place, and the main memory will give an unexpected value. Consequently, the fault will be detected. Notice that the main memory has a different value than the expected value by Lemma 4.4. The case of (P > a) is the same as above except we replace MTO by MT1. For the proof to be complete, we need to study the behavior of the march elements that are applied before MTO and MTI. We need to be sure that the presence of any march element before them will either end with the expected fault-free value at MData[A, a] or an AD fault will be detected. The following lemmas prove this fact and hence complete the proof. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. For the coining proof, notice that only operations with index a can change the value of MData[A, a] due to the MDF property. As a result, we ignore the effect of applying a march element to the rest of the locations after it is applied to index a. Lemma 4.7: By the end of applying MO to location a, MData[A, a] will have the expected error-free value. Proof: The lemma follows from the following observations: 1 . If P is visited before a, then the fault will not lead to any erroneous behavior since no known initial value is assumed at locations corresponding to a in the cache and the main memory. Consequently, by the end of applying M O to location a, MData[A, a] will have the expected value. 2. If (5 is visited after a, then MData[A, a] will not be changed due to the MDF property. ■ We need to show that Ml ends with the correct value in MData[A, a] or it detects the fault. Based on the second march element direction, a and P will be visited in one of the two sequences: either P is visited before a , or vice versa. Lemma 4.8: By the end of applying M l to location a, MData[A, a] will have the expected error-free value, or Ml will detect a fault. 117 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Proof: Case 1 : Location (3 is visited before a. If the fault has changed the tag or data values of location a in the cache, then the fault will be detected by the first read in Ml since a cache hit leads to reading the erroneous value and a cache miss leads to reading the main memory value which is fault free (Lemma 4.7) and differs from the expected value (Lemma 4.4). Otherwise, the cache contains the error-free values at location tx, and consequently Ml operates on index a starting from error-free values leading to error-free values in MData[A, a] by the end of applying Ml to index a. Case 2: Location (3 is visited after a. Same proof as in Case 1 holds here. So, Ml ends with the correct value at MData[A, a] in all possible cases. The proof for M2 and the other march elements occurring before MTO and MT1 is same as the proof for Ml. Hence, we are certain that the march elements before MTO and MT1 either detect the faults AF3 and AF4, or end with the error-free value at MData[A, a ] .l B. Linked Address decoder faults The first two types of faults (AF1 and AF2) are identical to SA faults. So, they will be detected by any test that detects SA faults. We have seen that SA faults can be detected with the presence of other faults except AD faults. Consequently, these two types are covered when no other address decoder fault is linked with them, but any other type can be linked to them. 118 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Now, we will handle the possible combination of faults. (a) We may have a SA fault at cell Ca that will be detected even if an AD fault of type AF3 or AF4 affects Ca, since the part of the test that detects S A faults will be able to detect the SA fault. This is also the case when AF1 or AF2 are linked with AF3 or AF4. (b) If Ca has aTF linked with any AD fault of type AF3 or AF4, then the fault is detected if TFs linked with CFs are detected. The proof is the same as the proof of C3. (c) If Ca has a coupling fault linked with an AD fault, then one of them will be detected, as proven in [9], (d) If Ca has any type of fault besides an AD fault, then detection depends on the case of Ca as mentioned above. Changes in cell Cp are not important since we depend only on erroneous effects on cell Ca, which have already been proven to be sufficient. Consequently, AD faults linked with other faults are detected. Also, AF1 and AF2 linked with AF3 and AF4 are detected. It is obvious that AF1 linked with AF2 is actually AF2, and AF3 linked with AF4 can be proven to be detected by MT1 and MT2 using proofs that are similar to those for unlinked faults. However, the fault shown in Figure 4.3 is undetectable since the values returned from both locations a and 0 are unknown. More details about this type of faults is given in [1]. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. a P > Cp Figure 4.3: Uncovered Address Decoder Fault 4.5.23 Fault detection Capabilities of Transformed Tests Theorem 4.1: The transformed tests preserve the fault detection capabilities of the original tests by adding necessary read operations. Proof: 1. SA faults and unlinked transition faults can be detected by any test since we are guaranteed to have at least four write operations, by A3, and read operations are harmless, by A4, and can be added. This way we are able to satisfy Cl and C2. 2. The condition C3 is a special case of C2. Hence, it can be satisfied for any test. 3. The transformation preserves the original test coupling fault coverage (Lemma 4.6). 4. If the original test detects the address decoder faults, then it satisfies the two conditions of address decoder detection. Consequently, by C4, address decoder faults will be detected by the transformed test. ■ 120 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4.6 Transformation Examples Let us take two march tests with different complexities and convert them for in- system test of caches. March B algorithm [9] is a 17N memory test given by: 1 T (w O ); 1t(r0, wl, rl, w O , rO , wl); 1t(rl, w O , wl); M O Ml M2 U(rl, w O , wl, w O ); li(rO, wl, wO ), M3 M4 which detects address decoder, stuck-at, linked transition and coupling faults. It can be modified for in-system testing of the tag part of a cache using the transformation to get: ft{w([A, a], 1), w([B, a], 1), w([A, a], 0)}; M O ft{r([A, a], 0), w([B, a], 0), r([B, a], 0), w([A, a], 1), r([A, a], 1), w([B, a], 1), r([B, a], 1)}; Ml 1t{r([B, a], 1), w([A, aj, 0), r([A, a], 0), w([B, a], 0)}; M2 il{r([B, a], 0), w([A, a], 1), w([B, a], 1), w([A, a], 0)}; M3 U{r([A, aj, 0), w([B, a], 0), w([A, a], 1)}. M4 121 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. March X algorithm [9] is 6N memory test given by: ft(wO ); lt(rO, wl); Ii(rl, wO); li(rO), M O Ml M2 M3 which detects address decoder, stuck-at, unlinked transition and inversion coupling faults. It can be modified as: ft{w([A, a], 1), w([B, a], 1), r([B, a], 1), w([A, a], 0)}; M O 1t{(r[A, a], 0), w([B, a], 0)}; Ml a], 0), w([A, a], 1)}; li{r([A, a], 1)}. M2 M3 Notice that we added r([B, a], 1) in MO since it is a requirement for testing the SA and TF faults in the tag part. Adding read operations anywhere in the test should not cause any problem since if it is a read miss causing replacement, then the fault is detected due to the property that the memory has different data value than the cache. 4.7 Comparison of Tests Complexities In this section, we will compute the complexities of the new March Test algorithms and compare them with the previous work reported in the literature. 122 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4.7.1 Complexity of the Proposed March B Test The modified March B test has a complexity of 2IN in terms of total number of operations, where N is the number of block frames in the cache. Assuming the cache has no write-back buffer and a replacement requires a full main memory access, the complexity becomes: - Main memory accesses: 13N (times when replacements occur) - Cache accesses: 8N (times when cache is accessed without replacement). The above results are obtained based on the following assumptions. - The first memory access in M O always causes a cache miss. - Every read operation causes a cache hit since it causes a cache miss only in the presence of faults. Notice that a fault is detected when a read operation causes a cache miss (in most cases) which means that the algorithm stops execution. - A cache miss time is the main memory access time and not the addition of the main memory and cache access times, since the main memory takes a long time to complete the operation and the cache access is often overlapped with that operation. Note that the processor writes to the cache while the MMU deals with the writing to the main memory since it handles replacements. Furthermore, read operations in March B occur between write operations. Since each read operation in this test causes a cache hit while each write operation causes a 123 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. miss, the cache access in a read operation is easily overlapped with the replacement caused by a cache miss in a previous write operation. Consequently, the time complexity of the modified March B is: Ttesting = 13 NTM , where Tm is the main memory access time. 4.7.2 Comparison With the Previous Work We have presented a modified March B test to test the tag field of a direct mapped cache whose architecture is identical to that proposed in [34] and [33]. The complexity of our test is 13NTm while that of the test proposed in [34] and [53] is 33NTm + 17NTc, where Tm is main memory access time and Tc is the cache access time. In the algorithm in [34] and [33], all cache accesses cause misses. Also, the presence of a buffer will not have any effect since the main memory accesses are all direct. Consequently, the proposed test saves at least 60.6% of the test time for the tag part of the cache memory. Furthermore, our modified March B test can work even if the cache does not have enable/disable capability and requires no hardware overhead. 124 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4.8 Summary A methodology to transform march tests for in-system testing of direct mapped caches is presented. The effect of tag faults is covered so they do not mask data faults. The methodology for testing the tag part is applied to obtain new versions of March B and March X tests. Unlike previously proposed tests for cache tags, these tests can be applied without making any modification to the memory system hardware. Furthermore, the proposed March B test has been shown to have significantly lower complexity than the previously proposed version. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Chapter 5 5 Conclusions and Future Research Our research has led to many new results in the field of memory testing. In this chapter we discuss the conclusions of the previous chapters and include the planned expansion of our research for the future. 5.1 Conclusions 5.1.1 Condition Generation for Fault Detection • A new presentation for unlinked faults is presented. • Requirements for detection of unlinked faults were studied. • A procedure for generating conditions for fault detection was presented. • Necessary and sufficient conditions for detecting unlinked faults are presented. • Necessary and sufficient conditions for detection of single-cell faults when linked with other faults are presented. • Address decoder faults are proven to be dominated by other classical faults. 126 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. • Linked inversion coupling faults were proven to be dominated by a set of 16 linked inversion coupling faults. • CFid#CFid faults are proven to be dominated by eight CFid#CFid faults. • CFid#CFin faults are proven to be dominated by the U, D2 and N sets. • The necessary and sufficient conditions for detecting the dominating faults for CFin#CFin, CFid#CFid and CFid#CFin are presented. • Sufficient conditions for detecting the extended fault models linked with any set of faults are presented. 5.1.2 March Test Generation • The search space for march tests is reduced by proving that some read-only march elements and consecutive march elements starting with write operations can be ignored. • Dominance is used to reduce the number of faults to be considered. • A tree structure for test generation is introduced. • A new efficient algorithm for generating optimal and uniform march tests has been provided. • Twelve new tests for different combinations of unlinked faults for unconstrained memories are generated. • The superiority of the newly generated march tests is proven over other well known tests such as march C-. 127 permission of the copyright owner. Further reproduction prohibited without permission. • The optimality of well known march tests is proven in terms of their time complexities. • The optimality of March A and March B tests is proven. • New optimal tests for all linked faults are presented. • The detectable faults in unidirectional memories were identified and their necessary and sufficient conditions are presented. • Ten new march tests that are applicable to unidirectional memories and cover different combinations of faults are presented. • The detectable faults in queues are identified and their necessary and sufficient conditions presented. • Five new march tests that are applicable to queues and cover different combinations of faults are presented. • The test generation process for queues is significantly improved by ignoring march elements that are not applicable to queues. • Two new march tests for stacks are presented. • The previously published methodologies are proven to be inefficient and in some cases proven to generate march tests that do not detect target faults. 5.1.3 Cache Testing • New factors for speeding up cache testing are presented. • A methodology for transforming march tests to tests applicable on testing cache tags is presented. 128 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. • The necessary and sufficient conditions for detecting single cell faults in tags are presented. • The observance of original test capabilities in terms of detection of multiple cell faults is proven. • A new version of March B test that is applicable for testing cache tags is provided. • The new version of March B is shown to save at least 60.6% of the test time for the tag part of the cache memory. 5.2 Future Research 5.2.1 March Test Generation Many new fault models have been introduced in the past few months. The new fault models are the result of experiments done by a test group at Delft University of Technology, The Netherlands, and Intel Corporation [12]. While new march tests were introduced for the new fault models, it seems likely that more efficient march tests can be generated for them using an enhanced version of the test generation methodology presented in this dissertation. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 5.2.2 Memory Structures We have considered several memory structures including unconstrained and constrained memories. It is important to include several additional structures that have come into common usage. One of the new structures is the content-addressable memory [18,33,59]. For this type of memory, march tests might not be applicable since the test should apply different data to every location, which violates the definition of march tests. Another commonly used memory is the multiple port memory [11,47]. In this type of memory, two or more different address locations can be accessed at the same time. Fault models for this type of memory have been under study in the past few years. Expanding our research to include this type of memory is a subject of future research. 5.2.3 Cache Testing We are planning to expand our work in cache testing in two directions. The first one is by considering other cache structures such as write-through cache memories, which are commonly used in computer systems [4]. The second direction is by considering multilevel cache memories, which are in contemporary usage, in order to improve the performance of memory systems [21,30]. Both structures require 130 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. significant changes in the transformation methodology presented in the previous chapter. 5.2.4 BIST Design One of the properties of the newly generated march tests is uniformity. As we have mentioned in Chapter 3, uniform tests simplify the Built-In-Self-Test structure. BISTs are commonly used in memories and SoC chips [14, 57]. Designing new BIST circuits for memories using uniform tests is also a subject for future research. We believe that the new BIST design will be significantly simpler than the currently available ones. 131 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. References [1] Adams, R., Connor, J., Koch, G., Temullo Jr., L. (1995). A 370-MHz Memory Built-In Self-Test State Machine, European Design and Test Conference, pp. 139-141. [2] Barbagalio, S., Bodoni, M., Medina, D., Blasio, G., Ferloni, M., Fummi, F. and Sciuto, D. (1996). A Parametric Design of a Built-in Self-Test FIFO Embedded Memory, Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 221-229. [3] Cheung, H. and Gupta, S. (1996). A BIST Methodology for Comprehensive Testing of RAM With Reduced Heat Dissipation, Proceedings of IEEE International Test Conference, pp. 386-395. [4] Chu, P. and Gottipati, R. (1994). Write Buffer Design for On-Chip Cache, Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 311-316. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. [5] Dandamudi, S. and Cheng P. (1995). A Hierarchical Task Queue Organization for Shared-Memory Multiprocessor Systems, IF.FK Transactions on Parallel, and Distributed Systems, Vol. 6, No. I, pp. 1-16. [6] Dekker, R., Beenker, F. and Thijssen, L. (1990). A Realistic Fault Model and Test Algorithm for Static Random Access Memories, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 6, pp. 567-572. [7] Dekker, R., Beenker, F. and Thijssen, L. (1988). A Realistic Self-Test Machine for Static Random Access Memories, Proceedings of IEEE International Test Conference, pp. 353-361. [8] Dekker, R., Beenker, F. and Thijssen, L. (1989). Realistic Built-In Self-Test for Static RAMs, IEEE Design and Test of Computers, Feb., pp. 26-34. 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Modeling and testing transistor faults in content- addressable memories, Proceeding of IEEE International Workshop on Memory Technology, Design and Testing, pp. 83-90. 137 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. [34] Sosnowski, J. (1995). In System Testing o f Cache Memories, In Proc. IEEE Int. Test Conference, pp. 384-393. [35] Suk, D. and Reddy, S. (1981). A March Test for Functional Faults in Semiconductor Random Access Memories, IEEE Transactions on Computers, Vol. C-30, No. 12, pp. 982-985. [36] Takeshima, T., Takada, M., Koike, H., Watanabe, H., Koshimaru, S., Mitake, K., Kikuchi, W., Tanigawa, T., Murotani, T., Noda, K., Tasaka, K., Yamanaka, K., and Koyama, K. (1990). A 55-ns 16-Mb DRAM with Built-in Self-Test Function Using Microprogram ROM, IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, pp. 903-911. [37] Tang, P. and Tai, T. (1999). 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Creator Al-Harbi, Sultan M. R. F. (author)

Core Title Functional testing of constrained and unconstrained memory using march tests

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School Graduate School

Degree Doctor of Philosophy

Degree Program Computer Engineering

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag Computer Science,engineering, electronics and electrical,OAI-PMH Harvest

Language English

Advisor Gupta, Sandeep (committee chair), [illegible] (committee member)

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c16-141420

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