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Design, fabrication, and integration of a 3-D hybrid electronic/photonic smart camera

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Design, fabrication, and integration of a 3-D hybrid electronic/photonic smart camera

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Content NOTE TO USERS This reproduction is the best copy available. UMI DESIGN. FABRICATION. AND INTEGRATION OF A 3-D HYBRID ELECTRONIC/PHOTONIC SMART CAMERA by Patrick Nasiatka A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2003 UMI Number: 3103950 INFORMATION TO USERS The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleed-through, substandard margins, and improper alignment can adversely affect reproduction. In the unlikely event that the author did not send a complete manuscript and there are missing pages, these will be noted. Also, if unauthorized copyright material had to be removed, a note will indicate the deletion. UMI UMI Microform 3103950 Copyright 2004 by ProQuest Information and Learning Company. Ail rights reserved. This microform edition is protected against unauthorized copying under Title 17, United States Code. ProQuest Information and Learning Company 300 North Zeeb Road P.O. Box 1346 Ann Arbor. Ml 48106-1346 UNIVERSITY OF SOUTHERN CALIFORNIA THE GRADUATE SCHOOL UNIVERSITY PARK LOS ANGELES, CALIFORNIA 90089-1695 This dissertation, written by Patrick J. Nasiatka under the direction o f h 1S dissertation committee, and approved by all its members, has been presented to and accepted by the D irector o f Graduate and Professional Programs, in partial fiilfillment o f the requirements f o r the degree o f DOCTOR OF PHILOSOPHY Director Date May 16, 2003 Dissertation Committee Acknowledgments I am indebted to a number of individuals that helped make this thesis possible. The love and support of my parents were instrumental in allowing me to pursue my graduate studies. I owe them a lot. Dr. Armand Tanguav, my thesis adviser, is truly an incredible researcher, mentor, and, more importantly, a good friend. Watching him approach and solve problems, from the mundane to the complex, was the linchpin of his teaching style. His research guidance and support of my studies made my USC graduate experience incredibly fullilling. The additional members of my graduate committee, Ted Berger, B. Keith Jenkins, John O’Brien, and Chuck Weber helped form and direct aspects of my research. Their fruitful discussions opened up research avenues that were hidden to my young eyes. I am further indebted to the assistance received from OMDL members. These individuals include Kartik Ananthanarayanan, Josh Wyner, Martin Han, and Lormen Lue. I hope we have a chance to work together in the future. Two of them, Kartik and Josh, were oflice-mates that provided fruitful, and some times not so fruitful, discussions. 1 especially enjoyed their friendship. Additional graduate students at USC were also helpful and made my graduate experience more enriching. Nan-Kyung Suh, Johan Berger, Thong Sangsiri, and Roshanak Saafriha all assisted in aspects of my research. For that, I am in your debt. Diane Chambers, at the University of Alabama-Huntsville (UAH), was instrumental in a key collaborative effort between USC and UAH. The reason I attended USC resides with the influence and teaching of Dr. Greg Nordin at the University of Alabama and Dr. Zaheed Karim, previously at the Hong Kong University of Science and Technology. These are two incredi ble people. Finally, I would be remiss if I didn’t mention the excellent support of Karen Johnson, our Optical Materials and Devices Laboratory (OMDL) administrative assistant. She kept a lot of the “grunt” work from falling into my lap, leaving more time for my research responsibilities. She is also a good friend. Thanks, Karen. Table of Contents A cknow ledgem ents.............................................................................................ii List of F igures....................................................................................................... viii List of T ables......................................................................................................... xxi A bstract...................................................................................................................xxii Chapter 1 Introduction..........................................................................................................1 1.1 Introduction......................................................................................1 1.2 Smart Cameras.................................................................................3 1.3 Biological Vision Models and Optical Implementations...........4 1.4 Thesis Organization...........................................................................12 1.5 References...........................................................................................13 Chapter 2 System Level Considerations : M otivation for the R esearch................16 2.1 Introduction........................................................................................16 2.2 Introduction to Smart Cameras.......................................................17 2.3 Selected Smart Camera Designs..................................................... 18 2.3.1 University-Based..................................................................18 2.3.2 Commercial-Based...............................................................19 2.4 Benchmarking of Smart Cameras....................................................19 2.5 I VP MAPP 2200 Smart Camera........................................................23 2.5.1 MAPP 2200 Architecture.....................................................23 2.5.2 MAPP 2200 Performance...................................................27 2.5.3 MAPP 2200 Limitations...................................................... 27 2.6 General Purpose Computers as Smart Cameras..........................28 2.7 MPI Cluster Implementation .........................................................30 2.7.1 MPI Results...........................................................................30 2.8 Conclusions........................................................................................33 2.9 References...........................................................................................34 Chapter 3 PMCM - Photonic M ultichip M odule................. 38 3.1 Introduction........................................................................................38 3.2 Smart Camera Architecture............................................................. 43 3.3 Electrical Interconnections................................................................47 3.4 Optical Interconnections...................................................................50 3.5 Photonic Multichip Modules (PMCM).......................................... 53 3.6 Evolution of the PMCM Architecture............................................ 57 3.7 Vertical Cavity Surface Emitting Lasers........................................ 59 3.7.1 VCSEL Operating Principles............................................ 60 3.7.2 VCSEL Testing Procedures................................................ 61 3.7.3 Operating Wavelength....................................................... 63 3.7.4 Optical Power Budget........................................................ 68 3.7.5 Emission Geometry.......................... 73 3.7.6 VCSEL Modal Properties....................................................73 3.7.7 VCSEL Intensity and Array Uniformity..........................76 3.7.8 VCSEL Threshold and Array Uniformity........................78 3.7.9 VCSEL Polarization Properties......................................... 78 3.7.10 VCSEL Sum m ary...............................................................80 3.8 Conclusions........................................................................................80 3.9 References...........................................................................................82 Chapter 4 Diffractive Optical E lem ents............................................... 90 4.1 Introduction........................................................................................90 4.2 Preliminary Concepts........................................................................93 4.3 Grating Types.....................................................................................96 4.3.1 Optical Properties of Thin Gratings..............................97 4.3.2 Optical Properties of Thick Gratings.............................98 4.4 DOEs for use in the PMCM..............................................................98 4.5 Computer Generated Holograms (CGHs).................................... 101 4.5.1 Design of Computer Generated Holograms................102 4.5.2 Fabrication of Computer Generated Holograms 108 4.5.3 Computer Generated Holograms Characterization....114 4.5.3.1 Material Characterization............................. 116 4.5.3.2 Demonstration of Optical Fan-Out..............119 4.5.3.3 Demonstration of Optical Fan-Out / Fan-In..........................................................................128 4.6 Stratified Volume Diffractive Optical Elements...........................132 4.7 Conclusions........................................................................................146 4.8 References...........................................................................................147 Chapter 5 Thin Films for PM CM ...................................................................................... 153 5.1 Introduction ......................................................................................153 5.2 Design of Multifunction Antireflection Coating..........................156 5.3 Fabrication of Multifunction Antireflection Coating....................159 5.4 Optical Characterization of ITO Antireflection Coating .............161 5.5 Thin Film Coating for PMCM..........................................................164 5.5.1 Optical Power Budget.........................................................165 5.5.2 AR Coating on Computer Generated Holograms...........168 5.5.3 AR Coatings on SVDOEs...................................................173 5.6 Additional ITO Benefits.................................................................... 180 5.7 Conclusions........................................................................................ 181 5.8 References........................................................................................... 182 Chapter 6 Flip Chip Integration of PMCM .....................................................................185 6.1 Introduction....................................................................................... 185 6.2 Indium Bump Evolution....................................................................187 6.3 Indium Bump Fabrication................................................................. 193 6.4 Electrical Performance ..................................................................... 197 6.5 Fabricated Devices using Double-Sided Bonding........................200 6.6 Single-Sided Bonding........................................................................204 6.7 Performance of Single-Sided Bonding........................................... 206 6.8 Fabricated Devices using Single-Sided Bonding .........................206 6.9 Passive Device Integration................................................................211 6.10 Additional Challenges with MOSIS IC........................................ 216 6.11 Single-Sided Indium Bump Strength............................................ 218 6.12 Extension of Single-Sided Bump Bonding.................................. 219 6.13 Conclusions....................................................................................... 220 6.14 References......................................................................................... 221 Chapter 7 PMCM Integration Efforts..................................................... 227 7.1 Introduction....................................................................................... 227 7.2 VLSI Computation Integrated Circuit Design............................... 228 7.1.1 Device Design.................................................................... 230 7.3 Demonstration of Two Layer, Single Channel PM CM ................234 7.4 Towards Fully Integrated PM C M ....................................................239 7.5 Digital PMCM Preliminary Design.................................................242 7.6 Conclusion...........................................................................................248 7.7 References............................................................................................249 Chapter 8 Potential Applications.................................................................................251 8.1 Introduction....................................................................................... 251 8.2 Augmented Reality............................................................................. 252 8.3 Immersive Camera............................................................................. 255 8.4 High-Performance Neural Prosthetics/Probes .............................. 257 8.5 PMCM for Biosensors....................................................................... 258 8.6 Conclusion...........................................................................................261 8.7 References............................................................................................261 Chapter 9 Conclusions and Future Research Directions...................................... 263 9.1 Introduction...................................................................................... 263 9.1.1 Smart Cameras and PMCM.................................................264 9.1.2 Diffractive Optical Elements............................................265 9.1.3 Thin Films for PM CM ......................................................267 9.1.4 Hybrid Photonic/Electronic Packaging........................... 268 9.1.5 Integration Efforts............................................................. 269 9.2 Future Research Directions.............................................................. 270 9.2.1 Photonic Multichip Modules (PMCMs)..........................270 9.2.2 Computer Generated Holograms.....................................270 9.2.3 Indium Bump Bonding..................................................... 272 9.2.4 ITO Thin Films...................................................................272 9.2.5 SVDOEs..............................................................................274 B ib liograp h y................................................................................................................277 vii List of Figures Figure 1-1. Figure 2-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 3-1. Photonic multichip module with integrated VCSELs 8 Hip chip bonded to a silicon, integrated circuit sub strate. The use of a substrate containing diffractive optical elements provides for the optical interconnec tion pattern between electronic layers. (a) Original 256 x 256 pixel, 256 grey level image of 24 Lena. (b) Image of Lena after 3 x 3 Sobel filtering algorithm. 24 Notice the bright areas in this image are the ones with the greatest gradient in the original image. The IVP MAPP2200 senior head [Astrom, 1993]. 25 MAPP 2200 function block diagram. 26 Graph of Sobel filter execution time as function of 32 processors. Four different Sobel kernel sizes are graphed. Conceptual diagram of 3-D photonic multichip mod- 39 ule (PMCM) device, showing silicon-based ana log/digital VLSI chips and optical fan-out/fan-in interconnection fabric between these chips [Tanguay, 1993]. viii Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Schematic diagram of multilayer hybrid elec tronic/photonic photonic multichip module, showing tw'o silicon VLSI chips optically interconnected by vertical cavity surface emitting laser (VCSEL) and diffractive optical element arrays. Two adjacent pixels are shown in cross section. An operational schematic of a hypothetical multilayer PMCM. As an input scene enters the stack, the neces sary low-level vision operations (e.g., contrast enhancement, adaptive localized gain, edge detection, Sobel gradient index filters) are performed. Travelling further through the stack the mid-level vision opera tions (e.g., recognition of features in the input scene and their co-occurrence) and high level vision opera tions are then performed leading to a compact, smart representation of the input scene [Tanguay, et. al. 2001]. Generalize schematic of adaptive vision sensor show ing information flow. An optional region-of-interest discriminator is also shown as a layer between the pre- dection optics layer and the PMCM stack. The right most bars indicate the portion of electronics and optics used in the system. Schematic diagram of multilayer hybrid elec tronic/photonic photonic multichip module, showing two silicon VLSI chips optically interconnected by vertical cavity surface emitting laser (VCSEL) and diffractive optical element arrays. Two adjacent pixels are shown in cross section. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure showing the early architecture of the 3-D pho tonic multichip module using an optical power bus integrated with a GaAs MQW modulator for use as an integrated SLM [from Tanguay, 1993]. Schematic diagram of the optical system employed for VCSEL data collection and loaeing. Entire control of C : C - O the experimental setup was performed by Lab View software running on a Macintosh Ilfx computer and, later, a Macintosh G3 computer. MODE VCSEL output optical wavelength spectrum measured by the HP 7095 IB OS A showing single mode operations with a laser driving current of 8.5 mA. Peak center wavelength is measured as 849.6 nm. Plot of the optical transmission thru a silicon substrate as a function of photon energy and wavelength. Plot of a silicon substrate’s transmission as a function of photon energy and wavelength. The two graphed traces correspond to the old (304.8 micron) MOSIS chip thickness and the newr (254 micron) MOSIS chip thickness. Optical output spectrum for the USC VCSEL at three different input driving currents showing the “red-shift” effect. Figure 3-12. Schematic figure of the PMCM characterizing all unwanted optical losses. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 4-1. MODE VCSEL output optical wavelength spectrum measured by the HP 7095 IB OS A showing multimode operations with a laser driving current of 9.5 mA. An increase of 1 mA, from 8.5 mA to 9.5 mA, causes an unwanted lasins mode to be formed. Spatial distribution of the lasing modes on the MODE VCSEL as a function of input electrical driving cur rent. Contour plot of maximum output optical power as a function of position for the 8 x 8 MODE VCSEL array. Contour plot of laser threshold as a function of posi tion for the 8 x 8 MODE VCSEL array. VCSEL property comparison between MODE, NEC, and USC vertical cavity surface emitting lasers. Schematic diagram of a square wave grating showing a plane wave readout. The DOE grating is shown operating in the transmission mode. The incident beam is diffracted into individual orders that is depen dent on the substrate's refractive index, the grating pitch, the incident beam angle, the grating groove etch depth, and the surface relief profile of the gratings. Note: input/output optical beam displacement is assumed to be neglable is not showm in the figure. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. 3-D schematic of showing a DOE structure providing 99 a l-to-3 optical fan-out. The DOE illumination area, detector pitch, distance between layers, and detector size are needed prior to DOE design. The VCSEL array and lens array are not shown. Processing steps for the construction of a computer 104 generated hologram based upon the Gerchberg-Saxton algorithm. c The output intensity reconstruction of a CGH design 106 with four different numbers of phase levels. Schematic diagram of multilayer hybrid elec- 108 tronic/photonic photonic multichip module, showing two silicon VLSI chips optically interconnected. Thermal issues ideally lead to the use of GaAs as the DOE substrate material. Schematic diagram showing the processing steps 110 involved in the fabrication of binary phase diffractive optical elements. SEM photograph of a GaAs DOE sub-element. 115 Dektak surface profile of the etched GaAs sample 117 shown in the SEM micrograph. Experimental setup used for the evaluation of the DOE 120 output performance. The output plane is located at the CCD surface. xii Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Output ~ cal reconstruction pattern from a quartz E- 122 beam fu ated DOE illuminated with a 970 nm light source. The figure on the left shows the output pattern on the face of the Sony CCD camera, w'hile the corre sponding contour plot is shown on the right. Grey scale value of the of the right nearest neighbor 125 spot of the DOE reconstruction pattern as a function of DOE substrate rotation. Grey scale value of both the of the right and left near- 126 est neighbor spot of the DOE reconstruction pattern as a function of DOE substrate rotation. The images cor respond to the angle values indicated by the vertical green lines on the graph. Experimental configuration for investigation of the 127 DOE rotational performance, a consequence of the Fabry-Perot optical effect. Fan-in pattern (left) from two 970-nm VCSEL ele- 130 ments within an 8 x 8 array, transmitted through the same 4:2:1 diffractive optical element (DOE). Mea sured optical reconstruction pattern (right) from two 970 nm VCSEL elements within an 8 x 8 array, trans mitted through the same 4:2:1 diffractive optical ele ment (DOEn The spot size (FWHM) was 125 to 250 pm, with a spot separation of 2.5 mm. Combination fan-out/fan-in for one, two, three, and 131 four lasers. Analog weighted optical intensity is shown in three of the figures. xiii Figure 4-16. Multilevel DOE with layers of phase or amplitude 133 modulation interspersed with buffer regions. Figure 4-17. Figure 4-18. Figure 4-19. Figure 4-20. Figure 4-21. Figure 4-22. Figure 5-1. Schematic of two level GaAs-based SVDOE. Low-resolution screen capture of one SVDOE mask showing the layout and orientation of the individual gratings. Color optical micrograph showing grating area, high resolution alignment fiducials needed for device inte- w gration, and large bonding pads for subsequent indium bump deposition. SEM image (top) of single layer of SVDOE stack. Seen are indium bumps, alignment fiducials for subse quent flip chip bonding, and a phase grating region. Sample substate is SI GaAs. Closeup SEM image (bottom) of single layer of SVDOE stack showing square indium bumps (two seen) and a high resolution Ronchi ruled phase grating. Two SVDOE samples fabricated using the described processing sequence. Optical intermodulation caused by Fabry-Perot effects; it is critical to reduce these Fabry-Perot effects. TFCalc plot of reflectance as a function of wavelength for an optimized thin film coating of thickness 1296 A, 136 137 138 142 143 145 159 xiv Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6 Figure 5-7. Figure 5-8. Figure 5-9. Summary of ITO thin film coating on a GaAs and Si planar substrates (measured using the Cary Varian Spectrophotometer). Schematic figure of an AR-coated PMCM characteriz ing all unwanted optical losses. Percent error in reconstructed output optical diffrac tion profile for a coated and uncoated DOE. Graph characterizes variation of optical intensities (as measured on a Cooke 12-bit, cooled-CCD camera) as a function of angular tilt. Fan-in pattern (left) from two 970 nm VCSEL ele ments within an 8 x 8 array, transmitted through the same 4:2:1 diffractive optical element (DOE). Mea sured optical reconstruction pattern (right) from two 970 nm VCSEL elements within an 8 x 8 array, trans mitted through the same 4:2:1 GaAs diffractive optical element (DOE). The spot size (FWHM) was 125 to 250 pm, with a spot separation of 2.5 mm. GaAs Ronchi ruling with a 32 pm pitch and a 16 pm grating fingers. Diffraction efficiency as a function of incident angle for the GaAs Ronchi ruling with a 32 pm pitch and 16 pm grating fingers. GaAs Ronchi ruling with a 32 pm pitch, a 16 pm grat ing fingers, and an ITO backside AR coating. 164 166 170 171 173 174 175 177 xv Figure 5-10. Diffraction efficiency as a function of incident angle 178 for the GaAs Ronchi ruling with a 32 |_im pitch, 16 pm grating lingers, and a backside AR coating. Figure 5-11. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Expected optical “picket-fence” diffraction pattern for a two-layer SVDOE structure. SEM photomicrograph of the non-"velcro~” like indium bump for use with integrating multiple quan tum well spatial light modulators. These bumps caused significant de-bonding problems. "Velcro” indium bump prior to flip-chip bonding. Notice the indium grain distribution and the overall surface morphology that significantly reduces the effects of the native indium oxide layer during the flip- chip bonding attachment process. Semiconductor processing steps for the formation of discrete indium bumps by utilizing a multilayer photo resist flood exposure lift-off process. Exploded schematic diagram of the daisy chain struc ture used for electrical and mechanical characteriza tion. Shown is a single 1 x 40 array of bumps between the "top” and “bottom” substrate. SEM micrograph of the top corrugated surface of an indium "velcro” bump. SEM micrograph of indium bumped X-ray detector elements prior to silicon hybridization. 179 190 192 194 198 201 202 xvi Figure 6-7. Figure 6-8. Figure 6-9. Figure 6-10. Figure 6-11. Figure 6-12. Figure 6-13. Optical micrograph of the hybridized 1-D laser array. The electrical signal lines are shown leading to the 1-D array on the bottom edge of the picture. Optical power as a function of input electrical current for pre-bonded (top figure) and post-bonded array (bottom figure). Plot of the laser input voltage as a function of input current, both pre- and post-bonding. SEM micrograph of a USC designed and fabricated low-threshold VCSEL, illustrating the surface topol ogy. SEM micrograph of silicon mating substrate with ther mally deposited indium bumps. Optical micrograph showing VCSEL flip-chip bonded to a Si mating substrate. One laser is shown in opera tion. Output optical power and change in optical power as a function of input electrical driving current for the USC designed, fabricated, and post-bonded VCSEL. Notice the Fabry-Perot effects caused by the GaAs high refractive index substrate. 207 208 209 210 211 212 213 xvii Figure 6-14. Figure 6-15. Figure 6-16. Figure 6-17. Figure 6-18. Figure 7-1. Figure 7-2. Schematic diagram of multilayer hybrid elec- 214 tronic/photonic photonic multichip module, showing two silicon VLSI chips optically interconnected by vertical cavity surface emitting laser (VCSEL) and diffractive optical element arrays. Two adjacent pixels are shown in cross section. Photomicrograph of daisy chain structure fabricated 215 with ITO trace lines atop quartz substrates. Note the lettering under the quartz substrates. Zincation bump (35 pm x 35 pm) atop an aluminum 216 bonding pad. SEM micrograph of GaAs VCSEL mesa embedded in 218 an indium bump. The VLSI substrate broke away from the silicon mating substrate after a 3 foot fall (destructive evaluation test). SEM micrograph of indium strip retaining the “vel- 219 cro”-like properties. Schematic circuit block diagram of a pixel of the 2-D 231 Si neuron unit array, showing the stages between opti cal detection and the voltage output stage [from Su, 1997]. OMDL neuron-like smart pixel chip fabricated by 234 MOSIS. The chip is configured with an 11 x 11 array of smart pixels with a spatial pitch of 125 pm per smart pixel element [Lue, 2001 ]. xviii Figure 7-3. Figure 7-4. Figure 7-5. Figure 7-6. Figure 7-7. Figure 7-8. Figure 7-9. Optical microphotograph of ARL VCSEL packaged in 235 a pin grid array. Notice the irregular surface pattern on the VCSEL caused by the poor AR thin film coat ing adhesion. Performance data curves for the ARL VCSEL. A plot 236 of the voltage as a function of current is shown (Top). A plot of the output optical power as a function of electrical driving current (Bottom) is also shown. Plot of the VLSI chip output electrical current (Top) as 238 a function of input opitical power. Plot of the ARL VCSEL output optical power (Middle) as a function input electrical current. Plot of the ARL VCSEL out put (Bottom) as a function of input optical power strik ing one of the two VLSI photodetectors. Silicon IC with holes in two layer photoresist for later 241 indium bump deposition. The top holes are co-located with the output pad of the smart pixel, while the bot tom two holes are aligned for the necessary ground pads. The digital pulse shape used for driving the VCSEL. 245 Output intensity profile as a function of varying duty 246 cycle. Waveform schematics showing how simple 1-bit 247 instructions could be sent to the next stack layer with out affecting the analog weighted interconnection scheme Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 9-1. Figure 9-2. Enhanced augmented reality demonstration (from Tanguay, et. al., (2000)). In this case the image scene is overlaid with graphical annotations. Three elements of the eight-element Immersivision design shown. Neural prosthetic containing a PMCM. Neuronal growth atop semiconductor substrate. Biological sensor system using a stratified volume dif fractive optical element for further pattern classifica tion and characterization. Four direct-write E-beam computer generated holo grams with 3.125 pm, 1.6 jam, 0.6125 |am, and 0.3125 pm minimum feature sizes. MOSIS TinyChip illustrating feasibility of foundry fabrication SVDOE structures. 253 256 257 259 260 273 275 xx List of Tables Table 2-1. Performance of MAPP 2200 Smart Camera 27 Table 2-2. Sobel operation times 29 Table 2-3. Sobel operational performance on MPI system 31 Table 4-1. ECR process parameters 114 Table 5-1. ITO deposition parameters 160 Table 6-1. Properties of bulk indium 189 Abstract A set of technologies needed for the design and construction of an intelli gent smart camera, including the issues related to the use of diffractive optical elements, optical thin films, and hybrid electronic/photonic packaging is dis cussed. The thesis starts by considering the feasibility of mploying conventional single- and multi-processor computer workstations for an implementation of a smart camera system. A commercially available camera known as the MAPP 2200 is then analyzed. The limitations of both systems lead directly to the adoption of a multilayer stack architecture, known as a photonic multichip mod ule (PMCM), for use as the basis of a novel smart camera system. We report the implementation of two distinct types of diffractive optical elements to support the needs of the PMCM: computer generated holograms (CGHs) and stratified volume diffractive optical elements (SVDOEs). Both components are fabricated using a high-refractive-index, gallium arsenide sub strate. Experimental measurements of both optical fan-in and fan-out needed for the optical interconnection scheme led to a previously unreported optical effect based on multiple internal reflections that could obviate successful opera tion of CGHs. SVDOEs are devices in which multiple layers of thin diffractive material are interleaved with optically homogeneous buffer layers. In this way, devices can be built that can emulate conventional volume holographic optical elements. These devices were experimentally shown to be susceptible to the xxii same unwanted optical effect seen during the CGH experiments. This novel device also integrates a previously reported indium tin oxide (ITO) anti-reflec tion (AR) coating, necessary to show agreement between expected and experi mental results. We analyze the effects of this AR coating on high refractive index diffractive substrates. Finally, we show how a previously-reported novel indium-bump-bonding method can be extended to allow for commercial VLSI substrates and vertical cavity surface emitting lasers (VCSEL) in the PMCM. Known as single-sided indium bump bonding, it allows for the formation of an electrical and mechani cal bond by defining indium bumps on only one of the two mated substrates. In this way, substrates that are not available in wafer form, such as commercial integrated circuits and MOSIS-ICs, and substrates with unusual surface topolo gies, such as VCSELs, are now easily mated. Chapter 1 Introduction 1.1 Introduction Modern computers are incredibly powerful. However, despite the extraordinary progress made in the computer field, there are still computational problems that require even greater processing power. Such power is, however, not easily obtainable in current or near-term computer designs, especially those that still embrace the von Neumann’s computer architecture model. Real-time computer vision, target/object recognition, and object tracking all encompass a class of problems that is seemingly out of the range of current computer tech nology. At the same time, optical technology has made enormous strides in the past couple of decades. Examples include fiber-based optical communication systems, optical disk technology for the storage of audio (CD), video (DVD), computer data (CD-ROM), and optical devices for biomedical diagnosis and treatment. 1 In this thesis, the design, fabrication, and integration of a set of core technologies needed to enable a truly smart camera capable of limited real-time, low latency, semi-autonomous object recognition and tracking is reported. The focus of this project is a small adaptive sensor system capable of cue determination and cue fusion for real-time target tracking and target recog nition in a noisy environment. In its final deployable form it will be low power, compact, and adaptable to the corresponding environment. In order to accom plish these tasks the smart camera architecture is designed to facilitate multi-spectral processing, and both temporal and spatial cue determination, all in real-time. The embracing of various computational neurobiological methods has further enhanced this functionality. As was proposed earlier and is being separately developed [Tanguay et. al., 2000], biological vision processing tech niques such as those employing Gabor wavelets [von der Malsburg, 1981], seg ment based vision [Mel, 1997], and color mapping and recognition [Biederman, 1995] are being mapped into our smart camera architecture. These approaches, it is hoped, will eventually extend the recognition ability of our system. Smart camera device development is enabled by leveraging VLSI digi tal/analog technologies, and advances in photonic devices, as well as by utiliz ing a novel, hybrid electronic/photonic packaging technology. The proposed system is configured using a photonic multichip module (PMCM) that has pre viously been described [Jenkins et al., 1992; Tanguay et al., 1993; Anantha- narayanan et al., 1995]. This thesis documents some of the first steps towards 2 the integration of this device. The as-configured PMCM allows for an extremely compact, very high capacity parallel I/O with weighted fan-in/fan-out interconnections among vertical arrays of processing elements. The following section introduces the concept of smart cameras in detail. Section 1.3 discusses aspects of biological vision modeling, and our biologi cally inspired smart camera implementation configured via a photonic multi chip module. This section also includes the specific issues involved in this design for use as a smart camera. The organization of this thesis is described in Sect. 1.4. 1.2 Smart Cameras A smart camera combines a classical optical sensing head with associ ated computational electronics in an attempt to add some increased functional ity to the system. The on-board sensor elements can be configured to take the form of phototransistors, photodiodes, or photogates (e.g., MOS capacitors exposed to light), while computational elements can exist in a binary, analog, or mixed-mode design. As will be seen, the choices available for sensors and computational elements are often dictated by the applications for which they are chosen. The most stringent requirement and the primary reason for the lack of a general-purpose smart camera are architectural issues regarding VLSI technol ogy, in particular layout and signal routing. Similar to current thinking in 3 high-end computer design circles, high performance computers are being cre ated by tightly coupling multiple processors in configurations that maximize processor data throughput. Mapping this architecture onto a single piece of sil icon (or, in some cases, GaAs) requires technology not yet ready for produc tion. Although companies such as IBM have demonstrated a prototype seven-layer metal process for high performance signal routing, this is still diffi cult to create a general-purpose smart camera. Another reason for the lack of general-purpose smart cameras is the nature of the photodetectors. First, detectors are in general analog devices, while general-purpose computational devices are typically made using digital logic components. In order to proceed, a stage of analog-to-digital converters is needed at the individual pixel level before a general-purpose smart camera can be realized. The most common VLSI technologies applied to the development of smart cameras are CMOS, BiCMOS, CCD, and forms of GaAs (MESFET and HEMT). Interestingly, availability rather than potential performance benefits almost always determines the choices of technology. In other words, CMOS designs dominate smart camera designs because foundry services, such as MOSIS, part of the Information Systems Institute (ISI) at the University of Southern California (USC), are readily available and relatively inexpensive. CMOS has the quickest design turnaround and is (by far) the cheapest of all of the competing technologies (especially significant since university researchers have initiated almost all smart camera research). 4 A further classification scheme for smart cameras includes those designs that employ biological vision models. Since the human visual system repre sents the current pinnacle of image acquisition and recognition systems, it is easy to see why research is underway to map aspects of biological vision onto smart cameras. In the next section we describe some common characteristics of these vision models and how they can be implemented in current elec tronic/photonic technology. 1.3 Biological Vision Models and Optical Implementation Biological vision, whether human or insect, are similar in a number of respects. The first aspect of biological vision is the grouping of “functionality'’ in a multilayered neuronal configuration. This is evident from both the human vision system [Livingstone et al., 1988] and non-human vision system [Veld- kamp et al., 1993]. One proposed anatomical/perceptual model of the visual cortex demonstrating this layering not only models the flow of visual informa tion through individual, discrete layers of the visual pathway such as the retinal ganglion cells, LGN areas, V I, V2, and V4 areas, but further classifies the flow of information inside the individual cellular regions of the VI region [Living stone et al., 1988]. Hence, we see layers within layers [Livingstone et al., 1988;Veldkamp et al., 1993], This leads to the second characteristic of biologi cal vision: namely the massive parallelism needed. As an example of this con cept, consider the VI, or primary visual cortex area which contains 1.5 x 10^ neurons. Although these neurons are all contained within a small spatial region, a large portion of the space is occupied by the interconnection architec- 5 1 ^ ture between neuronal layers (typically 5 x 10 interconnections) IWandell, 1995]. No current electronic system has the capability of supporting this inter connection fabric. A further aspect of biological vision modeling is the rela tively simple local processing units (neurons in the case of biological vision). Although some evidence suggests that a select few neurons have complex com putations, most are relatively simple, performing a single, non-linear operation. It has been suggested that this characteristic might be due to evolutionary biol ogy as simple processing units are very energy efficient, thereby allowing dense groupings [Veldkamp et al., 1993]. If we use biology as a starting point with the further understanding that we only have the capability to emulate, not replicate, biological vision, our design should be composed of a dense array of nonlinear computational ele ments supported by a dense interconnection fabric [Tanguay et. al., 2000]. This interconnection fabric needs to provide for weighted connection pathways between computational elements. Furthermore, let’s consider the pathways to be configured dynamically, meaning their properties can be altered in order to support supervised or unsupervised learning. When correctly configured this design has potential for applications such as pattern/target recognition, vision cognition and image recognition, and complex control, all of which are difficult to implement using conventional computer technologies. Photonic multichip modules (PMCM) have been previously proposed for use as a high-performance neural network-like computational device [Jen kins, 1992]. This theoretical device was shown to have significant advantages 6 over conventional electronic approaches due in large part to the use of a novel, massively parallel optical interconnection fabric between layers of simple elec tronic processors. This fabric, previously implemented using a multiple quan tum well (MQW) spatial light modulator (SLM), a necessary optical power bus for coupling light into the PMCM from an out-board optical source, combined with analog weighted diffraction optical elements (DOEs), allowed a dense, parallel optical interconnection between electronic processors. A previously proposed PMCM [K. Ananthanarayanan et. al., 1995] is discussed in this thesis that uses a vertical cavity surface emitting laser (VCSEL) instead of an optical power bus and the multiple quantum well modulator array as in the other implementation. This configuration allows for easier device integration and implementation since the necessary optical power is now contained on-board. The advantages and associated disadvantages of this implementation will be discussed later. This PMCM with VCSEL array is shown schematically in Fig. 1 - 1 . In the first part of this thesis we quantitatively evaluate general purpose computers for use as smart cameras instead of our PMCM architecture. In doing so we compare current and future technologies that might allow these devices to better perform the higher level vision cognition tasks we attempt to solve using our novel approach. We will see that although some flexibility is afforded using workstation class machines, significant bottlenecks still predi cate the use of a new approach. One approach that the commercial company IVP used for their smart camera, the MAPP 2200, is also described in this the 7 Silicon GaAs Diffractive Optical Element Silicon Det. Elect, Det. Elect. VCSEL VCSEL Elect. Elect. F igure 1-1. Photonic multichip module with integrated V C SELs flip chip bonded to a silicon, integrated circuit substrate. The use of a substrate co n taining diffractive optical elem ents provides for the creation o f a unique opti cal interconnection pattern between electronic layers. sis. Their choice of architecture dictated necessary trade-offs that are explored and compared to the performance of general purpose computers. Finally, con sidering the rapidly advancing nature of computer technology, we then attempt to show how a potential future computer architecture, namely a large scale par allel computer configured as a Beowolf cluster, fares with high/low level visual cognition tasks such as those performed by smart cameras. We then show the advantages of our approach using the photonic multi chip module. We discuss the use of a VCSEL array as the optical source for the 8 system and compare/contrast this approach to the previous PMCM design using an MQW-SLM. In order to construct our proposed integrated system, a new and advanced method is needed to combine diffractive optics, thin-films, and elec tronic/photonic packaging in an integrated package. The various chapters in this thesis treat each topic individually, but the reader should proceed with the understanding that all the topics are, in fact, complementary to each other. As an example, the diffractive optical elements described in Chapter 4 are further enabled using a thin film coating for optimal performance as described in Chapter 5. Where appropriate, these crossover topics are detailed. Diffractive optical elements (DOB) are discussed in Chapter 4, which starts by considering the design and fabrication of diffractive elements config ured as computer generated holograms (CGH) in a high-index substrate. These CGHs are used for both fan-in and fan-out optical interconnections and, in par ticular, are used to generate the weighted, analog optical spot patterns to opti cally connect adjacent vertical electronic layers. We demonstrate up to a 4 x 4 optical weighted fan-in/fan-out using a DOE on a high-index substrate, the first such demonstration to this author’s knowledge. A new, unwanted optical effect caused by Fabry-Perot interference that affects the performance of high-index DOEs is also explored in this chapter. This effect alters the designed output optical intensity pattern by up to 50%. To the best of the author’s knowledge, no such effect has yet been reported or analyzed. 9 AR coatings atop diffractive optical elements are also explored in this chapter. Although others have suggested thin films on DOEs as a means to increase optical throughput [Ananthanarayanan, 2003; Pawlowski, 1994a; Pawlowski, 1994b] we investigate the effect of the thin films on the designed-for DOE output optical intensity profile. We show for the fiist time that not only does an AR coating on high-index diffractive optics increase the optical throughput but, in most cases, an AR coating is a requirement for the correct operation of these optical components. Further in Chapter 4, a novel and complementary technology base to construct the previously reported devices known as stratified volume holo graphic elements (SVHOEs) is presented [Johnson et al., 1988a; Johnson et al., 1988b; Nordin, 1993]. This new device, known as a stratified volume diffrac tive optical element (SVDOE), has similar optical properties to SVHOEs, but a novel fabrication technique using an electronic packaging technology allows for the integration of specifically tailored optical materials, in addition to potentially being easier to manufacture. This technology base shows promise for use as a novel interconnection fabric for biological vision modeling and/or artificial neural networks since it meets the requirements of both by providing large numbers of interconnections and a weighted fan-in/fan-out network topology. As was seen during the investigation of high-index DOEs, Fabry-Perot interference effects also occur with SVDOEs. Due to the way SVDOEs are constructed, this effect severely limits device performance. Using 10 a rigorous coupled wave analysis (RCWA) computer modeling program, these effects are fully characterized. Results for thin films configured for use as a anti-reflection (AR) coat ings demonstrate an increase in optical throughput for the entire system, as expected. Precise characterization of the optical throughput is needed in order to manage thermal dissipation loads, calculate through-wafer optical intercon nection performance, and quantify signal-to-noise ratios for the necessary elec tronic detector arrays. The same AR coating is further shown to provide needed ground planes for EM reduction in our stacked architecture. Additional benefits include equipotential biasing of electronic components, wide-bandpass optical transmission properties, good angular sensitivity, and tunability of thin film performance during fabrication. Significant advances were necessary in flip-chip bonded electronic/pho tonic packages using indium bumps in order to integrate our devices. Typically, flip-chip bonding requires a dual-bump bond structure, meaning that the indium bumps are co-located on both mated substrates prior to bump bonding. For integrating devices with either roughened surface profiles or devices with very little working space for indium bump deposition, a new method of electri cal connections via indium bumps has been developed: the single-sided indium bump process. The advantages and disadvantages of this new bonding tech nique are fully explored. 11 1.4 Thesis Organization The functional requirements for smarts cameras are described in Chapter 2. In order to help define our technological approach, a number of applications are also discussed. After these issues are presented, the use of a commercial smart camera, the I VP MAPP 2200 is explored. Due to the rapid advanced in computer technology it is also fitting to compare both current and (potential) future general purpose computer architectures for use as smart cameras. Chapter 3 surveys our approach to smart cameras through the use of a multilayered device configured as a photonic multichip module. This architec ture supports a massive parallel optical interconnection system, thereby provid ing a weighted, analog interconnections among simple electronic processors. Originally configured with multiple quantum well (MQW) modulators, the availability of vertical cavity surface emitting lasers (VCSELs) now allows for a simplified design. The requirements for the use of VCSELs are further exam ined in this chapter along with their advantages and disadvantages. Finally, optical power budgets are explored in this chapter. Diffractive optical elements are discussed in Chapter 4. Their design and fabrication on a high-index substrate, as dictated by the requirements of the PMCM, are discussed. SVDOEs are then introduced, including a complex modeling tool that accurately predicts their performance, with and without optical thin-film AR coatings. 12 This same modeling tool is used in Chapter 5: Thin Films for the model ing of PMCMs. Having already identified potential limitations in performance for both DOEs and SVDOEs, the modeling tool demonstrates that the use of a thin film anti-reflection coating is required for the correct operation of both dif fractive devices. Chapter 6 covers flip chip bonding, including the use of both traditional double-sided and the newer approach, single-sided bumping. Electrical resis tances for both approaches are explored in this chapter, along with the other advantages/disadvantages of each. In Chapter 7 final device integration is discussed. In particular, a number of experiments in which the flow of information from electrical to optical to electrical modes or representations is detailed. Potential uses for the PMCM/smart camera system are detailed in Chap ter B. This chapter further explores augmented reality systems, immersive cam era systems, and possible neuro-biological prosthetic devices. Chapter 9 discusses both future research directions, followed by a sum mary of the thesis. 1.5 References K. Ananthanarayanan, C. H. Chen, S. DeMars, A. A. Goldstein, C. C. Huang, D. Su, C. B. Kuznia, C. Kyriakakis, Z. Karim, B. K. Jenkins, A. A. Sawchuk, and A. R. Tanguay, Jr., “Multilayer Electronic/Photonic Multichip Modules with Vertical Optical Interconnections,” In OS A Annual Meeting, Technical 13 Digest 1995, 1995 OS A Technical Digest Series (Optical Society of America, Washington, DC) (1995). I. Biederman, “Visual Object Recognition,” in S. G. Kosslyn and D. N. Osherson, Eds., An Invitation to Cognitive Science, 2nd E d ., MIT Press, Cambridge, Ch. 4, p. 121-165, (1995). B. K. Jenkins and A. R. Tanguay, Jr., “Photonic Implementations of Neural Networks,” in Neural Networks for Signal Processing, B. Kosko, Ed., (Prentice- Hall, Englewood Cliffs, NJ, 1992), pp. 287-382, (1992). R. V. Johnson and A. R. Tanguay, Jr., “Stratified Volume Holographic Optical Elements,” Opt. Lett., 13(3), p. 189-191, (1988a). R. V. Johnson and A. R. Tanguay, Jr., “Stratified Volume Holographic Optical Elements,” Optics News, 14(12), p. 30-31, (1988b). M. S. Livingston and D. H. Hubei, “Segregation of form, color, movement, and depth: Anatomy, physiology, and perception” , Science, 240, p. 740-749, (1988). C. von der Malsburg, “The Correlation Theory of Brain Function”, Internal Report No. 81-2, Max Planck Institute for Biophysical Chemistry, (Gottingen, Germany, 1981). B. W. Mel, “SEEMORE: Combining Color, Shape, and Texture Histogramming in a Neurally Inspired Approach to Visual Object Recognition,” Neural Computations, (9), p. 777-804, (1997). 14 G. Nordin, “Volume Diffraction Phenomena for Photonic Neural Network Implementations and Stratified Volume Holographic Optical Elements, ” Ph.D. Thesis, University of Southern California, (1993). E. Pawlowski, H. Engel, M. Fersti, W. Furst, and B. Kuhlow, “Diffractive Microlenses with Antireflection Coatings Fabricated by Thin Film Deposition,” Opt. Eng., 33(2), p. 647-652, (1994 a). E. Pawlowski and B. Kuhlow, “Antireflection Coated Diffractive Optical Elements Fabricated by Thin Film Deposition,” Opt. Eng., 33(11), p. 3537-3546, (1994 b). A. R, Tanguay, Jr., B. K. Jenkins, and A. A. Sawchuk, “Dense 3-D Integrated Electronic/Photonic Computing Structures Enabled by Diffractive Optical Elements,” AFOSR Report, Washington, D.C., p. 1-29, (1993). A. R. Tanguay, Jr., B. K. Jenkins, C. von der Malsburg, B. Mel, G. Holt, J. O ’Brien, I. Biederman, A. Madhukar, P. Nasiatka, and Y. Huang, “Vertically Integrated Photonic Multichip Module Architecture for Vision Applications” , Proceedings of the International Conference on Optics in Computing (OC 2000), (International Commission for Optics, Quebec City, Canada, p. 1-17, June 18-23,2000). W. B. Veldkamp, “Wireless Focal Planes ‘On the Road to Amacronic Sensors”, IEEE Jour. Quant. Electronics, 29(2), 801-813, (1993). Wandell, B. A., Foundations of Vision, Sinauer Associates, Inc., Sunderland, Massachusetts, (1995). 15 Chapter 2 System Level Considerations: Motivation for the Research 2.1 Introduction The quest for real-time object/scene recognition has been ongoing since the early 1960s [Runge et al., 1968; Peterson et al., 1978; Mead, 1989]. A wide variety of smart camera systems have been suggested in order to achieve such object/scene recognition with a compact, low-power device that exhibits enhanced features over a traditional “picture-taking-only” camera. This sec tion includes the results of characterizations of different smart camera designs as obtained by direct experimentation. In so doing it establishes a baseline for comparisons with the PMCM approach discussed in Chapter 3. In Sections 3.1 and 3.2, selected smart camera designs from both aca demia and industry will be examined. In Section 3.3 the requirements for the experimentation needed to compare dissimilar designs is presented. Section 3.4 introduces and then describes in detail one of the most visible commercial smart cameras, the IVP MAPP 2200. After detailed measurements are made 16 with this system, we compare it to several popular, general-purpose computer workstations in Section 3.5, again using the same baseline experimental proce dure. Section 3.6 introduces an advanced computer architecture known as clustering. As the clustering architecture is the most logical path to future high-performance computing systems (e.g., the Petaflop class), we construct a simple high performance computer cluster system using a set of commercial Apple Macintosh G3 computer systems and compare the performance to the before-mentioned MAPP 2200 smart camera and general-purpose worksta tions. Section 3.7 discusses the final results and prepares the reader for our proposed smart camera architecture based on a photonic mulilayer stack archi tecture. 2.2 Introduction to Smart Cameras A smart camera is a sensor system containing both photodetection ele ments and computational elements. Phototransistors, photodiodes, or photo gates (i.e., MOS capacitors exposed to light) are the most common sensor elements, with computational elements consisting of binary, analog, or mixed-mode designs. The next two sections examine some existing smart cameras that have been constructed in both university and industrial research groups. 17 2.3 Selected Smart Camera Designs 2.3.1 University-Based Perhaps no research group has influenced the field more than Carver Mead’s VLSI research group. His analog VLSI designs have evolved from early simple logarithmic image sensors built on silicon to fully “smart” sensors based on biological models of vision, the cochlea, and other types of biological neuronal systems. Elements of these designs form the basis of neuromorphic engineering. Christoph Koch is also performing similar work at CalTech [Koch et al., 1991; Koch, 1991], although his chips are much more closely coupled to biological neural systems in design. Other sensor designs inspired by biologi cal models have been created by Andreas Andreou (John Hopkins) [Andreou et al., 1994a; Andreou et al., 1994b], Abdesselam Bouzerdoum (Univ. of Ade laide, Australia) [Bouzerdoum et al., 1992], Thierry Benard (ETCA, France) [Benard et al., 1994], and John Harris (Univ. of Florida)[Harris et al., 1990]. Imaging sensors designed for limited feature extraction or basic image processing is another area of university-based research. These devices often use CMOS-type Active Pixel Sensors (APS) combined with computational electronics to create devices that have high-performance over a small window of operations. Examples include work by Andres Astrom (Linkoping Univer sity and later IVP) [Astrom et al., 1996], and Hatori-Aizawa (Tokyo Univer sity) [Aizawa etal., 1996]. 18 The sensor type employed can further classify smart cameras. These include spatial-processing sensors that are used for selected local image pro cessing algorithms [Mead, 1989; Forchheimer et al., 1983; Astrom, 1993], spa tio-temporal sensors using cooperative time-space processing algorithms [Tanner et al., 1988; Delbruck, 1993; Lyon, 1981], and cellular neural network (CNN) sensors [Espejo et al., 1993] which can be designed to combine ele ments of both previous sensor types. 2.3.2 Commercial-Based A few companies are trying to commercialize various smart camera designs. IVP’s MAPP 2200 and 1100 series smart cameras are some of the more readily available systems. Mitsubishi has a number of sensors for hand and eye recognition, but these designs are still configured as research proto types [Nitta et al., 1993; Lange et al., 1993; Nitta et al., 1993]. The first gener ation of truly consumer smart cameras (mass produced) will probably come from the likes of Kodak or Motorola, employing an APS sensor with enough limited computational elements for basic image compression. 2.4 Benchmarking of Smart Cameras In this section we benchmark three systems in order to compare/contrast their relative strengths and weaknesses. The benchmarks were performed using the Sobel convolution operational filter and have been implemented on a (1) 19 commercial smart camera (the MAPP IVP 2200), (2) general purpose worksta tions, and (3) a specialized cluster computing system. The Sobel gradient image operator is one of the most universally employed image enhancement procedures for sharpening images in order to perform subsequent feature extraction algorithms, especially in the spatial domain. Given a two-dimensional image function f(x, y), the gradient of f at coor dinates (x, y) is defined by the vector G[f(x,y)) = 5v ~G.~ £ — Gy < 5 v It’s important to realize that this vector points in the direction of the max imum rate of increase of the function f(x, y), and that the magnitude of G[f(x, y)] is given by the following expression: which is the maximum rate of increase of f(x, y) per unit distance in the direc tion of G[f(x, y)J. This magnitude operation is used for edge detection applica tions. The gradient can be implemented using a first-order difference equation in a 2 x 2 pixel region. A more robust technique involves a correlation using a 3 x 3 pixel region around a point (x, y) of the image f(x, y). Consider a small region of the image f(x, y) as shown schematically below: X 1 X2 X3 X4 X5 X6 X7 X8 X9 The pixel at location X 5 is the gray level of the image pixel (x, y). By plac ing the following two submasks about the pixel X 5 we can calculate the gradi ent vector in the x direction -1 -2 -1 0 0 0 1 2 1 and the y direction 21 -1 0 1 -2 0 2 -1 0 1 Hence, the gradient vectors Gx and Gy are given by the expressions Gx — (.r7 + 2x8 4 - v9) — (x, + 2.v2 + .v3) Gv = (* 3 + 2xb + xl}) - (.v, + 2.xA + v 7) with g = V Gr + G,: An approximation for faster operation with minimal loss of information can be made by noting that G = JGX " + Gv~ =|G,| + The image chosen for benchmarking is the 256 x 256 pixel version of Lena, the standard image used for image processing applications. It is shown in Fig. 2-l(a). 22 After execution the following image is created illustrating the magnitude of the Sobel operation about all pixels in the image. This is seen in Fig. 2-1(b). The white areas in the image are the pixel regions with the greatest gradients. The next three sections implement the Sobel convolution filter on differ ent platforms: the IVP MAPP2200 smart camera, a variety of general purpose workstations, and a high-performance cluster computing system based on the Beowulf computer architecture. 2.5 IVP MAPP 2200 Smart Camera The IVP MAPP 2200 Smart Camera is a CMOS-based, active-pixel digi tal camera system containing 256 parallel processing elements designed for low-level vision processing routines. Each SIMD processor operates at 4 mil lion instructions per second. Figure 2-2 shows the IVP MAPP2200 sensor head. 2.5.1 MAPP 2200 Architecture The functional block diagram of the Matrix Array Picture Processor (MAPP) 2200 is shown in Fig. 2-3. The sensor array contains 256 rows and 256 column of photodiodes. The image data on each photodiode is read out row-rise in parallel to an analog reg ister for each column of photodiodes. As such, there are 256 analog registers contained on the entire MAPP sensor. The analog registers take the form of a 23 Figure 2 -1 . (a) Original 256 x 256 pixel, 256 grey level im age o f Lena. F igure 2 -1. (b) Image o f Lena after 3 x 3 Sobel filtering algo rithm. N otice the bright areas in this image are the ones with the greatest gradient in the original im age. Figure 2-2. The IVP MAPP2200 sensor head [Astrom, 1993]. capacitor. The charge stored at this register is then placed into an analog-to-dig- ital (A/D) circuit, which places the resultant 8 -bit binary valu * :nto eight suc cessive 1-bit registers labeled A0-A7. (Note, this is not a single 8 -bit register, but eight single 1-bit registers. This has some advantages for computational processing but will not be addressed here.) Communicating through a simple bus, the binary data can be sent to the GLU/NLU/PLU Arithmetic Logic Unit (ALU). Comprised of the Global Logic Unit (GLU), the Neighborhood Logic Unit (NLU), and the Point Logic Unit (PLU), the ALU performs all the compu tations. The GLU performs global operations on the entire row of 256 Process ing Elements (PE), the NLU employs a 3 x 1 binary mask operation on the nearest two PE, while the PLU operates locally within each PE and performs simple Boolean operations. Available to each PE are 127 bits of random access 25 !. 256 x 256 sensor analog resister . v* AO - A7 •• ” C A I A w ? ’ t * K * r , SO - S7 w »iw »w iH nw »jw i i y l{i ' i^ { A * u * < < •• 1 . n * ~ > 'n 't% ' 4 * * .' ” I V , -, f > ... ■ - . - i .......... .'.. * 5.*? tsr Memory R O - R95 ‘ - » <P\... Control I/O Channel ,L ~ V » * L < GLU/NLU PLU n * < 7 * ** v4 # , „ f ^* ; . < tp<u> Status F igure 2-3, M A PP 2200 function block diagram. memory and 1-bit of read only memory (set to 0). All digital output is formed through eight 1-bit registers labeled S0-S7. 2.5.2 MAPP 2200 Performance The MAPP 2200 camera frame-rate is limited only by number of compu tations programmed by the user. It has a theoretical computational throughput of almost 4 million instructions/sec Some typical performance parameters for the following filters are shown below in Table 2-1. Table 2-1: Performance of MAPP 2200 Smart Camera I B S 3 x 3 2 0 0 0 frames / sec 0.0005 7 x 7 400 fram es/sec 0.0025 M edian Filter 60 frames / sec 0.0167 Sobel Filter 30 frames / sec 0.033 seconds/ frame All of the filters described in the table below are preprogrammed in the MAPP 2200 camera system. Additional image processing filter operations can not be performed. 2.5.3 MAPP 2200 Limitations There are a number of other major limitations on the IVP smart camera. The most serious limitation is the lack of programmable filter operations. Since a significant amount of image processing and feature recognition can be per formed using mask convolution operations, a smart camera with programmable filters would be a significant achievement. 27 The current camera implementation does not support color, although a color sequential technique could potentially be implemented using tunable color filters. The lack of color support limits the camera to a smaller number of feature extraction routines. Another major limitation was the difficulty in programming the IVP sen sor. First, assembly language knowledge is required. Although documentation claims that you can write a C program on a PC computer to program the cam era, all instructions sent to the camera must be in assembly language. The nature of the IVP architecture also imposes a number of limitations. First, there are only 127 bits of RAM. Also, one is required to work with mem ory bits instead of bytes, greatly increasing the program complexity. There is no support for (IF (expression one) THEN (expression two)) statements. Finally, all computational operations are performed on the entire row of pro cessing elements (PE) with no way to program individual processors. 2.6 Characterization of General Purpose Computers As was seen, current smart cameras are often “smart” only within very confined regions, namely localized operations not requiring high bandwidth or large memory access. In is is not quite the hindrance as it appears to be, as a multitude of basic image/visual processing tasks rely on some localized filter ing processing. After these preliminary processing steps, more detailed feature extraction and recognition can take place. Most current image/visual process ing is performed by systems composed of a CCD camera sending image data to 28 a general-purpose computer for off-the-shelf processing. In this section we benchmark, again using the Sobel operation, general purpose workstations/per sonal computers and compare the results to the aforementioned MAPP 2200. Table 2-2 shows the times for execution of the Sobel operation on this test image. Although most workstations can perform the Sobel operation in less than half a second, it can’t compare to the performance of the IVP MAPP 2200. As most general-purpose computers are still built around the Von Neumann architecture, it is expected that the MAPP IVP will probably out perform most computers owing to the inherent memory bottleneck that exists. Table 2-2: Sobel Operation Times HP (apollo)’ 1 - 0.962 1.181 SGI Indy R50002 0.351 0.392 Sun Ultra^ 0.297 0.216 SGI R100004 0.087 0.109 IVP MAPP 2200 NA 0.030 1- OS : HP-UXCompiler : gcc 2.7.2 2- OS : IRIX 6.2Compiler : gcc 2.7.2.1 CPU : MIPS R5000, 180 Mhz 3- OS : Sun OX5.5.1 Compiler : gcc 2.7.2.1CPU : UltraSPARC, 170 Mhz 4- OS : IRIX 6.4 Compiler : gcc 2.7.2.1CPU : MIPS R10000, 195 Mhz 29 2.7 MPI Implementation In the previous section a Sobel gradient index filter was implemented on a variety of common personal computers (PCs) and workstation class machines. These types of computations are indicative of the types encountered when per forming common visual interpretation and classifications that are in use today. In this section we now consider a high-performance, state-of-the-art computer system that has shown the ability to scale to the petaflop computational perfor mance range. Although our implementation will not exceed the gigaflop perfor mance range, the computer architecture topology, interconnection scheme, and programming methology are similar to those in use at Los Alamos National Laboratory (Avalon — 48.5 gigaflops) and the NOAA Forecast Systems Labo ratory (est. 330 gigaflops), which will be used for most future US weather fore casting. The increased performance of this system lies in the larger number of central processing units and the incorporation of dedicated localized networks for faster interconnections. A short introduction to cluster computing will be followed by the same implementation that was performed in the previous section. After comparing the relative performance between these computer systems some concluding remarks will be made concerning the future scalability of this technology. 2.7.1 MPI Results A cluster of Apple Macintosh G3s was chosen as the system. The first test consisted of seven G3 (266 MHz, 192 MB RAM, 4 G HD) running the 3 x 3 30 Sobel kernel across the Lena 256 x 256-test image. These seven G 3’s each operate on an individual portion of the test image and yield a benchmarking score of Table 2-3: Sobel operational performance on MPI system Sobel Filter 4.587 fram es/sec 0.218 sec/fram e This number is a measurement of the time it takes the seven G3s to oper ate on the image or, in this case, operate on a different 1/7 section of the test image and then send the completed data back to the central node of the cluster for reassembly. Due to the small amount of data transferred (the image size is 256 x 256, 8 -bit grayscale) and the 10Mbit Ethernet system connecting the computers this communication system has little effect on the overall system performance. For this test we only sent the results back to the central node once. A more accurate portrayal of this system’s performance is when this sys tem is not used for off-line processing, but for real-time image processing. In this case we must distribute the data to each individual computer, have each computer independently operate on a select portion of the image (dependent on the number of available processors), wait for all computers to finish their pro cessing, have all computers send their data, and finally have the central node of 31 Execution Time as a Function of Participating Processors 2.0 o & a ) E 1 5 to 1 15x15 Kernel Size 11 x 11 Kernel Size S 0.5 L U 7 x 7 Kernel Size .3x3 Kernel Size. 2.5 0.0 5.0 4.0 4.5 3.0 3.5 2.0 Number of P rocessors Figure 2-4. Graph o f Sobel filter execution tim e as function o f processors. Four different Sobel kernel sizes are graphed. the cluster reassemble the data in the correct sequence. This occurs before the next image scene would be computed in a video sequence. The following is a graph of execution time as a function of participating processors for an Apple G3 computing cluster. This graph also plots the data obtained when a large kernel size is desired, for example, when more global image parameters are needed. A couple key points can be ascertained. Most importantly, the graphed data show an asymptotic relationship, namely that as the number of processors grow larger the corresponding increase in performance gets smaller until it sat 32 urates. At this point the communications, not the processing, dominates the total execution time. This graph also shows that when more global operations are needed, multiple processing elements can make a substantial difference in total processing time; but this too has a leveling in performance as processors are added. We see finally that parallel processing is not directly scalable as pre dicted by theory. 2.8 Conclusion The IVP MAPP is a high-performance, limited smart camera. For low-level image processing operations such as threshold equalization, Sobel operations, edge detection, and thinning, this camera has no equal in general workstation-class computers. Unfortunately, the architecture is designed only for these operations. Additional processing capabilities are not only slow, but in most cases, can not be performed at all. This is especially true when global parameters are needed for image recognition/cognition operations. General-purpose computers can extract more information from a scene but are slower in execution speed. In this case the total execution time is not always dependent on the speed of the CPU but rather the communications bot tleneck between the CPU and memory. This communications bottleneck was further explored using a cluster computer system. The significant result in this set of experiments is that classes of computer problems, such as image/scene recognition and feature extraction, cannot be solved by adding more CPUs. Rather, a robust interconnection scheme is needed. 33 2.9 References K. Aizawa, Y. Egi, T. Hamamoto, M. Hatori & J. Yamazaki, ”A image sensor for on-sensor-compression,” Workshop on Computer Architecture for Machine Perception, p. 14-20,(1995). K. Ananthanarayanan, C. H. Chen, S. DeMars, A. A. Goldstein, C. C. Huang, D. Su, C. B. Kuznia, C. Kyriakakis, Z. Karim, B. K. Jenkins, A. A. Sawchuk, and A. R. Tanguay, Jr., “Multilayer Electronic/Photonic Multichip Modules with Vertical Optical Interconnections,” In OS A-Annual Meeting, held at Portland, Oregon, (Optical Society of America, Washington, D.C.), (1995). Andres Astrom. Smart image sensors. PhD thesis, Department of Electrical Engineering, Likoping University, S-581 83 Linkoping, Sweden, (1993). A.G. Andreou and K.A. Boahen, “A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS,” in Proc. 37th Midwest Symposium on Circuits and Systems, p. 97-102, (1994). A.G. Andreou and K.A. Boahen, “Neural information processing II,”. In M. Ismail & T. Fiez, editor, Analog VLSI Signal and Information Processing, Chapter 8, p. 358-413. McGraw-Hill, (1994). A. Astrom, J. Eklund & R. Forchheimer, “Near-sensor image processing- theory and practice,” Proc. SPIE, Advanced Focal Plane Processing and Electronic Cameras, Vol. 2950, p. 242-253, (1996). T.M. Bernard, B.Y. Zavidovique & F.J. Devos, “A programmable artificial retina,” IEEE Journal of Solid State Circuits, Vol. 28, No. 7, p. 789-798, (July 1993). 34 A. Bouzerdoum, R.B. Pinter and B. Nabet, “Nonlinear lateral inhibition applied to motion detection on the fly visual system,” In R.B. Pinter & B. Nabet, editor, Nonlinear Vision, p. 423-450. CRC press, (1992). T. Delbriick “Investigations of analog VLSI visual transduction and motion processing,” Ph. D. Thesis, California Institute of Technology, Pasadena, California, (1993). S. Espejo, A. Rodriguez-Vazquez, R. Dominguez-Castro, B. Linares and J.L. Huertas, “A model for VLSI implementation of CNN image processing chips using current-mode techniques,” Proc. IEEE Int. Symposium on Circuits and Systems, p. 970-973, (1993). R. Forchheimer and A Odmark, “A single chip linear array processor,” Proc. SPIE, Applications o f Digital Image Processing, Vol. 397, pp. 425-430, 1983. J.G. Hands, C. Koch & J. Luo, “A two-dimensional analog VLSI circuit for detecting discontinuities in early vision,” Science, Vol. 248, p. 1209-1211, (June 1990). C. Koch, “Implementing early vision algorithms in analog hardware-an overview,” Proc. SPIE, Visual Information Processing: From Neurons to Chips, Vol. 1473, p. 2-16, (1991). C. Koch, A. Moore, W. Bair, T. Horiuchi, B. Bishofberger & J. Lazzaro, “Computing motion using analog VLSI vision chips: an experimental comparison among four approaches,” Proceedings of the IEEE Workshop on Visual Motion, p . 312-24, (1991). 35 C. B. Kuznia, C. C. Huang, K. Ananthanarayanan, C. H. Chen, and A. A. Sawchuk, “Micro Diffractive Optical Element for Smart Pixel Fan-out Interconnections,” OS A, Annual Meeting (Optical Society of America, Washington, D. C.), ILS/X1, p. 149, (1995). E. Lange, E. Funatsu, K. Hara & K. Kyuma, “Artificial retina devices — fast front ends for neural image processing systems,” Proc. Int. Joint Conf. Neural Networks, p. 801-804,(1993). R.F. Lyon, “The optical mouse, and an architectural methodology for smart digital sensors,” VLSI-81-1, p. 1-19, August (1981). C. Mead, “Adaptive retina,” In C. Mead & M. Ismail, editor, Analog VLSI implementation of neural systems, chapter 10, pp. 239-246. Kluwer Academic Publishers, Boston, 1989. Proceedings of a workshop on Analog Integrated Neural Systems. Y. Nitta, J. Ohta, S. Tai & K. Kyuma, “Optical neurochip for image processing,” Proc. Int. Joint Conf. Neural Networks, Vol. 1, p. 805-808, (1993). Y. Nitta, J. Ohta, S. Tai & K. Kyuma, “Monolithic integration of optical neurochip with variable sensitivity photodetector,” IEEE Photonics Technology Letters, Vol. 5, No. l,p p . 67-69, (January 1993). G.P. Petterson & L. Lindholm, “Position sensitive light detectors with high linearity,” IEEE Journal of Solid State Circuits, Vol. 13, No. 3, pp. 392-399, (June 1978). 36 R.G. Runge, M. Uemura & S.S. Viglione, “Electronic synthesis of the neural networks in the pigeon retina,” In Cybernetic Problems in Bionics, pp. 791-800, Dayton, Ohio, USA, 3-5 May 1968. J. Tanner and C. Mead, “An integrated analog optical motion sensor,” In R.W. Brodersen & H.S. Moscovitz, editor, VLSI Signal Processing //, p. 59-87. IEEE, New York, (1988). 37 Chapter 3 PMCM - Photonic Multichip Module 3.1 Introduction The previous chapter compared single and multiprocessor conventional computer architectures for use in a simple visual processing/recognition task, namely the Sobel gradient index filter. It was determined that the interconnec tion fabric had a heavy influence on the overall computational performance. This was especially evident during the implementation of the Sobel gradient filter operation on the MPI cluster. In this case, as more processors were added, the total computational performance quickly leveled off due to network overhead of the 10-baseT ethernet connection (operating at 10 Mbps) between individual processors in the MPI cluster. In this chapter we introduce our smart camera architecture, paying partic ular attention to the use of biologically inspired layering and the high perfor mance optical interconnection architecture. The key system component of our smart camera is a novel 3-D photonic multichip module (PMCM) that incorpo rates an optical interconnection fabric between arrays of simple electronic pro- 38 cessing elements, as has been previously proposed [Tanguay, 1993; Jenkins et. a l., 1992]. This novel dense interconnection architecture supports an intercon nection fan-out/fan-in capability and is matched for high performance comput ing architectures, particularly visual processing and target recognition tasks. By tightly coupling the processors together with this novel interconnection technology, a high performance computational system can be constructed that is ideally suited for our adaptive vision sensor. A schematic figure of a generalized, proposed PMCM is seen in Fig. 3-1. This device has been discussed [Tanguay, 1993] for use as an optically inter- Optics/ Photonics F igure 3 -1 . Conceptual diagram o f 3-D photonic m ultichip module (PM CM ) device, showing silicon-based analog/digital V LSI chips and optical fan-out/fan-in interconnection fabric betw een these chips [Tanguay, 1993]. connected artificial neural network, another application that is well suited to a photonic implementation [Jenkins et. a l., 1992]. The inherent parallelism and Si licon Ei ectronics y 4 - ? v / y : 39 interconnectivity of optics, coupled with the large integration densities, flexi bility, and adaptability of current VLSI technologies allows for the unique real ization of artificial neural networks (ANNs), which require parallel structure, large interconnectivity, and plasticity. These attributes are paramount for this thesis’ proposed smart camera. We begin this chapter similar to the previous chapter: namely by discuss ing if any existing technology bases in their entirety can be used for our smart camera. In particular, both VLSI packaging technology and optical packaging technology will be investigated to determine if these alone can be used in place of the proposed complex electronic/photonic hybrid PMCM design of our smart camera. Therefore, we begin by discussing both 2-D and 3-D electrical packaging technologies, specifically those based on electronic multichip mod ules (MCM), including projections of future electronic packaging technologies and systems. These technologies will vary from the common (Dual-In-Line or DIP packages) to the exotic (MCM-F packaging) and will be explored from the standpoint of suitability for use in visual cognition tasks like those envisioned for our smart camera. Following electronic packaging, photonic/optical packaging solutions are investigated. Many limitations inherent in electronics packaging, such as sys tem bandwidth and input/output (I/O) count, are reduced when using available optical solutions. After discussing and comparing both electronic and photonic packaging we will determine that neither technology, in its entirety, can be used 40 for our smart camera design. Rather, a blending of both these packaging tech nologies is required and will be discussed. A component of the PMCM, and one which assists in the necessary blending of electronic and photonic devices, is a spatial light modulator, imple mented, in our system, as a vertical cavity surface emitting laser. SLM ’s are 2-D optical signal processing devices that can spatially modulate the phase, intensity, or polarization of an optical beam, based on optical or electrical inputs. For the SLM used in this thesis, an integrated silicon integrated circuit (IC) and a GaAs based VCSEL array were chosen to provide intelligent control of the laser optical intensity and, in doing so, form one of the key elements in the PMCM. As designed, the Si integrated circuit serves as the detection device, a simple computational device, and the VCSEL driver device providing the voltage driver signals needed for the individual lasers of the VCSEL array. This hybridized device permits the transformation of electrical signals into optical signals, provides optical illumination for the diffractive optical element that is needed for routing these optical signals, and finally necessitates the con version of these processed optical signals back into electrical signals for further localized processing. A partial, two element cross-section of this device is shown in Fig. 3-2. This will be discussed in more detail later. Section 3.2 discusses some of the requirements of the adaptive vision smart camera. A short examination of both electrical, Section 3.3, and optical, Section 3.4, packaging techniques and how they help dictate the choices for our PMCM design are then compared. This PMCM design is discussed in detail in 41 Silicon GaAs Diffractive Optical Element Silicon Det. Elect. Det. Elect VCSEL VCSEL Elect. F igure 3 -2 . Schem atic diagram o f m ultilayer hybrid electronic/photonic photonic multichip m odule, show ing tw o silicon V LSI chips optically interconnected by vertical cavity surface em itting laser (V C SE L ) and dif fractive optical elem ent arrays. Two adjacent p ixels are shown in cross section. Section 3.5, including details of what was previously proposed by others, both at USC and other institutions, and how this new implementation is unique and further developed by this author. This section also discusses how the PMCM can be constructed into a truly smart camera system. An essential component of this newly designed PMCM is the use of VCSEL arrays. These arrays are discussed in Section 3.6 which include? a comparison of a number of commer cially available VCSEL arrays from both NEC Corp. and MicroOptical Device, Inc. (MODE). This section also includes and characterizes a recently available 42 low-threshold VCSEL array designed and fabricated at USC that is ideally suited for our PMCM implementation. A short conclusion about the PMCM is contained Section 3.7. 3.2 Smart Camera Architecture Smart cameras are a form of adaptive vision sensors used for applications that involve object identification and classification, object tracking and dynamic targeting, and, if used for an augmented reality system, for spatial pose and orientation estimation in order to precisely overlay artificial computer generated graphics onto the natural/environmental scene. As with any sensor, the requirements are highly application dependent. As will be introduced in Chapter 8, a USC developed vision sensor package known as an Immersivision camera system has been designed as a 360° field of view (FOV) smart sensor for remote monitoring/reconnaissance. This system would ideally be small and stealthy, with little or no EM and/or optical band emissions until movement is observed. At this point the sensor might be designed to either compress the image information before sending data to a central receiver array located miles away or simply send an attention getting signal to the remote human operators. Another application for the adaptive vision sensor system might be target acquisition and/or tracking. In this case the processing latency and computational throughput might be substantially different if the vision sensor is tracking either a high speed moving object, or a slow object. Finally, when configuring an adaptive smart camera for use with 43 an augmented reality system, the human perception or response time deter mines the upper bound for the processing latency. Considering that a human eye can “process” between 24-30 discrete image frames a second, all object/scene processing on the smart camera must be performed greater than this rate. Although the required execution times for the adaptive vision sensor applications are different, the computational approaches to scene/vision pro cessing/cognition are not. In the described above cases, hierarchical process ing stages are used to extract information from the scene. Part of this functionality has been drawn from biological systems. At the retina layer of the eye, the lowest levels of vision processing are performed using a fixed layer of photoreceptors and neurons locally interconnected using fixed weighted interconnections. These operations include edge and corner detection, image intensity normalization, and some simple color processing. As information moves further up our visual processing system more global operations are per formed on this image data. This processing requires a more robust biological interconnection architecture, from 103 to 104 [Wandell, 1995; Dowling, 1992] interconnections per individual neuron. As we continue further up the biological processing stream, one truly is amazed at the performance of the biological vision processing system. Cur rently, no technologies can truly replicate the entire biological vision system. We need to be inspired by biological vision, rather than attempt to replicate these functions, in order to define an adaptive vision processing camera. 44 1 1 Incoming Light Pre-Detection Optics Detection and Local Operations Storage and X-Scrolllng Y-Scrolllng Low Level Filtering Storage and Shifting 2nd Stage of Filtering Storage and Shifting Mid-Level Feature Extraction Cellular Neural Network 2nd Mid-Level Stage Invariant Representation F ig u re 3-3. An operational schem atic o f a hypothetical multilayer PM CM . As an input scene enters the stack, the necessary low -level vision operations (e.g., contrast enhancem ent, adaptive localized gain, edge detection, Sobel gradient index filters) are performed. Travelling further through the stack the m id-level vision operations (e.g., recognition o f features in the input scene and their co-occurrence) and high level vision operations are then performed leading to a com pact, smart representation o f the input scene [Tanguay, et. al. 2001]. A general, biologically inspired schematic for our smart camera is shown in Fig. 3-3. As configured in this figure, the information flow is top to bottom between discrete electronic computational processing layers inspired by biol ogy. The detection and local operations, those dependent on the nearest or next-nearest-neighbor pixels, are performed in the first couple computational 45 “layers”. These layers might be responsible for image focus feedback, image attention actions, and/or image stabilization. As one progresses through this biologically inspired system, additional filtering and feature extraction on localized image regions are performed. These could include various process ing routines for edge or gradient detection (such as Sobel filtering), color con stancy calculations, wavelet or Gabor filter processing, and/or optical intensity matching. At the bottom of the stack global operations such as scaling, image transformations, elastic graph matching, or high-level model representation (such as those driven by the geon model representation [Hummel et al., 1992; Biederman, 1995]) are performed. Typical performance parameters of the human visual system have been estimated in a number of biological studies [Tanguay et. al., 2002; Livingstone et al., 1988; Veldkamp et al., 1993]. Although the relative neurobiology “band width” of the human brain is low, with some estimates near 80-100 Hz, the number of neurons and their associated interconnections allow an estimated 5 x 1014 connections per second (CPS). This CPS metric assumes that biological systems have a direct analogy with this common neural network implementa tion metric. Further information on this model is detailed elsewhere [Tanguay et. al., 2002]. The next sections in this chapter look at some existing electronic and pho tonic technologies that can be used to help define architectural aspects of our system. One will discover the flexibility of VLSI electronics combined with the interconnection fabric afforded by the micro-optical devices provide the 46 ideal balance required for our adaptive vision sensor. Only in this way can one approach some of the performance metrics of the human visual system. 3.3 Electrical Interconnections High performance electronic VLSI devices seek an optimal compromise between bandwidth limitation, computational performance, cost, unwanted thermal issues, ease of manufacturing, materials, etc. Our proposed system introduces optics as a way to interconnect these processors, but combining optics in this way with computational electronics is not trivial. Hence, in this section, we once again examine existing technology bases searching for possi ble solutions for the integration of our smart camera. Electronic packaging in this discussion refers to the technique of send ing/receiving electronic signals from an integrated circuit to other companion integrated circuits or to other electronic devices. Typical performance parame ters used to evaluate packaging include operating speed, number of input/out put (I/O) connections, cost, thermal properties, materials, and the ease of manufacturing. All these issues help define the bandwidth limitations, the power dissipation limitations, and the interconnection topology limitations of a package type, issues of primary importance for adaptive smart cameras. Older electronic packaging technologies including Dual-in-Line (DIP) packages, Leadless Chip Carrier (LCC) packages, and Pin-Grid-Array (PGA) packages are already being phased out for medium-to-high performance devices due to constrained I/O counts, slow operating frequencies, and size. Hence, we will 47 only concentrate on various surface mounting and chip-scale packaging tech nologies configured into multi-chip-modules (MCM). A multichip module is an electronic packaging technology that places multiple bare die onto a single substrate containing the electrical signal and ground lines for the necessary interconnections. MCMs have a number of advantages over the previously mentioned techniques. First, since the overall packaging size is smaller, the electrical signal/trace lines are shorter, therefore there are fewer parasitics and lower electrical resistances. This technology also allows for mixed technologies on the same substrate. Additionally, different substrates can be utilized on the same MCM substrate, such as silicon, GaAs, and/or InP bare die. This flexibility allows for photonic and electronic devices to be easily integrated. Finally, MCM tends to be much more reliable as a packaging technology. The three most advanced MCM technologies are: MCM-C, based on ceramic substrates, MCM-D, based on thin-film deposition techniques and hence lends itself to semiconductor fabrication technologies, and MCM-F, based on flexible polyimide structures and tends to be the most advanced of these packaging technologies. MCM-F directly overlays the bare chips with a polymer interconnection structure and provides for a direct metallurgical con nection of the MCM interconnection structure to the bare die’s I/O pads. In this way very low parametric losses are obtained, with a high signal integrity and isolation. Some recent demonstrations of this technology show a greater than 120 dB isolation between adjacent inputs on the same device. Due to this 48 factor, the use of low voltage IC can share the same substrate with high voltage IC (such as analog IC, microwave, or power devices). In order to overcome the limitations of I/O count and spatial dimensions of these MCM designs, the next progression of electronic packaging was to uti lize the third dimension. This began in the early 90’s, mainly to increase mem ory chip densities for personal computers [Caterer et. a l., 1999; Saia et. al., 1994; Bertin et. a l., 1993] or dense memory modules for solid state audio/video recorders [Terrill et. al., 1997; Gann, 1998]. In the latter case, Texas Instru ments and Irvine Sensors stacked bare memory on edge and used a polymer, thin film metallization technique to electrically interconnect all the memory devices into a package the size of a sugar cube. Cost, reliability problems, and availability made this packaging technology difficult to get space qualified for the designed-for space satellite systems. Eventually Harris Corp. perfected these packaging techniques using a low temperature co-fired ceramic module encased in hermetic sealing glass to make one of the few high density, space qualified, 3-D memory cubes. The problem with nearly all these devices is heat dissipation as there is significantly reduced air flow around the substrates. Some of the more enter prising solutions include forced air convection [Watson et. al., 2001], fluoro- chemical liquid encapsulation [Lee et. al., 1997], boiling heat transfer [Rush et. al., 1975], and spray cooling using fluorinerts [Xia, 2001]. The last method demonstrated the removal of a 1000 Watts per cm thermal load by spraying a fluorinert solution on the back surface of a high energy laser array. 49 With the flexibility of individual VLSI integrated circuits packaged using one of the MCM techniques in this section, one would think this might be the best approach for the adaptive vision sensor. But there are significant problems with all the MCM techniques discussed here, specifically those with regards to the off chip bandwidth and input/output count. Our vision sensor system needs to perform local to global operations 0 1 1 various input image scenes. This requires a bandwidth capability not easily met using conventional electronic packaging technology. Furthermore, the bandwidth of individual data chan nels still won’t allow the needed data throughput needed for our smart camera implementation. These factors suggest the use of optical packaging technolo gies. 3.4 Optical Interconnections Optical communications typically invoke images of long-haul, long dis tance systems based on commercially available fiber optics. More recently, optical communications has evolved into shorter optical links for connecting individual computers in a local-area network (LAN), connecting separate cir cuit boards together, or for connecting individual integrated circuits on circuit boards together. Some have further suggested the use of optical interconnec tion for use to connect subsystems with an integrated circuit, possibly using photonic bandgap technologies. From electrical circuit analysis we know that an electrical wire’s maxi mum sustainable bit rate is dependent on the parasitic resistance, capacitance, 50 and inductance. At low operating frequencies resistance and shunt capacitance uniquely determine the rise and fall (or transition times) of discrete data sig nals. As the frequency increases, inductance tends to be the limiting factor and, hence, dominate the maximum data bit rate. Additionally, as operating fre quencies increase electrical signal lines tend to be more sensitive to electro magnetic interference and require more stringent impedance matching procedures to eliminate unwanted wave reflections. Although some of these limitations of electrical wires can be managed by increasing the cross-sectional diameter of these wires and making use of additional grounding lines, new problems arise since these solutions require substantial on chip VLSI surface real estate or circuit board area. The use of free space optical interconnections is one way to alleviate the limitations of electronic signal interconnection systems. In this way one can combine high data rates with multiple parallel optical channels for a high per formance interconnection system. This is a partial result of mutually incoher ent optical waves not interfering with each other as they propagate in free space (i.e., no crosstalk between adjacent data channels). Furthermore, these same waves can consist of multiple wavelengths, each encoded with different infor mation to further increase interconnection density when configured in a multi wavelength division multiplexing architecture. A number of studies confirming the performance benefits of optical inter connections in chip to chip interconnections above a certain break-even length [Feldman et al., 1988] have been performed. Furthermore, additional studies 51 consider the ideal systems level architectural configuration to maximize perfor mance based on factors such as power, delay time, and interconnect density [Feldman, 1994]. Optical solutions might seem the ideal candidate for portions of our PMCM, but there are a number of drawbacks to this technology that need to be carefully characterized before possible device integration. First, most optical systems require a high degree of alignment accuracy for optimal performance. Second, photonic devices tend to dissipate large amounts of heat. A secondary effect is that most photonic devices tend to also change their optical properties with the changing device temperature. Finally, optical packaging is still a rela tively immature technology. That being said, optical packaging still provides the necessary signal rout ing and I/O counts needed for our smart camera system. The use of electronic devices in our PMCM are still required for the computational aspects of our design and the nature/nuture learning component of our adaptive vision sensor. This required adaptability or learning capacity can’t easily be performed in a pure optical solution. The next section discusses which elements of electronic and photonic packaging are used and how they can be used to fabricate a truly smart camera. 52 3.5 Photonic Multichip Modules (PMCM) The PMCM will be built using a hybrid technology by leveraging the advances in VLSI microelectronics devices with the advantages of the opti cal/photonic interconnections. The proposed hybrid photonic/electronic tech nology is also modular to keep pace with the changing trends in VLSI technology and photonic devices. This thesis attempts to address the changing landscape of VLSI and photonic components and the packaging technology used in integrating the photonic/electronic devices in later sections. An electronic MCM provides the basis of our smart camera. In this case, the MCM allows for the direct flip-chip die attachment of silicon based inte grated circuits for the necessary learning ability with the photonic devices needed for the bandwidth and I/O data channels. In this way we play to the associated strengths of each packaging technology. These photonic systems will typically perform simple parallel tasks on massive streams of data with a low local memory requirement. This is opposite in design to high performance parallel computing machines today that are designed for low throughput and high memory operations. The technology used herein can potentially be used to build parallel computing, computationally intensive, low power, photonic computational modules that are compact and manufactured using planar micro electronic processing techniques. The necessary computational layers are implemented as a smart-pixel Complementary Metal Oxide Semiconductor (CMOS) integrated circuit hybridized via flip-chip bonding to the VCSEL laser array. The computational elements are configured in a smart pixel design as a 53 group of transistors used to convert low-level optical signals incident on its two integrated photodiode detectors into a large amplitude differential output cur rent suitable for driving a VCSEL. Figure 3-4 shows one proposed system level architectural model of the smart camera. The photonic multichip module in the smart camera is indicated in the middle of the figure. In this proposed model a 2-D scene/image is cap tured with a traditional sensor/detector array. An optional set of pre-detection optics can be placed in-front of the sensor/detector array and can take the form of wavelength filters, polarization filters, etc. to be used for additional recogni tion/parsing information. The image sensor then sends the image data to an initial VCSEL for conversion of the electrical signals representing the image data into a set of optical signals. Ideally each pixel of the sensor would be 1 -to-1 matched to a unique laser in the VCSEL array. At this point the PMCM takes over the signal processing. The DOE/VLSI electronics multilayered stack of the PMCM is also seen in this figure. The designed 3-D photonic multichip module architecture allows for mas sively parallel, high I/O interconnections between parallel layers of Si inte grated circuits shown in Fig. 3-5. Applications best suited to such a photonic approach would involve image processing, object recognition, data mining/fil tering and compression. Previous estimates [Tanguay et. al., 2002] on the performance of the designed PMCM yields an aggregrate connection performance rate of 1 x 1014 CPS for an eight layer and 1 cm x 1 cm x 1 cm volume PMCM using 0.8 pm 54 I k f i f f l U L '| C §? o | Eg o m U m "<3 4 I I £ ta Pre-D etection O ptics • W avelength • P olarization • etc. S e n so r Array R egion-of- I n te re s t D iscrim inator VCSEL o r G aA s A rray CL DOE / E lectron ics M ultilayered Stack Detectors I Post- Processing Layer I Output F igure 3 -4 . Generalize schem atic o f adaptive vision sensor show ing infor mation flow. An opticnal region-of-interest discrim inator is also show n as a layer betw een the predection optics layer and the PM C M stack. T he right most bars indicate the portion o f electronics and optics used in the system . 55 Silicon GaAs Diffractive Optical Element Silicon Det. Elect Det, Elect. VCSEL Det. Elect. Det. Elect. F ig u re 3 -5 . Schem atic diagram o f m ultilayer hybrid e le c fronic/pho- tonic ohotonic multichip m odule, show ing two silicon V LSI chips optically interconnected by vertical cavity surface em itting laser (V C SE L ) and diffractive optical elem ent arrays. Tw o adjacent pixels are shown in cross section. VLSI technology rules. Considering that each pixel of the electronics layers is 100 pirn by 100 pun and each pixel is optically addressable by 25 other pixels (a 5 by 5 fan-out pattern) this potentially allows nearly 8 x 10^ processing ele- ments per cm . 3.6 Evolution of the PMCM Architecture Earlier attempts at USC involved the direct integration of Complementary Metal Oxide Semiconductor (CMOS) silicon (Si) integrated circuits (IC) hybridized to InGaAs/AlGaAs multiple quantum well (MQW) modulators as seen in Fig. 3-6. This system required an additional optical source layer to pro vide the needed optical energy for the “passive”, reflective MQW layer known as an optical power bus. This approach used a smart-pixel module consisting of hybrid flip-chip integration of a CMOS Si device with multiple quantum well modulators of InGaAs/AlGaAs fabricated on a GaAs substrate. The smart pixel device was capable of optical signal detection using an array of integrated pn junction pho todetectors and computational processing within each pixel of the array similar to those reported by others [D’ Asaro, 1993; Hinton, 1996; Tooley, 1996]. The photocurrent generated by the pn detectors was transformed to a sigmoidal output voltage response by the signal processing circuitry present in each smart piAel. This output voltage from the Si IC was then used to drive the electroab- sorption-based asymmetric Fabry-Perot MQW modulators, whose reflectiv ity/absorption was varied by the voltage level applied to the silicon device. Additional details of this device can be found elsewhere [Ananthanarayanan, 2002]. The current PMCM system replaces the MQW and optical power bus with a vertical cavity surface emitting laser array. In this device, all optical energy is generated wbhin the stack, at a cost of higher thermal dissipation. 57 The next section discussed aspects of vertical cavity surface emitting lasers from a system level perspective. Three VCSEL designs are discussed including devices from MicroOptical Device (MODE), Inc., NEC, and USC. The three VCSELs will be compared and judged for their suitability as SLMs in the laser based PMCM discussed here-in. Some of the major VCSEL prop erties of interest include optical output power, lasing threshold, output spectral distribution, VCSEL array uniformity of power and threshold, laser modal pat terns, laser emission geometry, and the laser polarization properties. Silicon GaAs Optica! Power Bus Diffractive Optical Elem ent Silicon Det* Elect, Det. Elect. MQW Mod MQW Mod u Det. Elect. Det. Elect. F igure 3-6. Figure showing the early architecture o f the 3-D photonic m ul tichip module using an optical power bus integrated with a G aA s M QW modulator for use as an integrated SLM [from Tanguay, 1993]. 58 3.7 Vertical Cavity Surface Emitting Lasers The previously proposed PMCM relied upon the use of a MQW array combined with an optical power bus for the necessary spatial light modulation (SLM). In the PMCM discussed here-in these components have been replaced with a single VCSEL array. There are a number of compelling reasons for such a switch including easier device integration, more compact size, and no need for an external optical source. The disadvantages include increased thermal effects due to the laser array being bonded inside the PMCM and the limited availability of VCSEL arrays. This section introduces VCSEL and describes the role of this device for use in our PMCM. The advantages and disadvantages of such devices will continually be examined as a number of VCSEL properties can simultaneously be helpful in some areas while being detrimental in others. For example, a VCSEL has a wall-plug electrical efficiency of 30-40% which is an advantage for power considerations, yet even with this high efficiency a substantial amount of the heat is generated just a few microns from the thermally sensitive silicon substrate. The next section describes VCSEL from the standpoint of device con struction and characteristics which effect the PMCM. The following section describes the testing procedure and experimental setup used for the character ization of three available VCSEL arrays. The three laser devices have been fabricated by either NEC, MODE Corporation, or USC and each have vastly different operating procedures and performance characteristics. The next sec 59 tions discusses these characteristics starting with laser operational wave lengths. This is followed by the output optical power and a short calculation of the entire optical power budget of our PMCM. Next, the VCSEL modal prop erties are detailed including their creation and the effect on our DOE design. VCSEL array uniformity is examined followed by VCSEL threshold proper ties. Finally, VCSL polarization characteristics are discussed followed by a short summary of the VCSEL characteristics. 3.7.1 VCSEL Operating Principles The structure of all VCSELs consists of a small active region in-between two parallel reflectors. The two reflectors are most often composed of distrib uted Bragg reflectors (DBR) and typically have reflectivities greater then 99.9%. A key issue for VCSEL designs is the injection mechanism for holes and electrons into the laser’s active region. The two approaches used for the VCSELs under consideration here use either a proton implantation or an oxide confinement technique to assist hole/electron injection. The proton implanta tion method works by turning the p-DBR into an insulator everywhere except in a small electrically conductive aperture through which all current flows. The MODE Corp. VCSEL uses this technique. The better technique, and the one used by NEC and USC, is the oxide confinement method which partially oxidizes a semiconductor layer near the active region of the VCSEL. This produces a very small conducting aperture that serves as both a current aperture and as an optical waveguide since the 60 thermally formed oxide layer has a slightly lower refractive index. In this way VCSELs have been produced with some of the highest reported efficiencies, smallest spatial dimensions, and with the lowest reported laser threshold cur rents [MacDougal et. al., 1998]. 3.7.2 VCSEL Testing Procedure The following diagram, shown in Fig. 3-7, schematically illustrates the optical system setup employed for data collection and system evaluation of the individual VCSEL laser arrays. Entire control of the measurement components is performed by the Lab View software suite running on a Macintosh computer. A GPIB interface board and the Nu-Bus equipped Macintosh G3 and/or a Mac intosh Ilfx computer are used to send commands to the HP4142B Measure ment and Controller System. The HP4142B Measurement System consists of two slots containing a HP4142B Voltage/Current Output Card and a HP4142B Voltage/Current Mea surement Card. With this configuration one can electrically drive the VCSEL under measurement and simultaneously measure the VCSEL optical output properties using the same HP 4142B system. For most measurements involv ing optical power measurements an EG & G DR-110 calibrated silicon detector was used. The device was calibrated for all VCSEL wavelengths under study. The detector had an active area diameter of 11.2 mm allowing all optical energy to be collected within the active area of the sensor. 61 Figure 3-7. Schematic diagram of th e optical system employed for VCSEL data collection a n d logging. Entire control o f th e experimental setup was performed b y LabView software running o n a Macintosh Ilfx computer and, later, a Macintosh G 3 computer. HP 4142B Measurement and Controller System HP 41421B Voltage/Current Output Card prenn — HP 41421B Voltage/ Current Measurement Card VCSEL Lac Driving Signals Active Area Calibrated Detector S u £ o 4 3 EG&G DR-110 Silicon Detector <-> -10 mm Apple Ilfx Running LabView 2.2.1 o\ to 3.7.3 Operating Wavelength The operating wavelength of the VCSEL has a significant impact on the design of the PMCM as our device is configured using a novel, thru-chip opti cal addressing scheme in order to address the electronic computational ele ments. In this case, a balance between the photodetector responsivity, the unwanted Fresnel surface reflection, and the substrate absorption losses must all be accounted and carefully characterized for correct operation of our PMCM stack. For example, a VCSEL operating wavelength that reduces the absorption losses in the bulk substrate also reduces the amount of optical energy being absorbed by the silicon photodetectors. The wavelengths of the three VCSELs were measured using an HP 7095IB Optical Spectrum Analyzer (OSA). The MODE wavelength values varied from 840.0 nm to 858.0 nm based on individual lasers tested and the electrical driving current. A plot of the MODE output optical spectrum is shown in Fig. 3-8. The NEC VCSEL had a measured wavelength value between 968.4 nm and 970.2 nm again depending on the laser tested and elec trical driving current. The USC VCSEL wavelength was measured at 978.8 nm when driven with I = 2.0 mAmps. In all cases the unique fiber coupling between the VCSEL output beam and the HP OSA as well as the nature of the monochrometer configuration inside the OSA did not allow for calibrated opti cal power measurements, hence all graphs are plotted in arbitrary units (A.U.). The significance of these wavelength values is best realized using Fig. 3-9 63 8 4 3 :6 5 3 -nit M - US gBfl H? Figure 3-8 . M O DE V CSEL output optical wavelength spectrum measured by the HP 7095 IB O SA show ing single mode operations with a laser driv ing current o f 8.5 mA. Peak center wavelength is measured as 849.6 nm. shown below. This figure plots the percent transmission of a flat, parallel sili con substrate as a function of optical wavelength and photon energy for four substrate thicknesses. The data in this graph considers optical Fresnel losses, dispersionary effects of the substrate’s optical refractive index, and the sub strate’s absorption properties for undoped, perfectly flat silicon substrates. A couple of facts can be ascertained. First, thinning this high absorption loss sub strate has a substantial effect on the final optical power throughput. This might force us to consider thinning all the silicon substrates in the PMCM stack if the VCSEL output power, or the silicon’s detector responsivity is to low. Second, the Fresnel reflection values are large due to the high refractive index value of 64 silicon (n = 3.45). These unwanted reflections might require the use of an anti-reflection thin him optical coating to assist in increasing optical through put. Third, a VCSEL wavelength of at least 950 nm is needed for the PMCM to function properly. The MODE Corp, 850 nm top emitting laser is not compati ble with our PMCM in its current architecture configuration. Fig. 3-10 plots the same percent transmission of a silicon substrate as a function of optical Percent Transmission of Silicon as Function of Photon Energy 500 rmcrons 250 microns 125 microns 75 microns o o-40 1.2 1.3 1.4 photon energy (eV) Percent Transmission of Silicon as Function of Wavelength 50u intcron 250 micron 125 microns 75 micron P ,40 0.9 0.95 1 1,05 1.1 Wavelength (microns) 1.25 F igure 3-9. Plot o f the optical transmission thru a silicon substrate as a function o f photon energy and wavelength. 65 Percent Transmission of Silicon as Function of Photon Energy 304.8 microns 254 microns 0 — 1.23 1.24 1.25 1.26 1.28 1.27 1.29 1.3 1.31 1.32 photon energy (eV) Percent Transmission of Silicon as Function of Wavelength 304.0 microns 254 mic rons 0.96 0.97 Wavelength (microns) 0.98 0.99 1.01 F igure 3 -1 0 . Plot o f a silicon substrate’s transmission as a function o f photon energy and wavelength. The two graphed traces correspond to the old (304.8 micron) M O SIS chip thickness and the new (254 micron) M O SIS chip thickness. wavelength and photon energy but with data traces configured to the same sub strate thicknesses that are currently available from the USC-based MOSIS IC seminconductor foundry service. Previous generations of MOSIS Tiny-Chips consisted of 304.6 micron thick silicon substrates, but this has recently been reduced to 254 microns for the current generation of fabrication runs. At an operational wavelength of 970-980 nm, this reduction in substrate thickness 66 yields nearly a 45-50% increase in optical throughput, hereby placing lower requirements on the optical sources in our PMCM stack. Any time the temperature rises in the VCSEL array, an effect known as a redshift of the laser gain curve occurs. This effect manifest itself in a wave length shift of a VCSEL laser. Fig. 3-11 shows the USC VCSEL driven at dif- ZD < c o 4_ i • + -1 T O 5 CD 5 o o_ " t o o ‘4 - 1 C L o F igure 3 -1 1 . Optical output spectrum for the U SC V C SEL at three different input driving currents showing the “red-shift” effect. ferent electiical currents. As the input driving current increases, the corresponding VCSEL temperature increases, causing a shift in the single modal wavelength operations of the laser. These temperature increases can occur by increasing the input electrical current, increasing the laser modulation l=0.5mA, center= 97B 335nm 1=2.OmA, center=97B 836nm 1=4 0mA, centei=:979 662nm 975 985 970 9 8 0 9 9 0 Wavelength (nm) 67 frequency (due to the change of carrier density of the active layer resulting in a variation of refractive index [Makaihara e t al., 1994]), or a rise in the ambient temperature surrounding the laser array. Traditionally, this redshift has been of interest since it limits the performance of high-bit rate optical communication systems. For this thesis, this effect causes unwanted shifting of the diffractive optical element optical spot distribution as well as the dispersionary effects of the substrates used in the PMCM stack and will be discussed later. Further issues related to the thermal effects of VCSEL are discussed in the VCSEL modal properties and VCSEL polarization properties sections. 3.7.4 Optical Power Budget Fig. 3-12 characterizes the optical power budget for the VCSEL-based PMCM stack. Shown in cross section are two adjacent VCSELs illuminating a single DOE substrate in a simple two-layer PMCM device. The output optical beam width at each substrate is initially determined by the VCSEL oxide con finement size and later by the refraction properties predicted by Snell’s Law. Also shown on this schematic is a plot of the optical power as one progresses through the stack. As configured for this calculation, each VCSEL is assumed to a have a wall plug lasing efficiency of 33% and a maximum output optical power of Iq mWatts (3 mWatts in this case). The width of the orange line rep resents the total optical power at that point in the PMCM. This simplified model takes into account all Fresnel reflection and absorption properties of substrates while ignoring all unwanted optical diffraction effects. Furthermore, 68 4 > C O c C J t in s . 8 ° '? u £ I F igu re 3 -1 2 . Schem atic figure o f the PM CM characterizing all unwanted optical lo sse s. 1 69 this model assumes that all light is normal to each surface, excludes any disper- sionary effects, and does not include multiple reflections within the stack archi tecture. Those effects withstanding, this model still provides an excellent starting point for initial optical power estimates. The two VCSELs are separated by a 125 pm pitch with the red-lines rep resenting the optical beam path of a 8 pm VCSEL oxide aperture and the blue lines representing the optical beam path for a 6 pm VCSEL oxide aperture. Both beams propagate thru the GaAs VCSEL substrate with little loss until striking the back VCSEL surface. At this point two optical effects occur. First, a Fresnel loss decreases the total optical power by nearly 33%. The second optical effect is the refraction properties caused by the difference in optical indices as characterized by Snell's Law. In our case, as the optical ray leaves a high index substrate and enters a lower index substrate (air) the optical beam is refracted at a greater angle from the interface surface normal. Another aspect of the laser’s oxide aperture is also discovered here. Since the laser’s substrate thickness is 350 mm, the optical output paths from adja cent lasers do not overlap on the laser array's back surface. This is another design parameter that can be exploited for future PMCM designs. In this case, one can envision separate diffractive optical elements being designed for each individual laser. As configured in the figure, the optical paths for both adjacent VCSELs exit the GaAs VCSEL substrate and enter the shared DOE substrate. The DOE substrate consists of a 375 pm thick GaAs material in this configuration and is 70 1103 jam away from the VCSEL substrate. The distance between both sub strate^ is chosen to correspond to the silicon detector dimensions as predicted by Fourier optics principles. Generally, the greater the illumination area of the incident optical beam the smaller the (FWHM) diffracted optical beam profile. In this figure the same area of the DOE pattern is simultaneously illuminated by the two adjacent VCSELs. After passing through the DOE a secondary substrate composed of a lens array is needed to perform the necessary Fourier transform. In previous figures in this thesis the DOE and the lens array were configured in the same substrate. This was achieved bv creating a refractive index distribution which can func- tion as a lens within which the DOE can be contained. For convenience, this model breaks these two necessary functions into separate substrates. The lens array in this model is a surface relief pattern on a GaAs substrate. As configured, a single lens is used to perform the Fourier transformation of the DOE. Additional effects caused by the adjacent VCSEL light output including lens aberration, non-normal Fresnel reflections, light spill into adja cent lens, and any additional diffraction effects are not considered here. The DOE and the lens array then causes light to be focussed onto the back surface of the MOSIS fabricated VLSI IC. An equation relating the input optical intensity Iq to the optical intensity received on a single detector I^et is expressed by the following equation 71 A = : C M s ^ ^ X dO E ^ A g^ p ~ a CdA.^L-ns vj n p ~ a y ih: D L I G aA s A ir I A ir Silicon 1V d detector where Iq is the input optical power. otQaAs ls absorption coefficient of GaAs, d < 3 aAS is the thickness of the VCSEL GaAs substrate, T) GaAs/Air * s ^ e Fresnel reflection coefficient of the GaAs/air interface, T |s j/^ r is the Fresnel reflection coefficient of the silicon/air interface, djens is the thickness of the lens GaAs substrate, dsj is the thickness of the silicon substrate, a si is the absorption coefficient of silicon substrate, %doe is the percent of light diffracted into the DOE orders, and -^detector the responsivity of the silicon detector. The surface normal transmittance through each interface is calculated by the expression - . 4/1./!, rj — 1 ra n sm itta n c e — (/!,+/!,)* and is equal to 68.67c, or a Fresnel reflection loss of 31.47c for a GaAs/Air interface. Due to the number of surfaces and their associated refrac- 72 tive indices, this number has a substantial effect on the final optical power reaching the silicon detectors. Assuming that 759f of the light is diffracted bv the DOE into the neces- • m . * — • * > sary orders, indicated by the Xjoe term, and the silicon detector's responsivity is 0.15 Amps/Watt, the final value of electrical current reaching the photodetec tor is 0.22 pAmps for a 1 mWatt input optical source. The significance of this value will be discussed in the next chapter. 3.7.5 Emission Geometry A further consideration of any potential VCSEL array is the output emis sion geometry. All three devices exploit another key advantage of VCSEL, namely vertical stack integration. Unlike edge emitting laser arrays, VCSELs allow for 3-D vertical integration. The MODE device is top emitting w’hile both the NEC and USC devices are bottom emitting. Although both emission geometries can easily be inte grated into the PMCM, both the NEC and USC provides easier integration as both p- and / 7-contacts are co-located on the same side of the VCSEL substrate. 3.7.6 VCSEL Modal Properties The USC and NEC VCSELs are configured for single mode operation while the MODE VCSEL is multimode. Multimode operations cause a num ber of problems when VCSELs are coupled with DOEs. The first unwanted modal effect is a seen with the help of Fig. 3-13. This is a plot of the optical 73 ■ v 'W L IT j 1 3 S 8 * R S .000 rH t Vm *\» SC8S 180 pH U W tfiR %td CENTER UftVELEHGTH B5I.IM n» K arhcr „ SPfi^ « S T A R T *,«» C E N TER 850.800 nm . « b 0 8 B n* UD F igure 3 -1 3 . M O DE VCSEL output optical wavelength spectrum m ea sured by the HP 7095 IB OS A showing multimode operations with a laser driving current of 9.5 mA. An increase o f 1 m A , from 8.5 m A to 9.5 m A . causes an unwanted lasing mode to be formed. spectrum of the same individual MODE VCSEL laser as was previously seen in Fig. 3-8. Unlike the previous figure, the input electrical current increases in this figure from 8.5 mAmp to 9.5 mAmp. This has the effect of changing the output optical spectrum caused by the additional lasing mode. In this case, the additional mode occurs at a higher optical frequency and the superposition of these two modes determine the entire VCSEL output frequency spectrum. Another unwanted modal effect is the unusual spatial distribution within the cavity of each of these modes. Fig. 3-14 shows the spatial distribution of the 74 'f“i r v Output Photpcurrent (m w ) Figure 3-14. Spatial distribution of the lasing modes on the M O DE VCSEL as a func tion o f input electrical driving current. 75 multimode lasing properties on a single laser of the MODE VCSEL array. This spatial distribution could cause optical misalignment between layers in the PMCM stack architecture. 3.7.7 VCSEL Intensity and Array Uniformity Another important laser parameter and one which gives design flexibility is the maximum optical output intensity. A consequence of the thru-substrate optical addressing of the silicon layer’s detectors and the number of high refractive index substrates using the PMCM stack would suggest the use of a high intensity VCSEL array, although additional considerations such as optical efficiency and VCSEL thermal dissipation would need to be examined. The maximum output power was measured using the same optical setup shown in Fig. 3-7. The MODE VCSEL was measured at 5.5 mWatts (1=13 mAmp electrical driving current), the NEC yielded 0.8 mWatts (1 = 4 mAmp electrical driving current), and the USC VCSEL had a value of 3 mWatts (1 = 5 mAmp electrical driving current). This data is also summarized at the end of this chapter in Fig. 3-17. The computational electronics in the PMCM stack assume not only that the VCSEL array provides enough optical intensity to correctly illuminate the next silicon detector layer but also that the VCSEL array is uniform. Fig. 3-15 shows the VCSEL optical output intensity values for the MODE laser array. The maximum output power varied from 1.6 mWatt to 3.56 mWatt from lasers located, surprisingly, just 500 microns away from each other. 76 Contour Plot of maximum power output (mWatts) ■ 3 .2 2.a 2.8 - 2.4 2.2 1.8 3 4 5 8 Laser Position (col) Figure 3 -1 5 . Contour plot o f maximum output optical power as a function of position for the 8 x 8 M ODE V CSEL array. Both the NEC and USC VCSEL were also tested for uniformity. These lasers, unlike the MODE, were much more uniform in optical power output and hence did not require the same characterization method as the poorly perform ing MODE laser. The uniformity for both the NEC and USC VCSEL varied by 10%. Uniform optical intensity of a VCSEL array is important as individual smart pixels are incapable of correcting for this (e.g., there are no provisions 77 for individual biasing factors within each smart pixel). If, for example, one laser has a significantly higher threshold than nearby lasers, one runs the possi bility of not correctly calculating the appropriate output level of the smart pixel. 3.7.8 VCSEL Threshold and Array Uniformity A further VCSEL characteristic and one which needs careful evaluation prior to the VLSI circuit design is the lasing threshold value and the associated thresnold uniformity across the VCSEL array. Fig. 3-16 shows a contour plot of the MODE VCSEL threshold values for all 64 lasers in the 8 x 8 array. The lasing threshold value varied from 9.62 mAmps to 7.02 mAmps. Similar to the output power, the threshold uniformity for both the NEC and USC VCSEL varied by 10%. 3.7.9 VCSEL Polarization Properties The polarization switching properties of VCSEL have been well docu mented. The physics mechanism for polarization selection include spatial hole burning (SHB) [Valle et. al., 1996], temperature dependence free carrier absorption [Panajotov et. al., 1998; Ryvkin et. al., 1999], and polariza tion-selective anisotropic optica] guiding due to field-induced birefringence [Degen et. al., 2000J. Polarization properties are not as much an issue as the previously men tioned optical properties as long as the minimum feature size of the DOE pat- 78 Contour Plot of threshold lasing values (mAmps) A o o 4 —; CO o 0_ 4 ^v .' . .......... 4 5 6 Laser Position (col) 8.5 Figure 3-16. Contour piot o f laser threshold as a function o f position for the 8 x 8 M ODE VCSEL array. terns are not submicron. As this architecture develops further and DOEs use smaller feature sizes in order to enable more global optical interconnections these polarization properties will need to be examine more closely. This prop erty will be further complicated due to the polarization properties of multimode VCSEL. As was seen during the discussion of the modal spatial distribution 79 each lasing mode has a unique polarization orientation, in most cases 90 degrees out of phase with each other. 3.7.10 VCSEL Summary The following figure, Fig. 3-17, summarizes the results of all the measure ment values for the NEC, MicroOptical Devices, and USC VCSEL arrays. The first two arrays, the NEC and MODE, were problematic and did not have all the necessary characteristics needed for our PMCM. One key factor, and one not discussed, was availability. Early in this project the only VCSELs available for potential PMCM integration were the NEC and MODE. Not until two/three years into the DARPA funded project did low-threshold VSCELs at the required optical wavelength from USC become readily available. 3.8 Conclusions This chapter chronicled the evaluation of the smart camera design. Start ing with the benchmarking data from Chapter Two, a previously, generalized PMCM architecture was introduced. This architecture was configured in order to use some of the advantages of optical interconnections for high performance parallel 3-D modules which can not be implemented using traditional electrical interconnections. 80 Threshold Current Output Power Voltage Modal Pattern Emission Type Packaging Array Size m 1 6.8 m A to 9.6 m A 1.0 m A to 1.3 m A .... ............... ...... ........ i 3 5 0 pA 3.5 mW (@ 1 = 13.0 mA) 0.8 mW (@ I = 4.0 mA) 3.0 mW (@ I = 5.0 mA) 2.31 V (@13.0 mA) 2.88 V (@4.0 mA) untested 840 nm to 858.0 nm 968.4 nm to 970.2 nm 978 nm to 879.6 nm Single mode to multimode Single mode Single inode Top Emitting Bottom Emitting Bottom Emitting Packaged or Bare Die Packaged or Bare Die Bare Die 8 x 8 array 8 x 8 array 8 x 8 array Figure 3-17. VCSEL property com parison between M O D E , N E C , and U SC vertical cavity surface em itting lasers. 81 This 3-D integration approach allows for a compact 3-D interconnection between arrays of silicon based processing elements. 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Shore, “Polarization selection in birefringent vertical cavity surface emitting lasers," J. Lightwave Technology, vol. 14, pp. 2062-^ 1 . (1996). W. B. Veldkamp, “Wireless Focal Planes 'On the Road to Amacronic Sensors’", IEEE Jour. Quant. Electronics, 29(2), 801-813, (1993). Thomas, H. Wood," Multiple Quantum Well (MQW) Wave Guide Modulators,"J.Light Wave Technology, 6 (6 ), 745-757, (1988). Wandell. B. A., Foundations of Vision, Sinauer Associates, Inc., Sunderland, Massachusetts, (1995). C. Warde and A.D. Fisher. “Spatial Light Modulators: Application and Functional Capabilities", Optical Signal Processing, J. L. Horner, Ed., (Academic Press Inc., Englewood Cliffs, NJ), pp 477-523, (1987). Sean P. Watson, Bruce T. Murray, Bahgat G. Sammakia, “ Computational parameter study of chip scale package array cooling," Components and Packaging Technologies, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part A: Packaging Technologies, IEEE Transactions on]. Volume: 24 Issue: 2, pp. 184 - 190, June (2001). T. L. Worchesky, K. J. Ritter, R. Martin, and B. Lane," Large Arrays of Spatial Light Modulators Hybridized to Silicon Integrated Circuits," Appl. Opt. 35(8L pp. 1180-1182,(1996). 88 Chunlin Xia, “Spray/jet cooling for heat flux high to lkW.” Semiconductor Thermal Measurement and Management, 2002. Eighteenth Annual IEEE Symposium, San Jose, CA, USA , 12-14 March 2002, pp. 159 - 163, (2002). 89 Chapter 4 Diffractive Optical Elements 4.1 Introduction The previous chapter discussed the details of the photonic multichip module (PMCM). One of the key components of this proposed system is the massive parallel optical interconnection fabric afforded by the use of devices known as diffractive optical elements. As configured for use in the PMCM, these devices provide the vertical signal/information routing through the use of weighted analog optical interconnections between adjacent layers of simple electronic processors. Diffractive optical elements have been used for various applications including optical telecommunications [Deng et. al., 2000], optical interconnec tions [Kuznia et. al., 1995], astronomy [Skinner, 2001], optical beam shaping [Liu et. al., 2002], and wavefront sensing for biomedical applications [Golub et. al., 1997]. In these applications, DOEs were the optimal solution based on performance, size, materials, and/or cost considerations. 90 The diffractive optical elements (DOE) reported in this chapter are all phase elements constructed using either a high optical refractive index and optically transparent substrate material known as gallium arsenide (GaAs) or an optically transparent, small optical refractive index quartz. Both DOE devices investigated in this section, one known as a computer generated holo gram (CGH) and one known as a stratified volume diffractive optical element (SVDOE), can be used for the parallel optical interconnection system, although as we will see later, the SVDOE has a number of additional applications. The first device reported in this chapter is a computer generated holo gram (CGH) diffractive optical element (DOE) that is designed using Fourier optic principles to calculate a specific 2-D substrate surface phase profile. When these devices are illuminated with an optical input wave, the subsequent optical energy after passing through the DOE is split into separate optical beams of varying energy, each propagating in slightly different directions according to the designed CGH phase profile. The individual diffracted optical beam properties can be precisely tailored for their chosen applications, in our case an analog fan-in/fan-out interconnection between successive silicon VLSI layers in the PMCM. Here we discuss the design and fabrication of the CGH DOE to form an interconnection fabric. When correctly designed, the output of the illuminated DOE will direct these beamlets onto the silicon’s detectors of the next electrical processing layer in the PMCM stack. To the author’s knowledge no similar DOEs performing these tasks have been fabricated in GaAs for use as both fan-in and fan-out elements. DOE optical characteriza 91 tion will be discussed in Section 4.5.3.2 (Demonstration of Optical Fan-Out) in which a previously unreported, unwanted DOE optical effect is discovered and discussed. This optical effect makes it nearly impossible for any high-index DOE to work as predicted without a significant, additional manufacturing step to be described in Chapter Five. Stratified volume diffractive optical elements (SVDOE) are new devices that rely on a stacked set of 2-D substrates containing a phase and/or amplitude profile to replicate the optical functionality of a 3-D volume optical media. By stacking discrete, 2-D substrates in a novel fashion using an advanced elec tronic packaging technology, an easily manufacturable, 3-D volumetric optical device can be constructed. These volumetric devices show great promise for use as wavelength filters, optical interconnections, compact polarization devices, and read-only optical storage devices. To the author’s knowledge, no similar fabrication technique has been reported for these relatively new optical devices. The following section introduces some preliminary concepts concerning diffraction gratings in order to gain a familiarity with later reported results, both in Chapter Four and Five. Section 4.3 introduces “thick” and “thin” grat ings and their associated optical properties. The use of DOE for the PCMC are quickly reintroduced in Section 4.4 before a more detailed investigation of computer generated holograms occur in Section 4.5. This section describes the fabrication and experimental performance of a CGH designed for fan-in/fan-out operations in our PMCM. Stratified volume diffractive optical 92 elements are discussed in Section 4.6 which include the design, computational modeling, fabrication, and subsequent experimental performance of these devices, finally followed by the conclusion in Section 4.7 that will also assist in transitioning to Chapter Five. 4.2 Preliminary Concepts Before discussing the use of diffractive optics for use in the PMCM, a short review of the operating principles of both “thin” and “thick” gratings is performed. Both “thin” and “thick” gratings will be constructed for research purposes in this thesis. Although both grating types are well known, certain aspects of both grating types need to be reformulated in order to precisely model these diffractive optics for use in the PMCM design. “Thin” gratings are defined as gratings that operate in the Raman-Nath diffraction optical regime, while “thick” gratings operate in the Bragg diffrac tion regime. The operating principles of concern to us include the fraction of incident optical power that is diffracted into a particular diffraction order (i.e., the grating diffraction efficiency) and the grating’s angular sensitivity. The fol lowing sections, entitled Optical Properties of Thin Gratings and Optical Prop erties of Thick Gratings, review the basic diffraction equation and discusses the distinquishing characteristics of both thin and thick grating types. For this review, we assume that each grating consists of a square wave phase refractive index perturbation in a homogeneous lossless medium with infinite lateral 93 dimensions and a finite substrate thickness. The resultant diffracted optical beams are read with a TE polarized monochromatic plane wave. Optical diffraction from a phase grating operating in transmission mode is shown in Fig. 4-1. In this figure a light ray of wavelength X, incident at an incidence angle a from the surface normal, is diffracted by a grating with a grating pitch of d along the angles (3 m. This angle is measured from the grating normal as indicated in the figure. The sign convention for these angles depend on the diffracted orders being reflected or transmitted. For convenience, posi tive orders are measured counter-clockwise for the reflected orders and clock wise for the transmitted orders. The grating equation is derived from standard optical interference principles. Hence, when the geometric optical path differ ence (OPD) between adjacent grating grooves is equal to X the light from adja cent grooves is in phase which can be used to derive the well known grating equation expressed as d (sin a i — sin /3,„) = mX where X is the optical wavelength, cl is the grating pitch, a is the incident angle, ( 3 is the orders, and m is a positive integer. 94 Incident Beam F igure 4-1. Schem atic diagram o f a square wave grating show ing a plane wave readout. The DO E grating is shown operating in the transmis sion mode. The incident beam is diffracted into individual orders that is dependent on the substrate’s refractive index, the grating pitch, the in ci dent beam angle, the grating groove etch depth, and the surface relief pro file o f the gratings. Note: input/output optical beam displacem ent is assum ed to be neglable is not shown in the figure. 95 4.3 Grating Types Only two types of gratings will be considered here, those based on amplitude modulation and those based on phase modulation. An amplitude modulation grating is a two dimension transmittance pattern that attenuates the electric field amplitude as the incident optical wave passes through the grating substrate. A phase grating is designed to delay a portion of the incident optical wave as it passes through the grating structure. Phase delays can be caused by the thickness of the gratings and/or the profile of the refractive optical index. Gratings that rely on phase modulation absorb no incident optical energy, hence the total diffracted light power for a lossless grating ideally equals the incident optical power (assuming that Fresnel losses are negligible and the grating substrate is lossless) which will be a prime reason for designing both the computer generated hologram and stratified volume diffractive optical ele ment reported in this thesis as phase devices. For an amplitude square wave thin grating the maximum diffraction efficiency of the +/- first order is 1 0 .1 % as compared to the square wave phase grating that is capable of a 40.5% maxi mum +/- first order. The next two sections consider the various optical diffraction properties of both thin and thick gratings. A clearer distinction between the so-called “thin” and “thick” gratings will be introduced. A further clarification, on one of interest for optical volume material, will be developed when investigating the angular properties of both grating types. 96 4.3.1 Optical Properties of Thin Gratings A thin optical grating is a grating which operates in the so-called Raman-Nath diffraction regime. In a series of eloquently written papers [Raman et. al., 1935a; Raman et. al., 1935b; Raman et. al., 1936a; Raman et. al., 1936b; Raman et. al., 1936c], Raman defined these properties. Generally, we can define a thin grating as one in which the thickness of the diffracting surface is small compared to the grating pitch, d, and the angular selectivity effects are not significant. vVhen an optical wave impinges on a grating operating in this regime, the input optical field is split into many dif fracted orders. A more accurate, quantitative definition of a thin grating is described by the equation ^ 2 rcXt Q = ------ 5- nd where Q is the so-called thickness parameter, t is the grating thickness, X is the optical wavelength, d is the grating pitch, and n is the optical refractive index of the grating substrate. The operational regime of a thin grating occurs at Q < 1 [Klein et. al., 1967] while thick gratings occur at Q > 10 [Klein et. al., 1967]. 97 43.2 Optical Properties of Thick Gratings The 1969 paper published by Kogelnik discusses the behavior of thick diffraction gratings [Kogelnik, 1969]. This fundamental paper derives an ana lytical expression for the diffraction behavior of the zeroth and + 1 orders. For a thick holographic grating the +1 diffraction efficiency at Bragg incidence allows, under certain conditions, a 1 0 0 % diffraction efficiency to be obtained [Kogelnik, 1969]. This results from the orientation of the incident light and physical parameters of the grating such that only the + 1 order is gen erated during illuminated readout. Similar to the derivation of the simple “thin” grating equation derived in the previous section, the relative phase conditions between the + 1 and the zeroth orders are used to derive the conditions under which Bragg diffraction occurs. A detailed discussion of these calculations are obtained elsewhere [Nordin, 1993; Collier et. al., 1971; Kogelnik, 1969] and will later be referred to when discussing the optical properties of the stratified volume diffractive optical elements. 4.4 DOEs for use in the PMCM Figure 4-2 is a 3-D schematic showing a DOE providing a l-to-3 optical fan-out by diffracting light into three separate detectors on a silicon VLSI sub strate. The PMCM DOE is designed apriori to precisely direct light on the VLSI IC containing multiple detectors of fixed pitch and fixed size. In addi 98 tion, these DOE also are designed to control the amount of optical energy opti cally diffracted by each beamlet. In this way, the top silicon layer in a multilayer stack architecture is optically interconnected to the three nearest neighbors (shown in the 3-D PMCM configurations in Fig. 4-2) of the next sil- DOE Illumination Area GaAs DOE Smart Pixels (Three shown) Silicon 1 C Distance Detector Size Silicon 1 C < > Detector Pitch F igu re 4-2. 3-D schem atic o f show ing a D O E structure providing a l-to-3 optical fan-out. The DO E illum ination area, detector pitch, distance betw een layers, and detector size are needed prior to D O E design. The V C SE L array and lens array are not sh ow n . icon layer in the PMCM stack. The individual beams, after passing through the DOE substrate, are focused onto the computational electronic processing plane containing sets of detectors by a corresponding array of focusing diffractive or refractive microlens arrays that lie contiguous to the DOE element (not shown 99 in the schematic). The spatial pitch between individual diffracted beamlets, the FWHM size of each diffracted beamlet, and the amount of optical energy in each output optical beamlet is precisely controlled by the predesigned DOE phase profile, the illumination area on the DOE, and optical energy provided by the lasers in the VCSEL array of the PMCM. These fanned-out optical beams are incident on the next cascadable 3-D PMCM layer. By simultaneously illu minating the DOE from multiple sources a fan-in/fan-out capability is sup ported by means of an incoherent superposition of all of the optical beams incident on the plane of the detector element (representing an addition of opti cal intensities). From the previous chapter, no electronic packaging technology can support the required interconnection pattern or the interconnection density needed for the PMCM. Although flip-chip bonding will be used in our PMCM stack for vertical electrical data channels between smart pixels and individual laser elements in the VCSEL array, flip-chip bonding alone can not provide the same interconnection density as is needed for our PMCM implementation. Note that this figure only shows one single optical beam passing through the DOE structure, splitting into different diffracted orders, and illuminating a small set of detectors. During final device integration most lasers will be oper ating simultaneously, meaning optical incoherent addition from a number of VCSEL lasers will be performed at the silicon’s optical detectors. 100 4.5 Computer Generated Holograms (CGHs) Computer generated holograms are optical devices which alter the phase and/or amplitude of an incident optical field in such a way to precisely control the resultant optical intensity and directionality. The functions of the designed CGH for use with the PMCM are provid ing the localized, fixed (non-adaptive) 3-D fan-in/fan-out optical interconnec tion fabric between vertical arrays of electronic processors. This DOE can be designed for space-invariant or space-variant convolution kernels between lay ers of electronic processors based on desired functionality. Regardless of func tionality, the desired DOE must contain a high optical throughput efficiency and reconstruction accuracy in order to provide low channel-to-channel inter connection crosstalk on the silicon plane. Furthermore, since the PMCM con tains layers of light sensitive components, care must be taken to reduce any unwanted, stray light for external and internal sources, including poorly designed DOEs. The next section discusses the design of the computer generated holo grams for use with the PMCM. This section also details the design of a CGH known as the 4:2:1 hologram, so called because of its unique fan-out design. The fabrication of CGH are introduced followed by the mechanical and optical characterization of the final devices. In these sections a number of previously unreported issues regarding CGH are uncovered which preclude successful 101 operation of the CGH for use in the PMCM and leads directly to Chapter 5, Thin Films for Diffractive Optical Elements. 4.5.1 Design of Computer Generated Holograms Ideally one would like to design a hologram by exactly defining the opti cal field at the desired spatial location and back-propagating the optical field to calculate the requisite 2-D analog phase pattern/profile. There are two prob lems with this approach. First, this method requires an incredible level of fab rication technology needed for the construction of the exact 2-D analog phase profile on a substrate. This continuous, analog phase profile is difficult, if not impossible, to construct with today’s semiconductor technology unless signifi cant compromises are made. Second, this approach is computationally inten sive. An alternative approach is to use the flexibility and performance of modern digital computers to design a discretized, limited phase level hologram. By discretizing the output pattern and reducing the parameters of the 2-D phase pattern design, a computer generated hologram can be designed utilizing an iterative algorithm and, hence, reduce the computational complexity of this problem while still providing the necessary optical field for the optical inter connection fabric. A number of iterative approaches have been used for making computer holograms. One of the first methods was A. Lohmann’s binary detour-phase holograms [Brown et al., 1967] in which a desired optical wavefront is con structed after passing through a substrate containing an array of precisely 102 designed binary apertures. A more robust method was developed by Gerchberg and Saxton [Gerchberg et. al., 1972; Fienup, 1982] especially when later cou pled to a novel error-reduction technique independently developed by Hirsch, Jordan, and Lesem [Hirsch et. al., 1970]. Recently, both simulated annealing algorithms [Lin et. al., 1995] and genetic algorithms [Yoshikawa et. al., 1995] have shown great promise for further reducing computational time for the design of computer generated holograms. The Gerchberg-Saxton algorithm is used in this thesis since it is compu tationally less intensive than many other CGH DOE design approaches and is relatively easy to implement using standard computer programming tech niques. Furthermore, this algorithm tends to converge to an optimal solution faster with fewer computational iterations. The design process using the Gerchberg-Saxton algorithm (see Fig. 4-3) begins with the desired image plane intensity pattern (at the Fourier plane). In this case the desired image is a simple USC/OMDL logo encoded in a com puter file. After applying a set of random phases in the object plane, the algo rithm begins by computing the fast Fourier transform (FFT) of this complex amplitude object plane pattern (denoted by g in Fig. 4-3) to obtain the complex amplitude transmittance of a 2-D, discretized DOE CGH grating structure (denoted by G in Fig. 4-3). As semiconductor dry plasma etching fabrication technology is used to form the discrete phase-only elements, the magnitude of each phase element in the DOE plane is set to unity (i.e., no amplitude modula tion), and the phases are quantized to multiple levels by an optimized quantiza- 103 Desired Image - g OMDL t Computer Mean Square use iOMDL Compute Fourier Transform Compute Inverse Fourier Transform G = G e j 9 Satisfy Fourier Constraints G=lFleJe Calculated Image - g’ F i g u r e 4 - 3 . Processing steps for the construction o f a computer generated hologram based upon the Gerchberg-Saxton algorithm [after Fienup, 1982], tion algorithm. The inverse fast Fourier transform of the DOE phase grating is then calculated to obtain a first approximation of the desired reconstructed intensity pattern at the image plane. At this plane, the desired image plane intensity pattern and the reconstructed object plane intensity pattern is com pared and evaluated. Typically, an error parameter is specified by the user before program initiation. The program continues to iterate the 2-D discrete 104 phase profile of the DOE until this error criterion is fully met. This process typically takes hundreds of iterations before convergence occurs. A characteristic of all CGH designs is the unique relationship between the fidelity of the reconstructed optical signal and the spurious, unwanted noise as a function of substrate phase levels. Generally, the more phase levels, the better signal-to-noise performance of the desired reconstructed design. Figure 4-4 shows four different CGH designs performed by the author to validate this statement. The desired image is the same USC/OMDL logo shown previously in Fig. 4-3. This logo is initially discretized to a 256 x 256 image and used as the input to a Gerchberg-Saxton program of the author’s design. Four cases were run using this logo as the input image. The output intensity reconstruction of a 2-D CGH is shown in the first set of images. Both a 2-D intensity plot and the corresponding 3-D intensity contour plot are shown in adjacent plots. As the available number of phase levels increase, the corre sponding signal to noise ratio of the reconstructed optical design also increases. This potentially has an effect on the choices for the CGH used in the PMCM stack implementation. Not only are the reconstructed images closer to the desired image as the CGH includes more phase levels but the area surrounding the image, the background noise, is also reduced. Since our PMCM is a light sensitive device, this might be an important consideration for future CGH research. Typical program execution time was 3-5 minutes on a Sun Ultra 80 workstation. 105 6 4 Level 1 6 Level 4 Level 2 Level F i g u r e 4 - 4 . The output intensity reconstruction of a CGH design with four dif ferent numbers of phase levels. 106 For the rest of this section, the CGH under study is referred to as the 4:2:1 GCH DOE. This CGH was designed by Prof. B. K. Jenkin’s group at USC. The designed analog beamlets diffracted by this design form a 3 x 3 fan out pattern with analog weights of 1.0 for the central spot, 0.5 for the four first-nearest neighbors, and 0.25 for the four second nearest neighbors. The initial CGH device has been previously fabricated in an optically transparent quartz substrate and been characterized for optical fan-out by others [Kuznia et al., 1995; Huang et. ctl., 1995; Ananthanarayanan et. al., 1995; Ananthanaray- anan, 2 0 0 2 ] for use in selected optically interconnected devices. The 4:2:1 CGH device in this thesis uses the same computer design as the previously reported devices, but the DOE fabrication is performed using both a GaAs substrate and the previously mentioned quartz substrate. The rea son for transitioning to the GaAs substrate for this application is partially real ized using the familiar VCSEL-based PMCM stack schematic shown in Fig. 4-5. First, the DOE substrate ideally needs to be a transparent, lossless mate rial limiting our choices of DOE substrate. Second, the nature of the PMCM dictates careful characterization of any thermal issues for proper PMCM stack functionality. Any thermal mismatch between individual layers of the PMCM could result in optical misalignment and/or mechanical shear-stress on the elec trical contact bumps leading to premature PMCM layer separation. Third, power dissipation efforts are simplified if all substrates in the PMCM stack have similar thermal properties. These factors lead to the use of GaAs as the DOE substrate. 107 Silicon GaAs Diffractive Optical Element Silicon Del. Elect. Det. Elect. VCSEL VCSEL Det. Elect. Elect. F i g u r e 4 - 5 . Schem atic diagram o f m ultilayer hybrid elec tronic/photonic photonic multichip m odule, show ing two silicon VLSI chips optically interconnected. Thermal issues ideally lead to the use o f GaAs as the DOE substrate material. The next section describes the fabrication of the computer generated holograms using GaAs substrates and the facilities of the USC W. M. Keck Photonic Research Center and Cleanroom. 4.5.2 Fabrication of Computer Generated Holograms The fabrication methods used for the diffractive optical elements men tioned in this thesis all rely upon the planar semiconductor process technology originally suggested by Shockley for the manufacture of semiconductor inte 108 grated circuits. This technique allows for the precision and accuracy needed for our CGH DOE. Furthermore, due to the economics of semiconductor tech nology, we can leverage the enormous advances made in the semiconductor fabrication area for use with the manufacturing of passive DOE structures. This sections describes the use of microelectronic processing for use with DOE fabrication. After a computer file is generated by the Gerchberg-Saxton program containing all the requisite phase levels for the 2-D DOE structure, this file is electronically transferred into a chrome- or iron-oxide mask using an optical laser or electron beam raster system. The 5 inch by 5 inch darkfield mask fab ricated with the 4:2:1 pattern was completed by QPS Technology, Inc. (Pointe Claire, Canada) using their E-beam writing system which provides for a mini mum spot size of at least 0.1 pm. The same E-beam writing system was also used to direct write the DOE pattern on a separate quartz substrate. This method yields significantly better DOE patterns then patterns written using tra ditional photolithographic techniques. The gallium arsenide substrates needed for DOE fabrication were obtained from American Crystal Technology, Inc. (AXT) in Fremont, CA. The GaAs single crystal wafers were prime grade, epi-ready, semi-conducting, and undoped. Each wafer was 50.8 mm in diameter and had a thickness between 300-375 microns although most wafers had a USC measured thickness of 350 microns. Both sides of the wafer were optically polished and had two conflats for easy handling and identification. 109 The semiconductor processing sequence for the construction of these computer generated holograms is shown schematically in Fig. 4-6. It starts Photoresist layer on GaAs substrate Contact mask photolithographic exposure Gallium Arsenide AZ 5214 Photoresist 1 /-line UV light ^ ^ ^ ^ I ' M Gallium Arsenide Photomask with DOE pattern Photoresist developing Gallium Arsenide Electron Cyclotron Resonance (ECR) etching 1 BCi3 + Ar+ i . I I , 1 1 1 . . . I l l Gallium Arsenide Removal of photoresist Gallium Arsenide Final DOE device F igure 4-6. Schem atic diagram show ing the processing steps involved in the fabrication o f binary phase diffractive optical e le ments. 110 with a double-sided polished GaAs substrate which has been cleaned using a combination of methanol, acetone, and deionized (DI) water in order to remove organic and inorganic residues on the wafer surface. A Soli tec spinner is used in conjunction with Clariant AZ 5214 photoresist prior to photoresist explo- sure. When spun at 4,000 r.p.m., a uniform, 1.2 jam thin film of 5214 photore sist is formed on the wafer surface. The photoresist coated sample is then moved to the Brewer Science CEE 100 hot plate where the sample is heated at 120° C for 90 seconds to remove unwanted volatile solvents from the thin film of photoresist and to assist in photoresist polymer crosslinking for subsequent photoresist processing. After a short cool-down phase the substrates are now ready for the photolithographic patterning using the MJB-3 contact mask aligner. The mask aligners in the USC W. M. Keck Photonic Research Center and Cleanroom are Karl Suss MJB-3 contact mask aligners theoretically capa ble of 0.8 pm resolution. Typical photoresist exposure times are 5 seconds for a lamp intensity o f 8.0 mW/cm (at the /-line of the Xe UV lamp) on the mask aligner. After photoresist exposure the GaAs sample is immersed in a solution of Clariant 1:4 diluted 400 K chemical developer for 40 seconds allowing the exposed photoresist to be washed away. After rising and drying, a final UV exposure is performed for 2-3 minutes in order to remove any unwanted remaining undeveloped photoresist. This step also hardens the remaining pho toresist which is beneficial as the next processing step, reactive etching, is quite damaging to unhardened photoresist. Ill A variety of techniques are available for etching the diffractive optical elements. Although numerous wet etching techniques allow for high etch rates and excellent uniformity across large samples, the substantial amount of photo resist undercutting precluded its use. Dry plasma etching techniques afforded the best compromise solutions. The USC W. M. Keck Photonic Research Center and Cleanroom provide a number of different techniques for etching using dry plasma techniques. These include reactive ion etching, magnetically coupled ion beam etching, and electron cyclotron resonance (ECR) etching which is also a form of mag netically coupled ion beam etching. Reactive ion etching places the to-be-etched sample on a RF capacitive couple bottom electrode. The wafer is bombarded by energetic ions from the plasma due to the negative self-bias on the wafer surface. This yields a high etch rate with excellent etching uniformity. The problem with this technique is that the plasma/ion density is directly coupled to the ion energy, the applied power, and process background pressure. This is significant as low ion energy equals less surface damage but only when slow etch rates are used. Magnetically coupled ion beam etching decouples the plasma/ion den sity from the ion energy allowing high etching rates with low substrate damage. This technique works by placing magnets behind the wafer to generate a mag netic field in a direction parallel to the wafer surface. The field is also perpen- 112 dicular to the electrical field that confines the electrons to a circular trajectory near the cathode. This magnetic coupling is further enhanced using the electron cyclotron resonance (ECR) system. In this case, another set of magnets are used for increased ion density and hence yield high etching rates with low substrate damage. A microwave excitation is used in the presence of the magnetic fields for generation of a highly confined plasma. By tuning the cyclotron frequency correctly, a resonance coupling occurs between the electron energy and an electric field is created resulting in optimal ionization. The wafer is RF and DC biased to assist in the control of the ion energy in order to achieve desired etch anistrophy. A PlasmaQuest Model 98 was used for etching all the GaAs substrates reported in this thesis. A photoresist mask containing the desired DOE pattern was used as the etching mask for this system. Both BCI3 and Ar gas sources were used as the primary reactive gasses for etching. A constant BCI3 flow rate of 25 seem and Ar rate of 5 seem was used in conjunction with a 300 Watt RF power, a 100 Volt DC bias, and a current of 170 A/80 A on the upper and lower magnetic sources for increased anisotrophic etch profiles with reasonable etch rates (14.3 A/sec). The desired etch-depth was 1920 A. Table 4-1 shows the chosen ECR system parameters. A SEM micrograph of the fabricated 4:2:1 CGH fabricated on a GaAs substrate is shown in Fig. 4-7. The image shows a single DOE sub-element of 113 Table 4-1. ECR Process parameters Ar Flow Rate 5 seem BCI3 Flow Rate 25 seem Forward Power 300 Watts Reflected Power 5-10 Watts GaAs Etch Rate 14.3 A/sec Backside Pressure 5000 mtorr Chamber Pressure 4 mtorr Upper Magnet 170 Amps Lower Magnet 80 Amps Temperature 25 C° the entire 20 x 20 array forming the entire DOE pattern. The next sections characterize the DOE. 4.5.3 Computer Generated Hologram Characterization Two types of device characterization are performed for the 4:2:1 CGH DOE structure. The first set of experiments include characterization of the ECR etch uniformity, ECR etch depth deviations, the DOE etched sidewall pro file, and the substrate surface damage. These issues are quantitatively mea sured or estimated with the help of a Dektak IIA surface profilometer, a Phillips 114 Figure 4-7. SEM photograph of a GaAs DOE sub-element. XL-30 scanning electron microscope, and an Olympus BLH-20 optical micro scope. The optical performance of the fabricated DOE structure is ascertained in this section. Starting with a complex optical test bench, the DOE is charac terized for use as an optical fan-out element. Since the ultimate goal is fan-out/fan-in, the device is further tested u sing up to four lasers operating simultaneously to experimentally demonstrate analog, 4-to-16 fan-out/fan-in operations, the first such demonstration of this type to the author’s knowledge. This section also characterizes a previously unreported, unique angular tilt dependence of the GaAs DOE which markedly reduces the desired optical per- formance of the CGH. The causes of this effect are discussed and possible solutions explored. 4.5.3.1 Material Characterization A surface relief plot measured using a Dektak IIA surface profilometer on the same GaAs DOE seen in Fig. 4-7 is shown in Fig. 4-8 along with a close-up SEM of the sidewall profile of the etched GaAs substrate. The mea sured etch depth of the DOE is 1978 A, representing a slight deviation of the desired 1920 A etch depth calculated for a 970 nm operational wavelength. From a manufacturing perspective this result is considered nearly ideal and almost perfectly optimized. If the desired etch depth was not obtained in this example, the relative intensities of the DOE’s reconstructed spots would show deviation from the idealized intensity pattern. This effect is especially seen in the reconstructed spot of the zero diffracted order (i.e., the center spot of the 4:2:1 pattern) more strongly than the other neighboring spots. The DOE sidewall profile is characterized by the Dektak surface scan in Fig. 4-8. Any sidewalls that are not 90 degrees from surface normal cause unwanted noise in the desired diffracted profile. From the Dektak measured profile one might assume the measured sidewall is 82-83° degrees. In reality, this sidewall angle value represents the profile of the Dektak stylus tip. A scan ning electron microscope scan of the DOE cross-section determined the side wall was closer to 89° degrees, 116 ID 1 SCAM > 150ijM UERT - 1 ,9 7 8 A 23 -32 0 8 -1 8 -9 9 SPEED: MEDIUM HORIZ^ 13.uM 0 -500 - 1,000 -1 ,5 0 0 - 2,000 60 65 70 75 80 85 90 F I CUR'- 0 A ii 7 0 .iM r '1 CURSOR = 83 M CUR:- 1 ,9 7 8 A @ 88wM SLOAN DEKTAK I I ^ A c c . V . S p o t M a g n D o t W D E x p * 1 l6 .0 k V 4.0 7500X S E 37.2 0 ’"v: ? ? - , -. ■ - I — ! 1 2 ( im MURI USD G aA s DOE F igure 4-8. Dektak surface profile o f the etched GaAs sample shown in the SEM micrograph. N otice the optical proximity effects o f the photo lithographic process seen as a rounded com er in the G aAs DOE. Two additional areas where the Dektak was also used included the char acterization of the ECR etch uniformity and an estimation of the surface dam F . M 1 1 1 V . 117 age caused by the exposure to high energy ions during the ECR etching process. Assuming that the to-be etched GaAs samples were always placed in the center of the 8 inch graphite chuck of the ECR, and the corresponding GaAs substrate was always 1 cm by 1 cm or less, the etch uniformity for the GaAs DOE was measured during ECR chamber recalibration as 2-5% for the short etching times needed by our DOE structures. This value conforms to oth ers values reported by other USC research groups that regularly use the ECR system. The reason for such accurate results is threefold. First, the ECR sys tem is only configured for use as an etching system instead of a dual deposi tion/etching system as other university or commercial fab service have done. Second, everyone needs nearly perfect sidewall profiles for their photonic devices such as VCSELs, waveguides, photonic crystal structures, ring resona tors, etc. As such, comprehensive recalibration is performed often. Finally, there are only 10-15 people who use this machine on a regular basis allowing for rapid dissemination of optimized ECR etching recipes to take into account the naturally occurring system level equipment drifting. Finally, the last set of experiments used the surface profilometer to char acterize the etched surface roughness. This is necessary as the ECR ion energy can cause a slight surface roughness on the GaAs etched regions. Again using the Dektak, this surface roughness is estimated as +/- 1 0 0 A for a 1978 A etched substrate over a 1 cm by 1 cm sample. This ~2-5% variation is typical and similar to results reported by other users of the ECR. The unwanted rough 118 ness can cause very slight unwanted noise in the DOE reconstructed optical profile. 4.S.3.2 Demonstration of Optical Fan-Out Characterization of the optical performance of the designed DOE include quantification of output throughput efficiencies, measurements of the relative intensities between the reconstructed spots of the DOE output pattern, and comparison between the experimental and theoretical values. The experimental setup used for the evaluation of the DOE output per formance is shown in Fig. 4-9. For this system, a 970 nm light source was used for illumination of the GaAs DOE. A spatial filtering device (not shown), con sisting of a lens and a 5-25 pm pinhole filter, is initially used to reduce the noise and allow for the easy creation of an optical plane wave with the help of a lens, Lens #1, located a focal distance away from the pinhole. The spatial filter was initially used during the experimental configuration but later proved inef fective when multiple lasers in the VCSEL array were used. After DOE illumi nation, Lens #2 performs the necessary Fourier transformation and assists in the creation of the desired optical output pattern on plane denoted by PL At this location, a bare, lensless CCD camera captures the intensity profile and digitizes the data for subsequent processing by the attached computer. Two CCD cameras were used for the experimental results reported in this thesis. The first camera was a Sony DXC-101 CCD camera providing an 8 -bit resolution at room temperature operations. The advantage of this CCD 119 jr < » i n ~ ft - * 3, b r.s ' - t o 5 T c . r- r~ O £• < — c a CD c « a n 5' ^ o Z fi • - * > 3, S' i s ? n ; o a • o m HP 4142B M easurem ent and Controller System HP 41421B HP 41421B Voltage/ Current Voltage/ Current Output Card M easurement Card VCSEL Laser Driving Signals Lens #1 Achromat 100 mm EFL 25.1 mm diameter Broadband AR Coating A VCSEL Wire-bonded in DIP Socket Lens #2 Achromat 100 mm EFL 25.1 mm diameter Broadband AR Coating A DOE f « ___4 inches f Apple llfx Running LabView 2.2.1 Sony DXC-101 CCD 527 x 459 pixels 24 mm x 24 mm pixel 55 % fill factor room temperature operatic SensiCAM CCD 527 x 459 pixels 24 mm x 24 mm pixel 55 % fill factor -12° C to o over competing CCDs in this category include high pixel density, high pixel fill factor, and the ability to disable the automatic gain control circuitry which is needed in order to accurately sample the optical field. This camera was used extensively for all early work performed characterizing the DOE until the 8 -bit image resolution limitation proved cumbersome. At this point a Cooke Sensi- CAM scientific grade CCD was procured with greatly improved measurement performance including pixel count (1376 x 1040 for the SensiCAM versus 510 x 492 for the Sony), pixel fill factor (SensiCAM >80%), and the spatial dimen sions of the individual pixels (rectangular for the Sony versus square pixels on the SensiCAM). This system also provided 12-bits of imaging resolution by thermoelectrically cooling the CCD camera down to -11° C. This reduces the shot noise and other associated thermal issues providing for a greater dynamic range of captured images. Fig. 4-10 shows the experimental optical reconstruction pattern from a quartz E-beam fabricated DOE illuminated with a 970 nm light source. This DOE was initially chosen to experimentally confirm the operation of all the system components of the experimental setup. This figure also shows a con tour plot of the intensity profile as a function of the CCD spatial dimensions generated by the optical output pattern of the 4:2:1 DOE. From this figure the 4:2:1 pattern is seen, namely the center spot is 2 times the optical intensity of the four nearest neighbors and 4 times the intensity of the next nearest neigh bors . 121 250 200 200 150 150 100 row 100 50 100 50 200 150 c o l 250 h 1 I 1 i . 50 75 100 125 150 175 200 Figure 4-10. Output optical reconstruction pattern from a quartz E-beam fabri cated D O E illuminated with a 970 nm light source. The figure on the left shows the output pattern on the face o f the Sony CCD camera, w hile the corresponding con tour plot is shown on the right. The reconstructed output profile has a measured individual spot size, measured full width half-maximum (FWHM), of 125 pm with each spot sepa rated by 2.5 mm. The optical intensities of these reconstructed spots deviate slightly from the desired pattern. The percent error deviation from each order of the 3 x 3 reconstructed pattern from the desired pattern is shown below: 122 5.3% 0.7% 5.0% 3.6% 8.5% 2.7% 5.3% 5.4% 3.3% A GaAs DOE was then placed in the optical setup and illumination with the light source. The reconstructed output profile is similar to the quartz DOE pattern that is shown in Fig. 4-10. Using the Sony CCD and quantizing the optical output one can calculate the observed diffraction pattern deviation from the theoretical intensity pattern. The percent deviation of this GaAs sample is shown below: 13.3% 1.1% ^ .0 % 11.9% 6.8% 2.7% 15.4% 3.3% 24.0% The diffraction efficiencies of each of the nine diffracted orders were measured at the design wavelength of 970 nm, resulting in errors from the the oretical (relative) diffraction efficiencies of between 1% and 24%, depending on the diffracted order. Treating all error deviations as positive quantities regardless of sign, an average error magnitude of 11.5% was obtained. The deviation between the reconstructed output patterns of the quartz and GaAs DOE samples can be attributed to a number of factors including microfabrica tion processing errors (this being the main source of errors) but additional fac 123 tors include experimental setup issues, the limited resolution of the CCD, and laser source fluctuations. The percent error values for the GaAs DOE are sig nificantly higher than the errors for the quartz DOE. Recall that the quartz DOE pattern is constructed using a very high resolution E-beam technology and significantly better optimized quartz etching equipment. At this point one might be content with these causes for the GaAs non-ideal output reconstruc tion profile. It would further be presumed that any additional issues causing these errors could well be characterized as one of the previously listed issues. Such is not the case. Figure 4-11 plots the relative intensities of the right nearest neighbor from the 4:2:1 GaAs DOE fan-out pattern as a function of DOE substrate rota tion. As the high-index, lossless GaAs substrate containing the DOE is rotated about normal incidence, a modulation of the reconstructed DOE optical inten sity pattern occurs. This intermodulation is seen on the graph occurring with an angular width of 1.9° and is caused by a Fabry-Perot effect. Fabry-Perot effects occur whenever two interfaces are parallel to each other each containing a “significant” Fresnel reflectance. In this case, due to the measured GaAs refraction index equal to 3.52, the corresponding Fresnel reflection coefficient per surface is 32.2%. This effect destroys the desired optical intensity pattern whenever the DOE substrate is rotated slightly. Fur ther, in this case we see that if the 4:2:1 DOE is only 0.6° off from normal inci dence, the right nearest neighbor beamlet’s optical intensity experiences a 124 n 1 ------- 1 ------- 1 ------- 1 ------- 1 ------- 1 ------- 1 -------1 ------- 3 ------- 1 -------1 ------- 1 ------- 1 ------- 1 ------- 1 ------- 1 ------- r 800 D < 'o 600 > 0 C B 400 O (/) 0 ^ 200 ■ $ ; • o 0 0.0 - — — — I — i i i i 1 i i i i 1 i t i i l i i J l _ 0.5 1.0 1.5 Angle (deg) 2.0 2.5 F igure 4 -1 1 . Grey scale value o f the o f the right nearest neighbor spot o f the DOE reconstruction pattern as a function o f D O E substrate rotation. nearly 50% change from ideal. Such a DOE effect has never before been reported. Further insight can be gained by simultaneously examining two individ ual beamlets of the 4:2:1 reconstructed profile as a function of angular rotation. Figure 4-12 plots the relative optical intensities of the right and left nearest neighbor beamlets from the same GaAs CGH. In this case we see both intensi- 125 0.0 0.5 1.0 1.5 2.0 2.5 Angle (deg) F igure 4 -1 2 . Grey scale value o f both the o f the right and left nearest neighbor spot o f the DOE reconstruction pattern as a function o f D O E substrate rotation. The im ages correspond to the angle values indicated by the vertical green lines on the graph. ties being modulated in a similar pattern with the left nearest neighbor’s pattern shifted slightly in angle. Two experimental configurations were used to explore this DOE charac teristic. The first configuration was the one shown in Fig. 4-9 using a VCSEL as the input light source. The Fabry-Perot effect was observed and recorded using this system. But when this system proved inadequate, especially in terms 126 of tight (i.e., small) physical dimensions of the setup and the limited power out put of the VCSELs, a new optical setup was constructed. This experimental configuration is shown schematically in Fig. 4-13. Of special importance in Ti:Sa Laser Motion Controller SensiCam C C D Spatial Filter Collimation Lens Iris Diaphram Macintosh LabView Controlled Rotation Stage with D O E Fourier Transform Lens F i g u r e 4 - 1 3 . Experimental configuration for investigation o f the DO E rotational perform ance, a consequence o f the Fabry-Perot optical effect. both setups is the Newport SR50 series compact high-resolution rotation stage and the Newport ESP 700 Universal High-Performance Motion Control ler/Driver that provided the needed resolution to explore this optical phenom ena. Together, the optical motion controllers and actuators costs nearly $25k but represented a marked improvement compared to traditional DOE character 127 ization setups. In this case, the Newport SR50 rotation stage provides a rota tional resolution of 0 . 0 0 1 ° and a uni-directional repeatability of 0 . 0 1 ° for experimental reliability and repeatability. This section discussed the optical fan-out performance of a quartz and GaAs CGH DOE. The use of GaAs was dictated by the need for thermal and unique packaging issues related to our proposed PMCM. During the investiga tion of this output reconstructed optical pattern a new, previously unreported effect was discovered which would not have allowed the use of any high-index DOE in our desired PMCM. A further, and just as significant conclusion, is that all DOE patterns fabricated in thin flat and parallel surfaces will also exhibit this phenomena although potentially not as severe. Further investiga tion is warranted, but this Fabry Perot effect should also be seen in nearly all DOEs which would account for some error in their reconstructed optical pro file. This effect has never before been reported. The next section brings us closer to the desired DOE architecture required for the PMCM by introducing optical tan-out with optical fan-in. 4.5.3.3 Demonstration of Optical Fan-Out/Fan-In The previous section demonstrated a l-to-9 analog fan-out using analog VCSEL driving techniques. The computational performance of our PMCM relies not only on optical fan-out but a combination of optical fan-out/fan-in. In this way information encoded using analog optical weights can be systemat ically transferred by nine smart pixels (when using a l-to-9 fan-out DOE) from 128 the upper PMCM layer and subsequently broadcasted out to nine smart pixels in the lower PMCM layer. The demonstration of optical fan-out/fan-in is significantly different from the results reported by others. First, we consider an analog optical fan-in/fan-out to provide an optical weighting between smart pixels in our PMCM. Second, we use high refractive index GaAs substrates as our DOE material. The reasons for this material and the consequences of its use were previously discussed. The motivation of this important experiment was to demonstrate a key stage in the integration of the photonic multichip module (PMCM). The initial setup included two lasers in the 8 x 8 VCSEL array emitting at 970 nm wave length connected to two independent VCSEL device drivers. The lasers were previously measured to have exhibited 400 mA electrical lasing thresholds and were configured in this setup to operate either one at a time, or both simulta neously. The first demonstration used the E-beam fabricated quartz-substrate dif fractive optical element. Each laser in the array was turned on independently, resulting in the desired 3 x 3 fan-out pattern previously shown in Fig. 4-10. Both lasers were then turned on to matched output intensities, and a DOE was located in a fashion that allowed the output patterns from the two lasers to over lap, as shown in Fig. 4-14. 129 150 125 100 ■ 75 r 50 50 100 150 c o l 200 150 250 100 50 row -r _ H 1 -------1 ------ r ~ 25 50 75 100 125 150 F ig u re 4-14. (left)Fan-in pattern from tw o 970-nm V C SEL elem ents w ithin an 8 x 8 array, transmitted through the sam e 4:2:1 diffractive optical elem ent (DOE), (right) M easured optical reconstruction pattern from two 970 nm VCSEL elem ents within an 8 x 8 array, transmitted through the sam e 4:2:1 diffractive optical elem ent (D O E ). The spot size (FW H M ) was 125 to 250 (im, with a spot separation o f 2.5 mm. This output pattern demonstrates one of the key functions of an analog fan-in needed for the functionality of the PMCM, and is the first such demon stration of its kind, to the best of our knowledge. The percent deviation of this sample from ideal is shown in below. The minimum error observed in the fourteen resulting diffracted spots was 0 .2 %, and the maximum error was 16%, with an average error of 7% again treating all error deviations as positive quantities regardless of sign. 130 Four Model 3811 ILX Laser Controllers under control of the LabView software package are then used to simultaneously drive four lasers and perform a 4-to-16 optical fan-in/fan-out. In this case, the VCSEL array is the MODE device with a 850 nm wavelength and 3.6 mA threshold. As before, the E-beam lithography (QPS, Inc.) DOE is used in conjunction with the Sony CCD camera as a digitizing frame grabber. The reconstructed optical pattern for one, two, three, and four lasers operating simultaneously is shown below in F ig .4-15. - I * : F igu re 4-15. Combination fan-out/fan-in for one, tw o, three, and four lasers. A nalog weighted optical intensity is shown in three o f the figures. A GaAs DOE was then placed in the optical setup and illuminated with a 970 nm Ti:Sa light source. The GaAs devices performed as expected. Chapter 131 Five details these results including the performance benefits using a thin film coating on the GaAs DOE structure. 4.6 Stratified Volume Diffractive Optical Elements Volume holographic optical elements (VHOE) are optical devices that chiefly use angular selectivity of the Bragg diffraction process to enable a num ber of unique applications including optical interconnections, optical storage, and adaptive optical learning networks [Johnson et. al., 1988; Nordin et. al., 1992a; Nordin et. al., 1992b]. In these applications, the VHOE specifically allows a large number of gratings to be simultaneously multiplexed within the same VHOE material. As is the case with most current optical devices, mate rial limitations severely impede this technology’s full potential. Ideally, VHOEs require materials configured for use in the Bragg operational regime, but since typical thickness of most holographic materials is only microns or tens of microns thick, a new approach is needed. Stratified volume holographic optical elements (SVHOE) overcome some of these limitations by stacking thin holographic structures in-between optically homogeneous buffer layers. Each of these individual holographic layers operate within the Raman-Nath diffraction regime but when configured into the SVHOE device with the appropriate buffer region between each modu lation layer, the SVHOE device emulates the optical properties of a thick, vol ume material. In particular, this result manifests itself as a periodic, angular dependence of the Bragg diffraction responses for both the +1 and -1 diffrac- 132 Anti-Reflection Coated, Planar Computer- G enerated Diffractive Optical Elements O utput Beam: Input B eam s F igure 4-16. M ultilevel D O E with layers o f phase or amplitude modulation interspersed with buffer regions. tion orders. Detailed characterization using both numerical modeling (with optical beam propagation (OPD) methods) and experimental devices character ize the dependence of the SVHOE diffraction properties on buffer-layer thick ness, number of modulation layers, total device thickness, total grating strength, and SVHOE diffraction behavior as a function of the normalized buffer-layer thickness parameter [Nordin et. al., 1992a; Nordin et. al., 1992b]. These experimental devices relied upon a novel DuPont photopolymer material (HRF-150) that was chosen for its ease of processing and excellent optical properties [Johnson et. al., 1988; Nordin et. al., 1992a; Nordin et. al., 1992b]. In one set of experiments a five layer SVHOE structure was constructed by 133 spinning thin films of the DuPont photopolymer on commercially available glass coverslips. After mounting the initial photopolymer-coated coverslip on an optically transparent glass substrate for mechanical stability, the back sur face of the coverslip was then photopolymer coated. Each subsequently coated coverslip was then mounted to the proceeding back coverslip surface. Addi tional process details and experimental verification are detailed in previously mentioned references. A key technology being explored by this project is the fabrication and modeling of novel computer-generated volume holographic and diffractive optical elements known as stratified volume diffractive optical elements (SVDOEs). These structures consist of multiple DOE layers containing phase or amplitude modulation distributed with buffer layers containing no modula tion at all as illustrated in Fig. 4-16. Alignment between successive stages dur ing SVDOE fabrication can be accomplished by mask alignment and layer fixation procedures similar to those employed in semiconductor VLSI process ing. The proper choice of the grating frequency and buffer layer thickness can yield structures with novel diffractive properties, such as periodic Bragg peaks in the angular spectrum, wavelength notch filtering, and spatial fre quency notch filtering. These SVDOEs will be used for complex, neural-like global interconnection patterns between stacked arrays of electronic proces sors. SVDOE structures have also been used as beam scanning elements in a space-based coherent wind light detection and ranging (LIDAR) system 134 [Chambers, 2000]. For this case, a transmissive SVDOE element was used to deflect an incident normal beam at a fixed output angle. The use of this ele ment was dictated by the need to maintain the incident beam’s polarization properties, have a low mass, and be survivablc in a space environment. In this section we demonstrate a novel, fully semiconductor manufactur able SVDOE. This approach does not require the complex optical interfero- metric system for making high spatial frequency phase patterns and instead leverages the enormous strides made in semiconductor processing over the past decade. The DOE layers can easily be constructed using traditional optical photolithographic equipment, or even e-beam writing equipment. This method also allows for the easy integration of different materials in the same stack. These materials can be chosen for their optical properties such as refractive index, dispersionary effects, absorption properties, etc., or their mechanical and thermal properties. Traditional SVHOEs and the previously reported SVDOEs do not allow this flexibility. A first generation system was constructed to vali date the approach and to optimize the various processing parameters. A simple two layer, SVDOE device shown in Fig. 4-17 was chosen as the test vehicle for this technology demonstration. The SVDOE was con structed using a set of individual GaAs Ronchi substrates containing a set of high resolution gratings with 16 micron fingers and a 32 micron pitch. These gratings are batch fabricated in a set of eight gratings as shown by the pho tolithographic mask design in Fig. 4-18. Each grating substrate has dimensions 135 16 Microns 1 » 32 Microns 375 Microns 375 Microns n = 1.0 (air) n = 3 .6 ( GaAs) n = 3.6 ( GaAs) F igure 4-17. Schem atic of two level G aAs-based SV D O E . of 1 cm by 1 cm and is surrounded by high resolution alignment iiducials for flip-chip alignment and bonding pads for indium deposition. The device processing sequence for these sample substrates started with a front and backside deposition of the alignment fiducials and bonding pads, followed by the grating photoresist definition and ECR etching, and ending with the thick photoresist processing and indium deposition needed for indium bump formation. The GaAs substrates are obtained from AXT and are similar 136 unasHverz/ceiin Poly t"4 : t a M H a H i • ■ h : 35304 y: 17763 Figure 4-18. Low -resolution screen capture o f one SV D O E mask show ing the layout and orientation o f the individual gratings. to those used for the fabrication of GaAs CGH as previously reported. An opti cal microphotograph of a processed GaAs wafer, pre-indium deposition, is shown in Fig. 4-19 below. The large gold pads are designed for the Indium bumps while the smaller arrays of gold patterns are used for alignment fiducials for photolithography and subsequent flip-chip bonding. The gold pads are typically only 100-200 A thick and were deposited atop a 50 A layer of Ni, necessary for better mechan ical adhesion to the GaAs wafer surface. Both metals were deposited under vacuum conditions using an Edwards metal deposition system and later 137 C-:0.++^^ F igure 4-19. Color optical micro-graph showing grating area, high resolution alignm ent fiducials needed for d evice integration, and large bonding pads for subse quent indium bump deposition. “lifted-off’ while in a bath of acetone. Not shown in the Fig. 4-19 are the cor responding alignment fiducials on the back substrate of each Ronchi ruling. These additional alignment fiducials are needed for the flip chip bonding fabri cation sequence. The alignment accuracy between fiducials were later confirmed using a Research Devices IR microscope with a high-performance MTI IR camera. Typical measured alignment accuracy between front and backside fiducials was 1 pm. 138 552 The grating structures were first defined in a layer of Clariant AZ 5214 photoresist. The same photoresist processing used for the CGH processing was employed here; namely, spin a 1 . 2 pm thick film of photoresist, bake film to remove solvent and assist in polymerization, and then allow a short wafer cool down cycle before using the Karl Suss MJB-3 contact mask aligner to image the grating pattern on the wafer. A benefit of our Ronchi ruling design is the large feature size which makes the photolithographic processing significantly easier. This is also important since it easily allows excellent uniformity across many sets of GaAs wafers whose importance will be discussed in detail in Chapter Six. The final step in the photoresist processing was a UV blanket exposure for 2-3 minutes in order to harden the pattern photoresist layer for use as an etching mask. This etching mask was suitable for use in the PlasmaQuest Model 98 ECR at the USC Keck Photonics Research Laboratory using the same process ing recipe that was used for the fabrication of the GaAs CGH. Both BC13 and Ar gas sources were used with flow rates of 25 seem and 5 seem, respectively, to yield a 14.3 A/sec etch rate with an incident 300 Watt RF power source. The gratings were etched to an etch depth of 0.192 pm. The etched gratings can also be seen in the lower left of the picture. The large feature sizes of the photolithographically defined structures made the post-processing characterization of the Ronchi rulings easier than the other previously mentioned SVDOE devices fabricated by others. As before, a Dektak IIA surface profilometer was used to measure the surface structure, 139 including the sidewall profile and etch depth. The measured etch depth varied between '-4 880 A and ~ 2 0 0 0 A over multiple wafers depending on measure ment scan location. Etch depth calibration was always performed on a test GaAs sample before etching the “good” GaAs SVDOE wafers containing the entire set of grating structures. In order to fully integrate these devices a method to attach multiple sub strates together was needed. This method, recently developed for hybrid inte gration of photonic/electronic devices, is called single sided indium bump bonding and is discussed in detail in Chapter Six. By intentionally increasing the thermal deposition rate, increasing the flip-chip bonding pressure, and per forming additional surface cleaning procedures, a single indium bump bond can be used in place of the traditional dual-bump bond structure. This is ideal for the hybrid integration of multiple SVDOE layers. A thick, two-layer photoresist coating was applied to the GaAs wafer using the same processing recipe discussed in Chapter Six. A blanket exposure of the first layer followed by a pattern exposure of the second layer was per formed on each SVDOE substrate. This was followed by a dark-field photo lithographic mask used for defining regions in the two-layer thick photoresist where individual indium bumps are to be formed. Typical indium bumps 50 pm by 50 pm in size and from 5 pm to 8 pm high were constructed. In most devices fabricated here a 7.5 to 8.0 pm bump height was used. When bonded using 8 grams of bump (total indium bump tack time of 40 seconds at room temperature) a 4 pm separation between bonded substrates was experimentally 140 observed using an optical microscope. A shorter 5 pm bump allowed both sub strates to be nearly in contact wiih each other after a 8 - 1 0 gram per bump bond ing force was applied during flip-chip integration. Small bump heights were also beneficial as it helps keep both substrates parallel with each other, espe cially true when both substrates are touching each other. Additional bonding parameters for this integration technique are discussed in Chapter Six. Figure 4-20 is an optical SEM of the Ronchi ruling with etch grating structures, alignment fiducials, and final indium bumps. This substrate is ready to bond to another substrate for construction of an SVDOE device. After the indium lift-off process and the subsequent GaAs wafer cutting to yield individual indium bumped die, the Ronchi ruling die were then mated together at room temperature using only force/pressure as the bonding parame ter variable with a RD Automation M 8 -A Flip-Chip aligner/bonder. Typical bonding accuracy is 1-2 pm for the M8 -A. The bumps were not reflowed or heated above the melting point of the metal as is customary in most flip-chip attach processes using solder bumps. Typically a 8-10 gram per bump bonding force was applied during flip-chip integration. After bonding, the sample received small dabs of non shrinking epoxy on the corners to improve mechan ical stability of the sample and allow for handling. A picture of two fully bonded devices is shown in Fig. 4-21. Modeling efforts needed for the characterization of stratified volume dif fractive optical elements used rigorous coupled-wave analysis (RCWA) tech- 141 Det WD |----------------- M 60 iim ■ SE 14 6 USC\MUni .SVDOE ij F igure 4 -2 0 . (top) SEM im age o f single layer o f SV D O E stack. Seen are indium bumps, alignm ent fiducials for subsequent flip chip bonding, and a phase grating region. Sample substatc is SI G aA s. (bottom ) Clo- seup SEM image o f single layer o f SV D O E stack show ing square indium bumps (two seen) and a high resolution Ronchi ruled phase grating. F igure 4-21. Two SV D O E sam ples fabricated using the described pro cessin g sequence. niques based on earlier work by D. Chambers at University of Alabama-Huntsville [Chambers, 2000]. RCWA works by breaking arbitrary grating profiles into a set of thin layers parallel to the substrate to allow easy computer modeling. The relative permittivity of each thin layer is expanded as a Fourier series. The rigorous couple-wave equations were then solved for each layer. Finally, matching EM boundary conditions between layers were applied in order to achieve correct modeling results. Additional process details on this method, including a detailed comparison of this computational method with other methods, stability of he RCWA algorithms, and improvements incorporated for use modeling SVDOE structures is available elsewhere [Chambers, 2000; Moharam et. al., 1981; Moharam et. al., 1982; Li, 1996]. 143 After SVDOE integration, an experimental setup similar to the one spec ified in Fig. 4-13 was used to measure the angular sensitivity of the SVDOE optical diffraction properties. The same Ion-Argon, ThSaph laser was used as the optical source but a couple of additional components were needed to mea sure the small optical powers. An EG&G Lock-in amplifier and later a better Stanford Research SR-850 DSP Lock-in amplifier, an optical chopper, a TRAMP low-noise pre-amplifier, and a low-noise detector assembly were the key additions to this optical setup. These new components allowed for very low measurement levels especially the SR-850 lock-in used in conjunction with the pre-amplifier. This setup allowed for the discrimination of photodetector output signals as small as 2 nV, and as large as 1 V. Note that one of the prime functions of the pre-amplifier was to convert the photocurrent generated from the photodetector into a corresponding low-noise voltage value that was required by the lock-in system. As before, this experimental configuration rep resents a substantial financial investment as well as a substantial investment of this author’s time tweaking all the parameters. The same high-resolution motion stages shown in Fig. 4-13 were also used in this experiment. The +1 diffraction order efficiency as a function of incident angle for an uncoated SVDOE is shown in Fig. 4-22 below along with the theoretical results gener ated by the RCWA modeling. There are a number of interesting characteristics of this graph. First, this data is severely modulated and nowhere near the smooth curves previously described when characterizing the SVHOE. This data is, however, similar to 144 0.30 F^T t >* Q 0.25 C CD ■ H o 0.20 ■ MH 3= L U C °-15 o . Experimental 0.10 3= g 0.05 Theoretical 0.00 0 incidence Angle fdeg) 20 F igu re 4-22. Optical intermodulation caused by Fabry-Perot effects. Critical to reduce these Fabry-Perot effects. the data reported by others fabricating SVDOEs [Chambers, 1999; Chambers, 2000]. As will be discussed in the next chapter, this large intermodulation fac tor is closely related to the Fresnel reflections from the multiple high-index refractive substrates employed in our SVDOE device. Unfortunately, in this case, the experimental data is not as close as the theoretical data. Although the data curves are divergent, a number of key similarities are striking. First, the intermodulations occur at most of the angular points predicted by theory, although the optical intensity values are not similar. Second, the minimums of both data curves occur at similar angular ranges. Although the difference between the theoretical and experimental data curves are not as close as they 145 should, the graphs are slightly better than the results reported by others for a simple two layer SVDOE structure. The majority of this difference can be attributed to the large feature sizes of the gratings, 32 fim for this example, verses the 2 |_tm gratings reported elsewhere [Chambers, 2000]. Finally, it should be noted that a four-layer SVDOE structure was designed and fabricated with the same fabrication parameters specified previ ously. This device was fabricated to further verify the fabrication issues regarding this technology base for SVDOE structures. An unusual aspect of this device is this it required three bonding sequences in order to fully integrate this four layer structure. In this case the bonding sequence was successful but the device was very sensitive to angular variations and proved very difficult to get repeatable results. Additional experiments are progressing. 4.7 Conclusion This chapter discussed the fabrication and optical characterization of a number of DOEs fabricated in a high index substrate material. Using Fourier optic principles, a DOE pattern, known as the 4:2:1 DOE that was previously developed, was fabricated by semiconductor processing on a high refractive index GaAs substrate. The optical characterization included optical fan-out measurements. Aside from the traditional sources of errors in the desired opti cal reconstruction pattern a new effect was discovered. Using a high perfor mance optical setup, a Fabry-Perot effect was identified which significantly altered the performance of the DOE. This unwanted effect would preclude 146 operation of any high-index DOE in our PMCM. For the GaAs 4:2:1 DOE, if the substrate is rotated by 0 .6 ° off from normal incidence, the right nearest neighbor beamlet’s optical intensity experiences a nearly 50% change from ideal. This DOE effect has never before been reported. We have constructed a fully semiconductor manufacturable SVDOE. This approach does not require the complex optical interferometric system for making high spatial frequency phase patterns and instead leverages the enor mous strides made in semiconductor processing over the past decade. The first generation system was constructed to validate the approach and to optimize the various processing parameters. The next chapter addresses a number of issues which have been identi fied in both Chapter Three and Chapter Four. Both the limited optical power of the VCSEL and the Fabry-Perot effect on the performance of the DOEs will be affected. 4.8 References K. Ananthanarayanan, C. H. Chen, S. DeMars, A. A. Goldstein, C. C. Huang, D. Su, C. B. Kuznia, C. Kyriakakis, Z. Karim, B. K. Jenkins, A. A. Sawchuk, and A. R. Tanguay, Jr., “Multilayer Electronic/Photonic Multichip Modules with Vertical Optical Interconnections,” in OS A Annual Meeting Technical Digest Series, ILS/XI Program, (Optical Society of America, Washington, D.C.), Vol. 10, p. 150,(1995). 147 Brown, B. R. and A. W. Lohmann, “Computer-Generated Binary Holograms,” IBM J. Res. Develop. 13, pp. 160-168,(1969). Chambers, D. M., and G. P. Nordin, "Stratified Volume Diffractive Optical Elements as High Efficiency Gratings", J. Opt. Soc. Am. A 16(5), pp. 1168-1174(1999). Diana M. Chambers, Ph.D., "Stratified Volume Diffractive Optical Elements," University of Alabama-Huntsville, (2000). R. J. Collier, C. B. Burckhardt, and L. H. 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Tanguay, Jr., “Photonic Implementations of Neural Networks,” in Neural Networks for Signal Processing, B. Kosko, Ed., (Prentice-Hall, Englewood Cliffs, NJ), pp. 287-332, (1992). R. V. Johnson and A. R. Tanguay, Jr., “Stratified Volume Holographic Optical Elements,” Opt. Lett., 13, pp. 189-191, (1988). W. R. Klein and B. D. Cook, “Unified Approach to Ultrasonic Light Diffraction,” IEEE Trans. Sonic Ultrason., SU-14, pp. 123-134, (1967). H. Kogelnik, “Coupled Wave Theory for Thick Hologram Gratings,” Bell Syst. Tech. J., 48(9), pp. 2909-2947, (1969). L. Li, “Use of Fourier series in the analysis of discontinuous periodic structures,” J. Opt. Soc. Am. A, 13, pp. 1870-1876, (1996). Y. Lin, T. J. Kessler, G. N. Lawrence, “Design of continuous surface-relief phase plates by surface-based simulated annealing to achieve control of focal-plane irradiance,” Optics Letters, Volume 21, Issue 20, pp. 1703-1705, (1996). J. S. Liu, M. R. Taghizadeh, “Iterative algorithm for the design of diffractive phase elements for laser beam shaping,” Optics Letters, Volume 27, Issue 16, pp. 1463-1465,(2002). 149 C. B. I<.uznia, C. C. Huang, K. Ananthanarayanan, C. H. Chen, and A. A. Sawchuk, “Micro Diffractive Optical Element for Smart Pixel Fan-out Interconnections,” in OS A Annual Meeting Technical Digest Series, ILS/XI Program, (Optical Society of America, Washington, D.C.), vol. 10, p. 149, (1995). M. G. Moharam and T. K. Gaylord, “Rigorous coupled-wave analysis of planar-grating diffraction,” J. Opt. Soc. Am., 72, pp. 811-818,(1981). M. G. Moharam and T. IC . Gaylord, “Diffraction analysis of dielectric surfacc-relief gratings,” J. Opt. Soc. Am., 72, pp. 1385-1392, (1982). G. P. Nordin, R. V. Johnson, and A. R. Tanguay, Jr., “Diffraction Properties of Stratified Volume Optical Elements,” J. Opt. Soc. Am. A., 9, pp. 2206-2217 (1992). G. P. Nordin and A. R. Tanguay, Jr., “Polymer-based Stratified Volume Holographic Optical Elements,” Opt. Letts., 17, pp. 1709-1711 (1992). G. Nordin, “Volume Diffraction Phenomena for Photonic Neural Network Implementations and Stratified Volume Holographic Optical Elements,” Ph.D. Thesis, University of Southern California, (1992). D. H. Raguin, S. Norton, and G. M. Morris, “Subwavelength Structured Surfaces and Their Applications, in Diffractive and Miniaturized Optics, Sing Lee, Ed., Critical Review Vol. CR49, pp. 234-261, SPIE Optical Eng. Press, Bellingham, WA. (1993). 150 E. Pawlowski, H. Engel, M. Fersti, W. Furst, and B. Kuhlow, “Diffractive Microlenscs with Antireflection Coatings Fabricated by Thin Film Deposition,” Opt. Eng., 33 (2), 647-652, (1994a). E. Pawlowski and B. Kuhlow, “Antireflection Coated Diffractive Optical Elements Fabricated by Thin Film Deposition,” Opt. Eng., 33 (11), pp. 3537-3546, (1994b). C. V. Raman and N. S. N. Nath, “The Diffraction of Light by High Frequency Sound Waves: Part I,” Proc. Ind. Acad. Sci. A, 2, pp. 406-412, (1935a). C. V. Raman and N. S. N. Nath, “The Diffraction of Light by High Frequency Sound Waves: Part II,” Proc. Ind. Acad. Sci. A, 2, pp. 413-420, (1935b). C. V. Raman and N. S. N. Nath, “The Diffraction of Light by High Frequency Sound Waves: Part III,” Proc. Ind. Acad. Sci. A, 3, pp. 75-84, (1936a). C. V. Raman and N. S. N. Nath, “The Diffraction of Light by High Frequency Sound Waves: Part IV” Proc. Ind. Acad. Sci. A, 3, pp. 119-125, (1936b). C. V. Raman and N. S. N. Nath, “The Diffraction of Light by High Frequency Sound Waves: Part V,” Proc. Ind. Acad. Sci. A, 3, pp. 459-465, (1936c). G. K. Skinner, “Diffractive/refractive optics for high energy astronomy” Astronomy and Astrophysics, 375, pp. 691-700, (2001) A. R, Tanguay, Jr., B. K. Jenkins, and A. A. Sawchuk, “Dense 3-D Integrated Electronic/Photonic Computing Structures Enabled by Diffractive Optical 151 Elements,” Report document submitted by University of Southern California, Los Angeles to AFOSR, Washington, D.C., pp 1-29, (1993). A. R. Tanguay, Jr., B. K. Jenkins, C. von der Malsburg, B. Mel, G. Holt, J. O ’Brien, I. Biederman, A. Madhukar, P. Nasiatka, and Y. Huang, “Vertically Integrated Photonic Multichip Module Architecture for Vision Applications”, Proceedings of the International Conference on Optics in Computing (OC 2000), Quebec City, Canada, pp. 1-17, June 18-23,(2000). N. Yoshikawa, M. Itoh, T. Yatagai, “Quantized phase optimization of two-dimensional Fourier kinoforms by a genetic algorithm,” Optics Letters, Volume 20, Issue 7, pp. 752-754, (1995). 152 Chapter 5 Thin Films for PMCM 5.1 Introduction The operational wavelength regime for our PMCM was chosen to corre spond to the wavelength availability of VCSELs, the absorptive properties of the substrates making up the layers in the PMCM, and the unique through-sili- con optical addressing scheme employed by the PMCM. A further consider ation was the use of GaAs as the substrate for all diffractive optical elements due to thermal and mechanical issues between mated substrates in the PMCM stack. A consequence of employing these materials is an optical effect known as Frcsnel reflections which severely limits optical throughput by causing sig nificant amounts of unwanted surface reflections. Silicon has an index of refraction of 3.45 and GaAs has an index of 3.52 cam1 . ' ig Fresnel losses > 30% at each air/substrate interface. Anti-reflection (AR) filters are a way to reduce these optical losses. The desired minimum in reflectivity occurs when a thin-film is designed to be equal to a quarter-wavelength at the chosen optical wavelength. These filters have 153 been applied to numerous high refractive index devices including multiple quantum well spatial light modulators [Karim, 1993], Fresnel lens [Pawlowski et. al.\ 1994b], and semiconductor optical amplifiers [Vassallo, 1988]. For the case ol the AR coating on the GaAs-based spatial light modula tor (SLM), the AR coating fabricated was a unique transparent and conductive material known as indium ti" oxide (ITO). This ITO coating improved inser tion losses into the SLM while simultaneously improving contrast ratios for individual pixels in the SLM array. AR coatings using films such as MgC>2 and TiN have also been applied to passive, high-index devices including diffractive optics [Pawlowski et al., 1994a; Pawlowski et ciL, 1994b]. For these devices, however, the main impetus was a need for optical throughput improvements. The use of AR coatings for layers in the USC-designed MQW-SLM based PMCM has been suggested as a means to increase optical throughput [Ananthanarayanan, 2002]. In this chapter we explore the use of ITO coatings on multiple devices in our new VCSEL-based PMCM stack. Initially, we par allel the development of the AR coatings as others have suggested as a means to improve the optical power budget of our PMCM. In this way, the limited optical illumination provided by the low threshold and low power VCSEL can provide enough optical power for the successful operation of our through-sub- strate PMCM stack configuration. We then investigate the use of the ITO AR coatings on high refractive index diffractive optical elements, both the computer generated holograms and 154 stratified volume diffractive optical elements, but a different approach is taken. Our novel approach, and one to the author’s knowledge that has not been stud ied before, considers the effect of the AR coating on the performance of the dcsigned-for analog optical output profile of both DOEs. We examine the effect of the AR coatings on these high index substrates and show that not only does an AR coating improve the optical throughput but that this AR coating is actually needed for both DOEs to work as theoretically predicted. As will be discussed, the expected “picket- fence” optical effect for a two level SVDOE substrate [Nordin, 1992], like the one fabricated in Chapter Four, is only seen when using this ITO AR coating on the high refractive index GaAs substrates. When a similar AR coating is applied to a CGH, we remove the unwanted rotational effect that was explored in the previous chapter. Without this necessary coating, this unwanted effect would require extremely precise, if not unobtainable, PMCM integration. Section 5.2 discusses the properties and design of an antireflection coat ing using ITO. This is followed by a discussion on the fabrication of the multi function antireflection coating using a Sloan high vacuum sputtering system. A detailed characterization of the ITO thin film coatings using a variable angle spectroscopic eilipsometer (VASE), Dektak surface protilometers, and a Cary-Varian spectrophotometer is presented in Section 5.4. Section 5.5 describes the use of this coating on tf ^ PMCM including a detailed study of the ITO thin-lilm coatings on computer generated holograms (CGHs) and stratified volume diffractive optical elements (SVDOEs) presented in Section 5.6 and 155 Section 5.7, respectively. Finally, we will conclude this chapter with a brief re-evaluation of the ITO AR coating results. 5.2 Design of Multifunction Antireflection Coatings Indium tin oxide is used in many modern applications but is especially popular for the construction of liquid crystal (LC) displays due in part to the thin film’s low absorption properties in the visible wavelength regime. Of equal consideration is the thin film’s high conductivity, making it ideal for any applications requiring generation of EM fields or voltage/ground planes such as LC displays. Typical electrical sheet resistance of ITO thin films range from 20 O/square to more than 5000 O/square depending on ITO growth properties and post-growth thin film annealing times and temperatures. These films are typically deposited under high vacuum conditions using DC and RF sputtering techniques, although this film has also been applied via E-beam deposition, laser ablation, and ECR deposition techniques. Changes in the ITO sheet resistance and the absorption properties can be attained by the manipulation of the oxygen anion vacancies [Fan el al., 1977; Buchanan et al., 1980, Nath et al., 1981 J by controlling the background reaction oxygen partial pressure during the deposition process as has been identified previously [Karim, 1993; Vossen, 1971; Bender etal., 1998], A further tuning property of ITO, and one which has previously been exploited for use on the GaAs SLM, is that the refractive index can be altered 156 with oxygen content during ITO deposition [Karim, 1993; Bender et. al., 1998]. This property allows for the refractive index to be changed up to An = 0 .2 . The ITO thin films deposited in our deposition chamber use a 80% ^ 0 3 /2 0 % Sn2 0 3 target (index ~1.9) making it ideal for a single layer AR coating. The ideal ITO refractive index for GaAs is determined by the equation given by: ^ IT U ~ and for silicon n GaAs In order to determine the ideal thickness of the deposited film the follow ing simplified equation can be used: in which X is the wavelength at which the reflection is to be minimized [Hecht, 1987], C l 157 Although this equation is theoretically capable of determining the appro priate thickness layer, the software program TFCalc is used to calculate the final, optimal ITO film thickness. This software package optimizes thin film designs based on user designated target parameters and supports the inclusion of a variety of thin films parameters including dispersionary effects and absorp tion coefficient, unlike the simplified equation above which just incorporates the wavelength and optical index of refraction. A further reason for the supe rior performance of this software package is that it allows for the incorporation of the exact thin film ITO parameters fabricated by us and the accompanying substrate material parameters (in our case, both GaAs and Si substrates) in order to find the optimal ITO film. A graphical representation of the optical reflectance as a function of wavelength for our ITO film deposited atop a GaAs substrate is shown in Fig. 5-1. The optimized ITO thin film thickness results generated after 250 itera tion cycles on a Macintosh G3 computer with a 1 minute total program execu tion time is 1296 A. This value deviates slightly from the thickness predicted by the traditional thickness equation above (1293 A) and reflects the additional material parameters of the OMDL ITO thin film and the substrate material parameters. Using this program for a target wavelength of 970,0 nm, the optimal AR thickness is 1296 A for GaAs (measured refractive index value of n = 3.52) and 1305 A for a silicon substrate (measured refractive index value of n = 3.45). 158 5.3 Fabrication of Multifunction Antireflection Coating A Sloan sputtering system containing a set of S-310 sputter guns is used to deposit the ITO thin films by RF reactive sputtering. One of the S310 cylin drical sputtering guns held the ITO target composed of a hot pressed 90 wt.% I112O 3 10 wt.% Sn0 2 material. The substrates were 2-3 cm away from the tar get source during deposition. When combined with the substrate rotation, a uniform ITO deposition occurs across our 1 cm by 1 cm (or smaller) substrate sizes. A manual mass flow controller restricted the 99.9% Ar/ 0.1% O2 mixture flow rate at 55-60 seem that has previously been optimized [Karim, 1993] for use as an AR coating on a GaAs MQW-SLM. 2 . 0 - 900 920 940 980 1000 1020 1040 R e fle c ta n c e os Wavelength CnnO F i g u r e 5 - 1 . TFCalc plot o f reflectance as a function o f wavelength for an opti mized thin film coating of thickness 1296 A. 159 All deposition parameters were kept constant during the deposition pro cessing. Prior to actual deposition, the Sloan chamber with loaded sample was O pumped to a base pressure of 5 x 10“° Torr. The process pressure during depo- 9 sition was held constant at 10 microns Hg (1 x 10 Torr) by controlling the gate throttle valve on the CTI- 8 cryohead. The Ar/C> 2 mixture had a flow rate of 55-60 seem during deposition. The sample chuck was rotated at a rate of 20-25 rev/min in front of the target for better thin film uniformity. A 250 watt incident RF power with 0-2 Watt reflectance RF power was used during deposi tion to yield a typical deposition rate of 1 . 8 A/sec. Note that this number fluc tuates slightly and often requires recalibration. During deposition on the test substrates, a number of preliminary depositions are always performed to com pletely characterize this deposition rate. The entire deposition process was per formed at room temperature. Table 5-1 summaries these deposition Table 5-1: ITO Deposition Parameters Incident RF Power 0.25 kWatt Reflected RF Power 0.0 kWatts Argon Pressure 10-11 mTorr Oxygen Backbleed partial pressure 1 0"6 Torr Substrate Rotation Enabled Flow Rate 55 seem Typical Deposition Rate 1 .8 A/sec Base Pressure 5 x 10" 8 Ton- Deposition Pressure 10 microns Hg 160 parameters. All samples were cleaned using acetone, methanol, and DI water prior to placement inside the Sloan system. When placed on the 5’’ wafer chuck inside the chamber, the sample was always oriented in the center of the chuck, directly underneath the ITO target. In this way better him uniformity was obtained. 5.4 Optical Characterization of ITO Antireflection Coating Two Dektak profilometers and a J.A. Woollam variable angle spectro- graphic ellipsomcter was used to characterize the deposited ITO thin him prop erties. A high performance Cary-Varian 2300 Spectrophotometer was also used to measure the reflection and transmission properties of the ITO layer. The Dektak prohlometer is a relatively simple device that plots the sur face height as a function of lateral displacement by measuring the on-board sty lus deflection caused by the sample surface structure. Two separate Dektaks are initially used, a Dektac IIA in the W. M. Keck Photonic Cleanroon, and an older Sloan Dektak located in the Optical Materials and Devices Laboratory (OMDL). Both machines have a theoretical measurement accuracy of 10 A so this method of characterization is limited. The measured thicknesses of sam ples deposited for a 1296 A him varied between 1282 A and 2013 A. Since it turns our that the index requirement is a more stringent requirement than the ITO thickness to achieve the desired null in reflectivity, a better method is needed for ITO thin him characterization. 161 ITO films have always presented difficulties when attempting to com pletely characterize their optical properties. The prime reason is the complex graded microstruture of the deposited film seen as variations in the refractive index throughout the film thickness. Typically these variations are very small and don’t affect the optical performance of the device, such as those films used for AR coatings. But these variations present problems when attempting to characterize the structure of the film for use in relining the deposition parame ters of the ITO thin films. A J. A. Woollam Variable Angle Spectroscopic Ellipsometer (VASE) is a fully automated thin film characterization system. By combining a variable angle ellipsometer with a multiwavelength optical illumination source, this measurement system can yield highly accurate measurements of the refractive index, the absorption coefficient, and the thin film thickness. Variable angle ellipsometry works by measures the change in polariza tion state of light reflected from a sample under study at various angles of inci dence. The change in polarization state is related to the ratio of Fresnel reflections, expressed as Rp and Rs, for the p- and s-polarized light. This sys tem is further combined with a wide wavelength illumination source providing a wavelength range from 193 nm to 2200 nm for enhanced performance. In order to accurately gauge the ITO coating parameters a single layer ITO thin film was RF deposited onto a well characterized, stable, and optically flat quartz substrate. The film was deposited at 250 Watts for seven minutes 162 according to the same parameters shown in Table 5-1. The film, like all the ITO films in this thesis, was annealed at 200° C for 1-2 hours in a vacuum fur nace also located within the labs of OMDL. The ellipsomctric V F and A data were acquired at three incident angles (60, 65, and 70 degrees) over a spectral range of 700-1700 nm in steps of 10 nm. At this point we now need to lit the acquired data into an optical model to determine the parameters of the optical thin film. Although a simple Cauchy model could be used to fit this data, a Lorentz (harmonic) oscillator model was chosen for fitting this ellipsomctric data as it tends to offer the best performance [Synowicki, 1998]. This model is easily implemented using built-in software commands on the J. A. Woollam Co., Inc. VASE software on the attached PC. After fitting this data to the model, the ITO film thickness, the refractive index and the extinction coefficient, k, were obtained. A 7 minute ITO deposition yielded a film of 822.88 A thick, with n = 1.876, and k = 0.0. The values are similar to those reported earlier [Karim, 1993]. This data allows the TFCalc software to re-optimize the AR thin film coatings. An ITO AR coating was then applied to bare GaAs and silicon sub strates. Unlike earlier characterization attempts which were solely designed to determine the film thicknesses and their optical material properties, a Cary-Varian 2300 spectrophotometer is used to characterize the optical AR 163 properties of the film, namely the optical transmission and reflection. The Cary-Varian system was fitted with < . VW reflectance attachment for easy char acterization of the surface reflectance. Hie performance of the ITO AR coat ings on bare GaAs and silicon substrates is shown in Fig. 5-2. These results are Figure 5-2. Summary of ITO thin film coating on a GaAs and Si planar sub strates. (* measured using the Cary Varian Spectrophotometer). also similar to those reported by others [Karim, 1993] 5.5 Thin Film Coating for PMCM In the previous sections we fabricated a single layer thin film with AR properties which are useful for both GaAs and silicon. Both these substrates figure predominantly in our multiple layered photonic multichip module. Hav 164 ing optimized and separately characterized the thin films for both of these basic substrates, we now turn our attention to the application of this thin film for more specific uses with our PMCM. In Section 5.5.1 we consider the use of the films in relation to the total optical power budget available for our PMCM. Starting with the optical power available in our vertical cavity surface emitting lasers and ending with respon- sivity of our VLSI optical detectors, we trace the optical fields and associated optical powers as we pass through multiple surfaces in the AR coated PMCM stack. Section 5.5.2 then considers the use of thin films on computer generated holograms. We investigate the effect of the AR coatings on the desired optical fan-out and later fan-out/fan-in pattern using the same 4:2:1 GaAs DOEs as explored in the previous chapter. Finally, Section 5.5.3 characterizes the use of ITO AR coatings on strati fied volume diffractive optical elements. A comparison between theoretical and experimental performance is performed in this section including further characterization of the unwanted effects seen in the previous chapter. 5.5.1 Optical Power Budget This section characterizes the optical power budget for the AR coated VCSEL-based PMCM stack similar to the analysis performed in Section 3.7.4. Shown in Fig. 5-3 is a PMCM cross section in which two adjacent VCSELs are 165 M UR! : A R Coated P M C M Architecture -- Dual VCSEL Operation Figure 5-3. Schematic figure of an AR coated PM CM characterizing all unwanted optical losses. 166 '-0Z (lAmps - x C e t e c t o r illuminating a single DOE substrate in a mple two-layer AR coated system. Both the silicon and gallium arsenide substrates, including the lens array, are coated using optimal ITO layers. The output optical beam still obeys the refraction properties predicted by Snell’s Law. Also shown on this schematic is a plot of the total optical power as it travels through the stack. As configured for this calculation, each VCSEL is assumed to a have a wall plug lasing effi ciency of 33% and a maximum output optical power of Iq mWatts (3 mWatts in this case). The width of the orange line represents the total optical power at that point in the coated PMCM. Note, as before, that this simplified model takes into account all Fresnel reflection and absorption properties of substrates while ignoring all unwanted optical diffraction effects. Furthermore, this model assumes that all optical energy is surface normal to each surface, excludes any dispersionary effects, and does not include multiple reflections within the stack architecture. Those effects withstanding, this model still pro vides an excellent starting point for initial optical power estimates for an AR coated PMCM, especially for providing an estimate of the optical energy strik ing the VLSI photodetectors. As seen in the figure, two VCSELs are separated by a 125 pm pitch with me red-lines representing the optical beam path of a 8 pm VCSEL oxide aper ture and the blue lines representing the optical beam path for a 6 pm VCSEL oxide aperture. Both beams propagate thru the GaAs VCSEL substrate with little loss until striking the back VCSEL surface. At this point two optical effects occur, Fresnel losses and optical refraction. Of concern to us is the 167 change in Fresnel losses for this AR coated substrate. From previous optical power calculations we observed a total Fresnel loss at each air/substrate inter face equal to nearly 33%. For an ideal AR coated surface all this optical energy passes through the interface without any losses. Assuming that 75% of the light is diffracted by the DOE into the neces sary orders, indicated by the Xdoe term’ an< 3 the silicon detector’s responsivity is 0.15 Amps/Watt, the final value of electricalcurrent reaching the photodetec tor is 5.02 pAmps for a 1 mWatt input optical source— more than enough to drive the VLSI computational electronics. This is in contrast to the previously calculated result of 0.22 p.Amps for a 1 mWatt input optical source. Essen tially, we are removing the Fresnel reflection from six surfaces (five GaAs sur faces and the single back surface of the computational layer). Notice that final power, i.e., the power hitting the silicon photodetectors, is now only dependent on the input optical power, the efficiency of the DOE array, and the silicon VLSI substrate thickness. This makes any subsequent PMCM power optimiza tion problems considerably easier. 5.5.2 AR Coating on Computer Generated Holograms The previous demonstration of optical fan-out from a GaAs DOE yielded diffraction efficiency errors of between 1% and 24%, depending on the diffracted order, with an average error magnitude of 1 1.5%. again treating all error deviations as positive quantities regardless of sign. Typically these errors 168 are acceptable in a neural network-like environment, but we decided to reduce these errors by applying an antireflection (AR) coating. The first set of experiments characterized the effect of an AR coating on the DOE optical fan-out performance, especially in relation to the theoretical diffraction efficiencies. Later, the DOE optical fan-out/fan-in performance is considered. A 4:2:1 GaAs DOE fan-out pattern was coated on both front and back surfaces with a 1296 A layer of indium tin oxide (ITO), deposited by RF mag netron sputtering. The Sloan ITO chamber with loaded sample was pumped to Q a base pressure of 5 x 10 Torr. The process pressure during deposition was held constant at 10 microns Hg (1 x 10'“ Torr) by controlling the gate throttle valve on the cryohead. The Ar/Og mixture had a flow rate of 55-60 seem dur ing deposition as before. The sample chuck was rotated at a rate of 20-25 rev/min in front of the target for better thin film uniformity. A 250 W RF power source was used for ITO thin film deposition. The deposited antireflection coatings are ideal for use with the 4:2:1 DOE. Figure 5-4 shows the percent error data for the DOE optical reconstruc tion pattern for a coated (left) and an uncoated device (right). As compared with the previously described uncoated GaAs DOE array, the antireflection (AR) coated GaAs DOE array exhibited errors from the theoretical (relative) diffraction efficiencies of between 0.6% and 9.5%, depending on the diffracted order, with an average error magnitude of 5.29c. The uncoated DOE sample 169 Percent Error Data Percent Error Data Output Profile 5.2% 4.2% 3.7% 13,3% 1.1% 22.0% 2.9% 6.7% 0.6% 11.9% 6.8% 17.6% i 9.5% 4.5% 9.5% 15.4% 3.3% 24.0% Figure 5-4. Percent error in reconstructed output optical diffraction profile for a coated and uncoated DOE. exhibited theoretical (relative) diffraction efficiencies of between 19c and 24%. depending on the diffracted order, with an average error magnitude of 11.5%, again treating all error deviations as positive quantities regardless of sign. These results demonstrated substantial improvement with the AR coated DOE sample. Part of this improvement can be attributed to the elimination of the pre viously discovered, unwanted CGH Fabry-Perot effect. Recall that the Fabry-Perot effects occur whenever two interfaces parallel to each other, with each surface containg "significant" Fresnel reflectance. In this case, due to the measured GaAs refraction index equal to 3.52, the corresponding Fresnel reflection coefficient per surface is 32.2%. This effect wr as shown to destroy the desired optical intensity pattern whenever the DOE substrate is rotated slightly. Furthermore, this effect was significant when the 4:2:1 DOE was rotated only 0 .6 ° off from normal incidence. In this case, the right nearest neighbor beamlet's optical intensity experienced a nearly 50% change from ideal. 170 This same 4:2:1 GaAs DOE had both front and back surfaces coated with an ITO AR coating. A plot of intensity as a function of DOE substrate rotation of the rightmost diffracted order in the optical output reconstructed pattern is shown with and without an ITO coating in Fig. 5-5. In this case, no AR Coating A n g l e ( d e g ) Figure 5-5. Graph characterizes variation of optical intensities (.as measured on a Cooke 12-bit. eooled-CCD camera) as a function of angular tilt. intermodulation is seen for this CGH DOE. The significance of this plot is three-fold. First, as expected, an optical throughput increase is observed, providing more optical power into the desired 171 optical output pattern. Second, the overall accuracy of the desired pattern is increased. Finally, and potentially most significant, is that there is no longer a DOE rotational dependence. This makes is easier to fully integrate this DOE substrate with the PMCM. Any unintentional rotational effect caused by improper flip-chip integration is now removed. An AR coated GaAs DOE was then characterized for fan-in/fan-out per formance. Using the same optical setup that was discussed in the previous chapter, the GaAs DOE was mounted and fully characterized. The recon structed output profile using the dual coated 4:2:1 GaAs DOE is shown in Fig. 5-6. The high performance SensiCAM CCD was used to sample and quantize the resultant optical output. This 12-bit CCD camera also allowed for the char acterization of the observed diffraction pattern deviation in comparison to the theoretical intensity pattern. The percent deviation of each 4 x 4 diffractive order for this sample is shown below. 0.0 A 8.8 A 3.4 A 0.0 A 4.4 A 0.5 A 5.8 A 2.8 A 4.1 A 7.2 A 3.4 A 0.5 A 0.0 A 6.1 A 7.4 A 0.0 A Additional data calculations yield a 4.4A rms error and a a = 3.0A. These values represent a more desirable reconstructed output intensity perfor mance. Figure 5-6. (left) Fan-in pattern from two 970 nm VCSEL elements within an 8 x 8 array, transmitted through the same 4:2:1 diffractive opti cal element (DOE), (right) Measured optical reconstruction pattern from two 970 nm VCSEL elements within an 8 x 8 array, transmitted through the same 4:2:1 GaAs diffractive optical element (DOE). The spot size (FWHM) was 125 to 250 pm, with a spot separation of 2,5 mm. 5.5.3 AR Coatings on Stratified Volume Diffractive Optical Elements This section investigates the use of AR coatings on stratified volume dif fractive optical elements, specifically examining the effect of ITO coatings on the unwanted Fabry-Perot effect which was discovered in the previous chapter. We begin this analysis using simple 1-D Ronchi ruling gratings as the test vehi cles before expanding into multilayer SVDOE structures. In this way, we slowly build our knowledge and get additional insight into this Fabry-Perot phenomena. A Ronchi ruling is a two phase level DOE, in our case fabricated in a GaAs substrate, with square-wave phase only gratings shown schematically in Fig. 5-7. The period between etched grooves is 32 pm with a 50% grating duty 37 5 M icrons 1 6 Microns 32 Microns W n = 1 . 0 (air) GaAs Figure 5-7, GaAs Ronchi ruling with a 32 pm pitch and a 16 pm grating fingers. cycle. The Ronchi ruling fabrication technique was performed using the same photolithography and ECR etching protocols as was previously discussed for the GaAs computer generated holograms. One of the prime motivations for these large feature sizes was the ease of micro-fabrication which allows any cleanroom construction variables to be minimized between grating structures fabricated at slightly different times on different 2" GaAs wafers. 174 Earlier in Chapter Three a short discussion of the angular diffraction properties of both “thin” and “thick” gratings was performed. Thick gratings are those which have a strong angular dependence while thin gratings have req uisite diffraction efficiencies that vary little with incident angle. Figure 5-8 0.30 T h e o r e t i c a l O 0.25 y 0.20 ' 1 ifS , ff d t-' c °-1 5 E x p e r i m e n t a l 0.00 0 2 4 6 8 10 12 Incidence Angle (deg) Figure 5-8. Diffractive efficiency as a function of incident angle for the GaAs Ronchi ruling with a 32 pm pitch and 16 pm grating fin gers. shows an experimental and theoretical plot of the + 1 order diffraction effi ciency as a function of incident angle for the high index, GaAs Ronchi ruling grating configured as a thin grating. In this case, we see a strong dependence on the diffraction efficiency with the input optical beam's incident angle. Also plotted with the experimental data is the theoretical diffraction efficiency gen- 175 erated by the RCWA analysis program previously discussed. The experimental setup used for this device characterization is based on the setup shown in Fig. 4-13 with a few additional pieces of equipment. Having previously discussed the advantages of the high performance motion stages, the experimental config uration adds an additional SRS-80 Lock-in amplifier, a low noise pre-amplifier (TRAMP), and a precision optical chopper. Combined together, this setup allowed for high accuracy and repeatable results. In Fig. 5-8 we see a number of interesting characteristics. First, an unwanted intermodulation of the diffraction efficiency as a function of incident angle is seen. This intermodulation, like the intermodulation of the computer generated holograms, occurs tit very small angle displacements and is similarly caused by the Fabry-Perot optical effect. Second, although the theoretical and experimental data curves are not exactly equal, the general shape is similar. The deviation from the theoretical and experimental data curves is partially attributed to a slight mismatch between the real and actual grating etch depths performed during the semiconductor processing. This etch depth mismatch manifests itself in an overall lower diffraction efficiency. The same Ronchi ruling was then backside coated with an ITO coating similar the one used for the computer generated holograms shown schemati cally in Fig. 5-9. Prior to actual deposition, the Sloan chamber with loaded sample was pumped to a base pressure of 5 x 10 Torr. The process pressure during deposition was help constant at 10 microns Hg (1 x 10 Torr). The pre viously optimized A1VO2 mixture had a flow rate of 55-60 seem during deposi- 176 375 Microns 1 6 Microns 32 Microns t I n = 1.0 (air) GaAs thickness « 1296 A (ITO Figure 5-9. GaAs Ronchi ruling with a 32 |tm pitch, a 16 pm grating fin gers, and an ITO backside AR coating. tion. The sample chuck was rotated at a rate of 20-25 rev/min in front of the target for better thin film uniformity. Finally, a 250 watt incident RF power with 0-2 Watt reflectance RF power was used during deposition. A plot of the diffraction efficiency as a function of incident angle with the same DOE is shown in Fig. 5-10. Notice that with the inclusion of a single AR coating the Fabry-Perot angular dependence effect is eliminated. The resulting device has minimal angular dependence as expected. The overall dif fraction efficiency for normal incidence operation increases compared with the non-coated data. Also, like before, the non-optimal etch depth is still an issue, accounting for the difference between the theoretical and experimental data as seen in Fig. 5-8. 177 0.30 S ' 0.25 C O O 0.20 ■ t m m 3= L U C °‘15 o ■ w m m 0.10 Experimental | 0.00 0 2 4 6 8 10 12 Incidence Angle (deg) Figure 5-10. Diffractive efficiency as a function of incident angle for the GaAs Ronchi ruiing with a 32 |_tm pitch, 16 pm grating fingers, and a backside AR coaling. A two-layer, AR coated SVDOE substrate with the same parameters shown in Fig. 4-17 was then designed. Each GaAs wafer used for SVDOE pro cessing contained twelve individual single layer Ronchi rulings. Each ruling on the same wafer was fabricated simultaneously using the equipment in the cleanroom. Although no detailed evaluation was performed, simple Dektak surface scans confirmed little sample-to-sample variation for the Ronchi rul ings on each wafer, due, in part, to the designed large feature sizes. This is important since, unlike the single layer Ronchi rulings just reported, we have little flexibility in re-using the same layers making up the SVDOE structures 178 after bonding. Hence, we have to compares similar, but not exact SVDOE devices. The design for our AR-coated SVDOE is shown in Fig. 4-17. For this case, the AR coating is placed on all surfaces. After bonding using the same processing technique listed in Chapter Four, the sample is placed in the mea surement setup. Figure 5-11 plots the diffraction efficiency as a function of the SVDOE 0.6 > O 0.5 £ O O 0.4 £ uu £ o Experimental 0.2 it= ■ M D Theoretical o.o 0 5 10 15 20 Incidence Angle (deg) Figure 5-11. Expected optical “picket-fence” diffraction pattern for a two-layer SVDOE structure. angular rotation. We finally observe the expected optical “picket fence.” This data shape was theoretically predicted in earlier publications (Nordin, 1993) and similar to earlier fabricated SVDOE structures constructed using a differ 179 ent integration technique (Chambers, 1999). Hence, we confirm that Fresnel reflection at each interface between SVDOE layers is responsible for the observed variations in the diffraction efficiency. 5.6 A dditional ITO Benefits There are a number of additional benefits that accrue when integrating this ITO thin film into the PMCM design. This film, when configured as an AR coating, has good angular insensitivity characteristics. In addition, this coating has wide-bandpass transmission properties, including visible and near-IR wavelengths. As the PMCM design evolves, a multi wavelength optical inter connection scheme might be employed to allow for higher signal bandwidth between adjacent silicon layers. A single ITO coating could support this design. The non-optical properties of this ITO film also have a number of bene fits. The film could be used for various equipotential biasing and/or common electrical ground applications. In this case, we are solely exploiting the electri cally conductive properties of this film. The ITO layer can also act as a barrier metal to inhibit indium migration in bulk Si or GaAs. Finally, from a design standpoint, this film is very robust, easy to opti mize, easy to fabricate, and has relatively stable properties over time. 180 5.7 Conclusion This chapter detailed a study on the solution to the potential deleterious effects of multiple reflections on the integrity of the dense fan-out/fan-in opti cal interconnections and SVDOE structures. Having previously characterized that multiple reflections can in fact pose a severe problem, a novel ITO-based antireflection (AR) coating was designed and fabricated for application on the layers in the photonic multichip module. This section also detailed the fabrication, material parameters, and the performance of ITO coatings on high-index substrates. Starting with a simple surface profilometer and ending with a Cary-Varian spectrophotometer an ITO thin film model is built up to help re-optimize the AR coatings using an optical software modelling program, TFCalc. After optimization, these AR coatings were shown to have excellent optical properties for potential integration in our PMCM. We started by considering the use of the films in relation to the total opti cal power budget available for our PMCM. Starting with the optical power available in our vertical cavity surface emitting lasers and ending with respon- sivity in our optical power detectors, we traced the optical fields and associated optical powers as we passed through multiple surfaces in the AR coated PMCM stack. In this way we showed that for successful PMCM operations an AR coating is necessary due to the limited power output of the available VCSEL array and the low silicon photodetector responsivity. 181 We demonstrate not only an increase in optical throughput but an elimi nation of the unwanted CGH rotational effect that was investigated in the previ ous chapter. This effect, if not markedly reduced, would have placed extremely stringent alignment issues during the PMCM packaging. The use of AR coatings on SVDOEs are then discussed. Only with an AR coating does the familiar, and expected, "picket fence” effect for the dif fracted order of a two-layer SVDOE structure occur. This effect is investi gated. Finally, we discuss additional advantages that accrue using this ITO coating in our PMDM. Both the optical and electrical properties of this thin film make it an attractive candidate for use in the PMCM system. 5.8 References K. Ananthanarayanan, "3-D Hybrid Electronic/Photonic Multichip Modules,” Ph.D. Thesis, University of Southern California, (2003). K. Ananthanarayanan, C. H. Chen, S. DeMars, A. A. Goldstein, C. C. Huang, D. Su,C. B. Kuznia,C. Kyriakakis, Z . Karim, B. K. Jenkins, A. A. Sawchuk, and A. R. Tanguay, Jr., "Multilayer Electronic/Photonic Multichip Modules with Vertical Optical Interconnections,” in OS A Annual Meeting Technical Digest Series, ILS/XI Program, (Optical Society of America, Washington, D.C.), Vol. 10, p. 150.(1995). M. Bender, W. Seelig, C. Daube, H. Frankenberger, B. Ocker, and J. Stollenwerk, "Dependence of oxygen flow on optical and electrical properties 182 of DC-magnetron sputtered ITO films.” Thin Solid Films, 325, pp. 72-77, (1998). M. Buchanan. J. B. Webb, and D. F. Williams, “The Influence of Target Oxidation and Growth Related Effects on the Electrical Properties of Reactively Sputtered Films of Tin-Doped Indium Oxide,” Thin Solid Films, 80, pp. 373-382,(1981). J. C. C. Fan, F, J. Bachner and G. H. Foley, “Effect of Oxygen Partial Pressure During Deposition on Properties of R. F. Sputtered Sn-Doped In2 0 3 Films.” Applied Physics Letters. 31(1 1 ), pp. 773-775, (1977). Hecht, Eugene, Optics, 2nd Ed, Addison Wesley, (1987). P. Nath and R. F. Bunshah, “Preparation of InnOg and Tin-Doped ImO^ Films by a Novel Activated Reactive Evaporation Technique,” Thin Solid Films, 69, pp. 63-68, (1980). G. Nordin, “Volume Diffraction Phenomena for Photonic Neural Network Implementations and Stratified Volume Holographic Optical Elements,” Ph.D. Thesis, University of Southern California, (1992). D. H, Raguin, S. Norton, and G. M. Morris, “Subwavelength Structured Surfaces and Their Applications, in Diffractive and Miniaturized Optics, Sing Lee, Ed., Critical Review Vol. CR49, pp. 234-261. SPIE Optical Eng. Press, Bellingham, WA. (1993). E. Pawlowski, H. Engel, M. Fersti. W. Furst, and B. Kuhlow, “Diffractive Microlenses with Antireflection Coatings Fabricated by Thin Film Deposition,” Opt. Eng.. 33 (2), 647-652. (1994a). 183 E. Pawlowski and B. Kuhlow, "Antireflection Coated Diffractive Optical Elements Fabricated bv Thin Film Deposition," Opt. Ens., 33 (11), 3537-3546. (1994b). Z Karim, "Thin film photonic device coatings for optical information processing and computing applications," Thesis, University of Southern California, September (1993). R. A. Synowicki, “Spectroscopic Ellipsometry Characterization of Indium Tin Oxide Film Microstructures and Optical Constants," Thin Solid Films, 313-314, pp. 394-397, (1998). A. R. Tanguay. Jr.. B. K. Jenkins, C. von der Malsburg, B. Mel, G. Holt, J. O'Brien. I. Biederman. A. Madhukar, P. Nasiatka, and Y. Huang, “Vertically Integrated Photonic Multichip Module Architecture for Vision Applications", Proceedings of the International Conference on Optics in Computing (OC 2000), Quebec City. Canada, pp. 1-17, June 18-23, (2000). Vassallo, C.. “Antireflection coatings for optical semiconductor amplifiers: justification of a heuristic analysis," Electronics Letters, Volume: 24 Issue: 1, pp. 62 -64, Jan (1998). 184 Chapter 6 Flip Chip Integration of PMCM 6.1 Introduction Flip-chip bonding is an advanced packaging technique in which either similar or dissimilar dice are mated face-to-face using electrically conductive bumps that are fabricated on either one or both of the die. Developed in the late 1960s, flip-chip bonding was initially utilized by IBM as a reliable bonding technology for their electronic Solid Logic Transistor products [Golman, 1969]. In the past 20 years this technology has also been applied to photonics packaging applications as a means to electrically and mechanically hybridize silicon integrated circuits (ICs) with non-silicon photonic devices. In this way the flexibility and performance of silicon VLSI circuits can be used for the con trol of photonic devices based on non-silicon substrates, such as III-V and II-VI compound semiconductor materials including vertical-cavity sur face-emitting lasers (VCSELs) [Krishnamoorthy et. a l 2000: Kuznia et. al., 2001], multiple quantum well (MQW) spatial light modulators (SLMs) [Ayliffe et. al.. 2001: Lentine et. al.. 1996], infrared (IR) focal plane detector arrays 185 [Goossen et. al., 1998; Pouliquen et. al., 2000; Cohen et. al., 1999; Merken et. al., 2002], and real time x-ray detectors [Irsigler et. al., 1998; Fischer et. al., 1999]. Typically the electrical contacts between mated substrates are bumps composed of either solder, gold, nickel, indium, or polymer bumps. Indium bumps have been reported for use with IR focal plane arrays [Cohen et.al, 1999; Merken et. al., 2002], 3-D silicon IC chip integration [Williams et. al., 1993], and MEMS devices [Singh et.al.. 1999]. Here a novel flip-chip bonding technique is described that relies on a uniquely fabricated indium electrical contact bump that we refer to as a "vel cro” bump due to the unusual surface morphology based on previous w'ork [Karim, 1993; Ananthanarayanan, 2003]. When properly fabricated, the indium bump contact surface allows for room temperature cold-weld bonding without any extensive contact pad or pre-bonding surface preparation. Devices bonded using this technique include a number of test structures for device con tact characterization, multiple quantum well (MQW) spatial light modulators (SLM). high speed, cryogenic crossbar switches for advanced data routing, and real time X-ray detectors, all of which will be discussed in later sections. Typically two indium bumps are needed to form an electrical contact by- flip-chip bonding, one for each surface to be bonded, but by further refinement of our bonding technique a novel, single-sided bump bonding technique is demonstrated, further simplifying the device integration processing. This tech nique has been used for the bonding of both one- and two-dimensional laser arrays with passive silicon mounting substrates and is the focus of my work. 186 Section 6.2 starts by introducing indium and its unique properties. This section also discusses the development of our indium bump bonding technique including our early experiments and how these led to the optimized, “velcro” bump profile. Section 6.3 discusses the fabrication requirements for the opti mized bump profile and the various deposition parameters that affect its perfor mance. The electrical and mechanical performance for double-sided indium bumped structures is discussed in Section 6.4 including electrical contact mea surements and pull-test results. An in-depth discussion of various devices bounded using double-sided bonding is presented in Section 6.5. Section 6 . 6 introduces the impetus for single-sided indium bump bonding and how our bump bonding technology can be altered to accommodate this change. The electrical contact resistance measurements for single sided bonding is dis cussed in Section 6.7 followed by several examples of this bonding including a hybrid integration of a 1-D laser array and a 2-D vertical-cavity surface-emit ting laser (VCSEL) array in Section 6 .8 . The use of single sided indium bond ing for the integration of passive optical devices including the design of a photonic multichip module (PMCM) enabled using our bonding technology is presented in Section 6.9 and conclusions are drawn in Section 6.10. 6.2 Indium Bump Evolution The use of pure indium as the electrical contact bumps in our flip-chip attachment process is desirable for the hybrid integration of photonic devices for a number of reasons. 187 (a) Indium is highly ductile and malleable even at room temperature, thereby allowing the use of a cold-weld, compression only bonding process. Unlike gold or silver alloys that have high tensile strengths, indium does not require any application of heat during the flip-chip attachment process. Many photonics devices dis cussed in this paper are temperature sensitive and could be affected by an elevated bonding processing temperature. (b) Both the strain hardening and work hardening properties of indium are excellent, resulting in bumps that can absorb the stress due to thermal coefficient of expansion (CTE) mismatch between differ ent substrate materials. This effect will be especially important when the devices have to be cooled down to cryogenic tempera tures in order to enhance their performance such as in the testing of one of our hybridized devices. (c) Indium has good thermal conductivity and electrical properties as seen in Table 6 -1. (d) The viscoelastic/wetting properties of pure indium are good on both metallic and dielectric surfaces. Therefore, our deposited indium bumps can form a good physical/chemical bond with the underly ing material or substrate. This is also useful since we can deposit 188 indium directly atop our bonding pads without the need for elabo rate intermetallic interfacial layers. Melting Point 429.76 K Thermal Conductivity .837 W/cm-K Density 7.30 g/cm ■ Electrical Resistivity] 8.4 pQ-cm Tensile Strength 1. 6 MPa (at 295 K) 31.9 (at 4 K) Bulk Modulus 35.3 GPa Tensile Modulus 10.6 GPa Table 6-1. Properties of bulk Indium Zapella described some of the first applications of indium bumps, in this case for use in packaging of various IR focal plane arrays. The bumps had a rel atively flat indium bump surface morphology. From an optical component inte gration effort, precisely uniform arrays of identical bumps with perfectly fiat top surfaces for bonding seems to be ideal due to the stringent optical toler- 189 anccs needed in many optical components with a fine dimensional pitch between adjacent bond pads. This was the original path chosen for the integra tion of our multiple quantum well (MQW) spatial light modulators with silicon mating substrates. An example of one of our early, non-“velcro”-like bumps L- 5E1- EHI* 10,0 RU HD* 13 ™t 10. 0 ( 1 ( 1 1 t- .. Indium biunp nn I*i usin g 101) center tnuuR F i g u r e 6 - 1 . SEM photomicrograph o f the non-‘‘Velcro-” like indium bump for use with integrating multiple quantum w ell spatial light modulators. These bumps caused significant de-bonding prob lems. that were fabricated in our lab is shown in Fig. 6-1. These bumps were used in a room temperature, compression only flip-chip bonding of a number of test substrates. These test substrates were suc cessfully bonded with both bonded substrates parallel to each other with a uni- 190 form gap over the entire bonding area. However, problems occurred almost immediately. The hybridized devices often de-bonded after only 30-60 minutes after bonding and, prior to this occurring, the electrical contact resistance mea surements showed large contact resistance values. The culprit in both cases was the formation of an impenetrable thin layer (approx. 50-100 A) of native indium oxide. This unwanted layer of indium oxide could be minimized using a num ber of processing techniques. The thickness of this layer could be reduced (though not completely eliminated) by performing a quick chemical wet etch in a solution of either a dilute nitric or bromidic acid prior to bonding. But in order to completely inhibit the formation of the indium oxide layer, a cap layer of a non-oxidizing metal him would have to be evaporated on the surface of the indium prior to exposing the bumps to air. If both films are deposited while under vacuum conditions and prior to vacuum chamber evacuation, no indium would be exposed to the atmosphere, hence no native oxide layer. It is also conceivable that instead of room temperature bonding, indium reflow bonding can be used during the bonding procedure as is done by the commercial com pany Sofradir in France. Instead of these methods, all of which add additional processing steps to our hybridization efforts, we chose instead to alter to the surface morphology of our bumps to overcome the issues of the unwanted native oxide layer. The unusual surface morphology of our “velcro” bumps is shown in the SEM micrographs of Fig. 6-2. This novel technology base yields indium con 191 tact bumps with large surface areas and a high degree of corrugation, thus assisting not only in the adhesion strength of the bonded sample, but also in penetrating through the native oxide layer during the cold weld bonding proce dure. As opposed to other methods of forming bumps (such as electroplating or solder dipping with the use of flux), the evaporation method gives far greater l* SE l E H f- 10.0 W U D - to m n 20. O h m I - ------------- Thermal euap.3a; • 4 ? ■?"* . . . . * < . ... • '.T ... '* H .‘ Figure 6-2 . “Velcro” indium bump prior to flip-chip bonding. N otice the indium grain distribution and the overall surface mor phology that significantly reduces the effects o f the native indium oxide layer during the flip-chip bonding attachment process. compositional uniformity, purity of the bump, and control of the bump profile height uniformity, thereby enhancing the bump interconnection characteristics. The large surface area and height variation of the indium bump surface is obtained from a combination of the fast thermal evaporation rate used in con 192 junction with the low migration rate of the deposited species on the surface of the substrate. The low migration rate is a function of the large density of indium atoms (7.31 g/cm ) and the low temperature of the substrate surface (near room temperature) resulting from the use of a water cooled substrate stage and a large throw between the evaporation source and substrate holder. The indium bump surface shows a large surface modulation that is resembles “Velcro”. 6.3 Indium Bump Fabrication The formation of discrete indium bumps is formed by a semiconductor photoresist processing lift-off technique of a thick indium film as shown sche matically in Fig. 6-3. Since the film thickness is dependent on the desired bump height, a two-layer thick photoresist of positive-tone Clariant P4620 with a blanket exposure of the first layer followed by a pattern exposure of the sec ond layer is similar to an approach developed by Rockwell [Zappella et. al., 1992; Zappella et. al., 1989]. The same multilayer photoresist flood exposure lift-off procedure is also used for other photonic applications [Heremans et. al., 1997]. A dark-field photolithographic mask was used for defining regions in the two-layer thick photoresist where individual indium bumps are to be formed. After photoresist development the regions where indium bumps will be formed are the regions of removed photoresist on the substrate as seen in Fig. 6-3. Finally, after a uniform layer of thermally evaporated indium is deposited, the entire photoresist layer is dissolved into a bath of acetone by 193 Subi^r ; j1 < j First layer of 4620 photoresist spun I ^ i ^ ^ U V I .C J M 1 S ubslfr-ifo Uniform exposure of photoresist layer Substfaici | Second layer of 4620 photoresist applied I t y ^ y y y y U V liijh ! Photomask Photolithographic patterning n Development of photoresist. Undercut profile Indium film deposition n —o — a—□ —a------ Indium film lift-off F i g u r e 6 - 3 . Sem iconductor processing steps for the formation o f discrete indium bumps by utilizing a m ultilayer photoresist flood exposure lift-off process. 194 soaking for a period of 24 hours, leaving only the discrete bumps of indium on the exposed via holes in the photoresist. The layer of indium was deposited onto the sample via thermal evapora tion in a high vacuum environment using a dedicated Varian 3120 vacuum dep osition system. The Varian system used two pumps for high vacuum production, a mechanical roughing pump and a diffusion pump that can pro- o duced an ultimate vacuum of about 1 x 10 Torr. The Varian chamber had a long “throw” or the separati.^ distance from the source to the substrates of about 2.5 ft. which enabled a uniform deposition thickness of our “velcro” indium layer and further prevented excessive heating of the substrates due to radiation of heat from the molten indium in the evaporation boat. The chamber was also equipped with a quartz thickness monitor for in-situ monitoring of the deposition rate that was calibrated for indium evapo ration. For thermal evaporation, half-inch thick oxygen-free high purity copper bus bars and high current 4/0 welding cables were used to connect the power supply to the thermal boat (in order to reduce the series resistance). A 20 cc folded alumina-coated thermal boat with an 8 cm^ capacity was used in con junction with a 4 kVA low voltage power supply from R. D. Mathis & Com pany. Pure indium (six nines purity, either in the form of pellets/slugs or in bar form) was used as the initial charge. After the chamber was pumped down using the mechanical roughing pump and the diffusion pump, the indium 195 charge was pre-melted using a supply voltage of approximately 0.5 V and 175 A (AC current) for a period of five to seven minutes. A designed-for, consistent 15-20 A/sec deposition rate measured on an Inficon XTC/2 deposition meter was obtained at a deposition pressure of 5 x 10" 8 torr, a current of 300 A, and a voltage of 1 volt applied to the thermal boat by the power supply. This fast deposition rate significantly contributes to the ‘'velcro” effect seen atop our indium bumps. The thickness of the deposited indium was measured using a quartz thickness monitor that was calibrated for the geometry of the evaporation chamber and the material properties of indium. A hand-held silicon-con- trolled-rectifier (SCR) controller was used to manually control the current and voltage parameters from the power supply to the thermal source used during deposition. After the required thickness of indium was deposited on the sub strates, the chamber was allowed to cool for 3-4 hours and the indium-bumped substrates were kept under vacuum to prevent excessive oxidation. The cham ber was vented using dry nitrogen when the samples were ready for further pro cessing and bonding. Typical surface variation for a 7.5 pm high bump is 2 pm peak-to-peak. After the lift-off process and the subsequent wafer cutting to yield indi vidual indium bumped die, the opposing dice were then mated together at room temperature using only force/pressure as the bonding parameter variable with a RD Automation M 8 -A Flip-Chip aligner/bonder. The bumps were not reflowed or heated above the melting point of the metal as is customary in most 196 flip-chip attach processes using solder bumps. Furthermore, since our approach does not use reflowed bumps no additional pad metallurgy processing steps to form a ‘'solder wettable” under-bump-metal (UBM) are necessary. The method of defining the indium bump and its overall size and height is of concern as the bump size can limit the packaging density. Indium bumps of various sizes from as small as 8 x 8 |im to as large as 250 jam x 4 mm in dimension have been deposited with bump heights of between 6 (am to 24 jam. 6.4 Electrical Performance The first device integrated with our “velcro” bump bonding technology was a simple double-sided daisy chain structure as seen in Fig. 6-4. This daisy chain structure is composed of a 3 cm by 1 cm “base” or “bottom” chip and a smaller 1 cm by 1 cm “top” chip. A 40 x 40 array of isolated gold or aluminum electrodes in the middle of the base chip is physically aligned with the top chip’s correspondingly patterned aluminum or gold electrodes using a flip-chip bonder. After the top and bottom chips have been bonded together, a 40 x 40 array of top-to-bottom electrodes results, interconnecting the two chips electri cally and providing many test electrical patterns that include from 2 to 40 indium bumps in each independently accessible pattern. This allows for a number of tests to be performed, ranging from basic electrical continuity to measurement of the indium bump connection impedance as a function of fre quency over the range of interest. Discrete bump formation for both “top” and “bottom” substrates are similar. 197 Top S u b strate • • • • Indium B um ps 0 0 0 0 Bottom S u b strate Electrical C ontact T est Pad F igure 6-4. Exploded schem atic diagram o f the daisy chain structure used for electri cal and m echanical characterization. Shown is a single 1 x 40 array o f bumps between the "top" and "bottom’' substrate. The indium bumps used for this demonstration had dimensions of 35 pm x 35 pm x 7.5 pm high. A bonding pressure of 4 grams/bump yielded a total bonding pressure of 6400 grams (40 x 40 array of bumps) on the RD Automa tion M 8 -A Flip Chip aligner/bonder. A total tack time (time the bonding pres sure is maintained), was 40 seconds and done at room temperature as indicated earlier. No epoxy underfill or flip-chip encapsulate was used for any device bonding reported in this paper. 198 Using 35 //m x 35 }im x 7.5 ;/m high indium bumps, daisy-chained through a total of 40 flip-chip bonded bumps, the electrical contact resistance measured using a Hewlett Packard 3860 high precision meter with a two point probe was 300 mQ/bump. Previously reported results range from 4 Q. [Will iams et. al., 1993], to 1 Q [Matsui et. al.. 1993], to 1.5 mQ [Singh et. al., 1999] per bump. Such widely ranging values may depend on bump size, the experi mental setup, and measurement technique. The resistance values reported can be influenced by a number of factors including the type and thickness of metal lization used for the pads and the daisy-chain connections (i.e, Al or Au), the contact and measurement method (two- or four-point probe), whether the resis tance was measured on un-bonded or mated indium bump parts, and last but not least, the age (since indium forms a natural oxide layer on the surface) and surface morphology of the bumps. No pre-bumping indium surface cleaning was implemented for any of our devices. It is sometimes customary to briefly dip the to-be-bonded parts in a dilute solution of nitric bromide acid prior to bonding to remove the unwanted indium oxide layer. No pre-bumping surface cleaning wr as used for our devices, as the designed-for surface morphology of our “velcro” bumps is solely responsible for breaking the oxide layer upon bonding. As opposed to other methods of forming bumps (such as electroplating or solder dipping with the use of flux), the thermal evaporation method gives far greater compositional uniformity and purity of the bump as well as control of the bump profile and height uniformity, thereby enhancing the bump inter 199 connection characteristics. This is borne out by mechanical test data that was obtained for the pure indium bumps that were deposited using thermal evapora tion that has been previously reported [Anantahnanan, 2002]. The ultimate tensile strength measurements of the USC-deposited indium bumps were per formed at TRW, Inc. showed the ultimate tensile strength of the USC-deposited indium bumps to be as high as 139.6 Kg/cm**, when the theoretical ultimate tensile strength quoted for bulk single crystalline indium was 16.32 Kg/cm1 ' {Indium Corporation of America). This high value is attributable to various fac tors. including the greatly enhanced surface area of the bumps (for a given foot print of the bump pad), grain boundary effect that help to augment the tensile strengths (as they do not permit easy slip or glide of dislocations in the material during deformation as seen in Fig. 6 -6 ), and to the large plastic deformations that take place during the cold weld bonding procedure and may therefore help in work hardening the indium material. Additional detail are covered else where [Ananthanarayanan, 2003]. 6.5 Fabricated Devices using Double Sided Bonding Devices using double sided bump bonding include the aforementioned test structures for electrical and mechanical characterization, multiple quantum well modulators for use as spatial light modulators (SLM), infrared focal plane arrays, high-speed cryogenic crossbar switches, and real-time x-ray sensors. A desired feature of any SLM is the possible integration of the control electronics and the photonic functions on a single device. A fully integrated, 200 Figure 6-5. SEM micrograph o f the top corrugated sur face of a “velcro” bump. monolithic device containing both modulator and electronics has been difficult to achieve. An alternative presented here is to utilize “velcro” indium bonding for the integration of a silicon driver/detector chip to a direct band-gap AlGaAs/GaAs MQW structure. The modulator is based on an asymmetric Fabry-Perot etalon with a multiple quantum well structure as the electroabsorb ing cavity medium utilizing the quantum confined Stark effect (QCSE) as the modulation mechanism. Additional information of this device can be obtained elsewhere [Kezhong et. al., 1991; Karim, 1993]. A third device using our “velcro” double sided bonding technology is a high-speed cross-bar switch implemented using Josephson Junction device 201 * > .« > . i ^ J V^^.'O !T<fcMO i i * « ’•» V lU 'rtiV - ' • C * ! $ # $ # » * ■ - < - * ' . ! * * i ! * a » y - j : > q g p M M U U l r f 3ft r*V - ‘■<.~~'-Tfflf*rTIQtwju^lfrfgliW.CSiJ'F^,1 ^ : W W BM - ^ < V U = K E G ^ M S K » f.y i5 "fM w a w n rjSW ^ r r . * gX E .' 1 Z £XUmztZ*Sf M 1'H'flW H ,W - ' & * V ia iW M n c ^ . ^ « sii« n w w ri^ ^ jc i^ a a 5 u - r v ^^M aa-sseyasy j as? j« a a fcissrw»sr^->---••# w s n u s tf c f tg r «** M » . V S f - ; . x u f . i u; 7.*»i;vA^*W*«»«irRWRW£J»**tt jfrlff * II-‘ *g 1 ^ '« * * ^ * '* K » 5 C S ! '; j,j r —’■•'■■•Jr $ * z A * - ,“ -r i *\■ ;* ^ ■ • ’r'-j”^ r - " ; ^ j > :.t . : » / ^ v + s . j r'“ ; - ; r ^ " : r “r< r’' ' . ^ :’: ' ‘^ ^ '- i: s r ^ ',’ f3.,' -v “ '~:'‘" ^ ‘‘eJ ~ , - - < \ — - ? ■ - > ‘ - - * - i * , 'iv * '-.^ • v .-^ * V :., . . , ■ I L . 1 -* - ' 'il-^ ... ■ » ■ - j~V- * - . " * 1 F igure 6-6. Indium bumped SEM micrograph o f X-ray detector elem ents contain ing indium bumps prior to silicon hybridization. technology, and is based on the physical phenomena of superconductivity and electron tunneling. These devices have potential advantages over room tem perature semiconductor technologies in two predominant areas, namely very fast switching speed (~10 ps) and low power dissipation (-1 mW) [Lahiri et. al., 19821. However, there is a strong need for a sophisticated packaging tech niques in order to fully utilize the advantages of this technology in digital corn- 202 puting and communications applications. The packaging technology should allow for the electrical characteristics of the package to be compatible with the fast rise times of signals generated by the devices, and should provide for a minimum delay between chips in an MCM packaging scheme. In addition, the package should allow for modularity and the complex I/O requirements of the MCM architecture. The architecture of the superconducting cross-bar system consists of superconductive electronics (enclosed in a vacuum chamber and insulated from room temperature) having arrays of memories and processors integrated into a Superconducting Multi-Chip Module (SMCM) that is cooled to liquid helium temperature (4.2° K) using a specially designed cold head. The 128 x 128 crossbar is realized by using a 4 x 4 array of ’’switch” chips and 4 "glue” logic chips, for a total of 20 chips that are double sided flip chip bonded onto a 4” sil icon substrate. The switch and glue logic chips were implemented using Josephson junction technology designed by TRW, and fabricated by Hypres, Inc., New York, USA. Indium bump/bonding has also recently been utilized in the fabrication of real-time backside illuminated X-ray bio-medical detectors by hybridizing Cadmium Zinc Telluride (CdZnTe) detectors to Si CMOS readout chips. The X-ray sensors have been targeted for use in dental imaging and mammography applications providing real-time images with a much lower required X-ray dos age than film but with the same or superior resolution to film-based images. Digital X-ray images provide further advantages since they can be easily stored 203 and retrieved, transported by electronic means, and they allow for the use of image enhancement techniques [Spartiotis et. al., 1997; Spartiotis et. al., 1998]. Single die CZT X-ray detectors with arrays of 140,000 pixels were fabri cated using indium bumps fabricated by this author of size 1 2 jam diameter, 8 pm height on a 25 pm pitch as seen in Fig. 6 -6 . Indium bumps were fabricated on both single die CZT (on Au-metallized pixel pads) and on 4" CMOS readout chip wafers (with Al-metallized bond pads). The 4" wafers were subsequently diced and successfully llip-chip bonded to CZT using a pressure of 1-2 grams/bump. Due to the fragility and the thermal coefficient of expansion mis match between CZT and Si, indium bumps are favored for this application since their ductility allows for effective relief of stress resulting from thermal cycling. The "velcro" bumps are especially suited for this application because they reduce the required bonding pressure per bump. 6.6 Single Sided Bonding The next group of experiments tested the feasibility of employing sin gle-sided bump contacts using thermally evaporated indium bumps instead of the more traditional two-sided bumped structure. This unusual approach was dictated by our desire to use a more commercially viable bump bond technique for control, DSP, microprocessor, and DRAM chips in system-level implemen tations, as well as ASICs designed and fabricated by foundry services such as MOSIS. Often, such commercially available chips are available only as single 204 die and not in wafer form, making indium bumping of each individual die an expensive proposition. Integrated circuits are almost never released to custom ers in wafer form, as the easily obtainable wafer yield is considered highly pro prietary. A further complication with dual-bump structures is that often one or both substrates have usual surface topologies requiring planarization tech niques before photoresist processing can commence. The transition from double-sided bump bonding to single-sided bump bonding requires changes to the indium deposition processing and mechanical mating using the flip-chip bonder. Since only one surface is responsible for indium oxide breakage, an increase in the surface roughness of individual indium bumps is desired. This is accomplished by increasing the indium ther mal deposition rate from 15 A/sec to 30-35 A/sec, resulting in increased sur face roughness. In order to make better contact between the underlying, metallic indium and the contact pad metal, the bonding pressure is increased by over 50%, from 4 grams/bond to 6 - 8 grams/bond for the 35 pm x 35 pm bump. Since indium bumps are now bonded to unbumped metal contact pads and not to each other, greater surface preparation is now required. This manifests itself in a more comprehensive reactive ion etching (RIE) clean of all metal contact pads right before flip chip bonding. Finally, the last parameter that was changed used shorter times between indium deposition/lift-off and the actual flip-chip bonding. This limits the amount unwanted indium oxide growth atop the indium bumps. 205 6.7 Performance of Single Sided Bonding Using the same test substrate as was used for double sided bumping (as shown in Fig. 6-4, a set of 35 pm x 35 pm x 7.5 pm high indium bumps on only one substrate were deposited. After contact pad cleaning via RIE a contact pressure of 9600 grams was applied to mate the two substrates. The indium bump contact resistance was measured at 480 mQ/bump using a Hewlett Pack ard 3860 high precision meter measuring the resistance through 40 bumps with a two-point probe. This represents a slight increase in bump contact resistance from the double-sided bump bonding results probably due to less breakage of the indium oxide layer since only one side is responsible for the breakage. 6.8 Fabricated Devices using Single Sided Bonding The first demonstration of single-sided “velcro” indium bump bonding for photonic devices was a one-dimensional, 980 nm edge emitting laser array. For this device 22 lasers are arranged on a 4 mm by 12 mm substrate. The p-contact is atop the mesa structure and has dimensions of 4 mm by 80 pm. A distance of 500 pm separates each laser. The designed-for mating substrate is a passive, silicon substrate. This substrate has dimensions of 2 cm by 1 cm in size and contains a thin film deposited, 2 0 , 0 0 0 A layer of SiOx, electrical trace lines composed of a 2 0 0 A bottom layer of Cr for substrate surface adhesion, and 3000 A layer of Au for signal lines. Only the Si mating substrate was pro cessed for indium bumps since the photoresist processing needed for indium bumps on the edge emitting laser would be difficult due to the highly non-pla- 206 nar mesa profile as well as the unusual size and aspect ratio of the laser array that would not allow for a uniform spreading of a layer of photoresist. F igure 6-7. O ptical micrograph o f the hybridized 1-D laser array. The electrical sig nal lines are shown leading to the 1-D array on the bottom edge o f the picture. Due to the long length of the metal pads for the p-contact it was decided to fabricate six 50 pm by 50 pm indium bumps on the Si mating substrate prior to bonding. The total bonding pressure was 6500 grams for the entire device. This deviates from the designated bonding pressure but was done in order to guarantee that the bonding was successful. An optical micrograph of the bonded device is shown in Fig. 6-7. Electrical and optical characterization measurements are shown in Fig. 6 - 8 (a) for the pre-bonded and (b) post bonded 207 1 0 k . < L > o C L S a. = 7 o H O 60 80 TOO 1 2 0 140 0 40 Input Current (mAmps) 1 0 I— a. a. 0 20 40 60 80 100 120 140 Input Current (mAmps) F igure 6-8. Optical power as a function o f input electrical current for pre-bonded (top figure) and post-bonded array (bottom figure). laser devices. As expected the optical intensity as a function of drive current is unchanged. A graph of the voltage as a function of current is seen in Fig. 6-9. 208 3.0 :er bonding 2.5 Before bonding to 2,0 O > > 0 20 40 60 80 1 0 0 1 2 0 140 Input Current (mAmps) F igure 6 -9. Plot o f the laser input voltage as a function o f input current pre- and post-bonding. In this case the increase in total electrical resistance of the hybridized device can be determined by calculating the difference in slopes of the two measure ment traces. For this sample the increase is 8 ohms that corresponds almost entirely to the gold trace lines on the silicon substrate. A more challenging packaging demonstration was performed with a low threshold bottom emitting, 8 x 8 VCSEL as seen in Fig. 6-10. D. Dapkus and J. O ’Brien at the University of Southern California fabricated the VCSEL array. Since both n- and p-contacts are located on the same side of the laser array, and 209 Acc.V ' S pot Magn WD I — : — —— — H 10 pm 15.0 kV 2.1 2000X 1 21.1 tf5617_0703_______- F igure 6 -10. SEM micrograph o f a U SC designed and fabricated low -threshold V CSEL illustrating the surface topology. as the surface topology ideally requires a planarization step if a double-sided indium bump bonding approach is used making this device an ideal candidate for single-sided bumping. Indium bumps 8.0 pm high were deposited atop a 1- by 1- inch passive Si substrate as seen in Fig. 6-11 with a predefined elec trode array configuration designed to precisely mate and provide electrical driving signals to the p- contact of the low-threshold VCSEL. Thirty-six (36) additional indium bumps where deposited outside the array to provide electri cal contacts to the n- contact of the VCSEL. A bonding pressure of 550 grams was used to mate the two substrates together. An optical micrograph of the 210 Figure 6 -1 1 . SEM micrograph of silicon mating substrate with thermally depos ited indium bumps. completed device including one of the functioning lasers is shown in Fig. 6-12. . A plot of the optical intensity for an individual laser as a function of input electrical driving current is shown in Fig. 6-13. 6.9 Passive Device Integration A 3-D integrated electronic/photonic multichip module (PMCM) struc ture is composed of multiple layers of pixellated silicon VLSI chips that are m w st umm p m \ t + ^ « s = 3 5 K s * » s t s s s * s 8 a ! e s ^ ^ F i g u r e 6 - 1 2 . Optical micrograph show ing V CSEL flip-chip bonded to a Si mating substrate. One laser is shown in operation. densely interconnected by a combination of electronic, optical, and photonic devices to produce a high degree of fan-out and fan-in to each pixel or process ing node [D’Asaro et. al., 1993; Rolston et. al., 1996; Lentine et. al., 1994]. In our implementation, shown schematically in Fig. 6-14, a 2-D arrays of verti- cal-cavity surface emitting lasers are flip-chip-bonded on a pixel-by-p^xel basis to the silicon VLSI chips, which act as local detectors (from the previous layer), processors (either acting alone or in concert with electrical inputs from nearest and next-nearest neighbors within the plane), memory elements (prima rily in the analog domain) and VCSEL drivers. Proximity-coupled diffractive optical element (DOE) arrays fabricated atop either glass/quartz or GaAs sub strates, either combining refractive/diffractive elements or employing separate 212 2466646474 3.0 2.5 >. + - « 2.0 C 3 + ■ » 3 o 0.5 0.0 0 2 4 1 3 Input Current (mA) «- 0 -5 0.0 -0.5 jo 0 2 3 1 4 Inout Current (mA) F igure 6-13. Output optical power and change in optical power as a func tion o f input electrical driving current for the U SC designed, fabricated, and post-bonded VCSEL. N otice the Fabry-Perot effects caused by the G aAs high refractive index substrate. 213 Silicon GaAs Diffractive Optical Element Silicon Det. Elect, Det. Elect VCSEL VCSEL Elect Det. Elect. F i g u r e 6 - 1 4 . Schematic diagram o f multilayer hybrid electronic/photonic photonic multichip m odule, show ing two silicon VLSI chips optically inter connected by vertical cavity surface emitting laser (V C SEL) and diffractive optical elem ent arrays. Two adjacent pixels are shown in cross section. DOE’s and microlens arrays for focal power and weighted fan-out, establish interconnections that are modulated in intensity by each individual VCSEL and its associated Si driver circuit. The designed 3-D photonic multichip module architecture allows for massively parallel, high I/O interconnections between parallel layers of Si integrated circuits. Applications best suited to such a pho tonic approach would involve image processing, object recognition, data min ing/filtering and compression. 214 An electronic/photonic packaging technology that can be used with sili con, GaAs, and quartz/glass substrates is complex due to a variety of issues as was explored in earlier chapters in this thesis. In addition, both glass and quartz are difficult to bond using traditional solders. As a further test of our indium bump bonding technique we explored the use of these bumps for a chip-on-glass integration effort. Figure 6-15 shows an optical micrograph of a Figure 6-15. Photomicrograph of daisy chain structure fabricated with ITO trace lines atop quartz substrates. N ote the lettering under the quartz sub strates. daisy chain test substrate similar to the one shown in Fig. 6-4, but fabricated using a quartz substrate with indium tin oxide (ITO) signal/trace lines. Both 215 single and doubled sided bump bonds where fabricated on the ITO trace lines and were successfully bonded. 6.10 Additional Challenges with MOSIS IC Another outgrowth of the single sided flip-chip bonding experiments is the exploration of a technology base for the incorporation of Indium bump bonding with samples containing a previously applied zincation/electroplated treatment. The majority of flip-chip bonded substrates utilize electroplated lead-tin solder bumps which are then reflowed on specialized, mulitlayered, multi-metal bump bonding pads to form the solder contact balls. These solder balls are then reheated during actual flip-chip bonding, melting the solder again, to form the electrical contacts between mated substrates. The zincation process is used to simultaneous etch the native aluminum oxide layer on the aluminum contact pad while depositing a layer of oxide inhibiting zinc. This zinc layer is also the electroplating seed layer for all subsequent electroplating processes. We now seek to combine the room temperature, minimized bonding pad design, and high bonding strength attributes of the USC ‘velcro’ indium process with the more commercially accepted solder ball bumping. The below SEM micrograph is the first step of this process. In collabora tion with an electronics packaging/electroplating house, we have developed an electroplating process which artificially roughens the surface of the electro plated material, unlike nearly all electroplating processes. In this case, a zinca tion process is used to start the process, followed by an electroplated deposition 216 of 4 microns of Ni followed by a quick Au electroplated cap layer to prevent unwanted oxide buildup. Atop this substrate a 4-5 micron indium bump will be thermally evaporated. A key feature of this novel zincation process is that we intentionally detune the process in order to cause a premature surface rough ness. This step is necessary as the smaller than unusual 4-5 micron indium layer would not be rough enough to be considered “velcro”-like. Note that this work is still early and much needs to be developed for reliability. Figure 6-16. 35 pm by 35 pm zincation bump atop an aluminum bonding pad. 217 6.11 Single - Sided Indium Bump Strength Figure 6-17 shows the active region of a low-threshold VCSEL laser that Acc.V Spot Magn WD 15.0 kV 3.1' 120Qx 19.0 F igure 6-17. SEM micrograph o f GaAs V CSEL mesa em bedded in an indium bump, The V LSI substrate broke away from the silicon mating substrate after a 3 foot fall (destructive evaluation test). broke out during a destructive test evaluation. Although we are not claiming that the indium bump is stronger then bulk GaAs the figure does give an indica tion of the reliability of our bonding process. 218 6.12 Extension of Single Sided Bump Bonding Figure 6-18 is another indium bump technology we are exploring. - • f Figure 6-18. SEM micrograph o f indium strip retaining the “velcro”- like proper ties. In this case the desired bump has dimension of 65 p.m by 4 mm to mate with the /^-contact of the previously described 1-D laser array. Notice that the “velcro” top surface is still obtained for the very large indium bump contact. The larger “velcro” bump could potentially lead to lower electrical contact resistance and further assist in significant thermal load removal issues, an important consideration for all photonic/electrical hybridization. 219 6.13 Conclusion This article introduced the use of indium “velcro,” cold-weld double sided and single sided bump bonding. The designed-for, novel surface mor phology allows for simplified hybrid electronic/photonic device integration. Experiments involving double-sided bump-bonding show high reliability bonds with an excellent pull-test result of 139.6 Kg/cm , low electrical contact resistance of 300 m£2/bump (35 x 35 pm), and a simplified bond pad prepara tion allowing for easier device integration. Devices bonded using this technology base include a number of test structures for device contact characterization, multiple quantum well (MQW) spatial light modulators, high speed, cryogenic crossbar switches for advanced data routing, and real time X-ray detectors. Integration issues were the impetus for the creation of single-sided indium bump bonding, which is ideal for the integration of electronic/photonic devices with uneven surface profiles, or for devices unusually shaped or sized. Even with a slight increase in electrical contact resistance (480 mO/bump (35 x 35 pm)) this technology base allowed for the easy integration of commercially available, or custom ASIC IC with photonic devices. This was demonstrated by bonding two very different lasers arrays. In the first case we demonstrated the hybrid integration of a one-dimensional laser array to a single sided bumped passive silicon substrate. Next, a low threshold, two-dimensional VCSEL laser arrays was mated. 220 This technology base will eventually allow for the complete integration of our photonic multichip modules. This large-scale hybridized device consists of stacked arrays of silicon VLSI substrates, GaAs laser substrates, and associ ated optical layers between the VLSI/GaAs substrates to support a dense fan-in/fan-out interconnection. 6.14 Reference Ayliffe, M.H. Rolston, D.R. Chuah, A.E.L. Bernier, E. Michael, F.S.J. Kabal, D. Kirk, A.G. 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SPIE on Materials, Techniques and Applications for Z-Plane Focal Plane Array Technology, 1097, pp. 117-125,(1989). 226 Chapter 7 PMCM Integration Efforts 7.1 Introduction The previous thesis chapters described individual technologies incorpo rated in the photonic multichip modules including diffractive optical elements configured as computer generated holograms and stratified volume diffractive optical elements, optical thin films for increased PMCM performance, and double- and single-sided flip-chip bonding. In this section, we consolidate these technologies and take the first steps towards the construction of an inte grated PMCM device. We start be reviewing the properties of the PMCM’s VLSI computa tional layer. As configured, the analog VLSI integrated circuit (IC) chip is designed to emulate an array of biological neurons. These individual neu ron-like elements are configured as discrete smart pixels on the IC with each pixel providing an analog output response based on optical inhibitory and exci tatory signals. This silicon-based neuronal chip was initially developed by Howard Chin but later extensively modified by Dennis Su and most recently by 227 Lue [Lue, 2001], all previous or current OMDL members. The layout of these chips included non-periphery I/O pads needed for a flip-chip interconnection between the complementary metal oxide semiconductor (CMOS) IC and the specially designed GaAs substrate. The most recent design incorporates the same electrical circuit design but adds a special GaAs VCSEL driving stage to allow the hybrid integration of a VCSEL array instead of the older GaAs MQW-SLM. After a short review of the silicon chip we show a non-hybridized single channel, two layer operation of the photonic multichip modules. This experi ment help verify a number of optical and electronic components making up the PMCM. We conclude this chapter with a short discussion on the merits of digital VLSI technology for use in the PMCM computational layer instead of the cur rent analog circuit design. In particular, we show how this digital technology can still be used to provide a novel digital VCSEL signal which allows for the formation of our analog optical interconnects. 7.2 VLSI Computation Integrated Circuit Design The current generation silicon VLSI chip is functionally based on the pre vious work of Chin and Su. The functionality of the IC is based on the analog output response of biological neurons. As such, the chip is designed using a 228 dual rail system architecture, necessary to provide for inhibitory (negative) and excitatory (positive) weights using unipolar optical input signals. Although a number of VLSI technologies are available, as discussed in Chapter Two, complementary metal oxide semiconductor (CMOS) technology is used for all VLSI fabrication discussed herein. As also deliberated in Chap ter Two, this is mainly due to the cost and speed considerations of the USC-based MOSIS fabrication service. Additional information on the adop tion of this CMOS technology including power requirements and thermal dissi pation issues are discussed elsewhere [Ananthanarayanan, 2003] and beyond the scope of this thesis. The designed VLSI chip contains a 2-D array of discrete pixels (designed as smart pixels) with each pixel element containing two detectors to sense the input optical signals (for inhibitory and excitatory weighting), processing elec tronics containing 42 transistors that implements the neural-like sigmoidal non-linear response function, and a set of contact output pads to convey the generated voltage signals to the flip-chip bonded modulator array. Recently, this design was altered by J. Lue to provide an electrical current output instead of the originally fabricated voltage output [Lue, 2001]. This is easily accom plished by adding a single transistor on the output stage of the previous design. Essentially, this extra transistor provides a voltage to current transformation and is included without affecting any of the other computational electronics. In this final design, every pixel’s photodetector converts low-level optical signals incident on its two integrated photodiode detectors into a large amplitude dif 229 ferential output currents, suitable for driving a pair of lasers in the GaAs VCSEL array. Although the reader can refer to a number of additional resources to fur ther investigate the specific and detailed VLSI functionality [Ananthanaray- anan, 2003; Cartland et. al., 1998], a short discussion is warranted here. In the next section, a quick overview of each pixel’s design and operation is examined followed by details of the final device's fabrication and post-pro- cessing for integration with the GaAs VCSEL. 7.2,1 Device Design An operational schematic diagram of a single pixel element is shown in Fig. 7-1. Each smart pixel unit cell of the Si IC contains a photodiode stage, a keep-alive current source, a current mirroring stage, a sigmoidal stage, a cur rent-to-voltage conversion stage, and an output buffering stage. The photodiode stage consists of a pair of reverse biased pn photodiodes, which measures the optical input signals. A potential drawback of this detector design is the longer detector response time due to the current collection design and the photocarricr diffusion time for carriers generated deep in the substrate. The current mirror stage is an important stage as the manipulation of cur rents and their subsequent summation at a specific electrical node form the basis of the key computational step. This stage consists of groups of current mirrors that generate two oppositely signed copies of the input current. One current copy goes to channel one and the other to the channel two. The current 230 Non-linear Function Stage Current Mirror Stage 01 - b) Biasing Stage Current-to-Voltage Voltage Buffer Conversion Stage Stage Figure 7-1. Schematic circuit block diagram o f a pixel of the 2-D Si neuron unit array, showing the stages between optical detection and the voltage output stage [from Su, 1997]. mirror use the cascoded current mirrors configuration. The cascoded circuit design consists of a grounded cathode input stage driving a grounded grid out put stage. The advantage of this configuration includes a high gain and the low noise it provides. The analog cascode design enables duplicate copies of the photogenerated current with minimal noise. A potential disadvantage of this design is that power consumption varies with the input signal. Finally, a fur ther disadvantage of the VLSI design using this current mirror is that r .lltiple copies of the input current arc being created throughout the circuit, affecting the power dissipation and the thermal properties of the circuit. The small keep-alive current source stage is used to keep the current mir ror stage active when no optical input signal is present on the photodiodes. This stage is necessary as it prevents the current mirrors from shutting off as this would result in a significant speed penalty of the entire VLSI chip. The circuit works be generated two currents, denoted by l\ and I2 , from photodetectors one and two, respectively. These currents are then duplicated to generate a +Ij, -Ij, and a +I2 , -I2 currents (note that the negative currents are just currents flowing away from a certain circuit node). This circuit node is important as these currents are summed at this node according to Kirchoff’s current law. In particular, the sum of currents (I2 + (-1 ])) on one channel and (Ij + (-L)) on the other channel are generated, as seen in the circuit operational schematic shown in Fig. 7-1. After the summation is performed, a transistor operating in the sub-threshold regime peforms the non-linear sigmoidal trans formation for each channel based on the amount of electrical current passing 232 the summation node. As the newest chip is based on the GaAs MQW-SLM driving chip, a voltage-to-current conversion stage is also needed seen as the rightmost stage in Fig. 7-1. The copies of input currents generated from the photodetector stage and duplicated by the cascoded current mirror are summed up at the summing node of the circuit and compared to a threshold value at the current-to-voltage stage. The voltage at this node swings high or low depending on whether the input difference is above or below the threshold value with a nearly ideal sigmoidal response characteristic. The final stage, and one recently added, is grafted onto the output of the sigmoidal stage. At this point, a single transistor for each channel was incorpo rated to provide the electrical driving current for the VCSEL array. This tran sistor is designed to perform a direct, linear mapping from the output voltage to an electrical driving current needed for analog operation of the VCSEL array. A number of considerations including transistor size, the electrical current capability of the transistor, and the linearity of the voltage to current conversion have been considered and detailed elsewhere [Lue, 2001 J. The next section details the two individual PMCM designs which hybrid izes the integrated circuit computational layer with the VCSEL array. The first design is a segmented design while the second design is the full integration effort. 233 7.3 Demonstration of Two Layer, Single Channel PMCM An experimental setup consisting of two VCSEL laser arrays and a MOSIS fabricated silicon IC demonstrate a simple two layer, single channel PMCM operation. As this was a single channel operation, no computer gener ated hologram or lens array was needed for optical fan-in/fan-out. The experi mental was setup and performed by the author and assisted by L. Lue particularity with the electrical setup. A Signatone electronic probing station was used to optically align a 830 nm wavelength light onto a single photodetector in the chip shown in Fig. 7-2. H U H n;} taaro teM im m tl j > i □ , jrf . ^ j r jM wftimTO t * Figure 7-2 . OM DL neuron-like smart pixel chip fabricated by M O SIS. The chip is configured with an 11 x 11 array o f smart pixels with a spatial pitch o f 125 (Am per smart pixel elem ent I Lue, 20011. This laser was chosen for the optical source as the probe station was pre-con- figured with this laser and has been well characterized. A Mi tu toy a Apolong 234 long working distance microscope objective lens (f = 200 mm and N.A. = 0.42) was used in the probe station for both the laser beam focussing and the CCD camera imaging to assist with the optical alignment. A Melles Griot Laser Diode Controller model 06DLD102 was used to precisely control the amount of output optical power from the input laser. For this demonstration, an Army Research Lab’s 8 x 8 VCSEL was used as the final VCSEL laser shown in Fig. 7-3. The performance of the laser, F igure 7-3. Optical microphotograph o f A R L V C SE L packaged in a pin grid array. N otice the irregular surface pattern on the V C SEL caused by the poor AR thin film coating adhesion. including the output optical power as a function of electrical driving current and the V-I curve is shown in Fig. 7-4. The laser array is configured as a bot tom emitting substrate, but after flip-chip packaging, was configured as a top emitting laser. Only one laser element in the 8 x 8 array was used for this dem onstration. The measured lasing threshold for the entire array varied between 235 (f) « + - r f C C £ Im b i o CL 1 2 3 Current (mAmps) 0.20 0.15 0.10 0.05 0 1 2 3 Current (mAmps) F igure 7-4. Perform ance data curves for the ARL V C SE L . (Top) A plot o f the volt age as a function o f current is shown. (Bottom ) A plot o f the output optical pow er as a function of electrical driving current. 0.9 and 1.4 mAmp. An AR coating was placed on the device, but later pro vided ineffective as this thin film layer pealed off in sections as seen in Fig. 7-3, 236 The ineffectiveness of this thin film layer is also seen by the Fabry-Perot inter modulation effect on the output optical power as a function of the electrical driving current seen in Fig. 7-4. The three data traces shown in Fig. 7-5 plot various electrical currents and optical powers at various stages in this demonstration. The sum of these plots represent the successful operation of our PMCM demonstration. The first data curve plots the output electrical driving current as a func tion of input optical power striking one of the two silicon photodetectors within a single smart pixel element. The sigmoidal operation is shown by this graph. As expected, as the input optical power from the 830 nm laser increases, the output electrical driving current drops according to the computational designed sigmoidal function. The second data curve is the measured output optical power as a func tion of input electrical driving current for the chosen laser in the ARL VCSEL array. The lasing threshold for this chosen VCSEL element occurs at 1.42 mA with a maximum current of 2.1 mA, partially chosen for VLSI power consider ations and linear operating regime of the ARL VCSEL. This laser is connected to the output pad of the silicon IC through the uses of a low resistance, low capacitance electrical probe tip. The final data curve plots the final output optical power of the ARL laser connected to the output pad of the silicon chip through the low resis tance/capacitance probe tip. As expected, as the input optical power from the 237 a 3.0 E 25 ■s < 2 5 D - £ 2.0 • 4 - * k ' * — ^ 3 -I-* 4 r o § 55 t 10 q 0.5 0.0 " T T " ! " " ! — 1 ‘ 1 ] i i i j . . . . \ . . . r — n . . . . . r " — rT " " p r* r,rnr,H — i' i i | i"n"rrrrTT"p"i __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. . . . . . . . . . .L. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . X ..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Lj i i t i i 1 -• • ■ ........ j . 1 . 1 . 1 111-1- 111 I 1 1 1 I 1 l 1 ! 1 ! 1 1 1 1 ! ill 1111 1 1 1 1 1 I 1 I 1 - 1 — 1 1 1 i 1 100 200 300 400 Input Optical Power (uWatts) 500 Q. * C D " -jj ^ -J £-20 D C = 3 < O 10 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VLSI Driver Current (mAmps) £2 50 . Q .^ I 4^ D C 3 10 < O 400 100 200 300 500 Input Optical Power (pWatts) F igure 7-5. (Top) Plot o f the V LSI ouput electrical current as a function o f input opitical power. (M iddle) Plot o f the A RL output optical pow er as a func tion input electrical current. (Bottom ) Plot o f the A RL output as a function o f input optical pow er striking one o f the two VLSI photodetectors. 238 830 nm laser is slowly increased, a sigmoidal computation occurs in the silicon IC. This sigmoidal curve’s output is an electrical current swing. This is repre sented as the output optical swing shown in the last graph in Fig. 7-5. 7.4 Towards Fully Integrated PMCM Having shown the PMCM operation using a set of disjoint, separate components, attention is now turned towards the hybridized flip-chip bonded structure envisioned earlier. An attempt to integrate the silicon IC with indium bumps with the USC-designed, low threshold will be made and discussed in this section. In order to hybridize the VLSI and VCSEL together, one substrate needs to be selected for indium bump bonding. Recall from Chapter Six, that one of the prime motivations for transitioning from double- to single-sided bump bonding was the size and topographical issues related to the photoresist pro cessing. For this hybridization effort we, unfortuneately, are faced with the unusual situation in which both substrates are too small for correct photoresist processing, making this processing tenuous. The MOSIS IC chip has dimen sions of 2.2 mm x 2.2 mm while the VCSEL is even smaller with dimensions of 1.1 mm x 1.1 mm. The larger VLSI substrate was chosen for the semiconduc tor processing. Before commencing with the thick photoresist deposition needed for the indium bump lift-off procedure, a technique involving the placement of multi 239 pie silicon substrates around the VLSI chip was used. In this way, it was hoped that the unwanted photoresist lip-effect could be reduced. A two-layer thick photoresist of positive-tone Clariant P4620 with a blanket exposure of the first layer followed by a pattern exposure of the second layer, like the method discussed in Chapter Six, was used. A dark-field photo lithographic mask with regions for the laser p-contact and the electrical ground contact was used for defining regions in the two-layer thick photoresist where individual indium bumps are desired. After photoresist development the regions where indium bumps will be formed are the regions of removed photo resist on the substrate as seen in Fig. 7-6. Finally, after a uniform layer of ther mally evaporated indium is deposited, the entire photoresist layer is dissolved into a bath of acetone by soaking for a period of 24 hours, leaving only the dis crete bumps of indium on An optical micrograph of the silicon IC with the requisite two layer photoresist with opening for subsequent indium bump bonding is shown in Fig. 7-6. This optical micrograph show two adjacent smart pixels in the MOSIS fabricated IC with a patterned two layer photoresist thick film. The top two photoresist holes are designed for indium bump formation needed for electrical interconnection between the p-contact of the VCSEL array and the output pad of a single channel on the MOSIS device. The bottom two pads arc co-locatcd to provide the necessary ground pad on the VCSEL. 240 . ’ $ ' * . ■ > - W w ijw iS itkIM .I ^ J F igure 7 -6 . Silicon IC with holes in two layer photoresist for later indium bump deposition. The top holes are co-located with the output pad of the smart p ixel, while the bottom two holes are aligned for the necessary ground pads. After indium deposition, an overnight lift-off procedure was attempted. Upon liftoff it was determined that no-indium bump formation was achieved. An in-depth evaluation was launched and later determined this fault; the photo resist processing. The desired undercut profile in our photoresist profile was achieved, but the desired photoresist thickness coating was too thin. The effect of this thin coating is that the indium thick film was continuous on both the photoresist and the desired bump area For lift-off to be correctly achieved, the deposited thick indium film in the photoresist holes must not be in contact with the deposited film atop the photoresist layer. If so, the indium in the photoresist holes tends to be lifted-off with the rest of the deposited indium film during the ace tone-induced lift-off procedure. This prevented indium bumps from correctly forming on the MOSIS chip. The fabrication processing error occurred during the photoresist process ing. Although the same experimental procedures where followed which led to successful bump formation on many previous structures, the lip effect and sub sequent photoresist relaxation caused the formation of an uncalibrated photore sist thicknesses. It appears that the placement of multiple substrates around the VLSI chips stll allowed this unwanted effect to occur. In particular, the small micro-gap between the mated substrate and the photoresist surface tension both assisted in the incorrect film thickness. The solution to this problem is easy, although it does require some time. By accurately recalibrating this thick film formation on small IC sample sizes, this problem can be eliminated and allow for future hybridization success. 7.5 Digital PMCM Preliminary Design The current implementation of the MURI architecture using, fixed inter connection weights and fixed analog VLSI electronics, does not readily lend itself to reconfigurability. An approach to overcome this limitation is one of the prime factors leading to a novel method of driving the VCSEL and creating an unique fan-out/fan-in interconnection system. Instead of an analog VCSEL drive signal needed to form the optical input to the DOE, a discrete, digital 242 driving scheme is now employed. The reasons for this novel method are four fold. (1) This method, as will be shown, can incorporate operational instruc tion sets for feed-forward learning capability. By incorporating this simple instruction sets the performance of the individual smart pix els can be dynamically altered. (2) By using a VLSI digital design we simplify the total IC design pro cess. Digital logic is typically easier to model and simulate then designs using analog or mixed signals. In addition, digital designs can quickly leverage advances made in VLSI fabrication technol ogy* (3) Digital designs are typically fast than corresponding analog designs. Our existing VLSI chip for the PMCM has an analog VLSI driver circuitry that operates below 10 MHz [Lue, 2001] with little pros pect of operating significantly faster without significant changes. (4) Digital electronics can incoiporate a higher degree of programmabil ity than analog electronics. The current PMCM stack is powered via sets of VCSEL which require analog driver circuits. Now, lets consider the case in which we digitally drive the VCSEL faster than the slower photodetectors. In this case the amount of photocurrent collected by the detector is proportional to the optical intensity of the optical beam, the length of time the light hits the detector, and the collec 243 tion time and readout time of the photodetector. By optimally matching the length of time the light hits the detector and the collection time of the photode tector we can utilize pure digital electronics for the VLSI component of the MURI stack while still providing the analog weight interconnection scheme. The previous section demonstrated a l-to-9 analog fan-out using both analog VCSEL driving technique. In this section we demonstrate the same analog l-to-9 fan-out, but using a constant current (i.e., digital) driving tech nique. The experimental setup is similar to the one shown in Fig. 4-9 with the SensiCam CCD camera being used at the readout plane of the 4:2:1 GaAs DOE substrate. The SensiCam CCD achieved a measurement temperature of -11° Celsius for low noise operations. Using the attached computer, a CCD expo sure time of 6.33 msec was programmed, using all 1280 x 1024 pixels with each pixel set to record with a 12-bit pixel dynamic range. The SensiCam is representative of the photodetector on the newly designed VLSI chips, namely that the photodetector has a set collection time and then the generated photo current is transferred into the computational component of the electronics. Using an ILX Lightwave LDP-3811 Precision Pulsed Current Source laser diode controllers and Lab View programming the VCSEL driving period of each digital pulse is set at 6.33 msec with the VCSEL electrical driving cur rent at 2.8 mAmps as shown in Fig. 7-14 below. The SensiCam will not record 244 ^ Duty Cycle 2.8 mAmp ---------------------------------------------------- ---------------------------- 1 — time <- > 6.33 msec Figure 7-7. The digital pulse for driving the VCSEL the instantaneous change in the optical intensity, but rather the integral amount of optical intensity that falls on the detector during the 6.33 msec time frame. Hence, by only controlling the duty cycle of a digital pulse we are able to generate an analog weighted fan-out pattern with a VCSEL. Figure 7-8 shows nine optical fan-out patterns using the 4:2:1 GaAs DOE with varying duty cycles. The experiment started with a digital pulse with duty cyle of about 8 % and end with a digital pulse of nearly 72%. Further experiments also show that a sequence of digital pulses can also generate this analog weighting func tionality. For this experiment the number of small digital pulses in the same 6,33 msec time period generated the analog fan-out pattern. We can now consider sending instructions to the individual smart pixels as additional digital pulses within the pulse train. Notice how the experiment was stopped at a duty cycle of 71.09%. Instead of saturating the DOE fan-out pattern, lets reserve the last -25% of the duty cycle for the instruction set. For example, the following three waveforms in Fig. 7-9 each generate the same 245 I = 2.8 mAmp Turn on time = 500 usee Duty Cycle = 7.89% I = 2.8 mAmp Turn on time = 1 msec Duty Cycle = 1 5.79% I = 2.8 mAmp Turn on time =1.5 msec Duty Cycle = 23.69% I = 2.8 mAmp Turn on time = 2.0 msec Duty Cycle = 31.59% I = 2.8 mAmp Turn on time = 2.5 msec Duty Cycle = 39.49% I = 2.8 mAmp Turn on time = 3.0 msec Duty Cycle = 47.39% I = 2.8 mAmp Turn on time = 3.5 msec Duty Cycle = 55.29% I = 2.8 mAmp Turn on time = 4.0 msec Duty Cycle = 63.1 9% I = 2.8 mAmp Turn on time = 4.5 msec Duty Cycle = 71.09% F i g u r e 7 - 8 . cycle. Output intensity prolile as a function of varying duty 246 analog weighting function, but using a simple sample and hold circuit on the VLSI chip, wc can send I to 3 different instructions to the smart pixel. 8 mAmp 8 mAmp 8 mAmp Duty Cycle Duty Cycle Duty Cycle -time -time -time 6.33 msec F i g u r e 7 - 9 . Waveform schematics showing how simple 1-bit instructions could be sent to the next stack layer without affecting the analog weighted interconnection scheme. Each smart pixel could contain a simple, couple-transistor sample and hold circuit which can measure the optical intensity at the times corresponding 247 to the three dashed lines in the above figure. If a pulse is detected at any of these times, the computational electronics act accordingly. Finally, a method to individual address each separate smart pixel could be incorporated by adding an address header sequence in the beginning of the pulse train much like an Ethernet address. Each smart pixel could have an unique address for maximum flexibility. We would be remiss without mentioning the various disadvantages of this driving scheme. The main issues is that this design requires an analog to digital converter to be incorporated. The A/D typically are large, power hungry devices requiring significant amounts of VLSI real-estate. Additional research is needed to fully exploit this design. 7.6 Conclusion The chapter discussed the early steps toward the integration of a com plete photonic multichip module. After a short introduction to the inner work ings of the VLSI computational electronics, a simple two layer, single channel PMCM experiment was demonstrated. In this case, a electrical probe station was used to externally focus and direct light from a 830 nm laser diode onto one of a pair of photodetectors on the silicon chip. By optically activating only one of the two detectors an electrical driving current in the shape of a sigmoidal curve is generated as a function of input optical power. The output pad of the 248 silicon processing element was connected to the p-contact of an ARL VCSEL element. The laser element was driven with the silicon’s current output. The road to a fully integrated PMCM included an attempt at flip-chip bonding the previously described silicon chip. In this case, we attempted to overcome the same issues that led us to adopt single sided bump bonding. The silicon IC was coated with the dual-layer thick photoresist but edge effects caused unwanted photoresist thickness. The indium lift-off attempts proved unsuccessful. Finally, this chapter ended with a short discussion on the analog vs. dig ital nature of the computational electronics. The use of digital logic instead of analog logic as currently used has a number of compelling reasons including speed and prototyping effort. The problem occurs with integrating this poten tial technology with the analog nature of the weighted optical interconnections. We showed a unique method using a pulse-width modulation scheme for driv ing the VCSEL lasers. A future benefit of this design is that provisions are made potentially allowing feed-forward computational instructions to be sent through the PMCM multilayer stack. 7.7 References K. Ananthanarayanan, “3-D Hybrid Electronic/Photonic Multichip Modules,” Ph.D. Thesis, University of Southern California, (2003). 249 K. Ananthanarayanan, C. H. Chen, S. DeMars, A. A. Goldstein, C. C. Huang, D. Su, C. B. Kuznia, C. Kyriakakis, Z. Karim, B. K. Jenkins, A. A. Sawchuk, and A. R. Tanguay, Jr., “Multilayer Electronic/Photonic Multichip Modules with Vertical Optical Interconnections,” In OSA Annual Meeting, Technical Digest 1995, Vol. 32 of the 1995 OSA Technical Digest Series (Optical Society of America, Washington, DC, 1995). B. K. Jenkins and A. R. Tanguay, Jr., “Photonic Implementations of Neural Networks,” in Neural Networks for Signal Processing, B. Kosko, Ed., (Prentice- Hall, Englewood Cliffs, NJ, 1992), p. 2S7-382, (1992) C. von der Malsburg, “The Correlation Theory of Brain Function”, Internal Report No. 81-2, Max Planck Institute for Biophysical Chemistry, (Gottingen, Germany, 1981). L. Lue, 87th OSA Annual Meeting & Exhibit, Long Beach, CA., (2001). L. Lue, Personal Communications, 2001. A. R. Tanguay, Jr., B. K. Jenkins, C. von der Malsburg, B. Mel, G. Holt, J. O’Brien, I. Biederman, A. Madhukar, P. Nasiatka, and Y. Huang, “Vertically Integrated Photonic Multichip Module Architecture for Vision Applications”, Proceedings of the International Conference on Optics in Computing (OC 2000), Quebec City, Canada, pp. 1-17, June 18-23, (2000). 250 Chapter 8 Potential Applications 8.1 Introduction The design and construction issues of the photonic multichip module (PMCM) for use as the key component of the smart camera have been previ ously discussed. The incorporation of the PMCM in the smart camera system was dictated by the need for massive bandwidth between adjacent electronic processing elements. Only with this architecture can the concept of a “true” smart camera be realized, as no purely electronic or purely photonic solution exists. In this chapter some potential applications of the PMCM/smart camera are introduced. In much the same way that the PMCM was developed, the applications described here all require a technology base that is not easily met with existing electronic solutions, dictating C » , need for innovative approaches. Three specific applications are discussed in this chapter. The first one, enhanced augmented reality, uses the existing smart camera design in a number of unique ways which will be discussed. In this application, graphical annota tions are overlaid onto a real-world image designed to truly enhance our exist 251 ing human vision. This same application can be further enhanced by a novel 360° field-of-view (FOV) camera dubbed, herein, as the Immersivision camera system. A combination of mirrors and beamsplitters are incorporated in such a way to allow a group of conventional cameras with limited field-of-view to be uniquely combined to yield a true 360° FOV camera system. Furthermore, by integrating multiple smart cameras together, a true 3-D, 360° FOV smart cam era system can be constructed. Finally, this chapter ends by examining the potential of integrating biological tissue with elements of the photonic multi- chip module for use as biological prosthetics and biological sensors. 8.2 Augmented Reality Virtual reality (VR) creates a completely artificial environment for the user. An alternative approach, and potentially more useful, is an augmented reality system: an artificial, computer generated overlay onto real world images operating in real-time. For example, a field-deployable head-mounted display can be designed to nrovide navigational (GPS) and threat-warning/targeting information preciselv registered with environmental features, regardless of head pose orientation. The illustration in Fig. 8-1 below shows such an exam ple of augmented reality. In this specific example, a real world image is com bined with relevant information needed for a ground soldier in a combat situation. Precise navigation information is immediately available on the top and left side of the image. The more important information, including hostile threats, is quantified by the system and color coded for attention purposes. In 252 ' ; * £ W lldstrubel tiljr/tv. 3253 m te S -* 1 " ’, Toxic Threat None M t. Weisshorn fcte v. 4505 m fia n g e 3 4 0 m 1 •Mtevntton 20Q5 n> Figure 8-1. Enhanced augmented reality demonstration. In this case the image scene is overlaid with graphical annotations [Tanguay et. i d 2000], addition, this system can incorporate additional annotations from remote sen sors; take, for example, the small IR image projected onto the target’s spatial location on the image (denoted by the blue dot in Fig, 8-1). The entire system would include IFF pass/fail queries, objects hidden by camouflage, and/or bio logical/chemical threats. The graphical annotations in Fig. 8-1 require a degree of object recognition, such as identification friend-or-foe (IFF) (e.g., the car and the truck), target threat assessment based on a combination of thermal (e.g., the truck), moving component (e.g., the car and the truck), and chemical signatures, and chemical/biological/viral threat identification (e.g., the clouds). 253 The smart camera described herein is an ideal solution for the object identifica tion/recognition tasks. Augmented reality is not designed for non-human, remote operations. Rather, with this system, we seek to supplement the performance of the human visual system. Although the acuity and dynamic range of the human visual system is unsurpassed in dynamic image acquisition and interpretation func tions, the human visual system has limits which can be used by adversaries thereby making visual identification and recognition difficult. Camouflage is one such example. In this case, objects of importance are covered with a spe cific paint pattern to blend into their operating environment. The paint pattern is designed to fool the spatial and spectral properties of the human visual sys tem. But by extending the wavelength range with an IR sensor (see insert in Fig. 8-1) or by searching for metameric differences in an environment, the sol dier can be cued to a region within the field of view for further identification. An important consideration with this system is the latency associated with the image acquisition, processing, recognition, and head pose functions, which must be reduced to less than a human response time. This also includes all computation, registration, and display of graphical annotations. Finally, additional considerations are needed when targeting fast-moving targets and threats. Additional details on this project are discussed elsewhere [Tanguay et. al., 2 0 0 0 1 . 254 8.3 Immersive Camera The Immersivision camera project is not directly related to the described smart camera system but future efforts to merge both projects will offer some unique capabilities. The Immersivision camera project was initially started under the direc tion of The Integrated Multimedia Systems Center (IMSC), a NSF funded ERC at USC. The goal was to create an imaging system which takes separate static images (and later video streams) from disjoint cameras capturing separate seg ments of a scene and combine the images into a single composite panoramic image. With the correct optical configuration for the camera, accomplished using precisely aligned beamsplitters and mirrors and the necessary merging software, some simple merged scenes have been created. Figure 8-2 shows one prototype. In this case, three (of a total eight) standard CCD, board-mounted cam eras are shown on a top mounting plate pointing downward onto two angled beamsplitters and a mirror. By orienting the cameras in this fashion, a central common viewpoint is shared between all cameras. The cameras are further configured to overlap the field of view with the adjacent cameras by 5-10°. In this way the computer software has enough common data points for precise registration for subsequent image warping and stitching. The final implementation of this system will contain eight CCDs, each with 512 x 492 pixels. A desired 8 ° overlap between cameras was deemed 255 Figure 8-2. Three elements of the eight-element Immersivision design shown [Wyner, 2001]. appropriate after extensive software validation [Wyner, 2000]. The resultant, composite 360° FOV image will have an effective resolution of ~3000 x 492 pixels. By merging both the Immersivision camera and the smart camera a true 360° smart camera can be constructed. When combined together, this enhanced augmented reality system would span the largest possible field of view, providing for all-aspect sensing, identification, and threat classification functions. 256 With the incorporation of two such combined systems a true 360°, 3-dimensional feature extraction and recognition can be envisioned. In this system two stationary cameras provide the necessary two viewpoints for 3-D reconstruction. 8.4 High-Performance Neural Prosthetics/Probes Neuronal signals are generated by a population of neurons operating corpus callosum fornix am ygdala hippocampal formation nn *as£ FV* Figure 8-3. Neural prosthetic containing a PMCM [Tanguay et. al„ 2002], within a network of dense interconnections. The power of the brain lies in the enormous connectivity between neurons, in some cases a neuronal cell is con- 257 nected to 10,000 nearby cells. Any neural prosthetic that attempts to replicate any tissue functionality must recognize the need for a dense, but highly com pact, interconnection model in order to interface into the biological network. This application does not use the smart camera as configured but rather uses the PMCM module, the heart of the smart camera. An envisioned neural prosthetic using the PMCM as the computational engine is shown above in Fig. 8-3. The PMCM must interface with the living neural tissue. Hence, work has been undertaken to explore biocompatibility with typical semiconductor materials. Fig. 8-4 shows the result of an early experiment growing neuronal tissue atop thin film deposited aluminum on a silicon substrate. 8.5 PMCM for Biosensors Multisite electrodes are a significant technological advancement in the field of neurobiology as they can monitor the temporal and spatial membrane voltage potentials of a cultured medium in real-time. Unlike techniques which only consider the interactions of a single neuron, multisite electrodes allow for a systems level approach towards the understanding of neuronal groups to be undertaken. Therefore, phenomena previously not easily investigated, such as cellular/neuronal plasticity, can be measured. One major area of current research which relies on the use of multisite electrodes is neuronal pattern development in the nervous system. Cell biologists are currently trying to evaluate large scale neuronal pattern development under the influence of topo graphic reaction of adjacent cells, electric fields generated by the cells them- 258 Figure 8-4. Neuronal growth atop semiconductor substrate previously taken by the author. selves, gradients of soluble chemicals, and patterns of adhesion or gradients of adhesion guiding the cellular structures. Finally, multisite electrodes are one of the few ways in which to investigate the rhythmic pattern generation in selected neuron groups. Although significant progress has been made with the current probes for use as biosensors, the inclusion of a PMCM can further enhance the sensor pro cessing capability. A proposed biological sensor module is shown in Fig. 8-4. A patterned surface structure for a piece of biological tissue is shown on the left side of the multi chip module. A set of electrical interconnection lines 259 260 S L *1 2 T O si c O " J 5 Z o c a 3 U l =r ca n — • V - ° £ < 2 . ? s n X X c ; v ; c « o 3 C C - = £ . n 3 sr e r a R q f 3 J S N ~ £ i F T o' “• 3 < ‘ 2. 3 3 rs 3- o n > o ra Patterned surface structures for cellular outgrowths V ia thru hole VCSELS array E V L S I Electronics Cold-Well Indium Bumps Silicon Substrate Holographic Interconnections/ Processing Elen.snts (SVHOE) Proposed Neuro-Chip EB-MCM Advantages: 1. Electrodes ■ Between 300-500 urn long .-.very low resistance.capacitance, and inductance .-.large electrode packing density • Electrode array density is independent of the bus lines between biological and electrical sections of EB-MCM since multiplexers can be designed In the VLSI electronics • VLSI Electronics directly below electrodes 2. Separate cultured medium and readout electronics 3. VCSEL array is heat-sinkabie 4. Learrning weights can be encoded in SVDOE Electrical Interconnection between biological/electrical and photonics sections of M C M Container wall (Section of Glass Test Tube) Cellular G rowth Area Photonics and Electronics (Under) Chamber Electrical Interconnection \ between biological and j 'photonic sections of MCM | V G S E L S a r r a y Holographic interconnections/ Processing Elements 35 between the chamber and a VCSEL array transfer signals from individual neu rons or groups of neurons. The lasers provide the conversion from small volt age or current cellular signals to optical signals for processing by the stratified volume diffractive optical element. This optical element is predesigned to fur ther classify the neural signals from large groups of neuronal ensembles for final classification of biological agents. 8.6 Conclusion The chapter introduced a number of novel, potential applications of either our smart camera, or the key component of the smart camera, the PMCM. In all these applications, a driving need for object recognition and classification allowed for the integration of elements of the smart camera. 8.7 References A. R. Tanguay, Jr. and IC . B. Jenkins, “Hybrid Electronic/Photonic Multichip Modules for Vision and Neural Prosthetic Applications,” Toward Replacement Parts for the Brain, (D. Glanzman and T. Berger, Eds.), MIT Press, Boston, MA, 2002 (in press). A. R. Tanguay, Jr., B. K. Jenkins, C. von der Malsburg, B. Mel, G. Holt, J. O'Brien, I. Biederman, A. Madhukar, P. Nasiatka, and Y. Huang, “Vertically Integrated Photonic Multichip Module Architecture for Vision Applications”, Proceedings of the International Conference on Optics in Computing (OC 2000), Quebec City, Canada, pp. 1-17, June 18-23,(2000). 261 J. Wyner, Personnal Communications, (2000). 262 Chapter 9 Conclusion and Future Research Directions 9.1 Introduction We have examined a set of core technologies needed for the realization of a truly smart camera. Starting with conventional computers and existing commercially available “smart” cameras we began to define the architectural issues needed for our envisioned applications. After adopting a multi-layer photonic multichip module as the core of our design, we identified the key components and their requirements needed for successful operation. This included the development and experimental verification of high refractive index substrates used for both computer generated holograms and stratified volume diffractive optical elements, optical thin films deposited atop these dif fractive surfaces, and the development of a novel packaging technology which allowed all the individual components to be easily integrated into a compact system. 263 The investigation of each of these areas is discussed below followed by a discussion of various future research directions. 9.1.1 Smart Cameras and PMCM The IVP MAPP is a high-performance, albeit limited, commercially avail able smart camera. For low-level image processing operations such as thresh old equalization, Sobel operations, edge detection, and thinning this camera has no equal when compared to general purpose workstation-cla computers. Unfortunately, the architecture is designed only for these limited operations. Attempts to add additional processing capabilities are difficult the camera runs slowly, but in most cases these additional capabilities can not be per formed at all. This is especially true when the camera needs global image parameters. General-purpose computers can extract more information from a given image scene but are slower than the MAPP 2200 in total execution speed. In this case, the total execution time of general purpose computers depends not only on the speed of the CPU but, to a large degree, on the communications bottleneck between the CPU and memory. This communications bottleneck is further explored using a MPI cluster computer system using commercial Apple Macintosh G3 computers interconnected with a standard 100BaseT 100 Mbps Ethernet system. The significant result in this set of experiments is that classes of computer problems, such as image/scene recognition and feature extraction, cannot be solved by adding more CPUs. Rather, a more robust interconnection scheme combined with computer processors is needed. 264 Starting with the benchma- mg data from Chapter Two, a previously gen eralized PMCM architecture was introduced. This architecture was configured in order to utilize advantages of optical interconnections for high performance parallel 3-D modules. Such interconnection densities can not be easily imple mented using traditional electrical interconnections. This 3-D integration approach allowed for a compact 3-D interconnec tion between arrays of silicon based processing elements. Previous PMCM architectures relied on the use of a GaAs MQW SLM along with a novel opti cal power bus in order to provide the modulated optical illumination needed for the 3-D stack. The new architecture reported here-in eliminates both compo nents and replaces them with a vertical cavity surface emitting laser. The parameters of interest for potential VCSEL integration include, but are not lim ited to, operating wavelength, lasing threshold, maximum output power, laser mode structure, emission geometry, VCSEL array uniformity, spatial dimen sions, polarization effects, and VCSEL packaging type. 9.1.2 Diffractive Optical Elements The fabrication and optical characterization of a number of DOEs fabri cated in a high index substrate material was then discussed. Using Fourier optic principles a DOE pattern, known as the 4:2:1 DOE (that was previously developed for use in a quartz substrate) was fabricated by semiconductor pro cessing on a high refractive index GaAs substrate. The optical characterization of this new device included optical fan-out measurements. Aside from the tra 265 ditional sources of errors in the desired optical reconstruction pattern a new effect wras discovered. Using a high performance optical setup, an unwanted, and previously unreported, Fabry-Perot effect was identified w'hich signifi cantly altered the performance of the DOE. This unwanted effect would pre clude operation of any high-index DOE in our PMCM. For the GaAs 4:2:1 DOE, if the substrate was rotated by only 0.6° off from normal incidence, the right nearest neighbor beamlet’s optical intensity experiences a nearly 50% change from ideal. This DOE effect has never before been reported. Later, by utilizing multiple lasers in the same VCSEL array, optical fan-out/fan-in was demonstrated. The desired output pattern demonstrates one of the key functions of fan-in, and is the first such demonstration of its kind, to the best of this author’s knowledge. A new' type of diffractive optical element was then discussed, the strati fied volume diffractive optical element. Our approach is fully compatible with semiconductor manufacturable technology and does not require the complex optical interferometric system for making high spatial frequency phase pat terns. Instead it leveraged the enormous strides made in semiconductor pro cessing over the past decade to make a 3-D module of stacked diffractive elements that can emulate the optical performance of volumetric material. The first generation system w'as constructed to validate the approach and to opti mize the various processing parameters. 266 9.1.3 Thin Films for PMCM Starting with the optical power available in our vertical cavity surface emitting lasers and ending with responsivity in our optical power detectors, we traced the optical fields and associated optical powers as we passed through multiple surfaces in the AR coated PMCM stack. In this way we showed that for successful PMCM operations an AR coating is necessary due to the limited power output of the available VCSEL array and the low silicon photodetector responsivity. This section also detailed some of the fabrication, material parameters, and the performance of ITO coatings on high-index substrates. Starting with a simple surface profilometer and ending with a Cary-Varian spectrophotometer an ITO thin film model was built up to help re-optimize the AR coatings using an optical software modelling program, TFCale. After optimization, these AR coatings were shown to have excellent optical properties for potential integra tion in our PMCM. We demonstrated that not only do we observe an increase in optical throughput but, more importantly, we eliminate the unwanted CGH rotational effects that were investigated in the previous chapter. This effect, if not mark edly reduced, would have created extremely stringent alignment issues during the PMCM packaging. The use of AR coatings on SVDOEs was then discussed. Only with an AR coating does the familiar, and expected, "picket fence” effect for the dif 267 fracted order of a two-laver SVDOE structure occur. This effect was investi gated and characterized. 9.1.4 Hybrid Photonic/Electronic Packaging In order to fully integrate the proposed PMCM, the use of indium “vel cro," cold-w'eld double sided and single sided bump bonding was introduced. The designed-for. novel surface morphology allowed for simplified hybrid electronic/photonic device integration. Experiments involving double-sided bump-bonding showed high reliability bonds with an excellent pull-test result of 139.6 Kg/cm- , low electrical contact resistance of 300 mO/bump (35 x 35 pm), and a simplified bond pad preparation which allowed for easier device integration. Devices bonded using this technology base include a number of test structures for device contact characterization, multiple quantum well (MQW) spatial fight modulators, high speed, cryogenic crossbar switches for advanced data routing, and real time X-ray detectors. Integration issues were the impetus for the creation of single-sided indium bump bonding, which is ideal for the integration of electronic/photonic devices with uneven surface profiles, or for devices unusually shaped or sized. Even with a slight increase in electrical contact resistance (480 mQ/bump (35 x 35 pm)) this technology base allowed for the easy integration of commercially available, or custom ASIC IC with photonic devices. This was demonstrated by bonding two very different lasers arrays. In the first case we demonstrated 268 the hybrid integration of a one-dimensional laser array to a single sided bumped passive silicon substrate. Next, a low threshold, two-dimensional VCSEL laser arrays was mated to a passive silicon substrate and was shown to operate as predicted. 9.1.5 Integration Efforts A simple two layer, single channel PMCM was then demonstrated. A 830 nm laser was used to provide the analog input optical beam for one of the optical detectors on the MOSIS IC. The MOSIS IC processed these signals using the previously described sigmoidal processing technique and provided the electrical input driving signal for an externally mounted ARL VCSEL. The output beam pattern was similar to the theoretical output pattern. We then turned attention to some of the preliminary steps undertaken for complete integration of the PMCM. Problems with the multilayer, thick photo resist needed for indium bump formation were documented. A short discussion followed describing some potential advantages of using digital technologies for the computational layer in the PMCM. Such dig ital technologies were capable of providing analog optical weights. 269 9.2 Future Research Directions 9.2.1 Photonic Multichip Modules (PMCMs) There are a number of directions in which to expand this project. First, the complete integration of a PMCM using the entire 8 x 3 VCSEL array is needed to permit the full evaluation of this architecture. By altering the DOE layer (responsible for the associated optical fan-in/fan-out patterns), a quantita tive evaluation of multiple architectural designs can be compared/contrasted in terms of computational performance, thermal dissipation issues, required num ber and configuration of interconnection schemes, learning ability, and packag ing requirements. Second, by increasing the number of optical data channels in the integrated PMCM we can examine the scaling trends as larger VCSEL arrays become available. In this way we can compare and contrast the role of the architecture as the optical interconnection scheme evolves. 9.2.2 Computer Generated Holograms There are a number of logical extensions for furthering computer gener ated hologram research. First, the existing CGH computational design and modeling software needs to be extented in order to correctly model the effects of AR coatings. The current approach for the design of the CGH can not model any of these effects as a FEM or a fully vector EM approach is needed. A sec ond research direction would be a detailed characterization of alternative DOE materials for use in the PMCM stack. Although we preliminarily decided to utilize a GaAs substrate, there were a number of additional substrates available 270 for use, including sapphire and indium phosphite substrates. Third, a detailed analysis of other thin film coatings on CGHs would provide data needed for future PMCM integration. This analysis could also include a comparison between thin films and high spatial frequency binary optical elements used as an AR coating. Finally, in an attempt to increase the number of diffracted beams and the number of electronic processors to optically interconnect, a high spatial fre quency CGH could be researched. By integrating these devices into the PMCM a more global interconnection scheme could be employed as high spa tial frequency CGH allows optical beamlets to be diffracted at greater angles then lower frequency CGH. The construction of these devices is difficult as the optical photolithographic equipment in use at the M. W. Keck Photonics Clean- room Laboratory is limited to a 0.8 |Um resolution. An alternative approach, and one that is started to be explored, is using a proprietary E-beam direct write system using a Philips XL-30 Scanning Electron Microscope (SEM). The Philips SEM is equipped witn a tungsten filament providing a 3.5 nm resolu tion at 30 kV, and a high resolution motorized stage for accurate positioning of samples. The SEM can write onto a large 500 mm by 500 mm field of view with a slightly larger lithographic beam-pointing resolution of about 8 nm. In this way computer-generated patterns (such as DOE’s) can be written directly in electron beam resist. The necessary 29c PMMA photoresist layer on top of the substrate is approximately 50 to 70 nm high, and due to electron proximity effects, limits the obtainable lithographic resolution to about 50 to 60 nm. 271 Several DOE arrays were successfully written using this pattern genera tion capability. Figure 9-1 shows four direct E-beam written 4:2:1 CGHs of varying spatial frequency. In order to progress further a number of additional areas need optimizing including CGH e-beam dosage levels, optimal ECR etching for these designs, and re-evaluation of the optical characterization setup as the DOE pattern is too small to optically align. 9.2.3 Indium Bump Bonding The use of "velcro” indium bumps for the integration of a number of devices was thoroughly examined. These devices provided a number of future research directions which could be examined. A key future research direction should be the dynamics of the indium bump during the bonding process. A careful examination of the final bump dimensions after bumping, an investiga tion of the actual breakage of the indium oxide layer, and the effect of the com pressed single sided bump dimensions on the mechaniced properties all need to be performed. 9.2.4 ITO Thin Films Although the deposition procedure, modeling, and experimental perfor mance of the ITO coating for planar surfaces was investigated, a number of additional avenues of exploration can be performed. The fist area might be a comprehensive characterization of the deposited ITO thin film conformality on substrates with irregular surface profiles. This conformality can affect the 272 M agnification 2000x Magnification! 350x - . •. • «*,.* ‘ • . * . * • ", ‘""'i* * \ * ■ i P * •- f * .. u t a ■ . i, ... t i * » k » « • * ■ M «*«* I'M 4 * * • . 1 • . ■ . ► .■■.'■<■ * I, . , ' ' . * • .!( . m v ■ ■ • .: ■- ■ ■■■..• * . .‘"‘K . . ‘ rVS : J- ’J - -J. ’ !•' ■r - r i * - ’ V “ * * * * 1 . . . r r - • - r •/* r * * f * _ r * j r\. ■ « ' I ? \* 4 » Mih Feat. 0.625 ixm Min Feat. 3.125 fim Min Feat. 0.3125 |im Min Feat. 1.6 |im . i s r U 4 . f, > . 'hi e i i ? / i';Y< . > < * ' f * * * ii 1 * ■ * „ * ■ , . /» i t T * ■ * -. M.4 ■ 1 ' .... v . * < / V -- - 3 f ; & 3 : f t * f * ' * -. « . •. v „ * e v - , . ; * r ~ c < u r « V ( ^ *, f . f * f — \jf^ r.fr. r . ! ,-.7- . •** - A •. D , •, * » . v, » - ,?'£ ^ > > • y. if * i ’ f V y . . ■ i )j'*. ^ '4 •' 7><1 ’ * * SI M agnification 3500x M agnification 800x Figure 9-1. Four direct write E-beam computer generated holograms with 3.125 pm, am, 0.6125 pm, and 0.3125 pm minimum feature sizes. overall film performance in ways no yet fully explored. An additional future research direction is the integration of an ITO-based AR coating for the use in the reduction of the Fabry-Perot effects on VCSEL. A number of tested VCSEL, including the ARL laser, the NEC, and the low threshold USC VCSEL, are all single-mode lasers that exhibit a slightly fluctuation in output optical power as the input electrical driving current increases. By applying an ITO coating this effect could be conceivably be eliminated. 9.2.5 Stratified Volume Diffractive Optical Elements Of all the technologies explored in this thesis, the SVDOE devices potentially hold the most promise for future high performance optical compo nents. A couple future research directions were touched upon earlier but are expanded here. A prime consideration for the utilization of our novel fabrication method is the unique opportunity to incorporate different materials into a single SVDOE stack. Thus a stack constructed with these different materials might be the first future research direction. In this way, we could test alternative materials for the case of integration, in addition to modeling its optical proper ties when configured for use in the SVDOE stack. Instead of performing the micro-fabrication ourself, we could also inte gration substrates fabricated by IC foundry services. Figure 9-2 shows a MOSIS fabricated IC used to explore the feasibility of foundry fabricated SVODE structures. 274 < m * * w Figure 9-2. MOSIS TinyChip illustrating feasibility of foundry fabrication SVDOE structures. The real performance of the SVDOE substrates was only realized with the application of a unique AR coating. The investigation on the conformality both for SVDOE and CGH devices will eventually be needed to further explain and characterize the optical effects we are observing. This data can be used for incorporation of more accurate SVDOE computational modeling. Finally, having fully discussed the potential for SVDOEs a careful char acterization of the limitations of such a device are needed. The maximum number of diffractive optical layers, the materials used and thei. mechanical stability, any additional fabricational requirements and the problems associated with flip-chip bonding 4+ layers all need to be characterized. The use of opti 275 cal spacers which can guarentee a specific spacing between adjacent layers in the SVDOE stack is also needed. Most of the initial experiments were hit and miss with regards to the actual spacing and a more detailed examination is war- rented. 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Asset Metadata

Creator Nasiatka, Patrick Joseph (author)

Core Title Design, fabrication, and integration of a 3-D hybrid electronic/photonic smart camera

Contributor Digitized by ProQuest (provenance)

School Graduate School

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag engineering, electronics and electrical,OAI-PMH Harvest

Language English

Advisor Tanguay, Armand R. (committee chair), Berger, Theodore W. (committee member), Jenkins, Keith (committee member), O'Brien, John (committee member), Weber, Charles L. (committee member)

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c16-375197

Unique identifier UC11339268

Identifier 3103950.pdf (filename),usctheses-c16-375197 (legacy record id)

Legacy Identifier 3103950.pdf

Dmrecord 375197

Document Type Dissertation

Rights Nasiatka, Patrick Joseph

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the au...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus, Los Angeles, California 90089, USA