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CMOS gigahertz -band high -Q filters with automatic tuning circuitry for communication applications

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CMOS gigahertz -band high -Q filters with automatic tuning circuitry for communication applications

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Content CMOS GIGAHERTZ-BAND HIGH-Q FILTERS WITH AUTOMATIC TUNING
CIRCUITRY FOR COMMUNICATION APPLICATIONS
by
Yuyu Chang
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
August 2002
Copyright 2002 Yuyu Chang
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UMI Number: 3094408
UMI
UMI Microform 3094408
Copyright 2003 by ProQuest Information and Learning Company.
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UNIVERSITY OF SOUTHERN CALIFORNIA
THE GRADUATE SCHOOL
UNIVERSITY PARK
LOS ANGELES, CALIFORNIA 90089-1695
This dissertation, written by
under the direction of h dissertation committee, and
approved by all its members, has been presented to and
accepted by the Director of Graduate and Professional
Programs, in partial fulfillment of the requirements for the
degree of
DOCTOR OF PHILOSOPHY
^ '^=3-
Date
Director
A u g u s t 6 , 2002
Dissertation Committee
C ? k .
. ' vi- - - - - - - - - -
Chair
ryyw L w h e f |.
J i t t J M t
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A cknow ledgem ents
Working on a Ph.D. is a long but interesting learning process, and cannot be
completed without the competent and extensive help of many people. My advi
sor, Professor John Choma, is an outstanding teacher. He led me to the analog
design and guided the project. I thank him. My co-advisor, Dr. Jack Wills, is
a knowledgeable person and made important contributions to this research and
projects. He always conveys precious insights and direct solutions to the prob
lems I have, and patiently guides this research. In addition, he helped proofread
my dissertation and many publications. I am grateful to him. Professor Robert
Scholtz provided generous support for the circuit fabrication through MOSIS.
He deserves my special thanks. The class, RF Electronics Design, provided by
Professor Behzad Razavi at UCLA is extremely helpful and I thank him. Dr.
Louis Luh gave valuable suggestions and feedback in the design and I thank
him. Steve Bucher did a remarkable job in helping me format and proofread
the manuscript. I am indebted to him. I am extremely indebted to Chin-Tzu
Chang for her untiring support and unlimited belief in me for over a decade and
I thank her. I would like to thank Dr. Man-Ying Wang for her warm encourage
ment and unconditional support. I also would like to acknowledge individually
the following people who participated in this process: Dr. Jeff Draper, Dr.
Herming Chiueh, Dr. Ivan Horn, Weesan Lee, Joong-Seok Moon, and Vincent
ii
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Shao. I thank them. I wish to acknowledge Jeff LaCoss and Advanced Systems
Division at USC/Information Sciences Institute for providing me research assis-
tantship during my doctoral study. Finally, I express my heartfelt appreciation
to my parents and family for their constant and warm support over the years.
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C ontents
Acknowledgem ents ii
List Of Tables vi
List Of Figures vii
Abstract xi
1 Introduction 1
1.1 M otivation.............................................................................................. 1
1.2 Research Objectives.............................................................................. 8
1.3 Organization of D issertation.............................................................. 9
2 Research Background and Problem s on Continuous-Tim e Fil
ters and A utom atic Tuning 11
2.1 Introduction........................................................................................... 11
2.2 Continuous-Time Filter O verview .................................................... 14
2.2.1 Active RC Op-Amp Based F ilte rs ......................................... 14
2.2.2 Transconductance-Capacitance Filters ............................... 16
2.2.3 RFC Filter .............................................................................. 24
2.3 On-Chip Automatic Tuning Scheme O v erv iew ............................. 27
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2.3.1 Introduction.................... 27
2.3.2 Indirect Tuning Scheme ......................................................... 29
2.3.3 Direct Tuning S c h e m e ............................................................ 33
3 Theoretical Foundations and D esign Techniques 36
3.1 Gigahertz-Band Filter D e s ig n .......................................................... 36
3.1.1 Introduction............................................................................... 36
3.1.2 Aggressive Transconductance Filter D esign........................ 39
3.1.3 Active Notch Filter D esign..................................................... 67
3.1.4 Passive RLC Bandpass Filter D e s ig n ................................... 81
3.1.4.1 CMOS Technology Overview ........................... 81
3.1.4.2 Spiral Inductor D esig n ................................. 82
3.1.4.3 On-Chip Varactor D e s ig n ..................................... 90
3.1.4.4 Filter D e s ig n .................................................... 99
3.2 Automatic Frequency Tuning D e s ig n ............................................. 104
4 Experim ental P rototype and Test R esult 115
5 Research Contribution 125
6 Conclusion and Future Work 128
v
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List O f Tables
3.1 The performance metrics of the bandpass and lowpass filters with
<3=31............................................................................................... 60
3.2 The performance metrics of bandpass filters with a designated
Q=33....................................................................................................... . 66
4.1 The performance metrics of bandpass.......................................... 119
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List O f Figures
1.1 Front-end of a transceiver..................................................................... 2
1.2 Frequency allocations for different filter topologies.......................... 3
1.3 Master-and-slave tuning scheme with a VCF.................................... 5
1.4 Transmitting (TX) and receiving (RV) modes for a transceiver. . 7
2.1 Second-order state-variable filter and Op-Amp integrator cell. . 15
2.2 (a) Ideal Gm-C integrator, (b) non-ideal Gm-C integrator, and
(c) gain and phase responses of an ideal integrator (dash lines)
and a non-ideal integrator (solid lines) .......................................... 17
2.3 Biquad Gm-C f ilte r .............................................................................. 21
2.4 (a) RFC filter and (b) small signal analysis...................................... 24
2.5 Indirect tuning scheme.......................................................................... 29
2.6 Constant-#™, tuning technique........................................................... 30
2.7 (a) VCF and (b) VCO tuning techniques......................................... 31
2.8 Self-tuned filter........................................................................................ 34
3.1 Bandpass filter, LNA, and image-reject filter in a receiver. . . . 37
3.2 Basic biquad filter.................................................. 39
3.3 Block diagram of filter circuit II.......................................................... 43
3.4 Sub-gigahertz AGm filter....................................................................... 44
3.5 Negative conductance generator........................................................... 46
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3.6 Frequency responses at 559MHz, 877MHz, and 970MHz with
high-Q capabilities......................................... 50
3.7 Filter frequency response with u > 0=881MHz and Q— 34................ 50
3.8 Gigahertz AGm bandpass filter........................................................... 52
3.9 Independent Q tuning of the AGm filter with a center frequency
at 1.5GHz................................................................................................ 55
3.10 AGm filter with Q larger than 500 at 940MHz, 1.5GHz, and
2.17GHz............................................................... 56
3.11 Gigahertz AGm lowpass filter............................................................. 57
3.12 Frequency response of the lowpass filter with f 0= 2.48GHz and
Q=2.4 (without cq)................................................................................ 58
3.13 The independent Q tuning of the lowpass filter with a resonant
frequency at 2.07GHz (with c9=0.35pF)........................................... 59
3.14 Gigahertz AGm bandpass filter........................................................... 61
3.15 AGm filter with Q larger than 300 at 625MHz, 1.25GHz, and
1.65GHz................................................................................................... 63
3.16 Q tuning of the bandpass filter with a resonant frequency at
876MHz.................................................................................................... 64
3.17 Q tuning of the bandpass filter with a resonant frequency at
1.68GHz................................................................................................... 65
3.18 Hartley and Weaver image-reject mixers........................................... 68
3.19 Passive notch filter and feedback block diagram............................. 70
3.20 Input impedance load with bandpass characteristics...................... 73
3.21 Notch filter.............................................................................................. 75
3.22 Simplified model for the derivation of the notch filter.................. 76
3.23 High-Q image-reject filter with center frequencies between 595MHz
and 1354MHz.......................................................................................... 78
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3.24 Q tuning with a uiz at 1089MHz........................................................ 79
3.25 Physical model representation of a spiral inductor........................ 83
3.26 (a) Two-port inductor model and (b) one-port inductor model. . 85
3.27 Induction of eddy currents in CMOS technology............................ 86
3.28 Layout geometry of a spiral inductor................................................ 87
3.29 Impedance transformation of a varactor: (a) series equivalent
circuit and (b) parallel equivalent circuit.......................................... 91
3.30 pn-junction varactor in CMOS technology: (a) structure and (b)
layout........................................................................................................ 91
3.31 NMOS varactors: (a) inversion region in p-substrate and (b) ac
cumulation region in n-well technology.............................................. 94
3.32 PMOS varactors: (a) the accumulation region and (b) the inver
sion region..................................... 95
3.33 Capacitance versus control voltage V g — Vcti................................... 96
3.34 NMOS varactor models (a) in the accumulation region and (b)
in the depletion region.......................................................................... 98
3.35 LRC bandpass filter..................................................................................100
3.36 Wide frequency tuning capacities...................................................... 102
3.37 Wide Q tuning capacities........................................................................ 103
3.38 Frequency versus tuning voltage............................................................ 103
3.39 Proposed tuning circuit block diagram.................................................105
3.40 Synchronous rectification tuning scheme: (a) V\ > V 2 , (b) circuit
response of (a), (c) V\ < V 2 , and (d) V\ — V 2 ................................... 105
3.41 Selection of the input stimulus............................................................... 107
3.42 Peak amplitude detector...................................................................... 108
3.43 Switch-and-delay generator......................................................................109
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3.44 Gilbert cell multiplier...................................................... 109
3.45 Op-Amp integrator: (a) symbol and (b) circuitry.................................110
3.46 Bias circuit............................................................................................. 112
4.1 Chip photo............................................................................................. 116
4.2 Printed-circuit board layout. ......................................................... 117
4.3 Reflection coefficient of a trace on PCB...............................................117
4.4 Bandpass filter layout.............................................................................. 119
4.5 CMOS switch measurement............................................................... 121
4.6 Peak detector measurement................................................................ 121
4.7 The output of the switch-and-delay generator......................................122
4.8 Multiplier measurement............................................... 122
4.9 Op-Amp frequency response............................................................... 123
4.10 Outputs of bandpass filter and peak detector.......................................124
4.11 Tuning voltage of a CMOS varactor......................................................124
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A bstract
Gigahertz-band CMOS front-end filters with high quality factors have been
long considered as one of the most substantial and challenging building blocks
in transceiver design. The filters have to satisfy stringent requirements for
wireless standards, including gigahertz resonant frequency, high quality factor,
low noise figure, high dynamic range, and excellent stability. Therefore, discrete
components are usually utilized.
Considerable research has been conducted for two decades in developing high
performance monolithic active filters to be implemented with other circuits onto
the same chip. However, conventional Op-Amp based filters and state-of-the-art
Gm-C filters cannot reach this goal because they are fundamentally frequency-
limited implementation topologies; thus, only low hundred megahertz filters are
reported to date. Another design consideration is that the characteristics of fully
integrated analog filters usually deviate from the filter design specification due
to process variation and temperature fluctuation, leading to performance errors.
The master-and-slave scheme is a widely-used tuning circuitry for medium-Q
video-band active filters. However, its tuning accuracy relies on the matching
and tracking between both filters. Therefore, this tuning scheme is not suit
able for gigahertz-band high-Q filters because parasitic capacitances cannot be
matched well in such a high-frequency range.
xi
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To circumvent the aforementioned problems, we proposed three aggressive
Gm filters and one RLC filter with Q-enhancement circuitry in this work, which
essentially extend the filters’ operation to gigahertz frequency range with rea
sonably high quality factors. A new image-reject filter is also demonstrated
using this design technique.
Based on tuning in the idle periods of the burst-mode transmissions and
reception, a new synchronous rectification scheme is proposed to automatically
correct the resonant frequency of filters. Since this scheme directly tunes the
filters, it does not have matching and tracking problems inherent in the master-
and-slave scheme. Furthermore, it consumes a smaller silicon area and little
power. The proposed tuning scheme can also be utilized in lowpass, highpass,
and notch filters.
A 1.15GHz high-Q RLC filter with a synchronous rectification tuning scheme
has been designed, prototyped, and tested using 0.5/rm digital CMOS technol
ogy. The proposed filters indicated a great potential to be used in transceiver
front-ends.
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C hapter 1
Introduction
1.1 M otivation
All modern communication systems, such as television and telephony, measure
ment equipment, and instrumentation systems contain various forms of electrical
filters that designers have to implement in an appropriate technology. Filters
are circuits that have a specific transfer function between the output and in
put ports that sets the amplitudes and the phases of signals. Included among
several familiar filtering functions are lowpass, bandpass, highpass, and notch
filtering.
In radio frequency (RF) systems, wireless receivers often use a heterodyne
architecture consisting of a bandpass filter, a low noise amplifier (LNA), an
image-reject filter, and a mixer [51], as illustrated in Figure 1.1. To date,
these RF circuits are dominated by discrete components or low integration level
monolithic microwave integrated circuits (MMICs). Moreover, virtually all high
performance wireless products employ bulky discrete devices, such as ceramic,
1
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Band selection Low noise Image-reject
filter amplifier filter
Mixer
Local oscillator
Figure 1.1: Front-end of a transceiver.
surface acoustic wave (SAW), or LC devices for the realization of RF band
However, the trends in very large-scale integrated (VLSI) circuits are to
tion level by incorporating as many devices as possible in a single chip. System
integration offers several advantages: low cost, high speed, and less power dis
sipation. W ith the swift shrinkage in a transistor size, circuit minimization can
reduce the number of input and output pins, and the size of the circuit, leading
to production cost reduction. For high-speed circuits, parasitic capacitances im
pose limits on the upper operating frequency. An integrated single chip design
minimizes interconnect and parasitics compared with a multi-chip or discrete
design, allowing faster circuits that use less power. Another benefit of the sin
gle chip solution is the time-to-market reduction in fabrication, assembly, and
system testing.
selection and intermediate frequency (IF) channel selection bandpass filtering.
scale down the physical dimensions of transistors and achieve a maximal integra-
2
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Figure 1.2: Frequency allocations for different filter topologies.
Gigahertz-band CMOS on-chip filters with high signal selectivity have long
been considered one of the most substantial and challenging building blocks in
electronic system design. This is primarily due to the fact that on-chip filters
using traditional filter design topologies cannot meet the stringent requirement
of the system. In addition, filter characteristics vary between devices due to
process and temperature variations. Current cellular communication applica
tions require front-end filters with resonant frequencies higher than 800MHz
and reasonably high quality (Q) factors approximately equal to 30.
Generally, continuous-time filters can be classified in three categories: RC
operational amplifier (Op-Amp) based active filters [54][27], transconductance-
capacitance (Gm-C) filters [29] [30], and passive RLC filters [49]. Their typical
frequency ranges of operation are shown in Figure 1.2. Conventional Op-Amp
3
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based active filters utilizing resistive or capacitive feedback suffer from inher
ently limited frequency responses because Op-Amps must be compensated to
maintain closed-loop stability [4]. The limited frequency response of the filter
usually restricts the operation to frequencies below 1MHz. State-of-the-art Gm-
C filters use an open-loop integrator as a building block and essentially exploit
a linear transconductor whose high impedance output port is terminated with
an integrating capacitor. Because the Gm-C integrator is open-loop, they have
much higher operating frequencies than Op-Amp based filters. However, the
overall filter configuration still applies global feedback, thereby limiting its use
at very high frequencies. Another problem is the excess phase shift [20] caused
by parasitic poles and zeros in an integrator, causing instability at very high
frequencies. In addition, the limited dynamic range of this topology prevents its
application in RF front-end filters [59]. Gm-C filters reported in the literature
have resonant frequencies ranging from a few kHz up to 250MHz [43]. Passive
RLC filters, composed of resistors, inductors, and capacitors, are suitable for
gigahertz-band operation, but the limited quality factors of monolithic induc
tors (usually less than 5 when built in digital CMOS technology) impede their
usage for high-Q filtering applications.
To circumvent the aforementioned problems, two filter design topolo
gies, aggressive Gm (AGm) filters and passive RLC filters with Q-enhancement
circuitry, are proposed. The proposed topologies have advantages including
4
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reference
Lowpass
Filter
Phase
Detector
Master filter:
VFO
Slave filter
Figure 1.3: Master-and-slave tuning scheme with a VCF.
gigahertz- band operation, high signal selectivity, and full integration with other
analog and digital circuits on the same chip. In addition, the proposed filters
provide a certain range of tunability which allows tuning circuitry to work prop
erly.
Another important consideration in the design of analog VLSI filtering de
vices is that the performance of fully integrated filters usually deviates from the
design specification due to the fact that exact value components are not obtain
able to guarantee the characteristics of the filters [44]. The problem becomes
severe or even unacceptable when the filters are used in narrow-band applica
tions. In addition, active devices are more sensitive to temperature fluctuation
than passive elements, leading to large performance errors. A solution to this
problem is to use an accurate external reference signal (e.g., system clock) to
tune filters.
5
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Two tuning approaches have been reported: indirect tuning and direct
tuning [55]. The master-and-slave scheme [5][35][7], as illustrated Figure 1.3,
is a widely used tuning circuit that is based on the indirect tuning approach
for low- to medium-Q video-band active filters. The master filter is designed
to model all the relevant behaviors of the slave (i.e., main) filter. The master
filter, essentially the duplication of the slave filter, can be a voltage-controlled
oscillator (VCO) or a voltage-controlled filter (VCF) [59] type of configuration.
An accurate external signal freference is employed as a reference for the tuning
loop that includes the master filter. The master filter will be finally tuned to
the desired resonant frequency by using the phase-locked loop technique, and
the resulting frequency-controlled voltage V f _ t u n in g is simultaneously applied to
both master and slave filters. Q tuning can be achieved in a similar approach
[55]. Consequently, the accuracy of the indirect tuning heavily relies on the
matching and tracking between both filters. However, parasitic effects in the
gigahertz-band CMOS high-Q filter are very large and cannot be matched well.
In addition, the cost of the extra tuning circuitry needs to be minimized, such
as the silicon area, noise, and power dissipation. We also need to consider
the possible interference between the reference signal freference and the slave
filter. Alternatively, we may consider the direct tuning approach [58]. The basic
idea for the direct tuning system is to tune one filter (filter A), while another
replica (filter B) functions and processes the desired incoming signals. After a
6
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t
Figure 1.4: Transmitting (TX) and receiving (RV) modes for a transceiver.
period of time, we switch filter B to tuning activity, but filter A receives the
incoming signals. The switching between filters is because the control voltage
drifts with time, and thus the control voltage needs to be refreshed (or tuned)
periodically. One disadvantage of this approach is that the incoming signals
must tolerate a series of the short switching times when switching from one filter
to another, which might be unacceptable for high performance communications.
Besides, another replica of the filter is necessary for this tuning approach to
work, increasing silicon area and power dissipation.
Fortunately, current mobile communication devices typically use time-
division multiple access (TDMA) to enable burst-mode transmission and recep
tion, as shown in Figure 1.4, to overcome the limited isolation between receiving
and transmitting paths, thus allowing us to directly tune filters in the receiving
path while the filter is in the TX mode, and vice visa. The tuning approach we
proposed, called synchronous rectification (SR) tuning, solves the matching and
7
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tracking problems of indirect tuning, while eliminating the additional copy of
the filter needed for direct tuning. Consequently, several reference signals can
be used to tune an on-chip filter based on required filter specifications without
interfering with main receiving signals.
One RLC filter and five AGm filters, including one lowpass filter, one
image-reject filter, and three bandpass filters, have been demonstrated in this
work. Furthermore, the proposed SR tuning scheme can be applied to the above
filters to correct their resonant frequencies. A gigahertz-band CMOS on-chip
bandpass filter using passive RLC filter with Q-enhancement circuitry as well
as SR tuning has been proposed, analyzed, simulated, prototyped, and tested.
The proposed filter system demonstrated its potential to meet requirements of
current mobile devices.
1.2 R esearch O bjectives
The research objective of this project is to develop new filter topologies with au
tomatic resonant frequency tuning circuitry in the gigahertz operating frequency
range, notably targeting current mobile communication front-end filters. More
detailed objectives are stated as follows:
® Develop continuous-time filter topologies capable of operating in the gi
gahertz frequency range with a high quality factor in CMOS technology -
The tunability of the filter is highly desirable due to the resonant frequency
8
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and quality factor being sensitive to device parameter deviations. A wide
tunability in filter design is also desired to facilitate automatic tuning cir
cuitry to work properly for the largest performance deviation. In addition,
the filter topologies have to be versatile enough to implement other filter
ing functions, e.g., lowpass, bandpass, highpass, and notch filterings. To
maximize the integration level, off-chip capacitors and inductors cannot
be used in the design.
• Develop an automatic on-chip tuning scheme to correct the resonant fre
quency of the filter - Automatic tuning circuitry is required to bypass the
difficulties related to aging, manufacturing, and temperature variations in
order to be practically utilized in portable communication devices.
1.3 O rganization of D issertation
This dissertation consists of six chapters. Chapter 1 gives a general introduction
to current high-frequency filter design to provide the motivations and objectives
of this work. Chapter 2 describes the research background of three popular fil
ter design topologies and traditional filter tuning approaches. We also point
out their basic limitations in gigahertz-band applications. Chapter 3 deals with
the analyses and designs of the proposed filter topologies and a new automatic
9
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tuning scheme. Additionally, the designs of monolithic varactors and induc
tors in CMOS technology are discussed. Chapter 4 demonstrates the testing
results of a 1.15GHz CMOS filter with tuning circuitry. Chapter 5 addresses
the importance of this work to academia and industry. Finally, Chapter 6 draws
conclusions and discusses further research directions.
10
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C hapter 2
R esearch Background and P roblem s on
C ontinuous-T im e Filters and A utom atic
Tuning
2.1 Introduction
Driven by the advance of very large-scale integrated (VLSI) technology, the
rapid migration to digital CMOS digital technology [32] in commercial prod
ucts has generated intense interest in both academia or industry to implement
virtually all circuits on the same chip. The impetus to use CMOS technology
is primarily due to its low cost compared with Bipolar, GaAs, and SiGe tech
nologies. The trend in digital circuits is to reach high levels of integration, but
designers have found it difficult to achieve similar levels of integration in analog
circuits. In particular, high performance and high selective analog filter de
sign usually is an obstacle to integration with other circuits due to the limited
11
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frequency response and nature of sensitivity to the process and temperature
variations.
In telecommunication applications, analog filters ranging from a few kilo
hertz up to several gigahertz are required. The progress in extending the in
tegrated active filter frequency range has not, however, kept pace [59]. One of
the most difficult challenges lies in the radio frequency (RF) front-end bandpass
filter design as far as the speed attribute and the dynamic range are concerned.
This type of filter is required to function at sub-gigahertz frequency range or
above with a very high quality factor. Furthermore, this filter is located at
the first stage of the receiver, so its noise and distortion contribute most to the
whole system. Therefore, low noise and low distortion are critical design factors.
Unfortunately, current state-of-the-art monolithic active filter implemen
tations only have a low hundred megahertz frequency range and CMOS on-chip
passive inductors in RLC tank filters cannot be obtained with sufficiently high
Qs due to lossy parasitic resistance and capacitive coupling to the substrate
[38] [18]. In addition, the inductor models are not accurate enough for narrow
band applications in monolithic CMOS technology. Another issue is that the
design of the automatic tuning circuitry against process and environmental vari
ations has not been fully exploited yet, leading to possibly large performance
errors or even circuit oscillation. Under such a circumstance filtering elements
are usually built as external devices such as ceramic filters or surface acoustic
12
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wave (SAW) filters. The properties of these discrete filters are relatively sta
ble and reliable with respect to environmental changes. Nevertheless, they are
produced in different material and cannot be integrated with other CMOS or
Bipolar circuits.
Analog filters are plagued by high sensitivity to device parameters and
temperature variations. To guarantee the performance of the filters, the extra
tuning circuitry is inevitable to stabilize filters’ operation. In addition, after
high-Q filters are manufactured, the tuning system must perform self-tuning
automatically since the filter performance is extremely sensitive to environmen
tal changes, e.g. temperature fluctuation, power supply variation, and aging.
Traditional one-time Post-process tuning cannot correct the above variations.
In the following sections, we introduce several popular continuous-time
filter design approaches and identify their merits and drawbacks. First, a
conventional Op-Amp based active filter is introduced. We then discuss a
transconductance-capacitance (Gm-C) filter and detail its basic operation for
the high-speed design. The description of a passive RLC filter follows. To sim
plify comparison and discussion, a second-order bandpass filter is analyzed in
order to clearly demonstrate different characteristics among these filters. Em
phasis is placed on discussing their high-frequency operation capacities. Two
tuning approaches are then discussed: indirect tuning and direct tuning. The
most well-known and m ature indirect tuning strategy is based on phase-locked
13
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loop (PLL), which will be introduced in section 2.3.2. The direct tuning scheme
is seldom seen in the literature due to the temporary switching time problem
in switching signals for tuning. However, in view of the wireless standards in
current mobile telecommunications, direct tuning is obviously a better candi
date for the gigahertz-band tuning design. This tuning scheme will be discussed
briefly in section 2.3.3 and in detail in section 3.2.
2.2 C ontinuous-T im e F ilter O verview
2.2.1 A ctiv e R C O p-A m p B ased F ilters
In general, monolithic filter realization uses a state-variable filter architecture
consisting of inverting integrators [27]; a typical second-order filter is shown
in Figure 2.1. Two essential observations can be made regarding this basic
filter architecture. First, integrators are basic building blocks. Accordingly, the
attributes of integrators directly affect the characteristics of the filter, which
means non-ideal integrators result in performance deviations of the filter.
Second, two global feedbacks are applied to the system and one local
feedback is applied to each integrator cell. The Op-Amp of the integrator cell,
containing parasitic poles and zeros, is designed to be closed-loop stable, but
once the global feedback is applied to the integrators, these poles and zeros
may move closer to the imaginary axis, even to the right-half s-plane, creating
14
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out
V ,
i
out
Figure 2.1: Second-order state-variable filter and Op-Amp integrator cell.
a stability problem. Therefore, there are some stability criteria that need to be
satisfied between the specifications of the integrator and the performance of the
filter system [20]. This nested feedback structure is the major obstacle to using
this topology in high-frequency applications.
It has been shown that to maintain the filter stability the gain bandwidth
product of the integrator has to be larger than two times the product of the
resonant frequency and the quality factor of the filter [4].
Av ubw > 2 u 0Q. (2.1)
15
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This stability criterion puts a very tight limitation on the upper frequency range
and restricts the filter operation to frequencies below 1MHz.
2.2.2 T ranscon du ctance-C apacitan ce F ilters
In analog filter design for very-high-frequency (VHF) operation, transconductance-
capacitance (Gm-C) filters [64] [1] [42] [15] have received considerable attention
not only in academic research but in industry as well. One of the key applica
tions for the large-scale industrial acceptance of the filters is the filter implemen
tation in the read channel of disk drives [42] [36]. Other applications include tele
vision IF filters, decoders in high-definition television systems (HDTV), phase-
locked loops, wireless communication systems, and signal processing related
areas [15] [48]. A high-frequency continuous-time integrator is the basic build
ing block for most continuous-time filters and can be constructed simply by
putting an integrating capacitor on the output port of the transconductor to
form an open-loop configuration, as illustrated in Figure 2.2(a).
The Gm-C filter is the dominant type of filter in applications above tens
of megahertz frequency range. This is due to the fact that the transconductor
is simply referred to as a single stage Op-Amp with only one high impedance
output, and more importantly that this integrator is open-loop in contrast to
integrators in an Op-Amp based active RC filter that has to be compensated to
ensure the closed-loop stability [17], To obtain more thorough insights on the
16
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(a )
w, w, w (log scale)
Vi
Vo
•go
(b)
'i T
< U
0 0
- o
-90
a,
-180
Figure 2.2: (a) Ideal Gm-C integrator, (b) non-ideal Gm-C integrator, and (c)
gain and phase responses of an ideal integrator (dash lines) and a non-ideal
integrator (solid lines)
limitations of Gm-C filters, we explore their basic theory and point out their
shortcomings in RF applications in this section. A second-order bandpass filter
is used to illustrate the effects of non-idealities in the integrator.
Effects of Finite Gain and Excess Phase
As mentioned earlier, a filter usually consists of many integrators, so the charac
teristics of the integrator building block is key in determining the performance of
the filter [20] [25]. Figure 2.2(a) shows an ideal Gm-C integrator. This transcon
ductor can be viewed as a voltage-controlled current source with the output
current equal to gm ry, and exhibits infinite input and output impedances. In
17
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addition, it has an infinite bandwidth. The transfer function of an ideal inte
grator is equal to
and the unity-gain frequency is
The transfer functions of an ideal integrator are shown in Figure 2.2(c) (dashed
lines). The circuit has an infinitely high DC gain and an exact — 90° phase
shift at all frequencies. We then introduce variations we encounter in practical
circuits. To simplify the expression of parasitic effects, we assume that only one
parasitic zero exists inside the transconductor, as illustrated in Figure 2.2(b).
Therefore, the parasitic effects of the transconductor are simply characterized
by a parasitic zero u> 2 and a non-zero output conductance g0. The transfer
function of the non-ideal integrator is given by
(2.2)
U M _ i - 1
(2.4)
where
c
^ u n i t y
18
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A 0 is the finite DC gain, aq is the dominant pole, ujunity is the unity-gain fre
quency, and uj2 is the parasitic zero in the transconductor, which is located at
much higher frequency than uq. If the transfer function of the integrator is
expressed as
A n < (w ) = X(v)+j Y(o jY ( 2 ‘5)
we then define the quality factor of the integrator as
(2.6)
Therefore, the quality factor of the integrator in Equation (2.4) can be simplified
(2.7)
as
1 uq to
__
Qint{w) U U J 2 '
Please note that the finite DC gain and the parasitic zero modify the ideal fre
quency response and deviate the phase response of the integrator from — 90°
at the unity-gain frequency, leading to a finite Qint , shown in Figure 2.2 (c).
The phase shift from the ideal — 90° arises from the dominant pole uq and the
parasitic zero u> 2 creating phase lead and phase lag. Excess phase is a major
problem in Gm-C filters and restricts their frequency range only up to low hun
dred megahertz. As we will show below, this excess phase substantially governs
the filter stability, notably when aggressive designers desire to implement Gm-
C filters with a reasonable high quality factor above one hundred megahertz [45].
19
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Parasitic Capacitances
A practical transconductor has parasitic capacitances associated with the in
put port, output port, and other internal nodes. In low-frequency applications,
parasitic capacitances can be safely neglected because they are much smaller
than an integrating capacitor c. However, in high-frequency applications above
tens of megahertz, parasitic capacitances play important roles in determining
the unity-gain frequency ,u )unay. As a result, some of the parasitic capacitances
need to be incorporated into the integrating capacitor c to calculate the actual
(jJu n ity location. Remember that wunny of a non-ideal integrator is given by the
expression gm ~g° , so to increase L O unity we could decrease the capacitor c, but
this leads to the parasitic capacitances being a larger percentage of the overall
capacitance. Alternatively, we could increase gm or decrease g0\ however, either
results in a larger transconductor size, which in turn means larger parasitic ca
pacitances. Practical Gm-C filters operating between 22MHz to 98MHz have
been reported with parasitic capacitances that contribute from 25% to 100% of
the total integrating capacitance [43].
N on-idealities of Filters
A second-order bandpass filter is depicted in Figure 2.3 [32] and the transfer
function is
20
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bp__out
lp_out
S m 3
£ m 4
Figure 2.3: Biquad Gm-C filter
V bp^ ou t (^)
( 9 m l
' Cl
Vin{s) S2 + 5 ( ^ ) + (&*)(*»*) ’
(2.8)
and thus the resonant frequency and the quality factor of the filter are expressed
as
I^ 9m3 \ /9m4n
Cl C2
(2.9)
and
1 9m3 9mA Cl / Ci
tybp — ~ — \ / — ( ) ■
9m2 y C 2 < 7 m 2
(2 .10)
If we take non-ideal effects (same finite DC gain and parasitic zero for each
transconductor) into account, we obtain new transfer functions for the resonant
frequency J 0 and quality factor Q 'b assuming gol— go 2 =g 0 and go3, go 4 < C g0
i. 1 u ,9 ° 9m 2
U0 ~ + ----p — + --------
^2 bjbp C i C 2
(2.11)
21
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_L ~ JL + . 2 J ^ 1 _ = _L + 2 ( 2.1 2 )
Q b p Q b p ^ 2 Q b p Q i n t { , ^ o )
From the above equations, it can be seen that uj' 0 and Q 'b p deviate from ideal
u >0 and Qbp ■ Of particular importance is that Q 'b p is closely related to the
quality factor of the integrator Qint at oj0. Consequently, to guarantee the
filter characteristics, a quasi-ideal integrator is required. Some compensation
techniques have been reported to have a — 90° phase shift at tu0, resulting in
infinite Qint(oo0) and thus Q 'b p = Qb p [48]. Note that Equations (2.11) and
(2.12) are approximation and only valid for low- to medium-Q filters.
We can use Routh-Hurwitz criterion [21] to assess the stability require
ment. It is shown that to sustain the filter stability, the parasitic pole needs to
be at least twice the product of the unity-gain frequency and the quality factor
of the filter [4]:
^pole ^ 2 LOunity Q • (2.13)
Equation (2.13) shows that the parasitic pole in the transconductor is propor
tional to the u )U nity and Q of the filter. For example, if a resonant frequency of
1GHz is desired and Q is 10, then the parasitic pole needs to be located at a
minimum of 20GHz to ensure stability. This equation is only an approximate
requirement for the stability.
However, the parasitic poles and zeros impose a much tighter range for
the unity-gain frequency, ujunny, of interest if the performance of the filter has to
22
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meet the original design specification; this is because the circuit characteristics
are significantly susceptible to the excess phase.
In general, to avoid errors in the filter performance, a sufficiently high
integrator DC gain is required and parasitic poles and zeros should be located
at frequencies much higher than the cutoff frequency of the filter in order to
keep the phase shift of the integrator close to — 90° at the unity-gain frequency.
This implies that roughly at least a 40dB DC gain and parasitic poles or zeros
located at least a factor of 100 beyond the cutoff frequency of the filter. This
is a strong constraint for filters at very high frequencies: the transconductor
necessitates parasitic poles of approximately 100GHz if 1GHz cutoff frequency
is required, which is unreasonable for current CMOS technology.
Moreover, there exist two major problems that need to be faced in using
Gm-C filters: performance tuning requirement and limited dynamic range. The
characteristics of Gm-C filters rely on transistor parameters, but these param
eters are not guaranteed due to fabrication process variations: 30% parameter
tolerance is not unusual. Tuning circuitry for tounity and Qbp is therefore re
quired, but tuning is extremely challenging to perform in gigahertz circuits.
High dynamic range is difficult to achieve in Gm-C filters due to trade-offs
between the speed, linearity, and noise performance. Typically, only a 60 dB
dynamic range can be reached. These two physical limitations prevent their
acceptance in the front-end filter design of a transceiver.
23
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Buffer
out
(a )
-AAAr
(b)
Figure 2.4: (a) RLC filter and (b) small signal analysis.
2.2 .3 R LC F ilter
An RF tuned amplifier is based on a conventional combination of a passive
capacitor and inductor to obtain a second-order bandpass transfer function,
shown in Figure 2.4(a). The output port of transistor M l is in shunt with a
capacitor and an inductor, and delivers the input voltage signal to a voltage
buffer. A simplified small signal model is shown in Figure 2.4(b), where gmi is
the transconductance of the transistor M l, L is the equivalent inductance of the
inductor, C is the total capacitance at the drain of the transistor M l, including
all parasitic capacitances and Cvar, and gtot is the output conductance g < isi of
the transistor Ml in shunt with the reciprocal of resistor R and the equivalent
parallel conductance gip of the inductor.
24
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Investigation of conventional VLSI devices demonstrates that on-chip in
ductors are usually smaller than 3GnH with a typical Q approximately equal
to 3. Thus, the equivalent parallel output conductance of a inductor at radio
frequencies, 900MHz for instance, is fairly large compared with the output con
ductance of the transistor M l, leading to gtot = gdsi + c ? ;P + ~ giP, assuming
9 ip > 9 dsi and It can be shown that the voltage gain is
A (s) = = ............. sLJ™. ____ ( 2 14)
M } Vin(s) s2LC + s Lgtot + 1 ’ 1 ' j
and we obtain
1 n _ 1 C ~ 1 C - 1
r Qtot — \ r ~ \ T — j ~ ■ (2.15)
LC Q tot V L Q ip V L gipu )0 L
The quality factor of a parallel equivalent circuit of the inductor is defined as
QiP = r- (2.16)
gipixi L
Therefore, Qtot = Qip at the resonant frequency ui0. From the discussion above,
we know that the overall quality factor of the filter is mainly determined by
the quality factor of the inductor. A monolithic inductor in current CMOS
and Bipolar technologies cannot be fabricated with a high quality factor, and
the prediction of the quality factor of an inductor is difficult [51]. Losses in
25
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monolithic inductors result from three mechanisms: metal resistance, magnetic
coupling, and capacitive coupling to the substrate [23]. In addition, a monolithic
inductor occupies a large silicon area even for an inductor as small as a few
nanohenries.
It can be shown that to achieve a required voltage gain for the front-end
of a transceiver, the power dissipation consumed by the transistor M l is quite
large and is unacceptable in modern hand-held systems. Process variations are
obviously problems in this topology for narrow-band applications. Because the
resonant frequency is determined by the values of the capacitor and inductor,
the filter must have a tuning capability to compensate aforementioned manufac
turing and environmental variations. This filtering approach is usually applied
to off-chip discrete IC applications since discrete inductors with high quality
factors can easily be obtained. To tackle the low-Q problem in integrated in
ductors, we can introduce a negative resistor to compensate the resistive loss,
thereby boosting the quality factor and enhancing the selectivity of signals. An
other advantage worth noting is that this approach is suitable for operating at
gigahertz frequency range because the required inductor value is on the order
of several nanohenries, which is feasible to be implemented in current VLSI
technology.
26
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2.3 O n-C hip A utom atic Tuning Schem e O verview
2.3.1 In trodu ction
A critical problem in today’s integrated analog circuits is to guarantee the accu
rate performance of circuits. While the fabrication variation and temperature
dependence of analog filters might be tolerated in broadband applications, un
fortunately analog filters are usually employed in narrow-band operation, which
has to meet stringent requirements for locations of resonant frequencies and
shapes of the filter transfer function. The most prevalent and industry-accepted
resonant frequency tuning is based on the constant transconductance (constant-
gm) and phase-locked loop (PLL). In Gm-C filters, the difference between these
two techniques relies on the tolerance on the time-constant value ” of an in
tegrator, shown in Equations (2.9) and (2.10) demonstrating that uj0 and Q
are functions of the time constant. Based on current CMOS technology, gm
contributes approximately 20% of the time-constant fluctuation, and an inte
grating capacitor c, including parasitic capacitances, accounts for another 10%
variation, leading to a possible 30% time-constant error. If a 10% variation can
be tolerated, then the constant-gm technique can be used. In the case of high
precision or high-frequency design where parasitic capacitances account for a
large percentage of the integrating capacitance, then PLL is mandatory to set
the required — . An additional point is worth noting: Equation (2.8) is the
27
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transfer function of an ideal second-order filter, so it seems that fixing u 0 by
setting ^ also determines the quality factor Qbp. However, after we factor in
non-idealities, Equation (2.8) is not valid, but it can be used as a guideline for
the design of low-frequency filters with low- to medium-Qs.
Tuning the shape of the filter transfer function is very challenging as it
includes the quality factor and amplitude tuning. Most filter tuning circuitry
in the literature assumes that amplitude tuning is equivalent to quality factor
tuning. Therefore, fixing the amplitude of the output signal also accomplishes
quality factor tuning. However, the transfer function of the filter is better
characterized by the resonant frequency, quality factor, and amplitude (voltage
gain). In cellular phone applications, a frond-end bandpass filter with a low
noise amplifier requires a resonant frequency located at 900MHz, quality factor
of 30, and voltage gain of 15dB. Therefore, one more tuning circuitry needs to
be considered in this regard.
In high-frequency and high-Q filter design, the techniques above are not
suitable any more due to unacceptable mismatching and incomplete tracking
between a master and slave filters. These tuning schemes will be explained in
the following section.
28
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Gm-C filters
tuning
Figure 2.5: Indirect tuning scheme.
2.3.2 Indirect T uning Schem e
A common approach to tune filters is to use an indirect tuning scheme,
shown in Figure 2.5. Filters are implemented using transconductors, and we
built an extra matched transconductor that is tuned. Then we used the same
control voltage Vtuning to tune the transconductors in the filters.
One of the constant-#™ tuning techniques is shown in Figure 2.6. The
transconductance is set by an off-chip resistor Rextemal that has a precise re
sistance value and a low temperature coefficient. Here we assume that gm is
controlled by V tuning and is proportional to the change of Vtuning ■ The feedback
of the Op-Amp keeps Vi at virtual ground and makes Ix = ~—-. If the out
put current of the transconductor IQ — gm Vc is larger than Ix, then the excess
29
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R
external
c
AA/V
K
tuning
Figure 2.6: Constant-gfm tuning technique.
current will be integrated by the Op-Amp through the capacitor c; Vtuning de
creases. As a result, the smaller gm decreases I0 until it reaches an equilibrium
state I0 = Ix, leading to gm = „— ----. The external resistor Rextemai can be
-fte x te r n a l
integrated on a chip if we use switched-capacitor circuits to replace Rexternai
[61].
The frequency-locked filtering technique based on the PLL theory was first
introduced by K. Tan and P. Gray in 1977. A second-order filter is used in the
tuning loop since there exist no simple tuning techniques to tune high-order
filters. Two approaches have been reported in the literature: voltage-controlled
filter (VCF) and voltage-controlled oscillator (VCO), as illustrated in Figure
2.7. Presently, this PLL tuning technique is regarded as a more precise and
popular strategy to achieve frequency tuning in high-frequency integrated filter
design.
30
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reference
Master filter: VCO
Master filter:
VCF
Slave filter
Slave filter
Q-tuning loop
Filter^
Lowpass
Filter
Lowpass;
Filter
Phase
Detector
Phase
Detector
Integrator
Amplitude
Peak
Detector
Figure 2.7: (a) VCF and (b) VCO tuning techniques.
The basic ideal of the VCF tuning technique is to duplicate a biquad filter
(master filter) from a high-order filter (slave filter) composed of biquad filters
in a cascaded fashion; when the master filer is tuned, the controlled voltage
Vf_tune is applied to tune the biquad filters inside the slave filter. We know that
a second-order filter usually has two outputs: one is the bandpass output with a
0° or 180° phase shift, and another is the lowpass or highpass output with a 90°
phase shift with respect to the input signal at the resonant frequency u0. The
bandpass and lowpass outputs at the resonant frequencies in Figure 2.3 can be
expressed as
Ab p_0U tM = (2.17)
9 m 2
and
= - j (2.18)
WQ 9m 2 c 2
31
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The property of a 90° phase shift in Equation (2.18) is the key for VCF tuning.
In Figure 2.7(a), an error voltage is generated by a phase detector and used to
adjust the resonant frequency of the VCF to reduce 0. It can be shown that for
a small 0, Vf_tunin g — Vjf Kvcj Kpd Kip 0, where K vcf is the VCF output/input
voltage gain, Kpd is the phase detector conversion gain, and Kip is the lowpass
filter voltage gain. The resulting Vf_tunin g is then used to adjust the transcon
ductances of the integrators in the master filter and ideally 0 is equal to zero.
In reality, the phase error, 0: depends on the loop gain of the feedback system
and the offset voltage of the phase detector circuit itself. Generally, 0 can be
a small value, but cannot be equal to zero. As a result, a residual phase error
results in a frequency error, leading to incorrect ui0 tuning. A 2° phase error
resulting in 1% frequency error for a low-Q filter has been reported [35].
The VCO tuning technique eliminates the residual frequency problem by
incorporating two integrators into an oscillator, as illustrated in Figure 2.7(b),
where a Q-tuning loop is included. If properly designed, the PLL will even
tually lock the oscillation frequency u 0 to the external frequency, uye/ erence.
Please note that since the VCO consists of two basic integrators with the same
transconductance gm and integrating capacitor c, the VCO will oscillate at the
resonant frequency uj0 = ^ with a 90° phase shift for each integrator. This
in turn compensates non-ideal integrators to have 90° phase shifts at u0, which
leads to integrators with infinite integrator quality factors at a certain frequency
32
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range. As discussed earlier, Equation (2.12) shows that this property leads to
an interesting result: the final quality factor of the designed filter is equal to
the ideal quality factor of the ideal filter, Q 'b = Qbp , and thereby Q tuning
has been achieved. We would like to point out here that Equation (2.12) is
an approximation and is only applied to filters with low- to medium-Qs. The
Q-tuning loop in Figure 2.7(b) guarantees the oscillation and controls the am
plitude of the VCO so that the VCO oscillates with a constant amplitude and
transistors in the integrators operate in the linear range. When the master filter
has correct uj0 and Qint, the integrators in the slave filter also have correct o o 0
and Qint since they share the same control voltages Vf tuning and Vqtuning ■
Although new tuning techniques will be developed in the future and might
be able to ideally tune the resonant frequency and quality factor of the master
filter, the mismatch and temperature variation between the master and slave
filter might be severe enough that the slave filter has totally different character
istics than the master filter, especially in high-frequency high-Q filter design. An
advantage of this indirect tuning scheme is that the slave filter is continuously
tuned, so the slave filter receives incoming signals all the time.
2 .3.3 D irect T uning Schem e
Instead of relying on matching and tracking between the master and slave filters,
Y. Tsividis proposed a direct tuning scheme in 1981 [58], shown in Figure 2.8.
33
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reference
signal _out
signal _in
Tuning
CKT
Tuning
CKT
Filter 2
Filter 1
Figure 2.8: Self-tuned filter.
Filter 1 is the exact replica of filter 2 and the basic operation is stated as follows:
after power up, filter 1 performs u 0 and Q tuning using a tuning signal, freference-
When the tuning process is done, filter 1 holds the tuning voltage and receives
incoming signals, Vsignaiini to provide the filtering function, but at the same
time filter 2 performs the same u >0 and Q tuning processes. Since the tuning
voltage of filter 1 is held by a capacitor, it changes with time; therefore, filter
2 needs to take care of the filtering task and put filter 1 into the tuning mode.
The switch at the output terminal needs to be synchronized with the switch
at the input terminal, so the system can deliver the input signal to the output
terminal at proper time periods.
To take advantage of this tuning scheme, the incoming signal must tolerate
a series of interruptions when switching from one filter to another. Therefore,
34
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the settling time is a critical issue in designing tuning circuitry. Another disad
vantage is the larger silicon area and power dissipation due to the requirement
of an extra copy of the filter and tuning circuitry. However, the system is capa
ble of performing direct tuning of the filter itself, eliminating the matching and
tracking problems in the indirect tuning scheme.
In current mobile communications, signals are received and transmitted al
ternatively, performing a burst-mode operation. In this application, the receiv
ing path only operates in certain time slots, allowing the direct tuning scheme
to tune the filter when the receiving path is in the “sleep” mode [14]. The
same conclusion applies to the filters in the transmitting path. This is the basic
tuning theory we adopt in this work.
35
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C hapter 3
T heoretical Foundations and D esign Techniques
3.1 G igahertz-B and F ilter D esign
3.1.1 In trod u ction
In heterodyne receivers, the development of a low noise amplifier (LNA) with a
monolithic bandpass filter, shown in Figure 3.1, has received intense attention,
and several approaches have been reported in the literature [31] [34], At the
present time, discrete components are employed in commercial wireless prod
ucts, but these off-the-shelf components require additional I/O pins for intercon
nection and often need impedance matching networks to work properly. Further
more, circuit performance may be limited by parasitic elements associated with
semiconductor packaging. Accordingly, On-chip filters are greatly demanded.
Gm-C filters [59] are the dominant integrated high-speed continuous-time fil
ter implementations and are widely used in tens of megahertz frequency range.
However, excess phase and limited dynamic range problems [4] gives Gm-C filers
little advantage in wireless applications.
36
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:v tv,j '.election Low no1 sc
filter Lirp.ilk”-
Mixer
Local oscillator
Figure 3.1: Bandpass filter, LNA, and image-reject filter in a receiver.
Unlike Gm-C filters or conventional Op-Amp based filters, which are fun
damentally frequency-limited implementation topologies [44] [50], the proposed
topologies in this work essentially extend the filters’ operation to gigahertz fre
quency range with reasonably high quality factors. Two gigahertz-band filtering
topologies were proposed: aggressive transconductance (AGm) and passive RLC
filters with Q enhancement filters.
The construction of a Gm-C filter is based on known transconductances
and integrating capacitances, whereas the AGm filter is based on only transcon
ductors to form the filtering functions. The integrating capacitances are actually
embedded within transistors, primarily consisting of parasitic capacitances of
the transistors. Since the filtering function depends on the characteristics of
the transistor, the filter can operate at very high frequencies. Here we use “ag
gressive” to emphasize its superior frequency response and distinctive design
procedure. Instead of using traditional pen-and-pencil calculations to approx
imate the filter performance, computer simulation is mandatory a priori for
37
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the AGm filter design because parasitic capacitances cannot be approximated
with reasonable precision. The filters we consider are primarily used in narrow
band applications; thus, (^-enhancement circuitry using a negative conductance
generator (NCG) is employed to increase the selectivity of the filter. It is im
portant to use corner parameters provided by semiconductor manufacturers and
different temperature settings to simulate the filter performance. Moreover, the
performance errors caused by the aforementioned parasitic capacitances are ex
pected and need to be corrected by automatic tuning circuitry. Therefore, the
tuning range is a critical factor in designing the filter system.
Section 3.1.2 covers one basic filter cell and four AGm filters, including
bandpass and lowpass filters, with features of low noise, high gain, RF band
resonant frequencies, and tunable Qs. Their design analyses are similar although
different techniques are employed. Section 3.1.3 demonstrates that this topology
can be extended to design an image-reject filter of the transceiver front-end. The
design of a passive RLC filter is described in section 3.1.4 and an NCG is used
to compensate for the inductor low-Q characteristic [34] [41]. The RLC filter is
chosen as a test drive for the VLSI implementation due to its relative simplicity
and stability compared with AGm filters. Noise performance is an important
consideration that governs the filter design; consequently, noise formulas are
derived as a useful vehicle to minimize the noise generated by the circuit and
its following stages. Other design considerations such as dynamic range and
38
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Vdd
Vbiasl
V ,
O ' out_Jp
Figure 3.2: Basic biquad filter.
transistor sizing are also discussed. In section 3.2, we proposed a new automatic
resonant frequency tuning scheme to compensate the variations of the filter
performance; analytical equations of the tuning system are shown finally.
3.1.2 A ggressive T ranscon du ctance F ilter D esig n
Circuit I. Basic Cell
The basic cell for the filter design is based on a transimpedance converter, illus
trated in Figure 3.2. It transforms the input current to the output voltage
V outJbp at the same terminal, and the architecture is substantially different from
a traditional transimpedance amplifier, which has different input and output
terminals [57]. The current source, hias, is used to ensure correct biasing cur
rents through the circuit. It can be proved through a small signal analysis that
39
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the circuit has a second-order transfer function with a low-frequency zero and a
pair of high-frequency complex poles, which can be viewed as a bandpass filter.
_ ___________________________(c2 + c3) S + g- 2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
s 2 c + s [C l g2 + C 2 (gi + g2 + gmg) + C 3 (gi + gm$)\ + [< ? i #2 + gm5 (#2 + < ? m 3)]
(3.1)
where
c2 — C1 c 2 + C2 C3 + Cl C3 ,
Cl — C g ,s 3 T Cgb3 T Cs^5 ,
C2 — Cgd3 T CgS5 ,
C3 = Cdb3 + Cgd4 + Q M + Cgd5 + Cgb5
9 i
— 9ds5 5
92 = 9ds 3 + 9ds4 ■
ci,c2, and C 3 represent accumulated parasitic capacitances in the circuit, gi and
g2 represent the equivalent output conductances at the source of M5 and the
drain of M3. Thus, we have
Rin{0)
92
9m3 9m *o
(3.2)
40
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Equation (3.2) shows that this negative feedback configuration constrains the
source of M5 to be a very low impedance node, which is much lower than 1 / gm5.
The resonant frequency o o 0 and quality factor Q are
_ y 9m3 9m5 0x
l o 0 ~ - — —— — (3.3)
c
Q « . (3.4)
^ 2 T C 3
Another important observation is that while operating frequencies increase, the
effect of the feedback starts reducing due to the zero in the transfer function
and the impedance level at this node rises, thereby acting inductive. At higher
frequencies, the impedance level drops due to the complex poles generated by
the feedback circuit, and the impedance becomes capacitive at this range of fre
quencies. Consequently, the input impedance R{n exhibits a bandpass behavior
across the full frequency range.
At first glance, the drain of M3 seems to be the only high impedance node
in the circuit, but further investigation proves that M3, M4, and M5 provide
negative feedback, leading to a low impedance node approximately equal to
1/ 9m3 ■
41
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Considering another output Vo u t j p at the drain of M3 in Figure 3.2, the
transfer function is equal to
A / B \ _ VoutJp(s)
A 0utjp\S) — { \
* i n )
S 2 C + s [Cl Q2 + C2 {gi + g2 + g m 3 ) + C3 ( g i + gmh)} + [(3.5)
Equations (3.1) and (3.5) show that this simple circuit has two second-order
filtering outputs: bandpass and lowpass outputs. They both have the same
poles in the transfer functions, and thus share the same resonant frequency and
quality factor. The shortcomings of this filter are that the filter Q is quite low
(usually less than 2) and a strong dependence between the frequency and Q
tuning, leading to difficulties on designing automatic tuning circuitry. However,
both problems can be solved by introducing extra Q-enhancement circuitry.
Circuit II. Sub-G igahertz AGm Filter
The first approach we adopt to circumvent the low-Q and tuning problems is
to introduce another compensation circuit, called negative conductance gener
ator (NCG) [9]. The block diagram of the AGm filter conceptually consists of
four signal processing stages, as illustrated in Figure 3.3. The first stage is a
voltage-to-current converter with features of low noise and input matching to
the antenna. The second stage is a transimpedance converter that transforms
42
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Input Port Output Port
Input Stage
V/I Converter
Output Buffer
V/V Converter
Freq. & Q
Tuning Circuit
Transimpedance
Stage
I/V Converter
Figure 3.3: Block diagram of filter circuit II.
tlie input current signal to the output voltage signal at the same node. It fea
tures low driving input and output impedances at low and high frequencies,
but exhibits very high impedance at the resonant frequency. The third stage
features a resonant frequency and quality factor tuning structure to increase the
signal selectivity of the filter. The final stage is a voltage buffer that delivers the
voltage signal to the following stage without causing a loading effect to the filter
circuit. Figure 3.4 shows the proposed filter with (^-enhancement circuitry. Ml
and M2 comprise the input amplifier stage. This common-gate configuration
not only provides a reasonable noise figure (NF) and input impedance match
ing, but also helps to increase the effective reverse isolation of the receiver. This
reverse isolation is crucial to prevent the signal leakage from the local oscilla
tor to the antenna due to the capacitive coupling and substrate currents. The
transimpedance stage is based on the basic filter cell in Figure 3.2, consisting
of M3, M4, and M5.
43
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vdd
Vbiasl
M5 M4
Vbias8
M 1 1
Vbias3
M9
M 1 3
Vbias2
M6
Vout
M3
V b ia sB o-|
Rs
-j|— , i
M2
M12
M14
Vbias9
M7 M8
M 1
Figure 3.4: Sub-gigahertz AGm filter.
The approach to boost the filter Q is to make the s term in the denomina
tor of Equation (3.1) close to zero and positive, so it does not cause instability
problems. That is
c i Q 2 T- C 2 (gi + 52 + 9m d,) + C3 (gi + gms) > 0 ,
(3.6)
then we have
. , C 2 9m Z + C3) gm5 + 92 (ci + c2) .
g 1 > - ( ------------------ : — -— ............. )
C2 + C3
(3.7)
44
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
and we know that gx is roughly equal to < 7^5 • We then introduce a negative
conductance in shunt with g& s5 and replace gx with g^ s5 + gneg ? where the value
Of gneg is negative
^ (C -2 g -m 3 + C 3 gm5 + § 2 (Cl + C 2) N ^
SW 5 > - ( -------------- ------; ------------— ) - gds5■ (3-8)
C2 + c 3
The NCG is constructed by M6-M9, as illustrated in Figure 3.5. The
principal idea is to generate an out-of-phase output current I0 with respect to
the input current Is, called a positive feedback configuration. M6 is a transistor
that provides a transconductance gain gm 6j and M7 and M8 form a current
mirror that provides an out-of-phase function and a gain if different (W/L)
ratios are employed. M9 provides a required DC current through the NCG,
M5, and the input stage. Assuming gm >> gds for all transistors and ignoring
non-dominant high-order terms, the conductance of the NCG can be expressed
as
_ gm6 < 7 m8 /o qx
y n e g — 5
Q m 7
where gmi is the transconductance of Mi.
This filter is sensitive to parasitic capacitances and any loading effect from
the following stage will modify the circuit transfer function; therefore, an out
put buffer is attached to the output terminal of the transimpedance converter.
Another merit of this output stage is that it also provides a range of the voltage
45
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Vbias3 ® -| M9
lo
Vbias2
Is
t
©
M8
iu M 7
Figure 3.5: Negative conductance generator.
gain or attenuation to suit many different application requirements. In wireless
communications, the output power of the filter needs to be large enough to com
pensate the loss of the image-rejection filter and reduce the noise contributed
by the following stages, but it cannot be so large as to overdrive the mixer and
degrade the third-order input intercept point (IIP 3 ) of the system. In addition,
the output port may need to exhibit a particular output impedance to drive an
off-chip image-reject filter. M il and M12 provide a moderate linearity and gain,
delivering the signal to the output voltage buffer. Ignoring non-dominant high-
order terms, the transfer function of the filter with the NCG is approximately
equal to
2 Qm i 1 c s2 + s A + B
(3.10)
46
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
where
A =
B =
D =
c2 =
C j 92 + C 2 {gi + g2 + gm 3) + c3 (g! + gm5)
c
92
c 2 + C3
Cl C2 + C2 C3 + Cl C3,
Cl — Cgi 2 + C (£ J 2 T Css3 + C3 & 3 + Cs65,
+ C S S 6 T C 9I Q 4” .
+ C 5d9 + C < /& 9 + C asi2 + Cgbu,
C2 — Cfl(i3 + C5S5 ,
c3 “ Q& 3 + Cgd 4 + Cdb4 + Cgd.5 + c gb5,
9ds2 ,
9l ~ ~~2 t " 9ds5 +
+ 9ds9 + gneg ;
92 — gds3 + 9ds 4-
A negative conductance g„e5 is explicitly shown in gx to minimize the resistive
loading at the gate of M3. The zero in Equation (3.10) is related to g2 and can
be reduced by cascading another PMOS transistor or increasing the channel
length of M4.
47
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The resonant frequency of the bandpass filter, lo0 , is given by
(3.11)
Equation (3.11), which has the same expression as Equation (3.3), reveals that
the resonant frequency is determined by transconductances of M3, M5, and par
asitic capacitances. The transconductance of M5 is chosen as a prime candidate
to be tuned by varying Vbias3, whereas Vbiasl remains constant for frequency
tuning. M2 is sized and biased to provide 500 input matching. The Q tuning
is accomplished by varying Vbias2 to tune gm6, as shown in Equation (3.9). An
observation can be made from Equation (3.11) that for the same u > 0, Q can be
independently tuned by varying gn eg without altering the resonant frequency. It
is worth noting that iterative tuning of Vbias2 and Vbias3 is needed to maintain
the same current through M5 for the same u > 0.
Noise determines the smallest input signal that the circuit can effectively
process. In RF design, Noise Figure (NF) is used as a figure of merit to assess
the noise performance. If only thermal noise is considered, the NF can be
approximately expressed as
NFb p «
48
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I ----------------- T (jm 9 +
9mQ 9ml2 3ml0
(3.12)
In the above equation, Rs represents the output impedance of the preceding
stage and is usually fixed at 500, and 7 is the coefficient of the channel thermal
noise. As a result, NF can be minimized by properly adjusting the transcon
ductances of the transistors: increasing gm2, gm3, gm6, gm7, gml0, and gml2]
decreasing gml, gm3, gm4, gm5, gm8, and gm9. However, for fair comparisons,
noise performance is evaluated by maintaining the same negative conductance
gn eg and resonant frequency uj0, as indicated in Equations (3.9) and (3.11), re
spectively. Conflictions exist in determining some of the transconductances,
but they can be optimized through computer simulations. Transistor M2 of the
input stage plays a critical role in the noise performance and a large transis
tor size W /L is required. But with the constraint of 500 input matching, gm 2
is roughly equal to 1/50. The most critical noise contributions are caused by
M l, M3, and M5. A reasonable low noise can be obtained by minimizing the
transconductances gmi and gm$, but enlarging gm 3 for the same uj0. For the same
bias current, a better strategy to minimize the transconductance is to increase
the gate-to-source voltage of a transistor without using a large transistor size,
resulting in smaller parasitic capacitances.
In Figure 3.6, simulations show that by tuning Vbias2 and Vbias3 a filter
with a resonant frequency ranging from 559MHz to 970MHz and a Q extending
49
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
38
30
20
m 1 0
>
<
0
-1 0
-20
-24
Figure 3.6: Frequency responses at 559MHz, 877MHz, and 970MHz with high-Q
capabilities.
600M 800M 400M
Frequency (Hz) (lin)
C O
jj,
>
<
16
12
S
o
-4
-8
•12
■ 1 6
■20
• 2g 600M 800M 4 0 0 M
Frequency (H z) (lin )
Figure 3.7: Filter frequency response with cj0=881MHz and Q=34.
50
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to over 400 can be obtained. A circuit has been designed to emulate the receiver
of the North American Digital Cellular (NADC) and AMPS; it shows that by
properly sizing the transistors we achieve a resonant frequency at 881MHz, Q
equal to 34, a 15.7dB voltage gain at oj0, a -12.4dBm IIP 3 , a 6dB noise figure,
and a 52.5mW power dissipation. The linearity of the narrow-band filter is
tested by performing a two-tone test at 879MHz and 883MHz so that the third-
order intermodulation products fall inside the passband of the filter with little
attenuation by the circuit frequency response. By tuning Vbias2 and Vbias3,
the Q variation at 881 MHz resonant frequency is from 1.2 to 400.
The advantage of the filter in Figure 3.4 is that no passive capacitors and
inductors are used for to 0 and Q tuning. But Q tuning by varying Vbias2 also
affects the current through M5, thereby shifting u > 0. This causes unwanted in
teractions between the tuning adjustments, but this problem can be solved in
the following circuits.
Circuit III. Gigahertz Biquad AGm Filter I
Bandpass filter
Figure 3.8 shows a biquad filter with Q-enhancement circuitry [10]. This filter
configuration has superior frequency and tuning capabilities to circuit II be
cause the (^-enhancement circuitry is connected in parallel with the basic filter
in Figure 3.2, minimizing the loading effect. M l and M2 comprise an input
51
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k Vdd
Vbiasl
M 8
Vbias2
M7 M10
M9
M6
Vout_bp
M2
M3
Rs
M1
Vs
Figure 3.8: Gigahertz AGm bandpass filter.
cascode common-source (CS) configuration. The reason to choose the CS con
figuration over the common-gate (CG) configuration shown in Figure 3.4 is that
a better isolation between the input and output terminals can be achieved for
high impedance loading, which is usually true for high-Q filters. However, extra
components such as inductors or capacitors are required for impedance match
ing in the CS configuration. Based on circuit I, the basic components of the
filter are formed by M3, M6, M7, M8, and M10.
Assuming gm g < is for all transistors and ignoring non-dominant high-
order terms, the bandpass filter transfer function can be expressed as
= y < ," T ,(,i)
vs{s)
52
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
9ml ( c 2 + C 3) S + D
s2 + sA + B ’
(3.13)
where
A
B
D
Q m & (*?m3 C 2 T 9m,7 C 3) 9m3 9m7 C 4
9 m 6 C
9 m 3 Q m 7
— 1
C
9ds
c 2 + c 3
c = c \ c 2 + c 2 e 3 + Ci c 3 ,
Cl = C5 d2 + C d b 2 + C g s S + C g b 3 + C s b 7 + C g d 9 + C d b 9 5
C2 — C g s7 '>
c 3 = Cd66 + Cff67 + C5 rf7 + Q m o + Cp d io ,
C 4 — C^53 -f- C gj,4 -|- C ^ s 4 -f- Csb Q “I - Cg,
fjd.zH 9ds! 0 || 9ds6 9ds3 ( fJdsA T fjdso )
fi'mlO 5W4 * 7m 6
Of particular importance in the above representation, c4 is a Q-enhancement
poly-silicon capacitor cq in shunt with parasitic capacitances at the drain of M3.
The resonant frequency and the quality factor of the bandpass filter are given
by
\ / 9m3 9m7 / 0 \
u 0 = ------- — , (3.14)
q 9m6 c yj9m3 9m7 ^
*?m 6 (53
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Equation (3.14) arrives at the same conclusion as Equations (3.3) and (3.11):
the resonant frequency is determined by gm3 and gm7. Here gmr is chosen for
frequency tuning by varying Vbias3, whereas other bias voltages remain con
stant. An observation from Equations (3.14) and (3.15) is that Q tuning can
be achieved by varying cg, thereby changing c4 without altering the resonant
frequency. Simulations show that Q increases from 2.45 to 980 at the resonant
frequency at 1.5GHz by including a capacitor cq equal to 0.6pF, and the fre
quency deviation is only 15.7MHz. The low-frequency zero entailed by gds in
Equation (3.13) can be modeled as the series resistance of a realistic inductor
in a passive LC filter. This zero is minimized by a cascode stage formed by M8
and M10, and the feedback stage constructed by M4, M5, and M6.
Further insight can be gained by considering other high-frequency para
sitic poles and zeros which are not shown in Equation (3.13) due to analytical
complexities. Assuming the basic feedback loop is broken, simulation shows that
increasing cq and Vbias2 generates more phase shift at the output unity-gain
frequency because the parasitic poles/zeros tend to move to lower frequencies,
thereby decreasing the phase margin of the open-loop circuit and boosting the
quality factor of the closed-loop circuit [16]. Consequently, the Q-enhancement
techniques result from two approaches: adding a poly capacitor cq and tuning
Vbias2. In this design, we compromise both approaches by selecting a 0.38pF
capacitor and tuning Vbias2 together to reach a wide Q tuning range at widely
54
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
5 0
(
S ' 40
" O
C L
CD
> '
<
3 0
20 - - I --------
10
-10
2G 1G
Frequency (log) (HERTZ)
Figure 3.9: Independent Q tuning of the AGm filter with a center frequency at
1.5GHz.
spaced resonant frequencies. Figure 3.9 shows that independent quality factor
variations from 4.8 to 1017 at 1.5GHz can be obtained by tuning Vbias2 from
2V to 3.385V, and the resultant resonant frequency deviation is 15MHz. Simu
lations depicted in Figure 3.10 demonstrate the potentially high Q (larger than
500) this bandpass filter can achieve at resonant frequencies between 940MHz
and 2.17GHz by varying Vbias2 and Vbias3. If a low-Q filter is required, then
the value of gq must be reduced. Q as low as 1.2 can be obtained in the frequency
of interest.
A two-tone test is performed to evaluate the linearity of a narrow-band fil
ter. We applied two 0.39mV sinusoids at 1495MHz and 1505MHz, and observed
the output spectrum with 1% IM3. The total input-referred noise voltage in
55
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Frequency (log) (HERTZ)
Figure 3.10: AGm filter with Q larger than 500 at 940MHz, 1.5GHz, and
2.17GHz.
the passband of the filter is qual to 0.29uVrms. The dynamic range is thus 63dB
and the power dissipation is 30.5mW.
Lowpass filter
A lowpass filter, shown in Figure 3.11, can be easily modified from the band
pass filter in Figure 3.8. The transfer function of the lowpass filter is similar
to that of the bandpass filter due to the fact that they both originate from
the same closed-loop circuit in Figure 3.2. In addition, the zero of the lowpass
transfer function is located at a much higher frequency than poles; thus, it can
be reasonably neglected in this analysis. In this design, only one transistor M8,
is employed at the output port because the cascode stage generates additional
56
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Vbiasl
Vbias2
M 8
M7
Vbias3 V o u tjp
M 6
M2
M3
Rs
M 1
Vs
Figure 3.11: Gigahertz AGm lowpass filter.
parasitic poles and zeros, deteriorating high frequencies capabilities. Similarly,
assuming gm » gds for all transistors and ignoring non-dominant high-order
terms, it can be shown that the transfer function of the lowpass filter is
Avjp(s) =
Q m l 9 m 3
V ou t^ dp (* ^ )
vs(s)
1
(3.16)
c s 2 + s A + B ’
where A, B, and c have the same symbolic expressions as Equation (3.13).
Accordingly, the resonant frequency lo 0 and the quality factor Q are the same
and given by Equations (3.14) and (3.15), respectively. Similar conclusions are
drawn regarding lo 0 and Q tuning: Vbias3 for lo 0 tuning, and Vbias2 and cq
for Q tuning. Without cq, a lowpass filter with a 2.48GHz resonant frequency
57
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1 8
lO
e
CQ o
-o
a °
I -2
6
10
• 1 4
1 8
22
1 0 0 x 1 0x 1 0 g
frequency (log) (Hertz)
Figure 3.12: Frequency response of the lowpass filter with / 0=2.48GHz and
Q=2.4 (without cq).
and a Q equal to 2.4 is shown in Figure 3.12. But, with cq equal to 0.35pF,
simulation shows that Q greater than 1000 with resonant frequencies between
1.26GHz and 2.3GHz is achieved.
The input-referred thermal noise can be expressed as
inJ,p
4 k T Rs + 4 k T ^ (—— h
9m7 9mS . 9m l
9ml 9m3
4--- 2 f
9ml
9ml
9rnU
9ml
9ml 9mZ
(3.17)
The above equation shows that the input-referred thermal noise can be mini
mized by properly adjusting the transconductances of the transistors: increasing
9m i, 9 m3 and decreasing gm7, gm $, and gm 9. In addition, to maintain the same
resonant frequency, gm 3 and gm7 need to be varied in opposite directions, thus
58
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6 0
50
30
20
1 O
ig
frequency (log) (Hertz)
Figure 3.13: The independent Q tuning of the lowpass filter with a resonant
frequency at 2.07GHz (with cg=0.35pF).
leading to a simple design for u 0 and noise minimization, compared with the
noise representation in Equation (3.12).
A lowpass filter with a resonant frequency at 2.07GHz and Q equal to
31 has been designed to illustrate the feasibility of this filter architecture. The
Q tuning range shown in Figure 3.13 is between 10 to 1256 by tuning Vbias2,
and the deviation of the resonant frequency is 25MHz. The Total Harmonic
Distortion (THD) is obtained by applying a 10MHz single-tone signal in this
broadband lowpass filter without significantly attenuating other dominant har
monic terms, and an lS.4mVrrn s input signal is the maximal input voltage for
1% THD. The total input-referred passband noise is 0.123raK.ms. Therefore,
the input dynamic range is 44dB and the power dissipation is 27.8mW. The
59
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Table 3.1: The performance metrics of the bandpass and lowpass filters with
g = 3 i.
BP filter LP filter
Capacitor Cq 0.38pF 0.35pF
Resonant frequency 1.5GHz 2.07GHz
Q-tuning range 4.8-1017 10-1256
Maximal input swing
for 1% I M3 in BP
for 1% THD in LP
0.39mVrms 18.4mVrms
Total passband noise 0.29 gVrm s 0.123mFrms
Dynamic range 63dB 44dB
Power dissipation 30.5mW 27.8mW
performance metrics of the bandpass and lowpass filters from this section are
listed in Table 3.1.
Circuit IV. Gigahertz AGm Filter II
Circuit III can be further developed by eliminating the extra Q-enhancement
feedback loop and the resultant filter is shown in Figure 3.14 [11]. The cascode
stage formed by M5 and M6 is a key for Q tuning. The input stage has been
designed to provide 500 input impedance matching to the source impedance Rs
without using on-chip or bond wire inductors. A negative feedback loop formed
by transistors M4-M8 simulates an inductor and the inductance can be tuned
by Vbias3. Assuming gm 3 > gds for all transistors and ignoring non-dominant
60
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Vdd
Vbias6 M 8
Vbias5 M7
M4
Vbias3 M3
Vbias4 M6
M2
M5
VouLBP
M 1
V biasl
Figure 3.14: Gigahertz AGm bandpass filter,
high-order terms, the transfer function of the bandpass filter can be expressed
as
AvjbpU
V cm t_6p(s)
vs(s)
9m2 gm6 f a + cz) S + D
2 (gm 6 C 2 + gm 4 c3 c4) s2 + sA + B ’
(3.18)
where
A — 9 m 6
N
(9m6 (A A 9m4 ^ 3 C 4^x
B
D
N
9 m 4 9m 5 9m 6
9m 6 C 2 A g m 4 C3 ' 1
9ds
C 2 + C 3 ’
9m § 9m& C2 C A 9 m 4 9m 6 C -3 C A Qm4 ^3 ^4
61
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
9mA 9m5 C 4 (c\ C 2 " I - C\ C 3 ) < 5 m 4 C 5 [i?m 6 C
+ f r 4 c3 C 4 + 9m5 C 2 + $ m 5 C 4 (C2 + C 3 )],
C2 — Ci C2 + C2 C3 + Ci C3,
Cl — Cgd 2 + Cdb2 + CS(£3 + Q&3 + Cs (,4 + C5S 5,
c2 — c5S 4,
C3 — CgdA “1" ('gdfi H" C^jg -)- Cgd7 H~ C( : //:j7 ,
C4 — CdbS “t Cgs6 H“ Csf>6,
C 5 = C g d S + C g,
$d$5 9ds6 j) 9 d s l 9dsS
9ds
Qmf> Q m l
Ci,C2, C 3, and C 4 are parasitic capacitances in the circuit. C 5 represents an
extra Q-enhancement poly capacitor, cq, in shunt with the parasitic capacitance
between the gate and the drain of M5. gds is the conductance at the gate of M4
and is very small. Consequently, the resonant frequency and the quality factor
of the bandpass filter are given by
/ 9 m 4 . 9 m 5 9 m 6
(jJ o —
V 9m6 ~ f " 9m A ^3 ^4
\f9mA 9m b
(3.19)
(3.20)
q 19mA 9m5 (9m& C -f- 9mA C3 C4) ^ ^ 2 \^)
V 9 rn 6 N
6 2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C O
■ a
c
O
-tt
C-_ _
o
>
— /-i-— i»r-
-20
600M 200M 1G 1.4G 1.8G
Frequency (Hertz)
Figure 3.15: AGm filter with Q larger than 300 at 625MHz, 1.25GHz, and
1.65GHz.
Again Equation (3.20) demonstrates that the resonant frequency is approxi
mately determined by the transconductances of M4, M5, and c. Here, we select
gm4 for resonant frequency tuning by varying Vbias3. Equation (3.21) shows
that the Q can be tuned by varying the capacitor cq in c5 from N without al
tering the resonant frequency. The tuning of Vbias4 has the similar effect as
cq, but is not shown in the proceeding equation due to the analysis complexity.
Similarly, Q tuning results from two approaches: adding a capacitor cq and
tuning Vbias4.
In Figure 3.15, simulations demonstrate the potentially high Q (larger
than 300) this bandpass filter can achieve at resonant frequencies between
63
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
60
50
40
30
A
20
10
1.2G 600M 700M 800M 900M 1G 1.1G
Frequency (Hertz)
Figure 3.16: Q tuning of the bandpass filter with a resonant frequency at
876MHz.
625MHz and 1.65GHz by adding cg and tuning Vbias3 and Vbias4. Figure
3.16 shows that the quality factor varying from 12 to 280 at 876MHz can be
obtained by adding cq equal to 0.28pF and tuning Vbias4 from 3.05V to 2.3V;
the deviation of the resonant frequency is 21MHz, corresponding to a 1.2% fre
quency shift. Figure 3.17 shows that the quality factor varying from 19 to 250
at 1.68GHz can be obtained by adding cq equal to 0.16pF and tuning Vbias4
from 1.9V to 3.55V; the deviation of the resonant frequency is 20MHz, corre
sponding to only a 0.58% frequency shift. Dynamic range is tested by applying
two sinusoids at 871MHz and 881MHz for a resonant frequency at 876MHz, and
1.675GHz and 1.685GHz for a resonant frequency at 1.68GHz, respectively. The
simulated I I P 3 is -30dBm and -31 dBm, and the power dissipation is equal to
64
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1.4G
Figure 3.17: Q tuning of the bandpass filter with a resonant frequency at
1.68GHz.
24.3mW. The dynamic range suffers because of the high voltage gain which
cannot be well controlled due to the trade-off between the noise and dynamic
range considerations.
Considering only input-referred thermal noise in the filter at the resonant
frequency, the noise figure can approximately be expressed as
NFbp — 1 + 7 [gm i Rs +
9 m 2 R s 9 m 2 R s
4 gm4 4 lv2 c4
9m2 Rs 9m2 9m5 ( + 2 + C 3 ) 2 Rs
| 4 ffL c4 A 2
9m2 9m5 9m6 (c2 + C 3)2 Rs
, 4 g2 ds5 9m7 C 4 A 2 U J2 ( 4 9m4 9rn8
---------------- -p.
9m2 9m5 9m6 ^ 2 Rs g 2 m 2 (c2 + C 3 ) 2 Rs
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Table 3.2: The performance metrics of bandpass filters with a designated $=33.
Capacitor Cq 0.28pF 0.16pF
Resonant frequency 876MHz 1.68GHz
Quality Factor 33 33
$-tuning range 12-280 19-250
Voltage Gain at lo 0 37dB 31.4dB
IIP 3
-30dBm -31dBm
Noise Figure 4.8 dB 5.5 dB
Power dissipation 24.3mW 24.3mW
M1-M5 have considerable noise contributions in the above equation; therefore,
the input-referred thermal noise can be minimized by increasing gm5 and de
creasing gm 1, < 7 m 3, and < 7 to4. gm2 is chosed to provide 500 input impedance
matching and cannot be arbitrarily large. In addition, gm 4 and gm 5 must be
simultaneously tuned to maintain the same ui0 for a fair noise comparison. The
larger noise contribution at higher resonant frequencies stems from the fact that
larger gm 4 is required for reaching higher resonant frequencies. Therefore, the
lower the resonant frequency, the lower the noise figure. Some simulation results
are listed in Table 3.2.
The tuning of the voltage gain may be required due to the process and
temperature variations. The DC voltage gain can be obtained as
Avj>p( 0) = / m29ds (3.22)
& gm4 gm 5
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The above equation shows that the gate of M5 has a very low impedance node,
exhibiting low voltage gain at low frequencies. Further analysis shows that the
voltage gain at ui0 can be tuned by changing the DC voltage gain and the zero
location. Therefore, if the voltage gain at uj0 needs to be reduced, we could
reduce the DC voltage gain or increase the zero frequency by increasing gds- To
arrive at this, several related parameters are considered. gm2 remains constant
as mentioned earlier. Increasing gm5 reduces the noise, but it raises the power
level and increases gdS l thus degrading the performance of the gain tuning.
Alternatively, we can increase gm 4 without altering the zero location; however,
this raises the noise level. The voltage gain also affects the linearity of the filter.
Higher voltage gain can saturate the M5 even for small input signal. Therefore,
the noise-gain-linearity trade-off exists and the design requires optimization.
3.1.3 A ctiv e N o tch F ilter D esign
O verview
The biquad filters we proposed thus far are versatile and they can be used to im
plement a tunable notch filter or an image-reject filter in a heterodyne receiver.
Here we use the circuit IV shown in Figure 3.14 to design a front-end image-
reject filter [12] [13]. The image-reject filter originates from a phenomenon that
a mixer downconverts frequency bands (image signals and desired RF signals)
symmetrically located above and below a local oscillator frequency to a same
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sin (w L0 t)
RF
IF
cos ( w L0 t)
sin ( w i02 0 sin (Wj
RF
IF
cos (w
LPF
LPF
LPF
LPF
Figure 3.18: Hartley and Weaver image-reject mixers.
intermediate frequency (IF); therefore, the image signals corrupt the desired
RF signals, mandating an image-reject filter to suppress the image signals. In
contrast, there is no image problem in direct conversion receivers, but problems
with the DC offset and flicker noise have prevented their widespread use.
The desired overall image rejection in most RF systems is typically 70-
lOQdB. In applications using a high IF frequency, considerable image attenua
tion may be provided by a front-end bandpass filter. However, to achieve such
a high image attenuation, the image-reject filter is usually realized by bulky
external passive components. This usually requires an LNA to drive 500 input
impedance of the filter and a mixer to exhibit 500 input impedance. In ad
dition, the passive components generally exhibit gain loss, thereby leading to
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large noise contribution to the system. In the literature [41] [6] [46] [47], mono
lithic image rejection has been demonstrated by employing image-reject mixers
which essentially exploit the Hartley or Weaver architectures [26] [63], depicted
in Figure 3.18. Critical problems with such architectures are that the image sup
pression is very sensitive to gain and phase mismatches between two receiver
paths due to process and temperature variations. In addition, there exists a
secondary image issue for the Weaver architecture if the second downconversion
is a non-zero IF. Therefore, the image suppression is typically in the range of
30-40dB. An alternate approach to achieve substantial image suppression is to
exploit on-chip inductors [44], A monolithic inductorless CMOS notch filter for
RF image rejection is designed in this section to reach a maximal integration
level for RF circuits.
Basic Passive A rchitecture
Consider a series LC resonator shown in Figure 3.19(a), where C is a capaci
tor, L is an inductor, Ri is the parasitic resistance of the inductor, and Z 0 is a
loading impedance. The input impedance Rin(s) can be expressed as
Y M . = 7 s 2 + s ( R i / L ) + 1 / L C
I(s) ° s ^ s ( R l/L + Z 0/L) + l/L C K J
= Z0 || Ri if u = lj 0 = yJl/LC (3.24)
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K
U
1/Z„
(a) (b)
Figure 3.19: Passive notch filter and feedback block diagram.
For a typical lOnH on-chip inductor with Q equal to 5 operating at 1GHz, R\is
around 10Q. To achieve a considerably small Rin at the resonant frequency,
the loading impedance Z0 must be extremely small, which is a difficult design
challenge at radio frequencies. Observe that this circuit configuration gener
ates both complex zeros and poles at the same resonant frequency c u 0, but the
notching effect of the zeros exceeds the limited gain caused by the poles, leading
to a lower impedance. In VLSI design, there are other resistive and capacitive
losses associated in the circuit, and these losses may cause the pole frequencies
to deviate from the zero frequencies, so the pole and zero cancellation does not
occur. We also note that if R\ and L are tunable, then the resonant frequency
70
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and impedance level can be tuned to correct the VLSI process variation. How
ever, passive inductors usually are not tunable. To achieve better tunability, an
active inductor is usually employed.
Alternatively, considering a feedback system [39], depicted in Figure 3.19(b)
the transfer function can be written as
7 ^ = i + z 0 / z r - (3'25)
The error current I0 is generated from the difference of the current source I and
the current Ir from the output voltage V0. If ^ is of bandpass characteristic,
then the transfer function is represented as
y = G ; ‘f V f f (3.26)
Zr S + s(u)0 /Q) + lo0
where u > 0 is the resonant frequency, Q is the quality factor of the filter, and G
is the gain of the transfer function at u0. Thus, the overall closed-loop transfer
function is shown as
Vo(S) _ _ y S2 + S{U0/Q ) +
I(s) ° Si + s (1 + G Z 0 )lu0/Q + u ;0 2 1 j
= T T g X , f w = ( 3 ' 2 8 )
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The above equation shows that if a bandpass filter is placed in the feedback
loop, then the closed-loop configuration exhibits a notch characteristic. It is
worth noting that the numerator shows a 1 + G Za reduction in the quality
factor, leading to better stability for the system. Substantial notching effect
can be achieved if G Z0 1, which is independent of the quality factor of the
bandpass filter. Figure 3.19(b) is actually the block diagram of Figure 3.19(a)
with G = 1 / R{, but the feedback elements are implemented using a series active
LC resonator in this work.
A ctive Inductor w ith Loss C om pensation
Figure 3.20 illustrates an impedance load circuit used to realize a tunable
active inductor. Z ,-n exhibits a bandpass function, which is essentially a tran
simpedance stage in Figure 3.14. The input impedance is expressed as
where
s 2 + s A + B '
A = gm s
B =
N
(gm s c2 + gm 6 c3 c4)2 ’
dm6 Qm7
C2
D = 9ds
c 2 A C s
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V d d
M 1 0
V b ia s 6
V b ia s5
V b ia s3
V b ia s4
Figure 3.20: Input impedance load with bandpass characteristics.
M
N
C 2 F c3
’
9m7 9m8 C -2 C F C jm d Q m 8 C 3 C -(- ^3 ^4
Q m & 9m7 C 4 (Ci C 2 F C i C 3) Q m 6 C 5 [Srn8 C
~ \~ £ lm 6 C 3 C 4 + g, m 7 F 9 m 7 C 4 (C 2 + C 3)],
C - C\ C 2 + C 2 C 3 + Cl C 3,
C l — C gd 5 F C d l> 5 F C sf t 6 F C ^ s7 F C jj& 7 ,
C 2 —
C 3 — Cgb6 F Cgd 6 + C scJ 8 + Qfts F Qb9 + C f i c © ,
C 4 — C d b 7 F C ‘ sb 3 F C gS 3.
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C 5 — C g d 7 +
9ds —
9ds7 9ds8 || fJdsO fjds\0
9m8 9m9
Accordingly, they share similar expressions for the resonant frequency and qual
ity factor:
x/9m6 9m7
l o p - ----------- , (3.30)
V » t o 6 9m7 fo OT\
Qp — ~ ~ ^ • (3.31)
The tuning techniques applied to Figure 3.14 are employed to tune the
impedance load to reach better tuning performance. In general, the resonant
frequency in Equation (46) formed by complex poles in the bandpass impedance
load transfer function corresponds to the resonant frequency formed by complex
zeros in the series LC filter with a only slight frequency shift. This property
will be clarified later.
A ctive Filter Architecture
A notch filter for RF image rejection is depicted in Figure 3.21. The input stage
consists of a common-source cascode amplifier with a source degeneration resis
tor Re to enhance the linearity of the notch filter. 50ff is chosen as a trade-off
74
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Vbias2
Vbias6
Vbias5
vout notch
v b ia si M 2 2in
Vbias3
Vbias4
Figure 3.21: Notch filter.
between linearity and direct noise contribution to the input-referred signal-to-
noise ratio. The input stage is biased such that it not only offers voltage gain
but also reduces the noise contributions of the following stages. In contrast,
discrete notch filters usually exhibit a gain loss. The capacitor cn provides a
notching function due to a series resonance with the bandpass input impedance
stage illustrated in Figure 3.20.
To facilitate the derivation of the transfer function, a simplified circuit
model is used in Figure 3.22 to represent the input impedance at the drain of M2.
As mentioned above, the capacitor cn in series with the inductive element Z ^ n is
used to generate a notching effect. cp is the accumulated parasitic capacitance
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o
ZirV
a
Figure 3.22: Simplified model for the derivation of the notch filter.
to the ground and R is the DC impedance level at the drain of M2. Considering
the output voltage established by the current flowing through Z 'in, it can be
shown that the transfer function of the notch filter in Figure 3.21 is expressed
as
A-v-notch (" S )
Vo out ..notch
(s )
9 m 1
1 + cn M
Vs{s) 1 + 9m l Re C n + C p( l + C n M)
s2 I . / A+cn D M \ |
5 "T 5 v 1+ c M ) 1 + C n M > 1 1+c„ M
c 3 i 2 r l + c n M + ( e n + c p ) A R+cn cp D M R -\ . ( A+cn D M+(cn+cp) B R ~ | ,
S "r 5 t R[c„+cp (l+c„M)\ 1 + 6 l R\c„+c„ (l+cr,. M)] J T
B
where
R h n + C p (1 +C„ M )] R [ c n + C p ( l - |- C n - ^ 0 ]
(3.32)
R
C gd ,2 + Cdb2 + C gd3 + C dbZ + Cdb41
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The resonant frequency and the quality factor of the notch filter (zeros) can be
obtained and given by
/ 9m& 9m7 /0
U z = i — i 1— T — v ( 3 -3 3 )
V c + Cn ( C2 + C3 )
^ _ ^ [ c 2 + cn (c2 + c3)] gm 6 gm 7 ^ 0 /1 ,
hh — ~ ~ ~ 2 A , • f3.o4)
c2 A + cn gd s
Comparing Equations (3.33), (3.34) with Equations (3.30), (3.31), it is obvious
that both bandpass impedance load and notch filter share similar expressions
for the resonant frequency and quality factor except for the additional terms.
The comparison also shows that the resonant frequency of the notch filter is
smaller than the resonant frequency of the bandpass impedance load due to
the insertion of a notching capacitor c„. Similar to the tuning of the bandpass
impedance load, the uiz tuning is accomplished by varying Vbias3, and the
Qz tuning is achieved by adding cq and varying Vbias4. The denominator of
Equation (3.29) also reveals that there is a pair of complex poles located close
to the complex zeros. Simulations show that the quality factor of the poles
increases with the quality factor of the zero. Therefore, the notching effect
is somewhat attenuated by the complex poles and thus the notching depth is
reduced. Simulations also show that increasing cn pushes the complex poles
to higher frequencies and decreases Qp, but this further reduces uz. Iterative
simulations must be performed to obtain an optimized c„; cn equal to 0.15pF is
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20
10
-10 -
C Q
T 3 ,
~ -20 -
3
03
0 3
C C -30 -
-'I
-40 -
-60 - I
0.2G 0.6G 1.4G 1.8G 1G
Frequency (lin) (HERTZ)
Figure 3.23: High-Q image-reject filter with center frequencies between 595MHz
and 1354MHz.
selected in this design. Figure 3.23 shows a wide uiz tuning range this filter can
achieve from 595MHz to 1354MHz with cq equal to 0.35pF, 0.2pF, and O.lpF.
We have designed an image-reject filter for Global System for Mobile Com
munication (GSM) standard with a passband centered at 947MHz. The first IF
is set to 71MHz with a high side injection local oscillator, leading to an image
at 1089MHz that must be suppressed. Figure 3.24 shows that the notching
depth ranges from 15dB to over 60dB with Vbias4 tuning from 2.5v to 2.19v,
and co z deviates from 1097MHz to 1089MHz. The frequency deviation is 8MHz,
corresponding to only a 0.7% frequency shift. Therefore, the tuning sensitivity
is 0.0056 v/dB. It is worth noting that the tuning of u > z and Qz is almost inde
pendent of each other, facilitating the design of automatic tuning circuitry. The
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H -20 -
c / >
o
t r -30 -
-40
-50
1.04G 1.16G 1G 1.12G 1.08G
Frequency (lin) (HERTZ)
Figure 3.24: Q tuning with a uiz at 1089MHz.
voltage gain and noise figure in the desired signal band are equal to 4.75 dB and
9.5dB, respectively. We applied two small sinusoids at 945MHz and 95QMHz,
and I IPs is -20dBm. The non-linearity is primarily due to the non-linear am
plifier stage formed by M5-M10. IIP 3 can be increased by increasing gm& and
applying another source degeneration resistor to M7, but NF will be increased,
leading to a linearity-noise trade-off. The power consumption is 27mW and is
mainly contributed by the input stage due to the noise consideration.
Filter Stability
The stability of the image-reject filter is analyzed using Routh-Hurwitz cri
terion. Directly applying Routh-Hurwitz criterion to the analysis of the pole
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locations in Equation (3.32) is complicated and tedious. Instead, we approach
this problem indirectly; we assume that we have tuned the Qz to infinity, and
then we use Routh-Hurwitz criterion to assess the stability. By this criterion,
for a third-order system to be stable
q(s) = a3 s3 + a2 s2 + axs + a0, (3.35)
it is necessary and sufficient that
a2 ai > a3 a0. (3.36)
It can be shown that if the complex zeros of the filter are located on the left
half of the s-plane, then the filter is guaranteed to be stable if and only if
> R (cn + Cp). (3.37)
9ds
In our design, since g^s is mainly determined by the output conductance of
the PMOS cascode stage formed by M9 and M10, it is much smaller than R.
Simulations also show that the capacitances on both sides of Equation (3.37) are
of the same order. Consequently, the above equation is automatically satisfied
in this filter design. Accordingly, if the complex zeros are negative, the stability
of the filter is guaranteed.
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3.1 .4 P assive RLC B an d pass F ilter D esig n
3.1.4.1 CMOS Technology Overview
The VLSI technology we employed to fabricate the prototype was Agilent 0.5/rm
CMOS n-well technology (HP_AM0S14TB). It features three metals, one polysil
icon, and a maximum 3.3V supply voltage. In addition, this process provides
block silicide and linear capacitors to facilitate analog design. Since this tech
nology utilizes an epitaxial substrate, it has some influences on analog circuit
performance, which will be clarified in the next section.
To take advantage of this CMOS technology, silicide block resistors and
linear capacitors are used in the design. To reduce the sheet resistance of the
gate polysilicon for interconnection in CMOS technology, silicidation by de
positing a thin layer of highly conductive material on polysilicon results in a
low sheet resistance (« 2.4H/D) [52]. However, the resistance is too small for
analog resistors. Agilent 0.5/um CMOS technology provides silicide block resis
tors with high linearity, high resistance, and a low temperature coefficient. This
analog process uses an additional mask to block out the polysilicon region from
being silicided, leading to a high resistance approximately equal to 115ff/n.
A poly-diffusion capacitor has a large capacitance (« 3500aF/ fim2) due
to a very thin gate oxide; thus, it is the most common way to serve as an on-
chip capacitor. However, the poly-diffusion capacitor suffers from poor linearity
because the width of the depletion region at the oxide-diffusion interface changes
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with the applied voltage, varying the gate oxide thickness and thus changing
the capacitance. Fortunately, the Agilent 0.5/im CMOS technology provides a
linear capacitor with high linearity and relatively high capacitance per given
area. Constructing of the overlapped region of polysilicon and diffusion in a
capacitor well, the linear capacitor has a capacitance at approximately 2245
aF//im 2.
After a brief description of the CMOS technology we used to fabricate
the circuit, the design of on-chip passive inductors and CMOS varactors are
discussed, and finally a bandpass filter is proposed.
3.1.4.2 Spiral Inductor Design
Traditionally, a lightly doped p~ layer (~ 20fl-cm) is used in CMOS technology
to form a substrate and the low conductive substrate provides enough noise
isolation between circuits; however, this leads to a latch-up problem. Modern
standard digital CMOS technology utilizes an epitaxial substrate to circumvent
this problem. The substrate starts with a heavily doped p+ layer (fa 0.050-cm),
followed by a thin p-epitaxial layer. Unfortunately, analog circuits do not favor
this technology for two reasons. First, the highly conductive substrate does not
prevent switching noises of digital circuits from traversing to analog circuits,
largely increasing the noise floor of the analog circuit. Second, the highly con
ductive substrate has detrimental influence on the design of passive inductors
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oxide
P - epi
P+ substrate
C ,
Figure 3.25: Physical model representation of a spiral inductor,
due to the induction of eddy currents, leading to low-Q inductors.
General Inductor Design
The requirements for a good inductor are large inductance, small series resis
tance, low substrate loss, high self-resonant frequency, and small silicon area.
A large inductance increases the small signal gain. A small series resistance
increases the inductor Q and thus enhances the selectivity of signals in filter
ing circuits. A low substrate loss benefits the inductor Q at high frequencies.
A self-resonant frequency limits the highest frequency an inductor can be ef
fectively used and thus a high self-resonant frequency is demanded in the RF
design. A spiral inductor consumes a large silicon area compared with that of
a transistor; therefore, a small layout area is required to reduce the production
costs and minimize parasitic effects.
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An inductor is used to store magnetic energy; any associated resistances
and capacitances are considered as unwanted parasitics, where parasitic resis
tances dissipate energy and parasitic capacitances store part of the desired en
ergy from the power source. Figure 3.25 illustrates a physical model of an induc
tor in CMOS technology. Rs represents an ohmic loss and corresponds to the
resistance of the metal track. To reduce Rs, a top-level metal layer is employed
because it is usually thicker than lower-level layers. Furthermore, increasing
the width of the metal track and connecting several levels of metal tracks in
parallel help to minimize Rs (DC resistance) in low frequencies. However, the
skin effect starts to rise at high frequencies. The skin depth is quantified as
5 — where p is the conductance of the metal, / is the frequency, and
p, is the permeability of the metal. The currents flow close to the outside of
the metal track when operating frequency increases, leading to a higher Rs (DC
+AC resistance). Therefore, wider metal tracks and parallel metal connections
only improve DC resistance, but not AC resistance at high frequencies. A direct
feed-through path exists between two ports of the spiral inductor and is mod
eled as C 's to represent capacitive couplings. The oxide capacitance between the
metal track and silicon substrate is modeled by Co x and is given by ( £s%° 2 £ °) A,
where ss,o2 is the dielectric constant, e0 is the permittivity of free space, to x
is the thickness of the oxide, and A is the area of the metal track. The top-
level metal layer is used to minimize the capacitive loss due to the relatively
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4 4
-''YYVv^ / v V '-
4; T " > i ? c s 4/
o-
4
4
(a) (b)
Figure 3.26: (a) Two-port inductor model and (b) one-port inductor model.
thick oxide compared with lower-level metal layers. Rsi and C% model the sub
strate loss. Co x y Csi, and Rsi can be virtually removed if the electric field is
terminated before reaching the substrate. A ground plane placed between the
inductor and substrate helps to achieve this effect; however, the ground plane
is highly conductive, leading to large eddy currents. A patterned ground plane
without eddy currents is reported to have 10% improvement in the inductor Q
[37] [66]. Figure 3.26 shows a two-port lumped-element model for a spiral in
ductor. In applications such as the bandpass filter design or voltage-controlled
oscillator design, one-port is usually connected to the supply voltage or ground,
and then one-port model is used.
Faraday-Lenz law in Maxwell’s equations can be represented as
E -dl
= - I I J J S '
dB
surface dt
■ ds. (3.38)
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B{t)
w * > ®
11
® ®
oxide
P ' layer
V s T
P substrate
Figure 3.27: Induction of eddy currents in CMOS technology.
It indicates that the time-varying magnetic field induces an electric field in
nearby conductors and this electric field causes eddy currents to flow in the
conductors with the direction opposite to the original magnetic field changes,
shown in Figure 3.27. The magnetic field generated by eddy currents also cou
ples back to the original magnetic field, leading to a smaller inductance and
larger series resistance. The Faraday-Lenz law also shows that the induced cur
rents increase as the frequency increases. The eddy currents in current CMOS
technology have detrimental effects on the design of spiral inductors and thus
reduce the inductor Q at least in half at high frequencies. The effect of the eddy
currents is not shown in the inductor model, but can be incorporated into Ls
and Rs.
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L
Figure 3.28: Layout geometry of a spiral inductor.
Inductor Layout and Sim ulation
Circular and octagonal layout structures are closer to an ideal inductor struc
ture, so they have better inductor quality than those of rectangular spiral induc
tors, leading to 10% improvement in inductor Q is possible. However, circular
and octagonal structures increase the complexity of generating photomasks and
consume more silicon areas. Accordingly, only rectangular spiral inductors are
considered here. Figure 3.28 shows the layout dimensions of a spiral inductor.
The design of the inductor involves complex trade-offs among technological pa
rameters. The general guidelines for designing spiral inductors are described
below.
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The spacing, S, between metal tracks is maintained as close as possible
to increase the magnetic coupling and shrink the layout area. Therefore, a
minimum spacing is recommended for a given technology.
At low frequencies, the wider the width of the metal track W is, the lower
the DC series resistance becomes. While the skin effect starts to dominate at
high frequencies, the wider metal track is of little advantage in reducing the
series resistance. The wider track also contributes more parasitic capacitances,
leading to a lower self-resonant frequency. Therefore, an optimized track width
needs to be determined and usually an 8-15/rm wide metal track is used in the
GHz inductor design.
The number of turns, N, is determined by the inductance. Note that due
to the severe induction of eddy currents in the inner turns of a spiral inductor,
these inner turns contribute a small inductance and a large series resistance;
therefore, the center area of the layout is usually not used.
Based on the spacing, track width, and the number of turns, the outer
dimension L is determined by the inductance value. Inductance between 1-
30nH is plausible for the on-chip inductor design.
To reduce the series resistance, oxide capacitance, and substrate loss, a
top-level metal layer is used due to the thicker metal layer and farther distance
from the substrate. Multi-layer metal can be connected in parallel and 20% Q
improvement is reported [8]; however, the self-resonant frequency is impaired.
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A rectangular spiral inductor is designed and the related technological pa
rameters of the Agilent CMOS technology are indicated as follows:
Layer 0
P+ bulk
Layer 1
P~ epi
Layer 2
Oxide Layer
Metal 3
Resistance O-cm 0.05 20 100
Sheet resistance 0/D 0.05
Thickness pm 500 6 50 1.2
Relative eepi 11.9 11.9 4
A simulator “Analysis and Simulation of Spiral Inductors and Transform
ers for ICs” (ASITIC), developed by Ali Niknejad, is employed to design, ana
lyze, and model the spiral Inductor. A two-port analysis is first used to assess
the inductor performance, followed by a time-consuming electromagnetic anal
ysis to validate the design results. An inductor using the top-metal layer (metal
3) with A=4.25 turns, LF=8.7/im, and T=200/rm is used in this
work. The resultant t t model with the inclusion of eddy currents in the p~ epi
and p+ substrates, as indicated in Figure 3.26, is as follows:
f=1.20 GHz, Q = 1.86, Ls= 4nH, Rs= 15.7ft, Coxl= 113fF, RHl= 57.70, Cox2=
106fF, RSt2= 86.20, and the resonant frequency = 7.83GHz. The asymmetry
origins from the fact that one port is terminated on metal 1 and another is on
metal 3.
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3.1.4.3 On-Chip Varactor Design
A varactor is considered as a capacitor with a value that can be varied by a
control voltage. In general, a varactor can be modeled as a resistor in series
with a capacitor, shown in Figure 3.29, and the quality factor of the varactor is
defined as
r \ _ P ° w e r store __ 1 __ ri
r ~ Powers - ■ ~ s r C ~ s r v ^ v (3.39)
i t/u/c-y dissipation ° * s s
Therefore, a high quality varactor has a small rs (or large rp); this helps to
alleviate the resistive loading in the passive RLC filter design. Because the
capacitance is variable, a large maximum-capacitance-to-minimum-capacitance
tuning ratio, ^aa x -, is required for a given voltage variation to attain a max
imal frequency tuning range for the filter design. Another desired property
is to have a linear relationship between the control voltage and correspond
ing capacitance. A non-linear relationship creates steep slopes at some control
voltage range, leading to sensitivity problems. Figure 3.29 shows the impedance
transformation for both RC networks to facilitate the discussion in the context.
The pn-junction Varactors
Traditionally, on-chip varactors are implemented with pn junctions under the
reverse bias. Two types of pn-junction varactors exist in CMOS technology.
They are p~-epi/re+ varactor and p+-diffusion/n-well varactor shown in Figure
90
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Figure 3.29: Impedance transformation of a varactor: (a) series equivalent cir
cuit and (b) parallel equivalent circuit.
1 1
t s S jkSt i
n w e ll J P layer
p 1 substrate
(a)
M
i ■ ■ ■ «
I I ■ ■ 9
a « « *
■ ■ ■ ■
(b)
Figure 3.30: pn-junction varactor in CMOS technology: (a) structure and (b)
layout.
91
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3.30(a). The p~ substrate is grounded in n-well CMOS technology; thus, the
p~-epi/n+ varactor cannot be utilized due to the requirement of two control elec
trodes in our applications. Consequently, only the p+-diffusion/ n-well varactor
is discussed here.
Figure 3.29(b) shows the equivalent small signal model of a p+-diffusion/n-
well junction. The equivalent parallel resistance rp is expressed as r ev^lT /vT_1;
where Vt = ~ ^ 26mV at 300° K, Is is known as the scale current and
proportional to the area of the junction, and Vpn is the bias voltage that is
positive for a forward bias and negative for a reverse bias. It follows that rp
is small (equivalently rs is large) for the forward bias but large for the reverse
bias. Accordingly, the p+-diffusion/ n-well varactor is always used in the reverse
bias condition due to its high Qvar. The resistive path in lightly doped n-well
also contributes to rs that can be minimized by putting more n-well contacts
(n+ diffusion) closer to the p+ diffusion.
The reverse-bias capacitance Cp primarily consists of the depletion ca
pacitance. Different reverse bias voltages modify the width of the depletion
region in the junction and thus change the effective capacitance, leading to
the tunable characteristic. The voltage-controlled capacitance is expressed as
Cp = [24], where Cpo is the depletion capacitance per unit area at
Vj,„=0, V pn is the bias voltage and negative in this application, < J > 0 is the built-in
voltage of an open-circuit p+-diffusion/n-well junction, esi is the permittivity of
92
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the silicon, A is the gate area, and tj is the width of the depletion region. It is
obvious that Cp is a non-linear function of the control bias voltage Vpn.
To increase the varactor Qvan it is advised to use many small islands in
the layout, instead of a large one, shown in Figure 3.30(b). Every small island
is completely surrounded by a series of n-well contacts, so the ground paths are
short, resulting in a small rs (large rp) and high Qvar. In contrast, the grounds
are only connected on the periphery of the large island, and thus the ground
paths are fairly long, leading to a large rs (small rp) and low Qvar. Furthermore,
small islands have a larger periphery than that of the large island and thus they
create larger fringing capacitances, leading to larger capacitances for the same
layout area.
The main problem for the pn varactor is the mediocre < ^mM, which is ap
proximately equal to two, resulting in limited tuning range for the filter.
CMOS Varactors
Instead of using the depletion region of a p-n junction as a varactor, a MOS
varactor exploits a thin gate oxide as a dielectric to be a variable capacitor.
This type of the MOS varactor has a higher Qvar, higher , and larger ca
pacitance per area than a p-n varactor [8] [62]. In addition, the Qvar increases
as the transistor dimension shrinks [2]; therefore, it is widely used in CMOS
technology.
93
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substrate
P + substrate
(a)
(b )
Figure 3.31: NMOS varactors: (a) inversion region in p-substrate and (b) accu
mulation region in n-well technology.
the threshold voltage with respect to the drain/source voltage Vg — Vcii > Vth,
where Vg and Vc n are two control electrodes of the varactor. The gate voltage Vg
herein is high enough to attract electrons to move freely to the silicon surface
under the gate from n+ diffusions. As a result, the NMOS operates in the
inversion region, and the capacitance seen from the gate is equal to
where Agate and O are the gate area and oxide thickness, respectively. For
voltage Vg — Vc ti < V -th -, few mobile charges and negatively charged irons reside
on the silicon surface; a depletion layer is created and the NMOS operates in the
depletion region with a smaller Cvar due to the increased tg to account for the
Figure 3.31(a) shows an NMOS varactor whose gate voltage Vg is beyond
var
(3.40)
94
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C ttt
P layer
m f ®
n - w e l l
P lay<
p + substrate
(a) (b )
Figure 3.32: PMOS varactors: (a) the accumulation region and (b) the inversion
region.
width of the depletion layer. Since the substrate contacts (p+ region) in n-well
processes are usually connected to ground, no mobile holes are accumulated
under the gate oxide (if Vg is varied between the ground and supply voltage).
Therefore, the NMOS varactor operates in the inversion and depletion region,
but not in the accumulation region. This NMOS varactor has two problems.
One is that the substrate noise can easily couple to the control electrodes,
degrading the filter performance. In the PLL design, this severely deteriorates
the phase noise level and cannot be tolerated. Another problem is that large
p-n junction capacitances between the drain/ source and substrate cause a lower
bound in Cvar and thus decrease the tuning ratio In general, Cmin is
O' m i n
approximately equal to 30% Cmax.
A accumulation-mode NMOS varactor shown in Figure 3.31(b) alleviates
the above problems. Instead of using a p-substrate, an n-well is utilized to isolate
95
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PMOS Varactor for (W/L)=1200/0.6 and Vg=3.3v
1.9
1.7
1.5
+-»
o
t b 1-3
U
1.1
0.9
0.7
0.5
0.3
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
Vg-Vctl
Accumulation Depletion Inversion
Figure 3.33: Capacitance versus control voltage Vg — Vcti.
the substrate noise and n+ diffusions are used to eliminate the pn-junction
parasitic capacitances. For Vg — Vcti > Vth, the mobile electrons provided by
n+ regions accumulate on the silicon surface under the gate; thus, the varactor
operates in the accumulation region with respect to the n-well. Then Cvar
reaches its maximal value and equal to the gate capacitance. As Vg — Vcti is
close to Vth, the varactor gradually enters the depletion region. Accordingly,
Cvar decreases from the maximum to the minimum. Since no p regions exist in
the n-well, the varactor does not operate in the inversion region.
1
A k k
A i
f i & I S ♦ Fast
m
4 i
► ♦ ♦ x A
ss Normal
♦ ♦ <
❖
k Slow
X
■
x HP05T13X
X
*
A
X
■
*
k
X
X
m x X
■
A
Tuning range ■
4 A
........................
-- ►
❖
1 ®
96
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Alternatively, a varactor can be implemented using a PMOS transistor in
the n-well, illustrated in Figure 3.32, and the relationship between the capaci
tance and control voltage is shown in Figure 3.33 using Agilent corner param
eters simulations. For Vg — Vcti > VA, the mobile electrons provided by a well
contact (n+ region) accumulate on the silicon surface and the capacitance C var
reach to the maximum, C max, that is equal to the gate capacitance C gate- With
the decreasing Vg, the PMOS varactor undergoes the depletion region and then
gradually arrives at a minimum capacitance C min. Figure 3.32(b) shows that the
further reduction in Vg — Vcti drives the PMOS varactor into the inversion region
where more mobile holes from the p+ region present on the silicon surface, and
then finally C var reach the maximal value C gate. Consequently, the operation of
the PMOS varactor involves accumulation, depletion, and inversion regions [24]
[65]. To obtain a monotonic function of C var, we could remove the connection
between the n-well contact and drain/source, and connect the n-well contact to
the highest supply voltage (Vdd). In this way, the mobile electrons in n+ region
cannot be attracted to the silicon surface, and therefore the PMOS varactor
operates only in the inversion and depletion regions. By confining Vg — Vcii to a
certain voltage range, we could restrict the PMOS varactor operation to either
the inversion-and-depletion or accumulation-and-depletion region, leading to a
monotonic function.
97
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i c ,
c R
it d e p
p acc
lAAArAAAr A A A t”A A A r
iAA/V
'w e / / 'we//
(a ) (b )
Figure 3.34: NMOS varactor models (a) in the accumulation region and (b) in
the depletion region.
The symmetrical models for the accumulation and depletion regions are
illustrated in Figure 3.34 [56]. In accumulation, Cvar mainly consists of the gate
oxide capacitance Cgate and other parasitic effects. Rg is the gate resistance and
Race represents the accumulation-layer resistance under the gate oxide. Rp is the
P+ diffusion resistance in the drain and source. The substrate loss is modeled by
a parallel combination of Rweii and Cweii■ The model in the depletion region is
similar, but the additional depletion capacitance has been split to capacitances
to the drain, source, and substrate. The quality factor of the varactor Qvar can
be calculated by transforming the desired model to a serial combination of Rs
The PMOS varactor shown in Figure 3.32 has been implemented in this
work due to its immediate availability, potentially high Qvar, and low noise cou-
and Cs.
pling from the substrate. The operation regions are limited to the accumulation
98
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and depletion regions by confining the certain range of tuning voltages, which is
between 2.9V to 3.3V in Figure 3.33. The layout of the varactor deserves much
attention to minimize the parasitic effect. To reduce the gate resistance Rgi the
related gate noise, and parasitic capacitances in drain/source, a fingering layout
technique is mandatory. In addition, the minimum transistor length is used to
reduce the channel resistance Racc [3]. The varactor is also closely surrounded
by n-well contacts to shorten the ground paths, leading to a small Rweu and
large Cweu.
3.1.4.4 Filter Design
An inductor and a PMOS varactor discussed in the previous section are used to
implement a passive bandpass filter illustrated in Figure 3.35 [14]. The cascode
input stage provides a good isolation between input and the following stages,
improving stability and reducing the Miller effect. A monolithic inductor, T,
with a conductance loss, Gl, (or resistance loss, R i = ^V,) is resonant with a
voltage-controlled varactor M13, generating a second-order bandpass response.
To tackle the problem of the low-Q inductor, a negative conductance generator
(NCG) formed by M5 to M7 is employed to be in parallel with the lossy inductor,
leading to a high-Q inductor and high-Q bandpass filter.
99
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R s c <
& A /W
Figure 3.35: LRC bandpass filter.
The principle of the NCG is to generate an out-of-phase current with
respect to an original input current at the same input port. The negative
conductance is expressed as
G. n e g
$ m 6 9m7
9m6 ~f~ Qm7
(3.41)
M5 not only provides required DC currents through M6 and M7, but it also can
be used to vary the transconductances gm 6 and gmr by changing Vq. Accordingly,
the Q tuning of the bandpass filter is achieved by varying Vq. The resultant
conductance is Gtot = G\v - Gneg, where Gip = and Qs
( jjL
R l '
100
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Ignoring high-order terms, the filter transfer function, the resonant fre
quency, the quality factor, and the peak amplitude at the resonant frequency
are given as
1
■],(3.42)
1
(3.43)
Lp Ctot’
Q
1 Ctot
/
tot
(3.44)
9ml
(3.45)
Since the resonant frequency of the bandpass filter u 0 is determined by the
product of the inductance and capacitance in the LC tank, a PMOS varactor
M13 with a tuning voltage Vjv is used to tune ui0. Consisting of M il and M12,
the buffer stage is used to shift the voltage level and a capacitor is added to
increase the tuning range. Since V) (also V/v) can only be varied between ground
and Vdd, so M13 operates only in the accumulation and depletion regions,
leading to a monotonic function between the tuning voltage Vj and resonant
frequency uj0. We also note that increasing the negative conductance, Gneg, also
increases Q and Aoutj,p. By detecting the peak amplitude A oui_ b p, the filter Q can
be tuned. Based on this fact, many Q-tuning techniques were developed [60] [33].
Simulations from the layout extraction, shown in Figure 3.36, demonstrate that
the frequency tuning this circuit achieved is between 1.06GHz and 1.19GHz for
101
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1g 1.05g l.lg 1.15g 1.2g 1.25g 1.3g
Frequency (lin) (HERTZ)
Figure 3.36: Wide frequency tuning capacities.
varying Vj from 0.5V to 2.5V. A wide Q tuning range from 2 to over 100 at
1.15GHz is shown in Figure 3.37. Figure 3.38 also demonstrates the frequency
tuning is between 1.07GHz and 1.2GHz for varying V) from 0.5V to 2V while
Q is maintained at 30. This corresponds to an 11% tuning range at 1.135GHz.
V outJbp h the regular output port for the communication channels and its
DC bias is set up by a buffer stage for proper peak amplitude detection in the
tuning process.
The noise figure has been developed as follows
NFbp — 1 + 7 (gm3 + s w )
(,9 m 5 9 m 6 + S rn v )]-
(3.46)
102
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20
l.2 g 1 .3 g 1.259
1.05g 1.19
Frequency (lln) (HERTZ)
Figure 3.37: Wide Q tuning capacities.
Filter tuning range with Q=30 and C_add=25pF
1.21
1.19
N
X
o
O ’
8
Li.
c
©
o
1.09
1.07
1.05
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2
V_f volt
Figure 3.38: Frequency versus tuning voltage.
103
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To provide 5011 input impedance, gm 3 is fixed at approximately It is obvi
ous that minimizing gm 1 , gm 4 , and gm . 5 reduces the NF; thus, these transistors
usually have large transistor sizes. A bandpass filter has been designed to have
a resonant frequency at 1.15GHz with Q=30, 23.6dB voltage gain, 5.2dB noise
figure, -15dBm IIP3, and 23mW power dissipation. A 4nH inductor, L, and a
6pF capacitor, C, are employed.
3.2 A u tom atic Frequency Tuning D esign
In most hand-held transceivers, the limited isolation between the transmitter
and receiver prevents simultaneous signal transmission and reception. The
transceivers are normally operated in a half duplex mode with the transmit
ter and receiver being used alternately. As a result, filters in the receiver can
be tuned while the transm itter is operating. After the filters are tuned to the
desired frequencies, they are then switched back to the main receiving paths for
normal operation [14]. The conceptual block diagram for this tuning scheme is
shown in Figure 3.39. The Q tuning is also shown in the figure, but we only
consider frequency tuning in this work.
Three clocks are employed in this scheme. CK1 and CK2 are high-
frequency signals that symmetrically located below and above the desired reso
nant frequency, and SW is a low-frequency clock that provides signal switching
104
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CK1
CK2
Clock & SW
Generation
Integrator Multiplier
Bandpass
Filter
Peak Detector
SW1+
Figure 3.39: Proposed tuning circuit block diagram.
VI,
f «
I !
*
I s
1 <
1 !
l i
CK
~ L T
i — s -— --- 1 -------p - v i-
CKl fm w f0 CK2 f
(a)
o r
(b)
A v ( f ) 1
+ i ' .
1 1
CKl f0 CK2 f
(c)
A v ( f )
/ I
fo
(4 )
CK2 f
Figure 3.40: Synchronous rectification tuning scheme: (a) Vi > V 2
response of (a), (c) Vi < V2, and (d) Vi = V2.
, (b) circuit
105
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between CKl and CK2. In this design, SW is equal to 2MHz. First, CKl is se
lected as an input signal to the bandpass filter and the corresponding waveform
is generated. The peak detector detects the peak amplitude VI, and then SW
switches the input to CK2, obtaining another corresponding peak amplitude V2
at the peak detector output. Therefore, only one of the two frequencies, CKl
or CK2, is used as an input signal to the bandpass filter by switching SW. The
amplitude difference AV between VI and V2 depends on the deviation between
the “current” resonant frequency fnow and the desired resonant frequency f 0.
The frequency tuning voltage, V/, is computed by feeding both AV and SW to
the multiplier. The integrator is used to obtain a high voltage gain and filter
out the high-frequency harmonics generated by the multiplier. V/ then varies
the DC bias voltage of the varactor of the bandpass filter, leading to a change of
the resonant frequency. Note that an SW delay circuit is intentionally inserted
to balance two signal propagation paths, leading to a more accurate multiplica
tion result. The tuning process is repeated until V) is settled to a stable value,
so that f 0 — fnow = This synchronous rectification tuning scheme
allows us to use a correlation between the output amplitude of the filter and
SW to form a negative feedback system. In this work, CKl and CK2 were
chosen to be -12 dB below the peak value of the resonant frequency amplitude
response. Figure 3.40 sketches three possible tuning situations and how to use
106
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SW1+ O
CKl O ------
CK2 O-----
SW1- O -
Figure 3.41: Selection of the input stimulus.
the multiplication unit to determine the correct direction for V } to tune the
filter.
Figure 3.41 illustrates the selection of the input stimulus. Only one of the
two test signals, CKl or CK2, is selected to pass through the bandpass filter
by Ma or Mb. The output test signal is then fed to the input of the bandpass
filter. Voltage swings of SW1+ and SW1- with 50% duty cycles are required
for the circuit to work properly. While Ma or Mb is ON, it conceptually forms
a short circuit, allowing CKl or CK2 to reach V0 U i_r/. Since the bandpass filter
has a 500 input matching impedance, the ON resistances of Ma and Mb need
to be very small; thus, a large transistor size is required for Ma and Mb.
The bandpass filter designed for tuning has been discussed in Section
3.1.4.4 and illustrated in Figure 3.35. The resonant frequency f 0 is tuned by
varying the capacitance of the varactor M13 through Vj. In addition, Q can
be tuned by varying the negative resistance by tuning Vq. Vo utj,p is the output
107
Ma
Mb
o u t _rf
—o
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.42: Peak am plitude detector.
port for the communication channels and the input port of the peak detector in
the tuning circuitry.
The peak detector depicted in Figure 3.42 consists of a source follower with
a charging capacitor C\ and an additional low pass filter formed by R 3 and C2 ,
leading to a considerable gain attenuation for high-frequency signals. The time
constant is arranged to filter out CKl and CK2, but the SW signal transitions
still maintain. M15 provides an extra gain with reasonable linearity. Illustrated
in Figure 3.43 is a clock generator. SW1+ and SW1- are generated to provide
proper switching activities to the Ma and Mb in Figure 3.41 and the multiplier.
W ith poly-to-poly lOpF capacitors C3 and C4, the clock generator also provides
108
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Figure 3.43: Switch-and-delay generator.
Vdd
M55 M76 M75 M56
S W 2 - SW 2 -
— I M 5 3 Z i , M 5 4
'p
s ^ 1 ---
I M 991 p
— L ------- M52
c i -+| M51 I
M74 . M73
j£. r
SW2+ M59M60 M61M62J M82 M81 M80 M79
M98
M72 M58 M77 M57 M78
M71
Figure 3.44: Gilbert cell multiplier.
roughly 15ns delay between SW1 and SW2. Voltage dividers formed by M41-
M47 and M51-M57 are designed to provide a proper voltage level to drive the
multiplier.
A Gilbert cell is used in the multiplication circuit due to its simple bal
anced architecture. Since a four-quadrant multiplication is required for the
synchronous rectification, differential input signals need to be generated. Here
we use Rip and Cip to form a lowpass filter, providing the same DC bias volt
age for the gate terminals of M53, M54, M73, and M74. Differential signals
109
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Vdd
^ r r “h i
1 in _ mull I
M 8
I
M10
bias 1
M7
" op
in _mult
M3
M9
M14
M12
biast
M11
bias 5
M13
bias 2
M15
bias 6
M5 M4
(a ) (b )
Figure 3.45: Op-Amp integrator: (a) symbol and (b) circuitry.
are created due to the high common-mode rejection of the differential pairs.
Source-degeneration transistors M98 and M99 help to increase the input linear
range by operating them in the triode regions. Switching pairs M59-M62 and
M79-M82 are designed to operate as ON or OFF states to provide a maximal
gain for this stage. After calculating with the input stimulus, the tuning voltage
Vj of the varactor needs to be a slowly varying signal without disturbing the
output amplitude of the filter. This is achieved by setting up a proper R C
time constant in an Op-Amp integrator in Figure 3.45. To minimize the tuning
error, a high gain amplifier is demanded since we know that
Krror = ^ , (3.47)
110
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where A is the voltage gain. The integrator is basically a lowpass amplifier
with a high DC gain and a low-frequency pole. A two-stage Op-Amp with
a high gain and wide-swing current mirrors has been implemented. Ccom p is
an on-chip compensation capacitor with a capacitance value of 30pF. A 30pF
SMT integrating capacitor, Cop, generates a low-frequency pole, and a lOMfl
external SMT resistor, Rop, is placed to provide a high voltage gain and a DC
bias feedback for the Op-Amp to function properly. The Op-Amp features a
54dB voltage gain, 540Hz pole, 6MHz gain bandwidth, and 40° phase margin.
The bias voltages generated to supply the bandpass filter and tuning cir
cuitry are depicted in Figure 3.46. To facilitate the circuit testing, an external
supply voltage Vs, a resistor Rs, and an Op-Amp are used to establish a current
through the on-chip transistor M3 and then the biasing circuit. All bias volt
ages are generated by current mirrors and thus can be well-controlled over the
process variations. Voltages that are equal to 0.9V, 1.1V, 1.3V, 1.8V, and 2.0V
are generated.
Analytical equations are derived below to verify the circuit operations.
Two input signals are represented as A sirnoi t and A sinuih t, where A is the
amplitude of the signals. SW is a squared wave, so it can be represented as
cyxr B sin(2k + 1) L O sw t B , .
s w = l ^ — l k T , 2 - < 3-48>
1 1 1
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
V d d
M 6 2.0 v M4 M 9
M 1 M 1 2
M 5 M 1 0
M 2
M 7
M 1 3
M 3
0.9 v
0.9 v
V *
M e
M 5 M 1 1
M14
Figure 3.46: Bias circuit.
where B is the SW amplitude. After passing through the bandpass filter, two
corresponding output signals are generated and represented as
.1 ^ sin(2 k + l)usw t 1, . , A sin( 2 k + l)ivsw t 1
> 2 £ — 2*71-----+ 21+* s ,n u lh 4 [2 £ — 2*71 2 ■
(3.49)
where A\ and Ah are resultant amplitudes of two signals. The peak detector
is designed to filter out high-frequency signals, and only SW square wave is
preserved. Thus, the output of the peak detector is
Ai + Ah Ai — Ah sin(2 k + \)u>sw t
~ 2~ + ~ t “ £ 0 — 2* 7 1 — ■ <3'50)
1 1 2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Before the square wave signal enters the multiplier, an AC coupling capacitor
is employed to remove the DC bias voltage, and then the resultant AC signal is
multiplied with SW. The multiplication leads to
sin(2k + l)usw t 1
2 Am ul Ady (A; A -h)
(3.51)
where Am ui and Ady are the voltage gains of the multiplier and delay circuit,
respectively. Finally, the Op-Amp integrator results in
The above equation shows that the tuning voltage V/ is not a sinusoid signal,
on the sign of Ai — Ah, and it also shows that the larger \Ai~Ah\ is, the faster the
final tuning voltage approaches. This result allows us to preserve the sampling
amplitudes A\ and Ah without using sample-and-hold circuitry. Therefore, this
tuning technique gives us better tuning performance.
The target resonant frequency 1.15GHz is selected as a test vehicle. Two
input testing signals with amplitudes -12dB below the peak amplitude of the
resonant frequency are 1.103GHz and 1.197GHz, and both generate 60mV to
the input port of the bandpass filter without causing much distortion.
(3.52)
but a voltage that integrates linearly with time. The tuning direction depends
113
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Care should be exercised to ensure balanced timing delays in both signal
tuning paths. The precision of the tuning basically relies on the choice of the
resonant frequency, peak detector, and the offset voltage of the multiplier. Al
though the bandpass filter functions at gigahertz frequency range, the following
voltage buffers and the peak detector have limited frequency responses, leading
to peak amplitude detection errors. Therefore, the higher frequency test signal
CK2 cannot be arbitrarily high. Iterative simulations need to be performed to
locate the appropriate value. Additionally, a simple CMOS peak detector can
not detect faithfully the true amplitude of the output voltage from the bandpass
filter if the incoming signal or the amplitude difference of two signals is small.
The offset voltage in the multiplier could cause problems too. Proper transistor
sizes and layout techniques are required to minimize this effect.
114
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C hapter 4
E xperim ental P rototyp e and Test R esult
A 1.15 GHz bandpass RLC filter with automatic tuning circuitry has been
fabricated employing Agilent 0.5pm digital CMOS technology through MOSIS
at USC. This CMOS n-well technology has three metal layers, one poly layer,
linear capacitors, and a highly conductive epitaxial substrate. Additionally, it
offers a silicide block option for poly layers to implement poly resistors. The
technology is intended for 3.3 volt applications. The circuit layout size is 1943
x 1943 pm 2 with 40 bonding pads, as shown in Figure 4.1. High-frequency
signal pads were surrounded by grounded pads to minimize signal coupling.
The circuits in the die featured a filter with tuning circuitry and other test
circuits. All outputs of the filter system shown in Figure 3.39 were brought out
for testing purposes. Other testing circuits were also implemented, including
an inductor, a varactor, and a bandpass filter, to characterize their individual
performance.
The die was packaged using a 48-pin plastic Thin Quad Flat Package
(TQFP) though ASAT. This surface-mounted package provides a space-efficient
115
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Figure 4.1: Chip photo.
packaging solution, resulting in smaller printed-circuit board space require
ments. Its reduced height and body dimensions are ideal for high-frequency
and space-conscious applications.
The chip was mounted on a two-layer printed-circuit board (PCB) with
500 traces for high-frequency signals, shown in Figure 4.2. Figure 4.3 demon
strates a -23.2dB reflection coefficient at 1.2GHz for a trace with 500 char
acteristic impedance on the PCB. Furthermore, the PCB layout was carefully
arranged to have all high-frequency traces close to the ground plane on the back
of the board to minimize the parasitic inductance in signal return paths.
116
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Figure 4.2: Printed-circuit board layout.
Figure 4.3: Reflection coefficient of a trace on PCB.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A bandpass filter with a resonant frequency of 1.15GHz was selected to
evaluate the performance of the system. Accordingly, two input test signals,
1.103GHz and 1.197GHz, with amplitudes -12dB below the peak amplitude of
the resonant frequency were chosen. A 2MHz signal SW served as a switching
signal for tuning circuitry.
The bias circuit of the system is depicted in Figure 3.46. The Op-Amp
was intentionally removed to simplify the testing procedure and two voltages,
0.9V and 2.1V, were directly added to the source and the gate of M3. Due to
well-matched current mirrors, bias voltages 0.9V, 1.1V, 1.3V, 1.8V, and 2.0V
were accurately generated and measured.
The performance of the bandpass filter illustrated in Figure 4.4 is listed in
Table 4. Here, only simulation results incorporating the effects of a bond wire
and a pad models are demonstrated because the original design did not include
eddy currents in the epi-substrate, leading to a higher inductor Q. Therefore,
the negative conductance generator (NCG) cannot fully compensate the loss of
the inductor; a low-Q filter results. This problem has been verified by circuit
simulations and can be circumvented by adding eddy currents in the inductor
or decreasing the value of the negative conductance of the NCG in the design
stage to account for this process variation.
The measurement of the selection of the input test signal, depicted in Fig
ure 3.41, is shown in Figure 4.5 and a -27.4dB attenuation at 1.2GHz is obtained
118
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Figure 4.4: Bandpass filter layout.
Table 4.1: The performance metrics of bandpass.
Resonant frequency 1.15GHz
Quality factor 30
Inductor L 4nH
Capacitance C 6pF
Varactor capacitance 0.7pF~1.6pF
Input impedance 500
Voltage gain 22.1dB
Noise figure 5.2dB
IIP3
-14dBm
Power dissipation 33mW
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
for CK1 if Ma is off. The performance of the peak detector is characterized in
Figure 4.6. It shows that the voltage gain is approximately equal to one when
the input signal swing is large, but the voltage gain is reduced when the input
signal swing is less than 0.3V, leading to a sensitivity problem to the tuning
circuitry. We also notice that a tuning error occurs if input signal is smaller
than 50mV.
The input signal SW2 (= SW2+ - SW2-) to the switching pair of the mul
tiplier was generated from the switch-and-delay generator; their output wave
forms are demonstrated in Figure 4.7. It can be seen that the resulting SW2 is
400mVp e a k —to —peak • The measurement of the four-quadrant Gilbert multiplier is
shown in Figure 4.8. The linear input range is between +1.2V and -1.2V. \Vin \
larger than 1.2V affects the sensitivity of the circuit, increasing the settling
time of the tuning circuitry. The integrator is composed of an Op-Amp and
an integrating capacitor. The measurement of the Op-Amp shows that it has
a 54dB voltage gain at lOKHz, a 40° phase margin at the unity-gain frequency
6MHz, a lOmV offset voltage, and a 0.1V to 2.4V common-mode input range.
The voltage transfer function is shown in Figure 4.9.
Simulation results are illustrated in Figure 4.10 and 4.11 to demonstrate
the operation of the tuning circuitry due to the exclusion of eddy currents in
the inductor design and insufficient negative conductance supplied by the NCG.
In the simulation, the inductor was changed from 4nH to 3.6nH to account for
120
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4.5: CMOS switch measurement.
Delta Yin (volt)
>
c a
©
Q
Figure 4.6: Peak detector measurement.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4.7: The output of the switch-and-delay generator.
Gilbert Cell Multiplier with Vin = 0.5MHz measurement
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Vin (volt)
j « SW2+=1.8v SW2-=1.6v ■ SW2+=1.6v SW2-=1.8v
Figure 4.8: Multiplier measurement.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
* A * ' V jU M lk - r V * -’ W S *
1 ^ ' ; * r .'£ « £ - <(%■ i - ^3t«?
Figure 4.9: Op-Amp frequency response.
a 10% process variation; the tuning circuitry corrects the resulting frequency
error by properly adjusting the capacitance of the varactor. Figure 4.10 shows
the outputs of the bandpass filter and peak detector. It can be observed that
the amplitude difference of the two signals gradually converge to almost zero.
Figure 4.11 illustrates that the tuning voltage of the CMOS varactor settles to
1.256V, corresponding to a resonant frequency at 1.153GHz; this leads to a 0.26
% tuning error.
123
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H 2.45 ■
£
2.40
5 ^ S T v *
2 b
-V TJSf\T T J
4u 6u 8u Time (tin)
Figure 4.10: Outputs of bandpass filter and peak detector.
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Figure 4.11: Tuning voltage of a CMOS varactor.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C hapter 5
R esearch C ontribution
Although digital CMOS technology continues to progress, analog continuous
time active filters still hit the brick wall in the low hundred megahertz fre
quency range. OP-AMP based filters, Gm-C filters, and current-mode active
filters [22] [40] are only suitable for applications well below the gigahertz range.
Moreover, monolithic passive inductors are difficult to model and implement
with high quality factors due to resistive losses and capacitive coupling to the
substrate, producing low-Q RLC filters. At the same time, hand-held gigahertz-
band communications demand on-chip filters with high selectivity to minimize
the size, cost, and power dissipation [53][28] [19]. For such radio frequency
applications, the only way to circumvent this problem is to employ external
passive elements such as crystal filters, ceramic filters, or surface acoustic wave
(SAW) filters in lieu of on-chip filters. However, to achieve the maximal inte
gration level, the number of external elements needs to be minimized. In such a
situation, new filter topologies are essentially required to be exploited to relax
125
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the design technique gap between the specifications of on-chip filters and the
stringent requirements of mobile communication systems.
In this project, we proposed continuous-time aggressive transconductance
(AGm) filters and a RLC filter that can efficiently circumvent the aforemen
tioned dilemma in the gigahertz frequency range. Furthermore, a synchronous
rectification (SR) tuning scheme based on burst-mode transmission and recep
tion in current mobile communications is devised to stabilize the resonant fre
quency of a filter regardless of the changes of device parameters and tempera
ture. The proposed filters feature high-frequency, high quality factor, low noise,
and low power consumption. Great attention has been placed on the design of
a bandpass filter that combines a low noise amplifier and a band selection filter
in the frond-end of a transceiver.
The selectivity of the new filter topology has been enhanced by decreasing
the phase margin of an open-loop circuit or introducing a negative feedback
configuration, leading to a tunable quality factor ranging from 2 to 100 being
possible. In addition, the proposed filter topologies do not require off-chip
capacitors and inductors in the circuit to considerably reduce the circuit area.
One lowpass filter, one image-reject filter, and four bandpass filters have been
demonstrated. The proposed SR tuning scheme can be applied to the above
filters to correct their resonant frequencies. An RLC filter with the SR tuning
scheme has been selected to be fabricated in CMOS technology and tested.
126
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We have proposed filter topologies with tuning circuitry to replace bulky
external discrete components that are currently used in mobile communication
circuits. Therefore, the proposed on-chip filters with high quality factors offer a
great opportunity to achieve the maximal integration level in System-on-Chip
design to reduce cost, power, and circuit area.
127
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C hapter 6
C onclusion and Future Work
Traditional approaches in designing various filters are well-established, and the
performance errors of the resulting filters can be estimated with reasonable
precision; therefore, these filters can be utilized to effectively select required
signal bands in low frequencies. However, as the operating frequency increases
into the gigahertz range, these approaches cannot be applied anymore.
To take advantage of the burst-mode transmission and reception in the
time-division multiple access (TDMA), we proposed AGm and RLC filters that
can be used in the gigahertz-band operation, and their resonant frequencies are
corrected by on-chip negative feedback tuning circuitry. The proposed topolo
gies have been analyzed and simulated. Furthermore, a prototype has been
fabricated and tested using 0.5pm CMOS technology. It features high speed,
high Q, low noise, low power, and a self-resonant frequency tuning ability. The
topologies show a great potential to be used in communication applications.
Additionally, the proposed synchronous rectification tuning scheme can be uti
lized to tune lowpass, bandpass, highpass, and notch filters (or image-reject
128
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filters). Other applications include the 500 impedance matching, constant-
transconductance loops, automatic gain control (AGO) circuits, and equalized
amplitude detection related areas.
To completely characterize the performance of a second-order filter, a spec
ified voltage gain, a resonant frequency, and a quality factor are required. There
fore, except for the SR tuning proposed in this work, two extra tuning loops
are necessary. The voltage gain can be simply tuned by a voltage-controlled
amplifier through an AGO loop, but the noise contributed by the loop needs to
be reduced. The Q tuning can also be implemented using an AGO loop; how
ever, the filter Q is proportional to the voltage gain of filter and other circuit
parameters. Therefore, the AGC circuit cannot correctly tune the filter Q by
determining the output voltage amplitude of the filter. Alternatively, the filter
Q can be tuned by considering the sum of the phases at -3dB frequencies of a
second-order bandpass filer.
Future work will focus on Q tuning design, so the proposed resonant fre
quency tuning scheme can be integrated with Q tuning circuitry to develop a
fully on-chip filter solution, maximizing the integration level of filters in com
munication devices.
129
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Asset Metadata

Creator Chang, Yuyu (author)

Core Title CMOS gigahertz -band high -Q filters with automatic tuning circuitry for communication applications

School Graduate School

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag engineering, electronics and electrical,OAI-PMH Harvest

Language English

Contributor Digitized by ProQuest (provenance)

Advisor Choma, John (committee chair), Kaplan, Richard (committee member), Wills, Jack (committee member)

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c16-551134

Unique identifier UC11339349

Identifier 3094408.pdf (filename),usctheses-c16-551134 (legacy record id)

Legacy Identifier 3094408.pdf

Dmrecord 551134

Document Type Dissertation

Rights Chang, Yuyu

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the au...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus, Los Angeles, California 90089, USA