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Accurate and efficient testing of resistive bridging faults

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Accurate and efficient testing of resistive bridging faults

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Content ACCURATE AND EFFICIENT TESTING OF RESISTIVE BRIDGING FAULTS by Hugo Chong-hing Cheung A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2008 Copyright 2008 Hugo Chong-hing Cheung ii Acknowledgements I thank Yvonne, Calvin, Cori, Casy, Clayton, and my parents for their years of continual support. I thank Dr Sandeep K. Gupta for his relentless mentoring to make this research successful. iii Table of Contents Acknowledgements......................................................................................................ii List of Tables ...............................................................................................................v List of Figures ............................................................................................................vii Abstract .......................................................................................................................ix Chapter 1 Introduction to bridging fault testing...........................................................1 1.1 Logic testing of bridging faults........................................................2 1.1.1 Background ..................................................................................2 1.1.2 A new model for logic testing of bridging faults .........................5 1.1.3 Objectives of our research in logic testing of bridging faults ......6 1.2 I DDQ testing of bridging faults ..........................................................7 1.2.1 Background ..................................................................................7 1.2.2 I DDQ test escape and yield loss metrics and threshold selection strategies.................................................................................11 1.2.3 I DDQ threshold profiling, discrimination and profile selection strategies.................................................................................12 1.2.4 Objective: I DDQ modeling and threshold selection strategies.....15 1.2.5 Objective: I DDQ profiling............................................................16 1.2.6 Objective: I DDQ fault excitation pattern......................................17 Chapter 2 Byzantine resistive bridging fault modeling .............................................18 2.1 Bridging fault local sub-circuit ......................................................18 2.2 Bridging fault effect excitation ......................................................21 2.3 Bridging fault effect computation ..................................................23 2.4 Fault resistance ranges ...................................................................24 2.5 Bridging fault composite value system..........................................27 2.6 FRR D-cubes..................................................................................28 2.7 Equivalence and dominance of FRR cubes and FRRs...................30 2.8 Summary ........................................................................................32 Chapter 3 Bridge fault simulation..............................................................................33 3.1 Bridging fault simulator composite value system..........................33 3.2 Fault simulation procedures ...........................................................35 3.3 Fault excitation check and fault effect propagation .......................36 3.4 Previous bridging fault simulation studies.....................................38 3.5 Fault simulation results ..................................................................39 3.6 Comparison with Zero Bridging Fault Resistance method............40 3.7 Comparison with Sectioned Resistance method ............................41 3.8 Summary ........................................................................................42 iv Chapter 4 Bridging fault ATPG .................................................................................43 4.1 Introduction....................................................................................43 4.2 ATPG procedures...........................................................................45 4.3 16-valued evaluations.....................................................................47 4.3.1 16-valued logic implication .......................................................48 4.3.2 16-valued logic cube covers.......................................................49 4.3.3 16-valued FRR D-cubes.............................................................50 4.4 A Byzantine ATPG example..........................................................53 4.5 Static indirect implication ..............................................................56 4.6 Search space data structure ............................................................58 4.7 D-drive ...........................................................................................59 4.8 Line justification ............................................................................60 4.8.1 Proposed cube enumeration scheme ..........................................61 4.8.2 Line justification procedures......................................................63 4.9 Logic implication ...........................................................................64 4.10 Computing ATPG coverage...........................................................66 4.11 ATPG system .................................................................................67 4.12 Results............................................................................................68 4.13 Summary ........................................................................................71 Chapter 5 I DDQ testing for bridging faults ..................................................................72 5.1 I DDQ bridging fault modeling..........................................................73 5.1.1 Defect severity metric ................................................................73 5.1.2 Characteristics of I DDQ test.........................................................74 5.1.3 Yield loss and test escape metrics..............................................77 5.1.4 Case study circuit .......................................................................79 5.2 I DDQ test strategies..........................................................................80 5.2.1 I DDQ threshold selection strategies .............................................80 5.2.2 I DDQ profile discrimination strategies.........................................86 5.2.3 I DDQ fault excitation profiles discrimination strategies ............100 5.3 Proposed research.........................................................................110 5.3.1 Comprehensive ZTET strategy ................................................110 5.3.2 Bridging fault covering problem..............................................112 5.3.3 Comprehensive ZTET ATPG ..................................................114 5.3.4 Comprehensive ZTEP strategy and ATPG ..............................116 References................................................................................................................117 v List of Tables Table 1-1 Example I DDQ profiles and profile sets. .....................................................12 Table 2-1 Fault excitation response table for the fault in Figure 2-1.........................25 Table 2-2 Threshold voltages of the gates in the fanout of the fault site in Figure 2-1. ............................................................................................................................25 Table 2-3 Fault characteristic table for the fault in Figure 2-1. .................................25 Table 2-4 16-valued composite value system with few commonly used symbols. ...27 Table 2-5 FRR cubes for the fault in Figure 2-1........................................................29 Table 3-1 Encoding scheme for the three-valued system. .........................................34 Table 3-2 Storage structure at a circuit node. ............................................................34 Table 3-3 PPSFP Bridging fault simulation results. ..................................................40 Table 4-1 Basic value truth table for 2-input NAND gate.........................................48 Table 4-2 Compact cube-cover representations for a multiple-input NAND gate. ...50 Table 4-3 ATPG for the example in Figure 4-2.........................................................54 Table 4-4 16-valued cube-coverings for 2-input NAND gate ...................................62 Table 4-5 Proposed justification enumeration scheme for a multiple-input NAND gate. ....................................................................................................................63 Table 4-6 Byzantine bridging fault ATPG results. ....................................................70 Table 5-1 Notations....................................................................................................75 Table 5-2 Possible intra-cell resistive bridges. ..........................................................80 Table 5-3 Critical severities and currents. .................................................................82 Table 5-4 Examples for fault characteristic profiles and I DDQ threshold values........92 vi Table 5-5 Summary of test results for four example DUTs.......................................95 Table 5-6 ZTEP/ZYLP/ZTET/ZYLT comparison.....................................................99 Table 5-7 I DDQ Profiles for ZYLP and ZTEP...........................................................101 Table 5-8 Critical Current Table with TER and YLR results. .................................109 Table 5-9 YL and TE comparison............................................................................110 Table 5-10 Example critical current.........................................................................111 Table 5-11 Four possible ZTET test sets for the example. ......................................111 vii List of Figures Figure 1-1: An example circuit with bridging fault represented by adding R f . ...........3 Figure 1-2: Circuit node voltages vs. R f when (c 1 ,c 2 ,c 3 ) = (0,1,1) for the example in Figure 1-1. ............................................................................................................3 Figure 1-3 Simple I DDQ threshold settings in past technologies...................................9 Figure 1-4 Simple I DDQ threshold settings in future technologies..............................11 Figure 1-5: I DDQ profiles for the example in Table 1-1..............................................14 Figure 2-1 An example circuit with a bridging fault, R f ............................................19 Figure 2-2 Local-sub-circuit for the bridging fault shown in Figure 2-1...................20 Figure 2-3 Fault effect excitation curves: V f vs. R f . ..................................................22 Figure 3-1 Proposed bridging fault PPSFP simulation procedure. ............................36 Figure 4-1 Modified D-algorithm ATPG procedures for Byzantine bridges.............45 Figure 4-2 An example circuit with FRR 4500 between c 2 and c 10 ...............................54 Figure 4-3 Search tree data structure. ........................................................................58 Figure 4-4 Implementation details of D-drive ATPG sub-task..................................60 Figure 4-5 Enumeration example to justify /D at gate output c j . ...............................62 Figure 4-6 Implementation details of line justification ATPG sub-task....................64 Figure 4-7 Forward implication procedure. ...............................................................65 Figure 4-8 Byzantine resistive bridging fault ATPG system.....................................67 Figure 5-1 Parameters associated with fault F k and test vector V i .............................74 Figure 5-2 Histogram H k denoting the distribution of severities for fault F k .............78 Figure 5-3 SRAM used as case study. .......................................................................79 viii Figure 5-4 An SRAM cell..........................................................................................79 Figure 5-5 I DDQ profile P 1 is completely below P 20 ....................................................90 Figure 5-6 I DDQ comparisons for ZYLP and ZYLT...................................................94 Figure 5-7 I DDQ comparisons for ZTEP and ZTET....................................................94 Figure 5-8 ZYLP, ZTEP and DUT I DDQ comparison...............................................101 Figure 5-9 P 14 , P 18 and P 19 fault excitation pattern comparison...............................106 ix Abstract Many studies show that bridging defects are major causes of fabrication failures. A bridging fault causes a short circuit between circuit nodes and can be tested by logic testing, which measures the erroneous logic values at the circuit outputs, or by I DDQ testing, which measures the elevated power supply current (called I DDQ ). This research spans logic as well as I DDQ testing for bridging faults. A bridging fault may cause intermediate voltages, i.e., voltages between the logic thresholds (V IH and V IL ), at the nodes involved in the bridge. In such cases, the gates in the fanout of the bridging fault site may output the expected or a faulty logic value, but we may not be able to determine which one. Furthermore, different gates in the fanout of the fault of the fault site may interpret the voltage as different logic values. Such bridge fault behavior is sometimes referred to as Byzantine behavior. We developed an accurate resistive bridging fault model to capture the Byzantine behavior. We developed the first fault simulator and ATPG at logic level to generate tests for the resistive Byzantine bridging faults. We demonstrate that the current approaches significantly overestimate coverage and that our methodology can generate additional vectors to achieve high coverage. I DDQ testing is essential to test quality requirements for todays deep- submicron devices. Studies show many defects in a CMOS device can only be detected via I DDQ testing. One of the key parameters in I DDQ testing is the threshold value of I DDQ . Typically, the value of the I DDQ threshold is determined heuristically. x If the value of I DDQ threshold is set too low, then many devices that have elevated I DDQ but cannot cause logic or timing will be erroneously declared faulty and discarded. Clearly, this causes unnecessary yield-loss. On the other hand, if the value of I DDQ threshold is set too high, devices with defects that cause logic, timing, or some other functional errors can be declared fault free. In such cases, I DDQ testing causes high test-escape. We developed new I DDQ test approaches that minimize test- escape and yield-loss. 1 Chapter 1 Introduction to bridging fault testing Many studies ([39][38][23][3]) show that bridging defects are major causes of fabrication failures. Many past studies assume that bridging defects are hard-short defects [1], i.e., they assume that the bridge resistance is negligible. Also, since TTL technology was used in the past, bridging faults are often modeled as wired-AND or wired-OR. However, in CMOS bridging faults may affect device operation current, output voltage levels, and output signal timing. Accurate and efficient bridging fault modeling and bridging test generation are hence essential for enhancing test quality and reducing test cost. A bridging fault causes a short between circuit nodes. Logic testing, where logic values are captured at outputs can be used to detect such a fault. I DDQ tests, which measure the elevated power supply (quiescent) current, can also be used to detect a bridging fault. This work covers both these major approaches for testing bridging faults. The proposed tests for bridging faults will be derived considering a more realistic fault behavior compared to existing methods. Hence, we develop new fault models as well as new test methodologies. The logic tests that we generate will be the first ones to provide high coverage for the bridging faults that cause indeterminate logic values. The I DDQ tests that we generate will be superior to prior tests in terms of test escape (faulty chips that are erroneously declared fault-free) and yield loss (chips that are erroneously declared faulty). 2 This chapter introduces the background concepts in logic and current testing of bridging faults. We present detailed summaries of the motivation for the proposed research, research objectives, as well as research results. 1.1 Logic testing of bridging faults 1.1.1 Background Figure 1-1 shows a bridging fault between the output of gate U1 and GND. Figure 1-2 shows the voltage at nodes c 4 , c 7 and c 8 for various values of bridging resistance, R f , when (0,1,1) is applied to inputs (c 1 ,c 2 ,c 3 ). The logic values output at nodes c 7 and c 8 depend on the voltage at node c 4 , which is involved in the example bridging fault. Gates U2 and U3 interpret the voltage at node c 4 according to the values of their threshold voltages. The logic threshold voltages V IL and V IH for a gate are the input voltage values at which the slopes of the gate voltage transfer characteristic (VTC) curve are minus-one. Voltages between V IL and V IH are interpreted by the gate as indeterminate logic values, while those above V IH and below V IL are interpreted as logic 1 and 0, respectively. The V IL and V IH for U2 and U3 are (0.9V, 1.4V) and (1V, 1.5V) respectively. Case 1: For a fault-free circuit or when the bridging resistance is very high, both gates, U2 and U3, interpret the voltage at the fault site as the fault-free value {1/1}. (The first value denotes the fault-free logic value while the second one denotes the logic value when a fault exists). This is the case when the bridging resistance is in the range of [infinite, 9.5kΩ]. 3 Case2: When the bridging resistance is very low, both U2 and U3 interpret the voltage at the fault site as {1/0}. This is the case when the bridging resistance is in the range of [4kΩ, 0Ω]. For both these cases, the voltage at c 4 is either above V IH or below V IL values of U3 and U4. Case3: When R f =[9.5kΩ, 5.5 kΩ], the voltage at node c 4 is between the V IH and V IL of U3 and hence causes U3 to output indeterminate logic value at node c 8 , which is marked x on signal c 8 in Figure 1-2. Similar situation arises for U2 when R f =[7.5kΩ, 4 kΩ]. Figure 1-1: An example circuit with bridging fault represented by adding R f . 0 0.5 1 1.5 2 2.5 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 Case1 Case2 Case3 c8='x' c7='x' c4 c7 Rf (ohm) V c8 Figure 1-2: Circuit node voltages vs. R f when (c 1 ,c 2 ,c 3 ) = (0,1,1) for the example in Figure 1-1. 4 The inconsistent interpretation of intermediate bridging voltage by different gates in the fanout of the fault site is described as Byzantine behavior and has been studied in detail over the past 20 years [29][19][21][23][3][9]. However, none of these models [31][35][22][34] consider the case where voltages at gate inputs are interpreted as logically indeterminate. Instead, they assume that for each gate V IH equals to V IL and assume that the gates transfer characteristic switches abruptly at this single threshold voltage and always expect logic values at (c 7 ,c 8 ) as being either {0/1} or {0/0}. Hence, whether a device with such a fault passes or fails is determined by the single threshold voltage selected for each input of each gate. Therefore, if the threshold voltages for U2 and U3 are set too high, some defective parts with this bridge may escape the test generated using this model. In such a case, such models will overestimate fault coverage. To avoid such overestimation of fault coverage, in our model we consider two threshold voltages, namely V IL and V IH , at each input of each gate. We then consider that a gate interprets any voltage at one of its inputs as logic 0 if the voltage is less than the corresponding V IL , logic 1 if the voltage is greater than the corresponding V IH . Any voltage between V IL and V IH is interpreted by the gate as logically indeterminate, i.e., either logic ‘0’ or logic ‘1’ but unknown to us. This is critical because in the high-slope region of the VTC curve between V IL and V IH , even a minor variation in operating conditions, e.g., a 2~3% fluctuation in V DD due to ground-bounce, can cause the same voltage to be interpreted either as logic 0 or as logic 1. Hence, we must not rely on any specific interpretation of such a voltage. 5 To avoid overestimation of coverage, we use the composite value notation {0/1, 0/0} and {1/0, 1/1} to represent such indeterminate logic values. A bridging fault resistance range is covered by a vector only if the vector propagates a {0/1} or {1/0} to a primary output. The study in [3] shows that a major percentage of bridging faults causes indeterminate logic values. Our bridging fault simulation results that are discussed in a later chapter also find that there is a significant percentage of bridging fault resistance values that may give raise to indeterminate logic values (shown as Case3 in Figure 1-2). 1.1.2 A new model for logic testing of bridging faults Bridging fault simulation study in [23] suggests that pattern generation must use the most accurate models, since less accurate models may lead to generation of vectors that do not provide high coverage. We use SPICE simulation for the local sub-circuit around the fault-site which can accurately capture Byzantine behavior [35][34]. The local sub-circuit for a particular bridging fault is a sub-circuit that includes the fault site, the gates in the immediate inputs in the fault site, all inputs of the above gates, and the fanout lines of the fault-site. Some other studies [31][21] use electrical analysis to compute the fault site behavior which would also generate comparable modeling accuracy as SPICE simulations. The modeling for the bridging fault site includes: 6 o Driving strength for the gates driving the bridging nodes. The fact that the strength of the pull-up and pull-down network of a CMOS gate varies with the vector applied at its inputs is also considered. o The resistive bridging fault. o The logic voltage thresholds, i.e., V IL and V IH , of the gates driven by the bridging nodes. 1.1.3 Objectives of our research in logic testing of bridging faults The first objective of this study is to develop a new model for Byzantine bridging faults. To enable accurate analysis at acceptable complexity, this model must provide accurate models near the fault site and logic level models that capture the indeterminate values in the remainder of the circuit. To enable such mixed-level modeling, we use a tabular representation of the behavior at the fault site. The tabular representation of the behavior at the fault site can then be used to define bridging fault equivalence and dominance relationships. These relationships can be used to reduce the number of faults to target. The second objective is to develop a bridging fault simulator. This simulator uses the above accurate model and identifies all ranges of bridging fault resistance values that are covered by a given set of test vectors. We use this simulator to compute Byzantine bridging fault coverage for benchmark circuits with high quality test vectors to demonstrate the necessity of the proposed Byzantine bridging model and associated tools, which consider indeterminate logic values. 7 The third objective is to develop a bridging fault and automatic test pattern generator (ATPG). The bridging fault ATPG must make use of the accurate model and must include an algorithm that generates test vectors for bridging faults with Byzantine behavior. By integrating this ATPG with the above bridging fault simulator we would develop the first ATPG system for Byzantine bridging faults. Chapter 2 details our approach for the Byzantine bridging fault model. A new composite value system and the concept of a local sub-circuit for a bridge are defined. A novel bridging fault simulator is then described in Chapter 3. Chapter 4 outlines the proposed ATPG algorithm and its procedures. 1.2 I DDQ testing of bridging faults 1.2.1 Background During I DDQ testing, each vector is applied and the circuit is allowed to stabilize. The steady state current flowing via the device, called the quiescent-current or I DDQ , is then measured. The measured I DDQ value is compared with a threshold value, called I DDQ threshold. If the measured value of the quiescent current for a device under test (DUT) is less than this threshold value for every test vector, then the DUT is declared I DDQ fault free; otherwise, the DUT is declared faulty. I DDQ testing is essential for achieving high quality requirements for todays deep-submicron devices. Studies show that many defects in CMOS devices can only be detected via I DDQ testing [30]. In [25] the relative effectiveness of scan-based AC tests, I DDQ tests, and functional tests are studied. Each type of test was found to detect some failures not detected by the other two types of tests. As described in [14], 8 some defects, such as high impedance bridges, gate-oxide-shorts, and floating gates, are detectable only by I DDQ tests. The study in [30] shows that both functional tests and I DDQ tests detect 805 of the total 980 defective devices. However, the I DDQ tests detect 53 defective devices that escape the functional tests. The study in [25] shows that both delay tests and I DDQ tests detect 180 of the total of 399 defective devices. Most defects that cause logic or timing errors in a CMOS device can also be detected via I DDQ testing. In addition, I DDQ testing also provides high test-parallelism, since fault effects for a large number of faults are simultaneously propagated (pseudo- stuck-at-fault model [27]) and made observable in the form of high quiescent current. This high test-parallelism drastically decreases the number of tests required to detect all such faults. 1.2.1.1 Yield loss or test escape for simple I DDQ threshold settings Typically, the value of the I DDQ threshold is determined heuristically, such as using histogram statistics of the type shown in Figure 1-3, obtained from device testing or probability density of MOSFET channel lengths ([32], [11], and [15]). However, it is well known that if the value of I DDQ threshold is set too low, then many devices that have elevated I DDQ but cannot cause logic or timing errors, or cannot cause violation of any other functional specification, will be declared faulty and discarded. Clearly, this would cause unnecessary yield loss - a complaint commonly raised against I DDQ testing [37]. 9 I DDQ Threshold Defective Devices Sample Frequency Non-defective Devices I DDQ Figure 1-3 Simple I DDQ threshold settings in past technologies. On the other hand, if the value of I DDQ threshold is set too high, a device with a defect that causes logic, timing, or some other functional errors may be declared fault free. In such cases, I DDQ testing causes high test-escape. Approaches in [11] and [26] use circuit-level and switch level models respectively to estimate defect-free I DDQ . These I DDQ estimates provide threshold settings that help avoid any test escape. However, these threshold values do not minimize yield loss. In past technologies, as shown in Figure 1-3, large differences existed between the quiescent current of a defect-free DUT and that of a DUT with a defect that could cause logic, timing, or any other functional error. This made it possible to select a fairly high threshold value of I DDQ current while maintaining low test escape and yield loss rates. 1.2.1.2 I DDQ testing in future technologies In future technologies, transistor sizes will continue to decrease and the number of transistors in a chip will continue to grow. Earlier it was postulated that I DDQ for a fault-free device would increase by six orders of magnitude and reach tens of milli-amperes (mA) due to a combination of several factors, including lower 10 transistor threshold voltages and short-channel effects. For example, short-channel- effects cause weak inversion current, reverse-bias saturation current, punch-through current, drain-induced barrier lowering current, as well as gate-induced drain- leakage-current. If such predictions become true, then not only would I DDQ test methodology become useless, chips would consume impracticably high amount of power and would be rendered unusable. Several changes are hence being made with each new process technology to limit the value of I DDQ for defect-free chips. Due to these changes, I DDQ testing continues to be a viable test methodology. [36] and [15] show that I DDQ testing is feasible in large-scale devices implemented in deep-submicron process, especially when certain changes are made to the fabrication process and the test setup. The I DDQ value for defect-free devices can be reduced to less than 10μA by employing several techniques. Advanced processing techniques such as angled ion-implant can better control channel widths and transistor threshold voltage, V T . Lower test temperatures can reduce I DDQ by ten thousand times, by decreasing the leakage currents via reverse-biased parasitic diodes in CMOS. V T can be decreased temporarily by the use of special substrate voltage during test application, reducing I DDQ due to sub-threshold leakage. On-chip built-in-current- sensors that partition logic blocks under test can enhance the ratio between non- defective and defective I DDQ . 11 I DDQ Threshold Defective Devices Sample Frequency Non-defective Devices I DDQ Figure 1-4 Simple I DDQ threshold settings in future technologies. Despite all the above enhancements, in future technologies, the quiescent current of defect-free devices and those of devices with defects that can cause errors will be of the same order of magnitude, as shown in Figure 1-4. Hence, the selection of an appropriate value for I DDQ threshold is becoming increasingly important to maintain reasonably low levels of test escape and yield loss. 1.2.2 I DDQ test escape and yield loss metrics and threshold selection strategies We propose the use of the system requirements as a reference to determine the value of I DDQ threshold to balance test escape and yield loss or to reduce both. The system-requirements include, for example, correct logic behavior and delay. We do not intend to replace logic tests or delay tests by I DDQ tests. Instead, we propose a new framework to develop I DDQ tests and identify thresholds so as to minimize test escape and yield loss. Since a different I DDQ pass/fail threshold value can be used for each I DDQ test vector (as discussed in [14]), each test vector will have one histogram or I DDQ probability density curve of the type shown in Figure 1-4. A defective device that 12 escapes detection by one vector may be detected by another vector. The above facts can be exploited in many ways. For example, increasing a low I DDQ threshold value for one vector can avoid discarding of defect-free devices while preserving the tests ability to detect all faults it previously detected, except F i . The fault F i would then escape the current vector but may be detected by another vector that has a lower non- defective I DDQ (since I DDQ value is vector dependent [12]). In this manner, a set of test vectors, where each vector has a carefully selected I DDQ threshold value, can reduce yield loss while maintaining low test-escape. 1.2.3 I DDQ threshold profiling, discrimination and profile selection strategies During testing, I DDQ vectors are applied to a device under test (DUT) and the quiescent current for the DUT is measured by the DUT tester for each vector. If the measured value of the I DDQ for a vector is greater than the corresponding threshold, the DUT is declared faulty, and subsequent vectors are not applied. The DUT is declared fault-free only if the measured quiescent current value for every vector is less than the corresponding threshold value. This effect can be demonstrated using the example in Table 1-1. Table 1-1 Example I DDQ profiles and profile sets. Critical current (μA) Fault Profile V 1 V 2 V 3 V 4 F 18 P 18 0 159 179 180 F 5 P 5 0 0 695 695 F 1 P 1 189 0 186 0 F 16 P 16 224 224 0 0 I DDQ threshold (zero yield loss) 224 224 695 695 13 Table 1-1 is based on an example circuit with a set of possible bridging faults, listed in the column entitled Fault. This table also shows critical current values for each of the faults, for vectors V 1 to V 4 . Critical current for a fault and a vector represents the I DDQ value for the vector when the fault has severity just sufficient to cause a logic error (more detailed description of critical current is presented in Section 5.1). Consider an example scenario where the goal is to achieve I DDQ testing with zero-yield loss. Therefore, for each vector, we must set the I DDQ threshold to the maximum critical current for all faults that are excited by the vector. The row entitled I DDQ threshold in Table 1-1 shows such a threshold value for each vector. For example, if an I DDQ value of 300μA is measured for a DUT when V 1 is applied, the DUT will be declared faulty. In the existing I DDQ test application methodologies outlined above, once the measured I DDQ value for a vector exceeds the corresponding threshold, any information that might have been obtained by the application of the remaining vectors is ignored. Any information obtained by previous vectors is also ignored. We propose to collect I DDQ measurements for all I DDQ vectors and use them to develop a new I DDQ discrimination strategy. 14 0 100 200 300 400 500 600 700 800 V1 V2 V3 V4 IDDQ (uA) DUTa Example P18 P5 P1 P16 IDDQ Threshold Figure 1-5: I DDQ profiles for the example in Table 1-1. The new concept of I DDQ fault characteristic profile collectively considers the I DDQ current for each vector for a specific bridging fault. Note that in this type of testing, all I DDQ vectors in the given test set are applied and corresponding I DDQ values recorded and collectively used to decide whether the device under test passes or fails. Each fault characteristic profile for a fault is the set of its critical currents for all vectors. For example, as shown in Table 1-1 in the row entitled F 1 , the corresponding I DDQ profile P 1 is: {189,0,186,0}. Figure 1-5 shows the I DDQ profiles for all the faults in Table 1-1. The new I DDQ discrimination strategy is based on the comparison of the I DDQ fault characteristic profiles and the I DDQ measurements. For a bridging fault that has bridge resistance low enough to cause logic errors (or other specification violations), the I DDQ measurement for each vector will be above the corresponding value in the I DDQ profile that corresponds to the fault; and the DUT will be declared faulty. For a bridging fault with very high resistance, the I DDQ measurements for each vector will be below its I DDQ profile, and the DUT will be declared faulty-free. 15 Consider an example that illustrates how the I DDQ testing profiling method achieves lower test escape or yield loss than previous I DDQ threshold methods. The bars in Figure 1-5 show the measured I DDQ values for an example DUT, DUTa, that has fault F 18 , as {0,191, 215, 216}. Since the fault has higher I DDQ than P 18 for test vectors V 1 to V 4 , DUTa is declared faulty. Let us compare this with the I DDQ testing using the thresholds shown in Table 1-1. Since I DDQ measurements for DUTa for each vector is lower than the corresponding I DDQ threshold {224, 224, 695, 695}, DUTa would be declared defect free and escape the test in a threshold based approach that was defined to obtain zero yield loss. If one fault profile has all its thresholds values below that of another fault profile and both of the profiles are included in a test set, yield loss may be caused. Therefore, only a subset of profiles can be selected from the set of profiles for all faults. Hence, profile selection strategies affect the test escape or yield loss. Several approaches for selection will be discussed in Section 5.2.2. 1.2.4 Objective: I DDQ modeling and threshold selection strategies Our first objective for I DDQ bridging fault testing is to develop a framework for I DDQ testing such that test escape and yield loss is minimized. The framework will include the followings. o A new model to compute the effectiveness of various I DDQ threshold settings for a bridging fault. o Generation of test vectors/sequences to detect bridging faults, 16 o I DDQ threshold selection strategies to achieve desired objectives, such as zero yield loss with minimum test escape or zero test escape with minimum yield loss. The efficiency of our approaches will be measured in terms of test escape and yield loss. We precisely model the bridging fault behavior. As a result, devices with bridging fault resistance values that are too high to cause logic errors are not considered defective. Therefore, discarding of any such DUT is considered yield loss. At the same time, devices with bridging fault resistance values low enough to cause logic or timing errors are considered defective. If any of such DUTs are not identified as defective by our test strategy, then these DUTs are considered test escape. Two I DDQ threshold selection strategies are proposed. o The first strategy provides I DDQ threshold value settings that causes zero yield loss and provides lower test escape than the traditional single I DDQ threshold value strategy. o The second strategy causes zero test escape, by considering not only the non-defective I DDQ [11] and [26], but also the resistances of, and the currents generated by, the target faults. 1.2.5 Objective: I DDQ profiling The second objective for this study is to further reduce test escape and yield loss by exploiting the newly proposed concept of I DDQ fault characteristic profile. Our I DDQ profile framework will includes the followings. o The new concept of an I DDQ threshold profile for a given bridging fault. 17 o The notion of an I DDQ profile discrimination strategy that compares the set of I DDQ measurement values for a DUT against the selected I DDQ threshold profiles. o I DDQ profile selection strategies that select a subset of profiles from the set of all profiles to control test escape and yield loss. We will develop two I DDQ profile selection strategies; one that causes zero test escape and minimizes yield loss and another that causes zero yield loss and minimizes test escape. We will also develop an approach to compute test escape/yield loss and use it to compare our two I DDQ profile strategies with the previous approaches as well as our own threshold-based approaches. 1.2.6 Objective: I DDQ fault excitation pattern Our third objective is to develop the concept of fault excitation patterns. An I DDQ profile scheme that also considers the fault excitation pattern measures the non- destructive leakage current for a device. Two I DDQ profile selection strategies are developed based on the fault excitation pattern. These selection strategies have lower test escape and yield loss than the previous methods. Chapter 5 discusses our research in I DDQ testing for bridging faults. The new model for I DDQ testing is discussed in Section 5.1. Section 5.2 discusses our three I DDQ test strategies. o Threshold selection strategy. o Profile discrimination strategy. o Fault excitation profile discrimination strategy. 18 Chapter 2 Byzantine resistive bridging fault modeling As discussed in Section 1.1.1, a bridging fault may cause intermediate voltages, i.e., voltages between the logic thresholds (V IH and V IL ), at the nodes involved in the bridge. In such cases, the gates in the fanout of the bridging fault site may output the expected or a faulty logic value, but we may not be able to determine which one. Such behavior is called Byzantine behavior and accurate modeling of Byzantine bridges requires high-precision circuit level simulation, such as SPICE simulation. Circuit level SPICE simulation is not feasible for large circuits. It is clearly infeasible during automatic test pattern generation, which often considers billions of partially specified vectors. Therefore, we propose a Byzantine model that is analyzed accurately at the fault site. The logic values at the lines outside of the fault site can be computed at lower complexity using logic-level simulation which is appropriately modified to consider indeterminate values. 2.1 Bridging fault local sub-circuit Consider a case where an intermediate voltage occurs at the inputs of one or more gates in the fanout of the fault site. Due to high gain of CMOS gates, in steady state, the gates in the fanout of the fault site will output logic 1 or logic 0 with a very high probability. However, whether the gate outputs a logic 0 or a logic 1 will be impossible for us to determine even with more accurate analysis, as long as we believe that any voltage at an input of a gate that is between the gates input threshold voltages, i.e., its V IL and V IH , cannot be counted on to reliably produce either of the two possible logic values at its output. 19 SPICE simulation for such sub-circuit around the fault-site can accurately capture such Byzantine behavior. We will define conditions to identify a local sub- circuit for each Byzantine bridge in such a manner that all intermediate voltages and circuit-level details (transistor-sizes, bridge resistances, etc.) that cause them are encapsulated within the local sub-circuit. All nodes outside the local sub-circuit will only receive logic values from the local sub-circuit. Hence circuit-level simulation will be required only for the local sub-circuit and logic-level analysis will be sufficient for the remaining circuit. In this manner, partitioning the logic around the bridge fault site, and defining the detailed behavior of the local sub-circuit will dramatically reduce the computation complexity of test generation and fault simulation. Under the condition stated in previous paragraph, this dramatic reduction in complexity will not cause any inaccuracy. Figure 2-1 An example circuit with a bridging fault, R f . In general, a bridging fault site involves a bridge between two circuit nodes. An example circuit is shown in Figure 2-1. The primary inputs (PIs) are signals c 1 to c 5 , and the primary output (PO) is signal c 16 . The bridging fault is shown as a resistor R f that connects the outputs of OR gates U1 and U2. OR gate U3, Inverter U4, and 20 XOR gate U6 are the gates in the fanout of the bridge site. The sub-circuit within the inner box marked local sub-circuit is the local sub-circuit for this fault. Since the gates in the fanout of the bridging fault site may output the expected or a faulty logic value according to their logic threshold voltage values, the properties of these gates are considered during local sub-circuit analysis. To capture the static characteristics between the voltages at the inputs and the output of each gate, the circuits within the outer box marked local sub-circuit analysis zone are considered. The local sub-circuit for the fault site is defined next. Definition 2-1: Local sub-circuit for a particular bridging fault g, L g , is a sub- circuit that includes the fault site, the gates that drive the fault-site, all inputs of above gates, and the fanout branches (if any) of the fault site. N1 P1 R f c9 N2 P2 c10 … U1 c1 c2 c3 c8 U2 c11 c12 (a) (b) Figure 2-2 Local-sub-circuit for the bridging fault shown in Figure 2-1. For the example circuit and fault shown in Figure 2-1, the local sub-circuit includes the OR gates U1 and U2; their inputs c 1 , c 2 , c 3 , and c 8 ; the lines in the fault 21 site, c 9 and c 10 ; and c 11 and c 12 of the fanout branches of c 10 . The local sub-circuit within the inner box in Figure 2-1 is shown separately in Figure 2-2 (a). (Each OR gate is assumed to be a NOR gate followed by an inverter.) The transistor level schematic for the OR gates, U1 and U2, and the bridging fault resistance, R f are shown in Figure 2-2 (b). The local sub-circuit has inputs (c 1 ,c 2 ,c 3 ,c 8 ) and outputs (c 9 , c 11 ,c 12 ). Once the local sub-circuit is defined, we can carry out analysis of fault effect excitation and fault effect propagation for the bridging fault. Before a target logic gate library can be used for any bridging fault simulations, SPICE simulations are carried out to prepare two tabular representations of the behavior for any bridging fault site for the library. The two tables are described next. 2.2 Bridging fault effect excitation An excitation network is a series connection of the CMOS pull-up network from any gate in the library, to a resistive bridging fault, and finally to the CMOS pull-down network from any gate in the library. We carried out SPICE simulations for all possible combinations of pull up networks and pull down networks in the gate library. Each combination of the pull up and pull down network is simulated with a bridging fault. Since the gates that drive the bridging nodes may have multiple pull- up/pull-down strengths, each excited by a different combination of input values, a total of 324 combinations are simulated for our digital library. We divided the bridging resistance of interest evenly from 0 to 100k ohm in steps of 500ohm for each simulation. The voltage values for the pull up as well as pull down network 22 involved in the simulated bridging node are stored in a fault effect excitation table for the target logic library. These voltage values are retrieved from the fault effect excitation table using the values of three parameters: (i) the types of logic gates driving the lines involved in the bridge, (ii) the logic values applied at their inputs, and (iii) the bridge resistance. The SPICE simulation runtime for the excitation networks on a Sun Enterprise server is less than 1.5 hours. The bridging fault shown in Figure 2-2 (a) is excited by six possible values at the inputs of the local sub-circuit (c 1 ,c 2 ,c 3 ,c 8 ), namely {(1,1,0,0), (0,1,0,0), (0,1,0,0), (0,0,1,1), (0,0,0,1), (0,0,1,0)}. Vf vs Rf 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 Rf (kohm) Vf (V) pull-up node voltage pull-dow n node voltage Figure 2-3 Fault effect excitation curves: V f vs. R f . In this example, which is similar to many real world designs, P1 and P2, shown in Figure 2-2 (b), have identical transistor sizes. Therefore, R f would experience only one distinct pull-up strength from the OR gates, U1 and U2. The same situation applies to N1 and N2 shown in Figure 2-2 (b). The plots of the voltages at the bridging node driven by the pull-up (pull-down) network vs. the 23 possible bridging resistance R f is shown in Figure 2-3. When the bridge resistance is zero, the voltages are equal. Next, we will describe how to compute fault effects at the gates in the local sub-circuit analysis zone by using the parameters from the voltage transfer characteristic curves of these gates along with the fault effect excitation table. Byzantine behavior of a bridging fault is the important factor to be considered. 2.3 Bridging fault effect computation We use the VTC curves of logic gates to define the logic thresholds for the gates in the fanout of the fault site. A VTC curve captures the static characteristics between the voltages at the inputs and the output of a gate. For logic gates with multiple inputs, multiple VTC curves are used to model the gates behavior. We use SPICE simulation to obtain the VTC curves for each input pin of each gate in the target logic gate library. To explicitly capture logically indeterminate values at the fault site, two input threshold voltages, namely V IH and V IL , from the VTC curves are used to determine whether the bridging voltages at the fault site are logic 1, 0, or logically indeterminate. Recall that, V IH and V IL are the input voltage values at which the slope of the VTC curve equals to minus-one (-1). In our framework, we assume that an intermediate voltage between V IL and V IH at an input of a gate causes the gates input value is a logic value, which is unknown to us. This is a reasonable assumption (and supported by our simulations) for two reasons. First, the slope of the VTC curve in this region is very high which helps resolve any intermediate voltage in this manner. Second, small variations in 24 V DD (e.g., due to ground bounce) can cause the output voltage to change from one logic value to its complementary logic value. Only the V IH and V IL values of the simulated VTC curves are stored in a fault response table for the target library. When bridging fault simulation is performed, the V IH and V IL values for the gates in the fanout of the fault site are retrieved from the fault response table. These values are used to identify the boundaries of the bridging fault resistance ranges and determine the logic level behavior of the local sub-circuit for the identified ranges. 2.4 Fault resistance ranges Each bridging fault from a fault list for a device under test is pre-processed to obtain the specific bridging fault behavior before fault simulation or test generation is carried out. All the possible excitation values at the inputs of the faults local sub- circuit are identified. Each excitation value is used to lookup the fault effect excitation table that contains the voltage values at the pull-up and pull-down nodes of the fault site and the corresponding fault resistance. The fault excitation response table for the fault in Figure 2-1 is shown in Table 2-1. The voltage values at the fault site are cross-compared with the threshold voltages for the inputs of the gates in the fanout of the fault site to identify the bridging fault resistance, which causes a voltage at the fault site that is equal to a threshold voltage. The threshold voltages of the gates in the fanout of the fault site in Figure 2-1 are shown in Table 2-2. The resistance is shown in the column entitled Fault resistance in Table 2-1. Since each input of a gate may have different threshold voltages, the threshold voltages shown 25 in column Gate-input# in Table 2-1 and Table 2-2 are designated with the input number of the gate. Table 2-1 Fault excitation response table for the fault in Figure 2-1. Gate Fault resistance Gate-input# Type thresholds [kΩ Ω Ω Ω,kΩ Ω Ω Ω] U4 INV-V IH 1.5V [INF,7.0] U3 input#1 OR-V IH 1.4V [7.0,6.0] U3 input#1 OR-V IL 1.3V U6 input#1 XOR-V IH 1.25V [6.0,5.0] U6 input#1 XOR-V IL 1.15V [5.0,4.5] U4 INV-V IL 1.05V [4.5,3.0] Table 2-2 Threshold voltages of the gates in the fanout of the fault site in Figure 2-1. Gate-input# Type V IL V IH U4 INV 1.05V 1.5V U3 input#1 OR 1.3V 1.4V U6 input#1 XOR 1.15V 1.25V The fault resistance values for various excitation values are sorted, rearranged, and grouped in ranges to obtain the fault characteristic table shown in Table 2-3. Composite value symbols are used to represent the Byzantine bridge excitation and response values. Bridging fault composite value system is described in Section 2.5. Table 2-3 Fault characteristic table for the fault in Figure 2-1. Excitation (c1,c2,c3,c8) Fault effect response (c9,c11,c12) 1: (0,0,1,x),(0,0,x,1) (0,1,1) (0,{D,1},1) (0,{D,1},{D,1}) (0,{D,1},D) (0,D,D) 2: (1,x,0,0),(x,1,0,0) (1,0,0) ({D,1},0,0) (D,0,0) FRRi [kΩ,kΩ] [INF,7.0] [7.0,6.0] [6.0,5.0] [5.0,4.5] [4.5,3.0] [3.0,0] 26 As can be seen in Table 2-1 that V IL and V IH values for the different gates in the fanout of the fault site partition the range of bridging fault resistance. Each range of a bridging faults resistance represents a unique sub-fault that the fault simulator and test generator must process. Each fault resistance ranges (FRR) defined in Definition 2-2 has a unique combination of fault excitations and response values. Definition 2-2: Let L g be a local sub-circuit for a bridging fault g. Fault resistance range R i (FRR Ri ) of L g equals to [R i , R i+1 ], where, R i and R i+1 are such that V f (R i ) and V f (R i+1 ) are respectively equal to two consecutive threshold voltages, Vth i and Vth i+1 , in the fault excitation response table for the gates in the fanout of a line in a bridge fault site. FRR INF represents the FRR that has infinite bridging resistance, which also represents the fault-free behavior of the local sub-circuit. The above fault resistance range concept is similar to the resistance interval and sectioned resistance concepts used in the bridging fault studies in [31] [35], with the extension that we partition the bridging resistance into sub-ranges by considering V IH and V IL values of the gates in the fanout of the fault site to model the Byzantine bridge behavior in a manner that captures indeterminate logic values. The fault characteristic table (Table 2-3) carries similar information as the critical resistance table in [35], with the extension that our fault characteristic table is able to capture the logically indeterminate values at the output of the gates in the fanout of the bridging fault site. 27 2.5 Bridging fault composite value system A composite value system represents the behavior of the fault-free as well as a faulty circuit in a compact manner and enables efficient ATPG and fault simulation implementations. To represent the behavior of Byzantine bridges, we use the D- notation [33] basic values, {0/0}, {1/1}, {1/0}, {0/1} which are denoted by 0, 1, D and /D. An intermediate voltage at an input of a gate in the fanout of a fault site that is expecting logic 1, is represented as {1/1, 1/0} and is denoted by {1,D}. Similarly, an intermediate voltage that occurs when logic 0 is expected is represented as {0/0, 0/1} and is denoted by {0,/D}. Hence, at the fanout of the local sub-circuit, there are six possible composite values, 1, 0, D, /D, {1,D} and {0,/D}. A circuit line, hence, may be assigned any composite value from the power set of the above six composite values. The result power set is the popular 16-valued composite value system [7] that is shown in Table 2-4. Table 2-4 16-valued composite value system with few commonly used symbols. {} {0/0}=0,{1/1}=1,{1/0}=D,{0/1}=/D {1,D},{0,/D},{0,1}=x,{0, D},{1, /D}, {D, /D} {0,1,D}, {0,1,/D}, {0,D,/D}, {1,D,/D} {0,1,D,/D}=X One of the well known advantages of using a 16-valued composite value system is to enhance the resolution of a test generation algorithm which can provide higher fault coverage than a system that uses lower-valued value system. Many test generators use the 5-valued composite value system, {0,1,D,/D,X}, where X represents all combination of the four basic values. Those test generators have the 28 option of using the 16-valued composite value system, hence, taking advantage of the enhanced resolving capability. In contrast, our proposed test generator for Byzantine bridges underline requires using the 16-valued composite value system. Followings are some of the reasons for this requirement. o 16-valued composite value system can capture the indeterminate logic values, {1,D} and {0,/D}. o 16-valued composite value system can propagate fault effect D or /D when in present of the indeterminate logic values. For example {1,D} AND D = D. If the 5-valued composite value system were used, for this case the fault effect would be masked, since X AND D = X. Meanwhile, test generators that use a 16-valued composite value system have larger search space than those using a 5-valued system. We develop new ways to organize search to overcome the complexity increase due to the use of 16-valued system. 2.6 FRR D-cubes Next, we define the notion of FRR D-cubes, which is an extension of the concept of the D-cubes of a single stuck-at-fault [33]. Each pair of fault excitation and response value for an FRR is designated as an FRR cube of the corresponding FRR. Definition 2-3: FRR D-cubes – Let L g be a local sub-circuit for a bridging fault g. Let FRR i be a fault resistance range for g. FRR D-cubes for FRR i , FRR i,j ={[V j ,W j ]} are the set of all two-tuples, [V j , W j ], where V j is a combination 29 of fault excitation values for FRR i for bridge fault g that causes a D or a /D at one or more outputs of L g and W j is the corresponding combination of fault response values. Table 2-5(a) repeats the fault characteristic table in Table 2-3 where (i) the indexed FRRs are shown in the row FRR i , (ii) the FRR cubes that have no D or /D are shaded, and (iii) the un-shaded FRR cubes show FRR D-cubes. For example, FRR 5000 in Table 2-5(a) (i.e. the FRR with maximum bridge resistance of 5kΩ), has an FRR D-cube that can be written as [{(1,x,0,0),(x,1,0,0)}, (D,0,0)]. Table 2-5 FRR cubes for the fault in Figure 2-1. Excitation (c 1 ,c 2 ,c 3 ,c 8 ) Fault effect response (c 9 ,c 11 ,c 12 ) 1: (0,0,1,x),(0,0,x,1) (0,1,1) (0,{D,1},1) (0,{D,1},{D,1}) (0,{D,1},D) (0,D,D) 2: (1,x,0,0),(x,1,0,0) (1,0,0) ({D,1},0,0) (D,0,0) FRR i FRR INF FRR 7000 FRR 6000 FRR 5000 FRR 4500 FRR 3000 (a) Excitation (c 1 ,c 2 ,c 3 ,c 8 ) Fault effect response (c 9 ,c 11 ,c 12 ) 1: (0,0,1,x),(0,0,x,1) (0,{D,1},D) (0,D,D) 2: (1,x,0,0),(x,1,0,0) (D,0,0) FRR i FRR 5000 FRR 4500 FRR 3000 (b) Further steps are carried out to reorganize the fault characteristic table such that the complexity for fault simulation and test generation can be reduced. An FRR is designated as an excluded FRR if none of the fault response values for the FRR equals to D or /D for all possible excitations. For example, FRR 7000 and FRR 6000 of 30 Table 2-5(a) are excluded FRRs as none of the excitation gives D or /D at c 9 , c 11 , or c 12 . FRR INF represents the highest FRR, which also represents the fault-free behavior of the local sub-circuit. The fault free FRR INF is also an excluded FRR. An FRR cube is an excluded FRR cube if none of the fault response values for the cube has D or /D. For example, FRR cube [{(0,0,1,x),(0,0,x,1)},(0,{D,1},1)] of FRR 5000 of Table 2-5(a) is an excluded FRR cube. All excluded FRRs and excluded FRR cubes are not targeted for fault simulations and test generation. Table 2-5(b) shows the reorganized fault characteristic table. In stuck-at testing, one set of D-cubes is associated with a fault. However, in our case, multiple FRRs are associated with a single bridge. We hence need to define coverage for each FRR. Definition 2-4: Covering FRR i – An FRR i is covered (detected) by a vector iff the vector propagates to any primary output a D or /D from any FRR D-cube of the FRR i . Computational complexity of covering a bridging fault can be reduced dramatically if the number of FRRs for a bridge fault can be reduced. FRR and FRR cube equivalence and dominance relationships help collapse or detect the FRRs of a bridge fault. 2.7 Equivalence and dominance of FRR cubes and FRRs FRRs equivalence and dominance relationships will help reduce ATPG system complexity by covering multiple FRRs of a bridge fault without requiring explicit ATPG and fault simulation for each FRR. Equivalence and dominance 31 relationships are defined at FRR cube level, intra-bridging fault level, and inter- bridging fault level. Definition 2-5: Equivalence of FRR cubes – Let FRR i,m and FRR j,n be the FRR D-cubes of FRR i and FRR j of fault g, respectively. FRR i,m and FRR j,n , are equivalent iff excitation and response of the corresponding cubes are identical. Definition 2-6: Equivalence of FRRs -- Two bridge FRRs, FRR i and FRR j , of fault g are equivalent iff all of their corresponding FRR D-cubes are equivalent. Definition 2-7: Dominance of FRRs: Let FRR i,m and FRR j,n be the FRR D-cubes of FRR i and FRR j of fault g, respectively. FRR i dominates FRR j iff FRR i,m ⊇⊇⊇⊇ FRR j,n . For example, as shown in Table 2-5(b), the FRR D-cubes FRR 5000,2 , FRR 4500,2 and FRR 3000,2 have the same excitation and response value [{(1,x,0,0), (x,1,0,0)},(D,0,0)]. Therefore, these FRR D-cubes are equivalent. Since FRR 5000,2 is the only FRR D-cube for FRR 5000 , and it is equivalent to FRR 4500,2 and FRR 3000,2 , FRR 5000 dominates FRR 4500 and FRR 3000 . For any test generation or fault simulation session, the detection of an FRR D-cube would imply detection of (i) all equivalent FRR cubes, and (ii) all equivalent or dominated FRRs. Hence, no additional explicit ATPG or fault simulation session is needed for those FRRs and FRR cubes. Note that FRR equivalence satisfies symmetric and transitive properties. That is, if FRR i is equivalent to FRR j , then FRR j is equivalent to FRR i . Furthermore, if FRR j is also equivalent to FRR k , then FRR i is equivalent to FRR k . 32 We discovered that few FRRs from different bridging faults satisfy dominance or equivalence relationships, and extensive computational effort is needed to identify these relationships. Therefore, such dominance or equivalent relationships are not used in the current research. 2.8 Summary We propose the first model for Byzantine bridges that captures indeterminate logic values caused by bridges. We describe a Byzantine model that is analyzed accurately at the fault site and the model is used to perform correct logic-level simulation as well as to properly guide ATPG for accurate and efficient test vector generation. Furthermore, we defined equivalence and dominance relationships for the proposed bridging fault model to reduce the number of faults to target. Our model accurately and yet efficiently captures behavior of resistive bridging faults. 33 Chapter 3 Bridge fault simulation ATPG for bridge faults generates test vectors for faults in a fault list. However, ATPG has high computational complexity. Running bridge fault simulation for each ATPG generated vector can identify other target faults the vector detects and helps reduce ATPG complexity significantly. The parallel pattern single fault propagation (PPSFP) fault simulation method is widely used for single-stuck-at faults [20]. This method propagates the effect of one fault at a time while simulating multiple patterns in parallel. If w patterns are simulated in parallel, the maximum simulation time speedup for each fault is w times over the simulation time if the patterns are simulated sequentially. The PPSFP method would provide significant speedup for bridging fault, especially since we need to simulate a large number of fault resistance ranges. We developed a PPSFP fault simulator for the proposed Byzantine bridging fault. We first describe our simulation methodology. We then use our simulator to show that existing models and simulators significantly overestimate the coverage of Byzantine bridges. Finally, we compare our simulation methodology with previous approaches. 3.1 Bridging fault simulator composite value system A composite value system represents the behavior of the fault-free as well as a faulty circuit in a compact manner and enables efficient fault simulation implementation. As described in Section 2.5, an intermediate voltage between V IL and V IH at an input of a gate in the fanout of a fault site that is expecting logic 1 in the fault-free case, is represented as {1, D}. Similarly, an intermediate voltage that 34 occurs when logic 0 is expected is represented as {0, /D}. In contrast to test generation, detail information for fault effects is not needed for fault simulation, a lower resolution composite value system is sufficient. Therefore, the above two composite values are assigned the logic symbol χ χ χ χ for fault simulation. (This logic symbol χ χ χ χ is different from the logic symbol x that represents {0,1} for our ATPG.) To represent the Byzantine bridge logic values for fault simulation and for simulations of partially-specified input vectors, a three-valued system that is composed of the symbols logic 1, logic 0, and logic χ χ χ χ, is used. Two storage bits {v,u} are used to encode the three-valued symbols. We use the commonly used encoding scheme for the three-valued system (Table 3-1). Table 3-1 Encoding scheme for the three-valued system. Symbol v u 0 0 0 1 1 1 χ χ χ χ 1 0 Not used 0 1 Table 3-2 Storage structure at a circuit node. Fault free value Faulty value Bit v u v f u f 1 v 1 u 1 v f1 u f1 2 v 2 u 2 v f2 u f2 w v w u w v fw u fw Each circuit node is allocated storage for both fault-free values and faulty values. Since a storage word has w bits, a circuit node can store w fault-free and w faulty values for w vectors. For our implementation, w equals to 64. Storage structure for our implementation to represent values implied at a circuit node for w 35 vectors is illustrated in Table 3-2. During fault simulation, parallel bit-wise logic operations (Table 3.3 of [17]) are used to evaluate the three-valued symbols. 3.2 Fault simulation procedures Figure 3-1 shows the outline of the proposed bridging fault PPSFP simulation procedure. A device under test (DUT) is read after the library is initialized. A set of w vectors is read and simulated in parallel for the fault-free version of the DUT using an ordered levelized list. The fault-free simulation results are stored in the fault free value variable at each line. Next, a bridging fault is read for faulty circuit simulation. Each bridging fault may have multiple FRRs. Using the allocated faulty value variables faulty circuit simulation is executed for each excitation of a selected FRR. Faulty circuit simulation results are then compared with the fault free simulation results and the FRR is marked as detected if any output has logic 0 for fault-free and logic 1 for faulty simulation, or vice versa. The process is repeated until all bridging faults from the input fault list and all vectors in the input vector set are simulated. The simulator processes each fault resistance range as a single fault entry. 36 Figure 3-1 Proposed bridging fault PPSFP simulation procedure. 3.3 Fault excitation check and fault effect propagation For an FRR to be detected, the FRR must be excited by at least one of the w vectors, and the fault response must be propagated to at least one primary output. An FRR is excited if the values implied via fault-free simulation at the inputs of the local sub-circuit are identical to the excitation values for the corresponding lines in the Read library fault effect excitation table and library fault response table; Read DUT; For each w vectors { Run fault free logic simulation; For each fault in the input fault list { Read fault characteristic table for the fault; For each fault excitation vector of the fault characteristic table { Compute excitation record for the fault characteristic table; } } For each excited fault resistance range (FRR) of the fault characteristic table { Run selective simulation in the transitive fanout of the FRR local sub- circuit; Current fault resistance range is detected if it is excited and the value at any PO is logic 0 for fault-free and logic 1 for faulty version, or vice versa; } 37 fault characteristic table. Before the faulty circuit simulation is performed, we compute and record the excitation status for all of the excitation values using the fault characteristic table. This excitation record is also used after the faulty simulation for the current bridging fault is complete. If no FRR of the bridging fault being simulated is excited by the current set of w vectors, faulty circuit simulation is skipped for this bridging fault. On the other hand, faulty circuit simulation is scheduled for the current fault if one or more of its FRRs are excited. However, only those FRRs that are excited are scheduled for faulty circuit simulation. During faulty circuit simulation, some of the w vectors may not excite the current FRR. Hence, by inspecting the excitation record, the faulty circuit simulation results for the corresponding vectors are ignored. Typically, a bridging fault affects only a fraction of the circuit lines. To speedup faulty circuit simulation, only values at the gates in the transitive fanout of the local sub-circuit are recomputed. First, we mark the lines in the transitive fanout of the local sub-circuit using a pre-computed levelized task list. Second, the marked lines are assigned the bridging fault response vector from the fault characteristic table. Third, similar to fault-free simulation, parallel bit-wise logic operations are used for faulty circuit simulation. The marked lines that are on the transitive fanout path of the local sub-circuit are unmarked after the faulty circuit simulation for the FRR is completed. 38 We found that fault simulation can be accelerated by preloading more than w vectors per fault simulation iteration. As a result, we reduce the total number of times the fault characteristic table must be loaded. 3.4 Previous bridging fault simulation studies Resistive bridging fault simulators are implemented in [35][22][34][9]. We discussed the modeling differences in Section 1.1.1. Since previous simulators from [35][34][9] process one target fault per test pattern, and the simulator in [22] uses pseudo-PPSFP that requires intensive computation for fault condition set-operations, they can only process a limited number of bridging faults. To resolve such limitation, we take advantage of parallel bit-wise logic operations with the PPSFP method and are able to process 10 times more bridging faults. There are two major challenges for Byzantine bridging fault modeling and simulation computations. First, our three- valued composite value system for representing the Byzantine bridge behavior requires double the number of simulation operations than the two-valued logic simulators used in the previous studies. Second, when Byzantine bridge behavior is considered, the number FRRs is typically almost two times more than conventional resistive bridging fault models. Our fault simulator is able to overcome these increases in computational complexity by the simulation time speedup obtained by our use of the PPSFP simulation, and the fault characteristic table optimizations discussed in Section 2.6 and Section 2.7. 39 3.5 Fault simulation results We used our methodology to simulate benchmark circuits. For a given bridging fault list, we use an ATPG for bridging faults to generate test sets. We used the ATPG [18] that uses the wired-AND bridging fault model. Our fault simulator uses the generated test sets along with the original fault list to compute coverage. Our bridging fault simulator does not consider bridging faults with feedback. Since PPSFP method is able to process large fault sets, our simulator can evaluate all possible bridging faults (non-feedback) for each of the circuits. Moreover, due to high complexity of ATPG, we only select a subset of all possible non-feedback bridging faults from the complete list. The number of faults in the subset is chosen to be around 200,000. Bridging fault simulation results are shown in Table 3-3. The approach in [31] uses a weighted distribution for bridging fault resistance values to compute coverage. We compute bridging fault fault-coverage by dividing the number of detected bridging fault resistance ranges by the total number of bridging fault resistance ranges. In our approach, each bridging fault resistance range is identified as undetected or detected (DetFRR). We discuss the coverage of FRRs ahead. The wired-AND model fault simulator reports fault coverage of almost 100%, much higher than that for our model of the bridging faults. These high fault coverage results agree with the study in [23], which shows that simple bridging fault models do not guarantee detection of faults that employ more accurate models. 40 Table 3-3 PPSFP Bridging fault simulation results. C432 C499 C880 C1355 C1908 C2670* C3540* C5315* C6288* C7552* NumBF 9132 16681 81899 90165 307416 171603 206839 156699 191363 163137 # of vec.** 157 149 207 399 557 581 540 299 61 271 Fault simulation with wired-AND Model DetBF 8994 16513 81669 89407 304900 171058 205575 156613 191347 160625 DetBF% 98.5% 99.0% 99.8% 99.2% 99.7% 99.9% 99.7% 100.0% 100.0% 98.5% Fault simulation with proposed model NumFRR 57926 59338 487627 484510 1762577 840662 1080470 793604 1189751 885064 DetFRR 31828 33129 306481 191483 963471 467956 638858 462903 506485 496737 DetFRR% 54.9% 55.8% 62.9% 39.5% 54.7% 55.7% 59.1% 58.3% 42.6% 56.1% CPU Time (mm:ss) 00:07 00:05 00:21 00:39 186:59 00:38 05:05 01:08 06:29 01:15 Fault simulation with Zero Bridging Fault Resistance method NumFRR 9132 16681 81899 90165 307416 171603 206839 156699 191363 163137 DetFRR 8862 15905 81045 66924 301082 169640 205417 155640 191234 161074 DetFRR% 97.0% 95.3% 99.0% 74.2% 97.9% 98.9% 99.3% 99.3% 99.9% 98.7% Over estimate 42.1% 39.5% 36.1% 34.7% 43.3% 43.2% 40.2% 41.0% 57.4% 42.6% Fault simulation with Sectioned Bridging Fault method NumFRR 33451 29840 265957 280095 968766 432949 529141 413154 642472 472482 DetFRR 30624 26225 255032 219427 906764 402814 496885 393348 519580 437704 DetFRR% 91.5% 87.9% 95.9% 78.3% 93.6% 93.0% 93.9% 95.2% 80.9% 92.6% Over estimate 36.6% 32.1% 33.0% 38.8% 38.9% 37.4% 34.8% 36.9% 38.3% 36.5% **: Vectors generated by wired-AND model ATPG *: Partial fault list to reduce ATPG CPU time Simulations are run on a 2.4GHz Core2 CPU 3.6 Comparison with Zero Bridging Fault Resistance method The study in [23] considers that bridging faults with zero resistance may cause intermediate voltages on the fanout nodes of the fault site. For zero bridge resistance, such intermediate voltages affect less than 0.007% of the total bridging fault coverage. Intermediate voltage values from Byzantine bridging faults can hence be ignored if the bridging resistance is always zero. However, the assumption that bridging faults have only zero resistance is overly optimistic. Since our proposed model considers not only resistive bridging fault, but also Byzantine bridging fault behavior, the number of FRRs is significantly higher than the zero resistance bridging fault model. For example, Byzantine bridging fault simulation for C6288 41 has 5 times more FRRs than that for the zero resistance bridging fault simulation. Therefore, modeling only zero bridging fault resistance would significantly overestimate the total fault coverage, e.g., as 57.4% for C6288. The corresponding coverage and the overestimated FFR coverage for the zero bridge resistance approach are reported in Table 3-3. 3.7 Comparison with Sectioned Resistance method As discussed in Section 2.4 regarding the bridging fault studies in [31][35], fault resistance range concept is called resistance interval and sectioned resistance, respectively. Both these methods do not consider V IH as well as V IL values of the gates in the fanout of the fault site to model the Byzantine bridge behavior in a manner that captures indeterminate logic values. Hence, both these methods overestimate in their fault coverage. To determine the amount of overestimation for the sectioned resistance approach, we modified our approach to use a single threshold instead of distinct V IL and V IH values. Note that each input of each gate can still have a distinct (single) threshold voltage value. This modified approach is identical to the sectioned approach [35]. The corresponding coverage and the overestimated FFR coverage for sectioned approach are reported in the last three rows of Table 3-3. This clearly shows that the previous approaches significantly overestimate coverage. Note that even a 1 to 2% overestimation in coverage is really significant, since it can lead to a significant underestimation of defect level, i.e., the number of defective chips shipped to customers. 42 Hence, our experimental results clearly show that it is critical to consider indeterminate logic values caused by bridging fault to avoid the risk of seriously overestimating coverage and compromising test quality. 3.8 Summary We have developed a bridging fault simulator to compute the fault coverage and compared our coverage with previous approaches. This fault simulator uses the proposed model for Byzantine bridges that captures indeterminate logic values caused by bridges. Our model and fault simulator accurately and yet efficiently capture resistive bridging faults. We demonstrate that the fault coverage can be seriously overestimated by all previous approaches. This demonstrates the necessity of the proposed bridging fault model and the proposed fault simulator. 43 Chapter 4 Bridging fault ATPG 4.1 Introduction As we describe in Chapter 1, many studies ([35][22][34][9]) show resistive bridging is an important class of faults. We have proposed the first Byzantine resistive bridge model that captures the indeterminate logic values caused by bridges (Chapter 2). We have also developed a bridging fault simulator to compute the fault coverage for this model (Chapter 3). We have demonstrated that all previous approaches seriously overestimate fault coverage. Hence, an ATPG algorithm that explicitly targets Byzantine resistive bridges is required to obtain high fault coverage for this fault model. Many ATPG algorithms for resistive bridging faults ([24][35][34][10]) have been developed. In [34], the ATPG targets only the highest bridging fault resistance; faults with lower bridging resistance are not targeted and hence may not be covered. Our proposed ATPG considers each fault resistance range as a separate fault. More importantly, none of the previous ATPG algorithms considers the Byzantine resistive bridge behavior, namely, potentially inconsistent interpretation of the intermediate bridging voltage by the different gates in the fanout of the fault site. Next, we describe the key challenges in developing the proposed ATPG and the research tasks we will undertake to overcome these challenges. Compared with previous ATPG algorithms for bridging faults, our task of generating tests for Byzantine bridging faults has significantly higher complexity. For example, the proposed ATPG must target a significantly longer fault list that 44 includes multiple FRRs for each bridge. Therefore, efficient modeling of the faults from the perspective of ATPG sub-tasks is essential. Our first objective is to derive the Byzantine bridge model for the ATPG by considering the following. o The fault model must explore fault equivalent and dominance relationships to reduce the number of explicit test generation and fault simulation runs. These relationships are described in detail in Section 2.7. o The fault model must identify the outputs of the fault site that have indeterminate logic values. Identifying such outputs and the circuit lines that are in their transitive fanout can reduce the complexity of the ATPG sub-tasks. Section 4.3.3 describes our approach. As described in Section 2.5, the proposed algorithm must use a more complex composite value system. Therefore, our second objective is to define efficient ATPG sub-tasks that are specific to Byzantine bridges. We introduce such new ATPG sub-tasks in Section 4.2. Our third object is to integrate the proposed Byzantine bridging fault simulator (described in Chapter 3) with this new ATPG algorithm to derive a complete Byzantine bridging fault ATPG system. Consequently, this novel ATPG system is capable of processing logic blocks of realistic size and generates compact and accurate voltage tests for resistive bridging faults in CMOS ICs. 45 4.2 ATPG procedures In this section, we describe the main procedures used by our ATPG algorithm for the proposed Byzantine bridging fault model. The proposed ATPG algorithm is based on the D-algorithm [33]. The proposed ATPG algorithm (as shown in Figure 4-1) constitutes various ATPG sub- tasks. Here we outline the proposed algorithm and its key procedures. More details on how the proposed ATPG algorithm is used to generate a test set are described in later sections. !" " #$ % " &#$ '$ () " '$ % " &'$ " * % " Figure 4-1 Modified D-algorithm ATPG procedures for Byzantine bridges. 46 The first ATPG sub-task in Figure 4-1 is the fault selection sub-task, which selects an FRR cube of an FRR of a bridging fault. Then, the local sub-circuit of the FRR is inserted into the circuit under test (CUT). The next two major ATPG sub- tasks are D-drive and line justification sub-tasks. The D-drive sub-task (Section 4.7) propagates the fault effect of the FRR to the primary outputs of the CUT; and the line justification sub-task (Section 4.8) justifies the unjustified lines, i.e., the lines with assigned values that are not completely implied by the values at their fanins. These two ATPG sub-tasks are executed iteratively until a test is found or the fault is proven untestable. Two sets of gates of the CUT, the D-frontier, DF, and the J-frontier, U, (Section 4.3 of [17]) store the ATPG search status, and are maintained by the sub- tasks. The D-frontier contains the set of gates, where the output of each gate of the set is assigned an incompletely specified value whose set representation includes a basic value D or /D and a fault effect appears at one or more of its inputs. The J- frontier contains the set of gates, where the value assigned at the output of each gate in the set is not uniquely obtained by implication of the value at its inputs. During the execution of the D-drive sub-task the results of two other ATPG sub-tasks, x-path check and unique D-drive, are used. X-path check (Section 4.5.2.2 of [17]) provides the status of tracing potential propagation paths for a gate in the D- frontier. Unique D-drive sub-task indicates if there is only one gate remaining in the D-frontier. 47 The D-drive and line justification ATPG sub-tasks activate the logic implication sub-task. The logic implication sub-task (Section 4.9) determines the logic values that appear at various lines of a circuit as a result of the values assigned to some of its line. If the search for a test fails, the backtracking (Section 4.3 of [17]) ATPG sub-task is activated, which reviews the most recent assignment that was made and replaces it by an alternative assignment. D-algorithm paradigm is selected for development of our proposed ATPG algorithm for Byzantine fault because of the following reasons. The Byzantine fault model we have developed typically identifies necessary excitation and propagation conditions at multiple lines near the fault site. These necessary conditions can be used to constraint the search space to find a test for the fault. D-algorithm is well known for constraining the search space by using the identified necessary conditions at multiple lines of a circuit by iteratively performing the abovementioned sub-tasks. D-algorithm reduces the search space independent of the specific location of the fault site or the size of the circuit involved at the fault site that are uniquely defined by our Byzantine fault model. 4.3 16-valued evaluations As far as we know, all previous bridging fault ATPG algorithms use the 5- valued value system. However, this composite value system is insufficient to represent the behavior of Byzantine bridges (discussed in Section 2.5). In contrast, we propose to use the 16-valued composite value system that captures the 48 indeterminate output conditions that occur for Byzantine bridges. Table 4-1 shows the 16-valued composite value system and few of the commonly used symbols. In this section we first describe 16-valued logic implications and cube covering for fault free logic gates. We then describe the 16-valued fault propagation for the Byzantine bridging fault site. 4.3.1 16-valued logic implication A fault free logic gate output has 16 possible composite values where each is a combination of four basic values. The composite logic value on the output of the gate is obtained by table look up which can speed up the logic value evaluation process. We use 16-valued tables to compute the fault free behavior of logic gates. The 16-valued table for each type of logic gate is derived from the basic value table of the corresponding gate. Table 4-1 shows the basic value truth table for the 2-input NAND gate. Table 4-1 Basic value truth table for 2-input NAND gate. NAND Input-1 gate 0 1 D /D 0 1 1 1 1 1 1 0 /D D D 1 /D /D 1 Input-2 /D 1 D 1 D Multiple input logic gates are evaluated via multiple look-ups of the composite value table of the two input logic gate. The logic implication, line justification and D-drive ATPG sub-tasks (Section 4.2) evaluate logic values using these 16-valued tables. 49 4.3.2 16-valued logic cube covers A compact representation of the fault free logic function can be derived by using the notion of cube-cover [33]. The propagation cubes of a gate propagate the fault effect at one or more inputs of the gate to its output; singular cubes of a gate imply logic value 1 or 0 at the output of the gate. The highlighted entries in Table 4-1 represent the propagation cubes for the 2-input NAND gate; and the remaining entries are the singular cubes. The notion of cube-cover is useful for the line justification ATPG sub-task. For example, if the output value of a 2-input NAND gate is assigned an incompletely specified value whose set representation includes a basic value 0, according to the singular cubes of the NAND gate from Table 4-1, both its inputs must contain basic value 1. For an ATPG algorithm that uses 16-valued composite value system, the behavior of a fault free 2 input NAND gate can be represented by 50 singular and propagation cubes. The cube combinations become more numerous for gates with multiple inputs. We derived compact representations for the cube-cover for multiple- input gates. Table 4-2 shows the example for a multiple-input NAND gate. For example, an incompletely specified basic value 1 on the output of a two-input NAND gate must be obtained by a 0 at any input, or a D at one and a /D at another. We derived similar representations for other gate types. With the proposed 16- valued cube cover definitions, the complexity for the ATPG algorithm is reduced significantly. 50 Table 4-2 Compact cube-cover representations for a multiple-input NAND gate. NAND gate Implication basic values Input line basic values 0 1 at all inputs Singular cubes 1 Case1: 0 at any input Case2: /D on one of the input and D on another input D /D at a input and other inputs have either 1 or D Propagation cubes /D D at a input and other inputs have either 1 or /D We just describe the cube-covers for basic values. For a composite value, the cube cover properties are applied repeatedly for each basic value contained in the composite value. In Section 4.8.1 we proposed a new scheme to simplify the compact the cube-cover representation from Table 4-2 to further reduce the complexity of ATPG algorithm. 4.3.3 16-valued FRR D-cubes One of the goals of an ATPG algorithm is to assign more specific logic values to the lines of a circuit to generate a test to detect the fault under consideration. In this section, we analyze the lines of the circuit under test to initialize some lines to more specific values or to mark some lines with special attributes. These steps significantly reduce the number of ATPG decision branches. The following sections describe new properties for the outputs of a local sub- circuit and internal lines to a local sub-circuit. These new concepts are unique properties for Byzantine bridges and are not considered by any previous ATPG algorithm. 51 4.3.3.1 Inputs of a fault free gate Since the inputs of a fault free gate can only take values 0, 1, or x ({0,1}) if the inputs are not in the transitive fanout of the fault site (and not the lines internal to the local sub-circuit corresponding to the fault), we initialize these lines with the more specific composite value x at the beginning of the ATPG session. 4.3.3.2 Outputs of local sub-circuit As discussed in Section 2.5, at the outputs of the local sub-circuit, there are six possible composite values, 1, 0, D, /D, {1,D} and {0,/D}. We divide the outputs of the local sub-circuit into three output types. o FRR singular outputs are the outputs of the local sub-circuit that have composite value 0 or 1. o FRR indeterminate outputs are the outputs of the local sub-circuit that have composite value {1,D} or {0,/D}. o FRR propagation outputs are the outputs of the local sub-circuit that have composite value D or /D. We derive more specific initialization values for the lines in the transitive fanout of the fault site to further bound the possible composite values. This is done according to the type of FFR outputs from which these lines can be reached. o Initialized with x Composite value x is assigned to the lines that are in the transitive fanout of FRR singular outputs but not of the FRR indeterminate outputs or the FRR propagation outputs. A line in this category is called an FRR singular line. Since these lines do not carry 52 any fault effect, they are handled like the lines that are not in the transitive fanout of the fault site. o Initialized with X Composite value X is assigned to the lines that are in the transitive fanout of any FRR propagation outputs or any FRR indeterminate output. Any line in the transitive fanout of any FRR propagation output (independent of whether it is also in the transitive fanout of any FRR singular output or FRR indeterminate output) is called an FRR propagation line. As these lines may lead to detection of the fault (see Definition 2-4), lines of this type are recognized by x-path check and unique D-drive ATPG sub-tasks for fault effect propagation. Any line in the transitive fanout of any FRR indeterminate output but not of any FRR propagation output (independent of whether no matter if it is in transitive fanout of any FRR singular output) is called an FRR indeterminate line. Since these lines cannot carry fault effect, i.e., neither composite value D or /D, these lines cannot lead to detection of the fault. However, these lines are also initialized to composite value X to accurately compute the indeterminate behavior of Byzantine bridges, as indeterminate values may help propagate fault effect during D-drive ATPG sub-task. For example, when an indeterminate logic value {1,D} is NANDed with the fault effect value D, it propagates the fault effect at the gate input by implying the composite value /D at the output of the NAND gate. However, values at such lines themselves cannot be considered as carrying a fault effect. 53 An attribute associated with each circuit line is defined and updated to specify the type of line. 4.3.3.3 Internal lines of a local sub-circuit In this section, we analyze the values at the internal lines of the local sub- circuit. This analysis is useful for indirect logic implication ATPG sub-task (Section 4.4). As defined in Definition 2-1, a local sub-circuit may include the stem of a fanout system. A stem of a fanout system inside a local sub-circuit is an internal line of the local sub-circuit. Definition 4-1 For a local sub-circuit of a particular bridging fault, the nominal value at an internal line is the fault free value of the line. The possible nominal values at the internal line of a local sub-circuit are composite value 0 and 1. 4.4 A Byzantine ATPG example In this section, we illustrate a simplified bridge fault ATPG with the aid of an example to show the basics of the proposed ATPG algorithm. In this example the ATPG targets the bridge between c 2 and c 10 of the CUT shown in Figure 4-2 where the FRR D-cube, FRR 4500 is selected. The FRR D-cube under consideration is [(c 2 ,c 3 ,c 8 ),(c 2 ,c 11 ,c 12 )] = [(0,1,1),(0,{1,D},D)]. We will describe the intermediate results from some of the ATPG sub-tasks (as shown in Table 4-3). Note that c 2 is both an input and an output of the fault site and c 10 is an internal line of the local sub-circuit. 54 Figure 4-2 An example circuit with FRR 4500 between c 2 and c 10 . Table 4-3 ATPG for the example in Figure 4-2. Step# 1 2 3 4 ATPG sub-tasks FRR Insertion Implication D-drive Line justification Line index Line attributes c 1 PI x x x 1 c 2 PI, LSC FRR sing. o/p 0 0 0 0 c 3 PI, LSC 1 1 1 1 c 4 PI x 1 1 1 c 5 PI x 1 1 1 c 6 x 1 1 1 c 7 x 1 1 1 c 8 LSC 1 1 1 1 c 9 FRR sing. line x x x 1 c 10 LSC internal - - - - c 11 LSC FRR indet. o/p {1,D} {1,D} {1,D} {1,D} c 12 LSC FRR prop. o/p D D D D c 13 FRR indet. line X {0,/D} {0,/D} {0,/D} c 14 FRR prop. line X /D /D /D c 15 FRR indet. line X {0,1,/D} {1,/D} U 1 c 16 PO FRR prop. line X {1,D} DF D D PI: primary input, PO: primary output, LSC: local sub-circuit, DF: D frontier, U: J frontier. See Section 4.3.3 for the line attribute definitions. Step 1 FRR Insertion: The first step of the ATPG is to insert the selected FRR into the DUT netlist. According to the values at the outputs of the local sub- 55 circuit ((c 2 ,c 11 ,c 12 ) = (0,{1,D},D)), we mark c 2 as an FRR singular output, c 11 as an FRR indeterminate output, and c 12 as an FRR propagation output. Since c 14 and c 16 are in the transitive fanout of c 12 , an FRR propagation output, they are marked as FRR propagation lines. c 13 and c 15 are in the transitive fanout of c 11 , an FRR indeterminate output but not an FRR propagation output, hence, they are marked as FRR indeterminate lines. Since c 9 is in the transitive fanout of c 2 , an FRR singular output, it is marked as an FRR singular line. FRR indeterminate lines and FRR propagation lines are initialized with composite value X and other lines are initialized with composite value x. c 10 is the only internal line of the local sub-circuit. It is not initialized with any value; and its nominal value is stored in the fault characteristic table of the fault in case logic implication ATPG sub-task needs to refer to this value. Step 2 Implication: Implication is performed after each step. It is found that the gate driving c 16 is in the D-frontier, DF. In addition, this is the situation for unique D-drive (only one gate in the D-frontier). Step 3 D-Drive: The D-drive sub-task is completed successfully and after assigning c 16 with composite value D. It is found that c 15 is in the J-frontier, U. Step 4 Line justification: The composite value for c 15 at the end of Step 3, {1,/D}, is more specific than the implication value, {0,1,/D}. Since c 15 is an FRR indeterminate line which cannot be reached by any FRR propagation output, c 15 does not carry any fault effect. Hence, justifying composite value /D at c 15 would cause 56 future implication conflict. A heuristic decision of justifying c 15 with composite value 1 is selected. J-frontier is empty and a test, (c 1 ,c 2 ,c 3 ,c 4 ,c 5 )=(1,0,1,1,1), is found. 4.5 Static indirect implication Static indirect implication ATPG sub-task identifies indirect implications in a pre-processing step, and thus, reduces the amount of search performed by ATPG. We modify the static indirect implication described in Section 4.4.3 of [17] for Byzantine bridge ATPG. This discussion will focus on the unique properties of Byzantine resistive bridges with respect to static indirect implication, which are not studied by any previous ATPG algorithm. Two types of static indirect implications are identified before the ATPG process. Global indirect implication: value of c j , v(c j ), equals u implies value of c i , v(c i ), equals w, where u and w equals to either logic-0 or logic-1. The deduced indirect implication, v(c j )=u v(c i )=w, is used during the logic implication ATPG sub-task. For example, the circuit in Figure 4-2 has one deduced global indirect implication: v(c 14 )=1 v(c 8 )=0. Fixed-value-logic implication: v(c j )=K, where K is a fixed-value-logic, independent of the input vector applied to the circuit. The circuit in Figure 4-2 has no deduced fixed-value-logic implication. The identified indirect implications are utilized 1) when a fault characteristic table is prepared, and 2) when the logic implication ATPG sub-task is performed. 57 When a fault characteristic table is prepared for a fault, fixed-value-logic implications may be utilized. An FRR cube is excluded from the fault characteristic table if its excitation value is in conflict with any fixed-value-logic implication at the fault site. For example, if one of the lines involved in a bridging fault expects an excitation value of logic-1 while a deduced fixed-value-logic implication at this line equals to logic-0, then, the bridging fault excitation condition is unsatisfied. Hence, any FRR requiring such excitation are excluded from the fault characteristic table of this fault. The identified indirect implications are used every time logic implication sub-task is executed. Since the deduced indirect implications are identified using the fault free version of the circuit, the implications are used only for lines without fault effect. The values at FRR indeterminate lines and FRR propagation lines are affected by the fault, i.e., these lines contain basic value D or /D. Hence, FRR indeterminate lines and FRR propagation lines are not considered for any deduced indirect implication. In order words, the results of static indirect implications are used only at the following types of lines. o Internal lines of a local sub-circuit (Section 4.3.3.3). o FRR singular lines (Section 4.3.3). o The lines that are not in the transitive fanout of the fault site. Assigning indirect implication values to any line of a local sub-circuit causes implication conflict if the assigned value is not equal to the value specified at the line by the fault characteristic table. 58 4.6 Search space data structure The D-algorithm establishes the paradigm of searching the space of decisions of ATPG sub-tasks and the alternatives local value assignments. We defined an efficient stack data structure (as depicted in Figure 4-3) to store the search tree information. The stacks store and retrieve decisions and/or circuit status in first-in- last-out order. Figure 4-3 Search tree data structure. During ATPG sub-task execution, three stacks are used to store a snapshot of the circuit status. The three stacks are Implication stack, D-frontier stack, and J- frontier Stack. The Implication Stack tracks the implication operations. The D- frontier Stack has snapshot of the D-frontier, DF. Each entry of the D-frontier Stack includes x-path-check attributes and the alternatives of local assignments for the D- frontier. J-frontier Stack has snapshot of the J-frontier, U. Each entry of the J-frontier Stack includes the alternatives of local assignments for the J-frontier. Pointers for 59 these three stacks are stored in Decision Stack. Decision Stack handles D-drive and line justification decisions. Note that the circuit status can be regenerated instead of being stored in the stacks. We decided to store the information such that we can retrieve the circuit status without re-computing. This data structure for the ATPG search tree is updated and used by the D- drive, line justification and backtracking ATPG sub-tasks. 4.7 D-drive D-drive ATPG sub-task propagates fault effect to primary outputs. We modify the D-drive concept from [33] for Byzantine bridging faults. This section describes the detailed procedures of the D-drive ATPG sub-task (as depicted in Figure 4-4) for a Byzantine fault. Before D-drive ATPG sub-task is called to propagate fault effect to the primary output lines, additional conditions are checked. Logic implication, x-path check and unique D-rive must be successfully completed before D-drive is executed. In order to propagate the fault effects to the primary output lines, we select a gate from the D-frontier, such that this gate is the closest to the primary output lines. The identified D-frontier is assigned with D or /D; and this decision is pushed to the Decision Stack. If subsequent logic implication or x-path check fails, D-drive sub- task activates backtracking which restores DF, U, and circuit states, and pops the Decision Stack. 60 Figure 4-4 Implementation details of D-drive ATPG sub-task. 4.8 Line justification Line justification ATPG sub-task is discussed by many previous studies ([7][2][33]). When forward implication is executed for a gate and the original value at the output of the gate is more specific than the forward implication result, the original value is unjustified. J-frontier, U, contains all gates that are unjustified. Line 61 justification ATPG sub-task selects a gate from U and justifies the unjustified line according to the cube-coverings of the gate. A test is found when U is empty. 4.8.1 Proposed cube enumeration scheme We propose a simple but efficient cube enumeration scheme that reduces the number of justification enumerations for the propagation cubes from N-1 to one, where N is the number of inputs of a gate. As far as we know, this simple scheme is not used by any previous ATPG algorithm. This scheme is applicable not only to Byzantine bridging faults but also to any ATPG that uses a high-valued composite value system. Here is the key concept for the proposed scheme. If justifications are not successful for all the singular cubes, the number of remaining enumerated justifications for the propagation cubes may be reduced based on the justification results of the singular cubes. Table 4-4 shows the 16-valued cube-coverings for a 2-input NAND gate with output c j and inputs c i0 , and c i1 . Figure 4-5 shows the enumeration example to justify a value /D at c j with propagation cube number 1, [(c i0 ,c i1 ),c j ]=[(D,{1,D}),/D], as shown in Table 4-4. This example assumes that the inputs of the gate implies composite value of {0,1,/D} at output c j . To justify /D at c j , we only have to justify a value D at c i0 . Justifying {1,D} at c i1 is unnecessary. It is because, justification for all enumerated singular cubes, including cubes [(D,0),0] and [(D,/D),0], have failed in previous justifications, hence, the value at c i1 must not be 0 or /D. 62 Table 4-4 16-valued cube-coverings for 2-input NAND gate Singular cubes Propagation cubes Cube# c i0 c i1 c j c i0 c i1 c j 1 1 1 0 D {1,D} /D 2 0 X 1 {1,D} D /D 3 X 0 1 {1,/D} /D D 4 D /D 1 /D {1,/D} D 5 /D D 1 cj={1,/D} cj=1 (0,X) (X,0) (D,/D) (/D,D) (ci0, ci1) cj=/D (D,{1,D}Dontcare) ({1,D},D) (ci0, ci1) cj={1,/D} implication={0,1,/D} ci0 ci1 (ci0,ci1) must not be (D,0) or (D,/D) Figure 4-5 Enumeration example to justify /D at gate output c j . Hence, applying the same analysis to an N input NAND gate, we would have enumerating N-1 propagation cubes to justify D at the first input and {1,D} at each of the remaining N-1 inputs. Actually, we need to enumerate only one propagation cube to justify D at the first, and the enumeration of propagation cube {1,D} at each of the remaining N-1 inputs are not necessary. This scheme reduces the number of enumeration propagation cubes from N-1 to 1. Table 4-5 shows the proposed cube enumeration scheme. 63 Table 4-5 Proposed justification enumeration scheme for a multiple-input NAND gate. NAND gate Implication basic values Input line basic values 0 1 at all inputs Singular cubes 1 Case1: 0 at any input Case2: /D on one of the input and D on another input D /D at a input and other inputs are dont care Propagation cubes /D D at a input and other inputs are dont care 4.8.2 Line justification procedures Line justification ATPG sub-task is executed after a successful execution of D-drive sub-task. An entry from J-frontier, U, is selected and decisions for the justification alternatives are stored in Decision Stack (Section 4.6). If an alternative causes implication conflict, the next alternative is tried. If all alternatives are exhausted, backtrack is executed, which restores DF, U, and circuit states, and pops the Decision Stack. If an alternative succeeds, another entry from U is selected for justification. A test is found when U is empty. 64 '$ #$ #$ & # ) + " & # & ,- '$ ' * '$ #$ * & ) # * * * * ' ) Figure 4-6 Implementation details of line justification ATPG sub-task. 4.9 Logic implication Bidirectional implication is implemented for our ATPG. Our implication procedure for Byzantine bridges is different from the implication procedure for 65 single stuck at fault (Appendix 4.A of [17]). Figure 4-7 shows the procedure for our Forward Implication. Figure 4-7 Forward implication procedure. Discussion for this section will focus on logic implication for Byzantine resistive bridges. Implication value assignments at local sub-circuit inputs or outputs return CONFLICT if the implication value mismatches with the value specified by the FRR D-cube. Backward implication ATPG sub-task at the outputs of the local sub-circuit do not spawn new backward implication sub-task. Similarly, forward implication sub-task at the inputs of the local sub-circuit do not spawn new forward implications. Forward Implication(c){ V=Vc j ; // original value V*=Gate(c); // implication value if ((V V*)=={}) return CONFLICT; if (V*⊇ V) { changed(c j )=0; } else { // changed if (c j ∋ LSC) return CONFLICT; changed(c j )=1; Vc j =V V* ; update D, U, Unjustified(c j ), Implication Stack; schedule Forward Implication; if (Unjustified(c j )) schedule Backward Implication return SUCCESS; } } 66 Identified static indirect implications for a line are examined when the value of the line is changed. New forward and/or backward implications at a line are scheduled if global indirect implications or fixed-value-logic implications are identified at the line. 4.10 Computing ATPG coverage Following describes the method we use to compute ATPG coverage. The ATPG selects an FRR D-cube of an FRR (bridging fault resistance range described in Section 2.4) of a bridging fault. The ATPG result for the FRR D-cube is identified as aborted, untestable, or detected. Here are the conditions for the FRR D-cube ATPG results. o Aborted FRR D-cube: the number of backtrack exceeds a preset limit. o Untestable FRR D-cube: entire search space is exhausted and no vector is found. o Detected FRR D-cube: ATPG is successful in generating a vector. The ATPG results for the FRR D-cubes are considered to obtain the ATPG result for the corresponding FRR. Each FRR is identified as undetected, aborted, or detected using the following conditions. o Aborted FRR: Some FRR D-cubes of the FRR are aborted and no FRR D-cube of the FRR is detected. o Untestable FRR: Every FRR D-cube of the FRR is untestable. o Detected FRR: Any FRR D-cube of the FRR is detected. 67 We compute the bridging fault ATPG coverage by dividing the number of detected bridging fault resistance ranges by the total number of bridging fault resistance ranges. 4.11 ATPG system We now present the first complete ATPG system for Byzantine resistive bridging fault shown in Figure 4-8. Figure 4-8 Byzantine resistive bridging fault ATPG system. The ATPG system has six phases. From our study in [6], vectors generated by a wired-AND ATPG [18] are able to detect over 50% of the targeted FRRs. Since a wired-AND ATPG requires much lower computation effort than our more accurate 68 Byzantine ATPG, Phase 1 of the proposed ATPG system generates an initial vector set using the wired-AND ATPG reported in [18]. Phase 2 of the ATPG system runs the proposed Byzantine fault simulation (Chapter 3). This re-simulates the vectors generated in Phase 1 (using the wired-AND fault model) for our Byzantine resistive bridging fault model and computes intermediate coverage for Byzantine bridging faults. Subsequently we use our Byzantine ATPG at two levels of computation effort, which is controlled by adjusting the backtrack limit, and turning on-or-off the propagation and singular cube-covering functions. The low-effort ATPG (Phase 3) would cover most of the FRRs and leave the hard to detect FRRs for the high-effort ATPG (Phase 5). Fault simulator (Phase 4 and Phase 6) is used after each Byzantine ATPG to further reduce the number of aborted faults. 4.12 Results We used our proposed ATPG system described above to simulate benchmark circuits. For each circuit, for a given bridging fault list we use the ATPG system for Byzantine bridging faults to generate test vector sets. Our ATPG does not consider bridging faults with feedback. Our simulator can simulate all possible non-feedback bridging faults for the smaller benchmark circuits and of the order of 10 5 bridging faults for the larger benchmark circuits. Even with the increased number of FRRs when Byzantine fault is considered, our approach can process more than 10 times the number of bridging faults considered in the study in [10]. This unmatched performance is achieved because of the following. 69 o Our PPSFP fault simulator is very efficient in processing large fault sets. o We developed the equivalent and dominance relations (Section 2.7) for the FRRs to reduce explicit invocation of ATPG and fault simulator. o We explore unique properties of 16-valued FRR cube cover (Section 4.3) and hence are able to reduce the number of decision branches by assigning more specific values to circuit lines. o We are the first to adapt many stuck-at fault ATPG techniques to our Byzantine bridging fault ATPG, especially static indirect implication, unique D-drive, and x-path check. o We introduce the simple but efficient cube enumeration scheme (Section 4.8.1) to reduce number of enumerations for line justification. Our experimental results are shown in Table 4-6. Our ATPG is successful in detecting an FRR or proving that it is undetectable for over 99% of faults for every circuit. Consequently, percentages of aborted faults can be controlled to well below 1%, when the proposed ATPG system is used. In particular, our ATPG system is able to effectively deal with circuits that have high percentage of untestable faults, e.g., C1355 which has 29% untestable faults. Note that even a 1 to 2% error in fault coverage estimation is really significant, since it can lead to a significant error in estimation of defect level, i.e., the number of defective chips shipped to customers. 70 C7552 82069 269144 30:53:00 174 05:02:52 7994 8168 6355 262168 621 97.4% 0.23% 2.4% C6288 199048 654487 04:52:51 46 05:34:28 1679 1725 122978 531496 13 81.2% 0.00% 18.8% C5315 155466 472090 23:25:17 281 01:18:33 7137 7418 4762 467317 11 99.0% 0.00% 1.0% C3540 114378 380360 00:31:11 540 03:34:48 2537 3077 19721 360500 139 94.8% 0.04% 5.2% C2670 168890 488090 40:28:50 547 22:10:11 4537 5084 11531 474682 1877 97.3% 0.38% 2.4% C1908 61606 209041 00:57:14 317 26:17:38 2047 2364 9394 199233 414 95.3% 0.20% 4.5% C1355 90165 274474 02:27:04 399 01:00:53 1108 1507 79721 194513 240 70.9% 0.09% 29.0% C880 81899 321117 0:14:06 207 00:15:30 4860 5067 3752 317361 4 98.8% 0.00% 1.2% C499 16681 39257 0:09:52 149 00:02:09 301 450 878 38379 0 97.8% 0.00% 2.2% C432 9132 35851 0:16:25 157 00:02:47 1429 1586 1210 34640 1 96.6% 0.00% 3.4% Num BF Num FRR CPU Time Num Vec CPU Time Num Vec Total Num Vec Untestable Detected Aborted Detected% Aborted% Untestable% Wired-AND ATPG (Phase1) Byzantine Bridging ATPG (Phase2~Phase6) Table 4-6 Byzantine bridging fault ATPG results. 71 Our results clearly show that it is critical to consider indeterminate logic values caused by bridging fault to avoid the risk of seriously compromising test quality. The simulation results shown in Table 4-6 are obtained without considering 1) the values of local sub-circuit internal line, and 2) the difference between the FRR indeterminate lines and the FRR propagation lines both types of lines are processed as FRR propagation lines (Section 4.3.3). Implementation of these two new ideas will further improve the results. 4.13 Summary In this study, we analyzed the unique and novel properties of Byzantine resistive bridging faults from the perspective of high-valued composite value system for ATPG systems. The properties we have identified enable us to cover the Byzantine fault indeterminate behavior accurately and without loss of ATPG efficiency. We developed the first ATPG algorithm for the Byzantine resistive bridging fault model. This new ATPG system embodies the above ATPG algorithm and our proposed Byzantine resistive bridging fault simulator. Results for benchmark circuits show that (1) existing approaches seriously overestimate coverage of Byzantine bridge, and (2) it is very practical to generate test sets that provide higher coverage for the Byzantine bridges. 72 Chapter 5 I DDQ testing for bridging faults In this chapter, we introduce the new concept of defect severity metric, and analyze the characteristic of I DDQ tests (Section 5.1). We then use the defect severity metric to compute yield loss and test escape for I DDQ testing. In the second section of this chapter, we propose three I DDQ test strategies to minimize test escape and yield loss. The first strategy (Section 5.2.1) uses a different I DDQ pass/fail threshold value for each I DDQ test vector to reduce test escape and yield loss. Our approaches take advantage of the following observations. First, increasing a low I DDQ threshold value that was originally selected for detection of one fault can avoid discarding of a device with another fault that is not severe enough to be considered defective. Second, a fault not detected by one vector can be detected by another. The second strategy (Section 5.2.2) collectively examines I DDQ test measurements for all vectors. During classical I DDQ testing, I DDQ vectors are applied to a device under test (DUT) and the quiescent current is measured for each vector. Once the measured I DDQ value for a vector exceeds the corresponding threshold, any information that might have been obtained from the application of the remaining vectors is ignored. Any information obtained from the previous vectors is also ignored. In contrast, in our second strategy, each bridging fault has an I DDQ profile, i.e., a sequence containing one specific I DDQ threshold for each vector. For a bridging fault that has sufficient severity, the I DDQ measurement of every vector will be above 73 the corresponding I DDQ threshold. For a bridging fault with low severity, the I DDQ measurement for at least one vector will be below its I DDQ threshold. Our third strategy (Section 5.2.3) examines not only multiple I DDQ test measurements collectively as our second strategy, but also the non-destructive leakage current of each test vector. 5.1 I DDQ bridging fault modeling 5.1.1 Defect severity metric The notion of bridging fault severity and critical severity are defined as follows. Let F={F 1 , F 2 ,,F N } be the bridging fault list. For a resistive bridge F k ∈ F, the fault severity S k is defined as 1/R k , where R k is the resistance of the bridge between the two nodes. Critical severity, S k , of fault F k is the minimum value of the severity, S k (i.e., the maximum value of R k ), of the fault for which the DUT fails at least one test vector/sequence by causing logic errors at one or more of the outputs of the DUT. The value of critical severity, S k , is unique for the corresponding fault F k , and is independent of which test vector/sequence is applied to the DUT. 74 5.1.2 Characteristics of I DDQ test I DDQ YLR i,k TER i,k I DDQ Test Vector V i ID i,k IN i I DDQi ,k IC i ,k (3) IT i < IC i ,k (1) IT i > IC i ,k (2) IT i = IC i ,k IT i Figure 5-1 Parameters associated with fault F k and test vector V i . Consider a fault-free DUT when a vector V i (or a sequence of vectors that has V i as its last vector) is applied. The non-defective I DDQ current caused due to the application of the vector V i , IN i , has two components, sub-threshold leakage and junction current, and is dependent on V i [12] [26] [11]. These values are depicted in Figure 5-1. Let us consider the same DUT with a single fault F k with severity level S k . Let the defective I DDQ current, ID i,k , be the additional current caused when vector V i is applied to the DUT that contains fault F k . The I DDQ vector V i is said to be a test vector for fault F k , if ID i,k > 0, i.e., if the application of vector V i to a DUT with fault F k causes an I DDQ current that is greater than IN i , the I DDQ current for the fault free DUT. Note that the magnitude of the defective I DDQ current depends not only on the fault F k but also on the test vector V i . Table 5-1 summarizes the notation used. The total I DDQ current that flows when V i is applied to DUT with a fault F k with severity S k is the sum of the corresponding defective and non-defective currents, 75 that is, I DDQi,k = ID i,k + IN i,k . Note that, in general, I DDQi,k increases as the severity S k of the fault F k increases. Recall that S k is defined as the minimum value of S k for which there exists a vector that can cause a logic error at one or more outputs of a DUT with fault F k . Let the I DDQ current when V i is applied to a DUT with F k with severity S k = S k be called the critical I DDQ , IC i,k for the given vector and fault. Note that the value of critical I DDQ for a fault varies with the test vector V i . Table 5-1 Notations. F k Bridging fault F k ∈ F, where F={F 1 , F 2 , , F N } is the fault list. S k Severity level of F k S k ’ Critical severity of F k S k * Threshold severity of F k V i A test vector/sequence that tests F k IN i Non-defective I DDQ current when V i is applied ID i,k Defective I DDQ current for a DUT with F k with severity S k , when V i is applied I DDQi,k Total I DDQ current for a DUT with F k with severity S k , when V i is applied IT i The value of I DDQ threshold current selected for vector V i IC i,k Critical I DDQ current for a DUT with F k with severity S k = S k , when V i is applied S i,k * Threshold severity of F k when V i is applied, i.e., severity of F k for which I DDQi,k =IT i . YLR i,k Yield loss range for DUTs with fault F k with severity levels in the range [S k *, S k ] when V i is applied TER i,k Test escape range for DUTs with fault F k with severity levels in the range [S k *, S k ] when V i is applied H k Histogram describing the probability of manufacturing a DUT with F k with severity S k Let IT i be the value of I DDQ threshold selected for vector V i . Obviously, IT i > IN i , since otherwise all DUTs will be declared faulty. During I DDQ testing, when a vector V i is applied, the I DDQ value for the DUT is measured and compared with IT i . If the I DDQ value for the DUT is higher than IT i , then the DUT is deemed to have failed the test and is discarded. Otherwise, the next vector in the I DDQ test set is applied to the DUT. A DUT that passes all tests in the I DDQ test set is declared fault- free. 76 Note that a single vector V i may detect many faults. However, only a single value of I DDQ threshold, IT i , can be selected for a particular vector. Due to this reason, the selected value of I DDQ threshold, IT i , may be greater than, equal to, or less than IC i,k . These three possibilities are depicted in Figure 5-1. (Note that this figure depicts the case where the severity level, S k , of fault F k is greater than its critical severity, S k . Therefore, I DDQi,k is shown as being greater than IC i,k .) Let S i,k * be the threshold severity level of F k when V i is applied, i.e., the severity at which I DDQi,k =IT i . Now consider the three cases described above. If IT i > IC i,k , then S i,k * > S k . This implies that a DUT that has the fault F k with a severity in the range [S k , S i,k *] will pass the test V i , despite the fact that such a DUT violates circuit specifications. Hence, DUTs with F k with severity levels in the range [S k , S i,k *] constitute test escapes for V i . If IT i = IC i,k , then S i,k * = S k . This is ideal for F k , since I DDQ testing will declare DUTs with fault F k that do not violate specifications as fault-free and those that do as faulty. If IT i < IC i,k , then S i,k * < S k . In this case a DUT with fault F k with a severity in the range [S i,k *, S k ] will be declared faulty and discarded, despite the fact that such a DUT does not violate the specifications. In this case DUTs with F k with severity levels in the range [S i,k *, S k ] constitute yield loss. 77 5.1.3 Yield loss and test escape metrics Consider a complete set of tests comprised of multiple test vectors/sequences V i , each with its own I DDQ threshold IT i . Let S k *, the threshold severity for F k , be the minimum threshold severity for all vectors: S k * = Min {S i,k *} ∀ ∀ ∀ ∀ V i that detect F k . Next, we will use S k * to define the overall yield loss and test escape for DUTs with fault F k . Recall that a DUT is declared faulty if it is declared faulty by even one test. Hence, if S k * < S k , DUTs with fault F k with severity levels in the range [S k *, S k ] will represent YLR k , the overall yield loss range among DUTs with F k . Note that if, S k * ≥ S k , it means that all V i that detect F k have IT i ≥ IC i,k . In this case, YLR k is an empty interval. On the other hand, a DUT is declared fault-free if it passes each test. Hence, if S k * > S k , DUTs with fault F k with severity levels in range [S k , S k *] will represent TER k , the overall test escape range among DUTs with F k . Otherwise, TER k is an empty interval. Now, the overall yield loss, YL (Equation 1), as well as the overall test escape, TE (Equation 2), for the entire population of DUTs, which includes fault-free DUTs as well DUTs with various possible faults with all possible fault severity levels, can be computed as follows. Let H k be the distribution shown in Figure 5-2, describing the probability that a randomly selected DUT from the entire population of DUTs has a fault F k with severity S k . Such information may be derived from the information obtained by diagnosis of faulty DUTs that is available after device 78 fabrication [32], or by analyzing process data bank that is available before device fabrication [11]. Equation 1: < ∀ = ' * ' * | k k dS H YL k k k k S S k S S . Equation 2: ≥ ∀ = ' * * ' | k k dS H TE k k k k S S k S S . TER k YLR k H k I DDQ Histogram for F k S k ’ S k S k * (>S k ’) S k * (<S k ’) Severity Figure 5-2 Histogram H k denoting the distribution of severities for fault F k . An ideal test set with zero test escape and zero yield loss is one for which S k * = S k for all F k . It is possible that some faults are not covered for severity range [S k , S k *] by the given test set. To enhance the test set, we can either add more vectors or reduce the value of ITi for some vectors. The first approach may increase test cost due to longer test time. The second approach may cause higher yield loss. Many test strategies discriminate faulty devices by setting IT i to IN i + ε, where ε is a small test margin [11] [15][26] [12] [13] [16]. In such a strategy, test- escape is close to zero. However, any such strategy inevitably creates yield loss. We refer to this strategy as single threshold with non-destructive current. The value of yield loss can be computed by substituting in Equation 1 the value of S k * that is obtained by setting IT i = IN i + ε, for all vectors V i that detect F k . 79 The concept of critical severity of a fault, S k , provides a link between the fault severity and violation of one or more specifications. Next, we use this concept to develop new frameworks to minimize TE and YL during I DDQ testing. The proposed frameworks provide various strategies to select the values of I DDQ thresholds and provide a mechanism to compute test escape and/or yield loss. 5.1.4 Case study circuit The proposed framework has been applied to the SRAM shown in Figure 5-3. Figure 5-4 shows an SRAM cell used in the SRAM. Faults F 1 to F 21 (Table 5-2), with the exception of F 6 , which is a bridge between power and ground, are used as examples to demonstrate the framework. SRAM Cell Pre-Charge SRAM Cell SRAM Cell Pre-Charge SRAM Cell … … . . . . . . Column Decode Read/Write R o w D e c … Figure 5-3 SRAM used as case study. BitB Line Bit Line Q QB Word Line Figure 5-4 An SRAM cell. 80 Table 5-2 Possible intra-cell resistive bridges. Q F 1 QB F 2 F 7 Bit F 3 F 8 F 12 BitB F 4 F 9 F 13 F 16 Word F 5 F 10 F 14 F 17 F 19 GND F 6 F 11 F 15 F 18 F 20 F 21 VDD Q QB Bit BitB Word 5.2 I DDQ test strategies This section introduces three I DDQ test strategies that we propose to reduce test escape and yield loss. Each test strategy includes multiple schemes, each optimizing a different combination of test escapes and yield loss. The three strategies are: o I DDQ threshold selection strategies (Section 5.2.1), o I DDQ profile discrimination strategies (Section 5.2.2), and o I DDQ fault excitation profile discrimination strategies (Section 5.2.3). 5.2.1 I DDQ threshold selection strategies As discuss earlier in this chapter, we propose to reduce test escape and yield loss by setting a different I DDQ threshold for each I DDQ test vector. We illustrate the strategy using the SRAM and the bridging fault list described in Section 5.1.4. We use the following steps for test generation. o Compute critical severity of each fault (Section 5.2.1.1). o Generate a test set (Section 5.2.1.2). o Set I DDQ threshold for each vector (Section 5.2.1.3 and section 5.2.1.4). 81 5.2.1.1 Computation of the critical severity of each fault Recall that critical severity S k of a fault F k is the minimum value of the severity of the fault for which there exists a test that can cause violation of one or more of the specifications. Note that the above definition necessitates the consideration of all possible combinations of state values and test vectors. In the following, we have computed approximate values of S k by performing SPICE simulations for the entire SRAM for a comprehensive memory test, namely March B, for various values of S k . The approximate value of critical severity, S k , is that value of S k , for which a logic error is observed at one of the memory outputs for one or more vectors in the test set. Binary search is employed to rapidly find the values of S k . The column entitled S k in Table 5-3 shows the values of critical severity (reciprocal of critical resistances in unit of 10 -3 Ω -1 ) for the targeted SRAM cell (Figure 5-4) computed in this manner. As part of our proposed research, we will develop an approach to compute accurate values of S k . 82 0.04 0.04 0.02 0.03 0.17 0.08 0.09 0.04 0.09 0.08 0.10 0.10 0.10 0.08 0.08 0.08 0.07 0.04 0.04 0.13 w1 iaw0 V21 *** 185 *** *** 492 242 *** *** 298 *** *** *** 298 *** *** *** *** *** *** *** 492 x w0 ipW0 V20 185 *** *** *** 491 242 *** *** 298 *** *** *** 298 305 *** *** *** *** *** *** 491 x W1 ipW0 V19 *** 186 *** *** 492 242 *** *** 298 358 *** *** 298 *** *** *** *** *** *** *** 492 x W1 ipw1 V18 *** 185 *** *** 492 242 *** *** 298 357 *** *** 298 *** *** *** *** *** *** *** 492 x W0 ipw1 V17 185 *** *** *** 491 241 *** *** 298 *** *** *** 298 305 *** *** *** *** *** *** 491 x w1 iar1 V16 *** 186 *** *** *** 349 *** 276 *** *** 257 *** *** *** 140 *** 111 *** *** 502 502 x w0 iaw0 V15 *** 186 *** *** *** 242 *** 257 *** *** 170 *** *** *** 139 *** 111 *** *** 502 502 x W1 iaR1 V14 *** 186 *** *** *** 349 *** 276 *** *** 171 *** *** *** 140 *** 111 *** *** 502 502 x W1 iaw0 V13 *** 186 *** 120 *** 242 *** 257 *** *** 170 *** *** *** 139 *** 111 *** *** 502 502 x W1 iaR1 V12 *** 186 *** 120 *** 346 *** 276 *** *** 257 *** *** *** 140 *** 111 *** *** 501 501 x W0 iaw0 V11 186 *** 115 *** *** 242 *** 163 *** *** 252 *** *** 305 139 *** *** *** 211 501 501 x W0 iaR0 V10 186 *** 115 *** *** 348 *** 163 *** *** 286 *** *** 305 139 *** *** *** 431 501 501 x W0 w1iar1 V9 186 *** 116 *** *** 349 *** 255 *** *** 287 *** *** 306 140 *** *** *** 272 501 501 x W0 iaR0 V8 186 *** 115 *** *** 346 *** 254 *** *** 286 *** *** 305 248 *** *** *** 271 501 501 x V7 *** 186 *** *** 695 243 *** *** 300 *** 284 284 301 *** *** 253 180 167 291 *** 695 x W1 iaW1 V6 *** 189 *** 125 *** 302 *** 301 *** 370 266 *** 518 *** 224 *** 159 563 *** 502 563 125 W0 iaW0 V5 189 *** 119 *** *** 302 *** 252 518 *** 318 *** *** 307 223 558 *** *** 318 501 558 x V4 *** 188 *** 569 *** 302 *** 301 *** 370 266 *** 518 *** 223 *** 159 563 *** 501 569 x V3 189 *** 119 *** *** 302 *** 252 329 *** 318 *** *** 307 224 284 *** *** 318 501 501 119 W1 ipR1 V2 *** 186 *** *** 695 243 *** *** 301 359 284 284 301 *** *** 253 180 167 291 *** 695 284 W0 ipR0 V1 186 *** *** *** 695 243 175 282 300 *** *** *** 301 306 *** 253 179 167 291 *** 695 175 F1 F2 F3 F4 F5 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 ZYLT ZTET S k w0ipr0 iaW1 iaW0 Table 5-3 Critical severities and currents. 83 5.2.1.2 Test sequence generation The second step is to generate the test sequences. Before we describe the test sequences, we present some basic definitions pertaining to memory timing and some symbols. SRAM accesses are divided into two phases: pre-charge phase during which chip enable control is low, and access phase during which chip enable control is high. These two phases are respectively denoted by p and a. Target cell is the cell under test. W0/1 (R0/1) denotes writing to (reading from) the target cell with value 0/1. w0/1 (r0/1) denotes writing to (reading from) any other cell in the same column as the target cell. A prefix ip or ia is added to the read or write operation to denote that I DDQ measurement is being performed during the pre-charge phase or the access phase of the cycle. Each I DDQ vector may require multiple cycles to set up the initial values required by the vector. For example, to detect F 1 (bridge between Q and VDD), test sequence iaW0 that measures the I DDQ during the access phase of a write 0 operation will detect the fault. This is an example of a test that requires only one memory cycle to detect a fault. Many other faults required multiple operations. For example, consider F 5 (a bridge between the word line and VDD), which can be detected by W0 followed by ipwr1. The first access initializes the cell content to some known value (0 in this case). The second access turns on the word line of a different cell in the same column. Since the bridge fault F 5 turns on the word line of the target cell, the word line is on at all times, even during the pre-charge-phase. Therefore, we can detect the fault by measuring I DDQ during the pre-charge-phase. 84 A manually generated set of tests that detects all faults under consideration is depicted as V 1 to V 21 and is shown in the second row of Table 5-3. This table also shows the critical current IC i,k of the entire SRAM, for every test vector for every fault. If a vector V i does not excite fault F k , then IC i,k is denoted as *** which is equal to IN i . Next, we describe the scheme threshold selection for two different objectives. 5.2.1.3 ZYLT: Zero yield loss I DDQ threshold selection strategy As discussed in Section 5.1.2, setting I DDQ threshold current lower than the critical current of a fault F k will cause inevitable yield loss. Therefore, the first strategy, ZYLT, discriminates faulty devices by setting IT i value for V i to the maximum IC i,k value for all F k to guarantee zero yield loss. That is IT i = Max ∀k {IC i,k }. IT i values corresponding to ZYLT are shown near the bottom of Table 5-3 in row entitled ZYLT. Under this strategy, we can lower test escape by applying additional vectors. Of course, this is accomplished at the cost of higher test time. The extra vectors will maintain the zero yield loss, as long as we set IT i = Max ∀k {IC i,k } for each vector V i . 5.2.1.4 ZTET: Zero test escape I DDQ threshold selection strategy The objective of this strategy is set the I DDQ threshold for a given set of vectors to achieve zero test escape with minimum yield loss. If a fault is excited by multiple vectors, then to achieve zero test escape for devices with that fault, for one of these vectors, V i , the I DDQ threshold IT i should be less than or equal to IC i,k . 85 For example, consider a case where we choose only vectors V 1 , V 2 , V 3 , and V 6 from Table 5-3. These four vectors excite all the 20 faults of interest (F 1 to F 21 except F 6 , which is the bridging fault between power supply and ground). For selection of threshold value for each vector, let us examine the conditions for faults excited by one vector, two vectors, and so on. First, for the fault excited by only one of the vectors in the given vector list {V 1 , V 2 , V 3 , V 6 } we have the following conditions. {F 3 : IT 3 ≤ 119 } and {F 4 : IT 6 ≤ 125} and {F 8 : IT 1 ≤ 175} and {F 13 : IT 2 ≤ 284}. Of the above conditions, note that 119 is the lowest of the critical currents for V 3 for all faults excited by the vector. Similarly, 125 is the lowest of the critical currents for V 6 for all faults excited by the vector. Hence, the best way to satisfy the above requirements for F 3 and F 4 is to select: IT 3 =119 and IT 6 =125. Once the above thresholds are selected, all faults other than F 5 , F 8 , and F 13 are detected with zero test escape. For these three faults, we have the following requirements: {F 5 : IT 1 ≤ 695 or IT 2 ≤ 695} and {F 8 : IT 1 ≤ 175} and {F 13 : IT 2 ≤ 284}. Note that, all the above requirements are satisfied by selecting: IT 1 =175 and IT 2 =284. Hence, for our ZTET strategy, if we use vectors {V 1 , V 2 , V 3 , V 6 }, then the corresponding threshold values are {175,284,119,125}. These threshold values will 86 minimize yield loss while guarantee detection of all 20 faults of interest with zero test escape. 5.2.1.5 Summary Two new strategies are introduced -- ZYLT and ZTET. The first strategy provides I DDQ threshold value settings that create no yield loss and provide test escape lower than the traditional single I DDQ threshold value strategy. The second strategy creates no test escape by using an appropriate threshold for each vector. Using appropriate threshold values, one can reduce yield loss. Approaches to systematically generate vectors and select I DDQ threshold values are proposed in Section 5.2.1.2, Section 5.2.1.3, and Section 5.2.1.4. The new concepts of threshold severity S k , critical severity S k *, and critical current IC i,k make many other new strategies possible for controlling test escape and yield loss. 5.2.2 I DDQ profile discrimination strategies In the I DDQ threshold selection strategies outlined above, once the measured I DDQ value for a vector exceeds the corresponding threshold, any information that might have been obtained by the application of the remaining vectors is ignored. Any information obtained from previous vectors is also ignored. Now we propose to collect I DDQ measurements from all I DDQ vectors and use them to develop a new I DDQ discrimination strategy. Note that in this case all tests are applied before any comparison between measured I DDQ values and profiles is made. 87 5.2.2.1 I DDQ fault characteristic profile The new concept of I DDQ fault characteristic profile, considers the I DDQ current for each vector. Definition 5-1: I DDQ fault characteristic profile P k for a fault F k is the sequence of IC i,k values for all I DDQ vectors, V i . P k = {IC i,k } ∀ ∀ ∀ ∀ V i . For example as shown in Table 5-4(b), the I DDQ profile P 16 , corresponding to F 16 , equals to {224, 224, ***, ***}. The profiles under consideration, P 1 , P 5 , P 16 , P 18 , P 19 , P 20 , correspond to the faults of interest, F 1 , F 5 , F 16 , F 18 , F 19 , F 20 , respectively. For a fault-free device, the I DDQ measurement equals to the sum of sub-threshold and reverse diode leakage currents for all transistors and parasitic diodes, respectively, in a device. Some of the vectors may not excite a fault. For example in Table 5-4(b), IC i,k for V 4 of P 16 equals to the leakage I DDQ which we represent as ***. 5.2.2.2 I DDQ profile discrimination strategy The new I DDQ discrimination strategy is based on the comparison of P k and the I DDQ measurements for all vectors for the DUT. This discrimination strategy collectively considers the I DDQ current measurements M i when vector V i is applied to DUT, for all vectors applied. Let M = {M i } ∀ V i , be the set of I DDQ measurements for the DUT. Each component M i is compared with P i,k ∀ V i . M i may be either greater than or less-than-or-equal-to P i,k . Therefore for each F k , the (M i , P i,k ) comparison can fall into three cases. 88 o Case 1) M i ≤ P i,k for all V i : This implies that either F k does not exist in the DUT, or the severity level of F k in DUT is less-than-or-equal to S k . o Case 2) M i > P i,k for all V i : This implies that if F k exists in the DUT, the severity level of F k in DUT is greater than S k . DUTs with such comparison result will be declared faulty and discarded. o Case 3) There exists some M i > P i,k and there also exists some other M l ≤ P l,k : This implies that F k does not exist in that DUT with severity greater than S k . If F k existed in the DUT with severity greater than S k , all M i values would be greater than corresponding P i,k for all V i . Despite the fact that some M i are greater than corresponding P i,k values, DUTs with such a comparison result pass the test for fault F k (via comparison with P k ). For example, if the severity level of F 9 is above S 9 , the fault will introduce functional error(s), and the I DDQ measurements for each vector, V i , will be above the corresponding value IC i,9 in P 9 , and the DUT will be declared faulty. If the severity level of F 9 is below S 9 (with the assumption of a single-bridge-fault), I DDQ measurement for every vector will be below P 9 . In this research, we propose two profile selection strategies, the zero yield loss I DDQ profile (ZYLP) strategy and the zero test escape I DDQ profile (ZTEP) strategy. 89 5.2.2.3 ZYLP: Zero yield loss I DDQ profile selection strategy In the ZYLP strategy, we select a subset of the profiles for the faults of interest. We make the selection in such a way that we are guaranteed zero yield loss, but may have non-zero test escape. Zero yield loss guarantee is secured by ensuring that any of the selected profile is not completely below another profile in the original profile set. Definition 5-2: ZYLP -- Let Π Π Π Π be the set of profiles P k of all fault of interest (F k ). ZYLP is the set of profiles obtained by removing from Π Π Π Π any profile P x for which there exists another profile P l ∈ ∈ ∈ ∈ Π Π Π Π such that P i,x ≤ ≤ ≤ ≤P i,l , ∀ ∀ ∀ ∀ V i . 5.2.2.3.1 Profile severity for ZYLP strategy Let S k * be the minimum severity level of F k for which there exists a profile P x in the ZYLP profile set, such that the I DDQ measurement for every vector is just completely above P x . If S k * > S k , then DUTs that have fault F k with severity levels in the range [S k , S k *] will pass the test, despite the fact that such DUTs violate circuit specifications. In other words, DUTs with F k with severity levels in the range [S k , S k *] represent, TER k , the test escape range for fault F k . If S k * = S k , then this is the ideal situation for F k , since I DDQ testing will declare DUTs with fault F k that do not violate specifications as fault-free and those that do as faulty. 5.2.2.3.2 ZYLP Example Among the profiles for the six faults of interest show in Table 5-4(b), the profile P 1 , {189, ***, 186, ***}, is completely below P 20 , {318, ***, 291, 291}. 90 Consider the case when both P 1 and P 20 are included in the target profile set. Any DUT with fault F 20 that has severity level below the critical severity of F 20 , S 20 , (i.e., which does not cause any functional error) but causes I DDQ levels greater than 189 and 186 for V 1 and V 3 , respectively, would fail the comparison with P 1 , and introduce yield loss for devices with F 20 . To obtain zero yield loss, P 1 must be excluded from the target profile set in the ZYLP strategy. After P 20 and P 1 are compared, P 20 is compared with another profile, e.g., P 18 , in Table 5-4(b). Since IC i,20 of P 20 for V 1 , V 3 , and V 4 are above those for P 18 , P 20 is not completely below P 20 . Similar comparison between P 20 and all other remaining profiles shows P 20 is not completely below any of the other profiles. Therefore, P 20 is included in the target profile set. This process continues until all profiles in the table are checked in a similar manner. The target profile set for the ZYLP strategy is {P 5 , P 16 , P 18 , P 19 , P 20 }. P1 P20 Profile IDDQ Yield loss for F 20 if P 1 is included in the profile set I DDQ for DUT with F 1 (S 1>S 1’) F 1 may escape if P 1 is removed from the profile set I DDQ for DUT with F 20 (S 20<S 20’) Figure 5-5 I DDQ profile P 1 is completely below P 20 . A DUT with fault F 1 , that has severity higher than S 1 (which will cause functional errors) and has I DDQ measurements lower than the I DDQ values of profile P 20 (Figure 5-5), would not be screened by the target profile set, which does not 91 include P 1 . A DUT with fault F 1 of such severity would hence escape this ZYLP. Hence, non-zero test escape may occur for ZYLP strategy. 5.2.2.4 ZTEP: Zero test escape I DDQ profile selection strategy The second profile selection strategy ZTEP guarantees zero test escape but may cause non-zero yield loss. ZTEP profile set is obtained from the set of all profiles, Π, by keeping any profile P x that is not completely above any other profile in Π. We could have kept all profiles in Π for ZTEP profile set which would also guarantee zero test escape. However, using all profiles in Π would increase the complexity of comparisons of the I DDQ measurement values (M i ) with profiles but provide no advantage in terms of test escape and yield loss. Definition 5-3: ZTEP – ZTEP is the set of profile obtained by removing from Π Π Π Π any profile P x for which there exists another profile P l ∈ ∈ ∈ ∈ Π Π Π Π such that P i,x ≥ ≥ ≥ ≥ P i,l , ∀ ∀ ∀ ∀ V i . 5.2.2.4.1 Profile severity for ZTEP strategy Let S k * be the minimum severity of F k at which there exists another profile P x in Π such that the I DDQ measurements are just completely above P x for all V i . If S k * < S k , then DUTs that have the fault F k with severity levels in the range [S k *, S k ] will fail the test, despite the fact that such DUTs do not violate any circuit specifications. In other words, DUTs with F k with severity levels in the range [S k *, S k ] represent YLR k , the yield loss range for fault F k . 92 Table 5-4 Examples for fault characteristic profiles and I DDQ threshold values. (a) Threshold current for ZYLT and ZTET strategies. IC i,k (μA) Profile V 1 V 2 V 3 V 4 ZYLT 318 563 695 695 ZTET 189 159 167 167 (b) I DDQ profiles and profile sets. Fault Profile IC i,k for vectors(μA) Profile Set F k P k V 1 V 2 V 3 V 4 ZTEP ZYLP F 18 P 18 *** 159 179 180 P 18 P 18 F 1 P 1 189 *** 186 *** P 1 -- F 16 P 16 224 224 *** *** P 16 P 16 F 20 P 20 318 *** 291 291 -- P 20 F 19 P 19 *** 563 167 167 P 19 P 19 F 5 P 5 *** *** 695 695 P 5 P 5 (c) DUT I DDQ measurements. M i for vectors (μA) V 1 V 2 V 3 V 4 Severity Level DUTa 413 413 *** *** S 16 =0.250 DUTb 274 274 *** *** S 16 =0.100 DUTc 214 214 *** *** S 16 =0.071 DUTd 102 102 *** *** S 16 =0.024 5.2.2.4.2 ZTEP Example In Table 5-4(b), P 20 is completely above P 1 . Hence, we exclude P 20 from the target profile set. Next P 1 is compared with the next profile, e.g., P 18 in Table 5-4(b). Since IC i,k of V 2 and V 4 of P 1 is below that of P 18 , P 1 is not completely above P 18 . Similar comparison amongst P 1 and all other profiles shows P 1 is not completely above any of the other profiles. Therefore, P 1 is included in the target profile set. This process continues until all profiles in the table are checked. The final profile set for the ZTEP strategy is {P 1 , P 5 , P 16 , P 18 , P 19 }. 93 DUTs with fault F 20 , with severity lower than S 20 (which will not cause any functional error) but with I DDQ measurements higher than the entries for P 1 (Table 5-4(b)), would be declared defective when this profile set is used. Such DUTs with fault F 20 would constitute yield loss. Hence, non-zero yield loss may occur for ZTEP strategy. 5.2.2.5 Comparison of I DDQ threshold and profiling strategies ZYLP and ZTEP I DDQ profiling strategies produce approaches for I DDQ testing that have lower test escape and lower yield loss than the ZYLT and ZTET strategies, respectively. These improvements are illustrated by applying the strategies to four example-devices. Four devices, DUTa, DUTb, DUTc, and DUTd are known to carry bridging fault F 16 with decreasing levels of severity as shown in Table 5-4(c). The bridging faults in DUTa and DUTb are so severe that they each cause logic errors at the primary output. Therefore, DUTa and DUTb are Known Bad Devices (KBD). The bridging faults in DUTc and DUTd are not severe enough to cause logic errors. Therefore, DUTc and DUTd are Known Good Devices (KGD). These results were verified with SPICE simulations. The DUT tests results are summarized in Table 5-5. Figure 5-6 shows the test results when ZYLP or ZYLT is used to test the DUTa, DUTb, DUTc, and DUTd and Figure 5-7 shows the test results when ZTEP or ZTET is used to test the DUTs. 94 0 100 200 300 400 500 600 700 800 V1 V2 V3 V4 IDDQ (uA) DUTa DUTb DUTc DUTd P18 P16 P20 P19 P5 ZYLT Figure 5-6 I DDQ comparisons for ZYLP and ZYLT. 0 100 200 300 400 500 600 700 800 V1 V2 V3 V4 IDDQ (uA) DUTa DUTb DUTc DUTd P18 P1 P16 P19 P5 ZTET Figure 5-7 I DDQ comparisons for ZTEP and ZTET. 95 Table 5-5 Summary of test results for four example DUTs. Test Results DUTa KBD DUTb KBD DUTc KGD DUTd KGD Descriptions ZYLT Fail → fault detected Pass → → → → fault escaped Pass → no yield loss Pass → no yield loss Zero yield loss with non-zero test escape (DUTb) ZYLP Fail → fault detected Fail → → → → fault detected Pass → no yield loss Pass → no yield loss Zero yield loss with lower test escape than ZYLT ZTET Fail → fault detected Fail → fault detected Fail → → → → yield loss Pass → no yield loss Zero test escape with non-zero yield loss (DUTc) ZTEP Fail → fault detected Fail → fault detected Pass → → → → no yield loss Pass → no yield loss Zero test escape with lower yield loss than ZTET 5.2.2.5.1 ZYLP and ZYLT test KBD DUTa and DUTc, and KGD DUTd Let ZYLT i be the I DDQ threshold setting values for vector V i as shown in the row entitled ZYLT of Table 5-4(a), and Ma i be the I DDQ measurement results for DUTa when vector V i is applied. When I DDQ threshold set for the ZYLT strategy is used to test DUTa, threshold value ZYLT 1 (318μA in column V 1 of Table 5-4 (a)) is compared with Ma 1 (413μA at column V 1 of Table 5-4 (c)). Since Ma1 is greater than ZYLT 1 , the KBD DUTa fails ZYLT test, the high severity fault F 16 in DUTa is detected, and the remaining vectors V 2 , V 3 , and V 4 are not applied. When ZYLP profile set is used to test DUTa, I DDQ measurements are collected by applying the complete vector set V 1 to V 4 with the measurement results {413, 413, ***, ***} as shown in the row entitled DUTa in Table 5-4(c). Since the measurements Ma 1 to Ma 4 are completely above the corresponding I DDQ values of profile P 16 (Figure 5-6 and row entitled P 16 in Table 5-4(b)). The KBD DUTa is 96 again declared faulty. Both ZYLT and ZYLP test strategies declare the KBD DUTa faulty. When I DDQ threshold set for the ZYLT strategy is used to test KGD DUTc, I DDQ measurements for DUTc from V 1 to V 4 are below the corresponding threshold values for ZYLT. Hence, the KGD DUTc passes the ZYLT test. When ZYLP profile set is used to test DUTc, I DDQ measurements for the vectors are completely below the corresponding I DDQ profile P 16 (Figure 5-6 and row entitled P 16 in Table 5-4(b)). Other remaining profiles (P 5 , P 18 , P 19 , P 20 ) in the ZYLP profile set are also compared with the I DDQ measurements for DUTc. None of the remaining profiles is completely below the DUTc I DDQ measurements. Therefore, the KGD DUTc passes the ZYLP strategy profile set. Hence, KGD DUTc passes both the ZYLT and ZYLP strategies. Similarly, ZYLT and ZYLP test strategies both declare the KGD DUTd fault-free. 5.2.2.5.2 ZYLP and ZYLT test KBD DUTb All I DDQ measurements of KBD DUTb are above P 16 , therefore, DUTb fails ZYLP test. However, the I DDQ measurements for DUTb are below corresponding threshold values for ZYLT. Hence, DUTb escapes the ZYLT test. In summary, in this example, both ZYLP and ZYLT guarantee zero yield loss (i.e., all KGDs pass), however, because of the use of profiling ZYLP provides lower test escape than ZYLT (Table 5-5). 97 5.2.2.5.3 ZTEP and ZTET test KGD DUTa, DUTb and DUTd I DDQ measurements for KBD DUTb are completely above ZTEP P 16 and ZTET thresholds; therefore, KDB DUTb fails both ZTEP and ZTET tests. Since I DDQ measurements for KBD DUTa are completely above those for DUTb, KBD DUTa also fails both ZTEP and ZTET. Hence, ZTEP and ZTET provide zero test escape. DUTd has I DDQ measurements completely below ZTET threshold values, and not completely above any of the profiles {P 1 , P 5 , P 16 , P 18 , P 19 } in ZTEP. Therefore, KGD DUTd passes both ZTET and ZTEP. 5.2.2.5.4 ZTEP and ZTET test KGD DUTc When ZTEP profile set is used to test DUTc, none of the profiles in the set is completely above the I DDQ measurements for the KGD DUTc. The KGD DUTc passes the ZTEP profile set. Again, because the severity of F 16 in DUTc is below the critical severity S 16 , DUTc is a KGD and does not cause any logic error. However, the elevated I DDQ measurement Mc 1 that is caused by F 16 , is over ZTET 1 threshold value (189uA), which is selected to prevent any test escape of F 1 (IC 1,1 = 189uA). Hence, the KGD DUTc fails the ZTET test and causes yield loss. From the above comparison, both ZTEP and ZTET strategies guarantee zero test escape, however, because of the use of profiles, ZTEP has lower yield loss than ZTET (Table 5-5). 98 5.2.2.6 Computation of TE and/or YL The proposed I DDQ profile discrimination framework has been applied to our CMOS SRAM design. Faults F 1 to F 21 , as shown in Table 5-2 (with the exception of F 6 , which is a bridge between power and ground), are used to demonstrate the framework. Column entitled S k in Table 5-3 shows the values of critical severity for the targeted SRAM cell (Figure 5-4) determined in this manner. Columns entitled ZYLP and ZTEP of Table 5-6 show the TER or YLR (as applicable) for each of the above strategies for selecting the value of P k . Again, since we do not currently have the histograms H k , we present the test escape and yield loss in terms of ranges TER k and YLR k , respectively. 99 Table 5-6 ZTEP/ZYLP/ZTET/ZYLT comparison. ICi,k for vector Vi Profile Profile V1 V2 V3 V4 Set [Sk* Sk'] Set [Sk', Sk*] [Sk*, Sk'] [Sk', Sk*] P01 189 *** 186 *** 0.04 -- [0.02, 0.04] -- -- [0.02, 0.04] -- P02 *** 189 *** 186 0.04 -- [0.03, 0.04] -- -- [0.03, 0.04] [0.04, 1.00] P03 119 *** *** *** 0.02 P03 -- -- [0.02, 0.03] -- [0.02, 0.03] P04 *** 125 *** *** 0.03 P04 -- -- -- -- [0.03, 0.03] P05 *** *** 695 695 0.17 -- [0.04, 0.17] P05 -- [0.03, 0.17] [0.17, 0.17] P07 302 302 243 243 0.08 -- [0.03, 0.08] P07 -- [0.03, 0.08] [0.08, Infinit] P08 *** *** 175 *** 0.09 P08 -- -- -- [0.04, 0.09] [0.09, Infinit] P09 252 301 282 *** 0.04 -- [0.03, 0.04] P09 -- [0.03, 0.04] [0.04, Infinit] P10 329 *** 300 301 0.09 -- [0.02, 0.09] P10 -- [0.02, 0.09] [0.09, 0.14] P11 *** 370 *** 359 0.08 -- [0.03, 0.08] P11 -- [0.03, 0.08] [0.08, 0.20] P12 318 266 *** 284 0.10 -- [0.03, 0.10] P12 -- [0.03, 0.10] [0.10, Infinit] P13 *** *** *** 284 0.10 -- -- -- -- [0.04, 0.10] [0.10, Infinit] P14 *** 518 301 301 0.10 -- [0.03, 0.10] P14 -- [0.03, 0.10] [0.10, 0.17] P15 307 *** 306 *** 0.08 -- [0.03, 0.08] P15 -- [0.03, 0.08] [0.08, 0.17] P16 224 224 *** *** 0.08 -- [0.03, 0.08] -- [0.08, 0.13] [0.03, 0.08] [0.08, Infinit] P17 284 *** 253 253 0.08 -- [0.03, 0.08] -- -- [0.03, 0.08] [0.08, 0.17] P18 *** 159 179 180 0.07 -- [0.03, 0.07] -- [0.07, 0.08] [0.03, 0.07] [0.07, 0.50] P19 *** 563 167 167 0.04 -- [0.03, 0.04] P19 -- [0.03, 0.04] [0.04, 0.03] P20 318 *** 291 291 0.04 -- [0.03, 0.04] -- -- [0.03, 0.04] [0.04, 0.50] P21 501 502 *** *** 0.13 -- [0.02, 0.13] P21 -- [0.02, 0.13] [0.13, 0.13] ZYLT 501 563 695 695 Sk=Infinit : ~0 Ohm bridging resistance ZTET 119 125 175 284 -- : empty interval Vector Sk' Strategies W1 ipR1 W0 ipR0 W1 iaW1 ZTET ZYLT YLRk ZTEP iaW0 YLRk TERk ZYLP TERk 5.2.2.7 Summary We defined I DDQ measurement record and the new concept of I DDQ fault characteristic profile. We introduced two new I DDQ discrimination strategies, (1) ZYLP, which reduces test escape while maintaining zero yield loss, and (2) ZTEP, which reduces yield loss while maintaining zero test escape. The reductions in test escape and yield loss are with respect to previous research [11] and [15], and our own I DDQ threshold approaches (Section 5.2.1, and [4]). 100 Next we consider enhancement of the I DDQ profile strategies, which will help further reduce test escape or yield loss, as appropriate. 5.2.3 I DDQ fault excitation profiles discrimination strategies The discrimination strategy for ZYLP and ZTEP is based on the comparison of profile P k with I DDQ measurements for the DUT. For example, consider two devices, DUTa and DUTb, which are known to carry bridging fault F 9 with different levels of severity as shown in Table 5-7(b). Let the I DDQ measurement for the DUT for vector V i be M i . DUTb with fault F 9 that has severity 0.062, which is above the critical severity S 9 (0.043), and hence would cause functional error(s). Therefore, DUTb is a known bad device (KBD), and I DDQ measurements for vectors V 1 to V 3 are above the corresponding values of IC i,9 in P 9 . Hence the DUT would be declared faulty if P 9 is compared with the I DDQ measurements for DUTb. However, since P 9 is completely below P 7 , P 9 is excluded from the ZYLP profile set. Therefore, KBD DUTb with fault F 9 would escape this ZYLP. Hence, non-zero test escape occurs for the ZYLP strategy. The severity level for fault F 9 in DUTa (0.033) is below critical severity S 9 (0.043). Therefore, DUTa is a known good device (KGD), and would not cause any functional error. I DDQ measurements for vectors V 1 to V 3 are below P 9 . Hence, DUTa will not fail the I DDQ test that has P 9 its profile set. Recall that the ZTEP profile set excludes P 9 but includes P 3 in the profile set. P 3 has IC 1,3 below M 1 , I DDQ measurement for V 1 for DUTa, therefore, KGD DUTa with fault F 9 would fail the test. Hence, non-zero yield loss occurs for ZTEP strategy. 101 Table 5-7 I DDQ Profiles for ZYLP and ZTEP. (a) I DDQ profiles and ZTEP and ZYLP profile sets. Faults Profiles IC i,k for vectors (μA) Prof. Set F k P k V 1 V 2 V 3 V 4 S k ZTEP ZYLP F 9 P 9 157 176 175 *** 0.043 -- -- F 3 P 3 119 *** *** *** 0.024 P 3 -- F 7 P 7 274 274 260 260 0.077 -- P 7 (b) DUT I DDQ measurements. M i for vectors (μA) V 1 V 2 V 3 V 4 Fault severity DUTa 123 135 136 *** DUT with F 9 @ S 9 =0.033 DUTb 200 233 226 *** DUT with F 9 @ S 9 =0.062 0 50 100 150 200 250 300 V1 V2 V3 V4 IDDQ (uA) . DUTa DUTb P09 P03 P07 Figure 5-8 ZYLP, ZTEP and DUT I DDQ comparison. 5.2.3.1 Fault excitation pattern Our new strategies consider both multiple I DDQ test measurements collectively as well as the non-destructive leakage current for each test vector. We introduce the new concept of fault excitation pattern (FEP) that is used as a metric for fault discrimination. We now define FEP(M), FEP(P k ), and equality of FEPs. 102 Definition 5-4 FEP of an I DDQ measurement set M: Let IN = Max{IN i } + ε ε ε ε, where ε ε ε ε is a small test margin. The FEP of an I DDQ measurement set M, FEP(M), is a set of vectors V i , such that M i > IN. Therefore, FEP(M) represents the set of vector that excite any fault that exists in the DUT. Definition 5-5 FEP of an I DDQ profile P k : FEP(P k ) is a set of vectors V i , such that IC i,k > IN. Therefore, FEP(P k ) represents the set of vectors that excite fault F k . Definition 5-6 Equality of two FEPs: FEP n = FEP m if the vector set in FEP n is identical to the vector set in FEP m . Noted that typically an FEP(M) is compared with an FEP(P k ). Therefore, if FEP(M)=FEP(P k ), fault F k is a possible fault that causes this I DDQ measurement M. If FEP(M)≠FEP(P k ), fault F k does not exist in the DUT I DDQ measurement M. 5.2.3.2 ZYLEP and ZTEEP discrimination strategies We propose new fault-free/faulty device I DDQ discrimination strategies called for ZYLEP and ZTEEP that each collectively considers the I DDQ current measurements M i for all vectors Vi, as well as the FEPs for the DUT. Let M = {M i } ∀ V i be the set of I DDQ measurements for the DUT. Each component M i is compared with P i,k ∀ V i . 103 P k and M may have the same or different fault excitation patterns and each M i may be either greater than or less-than-or-equal-to P i,k . Therefore for each F k , there are four possible results of (M i , P i,k ) comparison. o Case 1) FEP(M) ≠ FEP(P k ): If F k existed in DUT with sufficient severity, FEP(M) would be equal to FEP(P k ). Hence, this implies that either F k does not exist in DUT, or the severity level of F k in DUT is less-than-or-equal-to S k . o Case 2) M i ≤ P i,k for all V i , and FEP(M) = FEP(P k ): This implies that either F k does not exist in DUT, or the severity level of F k in DUT is less-than-or-equal-to the corresponding critical severity, S k . o Case 3) M i ≥ P i,k for all V i , and FEP(M) = FEP(P k ): This implies that if F k existed in the DUT, the severity level of F k in the DUT is greater than S k . DUTs with such a measurement result will be declared faulty and discarded. o Case 4) There exist some M i > P i,k and there also exist some M l ≤ P l,k , and FEP(M) = FEP(P k ): This implies that F k with severity greater than S k does not exist in DUT. If F k existed in DUT with severity greater than S k , M l would be greater than P i,k for all V i . Despite the fact that some M i values are above its corresponding values in the profile P i,k , DUTs with this measurement result passes the P k test. 104 5.2.3.3 An example to illustrate FEP discrimination strategy Refer to Table 5-7(a). Since V 4 does not excite the fault F 9 , IC 4,9 for P 9 for V 4 is equal to non-destructive leakage current and is represented as ***. When V 4 is applied to DUTa or DUTb, the I DDQ measurements are equal to the leakage current; even though both DUTs contain F 9 with different severities. This leakage current does not change with the severity level of F 9 . P 9 has IC 1,9 to IC 3,9 over IN, and IC 4,9 within IN. P 7 has IC 1,7 to IC 4,7 over IN. Therefore, P 9 has a different FEP than P 7 . When FEP comparison is integrated into ZYLEP discrimination strategy, P 9 and P 7 can both be used to screen DUTs, and P 9 need not be excluded from the ZYLEP target profile set. When P 9 is used to compare with DUTb I DDQ measurement, the measurement M 4 for DUTb as well as IC 4,9 are both equal to IN. Measurements M 1 to M 3 for DUTb, and the corresponding points in P 9 , IC 1,9 to IC 3,9 are above IN. Therefore, the measurement M={M 1 , M 2 , M 3 , M 4 } for DUTb and P 9 have the same FEP. Since the measurements M 1 to M 3 of DUTb are above IC 1,9 to IC 3,9 , either F 9 of severity level above S 9 or some other unmodeled fault exists in DUTb, and the KBD DUTb is declared faulty by the ZYLEP test without causing any test escape. When FEP comparison is integrated into ZTEEP discrimination strategy, P 9 and P 3 , which have different FEPs (for example, IC 3,3 = IN, and IC 3,9 ≠ IN), can be used to target DUTs with different faults to maintain zero test escape. Therefore, P 9 need not be excluded in the ZTEEP target profile set. When P 9 is compared with the measurement M={M 1 , M 2 , M 3 , M 4 } for KGD DUTa, P 9 and DUTa M have the same 105 FEP and M for DUTa is completely below P 9 . Therefore DUTa passes the comparison with P 9 . When P 3 is compared with the measurement M={M 1 , M 2 , M 3 , M 4 } for DUTa, P 3 and DUTa M have different FEPs. Therefore, no further threshold level comparison is needed. Hence, in contrast with the ZTEP profile set testing, DUTa passes the comparison with P 3 without causing any yield loss. 5.2.3.4 ZYLEP profile selection strategy To select profiles from the original profile set under the strategy ZYLEP, any selected profile must be not be completely below any other profile in the original set which has an identical fault excitation pattern. Definition 5-7 I DDQ profile selection strategy ZYLEP: Let Π Π Π Π be the set of profiles for all faults of interest. ZYLEP is the set of profiles obtained by removing from Π Π Π Π any profile P x for which there exists another profile P l ∈ ∈ ∈ ∈ Π Π Π Π such that FEP(P x )=FEP(P l ) and P i,x ≤ ≤ ≤ ≤ P i,l for all V i . 5.2.3.4.1 Profile severity for ZYLEP strategy Let S k * be the minimum severity level of F k at which there exists a profile P x in the ZYLEP profile set such that the I DDQ measurements M={M 1 , M 2 , ...} are just completely above P x for all V i and FEP(P x )=FEP(M). If S k * > S k , then DUTs that have the fault F k with severity levels in the range [S k , S k *] will pass the test, despite the fact that such DUTs violate circuit specifications. In other words, DUTs with F k with severity levels in the range [S k , S k *] represent test escapes and this range is TER k , the test escape range for fault F k . If S k * = S k , then this is the ideal situation 106 for F k , since I DDQ testing will declare DUTs with fault F k that do not violate specifications as fault-free and those that do as faulty. 5.2.3.4.2 ZYLEP Example 0 100 200 300 400 500 600 V1 V2 V3 V4 IDDQ (uA) . P14 P18 P19 Figure 5-9 P 14 , P 18 and P 19 fault excitation pattern comparison. As shown in Figure 5-9, FEP(P 14 ) = FEP(P 18 ) = FEP(P 19 ) and P 18 is completely below P 14 . Therefore, P 18 is excluded from the ZYLEP target profile set. Since IC 2,14 is below IC 2,19 but IC 3,14 is above IC 3,19 , P 14 and P 19 are not completely below each other, and both P 14 and P 19 are included in the ZYLEP set. Note that in Figure 5-8 the profile P 9 is completely below P 7 . If ZYLP strategy were used, P 9 would have been excluded from the target profile set. But since FEP(P 9 ) ≠ FEP(P 7 ), P 9 is not excluded from the ZYLEP target profile set. The column entitled ZYLEP profile set in Table 5-8 shows the target ZYLEP profile set. 107 5.2.3.5 ZTEEP profile selection strategy To select profile with zero test escape from the original profile set under the strategy ZTEEP, any selected profile must be not completely above any other profile in the original set, which has an identical fault excitation pattern. Definition 5-8 I DDQ profile selection strategy ZTEEP: Let Π Π Π Π be the set of profiles for all faults of interest. ZTEEP is the set of profiles obtained by removing from Π Π Π Π any profile P x for which there exists another profile P l ∈ ∈ ∈ ∈ Π Π Π Π such that FEP(P x )=FEP(P l ) and P i,x ≥ ≥ ≥ ≥ P i,l for all V i . 5.2.3.5.1 Profile severity for ZTEEP strategy Let S k * be the minimum severity level of F k at which there exists a profile P x in the ZTEEP profile set such that the I DDQ measurements M={M 1 , M 2 , M 3 , ...} are just completely above P x for all V i and FEP(M)=FEP(P x ). If S k * < S k , then DUTs that have the fault F k with severity levels in the range [S k *, S k ] will fail the test, despite the fact that such DUTs do not violate any circuit specifications. In other words, DUTs with F k with severity levels in the range [S k *, S k ] represent yield loss and this range is YLR k , the yield loss range for fault F k . 5.2.3.5.2 ZTEEP Example As shown in Figure 5-9, FEP(P 14 ) = FEP(P 18 ) = FEP(P 19 ) and P 14 is completely above P 18 . Therefore, P 14 is excluded in the ZTEEP target profile set. Since IC 2,18 is below IC 2,19 but IC 3,18 is above IC 3,19 , P 18 and P 19 are not completely above each other, and both P 18 and P 19 are included in the final set. Note that in 108 Figure 5-8, the profile P 9 is completely above P 3 . If ZTEP strategy were used, P 9 would have been excluded from the target profile set. However, since FEP(P 9 ) ≠ FEP(P 3 ), P 9 is not excluded from the ZTEEP target profile set. The column entitled ZTEEP profile set in Table 5-8 shows the target ZTEEP profile set. With the enhanced conditions that fault excitation pattern is considered by the profile selection strategy, we are able to include more profiles in the target profile set. Extra profiles in the final (ZYLEP or ZTEEP) profile set provide lower test escape and yield loss for ZYLEP and ZTEEP strategies, respectively. 5.2.3.6 Computation of TE and/or YL The proposed framework has been applied to our CMOS SRAM design (in Figure 5-3). Faults F 1 to F 21 with the exception of F 6 , shown in Table 5-8 are our target faults. Both the above I DDQ profile set selection strategies (ZYLEP and ZTEEP) are used. Columns entitled ZYLEP and ZTEEP in Table 5-8 show the TER or YLR (as applicable) for each of the above strategies for selecting profiles. 109 ZTET ZYLT P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P09 P08 P07 P05 P04 P03 P02 P01 119 501 501 154 *** *** 300 224 326 *** *** 318 *** 351 157 *** 274 *** *** 119 *** 189 V1 iaW0 569 569 501 *** 562 232 *** 223 *** 515 *** 266 325 *** 176 *** 274 *** 569 *** 188 *** V2 W1 iaW1 282 695 *** 174 172 270 265 *** 324 335 *** *** *** 317 175 282 260 695 *** *** *** 186 V3 W0 ipR0 172 695 *** 174 172 270 265 *** *** 335 284 284 324 317 *** *** 260 695 *** *** 187 *** V4 W1 ipR1 0.13 0.04 0.04 0.07 0.08 0.08 0.08 0.10 0.10 0.10 0.08 0.09 0.04 0.09 0.08 0.17 0.03 0.02 0.04 0.04 Sk' -- P20 P19 P18 -- P16 -- -- P13 P12 -- -- P09 -- P07 P05 P04 P03 P02 P01 Set Prof. [0.05, -- -- -- [0.04, -- [0.04, [0.07, -- -- [0.04, [0.04, -- -- -- -- -- -- -- -- [Sk* 0.13] 0.08] 0.08] 0.10] 0.08] 0.09] Sk'] P21 -- P19 -- -- -- P15 P14 P13 P12 P11 P10 P09 P08 P07 P05 P04 P03 -- -- Set Prof. -- [0.04, -- -- [0.08, [0.08, -- -- -- -- -- -- -- -- -- -- -- -- [0.04, [Sk', 0.50] 0.17] Infinite] Infinite] Sk*] -- -- P19 -- -- -- -- -- P13 -- -- -- -- P08 -- -- P04 P03 P02 -- Set Prof. [0.02, [0.03, -- [0.05, [0.03, [0.03, [0.03, [0.04, -- [0.03, [0.04, [0.02, [0.03, -- [0.03, [0.04, -- -- -- [0.02, [Sk* 0.13] 0.04] 0.07] 0.08] 0.08] 0.08] 0.10] 0.10] 0.08] 0.09] 0.04] 0.08] 0.17] 0.04] Sk'] P21 -- P19 -- -- -- P15 P14 -- P12 -- P10 -- -- P07 P05 P04 -- -- -- Set Prof. -- -- -- [0.07, -- [0.08, -- -- -- -- -- -- [0.04, -- -- -- -- [0.02, -- -- [Sk', 0.08] 0.11] Infinite] 0.03] Sk*] [0.02, [0.03, -- [0.05, [0.03, [0.03, [0.03, [0.04, [0.04, [0.03, [0.04, [0.02, [0.03, [0.04, [0.03, [0.04, -- -- -- [0.02, [Sk*, 0.13] 0.04] 0.07] 0.08] 0.08] 0.08] 0.10] 0.10] 0.10] 0.08] 0.09] 0.04] 0.09] 0.08] 0.17] 0.04] Sk'] -- [0.04, -- [0.07, [0.08, [0.08, [0.08, [0.10, [0.10, [0.10, [0.08, [0.09, [0.04, [0.09, [0.08, -- -- [0.02, [0.04, -- [Sk', 0.50] 0.50] 0.17] Infinite] 0.17] 0.17] Infinite] Infinite] 0.20] 0.14] Infinite] Infinite] Infinite] 0.03] Infinite] Sk*] -- : empty interval or empty profile Sk=Infinite : ~0 Ohm bridging resistance TERk ZYLP YLRk TERk ZTET ZYLT ZTEP ZTEEP New Strategies ZYLEP YLRk TERk YLRk Fault Profile ICi,k for vectors Strategies Table 5-8 Critical Current Table with TER and YLR results. 110 The number of faults that have non-zero YLR (TER) reduces from 16 (15) to 14 (4) when the concept of I DDQ fault profiling is used (Table 5-9). The number of faults that have non-zero YLR further reduces from 14 to 6 when the new concept of fault excitation profiling is proposed. Fault excitation profiling strategies also reduce the size of TER or YLR. For example, YLR 14 for ZTEP is reduced by 50% when ZTEEP is used. Table 5-9 YL and TE comparison. Excitation profiling strategies Profiling strategies Threshold strategies ZTEEP ZYLEP ZTEP ZYLP ZTET ZYLT No. of faults with non-zero YL 6 -- 14 -- 16 -- No. of faults with non-zero TE -- 4 -- 4 -- 15 5.2.3.7 Summary We have introduced new fault-free/faulty-device I DDQ fault excitation profile discrimination strategies and new fault excitation profile selection strategies. The new ZTEEP strategy reduces yield loss over the ZTEP strategy while maintaining zero test escape. The new ZYLEP strategy reduces test escape over the ZYLP strategy while maintaining zero yield loss. 5.3 Proposed research 5.3.1 Comprehensive ZTET strategy Given an original set of I DDQ test vectors, we propose to develop an I DDQ test vector selection strategy that selects a subset of vectors to achieve zero test escape with minimum yield loss for all targeted bridging faults. 111 Definition 5-9: Covering a fault – Given a target fault set F and an original set of vectors V. Consider a vector V i ∈ ∈ ∈ ∈ V and bridging fault F k ∈ ∈ ∈ ∈ F. If V i excites F k and IT i ≤ IC i,k , V i covers F k . Table 5-10 shows example critical currents for an original vector set comprised three vectors, V 1 , V 2 , and V 3 , for a fault list with four faults F={F 1 , F 2 , F 3 , F 4 }. Therefore, to cover the faults of interest with zero test escape, we have the following I DDQ threshold setting requirements. {F 1 : IT 1 ≤ 100 or IT 3 ≤ 200} and {F 2 : IT 1 ≤ 210 or IT 2 ≤ 220} and {F 3 : IT 2 ≤ 300} and {F 4 : IT 1 ≤ 150 or IT 3 ≤ 140}. Table 5-10 Example critical current. IC i,k (uA) Fault s V 1 V 2 V 3 F 1 100 -- 200 F 2 210 220 -- F 3 -- 300 -- F 4 150 -- 140 Table 5-11 Four possible ZTET test sets for the example. IT i Faults with YL IT 1 IT 2 IT 3 F 1 F 2 F 3 F 4 ZTET 1 210 300 140 X -- -- -- ZTET 2 210 220 140 X -- X -- ZTET 3 100 300 -- -- X -- X ZTET 4 100 220 -- -- X X X 112 There are four possible ZTET test sets, ZTET 1 to ZTET 4 , that meet the above requirements. Above four test sets are shown in Table 5-11. The faults with yield loss for the different ZTET test sets are shown in the columns entitled Faults with YL. Each of these tests contains different level of yield loss. For example, ZTET 2 has yield loss for both F 1 and F 3 , where ZTET 1 has yield loss only for F 1 . Furthermore, it can be shown that yield loss range (YLR) for F 1 is lower for the test set ZTET 1 than ZTET 2 . Hence, the test set ZTET 1 causes lower yield loss than for ZTET 2 . This is because, ZTET 2 uses IT 2 =220, which is an unnecessarily low threshold value, since raising IT i from 220 to 300, and without changing any of the other threshold values, the conditions of detection for all faults in F can still be satisfied. Similarly, ZTET 3 causes lower yield loss than ZTET 4 . Some test sets may achieve zero test escape with fewer test vectors. In the above example, ZTET 3 and ZTET 4 achieve zero test escape with a smaller subset of the original vector set. In order to analyze the trade-off amongst these solutions effectively, we propose to formulate a covering problem. Besides minimizing yield loss, we propose to cover the faults of interest with a minimal subset of the original vector set. 5.3.2 Bridging fault covering problem The yield loss minimization and test time reduction can be achieved by applying compatibility theory ([8] Appendix I, and [28] Chapter6) for test vector selection and threshold selection. We will formulate a covering problem that uses the definition for bridging fault coverage and properties of bridging vector compatibility. 113 Following are some of the properties we will use. o The selected vectors must cover all the faults in the given fault list. o The selected vectors must not cause unnecessary yield loss like ZTET 2 in the above example (see comparison with ZTET 1 ). o If a fault is covered by a single vector, V i , this V i must be included in the selected subset of vectors. Next are the corresponding proposed definitions for vector selection. Definition 5-10: Zero test escape test set -- Since the selected subset of vectors, V’, must achieve zero test escape, for each fault F k , ∃ ∃ ∃ ∃ a vector V i ∈ ∈ ∈ ∈ V’ such that IC i,k ≥ ≥ ≥ ≥ IT i . Definition 5-11: Zero yield loss test vector -- If V i is selected for inclusion in the set V’, then V i does not cause any yield loss if IT i = Max{IC i,k } for all faults F k , excited by V i . Definition 5-12: Essential vector -- If V i is the only vector in the original vector set V that excites fault F k , then V i is an essential vector and must be included in the selected set of vectors. Our research in this topic of I DDQ test vector selection with minimum yield loss would include the following. o Identification of additional properties of the type identified above. o Development of a covering procedure. o Identification of minimal number of vectors that can provide zero test escape. 114 Further research using compatibility theory for I DDQ bridging fault testing would include the following. o Application of the theory to threshold selection with minimum yield loss. o Application of the theory to I DDQ profile selection strategies. 5.3.3 Comprehensive ZTET ATPG For a given bridging fault list, our second proposed research task is to generate a test set and corresponding threshold current values that achieves zero test escape with zero or minimum yield loss. Following is the outline of a primitive test generation problem. For a target fault F k ∈ F, generate a vector that excites F k . This vector may excite some other faults in the fault list. If the critical current for the target fault is greater-than-or-equal-to the critical current for any other fault that the vector excites, then we can detect F k using this vector with zero yield loss. If no such vector can be found, we must consider all vectors V i that excite F k using I DDQ test threshold IT i =IC i,k , i.e., just low enough to cover the fault such that YL is minimized. The proposed ATPG will generate a vector, V i , for a selected fault F k . The critical current for such a fault may be (1) greater-than-or-equal-to the critical current for any other faults, F l , that the vector excites, or (2) less than the critical currents for some other faults that the vector excites. Therefore, we will have the following two cases for the IC i,k of vector V i . 115 o Case1: IC i,k ≥ IC i,l ∀ F l excited by V i . Zero yield loss for all faults of interest and zero test escape for F k . o Case2: There exist a fault F m excited by V i such that IC i,k < IC i,m . Yield loss for faults like F m and zero test escape for F k . Case2 causes yield loss. In order to reduce yield loss, we will include cost factors for the ATPG such that the difference between IC i,k and IC i,m is minimized. Although, the proposed ATPG may not able to always generate a vector that satisfies the criteria in Case1, the ATPG will generate vectors with yield loss much lower than other I DDQ ATPGs. With the goal of meeting the criteria for Case1, the ATPG may require a distinct vector per fault. This may suggest that test time would be too long for typical fault lists, which contain thousands of faults. However, this problem can be reduced significantly when threshold current proximity is considered. We found that: o Similar sized transistors are used in various gates in the library used for designs; therefore, bridge currents for many faults are similar. o Most logic libraries contain only a few types of logic cells. Therefore, bridges among cell outputs have only a small number of distinct critical current values. Due to these reasons, a single vector can detect many faults with zero yield loss and even many more with a small yield loss. 116 5.3.4 Comprehensive ZTEP strategy and ATPG For a set of I DDQ test vectors, when I DDQ profile testing strategy is used, there are many possible profile sets that cover the fault of interest. However, each of them can have different yield loss for different faults. In a manner similar to vector threshold selection for ZTET, we propose to develop covering algorithms for I DDQ profile testing such that we can achieve zero test escape and minimum yield loss. We also propose to cover the faults of interest with a subset of the original vector set that has minimum number of vectors. We propose to develop an ATPG algorithm for I DDQ profile testing that will achieve zero test escape at minimum yield loss. This ATPG algorithm will generate a set of vectors for the target fault list. This set of vectors will define an original I DDQ profile set. We will then select a final profile set from the original profile set. To achieve ZTE, any profile included in the final profile set must not be completely above any other profile in the original profile set. Sometimes, the test set generated by ATPG will contain some profiles in the original set that are completely above some other profiles in the profile set. The faults associated with such profiles would have yield loss. We will develop heuristics to direct ATPG to avoid generating profiles that cause significant yield loss. 117 References [1] M. Abramovici, and P. Menon, A practical approach to fault simulation and test generation for bridging faults, IEEE Trans. on Computers, C-34:658-663, 1985. [2] C. Cha, W. Donath, and F. Ozguner. 9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits, pp. 193-200, 1978. [3] B. Chess, D. Ferguson, and T. Larrabee, Diagnosis of realistic bridging faults with single stuck-at information, International Computer-Aided Design, pp. 185- 192, Nov. 1995. [4] H. Cheung, and S. Gupta, A Framework to Minimize Test Escape and Yield Loss during I DDQ Testing: A Case Study, IEEE 18 th VLSI Test Symposium, pp. 89- 96, 2000. [5] H. Cheung, and S. Gupta, I DDQ Profiles: A Technique to Reduce Test Escape and Yield Loss during I DDQ Testing, IEEE International Workshop on Defect Based Testing, pp. 45-50, 2000. [6] H. Cheung, and S. Gupta, Accurate Modeling and Fault Simulation of Byzantine Resistive Bridges, IEEE 25th International Conference on Computer Design, Oct 2007. [7] H. Cox, and J. Rajski, On necessary and nonconflicting assignments in algorithmic test pattern generation, IEEE Transactions on Computer-Aided Design, vol. 13, no. 4, pp.515-530, Apr. 1994. [8] J. Ellison, Techniques in Advanced Switching Theory, Department of Electrical Engineering, University of Southern California, 1995. [9] P. Engelke, I. Polian, M. Renovell, and B. Becker, Simulating resistive bridging and stuck-at faults, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(10): pp. 2181-2192, 2006. [10] P. Engelke, I. Polian, M. Renovell, and B. Becker, Automatic test pattern generation for resistive bridging faults, IEEE European Test Symposium, pp. 91-96, 2004. [11] A. Ferre, and J. Figueras, I DDQ Characterization in Submicron CMOS, International Test Conference, pp. 136-145, Nov. 1997. [12] A. Ferre, and J. Figueras, On Estimating Bounds of the Quiescent Current for I DDQ Testing, IEEE 14 th VLSI Test Symposium, page 106, 1996. 118 [13] J. Figueras, and A. Ferre, Possibilities and Limitations of I DDQ Testing in Sub- micron CMOS, IEEE Transactions on Components, Packaging, and Manufacturing Technology, part B, vol. 21, no. 4, pp. 352-359, Nov 1998. [14] C. Hawkins, J. Soden, A. Righter, and F. Ferguson, Defect classes-an overdue paradigm for CMOS IC testing, International Test Conference, pp. 413-425, 1994. [15] C. Hawkins, and J. Soden, I DDQ Testing: Issues Present and Future, IEEE Design & Test of Computers, vol.13, no.4, pp. 61-65, Dec. 1996. [16] T. Henry, and T. Soo, Burn-in Elimination of a High Volume Microprocessor Using I DDQ , International Test Conference, pp. 242-249, Oct. 1996. [17] N. Jha, and S. Gupta, Testing of Digital Systems, Cambridge University Press, ISBN 0521773563, 2003. [18] Z. Jiang, and S. Gupta, Threshold testing: Covering bridging and other realistic faults, IEEE Asian Test Symposium, 2005 [19] A. Keshk, Y. Miura, and K. Kinoshita, Procedure to overcome the Byzantine General's problem for bridging faults in CMOS circuits, IEEE Asian Test Symposium, pp. 121 126, Nov. 1999. [20] H. Lee, D. Ha, An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation, International Test Conference, pp. 946- 955, 1991. [21] K. Lee, and J. Tang, Two Modeling Techniques for CMOS to Enhance Test Generation and Fault Simulation for Bridging Fault, IEEE Asian Test Symposium, pp. 165-170, Nov. 1996. [22] C. Lee, and D. Walker, PROBE: a PPSFP simulator for resistive bridging faults, IEEE 18 th VLSI Test Symposium, pp. 105 110, Apr. 2000. [23] S. Ma, I. Shaik, and R. Fetherston, A comparison of bridging fault simulation methods, International Test Conference, pp. 587 595, Sept. 1999. [24] T. Maeda, and K. Kinoshita, Precise Test Generation for Resistive Bridging Faults of CMOS Combination Circuits, International Test Conference, pp. 510-519, 2000. [25] P. Maxwell, R. Aitken, K. Kollitz, and A. Brown, I DDQ and AC Scan: The War Against Unmodeled Defects, International Test Conference, pp. 250-258, 1996. 119 [26] P. Maxwell, and J. Rearick, Estimation of Defect-Free I DDQ in Sub-micron Circuits Using Switch Level Simulation, International Test Conference, pp. 882- 889, 1998. [27] P. Maxwell, and R. Aitken, I DDQ testing as a component of a test suite: the need for several fault coverage metrics, Journal of Electronic Testing: Theory and Applications, vol. 3, no. 4, pp. 305-316, Dec. 1992. [28] E. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits, Prentice Hall, ISBN 0-13-539784-7, 1986. [29] T. Nanya, and H. Goosen, The Byzantine Hardware Fault Model, IEEE Transactions on Computer-Aided Design, vol. 8, no. 11, pp. 1226-1231, Nov. 1989. [30] J. Pair, B. Carbajal, and T. Powell, Correlating Defects To Functional And I DDQ Tests, International Test Conference, pp. 501-510, Oct 1996. [31] M. Renovell, P. Huc, and Y. Bertrand, The concept of resistance interval: a new parametric model for realistic resistive bridging fault, IEEE 13 th VLSI Test Symposium, pp. 184 189, Apr 1995. [32] A. Righter, J. Soden, and R. Beegle, High Resolution I DDQ Characterization and Testing - Practical Issues, International Test Conference, pp. 259-268, Oct. 1996. [33] J. Roth, Diagnosis of automata failures: a calculus and a method, IBM Journal of Research and Development, vol. 10, pp. 278-291, Jul 1966. [34] V. Sar-Dessai, and D. Walker, Resistive bridge fault modeling, simulation and test generation, International Test Conference, pp. 596 605, Sept. 1999. [35] T. Shinogi, T. Kanbayashi, T. Yoshikawa, S. Tsuruoka, and T. Hayashi, Faulty resistance sectioning technique for resistive bridging fault ATPG systems, IEEE 18 th VLSI Test Symposium, pp. 76 81, Nov. 2001. [36] J. Soden, C. Hawkins, and A. Miller, Identifying defects in deep-submicron CMOS ICs, IEEE Spectrum, vol. 33, no. 9, pp. 66-71, Sept. 1996. [37] J. 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Abstract (if available)

Abstract Many studies show that bridging defects are major causes of fabrication failures. A bridging fault causes a short circuit between circuit nodes and can be tested by logic testing, which measures the erroneous logic values at the circuit outputs, or by IDDQ testing, which measures the elevated power supply current (called IDDQ). This research spans logic as well as IDDQ testing for bridging faults.

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Asset Metadata

Creator Cheung, Hugo Chong-hing (author)

Core Title Accurate and efficient testing of resistive bridging faults

School Andrew and Erna Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering (VLSI Design)

Publication Date 04/15/2008

Defense Date 03/24/2008

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag ATPG,Byzantine resistive bridge,fault simulation,IDDQ,OAI-PMH Harvest

Language English

Advisor Gupta, Sandeep K. (committee chair), Medvidovic, Nenad (committee member), Ung, Monte (committee member)

Creator Email cheung_hugo@ti.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-m1108

Unique identifier UC1103479

Identifier etd-Cheung-20080414 (filename),usctheses-m40 (legacy collection record id),usctheses-c127-52759 (legacy record id),usctheses-m1108 (legacy record id)

Legacy Identifier etd-Cheung-20080414.pdf

Dmrecord 52759

Document Type Dissertation

Rights Cheung, Hugo Chong-hing

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Repository Name Libraries, University of Southern California

Repository Location Los Angeles, California

Repository Email cisadmin@lib.usc.edu