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Synthesis, assembly, and applications of single-walled carbon nanotube

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Synthesis, assembly, and applications of single-walled carbon nanotube

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Content SYNTHESIS, ASSEMBLY, AND APPLICATIONS
OF SINGLE-WALLED CARBON NANOTUBE

by
Koungmin Ryu

A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(MATERIALS SCIENCE)

December 2009

Copyright 2009 Koungmin Ryu

ii
Epigraph

“大器晩成”
“Great talents mature late”

iii
Dedication

Dedicated to my wife, Youngsun, my baby, Leah, and my parents.

iv
Acknowledgements

First of all, I would like to thank my advisor, Dr. Zhou, for offering me the
opportunity to study at USC, experience the most advanced nanotechnology and finally
get a Ph. D in Materials Science. His guidance and encouragement is indispensable to my
research work. Moreover, I deeply appreciate the constant support I have received during
the past four years.

I also would like to thank my family: specially, my wife, Youngsun, for her
endless support and love (Half of my degree belongs to her), my baby, Leah, for being
my daughter, my parents for their sacrifice to support me, and my brother and sisters for
trusting me all the time.

Finally, I want to thank my colleagues and collaborators: Dr. Song Han, Dr.
Daihua Zhang, Dr. Bo Lei, Fumiaki Ishikawa, Pochiang Chen, Alexander Badmaev,
Lewis Gomez, Akshay Kumar, Hsiaokang Chang, Keng Saowalak, Chuan Wang, Yi
Zhang, Jialu Zhang, Anuj Madaria, Haitian Chen, Yue Fu, Akshay Kumar, Nishant Patil,
Alber Lin, Guangyu, Prof. K. L. Wang, Prof. Philip Wong, Prof. Subhasish Mitra and all
other people who offered their precious help. I also would like to thank the members of
my Quals and Dissertation Committees, Prof. Eun Sok Kim, Prof. Edward Goo, Prof.
Mark E. Thompson, Prof. Dan Dapkus.

v
Table of Contents
Epigraph…………………………………………………………………………………..ii
Dedication………………………………………………………………………………...iii
Acknowledgements……………………………………………………………………..iv
List of Figures……………………………………………………………………………vii
Abstract………………………………………………………………………………….xiii
Chapter 1 Introduction…………………………………………………………………….1
1.1 Introduction of carbon nanotube…………………………………………..1
1.2 Structure of carbon nanotube……………………………………………...2
1.3 Electrical properties of carbon nanotube…………………………………..3
1.4 Research directions………………………………………………………..8
Chapter1. References………………………………………………………...10

Chapter2 Position and direction controlled carbon nanotube synthesis…………………12
2.1 Review of existing methods of synthesizing carbon nanotubes………….12
2.2 Nanolithography for catalyst deposition…………………………………13
2.3 Position and direction controlled carbon nanotube synthesis……………18
Chapter2. References………………………………………………………...21

Chapter 3 Wafer-scale integrated aligned carbon nanotube circuits…………………….23
3.1 Wafer-scale aligned carbon nanotube synthesis………………………….23
3.2 Wafer-scale aligned nanotube transfer…………………………………...26
3.3 Integrated nanotube circuits ……………………………………………..28
Chapter3. References………………………………………………………...44

Chapter 4 Aligned carbon nanotube for flexible electronics…………………………….46
4.1 Transfer imprinting of aligned nanotubes………………………………..46
4.2 Characterization of transferred aligned nanotubes……………………….49
4.3 Flexible Transistors based on transferred nanotubes…………………….51
Chapter4. References………………………………………………………...56

Chapter 5 Transparent, conductive, and flexible carbon nanotube film…………………58
5.1 Overview of carbon nanotube films……………………………………...58
5.2 Fabrication of carbon nanotube films…………………………………….59
Table 5.1: Comparison between pristine nanotube films based on HiPCO
and P3 nanotubes…………………………………………...63
5.3 Application on OLED……………………………………………………68
Chapter5. References………………………………………………………...71

vi
Chapter 6 High-performance metal oxide nanowire chemical sensors………………….72
6.1 Overview of metal oxide chemical sensors………………………………72
6.2 Nanowire chemical sensors with micro-machined hotplates…………….73
Chapter6. References………………………………………………………...81

Chapter 7 Conclusion…………………………………………………………………….83
7.1 Summary………………………………………………………………... 83
7.2 Future work………………………………………………………………84

Bibliography……………………………………………………………………………..86

vii
List of Figures

Figure 1.1 Schematic diagram of Graphene layer. A carbon nanotube can be constructed by
cutting a graphene layer along lines OB and AC, and then rolling it up into a tube, so
that O meets A and C meets B. Vector OA is called the chiral vector (Ch)……………2

Figure 1.2 Schematic diagram of Zigzag, Armchair, and Chiral nanotube………………………..3

Figure 1.3 Energy dispersion relations for graphene. The inset shows the energy dispersion
relations along the high symmetry points, Γ, Κ, Μ……………………………………...4

Figure 1.4 The wave vector k for one-dimensional carbon nanotubes is shown in the two-
dimensional Brillouin zone of graphene (hexagon) as bold line for metallic
nanotubes………………………………………………………………………………..5

Figure 1.5 Dispersion relations for a semiconducting (10,0) nanotube (upper) and a metallic (9,0)
nanotube (lower)………………………………………………………………………...6

Figure 1.6 Density of states for a (10,0) semiconducting nanotube and a (9,0) metallic nanotube.
Note the nonzero density of states near zero energy for the metallic nanotube………...7

Figure 2.1 a) Schematic diagram of nanosphere lithography for aligned nanotube growth. b)
Photograph of a three-inch quartz wafer with spin-coated polystyrene nanospheres. c-e)
SEM images of ordered monolayers of 50 nm, 100 nm and 200 nm polystyrene
nanospheres, respectively. e) inset: SEM image of an ordered bilayer of 200 nm
nanospheres (The bottom layer is visible through the missing nanosphere in the top
layer)…………………………………………………………………………………..14

Figure 2.2 a) and b) SEM images of catalyst arrays prepared using nanosphere lithography before
and after annealing. c) and d) AFM images of catalyst arrays prepared with 3 Å and 5
Å Fe films deposited, respectively. Inset: histograms of the catalyst particle size……15

Figure 2.3 Calculated geometrical factor S( α, φ) for a monolayer (a) and (b) for a bilayer of
packed nanospheres……………………………………………………………………16

Figure 2.4 Calculated catalyst nanoparticle diameter v.s. the metal deposition angle for
monolayers and bilayers of 200 nm, 100 nm and 50 nm nanospheres………………...17

Figure 2.5 a) AFM image of catalyst arrays prepared using nanosphere lithography with a packed
bilayer of 100 nm nanospheres and with 20 Å Fe deposited. b) Histogram of the
diameter of catalyst nanoparticles……………………………………………………..17

Figure 2.6 a) Photograph of a quartz substrate with polystyrene nanospheres packed in stripe-
shaped trenches patterned in photoresist. b) SEM image of an ordered array of
nanospheres inside the trench. c) SEM image of aligned nanotubes grown from the
catalyst prepared using NSL. d) Polarization-dependent Raman spectrum of a
nanotube……………………………………………………………………………….18

Figure 2.7 Raman spectrum of a nanotube……………………………………………………….19
viii

Figure 3.1 Photograph of a 4 inch quartz wafer with aligned nanotubes and patterned electrodes.
Inset: SEM images of aligned nanotubes between electrodes at different locations of the
wafer…………………………………………………………………………………...25

Figure 3.2 a) Photograph of 4 inch sapphire wafer with aligned nanotubes. b) Schematic diagram
of 9 feet-long furnace for wafer-scale nanotube growth. c) and d) SEM images of
aligned nanotubes and Temperature flow charts for the annealing and the nanotube
growth on sapphire and quartz wafer, respectively…………………………………...26

Figure 3.3 Wafer-scale aligned nanotube synthesis, transfer, and fabrication. a) Schematic
diagram and photograph of full wafer synthesis of aligned nanotubes on a 4 in. quartz
wafer. Inset shows SEM image of aligned nanotubes. b-f) Schematic diagrams and
photographs showing the transfer procedure, i.e., gold film deposition b), peeling off
the gold film with nanotubes c), transfer of the gold film with nanotubes onto a Si/SiO2
substrate d), etching away the gold film e), and device fabrication on the transferred
nanotube arrays f)……………………………………………………………………...27

Figure 3.4 Photo images of nanotube devices and circuits built on a 4 in.Si/SiO
2
wafer: 1, back-
gated transistor; 2, top-gated transistor; 3, CMOS inverter; 4, NOR logic gate; 5,
NAND logic gate………………………………………………………………………28

Figure 3.5 Characteristics of back-gated transistors down to submicron channel length. a)
Schematic diagram of a back-gated transistor built on transferred nanotubes. b) SEM
image of a transistor with submicron channel length. c) Transfer (I
ds
-V
g
) characteristics
of transistors with different L= 0.5, 0.75, 1, 2, 5, 10, and 20 μm, and W = 100 μm. d)
Normalized on and off- current densities and transconductance (gm) derived from c). e)
– g) Electrical breakdown study of the transistors; Ids-Vg curves for a typical transistor
after consecutive electrical breakdown e), Ids-Vg curves and Ids-Vds curves of the
transistor in e) after three rounds of electrical breakdown (f), and Statistics of devices
before and after electrical breakdown g). h) Ids–Vg curves of two representative
devices, with one (black) and two (red) steps of transfer, respectively. Inset illustrates
the multiple transfer process…………………………………………………………..30

Figure 3.6 I-Vg and gm curve from a device with 50 μm channel length………………………..31

Figure 3.7 Top-gated transistors for doping and truly integrated CMOS inverters. a), b) Schematic
diagram and SEM image of a top-gated transistor, respectively. c) Ids-Vg curves of the
transistor with L= 3 μm and W = 25 μm at different Vds = 0.1 to 1.1 V in step of 0.1 V.
Inset: Ids-Vg curve in logarithm scale. d) Ids-Vds curves at different Vg = -20, -15, -
10, 10, 15, and 20 V for the same device in (c). e) Ids-Vg curves of the top-gated
transistor before (red) and after (black) K doping. f) Voltage transfer characteristic
(VTC) of a CMOS inverter with selective K doping. Inset: schematic diagram (left) and
photograph (right) of the circuit. g) Ids-Vg curves of a dual-gated transistor before (red,
back gate at -20 V) and after (black, back gate at 20 V) electrostatic doping. h) Ids-Vg
curves at different Vbg = -20 to 20 V for the same device in (e), showing a significant
shift of threshold voltage and enhancement of n-type conduction…………………….33

ix
Figure 3.8 a), b) I-Vg curves of a back-gated device before and after PEI doping, respectively. c),
d) SEM images of the top-gated devices before and after soaked in N2H4, respectively.
e), f) I-Vg curves before and after N2H4 doping on the back-gated devices without and
with PMMA passivation, respectively…………………………………………………35

Figure 3.9 PMOS NOR and NAND gates with top-gated transistors. a)-c) Schematic diagrams of
a defect-influence layout and two defect-tolerate layouts with two transistor in parallel,
respectively. d), e) Output characteristics of PMOS NOR and NAND, respectively.
Inset: SEM image of integrated pull-up networks and schematic diagram of PMOS
circuits. f), g) Output characteristics of PMOS NAND with pull-up network (b) and (c),
respectively, where the nanotube density was not uniform in the circuit, as depicted in
schematic diagram in inset…………………………………………………………….38

Figure 3.10 a), b) I-VA curves at different VB = 5, 0, -5 V from the two different types of
NAND pull-up networks, as shown in SEM images and schematic diagrams………..39

Figure 3.11 Defect-tolerant CMOS NOR and NAND with individual back-gated transistors. a), b)
Schematic diagrams of CMOS NOR and NAND, respectively. c), d) SEM images of
CMOS NOR and NAND, respectively. e), f) Output characteristics of CMOS NOR and
NAND, respectively…………………………………………………………………...41

Figure 3.12 a), b) I-Vg curves of the pull-up network (in dotted line) in CMOS NAND before and
after potassium doping, respectively. c), d) I-Vg curves of the pull-down network (in
dotted line) in CMOS NAND before and after potassium doping, respectively………42

Figure 4.1 Transfer printing of aligned nanotube arrays. a) Diagrams illustrating the aligned
nanotube transfer process. b) SEM image of as-grown aligned single- walled nanotubes
on a quartz substrate with stripe patterned catalyst. The image shows that nanotubes are
well aligned, straight and uniformly grown between two Fe catalyst stripes (bright
region). c) Optical micrograph of transferred aligned nanotubes on PET with patterned
source/drain electrodes. The PET coated with 50 nm ITO was first spin-coated with 2
µm SU-8 (Microchem) as a dielectric layer, and then nanotubes were transferred,
followed by photolithography and e-beam evaporation of Ti/Au films to define source
and drain. Inset shows a SEM image of the aligned nanotubes bridging between source
and drain electrodes. d) Optical micrograph of transferred nanotubes on fabric with
source/drain electrodes. e) and f) SEM images of aligned nanotube arrays transferred
onto the same substrates at parallel orientation, where the density of nanotubes are ~ 14
tubes /µm and ~ 21 tubes / µm after the second and third round of transfer, respectively.
g) Plot of nanotube density as a function of the number of transfer steps, showing the
linear increase of nanotube density……………………………………………………47

Figure 4.2 Characterization of transferred nanotubes. a) Raman spectra of a nanotube before and
after transfer, showing little difference. b) Raman intensity of D-band and G-band of an
ensemble of 60 nanotubes before and after transfer. c) Contact angle of water droplet
as a function of the number of transfer steps. The Contact angle ( θ) is defined as cos θ =
(f
VS
-f
LS
)/f
LV
, where f
VS
, f
LS
and f
LV
are interfacial force of vapour and substrate, water
and substrate, and water and vapour, respectively. As the quartz substrate are covered
by transferred nanotubes, f
LS
becomes smaller due to the low surface energy of
nanotubes, making the surface hydrophobic. Clearly, the water drop on a blank quartz
substrate (bottom) reveals a hydrophilic surface, as compared to the hydrophobic
x
surface for the quartz substrate with a transferred nanotube network (top). d) SEM
image of an aligned nanotube network on quartz, which are obtained by two steps of
nanotube transfer with orthogonal orientations. e) The transmittance spectra of a glass
substrate before and after transfer, showing the high transparency of the transferred
nanotubes. The substrate after transfer contains nanotubes of 1.3 nm average diameter
with a density of ~ 10 tubes / µm, which can cover 11.3% of the surface area ( the
stripe patterned area of 5 µm width was included). f) The change of resistance (R) as a
function of the bending angle of a device (channel length L = 4 µm, channel width W
= 50 µm, nanotube density D = 5 tubes / µm) fabricated on a PET substrate. Two-
probe dc conductance measurements were performed to get resistance of the device,
and the bending angle was determined by measuring the angle between the two
tangential lines drawn on the edge of the substrate as shown in the inset…………….50

Figure 4.3 Wearable transistors based on aligned nanotubes transferred to fabric. a) Schematic
diagram showing a transistor structure that uses polyethylene- coated fabric as the
substrate, 50 nm thick Ti film for the back-gate electrode, 2 µm SU-8 as the dielectric
layer, and the transferred aligned nanotube array as the active channel. The optical
micrograph shows an array of such transistors built on a flexible fabric. b) I-Vg curves
of a transistor (L = 4 µm, W = 10 µm, D = ~ 2 tubes / µm ) before and after electrical
breakdown. c, I -Vg curves at different Vds for the device in (b). The curves labelled 1
to 6 correspond to Vds= 0 to -1 V in steps of -200 mV. The inset shows the logarithm
plot of the I-Vg curves. The subthreshold swing ( S = dVg/dlog(Ids) ) and the on/off
ratio are 2.5 V/decade and 105, respectively. d) I – Vds curves at different Vg for the
same device in (b). The curves labelled 1 to 6 correspond to Vg = 0 to -30 V in step of -
6 V. e) The on-current change of a transistor at different relative humidity ( Vg = - 30
V, Vds = 0.4 V)………………………………………………………………………..52

Figure 4.4 Use of the transferred aligned nanotubes built on fabric as chemical sensors. a)
Schematic diagram showing a nanotube chemical sensor detecting NO2 molecules. b)
Chemical sensing performance of the device with L = 4 µm, W = 150 µm, D = ~ 5
tubes / µm) upon exposure to 10 and 50 ppm NO
2
. Normalized conductance change (S)
for 10 ppm NO
2
was estimated as around 500% with the definition S = ΔG/G0 = (G –
G0)/G0, where G0 and G denote the nanowire conductance before and after NO2
exposure. The conductance change became significant with increased NO2
concentrations, from 500% at 10 ppm to over 1500% at 50 ppm. The minimum
detectable NO2 concentration which is derived by the conductance change at different
concentration can be down to ~ several ppm NO2 in air. c) Sensing data to 0.6 ppm
TNT using the same device in (b) 0.6 ppm TNT vapour was obtained by heating up
TNT source to 60 °C and using 100 sccm Ar as the carrier gas. The nanotube sensor
was maintained at 90 °C for improved sensing efficiency, and the sensing experiments
were carried out by monitoring the nanotube device conductance change under the
vaporized TNT. The chemical structure of TNT (C
6
H
2
(NO
2
)
3
CH
3
) is shown in the inset.
After TNT exposure, the nanotube device showed around 40% suppression of the
conductance……………………………………………………………………………53

Figure 5.1 a) Schematic diagram of a typical multilayer OLED. b) Photograph of a SWNT film
on an alumina filtration membrane. Inset: An SEM image showing the microscopic
structure of the porous membrane surface (before SWNT deposition). c) Illustration of
the dry transfer process, in which the SWNT-film is peeled off from the filtration
xi
membrane using a PDMS stamp and successively printed on a rigid or flexible
substrate. d) A transparent 40-nm thick SWNT film on a glass substrate 2” in diameter
and (e) a flexed SWNT film on a PE sheet. A sheet of paper with printed “USC” was
placed underneath the nanotube films to illustrate the transparency………………….60

Figure 5.2 a) and b) SEM images of a HiPCO and a P3 SWNT film taken from a perspective
angle (60° from the normal direction), respectively. c) and d) are top views of the same
SWNT films. The inset images (1 μm by 1 μm) are taken at higher magnifications. e)
Sheet resistance vs. transparency curves of HiPCO and P3 SWNT films…………….62

Figure 5.3 a) AFM image of a pristine P3 SWNT film. b) AFM image of a PEDOT-passivated
nanotube film showing a surface roughness of 3.1 nm, which is comparable to 2.4 nm
roughness of typical ITO substrates (inset). c) Sheet resistance vs. film thickness of P3
SWNT films. Inset: conductivity vs. film thickness. d) Transmittance spectra for
SWNT films of thickness 20, 40, 80, and 120 nm. The transmittance of the SWNT-
films decreases monotonically with the film thickness. The 20 nm and 40 nm films
exhibit sufficiently high transparency (>80%) over a wide spectral range from 300 to
1100 nm. Inset: sheet resistance vs. temperature curve taken with a SWNT film of 40
nm in thickness………………………………………………………………………...64

Figure 5.4 a) Four probe I-V curves taken on a 40 nm SWNT film before (dashed) and after (solid
line) SOCl
2
treatment, indicating a decrease in sheet resistance by a factor of ~ 2.4. b)
Transmittance spectra of a pristine (dashed) and a SOCl
2
-treated (solid line)
sample………………………………………………………………………………….66

Figure 5.5 a) Structure of the OLED device employed for the present study. The device consists
of multi layers of patterned SWNT-film (40 nm), PEDOT (10 nm), NPD (50 nm), Alq
3

(50 nm) and LiF(10 Ǻ)/Al (1500 Ǻ). The energy diagram of the device is illustrated in
the upper-right inset. The upper-left inset shows a photograph of a completed device
fabricated on a glass substrate. b) Photoluminescence spectrum of the Alq3 coating. c)
Current density vs. voltage bias curve recorded on one device pixel. d) Brightness vs.
voltage bias. The device shows a threshold voltage of ~ 5V and a maximum brightness
of 17 Cd/m2. e) Quantum efficiency as a function of current density………………...67

Figure 6.1 a) Schematic diagram of a micromachinced heater on a suspended SiN membrane. b)
Photograph of a 3 × 3 array of chemical sensor chips. Inset: photograph showing the
SiN membrane with a micromachined heater and sensing electrodes. c) SEM image of
the active area of one chemical sensor chip, where the dashed box indicates the SiN
membrane. d) SEM image of a sensing device with a nanowire bridging two
electrodes………………………………………………………………………………75

Figure 6.2 a) Hot plate temperature as a function of the applied voltage. Inset: the measured Pt
heater resistance versus the calculated temperature. b) Hot plate temperature as a
function of the power consumption of the Pt heater. c) Conductance change of an In
2
O
3

nanowire sensor as a function of the hotplate temperature, where the sensor chip is
placed in air and in argon (inset), respectively………………………………………...76

Figure 6.3 a) and b) Sensing response of an In
2
O
3
nanowire sensor to 100 ppm ethanol diluted in
air with the hotplate controlled at different temperatures. The normalized conductance
change ( ΔG/G) of an In
2
O
3
nanowire is plotted as a function of time (a) and as a
xii
function of temperature (b), respectively. c) and d) Sensing response of an In
2
O
3

nanowire sensor operated at 275 °C to four different ethanol concentrations (1, 10, 50,
and 100 ppm). The normalized conductance change ( ΔG/G) of an In2O3 nanowire is
plotted as a function of time (c) and as a function of concentration (d),
respectively…………………………………………………………………………….77
Figure 6.4 a) and b) Sensing response of an In
2
O
3
nanowire sensor operated at 275 °C to 10, 50
and 100 ppm CO carried in air (a), while the sensing response to 50 and 100 ppm
hydrogen is shown in (b)………………………………………………………………79
Figure 7.1 Metal contact Engineering. a) Schematic diagrams of n-type transistor with Gd
contacts. b) I-Vg curves of a n-type nanotube transistor before and after electrical
breakdown. c), d) I-V
g
and I-V
ds
family of the transistor in Figure b,
respectively…………………………………………………………………………..84

xiii
Abstract
This dissertation presents the synthesis and assembly of aligned carbon nanotubes, and
their applications in both nano-electronics such as transistor and integrated circuits and macro-
electronics in energy conversion devices as transparent conducting electrodes. Also, the high
performance chemical sensor using metal oxide nanowire has been demonstrated.
Chapter1 presents a brief introduction of carbon nanotube, followed by discussion of a
new synthesis technique using nanosphere lithography to grow highly aligned single-walled
carbon nanotubes atop quartz and sapphire substrates. This method offers great potential to
produce carbon nanotube arrays with simultaneous control over the nanotube orientation, position,
density, diameter and even chirality.
Chapter3 introduces the wafer-scale integration and assembly of aligned carbon
nanotubes, including full-wafer scale synthesis and transfer of massively aligned carbon nanotube
arrays, and nanotube device fabrication on 4 inch Si/SiO
2
wafer to yield submicron channel
transistors with high on-current density ~ 20 μA/ μm and good on/off ratio and CMOS integrated
circuits. In addition, various chemical doping methods for n-type nanotube transistors are studied
to fabricate CMOS integrated nanotube circuits such as inverter, NAND and NOR logic devices.
Furthermore, defect-tolerant circuit design for NAND and NOR is proposed and demonstrated to
guarantee the correct operation of logic circuit, regardless of the presence of mis-aligned or mis-
positioned nanotubes.
Carbon nanotube flexible electronics and smart textiles for ubiquitous computing and
sensing are demonstrated in chapter4. A facile transfer printing technique has been introduced to
transfer massively aligned single-walled carbon nanotubes from the original sapphire/quartz
substrates to virtually any other substrates, including glass, silicon, polymer sheets, and even
fabrics. The characterization of transferred nanotubes reveals that the transferred nanotubes are
highly conductive, transparent, and flexible as well. Based on transferred nanotube arrays on
xiv
fabric, we have successfully demonstrated nanotube transistors with on/off ratios ~ 10
5
, and
chemical sensors for low-concentration NO
2
and 2,4,6-trinitrotoluene (TNT).
In Chapter5, I present the study of transparent conductive thin films made with two kinds
of commercial carbon nanotubes: HiPCO and arc-discharge nanotubes. These films have been
further exploited as hole-injection electrodes for organic light emitting diodes (OLEDs) on both
rigid glass and flexible substrates. Our experiments reveal that films based on arc discharge
nanotubes are overwhelmingly better than HiPCO-nanotube-based films in all the critical aspects,
including the surface roughness, sheet resistance, and transparency. The optimized films show a
typical sheet resistance of ~160 Ω/ □ at 87% transparency and have been successfully used to
make OLEDs with high stability and long lifetime.
Lastly, I present the fast and scalable integration of nanowire chemical sensors with
micromachined hotplates built on SiN membranes. These hotplates allowed nanowire chemical
sensors to operate at elevated temperatures in order to enhance the sensitivity of chemical sensors
to target gases. By applying different current through the platinum heating filament, we can easily
vary the device temperature from room temperature to 350 °C. These nanosensors with integrated
hot plates have been exploited for the detection of ethanol, CO and hydrogen down to
concentrations of 1 ppm, 10 ppm and 50 ppm, respectively.
1
Chapter 1. Introduction

1.1 Introduction of carbon nanotube
Since discovered by Sumio Iijima at NEC Corporation in Japan in 1991[1], carbon
nanotubes (CNTs) due to their remarkable electronic and mechanical properties have stimulated
enormous interest for both fundamental research and future applications.
CNT has a honeycomb structure with smaller size than the most advanced semiconductor
devices fabricated so far. Study of CNT may lead to new understanding of semiconductor physics
at nanoscale because of its very small size and the special electronic properties. One of the most
significant properties of carbon nanotubes is their electronic structure which depends only on
their geometry, and is unique to solid state physics. For instance, CNTs can be either metallic or
semiconductive, depending on their structures, without any extended doping. In addition, CNTs
have high current-carrying capability, high carrier mobility[3], high saturation velocity[4],
excellent thermal conductivity[5], ultra-thin geometry, and the potential to be integrated with
mainstream silicon-based semiconductor electronics. Furthermore, CNTs exhibit extraordinary
mechanical properties, with Young’s modulus over 1 TPa [6]and tensile strength ∼200 GPa. Due
to the ultra-high surface-to-volume ratio of CNTs, they can be further employed to work as high-
performance chemical and biosensors. It is possible to attach other chemical groups to the tip or
sidewall of the CNTs and alter the electrical property to suit the application.

1.2 Structure of carbon nanotube
Carbon nanotubes can easily be visualized as graphene sheets rolled up into seamless
cylinders. A single walled carbon nanotube (SWNT) can be as long as several centimeters, while
the diameter is only one to two nanometers. The most interesting aspect is the change of its
properties depending on how one rolls the graphene sheet to make the nanotube. As shown in
Figure 1, we can cut the graphene along the lines of OB and BB’ and then roll it up into a
nanotube, so that O meets A, and B meets B’. The chiral vector(C
h
) OA is defined on the
hexagonal lattice as OA = ma
1
+ na
2
, where a
1
and a
2
are two basic vectors shown in Figure 1,
and n and m are two integers that can be used to fully define the structure of this nanotube. The
chiral angle, θ , is measured relative to the direction defined by a.

Figure 1.1 Schematic diagram of Graphene layer. A carbon nanotube can be constructed by cutting a graphene layer
along lines OB and AC, and then rolling it up into a tube, so that O meets A and C meets B. Vector OA is called the
chiral vector (C
h
)[2].

The diagram in Figure 1.1 has been constructed for (m, n) = (4, 3), and the unit cell of
this nanotube is bounded by OABB’. Different types of carbon nanotubes have different values of
n and m. Figure 1.2 display the schematic diagram of three kinds of carbon nanotubes: zigzag,
armchair, and chiral nanotubes. Zigzag nanotubes correspond to either m or n is 0, and have a
chiral angle of 0°. Armchair nanotubes (named so, because the configuration is similar to an
2
armchair) have n = m and a chiral angle of 30°, while other nanotubes are generally called chiral
nanotubes.

Figure 1.2 Schematic diagram of Zigzag, Armchair, and Chiral nanotube.

In addition, with the index (n, m), one can clearly specify the structure of a SWNT and
calculate the important geometric parameters such as the diameter π / ) (
2 2
nm m n a d
t
+ + =
and chiral angle )] 2 /( 3 [ tan
1
n m m + =
−
θ .

1.3 Electrical Properties of Carbon nanotube
The electronic structure of a SWNT can be derived simply from that of graphene[7]. In
graphene, three σ bonds hybridize in a sp
2
configuration, while the other 2p
z
orbital, which is
perpendicular to the graphene plane, makes π covalent bonds. It is known that the π electrons are
valence electrons which are relevant for the transport and other solid state properties. Therefore,
only π energy bands for graphene are considered to determine the electrical properties of
graphene. The electronic energy dispersion relations for graphene are derived by a simple tight-
binding calculation[7], given by,
3
()
2
1
2
0 2
2
cos 4
2
cos
2
3
cos 4 1 ,
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+ ± =
a k a k
a k
k k E
y y
x
y x D g
γ , (1.1)
where
0
γ is the C-C transfer energy, and the positive and negative E correspond to the π* and π
energy bands, respectively.

Figure 1.3 Energy dispersion relations for graphene. The inset shows the energy dispersion relations along the high
symmetry points, Γ, Κ, Μ.

Figure 1.3 shows the plot of the electronic energy dispersion relations for graphene as a
function of the two-dimensional wave vector k in the Brillouin zone. In a nanotube, the wave
vector (K
1
) along the circumferential direction of nanotube becomes quantized due to the periodic
boundary condition, and the wave vector (K
2
) along the nanotube axis remains continuous for a
nanotube of infinite length. Therefore, based on the energy dispersion relations of graphene, the
nanotube dispersion relations are given by
), ( ) (
1
2
2
2
K
K
K
k E k E
D g
μ
μ
+ = ( μ=0, ⋅⋅⋅, N-1, - π/T < k < π/T), (1.2)
where T is the magnitude of the translational vector T, k is a 1D wave vector along the nanotube
axis, and N denotes the number of hexagons within the nanotube unit cell. Furthermore, the N
4
5
e 2D
tion
on, e third of the
nanotubes are metallic and the other two thirds are semiconducting.
pairs of energy dispersion curves given by Eq. (1.2) correspond to the cross sections of the two-
dimensional energy dispersion surface shown in Figure1.3, where cuts are made on the lines of
kK
2
/ ⏐K
2
⏐ + μK
1
. If the cutting line for one (n, m) nanotube passes through a K point of th
Brillouin Zone shown in Figure1.4, where the π and π* energy bands of 2D graphite are
degenerated by symmetry, the 1D energy bands have a zero energy gap and this nanotube
therefore is metallic. On the other hand, if the cutting line does not pass through a K point, this
nanotube can be semiconducting with a finite energy gap between the valence and conduc
bands. Furthermore, the condition for a metallic nanotube is that (n-m) is a multiple of 3,
otherwise, the nanotube is a semiconducting one. Based on this relati on

Figure 1.4 The wave vector k for one-dimensional carbon nanotubes is shown in the two-dimensional Brillouin zone of
and a
graphene (hexagon) as bold line for metallic nanotubes.

Figure 1.5 shows the band structures of two zigzag nanotubes with different diameter,
showing different electrical properties such as semiconducting nanotube (10, 0) in the upper
6
metallic nanotube (9,0) in the lower, respectively. One can clearly see the band gap from a
semiconducting nanotube (upper), while there is no band gap in a metallic nanotube (lower).
X Ga m m a
-2
-1
0
1
2
D ispersion re la tion for (10,0)nanotube
k
0
X Ga mm a
-2
-1
0
1
2
D ispersion re la tion for (9,0)nanotube
k
0

Figure 1.5 Dispersion relations for a semiconducting (10,0) nanotube (upper) and a metallic (9,0) nanotube (lower).
Furthermore, based on the energy
also calculated by the following equation,

dispersion relations, the density of states (DOS) of nanotube is
1
1
) (
2
1
−
=
N
j t
t j
dk
k dE
π
Figure 1.6 shows the comparison of DOS for semiconducting (10, 0) and metallic (9
nanotubes. We
) (
∑
= E D . (1.3)
, 0)
can notice the difference between two cases near the Fermi level E
F
located at E=0.
This density of states has a value of zero for semiconducting nanotubes, but is non-zero for
metallic ones.
-5 -4 -3 -2 -1 0 1 2 3 4 5
0
0.2
0.4
0.6
0.8
1
D en sity of sta tes (1 0,0 )
E (e V)
n(E ) (s tates /eV )

-1 0 -8 -6 -4 -2 0 2 4 6 8 10
4.5
7
0
0.5
1
1.5
2
2.5
3
3.5
4
D e n s ity o f s tates (9,0)
E (e V)
n(E ) (states/eV )

Figure 1.6 Density of states for a (10,0) semiconducting nanotube and a (9,0) metallic nanotube. Note the nonzero
density of states near zero energy for the metallic nanotube.

8
Kinks in DOS, what is called van Hove singularities, are very important for determining many
solid state properties of carbon nanotubes, such as the spectra observed by scanning tunneling
spectroscopy, optical absorption, and resonant Raman spectroscopy.

1.4 Research directions
Synthesis of aligned nanotubes
Synthesis of highly aligned single-walled carbon nanotubes (SWNTs) with controlled
positions is an important step towards manufacturable ultra dense carbon nanotube integrated
circuits. One of the most promising synthesis methods is chemical vapor deposition (CVD)[8], in
which small catalyst particles with diameters ~ a few nanometers determine the position and
diameter of SWNTs. Significant advance has been made in the preparation of catalyst
nanoparticles, including chemical synthesis and e-beam patterning[9-13] In parallel, aligned
nanotube growth has been achieved on sapphire[14, 15] and quartz substrates[16] using randomly
distributed ferritin or evaporated metal particles. Novel techniques that combine innovative
catalyst preparation and aligned nanotube growth will be essential for further progress in the
nanotube field. In addition, Aligned nanotube growth was previously limited to small pieces of
quartz or sapphire substrates[17, 18], as growing nanotubes over complete 4 inch wafers has been
very difficult due to the quartz wafer breakage during temperature ramping and the difficulty in
uniform growth on complete wafers.
In chapter2 and 3, I discuss the development of a nanosphere lithography (NSL)
technique[19-21] for the preparation of catalyst nanoparticles for the synthesis of aligned single-
walled carbon nanotubes, and the full-wafer scale synthesis of aligned SWNTs arrays on 4 inch
quartz and sapphire wafers, respectively.

9
Applications of aligned nanotubes for nanoelectronics
SWNTs due to their unique structural, mechanical and electronic properties are expected
to meet the emerging technological demands where silicon cannot provide a solution.
In particular, high mobility, inherent small dimension and mechanical flexibility of SWNTs make
them a good candidate for nanoelectronics such as a device for manipulating Terahertz frequency,
flexible and wearable electronics for display and chemical sensor. Dai et al.[4] have demonstrated
the state-of-the-art single tube transistor with ten times higher mobility than the most advanced
Si-based FETs. IBM has also produced 5 stage-ring oscillators based on individual SWNT
showing the potential for replacement of Si devices[22]. Nevertheless, there still exist difficulties
in the integration of multiple nanotubes to get performance comparable with Si devices in terms
of current output and reliability. Thus, synthesis and manipulation of massively aligned single-
walled carbon nanotubes are the desired steps toward manufacturable and scalable devices.
Chapter3 and 4 introduce the wafer-scale nanotube device fabrication such as transistors
and logic circuits, and the demonstration of the flexible nanotube transistors, respectively.

Other applications
Chapter 5 demonstrates Transparent, Conductive and Flexible Carbon Nanotube Films
and Their Application in Organic Light Emitting Diodes, and Chapter 6 discusses high
performance metal oxide nanowire chemical sensors with integrated micromachined hotplates.

10
Chapter1. References
1. Iijima, S., Helical Microtubules of Graphitic Carbon. Nature, 1991. 354(6348): p. 56-58.
2. Dresselhaus, M.S., G. Dresselhaus, and R. Saito, PHYSICS OF CARBON NANOTUBES.
Carbon, 1995. 33(7): p. 883-891.
3. Durkop, T., et al., Extraordinary mobility in semiconducting carbon nanotubes. Nano
Letters, 2004. 4(1): p. 35-39.
4. Javey, A., et al., Ballistic carbon nanotube field-effect transistors. Nature, 2003.
424(6949): p. 654-657.
5. Ruoff, R.S. and D.C. Lorents, MECHANICAL AND THERMAL-PROPERTIES OF
CARBON NANOTUBES. Carbon, 1995. 33(7): p. 925-930.
6. Treacy, M.M.J., T.W. Ebbesen, and J.M. Gibson, Exceptionally high Young's modulus
observed for individual carbon nanotubes. Nature, 1996. 381(6584): p. 678-680.
7. Saito, R., G. Dresselhaus, and M.S. Dresselhaus, Physical Properties of Carbon
Nanotubes. 1998: Imperial college press.
8. Kong, J., et al., Synthesis of individual single-walled carbon nanotubes on patterned
silicon wafers. Nature, 1998. 395(6705): p. 878-881.
9. Cheung, C.L., et al., Diameter-controlled synthesis of carbon nanotubes. Journal of
Physical Chemistry B, 2002. 106(10): p. 2429-2433.
10. Li, Y.M., et al., Growth of single-walled carbon nanotubes from discrete catalytic
nanoparticles of various sizes. Journal of Physical Chemistry B, 2001. 105(46): p. 11424-
11431.
11. Lu, J.Q., et al., High-quality single-walled carbon nanotubes with small diameter,
controlled density, and ordered locations using a polyferrocenylsilane block copolymer
catalyst precursor. Chemistry of Materials, 2005. 17(9): p. 2227-+.
12. Javey, A. and H.J. Dai, Regular arrays of 2 nm metal nanoparticles for deterministic
synthesis of nanomaterials. Journal of the American Chemical Society, 2005. 127(34): p.
11942-11943.
13. An, L., et al., Synthesis of nearly uniform single-walled carbon nanotubes using identical
metal-containing molecular nanoclusters as catalysts. Journal of the American Chemical
Society, 2002. 124(46): p. 13688-13689.
14. Ismach, A., et al., Atomic-step-templated formation of single wall carbon nanotube
patterns. Angewandte Chemie-International Edition, 2004. 43(45): p. 6140-6143.
11
15. Han, S., X.L. Liu, and C.W. Zhou, Template-free directional growth of single-walled
carbon nanotubes on a- and r-plane sapphire. Journal of the American Chemical Society,
2005. 127(15): p. 5294-5295.
16. Kocabas, C., et al., Guided growth of large-scale, horizontally aligned arrays of single-
walled carbon nanotubes and their use in thin-film transistors. Small, 2005. 1(11): p.
1110-1116.
17. Kang, S.J., et al., High-performance electronics using dense, perfectly aligned arrays of
single-walled carbon nanotubes. Nature Nanotechnology, 2007. 2(4): p. 230-236.
18. Liu, X.L., S. Han, and C.W. Zhou, Novel nanotube-on-insulator (NOI) approach toward
single-walled carbon nanotube devices. Nano Letters, 2006. 6(1): p. 34-39.
19. Haynes, C.L., et al., Angle-resolved nanosphere lithography: Manipulation of
nanoparticle size, shape, and interparticle spacing. Journal of Physical Chemistry B,
2002. 106(8): p. 1898-1902.
20. Hulteen, J.C. and R.P. Vanduyne, Nanosphere Lithography - a Materials General
Fabrication Process for Periodic Particle Array Surfaces. Journal of Vacuum Science &
Technology a-Vacuum Surfaces and Films, 1995. 13(3): p. 1553-1558.
21. Deckman, H.W. and J.H. Dunsmuir, Natural Lithography. Applied Physics Letters, 1982.
41(4): p. 377-379.
22. Chen, Z.H., et al., An integrated logic circuit assembled on a single carbon nanotube.
Science, 2006. 311(5768): p. 1735-1735.

12
Chapter 2 Position and direction controlled carbon nanotube synthesis

2.1 Review of existing methods of synthesizing carbon nanotubes
Synthesis of highly aligned single-walled carbon nanotubes (SWNTs)[1] with controlled
positions is an important step towards manufacturable ultra dense carbon nanotube integrated
circuits. One of the most promising synthesis methods is chemical vapor deposition (CVD)[2], in
which small catalyst particles with diameters ~ a few nanometers determine the position and
diameter of SWNTs. Significant advance has been made in the preparation of catalyst
nanoparticles, including chemical synthesis and e-beam patterning[3-7] In parallel, aligned
nanotube growth has been achieved using sapphire[8, 9] and quartz substrates[10] using
randomly distributed ferritin or evaporated metal particles. Novel techniques that combine
innovative catalyst preparation and aligned nanotube growth will be essential for further progress
in the nanotube field.

2.2 Nanolithography for catalyst deposition
Here we report the development of a nanosphere lithography (NSL) technique[11-13] for
the preparation of catalyst nanoparticles for the synthesis of aligned single-walled carbon
nanotubes on quartz. This technique, also known as colloidal crystal lithography for catalyst
nanoparticles formation, uses close-packed monolayer or double layer of nanospheres as a
shadow mask for metal evaporation, where the size and shape of resulting nanoparticles depend
on: 1) the size of template nanospheres, 2) incidence angle of metal evaporation, and 3) thickness
of deposited metal layer. Previously, NSL utilized mostly large nanospheres (e.g., 895 nm in Ref.
14) and was shown to produce regular arrays of particles with uniform size (~ several tens of nm)
that have been successfully implemented to produce arrays of vertical nanowires[14] or multi-
13
walled carbon nanotubes[15]. Packing of smaller nanospheres and synthesis of SWNTs has been
achieved with the assistance of confinement defined by e-beam lithography, which has the
drawback of being a serial, slow and expensive technique. In this paper we demonstrate that
ordered arrays of nanospheres as small as 50 nm, 100 nm and 200 nm can be obtained via a
simple and reliable spin-coat technique, which subsequently led to highly ordered catalyst
nanoparticles with narrow diameter distributions suitable for single-walled nanotube growth. In
addition, we have combined photolithography and nanosphere lithography to gain simultaneous
control over the packing and location of the nanospheres and catalysts. This technique has led to
the successful synthesis of highly aligned and defect-free single-walled carbon nanotubes on
quartz and sapphire, as revealed by scanning electron microscopy (SEM) and Raman
characterization.
Figure 2.1a shows the schematic diagram of nanosphere lithography for aligned nanotube
growth. Quartz or sapphire substrates were first cleaned in piranha (H
2
SO
4
:H
2
O
2
=3:1) followed
by base treatment (H
2
O:NH
4
OH:H
2
O
2
=5:1:1) with sonication for 1 hour to render the surface
hydrophilic[13]. We subsequently optimized the recipe for the deposition and packing of
polystyrene spheres by comparing different deposition techniques (spin coat v.s. drop and drying),
and using polystyrene from different vendors, of different sizes, and with different concentrations.
The optimum packing has been achieved by spin coat of 200 nm, 100 nm and 50 nm polystyrene
nanospheres (from Duke Scientific Co. and Alfa Aesar) at concentrations of 2%, 2% and 1% and
at spin rates of 4000, 4000 and 5000 rpm, respectively. This process resulted in self-assemble of
nanospheres into a close-packed monolayer or bilayer structures. Figure 1b shows the photograph
of a three-inch quartz wafer with spin-coated 200 nm polystyrene nanospheres. Figure 2.1c-e
display the SEM images of highly ordered monolayers of 50 nm, 100 nm, and 200 nm,
respectively, with domain size up to several µm
2
. Figure 2.1e inset shows the SEM image of a
200 nm polystyrene bilayer structure. We note that our work represents significant extension of
nanosphere lithography toward the deep submicron regime, as most previous work dealt with
rather large nanospheres around several hundred nanometers[14, 15].

We subsequently deposited 5-10 Å of catalyst metal films made of Fe, Ni or Co onto the
substrates through the nanosphere shadow mask at either normal incidence or at controlled angles
with respect to the substrate surface for fine-tuning of the catalyst size. The substrates coated with
the catalyst

Figure 2.1 a) Schematic diagram of nanosphere lithography for aligned nanotube growth. b) Photograph of a three-inch
quartz wafer with spin-coated polystyrene nanospheres. c-e) SEM images of ordered monolayers of 50 nm, 100 nm and
200 nm polystyrene nanospheres, respectively. e) inset: SEM image of an ordered bilayer of 200 nm nanospheres (The
bottom layer is visible through the missing nanosphere in the top layer).

metal films were then soaked into dichloremethane solution and sonicated for 3-5 min to
remove nanospheres, leaving metal films deposited through the openings of the NSL
mask on top of the substrate (Figure 2.2a). After annealing the substrates at 700 ~ 900°C
14
in H
2
ambient for 10 min, the remaining metal films aggregated into spherical catalyst
particles, as shown in Figure 2.2b.

Figure 2.2 a) and b) SEM images of catalyst arrays prepared using nanosphere lithography before and after annealing.
c) and d) AFM images of catalyst arrays prepared with 3 Å and 5 Å Fe films deposited, respectively. Inset: histograms
of the catalyst particle size.

By assuming all volume of the metal film deposited through a single opening aggregates
into a spherical particle, the diameter of these round catalyst particles can be estimated as D =
2(3 ×S( α, φ)× a2h/16 π)1/3, where h is the thickness of metal film, a is the diameter of nanospheres,
and S( α, φ) is a geometrical factor depending on the angle of metal deposition[11]. Detailed
calculation of the catalyst particle size can be found in the online supporting information (Figure
2.3). Geometrical factor S( α, φ) equals to the area of opening between 3 adjacent spheres for a
closely packed monolayer (or 6 for a bilayer) of unit radius as projected onto a plane
perpendicular to the deposition direction, where α is deposition angle, which is the angle between
the deposition direction and normal of the substrate plane, and φ is azimuthal angle, which is the
angle between the projection of deposition direction to the substrate plane and orientation of the
closely packed lattice of spheres. Numerical integration is done using Monte-Carlo method. We
15
note that this method offers many means to fine tune the catalyst size, as the catalyst size can be
precisely controlled by tuning the nanosphere size, the deposited metal film thickness, and the
deposition angle (Figure 2.4). Based on the geometrical factor S( α, φ), we have calculated the
catalyst particle diameter for relevant sizes of nanospheres.

Figure 2.3 Calculated geometrical factor S( α, φ) for a monolayer (a) and (b) for a bilayer of packed nanospheres.

Figure 2.4 shows the expected diameter of the annealed catalysts prepared using 6
different nanosphere structures (monolayers and bilayers of 200 nm, 100 nm and 50 nm
nanospheres) as a function of the deposition angle ( α) with 5 Å metal film deposited, where the
azimuthal angle ( φ) is fixed at zero degree. For nanosphere bilayers, as the deposition angle ( α)
16
approaches 35 °, the catalyst size goes to zero, while the catalyst size for nanosphere monolayers
goes to zero around 56 ° of deposition angle.

Figure 2.4 Calculated catalyst nanoparticle diameter v.s. the metal deposition angle for monolayers and bilayers of 200
nm, 100 nm and 50 nm nanospheres.

Figure 2.2 c-d display the AFM images of catalyst particles prepared using monolayers of
100 nm nanospheres with 3 Å and 5 Å Fe films deposited, respectively.
7
17

Figure 2.5 (a) AFM image of catalyst arrays prepared using nanosphere lithography with a packed bilayer of 100 nm
nanospheres and with 20 Å Fe deposited. (b) Histogram of the diameter of catalyst nanoparticles.

6
5
4
3
2
1
0
T he num ber o f catalysts
10 8 6 4 2 0
Diameter of catalyst(nm)
(b)
(a)
6.44±1.35nm
Histograms of the catalyst size determined by AFM are displayed in Figure 2c-d insets, revealing
distributions of 2.77 ±0.67 nm and 4 ±0.68 nm, respectively.
We have also prepared catalyst nanoparticles using packed bilayer nanosphere arrays,
showing three-fold triangular arrays (Figure 2.5). The catalyst arrays were prepared using
nanosphere lithography with a packed bilayer of 100 nm nanospheres, followed by 20 Å Fe
deposition and annealing at 900 °C for 10 min. The catalyst array exhibits a triangular lattice as
shown in Figure 2.5a. The Gaussian fit to the histogram gives a diameter distribution of 6.44 ±
1.35 nm (Figure 2.5b). Our results clearly reveal the potential of using NSL to prepare highly
ordered array of catalyst nanoparticles with controlled diameters.

2.3 Position and direction controlled carbon nanotube synthesis

Figure 2.6 a) Photograph of a quartz substrate with polystyrene nanospheres packed in stripe-shaped trenches patterned
in photoresist. b) SEM image of an ordered array of nanospheres inside the trench. c) SEM image of aligned nanotubes
grown from the catalyst prepared using NSL. d) Polarization-dependent Raman spectrum of a nanotube.
18

We have further combined nanosphere lithography, photolithography, and growth on
quartz / sapphire substrates for simultaneous control of the nanotube orientation and position.
Figure 2.6a shows a quartz substrate spin-coated with 200 nm nanospheres packed in stripe-
shaped trenches in photoresist patterned by photolithography. Nearly perfect packing of the
nanospheres with large domains ~ 5 µm × 5 µm was observed, as shown in Figure 2.6b, as a
result of the confinement of the photoresist trenches. Following the catalyst deposition and
removal of photoresist and nanospheres, we used chemical vapor deposition for the growth of
SWNTs at 900 °C for 10 min under gas flows of CH4, C2H4 and H2 controlled at 2000, 17 and
600 sccm, respectively. As shown in Figure 2.6c, very well aligned nanotubes arrays were
produced from the catalysts prepared using NSL, with lengths up to 100-200 µm and diameters of
1.8 ± 1.0 nm. We note that the yield of nanotubes still needs to be improved. Figure 2.6d shows
the Raman spectrum of a typical SWNT with the excitation laser polarization direction tuned to
various angles relative to the nanotube array orientation. One can clearly see a monotonic
decrease in Raman response when the laser polarization was adjusted from parallel to orthogonal
to the nanotube array, indicating the well aligned nature of the nanotubes.

19
Figure 2.7 Raman spectrum of a nanotube.

2500
2000
1500
1000
500
0
Intensity
1700 1600 1500 1400 1300 1200
Wave number(cm
-1
)
D-band
(a)
2500
2000
1500
1000
500
0
Intensity
(b)
450 400 350 300 250 200 150
1.41nm nanotube
100
Wave number(cm
-1
)
20
In addition, negligible D-band was observed in the Raman spectrum (Figure 2.7),
confirming very clean and defect-free nanotubes were grown. Figure 2.7a shows a representative
Raman spectrum of nanotube exhibiting negligible D-band, confirming very clean and defect-free
nanotubes were grown. Figure 2.7b displays the RBM mode of a typical carbon nanotube
prepared using nanosphere lithography. A single RBM peak at 175 cm-1 confirms that this
nanotube is single-walled. Other peaks in Figure 2.7b are from the quartz substrate.
In summary, we have extended nanolithography into deep submicron regime to obtain
packing of 50 nm, 100 nm and 200 nm polystyrene nanospheres, which were then successfully
employed to produce highly-ordered catalyst nanoparticles with narrow size distributions. We
have further combined NSL and photolithography to grow highly aligned single-walled carbon
nanotubes atop quartz and sapphire substrates. This method has great potential to produce carbon
nanotube arrays with simultaneous control over the nanotube orientation, position, density,
diameter and even chirality, which may work as building blocks for future nanoelectronics and
ultra high-speed electronics.

21
Chapter2. References
1. Iijima, S., Helical Microtubules of Graphitic Carbon. Nature, 1991. 354(6348): p. 56-58.
2. Kong, J., et al., Synthesis of individual single-walled carbon nanotubes on patterned
silicon wafers. Nature, 1998. 395(6705): p. 878-881.
3. Cheung, C.L., et al., Diameter-controlled synthesis of carbon nanotubes. Journal of
Physical Chemistry B, 2002. 106(10): p. 2429-2433.
4. Li, Y.M., et al., Growth of single-walled carbon nanotubes from discrete catalytic
nanoparticles of various sizes. Journal of Physical Chemistry B, 2001. 105(46): p. 11424-
11431.
5. Lu, J.Q., et al., High-quality single-walled carbon nanotubes with small diameter,
controlled density, and ordered locations using a polyferrocenylsilane block copolymer
catalyst precursor. Chemistry of Materials, 2005. 17(9): p. 2227-+.
6. Javey, A. and H.J. Dai, Regular arrays of 2 nm metal nanoparticles for deterministic
synthesis of nanomaterials. Journal of the American Chemical Society, 2005. 127(34): p.
11942-11943.
7. An, L., et al., Synthesis of nearly uniform single-walled carbon nanotubes using identical
metal-containing molecular nanoclusters as catalysts. Journal of the American Chemical
Society, 2002. 124(46): p. 13688-13689.
8. Ismach, A., et al., Atomic-step-templated formation of single wall carbon nanotube
patterns. Angewandte Chemie-International Edition, 2004. 43(45): p. 6140-6143.
9. Han, S., X.L. Liu, and C.W. Zhou, Template-free directional growth of single-walled
carbon nanotubes on a- and r-plane sapphire. Journal of the American Chemical Society,
2005. 127(15): p. 5294-5295.
10. Kocabas, C., et al., Guided growth of large-scale, horizontally aligned arrays of single-
walled carbon nanotubes and their use in thin-film transistors. Small, 2005. 1(11): p.
1110-1116.
11. Haynes, C.L., et al., Angle-resolved nanosphere lithography: Manipulation of
nanoparticle size, shape, and interparticle spacing. Journal of Physical Chemistry B,
2002. 106(8): p. 1898-1902.
12. Hulteen, J.C. and R.P. Vanduyne, Nanosphere Lithography - a Materials General
Fabrication Process for Periodic Particle Array Surfaces. Journal of Vacuum Science &
Technology a-Vacuum Surfaces and Films, 1995. 13(3): p. 1553-1558.
13. Deckman, H.W. and J.H. Dunsmuir, Natural Lithography. Applied Physics Letters, 1982.
41(4): p. 377-379.

22
14. Wang, X.D., C.J. Summers, and Z.L. Wang, Large-scale hexagonal-patterned growth of
aligned ZnO nanorods for nano-optoelectronics and nanosensor arrays. Nano Letters,
2004. 4(3): p. 423-426.
15. Kempa, K., et al., Photonic crystals based on periodic arrays of aligned carbon
nanotubes. Nano Letters, 2003. 3(1): p. 13-18.

23
Chapter 3 Wafer-scale integrated aligned carbon nanotube circuits

3.1 Wafer-scale aligned carbon nanotube synthesis
Single-walled carbon nanotubes (SWNTs) are expected to offer much better performance
for electronics than traditional silicon due to their high carrier mobility and current-carrying
capacity. Nanotubes can work as ballistic[1] and high mobility[2] transistors, and integrated logic
circuits such as inverters and ring-oscillators[3-7] have been constructed using individual
nanotubes. Recently, significant advance has been made using randomly grown nanotube
networks for flexible devices and circuits[8]; however, the stripe-patterning used to remove
heterogeneous percolative transport through metallic nanotube networks cannot be easily scaled
to submicron regime, and only PMOS transistors were demonstrated for the reported circuits. In
parallel, aligned nanotubes, with potentially significant advantages over randomly grown
nanotubes in terms of manipulation and integration of nanotubes for device applications, have
been grown on either sapphire or quartz substrates from several research groups[9-12] ,or
deposited on solid or flexible substrates by dielectrophoresis method for submicron RF
devices[13, 14]. Based on massively aligned SWNTs grown on sapphire, we have further
reported a high-yield, registration-free nanotube-on-insulator approach to fabricate nanotube
devices[15], in a way analogous to the silicon-on-insulator process adopted by the semiconductor
industry. The aligned nanotube devices such as transistors[16], RF devices[17], and high
frequency transistor oscillator[18] have also been made based on aligned nanotubes on quartz
with good uniformity over chip scale and minimized parasitic capacitance. However, previous
studies[15-18] on aligned nanotube devices usually share the following drawbacks: 1) small
sample size which prevents wafer-scale fabrication and integration, 2) micron-scale channel
length that limits the transistor performance, and 3) a lack of controlled doping that prevented
24
truly integrated circuits with p-type and n-type transistors on one chip. To demonstrate truly
integrated nanotube circuits and wafer-scale fabrication, technological components such as wafer-
scale synthesis and transfer of aligned nanotubes, and integrated submicron-scale device
fabrication and tuning, are highly desired for the high-performance integrated nanotube circuits.
In addition, defect-tolerant circuit design would also be an essential feature for such integrated
nanotube circuits.
Here, we report our recent advance on full wafer-scale processing of massively aligned
carbon nanotube arrays for high-performance submicron channel transistors and integrated
nanotube circuits, including the following essential components. 1) The massive highly aligned
nanotubes were successfully grown on 4 inch quartz and sapphire wafers via meticulous
temperature control, and then transferred onto Si/SiO
2
wafers using a facile transfer printing
method. 2) Wafer-scale device fabrication was performed on 4 inch Si/SiO
2
wafer to yield
submicron channel transistors and circuits with high on-current density ~ 20 μA/ μm and good
on/off ratios. 3) Chemical doping methods [19-23] were successfully demonstrated to get CMOS
inverters with a gain ~5. 4) Defect-tolerant circuit design for NAND and NOR was proposed and
demonstrated to guarantee the correct operation of logic circuit, regardless of the presence of mis-
aligned or mis-positioned nanotubes. Our wafer-scale nanotube-on-insulator processing using
multiple aligned nanotubes shows significant advantage over conventional processes based on
individual nanotubes with respect to current output and device uniformity, and suggests a
practical and realistic approach for integrated nanotube circuit applications.
Aligned nanotube growth was previously limited to small pieces of quartz or sapphire
substrates[15, 16], as growing nanotubes over complete 4 inch wafers has been very difficult due
to the quartz wafer breakage during temperature ramping and the difficulty in uniform growth on
complete wafers. Here, we successfully synthesized aligned SWNTs arrays (Figure 3.1 and 3.2a)
on 4 inch quartz and sapphire wafers by overcoming the above-mentioned technical difficulties.
First, both quartz and sapphire wafers were annealed to improve the alignment of nanotubes at
900 °C and 1100 °C for 1.5 hrs in air, respectively.

Figure 3.1 Photograph of a 4 inch quartz wafer with aligned nanotubes and patterned electrodes. Inset: SEM images of
aligned nanotubes between electrodes at different locations of the wafer.

In particular, the thermally robust a-plane sapphire wafer can be annealed at 1100 °C at
high ramping rate (45 °C/min) as shown in Figure 3.2c, while the 4 inch quartz wafer required
meticulous temperature control (extremely slow ramping rate < 1 °C/min) to avoid wafer
breakage due to the phase transformation of quartz from alpha ( α) to beta ( β) around 573 °C, as
shown in Figure 3.2d. In addition, we used the same total gas flow rate for both the ramping up
step (3000 sccm Ar and 600 sccm H
2
) and the growth step (3000 sccm CH
4
and 600 sccm H
2
) to
minimize the temperature perturbation. The uniform temperature on entire wafer is also an
essential requirement for the uniform wafer-scale growth of aligned nanotubes on both quartz and
25
sapphire wafers. Therefore, a 9 feet-long growth furnace with three-zone temperature
controller(Figure 3.2b) was used for this study.

Figure 3.2 (a) Photograph of 4 inch sapphire wafer with aligned nanotubes. (b) Schematic diagram of 9 feet-long
furnace for wafer-scale nanotube growth. (c) and (d) SEM images of aligned nanotubes and Temperature flow charts
for the annealing and the nanotube growth on sapphire and quartz wafer, respectively.

3.2 Wafer-scale aligned nanotube transfer
After growth (Figure 3.3a), we used a facile transfer method to transfer the aligned
nanotubes from 4 inch quartz or sapphire wafers to 4 inch Si/SiO
2
wafers as following. A 100 nm
thick gold film was first deposited onto the aligned SWNTs on the original substrate to ensure
conformal contact between nanotubes and the gold film (Figure 3.3b). To transfer SWNTs onto
the targeting substrate, our key innovation is the use of Revalpha thermal tape (from Nitto Denko),
which has an interesting temperature-dependent adhesive property: it is highly adhesive at room
temperature, but loses its adhesion at a moderate temperature of 120 °C. This tape was pressed
26
against the original substrate with nanotubes covered by the gold film, and then peeled off
together with the gold film and nanotubes (Figure 3.3c). The nanotube / gold film / thermal tape
trilayer structure was pressed against the target substrate, and the tape was then released by
simply heating to 120 °C (Figure 3.3d). The gold film was subsequently removed using gold
etchant, thus leaving a nice array of massively aligned SWNTs on the target substrate (Figure
3.3e). SEM images of transferred nanotubes on Si substrate with 50 nm thickness of SiO
2
are
shown in inset of Figure 3.3e. The device fabrication based on transferred nanotubes on 4 inch
Si/SiO
2
wafer (Figure 3.3f) was obtained by standard silicon CMOS technology such as
projection photolithography using a stepper with 0.5 μm resolution for submicron device
patterning, metal deposition for electrodes, and high k dielectric (HfO
2
or Al
2
O
3
) deposition for
gate dielectric.

Figure 3.3 Wafer-scale aligned nanotube synthesis, transfer, and fabrication. (a) Schematic diagram and photograph of
full wafer synthesis of aligned nanotubes on a 4 in. quartz wafer. Inset shows SEM image of aligned nanotubes. (b-f)
Schematic diagrams and photographs showing the transfer procedure, i.e., gold film deposition (b), peeling off the gold
film with nanotubes (c), transfer of the gold film with nanotubes onto a Si/SiO
2
substrate (d), etching away the
gold film (e), and device fabrication on the transferred nanotube arrays (f).

27
Figure 3.4 shows the photo images of nanotube devices built on a 4 inch Si/SiO
2
wafer,
and a typical chip is consisted of 5 different types of devices, including back-gated transistors,
top-gated transistors, CMOS inverters, and CMOS NOR and NAND logic gates.

Figure 3.4 Photo images of nanotube devices and circuits built on a 4 in.Si/SiO
2
wafer: 1, back-gated transistor; 2, top-
gated transistor; 3, CMOS inverter; 4, NOR logic gate; 5, NAND logic gate.

3.3 Integrated nanotube circuits
We first characterized the electrical properties of nanotube transistors as basic
components for nanotube circuits. Compared with previous work[15, 16] with micron or tens of
micron channel length, we have pushed the channel length to submicron. Figure 3.5 shows a
schematic diagram, SEM image, and electrical characteristics of back-gated nanotube devices.
Based on the transferred nanotubes on Si with 50 nm SiO
2
, 5 Å Ti and 70 nm Pd were deposited
as Source/Drain electrodes (Figure 3.5a), followed by the removal of nanotubes outside the active
channel with O
2
plasma. Such devices were made with channel length (L) of 0.5, 0.75, 1, 2, 5, 10,
20 μm and channel width (W) of 2, 5, 10, 20, 50, 100 μm. The SEM image in Figure 3.5b shows
28
a typical submicron channel device with 2-3 tubes/ μm. Figure 3.5c exhibits the current-gate
voltage (I
ds
-V
g
) characteristics of the transistors at V
ds
= 1 V with W = 100 μm and various
channel lengths, showing on-currents at V
g
= -10 V varying from several tens μA to 1.8 mA,
reversely proportional to the channel length. The normalized on and off- current densities (I
ds
/W )
are further deduced from the same devices in Figure 3.5c, and the transconductances (gm) are
also calculated from the linear proportion of the transfer curves, as shown in Figure 3.5d. The
highest on-current density in a transistor with W = 100 μm and L = 0.5 μm is up to 20 μA/ μm,
and gm is close to 100 μS. This on-current density is the highest achieved so far for aligned
nanotube transistors, as a result of the submicron channel length we used. The performance of
these devices can be improved even further with higher-density nanotubes.
In addition, the effective mobility ( μ) of the device was calculated by applying the
following equation[16].
g
d
w d
dV
dI
W C V
L
⋅ = μ

where L is the channel length, and W is the channel width. Cw is the specific capacitance per unit
area of the aligned nanotube channel calculated as follow,
⎥
⎦
⎤
⎢
⎣
⎡
⎥
⎦
⎤
⎢
⎣
⎡
⋅ +
=
−
RD
tD
C
D
C
s
Q
w
π
π
ε πε
2 sinh(
log
2
1
0
1

where D is the density of nanotubes, CQ is the quantum capacitance of nanotubes, t is the
thickness of the dielectric layer, R is the radius of nanotubes, and εs is the dielectric constant at
the interface where the nanotubes are placed. For our case, a device with 50 μm channel length
was chosen to minimize the effects of contact, and device mobility was estimated using the
maximum gm which was extracted from I-Vg curves as shown in Figure 3.6. In addition, D = 2
tubes/ μm, t = 50 nm, R = 0.6 nm (measured by AFM), and εs was estimated to be 4.
29

Figure 3.5 Characteristics of back-gated transistors down to submicron channel length. a) Schematic diagram of a
back-gated transistor built on transferred nanotubes. b) SEM image of a transistor with submicron channel length. c)
Transfer (Ids-Vg) characteristics of transistors with different L= 0.5, 0.75, 1, 2, 5, 10, and 20 μm, and W = 100 μm. d)
Normalized on and off- current densities and transconductance (gm) derived from (c). e) – g) Electrical breakdown
study of the transistors; Ids-Vg curves for a typical transistor after consecutive electrical breakdown (e), Ids-Vg curves
and Ids-Vds curves of the transistor in (e) after three rounds of electrical breakdown(f), and Statistics of devices before
and after electrical breakdown (g). h) Ids–Vg curves of two representative devices, with one (black) and two (red) steps
of transfer, respectively. Inset illustrates the multiple transfer process.

30
The value of CQ (=4.0 ×10
-10
F/m) was taken from a previous report 2. The effected device
mobility was calculated to be 2685 cm
2
V
-1
s
-1
. By assuming one third of the nanotubes are metallic,
one can further derive a nanotube mobility of 3571 cm
2
V
-1
s
-1
.

80
60
40
20
I
ds
( μΑ )
-4 -2 0 2 4
V
g
(V)
50
40
30
20
10
0
g
m
( μS)
I
ds
g
m

Figure 3.6 I-Vg and gm curve from a device with 50 μm channel length.
To improve the on/off ratio (Ion/Ioff), controlled electrical breakdown[24] was used to
remove metallic and high-leakage semiconducting nanotubes. Specifically, we developed an
automated electrical breakdown process by setting target on/off ratio and on-current, and then
using computer control to perform multiple steps of breakdown until the target values were
reached. This process, when combined with an automatic probe station, can make electrical
breakdown fairly practical for wafer-scale processing. The backgate was set to 15 V to turn off
the desired semiconducting nanotubes, while the source/drain voltage (Vds ) was swept from 0 to
-35 V to electrically stress and break the undesired tubes. The Ion/Ioff of a transistor with W =
100 μm and L = 0.75 μm in Figure 3.5e significantly increased from ~2 to 10
3
with multiple steps
of electrical breakdown, accompanied by a moderate degradation of the on current. After
electrical breakdown, Figure 3.5f and inset show the Ids – Vg curves at different Vds from -0.2 to
-1 V and Ids-Vds curves at different Vg from – 8 to 8 V. Figure 2g is a statistical study of about
50 devices from altogether 10 chips with L = 0.75 μm and various W before and after electrical
31
32
breakdown, where the on-state current density is plotted v.s. the on/off ratio. Ion is measured at
Vds = 1 V and Vg = -10 V, and Ioff is measured at Vds = 1 V and Vg = 10 V. Before breakdown,
the devices exhibited on/off ratios in the range of 1 to 10, due to the presence of metallic
nanotubes. In contrast, after electrical breakdown, the on/off ratios underwent significant
improvement to the range of 10
2
to 10
5
, which can be used as building blocks for the following
nanotube circuits.
In addition to the tuning of the on/off ratio using electrical breakdown, we can adjust the
transistor conductance by performing multiple steps of nanotube transfer to increase the tube
density. Figure 3.5h shows the Ids – Vg curves of two representative devices, with one and two
steps of transfer, respectively. Devices fabricated in the double transfer region showed ~2.2 times
more current per unit width in Figure 3.5h. Multiple nanotube transfer is a novel technique to
compensate the decreased current after electrical breakdown, and additional transfers can be
performed to achieve even higher current densities.
Besides the back-gated devices, top-gated devices were fabricated by defining top-gate
electrodes on back-gated devices. Compared with the common back-gate devices, the top-gate
structure has an intrinsic benefit such as individual control of each transistor in a nanotube circuit.
In order to make the top-gate electrodes, we first formed the pattern using photolithography,
deposited 50 nm Al
2
O
3
using atomic layer deposition(ALD) as top-gate dielectric, and then
deposited 5 nm Ti/45 nm Pd as the top-gate electrodes, followed by lift-off process. Figure 3.7a
illustrates a schematic diagram of a top-gated device, where top gate partially covers the active
channel so that nanotubes can be exposed to n-type dopants such as potassium. In Figure 3.7b,
one can clearly see nanotubes which bridge between S/D electrodes and are partially covered by
Al
2
O
3
and top-gate. Figure 3.7c and d are the typical transfer characteristics (Ids – Vg curves) and
output characteristics (Ids – Vds curves) for a transistor with W = 25 μm, L = 3 μm, and top-gate
length = 1 μm after proper electrical breakdown.

Figure 3.7 Top-gated transistors for doping and truly integrated CMOS inverters. a), b) Schematic diagram and SEM
image of a top-gated transistor, respectively. c) Ids-Vg curves of the transistor with L= 3 μm and W = 25 μm at
different Vds = 0.1 to 1.1 V in step of 0.1 V. Inset: Ids-Vg curve in logarithm scale. d) Ids-Vds curves at different Vg
= -20, -15, -10, 10, 15, and 20 V for the same device in (c). e) Ids-Vg curves of the top-gated transistor before (red) and
after (black) K doping. f) Voltage transfer characteristic (VTC) of a CMOS inverter with selective K doping. Inset:
schematic diagram (left) and photograph (right) of the circuit. g) Ids-Vg curves of a dual-gated transistor before (red,
back gate at -20 V) and after (black, back gate at 20 V) electrostatic doping. h) Ids-Vg curves at different Vbg = -20 to
20 V for the same device in (e), showing a significant shift of threshold voltage and enhancement of n-type conduction.
33
34
The Ids – Vds curves appear to be very linear, indicating that ohmic contacts are formed
between the electrodes and the nanotubes. The on-current is measured to be 20 μA, corresponding
to a current density of 0.8 μA/ μm, and the on/off ratio exceeds 10
4
. We used such devices in the
following doping study.
One of the most important characteristics of CMOS circuits is low static power
consumption. Significant power is only drawn when the CMOS circuits are switching between on
and off states. Unlike doping in silicon CMOS processes, nanotubes can not be easily doped via
ion implantation. The ability to obtain both p- and n-type nanotube FETs, therefore, is important
to construct complementary electronics. A p-type nanotube device can be doped electrostatically,
substitutionally, or via charge transfer to convert it into an n-type one. Four different methods,
with potassium[19, 21] and electrostatic[22] doping for top-gated devices, and polyethilenimine
(PEI)[23] and hydrazine (N
2
H
4
)[20] for back-gated ones, have been studied here to produce n-
type transistors and to evaluate the most practical way for integrated circuits. In order to dope
nanotube devices with potassium, we first spin-coated polymethylmethacrylate (PMMA) as a
capping layer for p-type transistor, and then opened up the window for other devices which can
be altered into n-type after doping, as shown in inset of Figure 3f. This device was loaded into
high vacuum (~ 10
-5
torr), followed by the evaporation of potassium. Figure 3.7e shows the Ids-
Vg characteristics of the top-gated transistor before and after potassium doping. This doping
produced n-type transistor by shifting the Fermi level of nanotubes to the conduction band, and
the conductance of the transistor increased at positive gate voltage. Based on the transferred
nanotube devices, we performed four different types of doping methods including potassium,
electrostatic, polyethilenimine (PEI), and hydrazine (N
2
H
4
), in order to get n-type devices for
CMOS circuits. The following shows in-depth studies of PEI and N
2
H
4
doping with relative
advantages and disadvantages discussed. Figure 3.8a and b show I-Vg curves of a back-gated
device before and after PEI doping, respectively. One can clearly see that the on/off ratio
significantly decreased from 10
5
to 10 after PEI doping presumable due to leakage through PEI.
Such n-type devices with poor on/offs ratio cannot be applicable to CMOS circuits, even though
PEI doping is a simple process compared with other doping methods. N2H4, known as a strong
base, was also studied here as an n-type dopant. SEM image in Figure 3.8c clearly shows the
ALD Al2O3 gate-dielectric layer under a gate electrode (50 nm in thickness) before the sample
was soaked in N2H4. However, we observed that the Al
2
O
3
dielectric layer was completely
etched away after the sample was soaked in N
2
H
4
for 30 minute, as shown in Figure 3.8d.

Figure 3.8 a), b) I-V
g
curves of a back-gated device before and after PEI doping, respectively. c), d) SEM images of
the top-gated devices before and after soaked in N
2
H
4
, respectively. e), f) I-Vg curves before and after N
2
H
4
doping on
the back-gated devices without and with PMMA passivation, respectively.

35
36
Furthermore, we noticed that N
2
H
4
can diffuse through even a relatively thick layer of
photoresist such as PMMA, leading to difficulty in passivation of p-type devices. In Figure 3.8e
and f, p-type devices were converted into n-type ones, regardless of whether PMMA passivation
was used. As a result, N
2
H
4
doping cannot be a feasible doping method for the integrated CMOS
circuits.
The potassium doping showed clear advantage over other doping methods such as PEI
showing low on-off ratio, and N
2
H
4
with toxicity and difficulty in integration. Armed with
potassium doping, we have constructed a truly integrated CMOS aligned nanotube inverter, i.e.,
with the p-type and n-type transistors residing on one chip and located side by side. Figure 3.7f
includes the voltage transfer characteristics (VTC), the schematic diagram, and the photo image
of the CMOS inverter. Our inverter was operated with a VDD = 2 V and an input voltage range
from 0 to 2.5 V, and the gain deduced from VTC data was 5, which can be high enough to drive a
more complicated logic circuit such as a ring oscillator.
In addition to potassium doping, electrostatic doping has been studied on top-gated
transistors with Si common back-gate. We utilized electrostatic doping effects[22] in the dual-
gate nanotube FET to obtain the polarity control (p or n) and to tune the threshold voltage of FET.
Figure 3.7g exhibits the current-gate voltage (I-Vg) characteristics of the dual-gated transistor,
and clearly shows p- and n-type properties at back-gate voltage (Vg) = -20 V and 20 V,
respectively, which can be understood as following. For sufficiently negative (or positive) back-
gate voltage, the Schottky barriers are thinned enough to allow for hole (or electron) tunnelling
from the metal contact into the nanotube, and thus the nanotube channel can be electrostatically
doped into p-type or n-type. Therefore, varying the top gate voltage can switch on and off the
transistor with assist of back-gate voltage, which determines the type of majority carrier and the
device on-current. In our device, the n-type conduction is slightly lower than the p-type
conduction, which is attributed to asymmetrical Schottky barrier heights for holes and electrons,
37
and environmental doping effect from O
2
and moisture. We also measured the current v.s the top-
gate voltage (I-Vg) at different back-gate Vg from -20 to 20 V, and a significant shift of threshold
voltage and enhancement of n-type conduction were observed from 0 to -6 V, as shown in Figure
3.7h. Compared with other doping methods such as potassium and hydrazine, which are not
stable in air, the electrostatic doping is stable and tunable, but requires sophisticated device
structure and circuit design.
Based on top-gated aligned nanotube transistors, more sophisticated PMOS circuits have
also been demonstrated. It is, however, inevitable that there are misaligned or misoriented
nanotubes in these devices, which can result in incorrect logic behaviour. Therefore, an
innovative circuit design such as defect-tolerate structure is required to guarantee the correct logic
behaviour. We hereby report defect-immune circuit layouts for PMOS NOR and NAND circuits.
Figure 3.9a-c show a defect-influence layout, and two defect-tolerate layouts with transistors
connected in parallel, respectively. For Figure 3.9a, misaligned nanotubes outside the gates are
not under the control of either gate and therefore may impair the logic operation. In Figure 3.9b,
the nanotubes lying between gate A and B are removed using oxygen plasma etching, and thus
this design is immune to such misaligned nanotubes. Furthermore, Figure 3.9c represents an even
better design, where two transistors controlled by gate A and B are connected in parallel and
utilize the same bunch of aligned nanotubes. This design enables virtually identical device
performance between two parallel transistors, as shown in Figure 3.10. Ideally the pull-up branch
of a PMOS NAND would require transistors A and B to be rather symmetrical, i.e., to deliver
similar transistor characteristics. We proposed two kinds of defect-tolerant designs for PMOS
logic circuits in the main text. However, one showed much better performance than the other
when the nanotube distribution was not uniform. Therefore, we performed in-depth study about
the transfer characteristics of pull-up network for two designs. Figure 3.10 displays the current
through two parallel transistors with Vdd = 1 V, Vout = 0 V, VA swept from -5 V to 5 V, and VB
set at 5 V, 0 V, and -5 V for different curves. Of particular interest is the current values at point I
and II, which correspond to the currents at (VA, VB) = (-5 V, 5 V) and (5 V, -5 V), respectively.
For symmetrical transistors, these two current values should be more or less equivalent.

Figure 3.9 PMOS NOR and NAND gates with top-gated transistors. a)-c) Schematic diagrams of a defect-influence
layout and two defect-tolerate layouts with two transistor in parallel, respectively. d), e) Output characteristics of
PMOS NOR and NAND, respectively. Inset: SEM image of integrated pull-up networks and schematic diagram of
PMOS circuits. f), g) Output characteristics of PMOS NAND with pull-up network (b) and (c), respectively, where the
nanotube density was not uniform in the circuit, as depicted in schematic diagram in inset.

38
Based on the NAND design in schematic of Figure 3.10a, such design showed significant
difference between the point Ι and II. This is attributed to the nonuniform nanotube density,
which was further proved by the SEM image in Figure 3.10a. In contrast, for the NAND design in
Figure 3.10b, two transistors, which were built on the same nanotube arrays in the SEM image,
showed equivalent performance, as shown in the I-Vg curves.

Figure 3.10 (a), (b) I-VA curves at different VB = 5, 0, -5 V from the two different types of NAND pull-up networks,
as shown in SEM images and schematic diagrams.

We fabricated PMOS circuits using the defect-immune layout. Figure 3.9d and 3.9e
include SEM images of the integrated pull-up networks, the schematic diagrams, and the output
characteristics for PMOS NOR and NAND, respectively. 20M Ω resistive load was chosen so that
it was between the on-state resistance and the off-state resistance of the transistors. The NAND
and NOR circuits were both operated with a VDD of 1V. 10V and -10V applying on gate A and
B were treated as logic “1” and “0”, respectively. For the NAND, the output was “1” when either
one of the two inputs was “0”, while for the NOR, the output was “0” when either one of the two
inputs was “1”. These output characteristics confirm that our circuits realized the logic function
correctly. However, the design in Figure 4b may suffer from the problem of having nonuniform
39
40
nanotube density and consequently different characteristics for gate A and B. Figure 4f shows the
data and schematic diagram of a PMOS NAND gate, where the nanotube density happened to be
nonuniform. One can clearly see that the outputs were asymmetric between the point Ι and II, and
also the transfer characteristics for gate A and B showed a significant difference in terms of on-
current (Figure 3.10). The low output at the point II was attributed to the relatively large DC
current leakage through the pull-down resistor, which was comparable to the on-current of
transistor controlled by gate A. In contrast, for the NAND with design shown in Figure 3.9c and
3.9g inset, the transistor transfer characteristics (Figure 3.10) and the outputs of circuits were
more symmetric than the ones in Figure 3.9f. This confirms that the NAND design in Figure 3.9c
performed the logic function correctly even with nonuniform nanotube density and misaligned
nanotubes.
While PMOS logic is easy to design and manufacture, it has several shortcomings as well.
The worst problem is that current flows through the pull-down resistor when the pull-up network
is active, as discussed above. This leads to static power dissipation even when the circuit sits idle.
In order to overcome such problem, CMOS nanotube circuits have been studied here using the
defect-tolerant design with individual back-gates for efficient chemical doping. Specifically, the
individual back-gated devices have relative advantages over the top-gated ones, such as easy
chemical doping and electrical breakdown owing to the fully exposed device structure. For the
individual back-gated devices, we first defined individual back-gate electrodes on Si/SiO
2
wafer
via photolithography, 5 nm Ti/ 45 nm Au deposition, and a lift-off process. 50 nm ALD HfO
2
was
deposited as the gate-dielectric, and then the aligned nanotubes were transferred. Finally, the
source/drain electrodes were formed. The CMOS NOR and NAND are depicted in Figure 3.11a
and b, respectively. After the device fabrication, we performed the potassium doping to get n-type
devices as mentioned in the CMOS inverter study. Figure 3.11c and d show SEM images of the
CMOS NOR and NAND, respectively. The pull-up and pull-down networks were built on the
same nanotube arrays, and the pull-down network was converted from p-type into n-type after
potassium doping, as described below. Figure 3.12a and b show the I-VA curves of the CMOS
NAND pull-up network before and after potassium doping, respectively. Owing to the PMMA
passivation, there was no significant difference in the transfer characteristics, indicating the p-
type transistors were protected from potassium doping.

Figure 3.11 Defect-tolerant CMOS NOR and NAND with individual back-gated transistors. a), b) Schematic diagrams
of CMOS NOR and NAND, respectively. c), d) SEM images of CMOS NOR and NAND, respectively. e), f) Output
characteristics of CMOS NOR and NAND, respectively.

For the CMOS NAND pull-down network shown in Figure 3.12c and d, the p-type devices in
Figure 3.12c were successfully converted into n-type in Figure S5d after potassium doping.
41
Compared with the PMOS circuits, the CMOS logic circuits showed almost ideal performance,
where the outputs were close to 0 V or 1.0 V, as shown in Figure 3.11e and f.

Figure 3.12 a), b) I-Vg curves of the pull-up network (in dotted line) in CMOS NAND before and after potassium
doping, respectively. c), d) I-Vg curves of the pull-down network (in dotted line) in CMOS NAND before and after
potassium doping, respectively.

In summary, we have reported significant progress on CMOS-analogous wafer-scale
processing of integrated aligned nanotube circuits, including progress on wafer-scale synthesis
and transfer of aligned nanotubes, metallic nanotube removal and chemical doping, and defect-
tolerant integrated nanotube circuits. Synthesis of massive aligned nanotubes has been achieved
on complete 4 inch quartz and sapphire substrates, followed by successful transfer of the
nanotubes to 4 inch Si/SiO
2
wafers. CMOS analogous fabrication was performed to yield
transistors and circuits with features down to 0.5 μm, with high current density ~ 20 μA/ μm and
good on/off ratios. In addition, extensive chemical doping has been studied and used to build
fully integrated complementary inverter with a gain ~ 5, and defect-tolerant designs have been
42
43
proposed and employed for NAND and NOR gates. Our work represents significant advance
toward the challenging task of nanotube assembly and integration for future beyond-silicon
integrated circuits.

44
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433-438.
10. Han, S., X.L. Liu, and C.W. Zhou, Template-free directional growth of single-walled
carbon nanotubes on a- and r-plane sapphire. Journal of the American Chemical Society,
2005. 127(15): p. 5294-5295.
11. Ismach, A., et al., Atomic-step-templated formation of single wall carbon nanotube
patterns. Angewandte Chemie-International Edition, 2004. 43(45): p. 6140-6143.
12. Kocabas, C., et al., Guided growth of large-scale, horizontally aligned arrays of single-
walled carbon nanotubes and their use in thin-film transistors. Small, 2005. 1(11): p.
1110-1116.
13. Chimot, N., et al., Gigahertz frequency flexible carbon nanotube transistors. Applied
Physics Letters, 2007. 91(15): p. 3.
14. Le Louarn, A., et al., Intrinsic current gain cutoff frequency of 30 GHz with carbon
nanotube transistors. Applied Physics Letters, 2007. 90(23): p. 3.
15. Liu, X.L., S. Han, and C.W. Zhou, Novel nanotube-on-insulator (NOI) approach toward
single-walled carbon nanotube devices. Nano Letters, 2006. 6(1): p. 34-39.
45
16. Kang, S.J., et al., High-performance electronics using dense, perfectly aligned arrays of
single-walled carbon nanotubes. Nature Nanotechnology, 2007. 2(4): p. 230-236.
17. Kocabas, C., et al., Radio frequency analog electronics based on carbon nanotube
transistors. Proceedings of the National Academy of Sciences of the United States of
America, 2008. 105(5): p. 1405-1409.
18. Pesetski, A.A., et al., A 500 MHz carbon nanotube transistor oscillator. Applied Physics
Letters, 2008. 93(12): p. 2.
19. Derycke, V., et al., Controlling doping and carrier injection in carbon nanotube
transistors. Applied Physics Letters, 2002. 80(15): p. 2773-2775.
20. Klinke, C., et al., Charge transfer induced polarity switching in carbon nanotube
transistors. Nano Letters, 2005. 5(3): p. 555-558.
21. Kong, J., et al., Alkaline metal-doped n-type semiconducting nanotubes as quantum dots.
Applied Physics Letters, 2000. 77(24): p. 3977-3979.
22. Lin, Y.M., et al., High-performance carbon nanotube field-effect transistor with tunable
Polarities. Ieee Transactions on Nanotechnology, 2005. 4(5): p. 481-489.
23. Shim, M., et al., Polymer functionalization for air-stable n-type carbon nanotube field-
effect transistors. Journal of the American Chemical Society, 2001. 123(46): p. 11512-
11513.
24. Collins, P.C., M.S. Arnold, and P. Avouris, Engineering carbon nanotubes and nanotube
circuits using electrical breakdown. Science, 2001. 292(5517): p. 706-709.

46
Chapter 4 Aligned carbon nanotube for flexible electronics

4.1 Transfer imprinting of aligned nanotubes
The past decade has witnessed tremendous progress for both carbon nanotubes and
nanowires. In particular, nanowires have been assembled into aligned arrays to produce nanowire
thin film transistors[1, 2], which have great advantage in terms of the carrier mobility over
traditional polycrystalline or amorphous silicon and organic semiconductors[3, 4]. In contrast,
single-walled carbon nanotubes (SWNTs) are expected to offer as good or even better
performance for flexible and wearable electronics due to their high carrier mobility (up to
100,000 cm
2
/Vs)[5], flexibility[6], chemical stability[7], and shock resistance. In spite of the
utmost importance, previous studies have mainly focused on transistors[8] and small-scale
integrated circuits[9, 10], based on individual carbon nanotubes on rigid substrates, due to the
difficulty in assembling aligned nanotubes. The assembly of carbon nanotubes into aligned
arrays on various substrates, including plastics and fabrics, is therefore highly desired for new
applications such as flexible electronics and smart textiles[11, 12]. In this paper, we have
developed a much simplified process to easily transfer aligned nanotubes from the original
sapphire/quartz substrates to virtually any other substrates, including glass, silicon, polymer
sheets, and even fabrics by using a special thermal tape, and multiple transfers of nanotubes have
further led to sophisticated carbon nanotube networks. The nanotube network transferred to
quartz substrates was found to alter the quartz surface from hydrophilic to hydrophobic, while
nanotube networks transferred to polyethylene terephthalate (PET) substrates were observed to be
highly conductive, transparent, and flexible as well. Furthermore, based on transferred nanotube
arrays on fabric, we have successfully demonstrated nanotube transistors with on/off ratios ~ 10
5
,
and chemical sensors for low-concentration NO
2
and 2,4,6-trinitrotoluene (TNT). These devices
have great potential for flexible electronics and smart textiles with integrated computation
elements and sensors.

Figure 4.1 Transfer printing of aligned nanotube arrays. (a) Diagrams illustrating the aligned nanotube transfer process.
(b) SEM image of as-grown aligned single- walled nanotubes on a quartz substrate with stripe patterned catalyst. The
image shows that nanotubes are well aligned, straight and uniformly grown between two Fe catalyst stripes (bright
region). (c) Optical micrograph of transferred aligned nanotubes on PET with patterned source/drain electrodes. The
PET coated with 50 nm ITO was first spin-coated with 2 µm SU-8 (Microchem) as a dielectric layer, and then
nanotubes were transferred, followed by photolithography and e-beam evaporation of Ti/Au films to define source and
drain. Inset shows a SEM image of the aligned nanotubes bridging between source and drain electrodes. (d) Optical
micrograph of transferred nanotubes on fabric with source/drain electrodes. (e) and (f) SEM images of aligned
nanotube arrays transferred onto the same substrates at parallel orientation, where the density of nanotubes are ~ 14
tubes /µm and ~ 21 tubes / µm after the second and third round of transfer, respectively. (g) Plot of nanotube density as
a function of the number of transfer steps, showing the linear increase of nanotube density.

47
48
Figure 4.1a illustrates our transfer printing process. We synthesized aligned SWNT
arrays (Figure 4.1b) on sapphire and quartz substrates with patterned catalyst stripes using
chemical vapor deposition (CVD) reported by us and other groups[13-15]. A 100 nm thick gold
film was first deposited onto the aligned SWNTs on the original substrate to ensure conformal
contact between nanotubes and the gold film. To transfer SWNTs onto the targeting substrate,
our key innovation is the use of Revalpha thermal tape (from Nitto Denko), which has an
interesting temperature-dependent adhesive property: it is highly adhesive at room temperature,
but loses its adhesion at a moderate temperature of 120 °C. This tape was pressed against the
original substrate with nanotubes covered by the gold film, and then peeled off together with the
gold film and nanotubes. The nanotube / gold film / thermal tape trilayer structure was pressed
against the target substrate, and the tape was then released by simply heating to 120 °C. The gold
film was subsequently removed using gold etchant, thus leaving a nice array of massively aligned
SWNTs on the target substrate. Compared with our facile transfer process, the previous approach
pioneered by Kang et al.[16] involves extra time-consuming steps such as coating of polyimide
onto the gold-covered nanotubes, curing of the polyimide films, and subsequent oxygen plasma
removal of the polyimide after the nanotube transfer. Based on the transfer process, we have
successfully carried out transfer printing of aligned SWNTs onto various substrates, including
polymer sheets, glass slides, glass rods, and even fabric. Figure 1c shows an optical micrograph
of flexible PET substrates of different dimensions with transferred aligned nanotubes and
patterned electrodes, where the nanotubes can be clearly seen bridging two electrodes in Figure 4.
1c inset. In addition, wearable device arrays with nanotubes transferred onto cleanroom garment
are shown in Figure 4.1d. These samples may work as multifunctional fabric, commonly referred
to as electronic textiles or smart textiles, which need to be flexible and conformable to human
body. These nanotubes have also been transferred to glass slides, which may serve as electronic
substrates for transparent transistors and circuits. Furthermore, we can perform multiple steps of
49
nanotube transfer to obtain aligned nanotube arrays with higher density. Figure 4.1e and f display
the SEM images of aligned nanotubes with two-step and three-step transfer, respectively, and the
nanotube density exhibited a linear increase from 7 to 21 nanotubes, as shown in Figure 4.1g. An
exponential increase in nanotube density can also be achieved by starting with nanotube samples
with n nanotubes per micron, performing one transfer to obtain multiple samples with 2n
nanotubes per micron, and then performing another transfer to obtain samples with 4n nanotubes
per micron.
4.2 Characterization of transferred aligned nanotubes
To characterize the transferred nanotubes on various substrates, extensive study has been
carried out using Raman spectroscopy, contact angle measurement, and transmittance
measurement, as shown in Figure 4.2a-f. We have taken Raman spectra from nanotubes before
and after the transfer to ascertain whether the transfer process induces defects in the nanotubes for
the first time. Figure 4.2a shows the typical result from one nanotube, where little difference was
observed, thus testifying to the high integrity of the transferred nanotubes. In addition, we
characterized the defect density of approximately 60 nanotubes by comparing the Raman G and D
line intensity. Figure 4.2b plots the distribution of the D-band and G-band intensities for those
nanotubes before and after the transfer process, and the dominant majority of nanotubes exhibited
very low D line intensity compared to G-band intensity, indicating very good nanotube quality
both before and after the transfer. Interestingly, the transfer of carbon nanotubes have been found
to alter the surface property of the underlying substrate profoundly. As shown in Figure 4.2c, the
quartz substrate was observed to convert from initially hydrophilic to hydrophobic with the
transfer of nanotubes, and the contact angle changed from 15 ° degree for the bare quartz substrate,
to 50 degree with one layer of aligned nanotubes, and eventually 68 ° degree with two layers of
nanotubes which are crisscrossed as shown Figure 4.2d.

Figure 4.2 Characterization of transferred nanotubes. (a) Raman spectra of a nanotube before and after transfer,
showing little difference. (b) Raman intensity of D-band and G-band of an ensemble of 60 nanotubes before and after
transfer. (c) Contact angle of water droplet as a function of the number of transfer steps. The Contact angle ( θ) is
defined as cos θ = (f
VS
-f
LS
)/f
LV,
where f
VS
, f
LS
and f
LV
are interfacial force of vapour and substrate, water and substrate,
and water and vapour, respectively. As the quartz substrate are covered by transferred nanotubes, f
LS
becomes smaller
due to the low surface energy of nanotubes, making the surface hydrophobic. Clearly, the water drop on a blank quartz
substrate (bottom) reveals a hydrophilic surface, as compared to the hydrophobic surface for the quartz substrate with a
transferred nanotube network (top). (d) SEM image of an aligned nanotube network on quartz, which are obtained by
two steps of nanotube transfer with orthogonal orientations. (e) The transmittance spectra of a glass substrate before
and after transfer, showing the high transparency of the transferred nanotubes. The substrate after transfer contains
nanotubes of 1.3 nm average diameter with a density of ~ 10 tubes / µm, which can cover 11.3% of the surface area
( the stripe patterned area of 5 µm width was included). (f) The change of resistance (R) as a function of the bending
angle of a device (channel length L = 4 µm, channel width W = 50 µm, nanotube density D = 5 tubes / µm) fabricated
on a PET substrate. Two-probe dc conductance measurements were performed to get resistance of the device, and the
bending angle was determined by measuring the angle between the two tangential lines drawn on the edge of the
substrate as shown in the inset.

50
51
This is attributed to the hydrophobic property of transferred nanotubes. Furthermore, the
transferred nanotubes exhibit good transparency, a property that can be exploited as optical
coating or transparent electronics.
Figure 4.2e displays the transmittance spectra of a glass substrate before and after the
nanotube transfer. The glass substrate with transferred nanotubes exhibited ultra high
transmittance to visible light (98% @ 520 nm), which is much better than that of typical ITO
films (~90%).
In order to further verify the flexibility of transferred nanotubes, two-probe dc
measurements were taken on transferred nanotubes on PET substrates with patterned electrodes,
and the resistance (R) is plotted in Figure 4.2f as a function of bending angle of the PET substrate,
which was determined as shown in Figure 4.2f inset and went up to 140 °. Although slight
fluctuation in resistance is shown, there is no significant change, owing to the robust bending
property of SWNTs[17, 18].

4.3 Flexible Transistors based on transferred nanotubes
The excellent electrical property, hollow structure and mechanical flexibility of SWNTs
make them ideal candidates for transparent and flexible nanoelectronics such as flexible displays,
flexible chemical sensors, and electronic skin, which will require the tolerance of significant
mechanical bending. Based on the transferred nanotubes, transistor arrays with 50 nm thick Ti as
the back-gate, 2 µm thick SU-8 as the dielectric, and Ti(5 Å)/Pd(400 Å) as Source/Drain
electrodes were fabricated as illustrated in Figure 4.3a. Figure 4.3b displays the current-gate
voltage (I-V
g
) characteristics of a typical flexible transistor on fabric before and after electrical
breakdown. The device showed significant improvement of the on/off ratio from 1.5 to 10
4
,
accompanied by decrease of the on-state current due to metallic nanotube removal. After
electrical breakdown, in-depth I-V
g
and the current v.s drain-source voltage (I-V
ds
) measurements
were also performed. Figure 4.3c displays the current magnitue ( │I│) as a function of gate
voltage (V
g
) at different V
ds
from 0 to -1V with ΔV
ds
= -200 mV, showing pronounced p-type
behavior. From the logarithm plot of the I-V
g
curves in the inset of Figure 4.3c, we extracted the
subthreshold swing of this device as 2.5 V/decade and the on/off ratio as high as 10
5
.

Figure 4.3 Wearable transistors based on aligned nanotubes transferred to fabric. (a) Schematic diagram showing a
transistor structure that uses polyethylene- coated fabric as the substrate, 50 nm thick Ti film for the back-gate
electrode, 2 µm SU-8 as the dielectric layer, and the transferred aligned nanotube array as the active channel. The
optical micrograph shows an array of such transistors built on a flexible fabric. (b) I-V
g
curves of a transistor (L = 4 µm,
W = 10 µm, D = ~ 2 tubes / µm ) before and after electrical breakdown. c, I -V
g
curves at different V
ds
for the device in
(b). The curves labelled 1 to 6 correspond to V
ds
= 0 to -1 V in steps of -200 mV. The inset shows the logarithm plot of
the I-V
g
curves. The subthreshold swing ( S = dV
g
/dlog(I
ds
) ) and the on/off ratio are 2.5 V/decade and 10
5
, respectively.
(d) I – V
ds
curves at different V
g
for the same device in (b). The curves labelled 1 to 6 correspond to V
g
= 0 to -30 V in
step of -6 V. (e) The on-current change of a transistor at different relative humidity ( V
g
= - 30 V, V
ds
= 0.4 V).

52
In addition, Figure 4.3d shows a family of I-V
ds
curves at different gate voltages. The highest
current obtained at V
g
= -30 V and V
ds
= -1 is 0.73 µA. This device even exhibited humidity
dependence as shown in Figure 4.3e. The on-current of the device linearly increased with the
humidity, probably due to the p-type nature of the nanotubes. This property can potentially be
exploited for electronic skin applications.
Furthermore, we have demonstrated the use of the transferred nanotube devices built on
fabric as chemical sensors, which can detect NO
2
and TNT of ppm level.

Figure 4.4 Use of the transferred aligned nanotubes built on fabric as chemical sensors. (a) Schematic diagram
showing a nanotube chemical sensor detecting NO
2
molecules. (b) Chemical sensing performance of the device with L
= 4 µm, W = 150 µm, D = ~ 5 tubes / µm) upon exposure to 10 and 50 ppm NO
2
. Normalized conductance change (S)
for 10 ppm NO
2
was estimated as around 500% with the definition S = ΔG/G
0
= (G – G
0
)/G
0
, where G
0
and G denote
the nanowire conductance before and after NO
2
exposure. The conductance change became significant with increased
NO
2
concentrations, from 500% at 10 ppm to over 1500% at 50 ppm. The minimum detectable NO
2
concentration
which is derived by the conductance change at different concentration can be down to ~ several ppm NO
2
in air. (c)
Sensing data to 0.6 ppm TNT using the same device in (b) 0.6 ppm TNT vapour was obtained by heating up TNT
source to 60 °C and using 100 sccm Ar as the carrier gas. The nanotube sensor was maintained at 90 °C for improved
sensing efficiency, and the sensing experiments were carried out by monitoring the nanotube device conductance
change under the vaporized TNT. The chemical structure of TNT (C
6
H
2
(NO
2
)
3
CH
3
) is shown in the inset. After TNT
exposure, the nanotube device showed around 40% suppression of the conductance.
53
54
The real-time chemical sensing for dangerous molecules can be expected as one of the
most important functions of wearable electronics. Figure 4.4b shows the current change of a
nanotube device before and after exposure to 10 and 50 ppm NO
2
, respectively. The NO
2

molecules, known as strong electron-withdrawing groups, reduced the electron density along the
nanotube, and thus led to an increase of the p-type conductance of nanotube as illustrated in
Figure 4.4a. The effect of NO
2
was clearly shown by the increase in conductance. Based on the
sensing data, the minimum detectable NO
2
concentration can be down to ~ several ppm NO
2
in
air, which is comparable with literature results[19]. In addition to NO
2
, we have further used the
aligned nanotube transistor on fabric for the first time for the detection of TNT, which is not only
the main explosive material for blasting charges, but also a highly poisonous agent[20]. TNT is a
distinct electron-acceptor molecule (inset of Figure 4.4c) that is able to readily form electron
donor-acceptor complexes on carbon nanotube surfaces. Figure 4.4c shows the sensing data with
the nanotube transistor operated at 90 °C and TNT powder was heated to 65 °C to produce 0.6
ppm TNT vapour. A significant decrease in conductance was observed, with the sensing setup
under ambient illumination. The underlying sensing mechanism is that TNT can easily
decompose to produce nitro groups with ambient illumination, and nitro group homolysis can
further yield nitrous oxide radical, which readily dissociates to nitric oxide (NO) at room
temperature[21], and NO is well known to be a good electron donor and a signature degradation
product of TNT[22]. As a result, the wearable nanotube-based sensing device showed both good
sensitivity and selectivity between TNT and NO
2
.
In summary, we have demonstrated facile transfer printing of aligned nanotubes from the
original sapphire/quartz substrates to glass, silicon, polymer sheets and fabrics. Based on
transferred nanotube arrays on fabric, we have demonstrated wearable transistors based on
multiple parallel nanotubes with on/off ratios ~ 10
5
and on-state current ~ 0.7 μA. These devices
were further used as wearable chemical sensors, and successful detection was achieved for NO
2
55
down to 10 ppm and TNT down to 0.6 ppm concentrations. These devices have great potential for
flexible electronics and smart textiles.

56
Chapter 4. References

1. Duan, X.F., et al., High-performance thin-film transistors using semiconductor
nanowires and nanoribbons. Nature, 2003. 425(6955): p. 274-278.
2. Huang, Y., et al., Logic gates and computation from assembled nanowire building blocks.
Science, 2001. 294(5545): p. 1313-1317.
3. Dimitrakopoulos, C.D. and D.J. Mascaro, Organic thin-film transistors: A review of
recent advances. Ibm Journal of Research and Development, 2001. 45(1): p. 11-27.
4. Garnier, F., et al., All-Polymer Field-Effect Transistor Realized by Printing Techniques.
Science, 1994. 265(5179): p. 1684-1686.
5. Durkop, T., et al., Extraordinary mobility in semiconducting carbon nanotubes. Nano
Letters, 2004. 4(1): p. 35-39.
6. Thostenson, E.T., Z.F. Ren, and T.W. Chou, Advances in the science and technology of
carbon nanotubes and their composites: a review. Composites Science and Technology,
2001. 61(13): p. 1899-1912.
7. Rochefort, A., D.R. Salahub, and P. Avouris, Effects of finite length on the electronic
structure of carbon nanotubes. Journal of Physical Chemistry B, 1999. 103(4): p. 641-
646.
8. Tans, S.J., et al., Electron-electron correlations in carbon nanotubes. Nature, 1998.
394(6695): p. 761-764.
9. Bachtold, A., et al., Logic circuits with carbon nanotube transistors. Science, 2001.
294(5545): p. 1317-1320.
10. Chen, Z.H., et al., An integrated logic circuit assembled on a single carbon nanotube.
Science, 2006. 311(5768): p. 1735-1735.
11. Carpi, F. and D. De Rossi, Electroactive polymer-based devices for e-textiles in
biomedicine (vol 9, pg 295, 2005). Ieee Transactions on Information Technology in
Biomedicine, 2005. 9(4): p. 574-574.
12. Laxminarayana, K. and N. Jalili, Functional nanotube-based textiles: Pathway to next
generation fabrics with enhanced sensing capabilities. Textile Research Journal, 2005.
75(9): p. 670-680.
13. Han, S., X.L. Liu, and C.W. Zhou, Template-free directional growth of single-walled
carbon nanotubes on a- and r-plane sapphire. Journal of the American Chemical Society,
2005. 127(15): p. 5294-5295.
14. Ismach, A., et al., Atomic-step-templated formation of single wall carbon nanotube
patterns. Angewandte Chemie-International Edition, 2004. 43(45): p. 6140-6143.
57
15. Kocabas, C., et al., Guided growth of large-scale, horizontally aligned arrays of single-
walled carbon nanotubes and their use in thin-film transistors. Small, 2005. 1(11): p.
1110-1116.
16. Kang, S.J., et al., High-performance electronics using dense, perfectly aligned arrays of
single-walled carbon nanotubes. Nature Nanotechnology, 2007. 2(4): p. 230-236.
17. Artukovic, E., et al., Transparent and flexible carbon nanotube transistors. Nano Letters,
2005. 5(4): p. 757-760.
18. Cao, Q., et al., Highly bendable, transparent thin-film transistors that use carbon-
nanotube-based conductors and semiconductors with elastomeric dielectrics. Advanced
Materials, 2006. 18(3): p. 304-+.
19. Kong, J., et al., Nanotube molecular wires as chemical sensors. Science, 2000.
287(5453): p. 622-625.
20. Yinon, J., Field detection and monitoring of explosives. Trac-Trends in Analytical
Chemistry, 2002. 21(4): p. 292-301.
21. Lemire, G.W., J.B. Simeonsson, and R.C. Sausa, Monitoring of Vapor-Phase Nitro-
Compounds Using 226-Nm Radiation - Fragmentation with Subsequent No Resonance-
Enhanced Multiphoton Ionization Detection. Analytical Chemistry, 1993. 65(5): p. 529-
533.
22. Bartberger, M.D., et al., The reduction potential of nitric oxide (NO) and its importance
to NO biochemistry. Proceedings of the National Academy of Sciences of the United
States of America, 2002. 99(17): p. 10958-10963.

58
Chapter 5 Transparent, Conductive, and Flexible Carbon nanotube film

5.1 Overview of carbon nanotube films
Evaluating the potential of carbon nanotubes (CNTs) as the basis of future
nanoelectronics technology has been the subject of intense research since their discovery. In
contrast, their applications in macro-electronics had received limited attention until three to four
years ago when fabrication and purification of macroscopic nanotube products became a
relatively mature technique.[1, 2] Recently, considerable research on macro-optoelectronics has
focused on optimizing the performance of organic light emitting diodes (OLEDs) by
incorporating CNTs into polymer matrices as a dopant material[3-9]. It is found that the
combination of CNTs with polymers offers an attractive route not only to reinforce polymer films
but also to introduce new electronic properties based on morphological modification or electronic
interaction between the two components. The effect of CNT doping has been systematically
investigated by embedding CNT powders in the emission[5-7, 9],

electron-transport[3, 4] and
hole-transport
9
layers of OLEDs (Figure 1a). By introducing additional energy levels or forming
carrier traps in the host polymers, the CNT dopant can selectively facilitate or block the transport
of charge carriers, and effectively improve the OLED performance at optimized dopant
concentrations.
In parallel with the research efforts on the CNT-polymer mixtures, continuous CNT
films[10]

could offer a new class of transparent conducting materials that complements indium-
tin oxide (ITO) for certain niche applications, including organic light emitting diodes and organic
photovoltaic (OPV) devices. For example, CNT films are superior to ITO in terms of the
flexibility, as the former can be bent to acute angles without fracture. In addition, while carbon is
the most abundant element in nature, the world-wide production of indium is limited, which may
59
soon find difficulty meeting the ever increasing demand for large-area transparent conductive
electrodes. Furthermore, CNT-films may offer additional advantages such as tunable electronic
properties through chemical treatment and enhanced carrier injection owing to the large surface
area and field-enhanced effect at the nanotube tips and surfaces[11]. In spite of the fact that ITO
films still lead CNT-films in terms of sheet conductance and transparency, the above-mentioned
advantages have stimulated significant interest in exploiting carbon nanotube films as transparent
conductive electrodes for OLEDs.
Pioneering work has been performed by Zhang et al. on using multi-walled nanotube
films as electrodes for OLED devices[12]. In addition, high-quality single-walled nanotube
(SWNT) films have been produced using nanotubes synthesized via laser ablation. In this paper
we report on comparative studies on transparent conductive thin films and also OLED devices
made with two kinds of commercial SWNTs: HiPCO nanotubes (Carbon Nanotechnology Inc.)
and arc-discharge nanotubes (P3 nanotubes from Carbon Solutions Inc.). This choice of materials
is based on the fact that HiPCO and arc-discharge nanotubes are currently the only two SWNT
products commercially available in bulk quantities. Systematic investigation of their transparent
networks can therefore provide practical information to interdisciplinary research on carbon
nanotubes and organic displays.

5.2 Fabrication of carbon nanotube films
Our control experiments demonstrate that arc-discharge nanotubes form far more
homogeneous and conductive networks than HiPCO nanotubes, and result in OLEDs with longer
lifetimes when serving as the hole-injection electrodes. We have also performed polymer
passivation and SOCl
2
doping to further reduce the surface roughness and sheet conductance of
the SWNT films. The optimized films show typical sheet resistance of ~160 Ω/ □, 87%
transparency, and surface roughness comparable to that of ITO substrates.

We adopted a vacuum filtration method to prepare SWNT-films. The technique was
originally developed by de Heer et al[13]. and has been recently reexamined. We started by
mixing HiPCO

and P3

SWNTs with 1 wt% aqueous sodium dodecyl sulfate (SDS) to make a
highly-dense SWNT suspension with a typical concentration of 1 mg/mL.
a
b
Cathode
ETL
EML
HTL
Anode
60

Figure 5.1 (a) Schematic diagram of a typical multilayer OLED. (b) Photograph of a SWNT film on an alumina
filtration membrane. Inset: An SEM image showing the microscopic structure of the porous membrane surface (before
SWNT deposition). (c) Illustration of the dry transfer process, in which the SWNT-film is peeled off from the filtration
membrane using a PDMS stamp and successively printed on a rigid or flexible substrate. (d) A transparent 40-nm thick
SWNT film on a glass substrate 2” in diameter and (e) a flexed SWNT film on a PE sheet. A sheet of paper with
printed “USC” was placed underneath the nanotube films to illustrate the transparency.

HiPCO SWNTs are as-produced nanotubes with a purity of 78.2 wt %, whereas P3 SWNTs are
purified arc-discharge nanotubes with a purity of 80 wt %. Both types of tubes were used as
c
PDMS stamp
SWNTs
Filtration membrane
Glass or PE substrate
d e
61
received without any further purification or intentional doping. The addition of SDS surfactant is
to further improve the solubility of SWNTs by sidewall functionalization. This highly-
concentrated SWNT suspension was then ultrasonically agitated using a probe sonicator for ~ 10
minutes, followed by centrifugation to separate out undissolved SWNT bundles and impurities.
To make a uniform SWNT film, the as-produced suspension was further diluted by a factor of 30
with deionized water and filtered through a porous alumina filtration membrane (Whatman, 200
nm pore size, Figure5.1b inset). As the solvent went through the pores, the SWNTs were trapped
on the membrane surface, forming a homogeneous grey layer (Figure5.1b). This film-forming
approach leads to greater production efficiency compared to previous methods, as one can
produce a large quantity of the highly concentrated SWNT suspension. This simplicity is
attributed to the use of a probe sonicator, which significantly facilitated the dispersion of SWNTs
in the aqueous SDS solvent.
Unlike the previous approaches, which require dissolving the filtration membrane in wet
chemicals to release the SWNT-film, here we use a dry method to transfer the SWNTs from the
filtration membrane to target substrates. This dry-transfer approach, initially developed by Zhou
et al[10], uses an adhesive, soft and flat poly(dimethysiloxane) (PDMS) stamp to peel the SWNT-
film off the filtration membrane and then release it onto a desired substrate, as illustrated in
Figure 1c. We note the press printing requires mild heating during contact (100 °C, 1 min) to
improve the adhesion of the target substrates. Using this technique, we have demonstrated
complete SWNT-film transfer to glass (Figure5.1d) and flexible polyester (PE) substrates
(Figure5.1e), which can be subsequently used as transparent conductive electrodes for OLEDs,
organic photovoltaic devices, or other optoelectronic devices.
Figure5.2 compares the surface morphology and electrical conductance of the as-
prepared HiPCO and P3 SWNT films. Figure5.2 (a) and (b) are perspective-view (60º from the
normal direction) SEM images of SWNT films made of HiPCO and P3 nanotubes, respectively.
While the P3 SWNTs form a rather dense and homogeneous network, HiPCO nanotube films
display a number of “bumps” distributed on the film surface, which presumably result from the
impurities or bundled nanotubes in the HiPCO product. The difference in surface quality is also
revealed by the top-view SEM images displayed in Figure5.2 (c) and (d).
62

Figure 5.2 (a) and (b) SEM images of a HiPCO and a P3 SWNT film taken from a perspective angle (60° from the
normal direction), respectively. (c) and (d) are top views of the same SWNT films. The inset images (1 μm by 1 μm)
are taken at higher magnifications. (e) Sheet resistance vs. transparency curves of HiPCO and P3 SWNT films.

2 μm
a
c
d
e
b
10
2
10
3
10
4
R
s
(Ω/)
100 90 80 70 60 50
transparency
Hipco
P3

HiPCO P3 2 μm
1 μm HiPCO P3 1 μm
63
The HiPCO SWNT film shows a higher roughness level due to the nanotubes and impurities
protruding from the surface, whereas P3 nanotubes tend to bind to the supporting substrate
conformally, forming a smooth network. Furthermore, we have observed that P3 SWNT films
consistently exhibit much higher sheet conductance than HiPCO nanotubes by more than one
order of magnitude at similar optical transparency, as shown in Figure5.2e. The origin of this
difference may be related to several factors, including difference in the nanotube dimension, the
defect density, the presence of resistive impurities, and the ease of separating bundled nanotubes.
A comprehensive comparison between the two types of commercial SWNTs is shown in Table 1.
In the rest of this report we will focus our discussion on P3 SWNT films, which outperform
HiPCO nanotubes in all critical aspects including the surface smoothness, sheet conductance, and
the stability of OLED devices, as discussed below.

Roughness (nm) R
s
at 87% transparency ( Ω) Lifetime of OLEDs
HiPCO 11 7200 < 30 s
P3 7 380 > 4-5 hours
*

Table 5.1 Comparison between pristine nanotube films based on HiPCO and P3 nanotubes.

Further examination of the surface roughness was carried out using atomic force
microscopy (AFM). Figure5. 3a shows a typical AFM image of a P3 SWNT film on glass,
confirming the formation of dense and homogeneous network of interconnected SWNTs. The
average surface roughness of typical pristine P3 SWNT-films is around 7 nm as measured for five
different samples with similar thickness (~40 nm, determined by AFM at step edges). This degree
of roughness compares favorably with that of nanotube films based on HiPCO nanotubes, which
have a typical roughness of 11 nm, as listed in Table 1. To further reduce the roughness of the P3
SWNT film and ensure uniform light emission across the OLED surface, we spin-coated a
commonly used conductive polymer, poly(3,4-ethylenedioxythiophene) (PEDOT), to smoothen
the sample surface. As seen in the AFM image in Figure5. 3b, the SWNT film shows a
pronounced improvement in surface flatness, with a substantially reduced roughness of 3.1 nm
after PEDOT spin-coating (100 Å). This degree of surface roughness is comparable to that of
standard ITO films, which is 2.4 nm as derived from the AFM image in Figure5. 3b inset.

b
a
64

Figure 5.3 (a) AFM image of a pristine P3 SWNT film. (b) AFM image of a PEDOT-passivated nanotube film
showing a surface roughness of 3.1 nm, which is comparable to 2.4 nm roughness of typical ITO substrates (inset). (c)
Sheet resistance vs. film thickness of P3 SWNT films. Inset: conductivity vs. film thickness. (d) Transmittance spectra
for SWNT films of thickness 20, 40, 80, and 120 nm. The transmittance of the SWNT-films decreases monotonically
with the film thickness. The 20 nm and 40 nm films exhibit sufficiently high transparency (>80%) over a wide spectral
range from 300 to 1100 nm. Inset: sheet resistance vs. temperature curve taken with a SWNT film of 40 nm in
thickness.

We have performed four-probe dc measurements on four different P3 SWNT films and
plotted their sheet resistance (R
s
) as a function of film thickness (t) in Figure5. 3c. To correlate
our data with literature results, the sheet resistance was further converted to electrical
conductivity, as defined as σ = 1/R
s
t. The σ vs. t curve (Figure5. 3c inset) shows a monotonic
1600
1400
1200
1000
800
600
400
200
0
Rs ( Ω/)
1 μm 1 μm
d
1 μm
ITO
140 120 100 80 60 40 20 0
thickness (nm)
c
800
600
400
200
conductance (S/cm)
120 80 40 0
thickness (nm)
100
80
60
40
20
0
transparency (%)
440
420
1000 800 600 400
wavelength (nm)
20nm
40nm
80nm
120nm
400
380
360
Rs ( Ω/ )
150 200 100
T (K)
250 300
65
increase with a tendency to saturate at greater thicknesses. The highest conductivity is 733 S/cm
for the 120 nm film, about two times higher than the saturation conductivity (400 S/cm) of P3
SWNT-films prepared by spraying.[14] We note that both values are far below the axial
conductivity of 10000 – 30000 S/cm for SWNT ropes[15]

due to the lack of alignment and the
presence of highly resistive intertube junctions in the random SWNT networks. In a qualitative
sense, the conductivity of the SWNT-film is determined by the density of conducting channels in
the random network, which is expected to scale as the concentration of low-resistance intertube
junctions formed by metallic SWNTs. The semiconductive-semiconductive and metallic-
semiconductive intertube junctions, in comparison, make less contribution to the overall
conductivity due to the high Schottky barriers formed at the interfaces. Adding SWNTs into an
initially sparse network causes significant increase in the concentration of the metallic-metallic
junctions, resulting in the sharp increase in conductivity at small thicknesses. As the SWNT
network becomes increasingly compact, the concentration of such conductive junctions tends to
saturate in thick films, which eventually leads to the saturation in electrical conductivity.
In comparison with the saturation conductivity of sprayed P3 SWNT-films (400
S/cm),[14] the higher conductivity (733 S/cm) observed in our measurements is a result of the
press-printing method we adopted, which produces more compact SWNT networks compared to
the spray approach.[14] The above microscopic view of the SWNT-film conductivity is also
supported by the temperature dependence measurement shown in Figure5. 3d inset, in which the
sheet resistance of the 40 nm film shows a very slight increase (10%) as temperature decreases
from 290 to 77 K. Such nonmetallic behavior and the weak temperature dependence are attributed
to the series conduction through the metallic SWNTs that are interrupted by small tunnel barriers
at the junctions. In Figure 3d, we present the transmittance spectra of the four SWNT-films.
Within the spectrum range from 300 to 1100 nm, the transmittance shows a monotonic increase in
the visible region and becomes relatively flat in the near-infrared. The 20 and 40 nm -films
exhibit sufficiently high transmittance to visible light (93% and 87% @ 520 nm), which is
comparable to that of typical ITO films (~90%).
66
b
a

Figure 5.4 (a) Four probe I-V curves taken on a 40 nm SWNT film before (dashed) and after (solid line) SOCl
2

treatment, indicating a decrease in sheet resistance by a factor of ~ 2.4. (b) Transmittance spectra of a pristine (dashed)
and a SOCl
2
-treated (solid line) sample.

OLED electrodes require high conductivity to distribute a uniform electrical potential
across the polymer surface. To enhance the conductivity of the SWNT films while retaining their
high transparency, we have carried out chemical doping using thionyl chloride (SOCl
2
), a liquid
organic solvent with remarkable reactivity toward graphite surface and SWNTs. The SOCl
2

treatment involved immersing the P3 SWNT-films in SOCl
2
(Aldrich) for 12 hours followed by
drying in N
2
flow. Figure5. 4a compares the four-probe I-V curves taken before and after the
SOCl
2
incubation, in which the treated film shows a significant increase in conductance by a
factor of 2.4. Such effect has been attributed to the strongly oxidizing nature of SOCl
2
, which
exhibits remarkable electron-withdrawing ability when adsorbed on the surface of SWNTs. In
fact, the conductivity enhancement effect is not limited to p-type semiconductive SWNTs.
Theoretical work
17
has suggested that the significant charge transfer induced by SOCl
2
(~ 0.1
electrons per adsorbate) could also enable Fermi level shifting into the van Hove singularity
region of metallic SWNTs, resulting in a substantial increase in the density of states at the Fermi
level.
100
80
60
40
20
0
transparency (%)
1000 900 800 700 600 500 400
wavelength (nm)
w/o SOCl
2
w SOCl
2
-4
-2
0
2
4
I (mA)
0.4 0.2 0.0 -0.2 -0.4
w/o SOCl
2
w SOCl
2
V (V)
67

Figure 5.5 (a) Structure of the OLED device employed for the present study. The device consists of multi layers of
patterned SWNT-film (40 nm), PEDOT (10 nm), NPD (50 nm), Alq
3
(50 nm) and LiF(10 Ǻ)/Al (1500 Ǻ). The energy
diagram of the device is illustrated in the upper-right inset. The upper-left inset shows a photograph of a completed
device fabricated on a glass substrate. (b) Photoluminescence spectrum of the Alq
3
coating. (c) Current density vs.
voltage bias curve recorded on one device pixel. (d) Brightness vs. voltage bias. The device shows a threshold voltage
of ~ 5V and a maximum brightness of 17 Cd/m
2
. (e) Quantum efficiency as a function of current density.

Moreover, we find that despite the significant modification in their electrical properties, the
treatment with SOCl
2
has a negligible effect on the optical adsorption of SWNTs in the visible.
This has been demonstrated in Figure5. 4b by comparing the transmittance spectrum of the
LiF/Al cathodes
Device pixel
SWNT
Alq
3
PEDOT
NPD
2.9 eV
Al
2.2 eV
2.4 eV
5.2 eV
5.5 eV
3.0 eV
5.7 eV
e
-
h
+
4.5 eV
a
Alq
3
NPD
PEDOT
Glass
SWNT stripes
Ti/Au electrodes
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Current density (mA/cm
2
)
20 15 10 5 0
V (V)
16
14
12
10
8
6
4
2
0
Brightness (Cd/m
2
)
20 15 10 5 0
V (V)
0.001
0.01
0.1
1
Q.E (%)
1.0
16 14 12 10 8 6 4 2
V (V)
0.8
0.6
0.4
0.2
0.0
normalized intensity
800 700 600 500 400
wavelength (nm)
b
e d
c
68
SOCl
2
-treated sample with that of a pristine P3 SWNT-film. With this doping technique, the
optimized films show a typical sheet resistance of ~160 Ω/ □ at 87% transparency.

5.3 Application on OLED
Lastly, we have demonstrated the use of the optimized SWNT films as hole injection
electrodes in OLEDs on both rigid glass and flexible plastic substrates. The device structure is
illustrated in Figure5. 5a. To fabricate multiple pixels on a single device, the continuous SWNT-
film was first patterned into 1.5 mm-wide stripes by selective O
2
plasma etching. As an optional
step, Ti/Au electrode was deposited at the end of each SWNT stripe to facilitate external
connections. PEDOT was then spin-coated on the SWNT-film to form a 200 Å-thick hole-
injection buffer layer. After annealing in vacuum for 20 minutes, 500 Å N,N’-Di-[(1-
naphthalenyl)-N,N’-diphenyl]-1, 1’-biphenyl)4,4’-diamine (NPD) and 500 Å Tris (8-
hydroxyquinolinato) aluminum (Alq
3
)

were successively deposited via thermal evaporation,
forming the hole-transport and emission layers of the OLED. In the final step, the top cathodes
were added by consecutive deposition of 10 Å LiF and 1200 Å Al through a shadow mask. A
photograph of the completed device (on glass substrate) is shown in the upper-left inset of
Figure5.5a.
Figure5.5b shows the photoluminescence spectrum of Alq
3
, with a single peak centered at
520 nm. We recall that the transparency of the SWNT electrode (40 nm thick) at this wavelength
is about 87% according to the transmittance spectra in Figure5. 3d. The current-voltage curve of
the OLED was recorded in Figure5. 5c with a Keithley 2400 source-meter. The current density,
derived using a device area of 2 mm
2
, showed a monotonic but nonlinear increase with the
voltage bias and reaches 0.7 mA/cm
2
at 20 V. An increase in brightness was accompanied with
increasing current density, as measured using a Newport optical meter (Model 1835C). Detailed
luminance characterization showed a threshold voltage of 5 V and a brightness of 17 cd/m
2
at 20
69
V (Figure5. 5d). Figure5. 5e plots the quantum efficiency as a function of voltage bias, which
varied between 0.21% and 0.34% within a wide bias range from 0.6 to 20 V.
All the OLED devices based on P3 nanotube films exhibited high stability and long
lifetime, as no degradation in light emission was observed within four to five hours. We stress
that this represents a lower limit imposed by the measurement time we used, while the device
lifetime can be much longer than 4-5 hours. In contrast, similar devices have been made with
HiPCO nanotube films, and they typically exhibited a lifetime shorter than 30 seconds before
they became either open or short circuits. This remarkable difference is a combined effect of the
difference in surface roughness and sheet conductance. As shown in Figure5. 2, HiPCO films are
typically much rougher than P3 films, and the “bumps” in the HiPCO films can easily lead to
local heating and filament formation, and eventually result in thermal damage and short/open
circuits. The relatively high sheet resistance of the HiPCO films may further hamper the
reliability of the OLED devices, as higher voltage is needed to operate the HiPCO-based OLED
devices than the P3-based counterparts. In addition, we note that even for devices based on P3
nanotube films, the observed current density and brightness are lower than those of typical ITO-
based OLEDs by 1-2 orders of magnitude made in our own lab. This may be related to both the
higher sheet resistance of the nanotube films as well as the lower work function of nanotubes (~
4.5 eV for nanotubes v.s. ~4.8 eV for ITO), which leads to a higher hole-injection barrier (as
shown in the energy diagram in Figure5. 5a inset) and also accounts for the suppressed current
density and brightness observed in our studies. Extensive chemical approaches are being
investigated in order to further reduce the sheet resistance and effectively modify the electrical
properties of the SWNT films. We are also exploring the use of other deposition methods for the
molecular organic materials, such as organic vapor phase deposition, which give conformal
coatings on highly irregular surfaces, such as the bare SWNT films (i.e. not coated with PEDOT-
70
PSS). Optimization of the device structures should eventually lead to nanotube-film-based
OLEDs with performance comparable to that of ITO-based OLEDs.
In summary, we have successfully demonstrated the preparation and optimization of
highly transparent SWNT films, which were further exploited as the hole-injection electrodes for
OLEDs on both rigid glass and flexible substrates. Our experiments reveal that the choice of
material is critical for the success of the application, as films based on arc discharge nanotubes
are overwhelmingly better than films based on HiPCO nanotubes in all the critical aspects,
including the surface roughness, sheet resistance, and transparency. Further improvement in arc-
discharge nanotube films has been achieved by using PEDOT passivation for better surface
smoothness and using SOCl
2
doping for lower sheet resistance. The optimized films show a
typical sheet resistance of ~160 Ω/ □ at 87% transparency and have been successfully used to
make OLEDs with high stability and long lifetime. Our work reveals the importance of
controlling the surface roughness and conductance of nanotube films, and may help to pave the
way for systematic studies on using commercial nanotubes as transparent conductive electrodes
for applications including organic light-emitting diodes and organic photovoltaic devices.

71
Chapter 5. References

1. Chiang, I.W., et al., Purification and characterization of single-wall carbon nanotubes
(SWNTs) obtained from the gas-phase decomposition of CO (HiPco process). Journal of
Physical Chemistry B, 2001. 105(35): p. 8297-8301.
2. Haddon, R.C., et al., Purification and separation of carbon nanotubes. Mrs Bulletin,
2004. 29(4): p. 252-259.
3. Fournet, P., et al., Enhanced brightness in organic light-emitting diodes using a carbon
nanotube composite as an electron-transport layer. Journal of Applied Physics, 2001.
90(2): p. 969-975.
4. Fournet, P., et al. A carbon nanotube composite as an electron transport layer for M3EH-
PPV based light-emitting diodes. 2001: Elsevier Science Sa.
5. Ha, Y.G., et al. Fabrication and characterization of OLEDs using MEH-PPV and
SWCNT nanocomposites. 2005: Elsevier Science Sa.
6. Kazaoui, S., et al., Near-infrared electroluminescent devices using single-wall carbon
nanotubes thin flms. Applied Physics Letters, 2005. 87(21): p. 3.
7. Kim, J.Y., M. Kim, and J.H. Choi. Characterization of light emitting devices based on a
single-walled carbon nanotube-polymer composite. 2003: Elsevier Science Sa.
8. Woo, H.S., et al., Hole blocking in carbon nanotube-polymer composite organic light-
emitting diodes based on poly (m-phenylene vinylene-co-2,5-dioctoxy-p-phenylene
vinylene). Applied Physics Letters, 2000. 77(9): p. 1393-1395.
9. Xu, Z.H., et al., Carbon nanotube effects on electroluminescence and photovoltaic
response in conjugated polymers. Applied Physics Letters, 2005. 87(26): p. 3.
10. Zhou, Y.X., L.B. Hu, and G. Gruner, A method of printing carbon nanotube thin films.
Applied Physics Letters, 2006. 88(12): p. 3.
11. Romero, D.B., et al., A carbon nanotube organic semiconducting polymer heterojunction.
Advanced Materials, 1996. 8(11): p. 899-&.
12. Zhang, M., et al., Strong, transparent, multifunctional, carbon nanotube sheets. Science,
2005. 309(5738): p. 1215-1219.
13. Deheer, W.A., et al., Aligned Carbon Nanotube Films - Production and Optical and
Electronic-Properties. Science, 1995. 268(5212): p. 845-847.
14. Bekyarova, E., et al., Electronic properties of single-walled carbon nanotube networks.
Journal of the American Chemical Society, 2005. 127(16): p. 5990-5995.
15. Thess, A., et al., Crystalline ropes of metallic carbon nanotubes. Science, 1996.
273(5274): p. 483-487.
72
Chapter 6 High-Performance metal oxide Nanowire Chemical Sensors

6.1 Overview of metal oxide chemical sensors
Chemical sensors[1-13] based on various metal oxide nanowires have stimulated a lot of
interest due to their quasi one-dimensional structures with ultra high surface-to-volume ratios and
semiconducting conductance that can be easily modulated by the surrounding gas molecules. For
instance, metal oxide nanowires such as ZnO nanowires[2, 5, 9], SnO
2
nanobelts[1], SnO
2

nanowires[3, 10], and In
2
O
3
nanowires[6, 7, 12, 13] have been employed to detect a wide variety
of chemicals, parallel to the advance in nanotube chemical sensing development.[4, 8] In
particular, indium oxide nanowires are known to be one of the best materials that have been
shown to detect various oxidizing and reducing gases as O
3
, NO
2
, and NH
3
.[6, 7, 12, 13]
However, metal oxide nanowire sensors usually cannot detect low concentrations of some other
important gases when operated at room temperature, such as ethanol, CO and hydrogen, which
are important for public safety, health care, environmental monitoring, and industrial applications.
Operating the nanosensors at elevated temperatures with minimal inconvenience and low power
consumption is therefore extremely important for practical applications of the metal oxide
nanowires. Recently, SnO
2
nanobelts have been deposited to bridge suspended SiN membranes
with microfabricated heating electrode for successful detection of NO
2
and dimethyl
methylphosphonate (DMMP)[14], and a SnO
2
nanowire sensor has been fabricated on a micro
heater consisting of a polysilicon heating electrode embedded in two layer of SiO
2
[15]. Both
approaches utilized sophisticated fabrication and focused ion beam deposition for electrical
contact. Therefore any improvement or simplification of the fabrication is still highly desired for
the cost-conscious chemical sensing application.

73
6.2 Nanowire Chemical sensors with micro-machined hotplates
Here, we report the facile integration of nanowire chemical sensors with micromachined
hotplates built on SiN membranes. This was achieved by simultaneous fabrication of both the
nanowire chemical sensors and the platinum heating electrode on SiN membranes atop silicon
wafers via one-step metallization, which can offer a wide spectrum of advantages such as cost-
effective and scalable fabrication, easy temperature control, minimal thermal budget, improved
sensitivity, fast response and fast recovery. Our approach allowed us to vary the device
temperature from room temperature to 350
o
C by tuning current flow through the platinum heater
with very low power consumption due to the minimized thermal mass of the membrane structure.
In addition, systematic study has been performed for the detection of ethanol at various
temperatures and gas concentrations. We have detected ethanol down to 1 ppm concentration at
an operation temperature of 275
o
C. These nanosensors with integrated hot plates have been
further exploited for the detection of CO and hydrogen down to concentrations of 10 ppm and 50
ppm, respectively.
The fabrication of nanowire sensors with integrated hot plates started with the preparation
of SiN membranes. This process began by coating double-side polished Si wafers with 100 nm
SiN using low pressure chemical vapor deposition (LPCVD). The SiN film on the backside was
then selectively etched using photolithography followed by CF
4
reactive ion etch (RIE).
Anisotropic wet etching of silicon through the openings was performed in boiling 40 wt. % KOH
solution, which led to the formation of 100 nm thick SiN membranes of 500 m × 500 m in 　
size on the front side of the wafers. A schematic diagram of a suspended SiN membrane is shown
in Figure6.1a. For the fabrication of nanowire devices on SiN membranes, In
2
O
3
nanowires were
first synthesized using a laser ablation method, and details can be found in our previous
publications[6, 7, 12, 13]. In
2
O
3
nanowires were then sonicated into a suspension in isopropanol
and deposited onto the membrane-side of the substrates until a reasonable density of nanowires
was reached. Standard photolithography was employed to pattern both the heating electrode and
contacting electrodes for the nanowires on top of the SiN membranes, followed by deposition of
platinum using e-beam evaporation. The SiN membrane thermally isolated the heated sensing
area from the silicon chip frame and led to minimized heat loss through the conduction of Si
substrate. Figure6.1b shows the photography of a 3 × 3 array of chemical sensor chips,
illustrating the power of batch fabrication. The bright squares correspond to the SiN membranes,
which are surrounded by electrodes connecting the active area with bonding pads. Figure6.1c is a
scanning electron microscope (SEM) image of the active area of one chemical sensor chip, where
the dashed box indicates the SiN membrane. The spacing between the heating electrode and the
contact electrodes was designed to be larger than most nanowires to eliminate unwanted bridging
of the dispersed nanowires. In contrast, the spacing between the contact electrodes was designed
to be 3 µm so that we can find many adjacent electrodes with bridging nanowires. Figure6.1d
shows one such device with one nanowire bridging two electrodes, which can be used as a
chemical sensor for subsequent studies. We used the same chemical sensing setup as in our
previous work[6, 7, 12, 13].
The fabrication of the nanosensor chips was followed by in-depth characterization of the
micromachined hotplates. We applied different voltages ranging from 0 V to 10 V to the Pt
heating electrode with the sensor chip sitting in air, and the resistance of the Pt heater was
measured and converted to the corresponding temperature. Figure6.2a plots the calculated hot
plate temperature as a function of the applied voltage, and one can clearly see that temperatures
as high as 350 °C can be easily reached with a moderate voltage of 10 V applied to the Pt heater.
In addition, the hot plate temperature exhibited a linear dependence on the applied voltage for
values between 3 V and 10 V, which can be fitted empirically as 911 . 17 467 . 37 − = V T . This
linear dependence can facilitate easy temperature control and calibration. Figure6.2a inset
displays the measured Pt heater resistance v.s. the calculated temperature. To further evaluate the
74
hot plate performance, we have measured the hot plate temperature as a function of the power
consumption of the Pt heater, as shown in Figure6.2b. In real sensing devices, only 60 mW of
power is enough to raise the heater temperature up to 300 °C in 1 minute. This minimal power
consumption stems from the ultra low thermal mass and also the reduced thermal dissipation of
the suspended SiN membrane. This represents a significant advantage of the micromachined
hotplate design, as compared to previously reported nanowire sensors fabricated atop ceramic
tubing with exterior heater[16, 17].

Figure 6.1 (a) Schematic diagram of a micromachinced heater on a suspended SiN membrane. (b) Photograph of a 3 ×
3 array of chemical sensor chips. Inset: photograph showing the SiN membrane with a micromachined heater and
sensing electrodes. (c) SEM image of the active area of one chemical sensor chip, where the dashed box indicates the
SiN membrane. (d) SEM image of a sensing device with a nanowire bridging two electrodes.

We have further studied the conductance of an In
2
O
3
nanowire sensor as a function of the
hotplate temperature, and a surprising nonmonotonic behavior was observed, as shown in
75
Figure6.2c. The nanowire conductance increased with increasing temperature from room
temperature to about 125 °C, and then decreased when the temperature varied from 125 °C to 350
°C. The complicated behavior is likely the consequence of several competing factors, the first of
which is the increase of carrier concentration in semiconducting In
2
O
3
due to thermal excitation.
An additional factor is the removal of moisture from the nanowire surface as temperature
increased from room temperature to 100 °C and above. The above-mentioned two factors would
contribute to the increase of the nanowire conductance. As temperature went beyond 125 °C with
the devices operating in air, we expect the effect is similar to annealing In
2
O
3
nanowires in an
oxygen-rich environment, which would lead to reduced electron concentration in the n-type In
2
O
3

nanowire and hence reduced conductance[16].

Figure 6.2 (a) Hot plate temperature as a function of the applied voltage. Inset: the measured Pt heater resistance
versus the calculated temperature. (b) Hot plate temperature as a function of the power consumption of the Pt heater.
(c) Conductance change of an In
2
O
3
nanowire sensor as a function of the hotplate temperature, where the sensor chip is
placed in air and in argon (inset), respectively.

76
We note that the enhanced reactivity toward surrounding gas molecules at elevated
temperatures can lead to improved sensitivity, and operating the nanosensors at temperatures
above 100 °C can eliminate the complicated effect of moisture and facilitate robust and reliable
operation in air. Control experiments were also carried out in pure argon environment with the
nanowire conductance measured at various temperatures. Figure6.2c inset clearly shows that the
nanowire conductance increased monotonically with increasing temperature, as a result of the
increased carrier concentration due to thermal excitation, and the removal of adsorbed water and
oxygen molecules from the surface.

Figure 6.3 (a) and (b) Sensing response of an In
2
O
3
nanowire sensor to 100 ppm ethanol diluted in air with the hotplate
controlled at different temperatures. The normalized conductance change ( ΔG/G) of an In
2
O
3
nanowire is plotted as a
function of time (a) and as a function of temperature (b), respectively. (c) and (d) Sensing response of an In
2
O
3

nanowire sensor operated at 275 °C to four different ethanol concentrations (1, 10, 50, and 100 ppm). The normalized
conductance change ( ΔG/G) of an In
2
O
3
nanowire is plotted as a function of time (c) and as a function of concentration
(d), respectively.

To fully reveal the potential of the nanosensors with integrated hotplates, we have
selected ethanol, carbon monoxide, and hydrogen as our targets species to be detected. These gas
77
78
molecules are important for health care, environmental monitoring and industrial applications;
however, they usually cannot be detected using metal oxide film or nanowire sensors at room
temperature. To mimic practical sensing environment, the nanosensor conductance was first
measured in air, and then the air flow was replaced by ethanol, CO or hydrogen carried in air.
Figure6.3a shows the sensing response of an In
2
O
3
nanowire sensor to 100 ppm ethanol diluted in
air with the hotplate controlled at five different temperatures. The change in nanowire
conductance ( ΔG) normalized by its initial conductance (G) is plotted as a function of time in this
figure. Before exposure to ethanol vapor, the nanowire conductance was fully stabilized for 200
seconds at each temperature to ensure accurate chemical sensing. At the operating temperature of
100 °C, the conductance of the nanowire sensor exhibited no change even after exposure to
ethanol vapor. Similarly very little change was observed with the device operated at 125 °C;
however, the device exhibited pronounced increase in conductance when operated at temperatures
above 150 °C, as shown in Figure6.3a. This temperature-dependent sensing highlights the
importance of the micromachined hotplates and is easy to understand. It is well known that
oxygen molecules can adsorb to various metal oxide surfaces and form oxygen ions such as O
2
-
,
O
-
, O
2-
, which leads to a reduction in electron concentration in the typically n-type
semiconductors. Upon exposure to ethanol vapor, ethanol reacts with the adsorbed oxygen ions
on the In
2
O
3
nanowire surface and releases electrons back to the nanowire, therefore resulting in
enhanced conductance. Thus, higher temperatures can lead to improved sensitivity due to
increased reactivity between adsorbed oxygen and ethanol molecules.
To further demonstrate the effect of temperature, normalized sensing response ( ΔG/G) to
100 ppm ethanol was plotted versus temperature in Figure6.3b. As expected, the nanowire sensor
exhibited little response for operation temperatures below 150 ºC, whereas significant change in
conductance was observed at higher temperatures. The normalized sensing response was about
1.0 for the nanowire sensor exposed to 100 ppm ethanol at 200 ºC when only 40 mW heating
power was applied. In addition, higher operation temperatures led to both fast response and fast
recovery. As revealed in Figure6.3a, when the nanosensor was operated at 275 ºC, the response
time corresponding to a conductance increase up to 90% of the saturated value[18] was about 22
seconds upon introduction of 100 ppm ethanol at t = 200 seconds, while the time it took for the
conductance to decrease to 90% of the saturated value is 10 seconds when the ethanol exposure
was replaced by air flow at t = 700 seconds.

Figure 6.4 (a) and (b) Sensing response of an In
2
O
3
nanowire sensor operated at 275 °C to 10, 50 and 100 ppm CO
carried in air (a), while the sensing response to 50 and 100 ppm hydrogen is shown in (b).

Further experiments with various concentrations were performed at 275 ºC to explore the
sensing characteristics, and the results are shown Figure6.3c and d. Even for 1 ppm ethanol
carried in air, a distinguishable conductance change was observed with a normalized sensing
response of 0.14. This sensitivity of 1 ppm compares favorably with the reported detection limit
of ethanol from various metal oxide film or nanowire sensors[19, 20]. In addition, with higher
concentrations of ethanol used, more pronounced conductance modulation was observed, as
revealed in Figure6.3c for 10 ppm, 50 ppm and 100 ppm ethanol in air. The normalized sensing
response was extracted from Figure6.3c and replotted v.s. ethanol concentration in Figure6.3d.
Qualitatively one can see that the sensing response increased monotonically with concentration
and exhibited somewhat linear dependence for this low concentration regime.
79
80
Our nanosensing platform can be readily applied to the detection of other flammable or
explosive gases, such as CO, hydrogen, and various hydrocarbons. Figure6.4a shows the
response of an In
2
O
3
nanowire sensor operated at 275 ºC to 10, 50 and 100 ppm CO carried in air,
while the sensing response to 50 and 100 ppm hydrogen is summarized in Figure6.4b,
respectively. Carbon monoxide reacts with pre-absorbed oxygen species like O
2-
to form carbon
dioxide: CO
(g)
+ O
2-
→ CO
2(g)
+ e
-
, therefore resulting in an increase of conductance in the n-
type In
2
O
3
nanowire. Detailed examination showed a normalized conductance change of ~ 5% for
10 ppm of CO, with a response time of tens of seconds. This detection limit is very close to the
lowest level so far achieved with various metal oxide film or nanowire sensors[21, 22].

Furthermore, high performance sensing was also achieved for hydrogen, as even 50 ppm
hydrogen exposure led to a dramatic increase in the nanowire sensor conductance with ΔG/G ~
0.5, as shown in Figure6.4b. The detection limit of H
2
can be down to several ppm levels given
that the noise level of nanowire sensor is around 1% of conductance.
In summary, we have developed nanowire chemical sensors with integrated
micromachined hotplates built on SiN membranes. Pronounced sensing response was observed
for operation temperatures above 150
o
C, and a good sensitivity of 1 ppm ethanol was established
at 275
o
C. We have further successfully detected carbon monoxide and hydrogen at an operation
temperature of 275
o
C down to concentrations of 10 ppm and 50 ppm, respectively.

81
Chapter 6. References

1. Comini, E., et al., Stable and highly sensitive gas sensors based on semiconducting oxide
nanobelts. Applied Physics Letters, 2002. 81(10): p. 1869-1871.
2. Fan, Z.Y., et al., ZnO nanowire field-effect transistor and oxygen sensing property.
Applied Physics Letters, 2004. 85(24): p. 5923-5925.
3. Kolmakov, A., et al., Detection of CO and O-2 using tin oxide nanowire sensors.
Advanced Materials, 2003. 15(12): p. 997-+.
4. Kong, J., et al., Nanotube molecular wires as chemical sensors. Science, 2000.
287(5453): p. 622-625.
5. Law, M., et al., Photochemical sensing of NO2 with SnO2 nanoribbon nanosensors at
room temperature. Angewandte Chemie-International Edition, 2002. 41(13): p. 2405-
2408.
6. Li, C., et al., Surface treatment and doping dependence of In2O3 nanowires as ammonia
sensors. Journal of Physical Chemistry B, 2003. 107(45): p. 12451-12455.
7. Li, C., et al., In2O3 nanowires as chemical sensors. Applied Physics Letters, 2003.
82(10): p. 1613-1615.
8. Li, J., et al., Carbon nanotube sensors for gas and organic vapor detection. Nano Letters,
2003. 3(7): p. 929-933.
9. Li, Q.H., et al., Oxygen sensing characteristics of individual ZnO nanowire transistors.
Applied Physics Letters, 2004. 85(26): p. 6389-6391.
10. Sysoev, V.V., et al., Toward the nanoscopic "electronic nose": Hydrogen vs carbon
monoxide discrimination with an array of individual metal oxide nano- and mesowire
sensors. Nano Letters, 2006. 6(8): p. 1584-1588.
11. Sysoev, V.V., et al., A gradient microarray electronic nose based on percolating SnO2
nanowire sensing elements. Nano Letters, 2007. 7(10): p. 3182-3188.
12. Zhang, D.H., et al., Detection of NO2 down to ppb levels using individual and multiple
In2O3 nanowire devices. Nano Letters, 2004. 4(10): p. 1919-1924.
13. Zhang, D.J., et al., Doping dependent NH3 sensing of indium oxide nanowires. Applied
Physics Letters, 2003. 83(9): p. 1845-1847.
14. Yu, C., et al., Integration of metal oxide nanobelts with microsystems for nerve agent
detection. Applied Physics Letters, 2005. 86(6): p. 3.
15. Meier, D.C., et al., Coupling nanowire chemiresistors with MEMS microhotplate gas
sensing platforms. Applied Physics Letters, 2007. 91(6): p. 3.
82
16. Chu, X.F., et al., Ethanol sensor based on indium oxide nanowires prepared by
carbothermal reduction reaction. Chemical Physics Letters, 2004. 399(4-6): p. 461-464.
17. Xue, X.Y., et al., Synthesis and ethanol sensing properties of ZnSnO3 nanowires.
Applied Physics Letters, 2005. 86(23): p. 3.
18. Virji, S., et al., Polyaniline nanofiber gas sensors: Examination of response mechanisms.
Nano Letters, 2004. 4(3): p. 491-496.
19. Makhija, K.K., et al., Indium oxide thin film based ammonia gas and ethanol vapour
sensor. Bulletin of Materials Science, 2005. 28(1): p. 9-17.
20. Wan, Q., et al., Fabrication and ethanol sensing characteristics of ZnO nanowire gas
sensors. Applied Physics Letters, 2004. 84(18): p. 3654-3656.
21. Chen, Y.J., C.L. Zhu, and G. Xiao, Reduced-temperature ethanol sensing characteristics
of flower-like ZnO nanorods synthesized by a sonochemical method. Nanotechnology,
2006. 17(18): p. 4537-4541.
22. Xue, X.Y., et al., Electronic transport characteristics through individual ZnSnO3
nanowires. Applied Physics Letters, 2006. 88(18): p. 3.

83
Chapter 7 Conclusion

7.1 Summary
The synthesis and assembly of aligned carbon nanotubes, and their applications in both
nano-electronics and macro-electronics have been demonstrated. In addition, the high
performance chemical sensor using metal oxide nanowire has been discussed.
Chapter1 presented a brief introduction of carbon nanotube, followed by discussion of a
new synthesis technique using nanosphere lithography to grow highly aligned single-walled
carbon nanotubes atop quartz and sapphire substrates. Chapter3 introduced the wafer-scale
integration and assembly of aligned carbon nanotubes, including full-wafer scale synthesis and
transfer of massively aligned carbon nanotube arrays, and nanotube device fabrication on 4 inch
Si/SiO
2
wafer to yield submicron channel transistors and CMOS integrated circuits. In addition,
carbon nanotube flexible electronics and smart textiles for ubiquitous computing and sensing
were demonstrated in chapter4. A facile transfer printing technique has been introduced to
transfer massively aligned single-walled carbon nanotubes from the original sapphire/quartz
substrates to virtually any other substrates, including glass, silicon, polymer sheets, and even
fabrics. In chapter5, I presented the study of transparent conductive thin films made with two
kinds of commercial carbon nanotubes: HiPCO and arc-discharge nanotubes. These films have
been further exploited as hole-injection electrodes for organic light emitting diodes on both rigid
glass and flexible substrates. Lastly, I presented the fast and scalable integration of nanowire
chemical sensors with micromachined hotplates built on SiN membranes. These nanosensors with
integrated hot plates have been exploited for the detection of ethanol, CO and hydrogen down to
concentrations of 1 ppm, 10 ppm and 50 ppm, respectively.

7.2 Future work
In this dissertation, I have successfully shown integrated carbon nanotube circuits such as
NAND and NOR logic gates. However, there is one important technology to be achieved to get n-
type device for advanced CMOS integrated nanotube circuits such as ring-oscillators, decoders,
and shifters.

Figure 7.1 Metal contact Engineering. a) Schematic diagrams of n-type transistor with Gd contacts. b) I-Vg curves of
a n-type nanotube transistor before and after electrical breakdown. c), d) I-V
g
and I-V
ds
family of the transistor in
Figure b, respectively.

CMOS logic can be an ideal candidate and the principle technology for CMOS such as
air-stable n-type transistor needs to be studied. The existing strategies for fabricating n-type
SWNTFETs can be classified into two categories such as the chemical doping and the metal
contact engineering. In the chemical doping, electron dopants such as alkali metals or polymers
84
85
are introduced to the nanotubes. The second approach entails engineering the contact barrier to
achieve a lower Schottky barrier for electron transport into the conduction bands of the nanotubes.
However, in practice, the chemical doping are vulnerable to oxidation and the work function of
the metal surface is likely to increase upon oxidation under ambient air. Therefore, achieving
long-term stability of n-type operation under ambient conditions remains a great challenge.
Therefore, combining both metal contact engineering and SiO
2
passivation for long-term
stability, air-stable n-type devices and their application for CMOS circuits need to be studied.
Figure7.1 show schematic diagram and preliminary results of n-type contact device.

86
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Abstract (if available)

Abstract This dissertation presents the synthesis and assembly of aligned carbon nanotubes, and their applications in both nano-electronics such as transistor and integrated circuits and macro-electronics in energy conversion devices as transparent conducting electrodes. Also, the high performance chemical sensor using metal oxide nanowire has been demonstrated.

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Asset Metadata

Creator Ryu, Koungmin (author)

Core Title Synthesis, assembly, and applications of single-walled carbon nanotube

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Materials Science

Publication Date 09/25/2009

Defense Date 08/12/2009

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag assembly,carbon nanotube,circuits,Energy,OAI-PMH Harvest,synthesis,transistor

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Zhou, Chongwu (committee chair), Goo, Edward K. (committee member), Kim, Eun Sok (committee member)

Creator Email koungmin@gmail.com,koungryu@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-m2616

Unique identifier UC1133237

Identifier etd-Ryu-3223 (filename),usctheses-m40 (legacy collection record id),usctheses-c127-255873 (legacy record id),usctheses-m2616 (legacy record id)

Legacy Identifier etd-Ryu-3223.pdf

Dmrecord 255873

Document Type Dissertation

Rights Ryu, Koungmin

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Repository Name Libraries, University of Southern California

Repository Location Los Angeles, California

Repository Email cisadmin@lib.usc.edu