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Unfalsified adaptive control with reset and bumpless transfer

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Unfalsified adaptive control with reset and bumpless transfer

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Content UNFALSIFIED ADAPTIVE CONTROL WITH RESET AND BUMPLESS TRANSFER by Sagar V. Patil A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulllment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) August 2016 Copyright 2016 Sagar V. Patil This Dissertation Is Dedicated To My Parents My Sister, Ashwini And My Beloved Wife, Veda i Acknowledgments I would like to express my sincere gratitude to my Ph.D. advisor, Professor Michael Safonov. I greatly appreciate the inspiration, motivation, and guidance provided to me by him. I learned a lot and gained invaluable experience through the discussions with him during my research work. I thank my thesis readers, Professor Firdaus Udwadia and Professor Ashutosh Nayyar. I also thank Professor Rahul Jain and Professor Paul Bogdan for serving on my qualication examination committee. I thank my friend Yu- Chen Sung for his contributions to my research work at USC. My deepest thanks to my family specially my mother Mrs. Surekha Patil, my father Mr. Vinayak Patil, my sister Dr. Ashwini Patil-Narkhede, my brother-in-law Dr. Sohan Narkhede, and my wife Mrs. Veda Patil for their understanding, patience, support, and love. ii Contents Dedication i Acknowledgments ii List of Figures v Abbreviations vii Abstract viii Chapter 1: Introduction 1 1.1 Review and Signicance of Related Previous Work . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 Outline of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Chapter 2: Preliminaries 6 2.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 3: Problem Formulation 14 3.1 Adaptive Switching Control System . . . . . . . . . . . . . . . . . . . . . 14 3.2 Controller Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1 Fictitious Signal Generator . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 Hysteresis Algorithm with Reset Condition . . . . . . . . . . . . . 18 3.3.2 Generalized Cost Function V . . . . . . . . . . . . . . . . . . . . . 21 3.3.3 Bumpless Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 4: Main Results 28 4.1 Generalized Bumpless Transfer . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1 Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.2 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.3 Types of Correction Signal u . . . . . . . . . . . . . . . . . . . . . 29 iii 4.1.4 Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3 Fictitious Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4 Reset Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4.1 Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4.3 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Chapter 5: Simulation Example 44 5.1 Nonlinear Time-Varying Plant . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2 Candidate LTI PI Controllers . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3 MATLAB Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.4 Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 6: Conclusion 52 Appendix A Proof of Lemma 2.1 54 Appendix B Proof of Lemma 2.2 56 Appendix C Proof of Theorem 4.1 58 Appendix D Proof of Lemma 4.1 60 Appendix E Proof of Theorem 4.2 62 Appendix F Proof of Lemma 4.3 65 Appendix G Proof of Lemma 4.4 67 Appendix H Proof of Theorem 4.3 69 Bibliography 71 iv List of Figures 2.1 System T with input r and output w. . . . . . . . . . . . . . . . . . . . . 8 2.2 Closes loop system (K;P ) with input r and output consisting of a controller K to control plant P . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Adaptive switching control system ( ^ K;P ) having supervisorS and can- didate controllers set K =fK 1 ;K 2 ;:::;K N g to control unknown plant P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Realization of a nonlinear candidate controller K = P r K K 2 K mapping [r ] 0 into u K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 Realization of a nonlinear controller K2K using its left Matrix Fraction Description (MFD) pair (N K ;D K ). . . . . . . . . . . . . . . . . . . . . . . 17 3.4 SupervisorS mapping [ r] 0 into switching signal ^ K and correction signal u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 Hysteresis algorithm (HA) with reset condition (RC) having hysteresis logic (HL) to compare cost functions V M of all controllers. . . . . . . . . . 18 3.6 Fictitious closed loop system (K;P ) with performance weights ofV (K;;t). 22 3.7 Switching time dependent bumpless transfer system B . . . . . . . . . . 25 3.8 Adaptive switching control system ( ^ K;P ) with the realization of a con- trollerK switched on at time and supervisorS (consisting the hysteresis algorithm with reset condition and bumpless transfer system). . . . . . . . 26 4.1 Switching time dependent bumpless transfer system B mapping [r ] 0 into the correction signal u . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 Block diagram of bumpless transfer system B mapping [r ] 0 into u consist of window system W 1 and system ~ B . . . . . . . . . . . . . . . . 33 5.1 Adaptive switching control system ( ^ K;P ) to control nonlinear time- varying plant P using LTI PI controllers K 1 and K 2 . . . . . . . . . . . . . 44 v 5.2 Case 1: Simulation results for hysteresis algorithm with reset condition and bumpless transfer (Algorithm 4.1). . . . . . . . . . . . . . . . . . . . . 49 5.3 Case 2: Simulation results for hysteresis algorithm with reset condition. . 50 5.4 Case 3: Simulation results for hysteresis algorithm (Algorithm 3.1). . . . . 51 6.1 Closed loop system (K;P ). . . . . . . . . . . . . . . . . . . . . . . . . . 60 vi Abbreviations BHMT : Battistelli-Hespanha-Mosca-Tesi LTI : Linear Time Invariant LTV: Linear Time-Varying MFD : Matrix Fraction Description HA : Hysteresis Algorithm HL : Hysteresis Logic RC : Reset Condition BT : Bumpless Transfer PI : Proportional Integral vii Abstract In this thesis, the BHMT (Battistelli-Hespanha-Mosca-Tesi) reset mechanism which is a new scheme to control time-varying plant under the framework of unfalsied adaptive control is investigated. The reset condition is modied and the switching algorithm is improved to admit bumpless transfer at switching times, and to relax several restrictive assumptions. The reset condition is designed based on the gains of the control system components, making it adaptive, free of uncertain parameters, and practically imple- mentable in a switching algorithm. Performance including stability is proved given only that the adaptive stabilization problem is feasible, removing the assumptions that the plant and controller are linear, and relaxing restrictions on controller state-initialization at switching times so as to allow bumpless transfer. Theoretical results are established considering proposed framework of switching time dependent generalized bumpless trans- fer system for switching of a controller. The proposed switching algorithm is nonlinear time-varying and it can control nonlinear time-varying plant using nonlinear controllers. An example is provided to support improved results. viii Chapter 1 Introduction 1.1 Review and Signicance of Related Previous Work The hysteresis algorithm [Morse et al., 1992], the stability overlay algorithm [Rosa et al., 2011], and the increasing cost level algorithm [Jin and Safonov, 2012] are all examples of adaptive switching control algorithms that can be interpreted within the theoretical framework of unfalsied adaptive control. These algorithms are equivalent in some way as shown in [Jin et al., 2011b]. But without modications these algorithms are not suitable for controlling a time-varying plant. If a plant to be controlled changes so much that an active controller no longer maintains a performance then a switch is necessary. The problem with these algorithms is that they use cost functions with in- nite memory which give equal importance to every element of the measured data no matter how old the data. In order to extend the results of unfalsied adaptive control to time-varying systems, one solution introduced in [Jin et al., 2011a] is to use a non- monotone cost function with the fading memory data. In the same context, another novel scheme proposed in [Battistelli et al., 2013] and [Battistelli et al., 2014] by Battis- telli, Hespanha, Mosca, and Tesi (BHMT) is a reset mechanism. But BHMT is the rst one to analyze the adaptive stabilization of a time-varying plant quantitatively. This innovative idea (reset mechanism) uses the fading memory data to evaluate the mono- tone cost function over the most recent memory time-window. The length of memory time-window is decided adaptively by a so called reset condition. This approach allows the supervisor to understand the most recent behavior of time-varying plant as well as to learn the most recent performance of each controller for time-varying plant and, without waiting for too long, selects an appropriate cost minimizing controller. 1 Roughly speaking whenever a controller is switched o we say it is falsied at the fal- sication cost level. In all the algorithms of [Morse et al., 1992], [Rosa et al., 2011], and [Jin and Safonov, 2012], this falsication cost level keeps on increasing with each switch and may tend to innity if the plant is time-varying. But use of the reset mechanism of [Battistelli et al., 2013] and [Battistelli et al., 2014] in switching algorithms prevents the falsication cost level from increasing to innity. The reset mechanism implementation in unfalsied adaptive control algorithms of [Morse et al., 1992], [Rosa et al., 2011], and [Jin and Safonov, 2012] is a great break- through which can solve an important problem of controlling unknown and time-varying plant. But we think it can be improved at some of the places, and so we intend to introduce some small improvements in it. 1.2 Motivation As mentioned before, in the recent developments of unfalsied adaptive control, Battis- telli, Hespanha, Mosca, and Tesi (BHMT) have come up with the idea of reset mecha- nism [Battistelli et al., 2013]. Their theoretical analysis proves that the adaptive system is stable under the hysteresis algorithm with reset mechanism. But this analysis has been built on the following unnecessary assumptions. The plant to be controlled is a strictly causal linear system of bounded order. Each candidate controller is linear. The initial conditions of the candidate controllers are not re-initialized or adjusted at switching times. We want to rebuild the theory of reset mechanism established by BHMT by discarding these restrictive assumptions. The reset condition must be adaptive in nature and should depend only on the control system. But on a certain level, the reset conditions in [Battistelli et al., 2013] 2 and [Patil et al., 2014] deviate from these constraints because they have a parameter, a designer can set with minimal restriction, but in reality it is system dependent. The papers [Battistelli et al., 2013] and [Patil et al., 2014] do not address how to calculate this parameter. The reason is that the theoretical procedures in [Battistelli et al., 2013] and [Patil et al., 2014] which lead to the reset conditions lag in considering the realiza- tions of the system components. So we intend to address this problem. Our work is needed to modify the reset conditions in [Battistelli et al., 2013] and [Patil et al., 2014] to make them practically implementable in a switching algorithm. In practice, sometimes it has been observed that whenever the reset mechanism is implemented in a switching algorithm it induces more switches. And we know that the abrupt switching inserts the undesired transients in the control signal. Therefore without bumpless transfer, the simulation results of [Battistelli et al., 2013] had very large transients. It is the motivation for us to use a bumpless transfer method to go beyond the wonderful work of [Battistelli et al., 2013]. We want to build the framework of bumpless transfer system applicable in direct adaptive switching control. We want the bumpless transfer system to be general in the sense that it should have exibility to make the control signal behave in any particular way as determined by designer. We need to build the switching algorithm based on the hysteresis logic of [Morse et al., 1992] to accommodate the modied reset condition and generalized bump- less transfer system at the switching times, applicable to the broad class of nonlinear controllers. 1.3 Contribution The contribution of this dissertation is the relaxation of several restrictive assumptions in the recent work of BHMT [Battistelli et al., 2013]. Among the assumptions that we relax are (i) the plant to be controlled is a strictly causal linear system of bounded order, (ii) each candidate controller is linear, and (iii) the initial conditions of the candidate 3 controllers are not re-initialized or adjusted at switching times. By discarding these assumptions this thesis aims to improve the theoretical results in [Battistelli et al., 2013], so that the only assumption required to prove stability of the adaptive system is that the adaptive stabilization problem is feasible. Another contribution of this dissertation is the formulation of a new and improved reset condition solely based on the gains of the system components, making it adaptive, free of uncertain parameters, and practically implementable in a switching algorithm. To derive this reset condition, this thesis aims to present theoretical stability results with the only assumption that the adaptive stabilization problem is feasible. This thesis presents the framework of a generalized bumpless transfer system appli- cable in direct adaptive switching control. This bumpless transfer system is switching time dependent and general, and hence can control the behavior of the control signal in many possible ways. Therefore the overall theoretical work is derived with the exibility to use generalized bumpless transfer system to manage undesired bumpy transients in the control signal. 1.4 Outline of the Dissertation This dissertation is organized as follows. Chapter 2 presents an overview of the preliminary denitions and notation used in the theoretical analysis. Chapter 3 formulates the problem. It talks about controller realization, supervisor consisting hysteresis algorithm with reset condition and switching time dependent bumpless transfer system, and generalized cost function having frequency depen- dent performance weights. Chapter 4 presents the main results about switching time dependent generalized bumpless transfer system, basic assumptions, bound on a ctitious input signal, the 4 modied and improved reset condition, adaptive switching algorithm, and stability of an adaptive switching control system. Chapter 5 provides a simulation example to support improved results due to reset mechanism and bumpless transfer. Chapter 6 covers conclusion of the presented work. 5 Chapter 2 Preliminaries 2.1 Notation In this thesis, we consider discrete time signals and systems. The notation and denitions mentioned hereafter will be used in theoretical results and supporting proofs. Z + : Set of non-negative integers R + : Set of non-negative real numbers jj : Absolute value [ ] 0 : Transpose de : Ceiling function y : Pseudo inverse z : Discrete time forward time-shift operator 2.2 Denitions Denition 2.1 (` pe Norm) For any real valued signal x dened onZ + and any t2Z + , the ` pe norm is dened as kxk `p[0;t] = p v u u t t X =0 jx()j p ; if p2 [1;1) and kxk `p[0;t] = max 2[0;t] jx()j; if p =1 6 Denition 2.2 (Stable Signal) A real valued signal x dened onZ + is said to be a stable signal if there exists %<1 such that8t> 0 we have 1 t kxk `p[0;t] = 1 t p v u u t t X =0 jx()j p %; if p2 [1;1) else kxk `p[0;t] = max 2[0;t] jx()j%; if p =1 Otherwise, x is said to be an unstable signal. Denition 2.2 implies that if a root mean p value of a signal is bounded then the signal is a stable signal. Denition 2.3 (` pe Norm) For any real valued signal x dened onZ + and any t2Z + , the ` pe norm is dened as kxk p[0;t] = p v u u t t X =0 p(t) jx()j p ; if p2 [1;1) and kxk p[0;t] = max 2[0;t] t jx()j; if p =1 where 2 (0; 1). The ` pe norm has the following properties. kxk p[0;t] kxk p[0;1] t+1 +kxk p[;t] ; 8t kxk p[0;] t kxk p[0;t] ; 8t 7 Lemma 2.1 For any real valued signalx dened onZ + , it holds8p2 [1;1],82 (0; 1), and8t2Z + that p p 1 p kxk p[0;t] kxk `1[0;t] sup 2[0;t] kxk p[0;] Proof. Refer Appendix A. Figure 2.1: System T with input r and output w. Denition 2.4 (` p Gain) [Zames, 1966] For the system T with input r and output w =Tr as shown in Fig. 2.1, the ` p gain is dened as kTk `p = sup krk `p[0;t] 6=0;t0 kTrk `p[0;t] krk `p[0;t] where p2 [1;1]. Denition 2.5 (` p Gain) For the system T with input r and output w =Tr as shown in Fig. 2.1, the ` p gain is dened as kTk p = sup krk p[0;t] 6=0;t0 kTrk p[0;t] krk p[0;t] where p2 [1;1] and 2 ( T ; 1) if T < 1, otherwise 2 (0; 1). 8 Lemma 2.2 If the system T shown in Fig. 2.1 is LTI system having an impulse response h(t) then the ` 1 gain is kTk 1 =kh k `1[0;1] where h (t) = h(t) t and 2 ( T ; 1) if T < 1, otherwise 2 (0; 1). Proof. Refer Appendix B. Denition 2.6 (ClassK Function) [Khalil, 2002] A function () :R + !R + is a classK function (2K) if it is continuous, (0) = 0, and strictly increasing. Denition 2.7 (ClassKL Function) [Khalil, 2002] A function(; ) :R + R + !R + is a classKL function (2KL) if it is continuous, classK function with respect to for each xed , and decreasing with respect to with lim !1 (; ) = 0 for each xed . Denition 2.8 (Stability) [Zames, 1966] The system T with input r and output w as shown in Fig. 2.1 is said to be stable if there exist 2K and constant 2R + such that for each stable input signal r and for all t 0 we have kwk `1[0;t] krk `1[0;t] + Otherwise, T is said to be unstable. 9 Denition 2.9 (Exponential Stability) [Sontag, 1989] The systemT with inputr and outputw as shown in Fig. 2.1 is said to be exponentially stable if there exist ;2K, constants 2R + and 2 (0; 1) such that for each stable input signal r and each pair of times t 0 we have kwk p[;t] krk p[0;1] t+1 + krk p[;t] + (2.1) Otherwise, T is said to be non-exponentially stable. The least possible for which (2.1) holds is called degree of exponential stability. Remark 2.1 Suppose the system T as shown in Fig. 2.1 is LTI system. Then Denition 2.9 implies that if the LTI system T is exponentially stable with degree then all the poles of the system T are inside the circle of radius . Suppose the system T with input r and output w as shown in Fig. 2.1 is LTI system having an impulse response h(t). Then the weighted output w of the system T can be expressed in terms of inversely weighted impulse response h and weighted input r as follows. 2 6 6 6 6 4 t w() . . . w(t) 3 7 7 7 7 5 = 2 6 6 6 6 4 h() h(1) . . . . . . h(t) t h(t+1) t+1 3 7 7 7 7 5 2 6 6 6 6 4 1 r(0) . . . r( 1) 3 7 7 7 7 5 t+1 + 2 6 6 6 6 4 h(0) 0 . . . . . . h(t) t h(0) 3 7 7 7 7 5 2 6 6 6 6 4 t r() . . . r(t) 3 7 7 7 7 5 (2.2) 10 Therefore, in case p =1, by taking the ` 1e norm of (2.2) and comparing it with (2.1), the LTI system T having an impulse response h(t) is said to be exponentially stable if there exist krk 1[0;t] = krk 1[0;t] =kTk 1 =kh k `1[0;1] where h (t) = h(t) t ; = 0; 2 (0; 1) such that for each stable input r and each pair of times t 0 we have kwk 1[;t] kTk 1 krk 1[0;1] t+1 +kTk 1 krk 1[;t] Denition 2.10 (Incremental Stability) [Stefanovic and Safonov, 2008] The systemT with inputr and outputw as shown in Fig. 2.1 is said to be incrementally stable if there exist;2K, constants 2R + and2 (0; 1) such that for every pair of stable input signalsr 1 ;r 2 with respective outputsw 1 ;w 2 and each pair of timest 0 we have kw 2 w 1 k p[;t] kr 2 r 1 k p[0;1] t+1 + kr 2 r 1 k p[;t] + Otherwise, T is said to be non-incrementally stable. Denition 2.11 (Asymptotic Stability) [Sontag, 1999] The systemT with inputr and outputw as shown in Fig. 2.1 is said to be asymptotically stable if there exist 2KL, 2K, constants 2R + and 2 (0; 1) such that for each stable input signal r and each pair of times t 0 we have kwk p[;t] (krk p[0;1] ;t + 1) +(krk p[;t] ) + Otherwise, T is said to be non-asymptotically stable. 11 + − Σ Figure 2.2: Closes loop system (K;P ) with input r and output consisting of a con- troller K to control plant P . Denition 2.12 (Unfalsication) [Safonov and Tsao, 1997] Exponential stability of the system (K;P ) with inputr and output as shown in Fig. 2.2 is said to be unfalsied by r and if there exist ;2K, constants 2 R + and 2 (0; 1) such that (2.1) holds; otherwise, it is said to be falsied by r and . According to Denition 2.12, it can be asserted that the system (K;P ) is exponentially stable if and only if its exponential stability is unfalsied by all possibler and. If it can be falsied byr and from even one experiment then is unstable. But if it is unfalsied by r and from one experiment then it cannot be concluded that is exponentially stable. Denition 2.13 ( Feasibility) Given 2 (0; 1), the adaptive stabilization problem for the system (K;P ) shown in Fig. 2.2 is said to be feasible if there exists at least one exponentially stabilizing controller K such that (2.1) holds according to Denition 2.9 with degree greater than . Any exponentially stabilizing controller K for the plant P in the system (K;P ) as shown in Fig. 2.2 is said to be feasible controller. 12 Denition 2.14 (Fictitious Reference Input Signal) [Safonov and Tsao, 1997] Given the data = [u y] 0 measured over the period [0;t] and a controller K, then its ctitious reference input signal ~ r K is a hypothetical reference input signal that would have exactly reproduced the measured data had the controller K been in the loop for the entire time period [0;t] over which the data were collected. Denition 2.15 (Cost-Detectability) [Wang et al., 2007] The pair (V;K) where V is non-negative real valued function of the controller K, data , and time t is said to be cost-detectable under the condition that exponential stability of the system (K;P ) shown in Fig. 2.2 is unfalsied by (r;) if and only if V (K;) is a stable signal. Denition 2.16 (Controller Falsication) [Stefanovic and Safonov, 2008] Given a pair (V;K) where V is non-negative real valued function of the controller K, data , and time t, the controller K is said to be falsied at the cost level at time t by the data = [u y] 0 measured over [0;t] if V (K;;t)> . Otherwise it is said to be unfalsied. The real parameter is called the falsication cost level. In Denition 2.15 and Denition 2.16, the data need not be collected with the controller K in the loop. It can be any open loop data of the plant P or it can be generated with any controller in the loop. 13 Chapter 3 Problem Formulation 3.1 Adaptive Switching Control System = 1 : Supervisor Σ 2 1 2 + + Figure 3.1: Adaptive switching control system ( ^ K;P ) having supervisor S and candi- date controllers setK =fK 1 ;K 2 ;:::;K N g to control unknown plant P . In general, an adaptive switching control system splits into two pieces namely super- visor and controller. As shown in Fig. 3.1, the supervisor S adaptively selects among the candidate controllers to control the plantP . In this thesis, we consider a data-driven adaptive switching control system; and hence the supervisorS uses an input-output data of the plantP and it does not need to have knowledge of the plant model. Therefore the plantP is considered as an unknown plant and it can be linear, nonlinear, time-invariant, time-varying, etc. But models of the plantP do play an important role in designing can- didate controllers. A switching algorithm in the supervisor S is nonlinear time-varying 14 because it is adaptive in nature. This makes an adaptive control law (supervisor S with all candidate controllers) nonlinear even if each controller K is linear, and hence the overall system is nonlinear. To formulate the problem, we consider the nonlinear system ( ^ K;P ) with reference input signalr as shown in Fig. 3.1. The plantP is considered as an unknown plant with zero initial state. The observed data of the plant P are denoted by = [uy] 0 . LetK be the set ofN nite number of nonlinear candidate controllers designed using some model of P . All the candidate controllers run in parallel with common input [r ] 0 . An output of a controllerK is denoted byu K . An active controller (connected in the loop) fromK at time t is denoted by ^ K(t). To select an active controller, the supervisor S generates a switching signal ^ K. At the same time, it generates a decaying correction signal u at each switching time to produce bumpless switch. 3.2 Controller Realization Σ + + − Σ K − + Σ y Figure 3.2: Realization of a nonlinear candidate controller K = P r K K 2 K mapping [r ] 0 into u K . 15 Without loss of generality, we decompose each candidate controller K2K as shown in Fig. 3.2. Generalizing [Morse, 1996] who considered only LTI controllers, each of our nonlinear controller K2K mapping [r ] 0 into u K is realized as u K = h P r K K i | {z } K 2 4 r 3 5 where K = h u K y K i is strictly causal, nonlinear, and exponentially stable. An output of the factor P r K with input r is denoted by v K . The reason for calling an output of the factor K with input as ~ v K u is explained in the next subsection. Remark 3.1 As in [Dehghani et al., 2007] and [Manuelli et al., 2007], let the pair (N K ;D K ) be a left Matrix Fraction Description (MFD) of a controller K2K such that K =D 1 K N K where N K = N r K N y K ; factorsN K ;D K are (possibly nonlinear) incrementally stable, causal, andD K has causal inverse. Then as shown in Fig. 3.3, any controller K2K can be realized using its left MFD by noting P r K =N r K ; u K =D K 1, and y K =N y K . 16 − 1 + + − Σ K − + N y Figure 3.3: Realization of a nonlinear controller K2 K using its left Matrix Fraction Description (MFD) pair (N K ;D K ). 3.2.1 Fictitious Signal Generator For controller realization as shown in Fig. 3.2, we modify Denition 2.14 of ctitious reference input signal as follows. Denition 3.1 (Fictitious Signal) Given the data = [u y] 0 measured over the period [0;t] and a controller K = [P r K K ]2 K, then its ctitious signal ~ v K is a hypothetical input signal that would have exactly reproduced the measured data had the controller [1 K ] been in the loop for the entire time period [0;t] over which the data were collected. Let a causal system ~ K = u K + 1 y K with input be the ctitious signal gener- ator for the controller K2K which generates its ctitious signal ~ v K such that ~ v K = h u K + 1 y K i | {z } ~ K 2 4 u y 3 5 |{z} Therefore ~ v K u = ~ K u = K . Hence we denote the output of the factor K with input as ~ v K u as shown in Fig. 3.2. 17 3.3 Supervisor In this thesis, we follow the general approach of [Battistelli et al., 2013], but will develop results that relax a number of assumptions and restrictions of the plant and switching algorithm. Without loss of generality, we decompose the supervisor S as shown in Fig. 3.4. Hysteresis Algorithm HA with Reset Condition (RC) : Bumpless Transfer (BT) System Figure 3.4: Supervisor S mapping [ r] 0 into switching signal ^ K and correction signal u . 3.3.1 Hysteresis Algorithm with Reset Condition The supervisorS uses the hysteresis algorithm (HA) [Morse et al., 1992] along with reset mechanism feature [Battistelli et al., 2013], to select an active controller ^ K(t) fromK at every instant for ( ^ K;P ) as shown in Fig. 3.5. , , ∀ ∈ RC HL ( , , ) Figure 3.5: Hysteresis algorithm (HA) with reset condition (RC) having hysteresis logic (HL) to compare cost functions V M of all controllers. 18 The supervisor evaluates the performance of each candidate controller using a per- formance function V M , without necessarily inserting the controllers in the loop. When the plant is time varying then it is important that more importance should be given to the recently evaluated performance than to the old one. To do this, we may select the performance function V M so that it depends only on data collected over some recent time-window. One method given in [Cheong and Safonov, 2006] is to x the length of time-window for V M . Another method given in [Battistelli et al., 2013] and [Battistelli et al., 2014] which we use in this thesis, is to use accumulating real-time data to adaptively decide the length of memory time-window. Specically, we consider a par- titionZ + = S k2Z + T k whereT k =ft k ;:::;t k+1 1g witht 0 = 0. The intervalT k is called the k th reset interval and t k is called the k th resetting time. Then8t2T k , performance function V M for a controller K2K is given by V M (K;;t) = 8 > > > < > > > : max 2[t k M;t] V (K;;); if tM max 2[0;t] V (K;;); if t<M where M 2 Z + is arbitrarily chosen by designer, and the sequenceft k g;k2 Z + is a resetting sequence decided adaptively by a reset condition (RC). A reset condition can be dened as the logic which decides times t k ; k 2 Z + such that the old evaluated performance V M prior to the time t k can be safely ignored without inducing instability. Therefore in the performance function V M , time interval [t k M ;t] denotes memory time-window and the old evaluated performance V M prior to time t k M is ignored. The parameterM gives the designer exibility to avoid switching due to possible abrupt drop in performance functionV M at resetting times. The cost functionV (K;;t) is non- negative real valued function of candidate controller K2K, data, and timet and it is described in the next subsection. The use of monotone cost function (e.g. cost function having max operator) restricts the problem of continuous chattering or persistent switching. Note that, the cost function 19 V M is monotone in time t over each reset interval T k but not8t2Z + because the max operator runs over a reset interval. Therefore sometimes it leads to a greater number of controller switches, but assures convergence to better performing (including stability) controller with minimum cost for any variation in the plant P . The hysteresis algorithm orders the candidate controllers based on their evaluated performance V M and then switches to the controller with minimum cost using the hys- teresis logic (HL). The logic is given by ^ K(t + 1) = 8 > > < > > : arg min K2K V M (K;;t); if V M ( ^ K(t);;t)> min K2K V M (K;;t) +h c ^ K(t); otherwise where h c 2R + is called hysteresis constant to avoid chattering; and initial active con- troller ^ K(0) is selected from the candidate controller set K by the designer. If the hys- teresis logic conditionV M ( ^ K(t);;t)> min K2K V M (K;;t) +h c is satised then we say that an active controller is falsied at the falsication cost level = min K2K V M (K;;t) +h c and switch to the controller with minimum cost V M , otherwise we say that an active controller is unfalsied and keep it in the loop. For any kind of variation in the plantP if the active controller is no longer stabilizing then the switching happens because of the hysteresis logic and reset condition. With each such switching the falsication cost level required to falsify the controller increases and may tend to innity if we do not use a reset condition. But if a reset condition is implemented in the hysteresis algorithm then it restricts the falsication cost level from increasing to innity. It is possible because whenever a reset condition is satised, at the start of each reset intervalT k the old evaluated performancesV M of all candidate controllers until time t k M are ignored. Remark 3.2 The original Hysteresis algorithm [Morse et al., 1992] using the cost function V is as follows. It does not consider a reset condition. 20 Algorithm 3.1 (Hysteresis Algorithm) 1. Initialize: t;h c 2R + ; ^ K(t)2K 2. Collect data (t), update ~ v K and V (K;;t) for all K2K 3. if max 2[0;t] V ( ^ K(t);;)> min K2K max 2[0;t] V (K;;) +h c then ^ K(t + 1) = arg min K2K max 2[0;t] V (K;;); else ^ K(t + 1) = ^ K(t) 4. t =t + 1 5. Go to step 2 3.3.2 Generalized Cost Function V A generalized cost functionV is a non-negative real valued function of controllerK, data , and time t. For a controller K2K, it is given by V (K;;t) = h W N ~ W N i 2 4 ~ v K 3 5 p[0;t] +kW D ~ v K k p[0;t] (3.1) where is small positive constant. W N is a frequency dependent performance weight on such thatW N is stable and minimum phase. ~ W N is a frequency dependent performance weight on ~ v K in the numerator of V such that ~ W N is stable. W D is a frequency dependent performance weight on ~ v K in the denominator of V such that W D is stable. 21 Given the data and time t, the cost function V gives the measure of performance of the ctitious closed loop system (K;P ) shown in Fig. 3.6 at time t. Let ~ =W N Since W N is stable and minimum phase, ~ is a stable signal if and only if is a stable signal. Hence we will consider ~ instead of to prove stability of the system ( ^ K;P ) shown in Fig. 3.1. We will show that the modied data ~ stays nite by deriving an upper bound on it. + − K Σ W W K K Σ Figure 3.6: Fictitious closed loop system (K;P ) with performance weights ofV (K;;t). Remark 3.3 A small positive constant in the cost function V is considered for the special case of possible eects of non-zero initial state of plant on its transient response for zero input signal (v = 0). In absence of , an algorithm in the supervisor prematurely falsies all candidate controllers because the cost V of all of them would be innite. 22 Cost Function Example 1 If we let W N = 2 4 1 0 0 1 3 5 ; ~ W N = 2 4 0 1 3 5 ; and W D = 1 in (3.1) then we have the following cost function V 1 which has been used in previous research work such as [Battistelli et al., 2013], [Jin et al., 2011c], [Jin et al., 2011a], etc. V 1 (K;;t) = 2 4 u ~ v K y 3 5 p[0;t] +k~ v K k p[0;t] Cost Function Example 2 If we let W N = 2 4 W I 0 0 W O 3 5 ; ~ W N = 0; and W D = 1 in (3.1) such that W I and W O are stable and minimum phase frequency dependent weighting functions then we have the following cost function V 2 (K;;t) = 2 4 W I 0 0 W O 3 5 2 4 u y 3 5 p[0;t] +k~ v K k p[0;t] The cost function V 2 is used for a data-driven H 1 loop-shaping controller design as in [Sung et al., 2016] where the weighting functions W I andW O are designed based on the desired loop shape. 23 Cost Function Example 3 As in Remark 3.1, let the pair (N K ;D K ) be a left Matrix Fraction Description (MFD) of controllerK2K with additional constraint thatN K is minimum phase ifK is minimum phase, otherwise N K is an all-pass factor. If we let W N = 2 4 W u 0 0 W p 3 5 ; ~ W N = 2 4 0 W p N 1 K 3 5 ; and W D = 1 in (3.1) such that W u and W p are mixed-sensitivity specications as in [Skogestad and Postlethwaite, 2005], that is W p is frequency dependent performance weight on the magnitude of sensitivity S and W u is frequency dependent performance weight on the magnitude of KS, then we have the following cost function V 3 (K;;t) = 2 4 W u 0 0 W p 3 5 2 4 u N 1 K ~ v K y 3 5 p[0;t] +k~ v K k p[0;t] 3.3.3 Bumpless Transfer Whenever a controller is switched, jumps and discontinuities may occur in the controller output signal at the switching times leading to transients called bumps in the control signalu. As said earlier, the use of a reset condition in the hysteresis algorithm may lead to a greater number of switches which indirectly causes more undesired bumpy transients in the control signal u. With each such transient the cost function V of each candidate controller tends to increase, and so does the falsication cost level. So the evaluated performance of each candidate controller may transiently mislead the hysteresis logic into brie y selecting destabilizing controllers, which may in turn result in unacceptably large transients [Dehghani et al., 2007]. 24 As shown in Fig. 3.7, the supervisor S uses switching time dependent bump- less transfer (BT) system B to tackle the undesired bumpy transients associated with switching. It needs the switching signal generated by the hysteresis algorithm to know the switching times s. With the help of past data and reference input signal r it generates a correction signal u . Then it injects a decaying correction signal u into the output of a switched controller at the switching time to ensure bumpless transfer. The paper [Battistelli et al., 2013] is a special case where u is zero. We will establish generalized bumpless transfer system implementable in direct adaptive switching control. : Bumpless Transfer (BT) System Figure 3.7: Switching time dependent bumpless transfer system B . The overall picture of the adaptive switching control system ( ^ K;P ) with con- troller realization and supervisor having the hysteresis algorithm with reset condition and switching time dependent bumpless transfer system is shown in Fig. 3.8. 3.4 Problem Description The theoretical stability analysis in [Battistelli et al., 2013] for an adaptive system under the hysteresis algorithm with reset mechanism has the unnecessary assumptions such as (i) the plant to be controlled is a strictly causal linear system of bounded order, (ii) each candidate controller is linear, and (iii) the initial conditions of the candidate controllers are not re-initialized or adjusted at switching times. We want to show that these restrictive assumptions are not necessary to prove the stability. Thus we want to 25 , , ∀ ∈ ॶ + Σ Σ ( , , ) ∈ ॶ Σ + + + − Σ - + Figure 3.8: Adaptive switching control system ( ^ K;P ) with the realization of a controller K switched on at time and supervisorS (consisting the hysteresis algorithm with reset condition and bumpless transfer system). prove that the adaptive switching control system shown in Fig. 3.1 is stable with only assumption that the adaptive stabilization problem is feasible. The simulation results in [Battistelli et al., 2013] have very large transients because of discontinuities and transients in the control system u associated with switching. We want to show that the results can be improved by removing abrupt changes in the control 26 signal u using bumpless transfer method. Thus we want to build generalized bumpless transfer system implementable in direct adaptive switching control. The reset conditions of [Battistelli et al., 2013] and [Patil et al., 2014] have design parameters 2 R + and c2 R + respectively which are arbitrarily chosen by designer. In fact these parameters are ctitious signal generator and bumpless transfer system dependent, and designer cannot choose them arbitrarily. We want to show that such parameters are formulated using realizations of ctitious signal generators i.e. indirectly realizations of sub-controllers K ;8K2 K and bumpless transfer system B . Moving from one reset intervalT k to the next reset intervalT k+1 , gains of ctitious signal gener- ators of all activated controllers during T k , gain of a bumpless transfer system B , and gains of corresponding ctitious closed loop systems play an important role in deciding the resetting time t k+1 . But since the plant P is an unknown plant, gain of a ctitious closed loop system can be expressed in terms of performance function V M . Based on all these gains, we want to design a reset condition which can adaptively generate a reset- ting sequenceft k g and designer cannot interfere it apart from designing controllers and bumpless transfer system. It will be a generalized reset condition using the ` pe norm and the ` p gain. In summary, our goals are to improve on the results of [Battistelli et al., 2013] by removing the linear plant and linear controller assumptions, to improve the reset condi- tion of [Battistelli et al., 2013] by making it completely adaptive considering gains of all the system components, and to allow generalized bumpless transfer system. 27 Chapter 4 Main Results 4.1 Generalized Bumpless Transfer In an adaptive switching control system, controller output signal mismatch at the switching times can cause discontinuities and/or fast transients (bumps or spikes) in the control signal u. To remove these undesired bumpy transients, there are bump- less transfer (BT) methods such as [Cheong and Safonov, 2012], [Hanus et al., 1987], [Turner and Walker, 2000], [Arehart and Wolovich, 1996], etc. 4.1.1 Properties In general, a bumpless transfer system used in direct adaptive control has reference signal r, data, and switching signal ^ K as inputs. It maps these inputs into a correction signal u as output. A bumpless transfer system itself has certain properties such as It is a stable and causal system. It is allowed to use the knowledge of all the switched candidate controllers and their states. It is allowed to use all the switching times which we do not know a priori. A switching time is a kind of trigger to a bumpless transfer system such that because of causality it produces output u at a switching time. So in real time, a bumpless transfer system is required to work only at a switching time. 28 4.1.2 Goals Typically, a bumpless transfer system is a system that injects the decaying correction signal u into the output signals of switched controllers at their switching times s, such that the control signal u is constrained by the following goals with assumption that the signals r and y do not change their behavior for few samples around a switching time. To ensure continuity of u at switching times i.e. u() should be as if the switch had not been made. Or to ensure behavior of u at switching times should satisfy any given condition such as rst derivative of u should be continuous, u() should be average of past few samples of u, etc. To achieve transients that have no spikes in u at switching times i.e. transients should have time constants that are no faster than the bandwidth of the system. 4.1.3 Types of Correction Signal u The control signal u produced at a switching time depends on the initial state of a switched controller. By initializing the state of a switched controller appropriately, we can force the control signal to behave in a desired way. Also we can control the behavior of the control signal by injecting another signal at the output of a switched controller to suppress its undesired output. So there are two types of correction signal u . It can be a state-initialization signal which re-initializes the states of a switched controller at a switching time. It can be an additional signal which is directly added to the output of a switched controller at a switching time. In theory, the correction signal can be a combination of the state-initialization signal and the additional signal. In this thesis, we treat u as the additional signal. Following is an example of state-initialization signal for bumpless transfer. In the next subsection we 29 build the framework of a generalized bumpless transfer system to generate the additional signal (correction signal u ). State-Initialization Signal Example One example of bumpless transfer system to generate the state-initialization signal is the slow-fast controller decomposition bumpless transfer method of [Cheong and Safonov, 2012]. Let the controller K i be switched on at the switching time . Consider the slow-fast controller decomposition for K i as K i = K islow +K ifast with the minimal realizations K islow = 2 6 4 A is B is C is D is 3 7 5; K ifast = 2 6 4 A if B if C if D if 3 7 5 where K islow is in the observable canonical form. The poles of K islow are of smaller magnitude than those of K ifast . Suppose the goal of the bumpless transfer system is to make u() = u( 1) provided the rst derivatives of r and y are continuous i.e. r()r( 1) =r( 1)r( 2) andy()y( 1) =y( 1)y( 2). Therefore by linear interpolation we predict the inputs r() and y() to the controller K i before the switch. Considering these facts, the bumpless transfer system B to generate state- initialization signal (correction signal) [X K islow () X K ifast ()] 0 is given as follows. 2 4 X K islow () X K ifast () 3 5 = h M i M r i i 2 6 6 6 6 6 6 6 4 2 4 1 z 1 3 5 0 0 2 4 1 z 1 3 5 3 7 7 7 7 7 7 7 5 | {z } B 2 4 ( 1) r( 1) 3 5 where M i = 2 6 4 C y is h 1 2[D is +D if ] 0 [D is +D if ] i 0 3 7 5; 30 M r i = 2 6 4 C y is h 2[D is +D if ] [D is +D if ] i 0 3 7 5 The matrices M i and M r i are designed based on the goal u() = u( 1) mentioned before, the state of the fast part of the controller K i at time is reset to zero, and the realization of the controller K i with assumption that the rst derivatives of r and y are continuous. According to [Cheong and Safonov, 2012], the controller state augmentation can be used in case K i does not have slow modes. We can augment its state space realization with the additional stable but uncontrollable slow modes that were not originally present in K i . In this case, correction signal acts as the additional signal. 4.1.4 Framework ( ) ( − 1) Bumpless Transfer System −1 + + ( ) ( −1) Figure 4.1: Switching time dependent bumpless transfer system B mapping [r ] 0 into the correction signal u . 31 A switching time dependent generalized bumpless transfer system B is shown in Fig. 4.1. The controller is switched from ^ K(1) to ^ K() at switching time. To make this switch bumpless, the bumpless transfer system B injects the correction signal u which is a decaying signal into the output u ^ K() of ^ K() at the switching time . The bumpless transfer system B is time-varying, causal, and exponentially stable system mapping [r ] 0 into the correction signal u given by u = ~ B W 1 | {z } B 2 4 r 3 5 The system W 1 is a LTV window system of length n, where n 2 Z + is a design parameter. It lters only the last n samples over the interval [n; 1] of the past data [r ] 0 . It does not modify the ltered samples. These last n samples are then processed by the system ~ B to generate the decaying correction signal u . The switching time dependent system ~ B is time invariant, causal, and exponentially stable and it can be described as ~ B =D 0 @ F o 1 2 4 ^ K() I 3 5 F o 2 2 4 ^ K( 1) +B 0 I 3 5 1 A F i (4.1) where System F i is an input lter. It predicts the sample r() y() 0 at time 1 just before switching based on a given condition, e.g. rst derivative of [r y] 0 is continuous. Its output consists samples of [r] 0 over the interval [n;1] along with predicted r() y() 0 . SystemsF o 1 andF o 2 are an output lters. They are designed to produce a condition related values based on a given condition on u; such as u should be continuous, u() should be average of past few samples of u, etc. The lter F o 1 predicts an actual condition related value due to the new controller ^ K() as if the switch is 32 not bumpless. The lter F o 2 predicts a desired condition related value due to the old controller ^ K( 1) and the old bumpless transfer system B 0 ( 0 denotes last switching time prior to ) as if the switch had not been made. It is allowed to set a desired condition related value directly using past samples of u. System I allows output lters F o 1 and F o 2 to have direct access of the past data [r ] 0 over the interval [n; 1] along with predicted [r() y()] 0 . System D is LTI, causal, and exponentially stable. It generates the decaying correction signal u having an initial value u () equal to dierence between the actual and desired condition related values. Block diagram of the bumpless transfer system B is shown in Fig. 4.2. −1 2 1 ( ) − 1 + ′ + − Figure 4.2: Block diagram of bumpless transfer systemB mapping [r ] 0 into u consist of window system W 1 and system ~ B . 33 Modied System ~ B As shown in Fig. 3.8, the factor u K of the realization of controller K has the control signal u as an input signal instead of controller output signal u K . Hence the transfer function from u tou is 1+ u K 1 rather than 1. It means the correction signal u gets modied by the factor 1 + u K 1 and the behavior of the control signal u changed by it would be dierent from the expected one. Therefore to compensate this modication, the correction signal must go through the lter 1 + u K before injecting into u ^ K(t) . So the system ~ B as in (4.1) takes the following form. ~ B = 1+ u ^ K() D 0 B @F o 1 2 6 4 h P r ^ K() ^ K() i I 3 7 5F o 2 2 6 4 h P r ^ K(1) ^ K(1) i +B 0 I 3 7 5 1 C AF i (4.2) 4.2 Assumptions We make the following assumptions to prove stability of the system ( ^ K;P ) shown in Fig. 3.1. Assumption 4.1 The reference input signal r is a stable signal. Assumption 4.2 We know 2 (0; 1) a priori such that ( ^ K;P ) is feasible. Let ~ = max K2K ~ K where ~ K is the degree of exponential stability of the ctitious signal generator ~ K . For theoretical analysis in terms of ` pe norm and ` p gain, we let 2 max ; ~ ; 1 Without loss of generality, we decompose the switching time dependent bumpless transfer system B as B = h B r B i . 34 Remark 4.1 MFDs are not unique and their poles can be arbitrary placed using Nett-Jacobson-Balas formula in [Nett et al., 1984]. So, if each candidate controllerK inK is realized in terms of its left MFD such thatP r K =N r K ; u K =D K 1, and y K =N y K then we can make ~ whatever we like by simply choosing dierent MFDs for the controllers in K. Therefore in this case, the constraint 2 max ; ~ ; 1 can be relaxed to 2 ( ; 1) by choosing an MFD for each controller inK such that ~ . 4.3 Fictitious Signal We show that the ctitious signal ~ v ^ K() of an active controller ^ K() switched on at switching time has an upper bound in terms of ` p gains of ~ ^ K() ;P r ^ K() ;B , and B r . The following theorem implies that the ctitious signal of an active controller is always nite even if it is a destabilizing controller and as long as it is in the loop. Theorem 4.1 Consider the hysteresis algorithm (without reset condition) and bumpless transfer sys- tem B for the system ( ^ K;P ) shown in Fig. 3.1 with Assumption 4.1. Suppose n ^ K( 0 ); ^ K( 1 );::: o is the switching sequence where f 0 = 0; 1 ;:::g is the sequence of switching times. Then for any ^ K( i ) 2 n ^ K( 0 ); ^ K( 1 );::: o where i 2 Z + , 8t 2 [ i ; i+1 1] we have ~ v ^ K( i ) p[0;t] ~ ^ K( i ) p + B i p t i +1 kk p[0; i 1] + P r ^ K( i ) p + B r i p krk p[0;t] Proof. Refer Appendix C. Uisng Theorem 4.1, we prove the following lemma showing relation between the cost-detectability property of a cost function and its performance weight on data . 35 Lemma 4.1 Given the cost function V (K;;t) as in (3.1) and a controller K2K, the pair (V;K) is cost-detectable if and only if the performance weight W N is stable and minimum phase. Proof. Refer Appendix D. 4.4 Reset Mechanism Over the k th reset interval T k =ft k ;:::;t k+1 1g;k2Z + , let N k be the number of switches T k[i] = h k[i] ; k[i+1] 1 i 2T k be the i th switching interval k = 8 > > > < > > > : min K2K max t2[t k M;t k+1 1] V (K;;t) +h c ; t k M min K2K max t2[0;t k+1 1] V (K;;t) +h c ; t k <M Remark 4.2 By Assumption 4.2, k is nite8k2Z + which implies there exists a robust cost 2R + such that k ;8k2Z + . Since the plant P is unknown, cannot be formulated beforehand. Lemma 4.2 Consider the hysteresis algorithm for the system ( ^ K;P ) shown in Fig. 3.1 with Assump- tions 4.1 and 4.2. Let n ^ K( k[0] ); ^ K( k[1] );:::; ^ K( k[N k ] ) o be a switching sequence gener- ated over T k with ^ K( k[i] ) active over T k[i] . Then8k2Z + ;8i2 [0;N k ], and8t2 T k[i] we have V M ^ K( k[i] );;t k V M ^ K( k[i] );;t +h c 36 and N k N & k V ^ K( k[0] );;t k h c ' Proof. Lemma 4.2 is a consequence of the hysteresis logic. To prove stability of the system ( ^ K;P ) shown in Fig. 3.1, basically we need to analyze it over each switching interval, then over each reset interval, and then over complete time. Consider thei th switching intervalT k[i] of thek th reset intervalT k with xed controller ^ K( k[i] ) in the loop. We can analyze the real time system ^ K( k[i] );P with input r and output in two stages. In the rst stage, the response depends on the ` p gain of ^ K( k[i] );P with input ~ v ^ K( k[i] ) . In the second stage, ~ v ^ K( k[i] ) depends on the ` p gains of ~ ^ K( k[i] ) ;P r ^ K( k[i] ) ;B k[i] ;B r k[i] with inputs ;r. Since the plant P is unknown, the ` p gain of ^ K( k[i] );P at time t is V M ( ^ K( k[i] );;t) k (By Lemma 4.2). By Theorem 4.1, ~ ^ K( k[i] ) p + B k[i] p is the ` p gain from to ~ v ^ K( k[i] ) . Hence, as we move from the switching inter- val T k[i1] to the next switching interval T k[i] , the overall gain with respect to is k ~ ^ K( k[i] ) p + B k[i] p . With the same logic, the next theorem states that as we move from the reset interval T k1 to the next reset interval T k , the overall gain with respect to is the product of gains calculated for each switching interval of T k . Theorem 4.2 Consider the hysteresis algorithm with bumpless transfer system B for the system ( ^ K;P ) shown in Fig. 3.1 with Assumptions 4.1 and 4.2. Then8t2T k we have ~ p[0;t] f k (t) ~ p[0;t k 1] +g 1 k krk p[0;t] +g 2 k (4.3) 37 where f k (t) = h k W D p + ~ W N p i W N 1 p N k +1 N k Y i=0 ~ ^ K( k[i] ) p + B k[i] p tt k +1 g 1 k = N k X i=0 h k W D p + ~ W N p i W N 1 p i+1 P r ^ K( k[N k i] ) p + B r k[N k i] p i1 Y j=0 ~ ^ K( k[N k j] ) p + B k[N k j] p g 2 k = k + k N k X i=1 h k W D p + ~ W N p i W N 1 p i i1 Y j=0 ~ ^ K( k[N k j] ) p + B k[N k j] p Proof. Refer Appendix E. 4.4.1 Reset Condition Our aim is to prove that the system ( ^ K;P ) shown in Fig. 3.1 is stable by showing that there exists an upper bound on the modied data ~ . To get the upper bound we must use (4.3) recursively and the upper bound will exist only if the function f k (t) is less than 1 at the end of each reset interval. But to get exponential stability, the resetting sequence ft k g should be chosen such that f k (t k+1 1) t k+1 t k ;8k 2 Z + where 2 (; 1). Therefore, by Theorem 4.2 and Lemma 4.2, we have the following reset condition. 38 Reset Condition Let t2T k[i] 2T k . Then t k+1 =t + 1 if V M ( ^ K( k[i] );;t) +h c W D p + ~ W N p W N 1 p ! i+1 i Y j=0 ~ ^ K( k[j] ) p + B k[j] p tt k +1 tt k +1 (4.4) where 2 (; 1): Remark 4.3 Since a pair (V;K);8K2K is cost-detectable, it is possible that if a destabilizing con- troller is inserted in the loop then the reset condition (4.4) will not be satised. But in the same situation, the reset condition in [Battistelli et al., 2013] and [Battistelli et al., 2014] can be satised, because by Theorem 4.1 ctitious signal ~ v of any active stabilizing or destabilizing controller is always nite and as proved in [Patil et al., 2014] it converges to the input signal v. The above reset condition has been designed in such a way that (i) practically it uses the cost function V M of an active controller to decide a resetting time t k which is used as the reference for discarding an old evaluated performance V M of each candidate controller and (ii) theoretically it ascertains an ultimate upper bound on the measured modied data ~ even if a resetting sequenceft k g is innite. By Theorem 4.2, reset condition (4.4), and Denition 2.9, the system ( ^ K;P ) shown in Fig. 3.1 with Assumptions 4.1 and 4.2 is exponentially stable with degree over each reset interval. But we cannot say that it is exponentially stable with the same degree for all t2Z + . To decide a resetting timet k by the reset condition (4.4), we wait untilf k (t) decreases exponentially below . But it can reduce asymptotically to and stay below it without converging to zero. In other words, it is not necessary that it should reduce exponentially 39 to . Under this condition, if we relax the exponentially decaying term in Theorem 4.2 then by Denition 2.11, the system ( ^ K;P ) shown in Fig. 3.1 with Assumptions 4.1 and 4.2 is asymptotically stable over each reset interval. But we cannot say that it is asymptotically stable for all t2Z + . 4.4.2 Algorithm We state the following adaptive switching control algorithm having the hysteresis logic, reset condition (4.4), and switching time dependent bumpless transfer system. Given the cost function (3.1) and bumpless transfer system (window systemW of lengthn2Z + and system ~ B in (4.2)), the following algorithm can be implemented in the supervisor S for the adaptive system ( ^ K;P ) shown in Fig. 3.1. Algorithm 4.1 (Hysteresis Algorithm with Reset Condition and Bumpless Transfer) 1. Choose: Comment: Cost Functions V and V M > 0;2 maxf ; ~ g; 1 ;p2 [1;1];M 2Z + Comment: Hysteresis Logic h c 2R + Comment: Reset Condition 2 (; 1) 2. Initialize: Comment: Hysteresis Logic t = 0; ^ K(0)2K Comment: Reset Condition k = 0;i = 0 Comment: Bumpless Transfer System u = 0 3. Collect data (t), update ~ v K and V M (K;;t) for all K2K 40 4. Comment: Hysteresis Logic and Bumpless Transfer if V M ( ^ K(t);;t)> min K2K V M (K;;t) +h c then ^ K(t + 1) = arg min K2K V M (K;;t); i =i + 1; i =t + 1; u =B i [r ] 0 else ^ K(t + 1) = ^ K(t) 5. Comment: Reset Condition (4.4) if V M ( ^ K(t);;t) +h c W D p + ~ W N p W N 1 p ! i+1 i Q j=0 ~ ^ K( j ) p + B j p tt k +1 tt k +1 then t k+1 =t + 1; k =k + 1; 0 = i ; i = 0 6. t =t + 1 7. Go to step 3 In Algorithm 4.1, if the system ~ K orB happen to be LTI then its ` p gain can be calculated using the ` p gain as follows. For a LTI system T having the transfer function T (z), we dene T (z) =T (z) to be the transfer function of a LTI system T . Lemma 4.3 If T is a LTI system then kTk p =kT k `p Proof. Refer Appendix F. 41 Gain Calculation In Algorithm 4.1, both Lemma 4.3 and the MATLAB function norm [Mathworks, 2013b] can be used to calculate the ` 1 gain of LTI system T having an impulse response h(t) as kTk 1 = norm(h ; 1) where h (t) = h(t) Since the ` 2 gain and H 1 gain are equal by [Sandberg, 1964] and [Green and Limebeer, 1995], both Lemma 4.3 and the MATLAB function norm [Mathworks, 2013a] can be used to calculate the ` 2 gain of LTI system T as kTk 2 = norm(T ; inf) where T (z) =T (z) and inf is1. The ` 2 gain of a nonlinear system can be calculated with the help of procedures given in [Safonov, 1983]. 4.4.3 Stability The following lemma states that subject to feasibility the reset condition (4.4) produces reset intervals of nite length. 42 Lemma 4.4 Consider the hysteresis algorithm with reset condition (4.4) and bumpless transfer system B (Algorithm 4.1) for the system ( ^ K;P ) shown in Fig. 3.1 with Assumptions 4.1 and 4.2. Then the reset condition (4.4) generates a resetting sequenceft k g such that8k2Z + we have t k+1 t k log f where 2 (; 1) and f is as in (G.4). Proof. Refer Appendix G. Now we prove that the system ( ^ K;P ) shown in Fig. 3.1 under Algorithm 4.1 is stable even if the sequence of reset intervals produced by the reset condition (4.4) is innite. Theorem 4.3 (Main Result) Consider the hysteresis algorithm with reset condition (4.4) and bumpless transfer system B (Algorithm 4.1) for the system ( ^ K;P ) shown in Fig. 3.1 with Assumptions 4.1 and 4.2.. Then the system ( ^ K;P ) is stable and8t 0 we have ~ `1[0;t] 1 1 g 1 p p 1 p krk `1[0;t] +g 2 where g 1 and g 2 are as in (G.1) and (G.2) respectively. Proof. Refer Appendix H. Theorem 4.2 and the reset condition (4.4) imply that the system ( ^ K;P ) shown in Fig. 3.1 is exponentially stable with degree. It means the eects of any non-zero initial state or past disturbances decay exponentially with rate . If is close to 1 then we get frequent resets and fast convergence but with low degree of exponential stability. On the other hand, if is close to then we get occasional resets and slow convergence but with high degree of exponential stability. 43 Chapter 5 Simulation Example = 1 : Supervisor Σ 2 1 2 + + Φ = Φ Figure 5.1: Adaptive switching control system ( ^ K;P ) to control nonlinear time-varying plant P using LTI PI controllers K 1 and K 2 . 5.1 Nonlinear Time-Varying Plant As shown in Fig. 5.1, consider the problem of stabilization of the unknown plantP using two controllers K 1 ;K 2 switched adaptively by the supervisor S consisting of Algorithm 4.1. Consider a linear time-varying plant ~ P as follows ~ P (z) = 8 > > < > > : ~ P 1 (z) = (z + 0:3)=(z 2 1:6z + 0:7); t< 300 ~ P 2 (z) = (z 0:3)=(z 2 1:6z + 0:7); t 300 44 At the input of ~ P , consider a dead-zone nonlinearity with input u and output ' described by ' = 8 > > > > > > < > > > > > > : u(t) 0:01; u(t) 0:01 0; 0:01<u(t)< 0:01 u(t) + 0:01; u(t)0:01 The dead-zone makes the cascaded plant P = ~ P nonlinear time-varying. The only purpose to consider the model of plant P is to generate data in MATLAB simulation because the supervisor has data-driven Algorithm 4.1. In practice, the supervisorS does not require the model of plant P and hence initially we called it as an unknown plant. 5.2 Candidate LTI PI Controllers We consider two LTI PI controllers K 1 = 0:003 + 0:007 z 1 and K 2 = 0:5 + 0:993 z 1 such that K 1 stabilizes ~ P 1 but K 2 cannot, and both K 1 ;K 2 stabilize ~ P 2 but K 2 provides better performance. Note that linear controller is special case of nonlinear controller. Both the controllers K 1 and K 2 are designed using the model of plant P . Hence models of a plant to be controlled play an important role in designing controllers 45 but they are not required for unfalsied adaptive control to work. According to Fig. 3.2, both the controllers K 1 and K 2 shown in Fig. 5.1 are realized as K 1 = h P r K 1 K 1 i and K 2 = h P r K 2 K 2 i respectively, where P r K 1 = 0:003z + 0:004 z + 0:5 ; K 1 = z 1 z + 0:5 1 0:003z + 0:004 z + 0:5 ; P r K 2 = 0:5z 0:493 z + 0:5 ; K 2 = z 1 z + 0:5 1 0:5z 0:493 z + 0:5 5.3 MATLAB Simulation Case 1 In MATLAB, we simulated the system ( ^ K;P ) shown in Fig. 5.1 by implementing Algorithm 4.1 (hysteresis algorithm with reset condition (4.4) and bumpless transfer system B ). At the beginning, we chose the following values. = 0:01; = 0:9891; p =1; M = 10; h c = 0:8; ^ K(0) =K 2 ; = 0:9892 We used the following cost function. V (K;;t) = 2 4 u ~ v K y 3 5 p[0;t] +k~ v K k p[0;t] 46 We took the ` 1e norm of signals in the cost function V M . The input reference signal to the system ( ^ K;P ) is r = sin(0:1t). Our aim for bumpless transfer is to ensure continuity of the control signal u. The switching time dependent bumpless transfer system B used here is B = ~ B W 1 where W 1 is a LTV window system of length 2. The system ~ B is as in (4.2) with output lters F o 1 =F o 2 = [I 0] and input lter F i consists of rst-order hold to predict [r() y()] 0 . In the reset condition (4.4), we used the ` 1 gain. Simulation results are shown in Fig. 5.2. Case 2 In MATLAB, we simulated the system ( ^ K;P ) shown in Fig. 5.1 by implementing the hysteresis algorithm with reset condition (4.4). We did not use any bumpless transfer system. For the simulation, we used the same setup of case 1 excluding bumpless transfer system. Simulation results are shown in Fig. 5.3. Case 3 In MATLAB, we simulated the system ( ^ K;P ) shown in Fig. 5.1 by implementing Algorithm 3.1 (hysteresis algorithm). We did not use any reset condition and bumpless transfer system. For the simulation, we used the same setup of case 1 excluding reset condition and bumpless transfer system. Simulation results are shown in Fig. 5.4. 5.4 Observations In all the cases, we started the simulation with destabilizing controller K 2 for ~ P 1 in the loop, but the hysteresis logic correctly selected the cost minimizing and stabilizing controller K 1 for ~ P 1 soon. The plant P changed from ~ P 1 to ~ P 2 at time t = 300. According to Fig. 5.2 and Fig. 5.3, the reset at time t = 330 in case 1 and at time t = 300 in case 2 due to the reset condition (4.4) allowed the hysteresis logic to select the better performing controllerK 2 for ~ P 2 witch had lower cost, though the stabilizing 47 controllerK 1 for ~ P 2 was in the loop. But according to Fig. 5.4, in absence of the reset condition (4.4) the hysteresis logic could not select the better performing controller K 2 for ~ P 2 because its cost stayed higher than that of K 1 from the beginning. In case 2, Fig. 5.3 shows large transients in the control signal u because switching is not bumpless like [Battistelli et al., 2013]. But according to Fig. 5.2, in case 1, the bumpless transfer system B injected the decaying correction signal u which removed the bumpy transients at the switching times and made the control signal u continuous. 48 -0.5 0 0.5 -1 0 1 -0.1 0 0.1 1 2 0 100 200 300 400 500 600 700 1 2 − 1 2 1 Φ 2 Φ Time Reset No Reset ( 1 , ) ( 2 , ) Time 0 5 0 100 200 300 400 500 600 700 0 5 Figure 5.2: Case 1: Simulation results for hysteresis algorithm with reset condition and bumpless transfer (Algorithm 4.1). 49 -0.5 0 0.5 -1 0 1 -0.1 0 0.1 1 2 0 100 200 300 400 500 600 700 1 2 − 1 2 1 Φ 2 Φ Time Reset No Reset ( 1 , ) ( 2 , ) Time 0 5 0 100 200 300 400 500 600 700 0 5 Figure 5.3: Case 2: Simulation results for hysteresis algorithm with reset condition. 50 − -0.5 0 0.5 -1 0 1 -0.1 0 0.1 1 2 0 100 200 300 400 500 600 700 1 2 1 Φ 2 Φ Time 1 2 Reset No Reset ( 1 , ) ( 2 , ) Time 0 5 0 100 200 300 400 500 600 700 0 5 Figure 5.4: Case 3: Simulation results for hysteresis algorithm (Algorithm 3.1). 51 Chapter 6 Conclusion In unfalsied adaptive control theory, until the BHMT (Battistelli-Hespanha-Mosca- Tesi) reset mechanism [Battistelli et al., 2013] there was no quantitative analysis of how to forget old data when we know the plant is changing. The BHMT reset mechanism is an important rst step towards addressing the adaptive stabilization of a time-varying plant. It is needed when plant time-variations are so large that the active controller no longer maintains a performance. It makes the data-driven control of nonlinear and time- varying plant possible using cost-minimizing controller. But it has major limitations. BHMT published some preliminary results in [Battistelli et al., 2013] but using unre- alistic assumptions, and we eliminated all of those assumptions except feasibility. We improved the theoretical results by removing the linear plant and linear controller assumptions. The BHMT reset mechanism has a limitation that it does not admit bumpless transfer because it does not allow to adjust the initial conditions of the switched controllers at switching times, resulting in large switching transients. So in this thesis, we removed this assumption to admit bumpless transfer. We established the framework of switching time dependent generalized bumpless transfer system. Our simulation results conrm signicant attenuation of switching transients. The BHMT reset mechanism has another limitation that its reset condition has uncertain parameter making it impractical and does not accommodate bumpless trans- fer. Hence, we designed the reset condition (4.4) based on the ` p gains of the system components. Our reset condition is practical, completely adaptive, free of uncertain parameters, and accommodates bumpless transfer. 52 Subject only to feasibility of the adaptive stabilization problem, we proved that an unknown plant can be made exponentially stable with degree using broad class of non- linear controllers. Our theoretical results are general in terms of ` pe norm and` p gain. We showed that the existing methods to calculate the ` p gain can be used to calculate the ` p gain. We designed the generalized cost function having performance weights. Hence our main result guarantees performance (including stability) and convergence for nonlinear time-varying plant. 53 Appendix A Proof of Lemma 2.1 Consider any real valued signal x dened onZ + . Then by Denition 2.1 and Denition 2.3,82 (0; 1) and8t2Z + we have Case 1: p2 [1;1), kxk p[0;t] = p v u u t t X =0 p(t) jx()j p p v u u t t X =0 p(t) kxk p `1[0;t] kxk `1[0;t] p v u u t t X =0 p(t) 1 p p 1 p kxk `1[0;t] and kxk `1[0;t] = max 2[0;t] jx()j = sup 2[0;t] kxk 1[0;] sup 2[0;t] kxk p[0;] 54 Case 2: p =1, kxk 1[0;t] = max 2[0;t] t jx()j max 2[0;t] jx()j (By assuming = 1) kxk `1[0;t] and kxk `1[0;t] = max 2[0;t] jx()j = sup 2[0;t] max ~ 2[0;] ~ jx(~ )j = sup 2[0;t] kxk 1[0;] Hence the claim follows by combining cases 1 and 2. 55 Appendix B Proof of Lemma 2.2 Let the system T shown in Fig. 2.1 be LTI system having an impulse response h(t). Then the weighted output w of the system T can be expressed in terms of inversely weighted impulse response h and weighted input r as follows. 2 6 6 6 6 6 6 6 4 t w(0) t1 w(1) . . . w(t) 3 7 7 7 7 7 7 7 5 = 2 6 6 6 6 6 6 6 4 h(0) 0 h(1) h(0) . . . . . . h(t) t h(t1) t1 h(0) 3 7 7 7 7 7 7 7 5 2 6 6 6 6 6 6 6 4 t r(0) t1 r(1) . . . r(t) 3 7 7 7 7 7 7 7 5 (B.1) Let h (t) = h(t) t (B.2) Therefore by substituting (B.2) in (B.1) we get 2 6 6 6 6 6 6 6 4 t w(0) t1 w(1) . . . w(t) 3 7 7 7 7 7 7 7 5 = 2 6 6 6 6 6 6 6 4 h (0) 0 h (1) h (0) . . . . . . h (t) h (t 1) h (0) 3 7 7 7 7 7 7 7 5 2 6 6 6 6 6 6 6 4 t r(0) t1 r(1) . . . r(t) 3 7 7 7 7 7 7 7 5 56 By applying the ` 1e norm to the above equation, we get kTk 1 = sup krk 1[0;t] 6=0;t0 kTrk 1[0;t] krk 1[0;t] = sup t0 2 6 6 6 6 6 6 6 4 h (0) 0 h (1) h (0) . . . . . . h (t) h (t 1) h (0) 3 7 7 7 7 7 7 7 5 `1 = 1 X t=0 jh (t)j (B.3) =kh k `1[0;1] Note: In (B.3), we used the induced ` 1e norm given as follows. For an mn matrix A as A = 2 6 6 6 6 6 6 6 4 a 11 a 12 ::: a 1n a 21 a 22 ::: a 2n . . . . . . . . . a m1 a m2 ::: a mn 3 7 7 7 7 7 7 7 5 ; the induced ` 1e norm is dened as kAk `1 = max i2f1;2;:::;mg n X j=1 ja ij j 57 Appendix C Proof of Theorem 4.1 For the system ( ^ K;P ) shown in Fig. 3.1, let n ^ K( 0 ); ^ K( 1 );::: o be the switching sequence generated under the hysteresis algorithm with bumpless transfer system B wheref 0 = 0; 1 ;:::g is the sequence of switching times. A switching interval of an active controller ^ K( i )2 n ^ K( 0 ); ^ K( 1 );::: o is denoted by [ i ; i+1 1] where i2Z + . Now consider any ^ K( i ) 2 f ^ K( 0 ); ^ K( 1 );:::g over the interval [0; i+1 1]. Then 8t2Z + , its ctitious signal is given by ~ v ^ K( i ) = ~ ^ K( i ) (C.1) ) ~ v ^ K( i ) = u ^ K( i ) + 1 u + y ^ K( i ) y (C.2) According to Fig. 3.1,8t2 [ i ; i+1 1] B i injects the correction signal u into the output of ^ K( i ) i.e. u = u ^ K( i ) + u . But according to Fig. 3.2,8t2 [ i ; i+1 1] we have u ^ K( i ) =P r ^ K( i ) r ~ v ^ K( i ) +u and hence (C.2) can be written as ~ v ^ K( i ) = u ^ K( i ) + 1 P r ^ K( i ) r ~ v ^ K( i ) +u + u + y ^ K( i ) y ) ~ v ^ K( i ) = u +P r ^ K( i ) r (By using (C.2)) (C.3) 58 where u =B i [r ] 0 Since B i = h B r i B i i , we have u =B i +B r i r (C.4) Therefore by (C.1), (C.3) and (C.4),8t2 [ i ; i+1 1] we get ~ v ^ K( i ) p[0;t] ~ ^ K( i ) p + B i p t i +1 kk p[0; i 1] + P r ^ K( i ) p + B r i p krk p[0;t] 59 Appendix D Proof of Lemma 4.1 For the given controller K2K, consider the cost function V (K;;t) = h W N ~ W N i 2 4 ~ v K 3 5 p[0;t] +kW D ~ v K k p[0;t] where ~ v K is nite and converges by Theorem 4.1. Let ~ =W N . + − Σ P Σ K Figure 6.1: Closed loop system (K;P ). Part A: Let the performance weight W N be stable and minimum phase. ) The data is a stable signal if and only if the modied data ~ is a stable signal. 60 ) The stable signal implies that the exponential stability of the system (K;P ) shown in Fig. 6.1 is unfalsied by (r;) and the stable signal ~ implies that the cost function V (K;) is a stable signal. ) The pair (V;K) is cost-detectable. Part B: Let the pair (V;K) be cost-detectable. ) The exponential stability of the system (K;P ) shown in Fig. 6.1 is unfalsied by (r;) if and only if the cost function V (K;) is a stable signal. ) The unfalsied exponential stability of the system (K;P ) shown in Fig. 6.1 implies that the data is a stable signal and the stable signalV (K;) implies that the modied data ~ is a stable signal. ) The performance weight W N is stable and minimum phase. Therefore by parts A and B, the pair (V;K) is cost-detectable if and only if the performance weight W N is stable and minimum phase. 61 Appendix E Proof of Theorem 4.2 Consider the i th switching interval T k[i] = k[i] ; k[i+1] 1 of T k with k[0] = t k ( k[0] need not be a switching time). Controller ^ K( k[i] ) is active over T k[i] . Then by Lemma 4.2,8t2T k[i] we have V ( ^ K( k[i] );;t) = h W N ~ W N i 2 6 4 ~ v ^ K( k[i] ) 3 7 5 p[0;t] + W D ~ v ^ K( k[i] ) p[0;t] k ) h W N ~ W N i 2 6 4 ~ v ^ K( k[i] ) 3 7 5 p[0;t] k + W D ~ v ^ K( k[i] ) p[0;t] ) ~ + ~ W N ~ v ^ K( k[i] ) p[0;t] k + W D ~ v ^ K( k[i] ) p[0;t] (* ~ =W N ) (E.1) 62 Consider the response ~ = W N of the system ( ^ K;P ) over the interval T k[i] . Then 8t2T k[i] we have ~ p[0;t] = ~ + ~ W N ~ v ^ K( k[i] ) ~ W N ~ v ^ K( k[i] ) p[0;t] ~ + ~ W N ~ v ^ K( k[i] ) p[0;t] + ~ W N ~ v ^ K( k[i] ) p[0;t] k + W D ~ v ^ K( k[i] ) p[0;t] + ~ W N ~ v ^ K( k[i] ) p[0;t] (By using (E.1)) k + W D p ~ v ^ K( k[i] ) p[0;t] + ~ W N p ~ v ^ K( k[i] ) p[0;t] k W D p + ~ W N p ~ v ^ K( k[i] ) p[0;t] + k (E.2) By Theorem 4.1,8t2T k[i] we have ~ v ^ K( k[i] ) p[0;t] ~ ^ K( k[i] ) p + B k[i] p tt k[i] +1 kk p[0;t k[i] 1] + P r ^ K( k[i] ) p + B r k[i] p krk p[0;t] ) ~ v ^ K( k[i] ) p[0;t] ~ ^ K( k[i] ) p + B k[i] p W N 1 p tt k[i] +1 ~ p[0;t k[i] 1] + P r ^ K( k[i] ) p + B r k[i] p krk p[0;t] (* =W N 1 ~ ) (E.3) 63 Then by substituting (E.3) in (E.2),8t2T k[i] we have ~ p[0;t] k W D p + ~ W N p W N 1 p ~ ^ K( k[i] ) p + B k[i] p tt k[i] +1 ~ p[0;t k[i] 1] + k W D p + ~ W N p P r ^ K( k[i] ) p + B r k[i] p krk p[0;t] + k (E.4) There are at mostN k +1 nite number of switching intervals overT k because the number of switchesN k overT k is nite by Lemma 4.2. Hence by the principle of induction using (E.4) over each switching interval of T k ,8t2T k we have ~ p[0;t] f k (t) ~ p[0;t k 1] +g 1 k krk p[0;t] +g 2 k (E.5) where f k (t) = h k W D p + ~ W N p i W N 1 p N k +1 N k Y i=0 ~ ^ K( k[i] ) p + B k[i] p tt k +1 g 1 k = N k X i=0 h k W D p + ~ W N p i W N 1 p i+1 P r ^ K( k[N k i] ) p + B r k[N k i] p i1 Y j=0 ~ ^ K( k[N k j] ) p + B k[N k j] p g 2 k = k + k N k X i=1 h k W D p + ~ W N p i W N 1 p i i1 Y j=0 ~ ^ K( k[N k j] ) p + B k[N k j] p 64 Appendix F Proof of Lemma 4.3 Let the system T shown in Fig. 2.1 be LTI system having an impulse response h(t). Then the weighted output w of the system T can be expressed in terms of inversely weighted impulse response h and weighted input r as follows. 2 6 6 6 6 6 6 6 4 t w(0) t1 w(1) . . . w(t) 3 7 7 7 7 7 7 7 5 = 2 6 6 6 6 6 6 6 4 h(0) 0 h(1) h(0) . . . . . . h(t) t h(t1) t1 h(0) 3 7 7 7 7 7 7 7 5 2 6 6 6 6 6 6 6 4 t r(0) t1 r(1) . . . r(t) 3 7 7 7 7 7 7 7 5 (F.1) Let h (t) be an impulse response of a LTI system T with input ~ r and output ~ w. Since we have dened T (z) =T (z) we get h (0) +h (1)z 1 +h (2)z 2 + =h(0) +h(1)(z) 1 +h(2)(z) 2 +::: which implies h (t) = h(t) t (F.2) 65 Therefore by Denition 2.5 and Denition 2.4 we have kTk p = sup krk p[0;t] 6=0;t0 kTrk p[0;t] krk p[0;t] = sup t0 2 6 6 6 6 6 6 6 4 h(0) 0 h(1) h(0) . . . . . . h(t) t h(t1) t1 h(0) 3 7 7 7 7 7 7 7 5 `p (By (F:1)) = sup t0 2 6 6 6 6 6 6 6 4 h (0) 0 h (1) h (0) . . . . . . h (t) h (t 1) h (0) 3 7 7 7 7 7 7 7 5 `p (By F:2) = sup k~ rk `p[0;t] 6=0;t0 kT ~ rk `p[0;t] k~ rk `p[0;t] =kT k `p 66 Appendix G Proof of Lemma 4.4 Let ~ = max K2K ~ K p P r = max K2K kP r K k p B = max 2Z + B p B r = max 2Z + kB r k p By Lemma 4.2, there exists N 2Z + such that8k2Z + we have N k N N h c So g 1 k ;g 2 k and f k (t) in Theorem 4.2 are bounded8t2T k and8k2Z + as follows g 1 k g 1 = X N i=0 h W D p + ~ W N p i W N 1 p i+1 ~ +B i (P r +B r ) (G.1) g 2 k g 2 = + X N i=1 h W D p + ~ W N p i W N 1 p i ~ +B i (G.2) 67 f k (t) " h W D p + ~ W N p i W N 1 p ~ +B # N +1 tt k +1 (G.3) Let f = " h ( +h c ) W D p + ~ W N p i W N 1 p ~ +B # N +1 (G.4) By Theorem 4.2 and the reset condition (4.4)8k2Z + we have f k (t k+1 1) t k+1 t k Therefore by (G.3) and (G.4), bound on a reset interval is given by f t k+1 t k ) log t k+1 t k log f ) t k+1 t k log f 68 Appendix H Proof of Theorem 4.3 Subject to Assumption 4.2, during each reset interval there is a cost detectable pair of cost functionV and feasible controller. Therefore the reset condition (4.4) in Algorithm 4.1 is satised at the end of each reset interval. Hence8k2Z + we have f k (t k+1 1) t k+1 t k where 2 (; 1). Therefore lim k!1 h 1 +f k (t k+1 1) +f k (t k+1 1)f k1 (t k 1) +::: +f k (t k+1 1):::f 0 (t 1 1) i = 1 1 (H.1) By the principle of induction using (E.5) over each reset interval from T 0 to T k and by using the following limit as k!1 zero initial state of the plant P Lemma 2.1 g 1 k g 1 and g 2 k g 2 ;8k2Z + 69 equation (H.1) 8t 0 we have ~ `1[0;t] 1 1 g 1 p p 1 p krk `1[0;t] +g 2 where g 1 and g 2 are mentioned in (G.1) and (G.2) respectively. 70 Bibliography [Arehart and Wolovich, 1996] Arehart, A. and Wolovich, W. (Dec 1996). Bumpless switching controllers. 35th IEEE Conference on Decision and Control, pages 1654{ 1655. [Battistelli et al., 2013] Battistelli, G., Hespanha, J., Mosca, E., and Tesi, P. (May 2013). Model-free adaptive switching control of time-varying plants. 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Abstract (if available)

Abstract In this thesis, the BHMT (Battistelli-Hespanha-Mosca-Tesi) reset mechanism which is a new scheme to control time-varying plant under the framework of unfalsified adaptive control is investigated. The reset condition is modified and the switching algorithm is improved to admit bumpless transfer at switching times, and to relax several restrictive assumptions. The reset condition is designed based on the gains of the control system components, making it adaptive, free of uncertain parameters, and practically implementable in a switching algorithm. Performance including stability is proved given only that the adaptive stabilization problem is feasible, removing the assumptions that the plant and controller are linear, and relaxing restrictions on controller state-initialization at switching times so as to allow bumpless transfer. Theoretical results are established considering proposed framework of switching time dependent generalized bumpless transfer system for switching of a controller. The proposed switching algorithm is nonlinear time-varying and it can control nonlinear time-varying plant using nonlinear controllers. An example is provided to support improved results.

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Creator Patil, Sagar V. (author)

Core Title Unfalsified adaptive control with reset and bumpless transfer

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 06/24/2016

Defense Date 04/25/2016

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag bumpless transfer,exponential stability,OAI-PMH Harvest,reset,unfalsified control

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Safonov, Michael (committee chair), Nayyar, Ashutosh (committee member), Udwadia, Firdaus (committee member)

Creator Email sagarpatil1986@gmail.com,sagarvpa@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c40-257195

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Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

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