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University of Southern California Dissertations and Theses
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Energy aware integrated circuits for communication and biomedical applications
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Energy aware integrated circuits for communication and biomedical applications
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ENERGY AWARE INTEGRATED CIRCUITS FOR COMMUNICATION AND BIOMEDICAL APPLICATIONS by Zahra Safarian A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulllment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2014 Copyright 2014 Zahra Safarian Dedication To my family ii Acknowledgements Firstly, I would like to thank my advisor, Prof. Hossein Hashemi, for being an excellent guide for me over the years. His energy, passion, and devotion to research and teaching have always been inspiring for me. I have learnt a lot from him which is going to help me forever in my professional career. I would like to thank the rest of my thesis and qualifying committee: Prof. Mike Chen, Prof. John Choma, Prof. Antonio Ortega, and Prof. James Weiland for their guidance and encouragement. I also thank my current and former labmates at Prof. Hossein Hashemi's group: Prof. Harish Krishnaswamy, Prof. Ta-shun Chu, Prof. Firooz A atouni, Dr. Ankush Goel, Dr. Behnam Analui, John Roderick, Masashi Yamagata, Alireza Imani, Timothy Mercer, Sushil Subramanian, Run Chen, Chenliang Du, Hooman Abedi, Fatemeh Rezaei, Pingyue Song, and Aria Samiei. They all have been great friends and help over the years. I am grateful for the family I have; I am lucky to have my husband Meisam and thank him for all of his love, support, patience and understanding. I would like to thank my brother and my sister-in-law for making me less homesick while being far iii way from family. And nally, I would like to thank my parents for providing every opportunity for me, and always trusting and supporting my decisions. This thesis is for all of your eort. iv Table of Contents Dedication ii Acknowledgements iii List of Tables viii List of Figures ix Abstract xxiv Chapter 1: Introduction 1 Chapter 2: Wirelessly Powered Passive Systems for Communication 8 2.1 Impedance Transformation Circuitry . . . . . . . . . . . . . . . . . 9 2.1.1 Bandwidth Limitation . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 Impedance Transformation Loss . . . . . . . . . . . . . . . . 14 2.1.3 Realizability of Components . . . . . . . . . . . . . . . . . . 16 2.2 Rectier Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.2 Full-Bridge Rectier . . . . . . . . . . . . . . . . . . . . . . 28 2.2.3 Four Transistor Cell . . . . . . . . . . . . . . . . . . . . . . 31 2.2.4 Technology Scaling . . . . . . . . . . . . . . . . . . . . . . . 37 2.3 Upper Bound on Power Harvester Performance . . . . . . . . . . . . 38 2.4 Passive Transponder with Dynamic Energy Storage and Sensitivity Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.1 Dynamic Energy Storage Mechanism . . . . . . . . . . . . . 42 2.4.2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . 45 2.4.3 Transponder Building Blocks . . . . . . . . . . . . . . . . . 50 2.4.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 55 2.5 Summary and Future Work . . . . . . . . . . . . . . . . . . . . . . 63 v Chapter 3: Wirelessly Powered Passive Downconverter Using Mem- oryless Nonlinearity 65 3.1 Concept and Implementation . . . . . . . . . . . . . . . . . . . . . 68 3.2 Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.2.1 Start-up Condition . . . . . . . . . . . . . . . . . . . . . . . 74 3.2.2 Steady State Solutions . . . . . . . . . . . . . . . . . . . . . 80 3.2.3 Eect of Detuning and Locking Range . . . . . . . . . . . . 82 3.2.4 MOSFET Nonlinear Core . . . . . . . . . . . . . . . . . . . 87 3.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.3.1 Discrete Frequency Downconverter . . . . . . . . . . . . . . 89 3.3.2 Integrated 12 GHz Divide-by-2 Self-Powered Divider . . . . 92 3.4 Summary and Future Work . . . . . . . . . . . . . . . . . . . . . . 95 Chapter 4: Event Driven Neural Recording System 96 4.1 Multichannel Neural Recording Systems . . . . . . . . . . . . . . . 99 4.1.1 System Requirements . . . . . . . . . . . . . . . . . . . . . . 102 4.1.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.2.1 Wake-up Receiver . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.2 Level-Crossing Detector . . . . . . . . . . . . . . . . . . . . 113 4.3 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.3.1 Probability of Detection and False Alarm . . . . . . . . . . . 120 4.3.2 Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.4 Summary and Future Work . . . . . . . . . . . . . . . . . . . . . . 135 Chapter 5: Implementation of the Multi-Channel Event Driven Neu- ral Recording System 137 5.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.2 Front-End Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.2.1 Low-Noise Neural Amplier . . . . . . . . . . . . . . . . . . 140 5.2.2 Successive Approximation ADC (SAR) . . . . . . . . . . . . 149 5.2.3 Precision Rectier . . . . . . . . . . . . . . . . . . . . . . . . 160 5.2.4 Level-Crossing Detector . . . . . . . . . . . . . . . . . . . . 161 5.3 Back-End Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.1 Power Management Unit . . . . . . . . . . . . . . . . . . . . 168 5.3.1.1 Wireless Battery Charger . . . . . . . . . . . . . . 171 5.3.1.2 Dual Output DC-DC Converter . . . . . . . . . . . 173 5.3.1.3 LDO and Bandgap . . . . . . . . . . . . . . . . . . 179 5.3.2 Clock Generation Circuitry . . . . . . . . . . . . . . . . . . 183 5.3.3 Uplink/Downlink Communication . . . . . . . . . . . . . . . 185 5.3.3.1 UWB Transmitter . . . . . . . . . . . . . . . . . . 186 5.3.3.2 PWM-ASK Demodulation . . . . . . . . . . . . . . 188 5.4 System Measurement Results . . . . . . . . . . . . . . . . . . . . . 189 vi 5.5 Summary and Future Work . . . . . . . . . . . . . . . . . . . . . . 195 Chapter 6: Conclusion 196 6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 References 199 Appendix Characterization of Process Used . . . . . . . . . . . . . . . . . . . . . . 208 vii List of Tables 1.1 Examples of energy sources for low-power sensors . . . . . . . . . . 4 2.1 Performance summary of the published rectiers . . . . . . . . . . . 38 2.2 Performance summary and comparison with recently published work 62 3.1 Performance Comparison among Dierent Passive and Active Dividers 94 4.1 Performance summary of the integrated neural recording systems . 107 4.2 Threshold voltages used in the simulation for dierent number of paths130 5.1 Input-referred noise and gain in dierent OTAs . . . . . . . . . . . 142 5.2 Devices geometries and DC operating points for the rst-stage of LNA144 5.3 Neural amplier performance summary and comparison with other works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.4 Comparison of dierent rechargeable batteries . . . . . . . . . . . . 170 5.5 Performance summary in comparison with other neural implant chips 194 viii List of Figures 1.1 The spread of the wireless sensors in the daily life. . . . . . . . . . . 2 1.2 General block diagram of a passive sensor with dierent sources of energy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Vision of restoring full motor function using brain-machine interfaces [48]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 (a) Dierent method for monitoring brain activity in the BMIs, and (b) their spatial resolution [85]. . . . . . . . . . . . . . . . . . . . . 7 2.1 A conceptual RF power harvester. . . . . . . . . . . . . . . . . . . . 8 2.2 (a) A lossless matching network with a parallel RC load representing the equivalent input impedance of the rectier, and (b) re ection coecient for optimum utilization of the Bode-Fano limit. . . . . . 10 2.3 Minimum achievable re ection coecients ( min ) for dierent load impedances when the bandwidth is (a) 26 MHz, and (b) 83 MHz. . 10 2.4 Maximum achievable voltage gain (V in =V s ) for dierent load impedances when the bandwidth is (a) 26 MHz, and (b) 83 MHz. . . . . . . . . 14 2.5 Eect of the inductor quality factor on the matching circuitry (a) eciency, and (b) voltage gain for dierent values of parallel load resistance, using the L-matching circuitry. . . . . . . . . . . . . . . 15 2.6 The inductor values and the achieved bandwidth at 915 MHz in the matching circuitry versus parallel load resistance for (a) 1-section L-matching circuitry, and (b) 2-section L-matching circuitry. . . . . 16 ix 2.7 Eect of the mismatch in inductor value on the voltage gain in the L-matching circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 The schematic of two common rectiers: (a) N -stage voltage multi- plier, and (b) self-driven synchronous rectier. . . . . . . . . . . . . 18 2.9 (a) Schematic of the voltage doubler, and (b) its transient voltage waveforms using ideal diode. . . . . . . . . . . . . . . . . . . . . . . 18 2.10 The large-signal model for (a) a PN diode, and (b) an NMOS transistor. 21 2.11 (a) Piecewise linear I-V curve, and (b) the voltage/current waveform of each diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12 The calculated (a) conduction angle , and (b) power eciency versus the device slope G m and V ON for the voltage doubler. . . . . 24 2.13 (a) Simulated I-V curve for the diode-connected regular transistors, and low voltage transistors (W=L = 5m=120nm), and the Schottky Barrier Diode (anode length=2m and width=5m), and (b) the zoomed view of the I-V curve. . . . . . . . . . . . . . . . . . . . . . 25 2.14 Simulated eciency of the voltage doubler versus transistor size for (a) V out = 0:375 V, and (b) V out = 0:75 V, while R load = 250 k for the voltage doubler. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.15 Schematic of the voltage doubler employing (a) diode-connected tran- sistors, and (b) transistors with comparators to reduce voltage drop. 26 2.16 The eciency degradation due to (a) the substrate loss, and (b) the gate resistance loss for the voltage doubler while V out = 0:375 V, R load = 250 k , and W = 5m. . . . . . . . . . . . . . . . . . . . . 26 2.17 (a) The input resistance R in and the required inductance value for matching, and (b) the matching circuitry and rectier eciency ver- sus number of stages. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.18 (a) Schematic of the full bridge rectier, and (b) the voltage/current waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.19 The calculated (a) conduction angle , and (b) power eciency versus the device slope G m and V ON for the full-bridge rectier. . . 32 x 2.20 Simulated eciency of the bridge rectier versus transistor size for (a) V out = 0:375 V, and (b) V out = 0:75 V, while R load = 250 k . . . 32 2.21 The eciency degradation due to (a) the substrate loss, and (b) the gate resistance loss for the bridge rectier while V out = 0:375 V, R load = 250 k , and W = 5m. . . . . . . . . . . . . . . . . . . . . 32 2.22 (a) Self-driven synchronous rectier (four transistor cell), (b) and the voltage/current waveforms across a transistor. . . . . . . . . . . 33 2.23 (a) Forward and reverse conduction loss, and (b) eciency versus device size V out = 0:375 V for the four transistor cell. . . . . . . . . 34 2.24 Simulated eciency of the self-driven synchronous rectier versus transistor size for (a) V out = 0:375 V, and (b) V out = 0:75 V, while R load = 250 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.25 Schematic of the four-transistor cell employing comparators to re- duce reverse conduction. . . . . . . . . . . . . . . . . . . . . . . . . 35 2.26 The eciency degradation due to (a) the substrate loss, and (b) the gate resistance loss in the four transistor cell while V out = 0:375 V, R load = 250 k , and W = 5m. . . . . . . . . . . . . . . . . . . . . 36 2.27 The simulated (a) I-V curve for a regular transistor with minimum channel length andW = 5m width, and (b) eciency of the voltage doubler versus transistor width for V out = 0:75 V and R load = 250 k in 65 nm and 130 nm technology. . . . . . . . . . . . . . . . . . 36 2.28 Simulated eciency of the voltage doubler versus frequency forV out = 0:75 V and R load = 250 k for in 65 nm and 13 0nm technology. . . 37 2.29 The power up thresholdP av;th for the bandwidth (a) 0, (b) 26 MHz, and (c) 83 MHz as the function ofV in;th andC in , assumingQ ind = 40, rectifier = 50%, R s = 50 , and P out = 2 W . . . . . . . . . . . . . 39 2.30 The total system eciency for the bandwidth (a) 0, (b) 26 MHz, and (c) 83 MHz as the function of V in;th and C in , assuming Q ind = 40, rectifier = 50%, R s = 50 , and P out = 2 W . . . . . . . . . . . 39 2.31 Dynamic energy storage mechanism: (a) concept, and (b) implemen- tation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 xi 2.32 The extension of the power range of the power harvester with dy- namic energy storage. . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.33 Conceptual block diagram of the proposed sensor with dynamic en- ergy storing and sensitivity enhancement. . . . . . . . . . . . . . . . 45 2.34 The transponder (a) passive operation mode, (b) passive operation with energy saving mode, and (c) semi-passive (extended sensitivity) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.35 The detail block diagram of the wireless transponder prototype with dynamic energy storage and sensitivity enhancement. . . . . . . . . 47 2.36 (a) The communication sequence used for the prototype transponder, the generated waveforms in (b) the semi-passive mode, and (c) the passive mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.37 The schematic of the rectier in the main and storage paths. . . . . 50 2.38 (a) The schematic of the threshold detector circuitry, and (b) the timing diagram of the circuitry. . . . . . . . . . . . . . . . . . . . . 51 2.39 The schematic of the envelope detector. . . . . . . . . . . . . . . . . 52 2.40 The schematic of (a) PWM demodulator, (b) modulator, (c) POR circuitry, (d) V DD switches, and (e) logic control circuitry. . . . . . . 53 2.41 Chip microphotograph of the fabricated transponder. . . . . . . . . 55 2.42 (a) The measurement set-up for transient V DD1 and V DD2 , the mea- sured transient waveforms of V DD1 and V DD2 at 2.4 GHz during charging and discharging using a 1.2F capacitor (C 2 ) for (b) Pin=-8 dBm, and (c) 0 dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.43 (a) The measurement set-up, the measured (solid) and simulated (dashed) steady-state V DD1 andV DD2 versus input power at (b) 900 MHz, (c) 2.4 GHz, and (d) 5.8 GHz. . . . . . . . . . . . . . . . . . 57 2.44 (a) The measurement set-up for passive mode operation, the mea- sured (b) input envelope, (c)V DD1 , (d) data signal, and (e) modula- tor output at 0.9GHz. . . . . . . . . . . . . . . . . . . . . . . . . . 58 xii 2.45 Measured V DD1 and V DD2 when (a) P in =-29 dBm<P th =-19.5 dBm, and (b) input signal is a sequence of P in =-16.5 dBm> P th =-19.5 dBm and P in =-29 dBm<P th =-19.5 dBm. . . . . . . . . . . . . . . . 59 2.46 The measured semi-passive mode operation at 0.9 GHz when P in is a sequence of -16.5 dBm and -29 dBm, (a) input envelope, and WUS/PM signal; zoomed views of input envelope, data signal, and modulator output in (b) passive, and (c) semi-passive modes. . . . . 60 2.47 The measured original and enhanced sensitivity of the transponder. 61 2.48 (a) The matching circuitry, the measured (b) V DD1 and V DD2 , and (c) S 11 before and after the matching versus available input power at 900 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.49 (a) The wireless measurement setup, and (b) the received backscat- tered data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.1 (a) Conventional wireless power harvester along with a representative simulated eciency, and (b) an alternative high frequency power harvester. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.2 (a) Generic frequency downconverter and divider, and (b) parametric frequency divider using a varactor. . . . . . . . . . . . . . . . . . . 67 3.3 (a) Self-sustained oscillator, and (b) the proposed passive subhar- monic generator using memoryless nonlinear circuitry. . . . . . . . . 68 3.4 Input/output voltage waveforms when (a)! in = 2! out , and (b)! in = 10! out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.5 Self-powered downconverter with state-variables along with its sim- plied second-order model. . . . . . . . . . . . . . . . . . . . . . . . 71 3.6 Transient behavior of the circuitry for (a) V in = 0:68 V, and (b) V in = 0:7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.7 Minimum required input power for start-up, P in;th , whenn = ! in !out = 2 versus (a) resonator quality factor Q, (b) resonator capacitance C, and (c) BJT saturation current I S . . . . . . . . . . . . . . . . . . . 79 xiii 3.8 (a) Minimum required input power for start-up, P in;th , versus n = ! in !out when Q = 13, and (b) normalized minimum required input power for start-up P in;th (n3) P in;th (n=2) versus resonator quality factor (Q). . . 80 3.9 Variation of (a) the steady-state amplitudes r ss , and (b) the power eciency asP in varies forf in = 2f out = 5:29 MHz and whenQ = 13. 81 3.10 Variation of the power eciency versus n for r = 50 mV and r = 150 mV when Q = 13. . . . . . . . . . . . . . . . . . . . . . . . 82 3.11 Dierent scenarios for the oscillator output signal, when it is detuned more than it can tolerate at dierent V in : (a) V in1 , (b) V in2 , and (c) V in3 , where V in1 < V in2 < V in3 . Zoomed versions are shown in the respective insets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.12 Phase portrait of the circuitry around the stable point at dierent values of n (a) n = 2, (b) n = 1:97, (c) n = 1:95, and (d) n = 1:93 for Q = 13 and V in = 0:695 mV. . . . . . . . . . . . . . . . . . . . . 84 3.13 (a) Input power at the edge of oscillation dying and pulling versus tank quality factor (Q), locking (tuning) range versus input power (b) at N = 2 for Q = 13 and 6, and (c) N = 1 and N = 4 for Q = 13. 86 3.14 Simulated minimum required input power for start-up, P in;th versus (a) n = ! in !out , and (b) NMOS channel width W at n = 2; (c) the steady-state amplitudes r ss , and (d) locking (tuning) range versus P in at n = 2 and Q = 13. . . . . . . . . . . . . . . . . . . . . . . . . 88 3.15 (a) The detailed schematic, and (b) the board photograph of the discrete low-frequency prototype. . . . . . . . . . . . . . . . . . . . 89 3.16 (a) The measurement setup, and the measured input and dierential output waveforms when (b) f in = 2f out , and (c) f in = 10f out . . . . . 90 3.17 (a) The measurement setup, and measured, simulated, and calcu- lated (b) minimum required input power (P in;th ) for subharmonic generation versus the input frequency, (c) locking (tuning) range, (d) output amplitude, and (e) power eciency versus input power at n = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 xiv 3.18 Measured output waveforms when the downconverter is pulled for n = 2 at (a) P in1 and (b) P in2 , where P in1 <P in2 . Zoomed versions are shown in the respective insets. . . . . . . . . . . . . . . . . . . . 92 3.19 (a) Detailed schematic, and (b) chip microphotograph of the inte- grated 12 GHz divide-by-2 self-powered divider. . . . . . . . . . . . 93 3.20 Measured and simulated (a) S 11 (return loss), (b) sensitivity curve, measured (c)P in;th versus the transistor bulk voltage, and (d) phase noise of the signal generator and the 12 GHz divider output. . . . . 94 3.21 Alternative conguration for the proposed passive subharmonic gen- erator without any DC power supply and their representative inpu/output waveforms: (a) dierential cross-coupled oscillator with tail transis- tor and (b) dierential noise-shifting Colpitts oscillator (f in = 2f out ) [2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.1 (a) Action potential waveform, (b) 3D top/bottom view of the Utah Microelectrode Array (MEA) [21], and (c) simplied microelectrode small-signal model [62]. . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.2 Neural recording from cat motor cortex using Utah microelectrode array [35]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.3 Block diagram of the generic neural recording systems with wireless telemetry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4 Simplied view of dierent congurations for implantable system for cortical recording, (a) all the system is above the skull, (b) all the system is below the skull, and (c) the dual-chip system. . . . . . . . 101 4.5 Electrode thermal noise versus electrode resistance for f = 10 kHz and T=37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.6 (a) Schematic of one channel in the conventional neural recording system, along with the energy costs for (b) neural ampliers, (c) ADC, and (d) short-range transmitters. . . . . . . . . . . . . . . . . 109 4.7 Schematic of one channel in the duty-cycling wake-up neural record- ing system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 xv 4.8 The calculated reduction ratio for the (a) data rate, and (b) power consumption resulting from duty-cycling wake-up system. . . . . . . 111 4.9 The generic scheme for the wake-up receiver. . . . . . . . . . . . . . 111 4.10 Single-threshold wake-up receiver along with its response to the spike and noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.11 (a) The shape of the spike V i;spike with the woken-up signal ^ V i;spike along with the variation of the mean squared error versus V th =V peak for the spike shown, and (b) upper bound on the number of false alarm in 1 second versus V th = N . . . . . . . . . . . . . . . . . . . . 113 4.12 Dierent action potentials waveforms recorded extracellularly. . . . 114 4.13 (a) Dual-threshold wake-up receiver, its response to (b) the spike, and (c) the noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.14 (a) Input signal corrupted with noise, and the response of (b) the single-threshold receiver, and (c) the dual-threshold receiver. . . . . 115 4.15 The generic scheme for the level crossing pre-processing. . . . . . . 117 4.16 (a) The correlator, and (b) the level crossing detector. . . . . . . . . 118 4.17 Bank of correlators with template shifting. . . . . . . . . . . . . . . 119 4.18 The dual-threshold scheme and simplied model for the slope detection.121 4.19 The model assumed for the noise. . . . . . . . . . . . . . . . . . . . 122 4.20 The error caused by the noise on the time and position of crossing point ( N1 < N2 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.21 (a) The ramp signal, and (b) the Gaussian noise. . . . . . . . . . . 122 4.22 The simulated (a) probability of detection, and (b) number of false alarm versus noise variance ( N ) for the ramp signal when V th2 = 1. 123 4.23 The simulated probability of detection and number of false alarm in 1 sec. versus the two threshold voltages V th1 and V th2 for the ramp signal when (a) N = 0:1, and (b) N = 0:2. . . . . . . . . . . . . . 124 xvi 4.24 The simulated probability of detection versus the threshold voltages V th1 and input amplitude/input slope when (a) V th2 = 1, (b) V th2 = 0:9, (c) V th2 = 0:8, and (d) V th2 = 0:7; N = 0:2. . . . . . . . . . . . 125 4.25 The triple-threshold scheme and simplied model for the slope de- tection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.26 The simulated (a) detection probability versus V th3 for the ramp signal when N th = 2, (b) N th = 1, and (c) number of false alarm versus V th3 in the triple-threshold scheme; V th1 = 0:2 V, V th2 = 1 V, and N = 0:2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.27 The quadruple-threshold scheme and simplied model for the slope detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.28 The simulated detection probability for the ramp signal in the quadruple- threshold scheme versusV th4 for (a)V th3 = 0:3 V, and (b)V th3 = 0:5 V; N th = 3, V th1 = 0:2 V, V th2 = 1 V, and N = 0:2. . . . . . . . . . 128 4.29 The simulated detection probability and number of false alarm in the quadruple-threshold scheme versusV th4 and dierentN th for the ramp signal; V th1 = 0:2 V, V th3 = 0:5 V, V th2 = 1 V, and N = 0:2. . 128 4.30 (a) The waveforms for the one cycle of sinusoidal signal and expo- nential pulse signal, the simulated detection probability and false alarm versus N th for (b) one cycle of sinusoidal signal (V th1 =0:3 V, V th3 =0:5 V, and V th2 =0:7 V), and (c) exponential pulse signal (V th1 = 0:3 V, V th3 = 0:5 V, V th2 = 0:8 V), and N = 0:2 . . . 129 4.31 The simulated ROC curve for dierent number of levels (N ) andN th for (a) one cycle of sinusoidal signal, and (b) exponential pulse signal when N = 0:2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.32 The simulated ROC curve for the bank of correlators with dier- ent number of paths for the template shifting (M ) and V th for (a) one cycle of sinusoidal signal, and (b) exponential pulse signal, in comparison with the level crossing detector. . . . . . . . . . . . . . 131 4.33 Dierent waveforms of the spike and noise used in the simulation. . 133 xvii 4.34 The simulated ROC curves for dierent number of paths, thresh- old voltages (V th2 , V th3 , and V th4 ), and N th ; V th1 = 0.3 V, for the corresponding spike waveforms shown in Fig. 4.33. . . . . . . . . . . 134 4.35 (a) Eect of comparator oset on the timing error, and (b) the sim- ulated probability of detection versus threshold-level oset inV th1 in the dual-threshold scheme, while V th2 = 1. . . . . . . . . . . . . . . 135 4.36 Eect of a linear and non-linear amplier on the output of the level crossing pre-processing. . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.1 Block diagram of the multi-electrode neural recording and signal conditioning front-end chip. . . . . . . . . . . . . . . . . . . . . . . 138 5.2 Block diagram of the back-end wireless power harvesting and wireless telemetry chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3 The microphotograph of (a) the 10-channel front-end, and (b) back- end chips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.4 Schematic of OTA-based neural signal amplier with capacitive feed- back along with its frequency response. . . . . . . . . . . . . . . . . 141 5.5 The schematic of the (A) folded cascode, (b) telescopic, and (c) inverter-based OTA. . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.6 The detail schematic of the rst stage low noise amplier along with the OTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.7 The detail schematic of the second stage amplier in the main path. 145 5.8 The detail schematic of the third stage amplier in the main path. . 146 5.9 The simplied schematic of the output stage of the third amplier along with its half circuit schematic. . . . . . . . . . . . . . . . . . 146 5.10 The eect of the gate resistance on the (a) frequency, and (b) tran- sient response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.11 (a) The schematic of the second/third amplier in the wake-up path, the transistor sizing for (b) the second amplier, and (c) the third amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 xviii 5.12 Measured and simulated frequency response of the three-stage LNA in the main path: (a) highest and lowest gain setting, and (b) highest and lowest high-pass corner setting. . . . . . . . . . . . . . . . . . . 147 5.13 Measured and simulated (a) input-referred noise, and (b) CMRR of the three-stage LNA in the main path. . . . . . . . . . . . . . . . . 149 5.14 (a) Input signal along with the generated WUS, and (b) measured transient response of the three-stage LNA in the main path upon receiving the WUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.15 Measured sinusoidal output signal for the ampliers in the main and wake-up paths at a frequency of 1 kHz for (a) 200V , and (b) 1 mV peak-to-peak input signals. . . . . . . . . . . . . . . . . . . . . . . . 150 5.16 (a) Measured and simulated frequency responses of the amplier in the wake-up path; (b) measured CMRR of the amplier in the wake- up path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.17 (a) The detailed schematic of the SAR ADC, along with its timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.18 (a) Sampler and the capacitive DAC, and (b) layout of the DAC. . 153 5.19 The schematic of the dynamic comparator. . . . . . . . . . . . . . . 154 5.20 (a) The schematic of the voltage booster, and (b) the extracted sim- ulation of the booster. . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.21 Simulated RC extracted sampler with booster at (a) 927 Hz, and (b) 9.213 kHz, while the sampling frequency is 20 kS/s. . . . . . . . . . 155 5.22 (a) The schematic of the successive approximation register (SAR), and (b) the synthesized control circuitry. . . . . . . . . . . . . . . . 156 5.23 Synthesized serializer and digital data organizer. . . . . . . . . . . . 157 5.24 Simulated ADC performance (a) at 927 Hz (schematic), (b) at 9.213 kHz (schematic), (c) at 927 Hz (RC extracted), and (d) at 9.213 kHz (RC extracted), all in the typical corner. . . . . . . . . . . . . . . . 157 xix 5.25 (a) A section of the SAR which has timing problem, the simulated waveforms in the SAR in the (b) TT corner (schematic), (c) TT corner (RC extracted), (d) FS corner (RC extracted) along with the zoomed-view version (the solid line are none-extracted while the dashed line are RC extracted). . . . . . . . . . . . . . . . . . . . . . 159 5.26 (a) The conventional precision rectier (half-wave), and (b) the pro- posed rectier with a representative simulation. . . . . . . . . . . . 161 5.27 (a) The schematic of the comparator with oset cancellation used in the rectier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.28 (a) The measurement setup, and (b) a representative measurement demonstrating functionality of the precision rectier. . . . . . . . . 162 5.29 The schematic of the level crossing detector. . . . . . . . . . . . . . 163 5.30 The schematic of the comparator with oset cancellation in the rec- tier with threshold variation. . . . . . . . . . . . . . . . . . . . . . 164 5.31 A representative simulation demonstrating functionality of the oset cancellation circuitry: the comparator output and the voltage oset (a) before, and (b) after oset cancellation. . . . . . . . . . . . . . . 166 5.32 The schematic of the variable pulse width timer circuitry. . . . . . . 166 5.33 (a) Edge Counter, (b) decision circuitry, and (c) the WUS generation.167 5.34 The measured output of the variable pulse width timer circuitry for the (a) 3-bit MSB variations and (b) 4-bit LSB variation. . . . . . . 167 5.35 (a) The measurement setup, and (b) a representative measurement demonstrating functionality of the oset cancellation circuitry. . . . 168 5.36 (a) The measurement setup, and representative measurement demon- strating functionality of the wake-up receiver with level-crossing de- tector for (b) N = 2, (c) N = 3 with N th = 1 and 2, and (d) N = 4 with N th = 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.37 the block diagram of the wireless battery charger. . . . . . . . . . . 170 xx 5.38 The rectier and the matching circuitry along with it simulation results for V rect = 1.5 V and I dc = 2.2 mA. . . . . . . . . . . . . . . 171 5.39 The schematic of the (a) battery charger, (b) charging control cir- cuitry, and (c) battery-status circuitry. . . . . . . . . . . . . . . . . 174 5.40 The complete simulation of the battery charger (a) versus initial voltage on the battery, and (b) dierent voltage node: red is RC- extracted and blue is original. . . . . . . . . . . . . . . . . . . . . . 174 5.41 The schematic of the step down switched-capacitor DC-DC converter for (a) V DD1 = 1 3 V DD , and (b) V DD2 = 2 3 V DD . . . . . . . . . . . . . . 175 5.42 The schematic of the capacitance sharing dual output DC-DC con- verter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.43 The schematic of the 4-phase non-overlapping clock generation cir- cuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.44 (a) The measurement setup, the measured (b) power eciency, (c) V DD1 , and (d) V DD2 versus R 1 and R 2 . . . . . . . . . . . . . . . . . 178 5.45 The schematic of the (a) 0.7 V LDO, (b) the two-stage opamp, and (c) simplied small-signal model with the desired position of the poles and zeros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.46 The variation of (a) Power Supply Rejection (PSR), (b) transient responde, and (c) open-loop phase margin and unity-gain frequency versus load resistance R L . . . . . . . . . . . . . . . . . . . . . . . . 180 5.47 The schematic of the (a) 0.35 V LDO, (b) the self-biased opamp, and the variation of (b) PSR, (c) open-loop phase margin and unity-gain frequency versus load resistance R L . . . . . . . . . . . . . . . . . . . 181 5.48 The schematic of the 0.35 V and 0.7 V bandgap circuitry. . . . . . . 181 5.49 (a) The transient response of the bandgap, the variation of the bandgap voltage versus (b) temperature, and (c) V BAT . . . . . . . . 182 5.50 The schematic of the (a) proposed clock generation circuitry, (b) the crystal oscillator, (c) the amplier and rectier. . . . . . . . . . . . 184 xxi 5.51 The transient response and dierent voltage nodes of the clock gener- ation circuitry when start-up condition (a) is satised, (b) not satised.185 5.52 The schematic of the UWB transmitter. . . . . . . . . . . . . . . . 187 5.53 (a) The measurement setup, the measured (b) transient waveform, (c) power consumption versus data rate. . . . . . . . . . . . . . . . 187 5.54 The schematic of the (a) envelope detector, and (b) PWM demodulator.188 5.55 A representative simulation for envelope detector and PWM demod- ulator for (a) bit 0, and (b) bit 1. . . . . . . . . . . . . . . . . . . . 188 5.56 The measurement setup of a complete system. . . . . . . . . . . . . 190 5.57 (a) The pre-recorded neural data, (b) the measured WUS, (c) the reconstructed output of the ADC in the raw mode and activity- dependant mode (wake-up mode) along with its zoomed-view ver- sion, the output of UWB transmitter in the (d) raw mode, and (e) activity-dependant mode. . . . . . . . . . . . . . . . . . . . . . . . . 190 5.58 (a) The measurement setup, the measured (b) ROC curve for dif- ferent number of paths N and N th , and (c) probability of detection versus the input amplitude. . . . . . . . . . . . . . . . . . . . . . . 192 5.59 The measured (a) correlation coecient and MSE versus input am- plitude, and (b) ON duration versus spike ring rate. . . . . . . . . 193 5.60 Power breakdown of the overall neural recording system in (a) raw mode, wake-up mode when all the channels have the (b) maximum, and (c) minimum ring rate. . . . . . . . . . . . . . . . . . . . . . . 193 .1 Metal stack for the CMOS 8RF process. . . . . . . . . . . . . . . . 209 .2 Drain current versusV DS for dierent values ofV GS for an NMOS of width 10 1 m and minimum channel length. . . . . . . . . . . . 209 .3 Transconductance versusV DS for dierent values ofV GS for an NMOS of width 10 1 m and minimum channel length. . . . . . . . . . . 210 xxii .4 (a) Drain current versus V GS , (b) transconductance versus V GS , and (c) the ratio of g m /I D versus drain current for an NMOS of width 10 1 m and minimum channel length. V DS is kept at 1.5V. . . . 210 .5 f T vs. drain current for an NMOS of width 10 1m and minimum channel length. V DS is kept at 1.5V. . . . . . . . . . . . . . . . . . . 211 .6 NF min vs. frequency for dierent drain currents for an NMOS of width 10 1 m and minimum channel length. V DS is kept at 1.5V. 211 xxiii Abstract The thesis presents system level and block level integrated circuit solutions for low power wirelessly powered passive sensors, specically biomedical implants and RFID systems. Wirelessly-powered battery-less sensors extract the required energy from ex- ternal radiators. As such, their sensitivity is very low. Chapter 2 presents the theoretical and practical constraints on RF power scavenging at low incident power levels. The concept of dynamic energy storage is introduced enabling an extended operation of battery-less systems wirelessly powered. As a proof of concept, an inte- grated wirelessly-powered passive transponder with dynamic energy storage mech- anism and sensitivity enhancement, realized in a 130 nm CMOS technology, is demonstrated. Millimeter-wave power harvesting can lead to a self-contained, CMOS-only sys- tem, since the antenna size can be reduced to enable on-chip integration. However, as frequency increases, the RF-to-DC power conversion eciency decreases. One possible solution for mm-wave power harvesting which may result in a more e- cient system is to have an ecient battery-less frequency downconversion scheme xxiv followed with an ecient low-frequency rectier. Chapter 3 presents a novel passive subharmonic generation and frequency downconversion method, using a memory- less nonlinear circuit coupled to a linear passive resonator, to transfer the energy from a high frequency signal to a lower frequency without requiring any DC power supply. A detailed nonlinear analysis is provided to determine the characteristic of the circuitry, and design trade-os have been shown for the specic case of a cross- coupled dierential pair nonlinearity. Analytical results and design procedures are veried in a discrete low-frequency and an integrated high-frequency prototypes. Advancements in the Micro-Electro-Mechanical Systems (MEMS) and inte- grated electronics enable implantable systems for various health-care applications. Neural recording systems are one of the important bioimplant devices, since they can enable accurate study of brain neurological activities, as well as creating neu- roprosthetics devices to help the disabled people. Neural implants have stringent requirements on the power and area consumption. In order to reduce the energy consumption, a new event-driven scheme is proposed in chapter 4. Chapter 5 presents design and implementation aspects of an implantable neural system that utilizes the aforementioned event-driven concept as well as several low-voltage de- sign techniques. A prototype has been implemented in a 130 nm CMOS technology to verify the operation principle of the proposed concepts. Chapter 6 concludes the thesis by providing the summary and oering ideas for future research following this work. xxv Chapter 1 Introduction It is conceivable that the world we live in will become a world where physical sensors, including medical, environmental, mechanical, commercial, etc. ones are pervasively utilized where they can communicate wirelessly with each other and wireless hobs such as micro base stations, handheld phones, etc. (Fig. 1.1). In all of these cases, long-term battery life/self-powered operation, low cost, and small size are vital. These sensors can use either battery as the energy source or harvest energy from the environment. Therefore, they can be divided into dierent categories, depending on power generation method [24]: Active sensors use the battery as their energy source; therefore, they have a longer wireless communication range and better processing capability, while they are typically more expensive and bulky. 1 Figure 1.1: The spread of the wireless sensors in the daily life. Passive sensors scavenge the required energy from external or ambient sources; therefore, they have shorter wireless communication range and limited pro- cessing capability, while they are typically cheaper and more compact. Semi-passive (semi-active) sensors are equipped with a battery as well as energy scavenging capability where the latter can be used to recharge the battery as well. These sensors typically cover moderate wireless communi- cation distance, posses moderate processing capability, and hence a modest price (primarily due to using cheaper battery). The most common energy scavengers transduce solar energy [30][10], temperature gradient [75][61], vibrational energy [11][60], or electromagnetic radiation emitted by radio Frequency (RF) sources [47][68] into electrical energy (Fig. 1.2). Another energy source for biomedical applications is bio-fuel cells utilizing glucose from 2 Figure 1.2: General block diagram of a passive sensor with dierent sources of energy. blood [58] where they are at the early stage of development. Table 1.1 summa- rizes the average power density for dierent powering methods. The main factors aecting the implementation of theses sensors are their size, cost, and energy con- sumption. The size of a sensor node is mainly determined by the size of energy storage device and the energy transducer as well as the footprints of other sensor components. Low-power circuit design and ecient power delivery are required for operation given battery or energy harvesting footprint constraints. There is no universally optimum solution across all applications. In fact, it is conceivable that some sensors will be powered by a combination dierent types of energy sources, e.g., solar and RF energy scavenging. The rst part of this thesis will focus on the RF wirelessly powered passive systems. Wirelessly powered passive systems harvests energy from the received RF signal and generate the required DC voltage to power up the sensor. They can be used in many sensors such as RFID systems, or biomedical implants [27]-[25]. However, their sensitivity is typically worse than -20 dBm when powered by high- frequency RF sources (e.g., 900 MHz and 2.4 GHz), due to the limitation of the RF 3 Table 1.1: Examples of energy sources for low-power sensors Source Power/Power Density Comment Batteries Primary battery [81] 90 W/cm 3 /year - Secondary battery [81] 34 W/cm 3 /year - Ultracapacitor [81] 1.6-3.2 W/cm 3 /year - Vibration [78] 40 W Piezoelectric, 35 mg mass, 1.8 kHz [81] 335 W Piezoelectric, 2.25 ms 2 , 60 Hz Thermal [53] 250 W Ambient indoor temperature [93] 24 W 2.7 V at T = 5 C Photovoltaic [29] 5 W 150 m 150 m, 20k LUX Solar [81] 15 mW=cm 2 outdoor Glucose bio-fuel cell [58] 2.8 W/mm 2 - Electromagnetic [50] 6 mW Inductive, 7 cm spacing, 13.56 MHz [47] 1 W Far-eld, 7.5 m spacing, 906 MHz power harvesting circuitry. In Chapter 2, we study the theoretical and practical constraints on the RF power scavenging at low incident power levels. The concept of dynamic energy storage is introduced to enable the operation of the passive systems at very low input power levels. Given the interest in compact low-power sensors, extracting energy from even higher RF frequencies is advantageous from the antenna size standpoint. In Chap- ter 3, a passive downconverter, using memoryless nonlinearity, is introduced that can be specially useful for mm-wave power harvesting. The characteristics of the self-powered frequency downconverter have been studied analytically, and veried through simulations and measurements. 4 One important area where low-power sensors are envisioned is within the biomed- ical implanted devices. Among the most well-known and pervasive electronic im- plants are cardiac pacemakers [99][101] and cochlear implants [66][65]. However, recent advances in Micro-Electro-Mechanical Systems (MEMS) and integrated elec- tronics along with a better understanding of human body has lead to new era for implantable electronic systems. Some of the recently FDA approved implants are Deep-Brain Stimulators (DBS), used to treat chronic pain, Parkinsons disease, tremor and dystonia [45], and articial retinas for restoring vision [39]. Another application of an implantable electronic system which is at a much earlier develop- ment stage compared to the previously introduced technologies, and is currently a topic of much research, is the Brain-Machine Interfaces (BMI). The ultimate goal of brain-machine interfaces is to restore full motor function for people suering from conditions such as spinal cord injuries through creating a direct communication between the human brain and a machine such as a computer. The basic concept is to sense and record the neural signals in the brains motor cortex, interpret the human intention from the recording signals, and then control a prosthetic device such as a robotic arm to perform the intended movement (Fig. 1.3) [48]. There are dierent methods for monitoring the brain activity (Fig. 1.4). Elec- troencephalograms (EEG) signals represents the overall brain activity recorded from sensors and electrodes on top of the head on the scalp; thus, they are completely 5 Figure 1.3: Vision of restoring full motor function using brain-machine interfaces [48]. non-invasive. However, EEG recording suers from low spatial and temporal resolu- tion since it represents the combination of the electrical activity of a large number of neurons. Brain activity may also be measured via electrodes on the cortical surface, using a technique that is called Electrocorticography (ECoG). The brain activity can also be monitored by depth microelectrodes with diameters of only a few 10s of m that are implanted deep in the brain (100s of m to a few mm) where the activity of the single neuron can be recorded. This method provides the highest spatial resolution, and clearly is much more invasive than EEG or ECoG; however, the increased safety risk is outweighed by the increased signal delity in many cases. The remainder of this thesis, Chapter 4 and 5, will look into this type of low-power sensing. Specically, new architectures, along with circuit techniques, are proposed to reduce the power consumption of this energy-constrained system. 6 Figure 1.4: (a) Dierent method for monitoring brain activity in the BMIs, and (b) their spatial resolution [85]. Finally, Chapter 6 concludes this thesis by summarizing the technical contributions, in addition to addressing topics for future research. 7 Chapter 2 Wirelessly Powered Passive Systems for Communication A generic RF power harvester consists of an antenna, an impedance transformation network, a rectier, and an energy storage element or load (Fig. 2.1). At very low incident power levels, the design of the RF power harvester circuit is challenging, resulting to the fact the RF-powered passive systems typically have sensitivity level worse than -20 dBm [79][89][3][74][42]. In this chapter, we rst analyze the theoretical and practical limitations of RF power harvesting with emphasis on power Figure 2.1: A conceptual RF power harvester. 8 eciency. Then, the concept of the dynamic energy storage is introduced to enable the operation of the RF-powered passive systems at very low incident power levels. An experimental wirelessly powered passive transponder that harvests energy from and communicates with a reader is demonstrated as a proof of concept prototype. 2.1 Impedance Transformation Circuitry Rectication is a nonlinear process. Therefore, the rectier devices must see large enough signal to act nonlinearly. Consequently, rectiers do not operate at small input signal amplitudes, in a so-called dead zone. Device and circuit level techniques have been used to reduce the dead zone. Examples include low- or zero-threshold transistors [104][97], Schottky diodes [71][98], etc. In order to enable energy harvesting at low input signal levels, the input am- plitude must be amplied passively before going to rectiers. By adding a passive impedance matching network between the antenna and the rectier, optimum power transfer and voltage gain boosting can be realized simultaneously. Theoretical and practical limits on impedance matching and voltage gain boosting will be discussed next. 2.1.1 Bandwidth Limitation There exists a fundamental limitation on the bandwidth over which an arbitrarily good impedance matching can be obtained for a complex load impedance. According 9 Figure 2.2: (a) A lossless matching network with a parallel RC load representing the equivalent input impedance of the rectier, and (b) re ection coecient for optimum utilization of the Bode-Fano limit. Figure 2.3: Minimum achievable re ection coecients ( min ) for dierent load impedances when the bandwidth is (a) 26 MHz, and (b) 83 MHz. 10 to Bode and Fano [9][22], the fundamental limitation on impedance matching to a parallel RC load impedance using a lossless matching circuitry can be derived as Z +1 0 ln 1 j(!)j d! R L C L ; (2.1) where (!) is the re ection coecient of the load with respect to the source impedance, R S , and R L and C L represent the load impedance (Fig. 2.2 (a)). The best exploitation of R L C L limit is to keep (!) constant ( min ) over the desired band, !, and unity outside this band (complete mismatch) as shown in Fig. 2.2 (b). In this case, ! ln 1 j min j R L C L ; (2.2) or j min je 1 2fR L C L ; (2.3) where f = ! 2 . The above equation oers a direct trade-o between the maxi- mum bandwidth and the maximum power transfer to the load for a given RC load impedance, which is a good model for the input impedance of a typical rectier 1 (Fig. 2.1). The trade-o between the quality of impedance transformation, cap- tured by min , and the operating bandwidth is evident from Eq. 2.2. Fig. 2.3 shows the minimum achievable re ection coecients, min , for dierent load impedances, 1 Describing function can be used to dene an eective input impedance for the nonlinear rectier. 11 when the bandwidth is 26 MHz (902-928 MHz) and 83 MHz (2.4-2.483 GHz), respec- tively, corresponding to maximum available bandwidth in the popular Industrial, Scientic, Medical (ISM) bands. As can be observed from these graphs, for a higher load quality factor Q L , where Q L =! 0 R L C L and higher bandwidth, the quality of the impedance matching over the desired bandwidth deteriorates. As mentioned previously, the impedance matching circuitry has two function- ality: providing optimum power transfer and voltage boosting. Now, we want to nd an upper bound on the the maximum achievable voltage gain. Assuming free space Line-of-Sight (LOS) propagation conditions, the received power P r collected by the power harvester antenna can be written as [73] P r =G r G t P t ( 4r ) 2 ; (2.4) where G t and G r are the transmitter and power harvester antenna gains, respec- tively, is the electromagnetic wavelength in the medium, P t is the transmitted power, and r is the distance between the power harvester and the transmitter. Based on the maximum power transfer theorem, half of the collected power is available for delivery to a load, thusP av = 1 2 P r . The power delivered to the parallel RC load (rectier) is P in = V 2 in 2R L ; (2.5) 12 whereV in is the amplitude of the RF voltage across the load (input of the rectier), as shown in Fig. 2.2 (a). Assuming a lossless matching circuitry, P in = (1 j(!)j 2 )P av , wherej(!)j is the magnitude of the re ection coecient from the antenna terminal. Considering Eq. 2.4-2.5, the voltage amplitude at the input of the rectier is V in = 4r p (1j(!)j 2 )G r G t P t R L : (2.6) From Eq. 2.3, an upper bound for the input amplitude is V in 4r p G r G t P t q (1e 1 fR L C L )R L : (2.7) Furthermore, we know thatP av = V 2 s 8Rs ; therefore, an upper bound for the achievable voltage gain using the lossless matching circuitry equals V in V s 1 2 r (1e 1 fR L C L ) R L R s : (2.8) To achieve the maximum voltage gain, the parallel load has to be matched to the source impedance (smaller ). Fig. 2.4 depicts the maximum achievable voltage gain (V in =V s ) for dierent load impedances, when the bandwidth is 26 MHz (902- 928 MHz) and 83 MHz (2.4-2.483 GHz), respectively. In these plots, the source impedance (R s ) is assumed to be 50 . As can be observed from these graphs, larger resistance R L and smaller capacitance C L increase the voltage gain. It will be shown in a later section that fortunately, the same condition leads to more 13 Figure 2.4: Maximum achievable voltage gain (V in =V s ) for dierent load impedances when the bandwidth is (a) 26 MHz, and (b) 83 MHz. ecient rectier implementations as well. We can also see that as the required bandwidth increases, it gets harder to get a large voltage gain. 2.1.2 Impedance Transformation Loss The impedance transformation ratio Q matching is given by [73] Q matching = r R L R s 1: (2.9) Generally, the loss of the passive impedance transformation network, P loss;m , is proportional directly to the transformation ratio and inversely to the eective qual- ity factor of the matching circuitry components (P loss;m / Q matching Q eff ). Specically, it can be shown that the eciency of the widely-used L-matching circuitry is matching = Q ind Q ind +Q matching ; (2.10) 14 Figure 2.5: Eect of the inductor quality factor on the matching circuitry (a) eciency, and (b) voltage gain for dierent values of parallel load resistance, using the L-matching circuitry. whereQ ind is the quality factor of the inductor (neglecting the loss in the capacitor) [28]. HigherQ matching reduces the eciency of the matching circuitry. The rectier input power is P in = (1j(!)j 2 )P av P loss;m , which equals P in = matching (1j(!)j 2 )P av : (2.11) Given the L-matching circuitry can achieve the maximum eciency that is possible with component Q [91] and assuming a low-loss matching circuitry (so Eq. 2.3 is still valid), an upper bound for the achievable voltage gain can be derived as V in V s 1 2 r (1e 1 fR L C L ) R L R s s Q ind Q ind +Q matching : (2.12) The eect of Q ind on the matching circuitry eciency and voltage gain are shown in Fig. 2.5 (a) and (b), respectively. 15 Figure 2.6: The inductor values and the achieved bandwidth at 915 MHz in the matching circuitry versus parallel load resistance for (a) 1-section L-matching cir- cuitry, and (b) 2-section L-matching circuitry. 2.1.3 Realizability of Components Another limitation for the impedance transformation is the realizability of the re- quired passive components. For example, the required inductance to achieve match- ing at 915 MHz for dierent load resistances are shown in Fig. 2.6, for 1-section and 2-section matching circuitry (R s = 50 ). In the 2-section matching circuitry, the minimum L 1 +L 2 satisfying the bandwidth requirement is used. For higher load resistances, Q matching increases leading to very large inductance values, mak- ing its compact realization a major challenge at the GHz range. As a point of reference, the maximum commercially available inductor value with a Self Reso- nant Frequency (SRF) above 5 GHz is 24 nH [20]. Reducing the inductor value, in a given impedance transformation topology, leads to lower voltage gain, making power harvesting more dicult and less ecient at low input signal levels. Also, by using 1-section L-matching network the bandwidth requirement may not be sat- ised for large load resistance (Fig. 2.6 (a)), requiring a higher order matching 16 Figure 2.7: Eect of the mismatch in inductor value on the voltage gain in the L-matching circuitry. network, such as the 2-section L-matching network (Fig. 2.6 (b)) which has lower eciency. Fig. 2.7 shows the voltage gain for dierent load resistances versus the mismatch in the required inductance for the matching using L-matching circuitry. 2.2 Rectier Circuitry The rectier in the power harvester converts the RF signal to a DC signal. The schematic of two common rectiers are shown in Fig. 2.8. In order to get higher DC voltage for a given input, multiple stages of the unit cell are cascaded. For example, the voltage multiplier (Fig. 2.8 (a)) is the cascade of several voltage doubler circuitries [42]-[18] and the self-driven synchronous rectier (Fig. 2.8 (b)) is the cascade of the four-transistor cell [57][67]. Previously published papers have shown analysis for various rectiers [100][17][105][5]. In the following sections, a brief summary of the rectier performance is covered where simple piecewise linear 17 Figure 2.8: The schematic of two common rectiers: (a) N -stage voltage multiplier, and (b) self-driven synchronous rectier. Figure 2.9: (a) Schematic of the voltage doubler, and (b) its transient voltage waveforms using ideal diode. model is assumed for the active devices to highlight the main sources of the eciency degradation. 2.2.1 Voltage Doubler In this section, the operation principle of voltage doubler which acts like a charge pump circuit (Fig. 2.9) is shown. Let us assume the input signal is a pure sinu- soidal voltageV in cos!t. Assume ideal lossless diodes with turn-on voltageV ON . In the negative cycles of the input signal, the capacitor C 1 is charged to V in V ON . 18 Therefore, the charge stored onC 1 isQ 1 =C 1 (V in V ON ). During the positive cycle of the input, a part of this charge is transferred to the capacitorC 2 . Therefore, the voltage across C 2 at the i th cycle, V out;i , is: V out;1 = 2C 1 (C 1 +C 2 ) (V in V ON ); (2.13) V out;2 = 2C 1 (C 1 +C 2 ) (V in V ON ) + 2C 1 C 2 (C 1 +C 2 ) 2 (V in V ON ); (2.14) V out;3 = 2C 1 (C 1 +C 2 ) (V in V ON ) + 2C 1 C 2 (C 1 +C 2 ) 2 (V in V ON ) + 2C 1 C 2 2 (C 1 +C 2 ) 3 (V in V ON ); . . . (2.15) V out;n = 2C 1 (C 1 +C 2 ) (V in V ON ) + 2C 1 C 2 (C 1 +C 2 ) 2 (V in V ON ) + 2C 1 C 2 2 (C 1 +C 2 ) 3 (V in V ON ) + + 2C 1 C n1 2 (C 1 +C 2 ) n1 (V in V ON ): (2.16) So, V out;n can be written as V out;n = 2C 1 (C 1 +C 2 ) (V in V ON )[1 + C 2 (C 1 +C 2 ) + ( C 2 C 1 +C 2 ) 2 + + ( C 2 C 1 +C 2 ) n1 ]: (2.17) As the number of sinusoidal cycles goes to innity, the output voltage asymp- totically reaches a steady-state voltage given by lim n!+1 V out;n = 2C 1 (C 1 +C 2 ) (V in V ON ) 1 1 C 2 C 1 +C 2 = 2(V in V ON ): (2.18) 19 Simulated transient waveforms of the mid-point and output voltage of a single- stage voltage doubler are plotted in Fig. 2.9 (b). Likewise, it can be shown that the output voltage of the N-stage rectier of Fig. 2.8 (a) is 2N(V in V ON ). An important point in the power harvester analysis is that although the power levels are in the range of Ws, the input impedance can be large, resulting in a large voltage swing across the devices. Therefore, the large-signal model for devices should be considered. The large-signal models for a PN junction diode and an NMOS transistor are shown in Fig. 2.10 (a) and (b), respectively. Based on these models and assuming the capacitances in the rectiers are ideal and therefore they do not dissipate power, the sources of the power loss in the devices are mainly due to the I-V dissipation of the device due to overlapping voltage and current wave- forms; the parasitic loss, including substrate loss, gate resistance loss, etc. The main source of power loss is the nonideal I-V characteristic of the active devices. The main assumption for the analysis is that the circuit has reached its steady-state point, so the DC voltage at the output has been built up to V out with an equivalent load resistance of R L . At DC, capacitances C 1 and C 2 are open 20 Figure 2.10: The large-signal model for (a) a PN diode, and (b) an NMOS transis- tor. Figure 2.11: (a) Piecewise linear I-V curve, and (b) the voltage/current waveform of each diode. 21 (Fig. 2.9 (a)), so DC voltage across each diode is Vout 2 (assuming identical diodes). Therefore, output DC current equals DC current of each diode as I out = 1 T Z T I D (t)dt; (2.19) where I D (t) is the current of each diode. Assuming the capacitances C 1 and C 2 are large enough to consider them short circuits at RF frequency and the input signal is V in cos!t, the voltage across each diode is V D (t) =V in cos!t Vout 2 : To simplify the analysis, let us assume a piecewise linear I-V model for the diode (Fig. 2.11 (a)), where G m is the slope of the I-V curve and V ON is the turn-on voltage of the diode. Considering Eq. 2.19, I out can be derived by taking the DC Fourier coecient of the current waveform shown in Fig. 2.11 (b) as I out = G m [V in sin( V out 2 +V ON )]; (2.20) where 2 is the conduction angle of the diodes. For a given V out and R L (V out = R L I out ), the conduction angle and the required input voltage amplitude V in can be calculated by solving the following two equations simultaneously: V out = R L G m [V in sin( V out 2 +V ON )]; V in cos V out 2 =V ON : (2.21) 22 The total input power is the summation of the power dissipated in the two diodes and also the output DC power, P out : P in = 2 T Z T I D (t)V D (t)dt +P out = G m V in 2 [ sin 2 2 ]: (2.22) Dening the power eciency of the voltage doubler as the ratio of the DC output power to the given input power at the main tone, the power eciency can be derived as: = V out V in sin cos sin 2 2 : (2.23) The calculated conduction angle and power eciency versus the device slopeG m and V ON for the voltage doubler are shown in Fig. 2.12 (a) and (b), respectively. The calculated results conrms well with the simulation results where the same diode model is used. As can be seen from these graphs, smaller V ON and larger slope G m improves the rectier eciency. In the ideal case, where the turn-on voltage is 0 and the slope is innity (no loss), = 0 and equals 100%. In that case, the device current and voltage waveforms are completely non-overlapping. The diode can be implemented using P-N or Schottky diodes. Since Schottky diodes have larger saturation current and therefore smaller threshold voltage, they can be a good candidate to be used in the voltage doublers. The IBM CMOS8RF technology oers a scalable Schottky Barrier Diode (SBD). It uses CoSi 2 as the 23 Figure 2.12: The calculated (a) conduction angle , and (b) power eciency versus the device slope G m and V ON for the voltage doubler. anode on n- silicon served as the cathode. Also, MOSFET transistors with con- nected drain-gate terminals can be used instead of the diode in a CMOS technology. Compared with the SBD, this 'diode-connected' MOSFET oers a less steep I-V response, but, a lower turn-on voltage due to the lower threshold voltage of scaled MOSFETs compared with that of diodes in the same technology (Fig. 2.13). Fig. 2.14 (a) and (b) shows the simulated eciency of the voltage doubler versus the diode and transistor width in a 0.13m CMOS technology for V out = 0:375 V and V out = 0:75 V, respectively. As predicted by the simple model, larger transistor size, corresponding to steeper I-V, increases the eciency. We can also see that using low voltage transistors which have smaller threshold voltage increases the eciency. Another way to reduce the threshold voltage and therefore improving the e- ciency of the rectier is shown in [49], where diode-connected transistors have been replaced with a transistor where their gate is controlled by a comparator (Fig. 2.15 (b)). Therefore, the transistor acts as a switch where there is a smaller voltage drop across the device, resulting in higher eciency. However, they are working at 24 Figure 2.13: (a) Simulated I-V curve for the diode-connected regular transistors, and low voltage transistors (W=L = 5m=120nm), and the Schottky Barrier Diode (anode length=2m and width=5m), and (b) the zoomed view of the I-V curve. Figure 2.14: Simulated eciency of the voltage doubler versus transistor size for (a) V out = 0:375 V, and (b) V out = 0:75 V, while R load = 250 k for the voltage doubler. 25 Figure 2.15: Schematic of the voltage doubler employing (a) diode-connected tran- sistors, and (b) transistors with comparators to reduce voltage drop. Figure 2.16: The eciency degradation due to (a) the substrate loss, and (b) the gate resistance loss for the voltage doubler while V out = 0:375 V, R load = 250 k , and W = 5m. low frequency (13.56 MHz). The main challenge with this method at RF frequency is designing extremely low power and high speed comparators. There are other sources of loss in the device mainly due to the substrate re- sistance, gate resistance, etc. which are frequency dependent. The eect of the substrate loss is simulated for one-stage voltage doubler in 0:13m CMOS tech- nology (Fig. 2.16 (a)). For this simulation, once the BSIM4 substrate model is disabled and enabled in the device model. Based on the model shown in Fig. 2.10, as frequency increases the bulk capacitance C B impedance gets smaller, allowing 26 more current goes into substrate and thus larger power is dissipated in the sub- strate. As can be seen from this graphs, this loss can substantially degrade the eciency as the frequency increases. The other parasitic loss is due to the gate resistance dissipation. Fig. 2.16 (b) shows the eciency of voltage doubler versus frequency. In this simulation, the number of ngers is changed in the transistors, compared with the case when the gate resistance is set to zero. As can be seen from these graphs, by using fewer number of ngers which translates to larger gate resistance, the eciency can degrades as frequency increases. In order to boost the DC voltage generated by the power harvester, cascade of N stages of voltage doubler are used. Thus, the required input voltage will decrease. As number of stages increases, more active devices are used in the rectier; therefore, the power dissipation increases, reducing the rectier eciency. The input resistance of the rectier can be derived as R in = V 2 in 2P in : (2.24) where the rectier input power, P in can be written as sum of the rectier loss and the delivered output power as P in = P out +P loss;r . So, R in can be represented by two parallel resistances, R in;loss , due to the loss in the rectier, and R in;out , due to the delivered output power. R in decreases with larger P loss;r or larger P out . In the multi-stage rectiers, the input capacitance C in can be represented as the parallel 27 Figure 2.17: (a) The input resistance R in and the required inductance value for matching, and (b) the matching circuitry and rectier eciency versus number of stages. combination of the capacitance of each stage in the rectier. So larger number of stages reduces R in while increases C in . Fig. 2.17 (a) shows the input resistance R in and the required inductance value (L) for the matching circuitry versus number of stages (assuming LC matching circuitry). Fig. 2.17 (b) shows the simulated eciency of both matching circuitry and rectier versus number of stages N at 0.9 GHz, assuming the Q L = 20 and R ant = 50 . As shown in this graph, larger N decreases rectier eciency while increases matching circuitry eciency. So, in practice, the number of stages should be dened not only by the rectier eciency, but also by considering that how much reactive impedance can be provided from the outside or the antenna design. 2.2.2 Full-Bridge Rectier A full-bridge rectier another type of the rectier circuits to convert the AC signal into a DC voltage. A typical implementation of the full-bridge rectier circuit is 28 Figure 2.18: (a) Schematic of the full bridge rectier, and (b) the voltage/current waveforms. shown in Fig. 2.18 (a). Let us assume V 1 and V 2 are large enough to turn on-o the diodes. When V 1 is high and V 2 is low, diodes D 1 and D 3 are on and D 2 and D 4 are o. So, the current ows into V out through D 1 and D 3 . During the other half cycle, D 2 andD 4 are on andD 1 andD 3 are o, but the current will ow with the same direction as before; thus, the current is rectied and the DC voltage V out is built up across the load. Assuming V ON is the drop voltage across each diode, the DC output voltage can be easily written as (V in 2V ON ). Since the capacitance does not pass DC current, the delivered DC current to the load is the addition of the DC current of the two diodes, D 3 and D 4 which equals I out = 1 T Z T 2I D (t)dt; (2.25) where I D is the current of each diode, depicted in Fig. 2.18 (b). If the output DC voltage is V out , the voltage drop across the each diode is Vout 2 (assuming identical 29 I-V for the diodes). Therefore, if the input dierential signal is V in cos!t; then V 1 and V 2 equals 1 2 (V in cos!tV out ) and 1 2 (V in cos!tV out ), respectively. Again, likewise the voltage doubler analysis, the same piecewise linear I-V model for the diode is assumed (Fig. 2.11 (a)). Considering Eq. 2.25, I out can be derived by taking the DC Fourier coecient of the current waveform shown in Fig. 2.18 (b) as I out = G m [V in sin(V out + 2V ON )]; (2.26) where 2 is the conduction angle of the diodes. For a given V out and R L (V out = R L I out ), the conduction angle and the required input voltage amplitude V in can be calculated by solving the following two equations simultaneously: V out = R L G m [V in sin(V out + 2V ON )]; V in cosV out = 2V ON : (2.27) The total input power is the summation of the power dissipated in the four diodes and also the output DC power, P out : P in = 4 T Z T I D (t)V D (t)dt +P out = G m V in 2 2 [ sin 2 2 ]: (2.28) 30 Thus, the power eciency can be derived as: = 2V out V in sin cos sin 2 2 : (2.29) The calculated conduction angle and power eciency versus the device slopeG m andV ON for the full-bridge rectier are shown in Fig. 2.19 (a) and (b), respectively. The calculated results conrms well with the simulation results where the same diode model is used. Theses results are close to the results obtained for the voltage doubler. Both schemes can achieve almost the same performance for the same device. Fig. 2.20 (a) and (b) shows the simulated eciency of the bridge rectier versus the diode and transistor width in a 0.13m CMOS technology for V out = 0:375 V and V out = 0:75 V, respectively. As predicted by the simple model, larger transistor size, corresponding to steeper I-V, increases the eciency. Also, we can see that the performance of the bridge rectier is similar to the performance of the voltage doubler, as predicted by the piecewise linear model. Fig. 2.21 shows the eect of the substrate loss and gate resistance loss on the eciency of the bridge rectier; likewise the voltage doubler, both of these loss mechanism degrade the eciency at higher frequency signicantly. 2.2.3 Four Transistor Cell Now, let us consider the four transistor cell shown in Fig. 2.22 (a). Its operation principle is very similar to the bridge rectier; when V 1 is high and V 2 is low, 31 Figure 2.19: The calculated (a) conduction angle , and (b) power eciency versus the device slope G m and V ON for the full-bridge rectier. Figure 2.20: Simulated eciency of the bridge rectier versus transistor size for (a) V out = 0:375 V, and (b) V out = 0:75 V, while R load = 250 k . Figure 2.21: The eciency degradation due to (a) the substrate loss, and (b) the gate resistance loss for the bridge rectier while V out = 0:375 V, R load = 250 k , and W = 5m. 32 Figure 2.22: (a) Self-driven synchronous rectier (four transistor cell), (b) and the voltage/current waveforms across a transistor. transistors M 1 and M 3 are on and M 2 and M 4 are o. So, the current ows into V out through M 1 and M 3 . During the other half cycle, M 2 and M 4 are on and M 1 andM 3 are o, but the current will ow with the same direction as before; thus, the current is rectied and the DC voltage V out is built up across the load. Assuming the V ON is the drop voltage across each transistor, the DC output voltage can be easily written as (V in 2V ON ). The delivered DC current to the load is the addition of the DC current of the two transistors M 3 and M 4 , which equals I out = 1 T Z T 2I tran (t)dt; (2.30) whereI tran (t) is the current of each transistor, depicted in Fig. 2.22 (b). Unlike the bridge rectier, during one cycle, at some points, the drain and source terminals interchange and the current direction changes. Thus, the main trade-os for these rectier topologies are the on-resistance and reverse conduction current, which 33 Figure 2.23: (a) Forward and reverse conduction loss, and (b) eciency versus device size V out = 0:375 V for the four transistor cell. limit the eciency of the rectier. Since the transistor can enter dierent operation regions, it can not be simplied with a piecewise linear model, making its analysis dicult. So, the design trade-os are shown through simulation. As the size of the transistors increase, the forward loss decreases; however, the reverse loss increases. Fig. 2.23 (a) shows how the forward and the reverse loss are aected by changing the transistor size, along with the power eciency shown in Fig. 2.23 (b). Fig. 2.24 (a) and (b) shows the simulated eciency of the the four transistor cell versus the transistor width for V out = 0:375 V and V out = 0:75 V, respectively. We can see there exists an optimum device size for a given output voltage. Also, since the devices are acting as the switch with smaller drop voltage compared to a diode or diode-connected transistor, this scheme can potentially achieve higher eciency. In [6] comparators have been used to reduce the reverse conduction and improves the eciency (Fig. 2.25); therefore, the transistors will act as a unidirectional switches; however, they are working at low frequency (13.56 MHz). Again, the 34 Figure 2.24: Simulated eciency of the self-driven synchronous rectier versus transistor size for (a) V out = 0:375 V, and (b) V out = 0:75 V, while R load = 250 k . Figure 2.25: Schematic of the four-transistor cell employing comparators to reduce reverse conduction. main challenge with this method at RF frequency is designing extremely low power and high speed comparators. Fig. 2.26 (a) and (b) shows the eciency degradation versus frequency due to the substrate, and the gate resistance in the four transistor cell, respectively. In the voltage doubler and bridge rectier, the eciency always increases with larger device slope and smaller threshold voltage, translating to have a larger device size which increases the device parasitics. On the other hand, in the four-transistor cell, depending on the output voltage, the eciency can increases/decrease with device 35 Figure 2.26: The eciency degradation due to (a) the substrate loss, and (b) the gate resistance loss in the four transistor cell whileV out = 0:375 V,R load = 250k , and W = 5m. Figure 2.27: The simulated (a) I-V curve for a regular transistor with minimum channel length and W = 5m width, and (b) eciency of the voltage doubler versus transistor width forV out = 0:75 V andR load = 250k in 65 nm and 130 nm technology. slope and threshold voltage, due to the reverse loss. This means considering the I-V dissipation, we do not need to use larger devices. So, potentially, the device parasitics can be reduced. Also, in the voltage doubler and bridge rectier, as V out increases, eciency also improves. However, there is the opposites trend for the four-transistor cell, since the reverse loss increases. 36 Figure 2.28: Simulated eciency of the voltage doubler versus frequency forV out = 0:75 V and R load = 250 k for in 65 nm and 13 0nm technology. 2.2.4 Technology Scaling In this part, the eect of the technology scaling on the rectier performance is shown. For these simulations, the voltage doubler is considered. Fig. 2.27 (a) shows the the simulated I-V curve for a regular transistor with minimum channel length and W = 5 m width in 65 nm and 130 nm CMOS technology. It shows that the turn-on voltage of the transistor is larger in 65nm, so the eciency should be smaller in 65nm as depicted in Fig. 2.27 (b). However, as frequency increases, since smaller technology node has smaller parasitic capacitance, it can outperform the rectier performance in the higher technology node, as simulated and shown in Fig. 2.28. The performance of the recently published integrated rectiers have been sum- marized in Table 2.1. 37 Table 2.1: Performance summary of the published rectiers Ref. Frequency (GHz) Process V DD @R L Min. P in (dBm) Eciency @ Min. P in Topology [68] 0.915 90nm CMOS 1.2 V @ 1 M -18.83 11% Multi-stage voltage doubler [42] 0.896 0.5m CMOS 1.5 V @ 1.5 M -20.1 14.5% Multi-stage voltage doubler by Schottky diode [44] 0.45 0.25 m CMOS 1.2 V @ 1 M -18.6 10.4% Multi-stage voltage doubler by low-V th transistors [57] 0.95 0.18m CMOS 0.5 V @ 125 k -20.1 23.5% Multi-stage synchronous rectier [86] 0.868 0.13m CMOS 2 V -21 10% Multi-stage synchronous rectier [97] 0.915 0.25m SOS 1 V @ 1 M -24.6 29% Multi-stage bridge rectier by zero-V th transistors [47] 0.9 0.25m CMOS 1 V @ 1.8 M -22.6 10% Multi-stage voltage doubler [54] 2.4 0.18m CMOS 0.5 V @ 2 k -2 20% Multi-stage synchronous rectier [74] 2.45 0.18m CMOS 1.8 V @ 5.45 M -16.2 2.4% Multi-stage synchronous rectier [74] 5.8 0.18m CMOS 1.8 V @ 5.45 M -14.22 1.5% Multi-stage synchronous rectier 2.3 Upper Bound on Power Harvester Performance Now, let us nd the bounds on the performance of the power harvester. From Eq. 2.11 the generated DC output power by the rectier can be expressed in terms of available power (incident power to the antenna) as P out = rectifier matching (1j(!)j 2 )P av ; (2.31) where a lower bound forj(!)j and upper bound for matching can be found using Eq. 2.3 and Eq. 2.10, respectively. Let us deneV in;th as the minimum required input RF amplitude for the rectier to provide V out to the load R out . The minimum power-up threshold P av;th and the 38 Figure 2.29: The power up thresholdP av;th for the bandwidth (a) 0, (b) 26 MHz, and (c) 83 MHz as the function of V in;th and C in , assuming Q ind = 40, rectifier = 50%, R s = 50 , and P out = 2 W . Figure 2.30: The total system eciency for the bandwidth (a) 0, (b) 26 MHz, and (c) 83 MHz as the function of V in;th and C in , assuming Q ind = 40, rectifier = 50%, R s = 50 , and P out = 2 W . 39 total eciency of the power harvester as a function of the V in;th and C in , can be found from Eq. 2.3, 2.10, and 2.31. As an example, Fig. 2.29 and 2.30 shows the lower bound for power-up threshold and upper bound for the system eciency, respectively, as a function of V in;th andC in for three dierent bandwidths (BW=0, 26 MHz, and 83 MHz) and 2W output power. For these graphs, rectier eciency andQ ind are assumed to be 50% and 40, respectively, which are high values at the RF frequency for the known rectiers. So, these graphs can be represented as the performance bounds of the power harvester (for a specic P out , BW). Also, the input capacitance is always higher due to capacitance of the pad and ESD protection circuitry that collectively can be as high as 0.5 pF. For these graphs, it is assumed that all passive components are realizable. However, as mentioned before some required inductance may not be achievable at the RF frequency; therefore, the minimum required P av;th increases due to mismatch (increase injj). As intuitively expected, we can see from these graphs that as bandwidth in- creases the input capacitance degrades the performance drastically. Also, lower V in;th improves the performance of the power harvester signicantly. Unfortunately, in order to decrease V in;th to improves the power harvester performance by using the known topologies for the rectier, either the number of stages or the device sizes must increase, leading to increasing the capacitance and thus degrading the power harvester performance. Therefore, there is a trade o between the V in;th and 40 C in . The performance of the power harvester is improved by reducing V in;th while keeping C in as small as possible. 2.4 Passive Transponder with Dynamic Energy Storage and Sensitivity Enhancement As shown in the previous section, there are both fundamental and practical con- straints on the RF power scavenging circuitry that limits the sensitivity and oper- ation range of the passive systems. In this section, a new architecture is proposed for the power harvester to improve their sensitivity. In the existing systems, the passive system functions the same irrespective of the received input power as long as it exceeds its sensitivity level [40][89][79][3][74][42] [18][57]. However, sometimes the system can receive larger power beyond its sensi- tivity level from the intended source of RF power (e.g. reader in an RFID system) or receive the power from ambient wireless signals which may not need it at the moment of receiving. The source of this ambient RF power source may be a closely transmitting cellular phone, a high-power broadcasting station, etc. In the existing passive systems, this extra received power is simply ignored. However, this extra power can be harvested, stored and later exploited to improve the sensitivity of the passive system when the power level is low. There is a trade-o between the stored energy and required storage time as a function of capacitor value. In a proposed 41 'dynamic energy storage' approach, the storage capacitor for the extra available power and the capacitor in the main energy harvester path are separated. In this section, rst the concept and implementation of the dynamic energy storage mechanism is presented and then its utilization to enhance the sensitivity of a passive system is discussed. 2.4.1 Dynamic Energy Storage Mechanism In order to have dierent functionalities at dierent input power levels, we need to discriminate between dierent power levels. Since there is no battery in the passive system, the power discriminator must be passive. One method to implement this idea is to have parallel paths with dierent storage elements in which the corresponding energy harvester of each path is activated at dierent power level, as depicted in Fig. 2.31 (a) for a 3-level power discriminator. For example, atP in1 , the rst path starts storing energy; while at P in2 the second path starts storing energy, and atP in3 the third path starts storing energy. In order to implement this scheme, one can place switches in series with each power harvester. The switches are controlled by the stored voltage on the previous path, shown in Fig. 2.31 (b). For example if P in is larger than P in1 , the rst path starts storing energy. If P in is larger than P in2 , V DD1 exceeds a certain threshold voltage (V T 1 ) and therefore it can close switch S 1 and enable the second energy-storage path. If P in is larger than P in3 , then both V DD1 and V DD2 exceeds certain threshold voltages (V T 1 and 42 Figure 2.31: Dynamic energy storage mechanism: (a) concept, and (b) implemen- tation. V T 2 ); thus, they close switches S 2 and enable the third energy-storage path. The reason for having two switches for the third energy storage path is that since C 2 can be much larger than C 1 , it can have previously stored charge on it resulting in a large-enough voltage to turn on its corresponding switch in the third path, while P in may not be large enough at the time to enable additional energy extraction through the third path. Therefore, the rst path which has the highest priority should only be active at the time. One feature of this scheme is that it can tolerate larger input power, thus en- hancing the power range of the system. As an example, Fig. 2.32 shows the eect of the number of storage paths onV DD1 . Assuming the maximum voltage that can 43 Figure 2.32: The extension of the power range of the power harvester with dynamic energy storage. be tolerated by the circuitry is 3 V, power harvester with one storage path reaches there at P in =7 dBm, while power harvester with two and three storage paths get there at P in =4:5 dBm and P in = 0 dBm, respectively. So, the system with two and three storage paths can tolerate 3.5 dB and 7 dB larger input power, re- spectively compared to the system without extra energy storage path. Therefore, rather than wasting the extra energy in the protection circuitry or voltage limiter, the extra energy is stored in separate storage elements, while the performance of the system does not degrade at low input power (V DD1 does not change) with the addition of extra energy storage paths. Also, as the extra path becomes active, the input impedance of the system changes. If the rectiers in all paths are the same and if M paths are on, then R in reduces by a factor M, while C in increases by a factor M, creating impedance mismatch which acts a protection circuitry at larger input power. So, it further extends the upper voltage limits of the power harvester. 44 Figure 2.33: Conceptual block diagram of the proposed sensor with dynamic energy storing and sensitivity enhancement. 2.4.2 System Block Diagram The block diagram of the proposed scheme for the passive sensor is shown in Fig. 2.33. Normally, the system does not function for an input power below the sen- sitivity level P th . With the addition of the energy storage mechanism, the stored energy across C L can be used to enable operation at input power levels below the original sensitivity P th . A threshold detector circuitry generates a Wake-Up Signal (WUS) prompting the sensor to use the stored energy only when the input power is less thanP th . Whenever there is no input signal or the input power is larger than P th , the stored energy will not be used. The threshold detector circuitry exploits the stored energy onC L as the energy source and voltage onC S as the input power indicator. The system has dierent operation modes. In the passive mode, shown in Fig. 2.34 (a), P in equals or larger than P th , and the sensor can work by extracting the required DC energy from the received RF signal and storing it on capacitance C S . IfP in is large enough,V DD1 closes switchS 1 and activate the second energy-storage 45 Figure 2.34: The transponder (a) passive operation mode, (b) passive operation with energy saving mode, and (c) semi-passive (extended sensitivity) mode. path. Therefore, the extra energy is converted to DC and stores on capacitor C L . This mode is called energy saving mode (Fig. 2.34 (b)). If P in is smaller than P th , and if there is enough energy stored on the capacitor C L , the WUS is generated to connect the sensor to C L . The stored energy on C L enables operation at P in below P th , thus enhancing the sensitivity of the sensor in the semi-passive mode (Fig. 2.34 (c)). In order to put the foregoing discussions in use, the principle of dynamic energy storage and sensitivity enhancement is applied to the design of a wireless transpon- der that communicates with a reader. The detail block diagram of the transponder is shown in Fig. 2.35. One extra energy storage path is used in this prototype as a proof of concept. This path includes a rectier, a storage capacitance C L , and a pair of switchesS 1 enabling energy storage that is controlled byV DD1 , generated in 46 Figure 2.35: The detail block diagram of the wireless transponder prototype with dynamic energy storage and sensitivity enhancement. the top path. An extra switch is placed after the rectier in this path, controlled also by V DD1 . Due to the leakage current of the rectier, the stored energy on the capacitor C L can be dissipated. Therefore, by using this switch, the rectier is connected only during storing energy period. The switches are implemented using regular NMOS transistors with the size of W=L = 15m=120 nm. Larger switches have less loss, but they add more parasitic capacitance. The threshold detector circuitry decides whether the input power is small enough to use the extra stored energy or large enough that it can extract its required energy from the received signal. It generates the Wake-Up Signal (WUS) if the input power is below P th . Otherwise the Passive Mode (PM ) signal will be activated, indicating that the in- put power is higher thanP th . The circuitry usesV DD1 as the input signal to decide 47 whetherP in is less/more thanP th . The main requirement of the threshold detector circuitry is to have zero static power consumption, since it usesV DD2 as the energy source. A successful communication session can be split into four parts (Fig. 2.36). In the power-up mode, the reader sends an un-modulated RF signal for a long period to provide enough energy for the system. The power-on-reset circuitry generates a short pulse at the beginning of the power-up mode to reset the D- ip- ops in the logic circuitry. In the addressing mode, the reader sends a Pulse- Width-Modulated (PWM ) address signal for a specic transponder. This address is demodulated by the envelope detector and PWM demodulator. In the respond- ing mode, the transponder whose address is called responds back by modulating its antenna impedance (backscattering modulation). The logic circuitry generates the Enable signal to activate the modulator. Other transponders whose addresses are not called remain silent. In this design, a 3-bit address is considered for the transponder. At the end of the communication, the logic control generates a control signal to discharge the capacitor C S , so that V DD1 that controls the storage path becomes zero. The Power-On-Reset (POR) circuitry generates a short pulse at the beginning of the power-up mode to reset the D- ip- ops in the logic circuitry. The logic circuitry generates the Enable signal when the transponders address is read to activate the modulator. 48 Figure 2.36: (a) The communication sequence used for the prototype transponder, the generated waveforms in (b) the semi-passive mode, and (c) the passive mode. 49 Figure 2.37: The schematic of the rectier in the main and storage paths. 2.4.3 Transponder Building Blocks In this section, the schematics of dierent blocks in the transponder are presented. The rst block is the rectier. Self-synchronous rectiers have been used as the rectier both in the main and storage path. As stated in the previous section, the four transistor cell can oer higher eciency compared to the voltage doubler at low input power level [57]-[67]. Since the transistors are implemented as switches in the four transistor cell, they are working in the triode region; so, there is lower voltage drop across them compared to the transistors in the voltage doubler where diode-connected transistors are used and therefore the transistors are working in saturation region. Bases on our simulations, 5-stage rectier oers relatively e- cient performance and also low input impedance that makes the matching circuitry more relaxed (Fig. 2.37). Low threshold PMOS and NMOS transistors with the size of W=L = 10 m=300 nm have been used in the rectier. An on-chip MIM capacitor is used as the primary storage capacitance (C S ) with the value of 47 pF. This capacitor should be large enough so that during the short interval of the 50 Figure 2.38: (a) The schematic of the threshold detector circuitry, and (b) the timing diagram of the circuitry. power shortage, V DD1 does not drop signicantly such that the transponder stops working. The rectier in the storage path is also realized by the 5 stages of the four transistor cell. Since low-threshold transistors have larger leakage current, regular PMOS transistors are used in the last stage of the rectier in the storage path. Low threshold transistors are used elsewhere. The next block in the transponder is the threshold detector circuitry shown in Fig. 2.38, which decides whether the input power is small enough to use the extra stored energy or large enough that it can ex- tract its required energy from the received signal. It generates the Wake-Up Signal (WUS) if the input power is below P th . Otherwise the Passive Mode (PM) signal will be activated, indicating that the input power is higher than P th (Fig. 2.38 (b)). The circuitry usesV DD1 as the input signal to decide whetherP in is less/more 51 Figure 2.39: The schematic of the envelope detector. than P th . The main requirement of the threshold detector circuitry is to have zero static power consumption, since it uses V DD2 as the energy source. The circuit has two branches, each with a Schmitt trigger circuitry. The top (bottom) branch has a large (small) threshold voltage to detect whether P in higher (lower) than P th . In order to detect the small P in (V DD1 ), an ultra low-power amplier with an 8.5 M resistor has also been used in the bottom branch before the Schmitt-trigger circuitry which is biased at the zero. The rst block in the data path is the envelope detector, depicted in Fig. 2.39. Since an ASK modulation scheme has been used, the circuitry consists of a passive rectier which is 2 stages of the four transistor cell with an RC load. Then, the circuit has two branches. In the passive mode, the output of the four transistor 52 Figure 2.40: The schematic of (a) PWM demodulator, (b) modulator, (c) POR circuitry, (d) V DD switches, and (e) logic control circuitry. cell is large enough to trigger the Schmitt-trigger circuitry (the bottom branch). However, in the semi-passive mode, the output of the four transistor cell is rst amplied enough by an ultra low power amplier to trigger the Schmitt-trigger, shown in the top branch. Since the data is coded as a Pulse-Width Modulated (PWM) signal, there is a PWM demodulator followed by the envelope detector, shown in Fig. 2.40 (a). The output of the envelope detector is integrated and then comparator decides whether the sent pulse is long or short, thus demodulates the signal. The envelope of the RF signal has the data and clock information for the transponder. The extracted clock by the PWM demodulator is utilized by the logic circuitry and also used as the 53 reset signal for the integrator. Therefore, no local oscillator is required and power consumption is reduced [42]. The integrator capacitor is approximately 800fF. If the transponder address is sent by the reader, the logic circuitry generates the Enable signal and activates the modulator, shown in Fig. 2.40 (b). It is a 1.7MHz relaxation oscillator [89], which is achieved by connecting an RC integrating circuit between the output and the input of an inverting comparator. The output is a continuous square wave whose frequency depends on the values of R and C, and the threshold voltage of the comparator. The modulator is the most power hungry block in this prototype transponder, which consumes about 0.8 W from 0.5 V. The Power-On-Reset (POR) circuitry which is shown in Fig. 2.40 (c), generates a short pulse to reset the D- ip- ops in the logic circuitry at the beginning of the power-up mode. As V DD increases, V x follows it till the transistors turn on, discharging the capacitor C and pulling down the drain node of transistor M 2n . The generated signal is then buered by two inverters. Series combination of PMOS and low-threshold NMOS transistors are used as V DD switches to minimize energy dissipation (Fig. 2.40 (d)). The schematic of the logic control circuitry for decoding the 3-bit ID address of the transponder (which is 111 in this case) is shown in Fig. 2.40 (e). As mentioned before, it generates the Enable signal when the reader calls the transponder. Also, at the end of communication, it generates the control signal End to discharge the capacitance C 1 . 54 Figure 2.41: Chip microphotograph of the fabricated transponder. 2.4.4 Measurement Results The wirelessly powered transponder is implemented in a 0.13m CMOS technology with 8 metal layers [82]. The total chip size, including the pads, is 0.9 mm x 0.8 mm (Fig. 2.41). Dierent blocks have been shown on the graph. An o-chip capacitor with the value of 1.2 F has been used for capacitor C 2 . As mentioned before, an on-chip MIM capacitor with the value of 47 pF is used for capacitor C 1 . The chip is wire-bonded to a duroid board and tested with a single-tone 50- source at 900 MHz, 2.4 GHz, and 5.8 GHz. A hybrid is used to convert the single-ended signal to a dierential signal. The set up for measuring charging and discharging of the capacitances C 1 and C 2 is shown in Fig. 2.42 (a), where a long pulsed sinusoidal signal at 2.4 GHz is applied to the system. The measured waveforms ofV DD1 andV DD2 during charging and discharging at forP in =-8 dBm and 0 dBm are shown in Fig. 2.42 (b) and (c), 55 Figure 2.42: (a) The measurement set-up for transient V DD1 and V DD2 , the mea- sured transient waveforms of V DD1 and V DD2 at 2.4 GHz during charging and dis- charging using a 1.2 F capacitor (C 2 ) for (b) Pin=-8 dBm, and (c) 0 dBm. respectively. Since C 2 is larger than C 1 , V DD2 takes longer time to fully charged. Also, as the input power increases, the charging time gets smaller. The measurement setup for measuring steady-stateV DD1 andV DD2 versus input power is shown in Fig. 2.43 (a). In the absence of matching, directional couplers have been used to measure the incident and re ected power in this measurement. The measured and simulated steady-state V DD1 and V DD2 versus input power at 900 MHz, 2.4 GHz, and 5.8 GHz are depicted Fig. 2.43 (b)-(d), respectively. Each point in these graphs is obtained as V DD1 and V DD2 reaches the steady state point for dierent input power level. The minimum required V DD1 for operation in the passive mode is approximately 0.4 V, determining the sensitivity of the system. As the input power increases, V DD1 increases, reducing the switch loss; thus V DD2 56 Figure 2.43: (a) The measurement set-up, the measured (solid) and simulated (dashed) steady-state V DD1 and V DD2 versus input power at (b) 900 MHz, (c) 2.4 GHz, and (d) 5.8 GHz. increases. We can see that at some point, the switch can be completely closed and V DD1 and V DD2 reaches almost the same value (since rectiers in both paths are similar). A complete communication sequence in the passive mode, including the power- up mode, addressing mode and responding mode with input power of -19.5 dBm is applied to the system at 0.9 GHz, shown in Fig. 2.44. As shown in the zoomed view of the waveforms, V DD1 is charged up to approximately to 0.4 V, the data can be recovered and the modulator is activated during the responding mode. At the end of communication, the logic control circuitry generates the End signal to discharge the capacitorC 1 , makingV DD1 zero. The system can work successfully in the passive mode when the input power is as low as -19.5 dBm at 0.9 GHz. Similar 57 Figure 2.44: (a) The measurement set-up for passive mode operation, the measured (b) input envelope, (c)V DD1 , (d) data signal, and (e) modulator output at 0.9GHz. measurements indicate that the sensitivity of the transponder in the passive mode at 2.4 GHz and 5.8 GHz is -15.4 dBm and -7.6 dBm, respectively. In order to test the functionality of the system in the semi-passive mode, rst a signal at the input power -29 dBm signal which is lower than P th (-19.5 dBm), is applied to the system (Fig. 2.45 (a)). With this power,V DD1 andV DD2 are charged up to approximately 0.1 V and 0 V, respectively. Therefore, the transponder can 58 Figure 2.45: Measured V DD1 and V DD2 when (a) P in =-29 dBm<P th =-19.5 dBm, and (b) input signal is a sequence ofP in =-16.5 dBm>P th =-19.5 dBm andP in =-29 dBm<P th =-19.5 dBm. not work. Now a complete communication sequence at P in of -16.5 dBm (> P th ) and -29 dBm (<P th ) has been applied consecutively to the transponder at 0.9 GHz. As shown in the Fig. 2.45 (b), during large and small input power receptions,V DD1 equals 0.65 V and 0.1 V, respectively; while V DD2 is charged up to 0.4 V. Now the system can work by storing the extra energy during the large input power and using it when the input signal is below P th . During large input power, PM signal is active (passive mode), whereas for the small input power, WUS signal is active (semi-passive mode), shown in Fig. 2.46 (a). The zoomed views of input envelope, data signal, and modulator output in both passive and semi-passive mode are shown in Fig. 2.46 (b) and (c), respectively. Similar measurements have been done at 2.4 GHz and 5.8 GHz. The measured original and enhanced sensitivity of the system in the passive mode and semi-passive mode for dierent frequencies is 59 Figure 2.46: The measured semi-passive mode operation at 0.9 GHz when P in is a sequence of -16.5 dBm and -29 dBm, (a) input envelope, and WUS/PM signal; zoomed views of input envelope, data signal, and modulator output in (b) passive, and (c) semi-passive modes. shown in Fig. 2.47. A scan be seen, the sensitivity of the transponder can increase by approximately 10 dB thanks to the energy storage mechanism. The system is also tested with an input passive impedance matching network. Fig. 2.48 (a) shows the matching circuitry, which includes an o-chip inductor with the inductance of 22 nH and maximum Q of 40. Fig. 2.48 (b) shows the measuredV DD1 andV DD2 as a function of the available power. Since the minimum required V DD1 for passive mode operation and semi-passive mode operation are 60 Figure 2.47: The measured original and enhanced sensitivity of the transponder. approximately 0.4 V and 0.1 V, the sensitivity of the system including matching circuitry in the passive and semi-passive mode are approximately -18.2 dBm and -27.5 dBm, respectively. At approximately -15 dBm the second path also starts storing energy. Fig. 2.48 (c) shows the measured S 11 versus the available power, before and after the matching circuitry (the 22 nH inductor). Power meters and directional couplers are used to measure both the re ected and available power. It shows that the best matching happens at -20 dBm which is close to the P th of the system. As input power increases, the input impedance reduces due to two eects. First, the transponder draws more current; so the input resistance of the rectier re- duces. Second, the second energy storage path turns on, which doubles the input capacitance and halves the input resistance. 61 Table 2.2: Performance summary and comparison with recently published work Ref. Power Consumption Process Sensitivity @ 0.9 GHz On-Chip Antenna Area (mm 2 ) [3] 1.5 A @ 2.7 V 0.18 m CMOS -18.5 dBm No 4.5 [74] 0.33A @ 1.8 V 0.18 m CMOS -19.41 dBm Yes 4.5 [89] 2 A @ 1 V 0.18 m CMOS -14 dBm Yes 0.8 This Work 1.9 A @ 0.4 V 0.13 m CMOS -18.2/-27.5 dBm No 0.72 The summary of the measured performance of the CMOS wirelessly powered transponder with dynamic energy storage and sensitivity enhancement and com- parison with representative reported passive transponders is presented in Table 2.2. As can be seen from this table, the sensitivity of the transponder can be improved signicantly as a result of the dynamic energy storage mechanism. The functionality of a complete wireless transponder is also veried experi- mentally. The wireless measurement setup is depicted in Fig. 2.49 (a). For the transponder, folded-dipole antenna used which is implemented on a duroid board. The CMOS chip is directly mounted on the same duroid board. The patch antenna with a matching stub is used as the TX and RX antenna. The received backscat- tered data at 2.4 GHz is shown in Fig. 2.49 (b). We can observe the backscattered data on top of a large directly coupled signal between the TX/RX antenna. 62 Figure 2.48: (a) The matching circuitry, the measured (b) V DD1 andV DD2 , and (c) S 11 before and after the matching versus available input power at 900 MHz. 2.5 Summary and Future Work This chapter focuses on the implementation issues of high eciency RF power har- vesters. First, the main constraints, both theoretical and practical ones, on the RF power harvesters have been analyzed. Then, a new scheme for the passive systems is presented, where the extra received power by the passive sensor is stored and later used to enhance the sensitivity of the sensor. The eectiveness of the proposed technique is veried through a passive transponder implemented in CMOS technol- ogy. Thanks to using dynamic storage, the sensitivity of the transponder has been enhanced by approximately 10 dB. Future research can be focused on improving 63 Figure 2.49: (a) The wireless measurement setup, and (b) the received backscat- tered data. the eciency of the power harvester, considering both the impedance transforma- tion circuitry and rectier, by reducing the V in;th , in addition to reducing C in;th at high frequency by new rectier topology as well as new devices. Ecient energy harvesting from existing electromagnetic sources in the environment (e.g.,broadcast signal) would be another interesting challenge for future research. 64 Chapter 3 Wirelessly Powered Passive Downconverter Using Memoryless Nonlinearity As mentioned in chapter 1, small size and cost for the passive sensors are important for widespread adoption of the technology. Size is usually dominated by the exter- nal components, especially the antenna in the wirelessly-powered passive systems. Therefore, there is a general interest in going to higher frequencies, because the size of the electronic circuitry and antenna will be reduced; also, it might further be possible to integrate the antenna on-chip. This would result in a self-contained, CMOS-only system. As shown in the previous chapter, power harvesting circuitries are key blocks in the wirelessly-powered passive systems. Their main requirement is to have high RF-to-DC power conversion eciency. However, as shown before, the eciency of the rectiers drops signicantly as frequency increases (Fig. 3.1 (a)). For example, a reported mm-wave power harvesting system shows the RF- to-DC conversion eciency of around 1.2% for the rectier at 45 GHz, including 65 Figure 3.1: (a) Conventional wireless power harvester along with a representative simulated eciency, and (b) an alternative high frequency power harvester. the losses of the on-chip matching network [69]. Another possible solution for high- frequency power harvesting which may result in a more ecient system is to have an ecient battery-less frequency downconversion scheme followed with an ecient low-frequency rectier (Fig. 3.1 (b)). The main challenge in this scheme is to have an ecient battery-less or passive frequency downconverter. Frequency downconverter and divider transfers the energy from a high frequency source to a lower frequency, either synchronously or asynchronously. Depending whether they are using DC power or not, they can be divided into active or passive ones (Fig. 3.2 (a)). Popular active frequency dividers are injection-locked frequency divider (analog) and counter-based frequency divider (digital). The main known technique for a passive frequency division is the parametric frequency downconver- sion and division, in which a subharmonic frequency is generated by exciting a non- linear circuitry with memory or reactance, usually a varactor (Fig. 3.2 (b)). There have been several designs on parametric frequency dividers implemented on Printed 66 Figure 3.2: (a) Generic frequency downconverter and divider, and (b) parametric frequency divider using a varactor. Circuit Board (PCB) using discrete components [33][36][64][41][34][92][90][96] and a few recent integrated RF parametric frequency dividers and downconverters in a CMOS technology [107][52][56]. In this chapter, a new method for passive subharmonic generation, utilizing a memoryless nonlinear core coupled to a linear passive resonator, is proposed in which the energy of a radio frequency source transfers to a lower frequency without consuming DC power. This lower frequency can be synchronized to the frequency of the input source, enabling realization of a passive frequency divider. Then, the derivation of the frequency downconverter properties using nonlinear analysis which is applied to an LC -tuned cross-coupled topology is presented. Two design examples, a low-frequency discrete downconverter and an integrated 130nm CMOS 12 GHz passive divide-by-two circuitry will be shown [83][84]. 67 Figure 3.3: (a) Self-sustained oscillator, and (b) the proposed passive subharmonic generator using memoryless nonlinear circuitry. 3.1 Concept and Implementation Memoryless nonlinear circuits combined with linear passives can be congured to generate frequencies that are dierent than the input frequency without the need for a DC power supply or consuming DC power. Let us consider the circuit shown in Fig. 3.3 (a) where a DC supply voltage,V DD , biases the transistors by supplying a DC current through them. With a large enough DC current, the small-signal conductance looking into the cross-coupled transistors, G, becomes more negative than the LC resonator loss, i.e., G + 1 R L < 0. This causes an oscillation start-up, and ultimately, a steady-state sinusoid at the frequency of the LC resonator is sustained due to the nonlinearity of active devices. 68 Figure 3.4: Input/output voltage waveforms when (a) ! in = 2! out , and (b) ! in = 10! out . Now, consider the circuit in Fig. 3.3 (b) where the DC voltage supply is re- placed with an AC sinusoidal voltage source at frequency ! in . We will show that, under the right conditions, this circuit can generate a steady-state sinusoidal out- put at frequency ! out < ! in . Output frequency ! out can be independent of the input frequency (asynchronous operation) or a subharmonic of the input frequency (synchronous operation). Fig. 3.4 (a) and (b) shows representative simulations of the circuit in the synchronous mode where ! in = 2! out and ! in = 10! out , respec- tively. It can be seen that in order to generate the subharmonic of the signal at the output, the input amplitude or power needs to be larger than a certain threshold. This is a known fact in frequency dividers, such as injection-locked or regenerative frequency dividers. 69 3.2 Characteristic This section shows the main characteristics of the proposed circuitry (Fig. 3.5) through analysis and simulations. Let's assume v 1 , v 2 , i 1 and i 2 represent the single-ended output voltages and inductor currents, respectively. Also, the input signal isV in cos(! in t). Neglecting base currents in the BJTs, the following equations can be written: C _ v 1 C _ v 2 =i 1 i c1 ; (3.1) C _ v 2 C _ v 1 =i 2 i c2 ; (3.2) L _ i 1 =Ri 1 +v 1 V in cos(! in t); (3.3) L _ i 2 =Ri 2 +v 2 V in cos(! in t); (3.4) i c1 I s e v 2 V T ; (3.5) i c2 I s e v 1 V T ; (3.6) where I s is the saturation current and V T = kT q 25:8 mV at room temperature 70 Figure 3.5: Self-powered downconverter with state-variables along with its simpli- ed second-order model. is the thermal voltage. Taking the independent state variables as v d = v 1 v 2 , i c =i 1 +i 2 , and i d =i 1 i 2 , the set of dierential equations for the system is 2 6 6 6 6 6 6 4 _ i d _ v d _ i c 3 7 7 7 7 7 7 5 = 2 6 6 6 6 6 6 4 R L 1 L 0 1 2C 0 0 0 0 R L 3 7 7 7 7 7 7 5 2 6 6 6 6 6 6 4 i d v d i c 3 7 7 7 7 7 7 5 + 2 6 6 6 6 6 6 4 0 ic 2C tanh( v d 2V T ) 2V in L cos(! in t) + 2V T L ln( ic 2Is sech( v d 2V T )) 3 7 7 7 7 7 7 5 : (3.7) Thus, the dynamics of the circuit is described by a third-order non-autonomous nonlinear dierential equation, where the dierential voltage v d and current i d de- pend on the common-mode currenti c . Some simplifying assumptions will be made in order to solve this equation. Assuming zero initial conditions for the inductor and capacitor, att = 0,v 1 and v 2 are equal to the common mode input voltage. Therefore, att = 0,v c =v 1 +v 2 = 2V in cos(! in t) and thus i c =i 1 +i 2 =(i c1 +i c2 ) =2I s e V in V T cos(! in t) : (3.8) 71 Fort> 0, while the dierential voltagev d is still small, we assume that the common mode voltage,v c , and common mode current,i c , remain approximately intact. With the approximate solution for i c , the dierential equations in Eq. 3.7 is simplied to the following second-order non-autonomous nonlinear dierential equation 2 6 6 4 _ i d _ v d 3 7 7 5 = 2 6 6 4 R L 1 L 1 2C 0 3 7 7 5 2 6 6 4 i d v d 3 7 7 5 + 2 6 6 4 0 1 2C 2I s e V in V T cos(! in t) tanh( v d 2V T ) 3 7 7 5 : (3.9) In this case, the circuit can be modeled as an RLC tank with the capacitor voltage and inductor current (v d andi d ) as state variables and a nonlinear time-dependent current sourcef(v d ;t) that represents the dierential current (i c2 i c1 ) in the tran- sistor pair (Fig. 3.5). In order to derive the transient waveforms, quasi-harmonic approximation is used, where the transient and steady-state expressions for the voltage and current waveforms are assumed to resemble sinusoids with slowly time-varying amplitude r(t) and phase (t) as [46] v d (t) =r(t) cos(! out t +(t)); (3.10) i d (t) = 2! out Cr(t) sin(! out t +(t)); (3.11) and ! out = 1 p 2LC . The quasi-harmonic approximation is valid as long as the RLC quality factor is reasonably large. By taking the derivatives ofv d andi d in the above 72 equations with respect to time and replacing them in the original equation (Eq. 3.9), the following rst-order dierential equations for r(t) and (t) are obtained _ r = 1 2C f(r cos(! out t +);t): cos(! out t +) + R L r sin 2 (! out t +); (3.12) _ = 1 2Cr f(r cos(! out t +);t): sin(! out t +) + R 2L r sin(2! out t + 2); (3.13) where f(r cos(! out t +);t) = 2I s exp( V in V T cos(! in t)) tanh( r 2V T cos(! out t +)): In order to convert the above non-autonomous dierential equations to au- tonomous ones and removing explicit time dependency, the equations are averaged over one oscillation period, T = 2 !out . Since the amplitude and the phase are slowly-varying functions of time over the oscillation period, they are assumed to be constant in the averaging process. Therefore, the averaged dierential equations for r(t) and (t) are given by _ r = 1 2C : 1 T Z T f(r cos(! out t +);t) cos(! out t +)dt + R 2L r; (3.14) _ = 1 2Cr : 1 T Z T f(r cos(! out t +);t) sin(! out t +)dt: (3.15) In steady-state, the amplitude and phase variations should be zero, i.e., _ r = 0 and _ = 0. Fig. 3.6 (a) and (b) shows the numerical solution of Eq. 3.14-3.15 using MATLAB and the simulated transient voltage waveform using Spectre for the dierential voltage, v d when V in = 0:68 V and V in = 0:7 V, respectively. Analysis and transient simulations consistently show growth and sustaining of a sinusoidal 73 Figure 3.6: Transient behavior of the circuitry for (a) V in = 0:68 V, and (b) V in = 0:7 V. dierential voltage for large input amplitudes, and zero dierential output for small input voltages. Throughout this section, the BJT model used for calculations and simulations is PBR951 UHF wideband transistor (Philips Semiconductors) with I s = 0:963 fA and = 102. All the simulations and calculations are performed for L = 2:2H andC = 820 pF, corresponding to a tuned frequency of approximately 2.64 MHz, and R = 2:8 , corresponding to inductor quality factor of 13 at 2.64 MHz. 3.2.1 Start-up Condition In this part, we nd the minimum required input amplitude V in;th required for the growth of dierential output voltage. To nd a closed form formula for the start-up condition, tanh(:) function in Eq. 3.14-3.15 is approximated with the rst two terms of its Taylor series expansion, i.e., tanh(x) xx 3 =3. Also, to simplify the analysis, we assume that the input frequency is an integer multiple of output frequency, i.e., ! in =n! out , where n is an integer. The following averaged 74 autonomous nonlinear dierential equations for the amplitude _ r and phase _ can be found for dierent values of n: 1) n = 1 _ r =rf R 2L + I s 4CV T [I 0 () +I 2 () cos(2)]g ( r 2V T ) 3 I s 2C [ 3 4 I 0 () +I 2 () cos(2) + 1 4 I 4 () cos(4)]; _ = I s sin(2) 4CV T [I 2 () ( r 2V T ) 2 ( I 2 () 2 + I 4 () 2 cos(2))]: (3.16) 2) n = 2 _ r =rf R 2L + I s 4CV T [I 0 () +I 1 () cos(2)]g ( r 2V T ) 3 I s 2C [ 3 4 I 0 () +I 1 () cos(2) + 1 4 I 2 () cos(4)]; _ = I s sin(2) 4CV T [I 1 () ( r 2V T ) 2 ( I 1 () 2 + I 2 () 2 cos(2))]: (3.17) 3) n = 4 _ r =r[ R 2L + I s 4CV T I 0 ()] I s 2C ( r 2V T ) 3 [ 3 4 I 0 () + 1 4 I 1 () cos(4)]; _ = I s I 1 () 16CV T ( r 2V T ) 2 sin(4): (3.18) 75 4) n = 3 and n 5 _ r =r[ R 2L + I s 4CV T I 0 ()] 3I s 8C ( r 2V T ) 3 I 0 (); _ = 0: (3.19) By denition, the amplitude and phase variation should be zero in the steady- state, i.e., _ r = 0 and _ = 0. The detailed analysis is shown for the case n = 2. So, the nonzero xed points (solutions to the simplied averaged dierential equations) are [r 2 ;] = [0; k 2 ]; (3.20) [r 2 ;] = [(2V T ) 3 R 2L + Is 4CV T [I 0 () +I 1 ()] Is 2C [ 3 4 I 0 () +I 1 () + 1 4 I 2 ()] ;k]; (3.21) [r 2 ;] = [(2V T ) 3 R 2L + Is 4CV T [I 0 ()I 1 ()] Is 2C [ 3 4 I 0 ()I 1 () + 1 4 I 2 ()] ; (2k + 1) 2 ]: (3.22) In order to analyze the stability of these solutions, the eigenvalues of the Jacobean matrix given by 2 6 6 4 @ _ r @r @ _ r @ @ _ @r @ _ @ 3 7 7 5 (3.23) 76 should be evaluated at each xed point. The rst solution, r = 0; cos(2) =1, has the following eigenvalues 1 = R 2L + I s 4CV T [I 0 () +I 1 () cos(2)]; (3.24) 2 = I s I 1 () 2CV T cos(2): (3.25) Therefore, r = 0; cos(2) =1 is either a saddle point or an unstable point de- pending on the value of . However, r = 0; cos(2) = 1 will be a saddle point if R 2L + Is 4CV T [I 0 () +I 1 ()]< 0 (which provides the start-up condition); otherwise, it is a stable point. This is when the start-up condition is not satised. The second solution exists only when R 2L + Is 4CV T [I 0 () +I 1 ()] > 0, in which case both the eigenvalues (shown below) will be negative 1 =2[ R 2L + I s 4CV T [I 0 () +I 1 ()]]; (3.26) 2 = I s 2CV T [I 1 ()V T (I 1 () +I 2 ()) R 2L + Is 4CV T [I 0 () +I 1 ()] Is 2C [ 3 4 I 0 () +I 1 () + 1 4 I 2 ()] ]: (3.27) 77 Consequently, this will be a stable steady-state solution when R 2L + Is 4CV T [I 0 () + I 1 ()]> 0. The eigenvalues corresponding to the third solution are 1 =2[ R 2L + I s 4CV T [I 0 ()I 1 ()]]; (3.28) 2 = I s 2CV T [I 1 ()V T (I 1 ()I 2 ()) R 2L + Is 4CV T [I 0 ()I 1 ()] Is 2C [ 3 4 I 0 ()I 1 () + 1 4 I 2 ()] ]; (3.29) which corresponds to a saddle point if R 2L + Is 4CV T [I 0 ()I 1 ()] > 0 and to an unstable point otherwise. Therefore, if R 2L + Is 4CV T [I 0 () +I 1 ()] > 0, the second xed point is the stable solution, satisfying the start-up condition; otherwise,r = 0 becomes the stable point. In summary, stability analysis of steady-state solutions oers the following start-up condition for dierent values of n n = 1 : I s [I 0 () +I 2 ()] V T > 2RC L ; (3.30) n = 2 : I s [I 0 () +I 1 ()] V T > 2RC L ; (3.31) n 3 : I s I 0 () V T > 2RC L : (3.32) It is more desirable to nd the circuit start-up condition and other properties in terms of input power instead of input voltage swing. In the synchronous mode, the average input power is P in = 1 T Z T V in cos(! in t)i c (t)dt; (3.33) 78 Figure 3.7: Minimum required input power for start-up, P in;th , when n = ! in !out = 2 versus (a) resonator quality factor Q, (b) resonator capacitance C, and (c) BJT saturation current I S . where T is the largest period in the system. At start-up and for small dierential voltage, v d , the common-mode current is given by Eq. 3.8. In this case, the input power is simplied to P in 2I s I 1 ()V in : (3.34) Equations 3.30-3.32 and 3.34 can be combined to nd the minimum input power, P in;th , required to start a growing oscillation at! out = ! in n . Fig. 3.7 shows the calcu- lated and Spectre simulated P in;th versus resonator quality factor (Q), capacitance (C), and BJT saturation current (I s ), respectively for n = 2. Higher resonator Q, smaller C (corresponding to larger eective parallel resistance for the resonator), and larger I s (corresponding to a steeper I c V BE and a smaller V BE;ON ) relaxes 79 Figure 3.8: (a) Minimum required input power for start-up, P in;th , versus n = ! in !out when Q = 13, and (b) normalized minimum required input power for start-up P in;th (n3) P in;th (n=2) versus resonator quality factor (Q). the start-up condition. Fig. 3.8 (a) shows P in;th versus n = ! in !out for Q = 13. As predicted by the calculations, n = 2 requires the minimum P in;th , and as n in- creases, P in;th stays almost constant. Finally, Fig. 3.8 (b) shows the ratio of P in;th atn 3 toP in;th atn = 2 versus Q. This ratio is approximately 2, suggesting that the minimum required input power to start a synchronous output at ! out = ! in n for n 3 is 3 dB more than that for n = 2, nearly independent of the quality factor. 3.2.2 Steady State Solutions Non-zero steady-state amplitude and phase solutions (r ss ; ss ) in the synchronous mode, i.e., n = ! in !out integer, are found by setting _ r = 0 and _ = 0 in Eq. 3.14- 3.15. Fig. 3.9 (a) shows the variation of the steady-state amplitudes r ss asV in and therefore P in varies, for n = 2 when Q=13. As can be seen, by increasing P in , v d increases smoothly in the power/current limited region and saturates at a specic value where it does not increase by increasing input power in the voltage limited 80 Figure 3.9: Variation of (a) the steady-state amplitudes r ss , and (b) the power eciency as P in varies for f in = 2f out = 5:29 MHz and when Q = 13. region. Since in deriving Eq. 3.14-3.15, we have assumed that v d has a relatively small amplitude, the calculation is not valid at large output swing values. The output power is dened as the power delivered to R L , the total parallel resistance of the tank P out = r 2 ss 2R L : (3.35) This resistor captures the resonator loss, represented by R P = 2 (L!out) 2 R , as well as any explicit load resistance. So, all the references to the resonator quality factor are intended for the loaded quality factor. The power transfer eciency can be derived as p = P out P in : (3.36) Fig. 3.9 (b) shows power eciency versus P in for n = 2 and Q=13. We can observe that in the current limited region, power eciency increases asP in increases. However, in the voltage limited region, the eciency drops by increasing P in , since the output voltage is almost constant. Fig. 3.10 shows power eciency versus n 81 Figure 3.10: Variation of the power eciency versus n forr = 50 mV andr = 150 mV when Q = 13. for dierent input voltage swing levels where n is assumed to be an integer number. The circuitry shows the highest eciency at n = 2. As n increases, the eciency does not change and it is almost half of the eciency at n = 2. 3.2.3 Eect of Detuning and Locking Range In practice, the passive resonator frequency may not be exactly equal to an integer frequency of input frequency, i.e., ! out 6= ! in n . In this section, we derive the max- imum frequency detuning for which the circuit still operates in the synchronous mode, i.e., it produces an output frequency that is exactly equal to ! in N where N is an integer number. Let us assume ! in !out =n =N + where N is an integer and << N represents the frequency detuning. For 6= 0, the output waveform may have dierent behaviors. At small input voltage levels, asn is detuned from integer values, the oscillation amplitude decreases till it dies (Fig. 3.11 (a)). As the input amplitude increases, by detuning n, the oscillation amplitude decreases till it goes 82 Figure 3.11: Dierent scenarios for the oscillator output signal, when it is detuned more than it can tolerate at dierent V in : (a) V in1 , (b) V in2 , and (c) V in3 , where V in1 <V in2 <V in3 . Zoomed versions are shown in the respective insets. out of the locking range where it has an asynchronous oscillation with amplitude much smaller compared to the integer n (Fig. 3.11 (b)). As input amplitude in- creases more, by detuning n, the oscillation amplitude does not change, saturated at approximately the maximum value; however, as it goes out of the locking range it has an asynchronous oscillation with negligible change in the peak amplitude (Fig. 3.11 (c)). Now, we want to nd the detuning range or the locking range. If the output signal is synchronized with the input signal, its frequency ! out + _ will be equal to ! in N . For << N, we assume that Eq. 3.16 - 3.19 can still represent the average equations for the system. In this case, _ r = 0 and _ = N ! out represent the steady-state locking condition. The detailed analysis is going to be shown for N = 2. In this case, there are two xed points, (r;). The rst one is r = 0; (3.37) 2 ! out = I s I 1 () 4CV T sin(2); (3.38) 83 Figure 3.12: Phase portrait of the circuitry around the stable point at dierent values of n (a) n = 2, (b) n = 1:97, (c) n = 1:95, and (d) n = 1:93 for Q = 13 and V in = 0:695 mV. corresponding to oscillator dying down (Fig. 3.11 (a)). To nd the stability of this xed point, the averaged equation is linearized around the xed point. In this case, the eigenvalues of the linearized equation are 1 = R 2L + I s 4CV T [I 0 () +I 1 () cos(2)]; (3.39) 2 = I s I 1 () 2CV T cos(2): (3.40) If n is an integer number ( = 0), will equal 0. Asjj increases, and the input frequency is further detuned fromN! out , goes to the rst or fourth quadrant (Eq. 3.38). As an example, Fig. 3.12 shows the phase portrait of the circuitry around the stable point at dierent values of n for Q = 13 and V in = 0:695 mV. Since 84 in rst and fourth quadrants, cos(2) > 0, consequently, 2 < 0. Thus, to nd the locking range in this case, we only need to nd the condition where 1 stays negative. In this case, the locking range equals Lock 2 ! out = I s I 1 () 4CV T s 1 ( 2RC L : V T I s I 1 () I 0 () I 1 () ) 2 ; (3.41) when I 0 ()< 2RC L : V T Is . So, in this case by detuning more than Lock derived in Eq. 3.41, the start-up condition will not be satised and oscillation will be stopped. For the other xed point, we have sin(2) =1 at the edge of locking; thus, cos(2) = 0 and cos(4) =1. Therefore, the second xed point is r 2 = 4(2V T ) 3 RC L + IsI 0 () 2V T I s [3I 0 ()I 2 ()] ; (3.42) 2 ! out = I s I 1 () 4CV T [1 ( r 2V T ) 2 ]; (3.43) corresponding to asynchronous oscillations (Fig. 3.11 (b)). So, the locking range equals Lock 2 ! out =f I s I 1 () 4CV T +I 1 () 2R L + IsI 0 () CV T 3I 0 ()I 2 () g: (3.44) In this case by detuning more than Lock derived in Eq. 3.44, the oscillator goes out of locking range and it shows asynchronous oscillation. As mentioned above, at the edge of these two regions, we have I 0 () = 2RC L V T I s : (3.45) 85 Figure 3.13: (a) Input power at the edge of oscillation dying and pulling versus tank quality factor (Q), locking (tuning) range versus input power (b) at N = 2 for Q = 13 and 6, and (c) N = 1 and N = 4 for Q = 13. Fig. 3.13 (a) shows the input power at the edge of the oscillation dying and pulling versus Q. For this calculation, maximum is derived from Eq. 3.45 and then replaced in Eq. 3.34 to nd P in;max . Fig. 3.13 (b) shows the locking range versus the input power for Q = 13 and 6. The calculation uses Eq. 3.41 and 3.44 for each region. Since the model in not valid when the output voltage saturates, Eq. 3.44 cannot predict the locking range accurately in that case. Following the same procedure mentioned above, the locking range for N = 1 in the two regions equals Lock ! out = I s I 2 () 4CV T s 1 ( 2RC L : V T I s I 2 () I 0 () I 2 () ) 2 ; (3.46) Lock ! out =f I s I 2 () 4CV T +I 2 () 2R L + IsI 0 () CV T 3I 0 ()I 4 () g: (3.47) 86 For N = 4, only oscillation pulling happens by detuning n. The reason is that _ = 0 for r = 0. Therefore, the locking range limited by the oscillation pulling is Lock 4 ! out = I 1 () 3I 0 () [ R 2L + I s I 0 () 4CV T ]: (3.48) Fig. 3.13 (c) shows the locking range versus the input power for N = 1 andN = 4 when Q = 13. For N = 3 and N 5, since _ = 0, detuning does not have any eect on the oscillation frequency. Therefore, the circuit will show an asynchronous oscillation and the output signal cannot lock to the input signal. 3.2.4 MOSFET Nonlinear Core In the previous subsections, the nonlinear core is assumed to consist of BJT tran- sistors. The exponential I-V characteristic of BJT eases the analysis and enables derivation of closed-form expressions from which intuition can be gained. In this section, we brie y discuss the eect of using MOSFET transistors in the nonlinear core. The I-V characteristic of MOS transistors is not as well behaved, especially, as transistor enters dierent operation regions (e.g., saturation, triode) throughout the large-signal operation. However, based on the simulation results, the circuit function does not depend on the exact nonlinear function. The simulations are done for the same schematic shown in Fig. 3.5, except that the BJT transistors are replaced with NMOS transistors in a 0.13m CMOS technology. The same passive devices have been used (L = 2:2 H; C = 820 pF; R = 2:8 , corresponding to 87 Figure 3.14: Simulated minimum required input power for start-up, P in;th versus (a) n = ! in !out , and (b) NMOS channel width W at n = 2; (c) the steady-state amplitudes r ss , and (d) locking (tuning) range versus P in at n = 2 and Q = 13. a tuned frequency of approximately 2.64 MHz and Q of 13 at 2.64 MHz). Fig. 3.14 (a) shows the minimum required input power for the start-up (P in;th ) versus n, with NMOS size ofW=L = 150m=130nm. Similar to the case where BJT de- vices have been used, n = 2 requires the minimum input power and as n increases, P in;th is relatively constant and approximately 3 dB more than n = 2. Fig. 3.14 (b) shows P in;th versus the width of the MOS transistor W when channel length is L = 130nm andn = 2. Again, we see that larger transistors and smaller threshold voltages are benecial as they reduce the minimum input power requirement. Also, P in;th shows stronger dependence on the device size at small device sizes. Fig. 3.14 (c) shows the steady-state amplitude r ss versusP in , whenW=L = 150m=130nm 88 Figure 3.15: (a) The detailed schematic, and (b) the board photograph of the discrete low-frequency prototype. forn = 2 in comparison with the BJT case 1 . Fig. 3.14 (d) shows the locking range versus the input power which is very close in both BJT and CMOS cases. 3.3 Measurement Results In this section, measurements results for discrete and integrated prototypes verify- ing the analytical claims are presented. 3.3.1 Discrete Frequency Downconverter To experimentally demonstrate the generation of various subharmonic signals in the synchronous operation mode and verify the corresponding locking ranges, the con- guration shown in Fig. 3.5 is implemented. The BJTs and passives are the same used in calculations and simulations (BJT transistor is PBR951, L = 2:2 H, and C = 820 pF), shown in Fig. 3.15 along with the board photograph. Representative 1 The circuitry with this size of NMOS transistor requires the same P in;th as a circuitry using BJT with I s = 0:963 fA. 89 Figure 3.16: (a) The measurement setup, and the measured input and dierential output waveforms when (b) f in = 2f out , and (c) f in = 10f out . measured input and dierential output waveforms of the circuit forf in = 2f out and f in = 10f out are shown in Fig. 3.16 (b) and (c), respectively. For the measurements, a high input-impedance oscilloscope has been used (Fig. 3.16 (a)); therefore, no output buer was required. Fig. 3.17 (b) shows the measured, simulated, and calculated minimum required input power (P in;th ) for subharmonic generation (not necessarily synchronous) versus the input frequency. As expected, dividing by 2 (n = 2) requires the minimum input power and as frequency increases, almost a constant input power is required. As predicted before, the dierence in P in;th for n = 2 and n > 2 is about 3 dB. The measured, simulated, and calculated locking 90 Figure 3.17: (a) The measurement setup, and measured, simulated, and calculated (b) minimum required input power (P in;th ) for subharmonic generation versus the input frequency, (c) locking (tuning) range, (d) output amplitude, and (e) power eciency versus input power at n = 2. range for n = 2 versus the input power is depicted in Fig. 3.17 (c). The dier- ential output amplitude and power eciency are shown in Fig. 3.17 (d) and (e), respectively. Q of 6 is assumed for the simulation and calculation to match to the measurement results. Also, since there is no matching circuitry at the input, direc- tional couplers have been used to extract the value of the input power that goes into the circuitry (Fig. 3.17 (a)). Also, as an example, the measured dierential output voltages during the circuit pulling at two dierent input power levels for n = 2 are shown in Fig. 3.18. 91 Figure 3.18: Measured output waveforms when the downconverter is pulled for n = 2 at (a) P in1 and (b) P in2 , where P in1 < P in2 . Zoomed versions are shown in the respective insets. 3.3.2 Integrated 12 GHz Divide-by-2 Self-Powered Divider As shown before, division by 2 requires lowest input power and also provides highest eciency. In order to demonstrate the applicability of this technique at higher frequencies, an integrated 12 GHz divide-by-2 circuitry is designed and fabricated in a 0:13m CMOS technology with 8 metal layers (Fig. 3.19). As mentioned in the previous section, smaller threshold voltage for the switching pair transistors relaxes the start-up condition; therefore, triple-well transistors have been used with positive bulk voltage to reduce the threshold voltage. Also, the bulk and N-well of the transistors have been oated with a large resistance (1.1 M ) to reduce the parasitic capacitance. The input at 12 GHz is matched to 50 using theL 1 C 1 L 2 C 2 ladder network. From simulations, the loss of the matching circuitry network at 12 GHz is about 2 dB including the matching circuitry, while the Q of the resonance tank at 6 GHz is approximately 15. An open-drain output buer has been placed after the divider to facilitate measurements. The N-well and bulk voltages are kept 92 Figure 3.19: (a) Detailed schematic, and (b) chip microphotograph of the integrated 12 GHz divide-by-2 self-powered divider. at 1.5 V and 0.5 V, respectively. Fig. 3.20 (a) shows the small-signal input re ection coecientS 11 whenP in =7 dBm. The measured and simulated sensitivity curves (locking range) are shown in Fig. 3.20 (b); the minimum required input power is about 2 dBm, while the locking range is approximately 1 GHz at P in =11.45 dBm. Fig. 3.20 (c) shows the measuredP in;th versus the bulk voltage. As the bulk voltage increases, the threshold voltage of the NMOS transistors reduces; thus the input power for start-up also reduces. Fig. 3.20 (d) shows the measured phase noise of the signal generator (Agilent E8257C) and the 12 GHz divider output. Table 3.1 summarizes the performance of this 12 GHz divider in comparison with other recent reported passive and active dividers. 93 Figure 3.20: Measured and simulated (a) S 11 (return loss), (b) sensitivity curve, measured (c) P in;th versus the transistor bulk voltage, and (d) phase noise of the signal generator and the 12 GHz divider output. Table 3.1: Performance Comparison among Dierent Passive and Active Dividers Ref. Frequency (GHz) Process V DD (V) P DC (mW) P in;th /V in;th Locking Range Topology Area (mm 2 ) [36] 2 Discrete pHEMT 3 N/A -14 dBm 0.4 GHz @ 0 dBm Active Parametric - [52] 20 0.13 m CMOS 0 0 440 mV 1 GHz @ 0.6 V Passive Parametric 0.24 (active) [95] 7 0.13 m CMOS 0.8 0.9 -28 dBm 2.43 GHz @ 0 dBm Injection- Locked 0.033 (active) [16] 23.5 0.18 m CMOS 0.9 8.28 -30 dBm 3.2 GHz @ 0 dBm Injection- Locked 0.62 (active) [38] 21.35 0.13 m CMOS 0.8 1.51 -12 dBm 4.1 GHz @ 10 dBm Injection- Locked 0.23 (active) This Work 12 0.13 m CMOS 0 0 2 dBm (with matching) 1 GHz @ 11.45 dBm Memoryless Nonlinear- ity 0.64 (active) 94 Figure 3.21: Alternative conguration for the proposed passive subharmonic gener- ator without any DC power supply and their representative inpu/output waveforms: (a) dierential cross-coupled oscillator with tail transistor and (b) dierential noise- shifting Colpitts oscillator (f in = 2f out ) [2]. 3.4 Summary and Future Work This chapter presents a passive frequency downconverter scheme to transfer energy from a higher frequency source to a lower frequency, which can be a subharmonic of the input source, without consuming DC power or source. In the proposed technique, a memoryless nonlinear core coupled to a linear passive resonator is exploited for frequency downconversion. The major motivation for this work is to enable battery-less systems that must extract energy from higher electromagnetic emissions. While all analysis, designs, and experimental results correspond to the cross-coupled dierential pair active core, the principles are general and applicable to other similar circuits as well. As an example, Fig. 3.21 shows the proposed passive frequency downconverter scheme with alternative nonlinear cores, along with their representative simulated input/output waveforms. Future research can be focused on nding new passive downconverter schemes that have the highest eciency at larger frequency ratio than 2. 95 Chapter 4 Event Driven Neural Recording System Simultaneous neural signal recording from many neurons is necessary for neural research and neural prostheses to assist humans with disabilities [85]. Wireless transmission of the recorded signal is required for miniaturized and untethered neural recording systems. The main challenges in the neural recording systems are limited power resources as well as wireless transmission of large amount of data generated by using large number of electrodes. Packaging and reliable operation in a sensitive implant environment have also great challenges. In order to prevent damage of tissues due to heat, the maximum temperature increase in the cortex has to be smaller than 1 C [43]. Thus, the maximum power density should be less than 0.8 mW/mm 2 or a more conservative value of 0.2 mW/mm 2 [87]-[43]. For implantable neural interfaces, low-power dissipation is desirable also from the perspective of limited battery life or limited energy harvesting capability. Neurons communicate with one another using voltage pulses known as action potentials or spikes. Each spike has an amplitude of around 100 mV (relative to the 96 Figure 4.1: (a) Action potential waveform, (b) 3D top/bottom view of the Utah Microelectrode Array (MEA) [21], and (c) simplied microelectrode small-signal model [62]. extracellular uid) and a duration of around 1 ms (Fig. 4.1 (a)). When these spikes are observed using an extracellular microelectrode a few tens of microns away, a potential of 50 - 500 V can be detected. Intracellular penetrating electrodes can measure the entire 100 mV signal, but they cause the cell death within a few minutes; thus, they are not suitable for chronic implants. A 10 10 array of these extracellular microelectrodes, known as the Utah microelectrode array [21], is shown in Fig. 4.1 (b). The Utah array has a 400 m pitch, 1-1.5 mm long electrodes with Pt-coated tips, parylene insulated shanks, and a glass base for insulation. A simplied small-signal model of an electrode is shown in Fig. 4.1 (c). The electrical double-layer capacitance formed at the interface of the metal-tissue, C DL , dominates the impedance in the signal band. In parallel to this capacitance, the resistance R LF is the leakage resistance due to charge carriers crossing the 97 Figure 4.2: Neural recording from cat motor cortex using Utah microelectrode array [35]. electric double layer, while R HF is the resistance of the metallic portion of the electrode and the solution resistance (the resistance between the working electrode and the reference electrode) [80][62]. The neural signal recorded by the extracellular electrode mainly consists of Action Potentials (AP) or neural spikes which occupy approximately the band of 300 Hz - 10 kHz and can be the activity of one to four neurons, accompanied by a low-frequency signal ( 10200 Hz) named Local Field Potential (LFP) which is the synchronous activity of many neurons in one region of the brain that are far from the recording electrode. Also, there is a large DC oset that is generated at the interface of the electrode and tissue that can be in the order of tens of mV [62]. Fig. 4.2 shows an example of a recorded neural signal from a cat motor cortex using Utah microelectrode array, which shows both spikes and LFPs. The main information of the neural signal is encoded in the position of the spikes; also, the shape of the spikes can be important for the task of spike sorting. A typical neuron generates 10-100 spikes per second, with the duration of 1-1.5 ms for each spike [35]. 98 4.1 Multichannel Neural Recording Systems The block diagram of a generic multi-channel neural recording system with wireless telemetry is shown in Fig. 4.3. Each channel has a low-noise neural amplier with a bandpass lter to limit the noise as well as to serve as an anti-aliasing lter. The front-end is followed by an Analog-to-Digital Converter (ADC) to digitize the data. Typically, a Successive-Approximation Register (SAR) ADC is used to minimize the power consumption. In order to reduce the chip area, oftentimes one ADC is shared between M ampliers, preceded by an analog multiplexer, where ADC should work M times faster. After the signal is digitized, it may pass through a signal processing unit for functions such as spike detection, sorting, etc. After the processor, the parallel channels are serialized by a digital multiplexer and wirelessly transmitted to an external unit for monitoring, decision making, feedback, etc. The system also requires a source of energy, which is typically a compact battery, or an external RF source that is harvested through near-eld inductive coupling. Depending on the position of the signal conditioning part, transmitter, and en- ergy source, dierent congurations for the implantable neural recording system can be envisioned. In the rst conguration, all sections of the system are implanted above the skull and under the skin (Fig. 4.4 (a)). The advantage of this setting is that there is less constraint on the size and power consumption, in addition to having smaller wireless propagation loss; however, the small analog neural signals (< 500V ) should be carried over wires through skull and thus would be susceptible 99 Figure 4.3: Block diagram of the generic neural recording systems with wireless telemetry. to dierent noise or interference sources [70]. In the second conguration, the whole system is implanted bellow the skull where the amplier array is ip-chip bonded to the microelectrode array (Fig. 4.4 (b)). Compared to the previous case, it has the advantage that the neural signal is amplied right after the electrode, resulting in a higher signal delity while being less vulnerable to the noise and interference. However, the space below the skull is limited and may not be enough for the ex- ternal components such as antenna, battery, etc. Also, the power consumption is more restricted, since the system is closer to the brain which is much more sensitive to temperature increase. Finally, the wireless propagation loss is increased in this scheme as signal must travel through the skull [32]. In the third conguration, a two-chip solution is adopted [108]. The rst chip, responsible for signal condition- ing, is implanted bellow the skull and ip-chip bonded to the microelectrode array, 100 Figure 4.4: Simplied view of dierent congurations for implantable system for cortical recording, (a) all the system is above the skull, (b) all the system is below the skull, and (c) the dual-chip system. while the second chip, including the transmitter and energy sources, is implanted above the skull (Fig. 4.4 (c)). The advantages of this two-chip approach are reduc- ing the wireless propagation loss, providing more space for the wireless telemetry and power harvesting sections that include several external components such as the antenna, quartz resonator, capacitors for DC-DC converters and voltage regu- lators, and a wirelessly rechargeable battery, better heat dissipation and thermal management, and architectural scalability; the front-end chip can be redesigned in improved technology nodes or with dierent specications without requiring costly redesign or technology porting of the back-end portion. The connection between the two chips is through a low-voltage high-speed serial link for data and supply lines for power delivery. Another important feature of the dual-chip solution is that the architecture can be modular. Dierent electrode arrays can be implanted to 101 cover larger area and they can share the same transmitter and power harvesting unit simultaneously (Fig. 4.4 (d)). 4.1.1 System Requirements In this section, the main requirements and characteristics of the multi-channel neural recording systems, in terms of the noise, dynamic range, and required number of bits and data rate are studied. The input-referred noise of the system includes the biological noise from the far-eld neurons V 2 n;bio [23], the thermal noise of the electrode V 2 n;electrode , and the noise from the electronic circuitry, including both thermal and icker noise of the ampliersV 2 n;amp and the ADC quantization noiseV 2 n;adc . Given that all these noise sources are independent, the total input noise voltage is given by V n;total = q V 2 n;electrode +V 2 n;bio +V 2 n;amp +V 2 n;adc : (4.1) The electrode thermal noise can be expressed by V 2 n;electrode = 4k B TRf; (4.2) where f is the signal bandwidth, T is the absolute temperature in Kelvin,k B is the Boltzman constant, and R is the equivalent real part of the electrode impedance. Fig. 4.5 shows the simulated electrode thermal noise versus electrode resistance for 102 Figure 4.5: Electrode thermal noise versus electrode resistance for f = 10 kHz and T=37 . f = 10 kHz (the maximum bandwidth of spikes) and T=37 C (body temperature). Considering the background noise due to the biological noise and the thermal noise of the electrode, the total input noise of the system (without the electronic circuitry) is around 10 V rms ; therefore, if the noise of the electronic circuitry is less than 5 V rms , then the overall system Noise Figure (NF) would be less than 1 dB. As stated before, the peak amplitude of the spike recorded by the extracellular electrode is smaller than 0.5 mV while the input noise of the system is around 10 V rms ; so, the best received Signal-to-Noise Ratio (SNR) is around 34 dB. The SNR will be lower as the electrode moves further away picking up smaller signals as low as 50 V . Variable Gain Amplier (VGA) with Automatic Gain Control (AGC) boost the level of the desired signal (neural signal) to the Full Scale Range (FSR) of the ADC. This leads to the best utilization of ADC resolution. The ADC resolution, specied as the Eective Number of Bits (ENOB), should be high enough not to degrade the received SNR further and to retain all the information of the neural signal waveform. For high enough resolution, the quantization noise of and ADC can be assumed to be white with Power Spectral Density (PSD) of 2 2 where 103 is the least signicant of the ADC given by = FSR 2 N . For the best case SNR of around 34 dB, the ADC ENOB 6 bits leads to the quantization noise level equal to that of the thermal noise and SNR degradation by 3 dB. Adding a few more bits pushes the ADC quantization noise below the received thermal noise. In our system, a 9-bit ADC is designed. Assuming 0.35 V as the full scale range for the ADC, the neural ampliers need to provide at least 57 dB of gain, since the input signal is < 500 V. The aggregate data rate of the system is given by the number of electrodes sampling rate ADC number of bits. The maximum bandwidth of the spike is 10 kHz; so, the minimum sampling rate should be 20 kS/s in order to satisfy the Nyquist sampling criteria. As an example, assuming 100 electrodes and 9 bit resolution for ADC, the aggregate data rate equals 100 20 kS/s 9-bit = 18 Mb/s. Processing or transferring this volume of data without dissipating excessive power is a challenge. 4.1.2 Previous Work A few of the previous state-of-the-art integrated neural recording systems are dis- cussed in this section. The rst scheme, a pioneering work of Harrison, et al. [32], is a 100-channel neural recording system with a 2.64 MHz inductive coupling link for power delivering and downlink communication, 100 low noise neural ampliers, one SAR ADC for 100 ampliers in a multiplexed fashion, spike detectors to reduce 104 the data rate, and a 433 MHz FSK transmitter for uplink communication. Due to the limited bandwidth of the FSK transmitter, only few individual channels or the output of 100 spike detectors can be selected concurrently for data transmission. The second work is a 128-channel neural recording systems reported in [13]. The system consists of 8-bank of 16-channel low noise neural ampliers and one SAR ADC per 16 ampliers, on-chip spike detection and sorting for one channel, and a 90 Mb/s IR-UWB transmitter. The ampliers use sequential turn-on scheme to reduce the power consumption. The battery is used as the source of energy. The third work is a 32-channel neural recording system developed at the Geor- gia Tech [51]. The system includes a 13.56 MHz inductive coupling link for power delivery. In this scheme, rather than digitizing the neural data using ADC, an Amplitude-to-Time Conversion (ATC) scheme using Pulse-Width-Modulation (PWM) is employed. For the uplink communication, a 902 - 928 MHz FSK transmitter is used. At anytime, 12 ampliers are on to reduce the power consumption. Another on-chip neural recording system is a 64-channel neural recording sys- tem presented in [1]. The system dedicates an 8-bit SAR ADC per channel, pro- grammable FIR lters for frequency discrimination, and a 915 MHz OOK/FSK transmitter for the uplink communication. The battery is used as the source of energy. 105 A 96-channel neural interface system, called HermesE and developed at Stanford [37], exploits a switched-capacitor bandpass lter rather than using continues lters with a dedicated SAR ADC per channel. The battery is used as the source of energy. A recent paper by the University of California, Berkeley, introduces a distributed sensor network architecture for neural recording systems [8]. Each sensor node composed of a oating silicon needle and all signal conditioning circuitry with RF energy harvesting module. The power is transmitted using a 1.5 GHz carrier, having a centimeter-range power link with 30 dBm of input power. Passive backscatter telemetry is used for uplink data communication. The specic implementation includes 4 neural amplier with a dedicated VCO-based ADC per channel. Table 4.1 summarizes the performance of several integrated neural recording systems. 4.2 Proposed Architecture Simplied schematic of a typical channel in a recording system is shown in Fig. 4.6 (a), along with the state-of-the-art energy eciency and power consumption of each block. The neural amplier typically consists of two stages, where the lower bound on the power consumption of rst and second stages are set by the input-referred noise V ni;rms and linearity requirements, respectively. The noise-power tradeo is 106 Table 4.1: Performance summary of the integrated neural recording systems Ref. #Ch. Input Ref. Noise ADC # Amp/ ADC TX Scheme TX Data Rate Power (mW) Area (mm 2 ) Power/ Channel Energy Source Process (CMOS) [32] 2007 100 5.1Vrms 10-bit @ 15 kS/s 100 FSK @ 433 MHz 330 kb/s 13.5 27.7 135 W Inductive coupling @ 2.64 MHz 0.5 m [13] 2009 128 4.9Vrms 9-bit @ 640 kS/s 16 IR-UWB 90 Mb/s 6 63.4 46 W Battery 0.35 m [51] 2010 32 4.9Vrms N/A N/A FSK @ 915 MHz 710 kS/s 5.85 16.4 182 W Inductive coupling @ 13.56 MHz 0.5 m [1] 2011 64 6.5Vrms 8-bit @ 56.8 kS/s 1 OOK/FSK @ 915 MHz 1.5 Mb/s 5 12 78 W Battery 0.13 m [37] 2012 96 2.2Vrms 10-bit @ 31.25 kS/s 1 N/A N/A 6.5 25 67 W Battery 0.13 m [8] 2013 4 6.5Vrms 10-bit @ 20 kS/s 1 Backscatter 1 Mb/s 0.0105 0.125 2.62 W Inductive coupling @ 1.5 GHz 65 nm [88] 2010 128 6 Vrms 8-bit @ 111 kS/s 8 N/A N/A 2.43 8.5 18.9 W Battery 0.35 m [103] 2011 32 5.4Vrms 8-bit @ 31.25 kS/s 4 N/A N/A 0.325 9.9 10.1 W Battery 0.18 m [62] 2012 1 4.9Vrms 8-bit @ 20 kS/s 1 N/A N/A 0.00504 0.013 5.04 W Battery 65 nm [108] 2013 100 4 Vrms 9-bit @ 245 kS/s 10 N/A N/A 1.16 28.2 11.6 W Battery 0.18 m [14] 2011 16 5.6Vrms 8-bit @ 31.25 kS/s 1 N/A N/A 0.365 2.88 22.8 W Battery 0.25 m [55] 2009 16 4.3Vrms 10-bit @ 256 kS/s 16 N/A N/A 0.06 8.25 3.76 W Battery 0.35 m 107 characterized by the Noise Eciency Factor (NEF), introduced rst in [94] and given by NEF =V ni;rms s 2I amp :V T :4k B T:BW amp ; (4.3) where I amp is the amplier current, V T is the thermal voltage, and BW amp is the bandwidth of the amplier. In the state-of-the-art low-noise ampliers, the mea- sured NEF is between 2 and 3 (Fig. 4.6 (b)). The linearity of the neural amplier is characterized by the Total Harmonic Distortion (THD). The ratio of the maximum output voltage to the THD is shown in Fig. 4.6 (a) for the state of the art neural ampliers. For example, the neural amplier reported in [55] achieves NEF=2.16 with 4:3V rms input-referred noise and 0:5% THD with 1.7W power consumption. The power of the ADC is given by P ADC =FOM 2 B f s ; (4.4) where FOM is the ADC Figure-of-Merit, B is the number of bits and f s is the sampling rate [63]. For the modern ADC in the similar range of resolutions and sampling speeds, the state-of-art FOM is about 10fJ/conversion step (Fig. 4.6 (c)). Considering 9 bit resolution and 20 kS/s sampling frequency, the power of the ADC can be assumed to be about 100 nW. Fig. 4.6 (d) shows the energy eciency for several short-range RF transmitters, where impulse Ultra-Wide Band (UWB) transmitters can achieve the lowest energy per bit. Considering 10pJ/bit energy 108 Figure 4.6: (a) Schematic of one channel in the conventional neural recording sys- tem, along with the energy costs for (b) neural ampliers, (c) ADC, and (d) short- range transmitters. eciency, the power required for transmitting one channel information is about 1.8 W (9bit20kS/s10pJ/bit). Thus based on these graphs, the main power hungry blocks are the neural ampliers as well as the transmitter. As stated before, the spike ring rate is between 10 - 100 spike/s with the du- ration of less than 1.5 ms. So, the information duty cycle is less than 15%. If the system is turned on only during the spike period, the power consumption can be reduced signicantly. The adaptive sampling, resulted by having duty-cycling system can also reduce the transmitter data rate and its power consumption, con- siderably. The proposed wake-up duty-cycling neural recording system is depicted in Fig. 4.7. As an example, let us assume a 100-channel neural system which 109 Figure 4.7: Schematic of one channel in the duty-cycling wake-up neural recording system. consumes 0.5 mW, while the wake-up receiver consumes 40 W . Assuming the sampling rate of 20 kS/s with 9-bit resolution for each channel, and a turning-on time of 1.5 ms for each spike, the data rate and the power reduction ratio versus the ring rate are calculated and shown in Fig. 4.8 (a) and (b), respectively. In the proposed scheme, the wake-up receiver should continuously monitor the input for the action potentials and activates the main path for a spike. So, it must be very low power, while having high probability of detection with small number of false alarm (wrong detection due to noise). 4.2.1 Wake-up Receiver A generic scheme for the wake-up receiver is shown in Fig. 4.9. Since the input signal is small, it should be amplied rst and ltered to reduce the noise and any undesired signal. Then it passes through a pre-processing unit which aims to improve the probability of detection by enhancing the feature of the desired 110 Figure 4.8: The calculated reduction ratio for the (a) data rate, and (b) power consumption resulting from duty-cycling wake-up system. Figure 4.9: The generic scheme for the wake-up receiver. signal. Its output is passed through a decision circuitry to decide whether the desired signal is present or not, and thus triggers the WUS generation circuitry to generate a Wake-Up Signal (WUS). The simplest scheme for the wake-up receiver is to have a single-threshold scheme shown in Fig. 4.10 (the gain stage is not shown), where the pre-processing stage is a simple unity-gain stage. In this scheme, a single comparator compares the input signal with the predened threshold voltageV th . If it is larger than V th , the timer circuitry generate the WUS with a spike duration (e.g., 1.5 ms); otherwise, it is zero. In this scheme, the value of V th oers a trade- o between false alarm rate, probability of detection, and signal integrity. In one hand, smallerV th is preferred to trigger recording a larger portion of the waveform in addition to have a high probability of detection. On the other hand, largerV th is 111 Figure 4.10: Single-threshold wake-up receiver along with its response to the spike and noise. preferred to minimize the number of false alarms. Fig. 4.11 (a) shows the variation of the Mean Squared Error (MSE) given by MSE = n X i=1 (V i;spike ^ V i;spike ) 2 n X i=1 V 2 i;spike ; (4.5) versusV th =V peak , whereV peak is the peak amplitude for the spike shown in the gure, V i;spike and ^ V i;spike are the samples of the original signal and the woken-up signal, respectively. This graph is plotted for the noise-less spike waveform shown in the left corner of the same gure. As intuitively expected, smallerV th results in smaller MSE. It can be shown that for a band-limited white noise with the standard deviation N and corner frequencyf 0 , the expected number of crossing the levelV th per unit time is given by [7] E[N V th ] = 0:577 (2f 0 ) exp ( V 2 th 2 2 N ): (4.6) 112 Figure 4.11: (a) The shape of the spikeV i;spike with the woken-up signal ^ V i;spike along with the variation of the mean squared error versus V th =V peak for the spike shown, and (b) upper bound on the number of false alarm in 1 second versus V th = N . Fig. 4.11 (b) shows the variation of E[N V th ] versus V th = N when f 0 = 10 kHz, which can be considered as an upper bound on the number of false alarms in 1 second. Again, as intuitively expected, larger V th results in smaller number of false alarms. Next, by exploiting the spike shape, a pre-processing unit called level crossing detector is proposed which can enhance the performance of the wake-up receiver. 4.2.2 Level-Crossing Detector Now, let us have a closer look at the shapes of the recorded spikes shown in Fig. 4.12. A common feature in all of these waveforms can be seen: a sharp null happens before the sample 20 which is less than quarter of the waveform. So, this common characteristic of the spikes can be exploited to shorten the duration of the false alarm and improving the detection. The waveform prior to this rst null can be 113 Figure 4.12: Dierent action potentials waveforms recorded extracellularly. approximated with a line with a known slope. Hence, two points are required to characterize this region. As such, two comparators with dierent reference voltages of V th1 and V th2 , are used. If the signal passes V th2 after a predened time passing V th1 , then the signal is considered as a spike, and thus the WUS is generated; otherwise, it is considered as noise (Fig. 4.13 (a)). The resulted WUS is OR- gated with the pulse generated from passing V th1 (C 1 signal in Fig. 4.13), so that recording starts from almost beginning of the spike. Fig. 4.13 (b) and (c) show the response of the receiver to the spike and noise, respectively. It can be seen that the false alarm duration has been shorten signicantly. Fig. 4.14 shows representative simulations for a single-threshold and a dual-threshold receivers responding to a spike waveform corrupted with an additive noise. It is clear that the duration of false positive WUS is much less in the latter scheme. The dual-threshold scheme with the feature encoded in the width of the gener- ated pulses is not limited to only spike waveforms; it can be generalized to other signals with dierent shapes. Let us consider an arbitrary signal such as the one 114 Figure 4.13: (a) Dual-threshold wake-up receiver, its response to (b) the spike, and (c) the noise. Figure 4.14: (a) Input signal corrupted with noise, and the response of (b) the single-threshold receiver, and (c) the dual-threshold receiver. 115 shown in the top right corner of Fig. 4.15. The signal can be approximated with a piecewise linear model, where the signal passesV th2 after (t 2 t 1 ) from the passing at V th1 , V th3 after (t 3 t 2 ) from the passing at V th2 , etc. A straightforward imple- mentation of the idea, referred to as the level-crossing pre-processing, is shown in Fig. 4.15. It consists of three main sections: a set of the parallel comparators with dierent thresholds, followed by a set of timer circuitries which generate pulses with predened widths upon receiving the triggers from the comparators, and a generic logic circuitry that can be either sequential, combinational, or a combination of them. When the signal passes V thi , the timer circuitry generates the pulse C i (t) with a pulse width equal to (t i t i1 ), which is based on a template signal that is desired to be detected. Therefore, the position of the C i (t) pulse is dened by the input signal and the width of the pulse is dened by the template signal. It can be said that C i (t) pulse is Pulse-Position Modulated (PPM) by the input signal and Pulse-Width Modulated (PWM) by the template signal. It should be mentioned that the pulse widths are set based on the minimum signal amplitude, since it has the longest pulse width. The two consecutive C i (t) are AND-gated (which acts as the multiplier for the pulses), and the resulted signals are added together. Thus, the output of this pre-processing N PP (t) can be written as N PP (t) = M1 X i=1 d i (t) = M1 X i=1 C i (t)C i+1 (t): (4.7) 116 Figure 4.15: The generic scheme for the level crossing pre-processing. If the signal is similar to the template, thenN PP (t) has a monotonically increasing function. There are some similarities between the proposed level crossing detector and the conventional correlator. Fig. 4.16 (a) shows simplied schematic of the correlation operation: multiplication with a known template and then summation of the output of each multiplication. The output is given by (assuming a discrete version) V corr = M X i=1 V in [i]V temp [i]: (4.8) Operation of the proposed level crossing detector is shown in Fig. 4.16 (b) where the input signal and the template signal are decomposed as the green and red graphs, respectively. If two consecutive pulses have an overlap at their edges, then 117 Figure 4.16: (a) The correlator, and (b) the level crossing detector. 118 Figure 4.17: Bank of correlators with template shifting. edge counter counts up; otherwise, it does not count, so the counter acts as the summation. Therefore, like a correlation, the input signal is multiplied by the template in a dierent domain and the resulting signal are summed up. However, there is signicant dierence between the correlation operation and level crossing detection. Since the position of the spikes are not known a priori, a bank of correla- tors, with the shifted template, are required for the detection (Fig. 4.17); thus, its implementation can be very power hungry. However, in the level crossing detector, a continuous comparison eectively acts as shifting the template (since the com- parison with threshold voltages are always done); thus making its implementation much less power hungry. 119 4.3 Characterization This section shows the main characteristics and limiting factor of the level crossing detector. First the probability of detection and false alarm is discussed and then the eect of nonidealities such as the the comparator oset on the performance will be shown. 4.3.1 Probability of Detection and False Alarm A piecewise linear waveform can be correctly detected by a combination of slope detectors. Our proposed scheme, shown in Fig. 4.18 for the dual-threshold case basically detects whether the slope of an input waveform is above or below a pre- determined value, since the threshold voltages are set by the user. Similar to any other detector, noise can aect the probability of correct detection and false alarm. Throughout this section, additive bandlimited white noise with zero mean ( = 0), variance 2 N =N 0 f c and autocorrelation function given by R N (t k ;t p ) =N 0 f c sinc(2f c jt k t p j) (4.9) is assumed (Fig. 4.19). Probabilities of correct detection and false alarm in the proposed scheme depend on the values of V th1 and V th2 , desired slope, and N , show through simulations in this section. Fig. 4.20 shows the eect of the noise on 120 Figure 4.18: The dual-threshold scheme and simplied model for the slope detec- tion. the detection. The noise perturbation causes a time-position error t1 =t 0 1 t 1 in crossing a certain threshold. This crossing time error can be written as t1 = N(t 1 ) dv dt ; (4.10) where dv dt is the slope of the signal at the crossing point. We can see that at small noise variance, this timing error caused by the noise can increase the timing dierence between the two crossing point and thus decreasing the probability of detection (Fig. 4.20 (a)). However, as noise variance increases, then noise can help other points cross the desired threshold voltage and therefore satisfying the minimum slope requirement, increasing the probability of detection (Fig. 4.20 (b)). The simulation is done for a ramp signal (single-slope signal) with the duration of 2 ms and an amplitude of 1 (Fig. 4.21 (a)). The noise is a bandlimited white noise with the bandwidth of 10 kHz (Fig. 4.21 (b)). The time dierence between the two pulses is set to t =N cycle T CLK = V th2 V th1 A T . 121 Figure 4.19: The model assumed for the noise. Figure 4.20: The error caused by the noise on the time and position of crossing point ( N1 < N2 ). Figure 4.21: (a) The ramp signal, and (b) the Gaussian noise. 122 Figure 4.22: The simulated (a) probability of detection, and (b) number of false alarm versus noise variance ( N ) for the ramp signal when V th2 = 1. Fig. 4.22 (a) shows the detection probability versus noise variance when V th2 = 1. As discussed before, as noise variance increases, P d starts decreasing and after certain variance, noise starts helping the detection probability. Fig. 4.22 (b) shows the number of false alarm versus the noise variance; as intuitively expected, larger noise variance increases the false alarm. The simulated probability of detection and number of false alarm versus V th1 and V th2 for the ramp signal for two noise variances are shown in Fig. 4.23. As the dierence between the threshold voltages increases, P d decreases, and obviously as both threshold voltages gets closer to the noise variances, both P d and number of false alarm increases. Fig. 4.24 shows the detection probability versus input amplitude, corresponding to dierent input slope, and V th1 for dierent values of V th2 . The minimum slope (and therefore the pulse width) is set for the amplitude 1. Based on Eq. 4.10, larger amplitude which has larger slope can decrease the timing error and therefore increases P d , as shown by the simulation results. 123 Figure 4.23: The simulated probability of detection and number of false alarm in 1 sec. versus the two threshold voltages V th1 andV th2 for the ramp signal when (a) N = 0:1, and (b) N = 0:2. A ramp or a single-slope can be characterized by only two points, and thus two threshold voltages. Now, the eect of adding more threshold levels on the detection performance will be studied. A third threshold level, V th3 , is added between V th1 and V th2 (Fig. 4.25). The detection probability consists of two slope detectors: the detection of the dual-threshold of V th1 V th3 as well as the dual-threshold of V th3 V th2 . Fig. 4.26 depicts the simulated detection probability for triple-threshold scheme versus the mid-threshold voltages V th3 , while V th1 and V th2 are set to 0.2 V and 1 V, respectively. On top of this curve, the detection probability for the dual-threshold ofV th1 V th3 (P D1 ) andV th3 V th2 (P D2 ), which was depicted before in Fig. 4.23 (b), are also shown. As we can see and expect intuitively, at small 124 Figure 4.24: The simulated probability of detection versus the threshold voltages V th1 and input amplitude/input slope when (a) V th2 = 1, (b) V th2 = 0:9, (c) V th2 = 0:8, and (d) V th2 = 0:7; N = 0:2. Figure 4.25: The triple-threshold scheme and simplied model for the slope detec- tion. 125 Figure 4.26: The simulated (a) detection probability versusV th3 for the ramp signal whenN th = 2, (b)N th = 1, and (c) number of false alarm versus V th3 in the triple- threshold scheme; V th1 = 0:2 V, V th2 = 1 V, and N = 0:2. V th3 the P D is limited by the probability of V th3 V th2 , P D2 , and at large V th3 the P D is limited by the probability of V th1 V th3 , P D1 . Basically, the P D follows the minimum ofP D1 andP D2 . In these simulations,N th is set to 2. It is also possible to setN th to 1; that means at least one of the dual-thresholds should happen properly. Fig. 4.26 (b) shows the simulated probability of detection versus V th3 when N th is set to 1. In this case, the P D follows the maximum of P D1 and P D2 as expected. Fig. 4.26 (c) shows the simulated number of false alarm versusV th3 forN th = 1 and 2. We can see that setting the N th = 2 makes the number of false alarm almost to zero, since it adds more restriction to the noise detection. 126 Figure 4.27: The quadruple-threshold scheme and simplied model for the slope detection. The same as before, another level V th4 can be added to the scheme, with the threshold levels of V th1 < V th3 < V th4 < V th2 (Fig. 4.27). Now, the detection probability consists of three slope detectors: the dual-threshold ofV th1 V th3 ,V th3 V th4 , andV th4 V th2 . Fig. 4.28 (a) and (b) depict the simulated detection probability for quadruple-threshold scheme versus the mid-threshold voltageV th4 forV th3 = 0:3 V and V th3 = 0:5 V, respectively, while N th = 3. In these simulations, V th1 and V th2 are set to 0.2 V and 1 V, correspondingly. On top of this curve, the detection probability for the dual-threshold case of V th1 V th3 (P D1 ), V th3 V th4 (P D2 ), and V th4 V th2 (P D3 ) are also shown. As intuitively expected, at any point theP D follows the minimum of P D1 , P D2 , and P D3 . Fig. 4.29 (a) shows the P D for dierent N th , 127 Figure 4.28: The simulated detection probability for the ramp signal in the quadruple-threshold scheme versus V th4 for (a) V th3 = 0:3 V, and (b) V th3 = 0:5 V; N th = 3, V th1 = 0:2 V, V th2 = 1 V, and N = 0:2. Figure 4.29: The simulated detection probability and number of false alarm in the quadruple-threshold scheme versus V th4 and dierent N th for the ramp signal; V th1 = 0:2 V, V th3 = 0:5 V, V th2 = 1 V, and N = 0:2. with V th1 = 0:2 V, V th3 = 0:5 V, and V th2 = 1 V; smaller one can achieve larger detection probability. Fig. 4.29 (b) illustrates the simulated number of false alarm in the quadruple-threshold scheme versus V th4 and dierent N th . We can see again largerN th can reduce false alarm signicantly, since it puts more restriction on the noise detection. The performance of the proposed level-crossing detector on representative other waveforms is shown next. Fig. 4.30 (a) shows the two simulated waveforms: one cycle of a sinusoidal signal and an exponential pulse signal. For these simulations, 128 Figure 4.30: (a) The waveforms for the one cycle of sinusoidal signal and exponential pulse signal, the simulated detection probability and false alarm versus N th for (b) one cycle of sinusoidal signal (V th1 =0:3 V, V th3 =0:5 V, and V th2 =0:7 V), and (c) exponential pulse signal (V th1 = 0:3 V, V th3 = 0:5 V, V th2 = 0:8 V), and N = 0:2 a random sequence of these waveforms with the added bandlimited white noise is applied to the detector. Fig. 4.30 (b) and (c) show the simulated detection probability and false alarm versus N th for the given threshold voltages for the sinusoidal and exponential signal, respectively. As before, larger N th decreases both detection and false alarm probability. Fig. 4.31 (a) and (b) show the simulated receiver operating characteristic (ROC) curve for dierent number of threshold levels (N ) andN th for the sinusoidal and ex- ponential signal, respectively. For both signals, the threshold voltages for dierent number of levels (N ) are summarized in Table 4.2. We can see that by increasing 129 Table 4.2: Threshold voltages used in the simulation for dierent number of paths Number of paths (N) One cycle of sinusoidal signal Exponential pulse signal 2 V th1 =0:3 V, V th2 =0:7 V V th1 = 0:3 V, V th2 = 0:8 V 3 V th1 =0:3 V,V th3 =0:5 V,V th2 = 0:7 V V th1 = 0:3 V,V th3 = 0:5 V,V th2 = 0:8 V 4 V th1 =0:3 V,V th3 =0:5 V,V th4 = 0:6 V, V th2 =0:7 V V th1 = 0:3 V,V th3 = 0:5 V,V th4 = 0:6 V, V th2 = 0:8 V N, the performance can improve and it is possible to get higher P D with smaller number of false alarm. Since correlators are the optimal detector, the performance of the level crossing detector is compared with the correlators. Since the position of the signals are not known a priori, a bank of correlators, with the shifted template signals, are required for the detection as shown before in Fig. 4.17. Fig. 4.32 (a) and (b) shows the simulated ROC curve for the bank of correlators with dierent number of paths for the template shifting (M ) and V th (applied to the output of the integrators) for the sinusoidal and exponential signal, respectively. On top of these graphs, the best performance of the level crossing detector (shown before in Fig. 4.31) is also plotted. We can see that the level crossing detector can achieve comparable performance with the optimal detector while its implementation can be much less power hungry, since it only requires digital circuitries and comparators which can be implemented as the dynamic comparators (will be shown in the next chapter), to reduce its power consumption even more. As the last example, the performance of level-crossing detector on detecting the action potentials is shown. For these simulations, a sequence of action potential 130 Figure 4.31: The simulated ROC curve for dierent number of levels (N ) andN th for (a) one cycle of sinusoidal signal, and (b) exponential pulse signal when N = 0:2. Figure 4.32: The simulated ROC curve for the bank of correlators with dierent number of paths for the template shifting (M ) and V th for (a) one cycle of sinu- soidal signal, and (b) exponential pulse signal, in comparison with the level crossing detector. 131 with dierent waveforms with the added lab-measured noise (includes both the gaussian noise and biological noise) is applied. The action potential and noise are measured before in the lab, shown in Fig. 4.33. The signal amplitude and N are 1 V and 0.2 V rms , respectively. When the signal is detected, a long pulse with a duration of 1.4 ms is generated. The threshold voltages are applied to the rst slope of the spike as discussed before in the wake-up receiver. Fig. 4.34 shows the simulated ROC curves for the dual, triple, and quadruple-threshold scheme for the corresponding spike waveforms. For these simulation, V th1 is kept constant at 0.3 V, determined by the MSE (which denes how close the signal to be awaken is to the original signal). The other threshold voltages (V th2 , V th3 , and V th4 ) and their corresponding pulse widths are varying as well as N th . We can see that by increasing N, the performance can improve and it is possible to get higher P D . It can also be concluded that adding more than 4 levels for a single slope does not improve the performance signicantly. 4.3.2 Nonidealities In addition to noise, other nonidealities of the detection circuitry aect the proba- bilities of correct detection and false alarm. The main nonidealities are the oset in the comparators and nonlinearity in the front-end ampliers. Comparator o- set essentially changes the levels of threshold voltages to unknown values, and as such degrades the accuracy of slope estimation (Fig. 4.35 (a)). To estimate how 132 Figure 4.33: Dierent waveforms of the spike and noise used in the simulation. 133 Figure 4.34: The simulated ROC curves for dierent number of paths, threshold voltages (V th2 , V th3 , and V th4 ), and N th ; V th1 = 0.3 V, for the corresponding spike waveforms shown in Fig. 4.33. oset aects the level-crossing detector performance, a simulation was performed. In this simulation, an oset is added to the V th1 in the dual-threshold scheme while V th2 = 1. Fig. 4.35 (b) shows the simulated probability of detection versus threshold-level oset in V th1 for two dierent values of V th1 . Given that the proposed scheme indicates a correct detection when the slope of the piecewise linear waveform is above as predetermined value, an increase in slope due to increase in the amplitude improves the probability of detection as shown before in Fig. 4.24. As shown in Fig. 4.9, there is always an amplier before the pre-proceeding circuitry which can be a power hungry block due to noise and linearity requirement. However, in the proposed detector, the robustness of the detector to the linearity of the amplication is an important feature of this detector. 134 Figure 4.35: (a) Eect of comparator oset on the timing error, and (b) the sim- ulated probability of detection versus threshold-level oset in V th1 in the dual- threshold scheme, while V th2 = 1. Fig. 4.36 illustrates how the linear and nonlinear amplier aects the level-crossing detector performance. We can see the detector output at both cases are equal. Therefore, the linearity of the preceding amplier is relaxed signicantly, since it only needs to be linear for the minimum signal amplitude (not the maximum); thus, smallerV DD andI DC can be used for the preceding amplier, leading to substantial power saving in the wake-up path. 4.4 Summary and Future Work Many signals in the nature, such as biological signals and specically the neural signals, have small information duty cycle. A clever scheme that only turns on and operates during the low duty cycle information signicantly reduces the power consumption. The main part of these systems is a signal-dependent robust and sensitive wake-up scheme. In this chapter, a new wake-up scheme, measuring slope 135 Figure 4.36: Eect of a linear and non-linear amplier on the output of the level crossing pre-processing. of the waveform through level-crossing detection is presented. Level crossing detec- tors consume small power, while providing high probability of detection with small number of false alarm. A unique feature of the proposed detector is the insensitivity to the nonlinearity of the preceding amplier resulting in a much reduced overall power consumption for the wake-up receiver. Future research utilizing similar de- tectors may lead to reduced sensitivity to the noise level of the preceding amplier through the application of the stochastic resonance, hence leading to even more power reduction. 136 Chapter 5 Implementation of the Multi-Channel Event Driven Neural Recording System In this chapter, the detail of the neural recording system will be shown. Compact size and low energy consumption requirement of implantable integrated solutions have led to innovations at the system and circuit design levels. In order to maintain low energy consumption, the system utilizes an activity-dependent scheme using the level-crossing detector shown in the previous chapter and other circuit innovations allowing for a low-voltage operation. 5.1 System Architecture As mentioned in the previous chapter, dual-chip system is a better solution for an implantable multi-electrode neural recording system. The block diagram of the front-end neural recording and signal conditioning chip to be directly mounted on 137 Figure 5.1: Block diagram of the multi-electrode neural recording and signal con- ditioning front-end chip. the multi-electrode neural probe, and a back-end wireless power harvesting and wireless telemetry chip to be inserted below the skin above the skull are shown in Fig. 5.1 and Fig. 5.2, respectively. The front-end chip consists of identical chains of Low Noise Ampliers (LNA) with event-driven activity-dependent power con- sumption, Successive Approximation Register Analog to Digital Converters (SAR ADC), and a digital multiplexer and serial link data organizer. In each channel, a low-power always-operating wake-up circuitry detects the onset of a neural activ- ity and sends a wake-up command to the front-end LNA and ADC. The detection part of the wake-up circuitry is based on the level-crossing scheme discussed in the previous chapter. The back-end chip consists of the power management unit, clock generation circuitry using crystal, uplink communication transmitter using a 138 Figure 5.2: Block diagram of the back-end wireless power harvesting and wireless telemetry chip. carrier-based 3-5 GHz Ultra-Wide Band (UWB) scheme, and downlink communi- cation receiver using Pulse Width Modulated (PWM) signal at 915 MHz. In the following sections, the detail schematic of all the blocks will be discussed. The chips have been implemented in a 130nm CMOS technology (Fig. 5.3). A 10-channel prototype is implemented to prove the concepts used in the front- end chip (number of channels are limited by the available chip area). Due to the time limitation imposed by available tape-out schedules, only the essential components of the back-end chip, specially, the dual-output DC-DC converter and UWB transmitter were taped-out. 5.2 Front-End Chip In this section, the detail of the front-end chip along with the design trade-os will be discussed. Each channel in the array can be congured in one of the two modes of 139 Figure 5.3: The microphotograph of (a) the 10-channel front-end, and (b) back-end chips. operation: raw mode where the signal at the electrode is continuously amplied and digitized, and activity-dependent mode where only portions of the input signal that contain information (as evaluated by the activity detection circuitry) are amplied and digitized. 5.2.1 Low-Noise Neural Amplier Front-end neural ampliers are critical building blocks in the implantable neural system. Low-power, low-noise and linear operation, stable DC interface with the electrode, and small silicon area are the main design specications of these am- pliers. Power dissipation is dictated by the input-referred thermal noise of the front-end amplier and the linearity of the last stage amplier. As stated in the previous chapter, the 50 - 500 V , 300 Hz - 10 kHz action potential is superim- posed on a DC oset as large as 50 mV. A key challenge in the design of a neural 140 Figure 5.4: Schematic of OTA-based neural signal amplier with capacitive feed- back along with its frequency response. signal acquisition chain is to separate this low frequency spike from the DC o- set. Fig. 5.4 shows the schematic of a common neural signal amplier that was rst described in [31]. The input is capacitively coupled through C 1 to remove the DC oset voltage from the electrode-tissue interface. Assuming an ideal Opera- tional Transconductance Amplier (OTA), the voltage transfer function is given by C 1 C 2 : 1sC 2 =Gm (1+ 1 sC 2 R 2 )(1+s C L C 1 GmC 2 ) . Therefore, the capacitive feedback network of C 1 and C 2 sets the midband gain of the amplier toA m = C 1 C 2 . Also,C 1 should be made much smaller than the electrode impedance to minimize signal attenuation. The resis- tanceR 2 in the feedback loop sets the low cuto frequency! L along with capacitor C 2 . Since ! L of the neural amplier should be a few hundred hertz, the required resistor value is large. MOS transistors biased in the triode region enable a more compact realization for this resistor as compared with various types of resistors that are available in a CMOS process [31]. The high cuto frequency ! H is set by G m , A m , andC L as Gm C L Am . If the noise contribution from R 2 is negligible, then the 141 output noise of the neural amplier will be dominated by the noise from the OTA. It can be easily shown that the noise of the amplier is V 2 n = ( C 1 +C 2 +C in C 1 ) 2 V 2 n;OTA ; (5.1) where V 2 n;OTA is the input-referred noise of the OTA. Dierent OTAs can be used in the amplier, some of which are shown in Fig. 5.5, oering trade-os for power consumption, noise, linearity, etc. The input-referred noise and voltage gain for the dierent OTAs are summarized in Table 5.1, assuming only the thermal noise for the devices. Similar expressions can be derived for the icker noise of the devices. As can be seen from this table, the inverter-based OTA has the lowest input- referred noise compared to the other topologies, with the same DC current. Since the current is shared between the NMOS and PMOS pair, the g m is doubled with the same current consumption. Also, it requires the minimum voltage headroom which make it suitable for low-voltage operation. However, this topology provides smaller gain compared to the other two with the same current consumption. In Table 5.1: Input-referred noise and gain in dierent OTAs Structure Input Referred Noise, V 2 n;OTA Gain Folded Cascode 16kT 3gm1 (1 + gm3 gm1 + gm9 gm1 ) g m1 [g m5 r o5 (r o1 jjr o3 )jjg m7 r o7 (r o7 jjr o9 )] Telescopic 16kT 3gm1 (1 + gm7 gm1 ) g m1 [g m3 r o1 r o3 jjg m5 r o5 r o7 ] Inverter Based 16kT 3 1 gm1+gm3 (g m1 +g m3 )(r o1 jjr o3 ) our design, the main signal path in each channel starts with three cascaded LNA 142 Figure 5.5: The schematic of the (A) folded cascode, (b) telescopic, and (c) inverter- based OTA. stages all based on a capacitive feedback scheme. Given the small signals levels at the very front-end prior to any amplication, the rst stage utilizes a 0.35 V supply and a relatively large current to ensure low-noise and modest linearity. The schematic of the rst stage amplier is shown in Fig. 5.6. The inverter-based OTA has been used since it can provide the lowest noise performance with small power consumption and low supply voltage. The input pair transistors have been biased in deep subthreshold, since that operation region provides the highest gm I D and therefore highest power eciency. The tail transistor device is biased in strong inversion to provide highest output impedance. Table 5.2 summarizes the device sizes and their corresponding operation region. The second stage amplier in the main path utilizes switched capacitors and switched resistors to enable gain and bandwidth (high-pass corner) programmability (Fig. 5.7), and a 0.7 V DC supply voltage since the signal amplitude is larger. A self-biased scheme is used as the OTA, since it provides high power eciency with 143 Figure 5.6: The detail schematic of the rst stage low noise amplier along with the OTA. Table 5.2: Devices geometries and DC operating points for the rst-stage of LNA Device W=L(m) I D (A) g m =I D (V 1 ) M 1 70=1 0.5 34 M 2 100=1 0.5 28 M 3 3=10 1 15 Feedback Transistors 0:36=10 0 N/A small noise contributions. The schematic of the third stage amplier in the main path is shown in Fig. 5.8. It is a two-stage amplier with Miller compensation, utilizing a self-biased as the rst stage following by a low-voltage active load with common-mode feedback. It has a 0.7 V DC supply voltage and large DC current to ensure linearity for the now-amplied signals. This third stage turns ON upon receiving the Wake-Up Signal (WUS) command from the neural activity detection circuitry. One important requirement for the third stage is having a short turn- on time. Output stage of the third amplier has signicant eect on the turn-on transient response of the amplier. The simplied schematic of this stage as well as its common-mode equivalent half-circuit schematic is shown in Fig. 5.9. AsI bias changes, the gate voltage at transistor M 9 changes; therefore, in order to study 144 Figure 5.7: The detail schematic of the second stage amplier in the main path. the frequency response of the circuit during turn-on transient, the transfer function from the gate of M 9 to the common mode output is derived as V out+ V in (s) = g m9 (1 +R G Cs) g m5 + (C m +C)s +R G C m Cs 2 : (5.2) If R G > (Cm+C) 2 4g m5 CmC , there will be two complex poles that cause peaking in the fre- quency response and ringing in the transient response. Fig. 5.10 shows the simu- lated frequency and transient response of the output stage for two dierent values of theR G . Large values ofR G while desirable in terms of the common-mode feedback (R G aects the open loop gain of the amplier), cause large ringing in the transient response. The schematic of the second and third stage ampliers in the wake-up path is shown in Fig. 5.11. They utilize a low-voltage active load with common-mode feedback. As shown in the previous chapter, the linearity of these ampliers in the wake-up path is signicantly relaxed; therefore, a 0.35 V DC supply voltage and 145 Figure 5.8: The detail schematic of the third stage amplier in the main path. Figure 5.9: The simplied schematic of the output stage of the third amplier along with its half circuit schematic. Figure 5.10: The eect of the gate resistance on the (a) frequency, and (b) transient response. 146 Figure 5.11: (a) The schematic of the second/third amplier in the wake-up path, the transistor sizing for (b) the second amplier, and (c) the third amplier. Figure 5.12: Measured and simulated frequency response of the three-stage LNA in the main path: (a) highest and lowest gain setting, and (b) highest and lowest high-pass corner setting. small DC current is used to reduce the power consumption signicantly. There is a source follower buer following the amplier for the measurement purpose. The measured and simulated frequency responses of the three-stage LNA in the main path, for the highest and lowest gain setting and high-pass corner frequency are shown in Fig. 5.12 (a) and (b), respectively. The achieved maximum and minimum midband gains are 57.7 dB and 51 dB, respectively, with a programmable -3 dB frequency bandwidth of 25250HzBW 3dB 9kHz: Fig. 5.13 (a) shows the input-referred noise of the amplier obtained by the output noise divided by the 147 midband gain. The measured total input-referred noise of the amplier integrated from 10 Hz to 10 kHz is equal to 4.7 V rms with a current consumption of 1 A drawn from a 0.35 V power supply, which results in a noise eciency factor of 1.9. Fig. 5.13 shows the measured Common-Mode Rejection Ratio (CMRR) of the amplier in the main path, where measured CMRR at 1 kHz is about 44 dB. The measurement transient response of the amplier in the main path upon receiving the WUS is shown in Fig. 5.14. The current of the third amplier is reduced from 680 nA when the WUS is 1, to 80 nA when the WUS is 0. The measured sinusoidal output signal for the amplier in the main and wake-up path at a frequency of 1 kHz is shown in Fig. 5.15 (a) and (b) for the 200 V and 1 mV peak-to-peak input signal, respectively. The measured THD for the amplier in the main path is 0.3% and 0.9%, while the measured THD for the amplier in the wake-up path is 1.3% and 12%, for 200 V PP and 1 mV PP , respectively. As mentioned in the previous chapter, using the level-crossing detector relaxes the linearity requirement of the preceding amplier. The measured and simulated frequency responses of the amplier in the wake-up path are shown in Fig. 5.16 (a), with a midband gain of 54.5 dB and -3 dB frequency bandwidth of 300HzBW 3dB 20kHz: Fig. 5.16 (b) shows the measured CMRR of the amplier in the wake-up path with about 38 dB CMRR at 1 kHz. Table 5.3 presents a summary of the results of the fabricated amplier and a comparison with the recently published works. In the comparison table, in addition to NEF, Power Eciency Factor (PEF) metric [62], dened as 148 Figure 5.13: Measured and simulated (a) input-referred noise, and (b) CMRR of the three-stage LNA in the main path. Table 5.3: Neural amplier performance summary and comparison with other works Ref. [102] [88] [108] [62] [55] [106] This Work V DD (V ) 2.8 3 1 0.5 1 1 0.35 and 0.7 Power (W ) 7 12.75 2.37 4 1.7 12.1 0.35 @ 0.35 + 0.57 @ 0.7 Max. Gain (dB) 40.85 73 60.09 30 60.5 40 57.7 Bandwidth (kHz) 5.32 5 5.1 10 7.8 10.5 9 Input Referred Noise (Vrms) 3.06 6.08 4 4.9 4.43 2.2 4.7 NEF 2.67 5.6 1.9 5.99 2.16 2.9 1.9 NEF 2 .V DD 19.96 94.08 3.61 17.96 4.66 8.41 1.27 THD 1% @ 0.8V PP N/A 1% @ 0.9V PP N/A 0.5% @ 0.9V PP 1% @ 0.1V PP 0.9% @ 0.76V PP CMRR (dB) 66 N/A 60 75 58 80 44 Process (CMOS) 0.5 m 0.35 m 0.18 m 65 nm 0.35 m 0.13 m 0.13 m PEF = NEF 2 :V DD which depends on the power rather than only current, is also shown for dierent ampliers. 5.2.2 Successive Approximation ADC (SAR) Implantable neural interfaces require ultra-low power Analog-to-Digital Converters (ADC). Among the dierent architectures for the ADC, charge redistribution SAR 149 Figure 5.14: (a) Input signal along with the generated WUS, and (b) measured transient response of the three-stage LNA in the main path upon receiving the WUS. Figure 5.15: Measured sinusoidal output signal for the ampliers in the main and wake-up paths at a frequency of 1 kHz for (a) 200 V , and (b) 1 mV peak-to-peak input signals. 150 Figure 5.16: (a) Measured and simulated frequency responses of the amplier in the wake-up path; (b) measured CMRR of the amplier in the wake-up path. ADC can have the lowest power consumption since it only consists of one compara- tor, a capacitor array, and logic circuitries, without requiring any opamp or linear blocks [59]. SAR ADC operates by performing a binary search until the code most closely corresponding to the sampled input voltage is found. The architecture of the fully dierential 9-bit, 20 kS/s SAR ADC, activated upon receiving the WUS command, is shown in Fig. 5.17. The ADC utilizes 0.7 V for the comparator and 0.35 V for other circuitries. Since the input signal full swing is about 0.7 V, the sample signal, generated by the control/timing circuitry, is boosted from 0.35 V to about 1 V by the voltage boosters, enabling low-distortion operation of the sample-and-hold circuitry for the 0.7 V input signal. Large area is a drawback of charge redistribution SAR ADCs as the total capacitance increases exponentially with the resolution. A common technique to minimize the area and power dissipa- tion is to use a split-capacitor array [26]. There is a direct trade-o between the power consumption and area of the Digital-to-Analog Converter (DAC) array and 151 Figure 5.17: (a) The detailed schematic of the SAR ADC, along with its timing diagram. its SNDR degradation due to the parasitic capacitance. The larger the capacitance is, the less sensitive the ADC is to the layout parasitic capacitance; however, the larger the area and power consumption would be. Also, linearity of the ADC relies heavily on the capacitor matching; the required matching for for 9-bit operation is about 2%, which denes the minimum capacitance size. Fig. 5.18 (a) shows the schematic of the capacitor array, serving both as the sampler capacitance and the capacitive DAC array to generate the comparison voltages. Each unit capacitor is implemented using a MIM (metal-insulator-metal) capacitor with a unit size of 80 fF as a direct trade-o between chip area and SNDR degradation as determined through post-layout simulations. It can be easily shown that for the two-stage ca- pacitor array with B L and B M bits for the LSB and MSB arrays respectively, the required series coupling capacitor is given by C split = 2 B L C 2 B L C 1 : (5.3) 152 Figure 5.18: (a) Sampler and the capacitive DAC, and (b) layout of the DAC. The split-capacitor value of 85 fF was determined through post-layout simulation. In order to have good capacitor matching, unit capacitors are used to implement the array and common-centroid layout techniques are applied. The layout of the capacitance array with switches are shown in Fig. 5.18 (b). There are also dummy capacitors around the array to provide better matching. During the sampling phase, the dierential input voltage is sampled on top plate of the the MSB array. For low power consumption, a fully dynamic comparator is used (Fig. 5.19) [37]. Except the leakage current, no other static current is consumed after the decision is made. The size of the input pair transistor is dened following the guidelines shown in [72] for reducing the input-referred noise. Based on [72], decreasing the input pair overdrive voltage during the initial transient period and increasing capacitance on the drain node of the input pair are the most eective means of reducing the input-referred noise. As stated before, the input signal peak-to-peak swing is 0.7 V, 153 Figure 5.19: The schematic of the dynamic comparator. while the generated sample signal is 0.35 V. In order to have a linear operation of the sampler, the sample signal is boosted to approximately 1.1 V. The schematic of the multi-stage voltage booster is shown in Fig. 5.20 (a). One degrading factor in decreasing the boosted voltage value is the parasitic capacitance at the output node of each unit cell. One way is to increase the number of the cascade stages as well as increasing the capacitance size. The capacitance used in the booster for the sample signal is implemented by a MIM capacitor with the value of 350 fF. There is also a voltage booster for the clear signal which increases the the clear signal from 0.35 V to 0.85 V. This capacitance is also implemented by a MIM capacitor with the value of 150 fF. The RC extracted simulation result of the voltage booster both for the sample and clear signals is shown in Fig. 5.20 (b). The RC extracted simulated SNDR of the sampler with the boosters are shown in Fig. 5.21 for the sampling frequency of 20 kS/s and input frequency of 0.927 and 9.213 kHz, respectively. The SNDR in the worst case is larger than 58 dB which is enough to support 9-bit 154 Figure 5.20: (a) The schematic of the voltage booster, and (b) the extracted simu- lation of the booster. Figure 5.21: Simulated RC extracted sampler with booster at (a) 927 Hz, and (b) 9.213 kHz, while the sampling frequency is 20 kS/s. 155 Figure 5.22: (a) The schematic of the successive approximation register (SAR), and (b) the synthesized control circuitry. operation of the SAR ADC. The schematic of the successive approximation register and the synthesized control circuitry are shown in Fig. 5.22 (a) and (b), respectively. The input signals to the control circuitry are CLK and WUS. The control circuitry generates the CLK SAR only if the WUS is one; otherwise CLK SAR signal is zero, means there is no sampling and ADC is o. At the end of conversion, the End of Conversion (EOC) signal is generated where at its falling edge, the generated digital output is transferred to the output buer. The digital output buer data of all the channels are serialized by the digital multiplexer and a data packet is generated by adding a 9-bit header to the serial data. The schematic and layout of the synthesized serializer are shown in Fig. 5.23. Fig. 5.24 shows the simulated ADC SNDR at 0.927 and 9.213 kHz, before and after RC extraction. Based on these results, the RC-extracted ADC has an ENOB of 7.6 bit. 156 Figure 5.23: Synthesized serializer and digital data organizer. Figure 5.24: Simulated ADC performance (a) at 927 Hz (schematic), (b) at 9.213 kHz (schematic), (c) at 927 Hz (RC extracted), and (d) at 9.213 kHz (RC extracted), all in the typical corner. 157 Due to a problem in the timing in the control circuitry and successive approx- imation register, the fabricated ADC did not work in the lab. The problem is explained next. Fig. 5.25 (a) and (b) show a section of the successive approxima- tion register which has the timing issue, along with the a representative simulation results of the circuitry. As the SET signal goes low, it makes S 0 low. In the next rising edge of the clock,S 1 becomes low; in each rising edge of the clock, this zero is propagating to the end of the chain. In all other corners, the simulated waveforms in the schematic view is the same. Fig. 5.25 (c) shows the RC extracted simulated waveforms in the typical corner, which shows the correct operation of the circuitry. However, the RC extracted view of the circuitry in the FS and FF corners does not work properly. Fig. 5.25 (d) shows the RC extracted simulated waveforms in the FS corner along with its zoomed view. As the SET signal goes low, S 0 becomes low; however, S 1 also becomes low which should have happened in the next rising edge of the clock. This happens because in the extracted view the clock edge slows down more than the SET signal, since it has larger parasitic loading. This problem propagates to the end of the chain. In order to prevent this problem, the SET signal should come after the rising edge of the clock; basically, it needs a little amount of the delay (which could be easily generated by a few inverters). Since both of these signals are generated by the synthesized control circuitry, they are synchronous to each other and no delay can be generated between them. 158 Figure 5.25: (a) A section of the SAR which has timing problem, the simulated waveforms in the SAR in the (b) TT corner (schematic), (c) TT corner (RC ex- tracted), (d) FS corner (RC extracted) along with the zoomed-view version (the solid line are none-extracted while the dashed line are RC extracted). 159 5.2.3 Precision Rectier The recorded action potential can have either positive or negative peak signal. Therefore, a precision rectier is required preceding of the level crossing detector. The schematic of a conventional precision rectier (half-wave) is shown in Fig. 5.26 (a). In order to have a low power consumption, all the blocks in the wake-up re- ceiver path are designed to work with theV DD of 0.35 V. However, the conventional rectier does not work properly at this low voltage. In the negative cycle, D 1 is o whileD 1 is on andV out isR 2 =R 1 V in . The opamp output voltage isV D2 +R 2 =R 1 V in where V in is negative; so, the opamp output voltage is larger than a voltage drop across the diode which is a dicult condition to have when theV DD is 0.35 V. The proposed rectier is shown in Fig. 5.26 (b) which is a direct implementation of the mathematical description of rectication: when the dierential input is positive, the output equals the input signal; however, when the dierential input is nega- tive, the output equals to the negative of the input (by connecting the switches to the opposite side). A representative simulation of the circuitry is also shown in this gure. We can see that there is no voltage drop in the output since the voltage drop across the switches are zero. The detail schematic of the comparator is shown in Fig. 5.27 (a). It utilizes a fully dynamic comparator to minimize the power consumption. It also has a dynamic oset cancellation where the successive approximation algorithm is used to add the required amount of capacitance auto- matically during the calibration phase. First, all the capacitances are set to zero; 160 Figure 5.26: (a) The conventional precision rectier (half-wave), and (b) the pro- posed rectier with a representative simulation. if one side is stronger than the other side, then binary-weighted capacitances are added automatically by the SAR to the stronger side to slow it down and cancel the oset. The measurement setup for the rectier along with a representative measure- ment demonstrating functionality of the precision rectier are shown in Fig. 5.28 (a) and (b), respectively. We can see that the timer output is generated at almost the same positive and negative voltage of the input signal. 5.2.4 Level-Crossing Detector As stated in the previous chapter, the level crossing detector can provide a high probability of detection while keeping the number of false alarm small, in addition to providing small MSE for the action potential signal when it is woken up. The schematic of the level crossing detector is shown in Fig. 5.29. In this implementa- tion, four threshold levels are used. The timer circuitry responds on the rising edge 161 Figure 5.27: (a) The schematic of the comparator with oset cancellation used in the rectier. Figure 5.28: (a) The measurement setup, and (b) a representative measurement demonstrating functionality of the precision rectier. 162 Figure 5.29: The schematic of the level crossing detector. of comparator output. The output of the level-crossing detector is OR-gated with the short pulses generated by the timer (pulse 14 ), so that the main path starts recording from the beginning of the action potential. The schematic of the com- parator is shown in Fig. 5.30. A dual-input fully dynamic comparator is used to reduce the power consumption. One input senses the dierential input signal and the other input senses the dierential threshold voltage. The threshold voltages are set by a resistive ladder, where a 4-bit decoder selects the required threshold volt- age. As mentioned in the previous chapter, one source of the error in the detection can be the relative oset among dierent comparators. The same oset cancellation mechanism as the one shown before is used to reduce the oset automatically. A 5-bit switched-capacitor bank is used for the dynamic oset cancellation, where the 163 Figure 5.30: The schematic of the comparator with oset cancellation in the rectier with threshold variation. capacitance are implemented using MOS capacitances. Fig. 5.31 shows the sim- ulated comparator output and oset voltage before and after oset cancellation, where the variance of the oset is reduced from approximately 10 mV to around 1 mV. The schematic of the timer circuitry is shown in Fig. 5.32 where the pulse width can be set by a 7-bit XOR-based comparator. The timer circuitry is followed by the edge counter which counts the correct transition of the edges (Fig. 5.33 (a)). Based on that, the decision circuitry decides whether there is a spike or not, and therefore generates the long WUS or not (Fig. 5.33 (b)). The threshold for the de- cision can be set by a 2-bit XOR-based comparator (since there are 4 levels). If the spike is detected, a long WUS is generated by the WUS generation circuitry shown in Fig. 5.33 (c) which is similar to the timer circuitry except it can generate longer pulse width. The width of the WUS can be set by a 4-bit XOR-based comparator. The measured output of the variable pulse width timer circuitry for the dif- ferent bits is shown Fig. 5.34. The measurement setup along with representative 164 measurement demonstrating functionality of the oset cancellation circuitry are shown in Fig. 5.35 (a) and (b), respectively. It can be observed that before oset cancellation, each of the four comparator triggers at a dierent input signal value for the same setting of the threshold voltage; however, after oset cancellation is activated, the four comparators trigger at almost the same input signal value. Fig. 5.36 shows the measurement results for the functionality of the whole wake-up re- ceiver, including its ampliers, precision rectier, and level-crossing detector. The WUS is shown on top of the input signal for the lowest desirable SNR (the ratio of the peak amplitude to N is about 4), demonstrating the functionality of the wake-up receiver for dierent number of threshold levels N and N th . An example of the long and short false alarm along with the detected and missed spike are shown on each gure. For this measurement, the lab-measured noise is added to an action potential signal, recorded before in the lab. The characterization of the wake-up receiver in terms of the probability of detection ad false alarm is shown in the system measurement results. 5.3 Back-End Chip The detailed schematic of the back-end chip is shown in Fig. 5.2, including the power management unit, clock generation circuitry, and uplink/downlink commu- nication circuitries. In the following sections, the detail of each part will be covered. 165 Figure 5.31: A representative simulation demonstrating functionality of the oset cancellation circuitry: the comparator output and the voltage oset (a) before, and (b) after oset cancellation. Figure 5.32: The schematic of the variable pulse width timer circuitry. 166 Figure 5.33: (a) Edge Counter, (b) decision circuitry, and (c) the WUS generation. Figure 5.34: The measured output of the variable pulse width timer circuitry for the (a) 3-bit MSB variations and (b) 4-bit LSB variation. 167 Figure 5.35: (a) The measurement setup, and (b) a representative measurement demonstrating functionality of the oset cancellation circuitry. 5.3.1 Power Management Unit The main duty for the Power Management Unit (PMU) is to provide a stable supply for the front-end chip and other circuitries in the back-end chip. In order to have continuous operation, one way is to support continuous wireless power transmis- sion mostly done through near-eld inductive coupling [51]. However, this method can be sensitive to the misalignment between the transmission and reception coils, which leads to an unreliable energy source and system operation. Another possible solution for providing power is to include a wirelessly rechargeable battery. The system takes its energy from the battery for the most part; it can also receive the required energy wirelessly if the battery is discharged. Table 5.4 shows the charac- teristic of dierent rechargeable (secondary) battery. In this work, a 1.2 V NiMH 168 Figure 5.36: (a) The measurement setup, and representative measurement demon- strating functionality of the wake-up receiver with level-crossing detector for (b) N = 2, (c) N = 3 with N th = 1 and 2, and (d) N = 4 with N th = 2 and 3. 169 Figure 5.37: the block diagram of the wireless battery charger. rechargeable battery is considered, since it does not contain any toxic material while it provides the lowest nominal voltage [12]. As stated before, the front-end chip is designed for the V DD of 0.35 V and 0.7 V. Since the battery voltage is 1.2 V, in order to have high eciency power conversion, a switching regulators including a dual-output switched-capacitor DC-DC converter is used, converting 1.2 V to approximately 0.8 V and 0.4 V, followed by two Low-Dropout (LDO) regulators which provides a clean, stable 0.7 V and 0.35 V V DD for the front-end chip. So, the PMU consists of wireless battery charger circuitries, DC-DC converters, LDOs and bandgap circuitry (Fig. 5.2 (b)). Table 5.4: Comparison of dierent rechargeable batteries NiCd NiMH Li-ion/Li-ion Polymer Gravimetric Energy Density (Wh/kg) 45-80 60-120 100-160 Volumetric Energy Density (Wh/l) 50-150 140-300 270-300 Cell Voltage (nominal) 1.2 V 1.2 V 3.6 V 170 Figure 5.38: The rectier and the matching circuitry along with it simulation results for V rect = 1.5 V and I dc = 2.2 mA. 5.3.1.1 Wireless Battery Charger The block diagram of the wireless battery charger is shown in Fig. 5.37. It starts with an antenna and a rectier. Higher frequency results in smaller antenna size at the expense of increased propagation path loss both in the air and body. In this work, the 900 MHz ISM band is selected for the power delivery, as a compromise between the antenna size and path loss. An example of a miniature antenna at this frequency is shown in [19]. As stated in Chapter 2, between two common rectiers, voltage doubler and self-synchronous rectier, the former can provide higher power eciency at larger output voltage and current. So, the rectier used in the system is a one-stage voltage doubler with an input impedance matching circuitry (Fig. 5.38). From the simulations, the rectier eciency is approximately 60% (at V rect = 1.5 V and I dc = 2.2 mA) while the total eciency at 915 MHz including the loss of the on-chip impedance matching circuitry is 33%. A 250 pF MIM capacitor is used as the storage element. The rectier is followed by the battery charger circuitry. Each type of a battery requires a specic prole for 171 charging. Some (such as NiMH batteries) require to charge with a Constant Current (CC) source ; others (such as Li-ion batteries) may require to an initial charge with a constant current followed by a Constant Voltage (CV) source. An important point regarding the battery is that it should not be over charged or it will be damaged. In NiMH batteries, after the voltage reaches a certain voltage, the charging should be stopped. This mechanism is controlled by the charging control circuitry. There is also a battery-status circuitry which detects when the battery voltage drops below a certain threshold voltage and thus requesting external power to be wirelessly delivered to charge the battery. The schematic of the battery charger is shown in Fig. 5.39 (a). It includes a temperature-constant current generation based on the one reported in [4]. The opamp sets the two voltages V 1 and V 2 equal. Therefore, I 3 current which is the addition of I 1 and I 2 is given by I 3 = V T lnN R 1 + V BE R 2 ; (5.4) whereR 1 andR 2 are 34k and 978k , respectively. Therefore, by settingR 1 ,R 2 , and N, I 3 can be set to be temperature-independent. This current is mirrored to the main charging transistorM 3 . One important point to be considered is that the charger should work properly at any initial voltage of the battery. For instance, there are transient situations during charging whereV rect is smaller than theV BAT . In this case, the bulk junction diode can turn on and draw signicant current, not lettingV BAT increase. In order to prevent this situation, the bulk voltage should be 172 connected to the largest potential ofV rect andV BAT . Therefore, the dynamic body- bias control transistors connect the bulk potential automatically to the highest potential ofV rect andV BAT . The same technique has been used for the gate voltage of transistorM C . The charging control circuitry (Fig. 5.39 (b)) monitors the charge and discharge of the battery voltage so it is not overcharged or undercharged. It has two comparators and compares the battery voltage with 1.2 V and 1.4 V; whenever it is larger than 1.4 V, it disconnects the battery from the transistorM C and when it drops below 1.2 V, it connects the battery to theM C . The battery-status circuitry (Fig. 5.39 (c)) monitors the battery voltage (not during the charging/discharging) and when it drops below 1.2 V, it activates a signal to request for the wireless power. Fig. 5.40 (a) shows the complete simulation of the battery charger versus initial voltage of the battery changes from 0 - 1.2 V. Simulated transient voltages at various nodes are shown in Fig. 5.40 (b). 5.3.1.2 Dual Output DC-DC Converter As stated before, the 1.2 V voltage supplied by the battery must be converted to 0.8 V and 0.4 V voltages as needed by various circuits in the system. There are two types of the switching supply regulators: switched-capacitor and switched- inductor. Switched-capacitor regulators are more appropriate for the low power application while consuming smaller area. The schematic of the step down DC-DC converter for 1 3 and 2 3 division is shown in Fig. 5.41 (a) and (b), respectively [76]. 173 Figure 5.39: The schematic of the (a) battery charger, (b) charging control circuitry, and (c) battery-status circuitry. Figure 5.40: The complete simulation of the battery charger (a) versus initial volt- age on the battery, and (b) dierent voltage node: red is RC-extracted and blue is original. 174 Figure 5.41: The schematic of the step down switched-capacitor DC-DC converter for (a) V DD1 = 1 3 V DD , and (b) V DD2 = 2 3 V DD . The following analysis shows how the circuitry can generate the scaled voltage of the input. The analysis is to be shown for the 2 3 division. The same can be done for the 1 3 division. In phase 1 of the operation, the charge transfer capacitors C are connected in parallel with each other. Therefore, the load voltage V L is charged to V L = 2C 2C+C L in the rst cycle. In phase 2 , charge transfer capacitors C are connected in series with each other. By writing the charge equation and considering charge conservation property, the load voltage at the end of the rst operation cycle V L;1 is V L;1 = 6C L C (2C +C L )(C + 2C L ) V DD : (5.5) If we repeat the same process for the second cycle, at the end of phase 2 , the load voltage V L;2 is V L;2 =V L;1 [1 + 2(C L C) 2 (2C +C L )(C + 2C L ) ]: (5.6) If we repeat the procedure for cycle n, the load voltage at cycle n is given by 175 Figure 5.42: The schematic of the capacitance sharing dual output DC-DC con- verter. V L;n =V L;1 [1 + 2(C L C) 2 (2C +C L )(C + 2C L ) +::: + ( 2(C L C) 2 (2C +C L )(C + 2C L ) ) n1 ]: (5.7) As the number of cycles goes to innity, the output voltage asymptotically reaches a steady-state voltage given by: lim n!+1 V L;n = V L;1 1 2(C L C) 2 (2C+C L )(C+2C L ) = 6C L C (2C+C L )(C+2C L ) V DD 1 2(C L C) 2 (2C+C L )(C+2C L ) = 2 3 V DD : (5.8) Now, in order to reduce the number of capacitance and therefore area, the two capacitances ofC are shared between the two converters by time multiplexing their non-overlapping control signals, as shown in Fig. 5.42. The schematic of the 4-phase non-overlapping clock generation circuitry is shown in Fig. 5.43. 176 Figure 5.43: The schematic of the 4-phase non-overlapping clock generation cir- cuitry. Fig. 5.44 (a) shows the measurement setup for the DC-DC converter. The charge sharing and output capacitors are implemented with a 100 nF o-chip ca- pacitors. Potentiometers, R 1 and R 2 , are placed at both outputs of the of the circuitry to represent the variable load. The input clock frequency is set to 500 kHz. Fig. 5.44 (b) shows the measured power eciency versus R 1 and R 2 . In this graph, the power consumption of the non-overlapping clock generation circuitry is also considered. The proposed DC-DC converter can achieve an eciency higher than 80% over the load variation, or the total output power variation of about 10-80 W . The variation of the output voltageV DD1 andV DD2 versusR 1 andR 2 are also shown in Fig. 5.44 (c) and (d), respectively. The V DD1 and V DD2 are close to 0.4 V and 0.8 V over the load variation. 177 Figure 5.44: (a) The measurement setup, the measured (b) power eciency, (c) V DD1 , and (d) V DD2 versus R 1 and R 2 . Figure 5.45: The schematic of the (a) 0.7 V LDO, (b) the two-stage opamp, and (c) simplied small-signal model with the desired position of the poles and zeros. 178 5.3.1.3 LDO and Bandgap The voltage generated by the DC-DC converters is given to linear voltage regulators to provide a clean, stable DC supply. Since the voltage should convert from 0.8 V to 0.7 V and from 0.4 V to 0.35 V, the drop-out across the regulators should be small, requiring Low Dropout Regulators (LDO). The schematic of the 0.7 V LDO using a two-stage opamp, along with the small-signal model and the desired positions of the poles and zeros are shown in Fig. 5.45. Based on the small-signal model, the open loop transfer function is given by V out V in (s) = g m1 r o1 g m2 r o2 g mp (r o kR L )(1 + s !z ) (1 + s ! P1 )(1 + s ! P2 )(1 + s ! PL )(1 + s ! PZ ) ; (5.9) where ! PZ = C Z (r o1 +r Z ) , ! z = 1 C Z r Z , ! PL = 1 C L (rokR L ) , ! P 1 = 1 C P1 r o1 , and ! P 2 = 1 C P2 r o2 (C P 2 = C gd g mp (r o kR L )). Since the LDO provides the power for the ampliers in the main path, which turns on and o as controlled by the WUS, the LDO output load current is variable. The LDO must be stable throughout all the load current variations. The output pole ! PL varies as the output load current (hence r o1 ) vary making the stabilization dicult. C Z and variable resistorr Z , implemented by the MOS transistor M Z , are added to create a variable pole ! PZ and a zero ! Z for compensation [15]. By properly choosing C Z and r Z , ! PZ can be made to be the dominant pole (Fig. 5.45 (c)). The variation of Power Supply Rejection (PSR), transient response, and open-loop phase margin and unity-gain frequency versus 179 Figure 5.46: The variation of (a) Power Supply Rejection (PSR), (b) transient responde, and (c) open-loop phase margin and unity-gain frequency versus load resistance R L . load resistance R L are shown in Fig. 5.46. The phase margin is better than 45 , for all the load values. The schematic of the 0.35 V LDO using a self-biased opamp is shown in Fig. 5.47. The LDO should convert 0.4 V to 0.35 V; so, its dropout voltage has to be very small. Thus, the bulk of the PMOS transistor is connected to ground to reduce its threshold voltage and the voltage drop. Since the PMOS source voltage is less than 0.5 V (the maximum V DD is 1.5 V and DC-DC converter generates one-third of that which is 0.5 V), the PN bulk junction diode will not turn on. The variation of PSR and open-loop phase margin and unity-gain frequency versus load resistance R L are shown in Fig. 5.47 (c) and (d), respectively. 180 Figure 5.47: The schematic of the (a) 0.35 V LDO, (b) the self-biased opamp, and the variation of (b) PSR, (c) open-loop phase margin and unity-gain frequency versus load resistance R L . Figure 5.48: The schematic of the 0.35 V and 0.7 V bandgap circuitry. 181 Figure 5.49: (a) The transient response of the bandgap, the variation of the bandgap voltage versus (b) temperature, and (c) V BAT . 182 In order to have a stable DC reference voltage for the LDOs, a bandgap circuitry is required. However, the conventional bandgap circuitry generates 1.2 V voltage [77]. The sub 1-V bandgap circuitry reported in [4] is used and shown in Fig. 5.48, where the bandgap current given by Eq. 5.4 is mirrored to the output resistance to generate the required voltage. A binary-weighted switched resistor bank is used to calibrate any process and mismatch variation. The reset circuitry for the bandgap circuitry is shown. The transient response of the bandgap voltage and dierent node voltages are depicted in Fig. 5.49 (a); the variation of the bandgap voltage versus temperature and V BAT is also shown in Fig. 5.49 (b) and (c), respectively. 5.3.2 Clock Generation Circuitry A clock generation circuitry generates the required clock for the front-end chip. Crystal oscillators provide both short term (phase noise) and long term drift stabil- ity. The schematic of the proposed Crystal Oscillator (XO), incorporating dynamic current consumption, is shown in Fig. 5.50 (a). The XO core uses an inverter-based Pierce oscillator. At small amplitudes, the inverter transconductanceg m is set high to ensure fast and reliable start-up. With increasing amplitude, g m is decreased by reducing the current until the amplitude saturates at a relatively small value to have a low power consumption. The XO-core is followed by a buer and two inverters that converts the dierential output to a single-ended rail-to-rail signal 183 Figure 5.50: The schematic of the (a) proposed clock generation circuitry, (b) the crystal oscillator, (c) the amplier and rectier. without signicantly aecting the phase noise. The amplitude is sensed by the rec- tier; if it is larger than a ceratin thresholdV th1 , the current of the Pierce oscillator is decreased; if it is smaller than a ceratin thresholdV th2 , then the oscillator current is increased. The negative resistance provided by the inverter amplier is gm ! 2 C 1 C 2 which should cancel the loss of crystal. The transient response of the circuitry and dierent voltage nodes, both for the satisfying the start-up condition and when it is not satised, are shown in Fig. 5.51 184 Figure 5.51: The transient response and dierent voltage nodes of the clock gener- ation circuitry when start-up condition (a) is satised, (b) not satised. 5.3.3 Uplink/Downlink Communication The proposed neural system has a dual-band operation for the communication. For the power and downlink data communication, the ISM band of 915 MHz is used. Higher frequency can reduce the antenna size and thus the system size but increases the propagation loss both in the air and in the body. For the downlink data com- munication, the Pulse Width Modulation (PWM) is used. In the neural recording system, the downlink data rate is very low as it consists of control signals. On the other hand, the uplink data rate is very high as it consists of the digitized version of the captured signals (e.g., 18 Mb/s for a 100-channel system). IR-UWB commu- nication is a popular choice for low-power, short range, high data rate system. In this work, a carrier-based UWB in 3.1 - 5 GHz band is used. 185 5.3.3.1 UWB Transmitter The schematic of the UWB transmitter is shown in Fig. 5.52. For low power consumption, a digital ring oscillator whose current sources are turned ON and OFF by the information bit sequence, generates a narrow pulsed-sinusoids. The width of each information bit is reduced in a digital circuitry to less than 1 ns enabling creation of UWB pulses. The output is ac-coupled to an o-chip mm- size UWB lter to create the narrow pulsed-sinusoids. The center frequency of the UWB signal is set by the ring oscillator frequency which is controlled by its bias currentI bias . The bandwidth of the UWB signal is set by the impulse width which can be controlled by V ctrl as it changes the resistance and hence the delay in the digital path. Fig. 5.53 (a) shows the measurement setup for the UWB transmitter. As stated above, there is an o-chip 3-5 GHz band-pass lter at the output of the transmitter to generate the pulsed-sinusoidal signal. Fig. 5.53 (b) shows a representative tran- sient waveform of the transmitter, while Fig. 5.53 (c) depicts the average power consumption of the transmitter versus data rate. It can be seen that the power consumption of this UWB transmitter is approximately linearly proportional to the data rate. In other words, the power consumption of the transmitter is also activity dependent. 186 Figure 5.52: The schematic of the UWB transmitter. Figure 5.53: (a) The measurement setup, the measured (b) transient waveform, (c) power consumption versus data rate. 187 Figure 5.54: The schematic of the (a) envelope detector, and (b) PWM demodula- tor. Figure 5.55: A representative simulation for envelope detector and PWM demodu- lator for (a) bit 0, and (b) bit 1. 5.3.3.2 PWM-ASK Demodulation The downlink communication consists of an envelope detector, followed by the PWM demodulator. The envelope detector is a cascade of several stages of the voltage doubler using diode-connected transistors, followed by two inverters (Fig. 5.54 (a)). The PWM demodulator is similar to the one previously reported in Chapter 2 (Fig. 5.54 (b)). Representative simulations for the combinations of the envelope detector and PWM demodulator for bits 0 and 1 are shown in Fig. 5.55. 188 5.4 System Measurement Results In the previous sections, the measurement result of each block is presented. In this section, the system measurement results are shown. The measurement setup of a complete system is shown Fig. 5.56. As mentioned before, unfortunately the ADC did not work. So, the measured data from the output of the amplier and also the WUS is fed into the ADC and serilizer in the Spectre simulator. Then, the generated digital serial data is given to the UWB transmitter (the digital data is loaded into the arbitrary waveform generator). The input signal which is a pre-recorded neural and the measure WUS are shown in Fig. 5.57 (a) and (b), respectively. The correct WUS as well as the short false alarm can be clearly seen in the gure. The reconstructed data captured in the raw mode and activity-dependent mode are shown in Fig. 5.57 (c). When the WUS is zero, as mentioned before the ADC is o (the ADC clock signal is zero), demonstrating the activity-dependent data generation. The output of UWB transmitter in the raw mode and activity-dependant mode are also shown in Fig. 5.57 (a) and (b), respectively. To characterize the wake-up receiver in term of probability of detection and false alarm, a sequence of action potential with the added lab-measured noise is applied to circuitry (Fig. 5.58 (a)). When the spike is detected, a long pulse with a duration of 1.5 ms is generated. The threshold voltages are applied to the rst slope of the spike as discussed before. Fig. 5.58 (b) shows the measured region of 189 Figure 5.56: The measurement setup of a complete system. Figure 5.57: (a) The pre-recorded neural data, (b) the measured WUS, (c) the reconstructed output of the ADC in the raw mode and activity-dependant mode (wake-up mode) along with its zoomed-view version, the output of UWB transmit- ter in the (d) raw mode, and (e) activity-dependant mode. 190 operation graph for dierent number of pathsN andN th . The measured probability of detection versus the input amplitude for dierent settings are shown in Fig. 5.58 (c). It can be seen that although the preceding ampliers are nonlinear, but as input SNR increases, the probability of detection increases since larger amplitude signal possess larger slope which causes less timing error in crossing a certain threshold, as shown in the previous chapter. Based on this threshold setting, the measured MSE and correlation coecient for the captured spike in the wake-up mode is shown in Fig. 5.59 (a). The correlation coecient is dened as = n X i=1 V i;spike : ^ V i;spike s n X i=1 V 2 i;spike n X i=1 ^ V 2 i;spike ; (5.10) where V i;spike and ^ V i;spike are the samples of the original signal and the woken-up signal. It can be seen that the correlation between the spikes in the raw mode and wake-up mode is better than 97 %. The measured ON duration versus spike ring rate is shown in Fig. 5.59 (b). This data is obtained based on the DC current variation of the third amplier in the main path as it turns on and o by the WUS. The measured result compares the case when WUS is always 1, when the wake-up receiver is activated for the noiseless case (so the number of false alarm is zero), and for the noisy case (the same input signal used in the measurement of Fig. 5.58) for N = 4 and N th = 2, since it has the highest probability of detection and also more false alarm compared to other cases. It can be seen that considering all the 191 Figure 5.58: (a) The measurement setup, the measured (b) ROC curve for dierent number of paths N and N th , and (c) probability of detection versus the input amplitude. short and long false alarm, the activity-dependent blocks are ON is less than 25% of the time in the maximum ring rate. Fig. 5.60 shows the power breakdown of the overall neural recording system in the raw mode, and activity-dependent mode assuming maximum and minimum ring rate (based on the ON duration of the activity-dependant blocks shown in Fig. 5.59 (b)). In these graphs, the simulated value for the ADC and serializer power consumption is considered. Compared to the raw mode, the wake-up mode reduces the total system power by about 50% in the average and improves the system power eciency signicantly. Table 5.5 summarizes the measured performance of this scheme with selected published multi-channel neural recording CMOS chips. It can be seen the proposed scheme achieves the lowest power/channel with comparable performance to other chips. 192 Figure 5.59: The measured (a) correlation coecient and MSE versus input ampli- tude, and (b) ON duration versus spike ring rate. Figure 5.60: Power breakdown of the overall neural recording system in (a) raw mode, wake-up mode when all the channels have the (b) maximum, and (c) mini- mum ring rate. 193 Table 5.5: Performance summary in comparison with other neural implant chips 194 5.5 Summary and Future Work The limited source of the energy in implanted systems motivates extremely low- power compact circuitry. In this chapter, an activity-dependent even-driven power consumption scheme using the level-crossing detector and other circuit innovations allowing for a low-voltage operation are utilized to realize a low-power neural record- ing integrated circuit chipset. Specically, having a dual power supply for the amplier in the main path and also ADC, the novel level-crossing detector which relaxes the linearity of the preceding amplier, the new low-voltage precision recti- er and voltage booster in the ADC led to better performance compared with state of the art. Future work includes implementation and fabrication of other blocks in the system, in addition to xing the problems in the blocks such as the ADC block, and measurements in emulated and realistic environments (in-vivo and in-vitro). Also, removing the wire between the two chips and using wireless scheme for data communication and power delivery between them is a possible future direction, since as there are many undesired issues with such wires. 195 Chapter 6 Conclusion Advancements in electronics has enabled emergence of new applications such as multi-function handsets, implantable biomedical devices, and low-power compact sensors nodes. This thesis presented architectures and integrated circuits for the re- alization of low power implantable biomedical devices, specically for neural record- ing systems, and wirelessly-powered battery-less systems (such as RFID tags). 6.1 Summary In the rst part of the thesis, the concept of dynamic energy storage is introduced to enable the extended operation of wirelessly-powered battery-less systems at very low input power levels. In the proposed scheme, the extra received power be- yond the sensitivity level is stored and later used to enhance the sensitivity of the wireless sensor. As a proof of concept, an integrated wirelessly-powered passive transponder with dynamic energy storage mechanism and sensitivity enhancement 196 is demonstrated in a 0.13 m CMOS technology. Moreover, a passive frequency downconverter, using memoryless nonlinearity, is introduced that can be especially useful for mm-wave power harvesting. Its characteristics were studied analytically, and veried through simulation and measurements of a low-frequency discrete pro- totype and a 12 GHz integrated version realized in a 0.13 m CMOS technology. The second part of thesis, was focused on the design and implementation of the biomedical implanted devices, in particular the design of low power neural recording circuitry. A new activity-dependant architecture utilizing level-crossing detector was presented to enable a low-energy system. Also, new circuit techniques were shown to enable the operation of the system at low supply voltages. A proof of concept prototype is demonstrated in a 0.13 m CMOS technology. 6.2 Future Work The investigations that have formed this thesis have opened up several topics for fu- ture research. In the context of the wirelessly power harvesting, the future research can be focused on the increasing the eciency of the power harvester systems by de- creasing theV in;th while reducingC in;th by investigating new topologies and devices for the rectiers. Another relevant and challenging research area is ecient energy extraction from the existing ambient radio frequency signals which typically have small voltage amplitudes, but are present for long periods of time (e.g., broadcast signals). Since the rectiers have a dead zone, a passive way to lower down this 197 barrier can be an interesting area for future research. Another are is developing new schemes for ecient mm-wave power harvesting systems based on CMOS only solutions. With respect to the neural recording systems, implementing a reliable system with small size and power that can work continuously for a long period of time is an open area of the research. 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Figure .3 shows the small signal g m for the same device size versus the V DS for dierent values of V GS . The exponential behavior in the subthreshold operation region is shown in Fig. .4, in addition tog m /I D for the same device size. Figure .5 shows thef T versus the drain current for the same device size. Figure .6 shows the NF min versus frequency for various values of the current. The above mentioned simulations are performed on the devices with RF layout. 208 Figure .1: Metal stack for the CMOS 8RF process. Figure .2: Drain current versus V DS for dierent values of V GS for an NMOS of width 10 1 m and minimum channel length. 209 Figure .3: Transconductance versus V DS for dierent values of V GS for an NMOS of width 10 1 m and minimum channel length. Figure .4: (a) Drain current versus V GS , (b) transconductance versus V GS , and (c) the ratio of g m /I D versus drain current for an NMOS of width 10 1 m and minimum channel length. V DS is kept at 1.5V. 210 Figure .5: f T vs. drain current for an NMOS of width 10 1 m and minimum channel length. V DS is kept at 1.5V. Figure .6: NF min vs. frequency for dierent drain currents for an NMOS of width 10 1 m and minimum channel length. V DS is kept at 1.5V. 211
Abstract (if available)
Abstract
The thesis presents system level and block level integrated circuit solutions for low power wirelessly powered passive sensors, specifically biomedical implants and RFID systems. The concept of dynamic energy storage is introduced enabling an extended operation of battery‐less systems wirelessly powered. Also, a novel passive subharmonic generation and frequency downconversion method, using a memory‐less nonlinear circuit coupled to a linear passive resonator, to transfer the energy from a high frequency signal to a lower frequency without requiring any DC power supply. Also, new event‐driven scheme as well as several low‐voltage design techniques is proposed to reduce the energy consumption of neural implants.
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Asset Metadata
Creator
Safarian, Zahra
(author)
Core Title
Energy aware integrated circuits for communication and biomedical applications
School
Viterbi School of Engineering
Degree
Doctor of Philosophy
Degree Program
Electrical Engineering
Publication Date
05/07/2014
Defense Date
02/18/2014
Publisher
University of Southern California
(original),
University of Southern California. Libraries
(digital)
Tag
biomedical application,CMOS,energy harvesting,event detection,frequency conversion,frequency divider,low power,neural recording system,nonlinear circuits,OAI-PMH Harvest,oscillators,passive transponder,rectifier,RF identification (RFID),subharmonic generation
Format
application/pdf
(imt)
Language
English
Contributor
Electronically uploaded by the author
(provenance)
Advisor
Hashemi, Hossein (
committee chair
), Chen, Mike (
committee member
), Choma, John, Jr. (
committee member
), Ortega, Antonio K. (
committee member
), Weiland, James D. (
committee member
)
Creator Email
zsafaria@usc.edu
Permanent Link (DOI)
https://doi.org/10.25549/usctheses-c3-412271
Unique identifier
UC11288036
Identifier
etd-SafarianZa-2500.pdf (filename),usctheses-c3-412271 (legacy record id)
Legacy Identifier
etd-SafarianZa-2500.pdf
Dmrecord
412271
Document Type
Dissertation
Format
application/pdf (imt)
Rights
Safarian, Zahra
Type
texts
Source
University of Southern California
(contributing entity),
University of Southern California Dissertations and Theses
(collection)
Access Conditions
The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...
Repository Name
University of Southern California Digital Library
Repository Location
USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA
Tags
biomedical application
CMOS
energy harvesting
event detection
frequency conversion
frequency divider
low power
neural recording system
nonlinear circuits
oscillators
passive transponder
rectifier
RF identification (RFID)
subharmonic generation