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Modeling the reliability of highly scaled field-programmable gate arrays in ionizing radiation

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Modeling the reliability of highly scaled field-programmable gate arrays in ionizing radiation

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MODELING THE RELIABILITY OF HIGHLY
SCALED FIELD-PROGRAMMABLE GATE
ARRAYS IN IONIZING RADIATION

BY D AVID L EE

A DISS ERT A T ION PRES E N TED TO T H E
F ACULTY O F TH E GRADUATE S CHO O L
U NIVERSITY OF S OUT H ERN CALIFO R NIA
IN PART I AL FULFI LL ME NT OF THE REQUIREM E N TS
FOR THE DE GREE OF
DOCT O R OF PHILOSOPH Y
COMPUTER E NGINEERING

M AY 2016

2

A CKNOWLEDG E MENTS
I’d like t o express my deepes t gra t itude to a n umber of p eople who have
helped me over the last several years; I would never have compl eted t his
work witho ut their hel p or guidance!
First, I would like to sincerely thank my advisor, Dr. Jeffrey Draper. I could
not have completed this work without his guidance to bridge my deeply‐
rooted e ng ineerin g m indset into t he w orld o f scient i fic theory. I am also
grat eful t o my disser t atio n and qualifier c o mmittee m e mbers, D r . Viktor
Prasanna, Dr. Aiichiro N akano, D r. S and eep G upta, and Dr. Alice Parker, for
their v alua ble feedback a nd s ugg e stio ns w hich h elped guide my r esea rch
path.
I would also like to extend a special thank you to my managemen t and
colleagues at work: William Perea, Tom Trodden, Dr. Heidi Ruff ne r, a nd J ohn
Vonderheid e, a long w ith T. B er n a det t e Mon t ano, J effr ey K alb, a n d Stev en
Greene, for helping support my efforts to return to school. On a similar note,
I’d also like to acknowledge and thank my employer, Sandia Nati onal
Laboratories, and their Doctoral S tudy P rog r am f or p roviding s u ch g reat
education a l opportunit ies to r e tur n to school.
Through this journey, I’ve had the fortune of being able to collaborate with
some o f the grea tes t p eople in t he r adia tion e ffects c ommunity. In particular,
I would like to extend a special thank you to Dr. Michael Wirth lin of B righam
Young Un iv ersity, Dr. Gary S w i ft o f Swift Eng i neerin g a n d Radia tion S erv i ces,
and Dr. Gregory Allen of N ASA’s Jet Propulsion L aboratory, a ll of whom

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provided i nvaluable t i me, resour ces, a nd a n occasional a ll‐nigh te r at t e s t
facilities t hat helped make this r es earch possible.
Finally, I’m most g rateful for my f amily and t h eir u nwav ering support. I
want to extend a special appreciation to my father, Kyong, and mother,
Okchu, f or t heir i nsp i rat i on i n pursuing m y Ph.D. and for r a is i ng m e to
appreciate the values of hard work and humility. Thank you to my brother
Jae and his wife Julanie, and their children Jonathan, Janelle, and Julian, and
my sister Hae‐Jung a nd h er h usband P atr i c k , and their children, M adelin e
and Keegan, for all of the const an t encouragement over the year s. Most of all,
my sincerest thanks goes to my wife, Kristina; no matter what, she wa s
always there for me to lean on whenever I needed it (which beca me q u i te
often near the end!) – I am forever indebted for her steadfast support a nd
unconditio nal patienc e and und er stand i ng!

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T ABLE OF C ONTENTS

List of Figu res ............................................... ............................................................... ................. 8
List of Tables ................................................ ............................................................... ................ 11
Abstract ...................................................... ............................................................... .................... 12
Chapter 1 ..................................................... ............................................................... .................. 15
1.1 Introductio n .................................................. ............................................................ 15
1.2 Motivation .................................................... .............................................................. 16
1.3 Contributions ................................................. ........................................................... 22
1.4 Outline ....................................................... ............................................................... ... 24
Chapter 2 ..................................................... ............................................................... .................. 26
2.1 Ionizing Radiation and Electronic Circuits ................ ........................................ 26
2.2 Sources of Ionizing Radiation ............................. ..................................................... 26
2.3 Ionizing Radiation E ffects in C MOS ........................ ............................................... 30
2.3.1 Total Ionizing Dose ..................................... ......................................................... 32
2.3.2 Destructive Single Event Effects ........................ ............................................. 34
2.3.3 Non‐Destructive S i ngle Event Effects .................... ...................................... 35
Chapter 3 ..................................................... ............................................................... .................. 39
3.1 Inv e st ig atin g the Ra diat ion Response of 20 and 28 nm FPGAs ................ 39
3.2 Devic e s Under Test ........................................ .............................................................. 40
3.3 Ion Beam Characteristics .................................. ......................................................... 43
3.4 SEU Test Procedure ........................................ ............................................................. 4 4
3.5 SEL Test Procedure ........................................ .............................................................. 46

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3.6 Results ................................................... ............................................................... ............. 47
3.6.1 28 nm Kintex‐7 S E U Results .............................. .............................................. 48
3.6.2 20 nm Kintex UltraScale SEU R esults ..................... ...................................... 49
3.6.3 Kintex‐7 SEL Results .................................... ....................................................... 52
3.6.4 New S E U Responses Observed in 28 nm and 20 nm FPGAs ..... ......... 56
Chapter 4 ..................................................... ............................................................... .................. 57
4.1 Identifying Physical ly Adj acent Multiple‐Cell Upsets ...... ............................. 57
4.2 Memory Organization ....................................... .......................................................... 58
4.3 Prior Work ................................................ ............................................................... ........ 61
4.4 MCU and MBU Extraction Technique .......................... ......................................... 62
4.4.1 Collec t ing SEU Data ..................................... ......................................................... 62
4.4.2 Identifying Upset Pair Offsets .......................... ................................................ 64
4.4.3 Create Physical Adjacency M o del ......................... ......................................... 66
4.4.4 MCU and MBU Extraction .................................. ................................................ 67
4.5 Validation of the Ph ysical Adjac ency Model ................ ...................................... 69
4.5.1 Co incident Single‐ Bit Upsets ............................ ................................................ 69
4.5.2 Val i dation with Physical Layout ......................... ............................................ 72
4.6 MCU Results for 28 nm SRAM‐Based FPGA ..................... .................................. 73
4.6.1 Obtaining SE U Data ...................................... ........................................................ 73
4.6.2 Creating the Physical Adjacency Model ................... ................................... 74
4.6.3 Extrac ting Device MCUs .................................. ................................................... 75
4.6.4 MBU Data Analysis ....................................... ........................................................ 78
4.6.5 MCUs a nd Technology Scaling.............................. ........................................... 79
4.7 Summa ry ................................................... ............................................................... ......... 81

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Chapter 5 ..................................................... ............................................................... .................. 83
5.1 Measuring Sensitive Volumes with Rotational Dependence......... ....... 83
5.2 Prior Work .................................................... ............................................................. 8 5
5.3 Proposed Technique ............................................ .................................................. 86
5.3.1 Data C ollection with Rotational Dependence .............. ............................. 87
5.3.2 Algorithmic Derivation .................................. ..................................................... 88
5.4 Example Application ........................................... ................................................... 93
5.4.1 Applic ation o f the M easurement Technique ................ ............................. 94
5.4.2 Effects of Measurement on S p ace Rate E stimates .......... ........................ 95
5.5 Summary ....................................................... .............................................................. 96
Chapter 6 ..................................................... ............................................................... .................. 97
6.1 A Failure Estimatio n M odel Inc orporating Angular Effects ...... ........... 97
6.2 Difficulties in Accurate R ate Prediction ...................... .................................. 99
6.2.1 Effective LET ........................................... ............................................................... . 99
6.2.2 Multiple‐Cell Upsets .................................... ..................................................... 102
6.3 Event Fault Model Generatio n .................................. ...................................... 105
6.3.1 Angular Experimental Data Collection .................... ................................. 106
6.3.2 Conversion to Event Rates ............................... .............................................. 110
6.3.3 Extrapolation and Inte rpolation of Missing Data ......... ....................... 111
6.3.4 Averaging of I nterpolated Data .......................... ......................................... 114
6.4 Error Rate E stimation on 28 nm FPGA Devic e .................... .................... 115
6.5 Summary ....................................................... ........................................................... 119

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Chapter 7 ..................................................... ............................................................... ............... 120
7.1 Summary ....................................................... ........................................................... 120
7.2 Implications of this Research ................................. ......................................... 122
7.3 Potential Future Paths ........................................ ............................................... 123
Acronyms ...................................................... ............................................................... ............. 126
Referenc es .................................................... ............................................................... .............. 127

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L IST OF F IGURES
Figure 1: Comparison o f common satellite orbits ............... ....................................... 28
Figure 2: I llustration o f Van All e n Belts s u rrounding t he
Earth, r esul ting i n belt s of t r a pped electron s (outer b elt) a nd
protons (inner belt) .......................................... ............................................................... ........ 29
Figure 3: Direct i o n ization from h eavy ion s t rikes vs. indirect
ionizatio n from nuclear collisions ............................ ......................................................... 31
Figure 4: Illustration of potential SEL path through parasitic
BJTs formed between well and substrate ........................ .............................................. 35
Figure 5: A schematic v iew o f how SEE‐induced current p ulse
translates i nto a voltage pulse in a C MOS inverter ............ ........................................ 37
Figure 6: Thickness measurement of o n e p repared K i nt ex
UltraScale D UT ................................................ ............................................................... ............ 42
Figure 7: Kintex U ltraScale test bo a rd with DUT mounted ....... ............................. 42
Figure 8: Orientation of tilt (  T ) and rotation (  R ) for ion
strikes into a sensitive v olume of silicon .................... .................................................... 44
Figure 9: Test setup at Texas A&M C yclotron F acility .......... .................................... 47
Figure 10: Weibull cur v e for Kintex‐7 c onfig u ration m emory
cell upsets ................................................... ............................................................... ................... 49
Figure 1 1 : Weibull curve for UltraScal e c onfigur a tion
memory cell upsets ............................................ ............................................................... ....... 50
Figure 12: W eibull fits f or X ilinx configu r atio n memory
scaling Xilinx Virtex‐II throug h Xilinx UltraScale devic e s .... ................................... 51
Figure 13: Current strip chart dur ing SEL testing of Kintex‐7 . ............................. 53
Figure 1 4 : W eibull curve for cu r r ent‐st ep e vents observed
during SEL testing ............................................ ............................................................... ......... 55
Figure 15: S a mple of MCU events m apped pictorally ............. .................................. 56

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Figure 16: 5‐bit Multi‐Cell Upse t within i nterleaved f ram e s ... .............................. 60
Figure 17: Two MBUs visible to th e user ....................... ................................................. 60
Figure 18: F P GA upset c oordinate s ystem and upset labeling .... .......................... 64
Figure 19: Probability of a CSEU as a function of the
percentage o f the array that has SCUs ......................... .................................................... 71
Figure 20: H istogram o f coincid e nt S BUs per tr ial when
vary ing the total percentag e of the device bits that is upset . ................................ 72
Figure 21: Occurrence of upset offset pairs ................... ............................................... 74
Figure 22: Highest pro b ability upset pairs (frame offset) ..... ................................. 75
Figure 23: MCU siz e s as a p ercentage of t he t otal o bserved
MCUs as a function of L E T ..................................... ............................................................... . 77
Figure 24: MBU sizes as a p ercentage of t he t otal o bserved
MBUs as a function of L E T ..................................... ............................................................... 79
Figure 25: MCU ev ents a s a percentag e o f SEUs f or f iv e Xilinx
FPGA families ................................................. ............................................................... .............. 81
Figure 26: An example of tilted DRAM irradiation with
varying ro tation a ngles ....................................... ............................................................... .... 84
Figure 27: Chang e in c r oss‐sectio n based on ion perspective ... ........................... 89
Figure 28: C alculation o f effec t ive cross‐ section for an
angular ion strike ............................................ ............................................................... ........... 91
Figure 29: R otation an gle depend ence o f the cross sectio n of
a 28 nm SRAM‐based FPGA ....................................... ........................................................ 101
Figure 30: Layout c haracteristics c ausing dependenc e on  R
for ion s t rik e s when  T > 0 .......................................................... ...................................... 103
Figure 31: Relativ e M CU p rev a lence with r espect t o tilt a nd
rotation ...................................................... ............................................................... .................. 104
Figure 3 2: Reduced test m atri x after consider ation of
symmetry ...................................................... ............................................................... ............. 109

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Figure 33: polynomial f it u sed to i nterpolate a nd e xtrap o late
cross‐sectio n as a func t ion of  T at a fixed  R ........................................................... 11 3
Figure 3 4 : A l in ear fit used t o int e rpolate c r oss‐section as a
function of  R for fixed values of  T .............................................................. ................ 114

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L IST OF T ABLE S
Table 1: Sample orbital dose rates ............................ ........................................................ 33
Table 2: Scaling fits and rate calculations ................... ................................................... 51
Table 3: Co mparison o f validatio n ............................. ....................................................... 73
Table 4: Percentage of MCU shap es extracted for each ion ...... .............................. 76
Table 5: Summary of angular study with 10 M e V/u Xenon ......... .......................... 93
Table 6: Raw data f or angular modeling study .................. ....................................... 117
Table 7: Predicted on‐o rbit error rate estimates .............. ....................................... 118

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A BSTRACT
Space processin g t echnologies e nable numerous c apabilities t ha t have
become pervasive in modern culture. As our reliance on this te chnolog y
grows, so does t he d esir e for g r eat e r on‐o rbit p roces sing to e n able n e w
capabilities. F ield‐Pro g rammable Gate A rr a y s (FPGAs) have p lay ed a key
role i n ful f illing spac e p rocess ing n eeds ; h owever, c u rrent spa ce‐grade
FPGAs are built using processes that a re n ow f our generations out of date. In
order to e n a ble the levels o f on‐orbit p rocessing desired b y fu ture m issions,
one possibility i s to f l y c ommercial‐grade FPGAs built with s ta te‐ o f‐the‐art
processes. However, c ommercial FPGAs are not designed t o opera te i n the
harsh space en viro n m ent. I n particular, there is o n e k ey e nv ir onmental
concern that must be addressed: the response of these devices i n the
presenc e of ioniz i ng r a diat i on.
Ionizing r a diat i on i nd uces singl e‐event effects (SEE) i n CMOS through
unwant ed c harge dep o sition w h i ch c auses a range of i ssues, the most
prominent of which is single‐event upset (SEU). Current proces ses fo r
quantifying the response o f devi ces to S EU w ere developed when te chn ology
nodes were almost an order of magnitude larger. Thus, existing approaches
to m odel o n‐orbit upset rates must b e validated for modern t ech nol o gy n ode
sizes for r e liability est i mates to a pply. W hen this r esea rch i nves tig a ted the
SEE response of modern technology node FPGAs in ionizing radiat ion, t wo

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new mechanisms o f up set were o bserved that m ust be c onsidered t o obtai n
accurate on‐orbit upset rates: a non‐trivial prevalence of mul tiple‐ce ll upset
(MCU) and a strong r otat ional depend enc e t hat is n ot a ccounted for by
exis tin g ra t e est i matio n tools.
MCU is caused when a SEU affects multiple physically adjacent c ells. I n
FPGAs constructed wit h 28 nm f eature siz es a nd smaller, the inc idence o f
MCU has r e ached non‐triv ial lev e ls o f prevalence. S ince M CU i s not factored
in e x i st ing rate p r e d i ction tool s, MCU e v e nts must b e ident i fie d and
accounted for before p erforming rate c alculations. H owever, id ent i fy ing
MCU is n ot stra i ghtfor ward a s th e physical a djacency o f memory cells i s
obfuscated b y the no n‐linea r , interleaved mapping o f these bits into the
device’s l o g ical a ddress space. A methodology is p ro posed to g enerat e a
stat istical adjacency model that identifies physically adjacent c ells a nd,
subsequently, MCU ev ents. T his methodology is v alidated t o d e r iv e the
physical adjacency of S R AM‐based memory cells with as little as 2% error.
A strong rotational or azimuthal dependency was also observed w hen
modern F PGAs w ere irradiat ed a t non‐normal i ncident angles, an artifact
creat e d by shrink i ng f ea ture s iz e a n d the fact t hat th e dimension s of t he
device v olume that i s sensit iv e to i o n iz ing r a diation are no l o nger
extr aordina r ily long a nd w id e c o mpared t o their d epth. T his re search
levera ges t h is a ngular i nfo r matio n t o measu r e the appr oximate d imensions
of the sensitive volume. The measured approximation of the sen sitive
volume can then be fed back into rate prediction tools to impro ve a ccuracy
by about 17%.

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The final component of the resea rc h present e d here formulates a new error
model that i dentifies and collaps es M CU c lusters into s ingle ev ents a nd
compensat e s fo r a n gular effects in o rder t o o b tain a n omnidir e c tio n al e vent‐
based fault model of t he d evice. T his approach c ompensates f or both MCU
and rotational effects, and provides a model that can be combin ed w ith
standard rate prediction tools to obtain on‐orbit failure rate estimates with
accuracies improved by a facto r of three.
This r es ea r c h ultimately e nables t he a ccurate p redict ion of o n‐ orbit error
rates – a k e y st ep i n forming the foundat i on t o using c o mmercia l FPGAs in
space. A s a consequence of shrink i ng t echnol ogy nodes, i t is a lso important
to observe the changing paradigm in which upsets occur. For eq uivalent
numbers of m emory cells, a dev i ce c onstructed w ith la rg er t echn ology nodes
will have bit upsets spread out over some period of time. Howe ver, s maller
technology n ode dev i ces demon strat e a longer p erio d of t ime bet ween
even ts, but with u psets now occurring i n a “bursty” f ashion w ith a relatively
high potential for multiple cells to be affected simultaneously from a single
ion strike. This fact is particularly important for designers looking to
mitigate SEU effects, as the effectiveness of current SECDED ECC protectio n ,
triple m odular r edundancy, a nd o ther m itigat ions a p p roaches cur rently
utilized ma y be severel y compromised.

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C HAPTER 1
1.1 I NTRODUCTION
Technology advancem ent is t ypic ally a ssociated w ith Moore’s law which
states that transistor count in an i ntegrated circuit should r o ugh l y double
ever y two years [1]. I n g e neral, c ommercial electro n ics have b een able t o
achieve ad vancement at t his rat e ; however , space‐based e lectron ics have
exper i enced hindered g rowth due to c ostly and time‐c onsuming m e asures
that a r e n ecessary t o qualify elect r onics for th e harsh spa c e e nv ironment [2].
This f ac t has limited the availability o f current s p a ce‐qualifi ed devic e
offer i ng s d e spite the g r owing n e ed f or m ore advanc ed s atellit e cap a bilities.
In p art i cular, o ne c lass o f processing dev ice – the Field‐P r ogr ammable Gate
Array (FPGA) – plays a key role in numerous space missions; however,
current space‐qualified FPGAs are built with technology processes a t least
four g ener a t ions b ehin d the current stat e ‐of‐t h e‐art [3, 4]. A s such, modern
space FPGAs have sign i fica ntly l ower p er for m ance a nd c apability compared
to commercially available devices. One possible approach to cl ose this
“technology gap” is to use cutting‐edge commercial FPGAs in spa ce, but

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certa i n r e liability facto r s must be addressed before th e space community will
accept commercial devices as a viable option for flight.
One of those reliability factors forms the foundation of this res earc h: t he
ioniz i ng r a diat i on p resent i n space causes single event effects (SEE) through
unwant ed c harge depo sition i nto the FPGA silicon [5]. A k ey r oad block to
pushing cutting‐ed g e c o mmercial de vice s into sp a ce syste m s is t hat the space
community has relativ e ly l ittle ex perience w ith SEE in m odern‐s cale d evices.
Feature size s caling c auses skew ed m easurements when c haracteri zing S EE
with c lassic a l approaches, affect ing the ability to a ccuratel y predict o n ‐orbit
device reliability. The following chapters introduce new techn iq ues and
processes t h at m it igat e the effect s of f eatur e s iz e sc aling whe n evaluating
SEE on F PGAs, thus i mproving t he f idel ity of devic e characteriz ati on an d
increasing the accuracy of on‐orbit reliability prediction. Th ese
improvements w ill provide v i ta l informat ion for sys t em desig ner s to
properly architect space systems utilizing commercial FPGA devices, and
help close the technology gap an d broaden future on‐orbit capab ilities.
1.2 M OTIVATIO N
SEE may result in a wide array of both destructive and non‐dest ructive
effects tha t c an h ave consequences f rom single‐event u pset ( SEU ) which
changes the stored value of memory cells, up to single‐event la tch‐up ( SEL)
which can cause a sh ort circuit and often destructio n of t he d e vice [ 6].
Chapter 2 provides a background on these effects and their mech anis ms.

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As SEE has an increasing impact o n semiconductor circuits a s a result o f
fea t ure s i ze s caling [ 7], trad it ional approaches d o not pr operl y quantify t h e
SEE respon se f or d ev ices b uilt w it h leading‐edge f eatur e s izes. Accurate rate
predict i ons are para mount for design ers to p roperly design s yst ems to
appropriate levels of reliability. Systems should neither be under‐
constrained , t hus failing before e xpec ted, n or o ver‐constrained ,
unnecess ar ily incr eas i ng c ost an d taxing t h e l imited a vailable size, weight,
and power.
Accelera ted testing of devices u sin g t errestr i al i onizing ra dia tion s ources t o
model on‐o rbit f ailure r ates i s a common pr actice. H owever, th e devices
used by the space community employ much larger transistor feature siz es
than those used in modern FPGAs. The current state‐of‐the‐art feature size
for space‐qualified C MOS devic e s in p roduction is c urrently t he 65 nm
technology n ode, w ith 45 nm t echnology nod e d ev ice o f ferings co ming s oon.
Research that has looked at characterizing SEE response in smal l nanometer
devices (fo r t he p urp o ses of t hi s res e arch, 30 nm f eature s ize o r l ess) i s
sparse, and processes have n ot m atured b eyond thos e utilized f o r older
generation devices. For that maturation to occur, a better und erstanding o f
SEE on small nanometer dev i ces is n eeded ; to t hat end, t his res earch first
seeks to d et ermin e :

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What are the mechanisms that differ for modern nanoscale devices in
the presence of ionizing radiation when compared to previous
generations of larger ‐scale devices?
The inv e stigatio n that h elped answer t his questio n i s described in Chapter
3 and led to c haracter izat ion studies o f this w ork’s exemplars, two SRAM‐
based FPGA devic es d esig ned by X ilinx, I nc. T he dev ices c harac t e ri ze d we re
the Kint ex‐ 7 F PGA, a device with 28 nm f ea ture siz es, and the K i n te x
UltraScale FPGA, utilizing 20 nm feature sizes. Upon investiga tion o f the
device r esp o nse in b ot h the 28 nm a nd 20 nm device families, n e w effects
were observed that invalidated the use of existing failure rate m odels used t o
predict th e device upset rat e in sp e cific space o r bits.
One of the effects first noted in 28 nm was an increased, non‐t riv i al
prevalence o f multiple‐cell upset (MCU). M CU o ccurs w hen a singl e ion i zin g
particle s tr ike trav els through the sens itiv e charge c ollection nodes of
multiple d ata bits, caus ing them a ll to c hange t h eir s t a te a nd “upset.” MCU is
not nec e ss arily a new effect a s it h as b een observed t o small d egrees i n
previous g enera t ion technology n odes. H owever, at 28 nm t echno logy n odes
and below, the prevalence of MCU is significant enough that it must b e
accounted for in order to obtain accurate failure rate estimates. These
observat ion s led to the following s ubsequent questions:
How can MCU be detected in modern devices, especially when data bits
physically adjacent on the die may be interleaved across a device’s

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logical memory address space? Also, to what degree does MCU inflate
the failure rate and error predictions in small feature technology nodes?
These questions motiv a ted the ex aminat ion of u pset m emory cells to try
and identify the independent ion izing strikes that c aused each cluster of
upsets. However, the identification of MCU can be a challengin g tas k
especially w hen device l ayout informat ion is n ot a vailable, as it may be
difficult to t ell which cells a re p hysically a djacent to e ach other. The
difficulty i s exacerbated for devices that utilize bit interlea ving, wh ich may
map physically a djacent bits o n t h e silicon t o d iffer e nt l ogica l words in t h e
device’s m emory address space. T his required t he d evelopment o f a new
statistical methodology to i dent ify MCU without prior knowled g e of the
device layout or the physical‐to‐logical memory mapping. This process is
described in Chapter 4.
Though s ome comple x modeling t echniques could possi bly be e mplo yed to
properly account for MCU effects, such models would require Mon te C arlo
techniques [8] o r are sig n ifican tly more c omplex t han standa rd
methodologies; a more p r a ctical a pproach i s to s implify dat a a n alysis b y
quantifying ionizing particle strike events (rather than the st andard p ractice
of counting individual upset bits) in order to utilize simpler modeling
techniques. In order to calculate accurate failure rate predicti on s i n t he
pr esenc e of non‐ trivi a l MC U rat e s i n a tract ab l e fash i on , t h e MCU events must
be extr acted from the d ata s e t ob t a in ed from radia t ion c h aracte rization.

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It is important to note that MCU is not the only new effect tha t was
observed t hat must b e accounted for in o rd er t o accur a tely e st i mate f ailure
rates. Another observation was a strong rotational dependency which
affected ionizing strikes that occurred at angle, suggesting th at r elative
dimensio ns o f sensit iv e volumes no l onger differ b y orders o f m agnitude a s
they d id i n older technology n odes. I n particular, the angular r es ponse is
now distinct enough to provide some in formatio n about the relat iv e
dimensio ns o f the sensit ive vol u me. T his fact i n spired the fol lowing
question:
What different characteristics are exhibited by angular ionizing
radiation events in small geometry devices, and can these
characteristics be leveraged to gain more information about the
dimensions of the sensitive volume?
The sensitive volume dimensio n s are important to o btain, a s mod els such
as CREME96 [9] and SPENVIS [10] utilize this information as par t of t heir
orbital rat e estima t ion models. In general, older dev ice geometries w ere able
to i gnor e t h e effects o f r ota t ion a s sens i tive v olumes w ere suf f i ciently large
enough that rotation of the angle of incidence of an ion strike would only
minimally a ffec t t he o bserved sens itiv e cross‐section of t he de vice. A s such,
larger‐featu re‐sized sensit i ve r eg ions c ould b e grossly ap proxi mated without
affecting ra te p redic t io n. H owever, in m oder n geometr i es, the length, width,
and depth of sensitive volumes appear to be on similar scales and the single‐

21

even t upset (SEU) response o f the device c an depend g r eatly on the angle a t
which the ionizing event occurs. Chapter 5 presents a methodol ogy that c an
levera ge t h i s rotat i ona l dependen c e in o rder t o derive a n appro ximation o f
the sensitiv e volume’s dimensio n s , p roviding g rea t er a cc uracy t han current
practices fo r dimens io nal approximation.
Finally, the predictio n o f operational failur e in o rbit i s of p aramount
importance to spacecraft designers. The culmination of the afo rem e nt ioned
changes in a devic e’s ionizing rad iation r espo nse ra ises t he qu estion :
How can a model be constructed to accurately predict failure rates for
modern ‐scale geometry devices?
Having accurate models is necessary to avoid over‐designing a s ys tem to
protect ag a i nst SEE (th u s impartin g higher c o sts a nd d esign tim e), or w orse,
to a void u nder‐designin g a s ystem wh ere lifetim e e xp ectat i ons are
unrealis tica lly high.
This r esear c h proposes a n ew f a i lure m odel i n Chapt e r 6 tha t p r o v ides
more accurate estimation of the failure rate of modern scale de vices in spac e
environments. E xisting classica l character i zat i on m ethodologie s do n ot
properly account for MCU effects and are based off of data obta ined f rom
normal i nc idenc e i r r a diat i on stu dies. A s modern sc a le dev ices have
demonstrated t hat they e xhibit stron g rota tion a l de p ende n c e , t h e sensitiv e
volume m ust be e valuated f rom multiple a ngles in o rder t o accou nt f or
angular dependenc ies. F urthermore, in o lder t echnolog y nodes, an upset bit

22

in t he dev ice used t o correlat e dir ectly to a single ion ev ent; modern devices
now exh i bit non‐tr iv ia l MCU r a t e s and this a ssumption c an n o lo nger b e
made. T echniques that i den t ify indiv i dua l i onizing even ts ( through t he
identification of MCU) transform traditional per‐bit upset data i nt o even t‐
based dat a t hat evaluates the ov erall dev i c e susceptib ility to ion strikes.
Formulating an e vent‐ b ased d at a set, c ombined with a dj ustments fo r angular
effects and rotat i onal depend e nc y, c rea t es t he f oundat ion for a new model
that c an b e used w ith exist i ng spac e e rror r a te e stimat ion tool s. T his model
improves the accuracy of rate predictions obtained with modern scale
devices, which would otherwise b e under‐repo rted by conventiona l m e ans.
1.3 C ONTRIBUTIONS
This diss e rt ation prov ides the foll o wing cont r ibutions:
 Quantified the effects of device scaling on the static bit erro r rate o f
commercial 20 nm and 28 nm SRAM‐based FPGAs when exposed to
ioniz i ng rad iation [11, 12].
 Developed a novel methodology to i dent ify physically a djacen t c ell s
on a silicon die through the cons truction o f a physical a djacency
model. T his model is g enerat ed u sing t he s t a tis t ical l oc ality of upset
cells f ollowing e xposure to i on izing rad i at ion. N o prior info r mation
about the device layout or the logical address mapping to physi cal cell
locations is required for this process, which is an important fact o r
since this i nformat i on i s often pr oprieta r y a n d not rea dily av ailab le.

23

This m eth o dology c an a lso be u sed to i dent ify int e rleav e d c e ll
structures. V alid atio n was per f or med on a d evice with k nown l a yo ut
which demonstra t ed t his ability of t his process to deter mine p h ysical
adjacency with as lit t le as 2% e rror [13].
 Developed a MCU extract i on t echnique t o iden tify i ndep end e nt
ioniz i ng e v e nts affect ing the FPG A s ilicon. T he a lgor it hm a ppl ies t he
new physic al a djacency m odel t o ext r act M C U cluster patterns an d
iden tifies t he l ocation and impac t o f each i o n izing ev en t [13]. This
technique identified significant MCU prevalence in 28 nm and 20 nm
FPGAs – a concern to t he space c ommunity, as r at e prediction t o ols
commonly used do not model these effects, a n d m itigat io n techni ques
are ill equip p ed to hand le multiple simultaneo us errors [1 4 , 15 ].
 Proposed a process to measure the dimensions of sensitive volum es
by o bserving t he d evice respons e t o a n gular irr a diatio n. 28 nm and
20 nm FPGAs exhibit a strong rotational dependence when irradia ting
at n on‐normal incident a ngles wh ich provides i nformation a bout th e
sensitiv ity of e ach face o f the sens itive RP P vo lume [16]. B y removing
MCUs and observing the event rate at different rotation angles, the
dimensio ns o f the RPP can be der ived a nd u sed in p lace o f class ical
assumptions used f or r ate pr edict i ons. T he n et r esult is a n im proved
error rate prediction b y about 15%.
 Proposed a new f ault m odel t hat provides h igh e r fid e lit y t o the impact
of ionizing events in 20 nm and 28 nm FPGAs. This fault model

24

provides a n omnidir e ct ional meas ure of s ens i tivity t o io n i zin g events.
Compared t o tradition a l approaches w hich u tilize u nid i rect ional bit
upset rate d ata, t his event‐base d fault model will account for ions t hat
strike the device from all angles and isolate the effects of MC U – tw o
key responses in 2 8 nm ( and smaller) d evices t hat current r ate
predict i on m odels cannot man a ge. T his new model provid es
improvement by a f ac tor of t hree i n the es timated failure rate of
modern‐scale FPGA devices in orbit [17].
1.4 O UTLINE
This diss e rt ation is org aniz ed as follows:
Chapter 2: Background information on ionizing radiation and the
basic mechanisms f or i oniz ing sin g le‐even t e ffec t s that a ffect CMO S
circuits ar e described.
Chapter 3: Research quantifying the effects o f ionizing rad iatio n in 20
and 28 nm FPGA technologies is presented. A comparison to prev io us
generat i ons of F PGA technologies i den t ifies n ew t r e nds in 2 8 nm and
smaller technologies compa red to earlier families.
Chapter 4: Creat i on o f a physic al a djacency m odel u sin g a s tat i st ic al
methodology is p res e nted. T his model iden tifies p hys i cally a dj acent
bits when layout information is not available, even when interl eav i ng
or o ther t echniques obscure physical a djacen cy i n the lo gical a ddress

25

map. This physical adjacency model can then be used to identif y and
isolate M C U s in the d e v i ce followin g irra dia t io n.
Chapter 5: A nov e l technique for mapp ing the d i mensions o f
sensitiv e vo lumes of s mall nanometer techno logies i s pr esen ted. This
technique was develo ped in l igh t o f new r o tatio n al depend e ncies
observed d uring angul a r irr a diation of 28 n m a nd 20 nm devices –
previous t echnology nodes were t oo large for a n y sign ifican t
rotat i onal d epend e ncy to be observed when ir radia t ing at angle.
Chapter 6: A new erro r fault model is p roposed that p ro vides higher
fidel i ty i n c h aracterizing u psets and angular effects in i rradi ate d F PGA
devices. When c ombined with e xi s t in g phenomenological m odels,
space erro r rates for small nanometer tec h nology n odes c an b e
predicted with improved accuracy compared to classical techniqu es.
Chapter 7: The final chapter conclude s and summarizes the wo rk,
and provid es t houghts for future a pplication of t his res e arch a nd t h e
path‐forward for SEE testing on new technol o gy nodes.

26

C HAPTER 2
2.1 I ONIZIN G R ADIA TION AND ELECTRONIC C IR CUITS
Ionizing radiation can be an esp ecially p roblematic i ssue for e lectronic
circuits, especially in high‐reliability systems where ensuring proper
operatio n with sig nificant u pt ime is o f paramount concern. Ion iz ing
radia t ion is r adiat i on t hat carr ies e nough en ergy t o rem o ve e le c t ro ns f rom
any atom it strikes, thus ionizing the atom [18]. Ionizing rad iat i on i s
comprised of m any sources, i nclu ding a lpha, beta, gamma p articl es, and
other subatomic particles [19]. H owever, t h e main s o u rces o f e nerg et ic
particles th at a re o f concern to spacecraft designers are typic ally c omprised
of protons, electrons, a nd heavy io ns [20].
2.2 S OURCES OF I ONIZING R ADIA TION
At t erres t rial a ltitudes, the typical background n eutron p artic le f lu x and
energy spectrum normally present at terrestrial altitudes can c ause
measureable upset rat e s in C MOS electronics [21, 22]. I n some cases, s light
radioact iv it y in m ater ials ( for exa m ple, l ead solder) can also generate a lpha
particles th at i nduce S EE in m odern na nomet e r‐scale devices [23 , 24]. T hese

27

effects, though, happen infrequently compared to those caused b y space‐
based radiation sources.
Since this r esearch is f ocused o n space‐based electro n ics, t he dialog
referring to radiation effects will focus on the space environm ent and its
effects on space‐based electronics whose primary operation occu rs o utside
of t he Earth’s a tmosphere at a ltitudes a bove 160 k i lometers. The var ious
ioniz i ng r a diat i on p ar t i cles i n outer space va ry i n typ e a nd f lux based on the
orbital altitude. Typical orbits are depicted in Figure 1. In space, ioniz i ng
radia t ion effects ar e considered f r o m three primary sour ces: g alactic cosmic
ray (GCR) background r adiation, p a rticles trapped by E arth’s m a gnetic f ield,
and solar energetic particle e vents [25]. E ach source m ay b e c omprised
primarily of one or more particle types, and the contribution f rom e a ch
source will vary based o n the oper ation a l orbit of the spa cecra ft.

28

FIGURE 1: COMPA R I S ON OF C O MM ON S ATE LLITE ORB ITS
GCRs c onsist o f the typ i cal background r adiation n ormally p rese nt i n space .
This t ype o f r adia tion i s typ i cally e ncounter ed a t higher o rbit s by s atellites
operating in Geostationary Earth Orbit or during interplanetary m issions.
GCRs o riginate f rom distant sourc e s outside the solar system a n d c o nsist of
approximately 85% protons, 12% h elium nuclei, 2% elect r ons, and 1% heavy
ions with an atomic number Z > 2 [26]. It should be noted that although
heavy ions c omprise a small portion of t he G CR spectrum, t hey a re still a
signific ant c o ntributor to SEE d ue to their high e r energies.
At l ower a l t itudes, cos m ic r adiation i s no l onger the p r imary s ou rce of
radia t ion, a s the Earth’s magnetos phere provides a c onsiderable amount of

29

shielding from GCRs [27]. While the measure of shielding offer ed b y the
magnetosp h ere helps reduce G CR f lux significantly, i t al so h as the side e ffec t
of creating magnetic bands that can trap smaller particles (nam ely electron s
and protons). Thus, trapped part icles compri se the second prim ary source of
ionizing radiation and the primary source of SEE at lower orbital altitudes. A
trapped proton belt is present closest to the Earth, while trap ped electrons
reside further out in space. An artist’s rendition of these belts is shown in
Figure 2 [28].

FIGURE 2: ILL U STRA TION OF VA N A L L E N BELTS SU RRO UN DING T HE E ARTH , RES U LTING
IN BEL T S OF TR AP PE D EL E C TR ON S (O UT ER B EL T ) A N D P RO TON S ( I NNE R B EL T )

30

The final source of radiation comes from solar activity. Occas ionally t he
sun ent e rs p eriods o f h igh activ i ty w here s olar f lar e s and CMEs r elea se
bursts of energy and atomic matter. These events are typically c omprised o f
protons but can contain heavier ion nuclei as w ell, a nd f or spa cecraft caught
in the path of these bursts, the flux of the various particle types can be very
high compared to normal conditions. Solar maximum conditions r esult in
three CMEs p er day, whereas typ i cal solar minimum conditio ns p r oduce only
one CME every five days [29].
2.3 I ONIZIN G R ADIATION E FF ECTS IN CMOS
When i oniz ing r a diatio n part icles strik e C MO S devices, o ne o f two p ossible
effects ma y occur. The part icle m ay g enera t e pro d uce either di rect
ioniz a tio n o r ind i rec t i oniz atio n effec t s, a s illustrated in F igure 3 [25]. Both
result in unwanted charge deposition into the device and differ only in the
mechanism through with t he c harge is g en erated. T he m easure o f charge
that i s deposited into t he d evice is r efer red to a s the “Linea r Energy
Transfer” or LET, and has units of MeV‐cm
2
/mg.

31

FIGURE 3: DI RE CT I ONIZ ATION F R O M H EAVY I ON ST R IKE S V S. IN D IRE C T I ONIZ ATION
FROM NUC L E A R COLLIS I ONS
Direct i oniz ation occurs primarily f rom heav y ion s t rikes into the s i licon.
An ionization trail resulting from the particle’s movement thro ugh silicon
results in the formation of many electron‐hole pairs [30]. Tho ugh many o f
the electro n ‐hole pairs recombine, some pairs do not. The grea ter mobility
of electrons and their attraction towards the gate interface al lows s ome pairs
to escape re combinatio n, and whi le the se carr i ers dr ift to ward the gate, freed
holes will drift toward s the SiO 2 inter f ac e. S ome number of freed hol e s w i l l
become trapped and form a positive oxide‐trap charge, while the remaining
carriers will either e ventually r ecombine or follow charge f low a s current
moves them through t he circuit.
Indirect i onization occurs w hen a particle ( typically a s mall p article, like a
proton) collides with a silicon atom in the substrate. This co llision causes a
small, nuclear reaction resulting in the atomic structure of th e silicon atom
losing one or more n eutrons. T his results in a n ion that d epos its ch arge a s it
recoils thro ugh the silicon lattice. At this point, the mecha nism f or e lectron‐

32

hole g enera t ion follows t hat of t he dir ect ion i zat i on m odel des crib ed a bove.
However, since the recoil distance is usually relatively short, t his typically
results in l ess over all charge d epositio n c o mpared t o direct i o niza tion
strikes.
For eith e r charge d epositio n mechanism, t her e i s a wid e a r r ay o f
deleterious effects that c an r es ult from i onizing radiation str ik es. S ome
effects, s uch as t otal d ose effects, r esult in a s low long‐term degradation in
performanc e while others, such a s singl e ‐event l atchup, may res ult in v ery
sudden destructive effects. Thes e effects will b e described in m ore deta il i n
the followin g section s.
2.3.1 TOTAL IONIZING DOSE
Total ionizing dose (TID) is a typically slow, gradually occurr ing effect t hat
causes t hr eshold v oltage sh i fts, l eakag e , a n d speed d egrad a tio n in MOS
t r a n si st or s [2 5 ]. T I D i s a cumulative effect based on the tota l radioactive
dose e xper ienced b y the MOS device. D ose rates can va r y signif icantly based
on orbital a ltitude, as illustrated in Table 1.

33

TABLE 1: S AMPLE OR BIT A L DO SE R AT ES

TID effects occur w h en r adiation passes through gate oxides c r e at ing
electron‐hole pairs fro m t he d eposited e ner g y [31]. Some of t h ese electron‐
hole pairs recombine immediately, but some escape recombination and since
electrons h a ve more mobility compared to h oles i n SiO 2 [32], they are swept
out of the oxide leaving only relatively immobile holes. The excess holes
cause a negative threshold voltage shift in the MOS transistor. Though some
annealing of this effect can take place over time, the process is v ery gradual
and ultimately TID will result in transistor failure if the dev ice r e mains in a
radiation enviro nment.

34

2.3.2 DESTRUCTIVE SINGLE EVENT EFFECTS
Ionizing radiation can cause a few types of destructive SEE. T he
destructive effects c a n result d irec tly as a r esult of t he i o n strike o r indirectly
through mechanisms e nabled b y c h arge d eposition into t he s ilico n. The m ain
destructive effects that r esult direc t ly f rom ion strikes inclu des displacement
damage ( DD), single‐event b urno ut ( SEB), an d single‐event d iele ctric rupture
(SEDR) [25, 33, 34]. However, these mechanisms are not prevale nt i n bulk
CMOS d ev ices, and thus r emain outside the scope of t his res e arch. One
mechanism that i s quite prev alen t, h owever, is single‐event lat chup ( SEL)
and is a major consideration wh e n evaluating e lectronics f or us e in s pace.
SEL occurs w hen a low‐resistanc e s elf‐sustaining p ath develops between
V DD a nd g round and can result i n hi gh‐current c onditions that c an cause
vaporiza tio n o f meta l traces, melting of s ilicon r egions f rom t hermal
runaway, o r other fail ures i nduced f rom the high c urrent d ens i t y [33]. T his
often resul t s in i rr ep arable damage to t he p art and is c ons i der ed a
catastrophic event for deplo yed spacecraft systems.
The path between V DD and ground, i llustrated in Figure 4 [ 35], is enab l ed by
two parasitic bipolar transistor s created between t he s ubstrate , well, a nd
diffu sio n . W h e n an io n stri ke ca u ses su f f i ci e n t ch arge c ol l e ct ion deposited on
the base of either TR1 or TR2 (normally off), the transistor ma y turn o n, a nd
with l arge e nough R well or R subst rat e, the positive f eedbac k w ill turn t he o t h er

35

transistor on as well, causing latchup to occur and complete th e p a th f rom
V DD to ground.

FIGURE 4: ILL U STRA TION O F POT E N T IAL SEL P A TH TH R OUG H P AR ASITI C BJTS FORMED
BETWEEN WELL AN D SUB S TRATE

Once latchup has occurred, the latched state will exist until e ither the
device b urns o ut f rom the large su pply current o r until V DD i s lowered past a
holding voltage thresh old where the voltag e is n ot l a r g e e nough t o sustain
positive feedback [36].
2.3.3 NON ‐DESTRUCTIVE SINGLE EVENT EFFECTS
Ionizing r a d iat i on c an a lso result i n non‐des t r u ctive, “ soft ” e rrors i n CMOS
devices. Though they may disrupt the behavior of the device, the e ffec t s are
not permanent and non‐damaging. I n the worst case, power cycli ng t he
device will reset the device back into a known state and will r eturn the
device back into a normal state (albeit without the operational contents of

36

any volat i le m emories, etc. t hat m a y have e xisted p rio r t o powe ring down).
However, s oft errors r esulting f ro m SEE often result i n much l e ss impactful
errors, such as flipping a stored logic value in a memory cell. There are three
types of soft errors: single‐event upset (SEU), single‐ev ent t r a ns ient ( SET),
and single‐ e vent functio nal interru pt (SEFI).
SEU occurs w hen radiation‐induce d direc t o r indirect i onization e ffec t s
cause sufficient charg e depositio n to o ccur to c hange the state of an
ordina rily s table feedback c ircuit. T he m ost notable occurrenc e is w ith static
random‐access memory ( SRAM) c ells, which use cross‐coupled inve rters to
store data v alues and access transistors to c hange the value st ored b y the
cross‐coupled in ver t er s. A n ener getic pa rtic le strik e in a sen si ti ve loca t i on
can cause a transient current i n the struck t rans istor [37]. T he r estoring
transistor will source current in an effort to balance the part icle‐ i nduced
current, but due to its finite current drive and channel conduc tance, w ill
cause a voltage perturb a tion t ha t will cause the opposing i nver ter to c hange
value and s u pplement driving the incorr ect v a lue back t o the up set invert er.
The net result is the storage of the upset value and a change i n the stored
value from zero to one (or one to zero).
The mecha n ism for in duced SET is v ery s i milar to t hat of S EU. SETs a re
current‐ind uced p ulses that c an m omentaril y c hange t h e value of a driven
wire away from its correct value. As shown in Figure 5 [38], a n energetic
particle s trike can caus e a unwa nt ed S EE‐ind u ced current i n an ou tput l ine.

37

This l ine results in a v oltage p ulse t hat rem a ins until t h e exc ess charge i s
dissipa ted through the “on” t ra n s istor. T h e l ength of t ime for this pulse
depends on a number of factors, including transistor sizing, cr itic al c harge
required to upset, the value of the line capacitance, and the R C time c onstant
of the discharging path [38], but is typically on the order of a few hundred
picosecond s minimum up t o a few nanos e c o nds. D ep ending o n t h e part o f
the circuit where the SET occurs , i t s potential impact to circu it operation may
rang e from c ompletely unobservable t o highly d isruptiv e. For e xample, SETs
on t he d ata input to a f lip‐flop w ill only b e observable i f the c lock e dge occurs
at t he s a m e time a s the SET pulse. H owever, SETs o ccurring o n an
asynchrono us r eset o r clock tree could potent ially h ave ver y o b vious
disruptive effec t s.

F IGURE 5: A S C H E M A TI C VI EW OF H O W S EE‐I N D U CE D CU RR ENT P U L S E TR A N S L A TES IN TO
A VOL T AG E P U L S E IN A C M O S I N VE RT ER

38

A SEFI, though described h ere a s a S EE alongside SE U and SET, i s not
describing a new type of radiation‐induced upset mechanism but rather a n
operational anomaly caused by SEU or SET that leads to temporar y non‐
functionality of t he a ffected de vic e , or some subset o f the dev ic e [39]. O ften
this non‐functionality will also be in a portion of the device o r c irc u it t hat is
not observ able o r has limited ac c e ssibility b y the user, making i t d i fficult to
understand the exact failure mechanism that caused the SEFI to occur. A s an
example, i n Xilinx F PGA circuits, one possible SEFI i s a Power‐ On R es et S EFI,
which causes t he devic e to e rrone ously issue a power‐on r eset, causing a loss
of all memory contents and disrupting operation until the devic e is r e‐
programmed [40]. T ho ugh the mechanism th at a c t iv ated t he p ower ‐on reset
circuitry was likely a result of SEU or SET, it is classified as a SEFI since it
causes a functional interrupt in device operation and the circu itr y i s no t
accessible to the user and thus the mechanism for failure canno t be e xactly
pinpoint ed.

39

C HAPTER 3
3.1 I NVES TI GATING T HE R ADIATION R ESPONSE OF 20 AN D 28 NM FPGA S
In o rder t o inves t ig a t e the pot e nt ial differences in small nano meter
response t o ionizing r adiation, two Field‐Programmable Gate A rr ay ( FPGA)
devices were c haract erized f or r esponse to i oniz ing r a dia t ion e ffects; o ne
device was constructed with 28 nm feature sizes, and the other with a 20 nm
feature sizes.
The ex emplar dev ices s elected to s tudy were F P GAs from X ilinx, Inc. FPGAs
are commonly utilized b y the space elect r onic s community a nd h a ve decades
of h erit age in f light applications a nd r adiat i on c haracter izat ion. FPGAs are
int e gra t ed c ircuits tha t contain a l a r ge v ariety of differen t h ard silicon blocks,
including st andar d d igital l ogic e lements (such as f lip‐flops, look‐up tables,
etc.), a nal o g elemen ts ( like p ha se‐locked loops and analog‐to‐digital
converters), and large memory arrays (like dedicated user‐acces sible
BlockRAM™).
The two FPGAs selec t ed f or s tudy a re SRAM‐based devic e s, a nd c u rre n t l y
lead t he c o mmercial market a s th e latest s tate‐of‐the‐art. Whi le other classes

40

of F PGAs e xist, such a s anti‐fuse and flash‐based devic e s, t he flash‐based
FPGAs limit e d to 6 5 nm f ea ture s iz es [41], wh ile space‐based an ti‐fus e FPGAs
are even f u r ther b ehin d, still utiliz ing a 0.15 µ m p rocess [42] . T his research
focused primarily on t he a nalysi s of t h e c onfiguration m emory o f the two
Xilinx F PG As, which is c omprised o f a lar g e number o f SRAM bits and
behaves much like an S RAM memory array.
3.2 DEVI CES UNDER T EST
The two d e vices tha t w ere irr a dia t ed a r e t he 2 8 nm Kin tex‐7 and t h e 20 nm
Kintex UltraScale FPGAs. The Kintex‐7 is the mid‐range offering in the Xilinx
7‐Series f a m ily of F PGAs b uilt o n the TSM C f oundry’s 28 nm, hig h‐  metal
gate process technology [43]. The UltraScale is built using TS MC’ s 20 nm
20SoC process [44, 45].
The Kintex‐ 7 p art used i n this s tudy w as t he X C7K325T‐1FBG900C, which
is a m id‐feature‐r ang e , commercial temperature‐gr ad e FPGA. K inte x‐7
devices operate with a nominal 1.0 V main core voltage (VCCINT) , an
auxiliar y vo ltage o f 1 . 8 V ( VCCAUX ), a nd p rog r ammable I/O pins at v oltages
from 1.2 V up to 3.3 V (VCCO) [46]. The Kintex UltraScale was the X C KU040‐
2FBVA115 6E, an e xt ended tem p erature‐g r ade device. U ltraScal e d ev ices
operate with a nominal 0.95 V VCCINT core, a VCCAUX voltage of 1.8 V , a n d
VCCOs from 1.2 V up to 3.3 V [47]. The configuration memory in these parts
is comprised of an array of highly robust CMOS configuration la tc hes that
behave similarly to a static random‐access memory (SRAM) [48, 49]. This

41

configura t ion memory c ontrols th e beha vior o f th e va rious in ter nal
components and the progr ammable in tercon n e ct.
Heavy‐ion cyclotrons available for SEE testing typically do not have the
requisit e io n ener gies n ecess a ry t o penetra t e the d e vic e l id a n d subst r a t e or
are difficult t o utilize because of l imited a va ilability or h igh cost [50]. In the
case o f the Texas A &M K500 and th e Berkeley 88‐inch C yclotrons, their ion
energies are relatively low, and as such, the device package li d had to b e
removed in o rder t o expose t he b are die u n der n ea th. F urthermor e, b oth
FPGA devic es u tilize f lip‐chip t echnology in l ieu o f wire b onds, so the silicon
substrate o n t he b ackside o f t he die i s exp o sed when t he d evic e lid is
removed. Thinning of the substrate is necessary as well in ord er t o ensur e
that the ions generated by the cyclotron have sufficient energy to penetrate
through the silicon substrat e into a ctiv e r e gio n s of t he sil icon. Both devices
had their s u bstrates t hinned to a pproximately 74 µm, which was confirmed
by infrared spectroscopy as shown below in Figure 6. Following that, the de‐
lidded and prepared D UT is shown in Figure 7.

42

FIGURE 6: THICKNESS ME ASU R EMENT O F ON E P R E P A RED KINT EX U LTR A SCA LE D U T

FIGURE 7: KI NTEX ULT R A SCAL E TEST B OARD WIT H D U T MO UNT E D

43

3.3 I ON B EAM C HARACTERISTICS
The devices wer e i rra diated w ith heavy ions a t sev e ral tes t c ampaigns. The
Kint ex‐7 w as i rrad i a t ed w ith heavy ions a t effec t iv e LETs f rom 1.5 to 126.1
MeV‐cm
2
/mg in S eptember 2013, M arch 2 014, A pril 2014, a nd J une 2014.
This testing was performed in air at the Texas A&M University ( TAM U ) K500
Cyclotron a n d in v acuum a t the Lawrenc e B er keley Labor a tory ( LB L) 88‐inch
Cyclotron. Measured SEU results for the FPGA configuration mem ory, t he
user‐accessible BlockRAM, and the u ser‐accessible flip‐flop cel ls w ere
obtained [12]. The Kintex UltraScale was irradiated with heavy ions at the
LBL 88‐inch c yclotron w ith effective LETs f rom 0.98 to 63.91 Me V‐cm2/mg
in May 2 015 and at t he T AMU K500 cyclotron with a L ET o f 79.2 M eV‐
cm
2
/mg in J uly 2015. The UltraScale t est obtained S EU r esults f or the FPGA
configuration memory and the user‐accessible BlockRAM, and test ed t he
device f or s ingle‐ev en t latch‐up [11].
Additionall y , for angul a r studies, a number o f separate i on b ea m studies
were conducted during these tes t c ampaigns where the angle of i nc idence for
ion strikes was altered with a variety of rotation and tilt angles. As best as
ion ra nge permitt e d, t ilt a n gles f rom 0 up t o 70 deg r ees wer e t es ted, a nd
rotation was varied from 0 to 90 degrees. The orientation of tilt and rotatio n
angles i s s h own below in F igure 8. Tilt angle is r ep resented b y  T and
rotation ( sometimes also r eferred to as azimuthal) angle is rep resented b y

44

 R . Normal incidence, the preferred angle for the majority of SE U s t udies, is
at (  T =0°,  R =0°).

3.4 SEU T EST P ROCEDURE
The goal o f this p articu lar SEU test ing is t o exa m ine the st ati c SEU response
of the fundamental components contained in the FPGA. Xilinx FP GAs are
designed to support synchronous designs and thus at a minimum r eq uire t he
use of flip‐flops, LUTs, routing interconnect, and occasionally BlockRAM.
LUTs and routing interconnect are configured by the configurati on m emory.
Flip‐flops and BlockRAM are comprised of independent cells. Th us, SE U
testing was comprised of e valuat ing us er f lip‐flops, B lockRAM, and
configura t ion SRAM memory cells in the K i nt ex‐7.
FIGURE 8: O R I ENT A TI ON O F TILT (  T ) AN D R O TA TION (  R ) FO R I O N STRI K E S IN TO A
S E NS ITIVE VOLUME OF S I LI C O N

45

During i rradiation, the clock wa s stopped, w hich m asked most d y namic
effects typically caused by SET. The post‐irradiation state of the DUT
compared to the starting state yielded static upset counts. SE U test ing w a s
conducted at ambien t tempera t ure and nominal voltage biases.
In order to obtain flip‐flop and BlockRAM upset rates, the FPGA desig n
loaded i n t o the DUT w a s designed w ith numerous f lip‐flop c hains preloaded
with an “all‐0s” or “all‐1s” pattern. Resets were configured t o either r eset o r
preset t he f lip‐flop s uch that r es et t rans ients would always f lip the value of
the flip‐flop opposite o f its initialized value. T he F PGA desi g n a lso included
all available BlockRAM i n the DUT, h alf preloaded to “ 1” v alues and the other
half with “0” values.
F ol l owing FPGA confi g u r ation, th e p art was ir radia t ed to a sp ec ified fluence
or until conditions arose that required stopping the beam, typi cally w hen
SEU‐induced contentio n c aused the die tem p erature to r ise beyo n d safe
thresholds or c aused p o wer consu m ption to i ncreas e beyond t he c apaci t y of
the power supply. The goal was to count events corresponding t o a total
fluence of 1 0
7
particles or at least 10
3
events for each LET in order to obtain
statistical s i gnificance f or S EU t es ts. I t w a s often neces s ary t o ach iev e the
target fluence by accumulating event counts from multiple short er r uns in
order to avoid conditions that r equired stopp i ng the r un e arly.

46

Once t he b eam was t u rned o ff, t h e configur ation memory w as r ead back
and saved for processing t o dete rmine t h e number o f upset flip‐ flop
regis t er s, BlockRAM bits, and the c o nfigura t io n memory bits.
3.5 SEL T EST P ROCEDURE
SEL testing was performed at e le vated t e mperatur e (above 90° C ) and at
with voltages at maximum specifications. Some runs were perfor med
simultaneo usly w ith SEU test in g and thus w ere performed at a mbient
temperature and nominal voltag es. T he p ar t was co nfigured, loggi ng w as
started to r ecord the current c onsumption o f each v oltage r ail for the
duration o f the run, then the devic e was irradiated.
Current increases that might indicate latch‐up were investigate d post‐
beam. To ensure current increases were due to latch‐up and not simply SEU‐
induced contentio n , configura t io n scrubbing w as e mployed to e li minate any
logic contention a nd h ardware re sets ( thro ugh assertion of t he PROG p i n )
were employed after the beam was turned off, since true latch‐u p conditio ns
would not be cleared by either of these methods. To further veri f y any
current increases are indeed latch‐up, the supply voltage would be lowered
low enough t o r e leas e t h e latch‐ up s it e without losing m emory contents. By
lowering the supply voltage beyond a minimum “holding voltage,” a latch‐up
site c annot sustain itself [51], s o l owering the supply voltage beyond a
certain threshold would be a nother i ndic ator t hat SEL has occur red.
However, care must be taken in seeking this latch‐up signature as l o w ering a

47

voltage too far w i ll activate i nter nal brown‐out circuitry on the device. Note
also that classical latch‐up is normally accompanied by loss of part
function alit y, s o any loss of f unction would help i ndicate tha t SEL has
occurred as well.
3.6 R ESUL TS
A picture of the test setup is shown in Figure 9. Overall, SEU c ross sections
yielded reasonably g ood r esults c onsistent with e xp ectations d erive d f r om
combining previous X ilinx FPGA f amily SEU performan c e with t r a n sistor
fea t ure siz e scaling.

FIGURE 9: TEST S ETUP A T TEX A S A& M CYCLOTRON FACILITY

48

3.6.1 28 NM KINTEX ‐7 SEU RESULTS
The Weibull curve illustrat i ng t h e c onfiguration m emory cell cr oss‐sectio n
vs. LET is shown in Figure 10. These curves are generated with the SERET
software t ool [52], which takes th e exper i mental d ata points a n d fits W eibull
curves a n d c an g enera t e spa c e ra te e stimat es u sing C RE ME96‐like
algorithms. I n these Weibull gr aphs, the LET is a m easure o f t he charge
depositio n c aused fro m t he h eavy i on, while cross‐sec t ion is a measure of
susceptibility represented by th e t a rget ar e a v u lnerable t o SEU .
When analyzing the readback files from SEU runs, comparisons ar e masked
to only include bits pertinent to device operation and to exclude dynamic
conten t, l ike flip‐flops. T he W eibull curve conforms t o parameters: L th =1.9
[MeV‐cm
2
/mg],  sat =1.43e‐8 [cm
2
/bit], W=125.3 [MeV‐c m
2
/mg], S=0.78.

49

FIGURE 1 0: W EIBULL CU RV E FO R KINT EX‐7 C ONFIG U RATION MEMORY CELL U PS ET S
An i nves tig a tion o f upset cells r ev ealed that m emory locations load ed w it h
0s or 1s upset approximately eq ually, indicating no bias.
3.6.2 20 NM KINTEX ULTRASCALE SEU RESULTS
The Kin t ex U ltraScale c r oss‐sectio n showed i mprovement o ver the Kintex‐
7 by about an order of magnitude at saturation, as shown in Fig ur e 11. The
Weibull parameters f or t he U ltraScale data a re L th =0.8 [MeV‐c m
2
/m g],
 sat =2.0e‐9 [cm
2
/bit], W=27.0 [M eV‐cm
2
/mg], S=0.88.

50

FIGURE 1 1: W EIBULL CU RV E FOR ULTRAS CA L E C ONFI GURA TION ME M ORY CE LL UPS E TS
For reference, Figure 12 provides a plot of scaling trends of X il in x FPGA
configura t ion memory i ncluding 0 .13µm Xilinx V irt e x‐ II [53], 9 0 nm X ilinx
Virtex‐4 [54], 28nm Xilinx V irte x‐7 [12], and 20nm Xilinx U ltra Sc ale [11].
Table 2 below provides W eibull parameter s a nd r ate calculations using
CREME96 [9] (a space error rate estimate tool), assuming a GEO orbit, solar
minimum conditions, and 100 mi ls of aluminum shielding .

51

FIGURE 12: WE I BULL FITS FOR XILIN X CONFIGU R ATI O N ME MO RY S CALING XILI N X
VIRTE X ‐II THROUG H XILINX ULTRASC A L E D E VIC E S

TABLE 2: S CALING FITS AN D R A T E C ALCULATI ON S

52

3.6.3 KINTEX ‐7 SEL RESULTS
In the SEL beam runs (with high temperature and high biases), a c urrent‐
step anomaly was observed on the VCCAUX supply rail at high LET. No SEL‐
like current signature was o bserved on any other rail.
During normal operation, the 1.8 V VCCAUX supply current would
ordinarily r emain fairl y c onstant with l ess than ±37.5 m A diffe r e nc e over t he
entire operational time. The current‐step anomaly resulted in multiple s mall
current steps a verag i ng 125 mA (  i = 40 mA) each. This current is quite
small for classical latc h‐up. A dditionally, no l oss of p art fu nct i onal ity w a s
observed to accompany these single‐event current steps. At low flux and
high LET, the current steps are clearly discernable in captured current strip
charts. One example is shown in Figure 13, which shows 7 or 8 potential
latch‐up sites dev eloping over t he b eam run.

53

FIGURE 1 3: C UR RE NT S T R I P C H A RT D URING SEL TES T IN G OF K INTEX‐7
This r esult neces sit at ed c ar eful i nvestig a t i on. T he f irs t m iti gatio n s teps
involved c o n figur a tio n s crubbing, part r econfigurat i on, a n d a f ull reset w i th
assertion of the hardware PROG reset pin. None of these steps re solve d t he
additional c urrent.
In o rd er t o ver i fy t hat these curr ent steps a r e indeed t he r esult o f some
form of current‐limited latch‐up, the VCCAUX supply voltage was
experimentally l owered i n increments o f 100 mV. R esults s how t hat
dropping the voltage to 1.2 V then returning to the nominal lev el o f 1.8 V
restores the normal current state of the VCCAUX supply rail. T h u s, t hese
current st e ps do demonstra t e th e holding voltage sig n ature of p arasitic

54

bipolar latch structures [51] and are not upset‐induced interna l contention
or s ingle‐event functionality mo de c hanges. W hat element or s t ructure is
limiting the current to such low levels is currently unknown, b ut u nder
investig at ion.
The LET threshold of t hese l atchup e vents appears to b e near a n e ffective
LET of 15 MeV‐cm
2
/mg. Only one VCCAUX current step event is present in
the data at this LET and none in any lower LET runs. The holdi ng v oltag e
signature was observed for this event; nominal current was rest ored b y
lowering VCCAUX to 1.2 V then restoring it back to 1.8 V (note that l owering
to 1.2 V was not enough to activate brownout reset circuitry, s o memor y
conten ts w ere r e t a in ed).
The cross section for t h ese small latch‐up e vents is f airl y sma ll. At h igh
LET, a device cross section of 2 .9 x10
‐4
cm
2
was measured. The event drops
over two orders of magnitude at an effective LET of 15 MeV‐cm
2
/mg. The
Weibull curve for th is e vent i s shown below in F igure 14 a nd c o nforms t o the
parameters L th =1.9 [MeV‐cm
2
/mg],  sat =3.16e‐4 [cm
2
/bit], W=53.4 [MeV‐
cm
2
/mg], S=3.8.

55

FIGURE 1 4: W EIBULL CU RV E FO R CU RR E N T‐ STE P E VE NTS OB SE RVE D D U R IN G SEL
TESTING
It should be noted that this effect should necessitate further examinatio n,
as s tructur e s such a s t h is o ne t hat exhibit latc h‐up‐like behav ior but seem t o
be current limited, have not been observed b efore in CM OS. Sinc e the studies
in t his dissertation a re f ocused on angular SEU effects, furthe r studies on t his
subject are not d e scr i bed her e , but are worth future i nv estig a tion ; i n
particular, it w ould b e very i nt er esting t o d e termine if t he l a ck o f current
draw in this SEL‐type structure is al so the result of tr ansis t o r scaling.

56

3.6.4 NEW SEU RESPONSES OBSERVED IN 28 NM AND 20 NM FPGAS
When i nv es tiga tin g t he l ocation of u psets with in t he c o n figurat ion m e mory
space, a n umber of i nter est i ng m ultiple cell upset clusters s eemed to be
present. The shapes of these MCUs seemed to indicate that conf igura t ion
words and adjacent l o g ical a ddre sses follow a physic al i nterlea ving p attern
of bits between words. A pictorial representation of this inte rl eaving i s
shown in F igure 1 5 , w h ere con f ig uration words span v ertical col umns, and
horizontall y a djacent columns are configuration wo rds logically a d j acent in
the configu r atio n memory space. T his int e rleav i ng i s likely e m ployed t o
preser ve t he b its used f or S ECDED error correctio n employed i n the
configura t ion words. A n analys is o f these multiple‐bit e v e nts an d the i r
implication to inferr i ng p hysica l device layout is discussed in Chapter 4.

FIGURE 1 5: SAMPLE OF M CU E V E NTS MAPPE D PI C TORA LLY

57

C HAPTER 4
4.1 I DENTIFYING P HYSICALLY A DJ ACENT MULTIPLE ‐CELL UPSETS
As observed by the characterizat ion discussed in C hapter 3 , a n umber of
patterns emerged in SEU testing that appeared to affect logical ly a djacent
memory words in the configuration memory address space. The pr evalence
of multiple‐cell upsets (MCUs) have been demonstrated to increa se wi t h t h e
shrinking feature size o f transi stors [55], and so t hese p atter ns a re
hypothesized to be clusters of MCUs. MCUs are single ion strik es t hat upset
multiple physically adj acent bits on the die.
MCUs a r e i mportant t o address because they r educe t h e effic a cy of e rror
correcting codes (ECC), s uch as s ingle‐error correct/d ouble‐error detect
(SECDED) s chemes t hat are not d e sig n ed t o correct m ultiple simu ltaneous
errors. Of importance to FPGA circuits, MCUs can disrupt mitigati o n
techniques a dded to u ser designs, such as Triple Modular Redund ancy
(TMR), which votes primary outputs with three copies of the log ic c ircuit.
MCU can affect t wo o f the three logic circuits s imultaneously, causing the
incorrect output to become erroneously voted as the majority at the circuit
output [14].

58

In recent years, interleaving memory cells has reduced the impa ct o f MCUs
in SRAM arrays by translating an MCU into individual errors tha t can be
corrected u sing S ECDED [56]. U nfor tunat e ly, these interl eav i ng s chemes
make it more difficult to identify MCUs in radiation testing un l e ss the
physical l ayout is k nown. In t his section, w e will discuss a te chnique for
extracting information about MCUs from bit interleaved memory c ells w hen
the physica l layout is unknown [1 3 ].
4.2 MEMORY O RGAN IZATION
Memory c ells c an b e view ed either as b eing physically o r logica lly
organized. The physical representation of the array is necessar y for
determinin g which SEUs a re M CUs, a s the physical a djacency o f m ultiple
SEUs identifies the MCU. The logical organization, such as a w ord in SRAM
array s or a cache line in a processor, determines how the memor y is accessed
by the user. Both representations are important when analyzing and
understa nd ing the M C U behavior i n a component. W h e n ECC is u se d, i t is
necessary to determine how MCUs overlay onto the logical struct ure to
determine whether M C Us o v e rco m e the enc o ding s cheme. W hile t he physical
location and the logical address are related, logical adjacency does not imply
physical adjacency, esp e cially if the cells are i nterl e av ed [57 ].
This d iffer e nce between the phy sical a nd l ogical r ep r e sen t at ion s of the
memory o rganiz at ion leads to c on fusion i n the terminology used in t he

59

literature. Here, we are using these definitions for the physic al
repres entations of erro rs:
 Multiple ‐Cell Upset (MCU): A single particle causes more than one
upset bit regardless of the logical rel ation sh i p. MCUs refe r t o all of t he
cells that are upset by the particle regardless of logical orga niz a t i on i n
the memory addres s s p ace.
 Single ‐Cell Upset (SCU): A single particle that causes only one
memory cell to upset.
In the logic al address re alm, we have this term :
 Multiple ‐Bit Upset (MBU): A MCU where multiple upsets occur in a
single “word” in the logical memory address space. A MBU refer s only
to the portion of the MCU that occurs within a single logical w ord and
ignor e s the any par t of the MCU that affect s ot h er words.
As a n artifact o f tes t ing, i t is p ossible to c onstruct M CUs thr ough t he
accumulation of SEUs [58]. For t his situation we use this term :
 Coincident SEU (CSEU): Two or more SEUs, whether MCU or SCU,
that are physically adjacent in such a manner that an MCU is
constructed (i.e. “fake MCU”). Because this effect is an artifa ct o f
accelera ted test ing, s uch events a re st a t i st ically r ar e in depl oyed
systems.

60

Start i ng i n the 28 nm 7 ‐series devices, Xilinx has started u s in g bit
interleaving and a 32‐bit SECDED ECC word to help correct and d et ect SEUs
as they occur. These ECC words are used to detect and correct S CU s in t he
logical “word” in an F PGA, which is called a frame .
Figure 16 demonstrates how a 5‐bit MCU would affect the content s of t wo
int e rlea ved frames. This s ame MCU corr esponds to t wo M BUs as s e en i n
Figure 17. The two MBUs are easily detected by the user throug h
configuration readback. The actual M CU, however, i s not det e ctable by t he
user.

FIGURE 1 6: 5‐ B IT M ULTI‐ C E LL UP SE T WI THIN I NT ERL E AV ED FR A M E S

FIGURE 1 7: T WO M BU S VISIBLE TO TH E U SER

61

4.3 P RIOR W ORK
The k e y cha llenge w i th i den t ifyi ng M CU i n modern F PGA devices is that the
physical l ayout and logical organiz a tion i s pro p riet ary. W ith physical l ayout
information, there a number of different MCU extraction techniq ues and
analys es t hat can be c ompleted, such a s the effec t o f well dept h, w ell
contacts, cluster size or input data dependence [57, 59, 60]. Oth e r
researchers have looked at methods for extracting MCUs from SEU data sets
when the physical layout was not known. [61] uses an analytica l model
based on t he g eometr ic distr ibution that m odeled “ gro u ped arriv als” a s a
proxy for MCU effects and was validated using the data f rom [56 ]. S everal
researchers have u sed logical adjacency to extract MCUs from th e SEU data
[62‐64]. I n [65], MCUs w ere extrac ted from t h e S EU d ata set fo r the S p artan‐
3 by running at very low fluence, so the statistical probabilit y of h aving more
than one upset in the configuration memory at one time was very low.
Prev iously, the authors have r elied u pon rever se en gin e er ing or p rop r iet ary
informa t ion to t r a nsla te l ogical a ddresses to p hysical addresse s in X ilin x
FPGAs [58, 66].
Our technique is a st a tist ical m et hod that c a n b e used w ith a m in imum o f
information about physical layout of the component and any SRAM a rray.
This t echn ique u ses the logical address e s of S EU s to deter mine the
probability of p hysical adjacen c y and st atis tically d efine the physical

62

adjacency model, which can be used to extract MCUs from the ori ginal data
set.
4.4 MCU A ND MBU E XTRACTION T ECHNIQUE
The MCU extract i on t echnique u ses rad i a t io n test d ata and the dimensions
of an array (SRAM or FPGA) to statistically determine which SEUs in the test
data are M CUs. This process invol v es thes e st e ps:
1. Collect SEU data with radiation testing and organize upset data into
logical addresses,
2. Determine the logical distances between SEUs a nd c reat e a histo gram
of common upset pairs,
3. Create phys i cal adjacency model from statist ic al data, and
4. Extract MCUs and MBUs from the SEUs using the physical adjacenc y
model.
These st eps will be discussed in more detail in the followin g s ection s.
4.4.1 COLLECTING SEU DATA
The first st ep i n this p rocess is t o collect S EU d at a fro m s tatic r a diat i on
test ing. In m any ca ses th e S EU da t a col l e ct ed f or th e S EU cros s sectio n can be
used for MCU analysis. However, it is important that the numbe r of S EUs in
each readback of the component is kept low so that CSEUs do not
contaminate the data. Collecting SEU data for MCU analysis req uires either
many short beam runs for static test methodologies or using a

63

dynamic/semi‐dynamic m ethodology t hat allows f or frequent full component
readouts.
To p erform p hysical adjacency an alysis, the indiv i dual u pset da ta m ust be
repres ent e d in s ome t w o dimensional form. F or e xample, in F PGA s the x‐
dimensio n is defined b y the nu mber o f configur atio n frames a n d the y‐
dimensio n is defined b y the number o f bits i n the frame. A SRA M could use
the number o f words for the x‐di mensio n and the number o f bits in the word
as the y‐dimension. This coordinate system does not necessaril y r e pr e sen t
any physical o rganiz ation and is u sed primar ily for bounding t h e loc a tions o f
the SEUs. It is not nec essary for th e 2‐D array to be square, as t h i s ar ray does
not need t o have a o ne‐to‐one c o rrelat i on w ith the p h ysical l ay out of t he
component.
For this work, an upset ui is r epresen t ed a s a (xi, yi ) tuple, w here x
corresponds t o the frame number l ocation of t he u pset a nd y corresponds to
the bit number of the upset within the frame. A similar proces s is p ossible
using the n u mber o f words and the word size for trad itional SRA M array s.
Figure 18 demonstra t es six different u psets labeled using this coordinate
system. U p set u1 which is denoted by the box with the number “1,” indicates
an upset in frame #2 (x1 = 2 ) and bit #3 within this frame (y1 = 3 ).

64

FIGURE 1 8: F PGA U P SET C OOR DIN A T E S YSTE M AND U P SET L A B E LI NG
4.4.2 IDENTIFYING UPSET PAIR OFFSETS
Once the SEUs from a test have been converted into (x, y) coordinates in t he
2‐D array, it is possible to determine the upset pair offsets a nd i dent if y
common upset patterns. P atterns are identified b y comparing ea ch S EU
location to all other SEU locations in the list. During this p rocess for a list of
N SEUs, N(N ‐1) distinct upset pairs are evaluated. The example in Figure 18
contains 15 unique upset pairs that must be evaluated. An upse t pair, UPi,j, is
represented as an ordere d set of two upsets, (ui, uj ).

65

To i dentify common co ordinate o ffs ets between upset pairs, t he upset pair
offse t UPOi,j is computed for each upset pair :

,∆ , ∆
,
,

, ( 1 )
for all upset pairs where i ≠ j . F or e xample, the upset pa ir o ffs et f o r u1 and u2
in F igure 1 8 i s UPO1,2 = (2 – 1, 2 – 3) = (1, ‐1). To ensure that there is only a
single upset pair offset for each pair of upsets, the upsets ar e ordered using
the following convention: if xi > xj , then ui > uj . I f xi = xj and yi > yj , then ui > uj .
Upset pairs, UPOi,j , are creat e d such that ui < uj .
Computing all of the upset pair offsets for large 2‐D arrays wi th a l arge
number of SEUs may not practical, depending on the size of the device. The
maximum number of upset pair off sets for a given 2‐D array is d efin ed as:
| | 1 ∗2 | | 1 1, (2)
where |x | and |y| are the dimensions of the 2‐D array. For the example of
Figure 18 w h ere |x |=10 a n d |y|=1 0 , the number of un ique upset pair offsets is
171. For the Kintex‐7 F PGA, w here |x |=22546 and |y|=3232, t he m aximum
number o f unique u pset p air o ffs ets is 1 47,708,335, m aking it impractical t o
calculate ev ery upset p a ir offset.
To simplify the computatio n of u pset p air o ffsets, o nly a small subset of
upset pair o ffsets is c onsidered. B ased o n previous F PGA test r esults, we
assume t hat physical a djacency i s most l ikely with c onfiguratio n bits with
relatively close frame numbers and bit numbers. The upset offse t v a lues t hat

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will be sear c hed are limited by a f rame d ista nce an d bit offset dis ta nce of 3 2
as follows: 0 ≤ x ≤ 31 and ‐31 ≤ y ≤ 31. This restriction limits the upset
pair offset s e arch space to 1,891 upset pairs, a m uch more trac table n u mber.
Once all of the pair upsets are determined from the SEU test da ta, a
histogram of a ll the offset p at tern s is c reat ed . I n the ex ample of F igure 18,
there is one upset pair offset with more than one count: ( x = 1, y = ‐1) = 2.
This u pset p air o ffs et ( x = 1, y = ‐1) is seen by the following upset pairs:
(u1, u2 ) and (u5, u6 ). The increased prev a l ence o f this u pset p air pattern
suggests it r epresents physical adjacency.
4.4.3 CREATE PHYSICAL ADJACENCY MODEL
Aft e r collecting the ind i vidual b it u pset data and t a bulating t he h istogram
of u pset o ffset counts, the upset pair offsets will be analyzed and used to
build a physical a djacency m odel. S pecifically , a physical a dj acency m odel i s
creat e d by s electing s pecific up set offsets and tagging such o f fsets as
“physically adjacent.” If a particular upset pair offset repre sents physical
adjacency and MCUs o ccur with t his upset offset, this p articula r o f fset w ill
appear i n t h e upset offset h istogr a m m ore frequently t han offse ts t hat do n ot
have physical adjacency. For example, if the upset offset ( x, y) = (0, 1)
corresponds to physical adjacency and MCUs occur between SEUs w ith this
offset then this offset will appear in the upset log with a far h igher fr equency
than upset o ffsets that d o not corr espond to physical adja c ency .

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If no MC Us occu r in a r adia tion t es t and the upsets occur unifo rmly ov e r the
array, t hen each u pset o ffset should appear w ithin the ra diat io n tes t data at
constant rate. If a specific upset offset corresponds to physi cal adjacency
then the upset offset rate will be much higher than this constant upset rate.
Those upset offsets that d emo n stra te t his higher r ate are chose n as
“physically adjacent” offsets. Any configuration upset pair that m atc h es t his
particular upset offs et w ill be iden t ified a s a MCU.
4.4.4 MCU AND MBU EXTRACTION
Aft e r the p h ysical a dja c ency m od el h as b een identified, discret e M C Us c an
be c reat ed b y comparing all pairs of u psets within i nd ividual r uns of t he
radiation test data. Any upset pairs observed in the radiation t est d a ta t hat
matches one of the chosen “adjacent” pairs are assumed to be ca used b y the
same p artic l e and are c o mbined t o form a single 2‐bit MCU. F or example, if
an upset pair offset of (0, 1) has been tagged as “physically a djac ent,” any
upset pair that matches this ups et o ffset will be combined into a 2‐bit MCU.
The process of c reatin g MCUs f ro m individu al S CUs continues it e rat i ve ly t o
build larger a nd l arger MCUs t o cr eat e m axim ally sized c lusters. Initially, the
offset o f all upset pairs are compar ed t o creat e 2 ‐bit M CUs fro m the full set of
discrete configuration upsets. Next, all 2‐bit MCUs are compar ed a gainst
other SCUs t o see if t hey ar e phys ically a djac ent. I f thes e MCUs are bridged
by an upset pair, they are combined to form a larger MCU. This process
continues u n til no M CUs conta i n upsets t hat are physic ally a dja cent t o any

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individual upset in the test data. This algorithm similar to t he a lgorithm
described in [58] to group adjacent upsets into larger M C Us.
To illustrate this process, the upset map of Figure 18 will be used w ith the
chosen adjacency coordinates to demonstrate how MCUs are cluste red. F irst
u1 is c ompared to u2 and an u pset p air offset m atch i s fo und (1, ‐ 1 ) . T h e s e
two upsets are grouped into a single MCU. Next, u1 is c ompared to u3 and
again, the upset pair offset match (1, 1) is found. This upset i s added to t he
MCU. When u1 is t hen compared t o u4, u5, and u6, no adjacencies are found.
This p rocess continues by c omparing e ac h upset in s orted o r der to a ll
remaining upsets t o itera t iv ely form l arger MCUs. T hree d i stin ct u pset
even ts w ill be i dentified w ith the physical a dj acency m od el d es cribed a bove:
(u1, u2, u3 ), (u4 ), and (u5, u6 ).
The ext r act e d MCU da t a can also be used to identify independent MBU s. An
MBU is extracted from the MCU data when more than one upset from the
same MCU is in the same frame. For example, one MBU will be ex tracted
from the MCU events of the example in Figure 18. Three upsets ar e seen i n
frame 3 of t his upset map: u2, u3 , and u4. Two of the upsets belong to the
same MCU: u2 and u3 . B ecause u psets u2 and u3 belong to the MCU, they are
iden tified a s an MBU i n frame 3. B ecause u pset u4 i s not associated w ith an
MCU, it is classified a s a n ind epend e nt SCU.

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4.5 V ALIDATION OF TH E PHYSICA L A DJAC ENCY M ODEL
Accurately e xtr acting M CUs from e xisting S E U data c an b e a chal lenge.
There can be a n umber of i ssues i n which uncert ain t y can be i ns erted into
the process. For this technique, there are two sources of unce rtainty:
 CSEUs in the data set, and
 Lack of physical layout informa t ion .
The firs t source o f uncerta i n t y needs to b e addressed through e xperiment a l
test methodologies. The second source of uncertainty is quanti fied b y
comparing results to a k nown data set.
4.5.1 COINCIDENT SINGLE ‐BIT UPSETS
CSEUs are caused by allowing too many SEUs to accumulate in the SRAM
array or FPGA before reading out the results. As the number of SEUs
increases, the probability of constructing an MBU from two exis ting S EUs
increases. Estimat ing the probability of a C S EU is a n importan t pa rt of the
test des ign process, a s exper i ment ers might need t o limit eithe r the exposure
time or the flux to keep the SEU rate below a c ertain level for MCU extraction.
In [ 67], the authors discuss meth ods for estimating C SEUs b y an aly z ing the
shape of MBUs, analytically and through Monte Carlo simulations , which lead
to the use of Monte Carlo simulations in [58, 66] to estimate t he p robability
of C SEUs. I n [68], th e author a d d resses the problem statistica lly u sing a n
ext e nsio n o f t he w ell‐k n own birth day p roblem. I n this p aper, M onte C arlo

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experiments and the equations from [68] provide bounds on the b ias from
CSEUs.
The Mont e Carlo exp e riment w as d es ign e d to b e paramet e r i z e d with
variables for the shape of the 2‐D array, the number of SEUs pe r trial and the
number o f trials. F or o ur e xperiment, w e chose the shape of t h e Kint ex‐7
two‐dimensional array (22,546 frames, 3,232 bits per frame). A variety of
values were chosen for the number of SEUs per trial to determin e how the
CSEU probability changed as more of the 2‐D array was upset. T he Monte
Carlo exp e riments w e re r un f or 1 ,600,000 trials f or s tatistical s ign i ficanc e.
From [68] we used eq u ation 17:
, 1
, (3)
where n i s t h e number o f bits i n the 2‐D array, k i s the collision ra nge (set t o
31) a nd p is the number of upsets. Both of these methods were used to
determine the probability that a given trial has CSEUs. The Mo nte Carlo
exper i ment s are also used to deter mine chara cteris tics a bout th e CSEUs, such
as the expected number of CSEUs in a trial.
The probabilities calculated b y the Monte Ca rlo experim e nts a n d [68] are
shown in F igure 19. N o t only d o t h ese t e chniques s how a good c orrelation t o
each other, the output shows the effect of accumulating SEUs. This f igur e
shows that w hen SEUs c omprise 0.00137%–0.01372% o f the array, t he
probability of h aving a trial with a C SEU goes f rom 5% t o 99%. Figure 20

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shows the histogram of CSEUs per trial. These figures show that when t here
are very few SEUs in the array, the probability of a CSEU is lo w and the
probability that a trial has more than one CSEU in a trial is very low. As SEUs
accumulate in the array, the probability of CSEUs will increase rapidly and
non‐linearl y . F or t his exper i ment , this p roblem i s negligible due to l ow l imits
on the number of upsets per trial.

FIGURE 19: PROB A BILITY OF A CSE U AS A FUNC TION OF THE PERCE N TA G E OF T HE A RR AY
THAT H AS S CUS

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FIGURE 2 0: H ISTOG R AM OF COI N CI D E NT S BU S P E R TRI A L WHEN V ARYING TH E TO T A L
PERCEN TAG E O F TH E DEVI CE BIT S T H AT IS UP SET
4.5.2 VALIDATION WITH PHYSICAL LAYOUT
While this p aper d iscusses the re sults of K intex‐7 radiation te st ing, o ther
FPGAs were previously analyzed for MBU and MCU effects as well. Historical
data set s of th e 65 nm Virt e x‐ 5 FP GA were av ailable to validat e th e eff icacy of
the technique. The MCU results for the Virtex‐5 were published in [66]. For
the proton data set in t hat paper, t he MCUs were e xtr acted usin g a tool t hat
was design ed u sing p ropriet ary informat ion from X ilin x. T he c o mparison
between th ese two too l s is p resen t ed i n Table 3. T hese r esults show that our
technique is accurate to within 2%–28% of results from the actu al p hysical

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layout. F urthermore, t h e techn i que properly r ecogniz e d that t h e co mponent
did not use bit interleaving.

TABL E 3: C O M P A RI SO N OF V AL I D ATI O N

4.6 MCU R ESULTS FOR 28 NM SRAM‐B ASED FPGA
The following s ec tions will describe the MCU analysis for irradiatio n o f the
28 nm Kintex‐7 device. The following sections will describe th e steps
describ e d i n S ect i on 4. 4 u sing dat a ob tai n ed f rom th e i r r a dia t ion described in
Chapter 3.
4.6.1 OBTAINING SEU DATA
Specific t est runs f rom t h e irr a diation studies in C hapt er 3 w e re u t i li ze d f o r
this analysis, all of which were at normal incidence, ambient temperature,
and normal v oltage b iases. I n order to m inimize the pres ence o f CSE U s, e ach
run was read b ack continuously t o ensure l ess than 500 ups e ts were
observed for each read through the memory. Any run that contai ned more
than 1000 upsets were remo ved from the analysis.

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4.6.2 CREATING THE PHYSICAL ADJACENCY MODEL
The ind i vid u al upsets collected d uring radiation testing were u sed to create
a physical a djacency m odel o f th e Kint ex‐7 c o n figur a tio n m emory. Using the
procedure described earlier, a ll upset pairs for each i ndiv idua l run were
analyz ed a nd c ounted t o ident i fy h igh probability upset offset pairs. To limit
the search space, pairs are upsets w ere only c onsidered with a frame
distance o f 32 or l ess ( i .e. x ≤ 32) and a bit number offset of 32 or less (i.e.,
y ≤ 32). The count of all upset pairs in the complete data set i s su m m a rized
in Figure 2 1 .

FIGURE 2 1: O CCUR R E N C E OF U PSET OF F SET P A I R S

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A wide variety of upset offset pairs are seen in the data set. However,
several upset offset pairs were seen with far more frequency th an o the r s.
The most common upset pair observed was (1,‐1), or a pair of co nfiguratio n
bits i n adja cent f r a mes (i.e. x = 1) and where the bit offset of the second
upset is one less than the bit offset of the first upset (i.e. y = ‐1). This c learly
suggests t h at some form o f fr ame in terl eaving i s being per f orme d –
configura t ion bits i n s e quential f r a mes ar e physically a djacent t o maximize
the benefits of the SECDED ECC. Other upset offs et pairs that occurred w ith a
high frequency include (0, 1), (1, 1), and (1, 0). All four up set patter ns o ccur
with a much higher frequency than other upset patterns and are sel e cted a s
“physically a djacent.” These four p atter n s are summarized gr aph ically i n
Figure 22 and are us ed to extr act MCUs from the upset d a ta.

FIGURE 22: HIGHES T PR OB A B ILITY UPS E T PA IR S (F R A ME OF F S ET )
4.6.3 EXTRACTING DEVICE MCUS
The physical a djacenc y m odel described earlier was used to extr act MC U s
from the upset data collected in the radiation tests. Our appr oach w as
applied to the upset list from each readback file. The result of t his process

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was to group individual upsets into MCUs using the adjacency mo del and to
identify the remaining upsets as SCUs. The majority of events were S CUs but
a number o f MCUs w ere found. T able 4 summarizes the top nine MCU
shapes t hat wer e e x t ra cted d uring this p roces s ( including the s ingle‐bit SC U
“shape” of one). This table lists the percentage of shapes ext ra ct e d f or e a c h
ion used during radiation testing. The total number of shapes e xtra c te d is
summarized in the last row.
T A BLE 4 : PE R C E N T A G E O F M CU S HAP E S E X T R AC TE D FO R EA CH I ON

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The sizes of e xtrac ted MCU ev ents a re p lotted in F igure 2 3 a s a function of
LET and MCU siz e . A t low LETs, only a small percent a ge o f events are MCUs.
As the LET increases, the percentage of SCUs decrease and the M CUs
signific antl y increase. W ith only 100‐500 upsets p er r u n , the conta m inat ion
from CSEUs is quite low. The expected number of CSEUs erroneou sly
counted as MCUs for th is data is between 0.0006‐0.062. I n comp arison t o the
experimental error, which is calculated using 95% Poisson confide nc e
int e rvals, th e contr ibution to t he error from CS EUs is negligib le.

FIGURE 2 3: MCU SIZ ES A S A PER C EN T A GE OF TH E TOT A L OB SERV ED MCUS AS A
FUNCTION OF LE T

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4.6.4 MBU DATA ANALYSIS
As described earlier, MBU events for FPGAs correspond to an SEU event
causing mo re tha n on e cell to ups et with i n a c onfigura t io n fr am e. M B U s re fer
only to the upsets of an MCU event that occur in a single frame. Under
normal c ircumstances, MBU events a r e r el ativ ely eas y t o iden tif y in t h e
FPGA. These events are identified by performing a configuratio n re adback
on a frame and comparing all bits of the frame against the corr esponding
golden configuration frame. If the number of bit differences i n the frame is
grea ter tha n one, the event is class ified as a n MBU.
The sizes of e xtrac ted MBU events f or t he K intex‐7 are plotted in F igure 24
as a function of LET and size. As with MCUs, at low LETs most of the events
are SCUs ( 99.23% a t 1. 5 MeV‐cm
2
/mg). A s the LET increases, t he p ercentage
of MCUs and MBUs increase, but the percentage of MCUs is always higher
than MBUs. At the high est tested L ET (60 MeV‐cm
2
/mg), 38.1% o f th e events
are classified as an MCU while only 29.5% of the events are cla ssified as
MBUs. This result suggests that interleaving is used to improv e the SECDED
memory protection o f indiv idual fr ames.

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FIGURE 24: MBU S IZES AS A PERCEN T A GE OF TH E TOT A L OB SERV ED MB U S AS A
FUNCTION OF LE T
It is im p ort ant to not e th at th e re a re f ewe r M B U eve nts t h an MCU ev ents, as
MCUs c an r epres e nt e vents that m ay span multiple l ogical f rames. When
view ed a s MBUs, thes e ev ents a r e split u p into m ultiple dist inc t eve n ts e a ch
in a logical frame. These results suggest that interleaving ce lls b etween
frames i s effec t iv e and that t he i ntern a l SECDED c oding scheme ca n repair
more MCU events by breaking suc h event s in t o multiple MBU events.
4.6.5 MCUS AND TECHNOLOGY SCALING
It is interesting to compare the MCU and MBU behavior of the 28 nm
Kint ex‐7 a gains t o lder X ilin x F P GA f amilies. F igur e 25 c ompare s the

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percent a ge o f ev ent s t hat cause MCUs ( mor e t ha n on e bit upset) for sev e ral
differ ent fa milies. T h e M CU d at a for the V i rtex‐5 ( 65 nm, UMC), Virtex‐4
(90nm, U M C ), V irtex‐II (150nm, U MC), a nd V irtex (180nm, U MC) te chnology
nodes was obtained f rom [69]. F or a ll f amilies, the percent a ge of MCUs
increases with higher LET values [58, 66]. The dotted line rep resents the 28
nm Kintex‐7 MCUs as a percentage of observed events. As seen in t h is g raph,
the 28 nm F PGA is m ore sensitive to MCUs at l ow L ET. A s the en er g y
increases, the MCU rate tracks the older Virtex‐II‐series FPGA sugges t ing that
the manufacturer i nvested add i tio n al e ffort to p rotect t he c onf iguration cells
from M CUs in t his smal ler proce ss geometry. T he d ashed line r e pr es ents 2 8
nm K in tex‐ 7 MBUs a n d h ighlight s the adva ntag e of c onfigur a tio n memory
interleaving. By interleaving the configuration memory, the ef fect i v e MBU
rate i s lower than all but the Vir t ex‐I FPGA family.

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FIGURE 2 5: MCU EV E NT S AS A P ER CE NTA G E OF SE U S FOR FIVE XILINX F PG A F A M I LIES
4.7 S UMMA RY
The purpose of i dentifying M CU i s important to i mprove t he a ccu racy o f
space erro r rate p redictions. T his chapter presented researc h which
provides a n ew s tat i st ical m ethodology t hat ident i fies t he p res ence o f MCU
following the irradiation of a SRA M‐based device. The MCUs are identified by
firs t identifying memory l ocations t hat are physically a djacent on the silicon
die. Then, clusters o f physically a djacen t upsets a re g r o uped together i nto
MCU pat t er ns. T he t echnique w as v alidat ed b y showing relat i ve a g reement

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with MCU information obtained on 65 nm technology with assistan ce f rom
the manufa cturer.

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C HAPTER 5

5.1 M EASURIN G S ENSITIVE V OLUMES WITH R O T ATIONAL D EPE N DE NCE
This c hapt er i nves tig a tes an a p p lication o f the rot a t i onal dep e ndenc e
observed following angular studies in 28 nm and 20 nm FPGA tech no logies.
Rotation al depend e nc e refers t o a change i n the device r esponse for a fixed
tilt angle by changing the rotation angle of the beam, for irra diatio ns a way
from n ormal incid e nc e. R otat io nal depend ence h as b een r elat iv e ly r are,
enough s o such t hat standardized t esting p rocedures define c omm on
practice to test at normal incidence with only a cursory check to e nsure that
no a ngular depend e nc e is p res e n t [70]. D espite t h i s, dep endenc e on r otation
angle is s till occasionall y o bserved when i rrad i atin g a t t ilt e d a ngles [ 71]; one
such example taken from [72] is shown in Figure 26, which shows a polar
plot of cross‐section at varying rotation angles, at a fixed ti lt a ngle, for the
irradiation of a DRAM with strong dependence on rotation angle. A possible
reason f or t his may be w ell orien tation o r layout c ell dimensions t hat favo r
one ax is. S tudies f rom [73] h ave ident i fied s ensit i ve v olume r egio ns w ith w

84

much l arger than l , thus c onfirming the exis tence of s u c h possible layout
parameters .

F IGURE 2 6: A N EX A M PL E O F TILTE D DR AM IR R A DI AT ION WITH VA R YING R OT AT ION
ANG L ES

Through the studies p erformed i n Chapter 3, p ro minen t r ot ation a l
dependence has been observed in both 28 nm and 20 nm Xilinx FPG As [11 ,
12]. Though often described as a n undesired effect t hat hinder s data
collection, r otat ional depend enc e c an a lso provide some m easure of
informa t ion about the sensitiv e v o lume [74]. I n part ic ular, th e ro tatio n al
dependence observed in the 28 nm and 20 nm Xilinx FPGAs may now be
p r om inent enou gh to deriv e th e di m ension s o f th e rect a n gu l ar p a rallelepiped
(RPP) sensitive volume.

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This c hapter p resen t s a novel method t o approximat e the dimensi on s of a
sensitiv e v o lume g iven t he a ngu l ar r espons e a n d rot a tional d epe ndency
observed i n the dev i ce. T hese m easurem e nts can t h en b e applied to
standard space error rates models (in lieu of standard practice s which
grossly ap proximate measurements f ro m saturated cross‐sections) to
improve t h e accuracy o f rate p redictio ns o n orbit, w here i ons a re
omnidirectional and may strike the device from any angle [9, 25 ]. T his can
also b e used a s a bounding t erm for the wor k i n Chapt e r 6 when attempting
to e xt rapolate d ev ice r e sponse f or i ons incid e nt t o o n e o f t he si de f ace s of a
sensitiv e vo lume.
5.2 P RIOR WORK
In o lder t echnology nodes, t he o verall shape of t he c harge coll ection
volume was of less concern, since the dimensions of the volume were f airly
disproportionate; the l e ngth a nd w idth o f th e sens it ive volume were m uch
larger t han its relatively s hallo w depth. A s such, approximating the sensitive
volume b y taking t he s quare roo t o f the saturated c r oss‐section has been
sufficient practice for many years [25, 74, 75] and the need fo r accurate
measurements o f s e ns itive volumes has been m inimal. T his is n o longer the
case for these FPGAs that exhibit strong dependence to an ion’s rotation
angle.
Others t ech n iques for measuring sensitiv e v o lumes have b een dev eloped
and t e st ed o n var i ous memory d evices. [ 76] a nd [7 3 ] utilize pu lsed l aser

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test ing tech niques t o measure both t he b ounding dimensions a nd sensitive
volume depth of various memory arrays. [77] produces a method that
measures sensitive volumes for devices whose effects scale with dose and is
primarily t a rgeted f or m easuring sensit i ve v olumes i n floating‐ gate f lash
memory d evices. [ 74] a pplies a m odified t e chnique to t h a t desc ribed in [ 78]
to measure charge collection depth, but this only provides info rmation about
depth, a nd r elies o n assumptions regard ing the length a nd w idth of the
sensitiv e vo lume.
The ben e fit to t he m ethod proposed i n this w o r k is t he a bility to o btain this
data using heavy‐ion studies, which are common practice when
characterizing c ommercial parts for space. A ll three d i mensio n s of t he
sensitiv e v o lume a re a pproximat ed, rather t han just t he depth. Also, laser
testing is not often included in a standard device characteriza tion p rocedure,
and part p reparation f or l aser t esting i nvol ves difficult steps such as die
polishing (for f lip‐chip d evices ). The technique proposed h ere i nv olves no
additional p reparation b eyond th at r equired for standard h eavy io n testing ,
and data can be obtained at the same time as any other angular heavy io n
studies that may be conducted.
5.3 P ROPOSED T ECHNIQUE
The following s ub‐sections describe t he t echnique u sed to m easu re t he
sensitiv e v o lume u sing a ngular h eavy‐ion irradiat ion studies. The work
described here i ncorporates so me s tandard general i zations ab out the

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sensitiv e v o lume t hat is b eing m easured. The sensit iv e volume is d escribed
as a RPP volume: a volume with a rectangular top of length l and width w
extruded to some depth h [79]. I f charge dep osited i n t o the sensit iv e volume
by a n ion tr ack exc eeds a critical charge threshold (Q crit ), a s ingle‐event upset
will occur.
Although there may be multiple sensitive volumes associated wit h one bit
cell, these sensitive volumes are lumped together into a single sensitive
volume that represents the combined sensitivity of each individ ual volume .
Th is assu m p tion ca n b e m a de as g r ou p i ng th e sens i ti ve v ol u m es t ogether will
yield the worst case; an ion traveling through a single volume will have a
longer ion track than if it were traversing one of several smal ler ind e penden t
constituent volumes.
5.3.1 DATA COLLECTION WITH ROTATIONAL DEPENDENCE
In o rder t o apply this p roposed technique, i t is n ecessa ry t o o btain three
key rot a tio n ally depen dent d ata p o ints: ( 1) n ormal incidence, (2)  R = 0°,
 T = 60° (or less, if ion range is limited), and (3)  R = 0°,  T = 60° (again, less
if constrained by ion range). The LET used for irradiation should be high, if
possible; i d e ally t he c r o ss‐section obtained a t the chosen L ET would match
the saturated cross‐section of the device. This ensures that the
measurements o btain e d through this t echnique y ield a worst‐ca se value,
thus return i ng cons e rv ativ e appro x imatio ns.

88

The next step i s to p rocess the removal of M CUs from t he d ata s et. T he
techniques described i n Chapter 4 can be uti lized for this p urp ose: building a
physical adjacency model and then isolating MCU clusters will a llow r e moval
of these events. The removal of MCU is important as MCUs will ar tificially
infla t e the cross‐sectio n of t he a n g ular strikes. T he r es ponse of the device
should b e measured b y its susceptibility t o ionizing e vents and not by how
many cells can be affec t ed by a single ion.
5.3.2 ALGORITHMIC DERIVATION
For the following s ection, σ eff‐0 represen ts t h e c ross‐sec t ion o f t he devic e
irrad i ated a t  T when  R =0° f o r  T > 0°, and σ eff‐90 represents t he c ross‐
section of t he device irradiat ed a t  T when  R =90° f or  T > 0°. σ n is the
cross‐sectio n observed a t normal incidence w hen  T = 0°.
This algorithm evaluates the three irradiation studies performe d in t he
previous step. The basis for measuring the dimensions of the R PP i s founded
on the observed cross section for each angle. Figure 27 illustrates the cross‐
section obs e rved b y t h e three ir radia t ion s. ( A) i s the typical c ross‐section
observed b y ions s trik ing the RP P at n ormal incidence. (B) sh ows t h e cross‐
section r e p r esented by σ eff‐0 , and its overall size i ncludes contributio n s from
both the left and top faces of t he R PP as pic tured. (C) shows the cross‐section
repres ent e d by σ eff‐90 , which is c omprised o f contributio n s from t he r ight a nd
top faces of the RPP. It is important to remember that one of th e
requiremen ts i s the use of h igh LET ions – t his ensur e s that a n ion that

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passes thr o ugh any a m ount o f t h e sens itiv e volume w ill cause an upset.
Without this a ssumption, calculation of t he t rack l ength would be r equired
through the sensit iv e volume t o ensure t hat charge g reater t han Q crit was
deposited, w hich can unnecessarily complicate matters.

FIGURE 2 7: CHANGE I N C R O SS‐ S EC TI ON B ASE D O N I O N P E R S PE CTI V E

Measurin g the dimens ions o f the sensit iv e volume r elies o n prin ciples
described by t he c osine law [80], which also f ormulates the fou ndat ion for
the concept of “ effectiv e LET.” E ffectiv e L ET i s gener a t e d by irr a diatin g a t
angles o f in cidence such that  T > 0°, wh i ch exten ds th e l e ngth of an ion tr a ck
through the RPP. S in ce t he d eposited e nerg y is l inearly propor tional t o the
track length through the RPP volume, the net result is a higher effective LET,

90

compared t o the nominal LET that t he i on w ould h ave impar t ed i n to t he
volume at normal incidence. The new effective LET is inversely p roportional
to the cosine of the angle, as shown below in (4):
°
, (4)
When irradiating at normal incid ence, the ef fective LET is n ot modified b y
the angle (since c os 0 ° = 1), and thus t he c ross‐section area available for a
normally i n c ident ion t o strik e is s imply the a r ea o f the t o p “face” of the RPP,
or:
∗, (5)
However w h en i rrad i ating at a ngl e , the observable c ross‐section “seen” by
ions st r ik in g the d e vic e i s lar g er a s more t han one face o f the R PP i s exposed.
As m ention ed i n the previous sub‐section, hig h L ET i ons near t h e saturatio n
are desired; part of the reason is to remove the need for consi deration o f the
amount of charge imparted into the sensitive volume. If the LE T is
sufficiently high, any ion contacting the RPP should cause an u pset a nd
consider ation of Q crit and effective LET can be ignored. At angle, the area
exposed to i ncid ent io ns c an b e c a lculated a s illustrated in F i gure 2 8, w hich
views the RPP incident t o one of th e side faces:

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FIGURE 28: CA L CULATION OF E FFEC T I V E CRO S S‐ SE C T I O N F O R A N A NG UL A R IO N STRI K E

Thus, when irradiating at angle, when the bottom line in Figure 28
repres ent s l (meaning t he w dimension goes into the page), the cross‐section
is det ermin e d as:

∗
, ( 6 )
Similarly, w hen view in g the RPP incident t o t h e other side f ace , wh ere the
bottom line in Figure 2 8 represent s w :

∗
, ( 7 )
The dimen s ions of h1 and h2 can be trigonomet r ically det ermined:
cos, (8)

92

sin, (9)
Thus, the effec t iv e cross‐sectio n observed b y the ion strik i ng at angle is
equal to the following:

∗ cos sin, (10)

∗ cos sin, (11)
These equations d e rived here f orm an a ltern a t e a rr angement o f t he
equation g iven i n [79], which was used t o correct m easu rement s taken using
the in vers e cosine l a w c oncepts . H ere, w e ext e nd t he a pplicat i on o f the
equation t o form a s ystem of t hree equations with ( 5), (10), an d (11),
yielding t hr ee unknow n var i ables repres ent i n g t he i nd ividual di mensions o f
the RPP. This allows us to solve for the individual dimensions of the RPP
model. Thus, continuing down tha t path, we rearrange (11) to y ield:

, (1 2)
Substitution of (12) into (10) yields:
∗

, (1 3)
Finally, combining (13) and (5) allows us to solve for one of t he dimensio n s
of the RPP:
∗

, (1 4)

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The data o b t ain e d from i rrad i at ion studies i n t h e previous sect ion can now
be used to progressively solve (14), (13), and finally (12). S olving t hese
series o f equations will provide the ap proximate dimensio ns o f the
abstracted s ensitiv e vo l ume for the memory cell at that p a rticu lar LET.
5.4 EXAMPLE A PPLICA T ION
This technique was demonstrated on data from the 28 nm Kintex‐7 FPGA
obtained f r o m the irra diat ion stu dies descr ibed i n Cha p ter 3. The Kint ex‐7
was irra dia t ed w ith 10 M eV/µ x en on a t a nominal LET of 49.3 MeV ‐cm
2
/mg.
Following each irradiation, the memory contents were read out o f the dev i ce
and a physical a djacen cy m odel d eriv ed f rom the upset bits ( as de scr i be d in
Chapter 4). This model was used to derive the MCU patterns in the device,
and allowed the data set to be collapsed into an event map, whe re e ach event
repres ent e d a single i onizing st rike t hat affected t he device r espon s e. T he
raw data and the number of extrac ted events are shown below in Table 5.
TABLE 5: S UM MARY OF ANG U LAR STU D Y WITH 1 0 M E V / U XE NO N

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5.4.1 APPLICATION OF THE MEASUREMENT TECHNIQUE
For the purposes of this application, the data at the following a ngl e s was
used: (  T =0°,  R =0°) , (  T =50°,  R=0°), and (  T =50°,  R =90°). Thus, the
input parameters are:
σ n = 2.42 x 10
‐9

σ 0 = 5.01 x 10
‐9

σ 90 = 4.49 x 10
‐9

 = 50°
Applying these values to (14), (13), and (12) result in the fol lowing
measurements (erro r calculated u sing two s ta ndard d e via t ions):
l = 0. 533 ± 0.060 µm
w = 0. 454 ± 0.048 µm
h = 0.846 ± 0.095 µm
These est i mates appear t o be r easonable, a s the charge c ollection depth is
within t he a pproximat e rang e sug g ested by [81], bounded by 0 .5 µm for SOI
to 1 µm or more for bulk, and with length and width parameters on p ar with
other meas urements t aken a t this technology node.
It is interesting to see that the assumptions that were once made about the
RPP dimensions no longer hold in this 28 nm technology node. A s one

95

example, t h e R PP dep t h was often consider ed t o be t he smallest dimensio n
[82]. A no ther i n t er esting e xam p le i ntrodu ced by device scalin g is the
discovery that angular strikes may actually now result in the l east
susceptibility, improving cross‐ section compared t o no rmal i nci d e nce [16,
83] – a n int e res t in g change f rom larger f ea ture‐size t e chnologi es, w h ere the
opposite w as t rue and angular st rikes alway s g ener ated h igher s usceptible
cross‐sectio ns when co mpared to normal incidence i rra d i at ion.
5.4.2 EFFECTS OF MEASUREMENT ON SPACE RATE ESTIMATES
Industry t o o ls, such a s CREME96 [9], calculate space ra te e st im ates a lso
using the RPP model. The sensitive volume dimensions are utili zed i n t ha t
calculation through t h e Integral R PP method, where the SEE rate is
calculated f rom a numerical int e gra t ion o v er t he L E T ‐depend e nt cross‐
section [ 82] around the device.
The sta n da rd a ssumption w hen R PP informa t ion is n ot a vailable i s to t ake
the square r oot o f the saturated cross‐sectio n to f ind th e w and l d imensions,
and assume h based on the type of technology (for bulk CMOS, usually 1 µm)
[74, 82]. In the example above, w = l = sqrt(2.42 x 10
‐9
) = 4.92 x 10
‐5
cm , and h
is assumed at 1 µm. This results in a failure rate estimate of 4 .997 x 10
‐9

upsets p er b it, per day, u sing s tandard ap proximatio n methods. When
compared t o a rat e p rediction usin g the appro x imated d imensions calculated
in this chapter, the estimate calculated using the IRPP model i s 5.792 x 10
‐9

upsets per bit, per day – an increase of almost 16%. Thus, thi s method o f

96

measuring RPP can produce modera te i mprovement i n resu lts using
available rate e stimation tools. T his metho d w ill also a ssist in b ounding
variables for the fault model generation proposed in Chapter 6 for the
consider ation of angul ar ev e nts.
5.5 S UMMARY
This c hapt er d escr ibes a n ew m ethodology t o mea s ure the c o llect ed
sensitiv e v o lume o f a memory c ell using angular irr a diat ion data. The
algorithm provided h er e can be u tilized to e st imate the relativ e d i mensions
of the RPP when inputting data into CREME96 or SPENVIS for rate
predict i ons. H owever, perhaps a more u seful application is t o ap ply the
dimensions of each side of the RPP as a bounding limit for data e xtr a polation
performed in Chapter 6. That application will be discussed mor e in t he n ext
chapter.
It i s important to n ot e that t his technique is desig ned for mod ern scal e
electron ics. A t larger t echnology nodes, dev ices a re n ot e xpec te d to show a s
much dependency on rotation angl e, s ince s ensitiv e v olumes w ill l ikely b e
much wider and longer than they are deep. This will reduce the ir r esponse
to r otational effects as t he e ffective cross‐section will be d o minated by o ne
face o f the RPP and the contrib u tion f rom the d e pth of t he v ol u me i s
signific antl y less than f or modern feature s i ze devices.

97

C HAPTER 6

6.1 A FAILU RE ESTIMATIO N MODEL I NCORPORATING ANGULAR EFF EC TS
Estimating t he e rror rate f or s pace e lectronics i s extremely im portant to
spacecraft d esigners. A s technol o gy s cales shrink, pro d ucing a ccurate o n‐
orbit error rate e st imates i s beco ming i ncr e a s ingly diffic ult d ue t o c h anges in
error s i gna t ures [84]. I n particul ar, heavy‐ion events h ave in creasing M CU
rates due to c harge sharing [8 5]. I n ad ditio n , rotational v ari ations a re
becoming more prominen t, violat i ng the conc e pt of effective LET [17].
These effec t s have b een o bserved with l arg e ‐scale devic es f or s om e time
now; however, their contribution to predicted rates was fairly insig n ifican t,
and thus e rror pred ic tion m odel s were a ble to dis regard t hes e e ffects
without considerable effect on the resulting calculations. How ever, a t
modern sca le, both M CU a nd a ngu l ar e ffects h ave non‐t r ivial eff ects o n rat e
calculations a nd s hould be c onsid e red in o rd er t o impro v e the a ccu racy o f
calculations, especially when us ing legacy tools for rate predi ctions.
This c hapt er e xamines the effect o f a n gular direc t i o n ization e ven t s on
space event rate e st ima t es a nd p ro poses a new fault model that improves t he

98

accuracy o f error rate p redictio ns w hen space phenomenological models a re
applied. In particular, t h e two key elements o f this model are :
 Ident i ficat i on o f each i nd epend e nt i o n iz ing event (r at her than the
classical approach o f bit coun ting), t o remove M CUs from
consider ation, and
 Consid era t ion of a ng ular i on strikes f rom all potential angles of
incid e nce, t o properly consider rotatio n al dep endence.
In o rder t o properly g enerat e this f ault m odel w ith consider ati on t o n e w
effects in l eading‐edge and emerging t echnolo g ies, rout in e SEE test in g need s
to t ake additio n al data that i nc ludes considerat ion of a ngular error
signa t ures. H owever , obtain ing angular r e sponse d ata also i n t r oduces
challenges i n da ta c ollection, d ue t o the sheer number o f possi ble rotation
and t i lt c ombination s. S inc e i rrad i a t in g in f ine s t eps throu g h these
combinatio ns i s neither practica l nor feasible, this c hapter a l so p resents an
approximat ion method t hat s i gn if icantly reduces the number o f t es t points
required f or angular charact eriz ation.
Finally, a d e monstra t ion of t his improved m odeling approach i s pr esen ted ,
applied t o t h e 28 nm K int e x‐7 test r esults t o obtain f a i lure a p prox imations
that account for angular ioniz a ti on events encountered in orbit .

99

6.2 D IF FICUL T I E S IN A CCU RATE R ATE P REDICTIO N
A sig n ifica n t breakdow n of e xis t in g rat e p r e d i ction mod e ls r ela tes to t he
consideration of ion strikes that occur at angles other than normal i n c idence.
There a r e t w o problems t hat result f rom changing r ota t ion angl e when ions
strike the device with a non‐zero tilt angle: a rotational dep endenc e with t h e
use of effective LET and the generation of MCUs. These factors a ffect the
accuracy of current on‐ orbit rate p rediction m o dels.
It should be noted that this modeling work is focused at non‐ra diation‐
hardened, commercial technology offerings. While there may sti ll be
applicabilit y to s ome upset‐hardened t ech n ologies l ike DICE [ 86 ], their
radiation responses can vary i n unique ways at angle [87] making t h em l ess
desirable for general study. On a similar note, the ratio of a vailable
radia t ion‐h a rdened d evices t o commercial devices a t m odern tech nology
nodes strongly f avors the latter , m a king c ommercial offerings v as tly eas ier t o
obtain and utilize. Thus, the work presented here focuses on t he c lassical
upset mechanisms s een o n stand a rd d ev ices , such a s the two comm ercial
bulk Xilinx SRAM‐based FPGAs.
6.2.1 EFFECTIVE LET
Effect iv e LET, defin ed a s the inc i dent L ET d ivided b y th e cosine of the tilt
angle, h as s erved the r a dia t ion effects community w ell for decades as a key
simplifying concept ( a long w ith "critical c h arge" to u pset). H owever, the
"cosine law " w orks b est for thin p ancake sh a ped charg e c ollecti on v olumes

100

that are widely separated and at least several ion track diameters apart so
that c harge sharing is n eglig i ble; n either a ss umption is t rue at t he c urrent
scale. M odern cell sizes are so s m a ll and closely spaced t hat a single c ell can
no longer absorb all of the deposited charge from an ion striki ng a t a t i lted
angle, v iola ting t he c oncept o f effectiv e LET. Thus, it i s not surprising to see
test da t a w i th serious c osine law breakdown s a nd simulation stu dies t hat
explain why in detail. At least one replacement "law" [80] and a t least one
complete r eplacemen t r a t e method [88] h ave been d evelo p ed, but
necessitate significant changes to data collection or r ate c a lc ulation
methodologies, which makes them t oo complicated fo r wide a do pti on t o
date. Thus, a model that provides consideration of angular eff ect s , while
minimizing the amount of additional work and using standard tes ti n g
practices, i s the key motivating f orce b ehin d the work p resented i n thi s
chapter.
Data f rom the 28 nm K intex‐7 FPGA demonstra tes t h ese break downs;
Figure 29 shows the cross‐section of SRAM configuration mem o ry cells
following irradiation with 25 MeV/µ krypton at a nominal LET of 2 6.4 MeV‐
cm
2
/mg. Data is shown at a variety of rotations between 0 and 90 degrees
for sev e ral discrete t ilt angles. T he g raph i llustrates the ra nge of c ross‐
sections t h a t can be e xperimenta lly o btained when a tt empting to utilize the
cosine l aw t o establish higher e ffec tive L ET b y incr eas i ng  T . A lthough  T is
an important variable, it can be clearly seen that consideratio n must b e given
to  R as well, especially if tilting at higher angles above 60 degre es.

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FIGURE 29: ROTATION AN GL E D E P E N D EN CE OF T H E CR OS S S E C T I O N OF A 28 N M S R AM ‐
BASED FPG A

The st rong r ota t ion a l depen d en ce o f Figure 2 9 ca n be f rom eithe r
differ ences in r ow v s. c olumn spacing or m ay b e due to w ell ori entation [89];
regardless, it is apparently a growing problem as node size scales. Industry‐
standard rate calculators like SPENVIS [10] and CREME96 [9] can not d e al
with this effect to the extent that rotation angle independence i s b u ilt into
those models.

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6.2.2 MULTIPLE ‐CELL UPSETS
The other problem related to c on sideration o f angular events i s the
generation of MCUs. Through dat a obtain ed f rom irrad i a t ion of the Kint ex‐7
memory array [12, 13], generation of MCU events has been observ ed a t
relatively low LET thresholds and has become a non‐trivial fact or w hen
consider ing bit upset counts. I t is w ell known that h igh e r MCU rates arise
from shrin king n od e sizes due to i ncreased c harge sharing [21, 84, 90, 91].
As a practical matter, the varying shape and bit count of MCU p att e rns make
it difficult t o isolate th e events t h a t caused t hese u psets – a non‐trivial issue
for rate prediction [ 92] .
The problem of M CU g en era t io n is a lso aggra v at ed b y a rot a tion al
depend enc e t hat ex ist s w ith r e sp ect to t he o rienta tion o f SRAM cell s within
the device. For example, the Kintex‐7 SRAM cells are arranged such t hat
memory words span down columns with spacing between groups of l ogically
adjacen t w ords. B eca u se o f well sharing, c ell‐to‐cell proximity, and their
columnar o rganizat io n, n on‐nor mal‐incident i ons that s trike al o ng t he
columns (near  R =0° f or  T >0°) creat e sign i ficantly h igh e r MCU siz e s than
those that strik e ag ainst the col u mns (near  R =90° f o r  T >0°). F igure 30
illustrates t h is p rincipl e , with t he s ensitiv e v o l umes f or e ach b it r epr e sen t ed
by each box; the bit is considered to upset if an ion track pas ses thro ugh that
region. The organization of the SRAM cells in the device clear ly c auses a

103

higher n umber of c ells t o upset w h en i on s gr aze along t h e colum ns, rath er
than against the columns o r from normal incidence.

F I G U RE 3 0: L AY O U T CH AR AC TE RI S T ICS CAUS ING DE PE ND EN CE O N  R FO R I ON S TRIKES
WHE N  T > 0
As a case study, the ratio of MCUs compared to SCUs was examine d for the
exper i ment al data obtain ed o n K i nt ex‐7. F igure 31 shows the gr aphical
repres ent a t i on o f relat i ve MCU g enera t ion fr om i rradiat ing with 10 MeV/µ
silicon (LET ~ 4.4 MeV‐cm
2
/mg) and its dependence on  R and  T . T he MCU
prevalence w as i nterpo lated betw een measur ed d ata points a nd s y m e trically
copied a cro ss hemispheres, b ut p rovides a good a pproximation of the MCU
response of the device. Due to the physical organization of th e SRAM cells,
both the number and size of MCU events is higher when ions strike along the
columns, compared to striking ag ainst the columns or at normal incidence.

104

F IGURE 3 1: R EL ATIV E M C U PR EV AL EN CE WITH RESPECT TO TIL T AND ROT ATI O N
Exist i ng r a t e estimat i o n m odels generally a n a lyze o nly indiv i du al sensitiv e
volumes and do n ot c onsider neig hboring sensit ive volumes or t h e presenc e
of M CU. E v e n if m odels wer e t o c o nsider a dj acent sensit ive vol umes, the fact
that e ach node c ollects a different portio n of l iberat ed c harge makes this
model problematic when c harge s h aring is i n v olved as a m echanis m of u pse t
[87]. When considering angular d ata, e xisting models w ill over‐est i mate t h e
on‐orbit r a t e s i nce angular str i kes can ha ve s ignific a ntl y h igh er MCU r at es
which infla t e ra w bit upset counts . T his is a ls o a problem in moder n dev ices
which have b een demonstra ted to show increasing M CU susceptability, e ven
when ions strike at normal incidence.

105

Although new models can factor in rotational angles, multiple s ensitiv e
volumes, a nd m utually e xclusive c harge collection (CREME‐MC [8] , for
example), t h ese model s a r e s ignificantly m ore complex ; t he e x t e nsi o n of
simpler phenomenolo g ical m odel s to a llow c o nsiderat ion of m oder n effects
is the desired goal of this work. The generation of a new faul t model
proposed i n the following s ection o utlines one possibility t o e xtend th e u se of
the existing i ndustry‐ stand a rd p henomenological models t o obtai n error
rates using data cons i stent w i th existing collection methods an d techniques.
6.3 EVEN T F AULT MODEL G ENERA T IO N
In o rder t o effect iv ely predict on‐orbit f a u lt r ates o f devic e s utilizing
modern technology nodes, a new fault model that address both MC U clusters
and rotational dependence must first be generated. Current testi n g
techniques f or m emory‐based tec h nologies t ypically e va luate ups et r ate as a
function o f LET and the number o f bits t hat are upset in t he de vice f ollowing
an e xper iment a l irr a diation. The methodology here w ill gen e ra t e a new fault
model that a ddress e s t h e convers i on o f this d ata obta ined f rom standard S EE
test ing prac tices in o rder t o ext r ac t even t rat e s (where o ne e v ent eq uates to
one ion strike that upsets one or more cells in the device) and removes
rotat i onal d epend e nce by m odulating the da t a b ased o n the respo ns e of t he
device a t all potential rotation and tilt angles. This fault model can then be
applied t o exis tin g r at e estimat i o n t ools to o btain more a ccurate space rate
error estim a tes.

106

This m ethod levera ges symmetry in dev ice co nstruction i n order to r educe
the quantity of data and processing required. There may be som e rar e
inst ances where specific dev ic e construction p rohibits t he u se of
assumptions made in the methodol ogy. Howe v er for standard cell arrays like
SRAM memories, thes e techniques s hould work w ell. A s mention e d earlier,
these techn i ques m ay n ot a pply to devices w ith irr e gu lar sens it ive regions,
such as radiation‐hardened dual‐node cells where two independen t nodes
must upset for a SEU to occur.
6.3.1 ANGULAR EXPERIMENTAL DATA COLLECTION
In o rder t o address rot a tion al dep endence, a c erta in a m o unt of acc e lerator
test ing at v arious t ilt a n d rot a tio n a ngles is n ecessary. T h e data f rom testing
at these angles should reduce observed bit errors into event co unts b y
removing MCUs. The problem that arises in attempting to experi mentally
identify angular MCU rates is the relatively large test matrix need ed,
comprised of a permutation of possible rotations and tilt combi natio n s from
(0° ≤  R < 360°, 0° ≤  T < 360° ). S ince t esting a t ev ery combination of
rotation and tilt is not feasible, the required test space has to b e reduced in
order to b e tractable. Taking a dv antage o f s y mmetries t urns o u t to b e quite
effective in r educing th e tes t matr i x to a reaso nable size.
There ar e t wo assumptions that n eed to b e made in orde r for th i s reduction
m e th od to ap p l y. F irst, we com b i ne al l sens iti ve vol u m e s assoc iat e d with on e
bit‐cell and abstract t hem into a singl e s e n sitiv e volume, and assume t his

107

sensitiv e v o lume i s recta n gular parallelepiped. I n order to p r ovide
orien tat i on f or t he r emainder o f this discussion, an y io n ent e r ing at  T =0°
will be c onsider e d to st r ike th e volume a t normal i nciden ce f ro m the top fac e
of the RPP. An ion entering from  T =90°,  R =0° shall be n ormally i ncident to
one of the s ide faces.
The second a ssumption this method will make is that two ions th at tr a vers e
the same p ath through a sensitiv e volume w ill have t he sa m e net effect, even
if t he i ons a r e t r av eling in o pposit e dir ectio n s having e n t ered f rom opposite
sides of the sensitive volume. Thus, an ion traveling through the sensitiv e
volume a t  T =90°,  R=0° will have the same path and present the same
cross‐sectio n as an ion at  T =90°,  R =180°, d e spite the fact they are trav eling
in o pposit e d irect i ons. The same w ould h old true f or a n ion entering the top
(  T =0°,  R =0°) and an i on e ntering the b o ttom (  T =180°,  R =0°) o f the
device. This generalization relies upon the principle that any ion that is able
to p enetr a t e shielding m aterials ( which includes b ox m aterials, aluminium
shields, h eatsinks, and device p ackaging) on one side should al so h ave
sufficient energ y t o en ter from t he o pposite s ide (which w ould likely h ave a
similar ar r a y of m aterials), a nd a lso that i n the spac e GEO env ironment,
sufficient p a rticles ex ist with h ig h energ y a nd t he c ap ability to p enetrate
through shielding m a t erials i nto the sens it iv e reg i on o f the de v i ce s ilicon
[93]. This generalization is also extended to assume that the particle i s of
high e nough energy t hat the LET will remain c onstant a s i t tra v els through
sensitiv e vo lumes.

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For general device l ay outs, these assumptions mean t hat the cro ss‐section
“seen” by a n ion for 0° ≤  R < 90° at any given  T should be equal to that for
180° ≤  R < 270° a nd s hould be s ymmetric f or c ases o f 180° >  R ≥ 90° a nd
360° >  R ≥ 270°. T hus, b y testing at r otations o f 0° ≤  R < 90°, data can be
obtained t h a t will also a pply to 9 0 ° ≤  R < 3 6 0 °, r educin g the r e quired t est
matrix by a factor of four. By the same principle, ions trave ling i n ex actly
opposite directions with respect to tilt may be considered equi valent ( that i s,
where  T ’ =  T + 180°). This again reduces the test matrix by half.
The n e t res u lt i s a n e ight‐fold reduction of t he r equired tes t i ng s pace , as
indicated by the yellow section in Figure 32. The wedge can be
symmetrically translated to the other three quadrants in the to p hemisphere,
and th e ent i re t op h emisphere is s ymmetric t o the botto m hemisp here. T hus
the tr ack length o f any ion traveling into the sensitive region from an angle
outside the yellow wedge can be r epresented symmetric ally b y an ion
strik i ng a t a n angle t hat is in the wedge.

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FIGURE 3 2: R ED UCED T EST MAT R IX A FTE R C ONS I DE RA T I ON O F S Y M M E T R Y
The cross‐s e ction for a ll points w ithin the yel l ow w edge ( bound ed b y the
three poin t s a bove) would ideally b e obtained e xper imentally. However, a s
mention e d before, the extr emely large matr ix o f possible rotation and tilt
combinatio ns ( even f o r t his redu ced angle s e t) m akes t his unrea so nable to
attempt. The most important points, which we will refer to as the “ b oundary
points,” are at (  R,  T ) = (0°, 0 °), (0°, 90°), a nd ( 90°, 90°) which p r ov id e th e
relative contribution from ions incident on each face of the se nsit ive volume.
From there, we can attempt to interpolate data for points withi n th e yellow
wedge in Figure 32 using the boundary poin t s.
A potential problem, t hough, i s the inability to obtain dat a at  T =90°, due t o
the limitations on available cyclotron ion range [94], obstruct ion of o ther

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board components o r device p ackaging, and so f orth. T o solve t his is sue, k ey
data points with respect to rota tion a nd t ilt should b e obtaine d which can
then b e used t o extrap olate missing data at  T =90°. T hose p oints should b e
along the line from nor m al inciden ce approaching  T =90° for both  R =0° and
 R =90° ( also depicted by t he “ edg e s” o f the y e llow wedg e orig inating f r om
the top pole of the sphere in Figure 32). As many tilt angles as r easonabl y
possible should b e obtain ed f or t h e se t wo r ot ations, a n d varied to be as steep
a tilt angle as ion penetration will allow.
6.3.2 CONVERSION TO EVENT RATES
In order to address the MCU problem, the data observed throug h
accelera tor testing must b e refined to dis t i nguish b et ween t he numbe r of
events and the number of upset bits. Regardless of the distrib ution of MCU
cluster sizes, the event rate is the important factor that shou ld b e assessed,
not the bit upset rate (which is always higher due to MCUs). T his behavior
will allow us t o utilize sta n dard e vent r ate estima tion t ools w hich do not
model MCUs, and thus a lways assume that one ion striking the de vice w ill
cause one bit to u pset. B y modifying the data set t o evalu a te MCU ev ent ra te
inst ead of u pset b it c ount, the tools will be a ble to p rovide a proper one‐to‐
one mappin g of ion st rikes to ev e n t s in th e device.
In o rder t o break dow n data obta ined f rom accelera tor test ing ( bit upset
rate) into a n ev ent r a te, the data f rom acceler a tor tests must be e xamined in
order to see which bits in the device have upset. Clusters of upset bits t hat

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are phys ica lly a djacen t should b e grouped together i n t o one ev e nt. T he
physical a djacency m odel d escrib ed i n Chapt e r 4 ca n be u tilized t o iden tify
MCU clusters w hen the physical l ayout of t he device is n ot k nown. Since we
know that each MCU was generated by a single ion, we can now id en tify e ach
MCU or SCU as a single ion event. By formulating the new model based on
ioniz i ng e v e nts ra ther t han upset bits, one of t he significant problems
iden tified i n [92] w it h respect to e rror rat e p redict io n in t he presence of
MCUs is addressed.
6.3.3 EXTRAPOLATION AND INTERPOLATION OF MISSING DATA
As mentioned earlier, it is generally not possible to obtain ex peri mental
data at the three boundary condi tions because of t he p hysical l imitat ions that
prevent da t a c ollection at  T =90°. H owever, a fitting func tion c an b e applied
to t he o btained dat a o btained in o rder t o ex trapolate th e data out to o btain
an a pproximation for  T =90° i n both t he  R =0° a nd  R =90° c ases . S imilar
approximations can be made for rotation in order to fill out va rying  R
be twe e n 0° an d 90° f or f i x e d  T .
A fitting function can often provide very reasonable approximat io ns, an d
the accuracy o f the fit will increas e a s more data points a re obtained. The
appropriate fitting function will depend on the device. In our e xperiment s
with t hese F PGA devices, a f ourt h‐degree p olynomial fit matches the data
well when f itting  T data with fixed  R , and having a t least four d ata points
helped ens ure quality fits.

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Since some fitting functions could potentially vastly under‐ or o ver‐report
the cross‐section at v ery high  T (approaching 90°), t he algorithm d escribed
in Chapter 5 should be used in order to determine a bounding va lue for th e
fit. T h e c as e wher e  T =90° m eans t he i on s triking the d e vice i s inc i dent t o
one of t he f aces o f the RPP if  R =0° o r  R =90°. T hus, b y obtaining
approximat e dimensio ns o f the RPP, t he l imiting cro ss‐section f or t he
(  T =90°,  R =0°) and (  T =90°,  R =90°) cases can be d etermined by
calculating the cross‐ section of e ach sid e , equal to (w * h) and (l * h)
respectivel y .
A f te r ti lt data wa s f i tted, the rotations at e ach tilt a ngle w e re e xamined (  R
with f ixed  T ) and a linear f it a ppear ed a ppr opriate for fit t ing  R . F igure 33
and Figure 34 show e xamples of f itting f or  T and  R , respectively. T he f inal
result o f this e xtr apolat ion and int e rpolation was the ap proxim atio n of c ross
section for any g i ven combination of (  R,  T ).
Ultimat e ly, it s hould be n oted t ha t any considerat ion of a ngula r effects is
better than n one. T hus, a lthough validation o f the fit may not b e possible for
some portions of extrapolated data (especially at steep tilt wh ere accelerato r
ion rang e is insuffic ien t ) , it is important to consider that an y fit that increas es
the angular cross section beyond t hat which is o btained from s t and a rd
test ing p r a c tices at n ormal incid e nce will either b r i ng t he r es ult closer t o
what the actual value should be, or in the worst case overshoot the actual
value. Thus t he n et r esult is a n approximat ion tha t i s either closer t o the

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correct value than before, or in the worst case a pessimistic a ppro x imatio n
(which is preferred over under‐r ep orting t he a ctual space upset rate).

FIGURE 3 3: P OLYNOMI A L F I T U S ED T O I N TERP OLAT E AND EXT R AP OLAT E C ROSS‐S E C T I O N
AS A FUNC T I O N OF  T AT A F I X ED  R

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FIGU R E 3 4 : A LIN EA R FIT US ED T O IN T E R P O L A T E C R O S S ‐ S E C T IO N AS A FUNC TI ON OF  R
FOR FIXED V A LUES OF  T
6.3.4 AVERAGING OF INTERPOLATED DATA
Once data points are obtained for the full range of angles on b oth tilt a nd
rotation and MCUs removed from the data, the interpolated data should
provide a matrix o f event cross‐ section at a ny g iven a ngle c omb inat ion of
rotat i on a n d t ilt. U sin g t his matrix, the aver a g e event cr oss section value for
each LET should be calculated. This value should be used as th e d a ta p oint
used for space rate estimation at each particular LET. By usin g the aver age

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observed e vent c ross‐ section obt a in ed f rom all angles, the data points are
made r otat ionally i nd epend e nt t o match the models u sed by i ndus tr y
standard to o ls.
One important consid erat ion when obtaining the average value is the
projection o f the d a t a set o nto a thr ee‐d i ment ional body. I f d ata is
repres ent e d by a t wo‐diment i ona l t able w ith axes r epresent ing r ot ation and
tilt, the values need to be corrected in order to properly proj ect th e points
onto a spherical surfac e b efore av erag ing. T h e sphere in Figure 31 il lustrates
this p roblem, where data c ells r epresent ing the MCU percent a ge that a r e
near the equator of the sphere are much larger than the cells n ear the poles.
By w eighting each r ow o f data w ith the cosine o f the an gle from the equator,
(also known as a M ercator project i on) the weight o f each 2 ‐D d a ta c ell can be
scaled accordingly based on its loc ation o n the 3‐D sphere.
This p roced u re i s then r epea ted fo r the r e maining tes t L ETs and ultimately
produces a c ross‐section Weibull curve a v er agin g all ro tatio n al effects and
representing only event rates. This model of the error cross‐s ection c an t hen
be u sed in e xist ing s i ng le‐bit single‐event o n ‐orbit r a t e pr edi ction too l s to g et
an on‐orbit rate w ith increased accuracy.
6.4 ERROR R ATE ESTIMATION ON 28 NM FPGA D EVICE
As a demo n stra tion o f this m eth o dology, this w ork ex amined t h e static
irradiation of the 28 nm Kintex‐7. With respect to MCU extract io n, C hapter 4

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investig at ed n ormal‐incidence io n strikes o n ly; the data p resen ted for this
chapter is d iffer e nt iat e d by the inc lusion of til t and ro t ation angles.
The configuratio n of t he K intex‐ 7 is d efined b y a “bit file” tha t is l oad e d in t o
the device w hich i s 91,548,896 bits a nd c omprised o f configurat io n values,
Block RAM contents, and unused filler. The analysis used in th is study
examined 70,868,064 of those bit s that directly controlled acti ve op e rat i on of
the dev i ce a nd w ere user‐accessible for read back ( these bits a r e sometimes
referred to as “unmasked bits”).
The test procedure for the angul ar r uns was described in C hapter 3. The
angular tes t s would in itialize t he F PGA configuration memory a r ray, b egin
irradiation, and stop irradiation once a certain threshold of e rrors was
reached. Readback of the SRAM memory array occurred every 10 s econds.
The flux w as e xperimentally det er mined for each i on a nd k ept lo w enough t o
limit the nu mber o f upset r a t e t o approximat ely 40 b its per second in o rd er
to minimiz e the chance o f experimental artifacts.
Using [9 5], the probability of a n upset cell f lipping t wice i s red u ced to
below 0.12% per readback, and coincident SBU, where a pair of s ingle‐bit
upsets m imics a M C U signature, i s reduced to s imilar l evels. T h is a lso en ables
ready filtering of control circuit upsets that cause large appa rent “ b u rsts” of
bit upsets.
In order to obtain the requisite data to analyze the effect of MCUs o n the
space rat e f or t his part icular devic e, p art irr a diat ion was performed at 0, 50,

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60, a nd 70‐degree t ilt. Following t his, t he part was ro tated 9 0 d e gr ees a nd
irrad i ation performed at 50, 60, a nd 70‐deg r ee tilt. 70 degree s was the
practical limit of tilt for the test board used. The raw data counts a re
presen ted b e low in Table 6.
TA BLE 6: RAW DATA FOR A N G U LAR MODE LING STUDY

The irr a dia t ions w ere performed using 10 M e V/µ io n species such t hat the
incid e nt LETs were 1 . 54, 4 .35, 7 . 27, a nd 49. 3 MeV‐cm
2
/mg. For each ion,

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data w as e xtrapolated to obtain steeper t han 70‐degree t ilt poi nts f or each
available ro tatio n .
Following the complet e interpolat ion and ext r apolation of tilt angl e data fo r
one LET, t h e d ata was then i nterpolated at e ach rotatio n a ngle, providing a
data set that had cross sections for each combination of rotation and tilt.
After correcting for the Mercator projections of our data point s and
aver agi n g t hese weigh t ed v alues, a per‐bit event cross‐section seen b y ions
strik i ng a t arbitrary angles for that incident LET was obtained.
Repeating this process for all available data and ions, a new e vent‐based
cross‐sectio n fault model was derived. This n ew model w as t hen a pplied to
CREME96 phenomenological mo d els to obt ain space error rate e sti mates.
The difference in on‐orbit error rates is shown in Table 7, when calculating
rates for a GEO orbit with 100 m i ls of aluminum shielding.
TABLE 7: P R E DICT E D O N‐O R BIT ER RO R RATE E STI M ATE S

The table c ompares t he t ra dit i on al a pproach of bit counting, bi t cou n ting
with a ngula r e f f ects, a n d the new proposed e vent‐based f ault model. As you
can see, classical approaches u se d to characterize older devices

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underes t im ate the actu al f ault r a t e that t he d evice w i ll see by a factor of ~3.
If the model were to only account for angular effects, the erro r rate t h e n
becomes overes timat e d by a bout 35%, since MCU effects are not c o n sidered.
The event fault model that r emoves t he i nc idenc e o f MCU and c o n siders
rotat i onal depend e nc e is t he m ost accurate, and will p reven t a system
desig n er f r o m having t o either over‐design or u nder‐desig n a mi tig a tio n
scheme based on the expected f au lt rate.
6.5 S UMMARY
This c hapter i n t roduces three no vel innovatio n s towards solving problems
presen ted by t he stronger a n gula r respons e o f modern scaled tec hnology
nodes. First, the methodology for extracting physical layout i nformation i n
Chapter 4 is e xtend ed t o non‐normal angles. Second, a method w as
developed for filling o ut a r elatively sparse s et o f angle meas urements t o a
dense virtual data set. Finally, a method for integrating the device a ngular
response w ith space environm ents o f in t e res t i n t o a normal s pace rat e
predict i on i s demonstra t ed. T he e ffica c y of t hese i nno va tions is
demonstra t ed v ia a c omplete exa m ple using heavy ion data o n th e 28 nm
Xilinx Kintex‐7.

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C HAPTER 7

7.1 S UMMARY
W i th th e ev ol u tion of t e ch nol ogy, i t is o f par a m ou nt im por tance to mainta in
proportional e volution o f our te sting proc esses and methodologi es. A s
transistor feature sizes are now scaled down to 20 nm and small er, there is
definitiv e e vidence th at c hangin g responses to i onizing radiati o n i n thes e
small scale devic e s demands new thought to o ur f ault m odeling a nd
estimation p rocesses.
The res e a r ch p rovided in t h i s d i sser t at ion provided a f irs t l oo k at t he
response o f modern‐scale, comme rc ial SRAM‐based FPGA d evices a t both 28
nm a nd 2 0 nm t echno l ogy nodes using classical techniq u es. W hen deeper
analys is o f the data w as p erform ed, a key observ ation w a s that the
prevalence o f MCU was much h igher tha n t hat observed f rom previ ous
generat i on d evices, a n d MCU ra tes quickly reached non‐ triv ial r at es e v e n at
low LET rates. A lso, t he device n o w exhibited a rotat i o n al dep end e nce not
observed i n older generations, requiring new consideration of a ngular
ioniz i ng e v e nts.

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To isolate the MCU events, a methodology is introduced to ident if y
physically a djacent memory c ells o n a device, even w hen physica lly a djacent
memory cells are not adjacent in the logical address space, and when no
knowledge of t he devic e layout i s available. T he g en era t ion of a statistically
generated physical adjacency model allows us to isolate upset b it c lusters
that b elong to a s ingle MCU even t. R esults w ere confir med usin g a device
with known layout; depending on the data set, the model was abl e to p redic t
physical adjacency w ith an er r or between 2% and 28% acc uracy.
Regard ing the newly observed r otatio nal depend ence, it i s important t o
recogniz e the implications o f t h is d iscovery, which invalida tes certain
classical testing t e chniques w hen irrad i at ing at a ngles away f r om n ormal
incid e nce. However, t his rotat i onal dependency ca n also p rovid e key
informa t ion about the sensitiv e volume n ot p reviously observable in l ar ger‐
generat i on devices. T his info rma t ion ca n be u sed to m easure t h e sensitiv e
volume, which provides h igher fid e lity dat a t h at m ay b e used w i th i ndustry
stand a rd m odeling tools to b ett e r estima te o n ‐ orbit fa ilure ra t es, im proving
predictions by about 15%.
Finally, a new fault m o del was generated th at t ook d ata from a relatively
sparse set o f normal incidence a nd angular studies and transfor med it into an
even t‐based data set t hat accounted for rotat i onal depen dence o f th e device.
This n ew m odel i s applied t o current p heno menologica l modeling tools and

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was demon s trat ed t o p r ovide mor e a ccurat e s pace r a t e estima tion than that
obtained f r o m convent i onal tec hniques by a factor of three.
7.2 I MPLICA TIONS OF TH IS R ESEARCH
With a ll of t he r es earc h applied h ere into c hanging res p onses of modern
scale devic e s, i t is a lso important to n ote the changing c harac teristics in t he
way that these devices upset. The increased prevalence of MCU is a larming
not on l y for th e fact th a t a grea t er q u a ntity of b its wil l u p se t, b u t also b e cau se
of a temporal factor where upset bits are no longer distributed o ver time, but
now occur simultaneously in clusters. Designers who attempt to m itiga t e
SEU effects must p articularly be m ade awar e of t his, a s standard mitigatio n
approaches must now be modified .
As an example, SECDED‐based ECC based on Hamming codes is a pop ula r
practice for space memory technologies. MCU would have obvious
implication s o n these memories, causing dec r eas e d ability to c orrect a large
percentage o f errors. A nother i mpact would be i n the area o f F PG A design
mitigation, where the current de facto standard is a technique known as
“Triple Mo dular Redundancy,” o r TMR [96]. T his tech nique repli cates the
FPGA d at a path t hree t imes, forming three in depend ent copies o f the circuit
that are “voted” at various stages. In theory, an upset in one c op y of t he
circuit will be overruled at the voter by the other two functio n a l copies. I n
the past, d e sig n ers ut ilizin g TMR have b een fortuna t e in t hat M CU e ff ects
often limit effects to o ne c opy o f t he l ogic. I n an a ttem p t to m itigate MC U,

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FPGA d esigners h ave incorporated p hysical cell in te rlea vi ng t o spread t h e
effects of M CU a cross multiple c onfiguration w ords (or logical frames).
While this i mproves t h e ability t o c orrect t hese c onfig u ration err o rs with
SECDED ECC, it has a negative implication in that the probabili ty o f affecting
multiple branches of a T MRed des ign is increa s ed.
Ultimat e ly, acceptin g these new paradigms and fa ilure mechanisms will
take t ime, a s the exis ting m ethodologies t h a t hav e s er ved the c ommunity
well for decades must n ow b e reconsider ed. U ltimately though, the outlook
for pushing the use of m odern sca l e devic e s into space i s promi sing a nd i f
done c arefu lly, will open a n abun d a nce of pot ent i al capa b ility for future flight
missions.
7.3 P OTEN TIAL F UTURE P AT HS
Fortunately for sys t em desig ner s, some e ffect s h ere hav e b een a nt icipated
by designers a nd r es earch has already begu n on sever al f ronts r elated t o
problems i ntroduced by t echnology scaling. There is a lr eady o n go ing work
to m itiga t e the effect s of M CU o n TMR schemes [14, 15]; prelimi na r y
research by Sterpone in [97, 98] has presented the need for car eful
placement of e ach bra n ch o f TMR logic in o r d er t o prev ent M C U e ffects f rom
breaking m ultiple copies o f the circuit simultaneously. T hough h is r esearch
is f ocused a round TMR , h is w ork c o uld easily b e applied t o the ge ner a l ca se ,
where non‐timing critical paths in a FPGA design could be pushe d apart to
improve resilienc e t o MCU. F urthermore, silicon desig n ers a r e looking for

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new ECC methods to mitigate MCU beyond a combination of SECDED and
interleaving; more a g g ressive a p p roaches are in c onsideration, including
incorporating more expensive ECC with a larger Hamming distance ,
increasing the number of bits th at c an be corr ected or d et ected in error.
At t he device level, t his is a n exciting t ime for semiconductor e lectronics,
with transistor feature sizes continuing to fall rapidly and the end of M oore’s
law predicted to o ccur within t he n ext few g e nerations of t echn ology nodes.
At l east f or t he n ear t e rm, new a dvances h a v e continued Moore’s law by
revolution izing t r ans i s t or design by c reat ing a three‐dimensional FET known
as “ FinFET. ” C hann el e ffects a r e l imiting t h e perform a nce of t raditio n al
planar t ransistors a s feature sizes shrink, thus m aking FinFET t h e tar get
technology of choice fo r manufac turers utiliz i ng <20 nm feature sizes.
FinFETs ar e especially e xcit ing for the radiation effects c o mmu nity a s these
FETs show excellent critical charge and sensitive volume scalin g [99, 100].
Furthermore, c harge s p reading is m ore difficult in a v er tical F ET s tructure,
and pr eliminary t e s t ing on 4 5 nm F in FETs s howed th ese structure s
collecting only a pproximately half the charge compared to a 45 nm p lanar
device f or m atched d rive [101]. Tes ting o n modern scale F inF ET s has
validated this claim, exhibiting among the lowest upset rates s een in a ny
scale device.
Despite the improved S EE perfor mance of F inFETs, MCU and MBU ar e still
expect ed t o be a p roblem, and on e that w ill s c ale exponentially with feature

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size [101]. It will also be interesting to examine the rotatio nal dependenc e
when i rrad i at ing these structures a t angle. Thus, as sc a ling c ontinues, the
research t hat was started here w ill need t o continue o n new tec hnology
nodes and further attempt to i de nt ify new dev i ce r es ponses, esp ecially i f
angular dep e ndencies a re observ e d .
Furthermore, it is quite possible that the newer effects we observe a t 28
nm and below may be more pronounced as technology advances, and staying
on top of these changes should be a principal goal for the spac e community
looking to t ake ad van t age of t he capabilities provided b y new t echnologies.

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A CRON YMS

CMD Coronal mass ejection
CSEU C oincident si ngle‐event u pset
DD Displa c e m ent da ma ge
ECC Error‐correcting codes
FPGA F ield‐Program mable Gate Array
GCR Galactic cos mic ray
LBL Lawrenc e B e r keley Labor a tory
LET Line ar E nergy Tr ansfer
MBU Multiple‐bit upset
MCU Multiple‐cell upset
RPP Rectangular parallelepiped
SCU Single‐cell upset
SEB Single‐event burnout
SECDED S ingle‐error corre ct, double‐error detect
SEDR S ingle‐e v ent dielectric rupture
SEE Single‐event effects
SEFI S ingle‐e v ent function al in t errupt
SEL Single‐event latch‐up
SET Single‐event transient
SEU Single‐event upset
T AMU T ex a s A&M Unive rsity
TID Tot a l ionizi n g dose
TMR Triple M od ular Red und a n c y

127

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Abstract (if available)

Abstract Space processing technologies enable numerous capabilities that have become pervasive in modern culture. As our reliance on this technology grows, so does the desire for greater on‐orbit processing to enable new capabilities. Field‐Programmable Gate Arrays (FPGAs) have played a key role in fulfilling space processing needs

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