University of Southern California Dissertations and Theses

Subthreshold circuit design for ultra-low-power sensors

(USC Thesis Other)

Subthreshold circuit design for ultra-low-power sensors

PDF

Download

Open document

Flip pages

Download a page range

Download transcript

Copy asset link

Request this asset

Transcript (if available)

Content
Subthreshold Circuit Design for
Ultra-Low-Power Sensors

by

Uldric Antao

A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(Electrical Engineering)

May 2016

ii

To my Family and John Choma, for their encouragement and wisdom.

iii

Table of Contents
Table of Contents ........................................................................................................ iii
List of Figures .............................................................................................................. vi
List of Tables ............................................................................................................... xi
Acknowledgment ........................................................................................................ xii
Abstract ...................................................................................................................... xiv
Chapter 1: Introduction ...............................................................................................1
1.1 Background: Seismic sensor and signals .......................................................... 3
1.2 Why subthreshold analog ................................................................................. 5
1.2.1 Previous version of seismic sensor ........................................................... 5
1.2.2 Low power digital approaches .................................................................. 6
1.2.3 Low power analog approaches .................................................................. 7
1.2.4 Subthreshold analog approach .................................................................. 8
Chapter 2: Subthreshold MOSFET Overview .........................................................10
2.1 Subthreshold physics ...................................................................................... 10
2.2 Variations in subthreshold domain ................................................................. 15
Chapter 3: 40 nW Subthreshold Event Detector for Seismic Sensors ...................18
3.1 System level .................................................................................................... 18
3.2 Circuit level .................................................................................................... 21
3.2.1 Band pass filter ........................................................................................ 21
3.2.2 Envelope detector .................................................................................... 31

iv

3.2.3 Divider ..................................................................................................... 37
3.2.4 Adder/subtractor, comparator, level converter ........................................ 38
3.2.5 Buffer ...................................................................................................... 39
3.3 System simulations ......................................................................................... 40
3.3.1 Noisy data and background-update-rate test in digital system ................ 41
3.3.2 Noisy data and background-update-rate test in sub-vt system ................ 44
3.3.3 Dynamic power ....................................................................................... 46
Chapter 4: Hardware and Chip Results ...................................................................47
4.1 Chip layout and hardware ............................................................................... 47
4.2 Chip simulations ............................................................................................. 52
4.2.1 Current sources ........................................................................................ 52
4.2.2 Buffer ...................................................................................................... 54
4.2.3 Band pass filters ...................................................................................... 55
4.2.4 Envelope detector .................................................................................... 56
4.2.5 Background cancellation and level converter ......................................... 57
4.2.6 Event detection ........................................................................................ 59
Chapter 5: Event Detector Conclusion .....................................................................62
5.1 Improvements/impact ..................................................................................... 64
5.2 Issues .............................................................................................................. 65
5.3 Parameter dependence .................................................................................... 65
Chapter 6: Mismatch-, PVT- and False-Positive-Insensitive Design .....................69
6.1 Mismatch ........................................................................................................ 69
6.2 Temperature .................................................................................................... 72
6.3 PVT-insensitive subthreshold g
m
: Past solutions and drawbacks ................... 73

v

6.4 PVT-insensitive subthreshold g
m
: Proposed design ....................................... 76
6.4.1 Setting V
G
for PTAT current ................................................................... 76
6.4.2 Circuit for V
G
and PTAT current ............................................................. 80
6.4.3 Squaring circuit ....................................................................................... 82
6.4.4 Correction block ...................................................................................... 88
6.4.5 Specific current extractor ........................................................................ 92
6.4.6 System simulations and comparisons ...................................................... 98
6.5 False-positive rejection ................................................................................. 102
6.5.1 System architecture ............................................................................... 103
6.5.2 Spike generator ...................................................................................... 104
6.5.3 Simulation ............................................................................................. 105
Chapter 7: Conclusion ..............................................................................................107
References ..................................................................................................................109

vi

List of Figures
Figure 1.1: Vehicle data. ................................................................................................ 4
Figure 1.2: Footstep data. ............................................................................................... 4
Figure 1.3: UGS seismic sensor. .................................................................................... 6
Figure 1.4: Digital seismic sensor. ................................................................................. 6
Figure 2.1: a) NMOS cross-section. b) Biases applied to NMOS. .............................. 11
Figure 2.2: NMOS in subthreshold a) cross section, b) energy band diagram in linear
region, c) energy band diagram in saturation region. .............................................. 12
Figure 2.3: Current vs. gate source voltage in log scale. ............................................. 14
Figure 2.4: Small signal model for NMOS. ................................................................. 15
Figure 2.5: Histogram of current for different transistor sizes. a) W = 1 μm and
L=150 nm, b) W=1 μm and L=8 μm. ...................................................................... 16
Figure 3.1: Digital event detector................................................................................. 18
Figure 3.2: Subthreshold event detector. ..................................................................... 19
Figure 3.3: OTA biquad. .............................................................................................. 22
Figure 3.4: Input resistance of BPF in Figure 3.3. ....................................................... 23
Figure 3.5: a) OTA C4. b) Equivalent circuit. ............................................................. 24
Figure 3.6: a) Q vs. g
m
ratio; maximizing Q. b) BPF frequency response. .................. 27
Figure 3.7: C4 BPF. ..................................................................................................... 28
Figure 3.8: a) High gain stages cascaded. b) High gain and low gain stages cascaded.
................................................................................................................................. 29

vii

Figure 3.9: a) 10 stages cascaded (stage 1, type 1 filter and stages 2–9, type 2 filter). b)
Normalized response of a). Bandwidth becomes narrower with increase in stages.
................................................................................................................................. 30
Figure 3.10: Q and power vs. number of stages. .......................................................... 31
Figure 3.11: OTA. ........................................................................................................ 31
Figure 3.12: a) Wilson current mirror as full wave rectifier. b) Peak detector. ........... 32
Figure 3.13: Envelope detector response. .................................................................... 33
Figure 3.14: a) I
in
(supplied at inputs of rectifier) vs. I
out
, dead-zone of about 4 pA due
to leakage. b) V
in
supplied at input of OTA vs. rectifier I
out
for different V
B
bias
voltages for OTA. Low bias voltages forces lower leakage.................................... 33
Figure 3.15: The left graph shows a 40 Hz transient response with no noticeable dead-
zone. On the right a higher frequency (500 Hz) sinusoid produces a noticeable
dead-zone. ............................................................................................................... 34
Figure 3.16: 1 kHz size wave applied to sub-vt (left) and above-vt (right) system. Sub-
vt system shows observable dead-zone, limiting frequency of operation. .............. 36
Figure 3.17: Divider. .................................................................................................... 37
Figure 3.18: Level converter. ....................................................................................... 39
Figure 3.19: Foot step simulation. ............................................................................... 40
Figure 3.20: Noisy footstep data supplied to digital system. Each column shows the
system’s response to the different noisy data (footstep along with 40 Hz, 60 Hz,
100 Hz, and 120 Hz noise from left to right). 40 Hz and 100 Hz spectral
components shown along with events. .................................................................... 42
Figure 3.21: Footstep data with different update rates in digital system, 50 ms update
(left), 12.5 s update (right). With 12.5 s update, only first 3 events of each 7 s
segment caught. ....................................................................................................... 43

viii

Figure 3.22: Noisy footstep data (footstep along with 40 Hz, 60 Hz, 100 Hz, and
120 Hz noise from left to right) supplied to sub-vt system. 40 Hz and 100 Hz
spectral components are shown along with events. ................................................. 44
Figure 3.23: Different background update rate in subthreshold system, 50 ms update
(left) 12.5 s update (right). No noticeable difference. ............................................. 45
Figure 3.24: Dynamic power of sub-vt system. Average analog power is 30 nW. ..... 46
Figure 4.1: a) Chip layout. b) Chip micrograph. .......................................................... 47
Figure 4.2: Test PCB for event detector chip. .............................................................. 48
Figure 4.3: Test PCB schematic: Control. ................................................................... 50
Figure 4.4: Test PCB schematic: DUT. ....................................................................... 51
Figure 4.5: a) Cascode source, b) diode connected transistors, c) low voltage bias
circuit. ...................................................................................................................... 52
Figure 4.6: I–V graphs, chips and Cadence. Zoom-in shows subthreshold region. ..... 53
Figure 4.7: a) I–V graph of cascode current source for different V
cas
voltages, showing
comparison between chip 6 and simulation. b) Chip 6 I–V graphs with constant V
cas

and varying V
ref
........................................................................................................ 54
Figure 4.8: a) Frequency response of buffer. ............................................................... 54
Figure 4.9: Reponses of different sections of a) 40 Hz BPF, b) 100 Hz BPF. ............ 55
Figure 4.10: Full wave rectification (top) for 1 mV 40 Hz sine wave. Peak detector
response (bottom). ................................................................................................... 57
Figure 4.11: Background noise cancellation. ............................................................... 58
Figure 4.12: Level converter output. ............................................................................ 59
Figure 4.13: Event detection for step increase in input amplitude. .............................. 60
Figure 4.14: Event detection for footstep data. ............................................................ 61

ix

5.1: Response to foot step data: Digital version (top), cadence simulation (middle),
chip simulation (bottom). ........................................................................................ 62
Figure 5.2: a) Monte Carlo simulation for diode connected current source. b) Corner
simulations for diode connected current source. ..................................................... 66
Figure 5.3: Monte Carlo simulations for different current sources of 40Hz BPF along
with distributions for center frequency and gain of the BPF. ................................. 67
Figure 6.1: a) Mismatches: ΔV
T0
(top) and ΔI (bottom) for transistors with a) W/L =
0.42 μm/2 μm, b) W/L = 4.2 μm/20 μm. ................................................................. 70
Figure 6.2: Relative current mismatch vs. temperature for small and large transistors.
................................................................................................................................. 70
Figure 6.3: Mismatches: Center frequency (top) and gain (bottom) of BPF with current
mirrors with a) original transistor sizes b) 100 times original transistor sizes. ....... 71
Figure 6.4: Current and g
m
vs. T for transistor in sub-vt with fixed gate-source voltage.
................................................................................................................................. 72
Figure 6.5: Frequency response of the four stage BPF at different temperatures. ....... 73
Figure 6.6: Beta-multiplier circuit for PTAT current................................................... 74
Figure 6.7: PTAT current generator. ............................................................................ 80
Figure 6.8: Simple current mirror depicting translinear loop. ..................................... 83
Figure 6.9: Stacked topology with 1 extra CCW transistor. ........................................ 83
Figure 6.10: Stacked topology with two extra CCW transistors. ................................. 85
Figure 6.11: Stacked squaring circuit with equal CW and CCW transistors. .............. 85
Figure 6.12: Squaring circuit using alternating topology............................................. 86
Figure 6.13: a) Squaring circuit output current dependence on changes in V
ref
. b)
Zoomed-in. .............................................................................................................. 87
Figure 6.14: Squaring circuit simulation. ..................................................................... 88

x

Figure 6.15: Correction block, using two different transistors with different m.......... 90
Figure 6.16: a) I
2
vs. T with constant I
1
. b) Extra plots with offsets in V
T0
and V
OFF
. . 91
Figure 6.17: a) Introducing V
S
to current mirror to remove exponential term. b)
Simulated data with V
S
matches required function, f = T
m1–m2
. ............................... 92
Figure 6.18: Specific current extractor......................................................................... 94
Figure 6.19: Stacked transistor. .................................................................................... 95
Figure 6.20: Graphical version of (6.61) asymptotes for small i
f2
. .............................. 96
Figure 6.21: Circuit that creates required voltage, V
X
. ................................................. 97
Figure 6.22: Specific current extractor without S.I. transistors. .................................. 97
Figure 6.23: Final system: PTAT current or constant subthreshold g
m
bias generator. 98
Figure 6.24: a) I
M3
better match than I
S
, as error divided down in squaring circuit. b)
Corrected PTAT current along with the g
m
of the transistor it biases. .................... 98
Figure 6.25: Frequency response of the four stage BPF at different temperatures. ..... 99
Figure 6.26: Power supply variations of a) I
S
and b) g
m
. ........................................... 100
Figure 6.27: g
m
vs. T for different V
S
. ........................................................................ 100
Figure 6.28: Corner analysis. ..................................................................................... 101
Figure 6.29: Subthreshold event detector with false positive correction block. ........ 103
Figure 6.30: False positive correction circuit. ............................................................ 103
Figure 6.31: Spike generator. ..................................................................................... 105
Figure 6.32: Corrected event without false positives. ................................................ 106

xi

List of Tables
Table 3.1: BPF performance. ....................................................................................... 26
Table 3.2: Subthreshold event detector specifications. ................................................ 41
Table 4.1: 40 Hz BPF specifications. ........................................................................... 56
Table 4.2: 100 Hz BPF specifications. ......................................................................... 56
Table 5.1: Power metric for event detector chip. ......................................................... 63
Table 5.2: Variations in current sources. N = 100 ....................................................... 68
Table 5.3: Events detected with variations in current sources. .................................... 68
Table 6.1: Comparison with state of the art. .............................................................. 102

xii

Acknowledgment
Over the years at USC I have made very special connections with so many people. At
the culmination of my Ph.D. career, I have grown technically and attained many life
lessons through all the highs and lows, through the setbacks and accomplishments. The
ability to go through the roller-coaster ride (a long ride indeed!) of technical and
emotional challenges was because of two reasons: I have grown stronger in facing
challenges, but most importantly, because of all the people who have supported me
through my Ph.D. career.
The first lab I had worked in was at the Information Sciences Institute. I worked
indirectly under Dr. Berger on the hippocampal implant. Back then I did not know that I
would be working with Dr. Berger directly at the Neural Dynamics Lab as my advisor. I
would like to thank him for his immense support through all the years. Through all our
discussions (and red bulls!) Dr. Berger not only critiqued my strategies on tackling a
project but he was always there whenever I needed guidance in dealing with many
hardships one would face in a Ph.D. career. For example: changing labs, losing a mentor,
funding issues. I thank you for all the help.
My mentor, advisor and friend Dr. Choma who left us a year ago, was my advisor for
a long time. I was first introduced to him while taking an Electrical Engineering class
with him. Our discussions over the first couple of years slowly ended in him being my
advisor. John was an awesome teacher and would talk for a while during discussions.
He was a very jolly person. He was also somehow able to keep that same personality
despite his ailments. John was a very strong man and I am proud to say that I am one of
his graduate students. This thesis is for you, John.
I would like to thank Dr. Parker for her support throughout my time at USC. I would
like to thank her for taking the time to talk with me, my first semester at USC. She was

xiii

very passionate about her work and also showed a deep interest in my work as well. We
have had a lot of discussions on bio-inspired circuits. I also thank her for her support
during the times I needed not just advice, but someone to talk to in times of need.
I would like to thank Dr. Chen for his advice on analog circuits during the past year.
He would make sure that I had taken all the necessary steps to complete my Ph.D. Thank
you for all the guidance.
At the Neural Dynamics lab, Dr. Dibazar helped me grow as a Ph.D. student. I
learned many useful skills in building hardware for the lab. He also encouraged me to
write papers and supported me in proof reading my papers and presentations. My other
lab mates, Ali Yousefi, Hyung Park and Maryam Nikizad were very knowledgeable and
imparted a wealth of information. I would also like to thank my other colleagues in Dr.
Choma’s group, Susan Schober, Viviane Ghaderi and Aaron Curry, for being a great help
on various discussions and for being good friends. I also thank my group at ISI: Dr.
Granacki, Jeff LaCoss, Dr. Wills, Vijay Srinivasan and Ankit Bhargav.
I would like to thank Sam Geha and Artur Balasinski, our contacts from Cypress
Semiconductor, who helped us with our chip fabrication and for the support to the
multitude of questions during the chip layout process and final fabrication.
I would like to thank staff members from both the EE and BME department: Consuelo
Correa, Karen Johnson, Kenneth Johnston, Mischal Diasanta, Diane Demetras and Jaime
Zelada.
I would like to thank all my friends who have made USC my home, and have made all
the years at USC so much more worthwhile. I would also like to thank Melroy Machado
and Iman Yadegaran, who have heard all my struggles and joys. They would be very
patient listening to my problems and would always offer good advice and make me feel
better when times were hard.
Lastly I would like to thank my family. Though they might not know the details of
my work, they have lived my experience as a graduate student through me. The phone
calls, the motivation, the love and support are hard to put in a thank you. I thank you all!

xiv

Abstract
Unattended ground sensors (UGS) are widely used for persistent, surveillance that
detects potential threats from intruders without generating false alarms. Battery life is the
limiting factor for solutions using digital processing. A 40 nW subthreshold event
detector chip in a 150 nm CMOS (complementary metal oxide semiconductor) process is
fabricated and tested, that wakes up a threat classifying stage. The event detector
processes the signal, using band pass filters, envelope detectors, noise canceling
mechanisms and a thresholding function to trigger an event. The chip is compared with a
previous generation all digital system. The chip consumes 160,000 times less power than
its digital counterpart, but due to subthreshold operation the chip is prone to mismatches
and temperature variations, resulting in loss in gain in the system thereby missing low
amplitude events.
Methods to reduce mismatches and temperature variations are proposed promising a
sturdy UGS. Constant transconductance is an important circuit feature that relates to
keeping gain and bandwidth of several analog circuits constant with process, voltage, and
temperature (PVT). A 9 nW PVT invariant subthreshold transconductance bias circuit is
developed using the 150 nm CMOS process. Comparing with previous constant
transconductance circuits, the circuit neither uses external components nor strong
inversion transistors, thereby improving stability and lowering the power. The design
method finds a temperature dependent gate voltage across a transistor producing a
constant transconductance current over temperature for subthreshold region. A
correction block improves the stability of the transconductance using the mobility
temperature exponent, m, of electrons of NMOS transistors. Simulations show that the
circuit can achieve ±0.63% variation in subthreshold transconductance over -40 °C to
125 °C; greatly enhancing the robustness of the event detector to PVT changes.

1

Chapter 1
Introduction
Smart-sensing technologies are emerging as practical foundations for solving the
continuing problems of an increasing need for persistent, sensor-based surveillance that
detects potential threats (humans or approaching vehicles) and does not generate alarms
for events or objects that share some (but not all) of the features of the target, i.e., "smart,
brain-like" surveillance that minimizes false positives. Seismic sensors are used to catch
vibrations produced by intruders. Such security sensors are placed in regions not
frequented by humans, for example, regions with bad terrain or at borders or any
undisclosed high security perimeter. Long-lived sensor networks are required to reduce
maintenance costs, inclusive of the person-hours of time entailed by the necessity of
regularly patrolling the ostensibly secured perimeter to test for battery voltage decline
and the attendant failure of the sensor system.
Power management strategies need to be employed to ensure longevity of the sensor
networks. Smart sensor-based surveillance systems deliver enhanced performance when
sensor fields are employed with electronic intelligence implemented at sensor nodes.
Intruders in remote locations are scarce and an event is considered a rare event. The
main processing block within the sensor need not be on continuously and as a result can
be in a sleep state. The main processing block classifies the kind of intrusion, whether a
threat or not. An ultra-low-power front-end sensor is always on to detect events. If a true
event has occurred, eliminating false positives, the main processing block is turned on.
We have designed and tested a subthreshold event detector chip for movement and
seismic detection for perimeter intrusion [1] and [2]. The features of the chip are: 1) The
front–end consumes 40 nW of power and such ideas can be implemented in other devices
where battery life is of crucial importance. The tremendous improvement in power

2

consumption implies longer life as well as the ability to add more processing capability
on chip. 2) Optimal stages of the system have been designed, in particular, band pass
filters, rectifier, divider and level converter. 3) A noise cancelling mechanism helps
improve the systems SNR, it also rejects false positives received from generators, motors
or any other constant noise sources. 4) Two filters clean the incoming signal as well as
do a pre-classification for footstep and vehicle signals.
Subthreshold operation affords extremely low power consumption, with transistors
being barely switched on. In this region, current in CMOS transistors has an exponential
relationship with the gate voltage applied. Due to this exponential behavior, small
changes PVT can dramatically affect the current in a transistor and alter the performance
of subthreshold circuits.
To overcome variability in subthreshold circuits, constant transconductance is required
to keep gain and bandwidth of several analog integrated circuits constant with PVT. Past
constant transconductance circuits have various drawbacks. The issues with them are
that they have precise external resistors, accurate clocks or strong inversion transistors
emulating on-chip resistors. The constant transconductance designed has no external
components, no resistors or switched capacitor circuits that require clocks and no strong
inversion transistors in order to keep the power low.
This Doctoral Thesis is organized as follows. Chapter 1 introduces seismic sensors
and signals for different stimuli. A case for the use of subthreshold analog circuits is also
discussed, mentioning the previous all-digital version of the seismic sensor followed by
other digital and analog low power approaches. Chapter 2 summarizes subthreshold
CMOS physics along with the inherent variations. Chapter 3 develops the method for the
entire subthreshold event detector system and the various circuit blocks. Chapter 4
discusses the hardware and chip results followed by the event detector conclusion in
Chapter 5. Chapter 6 tackles the mismatch and PVT sensitivity issue, by introducing the
constant transconductance bias circuit. False-positive rejection design is also discussed.
Concluding remarks of the Thesis are in Chapter 7.

3

1.1 Background: Seismic sensor and signals
A brief description of the sensor will be given followed by the types of signals
generated by different stimuli.
The geophone used in the seismic sensor as in [3] is a single axis seismometer
measuring motion in the direction of its cylindrical axis. For near surface deployments,
the geophone is packaged with a conical spike and buried a few inches underground to
ensure good coupling to vibrations from the ground. Motion in the ground causes the
hollow cylinder of the geophone to move with respect to the geophone housing. The
motion of the cylinder is measured by the interaction of the coil on the cylinder with the
magnetic field of the permanent magnet inside the geophone.
Faraday’s law states that the voltage across a coil is equal to the change in flux
through the coil with respect to time. In the case of a geophone, the change in flux
through the coil versus coil displacement, δ(φ)/δ(X), is constant for small displacements.
Therefore, the voltage across the coil is directly proportional to the velocity of the coil.
Geophone manufacturers typically report the constant of proportionality, G [V/(m/s)],
known as the transduction constant or generator constant. Huan and Paters demonstrated
that G varies by less than 0.005% as a function of position for displacements on the order
of 10% of the maximum displacement [4]. The response of a geophone is completely
substrate dependent. Rigidity, moisture, and temperature of the substrate can alter the
output signal of the geophone.
The signals generated by vehicles and human footsteps are shown in the Figure 1.1
and Figure 1.2. From the spectrogram we can that the vehicle signal has more of a lower
frequency component, whereas the footstep signal which has can be seen as discrete
footstep has lower as well as higher frequency components. It is due to this difference in
frequency spectrums that a pre-classifier is used in the event detection stage of the
seismic sensor. Two spectral components are obtained from the signal using an FFT,

4

after which each component has different gain settings depending on the environment and
weather vehicles vs. footsteps need to be detected.

Figure 1.2: Footstep data.
T im e
Frequency
0 2 4 6 8 1 0 1 2 1 4 1 6
0
2 0 0
4 0 0
0 2 0 0 0 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 1 4 0 0 0 1 6 0 0 0 1 8 0 0 0
-0 . 0 5
0
0 . 0 5
0 . 1
0 . 1 5
J T D A U G 0 7 t h R U N N C H 0 6 2 7 . w a v

Figure 1.1: Vehicle data.
T im e
Frequency
0 5 1 0 1 5 2 0 2 5 3 0 3 5
0
2 0 0
4 0 0
0 0 .5 1 1 .5 2 2 . 5 3 3 . 5
x 1 0
4
-0 .0 5
0
0 .0 5
0 . 1
0 .1 5
D o m e J U L 3 rd V E C H C H 0 5 3 2 . w a v

5

1.2 Why subthreshold analog
In this chapter, we will introduce the complete digital version of the seismic sensor,
then talk about an all digital low power event detector system as well as some analog
approaches and then build towards a complete subthreshold analog event detector.
1.2.1 Previous version of seismic sensor
The present working vibration sensor in [5], called the Smart Fence Unattended
Ground Sensor (UGS), shown in Figure 1.3, brings advanced situational awareness to
perimeter security. The current sensor only constitutes digital micro-processors. The
seismic based human threat sensor is to detect approaching humans and discriminate
between series of events caused by animal, and passenger vehicles vs. background and a
single vibration event, e.g. the falling of a tree limb. A geophone based seismometer has
been employed which is an inexpensive sensor that provides easy and instant deployment
as well as long range detection capability. The system was set up to discriminate between
human footsteps, vehicles, background (including disconnected incidents, animals’
footsteps). As soon as any event is detected a command center GUI raises alerts and
slews video for threat confirmation when ground sensors detect the approach of human
footsteps and the track of a vehicle to a virtual perimeter or fence-enhanced area. The
green box in Figure 1.3 consists of the circuitry; there is also a geo-sensor or vibration
sensor along with an antenna to communicate with the command center. In its idle state,
power consumption is 2 mA over 3.7 V (7.4 mW), which is being reduced in the new
approach taken in the paper.
The developed security system is equipped with functions to achieve significant long-
term reliability, power efficiency, load sharing, and rules-based functionality that beget
enhanced general system maturity. But in its current embodiment, the batteries used to
power these sensors have an operational life of no more than one year, which is not long
enough for practical deployment in the field. The judicious exploitation of subthreshold
electronics, as described in the forthcoming sections, affords a large magnitude of

6

increased battery life. As such, the USC sensor system proves ultra-low-power
operability of next generation perimeter protection.

Figure 1.4 shows the seismic event detector consisting of the seismic sensor followed
by a passive low pass filter to cancel high frequency noise. The block between letters A
and B is the event detector that is on continuously and wakes up the power hungry micro-
controller (that is mostly in the sleep state) only when an event has been detected. When
an event is detected there is an output that goes for gait analysis in the next stage (the
microcontroller after letter B) in Figure 1.4. This analysis classifies the threat. The event
detector in the previous generation of the seismic sensor was an off the shelf digital
microcontroller that consumed 7.4 mW of power. More details are in the forthcoming
sections.

1.2.2 Low power digital approaches
Digital processing at this end can also be used, but apart from the processing, a digital
implementation mandates the additional complication of analog -to- digital and digital -

Figure 1.4: Digital seismic sensor.

Figure 1.3: UGS seismic sensor.

7

to- analog converters, which certainly burn additional power and consume additional on
chip surface area.
If we were to use a low power ADC, to convert the seismic signal into digital, after
which, custom digital circuits can be built for the further processing. Low power ADCs
can be used for the first stage before off the shelf DSPs. Successive Approximations
ADCs (SAR ADC), sigma-delta ADCs, flash converters, pipelined ADCs, etc can be
used. An 8 bit SAR in 180 nm CMOS as in [6] consumes 27 nW along with an 8 nW
leakage power with a FOM of 79.9 fJ/Conversion step at 2 kS/s. A flexible SAR with 7–
10 bits and 0-4 MS/s with 6.5-16 fJ/conversion step is shown in [7] consumes 17.44 µW
for 10 bit resolution. Depending on the application there are various types of ADCs to
choose from. For biomedical applications an 8 bit 500 kS/s SAR ADC consuming
7.75 µW is shown in [8]. In addition to the SAR, that already consumes decent amount
of power an off the shelf DSP. A DSP from Texas Instruments like the C5000 ultra-low-
power DSPs, has a standby power of 0.15 mW already.
There are other dedicated DSP systems used for hearing aids as in [9]. In this
applications specific digital design that consists of A/D and D/A along with memory, a
weighted overlap-add (WOLA) filter bank and a 16 bit DSP core, the power consumption
over a 1.2 V cell is 2.16 mW. The basic structure to build a custom digital system for this
application would required low powered A/D and low power Multiply-Accumulate
(MAC) blocks, along with some memory. MACs can consume power from 6.9 mW to
0.23 mW as in with different speeds of operation as in [10] and [11]
1.2.3 Low power analog approaches
An analog approach to designing a MAC as in a Vector Matrix Multiplier (VMM) is
shown in [12]. For a bandwidth of less than 10 MHz, this architecture can perform 1
million MAC operations/0.27 µW compared to TI’s DSP (TMS320C55105x series) that
gives 1 million MAC/0.25 mW. This shows that taking an analog approach can save a lot
of power. But the event detector can be designed using analog filters.

8

The ultra-low-power front-end event detector can be designed like a low power
cochlea as in [13] and [14], where frequency bands are compared. The biological cochlea
can sense sounds over twelve orders of magnitude in intensity, providing a large dynamic
range with only a few tens of microwatts. The wide dynamic range is attained through
the use of a wide linear range transconductance amplifier along with dynamic gain
control at each cochlear stage. Since the range of the geophone is within the audible
sound range, ideas from the cochlea can be harnessed.
Other methods for low power event detectors use a time-domain approach instead of
frequency analyses using band pass filtering. Such approaches are based on
autocorrelation as in [15], consuming 835 nW of power, and periodicity detectors of a
time-domain envelope of acoustic signals as in [16], consuming 1.8 μW. The former has
a periodicity estimator algorithm based on the ‘bumpiness’ of the autocorrelation of a
one-bit version of the signal. In the latter a peak detector is used, after which a spike
generator produces a voltage spike at the peak. The intervals of the spikes are converted
to voltages through an interval to voltage stage. For a particular frequency there should
be a certain number of spikes and this is how the periodicity detector catches a particular
frequency in the signal.
These approaches are all analog solutions to different types of event detectors with
different functionality. Ideas can be adopted for the seismic event detection along with
the pre-processing needed for our system.
1.2.4 Subthreshold analog approach
The motivation for moving from the current digital sensor system to an analog system
is for the extremely low power operability, architectural simplicity and area compactness,
of transistors in the analog sub-threshold region of transistors. The advantage of an all
digital computation is its cheap and potentially unlimited precision and dynamic range.
However, such precise precision is not needed for tasks corresponding to perception of a
continuously changing environment. Low precision analog VLSI circuits are suited for

9

the task of event detection especially when cost, size and power consumption are the
biggest concerns [17].
The behavior of complementary metal-oxide-semiconductor (CMOS) transistors is
similar to that of bipolar junction transistors (BJTs) in this region and there is very little
current flow comparable to the leakage current flow in transistors. In [18] Gilbert shows
the translinear historical overview of BJTs with their exponential I–V relationship and
applying the same principle to CMOS only when the I–V relationship is exponential, that
is when CMOS is operated in subthreshold domain. The drain currents rarely exceed
several hundred nano-amperes, while requisite threshold voltages in 150 nm technology
are generally smaller than 400 mV. Thus using these transistors in this region can
dramatically decrease the power consumption of the sensor.
Moreover, in the subthreshold operating regime, the applied gate-source voltage,
which lies slightly below the device threshold voltage, is chosen to ensure that the
potential between the gate oxide layer and the semiconductor surface of the transistor lies
nominally at one Fermi potential for all time. In this regime of operation, the drain
current vs. gate-source voltage characteristic abides by a simple exponential relationship
as in (2.14) in the next chapter when V
DS
(drain-source voltage) is high.
The only caveat in designing subthreshold circuits is its intrinsic variability due to
process and temperature variations. More about these variations will be discussed in the
next chapter.

10

Chapter 2
Subthreshold MOSFET Overview
A brief overview of subthreshold Metal-Oxide-Silicon Field Effect Transistor
(MOSFET) is discussed in this section. The device physics with equations for MOSFETs
operating in subthreshold region will be discussed along with variations observed in these
transistors. The current in the subthreshold region depends exponentially on the applied
gate voltage, having similar characteristics with the bipolar junction transistor (BJT).
BJTs are used in applications that need higher current drive and for lower offsets between
transistors. In the current project, low power is vital and thus MOSFETs are chosen
operating in the subthreshold region because they draw very small currents.
2.1 Subthreshold physics
A MOSFET consists of a MOS structure and two p-n junction diodes. An n-MOSFET
is shown in Figure 2.1a. The NMOS is placed in a p
-
substrate or body. The n
+
regions
act as the source and drain, where the majority carriers are electrons. The region under
the gate, between the source and drain is the channel and has dimensions, width W and
length L.
Depending on how the MOSFET is biased there are several regions of operation. But
we will only talk about the subthreshold region, where the gate voltage V
g
is less than the
threshold voltage V
T0
. V
T0
delineates the subthreshold and above threshold regions of
operation. The bias voltages applied to an NMOS is shown Figure 2.1b.

11

Increasing V
g
increases the positive charge on the gate, repelling holes from the p
-
substrate in the channel region, leaving behind negatively charged ions balancing the gate
charge. In the above threshold region, if V
g
is increased more than V
t
an inversion region
is created in the channel consisting of electrons, but since we are talking about the
subthreshold region, the channel is devoid of any charges and is thus called the depletion
regions. The depletion region can be seen in Figure 2.2a. The energy band diagrams are
shown in Figure 2.2b and c. In the figure the axis for electron energy is upwards, while
the positive voltage axis is downwards. E
F
is the quasi-Fermi level.
The following discusses the Fermi level and describes how to find the concentration of
electrons in the source and drain regions [19]. The occupation of energy states follows
the Fermi-Dirac probability distribution. The probability that an energy state E is
occupied is given by

= 1 +

(2.1)
where E
F
(Fermi level) is the energy where the occupation probability is half, k is the
Boltzmann constant and T is absolute temperature. When |E – E
F
| >> kT, (2.1)
simplifies to
=

/
(2.2)
and the electron density dn(E,dE) in an energy interval dE around an energy E is given by
, = (2.3)

a) b)
Figure 2.1: a) NMOS cross-section. b) Biases applied to NMOS.

Source
Gate
Drain
L
n
+
n
+
p
-
W
Body

12

The total electron density in thermal equilibrium, with no external voltages applied, is
found by integrating (2.3) from the conduction band boundary to infinity, resulting in
=

/
(2.4)
where N
C
is the number of energy stages in the conduction band near its edge.
Looking at Figure 2.2 energy diagrams. The electron concentrations and the source
and drain ends depend on the energy barrier. This barrier is determined by the voltage
difference between the surface potential ψ
s
and the applied voltage V
s
and V
d
. The barrier
heights θ at the source and drain ends are given by

=

− ψ

−

(2.5)

=

− ψ

−

(2.6)
where θ
0
= qV
bi
is the built in energy barrier between n
+
and p
-
substrate, ψ
s
is assumed
to be constant. Using (2.4), (2.5) and (2.6) we can find the electron density at the drain

a)

b)

c)
Figure 2.2: NMOS in subthreshold a) cross section, b) energy band diagram in linear region, c)
energy band diagram in saturation region.
I
s-diff
E
C
E
F
E
V
E

13

and source regions, by

=

/ !
=

/ !
=

"

#$ψ

%

&
/ !

(2.7)
N
0
is the number of states per unit area in the channel. This applies to the drain as well.
From Figure 2.2b, since the barrier at the drain is higher that the source, the concentration
of electrons at the drain is lower and the differential leads to electrons diffusing from the
source to the drain.
The current in the channel is now given by

' = (
),*++
,- = −,- .
)

/

(2.8)
where J
n,diff
is the diffusion current density, t is the thickness of the channel, D
n
is the
diffusion coefficient and dN/dz is the concentration gradient across the channel. The
concentration gradient is

/
=

−

0
=

0

ψ

1
2

%
3
1
2
−

%

1
2

(2.9)
U
t
= kt/q and N
1
= N
0
e
-θo/kT
, and plugging into (2.8) we get

' = '
4

ψ

1
2

%

1
2
−

%
3
1
2

(2.10)
where I
t0
= q(W/L)t

D
n
N
1.

The surface potential varies with V
g
, and assuming small change about an operating
point we express ψ
s
as
ψ

= ψ

+ κ
6
(2.11)
where κ is the capacitive coupling ratio from gate to channel, with this we can express
the current by

' = '

κ
%
7
1
2

%

1
2
−

%
3
1
2

(2.12)
or

14

' = '

κ%
7

%

1
2
1 −

%
3
1
2

(2.13)
As V
ds
increases, as can be seen in Figure 2.2c, the diffusion current no longer depends
on the drain, since the barrier is to large and the concentration at the drain is not
comparable to that at the source and thus (2.13) can be rewritten as

' = '

κ%
7

%

1
2

(2.14)
Figure 2.3 shows the I–V graph for an NMOS, in log scale. The first linear portion with a
slope is the subthreshold region.
If there is body effect, the effect on the surface potential is seen as
8ψ

= 1 − κ8
9
(2.15)
and (2.12) becomes

' = '

κ%
7
:
κ%
;
1
2

%

1
2
−

%
3
1
2

(2.16)
It has been shown in [20] and [25] that the pre-exponential factor I
0
is

'

= 2
,
0
=
4
>
?@
A

κ%
!"
1
2
/κ
(2.17)
where V
T0
is the threshold voltage.

Figure 2.3: Current vs. gate source voltage in log scale.
0 0.5 1 1.5 2
-35
-30
-25
-20
-15
-10
Voltage (V)
Current (log scale)

15

The small signal model for an NMOS is shown in Figure 2.4. The small signal
transconductances are found by differentiating the current in (2.12) about their respective
control voltages. We then get
B
C6
=
8'
8
6
=
κ'
=
4
(2.18)

B
C
= −
8'
8

=
'

κ%
7

%

/1
2
=
4

(2.19)

B
C
= −
8'
8

=
'

κ%
7

%
3
/1
2
=
4
+
'

D

(2.20)
The second term in (2.20) is due to the channel length modulation effect in the saturation
region.
2.2 Variations in subthreshold domain
The effect of temperature on the transistor characteristics is as a result of temperature
dependencies on V
T0
, κ and µ. V
T0
and κ vary due to the Fermi potential and μ varies by
? ∝ F

G
(2.21)
where α depends on the doping concentration.

Figure 2.4: Small signal model for NMOS.

16

Mismatches in transistors due to differences in dimensions or variations in physical
parameters are reflected as differences in V
T0
, κ and β. From [20] and [24] the standard
deviation of the relative difference in currents is given by

H∆'
'
= JH
>
∆K + [
B
C
'
H∆

]
>

(2.22)
In subthreshold regime this tends to

H∆'
'
= H∆

κ
=
4
(2.23)
Similarly if two equal current are supplied to two transistors the standard deviations of
the offset seen at the gates will be

H∆
6
= NH
>
∆

+ [
'
B
C
H∆K
K
]
>

(2.24)
In subthreshold region this tends to
H∆
6
= H∆

(2.25)
From (2.23) and (2.25) we see that the current mismatch is higher for subthreshold

a) b)
Figure 2.5: Histogram of current for different transistor sizes. a) W = 1 μm and L=150 nm, b)
W=1 μm and L=8 μm.
-10 0 10 20 30 40
0
0.5
1
1.5
2
2.5
3
3.5
4
Current (nA)
Number
0.8 1 1.2 1.4 1.6
0
0.5
1
1.5
2
2.5
3
Current (nA)
Number

17

region. To reduce the deviation and since H∆

∝

√PQ
, we need to increase the area
of the transistor. Figure 2.5, shows that for a larger area, the standard deviation in the
distribution for the drain current is less. The average and standard deviation for Figure
2.5a) are 7.3 nA and 4.52 nA and for b) are 1.0865 nA and 79.15 pA respectively.

18

Chapter 3
40 nW Subthreshold Event Detector for
Seismic Sensors
The following describes the overall system level design followed by the circuit level
of the blocks within the system. The circuits are designed in a 150 nm process in the
subthreshold analog CMOS domain.
3.1 System level
Figure 3.1 shows the seismic event detector consisting of the seismic sensor followed
by a passive low pass filter to cancel high frequency noise. The signal measured from a
geophone has a 0.1 Hz ~ 200 Hz frequency range due to the resonant characteristics of
the sensors. Although the frequency response of the seismic sensor is in a narrow
frequency band, spectral analysis can be used for discriminating between seismic events
caused by human footsteps (or four-leg animals) and vehicles.

The block between letters A and B is the event detector that is on continuously and
wakes up the power hungry micro-controller (that is mostly in the sleep state) only when
an event has been detected. When an event is detected there is an output that goes for gait

Figure 3.1: Digital event detector.

19

analysis in the next stage (the microcontroller after letter B) in Figure 3.1. This analysis
classifies the threat. The event detector in the previous generation of the seismic sensor
was an off the shelf digital microcontroller that consumed 7.4 mW of power and had a
short battery life as had been explained in the earlier section.
The work here reports the power efficiency of the new event detector block operating
in subthreshold analog CMOS domain and has been expanded in Figure 3.2. From earlier
studies it has been shown that, in order to catch spectral information for footsteps or
vehicles, a low and a high frequency band is required. Two different bands within the
geophone range have been chosen to catch spectral information about the vibration
sources. One band pass filter is centered at a low frequency and the other at a higher
frequency, as can be seen in the figure.

In the digital version a fast Fourier transform (FFT) is carried out at these two
different frequencies. In the subthreshold case the analog of an FFT is carried out by
finding the power of the two frequency bands. The forthcoming processing relates to both
frequency bands and only one signal path will be talked about. The band pass filtered
signal goes through an envelope detector to catch the peak voltage of the time varying
signal. The envelope detector consists of a full wave rectifier followed by a peak
detector. Although the result is a peak voltage at each frequency band, it is a measure of
the power at the band, with the voltage being the square root of the power.

Figure 3.2: Subthreshold event detector.

20

A comparator is used to detect whether a certain threshold has been passed. If the
summation of the voltage peaks from both bands is higher than a threshold an event is
triggered. If that were the case loud noise sources at those frequencies would trigger the
system unnecessarily. Therefore a comparison of the voltage amplitude (VA) with the
Back ground noise (BG) value is carried out as can be seen in (3.1). The three
components after the peak detector, namely the subtractor, divider and the averaging
circuit are for that purpose. The averaging circuit is used to catch the background noise
level, which is the average of past samples of the input signal.

R

− ST

ST

(3.1)
VA
1
is the peak voltage of the low frequency band, BG
1
is the Background noise level of
VA
1
. If VA
1
is sufficiently higher than BG
1
, only then will there be an event; after carrying
out the other processing and comparing with the threshold.
The contribution from each of the signals as in (3.1), are adjusted using Gain
1
and
Gain
2
. The different gain settings are used for different environments, where one or the
other frequency band needs a boost compared with the other. Equation (3.2) shows the
mathematical operations taking place in the wake up detector. The indices 1 and 2
represent the two signal bands.

R

− ST

ST

TUV

+
R
>
− ST
>
ST
>
TUV
>
> FℎYZℎ[\ (3.2)
A level converter is used to boost the subthreshold low output voltage from the
comparator. As soon as an event is detected at letter B in Fig. 3, the switch before the
averaging circuit is opened and at that point VA is compared with a constant BG value.
After many of such events, the main controller is woken up and the input from letter A
goes directly to the micro-controller (at letter B) for further processing.
Some issues to consider when operating in subthreshold region are that the level of the
input should be in a 100 mV range and the noise of the system should be low. The
sensitivity level compared to the dynamic range is more important because the low end of

21

the voltage signal is limited by noise and the dead-zone of the rectifier, but the high-end
of the voltage signal will only saturate the system and will be higher than the set
threshold. Since a thresholding function takes place, purity of the signal at the output is
not required after crossing the threshold.
3.2 Circuit level
Various blocks of the system will be discussed in detail along with topology choice
and optimizations. The blocks discussed are a band pass filter, envelope detector, divider,
adder/subtractor, comparator, level converter and buffer.
3.2.1 Band pass filter
In the digital system only key features are extracted from the incoming signal. Only
the 40 Hz and 100 Hz components are selected after a Fast Fourier Transform (FFT) is
done using the Goertzel algorithm. The Goertzel algorithm is an efficient method to
evaluate individual terms of a Discrete Fourier Transform (DFT). Thus only particular
frequencies of interest are obtained making it an efficient tool to catch the two
frequencies of interest.
Moving from the digital logic to an analog architecture, the DFT can be done using
two band pass filters (BPF) centered at 40 Hz and 100 Hz with a large Q. Large Q is
required as the Goertzel algorithm only passes the required frequencies. The general
transfer function of a BPF is as follows

] Z =
^Z
Z
>
+ _
`
)
a
b Z + `
)
>

(3.3)
where s is the complex frequency, b is a constant, Q is the quality factor and ω
n
is the
center frequency. The bandwidth of the system is given by
c
d
e
. Since we want large Q, a
filter with the following specifications was designed using MATLAB. For the 40 Hz

22

filter the pass band was chosen from 37 Hz to 43 Hz, the stop band at 32 Hz and 47 Hz,
and the stop band attenuation at 10 dB. The filter obtained is as follows

] Z
=
0.000412Z
>
− 1
Z
>
− 1.99950Z + 0.99954

0.000412Z
>
− 1
Z
>
− 1.99957Z + 0.99959

(3.4)
The filter can be realized using passive components, but with the very low frequency
of operation, the inductor would be very large and not realizable physically on chip. The
next approach would be to design an active filter. Opamps can be used to realize
inductors, but opamps would draw a lot of current especially for the current application
and thus transconductance stages have been used instead and realizing the function as in
(3.3).

A versatile Operational Transconductance Amplifier (OTA) biquadratic structure as in
[25] is shown in Figure 3.3. It is a versatile structure as various types of filters can be
constructed with the same structure. The response at E
2
is given by

>
=
Z
>
@

@
>

l
+ Z@

B
C>

m
+ B
C
B
C>

Z
>
@

@
>
+ Z@

B
C>
+ B
C
B
C>
(3.5)
Different types of filters can be obtained by eliminating some of the terms. For
example for a BPF, E
1
= E
2
= 0 and the input is applied at E
4
. In this configuration the
response is given by

Figure 3.3: OTA biquad.

23

>

m
=
Z@

B
C>

m
Z
>
@

@
>
+ Z@

B
C>
+ B
C
B
C>
(3.6)
where the characteristics of the filter are as follows
`

= N
B
C
B
C>
@

@
>
(3.7)

a = N
B
C
@
>
B
C>
@

(3.8)
Ratios of capacitors or transconductances (g
m
) can be controlled with some accuracy,
from (3.13) and (3.8) it can be seen that the Q can be well controlled compared with the
center frequency, ω
0
. There are various other topologies of OTA based filters. Adding
more OTA stages to make a three-, four- or five- stage OTA will give the filter more
parameters to control for the center frequency, Q and the gain as well, but this will add to
the power of the system, and thus a two stage OTA filter is used as in Figure 3.3.
The OTAs can be designed using fully differential structure with single ended outputs
as in Figure 3.3, or a differential output OTA can be used as well to enhance common
mode rejection ratio, but would add more transistors and more power. There were
linearity concerns with this structure. Operating in subthreshold region requires very low
input voltages at the gates of the transistors. To show the effective voltage at the input of
the g
m2
OTA an equivalent circuit is shown substituting R
in
as in the Figure 3.4.
The value for the inductor and resistor are in terms of circuit parameters are as follows

Figure 3.4: Input resistance of BPF in Figure 3.3.
C
1
E
4
E
5
R
in
L
R

24

0 =
@
>
B
C
B
C>
(3.9)
n =
1
B
C
(3.10)
By substituting values, we find the voltage at E
5
at the center frequency to be

o

m
= N
@
>
B
C
@

B
C>
+ 1
(3.11)
and with the present values we get
o
>
m
, which causes linearity issues in the g
m2

OTA.
It was due to linearity issues especially while operating in the subthreshold region that
a capacitively coupled current conveyor (C4) [26] [27], shown in Figure 3.5a, has been
chosen over other band pass filter structures. The reason for this choice is its simplicity
and compactness. Analog filters consisting of G
m
–C (G
m
being the transconductance and
C the capacitance) filters are used to operate in the megahertz range [28], as compared to
filters based on op-amps (operational amplifiers). Since the operating frequency range for
this application is very low, < 100 Hz, the time constants associated with the filter are
large. For traditional integrated resistance values, these large time constants require very

a) b)
Figure 3.5: a) OTA C4. b) Equivalent circuit.

25

large shunting capacitances, which are impractical to implement in circuit monolithics.
An OTA operated in subthreshold regimes can be configured to deliver very large
two-terminal resistances that allow large time constants to be forged with small and
therefore integral capacitances. This will be more apparent with the transfer function of
one of the stages of the G
m
–C filter or in particular the C4 filter in this case. Equation
(3.13) is the transfer function for one sections of the C4. For low center frequency, low
capacitance values can be chosen if the transconductance values (g
m
) are low, as can be
seen in (3.14). Equation (3.15) shows the gain and (3.16) shows the relationship of the
quality factor of the C4 circuit. A crucial frequency to reject is the 60 Hz power line noise
and therefore large Q is required.
The complete transfer function of the C4 structure is as follows

p4

=
Z@

Zq
l
− B
C>

Z
>
r@
m
+ @
l
@

+ @
>
+ @
m
@
l
s + Z@
m
B
C
+ @
l
B
C>
+ B
C
B
C>

(3.12)
with @
l
≪ Bu
>
, we then get a BPF transfer function as follows

p4

=
−Z@

B
C>
Z
>
$@
m
+ @
l
@

+ @
>
+ @
m
@
l
&+ Z@
m
B
C
+ @
l
B
C>
+ B
C
B
C>

(3.13)
`

= N
B
C
B
C>
@
m
+ @
l
@

+ @
>
+ @
m
@
l
(3.14)
TUV=
@

B
C>
@
m
B
C
+ @
l
B
C>

(3.15)

a =
J$@
m
+ @
l
@

+ @
>
+ @
m
@
l
& B
C
B
C>
@
m
B
C
+ @
l
B
C>

(3.16)

26

where V
out
is the output voltage, V
S
is input signal, s is the complex frequency, g
m

represents the transconductances of the transistors M
1
and M
2
and C is the capacitance
found in the circuit.
Large Q is required and in fact larger Q is achieved by placing four such C4 stages
back to back. The reason for this is to obtain spectral purity at one particular frequency
and to reject other noise sources say come from 60 Hz hum from electrical power lines
and transformers. The required Q can be obtained with just one stage, but because of the
interdependencies of the Q on gain through the above equations, only one parameter can
be adjusted for at a time. Hence the four stages have been cascaded to create the
necessary filter specifications. The first stage adds the gain to the filter and the other
three stages have gains close to unity gain so as not to create large signals at the final
stage, thus maintaining subthreshold operation. The last three stages are there only to
increase the overall Q of the filter. The specifications of the band pass filter are shown in
Table 3.1 and the response is shown in Figure 3.6b.

3.2.1.1 Input impedance of BPF
Figure 3.5b, shows the equivalent input resistance seen at the gate of the g
m2
OTA.
The values of the equivalent circuit are as follows
0
D#
=
@
l
@
m
B
C
B
C>
(3.17)
Table 3.1: BPF performance.
Features

Power 612 pW
Bandwidth 4 Hz
Q 10
Rejection in stop band 45 dB
Noise 30 μV
rms
(input referred)

27

@
D#
=
@
l
@
m
@
l
+ @
m
(3.18)
n
D#
=
B
C
@
m
+ B
C>
@
l
@
l
+ @
m
(3.19)
Through simulation it can be shown that when C
2
> C
1
, a voltage division can be seen
at the input of the g
m2
OTA, and thus enhancing linearity. Each of the transconductances
can be replaced by traditional differential pair structures, but using just a single transistor
can offer a compact OTA structure as shown in Figure 3.7.
3.2.1.2 Maximizing Q
It has been shown in [27], that in order to maximize the Quality factor, the condition
stipulated by (3.20) is required. And that results in (3.21), along with a gain as in (3.22).

B
C>
B
C
=
@
m
@
l
(3.20)

a
CvA
=
1
2
w
@

+ @
>
+ @
l
+ @

+ @
>

@
l
@
m

@
l

(3.21)

a) b)
Figure 3.6: a) Q vs. g
m
ratio; maximizing Q. b) BPF frequency response.
10
-2
10
0
10
2
1
2
3
4
5
6
7
gm
1
/gm
2
Q
10
0
10
1
10
2
10
3
10
4
10
5
-150
-130
-110
-90
-70
-50
-30
-10
10
30
50
Frequency (Hz)
Voltage gain (dB)

28

TUV=
1
2
@

@
l
(3.22)
By varying the g
m
ratios we can find the peak of Q. Figure 3.6a, shows the peak of Q
at about a ratio of 1 for the capacitance values chosen. Using this technique the values
for C
4
and C
3
are chosen, and from the graph these capacitors are almost equal to each
other. Also from (3.21), we can see that for large Q we need to have small C
4
and C
3

and large C
1
+ C
2
. The lower bound on C
4
and C
3
is dictated by the parasitic caps at those
nodes of the order of 30 fF. And the upper bound on C
1
+ C
2
is constrained by area per
cell and thus a maximum of 20 pF was chosen.
3.2.1.3 Design algorithm
Steps to designing low frequency filter at 40 Hz.
Step 1: Make zero frequency negligible. Let it be at least greater than 60 Hz by a
factor of 10. Condition on zero:

B
C>
@
l
≥ 2y600
(3.23)
And C
3
≥ 10 × parasitic capacitances. g
m2
should be set to a large enough value so that
current through transistor is at least above 30 pA, else noise would affect reliable current
and transconductance.

Figure 3.7: C4 BPF.
M
1
M
2
I
dc1
I
dc2
V
DD
C
2
C
1
C
3
C
4
Out
In

29

Step 2: From (3.21) large Q attained with large C
1
+ C
2
. Ratio can be chosen so as not
to cause distortion by keeping within linearity range for transistor M
1
. The constraint on
the gain to ensure M
1
operating in its linear range is:
TUV×
*)CvA
× B
C
≤ '
}
(3.24)
which can be simplified to:
TUV≤
=
4
~
1

*)CvA
(3.25)
Step 3: From (3.14), we can then find C
4
. As an example: The first stage has the
design variables g
m1
≅ g
m2
= 750 pS, C
3
≅ C
4
= 200 fF and C
1
= C
2
= 10 pF, providing a
center frequency of 40 Hz and gain at the center of 25 V/V with Q = 5.
3.2.1.4 Stage design and optimizing number of stages
Adding more stages to the design will increase the Q, but depending on the gains in
the stage, distortion also increases. Figure 3.8a has a cascade of one type of stage having
high gain and the output from the fourth stage sees distortion. This is due to the small
signal swing being larger than the DC current as in (3.24). Figure 3.8b shows a cascade
with two types of stages. The first stage has higher gain, whereas the second through
fourth stage have a gain close to 1 and were just added to improve overall Q of the

a) b)
Figure 3.8: a) High gain stages cascaded. b) High gain and low gain stages cascaded.
0.2 0.3 0.4 0.5
0.4
0.45
0.5
0.55
0.6
Time (s)
Voltage (V)

BPF1(gain=24dB)
BPF2/2(gain=45dB)
BPF3/4(gain=66dB)
BPF4/16(gain=88dB)
0.2 0.3 0.4 0.5
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.62
Time (s)
Voltage (V)

BPF1(gain=24dB)
BPF2(gain=26dB)
BPF3(gain=28dB)
BPF4(gain=30dB)

30

system as well as increase roll-off. This strategy also reduces overall noise factor. From
Friis formula for noise factor

44v
=

+

>
− 1
T

+

l
− 1
T

T
>
+

m
− 1
T

T
>
T
l
(3.26)
where F
i
and G
i
are noise factor and gain of each stage, we can derive the overall noise
factor of the band pass filter. Therefore if the first stage has the highest gain the noise
factor will only be dependent on the noise factor of the first stage and not as much on the
rest of the stages.

Figure 3.10 a and b, is similar to Figure 3.8b, except the second type stage has been
cascaded nine times to create a total of ten filters back to back or a twentieth order
system. The roll off increases by 20 dB × n (stages). But from Figure 3.10c we see that
the Q doesn’t increase as fast with increase in stage unlike the power that increases
linearly with number of stages. It is for this reason that four stages have been chosen
having a Q of 10. The rejection in the stop band (20 Hz and 60 Hz) by the four stage
BPF is 45 dB. That suggests a noise of 1 mV at 60 Hz gets reduced to about a 5 μV
60 Hz noise after the BPF.

a) b)
Figure 3.9: a) 10 stages cascaded (stage 1, type 1 filter and stages 2–9, type 2 filter). b) Normalized
response of a). Bandwidth becomes narrower with increase in stages.
10
1
10
2
-150
-100
-50
0
50
Frequency (Hz)
Voltage gain (dB)
0.5 1 1.5
-50
-40
-30
-20
-10
0
Normalized frequency (Hz)
Normalized voltage gain (dB)

31

3.2.2 Envelope detector
The envelope detector consists of three stages all of which are shown in Figure 3.11
and Figure 3.12. The first state is an OTA, which is used to convert the voltage signal
from the band pass filter into a current. I
out+
and I
out-
from the OTA feed into the input of
the rectifier at I
in+
and I
in-
respectively. The next stage is a current rectifier. Current
mode rectification is chosen as it is faster and works better than diode based rectifiers

Figure 3.11: OTA.
M
3
M
1
M
5
M
7
I
out+
V
B1
I
b2
M
4
M
2
M
6
M
8
I
out+
V
B1
I
b3
I
b1
V
DD
V
in+
V
in-

Figure 3.10: Q and power vs. number of stages.
2 4 6 8 10
4
6
8
10
12
14
16
Q
Stages

0
1
2
3
4
5
6
Power(nW)
Q
Power

32

[29]. After rectification a peak detector in Figure 3.12b is used to catch the envelope of
the signal. The I
out
from the rectifier is mirrored into the input, I
in
, of the peak detector.
The OTA used is a simple current mirror type OTA and the necessary gain is added in
this stage to overcome the dead-zone inherent in the rectifier. The rectifier structure uses
a conventional approach and can be seen in [30] [31]; but power is lower here because of
the subthreshold bias currents. The full wave rectifier consists of two Wilson current
mirrors to rectify both phases of the signal. Qualitatively, by looking at Figure 3.12a,
when I
in+
(OTA output current) is greater than I
bias
, the V
DS2
of M
2
drops to maintain the
same I
bias
with increased V
GS2
. This in turn drops V
GS6
and M
5
turns off. When I
in-
is less
than I
bias
and since M
1
mirrors I
bias
, the additional current is supplied by M
5
and the
current is seen at I
out
. Thus M
5
turns on and off in one cycle. M
8
acts the same way in
opposite phase and thus there is always an on current only in one phase and we have a
full wave rectification. The waveforms are shown in Figure 3.13, for a sinusoidal input.
The OTA output current, I
n+
, and the rectified output current are in the top graph. The
bottom graph shows the output voltage from the peak detector. Equation (3.27) shows the
limits on I
n+
and I
n-
in order to overcome the dead-zone.
'
*):
> '
9*v
€
o
� & '
*)

< '
9*v
€
o
� (3.27)

a) b)
Figure 3.12: a) Wilson current mirror as full wave rectifier. b) Peak detector.
M
1
C
1
I
in
I
b1
M
2
M
3
V
out
V
pd
V
DD

33

3.2.2.1 Minimum rectifiable current
The minimum rectifiable current is shown in Figure 3.14. For (3.27) to be true there is

b) b)
Figure 3.14: a) I
in
(supplied at inputs of rectifier) vs. I
out
, dead-zone of about 4 pA due to leakage. b)
V
in
supplied at input of OTA vs. rectifier I
out
for different V
B
bias voltages for OTA. Low bias
voltages forces lower leakage.
-50 0 50
0
10
20
30
40
50
Iin (pA)
Iout (pA)
-5 0 5
0
2
4
6
8
10
12
Vin (mV)
Iout (pA)

VB=450mV
VB=525mV
VB=600mV

Figure 3.13: Envelope detector response.
0 0.2 0.4 0.6 0.8 1
0
100
200
300
Current (pA)

OTA output current
Rectified current
0 0.2 0.4 0.6 0.8 1
0.32
0.33
0.34
0.35
0.36
Voltage (V)
Time (s)

Peak voltage

34

a bias current out of the OTA equivalent to I
bias
of the rectifier. Thus any current swing on
top of I
bias
will be rectified. Figure 3.14a shows output current from rectifier vs. input
current. The input current has been normalized excluding the constant bias current, showing
only current swings above I
bias
. It can be seen that although I
in
is zero there is an output
current of about 4 pA, due to the leakage in the output stage of the rectifier. It is due to this
leakage an I
in
above this leakage is required for rectification. Figure 3.14b shows how this
leakage current can be minimized. V
B
is a bias voltage on an output transistor of the OTA,
by minimizing this voltage we can see that the minimum current that can be rectified moves
from a little below 4 pA to about 2 pA.

Figure 3.15: The left graph shows a 40 Hz transient response with no noticeable dead-zone. On the
right a higher frequency (500 Hz) sinusoid produces a noticeable dead-zone.
0 0.05 0.1
-50
0
50
100
Iout (pA)

Iin
0 0.05 0.1
0
20
40
60
80
Iout (pA)

IM
1
IM
5
0 0.05 0.1
0
20
40
60
Time (s)
Iout (pA)

Iout
0 2 4 6 8
-50
0
50
100
Iout (pA)
0 2 4 6 8
0
50
100
Iout (pA)
0 2 4 6 8
0
20
40
60
Time (ms)
Iout (pA)
1 1.5
20
40
Zoomed-in

35

3.2.2.1 Dead-zone
Figure 3.15 shows effects on the rectification due to increase in frequency. The input
current has an I
bias
of 30 pA with a swing of 44 pA. On the positive phase M
1
turns on
while M
5
is off, the transistors switch states on the negative phase. M
1
consists of the bias
current, I
bias
, as well as the sinusoidal swing, whereas M
5
only consists of the swing of
44 pA, which is seen at I
out
. With increase in frequency to 500 Hz the response of
switching ‘on’ transistor M
5
is slower. This delay in turning M
5
on is the dead zone. The
zoomed-in inset shows this lag in M
5
turning on and thus resulting in distortion in the
rectifier’s output current.
3.2.2.2 Rectifier maximum frequency
Figure 3.16 shows a similar dead zone for the sub-vt system on the left, where as no
observable dead zone for the above-vt system. Following are the calculations to find the
maximum frequency of operation for a sub-vt rectifier.
As mentioned earlier with a swinging I
in
,V
GS
of M
2
and M
6
change, and this is done so
by charging caps C
1
, C
2
and C
3
. By increasing frequency the reactance of the capacitors
drop, thus requiring more charging current. Due to the low I
bias
in subthreshold, the
charging current is limited and thus the worst case dead zone can be calculated from this
limit.
'
9*v
= '
„…
+ '
>
+ '
l
(3.28)
When V
GS
of M
6
falls to zero, the current though M
6
should be zero save for a leakage
current of about 10 pA, the rest of I
bias
flows through C
2
and C
3
. Since M
6
and M
5
are
matched transistors we assume equal I
C2
and I
C3
equal to 10 pA each. This approximation
can be seen in the left graphs of Figure 3.16. When I
C3
peaks, M
5
turns on having a V
GS

equal to V
C3
. Also I
C3
should peak before the I
in
peaks in its negative cycle (or its
minimum value) or M
5
will never supply a full I
out
equal to the peak I
in
.
Assuming that the peak occurs at the middle of the limiting dead zone interval, which
is T/2 (when I
in
falls below I
bias
and T is the period of I
in
,) to 3T/4 (when I
in
is minimum)

36

and I
C3
is a triangular wave until its peak, the worst case dead zone (t
dz
) can be found
from below:
†
'
l
max
-
Š
4
3‹

- - = @
l
Δ
l
(3.29)
with I
C3
(max) of 10 pA, C
3
is 1 fF (from spice data), and ΔV
C3
shown between the gray
lines in the graph, equaling about 220 mV, we get t
dz
= 44 us, and shortest time period is
F = -
Š
× 4 × 2 (3.30)
giving us the maximum frequency at 2.8 kHz.

Figure 3.16: 1 kHz size wave applied to sub-vt (left) and above-vt (right) system. Sub-vt system
shows observable dead-zone, limiting frequency of operation.
0 1 2 3 4 5
0
30
60
90
I (pA)

I
in
I
M1
I
M5
I
bias
0 1 2 3 4 5
-10
-5
0
5
10
I (pA)

I
C3
0 1 2 3 4 5
0
100
200
300
400
Time (ms)
V (mV)

V
C3
0 1 2 3 4 5
0
0.5
1
1.5
I (uA)
0 1 2 3 4 5
-20
0
20
I (pA)
0 1 2 3 4 5
0
0.2
0.4
0.6
0.8
Time (ms)
V (V)

37

The dead zone can be reduced by increasing I
bias
, as there will be a larger I
C3
. Looking
at the graph on the right, the rectifier is above-vt with no observable dead zone. Although
ΔV
C3
would be larger to turn on a transistor in above-vt, the current I
C3
is larger and
incomparable to I
bias
. Since I
C3
just spikes for a small period of time, being the dead zone
in this case, it can be approximated by a pulse of the max I
C3
. Therefore, using values
from spice, we get
-
Š
=
@
l
Δ
l
'
l
= 21 μZ (3.31)
which is 4.2% of the half cycle (0.5 ms) of a 1 kHz sine wave.
3.2.3 Divider
The translinear principle can be used [32], because operating in the subthreshold region
results in the exponential relationship of the current with respect to the gate-source
voltage as in (2.14). By looking at the direction of the translinear loop drawn in Figure
3.17, and comparing with the direction the sources of the p-type MOS (PMOS), we
categorize the PMOS as f-facing or o-opposing. The voltage around the translinear loop
(the dotted arrow) drawn in the Fig. 4c from V
ref
to V
ref
should add up to 0 as in (3.32).
The PMOS devices facing in the direction of the loop result in a rise in voltage, whereas
the PMOS devices facing in the opposite direction result in a drop in voltage.

Figure 3.17: Divider.
M
2
M
5
I
x
M
1
V
DD
V
ref
I
y
I
u
M
3
M
4
V
ref
I
out
+
-
V
1
+
-
V
2
+
-
V
3
+
-
V
4

38

�
Ž�)�
�
Ž�)
)∈ )∈+

(3.32)
Where V
SG
is the source-gate voltage of the PMOS transistors in the figure and I is the
current flowing through each of the PMOS transistors. And because of the exponential
relationship of the current we get the following:

’ '
)�
)∈+
’ '
)
)∈

(3.33)
Using (3.33) and from the figure we get the following result:
'
p4
=
'
A
'
“
'
p
(3.34)
where, I
x
is the current representing VA, I
y
represents BG and I
u
is a scaling factor. The
constant scaling factor is adjusted for each of the two bands and is a representation of the
Gain
1
and Gain
2
blocks in Figure 3.2. The division can be seen in the simulations in
section 3.3. PMOS transistors are used instead of NMOS (n-type MOS) to avoid body
effect.
3.2.4 Adder/subtractor, comparator, level converter
The adder, subtractor and comparator have not been shown because of their simplistic
designs. The adder constitutes adding two currents by tying two wires together. The
subtractor is a differential pair and a comparator is also a differential pair with very high
gain so as to digitize the output.
The output does not swing too high because of the subthreshold operation. A level
converter is introduced into the circuit. A level converter is used to convert the
subthreshold voltage level of the core analog processing block for connection to the
outside world or connecting to digital processing blocks that require rail to rail swing.
Figure 3.18 shows the level converter. The structure shows a differential pair with cross-
coupled PMOS transistors that deliver the positive feedback to push the input voltage to

39

the supply level. Since inputs A and A ̅ are subthreshold inputs, the currents in M
1
and M
2

when on, are very low as compared to the above threshold currents in the PMOS as
shown in Figure 3.18a. The PMOS (M
5
or M
6
), when on, draw a large current to charge
the output load capacitance. To combat the strong PMOS; when the NMOS has to turn on
and discharge the capacitance, either the NMOS current should be made higher or the
PMOS weaker. The latter is chosen in order to maintain subthreshold operation [33]. As
can be seen in Figure 3.18b, the diode connected PMOS (M
3
and M
4
) is added to weaken
the PMOS.
3.2.5 Buffer
Some interconnections between different stages of the system need buffers depending on
the input impedance seen by a previous stage. There are some buffers at the end of the
system to talk to the outside world; that is, to drive test equipment. These buffers draw
some current but are only for the test equipment and can be turned off. A critical place
for buffers in the system is in between each of the stages of the BPFs. Loading from the
next stage can change the operating frequency and thus simple buffers are placed. The
buffers are designed keeping in mind the input resistance of the C4 BPF as can be seen in
Figure 3.5b. The buffer consists of a differential pair followed by a common source stage
to increase the loop gain of the buffer when connected in feedback. The buffer also has
miller compensation at the last stage along with a resistor to improve the phase margin.

a) b)
Figure 3.18: Level converter.
M
3
M
1
M
4
M
2
V
DD
A A
V
out
‘1’
‘1’
M
3
M
5
M
1
M
4
M
6
M
2
V
DD
A A
V
out

40

3.3 System simulations
SPECTRE is used to simulate the proposed event detector system using a 150 nm
process, with a supply of 1.8 V. The power consumed by the system is 40 nW. A footstep
signal which is a sampled input received from the geophone is used to simulate the
system. Figure 3.19 shows the time domain analysis of the system. The top graph shows
the sampled footstep signal, along with the 40 Hz BPF response. The bottom graph
shows the envelope of the BPF response and the green graph is the background averaged
value of the signal. From the graph it can be seen that the background changes very
slowly because of the slow or long averaging window. The bottom graph also shows the
final event after the components from both bands have been summed, compared and then
level converted. The final level converted signal goes from 0 V to 1 V which is sufficient
to turn on and off switches. Table 3.2 displays the features of the subthreshold analog
event detector designed.

Figure 3.19: Foot step simulation.
0 0.5 1 1.5 2 2.5 3 3.5 4
-4
-2
0
2
4
6
8
Voltage (mV)

0 0.5 1 1.5 2 2.5 3 3.5 4
0.55
0.57
0.59
0.61
0.63
0.65
0.67
Voltage (V)
Input
40Hz BPF
0 0.5 1 1.5 2 2.5 3 3.5 4
0.28
0.29
0.3
0.31
0.32
0.33
0.34
Voltage (V)
Time (s)

0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
1
1.5
2
2.5
3
3.5
4
Voltage (V)
Envelope
Background
Event

41

3.3.1 Noisy data and background-update-rate test in digital system
The following simulations relate to the digital system and are here only for
comparison purposes with the sub-vt system.
The first simulation in Figure 3.20 is of the same footstep data along with added
noises. 40 Hz, 60 Hz, 100 Hz and 120 Hz noise signals have been added to the footstep
data and the respective components of the system are shown in the same column. The
40 Hz instantaneous power along with the background signal of the 40 Hz component is
shown below the input signals followed by the 100 Hz power and background signals and
finally a processed sum with the events detected. The processed sum includes
multiplying factors and noise canceling, which has been explained in earlier sections.
Since this is a digital system the value on the y axis is only an integer value that
corresponds to real voltage values which have been converted with an ADC. The swing
of the input has amplitude of about 20, and the noise introduced has amplitude of 4.
The two filters in the system should only pass 40 Hz and 100 Hz signal components.
Thus no change can be seen with the 60 Hz and 120 Hz noisy data. The 100 Hz noisy
data shows an increase in the 100 Hz power and background level, due to the increase in
100 Hz at the input. A similar situation can be seen with the 40 Hz noisy data, in that the
40 Hz power and background level are increased compared with the other noisy
simulations. Less events are caught with the 40 Hz noisy data, this is because of the rise
in the 40 Hz background level, and due to the noise canceling effect, only very significant
Table 3.2: Subthreshold event detector specifications.
Features

Power supply 1.8 V
Current consumption 20 nA
Power 40 nW
Process 150 nm
noise 30 μV
rms
(input referred)

42

events would be caught. Whereas with the 100 Hz noisy data all events are caught, this
can be attributed to the fact that the 40 Hz multiplier is larger than the 100 Hz multiplier
and thus the events are triggered predominantly by the 40 Hz power and background
levels.
A seven second segment has been placed back to back for the next experiment with
two different background update rates. Figure 3.21 shows the system’s response with a
50 ms update and 12.5 s update. The 50 ms update catches all events for each 7 s

Figure 3.20: Noisy footstep data supplied to digital system. Each column shows the system’s
response to the different noisy data (footstep along with 40 Hz, 60 Hz, 100 Hz, and 120 Hz noise
from left to right). 40 Hz and 100 Hz spectral components shown along with events.
0 5
-20
0
20
0 5
0
2
4
6
x 10
4
0 5
0
2000
4000
6000
0 5
0
1000
2000
Time (s)
0 5
-20
0
20
0 5
0
2
4
x 10
4
0 5
0
2000
4000
6000
0 5
0
2000
4000
6000
8000
Time (s)
0 5
-20
0
20
0 5
0
2
4
x 10
4
0 5
0
1
2
3
x 10
4
0 5
0
2000
4000
6000
8000
Time (s)
0 5
-20
0
20

Input
0 5
0
2
4
x 10
4

40Hz component BG
0 5
0
2000
4000
6000

100Hz component BG
0 5
0
2000
4000
6000
Time (s)

Event Sum

43

segment. This is because the background is allowed to track the instantaneous power
with the fast update of 50 ms. The 12.5 s update rate shows that even for the first 7 s
segment, only the first three events are caught and likewise for the other 7 s segments
until the end of 40 s. this shows that the first three events are able to significantly
increase the background value as can be seen in the 40 Hz component, and since the
background value has been raised significantly the other events are not caught.

Figure 3.21: Footstep data with different update rates in digital system, 50 ms update (left), 12.5 s
update (right). With 12.5 s update, only first three events of each 7 s segment caught.
0 10 20 30 40
-20
0
20
0 10 20 30 40
0
2
4
x 10
4
0 10 20 30 40
0
2000
4000
6000
0 10 20 30 40
0
5000
10000
Time (s)
0 10 20 30 40
-20
0
20

Input
0 10 20 30 40
0
2
4
x 10
4

40Hz component BG
0 10 20 30 40
0
2000
4000
6000

100Hz component BG
0 10 20 30 40
0
200
400
600
Time (s)

Event Sum

44

3.3.2 Noisy data and background-update-rate test in sub-vt system
The following are the identical experiments but with the sub-vt system. The
maximum input amplitude is 3 mV and the noise signal has an amplitude of 0.7 mV, a
fourth of the maximum input signal, the same proportion as in the digital system case.
In Figure 3.22 we see fewer events detected for the 40 Hz noisy data, a response
similar to the digital system. Should there be a constant noise source at the band pass
center frequencies of the system, in this case 40 Hz and 100 Hz, the center frequencies
should be moved to avoid the noise sources. The other noisy data don’t show much

Figure 3.22: Noisy footstep data (footstep along with 40 Hz, 60 Hz, 100 Hz, and 120 Hz noise from
left to right) supplied to sub-vt system. 40 Hz and 100 Hz spectral components are shown along with
events.
0 2 4
-2
0
2
4
mV
0 2 4
0.31
0.32
0.33
0.34
0.35
V
0 2 4
0.31
0.32
0.33
0.34
0.35
V
0 2 4
0
0.5
1
1.5
Time (s)
V
0 2 4
-2
0
2
4
mV
0 2 4
0.31
0.32
0.33
0.34
0.35
V
0 2 4
0.31
0.32
0.33
0.34
0.35
V
0 2 4
0
0.5
1
1.5
Time (s)
V
0 2 4
-2
0
2
4
mV
0 2 4
0.31
0.32
0.33
0.34
0.35
V
0 2 4
0.32
0.34
0.36
V
0 2 4
0
0.5
1
1.5
Time (s)
V
0 2 4
-2
0
2
4
mV

Input
0 2 4
0.31
0.32
0.33
0.34
0.35
V

40Hz component BG
0 2 4
0.31
0.32
0.33
0.34
0.35
V

100Hz component BG
0 2 4
0
0.5
1
1.5
Time (s)
V

Event

45

effect on the events. A crucial 60 Hz frequency has been eliminated and doesn’t affect
the system. The background noise canceling system helps in this case, because if the
40 Hz filter Q is not too high and some 60 Hz frequencies pass through the system, it will
be canceled.
A seven second segment has been placed back to back to test the different background
update rates in the sub-vt system. Figure 3.23 shows the system’s response with a 50 ms
update and 12.5 s update. Both the systems with the 50 ms and 12.5 s background update
rates catch all events for each 7 s segment. This is because the background for both cases
is below the instantaneous 40 Hz and 100 Hz components. The difference with the sub-vt

Figure 3.23: Different background update rate in subthreshold system, 50 ms update (left) 12.5 s
update (right). No noticeable difference.
0 5 10 15 20
-2
0
2
4
mV
0 5 10 15 20
0.31
0.32
0.33
0.34
0.35
V
0 5 10 15 20
0.31
0.32
0.33
0.34
0.35
V
0 5 10 15 20
0
0.5
1
1.5
Time (s)
V
0 5 10 15 20
-2
0
2
4
mV

Input
0 5 10 15 20
0.31
0.32
0.33
0.34
0.35
V

40Hz component
BG
0 5 10 15 20
0.31
0.32
0.33
0.34
0.35
V

100Hz component
BG
0 5 10 15 20
0
0.5
1
1.5
Time (s)
V

Event

46

and digital system is that the digital system obtains power at the BPFs, but in the sub-vt
system only a peak amplitude voltage is taken from the BPF. As a result the band pass
background amplitude is smaller than its power counterpart in the digital system and thus
the system is able to catch all events.
3.3.3 Dynamic power
Figure 3.24 shows the footstep data, with events, along with the dynamic analog and
digital power. The digital power consumption only spikes when there is an event and on
average only consumes 25 pW, whereas the average analog power consumption is almost
the same as the static analog power consumption (i.e. when there is no event), and that is
30 nW.

Figure 3.24: Dynamic power of sub-vt system. Average analog power is 30 nW.
0 0.5 1 1.5 2
-10
-6
-2
2
6
10
Voltage(mV)

0
0.4
0.8
1.2
1.6
Voltage(V)
Input
Event
0 0.5 1 1.5 2
20
30
40
Power(nW)
Pavg:30.3754nW

Analog power
0 0.5 1 1.5 2
0
200
400
Time (s)
Power(nW)
Pavg:0.025379nW

Digital power

47

Chapter 4
Hardware and Chip Results
In this chapter, the chip layout along with the hardware required to test the chip are
introduced. The entire chip simulation results including simulations of the various blocks
in the chip are also discussed.
4.1 Chip layout and hardware

The complete layout of the event detector chip is shown in Figure 4.1a. The chip
consists of all components as in the system diagram in Figure 3.2. The system also
consists of test circuits like buffers and switches. The switches help partition the chip
and test individual blocks at a time and the buffers are needed to drive the measuring test
equipment. Some of the components we see in the figure are the 40 Hz and 100 Hz

a) b)
Figure 4.1: a) Chip layout. b) Chip micrograph.
Divider
40 Hz BPF
100 Hz BPF
ED
Bias
Buffers
1 mm
1 mm
Contr.

48

BPFs; the Bias block is for the current sources; ED is the envelope detector; the divider
along with the adder, comparator and level converter; Contr. is the digital control (like
switches, etc.); and Buffers are the output buffers.
The area of the chip is 1 mm by 1 mm and is fabricated by Cypress Semiconductor in
a 150 nm process. Due to the low frequency of operation the capacitors related to the
filters are large and is apparent in the figure. The density of the capacitance isn’t as
large, as the only capacitors available were metal-metal capacitors. The analog circuits
compared with the capacitors occupy very little area. Figure 4.1b shows the unpackaged
die micrograph. There are no visible features on the micrograph, since top layer metal
has been placed at the top of the chip to pass Design Rule Check (DRC) for metal density
on chip. The bare die was wire bonded and packaged in QFN (quad-flat-no-leads)
package.

Figure 4.2: Test PCB for event detector chip.
68 QFN socket
Power supply
DAC boards: Bias voltage
μController: test control
LPF and switches

49

The event detector test board is shown in Figure 4.2. The packaged die is placed in a
68 QFN socket. The socket is easier to solder onto the board and protects the chip from
damage. The socket is soldered onto a daughter board that sits on the mother board. This
again makes the system modular and reusable on different test boards.
Powering of the chip is done by the power supply unit; there is a digital and analog
ground to reduce noise to the chip. The microcontroller is used to program the DAC
boards, which provide bias voltages for the various current sources on the chip. The
microcontroller is controlled by a PC serially. There are also potentiometers to control
bias voltages on the chip. The green box on the figure marking LPF and switches is for
the background noise averaging. Due to the large time constant required for averaging,
large resistance and capacitance values are required and thus placed off chip. The
switches here are control signals sent and received from the event detector chip and the
classifier microcontroller, which in this case is the same microcontroller in the figure.
The microcontroller is programmed for controlling bias voltages as well as carrying out
the classifying of the event.
Figure 4.3 and Figure 4.4 show the PCB schematics. Figure 4.3 shows the control
segments required for testing along with a power unit. The power unit supplies the
different power supplies required for different parts of the PCB including power supplies
for the chip. The master control unit consists of the Jennic microcontroller. One of its
functions is to program the slave-DACs, which set bias voltages for the chip. Figure 4.4
shows the event detector chip. The DUT (device under test) is on the top left corner.
There are other components for test and control of the chip as well.

Figure 4.3: Test PCB schematic: Control

50
t PCB schematic: Control.

Figure 4.4: Test PCB schematic: DUT

51
PCB schematic: DUT.

52

4.2 Chip simulations
Following are the simulations of important blocks in the chip. The blocks tested are:
current sources, buffers, the band pass filters and the envelope detector. The functions
tested are: background noise cancellation, level conversion and finally the event
detection.
4.2.1 Current sources
The key structure for the bias current is a cascode as in Figure 4.5a. A cascode is used
for large output resistance, making I
vref
less sensitive to the drain voltage of the cascode
transistor. The bias voltage for the cascode transistor is generated by the circuit in Figure
4.5b, which is two diode connected transistors in series. V
cas
is supplied from the DAC
and the current I
vcas
is measured through a pico-ammeter. Figure 4.5c, is a low voltage
bias circuit, again V
ref
is set by the DAC and I is measurable. Small changes in V
ref
has
large impact on I
vref
in Figure 4.5a.

The I–V graphs for Figure 4.5b are shown in Figure 4.6. Results from various chips
have been plotted along with a plot from Cadence simulations. The voltage is ramped up
all the way to the chip supply voltage, which is 1.8 V; showing the entire transistor
operating regions, from cut off to subthreshold to the above threshold saturation and
linear regions. The subthreshold region has been zoomed into. Since the I–V relationship
for subthreshold is exponential, there should be a linear relationship with the log of the

a) b) c)
Figure 4.5: a) Cascode source, b) diode connected transistors, c) low voltage bias circuit.
M
3
I
vcas
M
4
V
cas
+
-
V
cas
M
5
I
vref
V
ref
+
-
V
cas
M
6

53

current and applied voltage. This linearity is seen in the zoomed-in graph. We can see
an offset in the current readings compared to the Cadence plot, but nonetheless, by
changing the voltage bias we can move up and down the graph to obtain the current
required. The applied voltage can be changed in steps depending on the resolution of the
DAC and in this case is of the order of 100 µV.

There are eight V
refs
to set for the filters, divider, rectifier, buffers, etc. With different
V
cas
, the chips can produce graphs matching Cadence simulations as can be seen in Figure
4.7a. The figure shows the I–V graphs of Figure 4.5a, and in particular the I
vref
for the
first stage of the 40 Hz BPF. By varying V
ref
we see the response produced by the
corresponding I
vref
in Figure 4.7a similar to Figure 4.6. Figure 4.7a shows that responses
matching Cadence simulations can be attained by changing V
cas
of the cascode transistor
in Figure 4.5a.
Figure 4.7b shows all the eight I–V graphs for chip 6. The lower end of the graph is
important for subthreshold applications. V
ref
~ 200 mV–300 mV required and small
changes in this voltage leads to exponential changes in currents and can change operating
points of the circuits.

Figure 4.6: I–V graphs, chips and Cadence. Zoom-in shows subthreshold region.
0 0.5 1 1.5 2
0
0.5
1
1.5
2
Voltage(V)
Current(uA)

Cadence
Chip2
Chip6
Chip13
0.6 0.8
10
-4
10
-2
Voltage(V)
Current(uA)
Zoomed-in

54

4.2.2 Buffer
The buffer as described in section 3.2.5 is used to buffer the test points to the
measuring equipment as well as in between stages as in the filter. The frequency response
of the buffer is shown in Figure 4.8a. The bump in the response is due to the zero
introduced from the miller capacitance and series resistance. The 3 dB bandwidth is at
710 Hz. There is a drop in the gain with increasing input amplitude. This is due to

Figure 4.8: a) Frequency response of buffer.
10
1
10
2
10
3
10
4
-10
-8
-6
-4
-2
0
2
4
Frequency(Hz)
Gain(dB)

a) b)
Figure 4.7: a) I–V graph of cascode current source for different V
cas
voltages, showing comparison between
chip 6 and simulation. b) Chip 6 I–V graphs with constant V
cas
and varying V
ref
.
0 0.5 1 1.5 2
0
10
20
30
40
50
Voltage(V)
Current(nA)

v
cas
=0.5329(chip)
v
cas
=0.45(chip)
v
cas
=0.475(chip)
v
cas
=0.53(sim.)
v
cas
=0.5735(sim.)
v
cas
=0.617(sim.)
0 0.5 1 1.5 2
0
10
20
30
40
50
Voltage(V)
Current(nA)
0.3 0.4 0.5
10
-2
10
0
Voltage(V)
Current(nA)
Zoomed-in

55

distortion for higher input amplitudes, above 74 mV the buffer doesn’t function correctly
as it is pushed out of the subthreshold region at that point.
4.2.3 Band pass filters
The response of different sections of the 40 Hz BPF is shown in Figure 4.9a and the
specifications are in Table 4.1. The figure shows the response of stage one, S
1
, and stage
two, S
2
. S
1
and S
2
are designed with different gains and Qs. S
2
–S
4
is the cascade of the
last three stages and S
1
–S
4
is the cascade of all four stages. S
2
–S
4
are controlled by one
V
ref
current source. And thus mismatches in mirroring the currents leads to offsets in
center frequency peaks of each of the stages, resulting in drop in gain and Q when
cascaded. Also in the Figure 3.7 I
dc1
and I
dc2
are also only controlled by one current
source and could be another source for loss in gain. To increase control of various
parameters of each of the stage of the filter, more current sources would be require and
more manual programming would be required.
Similar response is seen for the 100 Hz filter in Figure 4.9b and the specifications are
shown in Table 4.2. The gain is better here than the 40 Hz counterpart. Although overall
gain maybe low in the 40 Hz BPF, gain can be increased at the OTA stage of the
envelope detector, or at the divider stage.

b) b)
Figure 4.9: Reponses of different sections of a) 40 Hz BPF, b) 100 Hz BPF.
20 30 40 50 60 70 80
-20
-15
-10
-5
0
5
10
15
20
Frequency(Hz)
Gain(dB)

S1
S2
S2-S4
S1-S4
10
2
-15
-10
-5
0
5
10
15
20
25
Frequency(Hz)
Gain(dB)

S1
S2
S2-S4
S1-S4

56

4.2.4 Envelope detector
The envelope detector consists of three stages: the OTA, full wave rectifier and peak
detector. The full wave rectification can be seen in Figure 4.10. A 1 mV 40 Hz sine
wave input is applied and is shown in the top graph. The reason the wave is noisy is
because it is pulled off after a LPF and interaction with other input circuits, like biasing
components on the PCB. The 40 Hz BPF output is also shown. It can be seen that the
noisy signal is cleaned up after the filtering, proving the functionality of the filter. The
output of the rectifier is pulled from the output of the peak detector, by setting a fast rise
and fall time, and thus the peak detector acts like a unity gain amplifier. The rectified
output shows a mismatch in the amplitudes of the different phases and this can be
adjusted by changing the bias voltage at the OTA.
Table 4.2: 100 Hz BPF specifications.
BPF Gain (V/V) BW (Hz)
S
1
15.15 27
S
2
1.03 35
S
2
–S
4
0.526 29
S
1
–S
4
7.4 21

Table 4.1: 40 Hz BPF specifications.
BPF Gain (V/V) BW (Hz)
S
1
6.65 16
S
2
1.14 13
S
2
–S
4
0.39 13
S
1
–S
4
3 8

57

Figure 4.10 (bottom) shows the output of the peak detector. Here the rise time is fast
whereas the fall time is slow for the peak detection. The response is like a triangular
wave and the slow fall time can be changed to make it even slower to get a steady DC
voltage. It can be seen that for the two different phases there is again a different peak,
again this is due to the bias voltage set at the OTA.
4.2.5 Background cancellation and level converter
The divider circuit in Figure 3.17 is used to divide out the background signal from the
instantaneous signal. The divider output also includes the multiplication factor as in
Gain
1
and Gain
2
. Since the averaging window for the background value is large, a
resistance of 500 MΩ and a capacitance of 25 nF are used for a 12.5 s time constant.
These components are very large and must be off chip. When an event is detected the
voltage is to be stored on the capacitor and the switching/control circuitry is also off chip
as the passive components. If the resistor can be placed on chip then the control switches
can also be on chip only leaving a large capacitor off chip. The purpose of the

Figure 4.10: Full wave rectification (top) for 1 mV 40 Hz sine wave. Peak detector response (bottom).
0 0.1 0.2 0.3 0.4 0.5
0
0.1
0.2
0.3
0.4
0.5
0.6
Voltage (V)

-10
10
30
50
70
90
Voltage (mV)
Rectifier
BPF
Input
0 0.1 0.2 0.3 0.4 0.5
0.2
0.3
0.4
0.5
0.6
0.7
Voltage (V)
Time (s)

BPF
Peak

58

background noise cancellation is to remove constant noise sources from the environment
such as generators and motors in the area.
Figure 4.11 shows the background noise cancellation. The input is multiplied by
seven for graphing purposes. The input is a 1 mV sine wave which is then stepped up to
an amplitude of 3 mV. The blue curve is the peak of the rectified output. We can see the
peak have a higher DC value for the 3 mV signal. The purpose of this experiment is to
show that only the instantaneous input step is caught and then after a while it is
considered a non-event and considered as background noise. The bottom graph is the
current output from the divider that does the background cancellation. The output current
going high is indicative of an event. The onset of the step in voltage causes an increase
in the output current from the divider. After a while this output current falls down back
to its original value, showing that the constant high input voltage is a background
constant noise and not an instantaneous event. This mechanism helps cancel out false
positives and makes the event detector sturdy to different types of environmental noise
sources.

Figure 4.11: Background noise cancellation.
0 5 10 15 20 25
-0.1
0
0.1
0.2
0.3
0.4
Voltage (V)

Input(x7)
Peak voltage
0 5 10 15 20 25
0.2
0.3
0.4
0.5
0.6
0.7
Time (s)
Current (nA)

BG cancelled current

59

The level converter is the output stage that outputs a digital level signal that is a high
and a low signal. The output from the comparator goes to two inverters, acting as buffers
to boost the signal and this output goes to the two inputs of the level converter.

Figure 4.12 shows this response. The input voltage to the first inverter is varied from
ground to supply voltage and the output. The final output is the green response of the
level converter. The output goes from 0 V to about 1.2 V which is sufficient to trigger on
the next output stage and turning on and off of switches.
4.2.6 Event detection
The experiment conducted here is similar to that in Figure 4.11, here the event from
the level converter, is also shown. At the onset of the increase in the input an event is
triggered. As long as the BG cancelled current (as in Figure 4.11) is high an event is
triggered and that is why a long pulse is seen at the event. Once the BG cancelled current
goes down the event pulse goes to 0 V. Some spurious events are detected at the rising
and falling edges of the event pulse. The reason for this is due to the high gain at the
comparator and level converter stages. So in Figure 4.12, if the input voltage wiggles at
that rising edge, the output can either go high or low and that’s why spurious events are
noticed. These events can be cleaned up by using a low pass filter at this output.

Figure 4.12: Level converter output.
0 0.5 1 1.5 2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Voltage (V)
Voltage(V)

Inverter
1
Inverter
2
Level converter

60

The final experiment is show in Figure 4.14 depicting the event detector’s response to
footstep signals. The same sampled footstep data used for the Cadence simulations is
supplied to the chip through a Data Acquisition (DAQ) card. The top graph is the input
data, the bottom graph shows the envelope of the filtered signal and the pink waveform
shows the events detected. The first three events are detected but not the next three. The
event in the middle is also detected. A comparison with the digital system as well as the
Cadence simulated system will be shown in the next chapter. The reason for missing the
three events is due to low gain from the BPFs as a result of unmatched center
frequencies. These events can also be missed because of the inherent dead-zone of the
rectifier. The latter issue can be prevented by improving the gain of the filters or by
adding an extra gain stage at the input of the system.

Figure 4.13: Event detection for step increase in input amplitude.
0 2 4 6 8 10 12
0
0.1
0.2
0.3
0.4
0.5
0.6
Voltage (V)

-20
0
20
40
60
80
Voltage (mV)
BPF
Input
0 2 4 6 8 10 12
-0.5
0
0.5
1
1.5
2
Voltage (V)
Time (s)

Event
Rectifier

61

Figure 4.14: Event detection for footstep data.
26 26.5 27 27.5 28 28.5 29
-10
-5
0
5
10
Voltage (mV)

Input
26 26.5 27 27.5 28 28.5 29
-50
0
50
100
150
200
250
300
350
Voltage (mV)
Time (s)

-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Voltage (V)
Rectifier
Event

62

Chapter 5
Event Detector Conclusion
An ultra-low-power event detector has been designed for long-term persistent sensor-
based surveillance systems. An analog front-end event detector operating in subthreshold
region of CMOS transistors consuming 38 nW of power has been designed, enhancing
the longevity of the sensor. The fabricated chip ensures feasibility of the design and the
realistic power savings achievable. A comparison of the footstep data processed by the
digital system (PIC microcontroller), Cadence simulations (subthreshold analog design)
and the subthreshold event detector chip are shown in 5.1. The top graph is the digital
system response showing the input along with the discrete events. An event is triggered
when the input crosses a threshold. The middle graph represents the response of the

5.1: Response to foot step data: Digital version (top), cadence simulation (middle), chip simulation
(bottom).
0 1 2 3 4
-15
25
65
105
145
Value

0
1
2
Value
Input
Event
0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75
-3
2
7
12
17
22
Voltage (mV)
0
0.4
0.8
1.2
1.6
Voltage (V)
25.75 26.25 26.75 27.25 27.75 28.25 28.75 29.25
-9
6
21
36
51
66
Voltage (mV)
Time (s)
0
0.4
0.8
1.2
1.6
Voltage (V)

63

Cadence simulation of the subthreshold analog system. It can be seen that the same
events are detected by this system. The bottom graph is the chip simulation. In this
graph we see that the first three events are detected by the system, but not the next three.
This can be as a result of low gain in the system as a result of loss in gain at the BPF
stages and also because of the dead-zone inherent in the full wave rectifier. The other
reason for not catching the last three events could be due to the fact that the footstep
signal is comparable with the noise floor and thus not differentiable from noise.
A complete list of power consumption by various parts of the circuit is shown for the
chip in Table 5.1. it can be seen that most of the power consumption goes into the
comparator and the buffers. The comparator needs this extra power to increase the gain

Table 5.1: Power metric for event detector chip.
Component Stage Power (nW)
40Hz filter S
1
0.115
S
1
–S
4
0.396
100Hz filter S
1
0.18
S
1
–S
4
0.432
Envelop Detector
(40 and 100Hz)
OTA 2.059
Rectifier 0.162
Peak detector 0.144
Divider

Input currents 0.432
Gain factor 0.72
Output 0.54
Comparator 11.88
Buffers In between filters 2.138
Envelope to divider 1.425
Additional for above (due to LPF) 18
Total 38.6

64

of the signal received from the system for the comparison to be possible. The buffers are
fine except for the unforeseen power consumption for the buffer driving the LPF. The
LPF for the long averaging time window, which was assumed to be 12.5 s, for testing
purposes was replaced by a shorter averaging window of 11 ms. It was observed that on
the falling edge of the input, the voltage at the output wouldn’t follow as the output
transistor would turn off and this was as a result of the low output drive current. For this
an external load resistor had to be added and then the transistor was biased at a point able
to supply this drive current. This buffer can be redesigned to accommodate for the LPF
and reduce power or even changing the LPF design is possibility to reduce power.
5.1 Improvements/impact
Comparing to the digital system in terms of power; the digital system consumed
6.3 mW and the subthreshold analog system consumes about 40 nW, delivering about a
160,000 times power reduction. In terms of performance, from the previous figure we
seen that a few events were lost, and this is due to loss in gain in some of the stages.
These issues can be fixed. Overall, with the power savings in mind, this is a huge
improvement and thus can add to battery life, or the tremendous improvement in power
consumption implies capability to add 160,000 times signal processing capability at the
front-end of these security sensors.
The noise cancelling mechanism help improve the systems SNR, it also rejects false
positives received from generators, motors or any other constant noise sources. The two
filters help clean up the incoming signal as well as help to do a pre-classification. From
previous statistical data, the 40 Hz and 100 Hz bands provide important information for
footstep and vehicular signals. All the above benefits along with the operation of the
entire front-end event detector for seismic sensors in subthreshold domain provide
insights into the tremendous power saving achievable.

65

5.2 Issues
One of the main concerns of the chip is that in operating in subthreshold region,
current sources need to be stabilized. Better PVT independent current sources need to be
designed. The currents were stable while testing, but variations were observed with
temperature changes. All the current sources were controlled using a DAC, giving the
necessary control. But for future versions of the chip, better current sources are required
that are PVT independent.
Even if current sources are sturdy, matching these current sources throughout various
parts of the chip can lead to mismatches and thus different operation for different circuit
components. This was seen in the BPFs, where the center frequencies among stages
differed, thus losing gain and quality factor in the filters. Different techniques will be
proposed in the next chapter to circumvent these effects.
Loss in gain due to matching of the filter stages leads to increased dead-zone in the
rectifier and some of the events as seen in the figure are not captured by the system,
increasing the gain though out the system is possible at the OTA of the envelope detector,
but having another gain stage at the input of the system could be used should an instance
like this occurs.
5.3 Parameter dependence
Transistor I–V curves vary depending on process, voltage, temperature or PVT. As
discussed in chapter 2.2, effects of temperature and mismatches results on changes in V
T0
,
κ, µ and β. These changes can be incorporated as small changes to the parameters and
thus Monte Carlo simulations are done. The Monte Carlo plot for the diode connected
current source shown in Figure 4.5b with its I–V curves shown in Figure 4.6 is shown in
Figure 5.2a. It can be seen that Monte Carlo standard deviations about the Cadence plot

66

does not encompass chip data. This is because the Cadence simulation is only a typical-
typical, TT, simulation.
A complete corner analysis is shown in Figure 5.2b. S and F stand for slow and fast n-
type or p-type transistors and it can be seen that the chip data is more towards the SF and
FF curves, suggesting that the n-type transistors in the diode connected current source
have fast characteristics. Since the chip data falls between the model predictions, the
model is dependable.

Monte Carlo simulations for the various current sources for the 4 stage BPF is shown
in Figure 5.3 and Table 5.2. Although the overall center frequency for the 40 Hz BPF
doesn’t have a large standard deviation, the overall gain can drastically decrease, with a
standard deviation of about 7 V/V.
Loss in gain due to matching of the filter stages leads to increased dead-zone in the
rectifier and some of the events are not captured by the system. Increasing the gain
throughout the system is possible at the OTA of the envelope detector, or another gain
stage can be added at the input as well. Table 5.3 shows the number of events detected
with different variations in current sources of the different BPF stages. Multiple I
vrefs

a) b)
Figure 5.2: a) Monte Carlo simulation for diode connected current source. b) Corner simulations for
diode connected current source.
0.5 0.6 0.7 0.8
10
-2
10
-1
10
0
10
1
Voltage(V)
Current(nA)

Cadence with MC
Chip2
Chip6
Chip13
0 0.5 1 1.5 2
0
0.5
1
1.5
2
2.5
3
Voltage(V)
Current(uA)

Chip2
Chip6
Chip13
TT
SS
FF
0.6 0.8
10
-4
10
-2
Voltage(V)
Current(uA)
Zoomed-in

67

supply the I
dc1
and I
dc2
biases of the filters. It can be seen that if the gain goes below 15.4
all the events aren’t detected.

Figure 5.3: Monte Carlo simulations for different current sources of 40Hz BPF along with
distributions for center frequency and gain of the BPF.
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF1 Idc1
mu = -30.4706p
sd = 3.34431p
N = 100
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF1 Idc2
mu = -30.2226p
sd = 3.4439p
N = 100
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF2 Idc1
mu = -30.5717p
sd = 3.17378p
N = 100
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF2 Idc2
mu = -29.7847p
sd = 2.78516p
N = 100
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF3 Idc1
mu = -30.2323p
sd = 3.47548p
N = 100
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF3 Idc2
mu = -30.7218p
sd = 3.13852p
N = 100
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF4 Idc1
mu = -30.2577p
sd = 3.09612p
N = 100
-40 -35 -30 -25 -20
0
5
10
Current (pA)
Number
BPF4 Idc2
mu = -29.9211p
sd = 3.23608p
N = 100
36 38 40 42 44 46 48 50
0
50
Frequency (Hz)
Number
Center frequency
mu = 42.7847
sd = 3.05028
N = 100
0 5 10 15 20 25 30 35 40
0
10
Magnitude (V/V)
Number
Gain
mu = 14.8512
sd = 6.84686
N = 100

68

Table 5.3: Events detected with variations in current sources.
Trial BPF stage V
ref
(mV) I
vref
(pA)
% I
vref

variation
Gain Events detected out of 6
1
S
1
287.9 30.6 +2
8.9 3
S
2
289 31.51 +5
S
3
285 28.13 -6
S
4
300 40.97 +36
2
S
1
284 27.7 -7
6.5 3
S
2
289 31.51 +5
S
3
285 28.13 -6
S
4
300 40.97 +36
3
S
1
284 27.7 -7
15.4 6
S
2
290 31.89 +6
S
3
290 31.89 +6
S
4
290 31.89 +6
4
S
1
282 26.43 -12
8.6 3
S
2
294 35.26 +17
S
3
294 35.26 +17
S
4
294 35.26 +17
5
S
1
282 26 +13
4.4 3
S
2
294 35 +16
S
3
282 26 -13
S
4
294 35 +16

Table 5.2: Variations in current sources. N = 100
Current source Average St. dev.
S
1
I
dc1
30.4706 pA 3.34431 pA
S
1
I
dc2
30.2226 pA 3.4439 pA
S
2
I
dc1
30.5717 pA 3.17378 pA
S
2
I
dc2
29.7847 pA 2.78516 pA
S
3
I
dc1
30.2323 pA 3.47548 pA
S
3
I
dc2
30.7218 pA 3.13852 pA
S
4
I
dc1
30.2577 pA 3.09612 pA
S
4
I
dc2
29.9211 pA 3.23608 pA
Overall center frequency 42.7847 Hz 3.05028 Hz
Overall gain 14.8512 V/V 6.84686 V/V

69

Chapter 6
Mismatch-, PVT- and False-Positive-
Insensitive Design
From the conclusions of the chip, there was a loss in gain in the system. Implying
mismatches in current sources for the cascaded band pass filters. From Figure 5.3,
differences in current sources lead to loss in gain in the BPF. Therefore the goal now is
to make the chip sturdy with respect to process, voltage and temperature (PVT). The
forthcoming sections will discuss the effects of mismatch and temperature and will show
methods on how to solve these issues.
6.1 Mismatch
The equations in Chapter 2 show that, in subthreshold region, current mismatch is
higher and to reduce the mismatch the area of the transistor is to be increased. The
following will show comparisons with small and large current sources in the system,
depicting mismatches and overall system performance.
The first set of simulations show mismatches in threshold voltage and current in two
similarly biased transistors. Two transistors are biased with a gate-source voltage of
375 mV to maintain subthreshold operation and the drain-source voltage is tied to the
supply for forward saturation region. Figure 6.1a and Figure 6.1b show mismatches in
the two transistors, for a smaller transistor with W/L = 0.42 μm/2 μm, and a larger
transistor with W/L = 4.2 μm/20 μm, respectively.

70

From the equations we saw H∆

∝

√PQ
. Since the larger transistor is 100 times
larger in area than the smaller transistor, we should see a factor of 10 smaller H∆

in
the larger transistor. The larger transistor will also see a factor of 10 improvement in
H∆', since
”∆•
•
= H∆

κ
1
2
in the subthreshold region. Figure 6.1a and Figure 6.1b
corroborate the reduction in mismatch in the larger transistor by a factor of 10.

Figure 6.2: Relative current mismatch vs. temperature for small and large transistors.
0 50 100 150
0
5
10
15
20
25
30
35
40
Temperature (°C)
σ(ΔI
d
)/I
d
(%)

W/L=0.42μ/2μ
W/L=4.2μ/20μ

a) b)
Figure 6.1: a) Mismatches: ΔV
T0
(top) and ΔI (bottom) for transistors with a) W/L = 0.42 μm/2 μm, b)
W/L = 4.2 μm/20 μm.
-20 -10 0 10 20
0
10
20
Voltage (mV)
Number
mu = 101.334uV
sd = 5.11384mV
N = 100
-2 -1 0 1
0
5
10
15
Current (nA)
Number
mu = -113.525pA
sd = 429.889pA
N = 100
-20 -10 0 10 20
0
10
20
Voltage (mV)
Number
mu = -8.05164uV
sd = 496.344uV
N = 100
-2 -1 0 1
0
5
10
15
Current (nA)
Number
mu = 11.0387pA
sd = 43.2686pA
N = 100

71

Figure 6.2 shows the relative current mismatch, for the same small and large transistor
set, with respect to temperature. Although the mismatch reduces for higher temperature
(the mismatch is inversely proportional to temperature) for the small transistor set, the
mismatch is still large (more than 25%). On the other hand, the larger transistor set has
almost constant mismatch over temperature and this mismatch is low (less than 5%).
Figure 6.1a, Figure 6.1b and Figure 6.2 show that larger transistors are better, having
less mismatch. Although mismatch is low for large transistors over temperature, the
absolute value of the current changes with temperature. Thus temperature variations will
still need to be reduced.
The next set of simulations is based on the mismatches present in the band pass filter
and its current sources as in Chapter 3. The areas of the transistors are changed to
compare the filter’s response for small and large transistors used in the current sources.
The transistors with the original sizes in the current mirrors show mismatches in center
frequency, f
c
, and gain of the four stage band pass filter as in Figure 6.3a. Figure 6.3b
shows the same simulation, but with the current mirrors sized 100 times larger than the
original.

a) b)
Figure 6.3: Mismatches: Center frequency (top) and gain (bottom) of BPF with current mirrors with
a) original transistor sizes b) 100 times original transistor sizes.
35 40 45 50 55
0
5
10
15
Center frequency (Hz)
Number
mu = 43.0859Hz
sd = 2.71049Hz
N = 100
0 20 40 60
0
10
20
Gain (V/V)
Number
mu = 16.6869
sd = 8.2014
N = 100
35 40 45 50 55
0
10
20
30
Center frequency (Hz)
Number
mu = 41.5831Hz
sd = 232.576mHz
N = 100
0 20 40 60
0
10
20
Gain (V/V)
Number
mu = 37.9488
sd = 1.25246
N = 100

72

In Figure 6.3a, the relative center frequency mismatch is 6% and the relative gain
mismatch is 51%, whereas in Figure 6.3b we have a 0.5% and 3% relative center
frequency and gain mismatch respectively. There is a large reduction in mismatch by
increasing the sizes of the current source transistors.
6.2 Temperature
The effect of temperature on the chip will be discussed in this section. The equations
for drain current and transconductance will be discussed in the forthcoming sections.
Figure 6.4 shows the current and g
m
variation with temperature for a transistor that has a
fixed gate-source voltage maintaining subthreshold operation. We can see a large change
in the transconductance with temperature.

Figure 6.5 shows the four stage band pass filter with large current sources to minimize
mismatch. The filter was simulated for different temperatures, from -40 °C to 125 °C.
The maximum gain of 92.36 V/V is at the lowest frequency of 1.6 Hz at -40 °C and the
gain drops for the highest temperature of 125 °C to 79.87 V/V at a center frequency of
523.6 Hz. This graph shows that due to the large change in the subthreshold g
m
with
temperature the center frequency of the filter varies over orders of magnitude.

Figure 6.4: Current and g
m
vs. T for transistor in sub-vt with fixed gate-source voltage.
0 50 100
0
0.1
0.2
Current (nA)
Temperature (°C)
0
1
2
Transconductance (100nS)

73

Therefore from the mismatch and temperature sections, we saw that mismatch can be
reduced simply by increasing transistor area, but temperature changes causes a wide
range of center frequencies in the band pass filter. As a result of subthreshold operation,
the current and transconductance changes a lot with temperature, thereby affecting the
center frequency. To combat this effect we need to design a constant transconductance
circuit to maintain a fixed center frequency for the band pass filter. The next sections
will discuss past methods for constant transconductance circuits as well as the new
proposed method.
6.3 PVT-insensitive subthreshold g
m
: Past solutions and
drawbacks
Several methods to build constant transconductance biases have been designed in the
past. The most common being the beta-multiplier circuit shown in Figure 6.6 [39] or a
similar version as in [40]. In Figure 6.6 X is a linear element, a resistor R
offchip
in this
case. Both circuits try to match a transconductance to precise external resistors. For the
above threshold region, g
m
= 1/R
offchip
. In the subthreshold region, M
2
and M
1
produce a

Figure 6.5: Frequency response of the four stage BPF at different temperatures.
10
0
10
1
10
2
10
3
0
20
40
60
80
100
Frequency (Hz)
Gain (V/V)

-40°C
-7°C
26°C
59°C
92°C
125°C

74

PTAT voltage at V
ref
in the figure, and a resistor converts this voltage into a PTAT
current that sustains a constant transconductance in the subthreshold region.
The issue in subthreshold region is the resistance required for pico-amp operation
would be very large and not feasible. Another issue is that the transconductance varies
with the supply. This is due to channel length modulation and since the drain voltages of
M
1
and M
2
differ leading to different currents. Also in either subthreshold or above
threshold, the use of an external component adds to the cost and complexity of the
design, as stability is degraded with a large parasitic capacitor at the pad associated with
the off-chip resistor.
To overcome the issues with external resistors, there are several techniques that use
master/slave tuning to obtain a constant g
m
. The slave transistor is supplied a voltage,
such that its effective resistance matches a switched capacitor based resistance [46]. In
this case, the transistor is biased in triode region to emulate a resistance and consumes
higher power being in strong inversion region. Also the switched capacitor circuit
requires accurate clocks. All these issues add to the power and complexity of the circuit.

Figure 6.6: Beta-multiplier circuit for PTAT current.

75

Another method that does not use a resistor is mentioned in [50]. Here the on-chip
resistance is generated using a triode transistor. The emulated resistance does not use
switched capacitors, but uses constant voltage and current sources as well as opamps to
force a gate voltage on the triode transistor generating the required resistance across the
transistor. Although there are no clocks used to generate the resistance, clocks are used
to cancel offsets due to threshold voltage mismatch. Also for proper feedback
functioning, high gain is required by the opamps raising the current and power
consumption of the circuit.
The next 3 methods introduced use resistors and thus will have the same issues as the
beta multiplier in terms of having external components. They will still be introduced as
the references show different approaches to tackling the constant g
m
problem.
The first method is similar in both [47] and [48] except the former is in above
threshold and the latter in subthreshold. Both designs use the beta-multiplier circuit in
[40] to generate a constant transconductance. In addition to the beta-multiplier, there is a
feedback mechanism that forces the gate, drain and source voltages of the beta-multiplier
constant transconductance transistor and the transistor to be biased to be equal. This
mechanism ensures equal operating points of the beta-multiplier circuit and the circuit to
be biased, delivering a precise tracking of the external resistor.
The second method designed for above threshold uses proportional, constant and
complementary to temperature current sources to generate a current source that
compensates for temperature variations due to mobility in transistors [41], [49]. This
method would only work for above threshold biasing, but the idea of creating a constant
transconductance bias using a combination of different types of current sources can lead
to ideas of pre-processing currents to get a constant g
m
for subthreshold circuits.
The last method works for both subthreshold and above threshold devices [51]. This
is handy when the region of operation is unknown, or when short-channel transistors do
not obey a simple I–V relationship. This method uses the definition of G
m
, a large signal
transconductance, where G
m
≡ ΔI/ΔV. Using an opamp, a feedback mechanism and a

76

constant current source, the slope of the incremental change in current and voltage (G
m
) is
forced to equal a precise resistor.
To sum up, the issues with all the above methods are that they have precise external
resistors, accurate clocks or strong inversion transistors emulating on-chip resistors. The
goal of the constant transconductance to be designed will have no external components,
no resistors or switched capacitor circuits that require clocks and no strong inversion
transistors in order to keep the power low. Paramount to the above requirements is that
the constant transconductance bias will generate a g
m
for subthreshold operation thereby
greatly reducing the power for subthreshold systems.
6.4 PVT-insensitive subthreshold g
m
: Proposed design
As mentioned in the earlier section, previous methods applied a PTAT voltage to a
linear element, X, to create a PTAT current, as in Figure 6.6. The linear element could be
a resistor, a triode transistor or a switched capacitor emulating a resistance. From the
figure and with the transistors in subthreshold region we get the following PTAT voltage:

–D+
= =
4
ln(™ (6.1)
In the new design we try to eliminate the use of a resistor. In order to do so, let’s say
X is another function of V
ref
and not linearly related as a resistor. Let X = G(V
ref
), where
G( ) is an unknown function. We also create another function for V
ref
, such that,
V
ref
= F(T), where F( ) is an unknown function. Now we need to find G( ) and F( ) such
that the current through element X, I(T) = H(X) is a PTAT current. H( ) is to be found to
satisfy the condition.
6.4.1 Setting V
G
for PTAT current
The method we are proposing develops the required gate voltage across a transistor
such that it passes a PTAT current without the use of a resistor. We have chosen the

77

element X to be a transistor and V
ref
is applied to its gate. This gate voltage will be a
function of temperature. In order to find the required gate voltage, we need to set the
temperature coefficient of the transconductance of the transistor to zero.
Following is the I–V relationship for subthreshold transistors including a pre-
exponential term, I
S
, called the specific current [20].
' = '
Ž
exp œ
~
�
−

−
Ž
=
4
� (6.2)
where κ is the coupling coefficient, V
G
and V
S
, are the gate and source voltages. V
T0
is
the threshold voltage when V
S
= 0 V, and U
t
is the thermal voltage. And I
S
is:

'
Ž
=
2?@
A
_
,
0
b =
4
>
~

(6.3)
The transconductance, g
m
is:
B
C
=
8'
8
�
=
κ'
=
4
(6.4)
It can be seen that if I is proportional to temperature, g
m
will be independent of T as the
U
t
divides out the temperature dependent term from I.
We can find the temperature coefficient (T.C.) of g
m
and find V
G
, such that the
T.C. = 0. To find the T.C. of g
m
(T.C.
gm
), we’ll start by finding the T.C. of the
subthreshold current (T.C.
I
) first as follows:

F. @.
•
=
1
'
'
F

(6.5)
It should be noted that the temperature dependence of the mobility, µ, and of the
threshold voltage V
T
are as follows [20]:
?F = ?F

ž
F
F

Ÿ

C
(6.6)

=

− RF (6.7)

78

where µ(T0) and V
T0
are the mobility and threshold voltage at the reference temperature,
T
0
, m is the mobility temperature exponent and A is the threshold voltage T.C.
By plugging (6.3), (6.6) and (6.7) in (6.2) and using (6.5) we find the T.C.
I
to be

F. @.
•
=
1
?
?
F
+
1
=
4
>
=
4
F
+
1
exp~
�
−

−
Ž
/=
4

F
exp œ
~
�
−

−
Ž
=
4
�
=
2 − u
F
+

F
œ
~
�
−

−
Ž
=
4
�
(6.8)
Now T.C.
gm
using (6.4) is

F. @.
6C
=
1
B
C
B
C
F
=
~
B
C

1
=
4

'
F
+ '

F
ž
1
=
4
Ÿ¡
=
~
B
C
ž
1
=
4
' × F. @.
•
− '
1
=
4
F
Ÿ =
~'/=
4
B
C
žF. @.
•
−
1
F
Ÿ
= F. @.
•
−
1
F

(6.9)
For T.C.
gm
=0, we can plug (6.8) in (6.9) to get

1 − u
F
+

F
~
�
−

−
Ž
/=
4
= 0
(6.10)
We can now find the required V
G
and V
S
such that (6.10) is true. We can simplify the
equation by setting V
S
= 0, thus having only one parameter to adjust for a PTAT current,
namely V
G
. We shall also replace V
G
by V
G
(T) to incorporate its temperature dependence.
Simplifying the derivative term in (6.10), we get

79

œ=
4

F
~
�
F −

−
~
�
F −

=
4
F
�
1
=
4
>
=
~
=
4
œ

F

�
F + R −

�
F −

− RF
F
�
=
~
=
4
œ

F

�
F −

�
F −

F
�
(6.11)
Inserting (6.11) in (6.10) produces

1 − u +
~
=
4
F

F

�
F −
�
F −

¡
= F
�
F
¢ −
�
F + S = 0
(6.12)
where B is

+ 1 − u
1
2
£
.
We can now solve the differential equation for V
G
(T), leaving us with the general
solution as follows:

�
F =

+ u − 1
=
4
~
\F + @F
(6.13)
where C is a constant and it should be chosen such that the transistor remains in
subthreshold region. To ensure this condition we need V
G
(T) – V
T0
< 0. From (6.13) we
can find the constraint on C to maintain the subthreshold condition as follows:

RF + u − 1
=
4
~
\F + @F < 0
(6.14)
Therefore the constraint on C is:

@ <
1 − u
F
=
4
~
\F − R
(6.15)
A PTAT current can now be created by applying a temperature dependent gate voltage as
in (6.13) with the constraint in (6.15).

80

6.4.2 Circuit for V
G
and PTAT current
If we apply (6.13) in (6.2) we can find the current to be
'
Ž
F
C

exp ž
~
=
4
@FŸ (6.16)
Therefore, if we pass the current in (6.16) through a diode connected transistor as in M
1

in Figure 6.7, we will have developed a PTAT current through it. In Figure 6.7 is a
PTAT current generator. I
M1
= I
M3
as M
2
and M
1
form a mirror. I
PC
T is the PTAT current
mirrored from I
M1
, I
PC
is the PTAT - current Coefficient that is temperature independent.
The functional block, ( )
m-1

raises the current I
M3
by the exponent m-1. The
multiplication/division block multiplies the specific current, I
S
, along with multiplying
exp _
£
1
2
@Fb and dividing I
PC
m-1
, both being temperature independent terms. The end
result is (6.16) which is the PTAT current.
With the current mirror we have
'
„
= '
„l
(6.17)
And by passing I
M3
through the blocks, we get

Figure 6.7: PTAT current generator.

~
=
-
@F
'
1
= '
¤
F
u −1

~
=
-
@F

81

'
„l
= '
Ž
¥
'
„l
'
¦
exp §
~
=
4
@F
u − 1
¨©
C

(6.18)
I
M3
can now be solved from (6.18) and we get two solutions
'
„l
= 0 (6.19)
And

'
„l
= œ
'

C

'
Ž
�

C
>

(6.20)
where '

=
•
ª
«¬
®
¯
2
!
°±²
¡
is a constant current. Only the second solution is meaningful and
thus a start-up circuit would be required to avoid the zero current solution.
In order to prevent the use of a start-up circuit, we can only design a circuit that
creates the useful solution in (6.20). It can be seen that a constant current source, a
specific current generator along with the function ( )
(1/m-2)
and a divider are required to
create the PTAT current source.
The value of m in most technologies is around 1.5 due to the value of mobility from
acoustic phonon interaction [21] therefore (6.20) turns to

'
„l
= œ
'
Ž
'

.o
�
>

(6.21)
The solution for a PTAT current source, for m=1.5, requires a constant current and
specific current source along with a divider and squaring circuit. These blocks will be
discussed in the forthcoming sections.

82

6.4.3 Squaring circuit
In this section, the translinear principle is discussed. This principle is the basis of the
squaring circuit design and various topologies are proposed. The final squaring circuit is
shown along with its simulations.
6.4.3.1 Translinear principle
The translinear principle [42] can be used in CMOS subthreshold region to multiply
and divide currents, producing squares, square roots, or other desired functions, by
simply multiplying the same current the number of times as the power required. The gate
source voltages around the translinear loop (the dashed arrow) as shown in Figure 6.8 add
up to 0 V, by KVL. The PMOS transistors, whose emitters point in the clock-wise or
counter-clock-wise direction with respect to the translinear loop, are labeled CW and
CCW respectively. Applying KVL to the translinear loop, we get

�
)
= �
)
)∈P )∈P

(6.22)
And due to the exponential relationship of the drain current with respect to the gate
source voltage as in (6.2), we obtain a product of currents in the CW direction to equation
a product of the currents in the CCW direction, as follows:

’ '
)
)∈P
= ’ '
)
)∈P

(6.23)
The simple case in Figure 6.8 has only one transistor in the CW and CCW direction,
therefore we get
'
p4
¤

= '

¤
>
(6.24)
which is inherently a simple current mirror.

83

6.4.3.2 Stacked topology with uneven CW and CCW transistors
In order to obtain a square of a current, all we have to do is multiply it with itself.
This can be done by passing the current through similarly oriented transistors in the same
branch. This leads to a stacked topology as in Figure 6.9.

With uneven terms we do not obtain the simple product of currents equation in (6.23).
Instead of using the I–V subthreshold current relationship in (6.2) we will use
' = '

exp ž
~
�
−
Ž
=
4
Ÿ (6.25)

Figure 6.9: Stacked topology with 1 extra CCW transistor.
M
3
I
1
V
DD
I
2
V
DD
I
out
V
DD
+
-
V
3
M
2
+
-
V
2
M
1
+
-
V
1
M
4
+
-
V
4
M
5
+
-
V
5

Figure 6.8: Simple current mirror depicting translinear loop.
I
1
M
1
V
DD
M
2
V
DD
I
out
+
-
V
1
+
-
V
2

84

where I
0
called the pre-exponential factor, contains the threshold voltage as well as the
specific current, I
S
.
'

= '
Ž
exp ž−
~

=
4
Ÿ (6.26)
Applying KVL along the loop as in (6.22) and using the I–V subthreshold current
relationship in (6.26) we get

�
=
4
~
ln ž
'
)
'

¤
)
Ÿ = �
=
4
~
ln ž
'
)
'

¤
)
Ÿ
)∈P

)∈P

(6.27)
By adding logarithmic terms we get

’
'
)
¤
)
)∈P
= '

³
´

³
´
’
'
)
¤
)

)∈P

(6.28)
Using (6.28), Figure 6.9 has an output current of

'
p4
= '

ž
'

'
>
Ÿ
>
¤
l
¤
m
¤
o
¤

¤
>

(6.29)
Therefore if we supply the input current at I
1
to be squared, we do get its square at the
output with an additional '

term. This additional term is not required, and therefore we
must only use equal CW and CCW transistors.
6.4.3.3 Stacked topology with more uneven CW and CCW transistors
From equation (6.21) we see that we need a square of the specific current, I
S
, and from
the previous section if we have uneven CW and CCW terms, we can get an extra I
0
term.
Therefore if we have two extra transistors in either the CW or CCW direction, we can get
two extra I
0
terms giving us a product which is proportional to I
S
2
. An example of a
stacked topology with two extra CCW transistors is shown in Figure 6.10. Going along
the translinear loop drawn in the figure, we can find the output current to be
'
p4
= '

>
œ
'

'
>
>
�
¤
>
¤
l
¤
m

¤

(6.30)

85

If I
1
and I
2
or constant currents, we are only left with the square of the specific current as
required by (6.21).
The issue with this circuit, is the fact that some of the transistors may go out of the
subthreshold region. They can either go in the cut-off or above threshold region, and will
not follow the exponential relation anymore. From the translinear loop, we observe from

Figure 6.11: Stacked squaring circuit with equal CW and CCW transistors.

Figure 6.10: Stacked topology with two extra CCW transistors.
M
2
I
1
V
DD
I
2
V
DD
I
out
V
DD
+
-
V
2
M
1
+
-
V
1
M
3
+
-
V
3
M
4
+
-
V
4

86

Figure 6.10 that

=
>
+
l
+
m
(6.31)
For this to be true, either V
1
has to be large, implying M
1
above threshold, or V
2
, V
3
, V
4
is
very small, implying M
2
–M
4
in cut-off.
6.4.3.4 Squaring circuit with even CW and CCW transistors
Figure 6.11 shows a stacked topology of a squaring circuit. Here I
S
is supplied to the
first branch and I
c
and I
b
are constant currents. Since we have equal CW and CCW
transistors, there is no extra term and the output current is

'
p4
= ž
'
µD}*+*}
'
}
Ÿ
>
'
9
¤
l
¤
o
¤
…
¤

¤
>
¤
m

(6.32)
The stacked nature reduces the headroom at the input nodes. This can be improved by
using an alternating topology. Figure 6.12 shows an alternating topology. As you go
across the translinear loop, the voltage drop increases and decreases one after the other.
The output current produced is

'
p4
= ž
'
µD}*+*}
'
}
Ÿ
>
'
9
ž
¤
>
¤
m
¤
…
¤

¤
l
¤
o
Ÿ
(6.33)

Figure 6.12: Squaring circuit using alternating topology.
M
2
M
7
I
specific
M
1
V
DD
V
ref
I
c
M
4
M
8
I
b
M
3
V
DD
I
c
I
specific
M
5
M
6
V
ref
I
out
+
-
V
1
+
-
V
2
+
-
V
3
+
-
V
4
+
-
V
5
+
-
V
6

87

Here V
ref
is introduced so that the feedback structure, M
2
and M
7
, are maintained in the
subthreshold region. V
ref
is not critical as long as the feedback structure works. Figure
6.14, shows the output current dependence on V
ref
. The zoomed in graph shows that I
out

does not change much with V
ref
. There is only a 1.2% change for 2 V change in V
ref
.
If the transistors are not large enough second order effects like channel length
modulation can affect the output current. The current for NMOS transistor in (6.2)
changes to
' = '
Ž
exp œ
~
�
−

−
Ž
=
4
� 1 + ¶
·Ž
(6.34)
Adding the channel length modulation for the PMOS transistors in Figure 6.12,
equation (6.33) becomes

'
p4
= ž
'
µD}*+*}
'
}
Ÿ
>
'
9
ž
¤
>
¤
m
¤
…
¤

¤
l
¤
o
Ÿ
1 + ¶
Ž·>
1 + ¶
Ž·m
1 + ¶
Ž·…

1 + ¶
Ž·
1 + ¶
Ž·l
1 + ¶
Ž·o

(6.35)
To cancel this error, all the source-drain voltages would have to be equal. For small λ,
and using Taylor series, the extra term becomes

a) b)
Figure 6.13: a) Squaring circuit output current dependence on changes in V
ref
. b) Zoomed-in.
1.4 1.45 1.5 1.55 1.6
119
119.2
119.4
119.6
119.8
120
120.2
120.4
120.6
V
ref
(V)
Iout (pA)
0 0.5 1 1.5 2
0
50
100
150
200
250
V
ref
(V)
Iout (pA)

88

1 + ¶
Ž·>
1 + ¶
Ž·m
1 + ¶
Ž·…

1 + ¶
Ž·
1 + ¶
Ž·l
1 + ¶
Ž·o

≅ 1 + ¶r
Ž·>
+
Ž·m
+
Ž·…
−
Ž·
+
Ž·l
+
Ž·o
s
(6.36)
Therefore we can also cancel the error term if

�
Ž·)
= �
Ž·)
)∈P )∈P

(6.37)
Figure 6.14 shows the squaring circuit functionality. It can be seen that the simulated
data matches the ideal function. I
c
and I
b
were set to 200 pA and 120 pA respectively. I
S

is I
in
and is swept from 200 pA to 400 pA.

6.4.4 Correction block
In this section first an error term is introduced and then a correction circuit is designed
to cancel the error. A fine-tuned constant transconductance bias system is thereby
created.
6.4.4.1 Error term introduced
The required function for PTAT current shown in (6.20) will be re-written as follows:

Figure 6.14: Squaring circuit simulation.
200 250 300 350 400
100
150
200
250
300
350
400
450
500
Iin (pA)
Iout (pA)

ideal function
simulation

89

'
„l
= œ
'

C+

'
Ž
�

C+
>

(6.38)
mf is introduced to differentiate from the actual physical mobility temperature exponent
m, of I
S
of the transistor. mf reflects the ideal function designed in the circuit. The ideal
mf was chosen to be 1.5 leading to (6.21), which can be re-written as
'
„l
=
'
Ž
>
'

(6.39)
The temperature dependence of I
S
can be seen in (6.3). If m of I
S
is 1.5, then

'
Ž
∝ F
>
C
= F

>

(6.40)
and I
M3
will be PTAT, by

'
„l
= ž
'
Ž
'

Ÿ
>
∝ F
(6.41)
The issue with the approach of squaring the specific current to get a PTAT current is
when m is not 1.5. For this case, let u ≡ uº + δu, where δm is an incremental change
in m. In this case, instead of getting a PTAT current, we have

'
Ž
∝ F
>
C+ :»C
= F
>
.o:»C
= F

>

»C

(6.42)
and I
M3
will be slightly off compared with (6.41) as follows

'
„l
= ž
'
Ž
'

Ÿ
>
∝ F × F

> »C

(6.43)
6.4.4.2 Correction circuit
Transistors with different sizes can have different physical parameters. We can have
two different transistors with different m values [22], as in the circuit in Figure 6.15. Let
us assume that they have similar threshold voltages. M
1
and M
2
form a current mirror
and I
2
can be expressed as

90

'
>
=
'
Ž>
'
Ž
'

= '

¤
>
¤

ž
F
F

Ÿ
C
²

C
¼
(6.44)
The specific currents will be different, as the transistors have different aspect ratios and m
values.
From (6.43), if we apply I
M3
to I
1
and if we set m
1
– m
2
to be equal to 2δm, we can get
the PTAT current as follows
'
>
= '
„l
¤
>
¤

ž
F
F

Ÿ
C
²

C
¼
∝ F × F

> »C
ž
F
F

Ÿ
C
²

C
¼
∝ F (6.45)
Figure 6.16a shows the output current vs. temperature with u

− u
>
≜ u
>

set to be
close 0.5. The input current is constant with T and the expected output current is
'
>
= '

¤
>
¤

ž
F
F

Ÿ
C
²

C
¼
∝ F
C
²

C
¼
(6.46)
We see that the cadence simulation does not match the expected function. To create a
simple solution as in (6.45) we assumed that the threshold voltages were the same for the
differently sized transistors. This is not true, as V
T0
will be different for different
transistor sizes. Re-writing a complete version of the I–V current equation in (6.2) we
have
'

= '
Ž
exp œ
κ
6
−

−
¾¿¿
−

=
4
� (6.47)

Figure 6.15: Correction block, using two different transistors with different m.

91

The equation above includes a V
OFF
term. V
OFF
is the subthreshold offset voltage and it
models the drain current at V
GS
= 0 [23]. With different V
T0
and V
OFF
the output current
of the current mirror becomes

'
>
= '

¤
>
¤

ž
F
F

Ÿ
C
²

C
¼
exp œ
~

+
¾¿¿
−

>
−
¾¿¿>

=
4
�
(6.48)
The extra exponential term effect can be seen in Figure 6.16b. The function including
ΔV
T0
and ΔV
OFF
almost matches the cadence simulation. It is off by less than a pico-amp.
To cancel the offsets in threshold voltage and offset voltage, we would need to find a
technology that has different m values but the same V
T0
and V
OFF
for different transistor
sizes. Since we are not afforded this option in the technology being used, another method
is used.
By incorporating a source voltage V
S
for one of the transistors, the exponential term
can be reduced to 1. The output current for the case having V
S
and using BSIM models,
results in

a) b)
Figure 6.16: a) I
2
vs. T with constant I
1
. b) Extra plots with offsets in V
T0
and V
OFF
.
-20 0 20 40 60 80 100
8.5
9
9.5
10
10.5
11
11.5
12
12.5
Temperature (°C)
I (pA)

simulation
f=T
m
1
-m
2
-20 0 20 40 60 80 100
6
7
8
9
10
11
12
Temperature (°C)
Current (pA)

f=T
m
12
simulation
f() with ΔV
T0
,ΔV
OFF

92

'
>
= '

¤
>
¤

ž
F
F

Ÿ
C
²

C
¼
exp œ
~

+
¾¿¿
−

>
−
¾¿¿>
+
Ž

=
4
�
(6.49)
If we set
Ž
= −

+
¾¿¿
−

>
−
¾¿¿>
, we cancel the extra exponential
term and have the required equation as in (6.48). Figure 6.17a shows the current mirror
along with the V
S
voltage source. Figure 6.17b shows that the function with V
S
as in
(6.49) matches the required function, f = T
m1–m2
. In this way we can create an accurate
correction block.
6.4.5 Specific current extractor
The specific current extractor uses the concept of inversion levels. In inversion level
defines whether the transistor is in subthreshold or above threshold. If i
f
< 1 the
transistor is in subthreshold and if i
f
> 1 the transistor is above threshold. The specific
current also corresponds to the cross point of the weak and strong inversion asymptotic
characteristics. In order to encompass subthreshold and above threshold regions in one
equation, an interpolation function of the EKV model will be used [43]:

a) b)
Figure 6.17: a) Introducing V
S
to current mirror to remove exponential term. b) Simulated data with
V
S
matches required function, f = T
m1–m2
.
-20 0 20 40 60 80 100
20
22
24
26
28
30
32
34
Temperature (°C)
Current (pA)

f=T
m
12
simulation
f() with ΔV
T0
,ΔV
OFF
f() with ΔV
T0
,ΔV
OFF
, Vs

93

'
¿À
= '
Ž
Áln ž1 + exp Á

¦
−
Ž·
2=
4
ÂŸÂ
>

(6.50)
where I
F(R)
is the forward or reverse current, if V
S
or V
D
is applied respectively. V
P
is the
pinch-off voltage. V
P
represents the voltage that should be applied to the equipotential
channel (source and drain tied together) to cancel the effect of the gate voltage. It is
related to the gate voltage by

¦
≅ ~
�
−

(6.51)
In subthreshold (6.50) becomes
'
¿À
= '
Ž
exp Á

¦
−
Ž·
=
4
Â (6.52)
And in above threshold it becomes

'
¿À
= '
Ž
Á

¦
−
Ž·
2=
4
Â
>

(6.53)
The drain current, I
D
can now be written as
'
·
= '
¿
− '
À
= '
Ž
V
+
− V
–
(6.54)
where i
f
= I
F
/I
S
and i
r
= I
R
/I
S
are dimensionless inversion levels of the forward and reverse
currents.
If a bias current equal to the specific current I
S-ref
of a reference transistors is available
(having aspect ratio, S
ref
= 1), any transistor M
x
with aspect ratio S
x
can be operated at a
given inversion factor by weighting by

™ =
¤
A
V
+A
$¤
–D+
V
+
–D+
&
= ¤
A
V
+A

(6.55)
with S
ref
and i
f-ref
of the reference transistor set to 1. i
f-ref
is 1 since the transistor is biased
by I
S-ref
. K is implemented by a weighted current mirror. Thus with a reference current
equal to the specific current of a transistor can generate inversion factors of other
transistors by weighting.

94

6.4.5.1 Specific current extractor using strong inversion
An example of a specific current extractor is shown in Figure 6.18. M
1
is biased in
weak inversion, whereas M
2
is biased N × M larger and is in strong inversion. The
comparison between the two drains at M
1A
and M
2A
is done in the middle branch. And
since M
4
is N times wider than M
1B
, its source voltage is equal to that of M
1B
. The drain
voltage of M
3,
which is M times longer than M
2A
, is equal to the source of M
2B
.
Connecting M
4
and M
3
forces the two channels to be equal. The inversion factor can then
be calculated as in [43]. The current can then be weighted to any output transistor. The
output current can also be divided down to get lower currents that are also process and
temperature invariant.

6.4.5.2 Specific current extractor without using strong inversion
The specific current extractor in [44] will be used, as it only uses weak inversion and
moderate inversion, thereby lowering power consumption of the current reference. The
self biased current source uses 1) a PTAT voltage produced by operating transistors in the
weak inversion, and 2) the output current is proportional to the transistor’s specific
current.

Figure 6.18: Specific current extractor.
M
6
M
1B
M
4
M
5
M
1A
M
3
M
2B
M
7
M
2A
1:N 1:M
I NxI NxMxI

95

The specific current generator is based on the stacked transistor in Figure 6.19. M
2
is
in saturation whereas M
1
is in triode. From the figure and since M
2
is in saturation we
have
'
·>
≅ '
¿>
= '
Ž>
V
+ >
= '
–D+
(6.56)
since I
F
>> I
R
in saturation. Since M
1
is in triode we have
'
·
= '
¿
− '
À>
= '
Ž>
V
+ >
− V
–>
= '
–D+
+ 1 (6.57)
M
1
and M
2
have the same pinch-off voltage, V
P
, as they have their gates are tied
together. This leads to the fact that i
r1
= i
f2
, and from (6.56) and (6.57) we get
V
+
= V
+ >
Á1 +
¤
>
¤

ž1 +
1

ŸÂ (6.58)
Using (6.50) we can find for M
2

¦
−
Ã
2=
4
= lnÄexp$ÅV
+ >
&− 1Æ (6.59)
and for M
1

¦
2=
4
= lnÄexp$ÅV
+
&− 1Æ (6.60)
Using (6.58)–(6.60) we can solve for V
X
:

Figure 6.19: Stacked transistor.
M
2
M
1
Sat.
Triode
NI
ref
V
DD
I
ref
V
DD
V
x

96

Ã
= 2=
4
ln Ç
exp$
Å
V
+ >
È&− 1
exp$
Å
V
+ >
&− 1
É (6.61)
where È = 1 +
Ž
¼
Ž
²
_1 +

³
b . Therefore if V
X
is known, we can find i
f1
or i
f2
and
consequently the current through the stacked transistor. A plot of (6.61) is shown in
Figure 6.20. For i
f2
values in the moderate inversion we need to use (6.61) to find V
X
. In
weak inversion where i
f2
is very small, the graph asymptotes and can be approximated by

Ã
= =
4
lnÈ (6.62)
V
X
can be set by the circuit in Figure 6.21. With M
5
and M
6
in weak inversion (W.I.)
and using (6.50) we find

Ã
=
Ž…
+ =
4
ln(™ (6.63)
V
S6
can either be 0 V or a PTAT voltage that is generated using another stacked transistor
in W.I. as shown in equation (6.62). The PTAT V
X
results in a constant i
f
regardless of
temperature as can be seen in (6.61).
By equating (6.61) and (6.63) we can obtain a fixed inversion coefficient resulting in a
drain current given by (6.56). Therefore the output current is a multiple of the specific
current. We reach this solution by tying the circuits in Figure 6.19 and Figure 6.21

Figure 6.20: Graphical version of (6.61) asymptotes for small i
f2
.
10
-2
10
0
10
2
10
0
10
1
10
2
if
2
V
X
/U
t

97

together, and the final result can be seen in Figure 6.22.
In our design, we have N = J = K = 1. S
2
/S
1
= 1.2, i
f2
= 3 and from (6.58) i
f1
= 10.2,
thus ensuring M.I. operation. At the nominal temperature we have I
D
= 560 pA. More
simulations on the specific current will be shown in the forthcoming sections.

Figure 6.22: Specific current extractor without S.I. transistors.

Figure 6.21: Circuit that creates required voltage, V
X
.
M
6
M
5
M
9
V
DD
M
8
V
S6
+
-
V
X
1:J
K:1
W.I.

98

6.4.6 System simulations and comparisons
The PTAT current source is created after connecting all the previous blocks together,
beginning with the specific current generator, then, the divider and squaring circuit
followed by the correction circuit as in Figure 6.23. The temperature characteristics at
each of the blocks are shown below. Figure 6.24a shows the specific current output that
has a nominal current of about 560 pA. Comparing I
S

with it corresponding function in T.
From (6.3) and (6.6) the function in T is T
2 – m
. At higher temperatures we see I
S
dipping
below the ideal expected function. This can be due to other higher order temperature
effects like channel length modulation. I
M3
matches the ideal function closely as the error
in I
S
has been divided down in the squaring circuit.

a) b)
Figure 6.24: a) I
M3
better match than I
S
, as error divided down in squaring circuit. b) Corrected PTAT
current along with the g
m
of the transistor it biases.
-40 42.5 125
400
500
600
700
Current (pA)

ideal f=T
2-m
I
S
simulation
-40 42.5 125
50
100
150
200
Temperature (°C)
Current (pA)

ideal f=T
2(2-m)
I
M3
simulation
-40 42.5 125
20
30
40
50
Current (pA)

ideal f=T
Corrected PTAT-I simulation
-40 42.5 125
850
855
860
865
Temperature (°C)
Transconductance (pS)

g
m

Figure 6.23: Final system: PTAT current or constant subthreshold g
m
bias generator.

99

After correcting the output from the squaring circuit we get a close match to a PTAT
current, as can be seen in Figure 6.24b. The transistor biased with this corrected current
shows a g
m
variation of ±0.63% for a temperature range of -40 °C to 125 °C. The same
corrected current when applied to the four stage BPF of the event detector chip shows a
variation of ±0.3% in the center frequency and ±3.4% in the gain. The PTAT current
generated ensures a sturdy BPF centered at 40 Hz. These results can be seen in Figure
6.25.

6.4.6.1 Transconductance sensitivity to different parameters
The following simulations will depict variations in the system due to different voltages
and different corners. Figure 6.26a shows the specific current change with power supply.
We see that the circuit can be operated at a power supply as low as 1.1 V and there is a
3.3% /V change in I
S
. These results are similar to that in [44]. For a ±5% change in
power supply there is a total ±0.8% g
m
variation over both V
DD
and T. Since the I
S
varies
with V
DD
due to the channel length modulation [44], the g
m
variation with V
DD
is also not
as sturdy in comparison with other state of the art constant gm circuits. Comparisons
with state of the art constant transconductance circuits will be shown in the next section.
To resolve this problem, we either need another I
S
circuit or a V
DD
accuracy depending on
the required accuracy of g
m
.

Figure 6.25: Frequency response of the four stage BPF at different temperatures.
41 41.5 42 42.5 43 43.5
80
82
84
86
88
90
Frequency (Hz)
Gain (V/V)

-40°C
-7°C
26°C
59°C
92°C
125°C

100

The correction circuit uses a voltage source, V
S
. This voltage is critical in canceling
the unwanted exponential term as can be seen in (6.49). Since V
S
is in the exponent, it
needs to be set accurately by a band gap reference circuit. Using a state of the art band
gap reference having a ±0.15% variation in voltage over T [45], and applying this
variation to the required V
S
of 26 mV and we can see the variation in g
m
in Figure 6.27.
The highest variation in g
m
(±0.64%) is for V
S
+ 0.15%. The total variation over V
S

and T is ±0.7%. To forgo the need of an accurate V
S
or any source voltage at all, we

Figure 6.27: g
m
vs. T for different V
S
.
-40 42.5 125
848
850
852
854
856
858
860
862
864
Temperature (°C)
Transconductance (pS)

V
S
=25.961mV
V
S
=26mV
V
S
=26.039mV

a) b)
Figure 6.26: Power supply variations of a) I
S
and b) g
m
.
0 1 2 3
0
100
200
300
400
500
600
V
DD
(V)
I (pA)
-40 42.5 125
848
850
852
854
856
858
860
862
864
Temperature (°C)
Transconductance (pS)

V
DD
=1.52V
V
DD
=1.6V
V
DD
=1.68V

101

would need to find a technology that has the same threshold voltage and off-set voltage
but different m values, since only different m values are required to create the correction
circuit.
Figure 6.28 shows a corner analysis. The slow-slow (SS) corner shows the highest
variation of ±0.6%. The fast-fast (FF) corner has the lowest variation of ±0.2%. The
specific current circuit is not as accurate for SS corner due to weaker transistors. A
different V
S
voltage needs to be set for the different corners. The absolute g
m
values can
be changed using the constant current sources in the squaring circuit.
6.4.6.2 Comparison with state of the art
Table 6.1 shows the features of the proposed constant transconductance circuit in
comparison with the state of the art circuits. We see that compared with the subthreshold
transconductance circuits we have the least variation (±0.63%) for a similar temperature
range (-40 °C to 125 °C). Including the V
S
change the g
m
change is ±0.7%, which is only
slightly higher than ±0.66% reported in [51]. But we attain a very low power
consumption of less than 9 nW and there are no external resistors or opamps. The only
drawback of this circuit is the variation with respect to power supply. It is higher than
other reported work and is a result from the effect change in power supply has on the

Figure 6.28: Corner analysis.
-40 42.5 125
600
700
800
900
1000
1100
1200
Temperature (°C)
Transconductance (pS)

SS, V
S
=27mV
TT, V
S
=26mV
FF, V
S
=24mV

102

specific current generator. The only way around this is by designing a new specific
current generator that has better power supply independence.

6.5 False-positive rejection
The smart seismic sensor must detect potential threats (humans or approaching
vehicles) and discriminate against false positives which are generated by random
spurious events e.g. a falling tree limb or foliage, etc. The redesigned system is shown in
Figure 6.29 [52] where a false positive detection block has been added between B and C.
If a true event has occurred, eliminating false positives, the microcontroller is turned ‘on’.
The seismic based threat sensor detects and discriminates among approaching humans,
animals, and vehicles vs. background and a single vibration event, e.g. the falling of a
tree limb. After some events, and after false positive correction, the main controller is
woken up for further classification processing.
Table 6.1: Comparison with state of the art.
Region g
m
change T range Power g
m
change with V
DD
Extras
Above-vt [46] ±1.5% 20 °C to 80 °C 1.275 mW ±1% for 20% V
DD
Accurate clocks
Above-vt [47] ±1.5% 100 °C - - Precise R
Sub-vt [48] ±0.7% -30 °C to 110 °C 110 nW - Precise R, opamp
Above-vt [49] ±1% -25 °C to 125 °C 486 μW ±0.3% for ±10%
V
DD

PTAT, CTAT, Rs,
BJTs
Above-vt [50] ±0.25% -20 °C to 100 °C > 300 μA ±0.18% for ±10%
V
DD

Feedback, opamp,
clocks
Above and sub-
vt [51]
±0.22%(above-vt)
±0.66%(sub-vt)
-60 °C to 130 °C 2 mA - R, opamp
This work Sub-
vt and M.I.
±0.63%
(±0.7% with V
S

change)
-40 °C to 125 °C < 9 nW ±0.8% for ±5%
V
DD

No R

103

A time interval between events is checked for true events. Only if consecutive events
occur within a time window (t
window
) will a true event signal be sent to the microcontroller
stage. Spike generators are used in the false positive. A periodicity detector, which finds
timing between spikes as in [34] uses only one spike generator and requires other timing
circuitry like reset and sample. In this case, two spiking generators are used without the
need for other sophisticated timing circuitry.
6.5.1 System architecture
After the event detector, the false positive detection sends a true event (V
Corrected-Event
)
to the micro-controller. The architecture of the false positive detector, shown in Figure
6.30, consists of two spike generators (SG), source followers (SF) and comparators each.
The spike generator circuit will be discussed.

Figure 6.30: False positive correction circuit.

Figure 6.29: Subthreshold event detector with false positive correction block.

104

A SG is used to catch the onset of an event, creating a ‘time stamp’. SG
2
has a long
refractory period T
ref2
(sets the time window constraint for next spike), and the other has a
short refractory period T
ref1
, that catches all the events. The refractory period as in
biological neurons is the time required for the neuron or circuit in this case to generate a
new spike after firing a spike. These signals are then passed through the SF, which has a
slow fall time to create ramps as shown in the figure. The first ramp of V
SF2
, spikes to the
supply voltage (V
DD
) and ramps down by (6.64) and V
thresh2
is set by (6.65), once the
desired time window (t
window
) has been reached. V
Turn-on
goes high when Comp
2
detects
V
SF2
below V
thres2
. V
Turn-on
, turns on Comp
1
.

V
Ž¿>
=
··
-
'-
@

(6.64)

V
4 Ì–DÌ>
=
··
-
'-
Í*)Í
@

(6.65)
where, I and C are the discharging current and capacitance of the SF respectively.
SG
1
catches all the events. The idea here is that when V
Turn-on
goes high (t
window
is
complete) and if V
SF1
> V
thresh1
, it would imply more than one spike within t
window
.
V
4 Ì–DÌ
=V
4 Ì–DÌ>
+ ε (6.66)
ε gives design freedom and can be chosen a little above V
thresh2
. Since SG
1
pulses for
every event, SF
1
resets the ramp to V
DD
. At t
4
in V
SF1
, there is only one pulse within t
window

and the ramp is below V
thresh1
, thus no output at V
Corrected-Event
at t
4
. Whereas at t
5
, two
pulses arrive within t
window
, and as a result V
SF1
is above V
thresh1
, and V
Corrected-Event
goes
high at t
5
. Another note is that T
ref2
> t
window
. T
ref2
– t
window
should be long enough so that
Comp
1
is on long enough to sample V
SF1
.
6.5.2 Spike generator
The SG shown in Figure 6.31 only catches the onset of an event. When an event
occurs, V
C
goes high and a current is forced into M
5
and thus M
6
by the mirror. The

105

output, spike, is pulled down. I
pull-up
, controls the spike duration. When V
C
stabilizes to
V
DD
, no DC current flows through C and the spike goes ‘off’.
The time taken for V
C
to go low is controlled by I
refr
. V
C
has to go low enough before a
new event can create a spike. If there are spikes within T
refr
, V
C
gets reset to V
DD
, and T
refr

has to be passed again for a new spike to be generated. If there are continuous spikes
before T
refr
is over, the circuit will never fire a spike. As can be seen in V
SF2
(Figure
6.30), if a new spike arrives at t
5
, no new spike is generated. V
SF2
is below V
thresh2
and
V
Turn-on
will remain on so Comp
1
can compare V
SF1
.
The source follower has a slow fall time controlled by the discharging current I over
C, which relates to (6.64) and (6.65).

6.5.3 Simulation
The same footstep signal is used to simulate the system. Figure 6.32 shows the output
along with the corrected event. It can be seen that there is no corrected event after the
second event, because the time interval is longer than t
window
, but the interval is less than
t
window
between the second and third event and likewise all the others and thus corrected
events are seen successively. Very short intervals between spikes may not be detected by
the false positive detector if T
ref1
is longer than the interval. Care must be taken in
selecting T
ref1
or a limiter should be added to the events to prevent such situations.

Figure 6.31: Spike generator.

106

Figure 6.32: Corrected event without false positives.
0 5 10 15 20 25 30
-5
0
5
Voltage (mV)

Footstep
0 5 10 15 20 25 30
0
0.5
1
1.5
2
Time (s)
Voltage (V)

Event (no false positive)
Event

107

Chapter 7
Conclusion
An ultra-low-power event detector has been designed for long-term persistent sensor-
based surveillance systems. An analog front-end event detector operating in subthreshold
region of CMOS transistors consuming 38 nW of power has been designed, enhancing
the longevity of the sensor. The fabricated chip ensures feasibility of the design and the
realistic power savings achievable.
Comparing to the digital system in terms of power; the digital system consumed
7.4 mW and the subthreshold analog system consumes about 40 nW, delivering about a
160,000 times power reduction. In terms of performance there is a loss in gain in some
of the stages of the BPF. Overall, with the power savings in mind, this is a huge
improvement and thus can add to the battery life. Also, the tremendous improvement in
power consumption implies the possibility to add 160,000 times the signal processing
capability at the front-end of these security sensors.
The noise cancelling mechanism helps improve the systems SNR, it also rejects false
positives received from generators, motors or any other constant noise sources. The two
filters help clean the incoming signal and also do a pre-classification. From previous
statistical data, the 40 Hz and 100 Hz bands provide important information for footstep
and vehicular signals. All the above benefits along with the operation of the entire front-
end event detector for seismic sensors in subthreshold domain provide insights into the
tremendous power saving achievable.
To make the chip insensitive to PVT variations, large transistors are required to
minimize mismatch and a constant transconductance bias consuming 9 nW of power has
been used to compensate for temperature variations. Compared with other constant
transconductance circuits we have the least variation (±0.63%) for a similar temperature

108

range (-40 °C to 125 °C). Including the V
S
change, the gm change is ±0.7%, which is
only slightly higher than ±0.66% reported in [51]. But we attain a very low power
consumption of less than 9 nW and there are no external resistors or opamps. The
variation with respect to power supply is a little higher than some reported work due to
the sensitivity of the specific current generator. Also to forgo the need of an accurate V
S
,
a technology with the same V
T0
and V
OFF
and different m values for different transistors is
required for the correction circuit.
The sensor chip with enhanced operating temperature range is promising for
implementing seismic sensors for various military needs like perimeter or border control
in harsh environments. The large power savings virtually makes the sensors last forever.
Low power also translates to low heat dissipation. Low heat dissipation and long lasting
subthreshold circuits are vital for biomedical implants. The subthreshold circuits
designed are insensitive to mismatches and PVT variations and prove an ideal candidate
for biomedical implants as well.

109

References
[1] U. Antao, J. Choma, A. Dibazar, and T. Berger, "40nW subthreshold event
detector chip for seismic sensors," in IEEE Int. Symp. on Technologies for
Homeland Security (HST), 2015, pp. 1-6.
[2] U. Antao, J. Choma, A. Dibazar, and T. Berger, "Low power, long life design for
smart intelligence, surveillance, and reconnaissance (ISR) sensors," in IEEE Conf.
on Technologies for Homeland Security (HST), 2012, pp. 631-636.
[3] H.-O. Park, A. A. Dibazar, and T. W. Berger, "Discrete Synapse Recurrent Neural
Network with time-varying delays for nonlinear system modeling and its
application on seismic signal classification," in International Joint Conference on
Neural Networks (IJCNN), 2011, pp. 2374-2381.
[4] A. Barzilai, T. VanZandt, T. Pike, S. Manionand, and T. Kenny, "Improving the
Performance of a Geophone through Capacitive Position Sensing and Feedback,"
in American Society of Mechanical Engineers International Congress, 1998.
[5] A. A. Dibazar, A. Yousefi, H. O. Park, B. Lu, S. George, and T. W. Berger,
"Intelligent acoustic and vibration recognition/alert systems for security breaching
detection, close proximity danger identification, and perimeter protection," in
Technologies for Homeland Security (HST), 2010, pp. 351-356.
[6] W. Hu, Y.-T. Liu, T. Nguyen, D. C. Lie, and B. P. Ginsburg, "An 8-Bit Single-
Ended Ultra-Low-Power SAR ADC With a Novel DAC Switching Method and a
Counter-Based Digital Control Circuitry," in IEEE Transactions on Circuits and
Systems I: Regular Papers, 2013, vol. 60, pp. 1726-1739.
[7] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, "A 7-to-10b 0-to-
4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step," in IEEE

110

International Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
2012, pp. 472-474.
[8] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, "A 8-bit 500-KS/s low power SAR
ADC for bio-medical applications," in IEEE Asian Solid-State Circuits Conference
(ASSCC'07), 2007, pp. 228-231.
[9] T. Schneider, R. Brennan, P. Balsiger, and A. Heubi, "An ultra low-power
programmable DSP system for hearing aids and other audio applications," in Proc.
ICSPAT, 1999.
[10] T. T. Hoang, M. Sjalander, and P. Larsson-Edefors, "High-speed, energy-efficient
2-cycle multiply-accumulate architecture," in IEEE International SOC Conference
(SOCC), 2009, pp. 119-122.
[11] J.-K. Chang, H. Lee, and C.-S. Choi, "A power-aware variable-precision multiply-
accumulate unit," in 9th International Symposium on Communications and
Information Technology (ISCIT), 2009, pp. 1336-1339.
[12] R. Chawla, A. Bandyopadhyay, V. Srinivasan, and P. Hasler, "A 531 nW/MHz,
128Ã— 32 current-mode programmable analog vector-matrix multiplier with over
two decades of linearity," in Proceedings of the IEEE Custom Integrated Circuits
Conference, 2004, pp. 651-654.
[13] L. Watts, "Cochlear mechanics: Analysis and analog VLSI," California Institute of
Technology, 1992.
[14] R. Sarpeshkar, R. Lyon, and C. Mead, "A low-power wide-dynamic-range analog
VLSI cochlea," Neuromorphic systems engineering, pp. 49-103, 1998.
[15] D. H. Goldberg, A. G. Andreou, P. Julian, P. O. Pouliquen, L. Riddle, and R.
Rosasco, "A wake-up detector for an acoustic surveillance sensor network:
Algorithm and vlsi implementation," in Information Processing in Sensor
Networks, 2004, pp. 134-141.

111

[16] H. Abdalla and T. K. Horiuchi, "An analog VLSI low-power envelope periodicity
detector," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2005,
vol. 52, pp. 1709-1720.
[17] E. A. Vittoz, "Analog VLSI signal processing: Why, where, and how?" Journal of
VLSI signal processing systems for signal, image and video technology, 1994,vol.
8, pp. 27-44.
[18] B. Gilbert, "Translinear circuits: an historical overview," Analog Integrated
Circuits and Signal Processing, 1996, vol. 9, pp. 95-118.
[19] S. C. Liu, Analog VLSI: Circuits and principles: The MIT press, 2002.
[20] A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-threshold design for ultra
low-power systems: Springer, 2006.
[21] S. M. Sze and K. K. Ng, Physics of semiconductor devices: John Wiley & Sons,
2006.
[22] M. C. Hsu and B. J. Sheu, "Inverse-geometry dependence of MOS transistor
electrical parameters," in IEEE Tran. on Computer-Aided Design of Integr.
Circuits and Syst., vol. 6, pp. 582-585, 1987.
[23] Y. Cheng, M. Chan, K. Hui, M.-c. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu,
and P. K. Ko, "BSIM3v3 manual," University of California, Berkeley, 1996
[24] P. Kinget and M. Steyaert, "Implications of Transistor Mismatch on Analog
Circuit Design and System Performance," in Analog VLSI Integration of Massive
Parallel Signal Processing Systems: Springer, 1997, pp. 21-81.
[25] K. L.-c. Su, Analog filters: Springer, 2002.
[26] D. W. Graham and P. Hasler, "Capacitively-coupled current conveyer second-
order section for continuous-time band pass filtering and cochlea modeling," in
International Symposium on Circuits and Systems, 2002, pp. V-485-V-488 vol. 5.

112

[27] D. W. Graham, P. E. Hasler, R. Chawla, and P. D. Smith, "A low-power
programmable band pass filter section for higher order filter applications," in IEEE
Transactions on Circuits and Systems I: Regular Papers, 2007, vol. 54, pp. 1165-
1176.
[28] K. Martin and D. Johns, Analog integrated circuit design, New York: Wiely, 1997.
[29] S. Khucharoensin and V. Kasemsuwan, "High performance CMOS current-mode
precision full-wave rectifier (PFWR)," in International Symposium on Circuits and
Systems, 2003, pp. I-41-I-44 vol. 1.
[30] J. Alegre, S. Celma, B. Calvo, and J. M. G. del Pozo, "Design of a novel envelope
detector for fast-settling circuits," in IEEE Transactions on Instrumentation and
Measurement, 2008, vol. 57, pp. 4-9.
[31] Y. Zhou, G. Huang, S. Nam, and B. S. Kim, "A novel wide-band envelope
detector," in Radio Frequency Integrated Circuits Symposium, 2008, pp. 219-222.
[32] B. Gilbert, "Translinear circuits: A proposed classification," Electronics Letters,
vol. 11, pp. 14-16, 1975.
[33] H. Shao and C. Y. Tsui, "A robust, input voltage adaptive and low energy
consumption level converter for sub-threshold logic," in International Solid-State
Circuits Conference, 2007, pp. 312-315.
[34] H. Abdalla and T. K. Horiuchi, "An analog VLSI low-power envelope periodicity
detector," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2005,
vol. 52, pp. 1709-1720.
[35] E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak
inversion operations," in IEEE Journal of Solid-State Circuits, 1977, vol. 12, pp.
224-231.
[36] B. Linares-Barranco, T. Serrano-Gotarredona, R. Serrano-Gotarredona, and C.
Serrano-Gotarredona, "Current mode techniques for sub-pico-ampere circuit

113

design," Analog Integrated Circuits and Signal Processing, 2004, vol. 38, pp. 103-
119.
[37] P. Heim, S. Schultz, and M. Jabri, "Technology-independent biasing technique for
CMOS analogue micropower implementations of neural networks," in Proc. 4th
Int. Workshop Cellular Neural Networks and Their Applications (CNNA-95),
1995.
[38] C. C. Enz and E. A. Vittoz, "CMOS low-power analog circuit design," in
Designing Low Power Digital Systems, Emerging Technologies, 1996, pp. 79-133.
[39] J. M. Steininger, "Understanding wide-band MOS transistors," in IEEE Circuits
and Devices Magazine, 1990, vol. 6, pp. 26-31.
[40] R. H. Zele and D. J. Allstot, "Low-power CMOS continuous-time filters," in IEEE
Journal of Solid-State Circuits, 1996, vol. 31, pp. 157-168.
[41] J. Chen and B. Shi, "Novel constant transconductance references and the
comparisons with the traditional approach," in Southwest Symposium on Mixed-
Signal Design, 2003, pp. 104-107.
[42] B. Gilbert, "Translinear circuits: A proposed classification," Electronics Letters,
vol. 11, pp. 14-16, 1975.
[43] C. C. Enz and E. A. Vittoz, "CMOS low-power analog circuit design," in
Designing Low Power Digital Systems, Emerging Technologies, 1996, pp. 79-133.
[44] E. M. Camacho-Galeano, C. Galup-Montoro, and M. r. C. Schneider, "A 2-nW
1.1-V self-biased current reference in CMOS technology," in IEEE Transactions
on Circuits and Systems II: Express Briefs, 2005, vol. 52, pp. 61-65.
[45] G. Ge, C. Zhang, G. Hoogzaad, and K. A. Makinwa, "A single-trim CMOS
bandgap reference with a inaccuracy of 0.15% from 40 C to 125 C," in IEEE
Journal of Solid-State Circuits, 2011, vol. 46, pp. 2693-2701.

114

[46] N. Talebbeydokhti, P. K. Hanumolu, P. Kurahashi, and U.-K. Moon, "Constant
transconductance bias circuit with an on-chip resistor," in Proceedings IEEE
International Symposium on Circuits and Systems, ISCAS, 2006, pp. 4 pp.-2860.
[47] S. Pavan, Y. P. Tsividis, and K. Nagaraj, "Widely programmable high-frequency
continuous-time filters in digital CMOS technology," in IEEE Journal of Solid-
State Circuits, 2000, vol. 35, pp. 503-511.
[48] V. Agarwal and S. Sonkusale, "Ultra low power PVT independent sub-threshold
gm-C filters for low frequency biomedical applications," Analog Integrated
Circuits and Signal Processing, 2010, vol. 66, pp. 285-291.
[49] J. Chen and B. Shi, "Circuit design of an on-chip temperature-compensated
constant transconductance reference," Analog Integrated Circuits and Signal
Processing, vol. 37, pp. 215-222, 2003.
[50] I. Mondal and N. Krishnapura, "Accurate Constant Transconductance Generation
without Off-Chip Components," in 28th International Conference on VLSI Design
(VLSID), 2015, pp. 249-253.
[51] C.-Y. Chu and Y.-J. Wang, "A PVT-Independent Constant-Bias Technique Based
on Analog Computation," in IEEE Transactions on Circuits and Systems II:
Express Briefs, 2014, vol. 61, pp. 768-772.
[52] U. Antao, A. Dibazar, J. Choma, and T. Berger, "Low power false positive tolerant
event detector for seismic sensors," in IEEE SOI-3D-Subthreshold
Microelectronics Technology Unified Conference (S3S), 2013, pp. 1-2.

Abstract (if available)

Abstract Unattended ground sensors (UGS) are widely used for persistent, surveillance that detects potential threats from intruders without generating false alarms. Battery life is the limiting factor for solutions using digital processing. A 40 nW subthreshold event detector chip in a 150 nm CMOS (complementary metal oxide semiconductor) process is fabricated and tested, that wakes up a threat classifying stage. The event detector processes the signal, using band pass filters, envelope detectors, noise canceling mechanisms and a thresholding function to trigger an event. The chip is compared with a previous generation all digital system. The chip consumes 160,000 times less power than its digital counterpart, but due to subthreshold operation the chip is prone to mismatches and temperature variations, resulting in loss in gain in the system thereby missing low amplitude events. ❧ Methods to reduce mismatches and temperature variations are proposed promising a sturdy UGS. Constant transconductance is an important circuit feature that relates to keeping gain and bandwidth of several analog circuits constant with process, voltage, and temperature (PVT). A 9 nW PVT invariant subthreshold transconductance bias circuit is developed using the 150 nm CMOS process. Comparing with previous constant transconductance circuits, the circuit neither uses external components nor strong inversion transistors, thereby improving stability and lowering the power. The design method finds a temperature dependent gate voltage across a transistor producing a constant transconductance current over temperature for subthreshold region. A correction block improves the stability of the transconductance using the mobility temperature exponent, m, of electrons of NMOS transistors. Simulations show that the circuit can achieve ±0.63% variation in subthreshold transconductance over -40 ℃ to 125 ℃, greatly enhancing the robustness of the event detector to PVT changes.

Linked assets

University of Southern California Dissertations and Theses

Conceptually similar

PDF

Improving the speed-power-accuracy trade-off in low-power analog circuits by reverse back-body biasing

PDF

Charge-mode analog IC design: a scalable, energy-efficient approach for designing analog circuits in ultra-deep sub-µm all-digital CMOS technologies

PDF

A biomimetic approach to non-linear signal processing in ultra low power analog circuits

PDF

A power adaptive low power low noise band-pass auto-zeroing CMOS amplifier for biomedical implants

PDF

Variation-aware circuit and chip level power optimization in digital VLSI systems

PDF

Power efficient design of SRAM arrays and optimal design of signal and power distribution networks in VLSI circuits

PDF

Power-efficient biomimetic neural circuits

PDF

An asynchronous resilient circuit template and automated design flow

PDF

Stochastic dynamic power and thermal management techniques for multicore systems

PDF

Low-power, dual sampling-rate, shared-architecture ADC for implantable biomedical systems

PDF

High power, highly efficient millimeter-wave switching power amplifiers for watt-level high-speed silicon transmitters

PDF

CMOS mixed-signal charge-metering stimulus amplifier for biomimetic microelectronic systems

PDF

Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template

PDF

Thermal analysis and multiobjective optimization for three dimensional integrated circuits

PDF

In-situ digital power measurement technique using circuit analysis

PDF

Building blocks for 3D integrated circuits: single crystal compound semiconductor growth and device fabrication on amorphous substrates

PDF

Verification and testing of rapid single-flux-quantum (RSFQ) circuit for certifying logical correctness and performance

PDF

Formal equivalence checking and logic re-synthesis for asynchronous VLSI designs

PDF

Designing efficient algorithms and developing suitable software tools to support logic synthesis of superconducting single flux quantum circuits

PDF

Advanced cell design and reconfigurable circuits for single flux quantum technology

Asset Metadata

Creator Antao, Uldric A. (author)

Core Title Subthreshold circuit design for ultra-low-power sensors

School Andrew and Erna Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 04/19/2016

Defense Date 12/11/2015

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag analog,CMOS,low power,mismatch,OAI-PMH Harvest,process,sensors,subthreshold,temperature,variations,voltage

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Berger, Theodore W. (committee chair), Chen, Mike S. W. (committee member), Parker, Alice C. (committee member)

Creator Email antao.uldric@gmail.com,uantao@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c40-231836

Unique identifier UC11277839

Identifier etd-AntaoUldri-4291.pdf (filename),usctheses-c40-231836 (legacy record id)

Legacy Identifier etd-AntaoUldri-4291.pdf

Dmrecord 231836

Document Type Dissertation

Format application/pdf (imt)

Rights Antao, Uldric A.

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA