Charge-mode analog IC design: a scalable, energy-efficient approach for designing analog circuits in ultra-deep sub-µm all-digital CMOS technologies

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Content CHARGE-MODE ANALOG IC DESIGN A SCALABLE, ENERGY-EFFICIENT APPROACH FOR DESIGNING ANALOG CIRCUITS IN ULTRA-DEEP SUB-µM ALL-DIGITAL CMOS TECHNOLOGIES by Susan M. Schober ______________________________________________________________ A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERISITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2015 Copyright 2015 Susan M. Schober ii Dedication To my beautiful and brilliant daughter, Eva, who is exactly as old as my Ph.D., & my awesome dad, Robert C. Schober, who showed me that math, circuits, and entrepreneurship are fun. iii Acknowledgments This work is the product of my Ph.D. journey through the last 8 incredible years while at USC. As my research evolved, so did I. My thesis includes creative new charge-based approaches which I have spent countless days uncovering and studying that aid in the design of CMOS analog ICs in ultra-deep sub-µm and nanoscale CMOS technologies; it also contains the proof of the value for these charge-mode experimental designs through their fabrication and characterization in silicon. Beyond this, what might not be easily seen in my writing, is the impact of those around me whose imprint on my life shaped these pages. I would not be here at this moment, able to express my thoughts freely if it were not for the encouragement, love, and support of a handful of key individuals who constantly and positively influenced me during this time. Equally, if it were not for those who engaged, challenged, and sometimes even discouraged me, I would not have spent time day-dreaming of innovations and undiscovered avenues beyond traditional IC design to experiment with. First and foremost, I would like to thank my Ph.D. advisor, Professor John Choma, who apparently saw something in me when he asked me to be his doctoral student while I was in my senior undergrad year at USC. John provided me with the unusual liberty to explore and choose my own path for discovering unconventional approaches for next-generation analog IC design. Ever-patient, he taught me how to analyze, compare, and most importantly, how to be confident and believe in my abilities. Choma truly was an amazing advisor, teacher, mentor, and friend. I iv will never forget him or how he encouraged me to be the person I am—for these things I am extremely grateful. There is not a day that goes by that I do not miss being able to talk to him. Due to an unexpected turn of events in the last year of my Ph.D., Professor Edward Maby deserves more than anything to be thanked a million times over for taking over the reins of my doctoral advisement. I find it incredible when looking back and realizing that the wonderful, motorcycle-riding teacher, who first introduced me to analog transistors at USC as an undergrad, later became the remarkable professor who stepped in, took charge, protected and advised me when I needed it the most. Thank you, Professor Maby, for always watching over me. My Ph.D. advisement committee from my qualification all the way to my defense has been nothing less than exceptional. I wish to thank Professors Mike Chen (who served as my Qualification Committee Chair), James Moore, Massoud Pedram, and Sandeep Gupta for their generous time, supportive guidance, and helpful feedback. Thank you for offering me a teaching position literally five minutes after I successfully defended my thesis. I am humbled and honored to be able to follow in Choma’s footsteps and teach his analog circuit design course at USC. There are quite a few professors who have had some of level of impact on my path during my Ph.D. years, from the ever-so-subtle to the uniquely profound, to whom I owe gratitude: Professors Eun Sok Kim (for always smiling and being helpful), Jack Wills (for all of the years of helping to teach me to solder and use the RF test equipment at ISI), Dan Goebel (for being the coolest professor I know), Aluizio Prata (for the antenna class and the trip to Goldstone, which blew my mind), Peter Beerel (for making digital circuits fun and always offering solid advice), Alice Parker (for always having an open door so we could hang out and talk), Ellis Meng (for letting me play in her BME lab developing wireless powering/telemetry biomedical implants), Theodore Berger (for DARPA REMIND support), John Granacki (for all my years of GRAships v at ISI), Hossein Hashemi (for making EE tough so I respect it when it’s simple and easy), Michelle Povinelli (for letting me hold Thanksgiving dinner at her house for all the women Ph.D. EE’s at USC every year and being the first to give me a big hug as I exited my defense), Shri Narayanan (for financial support via MHI and his work in autism), Urbashi Mitra (for being the first person to reach out and make sure I was okay after Choma’s passing), Bindu Madhavan (for making me know all my numbers inside and out so I am ready for anything), Behrokh Khosnevis (for always being supportive of my creativity and pushing me to file my first patent), Tom Katsouleas (for giving me my first paid job at USC), Andrew Viterbi (and his wife who basically funded my senior year at USC with a scholarship), Hans Kuehl (for helping me to choose the path to the Ph.D.), Kian Kaviani (for letting me teach MOS fabrication in USC’s clean lab), Kathleen Allen (See! I am finally graduating! And I have a startup thanks to you!), David Scott (for putting my name on an IC and placing it on Mars—true story), David Harris (thank you for hosting my two wonderful days at HMC), Maria Klawe (you are incredible—I hope to be as strong as you someday), Henry Samueli (for meeting at Broadcom to discuss the CiFET with my team), Asad Abidi (for always happily chatting with my dad and I), Carver Mead (who encouraged me to follow the route of the charge-mode analog IC design approach for CMOS and told me he liked my PLL charge pump circuit), Azita Emami (the most awesome female EE I know), Eric Fossum (for the positive words of encouragement and awe-inspiring stories about my dad), Bob Brodersen (who unknowingly confirmed the importance of my research topic with his talk at USC on next-generation CMOS analog IC design challenges in the early years of my Ph.D.), Thomas Mucciaro (who years ago helped me visualize the electron when I sought out his infamous organic chemistry courses and labs), Christian Enz (including his family and the EE “French Connection” gang—you know who vi you are), and my “brother-in-law” David Allstot (and cousin-in-law, Emily, who has always been fun to visit with every year at ISSCC and ISCAS). Thank you to everyone at USC who was also instrumental in one way or another during my doctoral studies at USC. This includes the EE student office headed by the fabulous Diane Demetras and all of the wonderful people I got to know, worked with, or merely bumped into now and then, sharing a laugh, in the EEB, OHE, and PHE buildings including Shane Goodoff, Tim Boston, Kim Reid, Ramona Gordon, Jaime Zelada, Christina Fontenot, Marilyn Poplawski, Fatemeh Kashfi, Hooman Akhavan, Kristen Pudenz (and her sister), Justin Simmons, Ankush Goel, John Roderick, and Harish Krishnaswamy, Zahra Safarian, Hooman Abediasl, Uldric Antao, Shervin Moloudi, Viviane Ghaderi, Vijay Srinivasan, Suruchi Wagh, Shirin Vakilian, Roya Sheybani, and Nick Wettels. Also, a nod to Aaron Curry, who became a great friend at the tail end of my Ph.D., when we collaborated and won a MOSIS IBM/Global Foundries fabrication proposal together for our research work on the Enigma project. Thank you to USC WiSE, USC MHI, and IEEE CAS for their generous international travel grants and student support. I would also like to thank USC’s Information Sciences Institute (including USC BMES and DARPA REMIND) and MOSIS for the many years of graduate research assistantships where I obtained valuable hands-on experience designing and testing a multitude of ICs over the years for a vast amount of projects in a top-notch facility. Also, thank you to John Sweet and the USC Stevens Center for Innovation for help with my first 2 patents while at USC. Many more thanks to the friends who have been my cheering squad over the years, including my special AOE sisters: Tasha Drew, Judy Hodes, Regidia Mayrena, Nan Chen, Catie Sherry, and Rosemary Frasure; and awesome girlfriends: Jamie Fischer-Granados, Jennifer Chang, vii Nirali Shah, Anna Efremova, Tracy Lewis, Renee Zazueta, Tracy Lewis, Cherri Phan, Erin Hart, Caroline Cazaumayou, and Susie Channels; and great guyfriends: Nick Lalic, Lee Druxman, Nakul Dakar, and Mehdi Yahyanejad. I wish to thank my brainstorming companions Herb Shapiro (who drafted William Shockley’s patents as well as the first practical MOS device at Bell Labs), Romeo Kharileh, Mehran Shahmiri, John Weitzner, and Dan Likins, for introducing me to the possibilities that my inventions could have on the world and for igniting my entrepreneurship passion. Thank you to everyone at InventionShare—including Greg Waite, Keith Taylor, Kensel Tracy, Lesley Gent, Alberto Perez, Kira Baccari, and Taiji Yoshino—and our first company, CircuitSeed, for making my startup dreams a reality through the immense support, patent protection, invaluable industry connections, and required funding. I also wish to thank the many wonderful people who encouraged and taught me new things over the years while interning at Qualcomm, Broadcom, and Scintera—mainly Alireza and Rozi Rofougaran, Shahla Khorram, Seema Anand, Janice Chiu, Yuyu Chang, Patrick Kilcoyne, and Kasim Mahmood. Rio also deserves a bit of praise here too for taking me anywhere I ask him for a quick escape and for never complaining as long as I promise to provide carrots. Thank you to the crazy horse gang for providing me with a place to refresh my mind and let go in between my research. Last, but not least, I want to say thank you to my family: my father, Bob, who has always been there for me, even at 4am when I get some unusual circuit idea and want to discuss it; my mother, Mary, who helped me in more ways I could count, from getting me something special to boost my mood to taking care of my daughter while I was at school trying to complete this degree; to my oldest brother, Bobby, who has always been there to make me laugh by pointing out the humor even in the most messed-up circumstances, visiting me at USC to watch movies in Leonard viii Maltin’s film class, or just being the best uncle ever to my daughter; my brother, Steve, and his family—Kim, Sabrina, and Sammy—for always popping up unexpectedly from Portland, thus getting my brain off working on my research so hard and forcing me to take a much-deserved break to enjoy family and take a bike ride to the beach; my daughter, Eva, who has made me stronger than I have ever been and, more importantly, provides me daily with the smiles and giggles I needed to keep going, to fight on, and to never give up; and my uncle Steve Kanuika, who passed away too soon, but whose inventive and courageous spirit will always be close to my heart. On a final special note, I want to thank Ehsan Pakbaznia along with his kind family. Thank you for your steady love, grounding sanity, brilliant thoughts, brutal honesty, rational encouragement, delicious food, and unwavering commitment. How lucky are we to have met in front of EEB? I will never forget when you asked me what I was studying and I replied “analog ICs” and you said “there was nothing new in analog”. Well, here is something new in analog. Eshghe man—those were some of the best days of my life after meeting you, sharing single malt scotch, eating at Spago, and dreaming of the future. Here’s to being EE in LA—the best city in the world! — Susie ix Abstract The demand for connectivity is expanding at an extremely rapid pace. By year-end 2015, the number of global network connections will exceed two times the world population (i.e. 7 billion), and it is estimated that in 2020 more than 50 billion devices will be wirelessly connected to the cloud forming the Internet of Things (IoT). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last few decades. This was fueled in large part by Moore’s Law, coupled with research and development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) transistors, which facilitated incorporating digital and analog circuit components, such as transceivers, into a single, reliable system-on-chip (SoC). However, in recent years, while digital circuits have largely followed their predicted path and have benefited from the scaling of CMOS into ultra-deep submicron (sub-µm) and nanoscale technologies, analog circuits have failed to follow the same trend. Analog and radio frequency (RF) designers remain to discover how to construct scalable, high-performance integrated circuits (ICs) for feature sizes below 45nm without losing the benefits of shrinking, including reduced power, compact area, and higher operational frequencies. A paradigm shift is the only way to break through the established science of analog design to meet the SoC demands of the next generation. x This work explores the historical trends of analog circuits, discusses present-day challenges, and introduces a novel charge-based approach for designing scalable CMOS analog circuits. The charge-mode perspective ultimately enables analog circuit fabrication in all-digital deep sub-µm IC processes and gives hope to the possibility of analog design flow automation due to its distinctive attributes (i.e. compact, simple digital-like device building blocks with no traditional current mirrors or bulky, threshold-stacked transistors). As a demonstration of the proposed analog design concept, a complete phase-locked loop (PLL) system is designed using specific circuits that have been created using the charge-mode methodology, namely the charge pump (CP), phase-frequency detector (PFD), and voltage controlled oscillator (VCO). Additionally, this dissertation introduces a promising new patented building block, the complementary injection field effect transistor (CiFET) device, to the charge-mode toolbox. The CiFET seminal cell and family of circuits allow for analog functionality, such as amplification, at nanoscale feature sizes and supply voltages far below 1V. All of these analog circuits have been fabricated in 40nm CMOS, physically tested, and compared to the state-of-the-art. The thesis concludes by envisioning the direction of where analog ICs are headed in the not-so-distant future. 1 Table of Contents Dedication ..................................................................................................................................... ii Acknowledgments ....................................................................................................................... iii Abstract ........................................................................................................................................ ix Table of Contents ......................................................................................................................... 1 List of Figures ............................................................................................................................... 3 List of Tables .............................................................................................................................. 13 Chapter 1: Introduction ............................................................................................................ 15 1.1 Organization ..................................................................................................................... 17 Chapter 2: Background ............................................................................................................. 19 2.1 Next-Generation CMOS Analog IC Design: Importance and Challenges ...................... 20 2.2 Vacuum Tubes: The Dominance of Voltage-Mode Circuit Design ................................ 30 2.3 FETs to BJTs: The Prevalence of Current-Mode IC Design ........................................... 37 2.4 CMOS: The Gradual Shift to Charge-Mode IC Design ................................................... 53 Chapter 3: Experimental Analog Phase-Locked Loop .......................................................... 77 3.1 Proposed PLL Charge Pump Designed with Charge Transfer ........................................ 78 3.2 Proposed PLL PFD Designed with Charge/Discharge Path Optimization ...................... 91 3.3 Proposed Voltage Controlled Oscillator Designed with Charge Coupling ................... 102 Chapter 4: Experimental CiFET Analog Building Block .................................................... 114 4.1 Step-by-Step Device Evolution: MOS to Split-Channel iFET to CiFET ...................... 115 4.2 The CiFET as an Analog Building Block ...................................................................... 142 Chapter 5: Conclusion ............................................................................................................. 163 2 Appendix A: C2L Methodology .............................................................................................. 165 Appendix B: CiFFET Analysis ............................................................................................... 174 Appendix C: iFET/CiFET Abstract and Behavioral Models .............................................. 178 Appendix D: Additional CiFET Amplifier Examples and Plots ......................................... 181 Appendix E: Other Useful CiFET Building Block Circuits ................................................. 228 Appendix F: Charge-Mode Insights Regarding the CiFET ................................................. 255 Epilogue .................................................................................................................................... 265 References ................................................................................................................................. 268 3 List of Figures Fig. 2.1 The internet of everything: history and projection of connected wireless and wireline communication devices which require analog combined with digital IC design ........................................................................................................................... 20 Fig. 2.2 The digital CMOS IC scaling trend for commercial Intel processors ............................. 21 Fig. 2.3 Three plots representing technology scaling from CMOS inception to present use with finFET technology: Moore, Dennard, and power supply voltage trends .................. 22 Fig. 2.4 Six plots representing nMOS transistor scaling impact on unity gain frequency, threshold voltage, and on/off drain currents, transconductance/output conductance, intrinsic gain, and oxide thickness. ................................................................................... 23 Fig. 2.5 The evolution of the planar MOSFET to the finFET. ..................................................... 25 Fig. 2.6 Examples of traditional analog IC structures which have difficulty scaling into ultra-deep sub-µm CMOS: current mirrors, inductors, and threshold-stacked transistors. ......................................................................................................................... 27 Fig. 2.7 Circuit and system design mode hierarchy of circuit. ..................................................... 29 Fig. 2.8 Triode symbol, small-signal model, and general I-V characteristics. ............................. 31 Fig. 2.9 Basic single-stage voltage-mode era vacuum tube amplifier configurations. ................. 34 Fig. 2.10 Basic voltage-mode vacuum tube differential LTP amplifier. ...................................... 35 Fig. 2.11 Ideal cross-section of integrated vertical n-p-n and lateral p-n-p bipolar junction transistors fabricated on a p-type substrate. ........................................... 40 Fig. 2.12 n-p-n BJT symbol, basic small-signal model, and IC-VCE characteristics. .................... 41 4 Fig. 2.13 p-n-p BJT symbol, basic small-signal model, and IC-VCE characteristics ..................... 41 Fig. 2.14 The general diode-based Ebers-Moll BJT model. ......................................................... 42 Fig. 2.15 BJT charge profile in the base area operating in the active region for an ideal n-p-n. ................................................................................................................................. 44 Fig. 2.16 Basic single-stage voltage-mode bipolar amplifier configurations adapted from the voltage-mode vacuum tube era amplifier designs. ...................................................... 46 Fig. 2.17 Current-mode seminal cell: the bipolar current mirror. ................................................ 47 Fig. 2.18 Voltage-mode differential pair adaptions with bipolars. ............................................... 49 Fig. 2.19 Current-mode analog cell evolution: from bipolar current mirrors to bipolar differential pair multiplier. ................................................................................................ 50 Fig. 2.20 The primitives of two general-purpose current-mode differential bipolar building block cores. ....................................................................................................................... 52 Fig. 2.21 Ideal cross-section of an integrated planar nMOS (left) and pMOS (right) in a typical CMOS IC process. ................................................................................................ 54 Fig. 2.22 nMOS transistor symbol, general small-signal model, and typical Id-Vds characteristics. ................................................................................................................... 55 Fig. 2.23 pMOS transistor symbol, general small-signal model, and typical Id-Vds characteristics. ................................................................................................................... 55 Fig. 2.24 nMOS cross-sectional view depicting operation regions with channel charge variations. .......................................................................................................................... 58 Fig. 2.25 MOSFET charge in the channel during saturation for an ideal nMOS. ........................ 59 Fig. 2.26 Schematic representation of the oxide capacitances for the nMOS in each region of operation. ...................................................................................................................... 60 Fig. 2.27 Basic adaption of the single-stage voltage-mode amplifier configurations implemented with n-type MOSFETs. ............................................................................... 62 Fig. 2.28 Voltage-mode MOSFET differential pair to inverter evolution from a restive load to an active load and the CMOS inverter with associated function symbols. ................... 63 5 Fig. 2.29 AiD example: Analog Gilbert-cell PD versus analog-in-digital CMOS PFD. .............. 65 Fig. 2.30 Switched capacitor charge transfer example. ................................................................ 66 Fig. 2.31 Switched capacitor building blocks. .............................................................................. 67 Fig. 2.32 Switched capacitor amplifier example. ......................................................................... 68 Fig. 2.33 Sub-threshold exponential region in the MOSEFT Id-Vg curve (log scale). ................. 69 Fig. 2.34 Basic bi-directional charge transfer concept. ................................................................ 71 Fig. 2.35 Basic charge/discharge path example. ........................................................................... 73 Fig. 2.36 Example of basic capacitive charge coupling between signals and phases. ................. 74 Fig. 2.37 Example of channel charge distribution in a MOS device during operation. ............... 75 Fig. 3.1 Block diagram of a state-of-the-art analog charge pump-based PLL. ............................ 78 Fig. 3.2 Switch view diagrams for the proposed and state-of-the-art CPs. .................................. 79 Fig. 3.3 Transistor-level schematics for the proposed and state-of-the-art CPs. .......................... 81 Fig. 3.4 The proposed PLL CP in idle mode. ............................................................................... 82 Fig. 3.5 The proposed PLL CP in pump up mode. ....................................................................... 84 Fig. 3.6 The proposed PLL CP in pump down mode. .................................................................. 86 Fig. 3.7 Simulated plot of the proposed CP output step and phase lock behavior. ...................... 88 Fig. 3.8 Simulated systematic % error between Up and Down currents and VC . ......................... 89 Fig. 3.9 The proposed CP layout (left) and die micrograph (right). ............................................. 90 Fig. 3.10 Silicon measurement of the PLL phase noise and spectrum characteristics. ................ 90 Fig. 3.11 The proposed PFD and a typical state-of-the-art DFF-based PFD. .............................. 93 6 Fig. 3.12 Switch view diagrams for the charge-based and state-of-the-art CPs. .......................... 94 Fig. 3.13 An example of a state-of-the-art DFF used in PFDs. .................................................... 95 Fig. 3.14 The proposed PFD DFF, where D=1 and =2 for no-added delay. ........................... 97 Fig. 3.15 Block diagram of the proposed PFD in a PLL. ............................................................. 98 Fig. 3.16 Example of the PFD Up to Idle mode in the PLL. ........................................................ 99 Fig. 3.17 Example of the PFD Down to Idle mode in the PLL. ................................................. 100 Fig. 3.18 The proposed PFD and DFF layout and die micrograph. ............................................ 101 Fig. 3.19 Proposed capacitively phase-coupled ring VCO concept. .......................................... 104 Fig. 3.20 Building blocks of the proposed expandable ring VCO. ............................................. 106 Fig. 3.21 Single-stage unit for proposed VCO rxs expansion and differential “gyrator” example. .......................................................................................................................... 107 Fig. 3.22 The proposed 4x3 quadrature ring VCO. .................................................................... 109 Fig. 3.23 VC versus VCO output frequency for the Ceq tuning bank. ......................................... 110 Fig. 3.24 Block diagram of the proposed PLL. .......................................................................... 111 Fig. 3.25 Die micrograph of the proposed 4x3 VCO in a PLL. ................................................. 111 Fig. 3.26 Measured phase noise and output spectrum at 28.0GHz. ............................................ 113 Fig. 4.1 Analog MOSFET symbol and planar 3D perspective. .................................................. 116 Fig. 4.2 Channel charge in a MOS device during sub-threshold and saturation regimes. .......... 117 Fig. 4.3 I-V characteristics of the MOS device during sub-threshold and saturation regimes. .. 118 Fig. 4.4 iFET symbol and 3D perspective with split channel and iPort (minimally-sized). ...... 121 Fig. 4.5 Channel charge distribution in the iFET device during biased operation. .................... 123 7 Fig. 4.6 Combined I-V/V-I characteristic views of the iFET device with and without input iPort injection current. .................................................................................................... 127 Fig. 4.7 Top layout view of the generic planar iFET source-to-drain channel ratioing for a) longer drain channel and b) longer source channel. ....................................................... 131 Fig. 4.8 The CiFET seminal cell. ................................................................................................ 132 Fig. 4.9 Biased planar CiFET 3-dimentional (top) and cross sectional (bottom) views. ........... 133 Fig. 4.10 Top layout view of the planar CiFET source-drain channel ratioing for a) longer drain channels and b) longer source channels. ................................................................ 134 Fig. 4.11 Two-finger CMOS inverter circuit. ............................................................................. 135 Fig. 4.12 Mid-biased two-finger CMOS inverter 3-dimentional (top) and cross sectional (bottom) views. ............................................................................................................... 135 Fig. 4.13 Biased single-stage CiFET transresistance amplifier. ................................................. 137 Fig. 4.14 NiPort/PiPort voltages versus source/drain iFET W/L ratios. .................................... 138 Fig. 4.15 Biased single-stage CiFET transresistance amplifier V-I characteristics. .................. 139 Fig. 4.16 CiFET input resistance (real impedance) and transresistance versus W/L ratios. ...... 140 Fig. 4.17 Examples of staged single-ended CiAmp voltage amplifiers. .................................... 142 Fig. 4.18 Miller capacitance augmented by a CiFET. ................................................................ 146 Fig. 4.19 3-Stage CiAmp supply voltage versus voltage gain plot. ........................................... 148 Fig. 4.20 3-Stage CiAmp supply voltage versus frequency plot. ............................................... 149 Fig. 4.21 3-Stage Feed-Forward CiAmp supply voltage versus power consumption. ............... 149 Fig. 4.22 3-Stage feed-forward CiAmp transient plot with input displacement (green-dashed) forcing +/- 1.0V step output (red-solid). ......................................................................... 151 Fig. 4.23 3-Stage feed-forward CiAmp transient plot with input displacement (green-dashed) forcing +/- 1.0µV step output (red-solid)........................................................................ 152 8 Fig. 4.24 Topology of the differential CiTRA/CiTIA. ............................................................... 153 Fig. 4.25 Differential 50 Ω CiTIA input impedance and 100GHz bandwidth for LNA use. ...... 155 Fig. 4.26 Differential 50 Ω CiTIA gain (red-solid), total input (green-dot-dash) and total output (violet-dash) referred noise, with phase (yellow-dot) for 100GHz through ratioing the CiFET. ......................................................................................................... 155 Fig. 4.27 Differential CiTIA input voltage (green) from 20pA into 50 Ω-matched input resistance and output (red) voltage transient plot for small input voltages. ................... 157 Fig. 4.28 Differential CiTIA supply voltage versus gain and frequency plots with 75 Ω input impedance matching (a) over whole range and (b) zoomed in. ............................. 158 Fig. 4.29 Differential CiTRA/CiTIA iPort injection current versus output voltage linear plot through zero. ............................................................................................................ 159 Fig. 4.30 Differential CiTRA/CiTIA iPort additive linearity illustration plot. .......................... 160 Fig. 4.31 Die micrograph of the 0.3mm 2 x 0.3mm 2 40nm CMOS charge-mode research chip containing the PLL and CiFET circuits presented in this thesis. ............................ 162 Fig. A.1 Complementary K-map with grouped Logic 1’s and Logic 0’s. .................................. 166 Fig. A.2 Resulting logic gate constructions for example............................................................ 168 Fig. A.3 Schematics resulting from logic construction. ............................................................. 169 Fig. A.4 String diagrams resulting from the logic schematics. .................................................. 170 Fig. A.5 Stick diagrams resulting from the logic schematics. .................................................... 171 Fig. A.6 Layout resulting from the stick diagrams. .................................................................... 172 Fig. B.1 Simplified input impedance circuit model of CiFET as TIA. ...................................... 175 Fig. B.2 Simplified input resistance small signal model of CiFET as TIA. ............................... 175 Fig. B.3 Frequency response circuit analysis for CiFET as TIA. ............................................... 176 Fig. B.4 Noise analysis for CiFET as TIA.................................................................................. 177 9 Fig. C.1 Various iFET abstractions. ........................................................................................... 178 Fig. C.2 iFET and CiFET self-cascode model. .......................................................................... 179 Fig. C.3 iFET and CiFET behavioral model. ............................................................................. 180 Fig. C.4 CiFET schematic and symbol. ...................................................................................... 180 Fig. D.1 Staging examples for the CiFET amplifiers. ................................................................ 182 Fig. D.2 Charge-mode transmission line receiver with CiFETs. ................................................ 184 Fig. D.3 Self-biasing high speed optical receiver concept with CiFETs. ................................... 184 Fig. D.4 CiTIA dual differential transimpedance antenna pre-amplifier with added gain and filter control inputs. ......................................................................................................... 185 Fig. D.5 3-Stage feed-forward CiAmp supply voltage versus acquisition time. ....................... 186 Fig. D.6 3-Stage CiAmp gain (red-solid), total input (green-dot-dash) and total output (violet-dashed) referred noise, with phase (yellow-dotted). ........................................... 188 Fig. D.7 3-Stage feed-forward CiAmp gain (red-solid), total input (green-dot-dot-dash) and total output (violet-dashed) referred noise, with phase (yellow-dotted). ........................ 188 Fig. D.8 3-Stage feed-forward CiAmp gain over Vdd for nominal and 4-corner IC process parameters. ...................................................................................................................... 189 Fig. D.9 3-Stage feed-forward CiAmp frequency over Vdd for nominal and 4-corner IC process parameters. ......................................................................................................... 190 Fig. D.10 3-Stage feed-forward CiAmp phase margin over Vdd for nominal and 4-corner IC process parameters. ......................................................................................................... 190 Fig. D.11 3-Stage feed-forward CiAmp noise over Vdd for nominal and 4-corner IC process parameters. ...................................................................................................................... 191 Fig. D.12 3-Stage feed-forward CiAmp temperature effect on voltage gain versus supply voltage. ............................................................................................................................ 192 Fig. D.13 3-Stage feed-forward CiAmp temperature effect on frequency bandwidth versus supply voltage. ................................................................................................................ 192 10 Fig. D.14 3-Stage feed-forward CiAmp temperature effect on phase margin versus supply voltage. ............................................................................................................................ 193 Fig. D.15 3-Stage feed-forward CiAmp temperature effect on total input referred noise versus supply voltage. ..................................................................................................... 193 Fig. D.16 Positive (log-log) CiFET composite gain plot. ........................................................... 195 Fig. D.17 Negative bidirectional input (log-log) CiFET composite gain plot. ........................... 196 Fig. D.18 Linear CiFET composite gain plot from continuous bi-directional zero-crossing input current. ................................................................................................................... 197 Fig. D.19 Linear CiFET composite gain plot from wide-range bi-directional input current. .... 198 Fig. D.20 CiFET overdrive plot with curser box indicating linear region. ................................ 199 Fig. D.21 CiAmp correlated double sampling circuit for DC and noise correction. ................. 205 Fig. D.22 CiAmp precision sum or difference circuit. ............................................................... 206 Fig. D.23 CiAmp precision multiply by 2x with ADC half-scale subtraction capability. ......... 206 Fig. D.24 3-Stage feed-forward CiAmp 1V step response settling time and ringout detail. ...... 209 Fig. D.25 3-Stage feed-forward CiAmp 1V step response settling time and ringout schematic example. ......................................................................................................... 209 Fig. D.26 3-Stage feed-forward CiAmp +/- 1V step response output waveform. ...................... 210 Fig. D.27 3-Stage feed-forward CiAmp +/- 1V step response input waveform. ........................ 211 Fig. D.28 3-Stage feed-forward CiAmp step response combined input/output waveforms with a 1.2V voltage supply. ............................................................................................ 212 Fig. D.29 3-Stage feed-forward CiAmp step response combined input/output waveforms with a 800mV voltage supply. ........................................................................................ 213 Fig. D.30 3-Stage feed-forward CiAmp step response combined input/output waveforms with a 300mV voltage supply. ........................................................................................ 214 11 Fig. D.31 3-Stage feed-forward CiAmp +1V pulse ringout detail with 3% overshoot perspective. ..................................................................................................................... 216 Fig. D.32 3-Stage feed-forward CiAmp +1V pulse ringout detail with 10fs input rise time. .... 217 Fig. D.33 3-Stage feed-forward CiAmp +1V pulse ringout detail with initial push-up at 10fs. ............................................................................................................................. 217 Fig. D.34 3-Stage feed-forward CiAmp +1V pulse ringout detail with output controlled by feed-forward inverter to 3.5ps and then with the 3 CiFET high-gain path ..................... 218 Fig. D.35 3-Stage feed-forward CiAmp +1V pulse ringout detail with feed-forward to high-gain slope change at ~3.5ps and 3% overshoot +peak (note: 30.2mV at 482ps). .. 218 Fig. D.36 3-Stage feed-forward CiAmp +1V pulse ringout detail with 3% overshoot of 482ps to first-ring valley (note: -1.32mV at 1.387ns). ................................................... 219 Fig. D.37 3-Stage feed-forward CiAmp +1V pulse ringout detail with first ring valley to second peak (note: +55.7µV at 2.297ns). ....................................................................... 219 Fig. D.38 3-Stage feed-forward CiAmp +1V pulse ringout detail with second peak to second valley (note: -3.072µV at 3.21ns). ...................................................................... 220 Fig. D.39 3-Stage feed-forward CiAmp +1V pulse ringout detail with second valley to third peak (note: -0.566µV at 4.14ns). ............................................................................ 220 Fig. D.40 3-Stage feed-forward CiAmp +1V pulse ringout detail with third peak to steady-state error (note: -0.656µV at 4.5ns) for 1-million-to-1 resolution. .................... 221 Fig. D.41 3-Stage feed-forward CiAmp waveform with 500mV rise time step added to the power supply. .................................................................................................................. 223 Fig. D.42 3-Stage feed-forward CiAmp output perturbation waveform from a 1ps 500mV rise time step added to the power supply. ....................................................................... 224 Fig. D.43 3-Stage feed-forward CiAmp normal (red) and 1ps 500mV power supply input perturbation (blue) waveform comparision. ................................................................... 225 Fig. D.44 dCiTIA baseline gain-bandwidth and noise simulation schematic. ........................... 227 Fig. E.1 CiFET PTAT, CTAT, and analog virtual ground reference topology. ......................... 229 12 Fig. E.2 NiFET PTAT and PiFET CTAT iPort voltages as a function of temperature plot. ..... 230 Fig. E.3 Stacked, self-biased CiFET voltage reference. ............................................................. 231 Fig. E.4 Rail to rail CiFET bypass control VCO. ....................................................................... 232 Fig. E.5 CiFET Schmitt trigger. ................................................................................................. 233 Fig. E.6 CiFET current inverter. ................................................................................................. 234 Fig. E.7 CiFET digital CCML concept. ..................................................................................... 237 Fig. E.8 NiFET as a 4-input iNOR gate (a summing current inverter). ..................................... 238 Fig. E.9 PiFET as a 4-input iNAND logic gate. ........................................................................ 238 Fig. E.10 Ultra-precise full floating 2x differential CiAmp application. .................................. 245 Fig. E.11 Full-floating ultra-precision 2x differential CiAmp waveforms. .............................. 246 Fig. E.12 Charge-mode flash ADC-DAC voltage ladder output waveform. ............................ 248 Fig. E.13 Conventional 4T-pixel focal plane array with readout. ............................................. 250 Fig. E.13 Conventional 4T-pixel focal plane array configured to a CiFET readout. ................ 253 Fig. F.1 Generalized parabolas which describes a FET voltage driven strong inversion operation in the positive plane. ....................................................................................... 256 Fig. F.2 Generalized exponential describing a FET diffusion driven weak inversion operation. ........................................................................................................................ 257 Fig. F.3 Combined exponential (below Vth) and parabola (above Vth) from the MOSFET I-V characteristics. .......................................................................................................... 257 Fig. F.4 Plot representing the MOS exponential region as a straight line on a log scale and the linear region is a straight line on the linear scale. ..................................................... 258 Fig. F.5 Newton’s cradle of collision balls as an analogy of the super-saturated channel conduction ....................................................................................................................... 262 13 List of Tables Table 2.1 General list of CMOS circuit structures that have difficulty scaling to ultra-deep sub-µm processes and examples of scalable alternatives. .......................................... 26 Table 2.2 General attributes of the triode vacuum tube device. ................................................... 36 Table 2.3 Single-stage BJT amplifier example configuration properties. .................................... 46 Table 2.4 Attributes of the bipolar transistor. .............................................................................. 52 Table 2.5 Approximate MOSFET operation region oxide capacitance contribution equations. .................................................................................................................... 60 Table 2.6 General attributes of the MOSFET device. .................................................................. 61 Table 2.7 Approximate single-stage MOSEFT amplifier configuration properties. .................... 62 Table 2.8 Snapshot of important CMOS device and design parameters with charge dependence. ................................................................................................................. 71 Table 3.1 PLL charge pump performance comparison. ............................................................... 91 Table 3.2 DFF-based PFD performance comparison. ................................................................ 101 Table 3.3 Performance of PLLs with DFF-based PFDs............................................................. 101 Table 3.4 Silicon measurements for the proposed VCO configurations. ................................... 112 Table 3.5 Silicon measurements and comparison for the proposed quadrature VCO in a PLL..................................................................................................................... 112 14 Table 3.6 Silicon measurements and comparison for the proposed quadrature PLL. ................ 113 Table 4.1 Various useful conventions for the iFET symbol. ..................................................... 131 Table 4.2 Comparison of the iFET and CiFET attributes to that of other active devices. ......... 141 Table A.1 C 2 L example truth table............................................................................................. 166 Table D.1 Comparison of the 3-stage feed-forward CiFET amplifier precision. ..................... 201 Table D.2 Analog resolution limits when defined as charge on a capacitance. ........................ 207 Table D.3 3-Stage feed-forward CiAmp +1V pulse ringout detail summary of peak and valley timing and peak voltage decay ....................................................................... 221 15 Chapter 1 INTRODUCTION Analog ICs are essential to modern communications, computer hardware, and complex industrial, medical, and automotive equipment. With the increase in complexity of digital circuits and systems, analog designers are being challenged to keep up with essential functions such as high-speed interfaces and wireless systems connecting digital to the real analog world. While digital circuits have benefited from “Moore’s Law” [1] and the shrinking of CMOS technology into ultra-deep submicron, analog circuits have not yet been able to follow the same path. Analog designers remain to discover how to obtain the required performance out of circuits below 45nm without losing the benefits of shrinking: reduced power, compact area, and higher operational frequencies are among those benefits. A paradigm shift is needed to break through the established science of analog design and bring it to the next level. This work introduces a “charge-mode” approach to traditional analog design techniques, using one of the more challenging and ubiquitous analog circuit blocks which is responsible for frequency synthesis, the PLL, and the newly invented, minimally-sized CMOS complementary current/charge injection field effect transistor (CiFET) device. The CiFET may be used as an analog building block to construct a novel family of circuits for applications such as amplification, mixing, and voltage or temperature referencing to demonstrate how analog may be designed in an all-digital process. The charge-mode method substitutes “charge transport within and between 16 devices” for “traditional voltage- and current- mode techniques” to improve dynamics with a more efficient use of energy through novel analog circuit topologies, without the use of large transistors, threshold stacking, or state-of-the-art current mirrors or inductors. An overview, in three associated parts, of a unique, patented design for a multi-GHz analog PLL is offered in this work which utilizes the charge-based design approach. The sections include the design, analysis, and comparison to the state-of-the-art for the following PLL blocks: 1) charge pump (CP), 2) phase frequency detector (PFD), and 3) voltage controlled oscillator (VCO). These are offered as perfect companions in an expandable PLL that has been implemented in an all- digital process for frequencies spanning 0.5-to-30 GHz while providing an array of designer- chosen phases. Nevertheless, these blocks may also be used individually to enhance other PLL and control loop designs. Next, single and differential versions of a CiFET amplifier and associated experimental CiFET circuits are designed, fabricated, and tested to complete the validation of this new device and to promote its usefulness in next-generation deep sub-µm analog CMOS ICs. The advantages of this charged-based analog approach include: fewer transistors, sub-1V supply voltages, reduced surface area, topologies that are amenable to scaling, and new circuits with highly desirable performance tradeoffs. Demonstrated among the proposed PLL benefits are: lower power, lower noise, higher speeds, and an easily reconfigured wide range of frequencies. Low power, a compact topology, and high linear gain at low supply voltages are observed in the proposed CiFET amplifier and experimental circuit configurations. Most importantly, these experimental designs have been fabricated in deep submicron CMOS technologies that are earmarked “for digital applications only”. Because of their digital-like structure, these analog 17 circuits have the potential to be automatically generated, from schematic to physical layout, with industry standard tools via a modified design flow. 1.1 Organization The main objective of this thesis is to introduce, study, develop, and prove the value of the charge-based approach to analog IC design using low cost CMOS processes in order to aid in the enabling of analog in the next-generation low-power deep sub-µm technologies. Chapter 2 provides a background of analog circuit trends while highlighting the current challenges being presented to today’s analog IC designers. Definitions and examples of the historical types of analog design are given from voltage-mode to current-mode while highlighting the importance of the use of CMOS for the future of analog ICs. In this chapter, the charge-mode approach to CMOS IC design is defined and characterized. In the next two following chapters, this work presents four techniques which use charge to dictate and optimize a circuit’s performance; these including 1) charge-transfer, 2) charge coupling, 3) complementary complex logic (C 2 L) optimization for analog-in-digital (AiD) design, and 4) charge manipulation using current injection with the split channel, multi-gate, CiFET device, which can be used as a building block for single and differential amplifiers, oscillators, temperature and voltage references, and even fast, charge-based digital logic. Chapters 3 is dedicated to the design, fabrication, and testing of a PLL which uses the first three examples of charge-mode design in its circuit blocks. The first block to utilize the charge- mode approach, specifically charge-transfer, is the analog charge pump—to date, this is the first time a CP has been designed using a digital-like topology with minimally-sized transistors. Next, a PFD is offered as an ideal mate to the fast switching, precise CP through the use of the special C 2 L K-map technique for its constituent D-flip flops (DFFs). Concluding this chapter is a new 18 design for an expandable capacitively-charge coupled ring VCO. This VCO is described and placed into a PLL with the CP/PFD circuits and fabricated in an all-digital 40nm CMOS process. In Chapter 4, the novel CiFET device, which uses channel charge to increase its performance is presented along with analog circuits that are constructed with the CiFET building blocks. Fabricated and physically tested examples presented in this chapter include multi-stage CiAmps and a transresistance differential amplifier. Most notably, the CiFET device allows for the construction of circuits that have ample gain without using the traditional voltage- and current- mode methods to amplifier design, current-mirrors, or large transistors, thus showing great promise for use in the newest ultra-deep sub-µm CMOS digital technologies. Concluding this dissertation is Chapter 5 where a summary of the tradeoffs and advantages of the charge-mode analog CMOS IC design approach is discussed and future work is suggested. 19 Chapter 2 BACKGROUND This chapter serves as a background for this thesis. First and foremost, this chapter discusses the importance of developing a modern approach and way of thinking for designing analog integrated circuits (ICs) in the newest ultra-deep sub-µm complementary metal oxide semiconductor (CMOS) technologies for use in next-generation devices. An overview of the future challenges facing analog IC designers due to the current limitations of traditional analog circuit design methods is presented while highlighting the origination and cross-process evolution of the seminal analog circuit cells still employed today. The significant historical device trends which ushered in the progressive eras of voltage-, current-, and charge- mode circuit design techniques that occurred over the last 100 years are presented including the triode vacuum tube, bipolar junction transistor (BJT), and metal oxide semiconductor field effect transistor (MOSFET), respectively. The purpose of this chapter is threefold: 1) to aid in the awareness and identification of the various modes of analog circuit design techniques, 2) to provide an understanding of the original uses of commonly-used state-of-the-art analog circuit structures and their shortcomings when designed in the lower double-digit CMOS processes, and 3) to promote the exploration of the unique CMOS charge-based properties and symmetric, complementary device characteristics in order to create new analog circuit topologies which are amenable to scaling in the newest digital processes. 20 2.1 Next-Generation CMOS Analog IC Design: Importance and Challenges The demand for connectivity is expanding at an extremely rapid pace. By this year’s end, the number of global network connections will exceed two times the world population and it is estimated that in 2020 more than 50 billion devices will be wirelessly connected to the cloud forming the Internet of Things (IoT) as is shown in Fig. 2.1 [1]. Enabling this new era are the revolutionary developments in mobile computing and wireless communications that have arisen over the last few decades which were fueled in large part by Moore’s Law coupled with low-cost, sub-µm CMOS process that facilitated incorporating digital and analog circuit components (e.g. transceivers) into a more reliable, single system-on-chip (SoC) for feature sizes below 1um (i.e. sub-µm). Despite the prevalence of digital circuits and systems, analog circuits 1 will always be Fig. 2.1 The internet of everything: history and projection of connected wireless and wireline communication devices which require analog combined with digital IC design [2]. (Source: Business Insider) 1 In this work, radio-frequency (RF) and mixed-signal circuits fall under the category of analog circuits. 21 essential to connect the real analog world to the digital computing domain. Therefore, it is vital for the future of wireless devices which will empower individuals globally, to continue to develop CMOS analog circuit topologies that have the ability to shrink with digital on the same chip—thus increasing SoC reliably and functionality, reducing battery power consumption, and keeping chip costs down. Yet, in more recent years, while digital circuits have largely followed their predicted path and benefited from the scaling of CMOS technology into ultra-deep sub-µm process nodes (as shown in Fig. 2.2), analog circuits have failed to follow the same trend [3]. Traditional approaches to analog circuit design, which can be traced back to older voltage- and current- mode techniques birthed by vacuum-tubes and bipolar devices, produce topologies that are not feasible, nor cost- effective in the newest CMOS process technology nodes. Analog designers remain to discover how to successfully create circuits used for analog functions in feature sizes well below 45nm without losing the benefits of shrinking including reduced power, compact area, larger transconductance, and increased operational frequencies. 2 Fig. 2.2 The digital CMOS IC scaling trend for commercial Intel processors [4]. (Source: Intel) 2 Power is defined generally as a circuit’s total current flowing multiplied by the power supply voltage: . 22 As CMOS technology shrinks gradually year-by-year 3 with each new process node into ultra-deep sub-µm (Fig. 2.3b) due to the push for more integrated digital CMOS transistors on a commercial processor chip (Fig. 2.3a), the power supply voltage has been moving downward below 1V (Fig. 2.3c). The impact of this miniaturization on an individual n-type MOSFET (i.e. nMOS) transistor is higher unity gain frequency 4 , fT, slightly lower threshold voltages, vth, and decreased on/off drain currents, Ion and Ioff 5 , as shown in Fig. 2.4a-c. While higher operational Fig. 2.3 Three plots representing technology scaling from CMOS inception to present use with finFET technology: Moore, Dennard, and power supply voltage trends [5]-[6]. 3 Moore’s Law states that the number of transistors in a processor doubles roughly every 2 years. Dennard’s Law states that as transistors get smaller, their power density stays constant so that the power use stays in proportion with area; both voltage and current scale down with length. Fig. 2.3c includes the planar MOSEFT and the introduction of the ultra-deep sub-µm finFET in this voltage scaling. The supply voltage for planar transistors is saturating to just under 1V; this trend decreases further with the introduction of finFET’s structure. 4 The unity gain frequency (also called transition frequency or gain-bandwidth product), f T , is when the current gain becomes equal to unity, “1”. Eq. (2.39) later in this work give an example on how to solve for the f T of a MOS transistor. As device capacitances also get smaller with each new CMOS process node, the unity gain frequency increases. f T is not to be confused with the lower frequency of operation or cutoff frequency (also called the corner frequency, break frequency, or 3dB point) which generally refers to the point at which the voltage gain of the transfer function, H(jw), falls by -3dB from its highest point, thus defining its bandwidth. Also, if unity gain frequency increases for a CMOS process, it can generally be expected that the operational frequency for a given analog circuit will also increase by a similar factor, given that the circuit components can be scaled and properly biased. 5 The MOSFET transistor drain currents I on and I off are also known as the saturation current, I d-sat , and sub-threshold current, I d-sub . 23 Fig. 2.4 Six plots representing nMOS transistor scaling impact on unity gain frequency, threshold voltage, and on/off drain currents, transconductance/output conductance, intrinsic gain 6 , and oxide thickness. frequencies can broaden possible applications for CMOS transistors, the lowering of the supply voltage below 1V presents a bottleneck to traditional methods of analog design as it limits the stacking of transistors (e.g. threshold stacking) commonly used by traditional analog methods in devices such as amplifiers, oscillators, and mixers. Yet, on a positive point, if a desired analog circuit can successfully be made to work at the newest process nodes, the decreasing values for the “on” current equate to lower power dissipation when that circuit is in use. In Fig. 2.4d, the increasing transconductance, gm, and output conductance 7 , gds, are plotted. State-of-the-art amplifiers are customarily thought of as transconductance-based devices, which rely on the 6 Data from TSMC CMOS technologies was used for all plots with results from MOSIS process monitoring (www.mosis.com) and the foundry. 7 Output conductance is the inverse of drain-to-source resistance of a transistor, r ds . 24 intrinsic gain, Avi, of the MOS transistor which is defined as the ratio of the transconductance to output conductance (i.e. Avi= gm/gds= gmrds). In Fig. 2.4e, the steadily decreasing intrinsic gain alerts analog designers of impending difficulty that they face when attempting to scale the design of an amplifier that may have run efficiently at 65nm or 90nm to the 14nm CMOS process, where it will most likely fail. Therefore, other methodologies which depart from conventional procedures, must be explored in order to find a viable tactic to harness inherent transistor gain in the newer ultra-deep sub-µm CMOS technologies. Finally, in Fig. 2.4f, the steadily decreasing gate oxide thickness, tox, is of importance because it is inversely related oxide capacitance, Cox. The oxide capacitance value is proportional to a transistor’s various device capacitances such as gate-to-source, Cgs, and gate-to-drain, Cgd, both of which are inversely related to the increasing unity gain frequency in Fig. 2.4a. Another major challenge for the scaling of analog circuits, which has arisen more recently, is the physical structural evolution of the MOSFET from the conventional large planar transistor to the gate-wrapped finFET as shown in Fig. 2.5 [8]-[10]. The finFET was developed to provide greater gate control and reduced drain induced barrier lowering (DIBL) of a transistor as the minimum transistor length, L, approaches that of the size of a few silicon (Si) atoms 8 . At smaller process nodes 28nm and below, the finFET device generally comes in one size fits all for width, Weff, and can be placed together in parallel arrays to adjust the sizing by a multiplication factor, n, for each parallel transistor finger. While this translates to desirable near-identical matching 8 A Silicon (Si) atom has a radius of 0.1176 nm. For example, at the 11nm process node, a minimum-sized nMOS transistor has a length, L, of 11nnm, and therefore, has roughly 9-10 atoms of Si across it. Also, the finFET can be considered multi-gate device with inputs on either side or all around. The finFET can be viewed as the combination of 3 channels in one device where there are channels on either sides of the height and at the top part of the width. For simplicity, each of those 3 channels act approximately like one planar transistor of that sizing during operation. 25 Fig. 2.5 The evolution of the planar MOSFET to the finFET. between devices, it also presents difficulty for state-of-the-art analog design methods which require larger widths and/or length typically used to set a particular transconductance for gain or an ample drain current for transistor operation. It defeats the purpose of going for area, cost, and power savings when a relatively massive, analog circuit with limited shrinkage between process nodes is placed on the same die as smaller, scaled-down digital circuits. This scaling issue also holds true for the limited portability of inductors used in the lower GHz frequency ranges (e.g. 0.9- 5GHz) utilized in analog circuits such as RF amplifiers, filters, and oscillators [7], [11], [17]. Additionally, inductors with respectable quality factors, Q, must have additional special process considerations and layers, which are not available in the newest standard digital CMOS technologies. 9 9 Analog/RF designers have enjoyed approximately two decades of availability of on-chip CMOS IC inductors [12]-[14]. These inductors generally are used for bandwidth enhancement in a wide range of frequencies from around 900MHz to 1 THz range for process nodes starting at 1- 2µm all the way down to 45nm. In the newest CMOS technology nodes 28nm and below, analog designers are realizing that they must abandon the use of on large IC inductors in favor or other techniques [15], [18]. This is because IC inductors have very limited scalability on-chip as their inductance is inversely proportional to the size of the component. For instance, if an inductor size is halved, its resonance frequency roughly doubles. 26 Difficult to Scale Analog Structures Scalable Alternatives for Analog Circuits Planar transistors Inductors LC oscillators Traditional current mirrors and sources Threshold-stacked transistors State-of-the-art amplifiers Slow, bulky analog switches Voltage and current-mode circuits finFETs Capacitors Inverter-based ring oscillators Adaptive and self-biasing Analog-in-digital and digitally-assisted circuits Sub-threshold designs Minimally-sized transistor switches Charge-sharing and transfer Table 2.1 General list of CMOS circuit structures that have difficulty scaling to ultra-deep sub-µm processes and examples of scalable alternatives. Table 2.1 provides a list of examples of analog structures which have difficulty scaling to CMOS technologies at 28nm and below. This table also gives a very basic list of scalable alternatives for designing analog ICs. This relationship is due to the reactance, X, component of the passive device’s impedance, Z: . The reactance of an inductor is equal to 2 , while it is for a capacitor, where the resonant frequency is equal to 2 . In both cases, a higher frequency calls for the use of smaller capacitors and inductors. While IC designers have a wide variety of ways to implement and layout a large variety of capacitances with available CMOS process layers and devices (e.g. MOS varactor, metal-insulator-metal (MIM), poly-diffusion, etc.), on-chip inductor design options is much more limited due to metal layers (type of metal and number of layers), rule-allowed geometry (square versus circular, width, and spacing), use of bond-wire, and shielding [16]. Furthermore, the figure-of-merit (FOM) or quality factor, Q, of an inductor, can suffer due to parasitic resistances that alter the value of R, which ideally is zero at resonance. The quality factor of a passive component, such as a capacitor or inductor, is equal to the frequency multiplied by the ratio of the energy stored in the component divided by the average power dissipated (i.e. the amount of energy lost per unit time): . For an inductor, , and for a capacitor, , while where I pk and V pk is known as the peak current and voltage, respectively. For an inductor, , and for a capacitor, . Note that for the inductor, the quality factor increases with frequency and inductance value (which is proportional to its size), but decreases due to parasitic resistance. On the other hand, on-chip capacitance is inversely proportional to the insulator thickness of the oxide, t ox , which decreases for each smaller process node, thus the quality factor improves slightly with scaling. Therefore, there is restricted ability to scale inductors between process nodes as easily as is done with capacitors [17]. For example, an IC inductor used at a certain frequency, such as 2.4GHz, in 65nm will barely change size when scaled down to 28nm, resulting in a large area being consumed by the component, in order to obtain a respectable quality factor for a given frequency. 27 Fig. 2.6 depicts examples of analog circuit topologies which have difficulty scaling to ultra- deep sub-µm CMOS processes. The simple current mirrors utilized for on-chip biasing in Fig. 2.6a require relatively large planar analog transistors to flow current while continuously consuming power; the oscillator in Fig. 2.6b requires large-bulky inductors which do not shrink to newer CMOS technologies; the amplifier in Fig. 2.6c has limited scalability below 1V due threshold stacking requirements for normal operation. Interestingly, each of these analog circuit examples have topologies which can be traced back to techniques which were established by older vacuum-tube voltage-mode and bipolar current-mode approaches. Understanding the origins and underlying purpose of the basic analog structures and how they adapted over time to CMOS technologies reveals insight as to why they were initially created, their limitations, and how a new way of thinking which exploits the charge-based device properties Fig. 2.6 Examples of traditional analog IC structures which have difficulty scaling into ultra-deep sub-µm CMOS: current mirrors, inductors, and threshold-stacked transistors. 28 of the CMOS transistor is necessary to bring analog IC design to the next-generation of devices [19]. Doing so allows for the creation of novel charge-mode structures for a charge-sharing PLL charge pump, reconfigurable multi-GHz ring oscillator, and high-gain trans-resistance amplifiers described in Chapters 3 and 4 of this thesis. Each of these novel circuits are amenable to scaling, operate at supply voltages <1V with good performance, do not use state-of-the-art current-mirrors for biasing, are truly low power, and have the compactness and speed of digital circuits. The approach for creating these novel analog circuits was first to recognize that state-of-the-art CMOS analog circuit design has evolved from older voltage- and current- mode schemes, and that these methods—although they worked efficiently for technologies above 45nm—are not optimized for the unique charge-based properties of the MOSEFT. The next steps explore ways in which the charge-mode characteristics of the CMOS transistor can be combined with the scalable alternatives on the right of Table 2.1. One of the most important steps in this process is to observe that at any moment in time voltage as charge is being held within or between devices and current as the movement of charge is within or between devices. Voltage and current still do exist and are equally important for a circuit’s design, but the designer’s viewpoint is momentarily switched in order to exploit CMOS technology’s most desirable attribute: the precise control of charge. This is possible with electric theory and the idea that energy has the ability to take on a variety of forms which are useful on multiple levels. Electrical circuit theory itself involves the transformation/conversion, control, storage, transmission, and utilization of energy in a large assortment of forms which has a foundation in the Law of the Conservation of Energy 10 . Therefore, passing from one mode to another mode 10 The Law of Conservation of Energy states that the total energy of an isolated system remains constant—it is said to be conserved over time. Energy can be neither created nor be destroyed, but it transforms from one form to another. Examples of various modes of design can be found 29 gives designers another view of a device, circuit, or systems operation which may reveal new information about the topology and be used as an advantage. The term for passing from one mode to another and mixing mode techniques has been termed “free-mode” design [20]. Fig. 2.7 is an illustrative chart of the various modes of design which a device, circuit, or electrical system can be viewed in, and where charge-mode design is situated in context to these approaches. For example, vacuum-tube design was responsible for the original voltage-mode approach which gave birth to many of the voltage amplifier structures still used today while bipolar transistors produced current- mode design which allowed for the first ICs to be biased on chip with the use of the current-mirror. In the next three sections, we take a look at the most influential active devices in the last century and the circuit design trends they produced: voltage-mode vacuum tubes, current- mode BJTs, and charge-mode CMOS. Fig. 2.7 Circuit and system design mode hierarchy of circuit. 11 throughout Chapter 2. Other examples of the Law of Conservation of Energy which are useful for circuits include KVL, KCL, and Conservation of Charge. 11 SNR stands for “Signal to Noise Ratio” and it is a measure of the signal strength compared to the background noise. 30 2.2 Vacuum Tubes: The Dominance of Voltage-Mode Circuit Design The turn of the 20 th century in the United States saw many extraordinary technological advancements and discoveries, including radio transmissions, electronic devices—most notably the vacuum tube, which would be utilized in the first digital programmable computers, and new uses for semiconductors—such as p-n junctions and light-emitting diodes (LEDs). By mid-century till today, with the discovery of the Nobel-prize winning “transistor-effect” in 1947 at Bell Labs by John Bardeen, Walter Brattain, and William Shockley, solid-state devices have come to rule supreme due to their lower cost, power, performance, size, reliability, and scalability when compared to vacuum-tube predecessors. A variety of transistor flavors have been developed and implemented over the years for a variety of both digital and analog purposes, from field effect transistors (FETs) to BJTs, each with their own structure and set of design techniques and tradeoffs. Largely, analog devices generally follow and are subjected to digital trends, such as the pervasiveness of low-cost CMOS, where the evolution of computers, and more recently, mobile devices, has been a driving force for innovation in the past decades. Patented in 1907 by Lee de Forest, the triode vacuum tube was the original electronic device capable of amplification—an essential function of analog circuit design [22]-[24]. This innovation had roots in the “Edison Effect” work published by John Ambrose Fleming over a decade earlier. Nevertheless, the vacuum tube, which controlled electric current through a vacuum in a sealed container and could be used as a switch, went on to be the chief circuit design component until the widespread use of lower-power, cheaper, less fragile and more reliable commercial solid-state electronics in the 1950’s. This era of vacuum-tube design was characterized by voltage-dependent circuit parametrics. Thus, the analog circuit-design technique associated with this type of approach is commonly referred to as “voltage-mode” design which, at 31 that time, was characterized by the use of large supply-voltage values, minimal current flows, huge voltage gains, low-frequency operation, and high direct-current (DC) power consumption 12 [23]. A working definition for a voltage-mode design approach is one in which the key variables used to describe the circuit or system are primarily in the form of voltage, V [20]. Current, I, is generally considered an “incidental” design variable in this approach. The voltage-mode approach allows for a circuit to be optimized for voltage features, the most important of which is voltage gain. The dominant signal representation initially being in the form of voltage historically has been attributed to two reasons, the first, historical/sentimental, and the second due to simplicity: 1) the triode vacuum tube’s voltage-dependent structure and foundational circuit implementations and 2) the ease of taking voltage measurements by hand without having to break the circuit when on the test bench. To better understand the triode vacuum tube’s voltage-dependent structure for the first historical reason, both the model and a typical amplifier example are given. In Fig. 2.8, the triode device’s symbol, small-signal model, and I-V characteristics are shown. Fig. 2.8 Triode symbol, small-signal model 13 , and general I-V characteristics. 12 Typical values for voltage-mode design in the vacuum tube era include: supply voltage of V dd ~ 250 V; current flows of I P ~ 1 mA range, voltage gains per stage of A v ~ 30-40 dB, frequencies in the f ~ 1 Hz - 100 kHz range, and power consumption in the ~ Watt range. There do exist specialty valves used for RF power amplifiers which can reach much higher frequencies up into the low GHz range. Note that a human with pristine hearing has a range within 20 Hz to 20 kHz. 13 Analog circuits generally operate with small signal levels (as compared to the circuit’s larger bias or “DC” currents and voltages), therefore the “small-signal” or “incremental” model of a device can be utilized to allow the calculation of the circuit’s gain and impedances without the use 32 The triode has three input/output (I/O) terminals: grid, cathode, and plate/anode. It can be naturally classified as a voltage-controlled voltage source (VCVS) device where the input grid voltage, Vg, modulates the plate voltage, Vp, and where the relatively minimal plate current, Ip, is immediately converted to voltage by the plate resistance, rp. The general I-V characteristic equation, which follows the 3/2 power relationship, describes the general behavior of the triode vacuum tube 14 : , (2.1) where VGK and VPK are the grid-to-cathode and plate-to-cathode voltages, respectively, µv is the unit-less and nearly constant voltage amplification factor of the triode, and Kv is the geometry- dependent triode perveance constant [23]: 32 81 , (2.2) where d is the distance from the cathode to the plate, ε 0 is the permittivity of free space (8.85×10 -12 F/m), q is the electron charge (1.602×10 -19 C), and me is the electron mass (~9.11×10 −31 kg). Although the plate current is relatively small compared to the large output voltage, the triode can be still viewed from a transconductance, gm, standpoint, where voltage controls or modulates the minuscule current. This transconductance is similar to that of the nMOS device invented and developed years later from 1959 to 1963 [25]-[27], which will be discussed later in this chapter. Therefore, if desired, the triode can be compared to other active devices’ small signal models via the relationships between rp, gm, and µv: of the bias values. For large signals capital letters for variables are used, for example, I C or V BE , and for small signals, lower case letters are generally used, such as i c or v be . 14 When V G + V P > 0. Also, typical values for µ v is ~ 10-100. 33 2 3 ∆ ∆ (2.3) ∆ ∆ ↔ ∆ ∆ . (2.4) The most interesting result from glancing at Eqs. (2.1), (2.3), and (2.4) is that the triode’s I-V characteristics, gm, and rp are all depend on the voltage ratio amplification factor, µv—thus highlighting the underlying voltage-mode VCVS properties of the triode vacuum tube device. The first building-block single-stage voltage amplification configurations included the common-cathode, common-anode, and common grid variations shown in Fig. 2.9. For example, in the common-cathode voltage amplifier circuit depicted in Fig. 2.9a, it is the grid voltage, VG, with its near-zero current, that modulates the small anode current, IP; this anode current is then immediately converted back to a large voltage at the output by the load. Thus, a relatively small grid-to-cathode voltage change can cause a relatively large voltage change across the plate resistor. The three triode amplifier configurations all produce a voltage gain, Av, which can be solved by finding 15 : . (2.5) For instance, using Eq. (2.5), the common-cathode single-stage amplifier has a 180 ⁰ phase inverting voltage gain of 16 : 1 ′ ′ ′ (2.6) 15 Also, to convert from linear gain to gain in decibels: 20 lo g . 16 For simplicity in Eqs. (2.6) and (2.7) allow || ; || ; and for low frequencies ( is included at higher frequencies for and includes the Miller capacitances of the triode model). 34 Fig. 2.9 Basic single-stage voltage-mode era vacuum tube amplifier configurations. where Eq. (2.4) can be used to switch between the voltage-mode variable, µv , to the small signal transconductance variable, gm, as desired for comparing device models. Furthermore, there is also a power gain as a consequence of mode transformation from voltage to power [22] 17 : . (2.7) This is an illustration of a mode-transformation where we take a device, circuit, or system description from one mode, in this case voltage-mode in Eq. (2.6), and convert it to another mode, such as power-mode as in Eq. (2.7), where the design may be further optimized for power gain characteristics if preferred. Other seminal cells, which were invented during the voltage-mode era, include the phase- inverting differential pair 18 (also useful as an inverter), vertically-stacked cascode and 17 To change from linear to decibels for power gain use: 10 log . 18 The vacuum tube differential pair was also known as a phase splitter, Schmitt phase inverter, and a long-tailed pair (LTP) (due to the long resistors required to produce current connecting to the tube cathodes). The differential pair could also be used as a logic inverter for digital applications due to the phase inversion of 180⁰ degrees of each output with respect to each other. [35]-[37] 35 horizontally-stacked cascade amplifiers, various classes of power amplifiers (PAs), LC (inductor- capacitor) oscillators such as Hartley and Colpitts, and logic circuits 19 (e.g. AND, OR, adders, etc.), which made the first computers possible [28]-[39] 20 . For example, the voltage-mode differential LTP pair in Fig. 2.10 allowed for higher gain, improved linearity, and better noise immunity to noise coupling as compared to the single-ended amplifier counterparts; its voltage gain, Av, may be found by calculating: . (2.8) The vacuum tube amplifiers, oscillators, and logic circuit examples of this generation all depict the characteristics of typical voltage-mode design of this era: VCVS circuits with a relatively large voltage gain, currents within the circuit that were generally of a secondary concern, Fig. 2.10 Basic voltage-mode vacuum tube differential LTP amplifier. 19 Boolean logic created with vacuum tubes was called vacuum tube logic (VTL). [24]-[27] 20 The first electronic general purpose programmable computer made in the early 1940’s at the University of Pennsylvania was called ENIAC (Electronic Numerical Integrator And Computer) and functioned with IBM punch card input/output. It utilized thousands of vacuum tubes in its design, occupied ~167 m 2 , and consumed 150 kW of power. It had low reliability, as many vacuum tubes burnt out and had to be replaced each day. Also, the basic machine cycle had 200 µs per cycle. [35]-[39] 36 and, finally, the ease at which one can find the voltages at any node within the circuit via probing. A summary of the attributes of the stand-alone triode vacuum tube device with the input at the grid and the output at the plate may be found in Table 2.2. This brings us to the second reason as to why voltage-mode design was the first natural approach to solving analog circuits in the discrete vacuum-tube era: in order to evaluate an accurate voltage at any node, one does not have to break a circuit branch, and one can simply apply a voltmeter (or multimeter set to voltage) to the node of interest. With this notion, Kirchhoff’s voltage law (KVL) could be used for implementing and solving for voltages in this type of circuit by hand. Consequently, to measure a current within any circuit, a break in a branch would have to occur and an ammeter (or multimeter set to amperes) would have to be inserted between the two broken nodes, which takes a little more effort. In this case, Kirchhoff’s current law (KCL) could be utilized to solve for the currents manually if so desired, although in voltage-mode vacuum tube circuits the currents generally are of a secondary concern. Triodes, even with their reliability issues, were a straightforward discrete device to work with and build multistage vacuum tube amplifiers: they could easily drive other compatible circuits while maintaining their large magnitudes. It was for these historical reasons that this type of voltage-mode design was established and readily used for a little more than half a century until the introduction of solid-state devices and the dual—current-mode analog design—was found to be valuable in making new lower power, higher performance topologies with bipolar transistors. Device Innate Control /Source Primary Design Technique Classification Secondary Circuit Design Techniques Employed Input Impedance (Rin) Output Impedance (Rout) Governing I-V Relationship Voltage Gain Factor Triode Vacuum Tube VCVS Voltage-Mode Power-Mode, Voltage-Mode High Low 3/2 Power µ v [unitless] Table 2.2 General attributes of the triode vacuum tube device. 37 2.3 FETs to BJTs: The Prevalence of Current-Mode IC Design There are 3 vital historical inventions which fueled the jump from bulky, discrete vacuum tubes of yesteryear to the development of compact, monolithic ICs: 1) solid-state devices 21 , 2) the transistor 22 , and 3) integrated circuits 23 . Analog circuits evolved during this time and at the peak of this era, a new design style coined “current-mode” design precipitated which allowed for substantial amplification at higher operational frequencies in one compact chip with a lower power dissipation. The first solid-state device can be traced back to 1901 with the “cat whisker” radio receiver which had a fine wire that moved across a solid galena (lead sulfide) crystal, but unfortunately this type of detector could not amplify a signal [40]. Half a world away in Russia in 1922, Oleg Losev tinkered with the use of LEDs as 2-terminal negative resistance solid-state amplifiers and oscillators for use in his RF receiver experiments due to the overwhelming cost of vacuum tubes in Russia, but his inventions never made it out of the country [23]. Applying the idea of the 3 terminal control grid structure of vacuum tubes, R. W. Pohl demonstrated a solid-state amplifier which displayed nominal gain at extremely low frequencies of about 1 Hz (i.e. 1 cycle per second) in 1938 [41]. With each of these gradual developments it became apparent that a new, more compact solid-state device which could amplify at higher, more useful radio frequencies 24 needed to be discovered for the future of wireless communications. 21 A solid-state device is one in which electricity flows through semiconductor crystals rather than through vacuum tubes. 22 The transistor is a semiconductor device with at least 3 terminals used to amplify or switch electronic signals or power; it is a fundamental building block of modern electronics. 23 An IC or “chip” is an electronic circuit (or circuits) fabricated on one plate of semiconductor material. 24 RF frequencies generally refer to the wide 3kHz to 300GHz+ range. 38 Although impractical in initial designs, the first FET-like structure was described and patented by Julius Edgar Lilienfeld in 1926; he failed though at actually constructing a working design due to the complexities of the copper-oxide materials utilized [42]. Research into other semiconductor materials, lead to the first p-n junction experiments in silicon (Si), where in 1941 at Bell Labs, Russel Ohl noticed that a voltage was produced at the boundary between the n-type and p-type doped Si 25 when the experimental device was exposed to light [43]. William Shockley's conception of the junction-gate FET (JFET) in 1947 which could modulate conductivity 26 in a semiconductor was derived from this p-n junction research and his previous efforts with copper- oxide and later, germanium (Ge), in trying to make a working FET. While attempting to make the JEFT a feasible device through diagnosing its shortcomings, Bardeen and Brattain, under the direction of Shockley, serendipitously invented the n-p-n transistor (i.e. BJT) which had the ability to amplify a signal at frequencies used for radio communications and could also be used as a current-controlled current source (CCCS) switch [44]-[46]. It would take another decade for the n-p-n transistor (and later the complementary p-n-p transistor) to be placed in the first integrated circuit while the FET concept would later be applied to make the ubiquitous MOSFET, which we shall talk about in the next section. In 1958, Jack Kilby at Texas Instruments designed 3 oscillators using bipolar transistors and integrated, for the first time, these analog circuits onto a slab of germanium—for this monumental achievement he co-won the 2000 Nobel Prize in Physics for this revolutionary miniaturization technology which allowed active devices to be made on the same material as 25 In n-type Si, the negative electrons are the majority carriers and in p-type Si, the positive holes are the majority carriers. 26 Conductivity, σ, is the ratio of the magnitude of current density, J, to the magnitude of the electric field, E; therefore, σ = J / E; also conductivity is the reciprocal of resistivity, ρ. J is in units of [A ⋅m −2 ], E is in [V ⋅m −1 ], and ρ is in [ Ω ⋅m]. 39 capacitors and resistors [47]. Today, a designer has the choice of a variety of semiconductor materials to make BJT circuits with, including inexpensive Si and higher performance, compound 27 semiconductors such as SiGe, (silicon germanium), GaAs (gallium arsenide), GaN (gallium nitride), and InP (indium phosphide)—each with their own tradeoffs 28 . Also, n-p-n BJTs tend to be much more popular than the complementary p-n-p BJTs due to their higher transconductance and electron mobility, un, resulting in the completive edge regarding performance. 29 By the early 1960’s, a lateral p-n-p was able to be fabricated on the same p-type substrate as the vertical n-p-n, depicted in the ideal BJT cross-section shown Fig. 2.11, but the complementary devices were asymmetrical and therefore had differing, unmatched properties. Despite this, the BJT could be used as a switch in addition to an amplification device; this was generally done with the n-p-n as using the p-n-p as a switch was undesirable due to the slower recombination from the diodes between the base width, Wb-p, for the collector (p-type) to base (n- type) to emitter (p-type) transition, as compared to the shorter width of the of the base, Wb-n, for the complement n-p-n transistor. For analog and RF devices, utilizing the p-n-p generally 27 Compound semiconductors are composed of elements from 2 or more different groups (e.g. binary, ternary, etc.) on the periodic table, typically groups 13-15. 28 There are tradeoffs between the use of various semiconductors which is dependent on their crystalline structure’s voltage bandgap. For instance, GaAs with a wide bandgap of 1.4eV provides higher gain, f T (unity-gain frequency; where the gain of the device becomes one; an indicator used to evaluate the operation frequencies of a device), and reliable operation at high temperatures, but the processes is much costlier than Si, which has a bandgap of 1.1eV, which is available in a variety of feature sizes and cheap in comparison. 29 The term bipolar refers to the fact that both electrons and holes are involved in the operation of a BJT. Minority carrier diffusion plays the leading role just as in the p-n junction diode. A n-p-n BJT is made of a heavily doped n+ emitter, a p-type base, and an n+ type collector. On the other hand, a p-n-p BJT has a p+ emitter, n-type base, and p-type collector. In a p-type substrate, the vertical n-p-n bipolar transistors exhibit higher transconductance and speed than lateral p-n-p transistors because the electron mobility, u e , is larger than the hole mobility, u h , and also the travel a shorter distance (Wb n-p-n vs Wb p-n-p ) of the base area. BJTs are almost exclusively of the n-p-n type (as opposed to p-n-p) since high performance is BJTs’ competitive edge over today’s MOSFETs, basically this is the main reason they are utilized in RFIC design today. 40 Fig. 2.11 Ideal cross-section of integrated vertical n-p-n and lateral p-n-p bipolar junction transistors fabricated on a p-type substrate. translates to lower frequency operation for RF devices and lower current gain as compared to n-p- n, yet the same general models may be used for both the n-p-n and the p-n-p, with the polarities reversed. The BJT symbols, simple small-signal models, 30 and general I-V characteristics are shown in Figs. 2.12 and 2.13 for both devices, respectively, in the active, saturation, and cutoff regions. Similar to the vacuum tube, we can find the bipolar transistor’s transconductance, which is useful for small signal model comparison between devices: , (2.9) where IC is the collector current at the Q-point 31 and VT is the thermal voltage: , (2.10) where k is the Boltzmann’s constant (1.3806488x10 -23 J/K) and T (in K) is the temperature. 32 30 More developed models, such as the Gummel-Poon charge-control bipolar model, developed at Bell Labs in the 1970’s, are used for simulation and characterization [48]. 31 The operating point of a device, also known as bias point, quiescent point, or Q-point, is the steady-state voltage or current at a specified terminal of an active device (i.e. a transistor or vacuum tube) with no input signal applied. For example, the Q-point is displayed in Fig. 2.12. 32 25.9 at room temperature, T=300K. 41 Fig. 2.12 n-p-n BJT symbol, basic small-signal model, and IC-VCE characteristics 33 . Fig. 2.13 p-n-p BJT symbol, basic small-signal model, and IC-VCE characteristics. The BJT is heavily dependent on diodes that form at each p-n junction, for instance, between the n-p-n for the emitter, base, and collector. Hence, the diode-based large signal Ebers- 33 In the BJT I-V characteristic plot, the positive I c vs V ce characteristics are shown for simplicity. There is however an inverse (or reverse) active region that exists using the negative I c vs V ce characteristics [49] which is not shown. There are 4 distinct modes of operation for the BJT including active, saturation, cutoff, and reverse active. The operating regions for the n-p-n transistor can be described in terms of the applied voltages (reverse for p-n-n transistors) using the general Ebers-Moll large signal model equations. For instance, active region has V E <V B <V C , saturation is V E <V B >V C , cutoff is V E >V B <V C , and reverse active is when V E >V B >V C . A simple chart depicting these regions: 42 Moll mathematical model shown in Fig. 2.14 is typically used to describe BJTs in all operating regions. The CCCS physical structure and resulting Ebers-Moll mathematical model, initially formulated in 1954 for n-p-n and p-n-p BJTs, naturally allows for the use of KCL, which is technically a current-mode technique due to the use of the state variables being described in terms of current via the summing of currents for the BJT: , (2.11) where IB and IE are the bipolar transistor’s base and emitter currents, respectively. A working definition for a current-mode design approach is one in which the state variables used to describe the circuit or system are primarily in the form of current, I, whereas voltage, V, is generally considered an incidental design variable in this approach [20]. This can be viewed as the dual of the voltage-mode approach previously discussed. For instance, to show the typical dependence of a bipolar device’s variables on current descriptions, the collector and emitter currents of the n-p-n BJT may be described for any operating point by the following equations via the Ebers-Moll diode-based model [49]: 1 1, (2.12) 1 1, (2.13) Fig. 2.14 The general diode-based Ebers-Moll BJT model. 43 where VBE and VBC is the base-to-emitter and base-to-collector voltage, respectively, IS the reverse saturation current 34 : , (2.14) where IES and ICS are emitter and collector saturation constants, respectively, A is the area of the base-emitter junction, ni is the intrinsic carrier concentration, NA is the dopant density of the p- type atoms in the base, DN is the diffusing constant of electrons in the p-side of the junction which is simply equal to the electron mobility multiplied by the thermal voltage (i.e. DN = µn·VT) and αF and αR are the forward and reverse common base current gain, respectively, where αF can be found by the current ratio: 1 , (2.15) and βF is the common emitter or forward current gain which may be found by the current ratio for this CCCS device: → . (2.16) In these equations VBC and VBE are viewed as “incidental” variables while the focus of describing the BJT is mainly in current form. Collector current is controlled by the base current linearly via Eq. (2.16) and alternatively collector current can be viewed as being controlled by base-emitter voltage exponentially via Eq. (2.12). Eq. (2.12) may be used for calculating the collector current in the n-p-n bipolar’s forward active region as: 34 Typically I S between ~10 −15 to 10 −12 A; 0.9 ; 0.7 , 2 0 500 , µ n ~ 0.05 m 2 /V·s, µ n ~ 0.02 m 2 /V·s,and n i =1.1 x 10 16 carriers/m 3 at a room temperature, T=300 K. 44 . (2.17) Eq. (2.17) combined with an understanding of the cross-sectional BJT view in Fig. 2.11 may be used to get a better picture of why the lateral p-n-p transistor is much slower than the vertical n-p- n. To do this, we can change from the current-mode view to a charge-mode view of the collector current as: ∆ . (2.18) This is another example of mode transformation, from current to a deeper layer, charge, Q. Using Eq. (2.17) we find the total charge depicted in Fig. 2.15 in the p-type base of the n-p-n transistor as: 2 , (2.19) while the transit time thru the p-type base of the n-p-n transistor is found to be: ∆ 2 . (2.20) Similar Eqs. to (2.19) and (2.20) for the charge and transit time may be found for the complementary p-n-p bipolar transistor. Comparing the transit times through the vertical p-type Fig. 2.15 BJT charge profile in the base area operating in the active region for an ideal n-p-n. 45 base of the n-p-n to the lateral n-type base of the n-p-n transistor we can see that the n-p-n bipolar is much faster than the p-n-p: ∆ 2 ≪∆ 2 , (2.21) due to the base widths for the lateral Wb (p-n-p) >> vertical Wb (n-p-n) and applying the knowledge that the electron mobility, µn, is ~2.5 times that of the hole mobility, µp 35 . Hence, looking into the charge-mode view of the BJT has given us insight as to why n-p-n transistors are much more popular as high performance analog devices as compared to their unsymmetrical p-n-p transistors complements. The first amplifiers built from n-p-n BJTs largely followed the same voltage-mode methods which originated from vacuum tube analog design 36 . For instance, the common-cathode amplifier in Fig. 2.9a became the common-emitter amplifier in Fig. 2.16a when a discrete n-p-n BJT, such as the still-widely available packaged 2N2222 initially developed by Motorola in 1962 37 , was simply substituted for the triode vacuum tube with the value of the capacitors and resistors adjusted to obtain desired voltage gain and desired operating frequency range. Table 2.3 provides properties for these single-stage amplifiers. 35 Example of the electron and hole mobility differences: 36 The p-n-p bipolar could also be used in the same amplifier configurations, but it was not as desirable due to the lower performance reasons mentioned previously. 37 The general purpose discrete 2N2222 n-p-n BJT is commonly used in electronics lab courses at universities. Texas Instruments and Fairchild Semiconductors still manufacture this part. [55] 46 Fig. 2.16 Basic single-stage voltage-mode bipolar amplifier configurations adapted from the voltage-mode vacuum tube era amplifier designs. Amplifier Configuration Input-to- Output Phase Relationship Voltage Gain Current Gain Input Impedance Ω Output Impedance Ω Eqs. Common Emitter 180⁰ (Moderate-High) (Moderate-High) (Moderate) (Moderate-High) (2.22) Common Collector 0⁰ 1 1 (Low) 1 (Moderate-High) 1 (High) 1 (Low) (2.23) Common Base 0⁰ (Moderate-High) 1 (Low) 1 (Low) (Moderate-High) (2.24) Table 2.3 Single-stage BJT amplifier example configuration properties 38 . It was not until the advent of ICs and their eventual expansion that there arose a need to find new ways to bias analog circuits on-chip beyond the traditional methods used in voltage-mode design. It was no longer feasible for analog ICs to have low-accuracy, bulky IC resistive dividers or a multitude of I/O (input/output) pads connecting off-chip biasing to the on-chip circuits. By 1965, a new analog cell, the CCCS “current mirror” shown in Fig. 2.17, possessed a structure not 38 Input impedance taken at front of device input and output impedance taken at device output as shown in Fig. 2.16 (a) for simplicity. R1, R2, and RL may be figured into these equations by taking the impedances from that particular perspective if desired. 47 Fig. 2.17 Current-mode seminal cell: the bipolar current mirror. seen before in vacuum tube design and readily solved this problem biasing problem 39 . Two variations of this current-mode circuit that are still in use today include the Wilson current mirror and the Widlar current source, both of which became key elements in allowing the famous 741 operational amplifier (Op-Amp) to be integrated and biased on-chip [50]-[54], [56]. For the simple current mirror example in Fig. 2.17, the state variables for this design easily expressed in terms of current for the current gain where: 1 2 , (2.25) when the bipolar transistors, Q1 and Q2, are equal in size, and Q1 is diode connected. It is important 39 The current mirror is a current-mode element with at least 3 terminals, where the common terminal is connected to a power supply (i.e. ground), the input current, I in , is connected to the input terminal, and the output current, I out , is equal to the input current multiplied by the current gain (adjusted via the width of the transistors). Current mirrors are current-controlled current sources. In addition to biasing current mirrors can provide an active load for circuits. The main downfall of current mirror is that there is always current running through the mirror, so there is always a static power dissipation dependent on the sizing of the transistors. Furthermore, the current mirror cell was not ever seen in voltage-mode vacuum tube design. This is because vacuum tubes require a negative grid voltage to reduce the plate/anode current to near-zero levels, therefore using a current-mirror would not naturally arise in vacuum tube voltage-mode design. 48 to note a few observations about the current mirror: 1) in this example both the Iin and Iout branches constantly flow DC current, albeit small (~in the µA to mA range), which consumes static power, 2) exact matching of the transistors, Q1 and Q2, in the IC design and layout is of high importance as the currents are directly dependent on this, and 3) the current mirror requires transistor stacking (also known as threshold-stacking in FETs) which limits the lowest possible supply voltage that can be used to keep the transistors amplifying in the active region—this is of importance when scaling analog ICs to smaller process nodes where the supply voltage decreases and also in low power analog designs. The differential pair amplifier from Fig. 2.10 was another traditional voltage-mode cell to give into the analog IC design evolution spearheaded by BJTs [57]. The first LTP vacuum-tube amplifiers in the 1930’s used the knowledge of push-pull circuit techniques and measurement bridges to obtain a larger voltage gain as compared to the simple common-cathode amplifier. In actuality, the implementation of the differential pair with bipolar transistors like the pair with resistive loads shown in Fig. 2.18a or the complementary active load differential-input to single- ended output adaption in Fig. 2.18b is more of a mode-transformation element where the voltage inputs, Vin1 and Vin2, give rise to the current outputs, Iout1 and Iout2, on the collectors of the BJTs from which the output voltages, Vout1 and Vout2, are taken due to the final transformation from current back to voltage by the loads. Some term this mixing of modes “Free-mode” design [20]. The problem with this method in reference of Fig. 2.18b is the non-linear Iout vs. Vin relationship. On the other hand, the transconductance, gm, from Eq. (2.9) for the cell in Fig. 2.18b was observed to be a linear function of the tail current, Itail; circuits of this type were called “translinear”. Barrie Gilbert baptized this new class of circuits which exploited the current properties as “current-mode” analog circuit design [20], [50]-[53]. 49 Fig. 2.18 Voltage-mode differential pair adaptions with bipolars. By 1966, Gilbert was quick to realize that one could merge two current mirrors together in order to obtain a linear current-mode multiplier with a differential pair configuration; this merging of cells is shown in Fig. 2.19. 40 This “super-cell” shown Fig. 2.19b in had the linearity of a fixed- gain current mirror coupled with the variable-gain properties of the differential pair—a perfect example of the exploitation of the circuit’s linear transconductance with respect to the gain- controlling tail current below the differential pair. Furthermore, it could be classified fully as a current-mode circuit. For example, ΔVBE, also called the “characteristic voltage”, in Fig. 2.19b is considered an “incidental” voltage in that it is fully dependent on currents and can be described as such: 40 The term “translinear” was coined in 1975 by Barrie Gilbert for transistors and circuits that have a transconductance that is linearly (or approximately linear) to the output current. 50 Fig. 2.19 Current-mode analog cell evolution: from bipolar current mirrors to bipolar differential pair multiplier. ∆ log log , (2.26) where the mirror ratio, M, determined by the transistor sizes cancels out, no longer determining the gain. Making the assumption that all transistors are operating at the same temperature, T, we can then make the deduction that: → , (2.27) where the currents shown in Fig. 2.19b can be plugged in: 1 1 1 1 , (2.28) which simply collapses to: . (2.29) The differential input current is Iin = (2x-1)Ix and the differential output is Iout = (2x-1)Iy. From this we can find the function of the cell in Fig. 2.19b to be: 51 → , (2.30) where the variable gain, GCM, has a total dependence on the circuit’s currents, such as is the case for ideal current-mode circuits. This is a perfect example of translinear design (i.e. current input to current output) which current-mode circuit design with bipolar was optimized for. This idea then fed into the development of two general-use current-mode cells used for amplification, frequency multipliers/mixers, dividers, differential and quadrature oscillators, and even DC-converters; these bipolar current-mode seminal cells are shown in Fig. 2.20 41 . In the next few decades to the present day, these primitive cells were readily adapted to analog CMOS IC design 42 with feature sizes narrowing down to the µm and nm range, where current-mode design— and most importantly the current mirror—was readily applied to traditional voltage-mode analog designs that had a foundation in the vacuum tube era, such as simple amplifiers and oscillators. Attributes of the bipolar transistor are summarized in Table 2.4. 41 As an interesting side-note, digital IC design also enjoyed a period of current-mode BJT circuit design approaches with emitter coupled logic (ECL) techniques from the mid-1960’s to the 1990’s; other names for this method included current steering logic (CSL) and current mode logic (CML). The designs employed the use of an overdriven differential BJT amplifier with a single-ended input and limited emitter current to ensure that all transistors remain out of the (fully-on) saturation region to avoid the BJT slow-turn off behavior as a switch. In ECL, input impedance is high and output impedance is low, and as a result the transistors can change “logic” states very quickly, minimizing delays as the expense of higher power. In FETs, the equivalent technique is called source-coupled FET logic (SCFL). It is important to note that even though this was a current- mode or current-steering method due to all separate ECL logic gates requiring a bias current which is steered between transistors according to the logic state, all the state variables were in voltage form like traditional logic methods [20] [59]. 42 There also exists an integration of BJT and CMOS which is known as BiCMOS technology. Another type of specialized transistor is the insulated gate bipolar transistor (IGBT) which is a combination of a FET with a BJT that can be used as an ultra-fast electronic switch. The tradeoff with both of these high performance, high frequency processes is a greater cost and a larger power consumption. 52 Fig. 2.20 The primitives of two general-purpose current-mode differential bipolar building block cores. Device Innate Control/ Source Primary Design Technique Classification 43 Secondary Circuit Design Techniques Employed Input Impedance 44 Output Impedance Governing I-V Relationship Current Gain Factor BJT CCCS Current-Mode Power-Mode, Voltage-Mode, Current-Mode Low High Exponential β F [unitless] Table 2.4 Attributes of the bipolar transistor. 43 Voltage-Mode is also used with BJTs such as in Fig. 2.16, but it is very important to point out that this is in a circuit configuration which takes voltage, converts it to current at the input of the BJT, which gives a current output, which is then converted to voltage with the load. Therefore, the bipolar device is still primarily utilizing a CCCS scheme internally. 44 Input impedance taken at base; output impedance at the collector. 53 2.4 CMOS: The Gradual Shift to Charge-Mode IC Design Three successive revolutionary improvements to FETs were responsible for increasing their usefulness and popularity compared to the bipolar transistor for both general purpose digital and analog IC design 45 : 1) the metal-oxide-semiconductor device, 2) the metal-oxide-semiconductor field effect transistor IC structure, and 3) complementary metal-oxide-semiconductor—and subsequently the CMOS inverter. The first MOS transistor device was demonstrated at Bell Labs in 1959 by inventors Dawton Kahng and Martin Atalla 46 [25]. In 1962, at RCA, Steven R. Hofstein and Frederic P. Heiman invented the IC MOSFET structure as we know it today enabling the MOSFET to become the most important FET [26]. The addition of the oxide to the gate of the transistor to control the carriers in the channel allowed for the MOSFET to be used as both an active amplification device and a voltage-controlled current source (VCCS) switch—somewhat of a hybrid of the input used for traditional voltage-mode vacuum tube design, yet with an output drain current similar to current-mode bipolar design. In 1963, the CMOS device which has both symmetric n- and p- type MOSEFTS (pMOS) on the same substrate was developed by C. T. Sah and Frank Wanlass out of Fairchild’s R&D labs [27]. The ability to have symmetric complementary devices on the same low-cost, readily available silicon die with just minor fabrication mask changes during manufacturing laid the groundwork for the explosion of digital design including microprocessors and memory where today there are billions of CMOS transistors per processor silicon chip [66]. The simple CMOS inverter was a new circuit topology never seen 45 BJT technology is still used today for high performance RF design, but it tends to utilize more expensive and specialized processes to extract its high performance traits such as speed (at the expense of power) as compared to digital CMOS processes in silicon. 46 Legend has it that at Bell Labs, the work was actually being done on n-p-n bipolar transistors in silicon. The device on the silicon was being fabricated and the engineers went home only to come back to work later to find that a layer of oxide (i.e. glass) had formed over the device. The device had new properties they realized were useful, thus the metal-on-silicon (MOS) transistor was invented. [59] 54 before in IC design; previously the differential pair (see Figs. 2.10 and 2.18) was the general circuit utilized for phase inversion 47 . The symmetry of the n-channel and p-channel FETs coupled with the capacitive oxide layer which precisely controlled the carriers in the length of the channel was ideally suited for fast inversion of a signal. The slower mobility of the p-channel, µp, as compared to µn, could be easily adjusted by increasing the width of the pMOS device by ~2.5 or slightly higher depending on the process. Also, the extra isolation of the bulk-biased n-well from noise and unwanted signals—which inherently travel through the substrate, made using pMOS devices as analog amplifiers much more desirable and even beneficial for certain applications. In addition, the advent of self-aligned polysilicon gates increased the performance and scalability of CMOS transistors. An ideal view of the cross-section of the nMOS and pMOS transistors in a general silicon CMOS process is shown in Fig. 2.21, where L denotes the conduction channel lengths of each device. Fig. 2.21 Ideal cross-section of an integrated planar nMOS (left) and pMOS (right) in a typical CMOS IC process. 47 There is also such a circuit as the complementary bipolar resistor-transistor logic (RTL) inverter which uses large resistors (and sometimes capacitors) in its design, but the circuit drew more power, was not entirely symmetric for the timing of the Up and Down output transitions due to the vertical n-p-n and lateral p-n-p device differences, and consumed more area. 55 The basic symbol 48 , basic small signal model, and I-V characteristics of the nMOS and pMOS transistors are shown in Figs. 2.22 and 2.23, respectively. The MOSFET has 3 general modes of operation including strong-inversion (e.g. saturation), linear (e.g. Ohmic or triode), and weak-inversion (e.g. sub-threshold or cut-off). The saturation and linear regions are typically characterized by the square law and linear models, respectively, while operation in the sub- threshold region is characterized by an exponential 49 . Fig. 2.22 nMOS transistor symbol, general small-signal model, and typical Id-Vds characteristics. Fig. 2.23 pMOS transistor symbol, general small-signal model, and typical Id-Vds characteristics. 48 Digital CMOS design typically forgoes the arrow convention at the source of the nMOS and pMOS transistors and instead places a bubble at the gate of the pMOS to denote the difference from an nMOS transistor. 49 There exist numerous MOSFET and finFET models for characterizing and describing the operation modes. Beyond the simple square law model used for hand calculations, there are other more involved transistor models used for simulation; for example, 2 of the more popular are the complicated Berkeley simulation (BSIM) model and the charge-based EKV model; the first joins several sequential operating mode equations with a numerical approximation and the latter uses one continuous equation to describe all modes of operation. The square law model is not accurate for the newer CMOS deep sub-1µm technologies due to their shorter channel length, nor does it explain sub-threshold characteristics. In this case a more advanced model such as aforementioned BSIM or EKV is required with computer-aided simulation. The new Berkeley BSIM6, introduced in 2013, has been completely rebuilt around the charge-based EKV compact simulation model. The square law model however is useful for quick hand calculations as it is a simple model from which approximate values may be extracted. [19], [61] 56 For example, for the nMOS, the basic I-V and equivalent charge-mode views of the equations for the saturation region (2.31), triode/Ohmic region (2.32), and the sub-threshold region (2.33) are: 50 : , 1 2 1 1 2 , (for finFETs like that in Fig. 2.5b, let 2 ), (2.31) 51 / : , 2 2 , (2.32) 52 : , , , , , , 1 , (2.33) 50 These are general equations for the nMOS. The pMOS equations are exactly the same, but with the pMOS model values substituted from Fig. 2.23 with reversed polarities. These equations also assume that the bulk is separately tied to the source of each nMOS and pMOS device, not accounting for back-biasing bulk effects. finFETS can be related to the basic nMOS and pMOS equations by recognizing the finFET’s actual Weff in Eq. 2.31 from Fig. 2.5b. Notably, the finFET has 3 charge conduction channels long the 2 sides of height and single width of the fin. 51 Ignoring the channel length modulations, λ, for simplicity. 52 This sub-threshold equation is valid when the source is tied to the bulk of the MOSFET where v T found by Eq. (2.10). Otherwise: . 57 while Cox 53 and CD is the gate oxide and depletion layer capacitances per unit area [F/µm 2 ], respectively, QD 54 , QDS, and QT are the varying depletion layer charges per unit of area [C/µm 2 ] for the MOSFET’s modes of operation 55 , W and L is the width and length of the transistor in [µm], VGS and VDS is the gate-to-source and drain-to-source voltages in [V], Vthn is the threshold voltage in [V], λ is the channel length modulation parameter in units of [V -1 ], and ID0 is the current in [mA] when VGS=Vthn. [19], [49], [61]. Most notable is the operation regions’ dependence on depletion layer charge which can be seen in Eqs. (2.31)-(2.33) where capacitance is multiplied by voltage, which indicates the MOSFETs high dependence on charge dictated by the capacitances in the device’s channel. When the equivalent transformation from voltage and current into a charge-mode view is taken, we can visualize the “charge-mode” view of the MOSFET in the various operation regions. By doing so, it gives us deeper insight into the MOSFETs operation and how we can exploit this charge property to optimize a circuit design with the MOSFET. Furthermore, the charge-mode view can be classified as an energy mode transformation from V and C to Q by way of Q = CV and the energy, E, stored in a capacitor where E= ½ (CV) 2 = ½ (QV). Eqs. (2.31) and (2.32) contain this energy relationship with Q multiplied by V. 53 , where is the thickness of the oxide in the MOSEFT in cm and is the dialectic constant for silicon is 3 .97 , where the dialectic constant in a vacuum is =8.85x10 -14 F/cm. gets smaller with each smaller process node, therefore, C ox increases. 54 Q D here is taken as positive, where we allow Q D =-Q inv if desired to equate to correct relationship of the charge being negative. Some texts use the negative value. 55 The depletion layer charges Q D , Q DS , and Q T are defined by the amount of charge held by the capacitive oxide in the channel during each mode of operation. For a clear picture of this, please refer to page 133 of [63] for a figure of approximate oxide capacitance values for the three modes of operation of the MOS transistor. 58 Fig. 2.24 depicts the variations of the depletion layer charge in the channel for each region of operation; the shape of the channel and amount of charge contained within is wholly dependent on the associated oxide capacitance between the gate and the channel region which varies with the biasing. Using Fig. 2.24c-d for the channel in saturation and Fig. 2.25 for the ideal view of the charge in the MOSFET channel, we could take Eq. (2.31) to take a look at the saturation current from another perspective in terms of total charge in the channel area, Qtot, divided by the transit time, ΔT, for the carrier electrons to travel the length of the channel similar to the BJT Eqs. (2.19) and (2.20). By plugging in and rearranging the terms to obtain the charge-mode view of the nMOS Fig. 2.24 nMOS cross-sectional view depicting operation regions with channel charge variations. 59 Fig. 2.25 MOSFET charge in the channel during saturation for an ideal nMOS. device where I=Q/T, we get: ∆ 2 → 1 2 ∆ . (2.34) Similarly, we can apply this to the pMOS to compare the transit time when WPMOS=2.5·WNMOS, to adjust for the differences in hole and electron mobility. Therefore, due to the symmetric structure of the CMOS devices and appropriate sizing, the transit times for the nMOS and pMOS can be made approximately equal: ∆ 2.5 ∆ , (2.35) However, the CMOS device is still slower than the vertical n-p-n bipolar due to the base area being much smaller than the channel length of the MOSFET. This is why much higher frequencies may be obtained by bipolar technology in the THz region as compared to CMOS which has a theoretical limit for the unity gain frequency, fT, up to the 100GHz range depending on how small the channel length becomes in each successive smaller process node. The unity gain frequency in radians, ωT, for a MOSFET may be calculated by: 2 , (2.36) 60 where Table 2.5 displays the approximate contributing relationship between the MOSEFT device capacitances and the gate oxide capacitance [63]. Fig. 2.26 displays the nMOS channel charge distributions in relation to the device capacitances for each of the operation regimes. As the devices become smaller and smaller with each new CMOS process node developed, the device capacitances get incrementally increased due to decreased tox. Fig. 2.26 Schematic representation of the oxide capacitances for the nMOS in each region of operation. Device Capacitance Sub-Threshold Linear Saturation Eqs. 0 0 (2.37) 1 2 (2.38) 1 2 2 3 (2.39) Table 2.5 Approximate MOSFET operation region oxide capacitance contribution equations. 61 We can also find the transconductance, gm, of the capacitive charge-based VCCS nMOS device in the saturation region in terms of the charge: 56 2 , (2.40) noting that the transconductance can also be described both as a function of the drain current and biasing, or more importantly, as a function of the depletion region charge as µn, W, and L are fixed parameters while the depletion region QD varies. Because of gm’s dependence on the oxide capacitance’s charge, we can call this transformation of terms from voltage and current into charge, a “charge-mode” view of the MOSFET transconductance. Also, using this Cox relationship, we can see that the frequency of the device is increasing with each new lower process via Eq. (2.36) using Eqs. (2.38)-(2.40). Table 2.6 summarizes the general attributes of the MOSFET device. Device Innate Control/ Source Primary Design Technique Classification 57 Secondary Circuit Design Techniques Employed Input Impedance 58 Output Impedance Governing I-V Relationship Gain Factor MOSFET VCCS 59 Charge-Mode: Transconductance Power-Mode, Voltage-Mode, Current-Mode, Charge-Mode High High Square Law (saturation) Linear (Ohmic) Exponential (sub-threshold) g m [ Ω -1 ] Table 2.6 General attributes of the MOSFET device. 56 For formal equations based on charge please see page 57 of [19] defining the transconductance(s) as a function of charge. 57 Because the stand-alone MOSFET it is neither a VCVS like the triode vacuum tube nor a CCCS like a bipolar device, it is really a mix of the two being a VCCS, thus in a circuit it can be configured for current attributes or voltage attributes. Thus Gilbert refers to this as “Free-Mode” design when building circuits with a MOSFET [20]. Additionally, if one makes a circuit out of the MOSEFT they can obtain a voltage-mode (like an inverter) or a current-mode (such as a current mirror) design (or any other mode) if so desired. 58 Input impedance taken at gate; output impedance taken at drain. 59 For the typical common source stand-alone MOSFET configuration when the gate is used as an input and the drain used as an output. In a common-gate amplifier configuration the MOSEFT in a circuit may be classified as a VCVS or even CCVS where the source is used as an input (voltage-input VCVS, but in reality this is a current input-CCVS) and the drain is used as output from which a resistive load is attached to obtain the output voltage. 62 The gm is an important parameter for determining the gain of the transistor when in a circuit configuration, such as in any of the adapted voltage-mode amplifier configurations shown in Fig. 2.27. For instance, applying the small-signal model from Fig. 2.22 to Eq. (2.5) to solve for voltage gain of the adapted basic voltage-mode amplifiers in Fig. 2.27a-c, results in Table 2.7. Fig. 2.27 Basic adaption of the single-stage voltage-mode amplifier configurations implemented with n-type MOSFETs. Amplifier Configuration Input-to- Output Phase Relationship Voltage Gain Current Gain Input Impedance Ω Output Impedance Ω Eqs. Common Source 180⁰ (High) ∞ (High) ∞ (High) (Moderate-High) (2.41) Common Drain 0⁰ 1 1 (Low) ∞ (High) ∞ (High) 1 (Low) (2.42) Common Gate 0⁰ (Moderate-High) 1 (Low) 1 (Low) (Moderate-High) 60 (2.43) Table 2.7 Approximate single-stage MOSEFT amplifier configuration properties. 60 Without the load R D , the common gate would have an output impedance of r o , which is low depending on the sizing of the transistor. 63 From Eqs. (2.41)-(2.43) for the VCVS single stage amplifier configurations we can see that the VCCS MOSFET uses impedance to convert the output current to voltage through multiplication with the MOSFET gain factor, gm, for each of the voltage-mode configurations— which they themselves use load impedance to transform the drain current into the output voltage. Fig. 2.28a-b depicts the evolution and adaption of the phase inverting topologies used for MOSEFTS which has roots all the way back to triodes and bipolars (Figs. 2.9 and 2.16). However, the digital CMOS inverter Fig. 2.28c was a new circuit topology, which was not established previously in either of those device technologies that used charge applied at the gate (voltage) to attract or inhibit channel charge of the opposite polarity from source to drain (current). Fig. 2.28 Voltage-mode MOSFET differential pair to inverter evolution from a restive load to an active load and the CMOS inverter with associated function symbols. 64 From this novel invention, low power CMOS logic 61 sprung up and again revolutionized computer processor, memory, and other digital circuit design for various applications. Soon analog designers began reevaluating traditional analog circuits and finding new topologies which could accomplish the same functionality, yet with simpler CMOS logic structures that did not require a large, power hunger current mirrors. This shift would aid in the low-power analog circuit design required for wearable wireless devices, cell-phones, and biomedical implants which operate using a battery. This new analog-in-digital (AiD) design gave way to new CMOS circuit topologies. For example, in the phase-locked loop system, the phase-detector (PD) was a very important circuit block which compared two frequencies’ phases and outputted the error difference between them. Previously in bipolar and MOSFET analog design, the sinusoidal-input gilbert cell mixer adaption from Fig. 2.20a was used to accomplish this task. With the advent of CMOS design, much more compact and lower power logic and flip-flops were developed to complete the same functionality with minimal tradeoffs with the sequential PFD. This phase detector evolution for MOSEFTS is shown in Fig. 2.29a-b. The digital PFD with an optimization will be discussed in the next chapter on charge-mode analog IC design 62 . Other examples of AiD design extended to digital PLLs (DPLLs), frequency dividers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital filters, ring oscillators (ROs), and other mixed-signal circuits. 61 General digital logic family diagram for reference: 62 See Fig. 3.13 for a typical DFF circuit that is placed in the PFD. 65 Fig. 2.29 AiD example: Analog Gilbert-cell PD versus analog-in-digital CMOS PFD. 63 Although CMOS analog IC design readily adapted fundamental voltage-mode and current- mode circuits including amplifiers, oscillators, and current mirror biasing due to the nMOS similarities to the n-p-n BJT, new types of analog design were also established beyond AiD design in an effort to increase functionality and save power. Other examples of innovation with CMOS analog IC design included switched-capacitor (SC) and sub-threshold design, which had never been seen before the advent of CMOS. They were both uniquely CMOS and also based on the function of charge in and between the devices. The previous examples of the common single-ended and differential amplifiers in Figs. 2.27a-c and 2.28a-b represented “continuous-time” circuits as the signal input was continuously available and the output could be continuously observed [62]. In many situations however, the 63 It is important to note that there are tradeoffs between traditional analog and analog-in-digital circuits that depend on the circuit being designed. They can include noise, frequency range, size, power consumption, and performance tradeoffs. 66 input to can be sensed at periodic instances and its value ignored (or held) at other times. These “discrete-time” or “sampled system” circuits process a sample value at each end of the period. A common class of these circuits are switched-capacitor (SC) circuits which are perfectly suited to CMOS technology due to the efficient control the gate has over the capacitive oxide in modulating the charge in the channel of the MOSEFT. In other words, the SC circuits can hold a voltage value via capacitive charge or transfer charge via the channel—it is very much a charge-mode analog design approach. In Fig. 2.30, we have a simple charge transfer example using the switch capacitor building blocks. The amount of charge transferred in 1 cycle of the non-overlapping clocks with a period of T depends on the equations for capacitive charge as in Eq. (2.44). Since this charge transfer is repeated every clock cycle for this example, we can find the equivalent average current due to the charge transfer by dividing the charge by the clock period, resulting in Eq. (2.45). ∆ (2.44) ∆ (2.45) Fig. 2.30 Switched capacitor charge transfer example. 67 Fig. 2.31 depicts the basic building blocks of SC design, which mainly consists of, but is not limited to, CMOS switches, inverters (see Fig. 2.28c), capacitors, Op-Amps (see Fig. 2.28b), and non-overlapping clocks ( Φ). When assembled, the SC building blocks give rise to new topologies for amplifiers, filters, ADCs, DACS, and other important analog and mixed-signal circuits in which charge transfer may be utilized. For example, the circuit in Fig. 2.32 depicts a simple switched capacitor amplifier which uses an Op Amp. Although an overall SC circuit design may consume a significant amount of power due to the hard-to-scale voltage-mode Op-Amps which generally use current-mode current mirrors internally, the switches, inverters, and capacitors can be quite low power and very portable to ultra-deep sub-µm CMOS processes. The capacitors and switches do not require current-mirrors or other power-hungry biasing, and if used thoughtfully, they can be developed into efficient, low power analog circuits that use minimally sized transistors as switches. For instance, the next chapter on charge-mode analog IC design will give an example of how to build a low power charge pump for a PLL. Fig. 2.31 Switched capacitor building blocks. 68 Fig. 2.32 Switched capacitor amplifier example. Another type of analog circuit design approach that is becoming increasingly popular in recent years is sub-threshold design. In Fig. 2.3c, we can see that in state-of-the-art IC design, the supply voltage is saturating slightly below 1V for the newest process nodes. With subthreshold design, this value can be further decreased to 0.5V and below to increase circuit efficiency for low power analog IC design while employing creative ways to maintain dynamic range 64 [56]. Eq. (2.33) for the sub-threshold region of operation for the MOSFET shows the reason as to why one would be interested in designing in this regime: the exponential relationship between the drain current, Id, and the effective drive voltage, Veff = Vgs-Vth. This leads to higher gain and more power-efficient operation as one could get more gain for the amount of biasing current and supply voltage (power efficiency) as comparted to a transistor in the liner or saturation region, which is dependent on the square law in Eq. (2.31). Fig. 2.33 depicts the exponential I-V relationship for the sub-threshold regime of the MOSFET. 64 Dynamic range is the difference between the smallest and largest usable signal. 69 Fig. 2.33 Sub-threshold exponential region in the MOSEFT Id-Vg curve (log scale). More interestingly, when working in the weak-inversion region with Eq. (2.33), we find that MOSFETs deliver the highest possible transconductance-to-drain current ratio: 1 , = (2.46) which is very close to that of higher performance bipolar transistors in Eq. (2.9), yet with a dependence on the MOS’s oxide capacitance charge 65 [56][61]. In Chapter 4, there will be an examples on how to exploit the CMOS device subthreshold regime while creating a linear amplifier much like that of a bipolar with desirable dynamic range and speed. Finally, reflecting on the MOSFET, we can observe that the CMOS transistor and the various examples of the new families of analog design this device gave birth too—including AiD 65 This maximization of the transconductance is important as it optimizes the speed per watt and precision per watt relationship, also known as the resource-provision equation found in [56] on pg. 657. 70 design, switched capacitor, and sub-threshold—all have a dependence on the device’s oxide capacitance and channel charge that can be explained from a charge-mode approach in addition to voltage-mode and current-mode. Doing so, helps a designer to exploit the CMOS charge-based properties for desirable attributes including lower power, increased performance, and scalability. Charge-Mode IC Design Examples The charge-mode design approach is one in which the variables used to describe the circuit or system are primarily in the form of charge. Furthermore, charge-mode circuit design can be used for control and skillful manipulation of charge within and between devices in order to optimize a circuit for performance (e.g. lower noise, higher speeds, and reduced power) and area. It can also be used to create new circuit topologies to meet these needs. This type of design suitably fits with CMOS as its structure is that of a charge-based device and can be modeled as such. 66 Charge-mode design does not negate other modes of design, which may be used in conjunction with this approach. Voltage is simply seen as charge being held by a device and current is viewed as movement of charge in and between devices. For the CMOS device, Table 2.8 gives a sampling of various parameters important for analog IC design which have a dependence on the charges within the transistor. In this thesis, a handful of example techniques which can be classified as charge-mode will be discussed and utilized to build scalable circuits for a phase-locked loop and amplification in Chapters 3 and 4. These circuit design techniques include charge transfer, charge/discharge path optimization, capacitive charge coupling, and CMOS transistor channel charge manipulation. Each of these are described briefly in the following sections. 66 Successful efforts to model the MOSFET device from a charge-based approach include the EKV, Mayer-Mead, and BSIM6 transistor models. 71 Parameter Description Importance for CMOS Analog IC Design Scaling Trend (w/each new process) gm Transconductance Eq. (2.40) and (2.46) -Found in amplifier gain Eqs. (2.41)-(2.43) and device frequency Eq. (2.36) Increasing rds Source-to-drain resistance - Charge flows through this resistance in the transistor - Found in intrinsic gain as it is the inverse of output conductance, gds, found in Fig. 2.4d Decreasing Cgs, Cgd, Cgb, Cox Device capacitances Eqs. (2.37)-(2.39) - Capacitances have the ability to store charge and/or have that charge transferred for operation Increasing fT Unity gain frequency Eq. (2.36) - Gives an idea of the frequencies for which the device may work and useful bandwidths Increasing Avi Intrinsic gain - Multiplication gm and rds show devices ability to amplify using traditional methods, see Fig. 2.4f Decreasing Id Drain current - The various operation regimes of the MOSFET are dictated by the channel charge in Eqs. (2.31)-(2.33) Decreasing (see Fig2.4c) vth Threshold voltage - Parameter which helps to define the operation regime of the MOSFET Decreasing (see Fig2.4b) P Power dissipation - The power of the device is directly dependent on energy consumed in each cycle dynamically or statically. Energy relates power and charge via Fig. 2.11. Decreasing (for scalable analog) Table 2.8 Snapshot of important CMOS device and design parameters with charge dependence. 1) Charge-Transfer Charge transfer is described as the intentional sharing of charge back and forth from one device or circuit to another to aid in its functionality and performance as shown in Fig. 2.34. In traditional analog design, the switched-capacitor technique discussed earlier in the CMOS section Fig. 2.34 Basic bi-directional charge transfer concept. 72 of this chapter, is an example of unidirectional movement of charge transfer with the additional use of mixed-mode (or free-mode) design including voltage-mode amplifiers and current-mode current mirrors. In this thesis, we will use a purely charge-mode approach. In Chapter 3 we will discuss how to use polarity-dependent, bi-directional charge transfer to completely redesign and optimize an analog PLL charge pump. The novel CP topology, operation, and performance will be overviewed and compared to the state-of-the-art. Other applications for which this approach has been used by the author and has proven to be useful include analog-to-digital and digital-to-analog converters (ADCs/DACs), low power biasing, reference generation, and analog circuit modeling of biological system function such as the heart and lungs. 2) Charge/Discharge Path Optimization AiD circuits have become extremely popular as CMOS technology scales into process nodes below 45nm. Using digital logic circuits to complete analog functions is unique to the CMOS device. Common examples include phase-frequency detectors, frequency dividers, digital PLLs, digital filters, ADC/DACs, and digitally-controlled power amplifiers. Analog designers typically utilize digital circuits and gates such as AND, OR, inverters, and flip-flops which have been pre-optimized for signal speed from a specific input to an output—also called the critical path. Some applications for which analog applications use digital circuits do not necessarily need this same input-to-output path to be the fastest. For instance, in digital design, a DFF may need its Clock-to-Q output to be the fastest, but for a DFF utilized in a phase-frequency detector, the Reset- to-Q path is of the utmost importance as excess delay on this path can cause errors in the control system of a phase-locked loop where this circuit is utilized. Therefore, analog designers seeking a certain excellence in their circuits must at times find a more custom solution for the desired 73 optimal performance as opposed to using the run-of-the-mill standard digital logic library which is available through the foundry with their technology files and optimized for minimal transistors. Complementary complex logic (C 2 L) is a one such method which may be used to optimize the desired path through the reduction of parasitics, for example in Fig. 2.35, at the circuit and layout level, for efficiency and speed, while delivering compactness and low power. It has use in both analog and digital circuitry by reducing the charge/discharge time to process a signal from the desired input to output path through analysis of the path, transistor sizing, and parasitic reduction in the circuit layout. In Chapter 3 (with supplement notes in Appendix A), we will explain the methods of this technique and where it differs from traditional approaches; after this, the redesign of a traditional PLL phase frequency detector using the C 2 L method will be completed. Fig. 2.35 Basic charge/discharge path example. 74 3) Capacitive Charge Coupling The phenomenon of phase and frequency coupling or “entrainment” 67 between devices is well documented in a variety of systems including mechanical, electrical, and physiological. In electronics, coupling can be due to unwanted parasitic effects wreaking havoc on signals or it can be intentional, as to benefit the circuits involved when used correctly, thus boosting their performance. The concept of phase-coupling is shown in Fig. 2.36. In Chapter 3 of this work, simple staged, inverter-based ring oscillators are placed together in different configurations and laid out with intentional parasitic capacitive charge coupling between their wirings to produce an expandable-phase, multi-GHz VCO with high performance and low power tradeoffs. Fig. 2.36 Example of basic capacitive chargecoupling between signals and phases. 67 Entrainment is the same as phase-coupling and phase-locking. The coupling of 2 similar, linearized systems with the same natural frequency will cause the signals to “couple”, thus coming into alignment. The coupling of 2 non-similar, linearized systems with the different natural frequency will cause signal “beating”, where the combined output shows the original 2 frequencies plus a new oscillation that corresponds to the difference between those 2 frequencies. 75 4) CMOS Channel Charge Manipulation Chapter 4 of this thesis is dedicated to the author’s most recent research endeavors regarding how to create useful analog circuits, including amplifiers, in ultra-deep sub-µm all- digital CMOS processes. It includes investigation into the novel complementary injection field effect transistor device, also known as the “CiFET” which manipulates charge in the channel region to produce a highly linear current-controlled voltage source (CCVS) device due to the merging of the MOS sub-threshold and saturation operation regions. An example of the charge in a MOS channel is shown in Fig. 2.37. The CiFET is a modification of the traditional CMOS device which can be used as a scalable building block for both analog and digital applications. CMOS charge-mode circuit examples for analog applications given in this thesis include: 1) Charge Transfer: Charge-based PLL charge pump, 2) Charge/Discharge Path Optimization: AiD DFF design using C 2 L, 3) Capacitive Charge Coupling: Expandable ring-VCO, 4) CMOS Channel Charge Manipulation: CiFET building block amplifiers. Fig. 2.37 Example of channel charge distribution in a MOS device during operation. 76 In Chapter 3, the first three examples will be utilized to construct an experimental PLL. The fourth example will be applied to build an array of analog circuits including amplifiers in Chapter 4. Each of these examples will be described, fabricated, tested, and compared to the state-of-the-art. With each of these charge-mode examples we will see that they all follow a pattern and can be characterized by: biasing of circuits through charge sharing and storage (no traditional power-hungry current-mode current mirrors are used), lack of need for transistor stacking typically seen in voltage- and current- mode designs for gain and impedance, use of symmetry from the complement devices to the circuit level, and minimal device sizes utilized (including ability to use finFETs). Advantages for using this charge-mode approach as set forth by this thesis include: new circuit structures, scalability to the newest process nodes, portability between nodes, reduced design time due to reusable structures, lower power, reduced noise, and desirable performance tradeoffs including increased speed, high gain, and linearity. 77 Chapter 3 EXPERIENTIAL ANALOG PHASE-LOCKED LOOP The phase-locked loop is a ubiquitous control system used for precise frequency and phase generation, clock synchronization, and signal recovery. PLLs are perhaps the most important and ubiquitous circuit block in modern electronics as they can be found in every computer processer, transceiver, and clocked system, including lab test equipment. Therefore, PLL cost, area, power, and performance—and ultimately scalability—is continuously of main concern for IC designers and manufacturers which will employ this circuit-based system in their next-generation devices. For multi-GHz wireline and wireless IC applications there are two primary PLL design approaches: 1) analog and 2) digital. Generally, analog PLLs, such as the charge pump PLL block diagram shown in Fig. 3.1, have a larger IC footprint and are typically more power hungry as compared to their digital phase locked-loop counterparts. On the other hand, DPLLs generally possess more complicated circuitry, are limited to frequencies significantly below 10GHz, and have a tendency to suffer from digital noise due to quantizing issues. Since PLLs in general are extremely useful in analog/RF, mixed-signal, and digital SoC applications for both wireless and wireline systems, much effort from both the industry and research sectors has been focused on finding new scalable low noise, high performance alternatives in CMOS [64]. 78 Fig. 3.1 Block diagram of a state-of-the-art analog charge pump-based PLL. In recent years, analog PLLs have incrementally adopted digital circuit elements to their constituent blocks (e.g. dividers, phase detectors, and oscillators) which perform analog functions with less area and power. To date, a digital-like, portable circuit component for every block in the analog PLL has been created except for the charge pump circuitry; this is due to the analog process extensions (e.g. current mirrors and switches which require large transistors and voltage swings) that have been necessary to design this block using state-of-the-art methods. This has been an important bottleneck in making analog PLLs scalable to and between ultra-deep sub- µm CMOS technologies. The first section of this work is dedicated to applying the charge-mode approach, specifically charge-transfer, to create a simple, yet novel architecture for the CP which is ultra-low power and scalable to the newest CMOS process nodes. 3.1 Proposed PLL Charge Pump Designed with Charge Transfer The main purpose of a PLL charge pump is to control the frequency of the voltage controlled oscillator in Fig. 3.1. The inputs to the CP are Up/Down error signals generated by a digital phase-frequency detector. The output of the CP is a control voltage, VC, stored as charge on the effective capacitance of the loop filter (LF), CL. Raising or lowering VC will result in an increase or decrease of the VCO frequency of operation, fVCO. 79 A typical closed PLL control loop operation would begin with the VCO in Fig. 3.1 producing frequency, fVCO, at phase, ϕVCO. This output frequency is generally divided down by an integer or fractional value to a lower “feedback” frequency, fFB, by the divider block. The stable reference frequency, fREF, and its phase, ϕREF, is then compared to fFB, and phase, ϕFB in the PFD. If there is a difference in frequency or phase between the reference and feedback signals, the PFD produces an Up or Down error signal for the duration of the frequency or phase difference. In this work, an Up=logic 1 error signal is produced by the PFD when the ϕFB lags behind ϕREF and a Down=logic 0 error signal is given when ϕFB leads in front of ϕREF. When the PLL is in phase lock (i.e. fFB=fREF and ϕFB= ϕREF), no error signal is produced (i.e. Up=Down=logic 0) and the loop is essentially open with the ideal CP designs shown in Fig. 3.2b [65]-[72]. The values of the PFD Up/Down error signals determine the action of the CP: Up=logic 1 causes various transistor switches (e.g. S1, S4, and Sb in Fig. 3.2) of the CP to close allowing charge to be placed on the LF’s CL, effectively raising VC and consequently fVCO; Down=logic 1 causes the opposite behavior in the CP to occur by closing the other switches (e.g. S2, S3, and Sa in Fig. 3.2) and taking charge away from CL, thus lowering VC and fVCO. Fig. 3.2 Switch view diagrams for the proposed and state-of-the-art CPs. 80 State-of-the-Art versus Proposed PLL CP State-of-the-art PLL charge pumps such as the single-ended examples shown in Fig. 3.3b- c, employ bulky current mirrors (i.e. IN and IP) and relatively large transistor switches (i.e. Sa-d) to flow substantial amounts of current linearly to and from the LF to alter VC. Although this is effective, these CPs have significant design concerns including: 1) relatively large active area, 2) wasted static power due to current mirrors and biasing always working even during PLL phase lock, 3) the large transistor switches take a relatively long time to open and close, hence there is an unwanted control loop delay before the VCO frequency is altered, 4) extra matching circuitry for the CP Up/Down output signal transitions is necessary for equal charge up and charge down, 5) analog process extensions (i.e. current sources, large transistors, amplifiers) are sensitive to process variation, 6) VC output errors easily occur due to undesirable leakage current slipping through the large transistor switches, thus affecting the VCO frequency while in phase lock, 7) limited headroom due to stacked transistors restricts use at lower supply voltages, and 8) scalability to deep sub-µm technologies is severely restricted due to the large current mirror and switch transistors required to flow considerable currents and typically requires re-design when moving to a new process node. The proposed charge pump described in the next section was designed in such a way as to overcome these challenges. The proposed PLL charge pump shown in the switch view in Fig. 3.2a and transistor level schematic in Fig. 3.3a is a new single-ended, capacitive charge transfer-based design that uses 4 minimum-sized transistor switches (i.e. S1-4) and a relatively small metal interconnect capacitor (i.e. CP) that is sized to be dominant over parasitics [73]-[74]. There are no current mirrors or other analog process extensions as in the state-of-the-art designs. This CP circuit uses the same inputs (i.e. Up/Down logic error signals from the PFD) and has a similar overall general result as 81 Fig. 3.3 Transistor-level schematics for the proposed and state-of-the-art CPs. the state-of-the-art CPs in that the VCO frequency is successfully controlled, yet there are a few marked differences including the architecture, how the charge is transferred and held, the output voltage behavior, and total power consumption. Additionally, the switched capacitor CP acts in itself as a second order filter for the PLL control loop. Proposed PLL Charge Pump Operation As with any PLL charge pump, there are 3 explicit switching modes of operation: 1) Idle, 2) Pump Up, and 3) Pump Down. The next 3 segments describe each of these modes in detail for the proposed CP in the PLL control loop while highlighting the unique output voltage behavior and the amount of energy transferred for each mode, which is necessary to find the total dynamic power consumed while the CP charges and discharges in the various modes. 5) Idle Mode Fig. 3.4 illustrates the switch view of the proposed CP in Idle mode with a general transient waveform. The Idle mode is always characterized by the Up and Down error signals being low (i.e. Up=Down=logic 0). There are two different times in which the Idle mode occurs in the PLL control loop, each with a specific purpose: 1) during phase lock to hold the VC value 82 Fig. 3.4 The proposed PLL CP in idle mode. constant (i.e. ϕFB equals ϕREF) and 2) for the recharging of CP in between Pump Up and Pump Down modes (i.e., ϕFB does not equal ϕREF). At the start of the Idle mode, switches S1 and S2 are closed while S3 and S4 are open; meanwhile this action causes CP, to charge to VDD. After CP charges to the supply voltage, VDD, the capacitor CP holds its charge, QP, in an open loop fashion until the CP is instructed by the PFD to change modes to either Pump Up or Pump Down. VC, will not change during Idle mode and, therefore, retains the voltage value, VC0, it held at the moment prior to starting Idle mode, namely: . . (3.1) Due to the switched capacitor structure of the CP circuit, there are relatively little to no errors in the VC value, ultimately reducing unwanted PLL phase errors compared to the state-of- the-art. There is no static power being dissipated due to biasing in the proposed CP (no current- mode current mirrors) and we must look at the switching dynamic power to find the total power 83 consumed while the CP sits quietly in the Idle mode. In order to do this, the energy at the start and end of the Idle mode needs to be analyzed. The energy utilized by the proposed CP at the start of the Idle mode when CP charges to VDD is: . (3.2) It must be noted that the CP charges only once at the very beginning of the Idle mode; this could be a full recharging or a partial recharging in Eq. (3.2) depending on the amount of charge required to bring the voltage across CP, VP, to VDD. The energy consumed by the proposed CP during the Idle mode after charging to VDD is: ≅0, (3.3) due to no changes in the switches of the CP with the reasonable assumption that the leakage current flowing through the stacked switches is negligible. Therefore, the total power dissipation of the proposed CP for a complete Idle mode cycle may be found via the dynamic power equation: ∆ , (3.4) where α is the activity factor (0 ≤ α ≤ 1) for the proposed CP working in 1 or more specific modes at the PLL reference frequency. 2) Pump Up Mode Fig. 3.5 depicts the Pump Up mode for the proposed CP with a general transient waveform example. In this case, the Pump Up mode is activated by a lagging phase difference between ϕFB and ϕREF; this causes the PFD to produce a logic 1 Up error signal for the duration of the phase difference between fFB and fREF. The CP responds by transitioning out of Idle mode with an opening of S2 and closing of S4 which allows the charge, QP, stored on CP to transfer to CL, thus raising the voltage on VC. The result for one Pump Up cycle is an increasing of ϕVCO and ϕFB in order to match ϕREF. At the end of every Pump Up cycle the CP returns to Idle mode to fully 84 Fig. 3.5 The proposed PLL CP in pump up mode. recharge CP. As the PLL approaches phase lock, partial Pump Up cycles take place incrementally raising VC which allows for accuracy in obtaining the correct frequency on the VCO. The exponential capacitive behavior of the CP output, VC, for a single Pump Up charge sharing event may be modeled by the following first order equation: 1 , , (3.5) where τUp is equal to the RC time constant for the S1-CP-S4 path which the charge must flow through to arrive at CL in the Pump Up mode. The time, t, is the exact time in which Up is high, whether a partial or full cycle. As the PLL gets close to acquiring phase lock, a partial Pump Up cycle occurs where the charge transfer event will get cut off midway (t << τUp) and the exponential portion of Eq. (3.5) may be linearly approximated to (1- t/ τUp) as is shown in Eq. (3.6) when the PLL is near phase lock: 85 1 1 . (3.6) This linear Eq. (3.6) results is precise phase lock at a high resolution for the proposed charge pump. The output step size is simply based on the ratio of CP to the LF’s CL. For example, to increase the output step size, increasing CP would suffice. The change in energy of the charge pump system during a Pump Up mode charge sharing event is: ∆ 1 2 1 2 1 2 , (3.7) where QP and QL are the initial charges held by CP and CL at the start of the Pump Up mode. Using Eq. (3.7), we can now calculate the power dissipated for the Pump Up cycle at the PLL reference frequency by using the following dynamic power equation: ∆ 1 2 1 2 1 2 . (3.8) 3) Pump Down Mode Fig. 3.6 illustrates the Pump Down mode for the proposed CP with a simple transient waveform example. The Pump Down mode occurs when the phase error swings in the opposite direction and ϕFB leads ϕREF, causing the PFD to produce a logic 1 Down error signal for the duration of the difference between fFB and fREF. Similar to the Pump Up mode, the CP responds by moving out of the Idle mode, but instead opens S1 and closes S3 which allows the pulling of the stored charge, QP, away from CL, thus lowering the voltage on VC. This action decreases fVCO and, consequently, fFB, in the closed PLL control loop. At the end of every Pump Down cycle, the CP recharges CP in the Idle mode. 86 Fig. 3.6 The proposed PLL CP in pump down mode. Analogous to the Pump Up cycle, the Pump Down CP output can be modeled by the first order equation: 1 , (3.9) where τDN is equal to the RC time constant for the S3-CP-S2 path that the charge must flow through to leave CL. The time, t, is the full or partial cycle time that the Down error signal is high. As the PLL draws near to phase lock, partial Pump Down cycles occur, where the charge transfer event will get cut off midway (t<< τDN). In this case Eq. (3.9) may be linearly approximated to: 1 1 . (3.10) The output Down step size of the CP may be adjusted via the ratio of CP to the LF’s CL and is equivalent to the Up step size due to CP being utilized for both transitions, thus eliminating the 87 need for extra matching circuitry compared to the state-of-the-art. The CP energy used during a Pump Down cycle is: ∆ 1 2 1 2 . (3.11) Finally, the power dissipated for the Pump Down mode is: ∆ 1 2 1 2 . (3.12) Power Consumption of the Proposed PLL Charge Pump The total dynamic power of the proposed CP may be found by adding Eqs. (3.4), (3.8), and (3.12) or via CP’s stored energy over time: ≅ = . (3.13) Therefore, the total power of the proposed CP with negligible leakage of the stacked transistor switches is simply: 2 ≅ . (3.14) Experimental Results for the Proposed PLL Charge Pump This section presents simulation and experimental results for the proposed charge-mode PLL CP. The proposed CP was simulated in a 1-10GHz ring VCO-based analog PLL with a varying supply voltage of 0.5-1.2V. The technology used was a TSMC digital 40nm CMOS process. The six transistors of the CP had a width of WN=120nm or WP=240nm and a length of L=40nm. The CP capacitor, CP, was 100fF, while the LF capacitance, CL, was 1pF, resulting in a 1:10 output step size ratio. The PFD utilized was a dual-reset DFF from [75] with no added delay due to the comparable switching time between the minimum-sized switches of the PFD DFFs 88 and the CP. Fig. 3.7 shows the simulated output for the Up and Down modes; the inset illustrates the high resolution, linear behavior of the CP output as phase lock is approached and acquired. Fig. 3.8 depicts the % error mismatch simulation comparison results for the proposed CP and the state-of-the-art CPs in Fig. 3.3b-c utilizing the same PLL; the proposed CP output has less than a 0.05% error for 0.05V ≤ VC ≤ 1.15V. Simulation results shown were taken at fOUT=5GHz and fREF=100MHz with a 1.2V supply and a divider of N=50. The average power of the CP was 253pW in simulation, while (b) and (c) had a static power of 1.12mW and 1.53mW, respectively, resulting in a 10 6 improvement in power consumption over the state-of-the-art. The 1-10GHz PLL was fabricated with the proposed CP in all-digital 40nm TSMC CMOS and physically tested. Fig. 3.9 displays the layout and die micrograph of the proposed CP, with the PLL LF capacitor and PFD. The measured performance results of the proposed CP with a Fig. 3.7 Simulated plot of the proposed CP output step and phase lock behavior. 89 Fig. 3.8 Simulated systematic % error between Up and Down currents and VC. comparison to state-of-the-art CPs is shown in Table 3.1. Fig. 3.10 illustrates a snapshot of the phase noise and spectrum characteristics of the physically tested PLL with the proposed CP. The unique, low power switched capacitor design of the proposed CP is responsible for the desirable minimal charge injection into the VCO control line. The power of the spurious sidebands of the PLL thereby is greatly reduced allowing for the reference spurs to be less than -70dBc. The proposed CP design overcomes the aforementioned state-of-the-art CP design concerns efficiently by eliminating current mirrors and adopting a switched capacitor approach to transferring charge to and from the LF’s capacitance. The result is a dramatic reduction of power and active area. Furthermore, the proposed CP is scalable to and between smaller process nodes and able to be used at very low voltages (<1V). The proposed CP possesses no analog process extensions that are parametrically sensitive to process variation, allowing for a matched Up and Down output step when acquiring phase lock. The use of the proposed CP allows for a low jitter, low phase-noise analog PLL with reduced reference spurs. 90 Fig. 3.9 The proposed CP layout (left) and die micrograph (right). Fig. 3.10 Silicon measurement of the PLL phase noise and spectrum characteristics. 91 This Work [b] 68 [c] 69 [70] [71] [72] Supply [V] 0.5-1.2 1.2 1.2 3.3 1.8 1.5 fVCO [GHz] 1-10 1-10 1-10 0.35-0.61 -- 4.8-5 fREF [MHz] 50-400 50-400 50-400 20 50-500 11 CP power [W] 250p 1.12m 1.53m 1.5m 940µ 2.2m CP VC range [V] 0.0-1.2 0.1-1.1 0.1-1.1 0.07-1.05 0.1-0.9 0.1-1.4 CP area [mm 2 ] 0.0004 0.0045 0.0065 0.015 0.015 0.16 RMS jitter [ps] 0.80±0.05 2.3 1.5 7.1 -- -- Ref. spurs [dBc] <-70 <-60 <-65 -- -- <-70 Phase error [º] 0.1-0.3 2.3 0.9 -- 1-5 -- Technology [m] 40n 40n 40n 0.35µ 0.18µ 0.24µ Table 3.1 PLL charge pump performance comparison. 3.2 Proposed PLL PFD Designed with Charge/Discharge Path Optimization Many types of PLLs, both digital and analog, employ a phase detection block for determining differences (i.e. errors) between the divided-down feedback oscillator frequency, fFB, and a stable reference frequency, fREF. An example of a PLL that utilizes a phase-frequency detector circuit is the analog charge pump PLL previously shown in Fig. 3.1. Although over the past 30 years, there have been many varieties of phase and/or frequency detectors for PLLs in ICs, such as analog multipliers or digital combinational circuits like an XOR gate, which could be applied to the block in Fig. 3.1, the state-of-the-art PFD generally is a sequential flip-flop based circuit operating in 1 of 3 states (i.e. Up, Down, or Idle modes) while in a PLL. The ubiquitous use of this type of detector in a PLL is due to the advantageous combination of low power, stability, speed, noise, and area tradeoffs possessed by a flip-flop based PFD as compared to its counterparts. In this section, we will use the C 2 L methodology to produce an optimized PFD for PLL functions. 68 Simulated results from state-of-the-art CP examples from Fig. 3.4b-c. 69 Estimated value from referenced paper. 92 State-of-the-Art PLL PFDs One of the most pertinent challenges in state-of-the-art PFD designs is that the fast propagation delay, τp, of the digital flip-flops does not match the slower analog switching times, τS, in the state-of-the-art CPs in a PLL [76]. To counteract this “dead zone” issue, traditional approaches point to simply adding carefully timed supplementary delay circuitry to the PFD reset path in order to allow for the Up/Down error signals to be extended, permitting the necessary extra time for the CP to react so that it may have the desired effect on the control voltage, VC. The concern that results with this widely-used method is that there is an undesirable added delay, τd, introduced into the PLL control loop, which has the ability to contribute significant noise, seen as jitter, in the PLL [69], [77]-[79]. The increased overall delay in the feedback loop is a source of instability in the PLL. This unsteadiness is a direct result of the PFD output signals causing VC dithering via the CP. The outcome is that the VCO’s frequency, fVCO, changes in either direction as the PLL continually attempts to acquire phase-frequency lock, but fails to do so, therefore undesirably increasing the phase noise of the VCO. Ideally in a PLL, the PFD and CP would have similar switching times allowing for quick and symmetrical corrections of errors in the control loop in real time. Recently, a promising new type of fast-switching, accurate charge-transfer based PLL charge pump, which was covered in the previous section, has been introduced facilitating the need for an improved PFD design that works seamlessly with this advanced block in the PLL [74]. Specifically, this CP does not require a PFD with the traditional delay compensation to account for the inability of the relatively large CP analog transistor switches to open and close quickly. Rather, this digital-like CP requires a PFD with minimal dual Reset-to- switching times on the same logic speed scale; this allows for high resolution of phase error correction in the PLL resulting 93 in extremely low levels of added noise (i.e. dither around phase lock) as compared to the state of the art designs. Therefore, this work aims to introduce a no-added delay dual reset D flip-flop (DFF) based PFD design that when used in conjunction with a charge-transfer based CP in a multi- GHz PLL, results in very low jitter characteristics and reduced reference spurs in the PLL’s frequency spectrum. State-of-the-art PFD designs [81]-[87], such as is shown in Fig. 3.11b, typically are composed of a pair of DFFs with their D=1 and Resets generated by a logic AND gate of both outputs, followed by carefully timed added delay circuitry (e.g. buffers) to compensate for the slow switching time, , , of current-based CPs, shown in Fig. 3.12b. This allows the critical Reset-to- propagation delay, , of the DFFs to be slowed down by to match the CP switching time. While there are a variety of circuits and latches that could be used in a PFD, the use of edge- triggered DFFs extends the phase detection range to span more than 1 period. This is essential for frequency lock over widely different frequencies. The main challenge in a state-of-the-art PFD design is in adding the correct amount of delay compensation to accommodate a traditional CP resulting in minimal dead zone, which is Fig. 3.11 The proposed PFD and a typical state-of-the-art DFF-based PFD. 94 Fig. 3.12 Switch view diagrams for the charge-based and state-of-the-art CPs. directly responsible for phase noise and spurious tones. For instance, if there was no buffering of the PFD reset path to add the appropriate delay, nonlinearities between the PFD and CP would readily be introduced, thus resulting in an incorrect amount of charge delivered to the loop filter. This is due to the differences in timing of the PFD propagation delay and the CP switches. Invariably these charge differences cause a distortion in the CP current spectrum and adversely raise the in-band noise floor of the PLL. In a PLL that uses these components, it is then absolutely critical to match the timing of the PFD Up/Down error outputs to the CP switches such that: . (3.15) A consequence of adding this delay is the unwanted generation of a brief Up/Down 1/1 state for the length of this dead zone in every cycle, even during phase lock, which unfortunately causes fluctuations in the CP producing PLL jitter. Additionally, at the circuit level, an ideal PFD will exhibit the following list of desirable attributes when placed in a PLL: 1) Reset-to- propagation delays are equal to the CP switch time, 2) balanced Up/Down error signal outputs for given phase error, 3) no digital glitch errors while in Idle mode, 4) wide frequency operating range, 5) compact area, 6) low power operation, 7) ability to be used with supply voltages <1V, and 8) scalability to and between process nodes for 95 ease of future reuse thus reducing design time. At the heart of PFD design are the flip-flop circuits utilized to meet these demands head on. State-of-the-Art PLL D Flip-Flops for PFDs To construct a flip-flop, a variety of logic gates may be used. They are essentially a combination of (one, the other, or both) tri-state inverters or transmission-gate selector gates. The Master Latch selects either the D input or its inverted output and the Slave Latch selects either the Master Latch output or its inverted output, where each are selected with opposite phases of the clock. An example of a typical state-of-the-art DFF used in PFD designs is shown in Fig. 3.13. This particular DFF has a positive-edge triggered true and complement clock input, , and a single asynchronous reset, R. The output of the DFF is and its complement is . The propagation delay of this type of DFF is based on the most critical path, in this case Reset-to- as opposed to -to- , unlike normal DFF design priorities which are optimized for Fig. 3.13 An example of a state-of-the-art DFF used in PFDs. 96 minimal clock delays. This reset delay, for the aforementioned reasons, is generally slowed down to work with a typical CP in the PLL. Beyond the negligible leakage current, the power of a DFF, and subsequently a PFD of this type, is wholly dynamic due to the switching current incurred in each DFF clock cycle. The PFD DFFs’ contribution to power in a PLL is by and large the lowest overall. Furthermore, the area of this digital circuit is regularly the smallest of all the blocks in the PLL. With the new compact charge-based CPs, shown in Fig. 3.12a, which switch fast and consume power in the pW range, there is much to be gained by optimizing a DFF for speed, power, and area in a PLL that employs a charge-based CP. Optimized Dual Reset DFF for Proposed PFD The proposed PFD design is shown Fig. 3.11a and is made out of 2 unique dual reset DFFs to match the faster switching speed, , of a charge-based CP design shown in Fig. 3.12a. In this PFD, the output of the DFFs, and , directly supply the error signals, Up and Down, with their complements for use in the CP. There is no added delay in the Reset-to- path as typically seen in the state-of-the-art designs. The proposed DFF of Fig. 3.14 is an optimization of the DFF shown in Fig. 3.13 where D=1 and an additional reset input has been added to internalize the typical PFD AND gate into the Slave Latch. This DFF also consists of three sections: 1) Master Latch, 2) Slave Latch, and 3) Output Buffers. Both latches are made entirely out of asymmetric complex gates for maximum performance. This charge/discharge path optimization approach is known as Complementary- Complex Logic (C 2 L) which is reviewed in Appendix A [88]-[89]. Here the P-channel devices are not a direct De-Morgan complement of the N-channel structure, but instead a logic function complement observed by using zeros for the pull-down and ones for the pull-up realization as visualized on a Karnaugh-Map [90]-[91]. This approach may use some “can’t-happen,” which are 97 Fig. 3.14 The proposed PFD DFF, where D=1 and = for no-added delay. extremes of “don’t-care,” conditions differently between the n-channel pull-down trees and the p- channel pull-up trees yielding dissimilar looking tree structures. A “can’t-happen” condition does not need to have the same logic state for both the pull-down and pull-up structures. Utilizing the C 2 L approach enables a more compact, fast, and lower power DFF design through reduction of interconnect parasitics and transistors in the critical path as realized by combining or sharing the active nodes instead of the normal metal interconnect in the circuit’s physical layout. Note that the proposed DFF in Fig. 3.14 uses a single phase clock, as opposed to Fig. 3.13, so that the delay difference between the internal and is not a consideration in the flip-flop response. The Slave Latch complex-gate structure in Fig. 3.14 combines a fast clock path with the optimized Reset-to- signal paths at node C for minimal delay. When goes HIGH, node C is directly pulled LOW and when the last of both resets go LOW, node C is directly pulled HIGH. It only remains to get the signal and its complement out with nominal delay to form the UP or DOWN CP commands. Observe that needs to be buffered before being tied back to the flip- flop’s through an inversion of , otherwise the complex gate’s output node C would be directly 98 controlling its own gate inputs. The delay to perform this self-reset defines the minimum Up/Down phase detector output pulse width as a couple of fast inverter propagations. This smallest possible PFD output pulse width is on the same scale as the charge-based CP switching time, allowing for an excellent match in operational speeds between these two blocks, which is unlike traditional PFD-CP designs. The 1 st inverter delay starts to turn the switch ON and the 2 nd pulls it back OFF in the Output Buffers. Note that the reset is directly tied to the final buffered output for the case of the charge-based CP. If a state-of-the-art current-based CP was utilized, additional delay would normally be added before both resets. This direct connection for the charge-based CP is reflected in both Figs. 3.11a and 3.14. Proposed PFD Operation in a PLL The implementation of the proposed PFD in combination with the charge-based CP in a PLL is then relatively straightforward as shown in Fig. 3.15: cross-couple the resets, eliminate the Fig. 3.15 Block diagram of the proposed PFD in a PLL. 99 AND gate and traditional delay circuitry found in state-of-the-art PFDs, and connect directly to the charge-based CP. With the charge-based CP, the switches are not the typical large slow opening/closing analog transistors required to flow large amounts of current from the current mirror, but rather minimum sized and relatively quick to open and close to transfer discrete amounts of charge from/to the LF capacitance, CL (e.g. ≪ , ). For a PLL that uses a charge-based CP, there is no added delay requirements (e.g. 0 ) for the PFD as the propagation delay of the switches of the CP are on the same order as the DFFs in the PFD. The timing issue therefore gets mitigated to the actual sizing of the transistors within the DFFs. Notably, the Reset-to- timing constraints now simply become: . (3.16) Figs. 3.16-3.17 display the Up to Idle and Down to Idle waveform characteristics of the proposed PFD in a PLL, respectively. Both examples reflect the new timing constraints. Fig. 3.16 Example of the PFD Up to Idle mode in the PLL. 100 Fig. 3.17 Example of the PFD Down to Idle mode in the PLL. Experimental Results for the Proposed PFD in a PLL The proposed PFD was implemented in a 1-10GHz PLL with the charge-based CP and a ring-based VCO. This PLL was fabricated in an all-digital TSMC 40nm process with a variable supply voltage of 0.5-1.2V. Fig. 3.18 shows the layout and die micrograph of the PFD, CP, and LF portion of the PLL; the PFD, which consists of two DFFs in its entirety, has a total active area of 16µm 2 . The PLL with the PFD was physically tested; the silicon measurements of the PFD are shown in Table 3.2. Notably, the PFD consumes 618.5nW with a 1.0V supply and a reference frequency of 100MHz, where the VCO frequency was 5GHz and a N=50 divider was used to produce the feedback frequency. Furthermore, due to the PFD-CP combination, there is 0ps dead zone, a low 0.1-0.3º phase error, and 0.80±0.05ps jitter for the entire operating range of the PLL. Fig. 3.10 displays an example of the phase noise and spectrum characteristics with reference spurs <-70dBc for this PLL. Table 3.3 provides a snapshot of the PLL performance in which the 101 proposed PFD was utilized; these results are compared to other PLLs which use DFF-based PFDs in their architecture. Fig. 3.18 The proposed PFD and DFF layout and die micrograph. This Work [81] [82] [83] [84] [85] Supply (V) 0.5-1.2 1.5 1.2 5.0 1.8 1.2 Freq. Range (MHz) 10-5000 10-100 50-3000 400-1200 200-1500 1- 2000 PFD Power (W) 618.5n 1.0m 496µ -- 1.4m 37.0µ Dead Zone (ps) 0.0 0.0 61.0 15.0 -- -- PFD Area (µm 2 ) 16 300 -- -- -- -- Technology (m) 40n 0.24µ 0.13µ 0.8µ 0.25µ 0.13µ Table 3.2 DFF-based PFD performance comparison. This Work [81] [86] [87] Supply (V) 0.5-1.2 1.5 1.0 1.8 fVCO (GHz) 1.0-10.0 4.8-5 2.9-9.8 5.27-5.6 fREF (MHz) 50-400 11 29-980 10 PLL Power (W) 1.20m 21.6m 96.0m 19.8m PLL Area (mm 2 ) 0.0040 1.45 0.056 1.610 RMS jitter (ps) 0.80 ±0.05 -- 0.81 -- Ref. Spurs (dBc) <-70 <-70 -54.8 <-70 Phase Error (º) 0.1-0.3 -- -- -- Technology (m) 40n 0.24µ 90nm 0.18µ Table 3.3 Performance of PLLs with DFF-based PFDs. 102 This work has introduced a low power, fast, and compact dual reset D flip-flop based phase-frequency detector design for use in multi-GHz PLLs. The no-added delay PFD design is composed of complex-complementary logic DFFs which were optimized for use with a discrete charge-transferring charge pump by matching the Reset-to- propagation delay to the charge pump’s switching time directly, resulting in zero dead zone between these two blocks. The desirable outcome of using this PFD-CP combination in a PLL is an overall decreased PLL control loop delay and an advantageous reduction in the phase noise and jitter in the PLL, providing a fast, accurate phase lock. Furthermore, the PFD is scalable to and between sub-µm process nodes and is able to be utilized at low supply voltages well below 1V. 3.3 Proposed Voltage Controlled Oscillator Designed with Charge Coupling This section of Chapter 3 presents a novel tunable wide-operating range capacitively phase- coupled low noise, low power ring-based voltage controlled oscillator for use in multi-GHz phase- locked loops. The basic building blocks of the ring oscillator (RO) design are discussed along with a technique to expand the VCO to a variety of phases and frequencies without the use of physical inductors. Improved performance with minimal phase noise are achieved in this ring VCO design through distributed passive-element injection locking (IL) of the staged phases via a network of symmetrically placed metal interconnect capacitors. Using this method, a 0.8-to-28.2 GHz quadrature ring VCO was designed, fabricated, and physically tested with a PLL containing the charge pump and phase-frequency detector from the two previous sections of Chapter 3, respectively, in an all-digital 40nm TSMC CMOS process. 103 State-of-the-Art Ring VCOs Ring oscillators based on digital logic building blocks are a popular choice for multi- protocol phase-locked loops operating in the 0.5-12GHz range due to their minimal area, wide- tuning range, low power consumption, scalability to and between sub-µm technologies, and general lack of required analog process extensions. Compared to tuned, high-Q LC oscillators which target specific higher frequencies at the expense of an increased power and area trade-off, ROs have inferior phase noise performance which restricts their use to only non-critical applications. Specifically, the “resonator” Q of a ring oscillator is low because the energy stored in every cycle at each output node capacitance is immediately discarded, then restored at the worst possible time at the resonator edges instead of at the ideal peak voltage as in an LC oscillator. In general, from a broad perspective, this lack of energy efficiency accounts for the well-known overall poor phase noise performance exhibited by state-of-the-art ROs. Other factors which affect phase noise in both single-ended and differential ring oscillators such as flicker (i.e. 1/f), shot, thermal, and white noise have been extensively studied over the last 20 years [92]-[94]. As IC technology scales to deep sub-µm, numerous works have been dedicated to applying these principles and developing circuitry to improve the performance of ROs in PLLs which operate in the multi-GHz range [95]-[104]. The importance of doing so lies in the inherent non-feasibility of fabricating LC oscillators at smaller feature sizes due to large area and cost as well as the lack of necessary analog extensions being readily available for ultra-deep sub-µm CMOS processes. Among the various practices utilized to lower the phase noise of a ring oscillator operating in a phase-locked loop, two techniques which have been proven successful at smaller feature sizes stand out: 1) using additional injection locking circuitry and 2) exploiting creative, yet strict 104 symmetry in the ring design and physical layout. For instance [100] uses precisely timed IL which yields extremely low phase noise results at frequencies up to 16GHz while [101] presents a unique symmetrical differential RO which can loosely be classified as IL though the use of passive resistors. In [102], IL techniques are applied to an innovative, highly symmetric ring oscillator structure composed of 3 single-ended logic-based rings. In these examples, IL techniques require extra circuitry which may increase the power and/or area. Additionally, symmetry may require extra design time and area. Proposed Expandable, Capacitively Charge-Coupled Ring VCO for PLLs This work uses phase injection locking via a network of symmetrically placed passive metal interconnect coupling capacitors to reduce the phase noise of an inverter-based ring VCO Fig. 3.19. The result of the proposed RO design is a more energy efficient circuit which evenly distributes charge between the various nodes during oscillation. Furthermore, the fundamental basic building blocks of the proposed ring oscillator are discussed in order to provide a straightforward methodology for expanding the design to work for multiple phases and a variety of frequencies in the 0.5-to-30GHz operating range. Using the aforementioned procedure, a 0.8- to-28.2 GHz quadrature ring VCO was designed, fabricated, and physically tested with a PLL in an all-digital 40nm TSMC CMOS process [106]-[109]. Fig. 3.19 Proposed capacitively phase-coupled ring VCO concept. 105 The ring VCO discussed here is designed using a current-starved inverter-based ring oscillator structure. One advantage of using this type of RO is its simplicity. More importantly, rings of this nature can be built using basic circuit elements readily available in any given IC process. In fact, multiple-staged inverter-based ring oscillators are used extensively on practically all silicon dies for process monitoring. However, traditional ROs suffer from two major disadvantages which have limited their usefulness in PLL designs: 1) poor jitter (noise) characteristics and 2) lack of spectral purity (distortion). Here a design approach is presented which takes two or more identical inverter-based staged-ROs and uses phase injection-locking via capacitive coupling to provide a VCO with improved phase noise performance and spectral purity properties superior to state-of-the-art RO designs, making the proposed ring VCO design more comparable to those of LC-based ones. Additionally, the application of the proposed ring VCO offers many other desirable properties beyond low noise attributes including: ability to have precise quadrature with many additional phase outputs available, wide range tunability, inductor-like spectral purity quality and stability without using inductors, full scalability to and between ultra-deep sub-µm IC process nodes, compact physical size with minimal sized inverters, and the ability to work at supply voltages at 1V and below with extremely low power operation due to the capacitors not dumping their energy on a cycle by cycle basis as in a ring oscillator. The building blocks of the proposed ring VCO, shown in Fig. 3.20 include: 1) current- starved inverters for control voltage, VC, tuning, 2) two or more rings, r, made up of a number of odd current-starved inverter stages, s, and 3) relatively small symmetrically laid-out interconnect capacitors, C0=Ceq, to couple the phases of the neighbouring input and output nodes of the rings, 106 Fig. 3.20 Building blocks of the proposed expandable ring VCO. and optionally, 4) a logic-controlled bank of interconnect capacitors, C1-C2, for wider frequency range tuning using transmission gate switches. The simplest unit form of the proposed ring VCO is the single-staged, double-ring differential oscillator Fig. 3.21. If the input is connected to the output of its respective ring with an appropriate impedance, Z, the 2x1 ring will possess a behaviour likened to that of a gyrator in that the capacitive circuit acts inductively due to its structure. This is due to a capacitor in the loop creating a “gyrator” that can masquerade as an inductor which functions as a “dual” circuit element [110]. These capacitors phase-couple the input and output nodes of the stages together forming a distributed spiral virtual inductor. This r=2, s=1 gyrator example is not to be confused with a simple latch where r=1, s=2. In the latter case, the inverters act in series and do not oscillate due to oscillation conditions not being satisfied. The differential gyrator must be strictly cross-coupled in the layout of the circuit and additionally, ZA and ZB must be set appropriately. As expected, from its simplicity, this is the highest frequency configuration. Additionally, the requirements for oscillation can be expedited via sufficient delay through the layout wire parasitics, which are readily found on any chip due to imperfect isolation and slight process variation, and therefore should be used to an advantage in this circuit. Although 107 Fig. 3.21 Single-stage unit for proposed VCO rxs expansion and differential “gyrator” example. exploratory examples of this gyrator point to very high frequencies being obtainable up to 75GHz, the circuit suffers from poorer phase noise performance as compared to multiple stages of s=3 and higher. This is due to the noise being correlated to a minimum number of nodes [94]. Increasing the number of nodes to 3 or 5 significantly improves the performance of the proposed ring VCO. Silicon measurements showing this can be found in the experimental results section at the end of this chapter. The single-stage unit may be easily expanded to a more useful ring VCO which provides multiple phases. The output phases available for the rxs tuned ring VCO may be found at every θ: 360° # 360° ∗ , (3.17) where s is an odd, positive integer representing the number of inverter stages in a single ring; r is a positive integer greater than 1 representing the number of rows. For the ring VCO in Fig. 3.20, there are s=3 ring inverter stages and r=2 rows connected by neighboring node capacitances. θ for this example is then calculated to be 60°; therefore, there are 6 output phases available at 0°, 60°, 120°, 180°, 240°, and 300° in this ring. 108 The frequency of a general rxs ring VCO is governed by the propagation delay of the s current starved inverters in a single ring. The finely-tuned VCO output frequency, fVCO, is controlled by means of Vc, by starving current through either (or both) the top pMOS or bottom nMOS transistors shown Fig. 3.20; in this work, the bottom nMOS transistors were used as the inverters’ current control. The inverters symmetrically self-bias around their midpoint. Additionally, fOUT is also affected by the intentional loading by the tuning capacitor(s) and any switch and wiring path resistance at each node; for instance, increasing the capacitance and/or resistance lowers fOUT. The general output frequency of an rxs VCO may be found by the following equation: 1 1 1 2 2 1 , (3.18) where τpd is the propagation delay of a single current-starved inverter in the ring; Ceq is the parallel combination of the coupling capacitors C0-2 that are in-use; and Req is the equivalent parallel resistance of the wired path and any switch resistance connected to the coupling capacitors in use. Parasitic capacitances, C0, should be factored into this equation for accuracy. This basic rxs ring VCO structure is reconfigurable to allow for a variety of phases (e.g. by adjusting r and s) and frequencies (e.g. by varying the VC for fine tuning and Ceq for course), an example of this will be presented in the next section for the quadrature configuration. The proposed tuned ring 4x3 VCO in Fig. 3.22 is one such expansion of the rxs ring oscillator. In this case, 4 of the 12 phases have been used to produce the quadrature outputs for the PLL. The 3D section of the ring in the upper left of Fig. 3.22 provides a picture of how charge is differentially cross-coupled within the ring through relatively small yet symmetrically laid-out, spirally-linked neighboring interconnect capacitances at every node. The charge coupling path creates a continuous, virtual inductor, adding to the resonance purity of the ring VCO. A capacitor 109 Fig. 3.22 The proposed 4x3 quadrature ring VCO. in a feedback path of the oscillator acts much like an inductor allowing the VCO to operate in a linear (i.e. high-quality sine-wave) mode, similar to an LC oscillator as opposed to a RO which operates in a switching mode. As a result of this virtual inductor in the feedback path, spectral purity (odd harmonics) is comparable to that of LC based oscillators, but this ring oscillator is scalable to deep sub-µm processes and has the added feature of a wide frequency tuning range. This provides low distortion which can be seen in the experimental results section. All of the inverters are operating in concert to produce a single sine wave cycle in precisely equal incremental phase steps. The distributed pseudo-inductor causes the energy lost during a cycle to be restored at the phase angle that adds minimal noise (i.e. jitter), which is the exact opposite of a conventional ring oscillator where energy is added at the most jitter sensitive phase angle. Lastly, the wide operating range of the proposed ring VCO is due to the digital logic-controlled bank composed of 110 Fig. 3.23 VC versus VCO output frequency for the Ceq tuning bank. 3 symmetrically laid-out interconnect coupling capacitors, allowing for coarse tuning over 4 overlapping frequency ranges shown in Fig. 3.23. Experimental Results for the Proposed VCO in a PLL with the CP and PFD This section overviews the silicon measurements of a variety of rxs expansions of the proposed ring VCO structure shown in Table 3.4 and the proposed quadrature 4x3 ring VCO implemented inside a charge pump PLL [106], all of which were fabricated in a 40nm all-digital CMOS process and tested. The block diagram of the PLL which the VCO—along with the CP and PFD from earlier in this chapter—were places is shown in Fig. 3.24. A die micrograph of the proposed 4x3 quadrature VCO in the PLL is shown in Fig. 3.25 and the phase noise and output spectrum are shown in Fig. 3.26. Table 3.5 compares the proposed 4x3 ring VCO results to state- of-the-art examples, while Table 3.6 compares similar PLLs to the one used for this work as is shown in Fig. 3.24 which uses the CP from PFD from earlier sections in Chapter 3. This work has introduced an expandable structure for a tunable wide-operating range capacitively phase-coupled low noise, low power ring-based VCO for use in multi-GHz PLLs. Using this technique, a quadrature ring-based VCO was implemented in an all-digital 40nm TSMC 111 Fig. 3.24 Block diagram of the proposed PLL. Fig. 3.25 Die micrograph of the proposed 4x3 VCO in a PLL. CMOS process. Most notably, the proposed 4x3 ring VCO occupies an area of 0.0024mm 2 , consumes a power of 0.77mW at a 1.0V supply voltage, and possesses a phase noise of - 124.5dBc/Hz at the 10MHz offset for a carrier frequency of 28.0GHz. Furthermore, this work has the widest reported operating frequency range of any published VCO from 0.8-to-28.2 GHz. The 112 VCO FOM is also the best reported for ring-based VCOs and is comparable to that of LC oscillators due to the passively-phase coupled IL symmetric ring topology and inherent low power operation. s r Inv. Size Ceq [fF] θ [º] Phases (rxs) fMAX [GHz] Power [mW] Area [mm 2 ] Phase Noise 70 [dBc/Hz] 1 2 4x 5.0 180 2 75.6 0.55 0.0020 -102.0 3 2 4x 1.0 120 6 27.5 0.52 0.0015 -115.3 3 3 4x 2.5 40 9 25.4 0.69 0.0021 -120.3 3 4 8x 1.0 30 12 28.2 0.88 0.0024 -124.5 5 2 4x 2.5 36 10 13.3 0.95 0.0050 -122.8 5 4 8x 1.0 18 20 16.5 1.40 0.0065 -121.2 7 2 4x 2.5 25.7 14 10.1 1.34 0.0110 -119.6 9 2 4x 5.0 20 18 6.7 1.52 0.0150 -114.9 Table 3.4 Silicon measurements for the proposed VCO configurations. This Work [98] [99] [100] [101] [102] [103] [104] [105] CMOS Technology 40nm 130nm 45nm SOI 20nm 65nm 65nm 130nm 28nm FDSOI 90nm Implementation Pass. IL-Ring Ring VCO Ring VCO IL-Ring Ring VCO Ring VCO Ring VCO Ring VCO LC-IL Frequency Range [GHz] 0.8-28.2 1.0-10.3 1.0-8.5 2.0-16.0 0.6-0.8 0.39-1.41 0.8-1.8 4.0-11.0 19.75-20.25 Output Frequency [GHz] 28.0 1.0-10.3 2.5 15.0 0.8 0.9 1.5 8.0 20.0 Int. RMS Jitter [ps] 0.77 <3.0 0.99 0.268-0.43421.5 1.7 0.4 0.558-0.642 0.085 Phase Noise [dBc/Hz] -124.5 N/A -114.9 -136.6 -124.0 * -124.0 * -145.0 * -116.6 * -150.0 Supply Voltage [V] 0.5-1.2 (1.0) 1.8 1.8/2.5 1.1/1.25 1.1-1.3 0.8 1.1 1.0 1.5 VCO Power (VCO) [mW] 0.65-1.25 (0.88) 8.0 2.0 * 5.0 * 0.51 0.4 * 0.4 * 1.63 * 70.0 * VCO Area [mm 2 ] 0.0024 0.714 0.006 * 0.0025 * 0.027 0.003 * 0.01 * 0.0025 * 0.0325 * Figure of Merit 71 [dBc/Hz] -194.0 -- -178.9 -193.1 -185.0 -187.1 -192.5 -192.5 -197.5 Table 3.5 Silicon measurements and comparison for the proposed quadrature VCO in a PLL. 72 70 Phase noise measurement uses f MAX and f OUT displays value at the 10MHz offset. 71 FOM for the VCO = PN - 20 log (f OUT /f OFFSET ) + 10log (P/1mW); FOM for the PLL = 10log [( σ t /1s) 2 x (P/1mW)]. 72 *Estimation from paper. 113 This Work [99] [95] [101] [102] [111] [100] PLL Type Pas. IL Analog Analog Analog Digital Digital Hybrid IL Digital Frequency Range [GHz] 0.8-28.2 1.0-8.5 0.5-2.5 0.6-0.8 0.39-1.41 1.4-3.2 2.0-16.0 Reference Range [MHz] 10-400 50-450 10-100 2-40 40-350 36-108 -- Output Frequency [GHz] 25.0 2.5 1.0 0.8 0.9 3.1 15.0 Clock Reference [MHz] 250 100 100 26 150 108 -- RMS Jitter, σt [ps] 0.82±0.0275 . 0.99 . 2.36 . 20-30 . 1.7 * 1.01 * 0.268 . Power Dissipated, P [mW] 0.64-1.25(1.08) 70.0 25.0 2.66 0.78 27.5 46.2 FOM [dB] -241.4 . -221.6 . -218.6 . -209.7 . -236.5 . -225.5 . -234.8 . Supply Voltage [V] 0.5-1.2 (1.0) 2.5 1.8 1.2 0.8 1.2 1.25/1.1 Area [mm 2 ] 0.0048 0.277 0.15 0.027 0.0066 0.32 0.044 Normalized Area 1 57.7 31.2 5.6 1.3 66.7 9.17 Technology 40nm CMOS 45nm SOI 0.18µm CMOS 65nm CMOS 65nm CMOS 65nm CMOS 20nm CMOS Table 3.6 Silicon measurements and comparison for the proposed quadrature PLL. Fig. 3.26 Measured phase noise and output spectrum at 28.0GHz. 114 Chapter 4 EXPERIMENTAL CIFET ANALOG BUILDING BLOCK This chapter is dedicated to the author’s most recent research endeavors regarding how to create useful analog circuits, most notably amplifiers, in ultra-deep sub-µm all-digital CMOS processes in order to allow fabrication of analog and digital ICs on one SoC for next generation applications. It includes investigation into the novel complementary injection field effect transistor device, also known as the “CiFET”, which was discovered through research into developing neuromorphic analog circuits [56], [61], [114]-[116]. The CiFET can be utilized as a CMOS building block composed of complementary iFET devices which are a modification of the traditional MOSFET that exploits the transistor's unique charge-based characteristics. Use of the CiFET allows for the manipulation of charge in the channel region to produce a highly linear current-controlled voltage source (CCVS) transresistance, rm, device due to the merging of the MOS sub-threshold and saturation operation regions within the structure. This charge-mode approach is a departure from state-of-the-art VCCS transconductance analog circuits, such as amplifiers, which—unlike the CiFET—are subject to the limitations of a transistor’s intrinsic gain as previously shown in Fig. 2.4e. Because of the unique, yet simple topology of the CiFET, the device is scalable, compact, and can be designed with planar transistors or finFETs with no analog process extensions or special layers for fabrication. The family of circuits developed from the CiFET building block have a range of potential applications, including amplification, mixing, voltage/temperature referencing, analog-to-digital/digital-to-analog conversion, sensing, 115 frequency synthesis, modulation/demodulation, analog filters, switch cap circuits, and fast charge- mode digital logic due to their highly desirable characteristics such as flexibility, low power operation, high gain, linearity, low noise, compact area, and increased speed, without forgetting to mention the full-circle back to the neuromorphic circuit concept. This work will cover the most basic operation and applications of the CiFET. 4.1 Step-by-Step Device Evolution: MOS to Split-Channel iFET to CiFET To understand the CiFET, we now look at the nMOS transistor and compare it to the n- type split-channel NiFET, which will become the lower half of the CiFET device, where the upper half of the device is composed of the complement PiFET. The basic structure and general operation of all three devices is reviewed, in order to reveal that the modifications to the MOSFET—including the ratioed split-channels and bi-directional current input ports—can yield very important and desirable results with huge performance tradeoffs. Review of the Basic MOSFET: Structure and Operation 1) MOS Symbol and Structure Fig. 4.1 depicts the basic symbol and 3-dimensional view of the MOS transistor structure in saturation which was covered previously in Chapter 2. The generic planar MOSFET here is shown with a typical longer/wider channel used in customary analog applications. The FET symbol and structure shown applies to either n- or p- type planar transistors which can further be related and applied to the wrapped-gate finFet structure as desired. Note that the FET has four ports including the gate (g), drain (d), source (s), and bulk (b). Typically, voltage is applied as input to the high-resistance gate port, while a voltage or current may be applied to the physically similar (and interchangeable) drain and source ports. The bulk port is generally attached to the 116 Fig. 4.1 Analog MOSFET symbol and planar 3D perspective. lowest (or low) voltage potential for n-type FETs and highest (or high) voltage potential for p-type FETs to control/prevent forward biasing of the bulk-source junction and to give the lowest Vgs relative to the supply voltage for normal operation (although there are exceptions and special uses for the bulk, they will not be covered here). Additionally, the planar 3-dimentional MOSFET structure in Fig. 4.1 is shown with a wider width, W, and longer length, L, commonly used for analog circuits, along with a channel in the pinch-off saturation region. In order to maintain a high intrinsic gain (see Chapter 2), the MOSFET requires a high output impedance. This is obtained through long channel lengths necessary for high ro=Rout. Since gm is proportional to the W/L ratio of the MOSFET, in order to keep gm high when the channel is long, the channel must also be proportionally wider. Gain here is ~gmRL/Rout. As the IC process shrinks gm increases, but Rout decreases faster, ruling out short channel lengths for analog. This is why as IC processes shrink analog transistors do not scale accordingly in the newest double-digit CMOS technologies. Also, keep in mind that the analog channel current travels close to the surface under the gate where the surface defect carrier traps create the characteristic MOSFET 1/f noise. 117 2) MOS Biased Cross-Sectional View Fig. 4.2a-b displays the cross sectional view of a biased n-type MOSFET in sub-threshold (i.e. weak-inversion) and saturation (i.e. strong-inversion) at pinch-off regimes; these views can also be related to the p-type FET by switching the polarities of the ports and channel charge carriers like that of Fig. 2.23. In sub-threshold operation of the FET the applied voltages follow the rules of Eq. (2.33) where . In Fig. 4.2a, we can see that a thin high-resistance conduction layer of channel charge accumulates above the depletion region much like the thin fog on the top of a lake, where carriers are principally moved by diffusion. It is in the sub-threshold region where the highest gain of the transistor can be observed via the exponential I-V relationship in Eq. (2.33). Increasing the gate voltage increases the amount of fog on the lake providing increased diffusion. On the other hand, when the same FET is placed into the saturation operation regime where the conditions of Eq. (2.31) are followed, namely . The resistance of the source-to-drain channel, rds, (the inverse of the source-to-drain conductance) and the transconductance vary dependent on the applied voltages. For instance, the more voltage that is applied to the gate input of the transistor, the deeper the charge in the channel flows until the point at which the Ohmic region begins and the transistor acts more like a resistor than an active gain device. Recall that these parameters scale also with technology as shown in Fig. 2.4d. Fig. 4.2 Channel charge in a MOS device during sub-threshold and saturation regimes. 118 The square-law gain of the FET in saturation is less than that of sub-threshold biased transistor which follows an exponential law. 3) MOS Basic Operation Plots and Characteristics Corresponding to Fig. 4.2a-b, the I-V drain characteristics are shown for the MOSFET in Fig. 4.3a-b, respectively. For the sub-threshold region, we can see in a Fig. 4.3a, that for very little applied voltage to the gate input (depending on the threshold and drain-to-source voltages), there is an explicitly proportional increase in drain current output which is literally exponential Eq. (2.33). On the other hand, in Fig. 4.3b for the saturation region, for a larger applied input gate voltage, we get a lesser change in the output drain current that is quadratically related via Eq. (2.31). In between these two operating regions, the gate voltage provides a linear change in drain current (Eq. 2.32). Therefore, the gain for a transistor biased in the sub-threshold region is greater and more energy-efficient (in that less voltage must be applied) than that of one in the linear or saturation regions. This is why it appears advantageous for analog IC designers to understand how to utilize the sub-threshold region of the MOSFET for circuits which have low power, high-gain, and/or sub-1V supply voltage requirements. Despite this, analog designers face drawbacks when Fig. 4.3 I-V characteristics of the MOS device during sub-threshold and saturation regimes. 119 sub-threshold circuits are employed. Specifically, in the traditional VCCS configurations (i.e. gate as a voltage input and drain as a current output) which are dependent on intrinsic gain of a transistor. Recall that intrinsic gain scales downward with technology according to Fig. 2.4e. Namely, the limitations of state-of-the-art sub-threshold analog circuits include insufficient output drive, higher noise due to carriers travelling near the imperfect surface where lattice defects reside, and relatively slow operation restricting multi-GHz applications. As a quick review, before moving on, we will review the features of the MOS device in sub-threshold and saturation as compared to the biased iFET. The characteristics of the MOS in sub-threshold in Figs. 4.2a and 4.3a include: 1) very high g m gain as the diffusion driven drain-to-source channel current is exponentially related to the gate voltage due to Eq. (2.33), 2) insufficient drive because the large drain-to-source resistance of the thin channel limits drain current and speed, 3) noisy due to carriers which travel along the top of the thin, uniform channel where surface defects arise, 4) unacceptably slow as low drain current makes driving loads difficult, 5) wide dynamic range useful for both small and large input signals, and 6) useful for low power and sub-1V supply voltage applications. Properties of the MOS in linear region, which corresponds to Eq. (2.32) include: 1) operation as a linear voltage controlled resistance, 2) low output conductance, and 3) voltage gain is a function of R out in parallel with R load . 120 Properties of the MOS in saturation in Fig. 4.2b and 4.3b include: 1) moderate-to-high g m gain due to the voltage imposed source-to-driven channel current being quadratically related to the gate voltage due to the square law properties from Eq. (2.31), 2) moderate-to-high drive due to the input gate voltage which modulates the output drain current, 3) noisy at the pinch-off region close to the surface where carrier velocities are at a maximum, 4) moderate speed dependent on output load and carrier transit time limitations, 5) limited dynamic range when compared to the weak inversion, and 6) generally higher power dissipation and limited in stacked-threshold voltage configurations (see Fig. 2.6c). Split-Channel iFET: Structure and Operation 1) iFET Symbol and Structure Let’s imagine if we take the simple analog planar MOSFET from Fig. 4.1 and cut the channel at some point and insert a current-injection port (i.e. iPort) via a metal/diffusion connection similar to that of the source or drain, all while drastically scaling down with the process node. The result is the split-channel iFET as shown in the 3-dimentional view of Fig. 4.4, where the new symbol of this device is also shown. There now are two channels, the source channel— which is located adjacent to the old source port, and the drain channel—which is located near the old drain port. Exactly where along the original channel that the iFET is cut and the iPort is inserted is referred to as the “iFET channel ratio” of the source channel to the drain channel such that: 121 Fig. 4.4 iFET symbol and 3D perspective with split channel and iPort (minimally-sized). . (4.1) Varying the iFET ratio by either width or length is important for the different applications of the CiFET, which we shall soon discuss. For instance, ratioing the channels affects the MOS operation regions for each of the new interdependent source and drain channels and therefore also the total drain current, inherent voltage at the new unbiased iPort along with its input resistance, the device’s gains, and frequency characteristics depending on how the iFET is utilized. 73 To the first order, the iFET properties are controlled by ratioing is independent of process parameters at each node, as these parametric differences drop out in the ratio of the source and drain channels. In general, only factors of two are needed in iFET device sizing and ratioing thus making sizing inherently compatible with the “one-size-fits-all” of the deeper sub-µm and nanoscale IC processes including finFETs. 73 This concept can be easily related to finFETs by way of connecting the transistors. For instance, if more width is desired (given that only one-size-fits all transistors are given for an ultra-deep sub-µm CMOS technology), a designer will need to connect transistors in parallel, and for increased length, the transistors can be connected in series. Keep in mind that there will be a new charge-mode approach to designing amplifiers discussed later in this section which will not rely on traditional large and bulky planar transistors. Therefore, one-size-fits-all finFETs are perfectly suited to the charge-mode approach as the transistors used are digital-like in appearance and size. 122 Looking at Fig. 4.4 we can observe the basic properties of the iFET. In this 3-dimensional view of the iFET device as a split channel modification of the MOS device we can see that there is a single connected gate which can be used as a voltage bias or signal input. 74 The iPort is a low impedance, bi-directional current signal or charge injection input/output node, reminiscent of the base of a BJT having exponential control and a relatively low impedance to a termination voltage, only the iFET is bi-directional and includes zero current input. The source channel is connected between the source node and iPort while the drain channel is connected between the iPort and the drain node. Depending on how the iFET is biased and the channel ratioing, a designer can force saturation in one channel and sub-threshold-like operation in the other channel. Similarly, a complementary p-type PiFET device can be made from a split-channel PMOS transistor with a similar structure while accounting for the difference in hole to electron mobility as is done by increasing the width as needed similar to normal CMOS IC design (remember for finFETs this can be achieved by connecting devices in parallel). For P to N conductance matching, this n-channel width increase is typically 3-4x for most ultra-deep sub-µm IC processes although 2-3x is normally anticipated at higher process nodes. In today’s CMOS, the IC processes has been optimized for best n-channel operation at the cost of p-channel, essentially relegating the p-channel as an active pull-up device. 2) Biased Cross-Sectional View of the iFET The n-type NiFET in Fig. 4.5 depicts the charge distribution and depletion regions under normal biased conditions where the iFET gate is biased at voltage, Vgs, the drain is biased with a current, Ibias, and loaded with a load capacitance, CL. For a zero input condition the iPort injection 74 Another modification includes the iFET as a multi-gate device where the gates over the source and drain channels are not connected. Here we will only discuss the basic single gate, iFET. Also, for simplicity, we will not show the appropriately-tied bulk (body) node in the iFET symbol. 123 Fig. 4.5 Channel charge distribution in the iFET device during biased operation. 75 current, Iinj, is at zero yielding a steady-state voltage output, Vd, at the drain. The result is a low resistance source channel which results in a low input resistance, Rin, if looking inward at the input iPort 76 . Also, note that the channel charge distribution and depletion region just adjacent to either side of the iPort is exactly the same—both sides of the iPort have the same gate and a common iPort diffusion. The iPort voltage is derived from the difference between the Vgs of the source channel and the drain channel Vg-iPort voltages. This forces a low voltage across the source channel—between the iPort and the source diffusions. This iPort voltage is setup by the voltage divider’s difference between the drain channel resistance and the source channel resistance which is being christened as the all-important “iFET ratio,” which is the defining variable of the iFET. When the drain channel is lower resistance or wider than the source channel, there is an easily identified voltage difference from lower current density in the in the drain channel to the current density in the source 75 This is enhanced further by widening the source channel so that it is greater than the nearly minimum-sized drain channel. Doing so will alter the input iPort impedance for obtaining a matched input if desired. 76 R in at the iPort is the larger 1/g m of the drain channel in parallel with the low resistance r ds of the source channel. Therefore, R in ~ low resistance of the source channel. 124 channel because the same current is distributed over the wider drain channel, thus has a lower current density similar to that of band-gap references. In fact, this is a handy reference voltage is a PTAT (Proportional To Absolute Temperature) reference voltage for NiFETS and a CTAT (Complimentary To Absolute Temperature) for PiFETS providing a low resistance pair of reference voltage sources (see Appendix E, particularly Fig. E.2). This iPort voltage performs the task of a cascode bias voltage, which in this case is on the iPort source-like terminal instead of the gate of the cascode output FET. Thus the drain channel performs the low output impedance task of a cascode pair’s output transistor without any additional parts or bias voltages (self-biased). With a zero (no) iPort injection current, the exact same current is passed through both channels. When current is injected into or removed from the iPort, the voltage between these two channels is disturbed in accordance with the sum of these channel resistances producing a proportional voltage change on the drain (which can be seen as the transresistance, rm). The effective series resistance of these two channels produce the high transresistance (i.e. transimpedance when considering the frequency component such as for matching) gain which looks like the input current has gone through the higher rm resistance instead of the lower RiPort resistance, only it has been buffered by the drain channel’s cascade output channel to provide a low output impedance which is highly desirable for driving varying loads without incurring parasitic induced errors. The disturbance is the equal to the iPort input current being incrementally applied to the iPort input resistance. Due to the iPort voltage being defined by the difference between these two Vgs and the Vg-iPort operating voltages, the iPort voltage changes very little, thus the iPort has a low incremental input resistance while the drain output changes a lot and is voltage-buffered by the low impedance of the self-cascoding drain channel. 125 When the iFET ratio is reversed by making the source channel lower resistance (wider) than the drain channel, the iPort voltage is squished down to near zero making the iPort input resistance very low. Due to this input resistance being created by the iFET ratio, it is a fixed constant resistance which is useful for matching transmission line resistances. Extra wide source channels yield extra low iPort termination resistances. Due to this resistance being set by the passive iFET ratio this resistance remains constant through RF frequencies and has a negligible dependence on IC process parameters. Since the iPort input resistance is constant, the iPort input current can be converted to voltage by Ohms law for analysis, but this masks the operational visibility obtained through charge-mode insights. The iPort inputs are externally driven by current sources that have high output impedance and a high compliance that decouples the external current signal source from the iFET iPort input which is locally referenced to the iFET source terminal. In addition, multiple input currents can be summed by simply wire-ORing them (see Appendix E, Fig. E.8). Due to the current input signals being fed to a relatively low impedance, there is little change in interconnect signal voltage making these inputs immune to typical parasitic capacitance loading and virtually eliminates the dominant AC power dissipated from the signal transitions. Keep in mind that these current inputs are also fully bidirectional. Another interesting property of the iFET is that there is no inversion or phase delay between the iPort input current and the drain output voltage. In this respect, the simple iFET device acts much like a common-gate amplifier configuration. Most important, however, is that the voltage across source channel between the iPort and source is clamped to a very low voltage while the gate voltage is forced high by a gate bias which is tied to the drain in the case of the later-described CiFET self-bias scheme, which explained in the following sections. This causes an abundance of 126 carriers in the source channel, which is termed “super-saturation.” This is likened to a thick dense fog on a lake where the water droplets (carriers) are moved by diffusion rather than wind (voltage) across the surface of the lake. In this analogy when fog is added, some of the abundance of fog is pushed off the ends by diffusion. The carriers do not have to be moved across the metaphorical lake, but only need to push on their neighbors to displace some carriers off the end—a charge- mode design insight. This is considered an exponentially-controlled property, which is weak- inversion on steroids—just what the doctor ordered. It yields weak-inversion like gains, but at very low impedances for all the speed desired. In fact, the speed is not limited by carrier transport from one end of the channel to the other as with velocity saturation, but the analog signal theoretically travels with a speed approaching that of light. As a side note, when the n- and p-type iFETs put together as discussed in the upcoming CiFET section, the individual complementary iFET drain channels are also operated with an abundance of carriers. Thus the terminal speed of the CiFET is relatively very fast when compared to a typical analog MOS device. The CiFET’s gain characteristics are also process independent on the first order as a result of the iFET ratio. Because the carriers do not move significantly, they do not travel the surface where they get caught in carrier traps—the primary source of MOSFET noise which is 1/f in nature. Also, the low resistance of the super-saturated channels has the minimum possible resistance generated noise. 3) iFET Operation Plots Figs. 4.6a-b displays the biased CCVS iFET device operation plots with and without iPort injection current for the source and drain channels from Fig. 4.5. Figs. 4.6c-d are the same plots, with inversed axes for a better visualization of the iFET output/input (i.e. Vds/Id) behavior. Note that in Fig. 4.6b and the inversed Fig 4.6d, that very little change in drain current (due to the 127 Fig. 4.6 Combined I-V/V-I characteristic views of the iFET device with and without input iPort injection current. 128 addition of a small iPort current) gives large gains in drain-to-source voltage (this is better visualized in Fig. 4.6d via interchanging the x and y axes). This is the converse or dual of a normal VCCS use of the MOS device where large changes in the drain-to-source voltage yield minimal changes in the drain current during saturation as shown in Fig. 4.3b. This gives an analog IC designer insight as to the usefulness of the iFET as an amplifier which does not require a typical large, bulky analog planar transistor for the needed transconductance to obtain gain. Instead, the NiFET in a CCVS configuration uses transresistance to boost the gain of the MOS-based device to new heights: ∆ ∆ ∆ ∆ . (4.2) Observing the biased iFET device example and operation plots in Fig. 4.4-4.6 we can see that this device has a combination of MOS characteristics in sub-threshold (source channel) and saturation (drain channel) when the input is at the iPort and the output is at the drain channel node. The source and drain channel depths and depletion regions in the iFET are dependent on the magnitude of gate voltage applied (which, in the source channel example, can push the channel current deeper than of the sub-threshold=linear regimes); whereas the shape of the channel (e.g. even in this case), is attributed to the difference in voltage across the channel, which is relatively very low to almost zero and the relatively higher gate voltage. 129 A general summary of the attributes of the basic iFET device include: 1) high, exponential transresistance gain 77 as a very small change in input current at the iPort delivers a substantial change in voltage at the drain channel output, 2) nearly load-independent drive as the iPort injection current facilitates all the necessary drain current to reach desired output drain voltage virtually independent of the load and parasitics, 3) lower noise as the carriers travel deeper, away from the surface defects in the low resistance modified sub-threshold and saturation combination regime, 4) high speed from highly saturated channel diffusion carrier transport and low impedance voltage output which is nearly load independent, 5) extreme dynamic range which allows the iFET to work with small or large input current signals while allowing the output voltage to swing within the full power supply if desired, and 6) high parametric tolerance to process and temperature variation. 77 The transconductance of a MOSFET is the ratio of the change in drain current to the change in gate voltage over a defined, arbitrarily small interval on the drain-current-versus-gate-voltage curve: The transresistance is the ratio of the change in iPort current to the change in output voltage for the iFET. For the CiFET, the transresistance gain factor, r mp adds to the r mn from each channel if utilized, as the transresistance has additive properties. For example, on the 4-input differential CiFET in Fig. 4.24, the gain is essentially a quadrupling to 4*r m if all iFETs are sized correctly. 130 3) A Few Important Notes Regarding the iFET Device: Ratioing the Symbol The generic iFET symbol is an enhancement of the conventional MOSFET symbol, which includes the iPort terminal connecting to the channel directly. This iPort is placed near one end of the MOSFET channel signifying that the iPort is electrically closer to one end of the pair of iFET channels than the other, as defined by the iFET channel ratio. 78 When using the iFET for ratios <1 it is more perceptive to instantiate this symbol with the source and drain reversed; MOSFETs , on the other hand, in comparison, can be used either way. A low iPort input impedance application (i.e. a “high” iFET ratio) instantiates the symbol with the iPort near the power supply source side (as shown later in Fig. 4.24), while a high-gain application instantiates the iFET symbol with the iPort near the output of the circuit (as shown later in Fig. 4.17) which takes advantage of the self- cascoding properties (i.e. a “low” iFET ratio). That leaves the lesser used 1:1 ratio application instantiation up for grabs, so therefore, as a default, in this case let’s revert to the high iFET ratio case—if that 1:1 ratio ever happens. To denote the PiFET device, the bubble convention can be used as is normal for digital CMOS IC design to differentiate from the NiFET. 79 Examples of these iFET symbols are shown in Table 4.1. Fig. 4.7 depicts the top view of the generic planar iFET with longer drain (for lower Rin) and source (for high rm) channels respectively. 78 The general default iFET ratio used is 4:1 (source channel is 4 times stronger than the drain channel) and can be optimized with any ratio as illustrated later in Figs. 4.15-4.16, normally going from a ratio of 1:1 and up seen as going from 1 to the right in these figures. Note that the ratios illustrated also go from 1 and down to the left in those plots. 79 If desired, a small dot near the source channel of the iFETs (both P and N) can also be used (similar to the arrow in the direction of the drain current convention for traditional analog MOSFETs—which is also acceptable). This convention is not mandatory, as it is only done for a designer’s convenience 131 iFET Symbol Convention Basic Description Example Sizing Importance in CiFET NiFET n-type iFET - Drain channel: W min /2xL min - Source channel: 2xW min /L min Lower half of the CiFET PiFET p-type iFET - Drain channel: 4xW min /2xL min - Source channel: 8xW min /L min *(PiFET is 4xNiFET) Top half of the CiFET NiFET (longer drain channel) iFET with longer drain channel - Drain channel: W min /2x L min - Source channel: >>2xW min /L min - Allows for lower input iPort resistance (for matching and high frequency uses) - Useful for current input amplification such as in the CiTRA/CiTIA NiFET (longer source channel) iFET with longer source channel - Drain channel: 4xW min /L min - Source channel: W min /2x L min - Allows for higher input iPort resistance (for high gain uses) - Useful for voltage input amplification such as in the CiAmp Table 4.1 Various useful conventions for the iFET symbol. Fig. 4.7 Top layout view of the generic planar iFET source-to-drain channel ratioing for a) longer drain channel and b) longer source channel. 132 Finally, it can be noted that the iFET device indeed has similarities to the common gate amplifier from Fig. 2.27c in the basic CCVS configuration. The crowning step is adding the complement ½ circuit p-type iFET, the “PiFET”, to the ½ circuit n-type iFET, the “NiFET.” With this step, we create a new foundational analog building block. This complementary iFET device is dubbed the “CiFET”. The CiFET Device The CiFET device is the combination of complementary iFETs placed together as shown in Fig. 4.8. This is the seminal cell for the CiFET family of circuits for analog and digital applications. The device has connected gates where a bias or signal voltage input, Vin, may be applied, two bi-directional current injection input/output iPorts, and a voltage output, Vout. Fig. 4.8 The CiFET seminal cell. 133 1) Biased CiFET 3-Dimensional Structure and Cross-Sectional View The CiFET device’s 3-dimensional and cross-sectional views are shown in Fig. 4.9. In the 3-dimensional structure there is a single DC voltage bias input attached to both gates of the NiFET and PiFET devices. The source of the PiFET is connected to the supply voltage and the source of the NiFET is connected to ground. Note that the four separate source and drain channels of both iFETs are all in series. In this specific example, due to ratioing and applied biasing, the source channels are in the super-saturated region (e.g. NiFET drain channel operation case when the voltage at the input Vg > Vd at the NiPort) and the drain channels are in saturation. There are two separate complementary current input iPort sites in the middle of either iFET. There is one single voltage output sight between the NiFET and PiFET drains. For simplicity, the iFET ratio is 1:1 of this example. Fig. 4.9 Biased planar CiFET 3-dimentional (top) and cross sectional (bottom) views. 134 A Note on Ratioing of the CiFET Source and Drain Channels To provide a feel for the default sizing and general physical configuration of the CiFET compound device, a pair of generic physical layout examples are given in Fig. 4.10ab for both the (a) iPort low input resistance (Rin) CiFET which has longer drain channels and (b) the high rm gain application which has longer source channels. For this example, the complementary p-channel iFET is 4 times the width of the n-channel in this typical configuration (unlike Fig. 4.9). From experience, most CMOS process nodes need approximately a 3:1 or 4:1 increase in width to ~match in conductance at the sweet-spot ~1/2 scale voltage from the optimised IC doping concentrations (as illustrated in footnote 35). This 4:1 p-to-n channel relationship works well for finFET’s one-size transistors, as in order to increase the width, finFETs in parallel are utilized and to increase the length, finFETs in series are connected. Also, the default 4:1 or 1:4 iFET transistor ratios are accounted for in these planar views of the layouts. Other ratios can be utilized, but for this work, the 4:1/1:4 ratioing is utilized for simplicity and balancing for device linearity. Fig. 4.10 Top layout view of the planar CiFET source-drain channel ratioing for a) longer drain channels and b) longer source channels. 135 2) Comparison of the CiFET to a Two-Finger CMOS Inverter For comparison, a basic two-finger CMOS inverter circuit is shown in Fig. 4.11 while its mid-biased (i.e. at ½ Vdd, the “sweet-spot”) 3-dimensional and cross-sectional views are shown in Fig. 4.12. Note that in this circuit, unlike the CiFET, the inverter has two fingers in parallel for each nMOS and pMOS transistor while there is one connected gate input. This eliminates the ability of the inverter to have the isolated iPorts on either transistor for current injection like the CiFET. For this particular example, note that the p-channels are not sized “correctly” based on hole-to-electron mobility; rather the nMOS and pMOS transistors are sized 1:1 for comparison reasons to Fig. 4.9. Additionally, when biased at the “sweet spot”—which is approximately equal to half the supply voltage—the inverter’s channels are all in saturation as is shown in Fig. 4.12. Fig. 4.11 Two-finger CMOS inverter circuit. Fig. 4.12 Mid-biased two-finger CMOS inverter 3-dimentional (top) and cross sectional (bottom) views. 136 All other connections are identical to the CiFET. The gates of each transistor are tied together for the voltage input. The source of the nMOS is connected to ground and the source of the pMOS is connected to the supply voltage. The drains of the complementary transistors are connected at the voltage output. Although the stand-alone MOSFET is a charged-based device, the inverter logic configuration is a voltage-in voltage-out circuit, which can technically be classified as voltage-mode. These attributes highlight the difference between a basic CMOS inverter and the CiFET device. 3) CiFET Device Characteristics The CiFET is a flexible seminal cell which can be used as a building block for a wide variety of configurations and circuits. For instance, the NiPort may be used as a current input while a voltage output may be taken at Vout. In this approach, the cell is a CCVS circuit, where the gain factor is based on the transresistance as defined in Eq. (4.2). If both iPort sites of the CiFET are utilized as a current input, the gains add from the PiFET and NiFET, such that 80 : 2 . (4.3) 81 To demonstrate the CiFET transresistance characteristics, a simple single stage amplifier with replica biasing made out of another self-biased CiFET is built and shown in Fig. 4.13. In this circuit example, the biasing voltage, Vbias, and the iPort “offset” voltages are set by the combination of two factors for a given supply voltage: 1) the ratioing the complementary iFET W/L channels, and 2) sizing the PiFETs with the appropriate multiplication factor that accounts for the hole-to-electron mobility differences in the same way pMOS is typically done for CMOS 80 The additive gains equal 2r m only if r mn and r mp are made to be the same via ratioing. 81 Assuming that the complementary iFETs are sized appropriately regarding mobility and ratioed correctly (see Table 4.1 for example sizing). 137 Fig. 4.13 Biased single-stage CiFET transresistance amplifier. logic gate sizing. For example, ratioing the complementary iFET source and drain channels results in the varying of the P- and N- iPort node voltages as is shown in in Fig. 4.14. This action also alters the input resistance, Rin, as seen at either of the iPort current input terminals, which is useful for impedance matching if desired. Consequently, this also increases or decreases the transresistance gain as was described previously in Table 4.1. 82 For instance, increasing the input resistance via ratioing results in massive gain for a smaller given circuit footprint. This is wonderful news for the scaled devices as it is not subject to the intrinsic gain like state-of-the-art amplifiers (see Fig. 2.4e). On the other hand, matching to a lower resistance for Rin for increased signal energy input has the tradeoff of a moderate gain for a larger circuit area. 82 The combined series resistance of all four CiFET channels sets the total bias current through the CiFET. Due to the small CiFET compound structure, the bias current is small, but is intentionally operated at a high density to yield maximum performance and minimum noise. That is, the CiFET operates with a maximum available current in combination with minimum capacitive parasitics for speed; and the high current density is driven away from the surface defects, along with a minimum resistive noise component for a given power. 138 Fig. 4.14 NiPort/PiPort voltages versus source/drain iFET W/L ratios. In Fig. 4.15, an example of the V-I transresistance gain characteristic of the circuit in Fig. 4.13 is shown. For a very small change in input current at either iPort, we get a large increase in voltage on the output. This plot is a log-log scale depicting the constant linear transresistance gain of rm-total=100,000 where the CiFET ratio used was 4. For the default high gain CiFET ratio of 0.25, this transresistance gain factor is 1.5 million, and for a 50 Ω matched Rin, the ratio is 64 for a transresistance gain factor of 5000. Furthermore, if we use either of the iFET’s source channels as an impedance matching element via ratioing, we can see the direct relationship this modification has on the transresistance gain in Fig. 4.16. 139 Fig. 4.15 Biased single-stage CiFET transresistance amplifier V-I characteristics. To the first order, the gain, input resistances, and iPort voltages are set by the iFET Ratio and not the IC process parameters, making CiFET based circuits relatively IC process independent thus maximizing portability of CiFET based analog intellectual property. Table 4.2 summarizes the iFET and CiFET device characteristics with a comparison to historical active devices. The desirable linear, high gain transresistance properties, simple low power biasing, and ability to easily match iPort input to the source impedance, making the CiFET device a useful building block for analog applications. In the next section, novel examples for the uses of the CiFET are given, particularly for amplification. Additional CiFET circuit examples and analysis on the CiFET impedance, frequency response, and basic noise profile may be found in the Appendices. 140 Fig. 4.16 CiFET input resistance (real impedance) and transresistance versus W/L ratios. 141 Device Innate Control/ Source Primary Design Technique Classification Input Impedance 83 Output Impedance Governing I-V Relationship Gain Factor Triode VCVS Voltage-Mode High Low 3/2 Power Rule µv [-] BJT CCCS Current-Mode Low High Exponential βF [-] MOSFET 84 VCCS Transconductance/ Charge-Mode High High Square Law (saturation/linear) Exponential (sub-threshold) gm [ Ω -1 ] iFET CCVS Transresistance/ Charge-Mode Low Low Exponential (source channel) Square Law (drain channel) rm [ Ω] CiFET CCVS Transresistance/ Charge-Mode Low Low Additive Linear 85 (due to complement) rmn + rmp [ Ω] Table 4.2 Comparison of the iFET and CiFET attributes to that of other active devices. 83 Vacuum tube input impedance taken at grid; BJT input impedance taken base; MOSFET input impedance taken at gate; CiFET input impedance taken at iPort. Vacuum tube output impedance taken at plate; BJT output impedance taken collector; MOSFET output impedance taken at drain; CiFET output impedance taken at CMOS drains. 84 The common-gate configuration for the nMOS may also be classified as a CCVS. The CiFET is at heart a common-gate circuit, yet it utilizes the complementary pMOS transistor to make for a more versatile building block as compared to the common-gate nMOS. 85 The CiFET is ultra-linearized because the complement aspects cancel out the non-linarites from each of the ½ circuit, opposite polarity PiFET and NiFET portions. For example, this is due to these steps happening simultaneously: 1. First, note that the CiFET gate is tied to the drain output to establish a constant self-biased voltage, therefore the current running through the NiFET and PiFET must be same. 2. If we change one of the iPort currents, say on the NiFET by 1pA (inward), that current change is subtracted from the NiFET drain channel current. Therefore, this same change is also reflected in the current running though the complementary PiFET. 3. The current into the NiFET iPort goes through its source channel and that produces an exponential voltage change on the iPort node due to the sub-threshold operation. This exponential voltage change is immediately applied to the drain channel, which is acting like a common gate amplifier configuration, which follows the saturation regime’s square law. 4. These changes get applied automatically to the complementary PiFET because its current is the same as the NiFET’s drain channel (due to the constant gate voltage). This complementary action cancels out the exponential and square law non-linarites, and produces an ultra-linear relationship between the output voltage and the input current, which can be observed in the gain factor, r m . The phase inversion is derived from the opposite diffusion type instead of some other circuit. The CiFET therefore can be viewed as a fast “current inverter” as it is a current-inverting circuit (as opposed to a normal voltage-inverting CMOS inverter). The author’s future work involves looking into uses for this type of circuit including developing fast CiFET digital logic and neuromorphic circuits. 142 4.2 The CiFET as an Analog Building Block The seminal CiFET cell shown in Fig. 4.8 may be used as a building block for both analog and digital circuits. This section highlights the initial investigational structures for amplification that have shown usefulness in deep sub-µm CMOS processes. CiAmps: Multi-Staged Single-Ended Voltage Amplifiers The CiFET can be built into multiple stages creating high gain voltage amplifiers, called CiAmps. For example, in Fig. 4.17, single-ended 2-stage, 3-stage, and 3-stage feed-forward CiAmp can be constructed. Each of the arrangements do not use traditional power hungry analog current mirrors or state-of-the-art bulky analog transistors for gain. Instead, the CiAmps are self- biased and can be made out of multiples of relatively small digital-like sized CMOS transistors, Fig. 4.17 Examples of staged single-ended CiAmp voltage amplifiers. 143 including finFETs. Furthermore, the CiAmp is a scalable voltage amplifier which can be readily utilized in switched capacitor circuits as shown in Fig. 2.31-2.32, thus enabling a large variety of useful analog circuits including filters (e.g. integrators, resonators, bandpass, lowpass, etc.), comparators, ADCs, and DACs to be fabricated in ultra-deep sub-µm CMOS technologies, which has not been feasible previously with state-of-the-art SC approaches. In feedback systems, generally high-gain amplifier outputs are tied back to inverting inputs. Let’s take the simple case that the amplifier is made up of a single CMOS inverter like that of Fig. 4.11, with the addition of feedback from the voltage output to the voltage input. This could be a resistor, capacitor, inductor, or even a voltage source. In analog terms, this inverting circuit will always have a 180⁰ phase shift which is considered unconditionally stable. When the output goes up (high), the inverting input pushes the output back down (low) through its feedback (which innately has a RC delay association). Quickly, this circuit will try to reach a stable input voltage bias point, christened the “sweet-spot”, based on the resistive divider formed by the sizing or conductance of the pMOS and nMOS channels. Unfortunately, a single-stage CMOS inverter amplifier does not have sufficient gain to be used effectively. When a second inverter is added (with the feedback connected from the voltage output to the voltage input again) the phase shift becomes 360⁰ making the circuit latch undesirably against one of the power supply rails. Making the open-circuit amplifier with three identical inverter stages provides a phase shift 540⁰, which is an attempt to regain the desired 180 ⁰ inverting circuit (i.e. 360 ⁰ + 180 ⁰), but instead of an inverting amplifier, the closed-loop amplifier configuration (with the feedback connected from the voltage output to the voltage input again) becomes a ring oscillator like that discussed in Chapter 3.3 (e.g. 120 ⁰+120 ⁰+120 ⁰=360 ⁰). Conversely, using three non-identical inverter stages 144 in the closed-loop amplifier changes the delay unequally at each node with uneven bias points (e.g. 110⁰+120 ⁰+130 ⁰=360 ⁰). Now if the feedback is arranged to connect between only one or two of the inverting, varying delay stages to make a closed-loop amplifier, it is possible that the oscillation issue can be overcome while providing adequate gain. For instance, at 30 ⁰ short of 360 ⁰ (e.g. 330⁰), there is generally enough phase margin for stability in that the amplifier will overshoot, but is not prone to oscillation. The overshoot can deliver the desired output quickly where the voltage output will ring out with an exponential decay (when driven with a step input like that of Figs. 4.22-4.23). An interpretation of this is where the dominantly slow stage consumes 180 ⁰ of the phase shift, leaving the remaining phase shift to be the sum of the other stages, whether it be two or four or six more stages. If any two of the three inverters are extremely fast as compared to the third, the circuit will act like the single slow inverter, thus the circuit is dominated by the delay of the slowest inverter stage, but still has the high composite voltage gain, which is established by multiplication of all the individual stage gains: ⋯ . (4.4) This is desirable for the staged CiAmp circuit in Fig. 4.17 because we want it to look like a single inverter, as then it is unconditionally stable. For example, this slowing down can be done by increasing its effective Miller capacitance 86 at any stage, by shunting the Miller capacitance with 86 Miller capacitance, C M , is due to the Miller Effect where it states that there is an increase in capacitance from the input to the output for an inverting amplifier such that: 1 , where C F is the feedback capacitance and A vi is the inverting gain (i.e. -A vi ). In a MOSFET-based amplifier such as the common source configuration of Fig. 2.27a, there is the Miller Effect such that C F = C gd where C gd can be referred to the input by 1+A vi . At the input, 1 has the effect of increasing the input capacitance with gain which leads to a smaller bandwidth of the circuit. Cascode topologies, on the other hand, have the ability to cancel the unwanted Miller Effect. 145 a fixed capacitor which is connected from an inverter output to its input, which inadvertently affects its delay. Ideally, a middle stage is best because it doesn’t alter the gain and noise of the first stage or weaken the output drive of the last stage. This solution places a capacitor from the output to the input of the desired slow stage CMOS inverter. There are three problems with this strategy: 1) the capacitor would be physically too large (>10pF), 2) in order to establish the appropriate RC time constant, an extra well-defined resistance would have to be placed in series with this capacitor 87 as there is no identifiable fixed resistor in series with this capacitor, and 3) the recovery from a transient overload of the circuit would take too long to recharge the capacitor to its operating point. Therefore, a different approach is taken to make a scalable and compact amplifier using the flexible, multi-input CiFET seminal cell from Fig. 4.8. This approach is shown in Fig. 4.18 where a roll-off capacitor, Croll-off, is placed between the voltage output of the second stage and fed into the input iPort of the first stage. The iPort has a fixed Rin resistance set by the ratioing of the CiFET (see Fig. 4.16), thus establishing a predictable fixed series resistance as required for the RC time constant. Since the input at the iPort has transresistance gain from the first to the second CiAmp stage’s voltage output, the added roll-off capacitance is multiplied by rm making Croll-off small (~100fF) which will recharge quickly from an overdrive. Also, if the power supply voltage or IC parameters change/modify the CiFET ratio, the gain of this CiAmp circuit in Fig. 4.18 will automatically self-adjust its effective RC time constant. This is because the transresistance gain, 87 There would still be resistance here without the addition of an extra resistor, but the issue is that it would be changing values and not fixed for the RC time constant. 146 Fig. 4.18 Miller capacitance augmented by a CiFET. rm, is proportional to Rin (see Fig. 4.16): a higher rm gives a higher Rin. Therefore, temperature or any process variations, such as individual voltage threshold shifts in the transistors, are innately self-compensated for without any extra circuitry or power usage. Additionally, Croll-off is split into 2 separate capacitors and placed between the complementary iPorts to balance noise and dynamic response maintaining symmetric response for the CiFET-based circuit. At some tradeoff with reduced gain (shown in Fig. 4.19 from 160dB to 145dB at a 1.0V power supply) and increased speed (shown in Fig. 4.20 from 1GHz to 3GHz at the same 1.0V power supply), an extra “feed-forward” inverter can be tied in parallel with this 3-stage ring-like CiAmp creating the “3-stage feed-forward CiAmp” as shown in Fig. 4.17. This parallel-connected inverter gets the amplifier output going in the correct direction at a fast inverter speed. A little later in time during the circuit operation cycle, defined by the slow inverter stage, the 3-stage CiAmp circuit comes in and performs a fine adjustment on the signal for accuracy. This transition from the fast to the slower high gain can be observed as a handover in output slope between these two gain paths. 147 The CiAmp is self-biased and uses no traditional current mirrors. In fact, the CiFET stages provide a very high gain due to their self-biased cascoding properties where they operate like a cascoded pair of transistors, yet with no extra voltage bias. The natural (or termination) voltage at the iPort becomes the cascode bias supply, but it is on the source (iPort) of the drain channel of the respective complementary iFETs, instead of an independent gate for bias voltage, like that of traditional cascode configurations. That is, a traditional cascode device requires an extra bias voltage source, whereas the circuit in Fig. 4.17 is entirely self-biased. Furthermore, the CiAmp configurations are not limited in terms of speed due to velocity saturation like traditional amplifiers. The super-saturated channels (see Figs. 4.5 and 4.9) transmit current predominately by diffusion rather than carrier transport. In other words, the electrons do not have to transverse the entire channel length, but rather have to only push on the adjacent electrons in order to knock an electron off the end of the drain channel (see the Appendices for more insight and musings on this topic). This in turn provides the low output impedance, which adequately drives CiAmp loads along with any additional parasitics. Fig. 4.19 displays the voltage gain of the two 3-stage CiAmps from Fig. 4.17 over extended supply voltage in all-digital 40nm CMOS. Note that there is a peak voltage gain for both amplifiers in the 600mV-800mV power supply range, clearly indicating that the CiAmp is not bounded by threshold voltages, and its highest gain is delivered when the source and drain channels of the complementary iFETs in the circuit are in the exponential sub-threshold regime. For instance, the highest gain for the 3-stage CiAmp is 160dB (100 Million, equivalent to ~28 digital bits) at a supply of 1.0V where the CiAmp has a bandwidth of 1GHz, while consuming less than 1.0µA which is a 1.0µW power dissipation. The CiAmps have the ability to work at very low supply voltages far below 1V with ample gain and a low output impedance, which has the ability to drive 148 Fig. 4.19 3-Stage CiAmp supply voltage versus voltage gain plot. a stiff load while maintaining accuracy at the cost of the load current. Recall that fundamentally, the CiAmp parameters are set by iFET ratio and not the IC process parameters. The CiAmp gain resulting from rm is controlled by the relative source/drain CiFET channel ratios as plotted in Fig. 4.16, which is not a primary function of IC process scaling. A wide power supply voltage range of 100mV to 1.8V (CMOS IC process permitting) characterizes the wide range available gains. For the same minimal size 3-stage CiAmps from Fig. 4.17 designed in all-digital 40nm CMOS, we can see the tradeoff between the bandwidth for a given supply voltage in Fig. 4.20. In this case, we can see that with a supply voltage of 1V, the feed-forward CiAmps have the ability to reach in the lower multiples of GHz with gains in excess of 140dB (10 Million) as shown for corresponding gain from Fig. 4.19. Fig. 4.21 displays the supply voltage versus power consumption and current for the 3-stage feed-forward CiAmp. For example, at a voltage supply of 1.0V the power is approximately 1µW at 1GHz operating frequency. 149 Fig. 4.20 3-Stage CiAmp supply voltage versus frequency plot. Fig. 4.21 3-Stage Feed-Forward CiAmp supply voltage versus power consumption. 150 This very low power operation along with high speed is due two reasons: 1) the minimum parasitic capacitance due to the attributes of the digital-like, minimally-sized transistors that make up the CiFET and 2) having a maximum current density within the CiFET to charge those capacitances, while the total current is relatively small because of the small device sizes. Fig. 4.22-4.23 show examples of the dynamic range of the 3-stage feed-forward CiAmp (from Fig 4.17) which amplifies signals as small as 1µV up to 1V with superb linearity illustrating a dynamic range of over six decades which is 1 million-to-one. A square wave response provides a good estimate of the performance of the amplifier. The rise time reflects the RC time constant of the circuit (note: π*τ = π*RC = ~10-90% rise time), the overshoot indicates the phase margin which can be adjusted with Croll-off, and the voltage gain is proportional to how close the output signal gets to the target output voltage. These features make the CiAmp circuits desirable for low power, low voltage applications in all-digital ultra-deep sub-µm CMOS processes where high voltage gain and wide bandwidth is desired. Additional data and plots regarding the CiAmps may be found in the Appendices. If substantial gain at increased multi-GHz operating frequencies or input impedance matching is desired, the differential transresistance CiFET amplifier discussed in the next section is another great example of the capabilities of the CiFET as a building block. 151 Fig. 4.22 3-Stage feed-forward CiAmp transient plot with input displacement (green-dashed) forcing +/- 1.0V step output (red-solid). 152 Fig. 4.23 3-Stage feed-forward CiAmp transient plot with input displacement (green-dashed) forcing +/- 1.0µV step output (red-solid). 153 Differential CiFET Transresistance/impedance Amplifiers (CiTRA/CiTIA) The seminal CiFET cell can be used for impedance matching much like a common gate, input-to-output 0 ⁰ phase shift trans-impedance amplifier (TIA), yet with a much higher multi-GHz frequency response and ability to scale due to its unique structure in the CiFET transimpedance or “CiTIA” CCVS configurations. When a CCVS configuration of the CiFET is utilized for transresistance gain (and not specifically for impendence matching), the amplifier is dubbed a CiFET transresistance amplifier or “CiTRA”. Although the structures are similar, the subtle difference resides in that a CiTIA is sized for matching/maximum input power transfer and the CiTRA is sized for optimum gain. One example CiFET structure for this dual CiTRA/CiTIA application is the self-biased differential CCVS CiFET amplifying circuit shown in Fig. 4.24. The differential topology consists of three appropriately-ratioed CiFET building blocks arranged to allow dual p- and n- iPort differential currents (either or both can be used), while the output is a differential voltage; the gain is therefore of the transresistance/impedance form innate to the CiFET device (i.e. CCVS). This particular CCVS CiFET-based circuit can be also used as an impedance-matched low noise Fig. 4.24 Topology of the differential CiTRA/CiTIA. 154 amplifier (LNA), wideband amplifier, or frequency mixer among other applications. It also shows promise for being fast enough to operate in the high hundreds of GHz (and possibly THz) range enabling multi-GHz frequency tracking ADCs. The fully-differential signal inputs and outputs of this pseudo-differential topology further cancel out non-linear differences between the PiFET and NiFET as well as single-ended power supply considerations. Focusing on the first use here as a CiTIA, we can ratio the first input CiFET (leftmost CiFET in Fig. 4.24) source and drain channels to obtain a 50 Ω input impedance matching through a >50GHz operating frequency. All iFETs source-to-drain channels are ratioed the same to maintain equilibrium. Fig. 4.25 depicts the wideband 50 Ω matching for the CiTIA circuit topology shown in Fig. 4.24 while Fig. 4.26 shows the gain, phase, total input referred noise, and total output referred noise plot for the same 50Ω matched differential CiTIA amplifier over the same frequency spread. At a frequency of 100GHz the gain has dropped to 25dB from the lower frequency baseline gain of 79dB. At 0dB the frequency is 1.5THz and the total input referred noise is as low as -200dB in the wide operating frequency band. Fig. 4.26 provides an awareness of the CiTIA’s ability to operate at the required signal to noise ratios that are enacted with low input signal levels (shown in the Fig. 4.27 waveform). This compact and scalable CiTIA circuit can be used as a low noise gain element that has the ability to operate at a wide range of multi-GHz frequencies with low distortion due to minimum phase shift and a wide ultra-linear dynamic range. A very small signal can ride anywhere on a large signal without incurring distortion. Passive components such as capacitors (which are RC related to the iPort input resistance) could be utilized to create an active network for filtering (i.e. bandbass, highpass) to amplify at the select frequency of interest with tunable properties by means of iPorts. Notably, this versatile CiTIA could ideally be used as an LNA for receivers. The low noise properties of the CiTIA from the circuit of Fig. 4.24 are illustrated in the frequency plot of Fig. 4.26 (also see Appendix D). In Fig. 4.26, the roll-off slope of the total input referred noise 155 Fig. 4.25 Differential 50 Ω CiTIA input impedance and 100GHz bandwidth for LNA use. Fig. 4.26 Differential 50 Ω CiTIA gain (red-solid), total input (green-dot-dash) and total output (violet-dash) referred noise, with phase (yellow-dot) for 100GHz through ratioing the CiFET. 156 (green dot-dash line) and total output referred noise (violet dash line) descends at 10dB per decade until the point at which the amplifier roll-off starts. At that point, the total output referred noise rolls off faster as a results of the amplifier roll-off (which happens at approximately 1GHz). Fig. 4.27 shows the ability for this topology to amplify very small nV signals (converted to current) with high precision, linearity, and a fast stable response. Fig. 4.28ab shows the range of the differential CiTIA’s operating frequency and gain versus supply voltage when the input is matched to a 75 Ω antenna for a radio receiver. Most notably, at an extremely low 25mV power supply this transresistance amplifier has approximately 10kHz bandwidth and a gain of 5dB as can be seen in Fig. 4.28ab—obviously revealing that the CiFET is not a threshold voltage limited device like state-of-the-art analog amplifiers. Fig. 4.28ab demonstrates that the CiTIA/CiTRA amplifier circuit from Fig. 4.24, like the CiAmps in Fig. 4.17, is not restricted by threshold voltages or their stacking, which makes these CiFET amplifier configurations extremely useful at very low power supply voltages and can be fabricated in ultra- deep sub-µm CMOS technologies with very desirable gain, frequency, and low power properties. 157 Fig. 4.27 Differential CiTIA input voltage (green) from 20pA into 50 Ω-matched input resistance and output (red) voltage transient plot for small input voltages. 158 Fig. 4.28 Differential CiTIA supply voltage versus gain and frequency plots with 75 Ω input impedance matching (a) over whole range and (b) zoomed in. 159 Fig. 4.29 depicts this topology’s similar linear, high gain characteristics to the individual CiFET current injection vs. output voltage plot previously shown in Fig. 4.15. Only here the input was swept through a minimal input range of -1pA through zero to +1pA which illustrates a dynamic range of over 1-million-to-1 with no zero-crossover discontinuity. Linearity and transresistance (rm-total) gain stays at 85,000 over the entire range (note: rm = the slope). This gain is set by the relative conductances of the source and drain iFET channels making the CiFET very process independent. In addition, the gain can be electrically varied by several mechanisms if desired. This CiFET transresistance gain rm depends on the relative channel conductance ratios normally set by relative channel sizes, as charted in Fig. 4.16, primarily and not the IC process parameters, yielding a high degree of design portability (see the Appendices for an expanded explanation regarding the linearity and dynamic range). Fig. 4.29 Differential CiTRA/CiTIA iPort injection current versus output voltage linear plot through zero. 160 If all four iPort sites of the differential CiTIA/CiTRA are utilized as a current input the gain adds from both of the PiFET and NiFET, such that: 4 (4.5) if the currents are similar and the sizing of the iFETs is done correctly regarding roughly equivalent pull-up mobility to pull-down. A small current input on one iPort can be offset with a large current on the other iPort without losing small signal linearity or sensitivity. Furthermore, gain can also be electrically altered, as mentioned previously, by using the opposing iPort along its self-bias generator’s iPort. In Fig. 4.30, the additive linearity plot is illustrated for this circuit. Here the NiPort was swept from -1µA through zero to +1 µA for each diagonal output plotted. At the same time, the PiPort iPort was stepped in 100nA steps for each diagonal trace. The importance of this plot is Fig. 4.30 Differential CiTRA/CiTIA iPort additive linearity illustration plot. 161 that it shows the uniformly equal spacing between the traces to verify that every time the p-channel differential input is stepped in current, the spacing between output traces is linear in both spacing and straightness of the lines. This is useful for adders and mixers in signal modulation operating at the high frequencies of the CiTIA. This plot in Fig. 4.30 also shows the composite gain: 1µA produces 340mV, which is 85mV for each input, resulting in an rm of 85,000 per input. Furthermore, the differential CCVS CiFET amplifier operates equally in all four quadrants, including zero, of the plot. The differential CiTRA/CiTIA has shown great usefulness for amplification applications in ultra-deep sub-µm CMOS technologies below 45nm. It has a wide dynamic range with optimal gain and a distortion-free linear response, which can dramatically improve distortion and SNR for multi-GHz communication systems. Finally, the circuit is low power and can work at supply voltages below 1V, which important for portable, battery-dependent wireless systems. The seminal CiFET cell from Fig. 4.8 may be arranged in a multiple of ways to produce new and useful topologies for traditional circuit uses beyond the amplifiers shown here. In Appendix E, a few of these example configurations are shown including proportional-to-absolute- temperature (PTAT), voltage reference, ring oscillator, and fast charge-mode digital circuits. The staged single-ended voltage CiAmps and differential CiFET transresistance amplifier circuits were the first investigational circuits into the possibilities for the CiFET family of circuits for analog applications for future CMOS technologies. These early circuits were fabricated in an all-digital 40nm TSMC CMOS process and physically tested. The die micrograph is shown in Fig. 4.31. The CiFET family of circuits is currently being expanded to include the next generation of low power analog and digital circuits for uses such as amplifiers, VCOs, mixers, voltage/temperature references, analog-to-digital and digital-to-analog conversion, and fast digital logic. 162 Fig. 4.31 Die micrograph of the 0.3mm 2 x 0.3mm 2 40nm CMOS charge-mode research chip containing the PLL and CiFET circuits presented in this thesis. 163 Chapter 5 CONCLUSION This thesis presented a new approach for developing analog circuits in ultra-deep sub-µm CMOS processes based on a charge-based view of the MOSEFT device. Charge-mode examples presented in this thesis include charge-transfer, capacitive charge coupling, optimization of the charge/discharge path for analog-in-digital circuits with the complementary complex logic method, and manipulation of the charge in a CMOS device’s channels with the CiFET seminal circuit. Results from these circuits include low power operation, ability to work at supply voltages well below 1V, manufacturability in feature sizes below 40nm, compactness, and high performance— such as increased speed, linearity, high gain, and low noise. These attributes are highly desirable for future IoT wireless devices where battery-life and portably are essential. The novel topologies presented in this thesis—the charge pump, phase frequency detector, expandable ring oscillator, phased-locked loop, and CiFET family of circuits—have been developed to aid analog IC designers in creating the next generation SoCs where analog and digital can be successfully combined on a single SoC in the newest all-digital CMOS processes. Furthermore, due to their digital-like building block structure and size, the automation of analog design becomes an increasingly feasible concept, allowing for automatically generated symmetric layouts and reconfigurable designs, which is part of the future work of the author. 164 Other future work includes developing the CiFET family of circuits. Beyond the CiAmps and transresistance amplifier’s ability to amplify at ultra-deep sub-µm CMOS processes without the need for traditional current mirrors or bulky analog transistors—which do not scale easily— the CiFET can be applied to other applications such as accurate ADC/DACs, voltage/temperature references, ring oscillators, and high speed digital logic, as shown in Appendix E. For instance, the CiFET charge-mode logic digital circuits operate on fast switching changes in current instead of voltage which show promise in the creating of the neuromorphic circuits of the future. Although the charge-mode analog IC design concepts presented in this thesis most likely could have a vital role in today’s CMOS analog circuits, their real value appears to be in the future as CMOS devices scale to 11nm and below. Most notably, the major impact of these charge-based circuits lay in the ability to facilitate the continuation of integrating analog and digital circuits on one SoC in the coming years as IoT and neuromorphic circuits gain popularity. Finally, in closing, this thesis provides a starting point to view CMOS analog circuits from a fresh charge-mode approach as opposed to the historical methods of voltage- and current- mode design. Doing so will lend analog, mixed-signal, and RF IC designers with the tools and knowledge of how to produce innovative, scalable circuit topologies for the next generation ultra- deep sub-µm and nanoscale feature sizes where analysis of charge becomes extremely important to render high performance circuits. 165 Appendix A C 2 L METHODOLOGY The procedure for C 2 L is simple and straightforward. In this section, we will give an example of a logic function and demonstrate how to construct the resulting gate for compactness and speed for a desired path. Examples of a normal digital circuit construction and the proposed C 2 L optimization of the same function will be demonstrated here for a basic understanding. This method can be applied to any digital or analog-in-digital circuit from which a truth table may be constructed and a function found, such as the PFD DFFs, shown in the next section. It is most useful when there is some complexity in the function as opposed to very basic gates such as the inverter or 2-input AND. Step 1: Construct the truth table for the desired function like the example in Table A.1. 166 Location Input Output # Hex 2 3 2 2 2 1 2 0 Y 8 4 2 1 D C B A 0 0 0 0 0 0 1 1 1 0 0 0 1 0 2 2 0 0 1 0 1 3 3 0 0 1 1 0 4 4 0 1 0 0 1 5 5 0 1 0 1 1 6 6 0 1 1 0 1 7 7 0 1 1 1 1 8 8 1 0 0 0 1 9 9 1 0 0 1 1 10 A 1 0 1 0 0 11 B 1 0 1 1 0 12 C 1 1 0 0 1 13 D 1 1 0 1 1 14 E 1 1 1 0 0 15 F 1 1 1 1 1 Table A.1 C 2 L example truth table. Fig. A.1 Complementary K-map with grouped Logic 1’s and Logic 0’s. 167 Step 2: Construct the complementary K-Map 88 and resulting function equations for both the grouped Logic 1’s and the Logic 0’s as shown in Fig. A.1 for the truth table in Table A.1. From the K-Maps, the resulting function equations are found to be: 1 ̅ (A.1) 0 ̅ ̅ ̅ (A.2) By constructing both of the complementary K-Maps and deriving the complement Eqs. (A.1) and (A.2) from this, we ensure that there is no doubling up or cross-over and that the final Y signal is logically correct. Normal methods, which optimize for minimum transistors, traditionally take the logic inverting Eq. (A.2) to construct the gates for the pull-down network with groupings made for minimum amounts of nMOS transistors which results in Eq. (A.3); after this, the De-Morgan 89 complement of Eq. (A.3) is taken to construct the pull-up network. 0 ̅ ̅ ̅ → ̅ ̅ (A.3) The C 2 L method does not use Eq. (A.3) and De-Morgan, nor does it group for minimum numbers of nMOS transistors. Instead C 2 L uses the opposite diffusion type of the P-channel transistors to perform the phase inversion which will be covered in the next step. 88 The Karnaugh Map (K-Map) is a method to simplify Boolean algebraic expressions invented in 1953. It takes truth table results and places these on a 2-dimensional grid in order to identify and eliminate race conditions where the output is dependent on other events. 89 In Boolean algebra, De Morgan's laws, named after a19 th century British mathematician, are a pair of transformations used by digital circuit designers. They state that: 1. "not (A and B)" is the same as "(not A) or (not B)", and 2. "not (A or B)" is the same as "(not A) and (not B)". 168 Step 3: Construct the pull-down nMOS or “N” network using the ungrouped Logic 0’s equation from Eq. (A.2) which results in Eq. (A.4). ̅ ̅ ̅ (A.4) For the pull-up pMOS or “P” network we must first notice that the P-channel transistors use the opposite diffusion type as compared to the N-channel transistors in order to perform a phase inversion. This is invoked by simply using the opposite phase signals on the P-channel gate, thus all of the terms in Eq. (A.1) become inverted as shown in Eq. (A.5) for the pull-up network: ̅ ̅ (A.5) It is now safe to wire-OR the P-channel pull-up to the N-channel pull-down “half” complex gates together from Y(P) and Y(N). This is how a CMOS inverter works. To finish, combine the resulting half logics for the pull-up and pull-down gates from Fig. A.2b-c to form the C 2 L logic gate in Fig. A.2d. Fig. A.2 Resulting logic gate constructions for example. 169 Step 4: From the logic gate in Fig. A.2d, which includes the pull-up and pull-down networks in Fig. A.2b-c, respectively, draw the corresponding schematics. This is shown in Fig. A.3b, whereas the traditional method is shown in Fig. A.3a, which is optimized form minimum nMOS transistors due to the original grouping in Eq. (A.3). Fig. A.3 Schematics resulting from logic construction. 170 Step 5: Draw the sideways “string” diagrams from the schematics in Fig. A.3, which results in Fig. A.4. When doing this for the C 2 L, make sure have no places where there are breaks in the active area and move transistors around to do so. The idea is that Eqs. (A.4) and (A.5) produce the right amount of transistors to make sure of this; this is because transistors take up much less space than a gap in active area in the layout, while also producing less parasitics than traditional methods due to more efficient interconnect within the cell. Fig. A.4 String diagrams resulting from the logic schematics. 171 Step 6: Draw the layout stick diagrams directly from the string diagrams in Fig. A.4 which results in Fig. A.5. Step 7: From the layout stick diagrams in Fig. A.5, create the layout as shown in Fig. A.6 making sure to account for the ~2.5 times in n-channel mobility, µn, as compared to the p-channel, µp 90 . Note the difference in area between the traditional minimum nMOS transistor layout Fig. A.6a as compared to the C 2 L method which has more small nMOS transistors and less of the bulky pMOS transistors Fig. A.6 b. Also note the active areas in the nMOS region where there is a split in due to the split in active area in Fig. A.6a, whereas the C 2 L method does not have this break. Fig. A.5 Stick diagrams resulting from the logic schematics. 90 Making the pMOS 2 to 2.5 (or even 3) times the size of the nMOS is generally sufficient based on the IC process due to the differences in electron and hole mobility for the process being used. (this can be determined by equating rise fall times in an inverter via sizing as covered by most digital CMOS design text books). If the path is extremely critical, a designer may increase the size of the pMOS (and the nMOS) in that path, but it is advisable to do this after a schematic simulation to ensure that the increased speed results are worth the tradeoff in area, as the C 2 L method is used to maximize for speed and area together at their peak. 172 Fig. A.6 Layout resulting from the stick diagrams. The normalized results from the C 2 L method in this specific example is a reduction of area and power by 25% and an increased speed of 1.5 times that of the traditional method which is due to the reduction of the parasitic capacitances (e.g. less charging and discharging required). This is a direct optimization of the power-delay product (PDP) 91 and energy-delay product (EDP) relationships through the reduction of parasitics: 2 2 2 , (A.6) 2 2 2 , (A.7) where Pavg is the average dynamic power dissipation, Etotal is the energy per operation, Qtotal is the charge which shifts (either charging or discharging) in a single operation, Ctotal is the total of the parasitic and output capacitances of the next gate, tp is the average of the low-to-high and high-to- low propagation delays of the circuit given by: 91 The PDP is a measure of energy per cycle or operation, whereas the EDP is a quality metric of the gate. 173 2 . (A.8) The high-to-low propagation delay may be found by: 2 2 , (A.9) with: 1 2 , (A.10) where the drain current in the saturation and linear regions may be calculated by Eqs. (2.31) and (2.32) for the nMOS transistor. For the average current from low-to-high this same equation in Eq. (A.10) may be calculated for the pMOS then Eq. (A.9) calculated for the same transition. Matching the low-to-high and high-to-low delays is of utmost importance and is easily done with the C 2 L method through normal sizing of transistors based on mobility (from Step 7). Finally, the C 2 L method may be applied to any digital or AiD circuit for which a designer can make a truth table. It can also be applied to the phase-frequency detector DFFs in the next section for which a fast Reset-to-Q path must be established. 174 Appendix B CIFET ANALYSIS This section provides a brief analysis in the input impedance, frequency response and noise pertaining to the CiFET device when used as a trans-impedance amplifier (TIA) configuration. Using the basic simplified CiFET as a TIA circuit diagram in Fig. B.1 we can find the basic small signal model of the CiFET as a TIA as shown in Fig. B.2. Doing so will yield the approximated input resistance, Rin, of this topology to be: 1 1 . (B.1) Therefore, varying the NiFET’s (or PiFET if the complement input is used) drain channel W/L ratio will provide an impedance match if desired for low noise amplifier applications. To model the frequency response of the CiFET as a TIA, we can use Fig. B.3 and a similar small signal model to that of Fig. B.2. For simplicity, neglecting ro, we find that the frequency response is: 175 Fig. B.1 Simplified input impedance circuit model of CiFET as TIA. Fig. B.2 Simplified input resistance small signal model of CiFET as TIA. 1 1 . (B.2) The input pole is mainly due to Cgs1, but if there is a photo diode typically used in TIA applications, Cin can be larger (~100fF) and can dominate. If this configuration is used as a CiAmp, 176 Fig. B.3 Frequency response circuit analysis for CiFET as TIA. then the frequency response only improves as technology scales due to the Cgs dependence on W, L, and Cox as dictated by equations (2.37)-(2.39). 92 Note that Rd models the complementary iFET and Cout models the next stage for simplicity. A basic noise model of the CiFET as a TIA can be seen in Fig. B.4. Simple modeling of the noise analysis, neglecting ro, yields the noise voltage and current equations: , , , 4 2 3 1 (B.3) , 4 2 3 1 . (B.4) 92 Note: W and L decrease by scaling factor, s 2 , for each descending technology node, while C ox is process dependent and increases due to its inverse relationship with the decreasing thickness of the gate oxide [63]. 177 Fig. B.4 Noise analysis for CiFET as TIA. Both the bias and Rd contribute to the input noise current. In the case of the CiFET, Rd can be altered via W/L ratioing of the drain channel of the complementary iFET as it is not limited by voltage headroom like traditional stacked analog TIAs. This makes the CiFET useful for low noise applications due to its ease of CiFET building block design and its stability. 178 Appendix C IFET/CIFET ABSTRACT AND BEHAVIORAL MODELS Figs. C.1-C.4 provide a collection of abstraction and behavioral model diagrams of the iFET and CiFET, which are based on transresistance. These various abstraction and model viewpoints provide an insight into circuit operation. They are a work in progress as the modeling, use, and applications of the CiFET evolve. Fig. C.1 Various iFET abstractions. 179 Fig. C.2 iFET and CiFET self-cascode model. 180 Fig. C.3 iFET and CiFET behavioral model. Fig. C.4 CiFET schematic and symbol. 181 Appendix D ADDITIONAL CIFET AMPLIFIER EXAMPLES AND PLOTS Fig. D.1 gives examples as to staging the CiAmp and CiTRA/CiTIA similar to Fig. 4.17 and Fig. 4.24, showing the flexibility of the CiFET configurations. All CiFET device ratios within an amplifier are normally set to the same ratio in order for all stages to be biased near the same self-bias “sweet-spot” or approximately ½ Vdd. These examples illustrate stronger source channels yielding lower input resistance that transfers energy into the amplifiers by means of input signal current into a low impedance input. Flipping the CiFET channels to make a stronger channel near the output node yields a higher voltage gain configuration (as in the CiAmp configuration in Fig. 4.17) with a higher input resistance. 182 Fig. D.1 Staging examples for the CiFET amplifiers. \ 183 The application concept Fig. D.2 is a Zin matched transmission line receiver. This is an example of using the CiTIA to receive transmission line or bus signals. The transmission line goes into one of the iPorts and a second stage may be used to increase gain. The iPorts can be used to set the threshold and the parallel use of all the IPorts can control the receiver gain. Specifically, Fig. D.2 is an example of matching iPort input resistance Rin to the characteristic impedance of a transmission line. This is achieved by ratioing the CiFET source to drain channels as illustrated in the plot of Fig. 4.16. A 100 Ω transmission line requires a ratio of ~32 as read from this plot. If the CiFET drain channels are 2x long, then the source channels are 16x wide for a combined ratio of 32. A differential version has higher noise immunity and speed. This impedance matching through iPort ratioing avoids transmission line reflections and maximizes power transfer to the CiTIA resulting low termination impedance which also creates a low noise receiver which operates on current, rather than voltage, that is passed down the interconnect wire. For low noise, the receiver is locally referenced at the receiver ground instead of the remote transmitter ground as in a voltage transmission system. The high output impedance of the transmitter current source provides high compliance to ground noise which normally enters the signal path between the source and receiver. A current into a low termination impedance means that there is insignificant voltage change on the transmission line, making the interconnect capacitive loading of no effect, thus a large power savings. This system is well suited for high speed data bus applications. The various bus talkers are just wire-ORed to the data bus wires, also the wire-OR property is useful in combining several interconnect signals over a single wire. Also due to the bi-directional iPort property, the signals can both source and sink their talking current while outputting zero current when offline. It works for both analog signal transmission and digital transmission, not to mention 184 Fig. D.2 Charge-mode transmission line receiver with CiFETs. \ a charge packet transfer, which is useful in neuromorphic circuits. At high data throughput, this eliminates the dominant power dissipation component of charging the transmission/interconnect wires, which is a tradeoff for continuous current operation. For lower data rates, current can be scaled down, or for DC, charge packets can be the transmitted and the result latched at the receiver. For higher noise immunity and higher speed systems, a differential configuration may be used similar to the following Fig. D.3. The next example in Fig. D.3. is an optical receiver. A pair of photodiodes are used with one active and the other as a replica bias or providing additional differential signal from the same light. This optical receiver operates in the differential mode with optional second or more gain stages. Currents can be wire-OR summed into the various iPorts to modify operation if desired. Fig. D.3 Self-biasing high speed optical receiver concept with CiFETs. \ 185 The amplifier circuit example in Fig. D.4 is a dual differential antenna preamplifier. It has a differential second stage with additional filter and gain control access into the iPorts. The first differential stage can also receive iPort control currents in addition to providing another quadrature summing antenna input for omnidirectional receivers. These circuits represent continuous domain applications for the CiFET as opposed to the sampled data domain CiAmp previously illustrated. This helps to break down any perception that sampled data applications are all that the CiFET can do. Correlated double sampled data systems get rid of 1/f noise and circuit parametric deviations which is extremely important. In order for newer receivers to operate with a 1V power supply, switching receivers are the new generation of RF circuits. Fig. D.4 CiTIA dual differential transimpedance antenna pre-amplifier with added gain and filter control inputs. 186 Fig. D.5 is a plot representing the varying acquisition time versus supply voltage for the 3- stage feed-forward CiAmp circuit from Fig. 4.17. Note that with a 1V power supply, it takes about 1ns to acquire a 1V step in voltage and 20ns to settle to 1ppm accuracy. Fig. D.5 3-Stage feed-forward CiAmp supply voltage versus acquisition time. \ 187 Figs. D.6 and D.7 show the 3-stage basic and feed-forward CiAmp, from Fig. 4.17, combined gain, phase, and noise plots respectively, which are similar to the CiTIA’s in Fig. 4.26. The common vertical scales are adjusted to accommodate for the differing gain and noise range of the CiAmp using -185dB to +180dB or degrees as compared to -200dB to +80dB or degrees for the CiTIA; which also has a differing frequency range of 1THz for the CiAmp as compared to 10THz for the CiTIA. Note that the feed-forward CiAmp configuration provides an extra phase and high- frequency gain boost while lowering the noise to -160dB in the 100MHz to 10GHz frequency region. In addition, the 3dB break frequency is pushed out from 13.97KHz to 49.37KHz at the expense of a reduction in the 3dB gain from 127.5dB to 118.6dB. This is effected with a kick in the phase shift (gold-dotted) by the feed-forward stage being operative in the last decade or two of its active frequency. This also pushes the total input referred noise (green dot-dash) down in this upper frequency range. 188 Fig. D.6 3-Stage CiAmp gain (red-solid), total input (green-dot-dash) and total output (violet- dashed) referred noise, with phase (yellow-dotted). \ Fig. D.7 3-Stage feed-forward CiAmp gain (red-solid), total input (green-dot-dot-dash) and total output (violet-dashed) referred noise, with phase (yellow-dotted). \ 189 The following series of eight graphs demonstrate the stamina of the CiAmp over extreme environmental conditions. The variables imposed are an overkill to illustrate its robustness and manufacturability which have not previously been imagined in any IC process, let alone a deep sub-µm logic-only CMOS process. This is the difference between university research and industrial strength design. Knowing and testing the limits provides insights and spurs innovation. Figs. D.8-D.11 plot the IC process parametric tolerance of the default example 3-stage feed-forward CiAmp. The solid red plots are for the nominal process parameters, the blue dotted is the fast-fast corner, grey dot-dash is slow-slow, green dash-dot-dash is fast-slow process corner, and the gold dashed is the slow-fast corner in all four of these plots. For each simulation plot, the power supply was incrementally swept from 100mV up to 2V, which is normally beyond the maximum gate oxide breakdown voltage, but is included to more than cover extremes. The total noise was taken at the amplifier bandwidth limit where the output is at its cutoff frequency. From Fig. D.6 and D.7 note that the total input referred noise is nearly constant at its low value for two or three decades of operating frequency where the CiAmp circuits perform advantageously. Fig. D.8 3-Stage feed-forward CiAmp gain over Vdd for nominal and 4-corner IC process parameters. \ 190 Fig. D.9 3-Stage feed-forward CiAmp frequency over Vdd for nominal and 4-corner IC process parameters. \ Fig. D.10 3-Stage feed-forward CiAmp phase margin over Vdd for nominal and 4-corner IC process parameters. 191 \ Fig. D.11 3-Stage feed-forward CiAmp noise over Vdd for nominal and 4-corner IC process parameters. \ Figs. D.12-D.15 plot the temperature variations of the default example 3-Stage Feed- Forward CiAmp. The solid red-lined plots are for the nominal room temperature of 27ºC, grey dot-dash is -55ºC, the brown dashed is for -25ºC, green dash-dot-dash is 0ºC, the gold dashed is 70ºC, and the blue dotted is 125ºC, in all four of these plots. For each plot, the power supply was incrementally swept via simulation from 200mV up to 1.8V, which is normally beyond the maximum gate oxide breakdown voltage of ultra-deep sub-um IC processes, but is included to more than cover extremes. 192 Fig. D.12 3-Stage feed-forward CiAmp temperature effect on voltage gain versus supply voltage. \ Fig. D.13 3-Stage feed-forward CiAmp temperature effect on frequency bandwidth versus supply voltage. \ 193 Fig. D.14 3-Stage feed-forward CiAmp temperature effect on phase margin versus supply voltage. \ Fig. D.15 3-Stage feed-forward CiAmp temperature effect on total input referred noise versus supply voltage. \ 194 The next five plots depict the CiFET’s transresistance-based transfer function linearity and dynamic range. Fig. D.16 is the upper right positive quadrant of the CiFET transfer function when taken through its full 10pA to 7µA dynamic input range for which it is fully linear as shown in this ~7 decade log-log plot. For this input range, the output goes from 1µV to 850mV plotting its constant transresistance gain of 850mV/7µA = 120k Ω. The CiFET channel ratio is 4 for these plots, which is the default CiTRA amplifier CiFET source to drain ratio. This is consistent with the Fig 4.16 relationship plot of rm versus CiFET ratio. Since log plots do not go through zero (only exponentially approach zero) Fig. D.17 is the same plot with a negative current at the iPort (recall that the iPorts are fully bi-directional) and belongs in the lower left negative transfer function quadrant when placed with the ~0 points aligned at a 0,0 composite origin. The ranges are exactly the same (the plotting program plotted this with minimal grid identifiers). Both log-log plots cover ~7 decades of dynamic signal range, which is equivalent to about 24 bits digital, 100 million, or 160dB consistent with the gain and settling accuracy of the 3-stage CiAmp and signal-to-noise ratios achievable. These numbers are optimal for ADC and DAC designs. Figs. D.18 and D.19 are linear plots to illustrate the bidirectional symmetry around zero on small and large scales. Fig. D.20 is an overdrive plot that illustrates its saturation behavior. The cursor box is the linear region that the other plots have expanded. Note: a slightly different CiFET ratioed device was used in Fig. 4.15 which has a transresistance of 500mV/5µA = 100k Ω. These four plots turn the iFET I-V curves of Fig. 4.6 on their side and cap them off with their complimentary iFET as a load to provide an ultra-linear gain element. 195 Fig. D.16 Positive (log-log) CiFET composite gain plot. 196 \ Fig. D.17 Negative bidirectional input (log-log) CiFET composite gain plot. \ 197 Fig. D.18 Linear CiFET composite gain plot from continuous bi-directional zero-crossing input current. 198 Fig. D.19 Linear CiFET composite gain plot from wide-range bi-directional input current. \ 199 Fig. D.20 CiFET overdrive plot with curser box indicating linear region. \ 200 For state-of-the-art amplification in analog circuit design, the active gain element (i.e. transistor) is normally loaded with a resistor or an active current source. The mismatch in linearities between the gain element and the load result in a nonlinear transfer function. The CiFET uses similar device structures for pull-down and pull-up canceling out these non-linearity mismatches. Thus in the CiFET phase inversion is supplied by the opposite semiconductor type devices. Rationing the pull-up conductance to approximate the pull-down conductance (sweet- spot or ½ Vdd biasing) easily pushes the composite transfer function nonlinearity to better than 1- million-to-one. Table D.1 displays basic results of the respectable precision of the CiFET amplifier configurations under parametric variations and power supply noise. The top section of the spreadsheet in Table D.1 imposes the worst-case 4-corner IC process parameter limits: ~1ppm 93 deviation. The central spreadsheet section illustrates that the CiAmp is highly tolerant to individual channel parametric changes or matching. Here each transistor was individually widened by 50% to impose an over-the-top parametric change and mismatch. Note that nearly all of the deviation is collected in the input CiFET stage (highlighted in yellow), but approximately none of this error gets through to the output (red amplitude deviation column), to the tune of less than a ppm. These errors are more than 10 times lower, at a relatively small cost in speed, for the CiAmp without the feed-forward gain-bandwidth option shown in Fig. 4.17. The lower section of the spreadsheet illustrates the CiAmp’s immunity to power supply variation injected noise. For this, an over-the-top positive and negative 500mV step with a 10fs rise time that was added to the power supply voltage. Again, around a 1ppm variation in amplifier output error. 93 ppm is parts per million, 201 Table D.1 Comparison of the 3-stage feed-forward CiFET amplifier precision. 202 Figs. D.21-D.23 are example illustrations on how sampled data CiAmp circuits are integrated into SOC digital systems, using the same all-digital ultra-deep sub-µm IC process without analog process extensions. Because sampled data approach not only cancels out IC process variations, but also most importantly this approach eradicates noise through correlated double sampling. In a digital system, analog should be limited to a minimal preprocessing of analog I/O signals and converting them with integrated ADCs/DACs so that digital signal processing algorithms can do their DSP magic. Additional analog circuitry is beneficial where signals are too fast to be efficiently handled in the digital domain. Analog assistance in filtering and demodulation are additional examples. Fig. D.21 illustrates correlated-double-sampling using a CiAmp in its basic sampled data configuration. A sample clock, Clk, controls this unity gain sample-and-hold circuit. Initially the cycle starts with the clock going high to close the “Phase-A” switches, identified as “Setup”, which connect: 1) the CiAmp output, Out+, back to its input which is also connected to the Coffset capacitor, causing the CiAmp to self-bias at its “sweet-spot” near ½ of the power supply voltage, 2) the other side of the Coffset capacitor between this CiAmp’s sweet-spot voltage and the output reference voltage, Ref-, to store the difference between these voltages as a charge on Coffset, and 3) the input voltage sampling capacitor. Cfly, across the input to store the input voltage as a charge on Cfly. These capacitors are small (in the 100fF range) and can be made from interconnect metal separated by the normal oxide insulator between interconnect; thus their capacitance is not a function of voltage. Their absolute capacitance value is of little importance; they just have to be 203 small enough to be charged quickly enough to settle to the desired accuracy, and these capacitors have to be large enough to absorb any switching charge imbalance and not decay significantly within the total clocking time period. At the end of Phase-A, the switches associated with Coffset are turned OFF faster than the sample Cfly capacitor switches. This is to guarantee that the stored charge on Coffset is presented with a high impedance to preserve its charge in the event that the CiAmp output moves as it is released. Any latency in turning off Cfly is just an insignificant delay in the sampling aperture time. The middle of this logic-quick turn OFF of Phase-A defines the aperture time along with its width as the logic transition time near the middle of its voltage swing. Also note that the “input range” is valid up to a diode drop outside of the power supply rails in either direction. “Phase-B” is the output “Enable” time where the Phase-B switches connect the sample capacitor Cfly in series with the Coffset capacitor and place this voltage stack from Amp output to its input. Here the sampled Cfly capacitor voltage is connected in series with the Coffset voltage, which corrects for the difference between the sweet-spot voltage and the output Ref- voltage. The CiAmp’s input will always return to its exact sweet-spot voltage when there is any feedback from its output back to its input. There is precisely only one exact sweet-spot voltage as determined by operating threshold voltages of the stack of CiFET channels which pass the same current path through all channels in series. There is no other path for this channel current to go except through all the channels in series. Passing this current requires each channel to re-acquire its operating threshold voltage. Because the gates of all the CiFET channels are tied together, the PiFET resistance must exactly equal the NiFET resistance for a sweet-spot balance, near ½ of the supply voltage. Any changes to the power supply are ratioed out of the balance equation to about 1ppm 204 in practice. The sweet-spot is the analog virtual ground. This is evidenced by the test of a 500mV step in power supply voltage test as tabulated in Table D.1. The noise voltage is sampled out by the correlated-double-sampling scheme: 1) the instantaneous noise voltage of the CiAmp is tracked by the Coffset capacitor during the Phase-A Setup time, 2) along with the instantaneous input voltage being tracked by Cfly capacitor up to the bandwidth of the associated circuitry, 3) in the middle of the fall time of the Setup Phase-A, defined as the sample aperture time, the instantaneous noise voltage is stored on these two capacitors, which throws out all the lower frequency noise power of all previous time, 4) the noise voltage is active only during the Phase-B Enable time period accumulating only its extreme high frequency energy of this time window, and 5) during this Phase-B Enable time window, the ADC comparator is enacted to make its binary decision. More than a single Cfly capacitor can be used sample multiple input voltages and when connected in series with the CiAmp in Phase B it will create a sum or difference in the output voltage as diagramed in Fig. D.22. Multiple Cfly sampling capacitors connected in creative ways yields other arithmetic options. For instance, in Fig. D.22, two capacitors are sampled in parallel and then connected in series in Phase B to yield an exact multiple of 2x which is fundamental to an ADC. Going the other way divides by 2 for a DAC. In either configuration, connecting the output Ref- terminal between ½ scale and zero is useful in adding or subtracting half scale in the ADC/DAC application. This CiAmp in Fig. D.23 creates an exceptionally simple ultra-accurate 205 ADC core building block out of a purely logic IC process that is process and parametrically independent and does not use precision parts or analog process extensions. The precision is primarily obtained by keeping a high impedance is series with the capacitors during hold time, so as to not alter their stored charge (charge-mode insight). Since the voltages on both sides of the Coffset capacitor does not change; parasitic capacitance is irrelevant here (another charge-mode insight). The top side of Cfly is always driven with a low impedance making this parasitic capacitance irrelevant also. This leaves only the bottom side of Cfly to be careful about in physical layout. This circuit concept is also compact and power frugal. It is easily buildable in focal plane readout ADCs where they are restricted to narrow pixel widths and must be sensitive and fast. Fig. D.21 CiAmp correlated double sampling circuit for DC and noise correction. 206 Fig. D.22 CiAmp precision sum or difference circuit. Fig. D.23 CiAmp precision multiply by 2x with ADC half-scale subtraction capability. 207 For reference, Table D.2 provides an overview prospective of the electron count for various capacitances and voltages along with their available dynamic ranges. For instance, one electron on a 100fF capacitor produces 1.6uV and it takes a million electrons to fill the capacitor to 1.6V enabling a 6-decade dynamic range, which is equivalent to 20-bits of digital resolution. This illustrates why 100fF is a preferred capacitance value starting point for building the circuits with the CiAmp, such as the focal plane array or the correlated double sampling circuit. Table D.2 Analog resolution limits when defined as charge on a capacitance. 208 Additional CiAmp Transient Simulation Waveform Details An important example application of the precision CiAmp is in the ADC applications including the differential amplifier utilized later in Appendix E, particularly Fig. E.10. In that example, the input pulse generator mimics inserting the sample capacitor voltage from “AmpOut” to the “Amp0-” CiAmp input. Fig. D.24 is an example of the input/output transient characteristics of the CiAmp. The standard-sized feed-forward version of the CiAmp was used for all the plots in this section of Appendix D. Due to this section being some of the first initial investigations into the CiAmp capabilities, all CiFETs were at that time modeled as MOSFET stacks, as is shown in each stage for simulation circuit in Fig. D.25. Therefore, this part of Appendix D is included in the thesis to highlight the initial transient simulation waveform details of the CiAmp. Additionally, the test circuit of Fig. D.25 isolates the CiAmp out of the circuit in order to separate the operational fine details from any external circuitry to provide its intrinsic performance shown in the many transient plots of this Appendix. Figs. D.26-D.27 provides the individual output and input waveforms as separate plots so that the combined plot waveform in D. 24 is clearly envisioned. Figs. D.28-D.30 shows transient waveforms similar to Figs. 4.22-4.23 for the 3-stage feed- forward CiAmp circuit of Fig. 4.17 with power supply voltages of 1.2V, 800mV, and 300mV, respectively, thus illustrating lower voltage operation according to the power supply dependence plots of Figs. 4.19-4.21. 209 Fig. D.24 3-Stage feed-forward CiAmp 1V step response settling time and ringout detail. Fig. D.25 3-Stage feed-forward CiAmp 1V step response settling time and ringout schematic example. 210 Fig. D.26 3-Stage feed-forward CiAmp +/- 1V step response output waveform. 211 Fig. D.27 3-Stage feed-forward CiAmp +/- 1V step response input waveform. 212 Fig. D.28 3-Stage feed-forward CiAmp step response combined input/output waveforms with a 1.2V voltage supply. 213 Fig. D.29 3-Stage feed-forward CiAmp step response combined input/output waveforms with a 800mV voltage supply. 214 Fig. D.30 3-Stage feed-forward CiAmp step response combined input/output waveforms with a 300mV voltage supply. 215 The feed-forward CiAmp responds with a 3% overshoot as set with the pair of 30fF rolloff capacitors, Crolloff. The overshoot actually recovers with an exponentially decaying normal ringout that is detained in the increasing magnification sequence of plots of Figs. D.31-D.40. Since the magnification goes to 1 million times, this requires a series of progressively greater magnified plots for each peak and valley of the ringout. Fig. D.31 is an overview and Fig. D.32 plots the 10fs rise time applied to the amplifier, while Fig D.33 show the corresponding output plot. 10fs was chosen to fully excite the amplifier parasitics. The initial CiAmp output was driven with this input to the balance level of the CiAmp circuit parasitics. Fig. D.34 shows the CiAmp feed- forward response to the rapid analog signal step out to about 3.5ps where the 3-stages of the CiAmp take over to increase the output accuracy. The slope of the output waveform changes as the dominance of the feed-forward and the high-gain path switch their control. Fig. D.35 shows the observable 3% overshoot at around 3.5ps and each successive plot steps through the ring-out peaks and valleys. The final settled voltage is -0.656uV short of the 500mV target illustrating the 1 million to one accuracy. This figure is the magnified insert in the upper left of Fig. D.24 overview, where the vertical scale is 1uV. This ringout set of waveform plots in Figs. D.31-D.40 are summarized in Table D.3 at the end of these transient waveforms. The curser values at the bottom of the plots are sequentially tabulated it this table and a summary of this series of waveform plots is: 1) 200ps to reach within -3% of the target voltage, 2) 500ps to reach the +3% overshoot peak, 3) 5,000ps to settle to its final 20-bit digital equivalent of 1-million-to-1 resolution of 0.7µV out of a 1V step representing Av=120dB, 216 4) each half of the ringout frequencies period is 900ps for a ringout frequency of 600MHz, 5) each half cycle of the ringout exponential decay reduces the error to 4% of the previous peak or valley error, and 6) the handover from a fast-forward accelerated output to the high-resolution occurs at 4ps. Fig. D.31 3-Stage feed-forward CiAmp +1V pulse ringout detail with 3% overshoot perspective. 217 Fig. D.32 3-Stage feed-forward CiAmp +1V pulse ringout detail with 10fs input rise time. Fig. D.33 3-Stage feed-forward CiAmp +1V pulse ringout detail with initial push-up at 10fs. 218 Fig. D.34 3-Stage feed-forward CiAmp +1V pulse ringout detail with output controlled by feed-forward inverter to ~3.5ps and then with the 3 CiFET high-gain path (slope change). Fig. D.35 3-Stage feed-forward CiAmp +1V pulse ringout detail with feed-forward to high-gain slope change at ~3.5ps and 3% overshoot +peak (note: 30.2mV at 482ps). 219 Fig. D.36 3-Stage feed-forward CiAmp +1V pulse ringout detail with 3% overshoot of 482ps to first-ring valley (note: -1.32mV at 1.387ns). Fig. D.37 3-Stage feed-forward CiAmp +1V pulse ringout detail with first ring valley to second peak (note: +55.7µV at 2.297ns). 220 Fig. D.38 3-Stage feed-forward CiAmp +1V pulse ringout detail with second peak to second valley (note: -3.072µV at 3.21ns). Fig. D.39 3-Stage feed-forward CiAmp +1V pulse ringout detail with second valley to third peak (note: -0.566µV at 4.14ns). 221 Fig. D.40 3-Stage feed-forward CiAmp +1V pulse ringout detail with third peak to steady-state error (note: -0.656µV at 4.5ns) for 1-million-to-1 resolution which is 120dB or a 20 digital bit equivalent (note: steps are from 8-digit file transfer to plotting resolution). Table D.3 3-Stage feed-forward CiAmp +1V pulse ringout detail summary of peak and valley timing and peak voltage decay. 222 In Fig. D.41, 10fs rise time 500mv pulse was added to the power supply to examine the CiAmp’s tolerance to supply noise. The output is observed in Fig. D.42. Fig. D.43 shows a comparison of the normal input and the input which has perturbed by the change in the supply voltage. The single-ended CiAmp initially sees some of the voltage step through the circuit parasitic capacitances as is normal for RF amplifiers, but the amplifier quickly returns to a 1- million-to-one accuracy of its operating output level at the full response speed of the CiAmp. Conventional amplifiers would stop working entirely, especially at the low power supply voltages. These accuracies are tabulated previously in Table D.1. The p-channel iFET transistors are 4 times the width of the n-channel iFET transistors; therefore, there is an unbalanced coupling from the power supply at the 10fs rise and fall times. The CiAmp quickly recovers from this power supply coupled voltage at its operational response characteristics to an error of less than 1ppm. If needed, this coupling can be balanced through various techniques with a little tradeoff in performance. However, the simplest circuit is the CiAmp, which has shown to usually work best overall. 223 Fig. D.41 3-Stage feed-forward CiAmp waveform with 500mV rise time step added to the power supply. 224 Fig. D.42 3-Stage feed-forward CiAmp output perturbation waveform from a 1ps 500mV rise time step added to the power supply. 225 Fig. D.43 3-Stage feed-forward CiAmp normal (red) and 1ps 500mV power supply input perturbation (blue) waveform comparison. 226 dCiTIA Baseline Simulation Schematic Used for DC and AC Characterization Fig. D.44 is the initial dCiTIA baseline simulation schematic used for DC and AC characterization for the CiFET. It is included here as it was used for investigational simulations on the dCiTIA, such as characterization, ratioing, performance, and noise. Here the inputs are differentially driven with current signals into the iPorts yielding a differential voltage output. The individual PiPort or NiPort inputs are enabled or ratioed through the use of “FPcurrent” and “NPcurrent” current controlled current sources driven with a common input current source “iInput.” The differential voltage outputs are combined with a voltage controlled voltage source “eTIOut.” Because the accuracy is more than the 8 bits, these signals are controlled by the circuit simulator instead of the graphic output program which receives 8-digit accuracy. The iPort current division is easily measured though the use of three 0V voltage sources named with iPin+, iPs+, and iPd+ relatively named at each iPort. Current through a zero-volt voltage source work best in circuit simulators when observing and meaningfully naming current signals. Currents are not as easy to observe as voltages and their direction must be reliably verified. Current sources often flip directions, especially when they do not go in the direction of a positive voltages across the current source. At times, the current direction flips in the middle of a simulation when the voltage across the current source reverses. The source channel-width multiplier “{Mul}” controls the iPort input resistance along with the transimpedance gain, rm. The dependent current and voltage sources are used to ensure that currents and voltages are precisely tracked since they run at the full native precision of the simulator. 227 Fig. D.44 dCiTIA baseline gain-bandwidth and noise simulation schematic. 228 Appendix E OTHER USEFUL CIFET BUILDING BLOCK CIRCUITS Exploration into other uses for the CiFET as a building block have yielded a variety of novel circuits, including voltage/temperature references, ring oscillators, frequency mixers, and even fast digital logic in addition to amplifiers. 94 These circuits, which are beyond the scope of this thesis, are currently under development and being placed into nanoscale silicon for a tapeout. In the next few sections samples of a handful of the CiFET family of novel circuits are briefly introduced. CiFET PTAT/CTAT Circuit Bandgap reference circuits are very important to analog circuits. Analog ICs require a stable reference for critical values such as voltage, which can change with a variation of temperature. Circuit performance is wholly dependent on correct biasing, and any fluxuations can render a design incorrect or even inoperable. Therefore, reference circuits, can be used to check 94 Currently, the author is expanding the novel CiFET family of circuits to include both analog and digital uses as companies such as Broadcom, Qualcomm, ARM, and Intel have shown interest in possible uses for the CiFET. Through the startup CircuitSeed (www.circuitseed.com), funded initially through InventionShare, these circuits are being developed and put into silicon for testing, in preparation for licensing and acquisition. 229 for changes so that the necessary corrections made to allow the circuit to perform well. The compact self-biased CiFET has been found to be a useful as proportional-to-absolute-temperature (PTAT) circuit as shown in Fig. E.1. In Fig. E.2, we can see that the voltage output is linear over an extremely wide range of temperatures. Additionally, the CiFET plot previously shown in Fig. 4.14 illustrates that the PTAT and complementary-to-absolute-temperature (CTAT) voltages are of the same magnitude—with precisely the opposite slope—and can be setup by the iFET ratios. Therefore the circuit in Fig. E.1 makes an ideal voltage reference—as a designer can set the voltage simply through the W/L ratios of the iFETs. The CiFET PTAT/CTAT is compact, low power, shows good PSSR 95 , and is scalable in ultra-deep sub-µm CMOS processes. Fig. E.1 CiFET PTAT, CTAT, and analog virtual ground reference topology. 95 PSSR stands for power supply rejection ratio and can be found by: 2 0 lo g ∆ ∆ where A is the gain of the circuit. Some manufacturers base PSSR on the offset voltage to the amplifier input and others base the PSSR on the voltage output as shown in the example equation. 230 Fig. E.2 NiFET PTAT and PiFET CTAT iPort voltages as a function of temperature plot. Fig. E.2 illustrates the NiPort PTAT and PiPort CTAT voltages tracking one another over extreme temperature limits. The NiPort PTAT voltage is measured up from the CiFET negative supply terminal voltage and the PiPort CTAT voltage is measured down from the CiFET positive supply terminal voltage. Thus these reference voltages are the iPort voltage away from their respective iFET source terminals and are a linear function of temperature. They are set by the various CiFET ratios and can be trimmed with small iPort current injection. Switch capacitor sampled data techniques can be used to generate various reference functions. The PLL charge pump (from Chapter 3) could be configured to actively trim a reference if desired. Combinations of these voltages can also be stacked as shown in Fig. E.3. 231 Self-Biased CiFET Voltage Reference The voltage reference circuit in Fig. E.3 is another example of the usefulness of the CiFET seminal cell. Here the bias and iPort reference voltages are set by the ratioing of the W/L vales in the iFET much like in that shown in Fig. 4.14. The circuit is self-biased, compact, low power, and can operate at low supply voltages in a deep sub-µm CMOS processes. Fig. E.3 Stacked, self-biased CiFET voltage reference. 232 CiFET Rail-to-Rail Voltage Controlled Ring Oscillator Similar to the VCO shown in Fig. 3.20, we can use the CiFET as an inverter with current bypassing to control the output frequency, as shown in Fig. E.4. This is accomplished by bypassing some of the capacitor network timing current around the CiFET drain channel. This allows the VCO output voltage swing to ~reach the supply voltage rails—independent of frequency control— with a similar high frequency operation. Fig. E.4 Rail to rail CiFET bypass control VCO. 233 CiFET Charge-Mode Logic Circuits (CCML) The CiFET building block has additionally been shown to be quite valuable as a low power fast digital circuit due to its complementary inverter-like properties. For example the CiFET can be configured into a Schmitt trigger as shown in Fig. E.5. More specifically though, the CiFET is a summing current inverter as shown in Fig. E.6 which is the dual concept of a normal voltage-inverting inverter. When a change in current at the either complementary iPort node is noted, the inverse average change of that current change can be seen on the overall channel current in the CiFET (the source channel current of the specific iFET utilized contains the positive average current change). This type of charge-movement or current-based logic concept originated in bipolars as current-mode logic (CML) where the inputs and outputs are in voltage, but the computation takes place with fast current signal swings in a staged differential BJT circuit much like Fig. 2.18a. The tradeoff with bipolar CML is that the power dissipation is great and it is only used when extremely fast digital logic is desired with little regard to a battery, and this CML requires a bipolar IC process. Here though, in the CiFET, its power dissipation is minimal as the current changes involved are in the pico- to nano- Fig. E.5 CiFET Schmitt trigger. 234 Fig. E.6 CiFET current inverter 96 . Amp range depending on the sizing of the CiFET. On the other hand, the results are similar, as there is a way to build logic gates out of the CiFET based on current, resulting in ultra-fast logic which has essentially no voltage change at both the input and output logic interconnect wires, and the inputs are referenced at the iPort termination resistance instead of the logic voltage transmitter providing very high noise immunity. This makes the logic parasitic insensitive and noise immune yielding very low power and extremely high frequency operation. There are also methods of throttling the speed/power relationship, or turning the circuits off and back on again at logic speed. When a current is injected into the iPort, it substitutes for its portion of the existing source channel current. This is because this total source channel current is controlled by its voltage between the gate and source, which has not been caused to change by the iPort current injection. Thus the origin of source channel current is steered around the drain channel through the iPort. 96 In theory, using the KCL ideal, we can see that the drain channel current is equal to the subtraction (or addition) of iPort current from (or to) the constant source channel current, which is fixed by the gate to source voltage. In reality, with any change to the iPort I/O current, the +/- change in source channel current is actually due to an averaging of the ratio of the sizing between the drain and source channels, which is entirely controllable. The top left behavioral model of Fig. C.1 illustrates the current swing effect. 235 This results in an exact subtraction of iPort current from the output drain current as there is no other current path. This introduces an entirely new MOS device: the ultra-fast precision “current inverter.” It is built out of digital parts and is process independent. More iPort current, yields less drain current, which is the output current. A current mirror operates the other way and is fragile. Also, the current can go in either direction passing through zero, truly bidirectional as compared to the base current of a bipolar. The source channel is exceptionally low resistance because it has a high overdrive on the gate while the voltage gradient along this source channel is clamped to near zero by the self- cascode structure of the iFET. This is similar to operating this channel in weak inversion, thus the channel current is driven by carrier diffusion (exponential), and not a voltage gradient (square- law) along this source channel. We have named this channel condition “super-saturation.” In contrast, weak inversion has few carriers which pass along the surface where they pick up noise from surface carrier traps. Because this source channel has an abundance of carriers and these carriers do not have to transit the channel length, the source channel operates faster than any other MOS channel known. The carriers only have to push on adjacent carriers (diffusion). A mental picture is that when a rock is thrown in the water, sound travels much faster than the wave produced. The iPort forms a new MOS device which will be called a “Current Inverter,” which is diagramed in Fig. E.6. Since the input is a current, multiple current signals can be wire-OR together by just connecting them; no additional inputs required. Fig. E.8 is a sketch of this. At low signal levels, this OR operation is a sum, at higher levels it is an OR gate, and for neuromorphic circuits, it connects neurons together for ultra-precision and fast operation. Here each input current 236 component adds to the total NiPort input current. If a PiPort is used the combination becomes AND. Fig. E.9 is a sketch of this. Each current takes away from the total PiPort input current. So far the source channel was discussed. The drain channel acts like a common gate MOSFET amplifier because its gate is held at the common iFET gate voltage bias and the drain channel is controlled by the current into its source. As such, the drain channel provides a low impedance voltage output drive completing the structure as a trans-resistance amplifier, where an input current transfers to a low impedance voltage output. Overall, the iFET appears to be an exponential device, but when the iFET is loaded by a current from some other source like a current mirror, there is a mismatch in the linearity of the combination. By loading the iFET with another iFET of the opposite diffusion type, this exact same circuit structure load linearizes the iFET, canceling all nonlinearities and yielding a totally linear circuit gain/transfer function. Any non-linearity cancels out by having the same deviation in the CiFET load device. They share the current path, thus they both pass the exact same current. For the fast feed-forward voltage amplifier output shown in Fig. F.1 in Appendix F, a precision of around 20 bits is illustrated. This is precision and linearity over a voltage gain of 1 million. If the feed-forward is not used, the voltage gain is about 100 million or 27 bits of digital accuracy. This of course, is limited by the noise floor, but indications are that the noise floor will cooperate as plotted in Fig. D.6-D.7. From what we have been able to project, the input referred noise will be around 10pA, but access to the newer IC processes is needed to prove this out it these target processes. 237 An example of the CCML concept is shown in Fig. E.7 while the current summing CiFET 4-input iNOR logic gate is shown in Fig. E.8 and a current summing 4-input iNAND logic gate is shown if Fig. E.9. The internal computation is performed by fast-switching small bi-directional iPort currents, while the inputs and outputs are converted from/to voltage signals for further computation as desired. Moreover, the complement iPorts can be utilized alone or in conjunction with each other; thus either adding together, or subtracting, or negating each other dependent on the polarity and magnitude of the iPort currents. The CiFET inverter, iNOR, and iNAND circuits are key neuromorphic circuit elements in the CiFET family of logic circuits. They can operate far below supply voltages of 1V, are extremely low-power, fast, compact, and able to be fabricated in the newest deep sub-µm processes. Expanding the CiFET CCML concept and family of circuits is part of the author’s future research work. Fig. E.7 CiFET digital CCML concept. 238 Fig. E.8 NiFET as a 4-input iNOR gate (a summing current inverter). Fig. E.9 PiFET as a 4-input iNAND logic gate. 239 CiFET High-Precision 2x Gain Amplifier without Precision Parts One of the most demanding, stringent, high precision, high linearity, and high speed requirements in analog IC design is for the precision 2x gain amplifier in a pipeline ADC. Nonlinear and unsymmetrical amplifier gain ultimately results in missing or overlapping codes. These amplifiers must also have the ability to subtract half scale dependent on the ADC’s comparator outputting a logic one or zero at each stage. If all pipeline ADC stages are the same, the errors imposed by the first stage contributes 50% since each succeeding stage errors are divided by 2. Therefore, it makes sense to design the first stage and a couple more with care. This first stage must also perform the input sample and hold function with a well-defined narrow aperture point in time that is highly independent of input voltage. The input stage may also require the highest dynamic range, often including signal swings a bit beyond the power rails while maintaining linearity over the extended range. The 3-Stage CiAmp provides exceptional performance in all these areas. The gain and speed are plotted in Figs. 4.18 and 4.19. If higher speed is required, at a little cost in gain the Feed- Forward version delivers. The CiAmp power and transient settling times are plotted in Fig. 4.20 and Fig D.5 respectively. An overview of design considerations illustrates the application of the CiFET to the next level of detail provides useful insight. Noise, especially 1/f noise, of MOS transistors limit the ADC’s usable resolution. Since the ADC is a clocked system, the use of correlated-double-sampling is the obvious means of circumventing the lower frequency 1/f noise. As a result, at higher conversion rates (higher frequencies), the CiAmp is less prone to its total output noise (V/Hz ½ ) characteristics which decrease faster than the gain as can be observed from Fig. D.8, making higher sample rates desirable from this standpoint. If needed the CiAmp can be optimized for lower noise, but its noise 240 is very low for the default CiFET sizing. The fully floating precision 2x differential amplifier configuration of Fig. D.22, using a pair of CiAmps, is a charge-mode candidate for this demanding application. The Phase-A switches around the CiAmps store the difference between the “Output Ref” and the sweet-spot self-bias voltage on “Coffset” capacitors and at the same time they track the 1/f noise of the CiAmps. During the same Phase-A time the “Cfly” capacitors acquire and track the input voltage (sample) and hold it at the sharp aperture time defined as the middle of the Phase- A turn-off logic fall time. In other words, at the end of the Phase-A the instantaneous 1/f noise along with the other voltages are immediately used to generate the output voltage during Phase-B cycle which holds this voltage on the CiAmp long enough to settle to 20-bit accuracy as plotted in Fig. D.5. During this Phase-B output time window, the offset voltage (between the sweet-spot and the Output-Ref) is switched in series with the sampled voltage (on “Cfly”) and these two series capacitors are tied around the CiAmp. During this Phase-B, the charge on these capacitors is preserved because one end of the series capacitors always sees the high impedance of the CiAmp input, thus not providing a charge transfer path (i.e. charge-mode design vantage point). The other end of these two series capacitors is tied to the CiAmp’s low impedance voltage output. This precisely places the exact voltage needed at the CiAmp output as the CiAmp input immediately returns to its sweet-spot voltage, analogous to the output being tied to input in Phase-A to establish the sweet spot. Fig. D.5 details these settling times and offsets using a ±500mV feedback. The reason the CiFET precisely self-biases at its sweet-spot is that the entire string of CiFET channels all pass exactly the same current (the current has no other path) and this requires a precise set of gate to channel voltages to get there. This combination of channel operating voltages bias the gate input somewhere around the middle of the power supplies at a precisely repeatable voltage, which 241 is also employed as the virtual ground reference that analog signals swing about. This is reminiscent of a differential pair but instead of voltage-mode it is observed from the charge-mode vantage point. If the CiAmp has a gain of 100 million, its input will move away from the sweet- spot by the output voltage divided by 100 million, in order to drive the CiAmp output there with a low output impedance. Since this feedback capacitor charge preservation prevents the output to input voltage difference from changing, the output error will be exactly the same as the input displacement voltage that drives the CiAmp output there. This is just like inserting a precision voltage supply from output to input. The output will not quite reach its intended value by the CiAmp gain error establishing accuracies approaching 160dB or 27 digital bit equivalent. This is why the errors in table D.1 are consistent with its feed-forward CiAmp somewhat lower gain of 1 million. There are a couple of non-error potential error sources to be noted. The most prevalent ones are the parasitic capacitances on the amplifier input terminal and also the input side of the Coffset capacitor. A change in voltage on the Coffset circuit nodes would transfer some charge between Coffset and the parasitic capacitances at either terminal of Coffset. Because the sweet-spot voltage on the amplifier input is unchanging and likewise the voltage on the other side of this Coffset capacitor is held constant from Phase-A to Phase-B, there is no voltage change on either side of Coffset along with all of its related parasitic capacitances. Thus, parasitic capacitance has no effect here (all easily observed through charge-mode design). Also, power supply noise injection is balanced out because the sweet-spot is halfway between the power rails. Careful physical layout should be observed here to balance the Coffset parasitics. The sampling capacitors, Cfly, do change voltage across them between Phase-A and Phase- B, but these 2 capacitors differentially go in opposite directions canceling out any parasitic induced 242 errors on their high impedance Coffset side. The parasitic capacitance on the output side of Cfly has no effect because this terminal is always driven from a low impedance of either the input signal source or the output of the CiAmp’s voltage output. Thus the critical node to be optimized during physical layout is the CiAmp input side of the sample capacitors which normally operate differentially around the system virtual ground which the input voltages usually swing about. This node is at a low impedance during sample Phase-A and high impedance during the output Phase- B. In a non-differential configuration, these capacitors are sized to control these parasitic induced errors. These capacitors may go from 50fF to 200fF or 300fF to reduce these errors sufficiently for high precision operation that the rest of the circuit operates to. There is another error source which is a result of imbalanced switch charge transfer from the control logic signals through the switches and on to the capacitors at the switch turn-off time. When viewed as a charge transfer, it has experimentally been verified that matching the switch p- channel and n-channel area capacitances best cancels out most of these errors. With this method, with default capacitor sizes, errors normally cancel in the 1 million to one ratio, which is similar to the gain errors of the CiAmps. These charge balance errors do increase with larger signal swings and are likely a limiting error component. This balanced charge cancelation is valid when signals are in the middle ¾ of the power supplies and not too bad closer to the rails. Several methods of further enhancing this charge injection has been tried, but they seem to be worse in practice, which is due to the more complicated structures required. Like in RF design, fixes with a Band-Aid often make the problem worse as opposed to operation without the Band-Aid attached. The rule of clean and simple generally indicates that the correct fundamental solution has been found. Other than noise, these are probably the limiting source of inaccuracies, but due to its known cause, some 243 errors can be compensated for or averaged with digital calibration processing when attacking ultra- high precision limits is the goal. There are several methods to subtract or add half scale for ADC and DAC applications. One way is to switch the Output-Ref terminal between half scale and zero and another method is to include an additional pair of capacitors with half scale in the series string during the output Phase- B. Any scaling voltage can be added or subtracted. There are also ways of running the circuit backwards in order to make a pipeline DAC. As an alternate to a pipeline, two stages can be clocked with opposite phases and their residue outputs tied back in a loop to make a fast high- precision recirculating successive-approximation class of ADC or DAC using minimal hardware and power. DACs do not use the ADC comparator but the rest of the ADC is essentially run backwards (LSB first instead of the ADC MSB first)—kind of a mind-bender, but it works perfectly. Note that the initial ADC inputs have an extended dynamic range up to a diode drop outside of the power supply rails. Here the residue can be reduced by alternative math for the first couple of bits. This leans a little harder on the accuracy of these more significant bits. Fig. E.11 pictorially illustrates the extreme precision and linearity of the ultra-precision fully-differential 2x gain amplifier of Fig. E.10. The sample input, sample clock, and 2x output waveforms are shown in Fig. E.11 for the circuit of Fig. E.10. The amplifier output data valid logic signal is the red trace in the middle of the input on the top and the amplifier output on the bottom. This “Floating Differential Output” voltage can be transferred to CLoad for a continuous output or used directly. Both input and output are floating differential signals independent of power supplies, where noise would enter the signal path. In this waveform plot of Fig. E.11 there 244 are 320 values of input voltage applied successively at 2.5mV spacing for a set of outputs with 5mV spacing. Using this 2x amplifier circuit, the input range was biased to go 500mV outside of the power rails for about 25% of the traces to demonstrate this capability. In addition, the capacitors that were used to generate these waveforms were unbalanced by 50% to demonstrate the ability to operate without precision parts. The output is also floating and the output waveform is taken across the floating load capacitor, which simulates the load of a following stage. The low impedance of CiAmp voltage-mode outputs drives these outputs with little regard to parasitic capacitive loading. These waveforms show a fine vertical line at the beginning of the data-ready logic signal, but this tiny transient goes away at CiAmp speed. This is where the differential load capacitor modeling the load of a following stage is connected from the raw CiAmp outputs to the load capacitor of the following stage or output load. 245 Fig. E.10 Ultra-precise full floating 2x differential CiAmp application. 246 Fig. E.11 Full-floating ultra-precision 2x differential CiAmp waveforms. 247 Fig, E.12 is a 64-level ladder voltage reference generator operating in a charge-mode. It has 64 voltage outputs spaced exactly 20mV apart. The ladder is for a flash ADC with a conversion range going from 256mV to 1,536mV. These 64 ladder voltages are also offset by +10mV to center the ADC conversion windows properly for ADC decisions in the middle of their respective voltage windows. This ladder gets its accuracy by considering it in the charge-mode. First the ladder capacitors are charged in series across the entire 1,536mV reference. As a side note, this is generated from a CiFET PTAT/CTAT reference including precision CiAmp amplification. After charging the series string of capacitors, they possess varying voltages which are proportional to their relative values. In order to avoid the requirement of precision capacitor matching, the entire string is reconnected in parallel to equalize their voltages, and then put back in series yielding precision 20mV steps. Just to prove the ability to generate precision without any precision parts, a pair of adjacent capacitor values were made 100% different. They are around the 2/3 level and with this mismatch, the precision remained better than 1µV. The ladder output pictured was derived in three 4x higher amplitude steps as can be seen on the left by the voltages coming from a split of 4 finer values each. This enhances precision while reducing the value of the capacitors used to around 25fF each. This stepped approach also illustrates that all the voltages do not need to be generated, but just the desired window of voltages. The half scale offset was made with a pair of series capacitors charged to the 20mV step voltage when the capacitor bank was connected in parallel, and then rearranging them in parallel at the bottom of the 64-series capacitor string to jack the entire set of voltages up by 10mV. All of this was conceived of with the charge-mode hat on and manipulating charge while preserving the voltage across the capacitors with high impedance as needed. It also reveals the potential error source limits clearly so that they can be dealt with cleanly. 248 Fig. E.12 Charge-mode flash ADC-DAC voltage ladder output waveform. 249 CiFET Charge-Mode Array Readout Looking at a conventional CMOS focal plane array (FPA) from a charge-mode analog prospective immediately reveals that the charge on the absolute minimum pixel capacitance, Cfd, must be preserved as the primary concern. Readout sensitivity at the single electron level on the Cfd capacitance is the ultimate design goal. For this, the Cfd charge level is read out by buffering its voltage Vfd through a common drain (i.e. source follower) amplifier configuration (see Fig. 2.27b and Table 2.7) to preserve stored charge without adding capacitance to Cfd. It works, but the limitations are: 1) the source follower configuration does not have voltage gain to lift the signal out of the noise while contributing some of its own, and 2) this readout is speed-accuracy limited because this readout circuit configuration pulls the analog readout bus up fast with the source follower low output impedance, but the pull-down depends on a constant current source which has a high impedance—therefore, it doesn’t have the ability to pull harder to settle the analog bus to the required ADC accuracy and also contributes more noise to the signal. In general, the higher the impedance, the higher the noise contribution. In order to obtain a general feel for the order of magnitudes and limits involved the following example is used: with a 10fF total Cfd capacitance and the assumption that all photons ionize 1 electron each, every photon would contribute 16uV to the pixel voltage; while 100,000 photons (1 * 10 5 = five digits or decades, equivalent to 17-bit digital resolution) would produce 1.6V as summarized previously in Table D.2. To maintain resolution, this signal must be kept clean and read out/digitized quickly to beat the 1/f noise that is knocking at the door. 250 Fig. E.13 is an example of a conventional 4 transistor (4T) pixel cell with its associated control and readout. The central pixel circuit details a single of many pixels, and the surrounding circuitry that processes this pixel. The pixel output voltage must drive the high impedance bias current source “ILoad,” along with a high capacitive “Readout Column,” plus the ADC input. This constant linear ILoad current is used to bias the source follower which is functionally mismatched to the source-follower square-law pull-up as will be discussed in the Appendices for the CiFET device. Fig. E.13 Conventional 4T-pixel focal plane array with readout. 251 The representative pixel circuit located in the center of Fig E.13 starts with the light sensing pin-photo diode (PPD). Initially the voltage on all PPDs are set to the externally provided Vrst voltage by means of turning on both of the “Initialize” and “Expose” transistor switches together. This initializes the voltage Vfd to Vrst which can be used to adjust the average exposure brightness by centering the dynamic range of the entire array’s readout. When the Initialize switch is turned off, the PPD begins to accumulate electrons from the conversion of photons being captured in the PPD. During the “Expose” time, these electrons are shared between the PPD capacitance and the Cfd capacitance. After the end of the Expose logic switch signal, the charge on Cfd is frozen with a small feed-through error charge passed from the gate to drain of the Expose transistor switch. Fortunately, since all pixels get the same turn-off charge packet offset, this error drops out. During the expose time and up to the readout time, Cfd is subject to acquiring 1/f noise, dominant in MOSFETs, as well as accumulating any charge leakage. This is minimized on the first row to be read out, but gets longer as the wave of readouts propagate across the array during the readout phase. The pixel storage capacitor Cfd is physically designed to have minimum possible capacitance in order to maximize sensitivity in low light conditions. Cfd is the parasitic capacitance of the pixel “Source Follower” transistor gate plus the minimum diffusion of two series transistors “TX” and “RT.” With a minimum Cfd capacitance, fewer photo generated electrons are required to increase voltage on Vfd. The Vfd analog voltage of each pixel is buffered by its pixel “source follower” transistor to read out one row at a time by turning on with the “Row Sel” switch, an analog word select operation. During the row select time, a bias current is drawn out of the all “Readout Columns” 252 through their pixel source-followers, routing their bias currents (ILoad) through the row switches and the pixel “source followers” configuring them as a unity gain buffer amplifier by biasing the source follower transistors in their active region. The purpose of the source followers is to preserve the pixel voltages Vfd by high-impedance sensing their stored charge on their respective Cfd pixel nodes. As a source follower, they have no gain and do in fact contribute noise. This presents an opportunity to use the exponential gain and low noise aspects of the super- saturated source channel of a CiFET, as seen in Fig E.14. Amazingly, this can be done without changing any of the pixel array cells, just: 1) replacing the current bias transistors with a PiFET, 2) connecting the “VDDPIX” voltage from Vdd to Vss in effect reversing the direction of the pixel readout currents, and 3) switching the “Row Select” logic signal between Vss and the CiFET “sweet-spot” self-bias voltage instead of the Vss to Vdd logic swing. Thus for each row readout, a new CiFET is formed by the pixel source follower plus the Row Select transistors for the NiFET with the common PiFET as the column bias supply. This engages the advantages of a fast, linear, accurate, low impedance voltage driven output, bypassing the shortcomings of the source-follower readout. The Vfd pixel capacitance is buffed with the same high impedance, but it has a high exponential gain, wide dynamic range, high-linearity, low- noise when loaded into its CMOS PiFET complement. Here the PiFET’s supplies a log-domain linearizing load to the exponential source channel within the pixel NiFET. In addition, a thin high accuracy, low power CiFET recirculating ADC would provide an ideal counterpart forming a low-pitch ADC readout digitizer array in the column readout electronics which is made up of a minimal number of small CiAmp transistors. 253 Fig. E.14 Conventional 4T-pixel focal plane array configured to a CiFET readout. 254 This introduces yet another variation of the CiFET compound device that exploits the self- cascode properties of the iFET, within the CiFET compound device structure as will be discussed in previously. In this case the analogous CiFET technique is also an attractive candidate for SRAMS. There can be separate access to the source channel in either or both polarities of the CiFET. This source channel gates operate super-saturated channels in a fully exponential mode. These additional voltage-mode input ports can be used to bias the compound device as in the seminal CiFET, or used to turn the compound CiFET device ON and OFF at logic speed where the low impedance voltage output is immediately biased and ready to go. For the time being, this variation of the CiFET is being named the CxiFET and follows the usual aaah-ahas of looking at circuits through charge-mode eyes. 255 Appendix F CHARGE-MODE INSIGHTS REGARDING THE CIFET MOS Output Characteristics for a Fixed V gs : The same fixed gate voltage, which is a convenient value to identify as threshold voltage, drives both conduction mechanism curves for both the voltage driven current component and for diffusion driven current component. 97 This is where these two curves are equal in output drain current as seen in Figs. 2.22 and 2.23. Thus at threshold voltage, ½ of the total MOS drain current is exponential (diffusion driven charge) and ½ of the current is quadratic (voltage driven charge). On a log scale, this exponential (diffusion) current component extends over a large number of decades as it approaches the y-axis, which is at zero drain-to-source voltage across the channel. The quadric (voltage gradient driven) current component does not contribute drain current up to the parabola’s vertex (0,0) = V0 after which it quickly dominates the total current as drain to source voltage increases. Thus, on a log scale, the exponential current goes on forever in the low current direction while the quadratic current is 50% imposed at threshold voltage and dominates at higher source to drain voltage adding about a decade of current increase. This gives the impression of a discontinuity at threshold voltage between turn ON and turn OFF in the digital world. 97 In the EKV and BSIM6 models, these two current components are simply summed over all operating ranges to provide the drain current. 256 When one considers that the drain current is made up of the sum of two separate components, it is apparent that there is actually no linear (triode resistance) region for the drain current, but this middle triode region is a linearized approximation of the merger of these two non- linear functions in this region of operation which is termed “moderate inversion.” This resistive linearization a useful minds-eye approximation around the “threshold voltage,” which is a carryover from vacuum tubes. It is actually a linearized approximation merger of approximately equal slopes of the exponential with the quadratic functions instead of being an authentic linear region. Figs. F.1-F.4 help one to visualize this description. This charge-mode design prospective suggests that in order to optimize for the higher gain and wider dynamic range, the quadric component should be suppressed and the exponential component enhanced. In general, this is realized by limiting the output voltage to less than V0 or moving V0 to a higher voltage. When the iFET operates in the exponential region, it is easy to linearize the output through the use of an anti-log load which is the exponential complement of the CiFET. Fig. F.1 Generalized parabolas which describes a FET voltage driven strong inversion operation in the positive plane and covers less than a decade of dynamic range. 257 Fig. F.2 Generalized exponential describing a FET diffusion driven weak inversion operation, which actually stretches way out in the x direction over ~8 decades before the noise floor. The y-axis crossover point is at the channel zero-bias leakage current I0. Fig. F.3 Combined exponential (below Vth) and parabola (above Vth) from the MOSFET I-V characteristics. 258 Fig. F.4 Plot representing the MOS exponential region as a straight line on a log scale and the linear region is a straight line on the linear scale (Source: Nanoscale). Now that there is a charge prospective understanding of the MOSFET conduction mechanism, it becomes obvious that the FET can be operated in a ~purely exponential mode through limiting the voltage below the parabolic vertex that drives the current along the conduction channel. The iFET does this inherently by clamping the iPort to a low voltage from both gates being tied together. The resulting super-saturated channel delivers the optimal solution. The end goal is to operate the input gain FET (herein identified as the source channel) in this exponential region and then to load its drain output (identified as the complementary source 259 channel) with a precise complement, derived through the CMOS enabled opposite diffusion type, to cancel the exponential gain transfer function (anti-log). Because the exponential holds over more decades than are useful, this yield a linearized output over the same number of decades. This leaves the drain channel with the CiFET output voltage causing it to operate in the quadratic mode. Because of the complementary device load to the drain channels also, these quadratic nonlinearities are canceled out very well, and even become more ideal at low power supply voltages. Here the drain channel operates with a low voltage across its drain channel pushing this device into super-saturation exponential operation also. This is why the gain peaks (exponential mode) at power supply voltages of around 600mV to 800mV where the drain channels are operated with about 200mV to 300mV across them. The process of extracting the model parameters from V-I characteristics can be characterized by this virtual threshold point to match these two (exponential–diffusion and quadratic drift) model defining equations to match in current, along with the 1 st and 2 nd order derivatives making 50%-50% drift = diffusion at this virtual threshold voltage crossover point. The newest compact simulation models do not switch between these two operating equations as all previous simulation models have done, but it merely adds these two current components to get a continuous result that matches the charge-based model viewpoint. The charge-based EKV [19] and Mayer-Mead [61] models of the MOSFET are good references for understanding this concept. 260 An Interesting Simulation Perspective Interrelated to Charge-Mode Design: Circuit simulation can be done in charge-mode. Here all circuit nodes have a capacitance associated with them. A resistive network connects these capacitors together forming the circuit of interest. In an integrated circuit at lower frequencies, unless specifically formed, inductances are insignificant on the scale of interest. When specifically required, such as higher frequencies, inductors can be modeled with a dual of capacitors similar to the coupled ring VCO of Chapter 3. At any instant of time, these capacitances contain a discrete charge that represent the voltages at their respective nodes. To get to the next discrete instant of time, there is a charge flow through these resistors for the duration time step to the following instant of time forming a new set of charged capacitances. This is simply repeated. The charge-mode advantage is similar to getting map directions in terms of a list of distances between incremental points as compared to working from a list of specific velocities with their durations. iFET Operational Synopsis: The iFET of Fig. 4.4 is a self-cascoding FET structure that has many of the benefits of a cascoded transistor pair, except that the additional cascode bias voltage is self-generated at the minimum possible voltage, i.e. zero voltage between the two levels of cascode gates, therefore eliminating stacked gate voltages which is especially advantageous at low voltage IC process nodes. This structure consists of two series FET channels, and since these two channels are in series, they conduct the same current. For an unambiguous identification of these two series transistors, the transistor adjoining the ultimate source will be named the “source channel” and the other transistor adjacent to the ultimate drain as the “drain channel.” The merged diffusion in 261 between the two channels is called the “iPort,” which is a trans-resistance current injection port to be explained soon. When there is no connection to the iPort, the current traveling through these two series channels is constrained to be the exact same current in both channels. If the drain channel is a little bit wider than the source channel, the drain channel will have a lower current density, which is proportional to the difference in widths. A slightly lower gate to source voltage is thus required to drive the drain channel, which is operating at a lower current density than the source channel. Since both channels have the same common gate voltage, this difference in operating voltage appears at the iPort. This iPort turns out to be a series bandgap type reference that exhibits a PTAT characteristic over an extended temperature range as shown in Fig. E.2. An interesting note is that through use of an opposite diffusion type P-channel cascode pair, its iPort voltage is the complement or CTAT. “NiPort” and “PiPort” will be used to differentiate these two iPorts. Their temperature dependence cancels offering the opportunity to make a reference that is independent of temperature. The limitations need to be investigated as one of the voluminous ah-ha’s that come up at every turn of this CiFET technology unfolding. Super-Saturated Channel Concept, Definition, and Insights A super-saturated channel is created by applying an excessive gate overdrive voltage while clamping the channel source to drain voltage at a low value, much lower than the gate voltage, forcing a high concentration of carriers deep in a subterranean channel ready to instantaneously pass a current by diffusion instead of carrier transport. The channel current has an exponential behavior, analogous to the sought-after high gain of a weak-inversion channel, but differs in that the output impedance is low as a result of the high concentration of carriers. 262 The charge transmission, or current, is an extremely high-speed mechanism resulting from carriers not needing to transit the channel, but instead pass their energy from one carrier to an adjacent carrier similar to Newton’s Cradle as shown in Fig. F.5. Here the velocity of the end ball resembles charge movement, and the much higher velocity through the dense ball set is vastly different. The animated Newton’s Cradle example is a very good likeness of iFET operation. 98 The first or right-most ball represents the charge entering the super-saturated source channel, which is the chain of balls in contact with one another. The speed of energy being transmitted into the chain is slow in comparison to rapid energy transmission through the chain, where the balls do not move significantly, to the end where the end ball continues to carry the energy to the next chain of balls, which represents the highly saturated drain channel (coincidently going up-hill a bit reflecting an increase in voltage). The energy comes out of the drain channel at a voltage gain depending on the drain channel length (representing rm, the iFET’s transresistance gain in Ω). Although the rm is high, the output impedance is low and not the anticipated resistance value of rm. Fig. F.5 Newton’s cradle of collision balls as an analogy of the super- saturated channel conduction. (Source: Sci. Am. N.Y.) 98 Newton’s cradle animation resource: https://www.lhup.edu/~dsimanek/scenario/cradle.htm 263 In the CiFET, the output impedance is similar to that of a logic inverter which drives varying capacitive loads fast and without significant effect on accuracy. If the balls are in multiple parallel chains or bigger in the first cradle then the ball is in the second cradle, there will be an instantaneous speed gain, according to the two channel ratios, when the energy is transferred to the upper cradle, representative to a gain (rm in the case of the iFET). Although it is not necessary, a mask consideration or process enhancement to both planar transistors or finFETs could optimize these CiFET properties by creating a doping profile that moves the preferred conduction path away from the surface slightly avoiding surface carrier traps forming a buried channel. Depressed and buried layers have been around since the bipolar devices used them as illustrated in Fig. 2.11 in the case of the BJT. A minimal doping profile adjustment which pushes the threshold slightly deeper in the channel could bias the carries mostly below the surface carrier traps. The doping profile could also be tapered between source and drain, possibly by mask enhancement, to enhance a uniform deep channel when the operating bias voltages are applied as in the drain channel. In another analogy, this super-saturated conduction mechanism is similar to the transmission speed of a sound pressure wave through deep water as opposed to water movement on the surface. Sound travels fast and cares little about the surface roughness, but surface flow rate is much slower and is affected by surface conditions. Likewise, this super-saturated channel mechanism avoids velocity saturation and hot carrier issues. The response speed is not limited to the MOFET carrier terminal velocity when charge is introduced or removed by the iPort, where the carrier injection is totally bi-directional and includes zero. This extra speed could be very beneficial to logic and neuromorphic circuit applications of the CiFET. In addition, in a CiFET the predominant MOSFET 1/f noise will be remarkably low as a consequence of channel carriers not significantly moving and being pushed down away from the 264 surface carrier traps. The low noise of the depressed conduction channel is reminiscent of a low noise JFET, only noise simulation indicates that the noise may be significantly lower as will be investigated in future research into the CiTIA as a low noise amplifier. Additionally, because the super-saturated channels are low resistance, the resistance (collision) generated noise component is at its lowest minimum. In the CiTIA configuration, an iPort input resistance can be set to 50 Ω, matching the source channels to a transmission line and will be well suited to S-parameter analysis in RF circuits. The CiFET device operation is primarily a function of the relative iFET channel strength (conductance) ratio and not so much the IC process node parameters such as feature size or threshold voltage. Since both the source and drain channels are adjacent to each other in the same silicon region, these ratios do not vary significantly. This attests to the portability of the circuits made out of CiFETs. 265 Epilogue Let me paint a picture. There is a crisp autumn wind blowing from the north. The air is tinted with salt and seaweed. A few wispy clouds dot the blue sky. The sun is shining. Ocean waves crash off the Huntington Beach pier pilings below me. I am sitting on a concrete bench dedicated to someone that was loved dearly. A lone blue-eyed pelican has just landed on the railing, keeping me company. It’s a Monday. November 30, 2015, at 1:21pm to be exact. Surfers are catching nicely-sized rights in the distance. A set of grandparents with their 3 giddy grandchildren stop to take a picture, posing next to the majestic bird. Seagulls playfully glide around me, looking for snacks. I am comforted by the warmth of the coffee in my hands and the powerful sounds of wind and water around me. I take a very deep breath. Then I exhale it all out. I will remember this moment forever. I am done. I have made it. I passed. I climbed one hell of a tough mountain in my career. I may not have been the fastest or have taken a well-defined route, but I did it. Against so many odds. When I began this journey, I was literally told that I would never make it. That I was stubborn. That I did not listen. That I did not belong. At times, I almost believed these things. When my daughter was born and I realized I was going to be a single mom in my first semester; when she was later diagnosed with non-verbal autism and I was left wholly stunned—staring into a dark hole which I had no idea of what to expect; when I had to support myself and was completely alone, working in the lab testing or at the computer all night laying out circuits; when people I thought were my friends ended up not really being so—just self-serving and backbiting; when I 266 lost my funding and had to work multiple teaching and research assistantships to make it through; when my advisor died unexpectedly and I did not know who to turn to; when I had family problems at home; when I was humbled with severe vertigo; when my work was denied; and when I felt like a complete failure in life. But these types of things happen. They are predictably unpredictable. They color my story. The truth is that it has always been my choice to follow this path. No one else’s. Mine. I am solely the master of my own fate. I believe this adventure that is the Ph.D. has made me a better person: full of gratitude, love, happiness, strength, resourcefulness, and compassion. It also taught me to ask for help. To keep trying when I was told “no”. To expect the expected. And to never become bitter, to remain hopeful, and to never give up. I say these things not to embarrass myself or those close to me with brutal honesty nor because there is that possibility that no one will ever get this far reading my thesis to even notice the Epilogue section. (I do have a healthy sense of humor.) But because maybe somehow and in some way I can impart courage onto a person out there who wants to make a positive impact in this world with their unconventional thoughts or creative handiwork, who also is silently suffering from self-doubt or exhaustion or hopelessness in their life and work. Maybe they will see this. To those nonconformists, I say: Believe in yourself. Be strong. Be brave. Keep going. These are the words I whisper to myself and my daughter. And I pass them on to you. Use them wisely. And don’t forget to take care of yourself. Hold your own hand like it is that of a child full of wonder and discovery. Protect your sense of awe and that of others. Know that what is called “truth” and “right” is ever-changing and subjective. In that sense, trust your gut, in order to know 267 the path you must follow. Remember to treat others as you yourself would like to be treated. And, lastly, do your best at all times. Meanwhile, the pelican hanging out next to me has just spread her wings, found her target, and fearlessly dive-bombed into the icy Pacific water, right in between the surfers. She re-emerges with a shiny, flapping mackerel, which unceremoniously is gulped down as the beautiful bird flies off into the horizon to join an odd-numbered crew gliding by. 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"COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS," PCT International Application No. PCT/US2015/042696. July 2015. 280 About the Author Susan Schober is an electrical engineer with expertise in the area of analog integrated circuit design. She is a co-founder at Circuit Seed, LLC and she also teaches in Los Angeles at USC, her alma mater. Susan has experience from the start to finish of an IC including the specifications, design, layout, simulation, photolithography, fabrication, testing, and commercialization of radio- frequency, mixed signal, and analog circuits and systems. Her research interests include creating novel, low power analog circuits for ultra-deep sub-um and nanoscale CMOS technologies, developing phase-locked loops for multi-GHz frequency synthesis, designing mixed-signal IC blocks for wireless and wireline systems including amplifiers, ADCs, and DACs, and the automation of analog circuit design. She holds numerous patents for her creative circuits. Usually, you can find Susan strolling around ISSCC every year with her father. Susan is an advocate for women in engineering and for those with autism and developmental disabilities. For fun, she rides and trains rescue horses for competitive endurance riding. She also swears by Crossfit to stay healthy, strong, and happy. Her updated CV is available at: www.linkedin.com/in/susanschober She may be contacted via email: susanschober@gmail.com

Abstract (if available)

Abstract The demand for connectivity is expanding at an extremely rapid pace. By year-end 2015, the number of global network connections will exceed two times the world population (i.e. 7 billion), and it is estimated that in 2020 more than 50 billion devices will be wirelessly connected to the cloud forming the Internet of Things (IoT). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last few decades. This was fueled in large part by Moore’s Law, coupled with research and development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) transistors, which facilitated incorporating digital and analog circuit components, such as transceivers, into a single, reliable system-on-chip (SoC). ❧ However, in recent years, while digital circuits have largely followed their predicted path and have benefited from the scaling of CMOS into ultra-deep submicron (sub-µm) and nanoscale technologies, analog circuits have failed to follow the same trend. Analog and radio frequency (RF) designers remain to discover how to construct scalable, high-performance integrated circuits (ICs) for feature sizes below 45nm without losing the benefits of shrinking, including reduced power, compact area, and higher operational frequencies. A paradigm shift is the only way to break through the established science of analog design to meet the SoC demands of the next generation. ❧ This work explores the historical trends of analog circuits, discusses present-day challenges, and introduces a novel charge-based approach for designing scalable CMOS analog circuits. The charge-mode perspective ultimately enables analog circuit fabrication in all-digital deep sub-µm IC processes and gives hope to the possibility of analog design flow automation due to its distinctive attributes (i.e. compact, simple digital-like device building blocks with no traditional current mirrors or bulky, threshold-stacked transistors). As a demonstration of the proposed analog design concept, a complete phase-locked loop (PLL) system is designed using specific circuits that have been created using the charge-mode methodology, namely the charge pump (CP), phase-frequency detector (PFD), and voltage controlled oscillator (VCO). Additionally, this dissertation introduces a promising new patented building block, the complementary injection field effect transistor (CiFET) device, to the charge-mode toolbox. The CiFET seminal cell and family of circuits allow for analog functionality, such as amplification, at nanoscale feature sizes and supply voltages far below 1V. All of these analog circuits have been fabricated in 40nm CMOS, physically tested, and compared to the state-of-the-art. The thesis concludes by envisioning the direction of where analog ICs are headed in the not-so-distant future.

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University of Southern California Dissertations and Theses

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Improving the speed-power-accuracy trade-off in low-power analog circuits by reverse back-body biasing

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Creator Schober, Susan M. (author)

Core Title Charge-mode analog IC design: a scalable, energy-efficient approach for designing analog circuits in ultra-deep sub-µm all-digital CMOS technologies

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 12/16/2015

Defense Date 09/04/2015

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag analog circuits,analog integrated circuit design,charge coupling,charge mode,charge pump,CiFET,CMOS,complementary complex logic,complementary injection field effect transistor,current mode,D flip-flop,DFF,energy efficient,finFET,frequency synthesis,high performance,iFET,Internet of Things,IoT,low power,nanoscale,neuromorphic circuits,OAI-PMH Harvest,PFD,phase frequency detector,phase locked loop,PLL,ring oscillator,scalable,Soc,switched capacitor,transistors,ultra-deep sub-µm,VCO,voltage controlled oscillator,voltage mode

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Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Chen, Shuo-Wei (Mike) (committee chair), Choma, John, Jr. (committee chair), Maby, Edward W. (committee chair), Gupta, Sandeep (committee member), Moore, James E., II (committee member), Pedram, Massoud (committee member)

Creator Email schober@usc.edu,susanschober@gmail.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c40-203856

Unique identifier UC11276884

Identifier etd-SchoberSus-4063.pdf (filename),usctheses-c40-203856 (legacy record id)

Legacy Identifier etd-SchoberSus-4063.pdf

Dmrecord 203856

Document Type Dissertation

Format application/pdf (imt)

Rights Schober, Susan M.

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA