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Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics

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Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics

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Content MODELING AND MITIGATION OF RADIATION-INDUCED CHARGE SHARING EFFECTS IN ADVANCED ELECTRONICS by Mahta Haghi A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2012 Copyright 2012 Mahta Haghi ii DEDICATION To my parents, Mehrangiz Changizi and Mohammad Ali Haghi, and my husband Alireza Kheirkhahi iii ACKNOWLEDGEMENTS I would like to thank my advisor, Professor Jeffrey Draper, who not only mentored me throughout this research but also inspired me as a human being. I also thank my PhD dissertation committee members. Special thanks to Jeff Sondeen for his help all through my PhD. iv TABLE OF CONTENTS DEDICATION .................................................................................................................... ii ACKNOWLEDGEMENTS ............................................................................................... iii LIST OF TABLES ............................................................................................................. vi TABLE OF FIGURES ..................................................................................................... viii ABSTRACT ...................................................................................................................... xii ABSTRACT ...................................................................................................................... xii CHAPTER 1: INTRODUCTION .................................................................................. 1 1.2 History of radiation effects ................................................................................. 4 1.3 Research contributions ........................................................................................ 5 1.4 Organization of the dissertation ........................................................................ 14 CHAPTER 2: RADIATION EFFECTS ON MICROELECTRONICS ....................... 16 2.1 Radiation sources and environments ................................................................ 16 2.2 Radiation effects ............................................................................................... 19 2.3 Radiation hardening .......................................................................................... 25 2.4 Technology CAD tools ..................................................................................... 26 CHAPTER 3: CHARGE SHARING AND COLLECTION IN DEEP SUB-MICRON TECHNOLOGIES .................................................................................. 29 3.1 Charge sharing mechanisms ............................................................................. 32 3.2 Circuit model for charge sharing and collection in deep sub-micron technologies .................................................................................................................. 40 CHAPTER 4: CHARGE SHARING AND COLLECTING MITIGATION TECHNIQUES ........................................................................................ 49 4.1 Proposed RHBD layout technique .................................................................... 50 4.2 Study of deep trench isolation (DTI) as an RHBP technique in MOSFET ...... 57 CHAPTER 5: MOS CURRENT MODE LOGIC ........................................................ 69 5.1 MCML structure ............................................................................................... 70 5.2 MCML performance ......................................................................................... 71 5.3 MCML applications .......................................................................................... 72 5.4 Single-event upset sensitivity analysis of MCML sequential elements............ 73 5.5 Proposed RHBD MCML sequential element ................................................... 82 v CHAPTER 6: SINGLE EVENT TRANSIENT IN COMBINATIONAL LOGIC ...... 91 6.1 Existing SET mitigation techniques.................................................................. 91 6.2 Proposed RHBD technique ............................................................................... 94 CHAPTER 7: RADIATION EFFECTS ON ELECTRONICS IN ALIGNED CARBON NANOTUBE TECHNOLOGY (RADCNT) ................................................ 103 7.1 Brief history of carbon nanotubes ................................................................... 104 7.2 Structure of carbon nanotube .......................................................................... 105 7.3 Electronic structure and properties ................................................................. 108 7.4 Synthesis ......................................................................................................... 109 7.5 Aligned single-walled carbon nanotube.......................................................... 110 7.6 Radiation response of SWNTs ........................................................................ 113 CHAPTER 8: CONCLUSION ................................................................................... 123 8.1 Future work ..................................................................................................... 124 REFERENCES ............................................................................................................... 126 COMPREHENSIVE REFERENCES ............................................................................. 135 vi LIST OF TABLES Table 1. Projected failure rate on sram-based applications due to neutron Effects (ACTEL)…………………………………………………………………………2 Table 2. Collected charge at drain of passive device for minimum nodal Separation (TCAD versus proposed model)…..…………………………….…………...44 Table 3. Collected charge at drain of passive device for 2x nodal separation (TCAD versus proposed model)…..………………………………………….45 Table 4. Collected charge at drain of passive device for 4x nodal separation (TCAD versus proposed model)…..……………….…………………………46 Table 5. Area comparison ……………………………...…………………………54 Table 6. Performance comparison from post layout simulations………………….55 Table 7. Collected charge at the passive PMOS for different LETs and mitigation techniques.……..…………………………………..…………………………63 Table 8. Collected charge at the passive NMOS for different LETs and mitigation techniques………………………..………………………………….……….63 Table 9. Percentage in the Collected charge reduction at the passive PMOS for different LETs and mitigation techniques….…………….…..………………64 Table 10. Percentage in the Collected charge reduction at the passive NMOS for different LETs and mitigation techniques.……………………..……………64 Table 11. Q crit Improvement with current bias at clock rate of 0.5 GHz...…………77 Table 12. Resistor and transistor sizes for ΔV =300 milivolts for bias current of 30 and 100 µA…………………………………………………………...…………....78 Table 13. Q crit Improvement with ΔV for different bias currents at clock rate of 0.5 GHz…………………………………………………………………………….....80 Table 14. Clock-to-Q delays for different bias currents……………………………80 Table 15. Critical Charge Improvement in Non-Hard and Hard MCML…………..86 Table 16. Critical charge improvement by increasing the bias current………...…..89 Table 17. Pulse width reduction for different SET pulse widths…………………...97 vii Table 18. Area overhead for the weak-latch…………………………………….....99 Table 19. Area and delay overheads comparison for chain of inverters versus weak-latch……………………………………………………………..………………..100 Table 20. SET pulse widths for heavy ions with different LETs………………….102 viii TABLE OF FIGURES Figure 1. Radiation Environments [72] ........................................................................ 16 Figure 2. Secondary particles generated by the interaction of cosmic rays with atmospheric atoms [107] ................................................................................................... 19 Figure 3. Ion Strike on drain of an off-NMOS Transistor [72] .................................... 20 Figure 4. Total ionization dose [72] ............................................................................. 22 Figure 5. Silicon on Insulator structure [53] ................................................................ 25 Figure 6. Gate-drain corner of an NMOSFET with finite-element grid ...................... 27 Figure 7. (a) an NMOSFET device structure, (b) Id-Vd curves for simulated NMOSFET device ............................................................................................................ 28 Figure 8. TCAD simulation results fro single-event induced NMOS drain current for different LETs for 90nm [51] ...................................................................................... 30 Figure 9. Induced transient current profiles for 65-nm NMOS at different LETs ....... 31 Figure 10. CMOS cross section, showing parasitic elements [9] ............................... 33 Figure 11. Relative range of charge cloud and potential distortion for the 1-micron and 90 nm technologies [25] ............................................................................. 35 Figure 12. Simulation set up for (a) NFET devices and (b) PFET devices ................ 36 Figure 13. Potential gradients for heavy ion with LET of 20 MeV.cm 2 /mg .............. 38 Figure 14. Active node drains current for (a) NMOS, (b) PMOS, and passive node drains current for (c) NMOS and (d) PMOS devices at different LETs. ................. 40 Figure 15. Passive node drains current and current from DR Double-exponential for NMOS at LET of (a) 40, (b) 20, (c) 10 and (d)5 MeV.cm 2 /gm .................................. 42 Figure 16. Passive node drains current and current from DR Double-exponential for PMOS at LET of (a) 40, (b) 20, (c) 10 and (d)5 MeV.cm 2 /gm ................................... 43 Figure 17. 2-D TCAD simulation time for 2 NFET devices next to each other with minimum spacing in 65-nm technology using 2 processors. .................................... 47 Figure 18. The DICE storage cell [20] ....................................................................... 51 ix Figure 19. One DICE latch is composed of two identical tiles .................................. 53 Figure 20. a) Tile layout, b)Double-DICE latch layout ............................................. 54 Figure 21. Quadrature-DICE latch. Interleaving four different DICE latches ........... 57 Figure 22. Simulation set-up for two adjacnet (a) NMOS and (b) PMOS devices .... 59 Figure 23. 2-D TCAD DTI structure .......................................................................... 60 Figure 24. Schematic cross-sections of (a) NMOS guard-ring, (b) NMOS guard-diode, (c) PMOS guard-ring and (d) PMOS guard-diode ...................................... 61 Figure 25. (a) Induced output voltage and (b) induced current transient at the drain of NMOS active and passive devices ...................................................................... 62 Figure 26. Charge collected at the drain of passive (a) NMOS and (b) PMOS for Minimum nodal separation, 2 times and 4 times more nodal distance, guard-ring, guard-diode and DTI ......................................................................................................... 63 Figure 27. Percentage of charge reduction at the drain of passive (a) PMOS and (b) NMOS for Minimum nodal separation, 2 times and 4 times more nodal distance, guard ring, guard diode and DTI....................................................................................... 65 Figure 28. Area comparison for different TCAS structures, (a) STI with base spacing, (b)DTI, (c) STI with double spacing, (d)STI with four times spacing, (e) guard-ring, and (f)guard-diode .................................................................................... 66 Figure 29. Induced voltage pulses at active device output for LET of 20 MeV.cm 2 /mg ................................................................................................................ 67 Figure 30. Percentage of increase or decrease in the output voltage pulse width at the active device while using different mitigation techniques compared to the minimum distance nodal separation for (a) active PMOS and (b) active NMOS ............ 68 Figure 31. Basic structure of MCML ......................................................................... 70 Figure 32. MCML (a) inverter, (b) NAND, and (c) Latch ......................................... 73 Figure 33. Collection charge between adjacent devices [79] ..................................... 73 Figure 34. 3-D TCAD simulations current pulses for LET<1 MeV.cm 2 /mg [73] ..... 74 Figure 35. Double-exponential current source placement .......................................... 76 Figure 36. Clock, Data and Output (Q) waveforms of a single-event hit flip-flop .... 76 x Figure 37. Critical charge (Qcrit) versus Bias current for different output voltage swings ....................................................................................................... 77 Figure 38. MCML latch layout for Δ Δ Δ ΔV=300 mV and clock rate=0.5 GHz for (a) I b =30 µA and (b)I b =100 µA ........................................................................................ 78 Figure 39. Q crit versus Output Voltage Swing for different Bias currents ................. 79 Figure 40. Proposed SEU-Hard MCML..................................................................... 83 Figure 41. Double exponential current model ............................................................ 84 Figure 42. Clock, Data, MCML output (Q) and SEU-Hard MCML output (Q) waveforms of a single-event hit MCML flip-flop for clock frequency of 2 GHz ............ 85 Figure 43. Dual-interleaved BiCMOS CML D-flip-flop circuit [55] ........................ 87 Figure 44. Gated-Feedback Cell-Based BiCMOS CML D latch [55] ....................... 88 Figure 45. (a) applying constant voltage to the PMOS gates, (b) clock, MCML fllip-flop input and output waveforms for circuit in (a) .................................................... 89 Figure 46. TMR structure ........................................................................................... 92 Figure 47. Temporal latch structure ........................................................................... 93 Figure 48. Narrower pulses (input A) have less probability of being sampled in the window of vulnerability of a flip-flop as compared to a wider pulse (input B) ......... 94 Figure 49. Schematic of proposed design with a weak-latch before the sequential element ............................................................................................................. 95 Figure 50. SET rejection and attenuation by weak-latch, (a) SET pulse is rejected (b) SET pulse narrows down and (c) Data signal is delayed and passes through the weak-latch without any pulse narrowing .......................................................................... 96 Figure 51. (a) Input to weak-latch, (b) output from minimum size inverter (input to Flip-Flop) and (c) Flip-Flop output .................................................................... 97 Figure 52. Input Data with a transient pulse width of 500 ps; Weak latch output, pulse width is reduced to 240 ps, and Flip-Flop outputs (a) using weak-latch (b) no weak-latch .............................................................................................................. 98 Figure 53. Layout of weak-latches in front of a DICE latch. Two weak-latches are added. One for SET filtering from the data and another for filtering SET from clock. ................................................................................................................ 99 xi Figure 54. TCAD NFET Structure ........................................................................... 101 Figure 55. Carbon Nanotube Lattice structure ......................................................... 105 Figure 56. Different single walled carbon nanotube : (a)zigzag, (b) armchair, and (c) chiral [90]............................................................................................................ 106 Figure 57. Different form of carbon nanotubes: (a) Multi-walled, and (b) bundle of nanotubes [33] ........................................................................................... 108 Figure 58. Growth mechanism:(a) root growth, and (b) tip growth [60] ................. 109 Figure 59. Wafer-scale aligned nanotube fabrication. a, b) temperature flowcharts for annealing and nanotube growth on sapphire and quartz wafer. c) schematic diagram and photograph of aligned nanotubes on a 4 in. quartz wafer. Inset shows SEM image of aligned nanotubes. d-h) schematic diagrams and photographs of the transfer procedure of nanotube arrays. i) photo images of nanotube devices and circuits built on a 4 in. Si/SiO 2 wafer: 1) back-gated transistor; 2) top-gated transistor; 3) CMOS inverter; 4) NOR logic gate; 5) NAND logic gate. [89] ............................................................................................... 112 Figure 60. a) Schematic of a back-gated transistor build on transferred nanotubes, b) SEM image of transistor, c) characteristics of transistors for channel length of 0.5, 0.75, 1, 2, 5, and 20 µm and channel width of 100 µm, d) normalized on and off current densities and transconductance (gm) derived from c, e) electrical breakdown study of the transistors, and f) Ids-Vg and Ids-Vds curves of the transistor in (e) after three round of electrical breakdown [89]. ......................................................... 113 Figure 61. Total dose radiation data for two different SWNT devices on one chip: a and b [35]...................................................................................................... 115 Figure 62. 3-D TCAD structure of back-gated SWNT, provided by Silvaco .......... 116 Figure 63. Drain current versus gate voltage from 3 D TCAD simulations for SWNT with tube diameter 20% larger and smaller than the base case for drain voltage of (a) 1, (b) 0.8, (c) 0.6, and (d) 0.4 volts ........................................................... 117 Figure 64. Drain current versus gate voltage for drain voltages of (a) 1, (b) 0.8, (c) 0.6, and (d) 0.4 volts when one out of three tubes diameter is 10% and 20% larger or smaller than the base case ................................................................................ 120 xii ABSTRACT As semiconductor industry continues to scale down to ever smaller feature sizes, radiation-induced soft errors are becoming a major concern for microelectronics reliability. A rising problem of a single particle strike causing upsets in more than one circuit node has become more frequent in deep sub-micron technologies. This is especially a troubling trend since most already existing single-event effect mitigation techniques for older technologies are based on the assumption of corruption of data in a single node. However, in deep sub-micron technologies, charge sharing and collecting among multiple nodes due to a single hit has invalidated the above assumption. Therefore, if sub-micron electronic circuits are targeted to be used in radiation sensitive environments, they have to be hard to charge sharing and collecting in addition to other single-event effects. This magnifies the necessity of charge sharing mitigation methods and prior to that a fast and accurate model to measure the sensitivity of adjacent nodes to charge sharing effects. After assessing the vulnerability of a circuit to charge sharing, appropriate mitigation techniques can be applied to reduce the induced error rate. We have developed a semi-empirical circuit model to predict the charge sharing effect between adjacent nodes. This is a fast and easy-to-use model with good accuracy that can be applied to circuit simulators at early stages of a design. The effectiveness of the proposed model is demonstrated by comparing the model with Technology Computer Aided Design (TCAD) simulation results for 65-nm CMOS technology. PFET devices are more prone to charge sharing than NFET devices due to PNP bipolar amplification; therefore removing them can reduce the charge sharing effect. Thus the use of MOS Current Mode Logic (MCML) circuit topology, which is comprised xiii of all NFET devices, can reduce the charge sharing effect for deep sub-micron technologies in radiation sensitive environments. We study the sensitivity of a MCML sequential element to single-event upsets and propose a Radiation-Hardening-by-Design (RHBD) method to mitigate single-event upsets for MCML sequential elements. We also suggest layout and process techniques to reduce charge sharing effects and compare the effectiveness of existing charge sharing mitigation methods in deep sub-micron CMOS technologies. Another growing radiation-induced problem in the deep sub-micron technologies is an induced single event transient (SET) pulse due to a single strike in combinational logic. Smaller noise margins due to reduced voltage supplies and higher operating frequencies in deep sub-micron technologies have made circuits more sensitive to SET errors. We have proposed a RHBD method to mitigate the SET problem in 65-nm CMOS technology with minimum area and delay penalties. Finally, we also initiated an investigation on the radiation effects on electronics in aligned carbon nanotube technology, one of the most promising post-silicon technologies, by using 3D-TCAD simulations. 1 CHAPTER 1: INTRODUCTION The distinctive success of CMOS technology, and, by consequence, the progress of information technology, can be attributed largely to the scaling of MOS transistors, which has rapidly advanced during more than thirty years to increasing levels of integration and performance. MOSFET transistors have been fabricated smaller, denser, faster and cheaper over time in order to provide ever more powerful products for both digital and analog electronics. However, this aggressive scaling of MOS transistors has increased their sensitivity to radiation effects [11]. Down-scaling of MOSFET transistors decreases the cell nodal capacitances as well as operating voltage margins. This results in a reduction of the critical charge (Q crit ) [26] and corresponding linear energy transfer (LET) [28] required for corrupting a stored bit. The percentage of ionizing particles that can affect a stored/output bit, both directly and indirectly, has considerably increased [10], and consequently the likelihood of bit upsets. Scaling down a transistor reduces nodal separation which in adverse increases multiple bit upsets due to a single ion strike [9] and [79]. Charge sharing among multiple transistors may cause multiple-bit corruption, a result of moving to smaller technology, making redundancy based Radiation-Hardening-by-Design (RHBD) methods, such as Dual Interlocked Cell (DICE Latch), less effective [8]. The frequency of single-bit upsets, and more recently multi-bit upsets, is now a major reliability concern in commercial electronics as reported by Sun Microsystems [96], Texas Instruments [13], Virage Logic Corporation [26], Intel [98], [62], Cypress Semiconductor [85], IBM [67]. The effect of scaling on soft error rate on electronics has also been reported by Actel Corporation [1]. This report shows neutron- 2 induced soft errors got worse by a factor of two as technology scaled from 130 nm to 90 nm, Table 1. The problem is even worse, as this table ignores alpha particle effects, which are also expected to be significant for nanometer technologies and will further increase the system failure rate. TABLE 1. PROJECTED FAILURE RATE ON SRAM-BASED APPLICATIONS DUE TO NEUTRON EFFECTS (ACTEL) Application Examples Altitude (feet) Neutron (relative) #upsets/1M- gate FPGA/day (0.13µ) MTTF (Mean Time to Failure) FIT (Failure in Time) 0.13µ 0.09µ 0.13µ 0.09µ (1) Ground-base Communication Network 5000 1 4.19e-4 112 58 8.92 17.24 (2) Civilian Anionic System 30,000 ~40 1.85e-2 324 162 3.09 6.17 (3) Military Avionic System 60,000 >160 8.33e-2 18 9 55.56 111.11 Radiation induced effects at a single node and the necessity of having radiation hard circuits are now clear. Different circuit models and methods are proposed to predict and mitigate different single-event effects (SEE) in a single struck node. However, the lack of a proper circuit model to quickly predict the multiple-node upsets due to a single strike for sub-micron technologies is still a challenge to be met. We suggest a semi- empirical model that can be used in circuit simulators, like HSPICE, to predict the effect of charge sharing among adjacent devices due to a single ion strike. This model can be employed in circuit simulators in early stages of a design minimizing the need to run long and slow device simulations or costly physical laser tests after fabrication. We also suggest layout techniques for charge sharing and collection reduction among adjacent devices to decrease multiple bit upsets. Then we compared the effectiveness of popular 3 charge sharing reduction techniques in deep sub-micron technologies and suggest a very effective charge isolation method. Recent studies show that multiple bit upsets due to a single ion strike is more severe among positive channel MOSFETs (PMOS) than negative channel MOSFETs (NMOS) due to PNP bipolar amplifications [79]. Naturally, removing PMOS transistors should mitigate such a charge sharing problem. One example of all negative channel MOSFET logic is MOS Current Mode Logic (MCML), which is used in digital and analog circuits of electronic chips such as high-speed cross-point switches for networks (LAN/WAN) [105], RF applications (PLL, pre-scalers, clock recovery circuits) [87], [46] and very high-speed buffer/links [84]. MCML is faster than conventional CMOS due to its smaller voltage swing and draws constant current from current supplies, and thus its power consumption is independent of operating frequency, which makes it an ideal case for low-power high-frequency systems. We investigate the single-event upset sensitivity of MOS Current Mode Logic (MCML) sequential elements, and suggest a Radiation- Hardening-by-Design (RHBD) method to mitigate single-event upsets for MCML latches and flip-flops enabling them to be used in radiation sensitive environments. Single-event transients (SET) are another growing problem that comes along with scaling technology to the deep sub-micron regime [28], [13], and [104]. Smaller noise margins and higher frequencies make sub-micron circuits more susceptible to SET pulses. We suggest an area and delay efficient RHBD method to reduce the sensitivity of combinational logic to SET pulses. CMOS reliability issues are not limited to radiation environments as scaling continues to small nano-meter feature sizes (16 nm gate length). It is anticipated that 4 CMOS scaling will likely become very difficult due to short-channel effects (SCE), high power dissipation and low drive current due to scaling of size as well as reduced mobility and reduced electron count [58], and [95]. Therefore, new materials, most notably carbon-nanotube-based technologies, are being investigated, which have already shown properties competing with the most advanced CMOS processes [63], and [89]. In consideration of these developments, we have started the exploration of responses of carbon nanotube devices to radiation effects. TCAD simulations have been used to study the possible effects of radiation particles on CNT devices. 1.2 History of radiation effects In 1975 the first cosmic ray induced upsets in space electronics were reported by Binder et al [17]. May and Woods reported alpha particle induced soft errors in dynamic memories at ground level in 1979 [66]. In 1979, it was mentioned that secondary particles created by the interaction of cosmic rays with the atmosphere could cause soft errors in ground-based electronics [109]. Over the past 3 decades soft errors have been considered as a great reliability issue, especially for the space electronics community. During the cold war era, the space community received substantial financial support from government funding, and consequently radiation-hardening-by-process (RHBP) was developed to employ special foundries for radiation hardening purposes. These processes were somewhat different from the ones used in commercial foundries and included a few modified process steps that produced circuits with greater radiation resistance. However, since these parts were more expensive than their commercial counterparts, and the RHBP foundries have lagged at least two generations behind in terms of speed, power, and size, these processes started losing importance, especially considering the changing economy 5 and fast scaling of technology in the commercial market. The low-volume market for space and defense electronics no longer justifies the cost of radiation-hardening-by- process. This condition has gradually led to the use of more commercial-off-the-shelf components in space and defense electronics [75]. Technology scaling, on the other hand, has also exacerbated the reliability problem even for terrestrial applications. Single-event upsets in avionics and high-end networking and financial servers pose significant threats for system reliability [68], [78]. Sun Microsystems encountered such an experience firsthand when some of its enterprise servers failed in the field because of soft errors in cache memory which resulted in major customer dissatisfaction [21], and [99]. Investigation of changes in soft error behavior, its mechanism and effects for deep sub- micron technologies and different circuit topologies, along with developing accurate models and techniques to predict and improve overall reliability is a must for today’s commercial and space applications. 1.3 Research contributions Scaling technology to the deep sub-micron regime increases charge sharing and charge collection among multiple nodes due to a single ion strike [79], [7]. Thus the sensitivity of adjacent nodes to charge sharing should be measured at the early stages of a design in order to choose the proper mitigation method. In this research we offer a semi- empirical model to predict the effects of charge sharing among multiple nodes in bulk processes. This model is to be used in circuit simulators to allow the designer to predict the sensitivities of different circuit nodes or hardness to single-event effects at the early stages of the design, without the need to run long, slow and sometimes impractical device simulations or wait until after fabrication to conduct costly physical laser tests. This 6 model can be applied to all kinds of bulk process circuits and topologies including CMOS SRAM, combinational logic and MCML to predict charge sharing effects. Multiple bit upsets due to charge sharing among multiple nodes in a circuit makes currently existing RHBD redundancy based techniques less efficient, if not ineffective. We suggest a layout method to mitigate charge sharing among multiple nodes. We also compare the effectiveness of most popular charge sharing mitigation techniques and their effects on the stuck node in deep sub-micron technologies. Based on the results we suggest the use of Deep Trench isolation between sensitive adjacent devices for better confinement of single-event effects to a struck device over other compared mitigation methods. Recent studies show that charge sharing effects are more severe among PMOS transistors, because an ion strike can perturb an n-well potential enough to turn on lateral bipolar parasitic PNP transistors and amplify the collected charge [79]. Therefore, all NMOS circuit topologies inherently have better charge sharing immunity. MOS Current Mode (MCML) logic is an all-NMOS circuit style that can perform in the GHz range and yields a better power-speed product than CMOS for high-frequency applications. MCML has been used in many different high-speed analog circuits and has also been proposed to be used in low-power, low-noise, and high-speed digital computational circuits [71]. We first investigate Current Mode Logic (MCML) single-event upset (SEU) sensitivity in radiation sensitive environments and then suggest an area- and power-efficient Radiation- Hardening-by-Design (RHBD) technique to mitigate MCML SEU susceptibility. Heavy particles that strike a sensitive node in a circuit can cause two major unwanted effects: SEU and single-event transient (SET). SEU is mostly a problem in 7 sequential and memory elements since it changes stored values. SET is mainly a problem in combinational logic and appears in the form of a transient voltage pulse. If this SET voltage pulse is not sampled by a sequential element, then it is inconsequential. However, as technology has scaled to deep sub-micron regimes supply voltages have reduced, implying smaller noise margins. At the same time, operating frequencies have increased, increasing the probability of a SET pulse being sampled at the sampling edge of Flip- Fops. Thus SET pulses are becoming more of a concern for advanced digital circuit designs [28], [13], and [104]. We suggest a RHBD method to mitigate SET effects in combinational logic for sub-micron technologies while keeping the area and speed overheads low. The research contributions of this work include: • A semi-empirical circuit model to predict charge sharing among adjacent nodes in circuit simulators for MOSFET transistors • Reduction of charge sharing effects in RHBD DICE latches/flip-flops by interleaving sensitive pairs • A study of the effectiveness of charge sharing mitigation methods for deep sub- micron technologies and demonstration of better isolation of devices by using Deep Trench Isolation • A study of MCML sensitivity to SEU and design parameter effects on SEU mitigation • A radiation-hardening-by-design technique for soft error mitigation in MCML latches and flip-flops 8 • A radiation-hardening-by-design technique for single-event transient mitigation in sub-micron combinational circuits • An exploration of possible responses of self-aligned carbon nanotubes to radiation effects 1.3.1 A semi-empirical circuit model to predict charge sharing among adjacent nodes in circuit simulators for MOSFET transistors As mentioned earlier, charge sharing mitigation techniques are needed for deep sub-micron technologies to enable their use in radiation sensitive environments. Various remedies have previously been proposed to reduce charge sharing in adjacent nodes. However, to choose a charge sharing mitigation method that best suits a specific design, the sensitivity of adjacent nodes to charge sharing should be evaluated at the early steps of a design. A single-node response (hit device) to single-event effects can be observed in both circuit and device simulators by applying existing circuit models [73], [64], [51] and [27]. However, these circuit models are confined to a single struck transistor and do not predict the charge sharing effects on any devices in proximity. Using device simulator tools, such as Synopsys TCAD, the charge sharing and collecting effects can be simulated, but these simulations are extremely slow, especially when more than one device is to be simulated. We suggest a semi-empirical circuit model to be applied to circuit simulators such as HSPICE to study the sensitivity of adjacent nodes to charge sharing in early stages of a design process without the need to run many long and meticulous device simulations for different layout configurations and different LETs. 9 1.3.2 Reduction of charge sharing effects in RHBD DICE latches/flip-flops by interleaving sensitive nodes The Dual Interlocked Cell (DICE) [20] is a well-known storage cell design that uses redundancy to overcome susceptibility to SEU. If a radiation particle strikes a sensitive node (drain of a NMOS or of a PMOS in off mode), and it loses its charge, the redundant nodes restore the state of the affected node and prevent an upset in the storage cell logic. The DICE design provides excellent protection against SEU for sub-micron technologies, where a single radiation strike results in charge collection at only one node. As technologies scale down to the deep sub-micron regime, nodal charge and device spacing are reduced as a consequence of feature size reduction. These characteristics can result in charge collecting and charge sharing across multiple nodes [101], [14], and [79]. Recent studies have shown that bipolar amplification between PMOS devices due to the n-well potential collapse and charge diffusion between NMOS devices in the case of a single strike are the main charge sharing mechanisms [7]. It has been shown that for 90 nm technology charge sharing can be an issue for devices as far as 5 µm from a strike location [9]. Therefore, any hardened design with sensitive nodes located within this distance is susceptible to charge sharing, and as a result the redundant nodes themselves can also be upset. This phenomenon causes the DICE design to lose its effectiveness of SEU tolerance for deep sub-micron technologies. As intuition would also support, it has been experimentally shown that nodal separation between sensitive pairs in a DICE element improves the tolerance to SEU [6]. We proposed Double-DICE [41] storage elements by using a layout technique to reduce susceptibility to upsets for DICE elements in 90 nm technology. The technique involves the interleaving of two DICE cells at a 10 layout level to meet the required spacing between sensitive nodes in an area-efficient manner and without the requirement for any change in the logical DICE design or different fabrication processes. This cell can be easily integrated into a 90 nm standard cell library and used in a regular ASIC design flow using synthesis and place&route tools. 1.3.3 Study the effectiveness of charge sharing methods for deep sub-micron technologies and demonstrate better isolation of devices by using deep trench isolation An ion strike creates extra charges through ionization of the substrate on the path it traverses. These extra charges move from the strike location to adjacent devices, by a drift mechanism, and show up at the drain of adjacent nodes before recombining with each other or being removed by substrate contacts. If these charges are confined to the strike location and can not move easily to adjacent nodes, then multiple node upsets can be prevented. Shallow Trench Isolation (STI) is generally used on CMOS process technology nodes of 250 nm and smaller and is sufficient for preventing current leakage between adjacent semiconductor device components [83]. However, STI can not prevent current flows due to ion strikes since the ions go much deeper into the substrate and create current flows underneath the STI that reaches nearby transistors, especially in deep sub-micron technology where the distance between adjacent devices is often less than 200 nm. Deep Trench Isolation (DTI) has been used widely as a process solution for latch-up and noise reduction in CMOS, RF CMOS, and BiCMOS Silicon Germanium [102], [16], and [88]. We investigate the effectiveness of DTI to limit the charge created by the ion strike to the struck node. We also compare DTI with other layout and process 11 charge sharing mitigation techniques and show how DTI can block the charge sharing effect to the struck device by conducting device simulations [39]. 1.3.4 Study of MCML sensitivity to SEU and design parameter effects on SEU mitigation Conventional CMOS circuitry is popular because of its small area, low static power dissipation, high noise margin and availability in standard library cells [59]. However in high-frequency systems, CMOS becomes less efficient, due to high dynamic power dissipation and the coupling of high switching noise to power supplies [23]. Additionally, in mixed-signal environments, CMOS causes crosstalk between analog and digital circuitry [4]. The CMOS maximum operating frequency is limited. An alternative to CMOS in these scenarios is MOS Current Mode Logic (MCML). MCML is a popular logic style in high-speed systems, especially when analog and digital circuitries are integrated onto the same die [91]. MCML has been used in multi-GHz communication systems such as high-speed cross-point switches for networks (LAN/WAN) [105], RF applications (PLL, pre-scalers, clock recovery circuits) [87], [46] and very high-speed buffer/links [84]. It has also been used in high-speed digital computational circuits [71]. MCML is all-NMOS logic, which is a plus for radiation environments since PMOS transistors show more sensitivity to single-event effects [79]. Since MCML shares the same fabrication process as CMOS, similar radiation hardening techniques applied to CMOS can be exploited for MCML without the necessity of moving to more costly fabrication methods. First we studied the sensitivity of MCML latches and flip-flops to SEU and compared to that of CMOS latches/flip-flops. We also investigated the effects of different design parameters such as transistor size, voltage swing and bias current on 12 the SEU tolerance of MCML at different operating frequencies. The results and observations can be used as guidelines for design of radiation hardened MCML sequential elements [40]. 1.3.5 Radiation-hardening-by-design technique for soft error mitigation in MCML latches and flip-flops As mentioned earlier, MCML is a viable candidate for modern communication systems operating at high frequencies. Considering the increased use of MCML in both digital and analog circuit applications, it is important to develop techniques for making it immune to radiation effects to enable its use in a broader variety of environments. Additionally as device feature sizes decrease, and as a result node capacitance likewise, SEU becomes more of an issue not just in space applications but also in terrestrial environments. Such causes are cosmic rays, charged particles originating from the radioactive decay of impurities within packaging or a chip itself, interaction of low energy and thermal neutrons with the Boron present in semiconductors as a dopant, or high-energy neutrons occurring indirectly through elastic scattering and nuclear reaction within the silicon [65]. We proposed a new radiation-hardening-by-design MCML sequential element [38], which achieves significant SEU immunity while it has modest area, speed and power penalties. Our proposed design uses controllable resistance in the feedback loop to make the circuit more SEU-tolerant with minimum redundancy. 13 1.3.6 Radiation-hardening-by-design technique for single-event transient mitigation in sub-micron combinational circuits As technology scales, there is a trend of Vdd decreasing while local clock frequencies are increasing. These are the two main factors that make electronic circuits more sensitive to SET pulses when moving to smaller technologies. Both SET pulse width and amplitude are important factors that affect the Soft Error Rate (SER). Only transient pulses with amplitudes larger than the noise margin can propagate; thus decreasing the noise margin increases the number of propagating SET pulses. Broader pulse widths have a higher probability of being sampled at the windows of vulnerability, the period between set up and hold times, of sequential elements. SET pulses that are sampled at sequential elements cause errors. We propose to use a pair of cross-coupled inverters at the data input of sequential elements to mitigate the SET problem. This acts as a weak-latch and slows down the circuit. As a result, SET pulse widths smaller than the added delay will be filtered out and SET pulse widths close to this delay value will be decreased, improving the SET immunity [42]. 1.3.7 Exploration of possible responses of self-aligned carbon nanotubes to radiation effects CMOS scaling to deep sub-micron feature sizes is increasingly challenging the reliable operation of commercial-process-based electronics in space and strategic radiation environments. Carbon-nanotube-based technologies exhibit performance rivaling the most advanced CMOS processes. Therefore, it is essential to establish an understanding of the basic mechanisms and phenomena from ionizing radiation effects on field-effect transistors and circuits, based on self-aligned carbon nanotube technology. 14 We conducted a set of 3-D device simulations to study the possible response of CNT devices under radiation environments. Our primary investigation and study suggests CNT devices as radiation resilient devices very much suitable for radiation sensitive environments. 1.4 Organization of the dissertation We begin with a short description of radiation effects on microelectronics and introduce some of the common terminology used throughout this dissertation in chapter 2. In chapter 3, we discuss the technology scaling and charge sharing problem that shows up dominantly in deep sub-micron technologies and its associated mechanisms in NFETs and PFETs. We propose and evaluate our semi-empirical charge sharing model for circuit simulators in the same section. In chapter 4, we discuss how charge sharing makes currently existing radiation-hardening-by-design methods less effective and introduce our layout methodology for reducing the problem for these technologies. In this section we also compare some of the radiation-hardening-by-process methods and layout techniques to reduce charge sharing among adjacent nodes in CMOS technologies and show how Deep Trench Isolation can isolate charge sharing effects. Recent studies show the severity of charge sharing among PFET devices; therefore we suggest the use of an all- NMOS circuit style to reduce this severity. In chapter 5, the MOS Current Mode Logic (MCML) structure and its applications, as an all-NMOS approach, is briefly introduced. We then present our study on radiation sensitivity of MCML and a radiation-hardening- by-design technique to mitigate single-event upset errors. Chapter 6 addresses the single- event transient problem in deep sub-micron technologies. This leads to our proposed 15 RHBD method for reducing SET errors in combinational logic. Chapter 7 focuses on Carbon Nanotube Technology and the study of radiation effects on CNT devices. 16 CHAPTER 2: RADIATION EFFECTS ON MICROELECTRONICS The radiation environment in space can significantly degrade the performance and functionality of space-borne electronic devices. These effects are not limited to just space environments; even in terrestrial environments, alpha particles, emitted from a small number of impurities in packaging material, may result in soft errors (also known as single-event upsets) [12]. High-energy neutrons can cause various effects in electronics through indirect ionization. All these sources cause errors in computing systems at higher altitudes and malfunctioning of controllers in aircraft. This section analyzes various radiation sources and their effects on electronic circuits. 2.1 Radiation sources and environments Figure 1. Radiation Environments [72] 17 2.1.1 Galactic cosmic rays Galactic cosmic ray (GCR) particles, shown in figure 1 [72], originate outside the solar system. They mostly consist of high-energy protons and heavy ions, and are the major source of radiation particles in space. Cosmic rays are 90% high-energy protons, 9% alpha particles, and the remaining consists of other heavy ions (Z > 1) and electrons. GCR particle flux levels are low. This is the case when GCR is the maximum contributor for the space radiation flux versus the energies of these GRC ions are very high and on the order of 100’s to 1000’s of MeV/amu (atomic mass unit) [61]. Therefore they have a very long range of penetration, and produce intense ionization as they pass through the targeted material. Low-energy particles can be attenuated by shielding, but no practical amount of shielding can stop high-energy particles. Earth’s magnetic field and atmosphere shield against most of the GCRs. 2.1.2 Solar cosmic rays Solar cosmic rays are produced by the sun as shown in figure 1. They include protons and heavy ions similar to GCRs but with lower energies. Solar flares and other explosions on the sun are the sources of these types of cosmic rays. Due to the low energy of its particles, solar cosmic rays can be attenuated by shielding. 2.1.3 V an Allen belts (trapped particles) As mentioned earlier earth’s magnetic field shields against both galactic and solar cosmic rays. This magnetic field traps charged particles and creates a high populated belt known as Van Allen Belts, shown in figure 1. This belt is not uniformly distributed 18 around the earth and has the most thickness above the equator. The population is mostly high-energy protons in the range of 10-100 MeV. 2.1.4 Atmospheric showers The collision of galactic cosmic rays with air molecules, when entering the earth’s atmosphere, produces lighter particles of mainly oxygen and nitrogen. This phenomenon is called an air shower. Even though the main products of these interactions are high- energy protons and neutrons, other particles such as pions, muons, and gamma rays are also generated as shown in figure 2 [107]. Secondary cosmic rays or terrestrial cosmic rays are other names for these particles. The particle fluxes vary with the geometry and altitude [108]. The minimum flux of these cosmic rays is at sea level, and it increases with increasing altitude. Neutrons are the main source of single event effects in terrestrial and aircraft applications. 2.1.5 Impurities in manufacturing materials Alpha particles emitted from solder balls and certain impurities in manufacturing materials of integrated circuits (IC) are another source of radiation particles. The alpha particle consists of two neutrons and two protons, i.e., a double charge helium ion ( 4 He 2 ). These alpha particles have energies in the range of 4.1 to 7.7 MeV, while in silicon 1 MeV of energy can generate 44.5 fC of charge, which is more than adequate to flip the state of a logic node [12], [50]. Secondary radiation particles, created from the interaction of neutrons from terrestrial cosmic rays with boron atoms, can affect electronics. Boron is found in insulating glass used in the fabrication of semiconductor electronics, (BPSG - Borophosphosilicate glass) [75]. 19 Figure 2. Secondary particles generated by the interaction of cosmic rays with atmospheric atoms [107] 2.2 Radiation effects Two types of radiation effects are of particular concern for electronic designers. The first, known as the total ionizing dose (TID), represents the cumulative effect of many particles hitting a device during the course of its life. TID gradually degrades the device until it finally fails. The second involves an energetic charged particle that penetrates deep into materials and components, immediately leaving a temporary trail of free charges. This is known as single-event effects (SEE). This section provides definitions and acronyms for some of the basic radiation effects. Figure 3 [72], shows an ion strike passing through the drain of a transistor. 20 Figure 3. Ion Strike on drain of an off-NMOS Transistor [72] Linear energy transfer (LET) is an important term in the radiation hardening community and will be used throughout this proposal. Therefore we describe this term before providing definitions for radiation effects. 2.2.1 Linear energy transfer LET is used to express the characteristic of a particle’s path through materials. It is defined as the energy being transferred to material by an ionizing particle as a function of distance and material density. LET units are energy lost per unit track length per unit mass density. Therefore LET is usually expressed in MeV-cm 2 /mg [(MeV/cm)/(mg/cm 3 )]. LET is also defined as the amount of charge an ion deposits/creates per unit length of targeted material. The units for the latter definition are pC/um. To convert LET units from MeV-cm 2 /mg to equivalent charge deposited per unit length (pC/um): Energy needed to create one electron-hole pair in silicon: 3.6 eV Electron charge: 1.6*10 -19 C Silicon density: 2.33g/cm 3 21 Charge generated by 1 MeV: 1.6 * 10 -13 C/3.6 Charge generated per unit cm by 1 MeV: 0.444 * 10 -13 C/cm Charge generated through unit density of silicon (1MeV/cm)/(mg/cm 3 ) by 1 MeV/cm: 0.444 * 10 -13 * 2.33 * 10 3 C/cm Charge generated by LET of 1 MeV-cm2/mg: 1.036 * 10 -10 C/cm = 1.036 * 10 -14 C/um = 0.01036 pC/um Charge generated in silicon in a length “L” in microns by an LET (MeV-cm 2 /mg) of ion can be expressed as: dQ (pC) = 0.01036 * L (micron) * LET (MeV-cm 2 /mg) (1) 2.2.2 Critical charge (Q crit ) Critical Charge (Q crit ) is generally defined as the minimum amount of charge that must be collected by a circuit node, following the strike of an energetic particle at a sensitive node, in order to change the logic state of the circuit node [29]. 2.2.3 Total ionizing dose (TID) When an energized particle strikes the dielectric part of a semiconductor device, like oxide, it ionizes the dielectric layers, and leaves a small electrical charge behind, shown in figure 4 [72]. These charges often migrate off of these dielectric layers due to electrical fields existing in gate or active areas of semiconductors, or some recombine with each other shortly after, but over time they eventually build up on the device. Once the part has accumulated enough excess charge, the device will function improperly or at some point will even stop to function. 22 Figure 4. Total ionization dose [72] Total ionizing dose is the amount of radiation or energy that a semiconductor has absorbed over its lifetime. Electronics are often rated at a specific TID level, indicating how much radiation exposure can be tolerated; exposure beyond this point can cause a device to fail. TID is measured in units of rads (rd). One rad is equal to a dose of 0.01 joules of energy per kilogram of mass (J/kg), and it is a function of the material. Electronic devices encounter a typical flux of less than one krad(Si)/yr (equatorial LEO with reasonable shielding or interplanetary at solar minimum), to 5 krad(Si)/yr (LEO with minimal shielding or interplanetary at solar maximum), and 20 krad(Si)/yr (GEO) in space environments [75]. The main mechanism for TID is the trapped charge in the insulating layers, both in gate and field oxides (SiO 2 ). These trapped charges change the transistor thresholds and result in increased leakage currents, both in individual transistors and in the bulk semiconductor covered by field oxide. An increase in TID causes device threshold shifts, increased device leakage and power consumption, and changes in performance parameters. 23 For spacecraft electronics that have long-term radiation exposure, TID plays a significant role in determining space system reliability. Therefore TID needs to be evaluated in order to assess risks for space objects [22]. 2.2.4 Single-event effects (SEE) Any immediate measurable or observable change of state or performance in a microelectronic device, resulting from a single energetic particle strike is called a single- event effect. 2.2.5 Single-event upset (SEU) An unwanted change of state in a memory cell or sequential element, due to a single energetic particle hit, is called a single-event upset. This state change is a result of free charge creation by an energetic particle in or close to a sensitive node. SEU is also called a soft error since it does not permanently destroy the device or its functionality. 2.2.6 Single-event transient (SET) A single-event transient is a voltage transient (glitch) that is induced by a single energetic particle hit in a combinational logic circuit. If this voltage transient can propagate long enough in the circuit to be captured in a sequential or memory element, it will cause an error. 2.2.7 Single-event latch- up (SEL) A single-event latch-up occurs when a spurious current, induced by a single energetic particle, activates parasitic transistors in the silicon substrate creating a circuit with large positive feedback. The device may be destroyed if the current is not limited or removed in time. If the induced device current stays below the maximum specified for 24 the device, a "micro-latch", a subset of SEL, can happen. To recover device operation in these non-catastrophic SEL conditions, the power should be removed from the device. 2.2.8 Single-event functional interrupt (SEFI) A single-event functional interrupt is an anomaly in microcircuits caused by a single energetic particle hit that leads to a temporary non-functionality or interruption of normal operation of the affected device. In some cases SEFI may last as long as the power is maintained, while in others it may last for a limited, but rather long period of time [32]. 2.2.9 Single hard error (SHE) If a single-event upset causes a permanent change to the device operation, it is called a single hard error. A permanent struck bit in a memory is an example of SHE. 2.2.10 Single-event gate rupture (SEGR) A single-event gate rupture occurs when a single energetic particle strike results in a breakdown and subsequent conducting path through the gate oxide of a MOSFET. SEGR causes an increase in gate leakage current and can result in either the degradation or the complete failure of the device. 2.2.11 Single-event burnout (SEB) Single-event burnout is a destructive condition which causes localized burnout due to a high current state, especially prevalent in power transistors. 25 2.2.12 Multiple-bit upset (MBU) A multiple-bit upset happens when a single energetic particle changes the state of more than one memory element or combinational logic node. 2.3 Radiation hardening 2.3.1 Radiation hardening by process To improve the radiation tolerance of electronic devices in radiation environments and mostly in space applications, specialized processes are employed at the manufacturing level. This method of obtaining system reliability is known as Radiation Hardening by Process (RHBP). Silicon-on-sapphire (SOS) is an example of silicon-on- insulator (SOI) hardening by process technique. In SOI, transistors are fabricated on a thin layer of silicon dioxide (SiO 2 ), figure 5 [53]. Figure 5. Silicon on Insulator structure [53] This insulator layer reduces the charge collection from the substrate, which is very thin as compared to normal bulk-CMOS processes. Similarly stress-free ion implantation helps in reducing these effects [45]. Other processing techniques such as extra doping layers [37], usage of triple-well [19], even quadruple-well [43] have been proposed to reduce single-event upset sensitivity. These processes are more costly and 26 have poor performance in comparison with their commercial counterparts. Therefore interest in RHBP is decreasing. 2.3.2 Radiation hardening by design In radiation hardening by design (RHBD), different circuit architecture, design and layout techniques are used to mitigate radiation effects while using commercial processes and foundries. RHBD methods have the benefits of lower cost and better performance over RHBP. Edgeless transistors and guard-bands [2], [97] are examples of special layout structures to improve TID tolerance and to minimize charge sharing and inter-device leakage currents among adjacent nodes. Adding spatial and temporal redundancies are other RHBD methods employed to reduce SEU and SET effects [44], [15], [94], [20], and [65]. On the other hand RHBD trades off circuit performance such as area, speed, and power for better system reliability. Decreasing gate oxide and field oxide thicknesses, as a result of technology scaling, have improved TID tolerance since lower amounts of charge can be trapped in these oxide layers. Lower supply voltages have resulted in minimizing the latch-up effects. Therefore, radiation-hardening-by-design techniques are now more focused to improve circuit response against SET, SEU, and MBU, which are the main radiation reliability issues in deep-sub micron technologies. 2.4 Technology CAD tools In Technology CAD (TCAD) tools, computer simulations are used to develop and optimize semiconductor processing technologies and devices. In TCAD simulation experiments, fundamental, physical partial differential equations that represent the silicon wafer or the layer system in a semiconductor device, such as diffusion and transport 27 equations for discretized geometries, are solved. This deep physical approach gives TCAD simulations predictive accuracy. Thus, TCAD tools make it possible to substitute TCAD computer simulations for costly and time-consuming test wafer runs when developing and characterizing a new semiconductor or technology. Semiconductor industry relies more and more on TCAD simulations since by increasing the complexity of semiconductor technology, TCAD simulations cut costs and speed up the research and development process. Also, TCAD tools are used by semiconductor manufacturers for yield analysis, that is, monitoring, analyzing, and optimizing their IC process flows, as well as analyzing the impact of IC process variation. TCAD has two main simulation parts: process simulation and device simulation. 2.4.1 TCAD process simulation In process simulation, processing steps such as etching, deposition, ion implantation, thermal annealing, and oxidation are simulated based on physical equations, which run the respective processing steps. The simulated part of a silicon wafer is modeled as a computational mesh and represented as a finite-element structure, Figure 5 [92]. Figure 6. Gate-drain corner of an NMOSFET with finite-element grid 28 2.4.2 Device simulation Device simulations can be considered as virtual measurements of the electrical behavior of a semiconductor device, such as a transistor or diode. A meshed finite- element structure represents the device. Each node of the device has properties associate with it, such as material type and doping concentration. The carrier concentration, current densities, electric field, generation and recombination rates, etc., are computed for each node. (a) (b) Figure 7. (a) an NMOSFET device structure, (b) Id-Vd curves for simulated NMOSFET device Boundary conditions, such as applied voltages, are imposed on areas which represent electrodes. The Poisson equation, carrier continuity equation and possibly other equations are solved by device simulator. The resulting electrical currents at the contacts are extracted after solving these equations by device simulator, figure 6 [92]. 29 CHAPTER 3: CHARGE SHARING AND COLLECTION IN DEEP SUB-MICRON TECHNOLOGIES As technologies scale down to the deep sub-micron regime, nodal charge and device spacing are reduced as a consequence of feature size reduction. At the same time the amount of charge required to represent a high logic state at a node has been reduced. This means smaller noise margin and more susceptibility to single-event effects (SEE) not only at the struck device but also at the devices in proximity. Smaller nodal separation results in charge sharing and collection at multiple nodes due to a single ion strike. This implies that when an ion strikes a MOSFET device, it can change the state of devices in a nearby vicinity as well as the struck node. This phenomenon has been detected and observed in sub 100-nm technologies [57]. Because of this growing problem, some existing RHBD methods based on redundancy such as Triple Modular Redundancy [81], Temporal Latch [20], and Dual Interlocked Cell (DICE) [101], are losing their effectiveness in deep sub-micron technologies. It has also been demonstrated that charge sharing causes a LET threshold decrease and two-orders of magnitude increase in the heavy-ion data cross-section of a hardened DICE [7]. A single-node response to single-event effects such as SEU and SET has been long studied, and accurate circuit and device models have been proposed to observe these effects in both circuit and device simulators. Various circuit models have been proposed to simulate a circuit response to a single ion strike. For example, the independent double- 30 exponential current source for particles with LETs smaller than 1 MeV.cm 2 /mg shows the best accuracy [73]. For particles with LETs larger than 1 MeV.cm 2 /mg, this double- exponential current source does not provide an accurate current profile. In figure 8 the NMOS drain currents for different LETs are compared from TCAD Mixed-Mode simulations for 90-nm technology [51]. Figure 8. TCAD simulation results fro single-event induced NMOS drain current for different LETs for 90nm [51] Figure 9 shows the induced current pulses from Synopsys TCAD Mixed-Mode simulations for 65-nm NMOS technology. As seen in both figure 8 and 9, a plateau is created in the current profile for particles with LETs larger than 1 MeV.cm 2 /mg. Therefore, an independent double-exponential current source can not accurately model the induced current at the struck node. 31 -300 -250 -200 -150 -100 -50 0 1492 1592 1689 1789 1884 1979 2077 2177 2276 2376 2476 Time (ps) Current (uA) LET0.5 LET5 LET10 LET20 Figure 9. Induced transient current profiles for 65-nm NMOS at different LETs Some prior research has suggested new models to be used in circuit simulators for modeling the single-event effects of particles with LET >1 MeV.cm 2 /mg [64], and [51]. However, these models are confined to a single struck transistor and do not predict the charge sharing effects on devices in proximity. Accurate circuit models that can simulate the effect of charge sharing among multiple nodes have not been developed yet, even though the significance of this model to predict charge sharing has been recognized and an empirical model has been proposed [34]. In the proposed empirical model, generic transistor device groups were created by extracting layout information, with each group being composed of 2 to 3 devices. Then for each group, multiple TCAD simulations were executed for different LETs. For each simulation, charge associated with each device was captured in a table according to group size, device spacing and strike LET. Then in a circuit simulator, current sources can be added to adjacent nodes while charges injected to circuit nodes are selected from the created look-up table. For using this method, all 32 possible layout configurations must be extracted, and specific software is needed to work with the resultant look-up tables. In addition, for each layout configuration group, all the TCAD simulations should be repeated for different LETs. Therefore, using device simulator tools, like Synopsys TCAD, charge sharing and collecting effects can be simulated; however, these tools are extremely slow, especially when more than one device is to be simulated. In this piece of work we develop a semi-empirical circuit model for charge sharing that can be used in circuit simulators to test the effect of charge sharing on all nodes in the vicinity of the struck node. Circuit simulators are fast, and there is support for a much greater number of devices being simulated, as compared to TCAD. Therefore, if a proper charge sharing model be applied to these tools, the charge sharing and collection effects on devices in the proximity of a struck device can be observed in a fast and easy way in the early stages of a design. The first step in developing this model is the understanding of the behavior of the struck and adjacent devices after an ion strike in deep sub-micron technologies. We used the Synopsys TCAD device simulator to observe this behavior by first developing NFET and PFET devices that match electronic characteristics (I ds vs. V gs and I ds vs. V ds curves) of IBM 65-nm PDK (Process Design Kit) by using TCAD Structure Editor and then simulated these devices using the sdevice simulator while the rest of the circuit in our simulations are from commercial compact models. 3.1 Charge sharing mechanisms When an energetic particle strikes a circuit node, many basic mechanisms affect charge transport and charge collection. The total charge collected at a struck node is the sum of drift, diffusion, and bipolar amplification components. It has been shown that for 33 CMOS technologies, the behavior of parasitic bipolar structures affects the collected charge [36], and [103]. As technology scales and gate length shrinks, the bipolar current gain increases [30]. The lateral bipolar transistors are formed by the drain, channel, and source regions of the MOSFET devices, shown in figure 10 [9]. The drain acts as the collector, the well as the base, and the source as the emitter for the parasitic bipolar transistor. Figure 10. CMOS cross section, showing parasitic elements [9] The charge deposited directly as the result of interaction of an energetic particle with silicon is subject to charge sharing with other nodes in proximity. However, the charge collected due to the parasitic bipolar action is associated with a single transistor and is not shared with neighbor transistors. If the well voltage perturbations on the adjacent devices are sufficient to turn on the parasitic bipolar transistors associated with those devices, then charges that reach those nodes can get amplified. Experiments for sub-micron technologies with 3-D TCAD mixed-mode simulations show that a parasitic bipolar transistor significantly increases the total charge collected by the adjacent (non-hit) node for PMOS devices, while the main mechanism for charge sharing in both NMOS and PMOS devices is diffusion of charges from the 34 struck node to neighboring nodes [9]. The diffusion current density equation is shown below: diff dn J eD dx = , where e is electron charge, D is a diffusion coefficient for electron or hole and has the units of cm 2 /s, n is charge concentration, and x is the distance [76]. Therefore moving to smaller technologies, x becomes smaller and the charge sharing current in adjacent devices increases. However, reduced nodal distance alone is not the reason that charge sharing is becoming worse in deep sub-micron technologies. There are other side effects that magnify the charge sharing at the nearby nodes, as discussed below. When a heavy ion strikes a device in a silicon CMOS technology where the minimum feature size is on the order of a micrometer, the generated charge cloud is mainly limited to the struck device. These changes to the carrier concentrations result in a distortion of the potential distribution, which is still confined to the struck junction. However, this is not true for deep sub-micron technologies; a single-event strike may produce a charge cloud over a region that encloses the entire hit device, nearby well contacts, and possibly nearby devices, see figure 11 [25]. 35 Figure 11. Relative range of charge cloud and potential distortion for the 1-micron and 90 nm technologies [25] In order to quantify the effect of a strike on the incident node, well contact, and adjacent device junctions, we conducted a set of mixed-mode TCAD simulations. Our simulation set-up is shown in figure 12. Our MOSFET (NMOS and PMOS) devices are calibrated to match the electrical characteristics (Id-Vd and Id-Vg curves) obtained from the IBM 65-nm Process Design Kit (PDK). Our MOSFET devices were developed with Synopsys Structure Editor and simulated with the sdevice simulator. The MOSFET sizing is W/L=150nm/60nm (minimum unit size). The rest of the circuit is modeled using commercial 65-nm compact models. All the ion strikes modeled in these experiments were normal to the surface of devices. 36 gnd Active Device gnd Passive Device Input 2 Input 1 Out2 Out1 Ion strike vdd vdd Drain Drain Source Source Well Contact Well Contact P Substrate gnd Active Device gnd Passive Device Input 2 Input 1 Out2 Out1 Ion strike vdd vdd Drain Drain Source Source Well Contact Well Contact P Substrate (a) vdd Input 2 Input 1 Out2 Out1 Ion strike gnd gnd vdd Active Device Passive Device Drain Drain Source Source Well Contact Well Contact N Well Well Contact gnd P Substrate vdd Input 2 Input 1 Out2 Out1 Ion strike gnd gnd vdd Active Device Passive Device Drain Drain Source Source Well Contact Well Contact N Well Well Contact gnd P Substrate (b) Figure 12. Simulation set up for (a) NFET devices and (b) PFET devices Figure 13 shows the changes in a struck node, well contact, and adjacent device junctions and depletion regions with an ion strike with LET of 20 MeV.cm 2 /mg from the time of the strike until 600 ps after the strike, at which point any lingering effect has mostly subsided. Conventionally, a device that is struck directly by a heavy ion is named the active device, and other devices in proximity are labeled passive devices. We follow that same terminology convention in this investigation. As seen in figure 13, the depletion regions in both active and passive devices are reduced by the extra induced charges. The electric field, produced by the depletion regions, creates a force on electrons and holes so that they experience a net acceleration and net movement. This movement of charge due to an electric field is called drift. ( ) drf n p J e n p E μ μ = + , where µ n and µ p are electron and hole mobilities, n and p are electron and hole charge concentrations, e is the magnitude of the electron charge and E is the electric field induced by junctions [76]. 37 Therefore, extra charge movements accelerate under these electric fields and recombine or are absorbed by the junctions faster, mitigating the single-event effects. But in the case that the electric field near passive devices reduces, more time is given to extra holes and electrons to linger in the substrate and change the substrate potential, exacerbating the SEE susceptibility in both active and passive devices. The P-well contact potential does not change since it is pinned to ground; however, in the region below the well contact, the potential is different due to extra deposited charge. These extra charges around the well contact increase the resistance of the substrate contact. The poor substrate contact can not recover the substrate potential and remove extra charges fast enough to recover the depletion regions. Due to reduction or removal of the depletion region at the drain of a passive node, the charge stored at its output capacitance decays to the substrate and changes its output voltage (forward biased drain junction). This is very similar to what happens at the active device drain. Therefore, it can be concluded that the main mechanisms of charge flow in the drain of passive nodes are also drift and diffusion of charges from the drain of passive nodes to the substrate but with slower rates. For PMOS devices if the decrease in the p substrate potential is large enough to turn on the lateral bipolar transistors (P-N-P), then induced charges will be amplified and more severe SEE are observed on the active, and consequently also the passive, devices. 38 Figure 13. Potential gradients for heavy ion with LET of 20 MeV.cm 2 /mg 39 We monitored the behavior of both passive and active nodes by measuring their drain currents for particles with LETs of 5, 10, 20 and 40 MeV.cm 2 /mg when there is minimum nodal spacing between devices by conducting TCAD simulations. Looking into the current profiles at the passive node, Figure 14 (c) and (d) , we can observe a double exponential behavior for LETs of 5 and 10 MeV.cm 2 /mg since the main mechanism is the drift and diffusion of charges from the drain to the substrate. For particles with larger LETs, the same mechanism happens; the only difference is the manifestation of a plateau in the current profile of the passive node very similar to the plateau in the active drain current profile. This plateau happens when a particle has LET large enough to completely remove the depletion region from the passive drain junction, shorting it to the substrate. Thus, constant current is drawn from the recovering network (pull-up in NMOS and pull-down in PMOS). For a LET of 40 MeV.cm 2 /mg, the plateau is clearly seen at the passive drain current profile, figure 14 (c) for NMOS and 14 (d) for PMOS. The duration of this plateau is dependent on the duration of the associated current plateau at the active node, figure 14 (a) and (b). The longer the active drain current plateau lasts, the longer the forwarded biased drain junction will last at the passive device. 40 0 50 100 150 200 0.09 0.24 0.39 0.55 0.70 0.85 1.00 1.16 1.31 Time (ns) Current (uA) LET5 LET10 LET20 LET40 LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg NMOS Active Drains Current (a) 0 50 100 150 200 250 300 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg 0 50 100 150 200 250 300 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) LET5 LET10 LET20 LET40 LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg PMOS Active Drains Current 0 50 100 150 200 250 300 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg 0 50 100 150 200 250 300 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) LET5 LET10 LET20 LET40 LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg PMOS Active Drains Current (b) 0 5 10 15 20 25 30 35 40 0.09 0.24 0.39 0.55 0.70 0.85 1.00 1.16 1.31 1.46 1.62 1.77 Time (ns) Current(uA) LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg NMOS Passive Drains Current 0 5 10 15 20 25 30 35 40 0.09 0.24 0.39 0.55 0.70 0.85 1.00 1.16 1.31 1.46 1.62 1.77 Time (ns) Current(uA) LET5 LET10 LET20 LET40 LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg NMOS Passive Drains Current (c) 0 10 20 30 40 50 60 70 0.45 0.58 0.71 0.83 0.96 1.09 1.22 1.35 1.48 1.61 1.73 Time (ns) Current (uA) LET 5 LET10 LET 20 LET 40 PMOS Passive Drains Current LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg 0 10 20 30 40 50 60 70 0.45 0.58 0.71 0.83 0.96 1.09 1.22 1.35 1.48 1.61 1.73 Time (ns) Current (uA) LET 5 LET10 LET 20 LET 40 0 10 20 30 40 50 60 70 0.45 0.58 0.71 0.83 0.96 1.09 1.22 1.35 1.48 1.61 1.73 Time (ns) Current (uA) LET 5 LET10 LET 20 LET 40 PMOS Passive Drains Current LET5 LET10 LET20 LET40 LET5 LET10 LET20 LET40 MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg MeV.cm 2 /mg (d) Figure 14. Active node drains current for (a) NMOS, (b) PMOS, and passive node drains current for (c) NMOS and (d) PMOS devices at different LETs. 3.2 Circuit model for charge sharing and collection in deep sub-micron technologies Based on the above we propose a modified double-exponential current source model for simulating the charge sharing effects. at the drain of nearby devices , The modification involves another parameter added to double-exponential current source 41 model in addition to rise (τ r ) and fall (τ f ) time constants .We call this new parameter Δt StrikePlateau , which is the duration of the current plateau at the drain of the active device. 0 ( ) [exp( / ) exp( )] StrikePlateau Adj r f t t I t I t τ τ −Δ = − − − , In the above equation, I 0 is the maximum current that can be drawn from the pull-up circuit in NMOS and pull-down circuit in PMOS passive devices. Δt StrikePlateau is the duration of time that extra charges linger under the junctions before starting to recombine and fade away (delaying the recovery process for the junctions). Because of this we call this equation delayed recovery double-exponential source (DR double-exponential). The TCAD simulation results show that particles with different LETs have very close τ r and τ f values for the same layout configuration. We assumed the same τ f and τ r for different LETs and calculated the error induced by comparing the collected charge at the drain of a passive device in the case of using a DR double-exponential current source at the passive node and TCAD simulation results. We measured the area under the current curves for both cases. Figure 15 shows both currents, from TCAD simulations and DR double-exponential, for LETs of 40, 20, 10 and 5 MeV.cm 2 /mg for passive NMOS devices. Figure 16 compares the same for Passive PMOS devices for different tested LETs. 42 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (s) Current (A) Passive NMOS_LET 5 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (s) Current (A) Passive NMOS_LET 5 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation (a) 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (s) Current (A) Passive NMOS_LET 10 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (s) Current (A) Passive NMOS_LET 10 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation (b) 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (ns) Current (uA) DR Double-Exponential TCAD Simulation Passive NMOS_LET 20 MeV.cm 2 /mg 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (ns) Current (uA) DR Double-Exponential TCAD Simulation Passive NMOS_LET 20 MeV.cm 2 /mg (c) 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (ns) Current (uA) Passive NMOS_LET 40 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation 0 5 10 15 20 25 30 35 0.10 0.25 0.41 0.56 0.71 0.86 1.02 1.17 1.32 1.48 Time (ns) Current (uA) Passive NMOS_LET 40 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation (d) Figure 15. Passive node drains current and current from DR Double-exponential for NMOS at LET of (a) 40, (b) 20, (c) 10 and (d)5 MeV.cm 2 /gm 43 0 10 20 30 40 50 60 70 0.45 0.57 0.69 0.81 0.93 1.04 1.16 1.28 1.40 1.52 1.64 1.76 Time (s) Current (A) Passive PMOS_LET 5 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation 0 10 20 30 40 50 60 70 0.45 0.57 0.69 0.81 0.93 1.04 1.16 1.28 1.40 1.52 1.64 1.76 Time (s) Current (A) Passive PMOS_LET 5 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation (a) 0 10 20 30 40 50 60 70 0.45 0.56 0.68 0.79 0.90 1.02 1.13 1.24 1.36 1.47 1.58 1.70 Time (ns) Current (uA) Passive PMOS_LET 10 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation 0 10 20 30 40 50 60 70 0.45 0.56 0.68 0.79 0.90 1.02 1.13 1.24 1.36 1.47 1.58 1.70 Time (ns) Current (uA) Passive PMOS_LET 10 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation (b) 0 10 20 30 40 50 60 70 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) Passive PMOS_LET 20 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation 0 10 20 30 40 50 60 70 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) Passive PMOS_LET 20 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation (c) 0 10 20 30 40 50 60 70 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) Passive PMOS_LET 40 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation 0 10 20 30 40 50 60 70 0.45 0.60 0.76 0.91 1.06 1.21 1.37 1.52 1.67 Time (ns) Current (uA) Passive PMOS_LET 40 MeV.cm 2 /mg DR Double-Exponential TCAD Simulation (d) Figure 16. Passive node drains current and current from DR Double-exponential for PMOS at LET of (a) 40, (b) 20, (c) 10 and (d)5 MeV.cm 2 /gm Table 2 compares the charge amount collected at the drain of the adjacent node as simulated in TCAD versus application of our proposed DR double-exponential current source model for LETs of 5, 10, 20 and 40 MeV.cm 2 /mg for minimum nodal separation (160 nm). 44 TABLE 2. COLLECTED CHARGE AT DRAIN OF PASSIVE DEVICE FOR MINIMUM NODAL SEPARATION (TCAD VERSUS PROPOSED MODEL) LET (MeV.cm 2 /mg) Collected Charge at Passive Drain-TCAD (C) Collected Charge at Passive Drain-I Adj (t) (C) Difference % 5 (NMOS) 1.5e-15 1.9e-15 26.6 5 (PMOS) 2.8e-15 3.2e-15 14.2 10 (NMOS) 3.07e-15 3.45e-15 12.4 10 (PMOS) 7.5e-15 8.3e-15 10.6 20 (NMOS) 1.1e-14 1.0e-14 9 20 (PMOS) 1.9e-14 2.1e-14 10.5 40 (NMOS) 2.15e-14 1.89e-14 12.1 40 (PMOS) 3.83e-14 3.43e-14 10.4 The difference in the collected charge obtained from TCAD simulations and applying DR double-exponential current source is smaller than 27% for minimum nodal separations. The benefit of using the same fall and rise time constants for different LETs is that by running a single TCAD simulation for a specific technology and layout configuration, the time constants are achieved. τ f and τ r can also be obtained from data available in the literature for a specific technology with minimum distances. Since the charge sharing mechanism between adjacent nodes is mainly due to diffusion of charges between nearby devices, increasing nodal separation mitigates the charge sharing effect. We increased the separation distance between nearest devices to 2x and 4x the minimum distance and repeated the measurements of the current at the passive node drain. The nodal separation has considerable effect on the current drawn from the drain of the adjacent device. As shown earlier, diffusion current density is [76]: 45 dif n p n p J eD eD x x Δ Δ = − Δ Δ , while Dn and Dp are electron and hole diffusion coefficients, Δn and Δp are electron and hole concentration gradients. The diffusion current density equation shows that by moving further from the strike location, for the same charge gradient, less amount of charge reaches the drain of a nearby device. Therefore the reduction in the depletion region thickness under the drain of adjacent nodes is less, and the leakage of output stored charges to the substrate slows down and reduces. Therefore τ r and τ f at the current profile for the adjacent device will be larger. We measured τ r and τ f for the 2x and 4x nodal separations from the TCAD simulations. However, if these time constants can be measured for one LET, it can be extended to other LETs, since τ r and τ f stay almost the same for different LETs for constant nodal separation. TABLE 3. COLLECTED CHARGE AT DRAIN OF PASSIVE DEVICE FOR 2X NODAL SEPARATION (TCAD VERSUS PROPOSED MODEL) LET (MeV.cm 2 /mg) Collected Charge at Passive Drain-TCAD (C) Collected Charge at Passive Drain-I Adj (T) (C) Difference % 5 (NMOS) 1e-15 1.1e-15 10 5 (PMOS) 1.9e-15 2.2e-15 15.8 10 (NMOS) 3.2e-15 3e-15 6.2 10 (PMOS) 5.2e-15 5.8e-15 11.5 20 (NMOS) 8.3e-15 7.5e-15 9.6 20 (PMOS) 1.4e-14 1.3e-14 7.1 40 (NMOS) 1.9e-14 1.8e-14 5.3 40 (PMOS) 3.5e-14 3.1e-14 11.4 46 TABLE 4. COLLECTED CHARGE AT DRAIN OF PASSIVE DEVICE FOR 4X NODAL SEPARATION (TCAD VERSUS PROPOSED MODEL) LET (MeV.cm 2 /mg) Collected Charge at Passive Drain-TCAD (C) Collected Charge at Passive Drain-I Adj (t) (C) Difference % 5 (NMOS) 5.6e-16 6.1e-16 7 5 (PMOS) 7.9e-16 9.1e-16 15.2 10 (NMOS) 1.9e-15 2e-15 5.3 10 (PMOS) 2.6e-15 2.8e-15 7.7 20 (NMOS) 4.8e-15 5.2e-15 8.3 20 (PMOS) 7.9e-15 8.7e-15 7.1 40 (NMOS) 1.5e-14 1.4e-14 10.1 40 (PMOS) 2.3e-14 2.1e-14 8.7 Table 3 and 4 show the collected charge at the drain of passive devices for 2x and 4x of minimum nodal separation from TCAD simulations and applying the proposed DR double-exponential current source model at the passive node. The difference between the collected charge obtained from the TCAD simulations and our proposed model is less than 16%. The key advantage of the DR double-exponential current source model over the empirical method is the significantly shorter simulation time. For example 2-D TCAD simulation for two NFET devices in 65-nm technology, using 2 processors, takes 23 hours, 26 minutes and 26 seconds, figure 17 (a), while applying the DR double- exponential source model in HSPICE for the same test scenario takes only 7.25 seconds with just one processor, figure 17 (b). 47 (a) (b) Figure 17. 2-D TCAD simulation time for 2 NFET devices next to each other with minimum spacing in 65-nm technology using 2 processors. 48 Even though the DR double-exponential current equation is achieved by adding a single term to an already existing Double-Exponential current equation, it is crucial for accurately estimating the charge sharing effect between adjacent nodes. The difference in the amount of collected charge at the drain of the adjacent node is less than 16% (except for a single case of 27%) when compared with the TCAD device simulation results. However, for different layout configurations, we still need τ f and τ r ., and that is why we call this a semi-empirical model. These data can be obtained from a single TCAD run or from the data available from literature for any specific layout configuration. Saving significant simulation time while maintaining a reasonably high accuracy are two major benefits of the DR double-exponential current source model. 49 CHAPTER 4: CHARGE SHARING AND COLLECTING MITIGATION TECHNIQUES Charge sharing in deep sub-micron technologies plays an important role in increasing the multiple error rate and lowering the LET threshold for redundancy based RHBD techniques. In memory systems like SRAM, in which devices are packed very close to each other, charge sharing can result in data corruption in multiple memory cells, while most simple Error Correcting Codes (ECC) can handle only a limited number of multiple errors. As mentioned earlier these charge sharing phenomena can completely negate the effectiveness of redundancy based RHBD methods like the DICE storage element and Triple Modular Redundancy (TMR). Therefore, multiple bit upsets due to charge sharing can entirely reduce circuit reliability. When a circuit is designed for radiation environments, the charge sharing and collection among multiple nodes should be taken into consideration in addition to Single-Event Upsets (SEU) and Single-Event Transients (SET) that affect individual devices. For older technologies, the distance between the struck device and its adjacent devices was large enough that most of the induced charges were collected by the hit node only and did not extend to adjacent devices. However, in deep sub-micron technologies, the proximity of devices results in diffusion of charges to nodes other than the hit node. In addition these technologies use a smaller amount of charge to represent a logic high value; therefore, the charge collected due to diffusion can change the state of adjacent nodes, resulting in multiple node errors. 50 We propose a RHBD layout technique and also study the effect of applying Deep Trench Isolation between devices to reduce charge sharing among multiple nodes in adjacent devices. We introduce both techniques in the following two subsections. 4.1 Proposed RHBD layout technique As mentioned above increasing the nodal separation reduces charge sharing and collection in adjacent nodes. Through 3-D TCAD simulations, Amusan et al., showed that the n-well potential collapse from an angular strike with a LET for 21 MeV.cm 2 /mg can extend as far as 5 µm from the strike location for a 90 nm technology [7]. Therefore, any hardened design with sensitive PMOS pairs located within this distance are susceptible to parasitic bipolar effects. Even a heavily contacted n-well can not effectively keep the well potential sufficiently high at all points and prevent collapse. Even though bipolar amplification does not happen for NMOS devices, but still due to small nodal distances, they are also vulnerable to charge sharing due to diffusion of charges to their drains. As intuition would also support, it has been shown experimentally by the same group that nodal separation between sensitive pairs in a DICE element improves the tolerance to single-event soft errors [6]. Thus, if the sensitive nodes are known in a circuit, one effective SEU mitigation techniques is proper separation of these nodes above a given threshold. We use this nodal separation effectiveness to propose a layout technique to reduce susceptibility to upsets for DICE elements in 90 nm technology. We first briefly introduce the DICE storage element. 4.1.1 The DICE storage element The DICE design has been widely used in radiation environments due to its excellent SEU hardness and not being dependent on precise optimal transistor sizing. 51 Two fundamental concepts are used in this design. First, redundancy provides a source of uncorrupted data after a single-event strike. Second, data in the uncorrupted section provides state restoring feedback to recover the corrupted data. The DICE design has four nodes (A, B, C, and D in figure 18) [20] that store the data as two pairs of complementary values, effectively comprising a pair of bi-stable latches, which is the essential element to all storage elements. In write and read operations, these complementary pairs are accessed simultaneously through four NMOS pass gates. We call the complementary pairs (e.g. A and C, B and D) sensitive pairs since any simultaneous changes in both of the nodes in one of these pairs will upset the state of the cell. Therefore, these nodes should be placed far enough from one another to prevent the values changing in both of them due to one single-event strike. Figure 18. The DICE storage cell [20] 4.1.2 Proposed double-DICE storage element To make the DICE design more resistant to SEU, sensitive nodes of one DICE is interleaved with sensitive nodes from another DICE. Sensitive pairs of each DICE are 52 separated in an area-efficient manner. In this way charge sharing between adjacent devices is not the problem anymore, since each cell is immune to charge collection in more than one node. This method saves area, because the otherwise empty spaces between the separated devices are filled with circuitry form another DICE. The main disadvantage to this approach is that more complicated wiring, including higher-level metals usually reserved for top-level routing, may be needed to complete all necessary connections within the Double-DICE cell. With limited cell height restrictions, higher- level metal layers may be needed since all the connections between nodes must traverse distances over other nodes. However, we were able to avoid using higher-level metals for the 90 nm technology. To test the performance of Double-DICE, we used the NAND- based DICE design, shown in figure 19, [74], [7], since it is a robust design even with minimum sizing. This design uses two inverters instead of the four NMOS pass gates shown in figure 18, and thus needs only single-ended inputs instead of differential inputs. In order to separate sensitive nodes in a sensitive pair, each DICE cell was broken into two identical blocks or tiles, as shown in the dotted box of figure 18. Each tile contains two sensitive nodes from two different sensitive pairs (e.g. A and B or C and D nodes in figure 18). 53 Figure 19. One DICE latch is composed of two identical tiles We have implemented a Double-DICE latch and a Double-DICE flip-flop by interleaving the tiles from two different DICE cells. The cells were laid out using the Cadence layout editor in IBM 90 nm technology. Each tile is 4.26 µm wide. Interleaving these tiles from two different DICE elements separates sensitive nodes by 8.5 µm. Only metal 1 and metal 2 were used in this design, reserving the higher level metal layers for top level routings. The layout of one tile (half of a DICE cell) and the Double-DICE latch are shown in parts a and b of figure 20, respectively. 54 8.5 µm 8.5 µm (a) (b) Figure 20. a) Tile layout, b)Double-DICE latch layout The total area of one Double-DICE latch is compared to the area of two DICE latches with sensitive node separations of 8.5 µm and 5 µm (minimum suggested distance between sensitive nodes for 90 nm [7]) in table 5. TABLE 5. AREA COMPARISON Structure Double-DICE Latch 2 DICe latches nodal distance 8.5 µm 2 DICE latches nodal distance 5 µm Total area µm 2 81.79 122.688 88.9 Table 5 shows that the Double-DICE latch has 33.33% less area compared to a pair of DICE latches with a sensitive nodal distance of 8.5 µm; the area saving drops to 8% when a sensitive nodal separation of 5µm is used. This means that we could make DICE latches more tolerant to SEU without compromising area. Indeed, a significant area savings results. The total area of one Double-DICE flip-flop is 167.66 µm 2 . Although intuitively we would not expect much impact on performance with the slightly longer wires connecting nodes in the Double-DICE design, we conducted simulations to confirm that assumption. The Double-DICE and DICE flip-flop performances are shown in table 6. 55 TABLE 6. PERFORMANCE COMPARISON FROM POST LAYOUT SIMULATIONS Structure DICE Flip-Flop Double-DICE Flip- Flop Change Clock to Q Delay (rise) ps 86 113 23% Clock to Q Delay (fall) ps 118 165 28% From SPICE simulations, Clock to Q delays are measured for a DICE and a Double-DICE flip-flop at a clock rate of 500 MHz and data rate of 250 MHz. It can be seen from table 6 that interleaving and adding additional routing has some non-negligible impact on the Clock to Q delay. To see this impact we conduct post layout simulations. The increases in Clock to Q delay for rise and fall edges are 23 and 28 percent, respectively. The extra immunity offered by the nodal separation distance far outweighs this minor speed penalty. Moreover, this result implies that the Double-DICE flip-flop is still fast enough to operate in the GHz range. In our work we implemented the Double-DICE latch and flip-flop, but the same method can be easily applied to other storage cell elements based on the redundant bi- stable latch concept. For instance if one were using redundant bi-stable latches as the basis of radiation-tolerant SRAM cells, by interleaving every two bits of memory in the SRAM, the whole SRAM could be made more immune to SEU without compromising space or memory capacitance. 56 4.1.3 Technology scaling effect on double-DICE In this layout configuration we have shown that the sensitive nodal separation is close to double that of the suggested distance for 90-nm technology. This result provides a very good immunity margin. As we move to smaller technologies, the distance required for mitigating charge sharing in sensitive nodes increases while the nodes actually become closer together in layout, assuming proportional scaling based on feature size. Consequently the immunity margin shrinks to a smaller value. As long as the sensitive nodal separation falls in the immunity margin, the same Double-DICE storage element can be used for such smaller feature sizes. For example if 65 nm technology is used, the width of a tile is around 2.84 µm. Accordingly, the distance between the sensitive nodes becomes approximately 5.7 µm in the Double-DICE design. Assuming the same 5 µm sensitive nodal separation distance is still effective for this technology, the resulting nodal separation is sufficient, albeit with little margin. However, if the required sensitive nodal separation exceeds the resulting layout distance then interleaving more than two storage elements is needed to meet the required distance. For example, for 45 nm, interleaving of four DICE cells may be required. This will change the Double-DICE storage element to a Quadrature-DICE storage element, shown in figure 21. 57 Figure 21. Quadrature-DICE latch. Interleaving four different DICE latches Therefore, as technology scales down, the number of interleaved elements, as well as the amount of wiring, must increase to maintain an adequate separation of sensitive nodes. Thus, the use of higher metal levels may be needed. This effect may cause a problem for standard cell routing tools which will now be restricted from using those higher-level metals, at least when routing signals over such Quadrature-DICE cells [41]. 4.2 Study of deep trench isolation (DTI) as an RHBP technique in MOSFET As mentioned in the previous section, physically separating the sensitive pairs in redundancy-based designs such as DICE is one solution to charge sharing. Physically separating sensitive nodes reduces charge sharing among sensitive nodes of a cell, thereby improving the radiation hardness of each individual cell. However, moving to smaller technologies increases the need for interleaving more cells in order to keep the same radiation immunity level. For example, as mentioned in the last section, instead of interleaving two DICE latches, four DICE latches should be interleaved to gain the same 58 immunity level in a smaller technology. This typically requires more metal layers to be used and complicates wiring. Hence, more loading is imposed on signals, which results in increased delay. Another common technique is adding guard-diodes and guard-rings to NFET and PFET transistors [5]. Adding guard-diodes and guard-rings mitigates charge collection in adjacent nodes but still increases area. Deep Trench Isolation (DTI) has been widely used for noise reduction and latch- up prevention for MOSFET and bipolar transistors [102] [16]. The effect of DTI on single-event effects (SEE) and the charge collecting behavior of SiGe HBTs has been thoroughly studied [88], [100], and [80]. We suggest the use of DTI as a charge collection isolator between adjacent nodes. We investigate the effects of employing DTI in 65-nm NFET and PFET transistors to mitigate charge sharing and collection between adjacent nodes. We use Synopsys 2-D TCAD mixed-mode simulation to compare collected charge at a node in close proximity to a node struck by a heavy-ion particle when two such devices are separated by STI, DTI, guard-ring, guard-diode and increased nodal distances. We conducted our 2-D TCAD mixed-mode simulations on NFET and PFET devices in an n-well process. Our MOSFET devices were calibrated to match electrical characteristics (I d -V d and I d -V g curves) obtained from the IBM 65-nm PDK (Process Design Kit). MOSFET devices were developed with the Synopsys Structure Editor and simulated with the Sdevice simulator. The mixed-mode simulation set-ups are illustrated in figure 22. Two 4-string chains of inverters are used where the MOSFETs of the second inverters, in both chains, are analyzed as 2-D TCAD devices, and the rest of the circuit is modeled using 65-nm commercial compact models. 59 gnd Active Device gnd Passive Device Input 2 Input 1 Out2 Out1 Ion strike Inverter chain 2 Inverter chain 1 vdd vdd Drain Drain Source Source Well Contact Well Contact P Substrate gnd Active Device gnd Passive Device Input 2 Input 1 Out2 Out1 Ion strike Inverter chain 2 Inverter chain 1 vdd vdd Drain Drain Source Source Well Contact Well Contact P Substrate (a) vdd Input 2 Input 1 Out2 Out1 Ion strike Inverter chain 2 Inverter chain 1 gnd gnd vdd Active Device Passive Device Drain Drain Source Source Well Contact Well Contact N Well Well Contact gnd P Substrate vdd Input 2 Input 1 Out2 Out1 Ion strike Inverter chain 2 Inverter chain 1 gnd gnd vdd Active Device Passive Device Drain Drain Source Source Well Contact Well Contact N Well Well Contact gnd P Substrate (b) Figure 22. Simulation set-up for two adjacnet (a) NMOS and (b) PMOS devices All the ion strikes are normal to the surface of the silicon. We used un-doped poly-silicon as the filling of our DTI structures with silicon oxide layers around it [86], as shown in figure 23. The DTI in our simulations is 1.2 µm deep and 160 nm wide (the same width as shallow trench isolation). 60 Figure 23. 2-D TCAD DTI structure The active and passive MOSFET W/L sizes are 150nm/60nm (minimum size transistors). Our test cases are: • NMOS-NMOS (PMOS-PMOS) with STI and base spacing (160 nm) (Base case) • NMOS-NMOS (PMOS-PMOS) with DTI and base spacing (160nm) • NMOS-NMOS (PMOS-PMOS) with STI and double the base spacing (320 nm) • NMOS-NMOS (PMOS-PMOS) with STI and four times the base spacing (640 nm) • NMOS-NMOS (PMOS-PMOS) with STI and guard-ring • NMOS-NMOS (PMOS-PMOS) with STI and guard-diode Schematic cross-sections of the last two cases are shown in figure 24 (a)-(d) for NFET and PFET devices, respectively. 61 n+ n + p+ p + n + p + p-substrate Source Drain gnd Gate Guard ring STI STI gnd n+ n + p+ p + n + p + p-substrate Source Drain gnd Gate Guard ring STI STI gnd (a) n + n + n + n + p-substrate Source Drain Gate V dd V dd Guard diode STI STI p + STI gnd n + n + n + n + p-substrate Source Drain Gate V dd V dd Guard diode STI STI p + STI gnd (b) p + p + p + n + n + p-substrate n-well STI STI STI Gate Drain Source V dd V dd gnd Guard ring p + p + p + n + n + p-substrate n-well STI STI STI Gate Drain Source V dd V dd gnd Guard ring (c) n + p + p + p + p + p + STI STI STI STI n-well p-substrate Gate Drain Source gnd gnd gnd V dd Guard diode n + p + p + p + p + p + STI STI STI STI n-well p-substrate Gate Drain Source gnd gnd gnd V dd Guard diode (d) Figure 24. Schematic cross-sections of (a) NMOS guard-ring, (b) NMOS guard-diode, (c) PMOS guard-ring and (d) PMOS guard-diode Simulations were repeated for LETs of 5, 10, 20 and 40 MeV.cm 2 /mg for all the above test cases. Both active and passive MOSFET devices were set up to be in the off state when the heavy ion strike occurs. 62 TCAD simulation results show that for 65-nm technology heavy ions with LETs of 20 MeV.cm 2 /mg and larger not only change the state of the active device, but also change the state of the passive device, which is located 160 nm from the strike location (drain of active device). Output voltages and induced transient currents of active and passive NMOS devices are shown in figure 25 (a) and (b). Time (s) Voltage (V) Active_Node Passive_Node Time (s) Current (A) Active_Node Passive_Node Time (s) Voltage (V) Active_Node Passive_Node Time (s) Current (A) Active_Node Passive_Node (a) (b) Figure 25. (a) Induced output voltage and (b) induced current transient at the drain of NMOS active and passive devices 4.2.1 Effectiveness in charge collecting reduction In order to compare the effectiveness of these mitigation methods, the total charge collected at the drain of the passive node from the time of the strike until the effect has subsided are measured by calculating the area under the I Drain (t) curves for LETs of 5, 10, 20 and 40 MeV.cm 2 /mg for different test cases . Table 7 shows the collected charge at the drain of passive devices for PMOS and table 8 for NMOS transistors when increased nodal separation, guard-ring, guard-diode and DTI are used. The collected charge at the passive nodes for different LETs for different mitigation techniques are also compared in figure 26. 63 TABLE 7. COLLECTED CHARGE AT THE PASSIVE PMOS FOR DIFFERENT LETS AND MITIGATION TECHNIQUES Collected charge (fC) LET (MeV.cm 2 /mg) Base-line 2x nodal distance 4x nodal distance Guard- ring Guard- diode DTI 5 2.8 1.8 0.7 0.3 0.1 0.07 10 7.4 5.1 2.5 1.0 0.6 0.02 20 18.8 14.4 7.9 3.6 2.3 0.2 40 38.3 35.4 23.2 11.0 8.4 0.3 TABLE 8. COLLECTED CHARGE AT THE PASSIVE NMOS FOR DIFFERENT LETS AND MITIGATION TECHNIQUES Collected charge (fC) LET (MeV.cm 2 /mg) Base-line 2x nodal distance 4x nodal distance Guard- ring Guard- diode DTI 5 2.6 1.0 5.6 3.4 2.4 0.06 10 4.5 3.2 1.9 9.9 7.3 0.1 20 1.1 8.2 4.7 2.0 2.1 0.1 40 2.1 1.9 1.5 5.9 7.4 0.5 0 5 10 15 20 25 30 35 40 5 10 20 40 LET(MeV.cm 2 /mg) Charge (fC) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Min_Nodal_Distance Passive NMOS 0 5 10 15 20 25 30 35 40 5 10 20 40 LET(MeV.cm 2 /mg) Charge (fC) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Min_Nodal_Distance Passive NMOS (a) 0 5 10 15 20 25 30 35 40 5 10 20 40 LET(MeV.cm 2 /mg) Charge (fC) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Min_Nodal_Distance Passive PMOS 0 5 10 15 20 25 30 35 40 5 10 20 40 LET(MeV.cm 2 /mg) Charge (fC) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Min_Nodal_Distance Passive PMOS (b) Figure 26. Charge collected at the drain of passive (a) NMOS and (b) PMOS for Minimum nodal separation, 2 times and 4 times more nodal distance, guard-ring, guard-diode and DTI 64 In the case of DTI, the amount of charge collected at the drains of passive NMOS and PMOS devices is negligible compared to other mitigation methods. The reduction in the amount of collected charge at the drain of passive device when using DTI is more than 97% for different LETs. For other methods, scenarios involving particles with larger LETs show a decrease in the reduction in collected charge. In table 9 and 10 the percentage of reduction in collected charge at passive nodes for PMOS and NMOS devices are shown for different LETs. TABLE 9. PERCENTAGE IN THE COLLECTED CHARGE REDUCTION AT THE PASSIVE PMOS FOR DIFFERENT LETS AND MITIGATION TECHNIQUES Charge collected reduction (%) LET (MeV.cm 2 /mg) 2x nodal distance 4x nodal distance Guard- ring Guard- diode DTI 5 34.0 72.1 87.6 93.0 97.4 10 30.6 65.7 85.4 91.0 99.6 20 23.6 57.9 80.4 87.6 98.9 40 7.35 39.19 71.0 77.9 99.0 TABLE 10. PERCENTAGE IN THE COLLECTED CHARGE REDUCTION AT THE PASSIVE NMOS FOR DIFFERENT LETS AND MITIGATION TECHNIQUES Charge collected reduction (%) LET (MeV.cm 2 /mg) 2x nodal distance 4x nodal distance Guard- ring Guard- diode DTI 5 61.0 78.7 87.1 90.6 97.4 10 29.5 57.9 78.1 83.8 96.6 20 25.1 56.6 81.4 80.9 98.3 40 11.4 30.2 72.6 65.2 97.6 65 % reduction in collectd charge at passive pmos 0 20 40 60 80 100 5 10 20 40 LET (MeV.cm 2 /mg) Charge reduction (%) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance (a) % reduction in collected charge at passive nmos 0 20 40 60 80 100 5 10 20 40 LET (MeV.cm 2 /mg) Charge reduction (%) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance (b) Figure 27. Percentage of charge reduction at the drain of passive (a) PMOS and (b) NMOS for Minimum nodal separation, 2 times and 4 times more nodal distance, guard ring, guard diode and DTI For better visualization and comparison of these changes in the charge reduction at the adjacent node for different mitigation techniques, we plotted them in figure 27 for both PMOS and NMOS devices. 66 It is seen that DTI exhibits a steady charge collection reduction even when the ion energy doubles, while other methods lose their effectiveness as particles with higher energies are applied. This implies that for higher LETs, DTI provides better charge sharing immunity than other tested methods. 4.2.2 Area overhead comparison Area is another important factor in today’s integrated circuit design. DTI has the least area overhead as compared to other alternative methods, figure 28. The area increases by 12% for double nodal separation and 24% for four times nodal separation, guard-ring, and guard-diode, as compared to the area required for DTI. Base distance DTI 2x distance 4x distance Guard Ring Guard Diode Area saved by DTI Base distance DTI 2x distance 4x distance Guard Ring Guard Diode Area saved by DTI Figure 28. Area comparison for different TCAS structures, (a) STI with base spacing, (b)DTI, (c) STI with double spacing, (d)STI with four times spacing, (e) guard-ring, and (f)guard-diode 4.2.3 Single event mitigation at the active node To study the effect of these different mitigation techniques on the active device, the induced output voltage pulse width for LETs of 20 and 40 MeV.cm 2 /mg are 67 measured. Figure 29 shows the induced pulses at the NMOS active node by a particle with LET of 20 MeV.cm 2 /mg for different mitigation techniques. 0 2e-9 4e-9 6e-9 8e-9 0 0.5 1 Time (s) Voltage (v) 0 2e-9 4e-9 6e-9 8e-9 0 0.5 1 Time (s) Voltage (v) Figure 29. Induced voltage pulses at active device output for LET of 20 MeV.cm 2 /mg The percentage of increase or decrease in the active device output voltage pulse widths are compared in figure 30. The pulse widths are measured at 0.5 volts (Vdd/2). Pulse broadening at the output of the active node is more severe in the case of DTI, while the guard-ring approach reduces the pulse width and consequently mitigates the SEE at the active device. The guard-diode scheme also reduces the pulse width for active PMOS devices; however, in NMOS for LET of 40 MeV.cm 2 /mg this scheme does not show any improvement in pulse width. Nonetheless, it causes less pulse broadening (2.6%) than DTI and increased nodal separation techniques. This data implies that employing DTI isolates the effect of particle strikes to the struck node, but the result is a pulse broadening at the struck node. 68 -30 -20 -10 0 10 20 30 40 50 20 40 LET (MeV.cm 2 /mg) Increase/Decrease in Active Node Output Pulse Width (%) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Active PMOS -30 -20 -10 0 10 20 30 40 50 20 40 LET (MeV.cm 2 /mg) Increase/Decrease in Active Node Output Pulse Width (%) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Active PMOS (a) -30 -20 -10 0 10 20 30 40 50 20 40 LET (MeV.cm 2 /mg) Increase/Decrease in Active Node Output Pulse Width (%) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Active NMOS -30 -20 -10 0 10 20 30 40 50 20 40 LET (MeV.cm 2 /mg) Increase/Decrease in Active Node Output Pulse Width (%) DTI Guard_Diode Guard_Ring 4x_Nodal_Distance 2x_Nodal_Distance Active NMOS (b) Figure 30. Percentage of increase or decrease in the output voltage pulse width at the active device while using different mitigation techniques compared to the minimum distance nodal separation for (a) active PMOS and (b) active NMOS In addition to pulse broadening, the extra fabrication cost of DTI must be taken into account. Therefore, based on the application, a designer can decide which of the above techniques is an appropriate mitigation solution; however these results show DTI to definitely be an effective fault isolation technique while guard-ring and guard-diode show better SEE mitigation at the active node (struck node) [39]. 69 CHAPTER 5: MOS CURRENT MODE LOGIC Integration of analog and digital circuitry onto the same die has been extremely desirable since it increases the device density. This integration has been delayed due to the difficulty in design of high precision analog circuitry in the presence of digital noise. Excess power dissipation is another problem that arises when the density of devices on a chip increases. A circuit style that seems to be capable of providing an analog friendly environment and reducing the power consumption is MOS Current Mode Logic (MCML). Therefore, MCML is in general an alternative circuit design style that has a differential input/output structure and creates less noise between analog and digital circuitry in mixed-signal environments and on power supply rails. It is also faster than conventional CMOS circuitry with less power consumption in high-frequency applications. Bipolar CMLs have been used for years in high-performance applications, but they are dependent on bipolar fabrication technology while MCML can be implemented in standard CMOS fabrication technology. This feature makes MCML an attractive alternative circuit to CMOS for high-speed, low-power applications for both mixed-signal and digital designs. It has been shown that a MCML 64-bit adaptively pipelined adder could dissipate less power than equivalent CMOS circuitry as well as adjust for clock skew and environment or process variations [69]. The all-NMOS transistor structure of MCML also mitigates the multiple bit upsets in environments with high-energy particles. 70 5.1 MCML structure The MCML structure is fully differential and switches current between two pull- up resistors. The output voltage swing of ΔV=IR is set by adjusting the pull-up resistors for a chosen bias current [71]. Figure 31 shows the basic MCML structure. The output voltage swing of MCML is not rail-to-rail and is also much less than that of CMOS. This is the primary reason that makes MCML faster than CMOS. The differential structure of MCML also rejects any common-mode noise and distortion. The reduced output voltage swing decreases crosstalk between analog and digital circuits, hence making MCML a better candidate for mixed-signal applications. It draws almost constant current from Vdd (dI/dt ≅ 0), which reduces noise spikes on power supply rails. It is also claimed that MCML is less sensitive to process, supply, environmental variations and coupling than CMOS [18]. It is also more flexible in design optimization than CMOS circuits. While CMOS circuits are optimized by changing the device sizes and Vdd voltage, MCML can be optimized by adjusting the output voltage swing, bias current, Vdd and transistor sizes [71]. Figure 31. Basic structure of MCML 71 5.2 MCML performance The main disadvantage of MCML is the high constant static power dissipation with respect to CMOS. Although it must be taken into account at low frequencies, at high frequencies CMOS dynamic power becomes the dominant term in power dissipation, and MCML becomes comparable to CMOS in power dissipation. A power-delay performance for MCML circuits better than that of equivalent CMOS circuits for high frequency systems has been shown by Muscier and Rabaey [71], as discussed below: Let’s assume a circuit with a linear chain of N identical gates, all with load capacitance C. The total propagation delay is proportional to: . . . . MCML V D N R C N C I Δ = = where N is the total logic depth of the circuit. While static CMOS gates tend to dissipate static and dynamic power, the current draw of MCML gates is independent of switching activity. With this assumption, the expression for power, power-delay, and energy-delay can be written as: MCML dd P N I V = × × 2 MCML dd dd N C V PD N I V N C V V I × ×Δ = × × × = × ×Δ × 3 2 2 2 dd MCML dd N C V V N C V ED N C V V I I × × ×Δ × ×Δ = × ×Δ × × = The delay, power, power-delay, and energy-delay for static CMOS logic are well known and approximated by: ( ) 2 dd CMOS dd t N C V D K V V α × × = × − 72 2 1 CMOS dd CMOS P N C V D = × × × 2 CMOS dd PD N C V = × × 2 2 2 2 ( ) dd CMOS dd t V C ED N K V V α = × × × − where k and α are process and transistor size dependent parameters. It can be noticed from the energy-delay product formulas that MCML circuits do not have a theoretical minimum to the energy-delay product while the CMOS circuits do [69], and [71]. However, the logic depth, N, should be taken into consideration when comparing CMOS and MCML energy-delay products. The performance of MCML gates in comparison to CMOS decreases linearly with N. This is because of the static power consumed by MCML circuits even when there is no switching. Therefore in order to have better energy-delay products than CMOS, MCML circuits should have a shallow logic depth. For slowly clocked circuits, CMOS circuits have better energy-delay products than MCML circuits. 5.3 MCML applications MCML is used in multi-GHz communication systems such as MUX/DEMUX ICs for SONET/SDH optic-fiber links, high-speed cross-point switches for network (LAN/WAN) applications, RF applications (PLL, pre-scalers, circuits for clock recovery and VCOs), high-speed buffers/links. Due to its power efficiency at high speed operations it is suitable for low-power DSP ICs [3]. And its low switching noise makes it very popular in mixed-signal high-accuracy ICs [71]. Some examples of MCML inverter, NAND and Latch gates are shown in figure 32. 73 (a) (b) (c) Figure 32. MCML (a) inverter, (b) NAND, and (c) Latch 5.4 Single-event upset sensitivity analysis of MCML sequential elements As seen in figure 33, PMOS devices are more sensitive to charge sharing than NMOS devices [79]. In this graph, the active device is the transistor that is directly struck by an ion, and the passive device is a transistor in close proximity. Figure 33. Collection charge between adjacent devices [79] Considering all these benefits of MCML, it is beneficial to study its response and behavior in radiation environements. A standard MCML latch is illustrated in figure 32 (c). Cross-coupling at the transistor-level, required for the storage cell functionality in the 74 MCML latch, increases the vulnerability of MCML to SEU [77]. As a result, the drains of the NMOS transistors in both the pass stage and the hold stage are the sensitive nodes in this circuit topology. If the value stored in one of these nodes changes, it will flip the value stored in the hold stage. In order to evaluate the MCML latch SEU sensitivity and compare it with CMOS, we use critical charge (Q crit ) as the measure. As mentioned in a previous section, critical charge is the minimum amount of charge needed to be collected in a sensitive node to change the state of that node. Drift and diffusion are the two well- known mechanisms that transport the generated charges to a circuit node. This creates a current pulse that disturbs the node level and leads to a corrupted data bit. Therefore for calculating Q crit in a circuit simulator, a current source is used to model the current pulse created by an ion strike. For strikes with LETs smaller than 1 Me.V.cm 2 /mg, it has been shown that the current has a double-exponential profile from the data obtained from laser tests and 3-D TCAD simulations, figure 34 [73]. 0 100 200 300 400 500 600 1950 1975 2000 2025 2050 2075 2100 time (ps) Current (uA) Pulses from 3D simulations ---- Best-fit Upset inducing pulse LET=1 LET=0.5 LET=0.25 LET=0.20 LET=0.1 Upset inducing Figure 34. 3-D TCAD simulations current pulses for LET<1 MeV.cm 2 /mg [73] 75 The double-exponential waveform equation is shown below: ( ) ( [exp( ) exp( )]) ( ) f r f r Q t t I t τ τ τ τ − − = − − Therefore, we use a double-exponential current source in our simulations. We choose the rise time (τ r ) of 16 psec and fall time (τ f ) of 161 psec from the data available in the literature for 90 nm technology [73]. All MCML circuits we evaluated were designed in IBM 90 nm technology. For different clock rates of 0.5, 1, 2, and 4 GHz, the output voltage swing is swept from 300 mV to 500 mV in order to see the effects of clock frequency and voltage swing on SEU sensitivity. We choose a minimum voltage swing of 300 mV to ensure signal integrity in the presence of thermal noise and device mismatch. In order to investigate the effect of bias current on SEU sensitivity, bias current is swept from 30 µA to 500 µA while output voltage swing and clock rate are constant. The same procedure is repeated for the other two output voltage swings to observe the effect of output voltage swing. The data frequency is chosen to be half of the clock frequency. As mentioned earlier a double-exponential current source is used to model a single-event strike. This current source is placed between the drain of the NMOS in the hold stage and ground, shown in figure 35. 76 Figure 35. Double-exponential current source placement We use a current mirror for accurate biasing of the sequential elements. Transistors have been sized according to output voltage swing. For each output voltage swing the transistors in the current mirror are sized to be in a saturation region. The lengths of these transistors are set at double the minimum length to increase the output impedance for the current source and to decrease the effects of transistor length mismatch between the biasing and logic circuit [71]. We use poly resistors, as poly has better accuracy compared to n-well and diffusion resistors. Area is the trade-off since poly resistors occupy more area compared to n-well resistors. In order to find Q crit , the charge injected by the double-exponential current source is swept to the point that it flips the output of the flip-flop, as shown in figure 36. Clock Data Q Error Bit Clock Data Q Error Bit Figure 36. Clock, Data and Output (Q) waveforms of a single-event hit flip-flop 77 As we increase the bias current, Q crit increases independent of operating frequency. Figure 37 shows Q crit versus bias current for different output voltage swings at clock frequencies of 0.5 and 2 GHz. Figure 37. Critical charge (Qcrit) versus Bias current for different output voltage swings A larger bias current implies larger transistor sizes, and as a result larger capacitances to hold charge and consequently more immunity to SEU. In table 11, the amount of increase in Q crit is shown for different output voltage swings at a clock of 0.5 GHz when moving from 30 µA to 100 µA. It can be seen that the amount of Q crit increases more than 3 times for output voltage swings of 400 mV and 500 mV. This increase is almost 5 times that for an output voltage swing of 300 mV. TABLE 11. Q CRIT IMPROVEMENT WITH CURRENT BIAS AT CLOCK RATE OF 0.5 GHZ Δ Δ Δ ΔV=IR(mV) Q crit (fC) at I=30 µA Q crit (fC) at I=100 µA Increase in Q crit 300 0.4 1.94 x4.85 400 0.73 2.67 x3.66 500 0.89 2.83 x3.18 In order to show how much area is sacrificed to gain more SEU tolerance, we laid out two latches with resistor and transistor sizes calculated for bias currents of 30 µA and 0 2 4 6 8 10 12 0.03 0.05 0.07 0.1 0.5 Bias Current (mA) Critical Charge (fC) Clock rate @ 2 GHz Δ Δ Δ ΔV=500mV Δ Δ Δ ΔV=400mV Δ Δ Δ ΔV=300mV 0 2 4 6 8 10 12 0.03 0.05 0.07 0.1 0.5 Bias Current (mA) Critical Charge (fC) Clock rate @ 0.5 GHz Δ Δ Δ ΔV=500mV Δ Δ Δ ΔV=400mV Δ Δ Δ ΔV=300mV 78 100 µA at an output voltage swing of 300 mV and a clock rate of 0.5 GHz. Sizes are shown in table 12. TABLE 12. RESISTOR AND TRANSISTOR SIZES FOR ΔV=300 MILIVOLTS FOR BIAS CURRENT OF 30 AND 100µA I (µA) Resistance (kΩ Ω Ω Ω) Pull-down transistor width (µA) Biasing transistor width (µm) 30 10 0.9 0.6 100 3 4.8 0.6 The layouts for bias currents of 30 and 100 µA at ΔV= 300 mV are shown in figure 38. Both layouts occupy about 75 µm 2 in area. (a) (b) Figure 38. MCML latch layout for ΔV=300 mV and clock rate=0.5 GHz for (a) I b =30 µA and (b)I b =100 µA This implies that increasing the bias current does not have a significant effect on total layout area. Even though the transistor sizes increase with bias current, the pull-up resistor sizes decrease, and this keeps the area almost constant. The important downside of moving to a higher bias current is the power consumption, which increases linearly with bias current. Even though the biasing current of 100 µA is in the tolerable range for MCML, the power budget is the key point that should be considered when designing 79 radiation-hardened MCML. For a bias current of 500 µA, the increase in Q crit is even more significant, but at a cost of a significant rise in power consumption and area. For example by changing the bias current to 500 µA, Q crit increases by 9.8 times compared to the Q crit at 30 µA, but the exorbitant cost of area and power consumption do not justify this improvement for most applications. For the next set of simulations, we sweep output voltage swing to see its effects on SEU sensitivity of MCML. As seen in figure 39, by increasing ΔV the SEU tolerance improves. Figure 39. Q crit versus Output Voltage Swing for different Bias currents Q crit increases as ΔV amplifies due to better margin on the effective voltage (V gs - V th ) of cross-coupled transistors in the hold stage. This is similar to increasing the noise margin of a circuit. Therefore with higher ΔV at a constant bias current and transistor size, more charge is needed to upset the state of the hold stage. This improvement is shown in table 13, when moving from ΔV=300 mV to ΔV=500 mV with constant bias current at a clock frequency of 0.5 GHz. 0 0.5 1 1.5 2 2.5 3 3.5 300 400 500 Output Voltage Swing (mV) Critical Charge (fC) I = 100 µA I = 70 µA I = 50 µA I = 30 µA Clock rate @ 0.5 GHz 0 0.5 1 1.5 2 2.5 3 3.5 300 400 500 Output Voltage Swing (mV) Critical Charge (fC) I = 100 µA I = 70 µA I = 50 µA I = 30 µA Clock rate @ 0.5 GHz 0 0.5 1 1.5 2 2.5 3 3.5 300 400 500 Output Voltage Swing (mV) C ritical C h arge (fC ) I = 100 µA I = 70 µA I = 50 µA I = 30 µA Clock rate @ 2 GHz 0 0.5 1 1.5 2 2.5 3 3.5 300 400 500 Output Voltage Swing (mV) C ritical C h arge (fC ) I = 100 µA I = 70 µA I = 50 µA I = 30 µA Clock rate @ 2 GHz 80 TABLE 13. Q CRIT IMPROVEMENT WITH ΔV FOR DIFFERENT BIAS CURRENTS AT CLOCK RATE OF 0.5 GHZ Bias Current (µA) Q crit (fC) at Δ Δ Δ ΔV=300 mV Q crit (fC) at Δ Δ Δ ΔV= 500 mV Increase in Q crit 30 0.4 0.89 x2.22 50 0.89 1.37 x1.54 100 1.94 2.83 x1.46 Improving the SEU immunity by changing the ΔV does not increase the power consumption in this case, since the bias current is constant. However area is compromised, since increasing ΔV=IR at constant I, increases the size of pull-up resistors (R). As mentioned before and as also can be seen from the layout in figure 37, poly resistors occupy a large percentage of the area in MCML. Thus, if we are limited by power, increasing the ΔV is a promising solution, but area is compromised. The clock-to-Q delay of MCML has been measured at different bias current, output voltage swings and clock frequencies. The delays are measured at both rising and falling edges of clock. All the delays are on the order of picoseconds. These delays for the case of 0.5 GHz are shown in table 14. There is little difference in delay values for the differing bias currents shown. TABLE 14. CLOCK-TO-Q DELAYS FOR DIFFERENT BIAS CURRENTS Bias Current (µA) Clock to Q delay for rise edge (ps) Clock to Q delay for fall edge (ps) Average delay (ps) 30 70 60 65 50 70 50 60 70 60 40 50 100 70 40 55 500 80 50 65 81 If we consider the RC model for out delay measurement, then as capacitance (C) goes up with increasing transistor sizes, the resistance (R) goes down as the result of smaller pull-up resistors, keeping the RC product almost constant. To compare the SEU immunity of a MCML latch with a CMOS latch, we simulate a D flip-flop in 90 nm technology with the same double-exponential current source at its sensitive node. The Q crit for the CMOS flip-flop is 3.24 fC. For the MCML flip-flop at the same frequency (0.5 GHz), Q crit values of 5.98 and 8.49 fC are achieved for a bias current of 500 µA at output voltage swings of 400 mV and 500 mV, respectively. However, the costs of power consumption and area of these MCML design points are very high. At lower bias currents, the Q crit value is less for MCML than CMOS. For example, at a bias current of 100 µA, Q crit is 2.83 fC for an output voltage swing of 500 mV, which is 1.14 times less than that of CMOS. The comparison was done at 0.5 GHz, at which both CMOS and MCML can operate accurately. At higher frequencies, it is difficult to achieve functionality with CMOS, and it is therefore impractical. We also measure the Clock-to-Q delay for the CMOS flip-flop and it is 105 picoseconds, which is 1.6 times slower compared to a MCML flip-flop with a worst-case delay of 65 picoseconds [40]. Based on the simulations results, an optimized MCML design having a Q crit close to that of CMOS at a clock frequency of 0.5 GHz, a bias current of 100 µA and output voltage swing of 400 mV are optimized design parameters in terms of power consumption and area. This results in a Q crit value of 2.7 fC, which is close to that of CMOS with critical charge of 3.2 fC. However, if an application can accommodate a bias 82 current as high as 500 µA, the critical charge value improves to 5.98 fC at the same output voltage swing. 5.5 Proposed RHBD MCML sequential element As mentioned earlier, cross-coupling at the transistor-level, required for the storage cell functionality in the MCML latch, increases the vulnerability of the MCML to SEU. As a result the drains of the NMOS transistors in both the pass stage and the hold stage are the sensitive nodes in this circuit. If the value stored in one of these nodes changes, it will flip the value stored in the hold stage. One simple solution to make the latch harder to SEU is to slow down the feedback loop by adding delay. In this way, there is more time for the induced charges (created electron-hole pairs) to re-combine. This can be done by adding resistors to the feedback path. However, to be hard enough, especially in deep sub-micron technology, the resistance must be large, and this adds delay and area penalties in amounts that are not acceptable for most circuits in high-speed systems. In our proposed SEU-hard MCML, shown in figure 40, we used resistors in the feedback loop, but we made their resistances controllable to minimize the delay penalty during normal operation. PMOS transistors operating in the triode region are used as the resistors, and their resistances are controlled by their gate voltages. In the case of an ion strike, the feedback resistances are increased, while in normal operation, the resistances are decreased to the minimum value. In our proposed design, PMOS gates are driven by a custom bias control circuit whose output voltage increases in case of an ion strike. The bias controller inputs are connected to the sensitive nodes of the MCML. 83 Figure 40. Proposed SEU-Hard MCML In normal operation, MCML outputs are differential: one is “vdd” and the other is “vdd-IR”. In the case of an ion strike, one of these nodes may discharge to “0”. This increases the bias controller output voltage. The bias controller output voltage does not go as high as Vdd since in the case of a single strike, if the strike hits the Vdd-charged sensitive node the other node is still Vdd-IR. The NMOS gate of the bias controller is not completely off. On the other hand, if a strike hits the Vdd-IR charged sensitive node the other NMOS gate is still connected to Vdd; hence the output will not turn off PMOS gates completely, but it does increase their resistances. The equation below shows the relation between the gate voltage and resistance of a PMOS transistor. where V gs is the gate-source voltage and V t is the threshold voltage of the PMOS transistors. , 1 ( ) on p p ox gs t R W C V V L μ = − 84 For the same resistance value, PMOS resistors occupy a smaller area compared to poly resistors, and their resistance is controllable by changing their gate voltage. By making the resistance controllable, speed is not sacrificed in normal operation. To test our proposed design, we implement it in IBM 65 nm technology. We repeat our simulations for four different clock rates of 0.5,1, 2 and 4 GHz, with an output voltage swing of 400 mV. For the MCML flip-flop to operate at 4 GHz pull-up resistors should be 2kΩ or less; otherwise the resulting delay is not acceptable. This results in a 200 µA bias current for the mentioned output voltage swing. A double-exponential current source is used to model a single-event strike in HSPICE. To calculate the rise and fall coefficients of the double-exponential current source for this technology, we first use 2-D Mixed-mode TCAD simulations. Synopsys TCAD is software that uses computer simulations to develop and optimize semiconductor processing technologies and devices. TCAD solves fundamental, physical partial differential equations, such as diffusion and transport equations. We use the TCAD structure editor to develop a generic 65 nm NMOS device and then simulate it with Sdevice simulator. The current pulse derived from the drain of the struck NMOS is imported to MATLAB and best fitted with a double-exponential waveform, figure 41. Figure 41. Double exponential current model 85 The rise time (τ r ) of 2 ps and fall time (τ f ) of 5.5 ps of this waveform is then used in our HSPICE simulations. This double-exponential current source is placed between the drain of the NMOS in the hold stage and ground. The drains of the NMOS transistors in the hold stage are the most sensitive nodes of the MCML latch since any change of the value at these drains changes the output value of the latch. We use a cascade current mirror for accurate biasing of the sequential elements. Transistors have been sized according to output voltage. The transistors in the biasing circuit are sized to be in the saturation region. The lengths of these transistors are set at double the minimum length to increase the output impedance for the current source and to decrease the effects of transistor length mismatch between the biasing and logic circuit [71]. In order to find Q crit , the charge injected by the double-exponential current source is swept to the point that it flips the output of the flip-flop, as shown in figure 42. CLK Data MCML Q SEU-Hard MCML Q Error Bit CLK Data MCML Q SEU-Hard MCML Q Error Bit Figure 42. Clock, Data, MCML output (Q) and SEU-Hard MCML output (Q) waveforms of a single-event hit MCML flip-flop for clock frequency of 2 GHz 86 From the above figure, it can be seen that the new SEU-Hard MCML generates the correct output in case of an SEU strike. Simulation results show that Q crit is improved more than 5 times (more than 440%), Table 15. TABLE 15. CRITICAL CHARGE IMPROVEMENT IN NON-HARD AND HARD MCML Q crit (fC) non-Hard MCML Q crit (fC) HardMCML Increased in Q crit 0.297 1.61 x5.4 The layout area is 21.4 µm 2 for a non-hard MCML and 28.88 µm 2 for the proposed SEU-Hard MCML, which represents a 35% increase in area. To quantify the speed penalty, we measure the clock-to-Q delay for the non-hard MCML which is 41 psec and for the proposed SEU-hard MCML is 65 psec. This shows that our proposed SEU-Hard MCML is still fast enough to be employed in GHz environments. The power consumptions of the non-hard and SEU-hard MCML are 474 µW and 940 µW, respectively (assuming Vdd=1.2 volts). This results in a 98% power penalty. Nothing has been published on RHBD techniques for MOS CML yet; however there are RHBD techniques for bipolar and BiCMOS CML circuits. Therefore, we compare the power and area penalty of our design to similar proposed RHBD approaches in bipolar and BiCMOS CML latches and flip-flops. We first briefly introduce these methods, assuming that they can be applied to MCML technologies as well. The first method discussed is the Dual- interleaved (DI) D-flip-flop, shown in figure 43. 87 Figure 43. Dual-interleaved BiCMOS CML D-flip-flop circuit [55] Cross-coupling at the transistor-level, required for the storage cell functionality in the standard CML D flip-flop, increases the vulnerability of this circuit to SEU. Therefore, local redundancy is built into the standard CML D flip-flop to include limited transistor-level decoupling in the storage cell, thereby lowering its SEU sensitivity. Unlike the standard D flip-flop, the base and the collector of the transistors in the storage cell of the DI flip-flop are not connected to the same differential pair in the pass cell, thus achieving effective decoupling of the base and collector terminals of the transistors in the storage cell. To maintain the storage cell functionality, the base and collector of each transistor in the storage cell are connected to complementary outputs from the pass cell. Therefore, a SEU transient current following through the collector of the transistor in the storage cell does not affect the base directly [55]. The second method discussed is the Gated-Feedback Cell-Based (GFC) RHBD CML, shown in figure 44. 88 Figure 44. Gated-Feedback Cell-Based BiCMOS CML D latch [55] The OR-gates available in the GDC architecture perform a logical OR operation on identical logic outputs from the pass cell pair and feed the result back to the appropriate inputs of the duplicate storage cell pair. The OR operation helps transmission of the correct logic to the storage cell inputs even when one of the OR gate inputs is in error due to an ion strike. The output of the two-input OR gate changes state only when both the inputs change state from high to low or low to high. If an ion strikes the storage cell node and pulls down its value, this spurious transition does not affect the output of the OR gate [55]. Comparing the percentage increase in the power and area for the above methods with our proposed RHBD method, our design has significantly less area overhead since we did not duplicate MCML stages (35% increase in area). Also the power consumption is less than that of GFC techniques (300% power penalty) and is comparable to the Dual- interleaved method (100% power penalty). In order to clarify the benefit of adding extra NOR logic to control the resistivity of the resistors in the feedback over adding fixed resistors to slow down the feedback, we connected the stages of PMOS transistors in a feedback loop to a voltage source to keep 89 their gate voltages at a constant value of 524 mV, figure 44(a), which is the voltage output of our NOR gate in the case of a strike, to achieve the same minimum Q crit . As seen in figure 45 (b), the output waveform is distorted because the average clock-to-Q delay increases to 81 psec (100% speed penalty). These large PMOS resistors also decrease the MCML output voltage swing, since they filter out some of the signal. This approach is therefore inferior to our proposed solution. MCML Q Data CLK MCML Q Data CLK (a) (b) Figure 45. (a) applying constant voltage to the PMOS gates, (b) clock, MCML fllip-flop input and output waveforms for circuit in (a) Another straightforward solution for making a MCML harder to SEU at constant output voltage swing is to increase its bias current [40]. We doubled the bias current to 400 µA and reran all the experiments. Q crit is shown in table 16. TABLE 16. CRITICAL CHARGE IMPROVEMENT BY INCREASING THE BIAS CURRENT non-Hard MCML I=200 µA Non-Hard MCML I=400 µA Increase in Q crit Q crit (fC) 0.297 0.665 x2.23 The larger bias current requires larger transistors; therefore, the area increases to 27.54 µm 2 which results in an area overhead of 29%. The power consumption increases 90 to 944 µW which is a 99% power penalty. This shows that with almost the same power and area penalties as our proposed design, the hardness is 2.4 times less. Again, this approach is therefore inferior to out proposed solution. In summary we can say that modern communication systems operate at high frequencies, and therefore proper circuits are needed to function at those frequencies without consuming excessive power. MCML is a viable candidate for this operating regime. However, for MCML to enjoy widespread use, its reliability should be at an acceptable level. One of the reliability issues is resistance to SEU, which can change the state of a circuit. Thus, our new SEU-hardened MCML can be employed in these circuits. 91 CHAPTER 6: SINGLE EVENT TRANSIENT IN COMBINATIONAL LOGIC As mentioned in chapter two, a heavy particle or an ion that strikes a sensitive node in a circuit can cause unwanted effects. The two major effects are: single-event upset (SEU) and single-event transient (SET). SEU is mostly a problem in sequential and memory elements since it changes stored values. SET is mainly a problem in combinational logic and appears in the form of a transient voltage pulse. If this SET voltage pulse is not sampled by a sequential element, then it is inconsequential. However, as technology has scaled to deep sub-micron regimes the supply voltage has reduced, implying smaller noise margins. At the same time the operating frequency has increased, increasing the probability of a single event transient (SET) pulse being sampled at the sampling edge of flip-flops. Thus SET voltage pulses are becoming more of a concern for advanced digital designs [11],[28] and [104]. Thus it is essential for deep sub-micron circuits, which are targeted for radiation sensitive environments, to be hard to both SEU and SET effects. In this chapter we briefly review the existing single event transient solutions in combinational logic. Then we introduce our proposed design of a weak-latch [42], which is immune to single-event transients on any of the inputs. 6.1 Existing SET mitigation techniques Different Radiation-Hardening-by-Design (RHBD) methods have been proposed over the past years to mitigate SET effects by sacrificing area, speed and power. RHBD methods use either spatial or temporal redundancies to mitigate SET effects. 92 6.1.1 Spatial redundancy techniques Triple Modular Redundancy (TMR) [81] is one of the simplest and most popular spatial redundancy methods. In this technique three copies of a data path and a majority voter are used, figure 46. The majority voter votes out any error. If TMR is aimed to be used for SEU hardening of sequential elements, then TMR can be applied to only replicate sequential elements (latches and flip-flops) three times, and then a majority vote is used to delete any corrupted value. TMR suffers from significant area and power penalties since three copies of the data path and a majority voter circuitry are needed to vote out incorrect data. On the other hand, TMR offers minimal speed penalty since only the voter circuit affects the critical path for speed. Another benefit of TMR is that it is easy to understand and implement. Input Input Original Circuit Duplicated Circuit Duplicated Circuit Majority Voter Input Output Figure 46. TMR structure Double-Mode-Redundancy (DMR) [52] is another spatial redundancy based SET mitigation method. In DMR two copies of a data path (or two copies of data is stored in two different sequential elements in case of SEU mitigation) and a comparator circuit are needed. The comparator circuit recognizes any discrepancy between the two versions of data. DMR has an advantage of less overhead compared to TMR but still results in more than twice the area and power. DMR can detect the error but is unable to correct it. 93 6.1.2 Temporal redundancy techniques The temporal latch [65] is a well-known temporal redundancy based SET mitigation technique. In temporal latches, three different sampling clock phases are used. Another data voting clock phase is needed to synchronize the three copies of data before the majority voter. Data is sampled and stored at three different instances of time; figure 47. The majority voter is used to vote out any error. The temporal latch suffers from a large delay penalty and complicated clocking scheme in addition to area and power penalties. Figure 47. Temporal latch structure Other suggested methods such as logical masking of SET by combinations of NAND gates, NOR gates and delay lines before the sequential elements [70] or Delay Filtered DICE (DF-DICE) [74] reduce some of the previously mentioned design penalties. In these designs, to filter the SET pulse, data is compared with its delayed version at a sequential element input. The delay lines are chains of inverters. However moving to smaller technologies and having faster gates increases the number of inverters needed to achieve the target delay. This results in larger area and power penalties. Also since radiation strikes a chip fairly uniformly in space and time, the probability of a particle strike at a combinational logic node is proportional to its active area. Therefore a 94 larger number of gates in the SET mitigation circuit increases the probability of an ion strike affecting the mitigation circuit. 6.1.3 Factors affecting SET error rate Both SET pulse width and amplitude are important factors that affect the Soft Error Rate (SER). Only transient pulses with amplitudes larger than the noise margin can propagate; thus, decreasing the noise margin increases the number of propagating SET pulses. Broader pulse widths have a higher probability of being sampled at the windows of vulnerability, the period between set up and hold times, of sequential elements, figure 48. SET pulses that are sampled at sequential elements cause errors. Windows of Vulnerability=Setup Time + Hold Time Input A Input B Clock Output A Output B Windows of Vulnerability=Setup Time + Hold Time Input A Input B Clock Output A Output B Figure 48. Narrower pulses (input A) have less probability of being sampled in the window of vulnerability of a flip-flop as compared to a wider pulse (input B) 6.2 Proposed RHBD technique In order to make a circuit more immune to SET, we suggest the cross coupling of two inverters before the data input of a sequential element, figure 49. 95 SET Pulse Combinational Logic Weak-Latch Figure 49. Schematic of proposed design with a weak-latch before the sequential element These added cross-coupled inverters have the same structure as a latch; however their purpose is not for latching data. Therefore they should be weaker than the combinational logic that drives them. Because of this we refer to them as a weak-latch for the rest of this thesis. To satisfy the condition mentioned earlier we size the weak-latch to be written by combinational logic but not to pass target SET pulses. To do that, we use minimum width transistors while their length is some multiple of the minimum length. This slows down the weak-latch. Therefore the weak-latch can not respond to pulses that are faster than its delay and eliminates them. Delay added to the circuit depends on the length of transistors in the weak-latch. SET pulses faster than the weak-latch delay, are completely deleted, figure 50 (a). For SET pulses for which the weak-latch output does not have sufficient time to settle, their pulse widths are reduced, figure 50 (b). For those pulses for which the weak-latch output does settle, the pulse widths are not changed, figure 50 (c). We must size the weak-latch such that the data signal falls into the third category. To cancel out the inverting effect of the weak-latch and sharpen the rise and fall edges of its output, a minimum size inverter is used after the weak-latch. The difference between this method and adding delay lines to delete SET pulses is that we do not delay the SET pulse and then compare it with the original copy. Here we actually delete the SET pulse and no comparator circuits such as C-element or majority voter are needed. 96 (a) SET to weak-latch Output of weak-latch Flip-Flop input (b) SET to weak-latch Output of weak-latch Flip-Flop input (c) Data to weak-latch Output of weak-latch Flip-Flop input (a) SET to weak-latch Output of weak-latch Flip-Flop input (b) SET to weak-latch Output of weak-latch Flip-Flop input (c) Data to weak-latch Output of weak-latch Flip-Flop input Figure 50. SET rejection and attenuation by weak-latch, (a) SET pulse is rejected (b) SET pulse narrows down and (c) Data signal is delayed and passes through the weak-latch without any pulse narrowing Simulations are conducted in HSPICE using the IBM 65 nm process. A clock rate of 500 MHz and a data rate of 250 MHz are applied. In the test-bench, a chain of minimum size inverters are used as combinational logic. To see the effectiveness of the proposed circuitry we inject a pulse to the input of the inverter chain. This SET pulse can propagate to the input of the weak-latch, and then we monitor the weak-latch output and minimum size inverter output, which is the same as the Flip-Flop input. To find the broadest removable pulse for the chosen size of weak-latch, we sweep the injected pulse width to the point that it passes through the weak-latch and is observed at the flip-flop input. Intuitively by increasing the weak-latch cross-coupled inverters length, larger SET pulse widths can be deleted; however, this capability incurs a larger cost in area, power and delay penalties. For our target SET pulse widths, we ascertained that a length of 1µm for the two NMOS transistors and a length of 400 nm for the two PMOS transistors is needed. While these values are large, since we have only two inverters (2 NMOS and 2 PMOS) the total area overhead is still negligible, compared to other SET mitigation 97 techniques. Results show that for this sizing of the weak-latch, pulse widths of up to 350 ps are completely filtered out from the flip-flop input, figure 51. Time (ns) (c) Flip-Flop Out (a) Input Data to Weak-Latch Voltage (v) (b) Flip-Flop Input SET Pulse Time (ns) (c) Flip-Flop Out (a) Input Data to Weak-Latch Voltage (v) (b) Flip-Flop Input SET Pulse Figure 51. (a) Input to weak-latch, (b) output from minimum size inverter (input to Flip-Flop) and (c) Flip-Flop output The delay added to the system by this weak-latch is 440 ps. Thus, only 90 ps (25.7 %) extra delay is added on top of the delay required to delete the target SET pulse width of 350ps. SETs with pulse widths of up to 500 ps are narrowed down to more than half of their original widths (more than 52%). This pulse width reduction is shown in table 17. TABLE 17. PULSE WIDTH REDUCTION FOR DIFFERENT SET PULSE WIDTHS Pulse width before the weak-latch (ps) Pulse width after the weak- latch (ps) Pulse width reduction (%) 400 88 78 450 150 75 500 240 52 Figure 52 shows the pulse narrowing at the output of the weak-latch. The flip-flop output is also shown for two different cases: One using weak-latch (a), and one without it (b). In case (a) the SET pulse narrows down after passing through the weak-latch; 98 therefore the flip-flop does not sample it at its sampling edge, while in case (b) the original SET pulse is sampled by the flip-flop edge since it has larger pulse width. (b) (a) Input Data Weak- Latch Out Time (ns) Voltage (v) SET Narrowed down SET Error Bit (b) (a) Input Data Weak- Latch Out Time (ns) Voltage (v) SET Narrowed down SET Error Bit Figure 52. Input Data with a transient pulse width of 500 ps; Weak latch output, pulse width is reduced to 240 ps, and Flip-Flop outputs (a) using weak-latch (b) no weak-latch To measure the area overhead, we layout our weak-latch in front of a Dual Interlocked Cell (DICE) latch, and DICE Flip-Flop [20] since the circuit is targeted for use in radiation sensitive environments and should be hard to both SEU and SET. Redundant nodes in a DICE restore corrupted data with correct data in the case of a Single-Event Strike. The DICE design is a well-known sequential element that provides excellent protection against SEU and is used widely in radiation sensitive environments. To remove SET pulses from the clock input and also keep the hold time and set up time untouched, we add the same weak-latch to the clock input. The layout is shown in figure 53. 99 Weak-latch Inverter Latch Weak-latch Inverter Latch Figure 53. Layout of weak-latches in front of a DICE latch. Two weak-latches are added. One for SET filtering from the data and another for filtering SET from clock. The weak-latch insertion adds 57.48% area penalty to the DICE latch and only 28.7% to the DICE Flip-Flop. Area overheads are shown in Table 18. TABLE 18. AREA OVERHEAD FOR THE WEAK-LATCH No Weak-Latch (µm 2 ) With Weak-Latch (µm 2 ) Area Overhead (%) DICE Latch 20.37 32.08 57.48 DICE Flip-Flop 40.75 52.48 28.7 We compare our proposed weak-latch with the case when a chain of inverters is used to remove the same SET pulse width. For this method, 6 triple length transistors and a C-element are needed to filter out SET pulses (350 ps). We repeat our simulations for this case. An area of 51.34 µm 2 results for a DICE latch. This translates to an area overhead of 151.9 % while the delay to delete the 350 ps is 490 ps. This shows that the area and delay penalties are 60% and 11.3 %, respectively, more than our proposed weak- latch. These overheads are summarized in table 19. 100 TABLE 19. AREA AND DELAY OVERHEADS COMPARISON FOR CHAIN OF INVERTERS VERSUS WEAK-LATCH DICE Latch with Weak-Latch DICE Latch with Delay Filtering Increase (%) Area (µm 2 ) 32.08 51.34 60 Delay (ps) 440 490 11.3 As we mentioned earlier, increasing the active area (source and drain areas) in a SET mitigation circuit increases the probability of the mitigation circuit itself getting hit by an ion strike. We compare the total drain area (the most sensitive area to a Single Strike) of the weak-latch approach with the total drain area of a delay line and a C- element. The total drain area for our proposed design is 0.216 µm 2 , and for the delay line and its filter is 0.648 µm 2 . This represents a reduction of 66.67% in total drain area. The same SET attenuation and rejection can be achieved by adding a low pass filter to the input of a sequential element. A first order low pass filter includes a resistor in series with a capacitor. In order to achieve a 350 ps pulse rejection, and assuming a resistance of 1 kohm, we need a capacitor of 81 fF or more. The total area of this implementation and a DICE latch is 48.43 µm 2 . Thus, the area penalty for this resistor and capacitor is 137%. This shows that the weak-latch is a better candidate than a low pass filter in terms of area overhead penalties. To study the effect of scaling on the weak-latch SET mitigation functionality and efficiency, we repeat our simulation in 90 nm technology. We can delete pulse widths of up to 350 ps with a time overhead of 448 ps, which translates to 28 % more delay than the deleted pulse width. The area overhead is 58 % for the DICE latch. This shows that scaling does not affect the functionality and efficiency of the weak-latch. 101 For different radiation environments, the LET ranges that different energetic particles can produce are known. For example, in the Van Allen belt, energetic particles can generate LETs in the range of 10-100 MeV.cm 2 /mg. Therefore, to estimate the hardness of our proposed design for different radiation environments we need to ascertain the SET pulse widths for different LET values. To measure the SET pulse widths we conducted 2-D TCAD mixed-mode simulations in an n-well process. Our device was calibrated to match electrical characteristics (Id-Vd and Id-Vg curves) obtained from the IBM 65-nm PDK (Process Design Kit). We developed our device with Synopsys Structure Editor and simulated it in Sdevice simulator. A cross-section of our NFET device is shown in figure 54. The NFET was a TCAD structure while we used 65-nm commercial compact models for the rest of our circuit. We used our TCAD device as the NMOS of the second inverter in a chain of 4 inverters. In our TCAD simulations we used heavy ions with LETs in the range of 1-20 MeV.cm 2 /mg. gnd Input Ion strike Inverter chain vdd Well Contact Source Drain gnd Input Ion strike Inverter chain vdd Well Contact Source Drain Figure 54. TCAD NFET Structure The measured SET pulse widths for different LETs are shown in table 20. For heavy ions with LETs of smaller than 14 MeV.cm 2 /mg the resulting SET pulse width is smaller than 350 ps and therefore will be completely filtered out from the sequential 102 element input using the weak-latch approach described above. For ions with LETs of larger than 14 MeV.cm 2 /mg up to 20 MeV.cm 2 /mg, a resulting pulse width will be narrowed down to more than half of its original width. For heavy ions with LETs of larger than 20 MeV.cm 2 /mg, the reduction in pulse width will be reduced [42]. TABLE 20. SET PULSE WIDTHS FOR HEAVY IONS WITH DIFFERENT LETS LET (MeV.cm 2 /mg) Pulse width (ps) 10 270 12 307 14 360 15 370 18 410 20 510 In summary we can say that decreasing supply voltage while increasing clock frequency with technology scaling make electronic circuits more sensitive to SET pulses. We then proposed the use of a pair of cross-coupled inverters at the data input of sequential elements to mitigate this SET problem. This acts as a weak-latch and slows down the circuit. SET pulses smaller than the added delay will be filtered out and ones close to this delay decreased. The pulse width of deleted SETs depends on the size of the transistors in the weak-latch. The larger the length of the transistors the broader the pulses that can be deleted while the area, speed and power penalties will increase accordingly. 103 CHAPTER 7: RADIATION EFFECTS ON ELECTRONICS IN ALIGNED CARBON NANOTUBE TECHNOLOGY (RADCNT) CMOS scaling below the 100 nm feature size is increasingly challenging the reliable operation of commercial-process-based electronics in space and strategic radiation environments. However, CMOS reliability issues are not limited to radiation environments as scaling continues to around a 16-nm gate length by 2016, as predicted by the 2009 International Technology Roadmap for Semiconductors (ITRS) [48]. It is anticipated that beyond this point, CMOS scaling will likely become very difficult due to short channel effects (SCE), high power dissipation and low drive current due to scaling of size as well as reduced mobility and reduced electron count [58], and [95]. Concurrently, we are seeing the emergence of carbon-nanotube-based technologies that are in some ways already exhibiting properties competing with the most advanced CMOS processes [63], and [89]. Single-walled carbon nanotubes (SWNTs) have significant properties that make them ideal in a wide range of applications. Semi-conducting carbon nanotubes have ultra high electron and hole mobilities (~ 10,000 cm 2 /Vs) [106] that make them very competitive for logic and memory devices. In addition, carbon nanotubes can work as ballistic conductors in the deep submicron regime, and such ballistic transistors can form the backbone for future dissipation-less nano-electronics [82]. Furthermore, metal carbon nanotubes can sustain high current densities (~ 10 9 ampere/cm 2 ) [93] without the problem 104 of electro- migration, thus making them ideal building blocks as interconnects for integrated circuits. In consideration of these developments, we propose the exploration of basic mechanisms and phenomena from ionizing radiation effects on field-effect transistors and circuits, based on self-aligned carbon nanotube technology. TCAD modeling and simulation of CNTs with basic device fabrication is used for the purpose of establishing a fundamental understanding of underlying radiation mechanisms and their effects on CNT-based basic FET structures, logic gates, and ultimately simple integrated circuits. 7.1 Brief history of carbon nanotubes Preparation of very small diameter (less than 10 nm) carbon filaments were started in the 1970’s and 1980’s through the synthesis of vapor grown carbon fibers [31]. The discovery of fullerenes by Kroto, Smalley, Curl, and coworkers in 1985 at Rice University [56], was a direct motivation to the systematic study of carbon filaments of very small diameters. Five years later, the successful synthesis of C 60 in bulk quantity by Wolfgang Kratschmer and Donald Huffman enabled the opportunity to study the properties of this new form of carbon [54]. However, the first detailed systematic studies of such thin filaments were reported in 1991 by Iijima of the NEC laboratory in Tsukuba, Japan [47]. Around the same time in 1992, Russia also reported the discovery of carbon nanotubes and nanotube bundles [33]. In 1993, single walled carbon nanotubes were synthesized successfully [31], and [33]. 105 7.2 Structure of carbon nanotube Carbon Nanotubes are seamless cylinders derived from the honeycomb lattice [31]. This lattice represents a single atomic layer of crystalline graphite, called a graphene sheet, figure 55. Ө Ө Figure 55. Carbon Nanotube Lattice structure A single-walled carbon nanotube structure is specified in terms of its 1D unit cell, defined by the vectors C h and T in figure 55. The circumference of any carbon nanotube is expressed in terms of the chiral vector C h =na1+ma2. This vector connects the two crystallographically equivalent sites on a 2D graphene sheet. The integer n and m denote the number of unit vectors along two directions in the honeycomb crystal lattice of graphene. T denotes the tube axis while a1 and a2 are the unit vectors of graphene in real space. On figure 55, Ө is the chiral angle between the chiral vector C h and the zigzag direction, which Ө is equal to 0. 106 When a graphene sheet is rolled up into a cylinder, three different nanotube structures can be generated: Zigzag, armchair and chiral nanotubes. If m=0 or n=0 or Ө=0, the nanotubes are called zigzag nanotubes, figure 56 (a). If Ө=30 o or m=n, the nanotubes are called armchair nanotubes, figure 56 (b). Otherwise, they are called chiral. For chiral nanotubes, chiral angle is 0<Ө<30 o , figure 56 (c). (a) (b) (c) Figure 56. Different single walled carbon nanotube : (a)zigzag, (b) armchair, and (c) chiral [90] 107 The nanotube diameter is calculated from its (n,m) indices as shown below [33]: 2 2 ( ) 2 a d n mn m π = + + , where a=0.246 nm. The chiral angle Ө is given by [33]: 1 3 tan (2 ) n m n θ −   =   +   , From the above formula for chiral angle, it follows that for Ө=30, n=m and for Ө=60 m=0 armchair and zigzag nanotubes result, respectively. As seen above, the properties of single walled carbon nanotubes change significantly with the (n,m) values, and this dependence is non-monotonous [31], and [33]. Single-walled carbon nanotubes are the simplest form of carbon nanotubes. The other nanotube varieties include multi-walled carbon nanotubes, figure 57 (a), nanotube bundles or ropes, figure 57 (b), inter-tube junctions, nanotori, coiled nanotubes, etc [33]. 108 (a) (b) Figure 57. Different form of carbon nanotubes: (a) Multi-walled, and (b) bundle of nanotubes [33] 7.3 Electronic structure and properties Special electronic structures of carbon nanotubes give them unique transport and optical properties. A single carbon nanotube can be metallic, semi-metallic or semiconducting, depending on its diameter and chirality [31]. It is established that if n=m 109 carbon nanotubes are metals, if n-m is a multiple of 3 the nanotubes are small gap semiconductors with band gap energy proportional to 2 1 d , while d is a nanotube diameter. In all other cases, nanotubes are semiconductors with an energy gap inversely proportional to 1 d [24]. 7.4 Synthesis There are three major techniques to produce carbon nanotubes: arc discharge, laser ablation, and chemical vapor disposition. In all the mentioned techniques, the generation of free carbon atoms and the precipitation of dissolved carbon from catalyst particles are involved [31]. Generally the formation of carbon nanotubes consists of three steps: the first step is the formation of metal catalyst particles. In the second step, under high temperature, free carbon atoms diffuse into the surface of the catalyst particles and form metastable carbide particles. The last step is the growth of rod-shape carbon tubes out of the particle, figure 58 [60]. Figure 58. Growth mechanism:(a) root growth, and (b) tip growth [60] 110 In the arc discharge method, carbon vapor is generated by an arc discharge between two carbon electrodes with a catalyst. Carbon nanotubes are formed from the accumulation of carbon vapor. Single-walled and multi-walled carbon nanotubes with different diameters are obtained by adjusting the pressure and catalyst carefully [60]. In the laser ablation method a high-power laser beam impinges on a graphite target sitting in a furnace at high temperature. Carbon nanotubes are found at the cold end [60]. Another widely used synthesis techniques is chemical vapor deposition (CVD), which is suitable to make on-chip nanotubes. CVD provides a convenient way for further device fabrication. The synthesis is achieved by breaking gaseous carbon molecules, such as methane, carbon monoxide and acetylene, into reactive atomic carbon in a high temperature furnace and sometime assisted by plasma to enhance the generation of atomic carbon. Then the carbon diffuses toward the substrate coated with catalyst particles. Under the proper growth conditions, carbon nanotubes will be formed following the mechanism described before [60]. 7.5 Aligned single-walled carbon nanotube Aligned nanotubes show significant advantages over randomly grown nanotubes, since the manipulation and integration of aligned nanotubes are easier for device applications. The complete wafer process including synthesis and transfer printing of aligned SWCNT and device fabrication is illustrated in figure 59 [89]. This figure shows the required steps of CNT synthesis on 4-inch quartz and sapphire wafers. Uniformly aligned SWNT arrays, figure 59 c, are achieved through meticulous temperature control, figure 59 a and b. The CNT arrays are moved to a Si/SiO 2 substrate through successive 111 gold film deposition, CNTs peel-off, transfer and gold etching steps (figure 59 d, e and f). These steps leave a nice array of massively aligned SWNTs on the target substrate, figure 59 g. Standard silicon CMOS fabrication technology and steps such as projection photolithography using a stepper with 0.5 µm resolution for sub-micrometer device patterning, metal deposition for electrodes, and high k dielectric (HfO2 or Al2O3) deposition for gate dielectric, figure 59 h, are used in the transferred nanotube fabrication process. Figure 59 i shows the photo images of nanotubes devices, including back-gated transistors, top-gated transistors, CMOS inverters, and CMOS NOR and NAND logic gates. Figure 60 shows a schematic diagram, SEM image, and electrical characteristics of back-gated nanotube devices. The SEM image, figure 60 b, is a typical sub-micrometer channel device with two to three tubes per micrometer. Figure 60 c shows the drain- source currents versus gate voltage for various channel lengths. To improve the I on /I off ratio, metallic and high-leakage semiconducting nanotubes should be removed, as is typically done by controlled electrical breakdown, figure 60 e. Figure 60 f shows the I ds - V g and I ds -V ds after the electrical breakdown. 112 Figure 59. Wafer-scale aligned nanotube fabrication. a, b) temperature flowcharts for annealing and nanotube growth on sapphire and quartz wafer. c) schematic diagram and photograph of aligned nanotubes on a 4 in. quartz wafer. Inset shows SEM image of aligned nanotubes. d-h) schematic diagrams and photographs of the transfer procedure of nanotube arrays. i) photo images of nanotube devices and circuits built on a 4 in. Si/SiO 2 wafer: 1) back-gated transistor; 2) top-gated transistor; 3) CMOS inverter; 4) NOR logic gate; 5) NAND logic gate. [89] 113 Figure 60. a) Schematic of a back-gated transistor build on transferred nanotubes, b) SEM image of transistor, c) characteristics of transistors for channel length of 0.5, 0.75, 1, 2, 5, and 20 µm and channel width of 100 µm, d) normalized on and off current densities and transconductance (gm) derived from c, e) electrical breakdown study of the transistors, and f) Ids-Vg and Ids-Vds curves of the transistor in (e) after three round of electrical breakdown [89]. 7.6 Radiation response of SWNTs Being able to fabricate a large number of transistors and logic gates out of SWNTs show the tremendous evolution in CNTs. However, still very little is known at this point about the radiation response of CNT FETs. In this section laser measurement and TCAD device simulations are used to understand and predict the behavior of SWNTs in radiation sensitive environments. 114 7.6.1 Total ionization dose Total Ionization Dose (TID) testing was done by Michael Fritze and his colleagues at ISI/USC [35], using a Co 60 radiation source on aligned SWNT FETs, fabricated based on the Rye et al method [89] at USC, in NRL facilities. TID testing has been repeated for 10, 100 and 1000 Krad. The Id-Vg curves for different radiation doses for two different SWCNT devices on the same chip are shown in figure 61 a and b [35]. As seen in the graphs for different radiation doses, when the gate voltage is swept form +5 volts to -5 volts and then -5 to +5 volts, the threshold shift is negligible. This shows that SWNT FETs are not sensitive to TID effects. However, a significant hysteresis effect, which is not related to the radiation exposure, is seen. This hysteresis effect needs to be eliminated from SWNT FETs but is out of scope of this research. 115 (a) (b) Figure 61. Total dose radiation data for two different SWNT devices on one chip: a and b [35] 7.6.2 Single event effect If a single heavy particle or ion hits a SWNT, the strike may change the SWNT’s diameter, and this change may cause changes in the electrical properties of the SWNT device. In order to investigate these electrical property characteristics, 3 dimensional 116 TCAD simulations are used. The SWNT model and TCAD software were provided by Silvaco and match the electrical characteristics of the SWNT fabricated by Ryu et al [89]. Figure 62 shows the 3D back-gated SWNT model. In order to study the effect of diameter change in SWNT devices, we first start with changing the diameter of all three tubes in a representative FET channel to 20% larger and 20% smaller than the base case. Figure 63 a-d shows drain current (Id) versus gate voltage (Vg) for different drain voltages (Vd) of 1, 0.8, 0.6 and 0.4 and varying CNT tube diameters. As seen in the figures, by increasing the diameter of all three tubes, the threshold voltage decreases while the drain current increases. When the diameters of all three tubes decrease, the threshold voltage increases while the current decreases. This agrees with the theory that the CNT band gap (Eg) is inversely proportional to its diameter. Figure 62. 3-D TCAD structure of back-gated SWNT, provided by Silvaco 117 (a) (b) Figure 63. Drain current versus gate voltage from 3 D TCAD simulations for SWNT with tube diameter 20% larger and smaller than the base case for drain voltage of (a) 1, (b) 0.8, (c) 0.6, and (d) 0.4 volts 118 (c) (d) Figure 63. Continued 119 However, a single ion particle may hit only one tube and just affect that single hit SWNT tube diameter. We repeated our simulation for the case when only a single tube diameter is changed among all three. Figure 64 compares the Id versus Vg curves for when only one tube’s diameter is changed by 20% and 10% with respect to the base case (when all three have the same diameter). As seen from the figure 64, the threshold shift is negligible even for 20% change in diameter, and the current increase is also not significant. 120 (a) (b) Figure 64. Drain current versus gate voltage for drain voltages of (a) 1, (b) 0.8, (c) 0.6, and (d) 0.4 volts when one out of three tubes diameter is 10% and 20% larger or smaller than the base case 121 (c) (d) Figure 64. Continued 122 Another important point that needs to be considered when interpreting the above data is that the tube’s diameter has been changed to more than 10% of its original diameter all along the tube length in our simulations. This is the worst case scenario as most probably the ion hit will change the diameter just at the hit point, which will have less effect on the threshold voltage shift and Id. Based on what we see from both measurement and simulations, SWNT devices are quite resistant to both TID and heavy particle hits. Therefore, SWNT devices may be the best radiation hard devices for radiation sensitive environments due to their inherent radiation resilience. 123 CHAPTER 8: CONCLUSION This dissertation addresses the issues of single-event effects (including charge sharing, single-event upsets and single-event transients) in deep sub-micron CMOS technologies. Technology scaling to the deep sub-micron regime has exacerbated single- event effects in electronic circuits [1]. Charge sharing among adjacent nodes in deep sub- micron technologies has lessened the effectiveness of already existing redundancy based radiation hardening techniques such as Dual-Interlock Cell (DICE) [8]. This amplifies the necessity of an easy, fast and accurate circuit model to predict the sensitivities of circuit nodes to charge sharing. The contribution of this dissertation includes suggesting a semi- empirical circuit model to assess the charge sharing problem at early stages of a design process. This is a fast and easy to use circuit model that significantly reduces the number of long and tedious device simulations typically used. The proposed model is compared with data obtained from mixed-mode 2-D TCAD device simulations with better than 73% accuracy. After quantifying the severity of the charge sharing problem in circuits, proper mitigation techniques can be applied to reduce the problem. This dissertation proposes a layout technique to reduce charge sharing among sensitive nodes for Double-Interlock Cell (DICE) sequential elements, which is a popular single-event upset hard sequential element [8]. Also the effectiveness of different charge sharing mitigation techniques is compared using mixed-mode 2-D TCAD device simulations, and Deep Trench Isolation (DTI) is proposed as an effective charge sharing reduction method. The single-event upset sensitivity of MOS Current Mode Logic (MCML) circuit topology, which has better immunity to the charge sharing effect due to removal of PFET devices, is studied, and a Radiation-Hardening-by-Design (RHBD) technique is introduced. Single-event 124 transient is another growing single-event effect problem in deep sub-micron technologies [28], [13], [104], due to smaller noise margins and higher operating frequencies. This problem is also addressed in this dissertation by proposing an RHBD technique with small area and delay penalties to reduce single-event transients in deep sub-micron technologies. The scaling of CMOS technology to small nano-meter feature sizes (16 nm gate length) causes reliability issues that are not limited to radiation effects. Some of these reliability issues are anticipated to be short channel effects (SCE), high power dissipation and low drive current due to scaling of size as well as reduced mobility and reduced electron count [58], and [95]. Therefore, carbon-nanotube-based technologies have emerged and are already showing properties competing with the most advanced CMOS processes [63], and [89]. In consideration of these developments, the basic exploration of carbon nanotube responses to radiation effects is studied in this piece of work. 3-D TCAD simulations are used to study the possible effects of radiation particles on CNT devices. Based on this study, carbon nanotube based transistors show very good tolerance to total ionization dose and single-event effects. 8.1 Future work As mentioned in this dissertation, charge sharing is a growing problem for sub- micron technologies and gets more severe as feature sizes become smaller. Therefore the charge sharing issue needs continued consideration in order to have reliable circuits for radiation sensitive applications. This research proposed a semi-empirical model that minimizes the number of device simulations and its related data. However, development 125 of a circuit model that does not rely on any data from device simulations is still a challenge and should be pursued in further research. Carbon nanotubes are attracting more attention due to their unique properties that can compensate for silicon-based CMOS technology, which is quickly approaching physical limits. The behavior of carbon nanotubes in radiation sensitive environment is a fairly new subject. In this dissertation, the radiation effects on Single Walled Carbon Nanotubes (SWNT) transistors have been studied. A deep study and analysis of single- event mechanisms and responses for different types of carbon nanotubes, such as Multi- Walled carbon nanotubes, is still a research area to be explored. 126 REFERENCES [1] Actel, (2002). Effects of Neutrons on programmable logic, a white paper. Technical report Actel corporation. [2] Alexander, D. R. (1996). Design issues for radiation tolerant microcircuits for space. NSREC conference. [3] Alioto, M., & Palumbo, G. (2005). Model and design of bipolar and MOS current mode logic. Kluwer Academic Publishers. [4] Allstot, D. J., Liang, G., & Yang, H. C. (1991). Current-mode logic techniques for CMOS mixed-mode ASICs. IEEE Integrated Circuits Conference, 49, 25.2/1-25.2/4. [5] Amusan, O. A., Casey, M. C., Bhuva, B. L., McMorrow, D., Gadlage, M. J., Melinger, J. S., & Massengill, L. W.(2009). Laser Verificaiton of charge sharing in a 90 nm bulk CMOS process”, IEEE Transactions on Nuclear Science, 56, 3065-3070. [6] Amusan, O. A., Massengill, L. W., Baze, M. P., Bhuva, B. L., Witulski, A. F., Black, J. D., et all (2008). Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process. IEEE Transactions on Device and Materials Reliability, 9, 311-317. [7] Amusan, O. A., Massengill, L. W., Baze, M. P., Bhuva, B. L., Witulski, A. F., DasGupta, S., Sternberg, A. L., Fleming, P. R., Heath, C. C., & Alles, M. L. (2007). Directional sensitivity of single event upsets in a 90 nm CMOS due to charge sharing. IEEE Transactions on Nuclear Science, 54, 2584-2589. [8] Amusan, O. A., Massengill, L. W., Baze, M. P., Sternberg, A. L., Witulski, A. F., Bhuva, B. L., & Black, J. D. (2008).Signle event upset in deep-submicrometer technologies due to charge sharing. IEEE Transactions on Nuclear Science, 8, 3. [9] Amusan, O. A., Witulski, A. F., Massengill, L. W., Bhuva, B. L., Fleming, P. R., Alles, M. L., Sternberg, A. L., Black, J. D., & Schrimpf, R. D. (2006). Charge collection and charge sharing in a 130 nm CMOS technology. IEEE Transactions on Nucearl Science, 53, 3253- 3258. [10] Baggio, J., Ferlet-Cavrois, V., Duarte, H., & FLament, O. (2004). Analysis of proton/neturon SEU sensitivity of commercial SRAMs-application to the terrestrial environment test method. IEEE Transactions on Nuclear Science, 51, 3420–3426. [11] Baumann, R. C. (2005). Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device Materials and Reliability, 5, 305–316. 127 [12] Baumann, R. C. (2001). Soft errors in advanced semiconductor devices – Part 1: The three radiation sources. IEEE Transactions on Device and Materials Reliability , 1, 17-22. [13] Baumann, R. C. (2005). Soft errors in advanced computer systems,” IEEE Design Test Computers, 22, 258-266, 2005. [14] Benedetto, J., Salomonson-Begay, C., & McGuirk, P. (2005). Single event upset hardening limitations in deep sub-micron digital designs due to critical node crowding. Hardened Electronics Radiation Technology (HEART). [15] Bessot, D., & Velazco, R. (1993). Design of SEU-hardened CMOS memory cells: the HIT cell. European Conference on Radiation and its Effects on Components and Systems (RADECS), 563 – 570. [16] Bhattacharya, S., Bnerjee, S., Lee, J., Tasch, A., & Chatterjee, A. (1991). The impact of trench isolation on latch-up immunity in bulk nonepitaxial CMOS. IEEE Electron Device Letters, 12, 77-79. [17] Binder, D., Smith, E.C., & Holman, A.B. (1975). Satellite anomalies from galactic cosmic rays. IEEE Transactions on Nuclear Science, 22, 2675-2680. [18] Bruma, S. (2003). Impact of on-chip process variations on MCML performance. IEEE International Systems-on-Chip Conference, 135-140. [19] Burnett, D., Lage, C. & Bormann, A. (1993). Soft-error rate improvement in advanced BiCMOS SRAMs. IEEE International Reliability Physics Symposium, 156-160. [20] Calin, T., Nicolaidis, M. & Velazco, R. (1996). Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Transactions on Nuclear Science, 43, 2874-2878. [21] Cataldo, A. (2001). SRAM soft errors cause hard network problems. EE Times. [22] Cochran, D., Buchner, S., Chen, D., Kim, H., LaBel, K., Oldham, T., Campola, M., O’Bryan, M., Ladbury, R., Marshall, C., Sanders, A., & Xapsos, M., (2010). Total ionizing dose and displacement damage compendium of candidate spacecraft electronics for NASA. IEEE Radiation Effect Data Workshop. [23] Comer., D. T., (1994). Introduction to Mixed Signal VLSI. Array Publishing Company, NY. [24] Crespi, V. H., & Cohen, M. L. (1997). In situ band gap engineering of carbon nanotubes, Physical Review Letters, 79, 2093-2096. [25] DasGupta, S., Witulski, A.F., Bhuva, B.L., Alles, M.L., Reed, R.A., Amusan, O. A., Ahlbin, J. R., Schrimpf, R. D., & Massengill, L. W. (2007). Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS. IEEE Transactions on Nuclear Science, 54, 2047-2412. 128 [26] Deracobian, N., Vardanian, V. & Zorian, Y. (2004). Embedded memory reliability: the SER challenge. IEEE International Workshop on Memory Technology, Design and Testing, 104– 110. [27] Dodd, P. E., Massengill, L. W. (2003). Basic mechanisms and modeling of single-evnet upset in didgital microelectronics, IEEE Transactions on Nuclear Science, 50, 583-602. [28] Dodd, P. E. (2005). Physics-based simulation of single-event effects. IEEE Transactions on Device and Materials Reliability, 5, 343–357. [29] Dodd, P. E., Sexton, (1995). Critical charge concepts for CMOS SRAMs, IEEE Transactions on Nuclear Science, 42, 1764 – 1771. [30] Dodd, P. E., Sexton, F. W., Hash, G. L., Shaneyfelt, M. R., Draper, B.L., Farino, A.J. & Flores, R.S. (1996). Impact of technology trends on SEU in CMOS SRAMs. IEEE Transactions on Nuclear Science , 43, 2797-2804. [31] Dresselhaus, M. S., Dresselhaus, G. , & Avouris, P. (2001). Carbon Nanotubes: synthesis, structure, properties, and applications, Springer. [32] EIA/JEDEC STANDARD, (1996). Test procedures for the measurement of single-event effects in semiconductor devices from heavy ion irradiation. Electron industries association, Engineering Department, Arlington, VA. [33] Fiorito, S. (2008). Carbon Nanotubes: Angeles or Demons,” Pan Stanford Publishing. [34] Francis, A. M., Dimitrov, D., Kauppila, J. , Sternberg, A., Alles, M., Holmes, J. & Mantooth, H. A. (2009). Significance of strike model in circuit-level prediction of charge sharing upsets. IEEE Transactions on Nuclear science, 56, 3109-3114. [35] Fritze, M. (2011). ISI Internal peresntation. [36] Fu, J. S., Axness, C. L., and Weaver, H. T. (1985). Memory SEU simulations using 2-D transport calculations. IEEE Electron Device Letters, 6, 422-424. [37] Fu, S. W., Mohsen, A. M., May, T. C. (1985). Alpha particle-induced charge collection measurements and the effectiveness of a novel p-well protec- tion barrier on VLSI memories. IEEE Transactions on Electronic Devices, 32, 49-54. [38] Haghi, M. & Draper, J. (2010). A Single-Event Upset Hardening Technique for High Speed MOS Current Mode Logic. ISCAS Proceeding, 4137-4140. [39] Haghi, M., & Draper, J. (2011). Comparison of Charge Sharing Reduction in Deep Sub- micron CMOS Processes. MWSCAS Proceeding. 129 [40] Haghi, M. & Draper, J. (2009). The Effect of Design Parameters on Single-Event Upset Sensitivity of MOS Current Mode Logic. GLSVLSI, Proceeding, 233-238. [41] Haghi, M. & Draper, J. (2009). The 90 nm Double-DICE Storage Element to Reduce Single- Event Upsets. MWSCAS Proceeding, 463-466. [42] Haghi, M., & Draper, J. (2011). Single-event transient mitigation in sub-micron combinational circuits. MWSCAS Proceedings. [43] Hayden, J. D., Taft, R. C., Kenkare, P., Mazur, C., Gunderson, C., Nguyen, B. Y., Woo, M., Lage, C., Roman, B. J., Radhakrishna, S., Subrah-Manyan, R., Sitaram, A. R., Pelley, P., Lin, J. H., Kemp, K., & Kirsch, H. (1994). A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM. IEEE Transactions on Electron Devices, 41, 2318-2325. [44] Hentschke, R., Marques, F., Lima, F., Carro, L., Susin, A., & Reis, R. (2002). Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy. Symposium on Integrated Circuits and Systems Design, 95 – 100. [45] Hughes, H. L., & Benedetto, J. M. (2003). Radiation effects and hardening of MOS technology: devices and circuits. IEEE Transactions on Nuclear Science, 50, 500-521. [46] Hung, C. M., Floyd, B. A., Park, N., O., K. K. (2001). Fully Integrated 5.35-GHz CMOS VCOs and Prescalers. IEEE Transactions on Microwave Theory and Techniques, 49, 17-22. [47] Iijima, S. (1991). Helical microtubules of graphitic carbon. Nature, 354, 56-58. [48] International Technology Road map for Semiconductors, 2009 edition. Available at http://www.itrs.net [49] Kang, S., & Leblebici, Y. (2004). CMOS digital integrated circuits analysis and design. McGrawHill. [50] Karnik, T., & Hazucha, P. (2004). Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Transaction on Dependable and Secure Computing, 128- 143. [51] Kauppila, J. S., Sternberg, A. L., Alles, M. L., Francis, A. M., Holmes, J., Amusan, O. A., & Massengill, L. W. (2009). A bias-dependent single-event compact model implemented into BSIM4 and a 90 nm CMOS process design kit. IEEE Transactions on Nuclear Science, 56, 3152-3157. [52] Kim, J. E., Lin, J., McMurchie, L., & Sechen, C. (2005). Mitigation of single and multiple- cycle-duration SETs using Double-Mode-Redundancy (DMR) in Time. IEEE Aerospace Conference, 1-10. 130 [53] Kodeti, N. M. (2009). White paper on silicon on insulator (SOI) implementation. www.infotech-enterprises.com. [54] Kratschmer, W., Lamb, L. D., Fostiropoulos, K., & Huffman, D. R. (1990). Solid C 60 : a new form of carbon. Nature, 347, 354-358. [55] Krithivasan, Marshall, P. W., Nayeem, M., Sutton, A. K., Kuo, W., Haugerud, B. M., Najafzadeh, L., Cressler, J. D., Carts, M. A., Marshall, C. J., Hansen, D. L., Jobe, K. M., Mckay, A. L., Niu, G., Reed, R., Randall, B. A., Burfield, C. A., Lindberg, M. D., Gilbert, B. K., & Daniel, E. S. (2006). Application of RHBD Techniques to SEU Hardening of Third – Generation SiGe HBT Logic Circuits. IEEE Transactions on Nuclear Science, 53, 3400-3407. [56] Kroto, H. W., Heath, J. R., O’Brien, S. C., Curl, R. F., & Smalley, R. E. (1985). C 60 : Buckminsterfullerene. Nature, 318, 162-163. [57] Lawrence, R. K., & Kelly, A. T. (2008). Single event effect induced multiple-cell upsets in a commercial 90 nm CMOS digital technology. IEEE Transactions on Nuclear Science, 55, 3367-3374. [58] Lee, K., Nam, I., Kwon, I., Gil, J., Han, K., Park, S., & Seo, B. (2005). The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application. IEEE Transactions on Electron Devices, 52, 1415-1422. [59] Li, L., Raghavendran, S., & Comer, D. T.(2005). CMOS Current Mode Logic gates for high- speed applications.12 th NASA Symposium on VLSI Design. [60] Liu, X. (2006). Synthesis, devices and applications of carbon nanotubes. PhD Dissertation, University of Southern California. [61] Lum, G. (2004). Hardness assurance for space systems. NSREC Short Course. [62] Maiz, J., Hareland, S., Zhang, K., & Armstrong, P. (2003). Characterization of multi-bit soft error events in advanced SRAMs. IEEE International Electron Devices Meeting (IEDM) Technical Digest, 21.4.1–21.4.4. [63] Martel, R., Drycke, V., Appenzeller, J., Wind, S., & Avouris, Ph. (2002). Carbon nanotube field-effect transistors and logic circuits. Design Automation Conference, 94-98. [64] Mavis, D. G., & Eaton, P. H. (2007). SEU and SET modeling and mitigation in deep submicron technologies. IEEE International Symposium on Reliability Physics, 293-305. [65] Mavis, D. G., & Eaton, P. H. (2002). Soft error rate mitigation techniques for modern microcircuits. IEEE International Symposyium on Reliability Physics, 216-225. [66] May, T. C., & Woods, M. H. (1979). Alpha-particle-induced soft errors in dynamic memories. IEEE Transactions on Electron. Devices, 26, 2-9. 131 [67] Meaney, P. J., Swaney, S. B., Sanda, P. N., & Spainhower, L. (2005). IBM z990 soft error detection and recovery. IEEE Transactions on Device and Materials Reliability, 5, 419–427. [68] Mitra, S., Seifert, N., Zhang, M., Shi, Q., & Kim, K.S. (2005). Robust system design with built-in soft-error resilience. Journal of Computer, 38, 43-52. [69] Mizuno, M., Yamashina, M., Furuta, K., Igura, H., Abiko, H., Okabe, K., Ono, A., & Yamada, H. (1996). A GHz MOS, Adaptive Pipeline Technique Using MOS Current-Mode Logic. IEEE Journal of Solid-State Circuits, 31, 784-791. [70] Mongkolkachit, P., & Bhuva, B. (2003). Design technique for mitigation of alpha-particle- induced single-event transients in combinational logic. IEEE Transactions on Device and Materials Reliability, 3, 89-92. [71] Musicer, J., & Rabaey, J. (2000). MOS Current Mode Logic for low power low noise CORDIC computation and mixed-signal environments. International Symposium on Low Power Electronics and Design, 102-107. [72] NASA/GSFC Radiation Effects & Analysis Home Page, www.radhome.gsfc.nasa.gov [73] Naseer, R., Boulghassoul, Y., Draper, J., DasGupta, S., & Witulski, A. (2007). Critical charge characterization for soft error rate modeling in 90nm SRAM. International Symposium on Circuits and Systems (ISCAS), 28-30. [74] Naseer, R., & Draper, J. (2005). The DF-DICE storage element for immunity to soft errors. Midwest Symposium on Circuits and Systems, 303 – 306. [75] Naseer, R. (2008). A framwork for soft error tolerant SRAM design. PhD Dissertation. [76] Neamen, D. A. (2003). Semiconductor physics and devices basic principles. McGrawHill. [77] Niu, G., Krithivasan, R., Cressler, J. D., Riggs, P. A., Randall, B. A., Marshall, P. W., Reed, R. A., & Gilbert, B. (2002). A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuits architectures. IEEE Transactions on Nuclear Science, 49, 3107-3114. [78] Normand, E. (1996). Single event upset at ground level. IEEE Transactions on Nuclear Science, 43, 2742-2750. [79] Olson, B. D., Ball, D. R., Warren, K. M., Massengill, L. W., Haddad, N. F., Doyle, S. E., & McMorrow, D. (2005). Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design. IEEE Transaction on Nuclear Science, 52, 2132-2136. 132 [80] Pellish, J. A., Reed, R. A., Schrimpf, R. D., Alles, M. L., Varadharajaperumal, M., Niu, G., Sutton, A. K., Diestelhorst, R. M., Espinel, G., Krithivasan, R., Comeau, J. P., Cressler, J. D. , Vizkelethy, G., Marshall, P. W., Weller, R. A., Mendenhall, M. H., & Montes, E. J. (2006). Substrate engineering concepts to mitigate charge collection in deep trench isolation technologies. IEEE Transactions on Nuclear Science, 53, 3298-3305. [81] Peterson, W. W., & Weldon, E. J. (1972). Error-correcting code. MIT Press, Cambridge, MA. [82] Pop, E., Mann, D., Wang, Q., Goodson, K., & Dai, H. (2005). Thermal conductance of an individual single-wall carbon nanotube above room temperature. Nano Letters, 96-100. [83] Quirk, M. & Serda, J. (2000). Semiconductor Manufacturing Technology. Prentice Hall. [84] Rabaey, J. M., Chandrakasan, A., & Nikolic. B. (2003). Digital Integrated Circuits. Prentice Hall. [85] Radaelli, D., Puchner, H., Wong, S., & Daniel, S. (2005). Investigation of multibit upsets in a 150 nm technology SRAM device. IEEE Transactions on Nuclear Science, 52, 2433–2437. [86] Parthasarathy, V., Zhu, R., Khemka, V., Roggenbauer, T., Bose, A., Hui, P., Rodriquez, P., Nivison, J., Collins, D., Wu, Z., Puchades, I., & Butner, M. (2002). A 0.25µm CMOS based 70V smart power technology with deep trench for high-voltage isolation. International Electron Devices Meeting, 459-462. [87] Razavi, B. (1996). Monolothic Phase-Locked Loops and clock recovery circuits. IEEE Press. [88] Reed, R. A., Marshall, P. W., Pickel, J. C., Carts, M. A., Fodness, B., Niu, G., Fritz, K., Vizkelethy, G., Dodd, P. E., Twin, T., Cressler, J. D., Krithivasan, R., Riggs, P., Prairie, J., Randall, B., Gilbert, B., & LaBel, K.A. (2003). Heavy-ion broad-beam and micoprobe studies of single-evnet upsets in a 0.2-µm SiGe heterojunction bipolar transistors and circuits. IEEE Transactions on Nuclear Science, 50, 2184-2190. [89] Ryu, K., Badmaev, A., Wang, C., Lin, A., Patil, N., Gomez, L., Kumar, A., Mitra, S., Philip Wong, H. S., & Zhou, C. (2009). CMOS-Analogous wafer-scale nanotube-on-isulator approach for submicrometer devices and integrated circuits using aligned nanotubes. Nano Letters, 9, 189-197. [90] Saito, S., Fujita, M., Dresselhaus, G., & Dresselhaus, M. S. (1992). Electronic structure of chiral graphene tubules. Applied Physics Letters, 60, 2204-2206. [91] Seckin, U., & Yang, C. K. (2008). A comprehensive delay model for CMOS CML circuits. IEEE Transactions on Circuits and Systems, 55, 2608-2618. [92] Sentaurus user guide, Version A-2008.09, Synopsys. 133 [93] Seunghun, H., & Myung, S. (2007). Nanotube electronics: A flexible approach to mobility. Nature Nanotechnology, 207-208. [94] Shi, Q., & Maki, G., (2000). New Design Techniques for SEU Immune Circuits. NASA Symposium on VLSI Design, 7.4.1-7.4.11. [95] Skotnicki, T., Hutchby, J. A., King, T., Wong, H. S. P., & Boeuf, F. (2005). The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and Devices Magazine, 21, 16-26. [96] Slayman, C. W., (2005). Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations. IEEE Transactins on Device and Material Reliability, 5, 397-404. [97] Snoeys, W. J., Gutierrez, T.A.P., & Anelli, G. (2002). A new NMOS layout structure for radiation tolerance. IEEE Transactions on Nuclear Science, 49, 1829 – 1833. [98] Spica, M., & Mak, T.M. (2004). Do we need anything more than single bit error correction (ECC)?. International Workshop on Memory Technology, Design and Testing, 111 – 116. [99] Sun microsystems- soft memory errors and their effect on sun fire systems, 2002. [100] Sutton, A. K., Bellini, M., Cressler, J.D., Pellish, J.A., Reed, R.A., Marshall, P.W., Niu, G., Vizkelethy, G., Turowski, M., & Raman, A. (2007). An evaluation of transistor-layout RHBD techniques for SEE mitigation in SiGe HBTs. IEEE Transactions on Nuclear Science, 54, 2044-2052. [101] Valazco, R., Calin, T., Nicolaidis, M., Moss, S. C., LaLumondiere, S. D., Tran, V. T., & Koga, R. (1996). SEU-hardenend storage cell validation using a pulsed laser. IEEE Transactions on Nuclear Science, 43, 2843-2848. [102] Voldman, S. H. (2006). The influence of a novel contaced polysilicon-filled deep trench (DT) biased structre and its voltage bias state on CMOS latchup. Symposium on Reliability Physics. [103] Woodruff, R. L., & Rudeck, P. J. (1993). Three-dimensional numerical simulation of single event upset of an SRAM cell. IEEE Transactions on Nuclear Science, 40, 1795-1803. [104] Writh, G., Kastensmidt, F., & Ribeiro, I. (2008). Single event transient in logic circuits-load and propagation induced pulse broadening. IEEE Transactions Nuclear Science, 55, no. 6, 2928-2935. [105] www.analogdevices.com [106] Zhao, Y., Liao, A., & Pop, E. (2009). Multiband mobility in semiconducting carbon nanotubes. IEEE Electron Device Letters, 30, 1078-1080. 134 [107] Ziegler, J. L., & Lanford, W. A. (1979). Effects of cosmic rays on computer memories. Science, 206, 776-788. [108] Ziegler, J. F. (1998). Terresterial cosmic ray intensities. IBM Journal of Research and Development, vol.42, no.1, pp.117-140, Jan. 1998 [109] Ziegler, J. F. et al (1996). IBM experiments in soft fail in computer electronics (1978-1994). IBM Journal of Research and Development, 40, 3-18. 135 COMPREHENSIVE REFERENCES [1] Actel, (2002). Effects of Neutrons on programmable logic, a white paper. Technical report Actel corporation. [2] Alexander, D. R. (1996). Design issues for radiation tolerant microcircuits for space. NSREC conference. [3] Alioto, M. & Palumbo, G. (2005). Model and design of bipolar and MOS current mode logic. Kluwer Academic Publishers. [4] Allstot, D. J., Liang, G., & Yang, H. C. (1991). Current-mode logic techniques for CMOS mixed-mode ASICs. IEEE Integrated Circuits Conference, 49, 25.2/1-25.2/4. [5] Amusan, O. A., Witulski, A. F., Massengill, L. W., Bhuva, B. L., Fleming, P. R., Alles, M. L., Sternberg, A. L., Black, J. D., & Schrimpf, R. D. (2006). Charge collection and charge sharing in a 130 nm CMOS technology. IEEE Transactions on Nucearl Science, 53, 3253- 3258. [6] Amusan, O. A., Massengill, L. W., Baze, M. P., Bhuva, B. L., Witulski, A. F., DasGupta, S., Sternberg, A. L., Fleming, P. R., Heath, C. C., & Alles, M. L. (2007). Directional sensitivity of single event upsets in a 90 nm CMOS due to charge sharing. IEEE Transactions on Nuclear Science, 54, 2584-2589. [7] Amusan, O. A., Casey, M. C., Bhuva, B. L., McMorrow, D., Gadlage, M. J., Melinger, J. S., & Massengill, L. W.(2009). Laser Verificaiton of charge sharing in a 90 nm bulk CMOS process”, IEEE Transactions on Nuclear Science, 56, 3065-3070. [8] Amusan, O. A., Massengill, L. W., Baze, M. P., Bhuva, B. L., Witulski, A. F., Black, J. D., et all (2008). Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process. IEEE Transactions on Device and Materials Reliability, 9, 311-317. [9] Amusan, O. A., Massengill, L. W., Baze, M. P., Sternberg, A. L., Witulski, A. F., Bhuva, B. L., & Black, J. D. (2008).Signle event upset in deep-submicrometer technologies due to charge sharing. IEEE Transactions on Nuclear Science, 8, 3. [10] www.analogdevices.com [11] Baggio, J., Ferlet-Cavrois, V., Duarte, H., & FLament, O. (2004). Analysis of proton/neturon SEU sensitivity of commercial SRAMs-application to the terrestrial environment test method. IEEE Transactions on Nuclear Science, 51, 3420–3426. [12] Baumann, R. C. (2005). Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device Materials and Reliability, 5, 305–316. 136 [13] Baumann, R. C. (2005). Soft errors in advanced computer systems,” IEEE Design Test Computers, 22, 258-266, 2005. [14] Baumann, R. C. (2001). Soft errors in advanced semiconductor devices – Part 1: The three radiation sources. IEEE Transactions on Device and Materials Reliability , 1, 17-22. [15] Benedetto, J., Salomonson-Begay, C., & McGuirk, P. (2005). Single event upset hardening limitations in deep sub-micron digital designs due to critical node crowding. Hardened Electronics Radiation Technology (HEART). [16] Bessot, D., & Velazco, R. (1993). Design of SEU-hardened CMOS memory cells: the HIT cell. European Conference on Radiation and its Effects on Components and Systems (RADECS), 563 – 570. [17] Bhattacharya, S., Bnerjee, S., Lee, J., Tasch, A., & Chatterjee, A. (1991). The impact of trench isolation on latch-up immunity in bulk nonepitaxial CMOS. IEEE Electron Device Letters, 12, 77-79. [18] Binder, D., Smith, E.C., & Holman, A.B. (1975). Satellite anomalies from galactic cosmic rays. IEEE Transactions on Nuclear Science, 22, 2675-2680. [19] Bruma, S. (2003). Impact of on-chip process variations on MCML performance. IEEE International Systems-on-Chip Conference, 135-140. [20] Burnett, D., Lage, C. & Bormann, A. (1993). Soft-error rate improvement in advanced BiCMOS SRAMs. IEEE International Reliability Physics Symposium, 156-160. [21] Calin, T., Nicolaidis, M. & Velazco, R. (1996). Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Transactions on Nuclear Science, 43, 2874-2878. [22] Cataldo, A. (2001). SRAM soft errors cause hard network problems. EE Times. [23] Cochran, D., Buchner, S., Chen, D., Kim, H., LaBel, K., Oldham, T., Campola, M., O’Bryan, M., Ladbury, R., Marshall, C., Sanders, A., & Xapsos, M., (2010). Total ionizing dose and displacement damage compendium of candidate spacecraft electronics for NASA. IEEE Radiation Effect Data Workshop. [24] Comer., D. T., (1994). Introduction to Mixed Signal VLSI. Array Publishing Company, NY. [25] Crespi, V. H., & Cohen, M. L. (1997). In situ band gap engineering of carbon nanotubes, Physical Review Letters, 79, 2093-2096. [26] DasGupta, S., Witulski, A.F., Bhuva, B.L., Alles, M.L., Reed, R.A., Amusan, O. A., Ahlbin, J. R., Schrimpf, R. D., & Massengill, L. W. (2007). Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS. IEEE Transactions on Nuclear Science, 54, 2047-2412. 137 [27] Deracobian, N., Vardanian, V. & Zorian, Y. (2004). Embedded memory reliability: the SER challenge. IEEE International Workshop on Memory Technology, Design and Testing, 104– 110. [28] Dodd, P. E. (2005). Physics-based simulation of single-event effects. IEEE Transactions on Device and Materials Reliability, 5, 343–357. [29] Dodd, P. E., Massengill, L. W. (2003). Basic mechanisms and modeling of single-evnet upset in didgital microelectronics, IEEE Transactions on Nuclear Science, 50, 583-602. [30] Dodd, P. E., Sexton, (1995). Critical charge concepts for CMOS SRAMs, IEEE Transactions on Nuclear Science, 42, 1764 – 1771. [31] Dodd, P. E., Sexton, F. W., Hash, G. L., Shaneyfelt, M. R., Draper, B.L., Farino, A.J. & Flores, R.S. (1996). Impact of technology trends on SEU in CMOS SRAMs. IEEE Transactions on Nuclear Science , 43, 2797-2804. [32] Dresselhaus, M. S., Dresselhaus, G. , & Avouris, P. (2001). Carbon Nanotubes: synthesis, structure, properties, and applications, Springer. [33] EIA/JEDEC STANDARD, (1996). Test procedures for the measurement of single-event effects in semiconductor devices from heavy ion irradiation. Electron industries association, Engineering Department, Arlington, VA. [34] Fiorito, S. (2008). Carbon Nanotubes: Angeles or Demons,” Pan Stanford Publishing. [35] Francis, S., Dimitrov, D., Kauppila, J. , Sternberg, A., Alles, M., Holmes, J. & Mantooth, H. A. (2009). Significance of strike model in circuit-level prediction of charge sharing upsets. IEEE Transactions on Nuclear science, 56, 3109-3114. [36] Fritze, M. (2011). ISI Internal peresntation. [37] Fu, S. W., Mohsen, A. M., May, T. C. (1985). Alpha particle-induced charge collection measurements and the effectiveness of a novel p-well protec- tion barrier on VLSI memories. IEEE Transactions on Electronic Devices, 32, 49-54. [38] Fu, J. S., Axness, C. L., and Weaver, H. T. (1985). Memory SEU simulations using 2-D transport calculations. IEEE Electron Device Letters, 6, 422-424. [39] Haghi, M. & Draper, J. (2010). A Single-Event Upset Hardening Technique for High Speed MOS Current Mode Logic. ISCAS Proceeding, 4137-4140. [40] Haghi, M., & Draper, J. (2011). Comparison of Charge Sharing Reduction in Deep Sub- micron CMOS Processes. MWSCAS Proceeding. 138 [41] Haghi, M., & Draper, J. (2011). Single-event transient mitigation in sub-micron combinational circuits. MWSCAS Proceedings. [42] Haghi, M. & Draper, J. (2009). The Effect of Design Parameters on Single-Event Upset Sensitivity of MOS Current Mode Logic. GLSVLSI, Proceeding, 233-238. [43] Haghi, M. & Draper, J. (2009). The 90 nm Double-DICE Storage Element to Reduce Single- Event Upsets. MWSCAS Proceeding, 463-466. [44] Hayden, J. D., Taft, R. C., Kenkare, P., Mazur, C., Gunderson, C., Nguyen, B. Y., Woo, M., Lage, C., Roman, B. J., Radhakrishna, S., Subrah-Manyan, R., Sitaram, A. R., Pelley, P., Lin, J. H., Kemp, K., & Kirsch, H. (1994). A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM. IEEE Transactions on Electron Devices, 41, 2318-2325. [45] Hentschke, R., Marques, F., Lima, F., Carro, L., Susin, A., & Reis, R. (2002). Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy. Symposium on Integrated Circuits and Systems Design, 95 – 100. [46] Hughes, H. L., & Benedetto, J. M. (2003). Radiation effects and hardening of MOS technology: devices and circuits. IEEE Transactions on Nuclear Science, 50, 500-521. [47] Hung, C. M., Floyd, B. A., Park, N., O., K. K. (2001). Fully Integrated 5.35-GHz CMOS VCOs and Prescalers. IEEE Transactions on Microwave Theory and Techniques, 49, 17-22. [48] Iijima, S. (1991). Helical microtubules of graphitic carbon. Nature, 354, 56-58. [49] International Technology Road map for Semiconductors. (2009). Available at http://www.itrs.net [50] Kang, S., & Leblebici, Y. (2004). CMOS digital integrated circuits analysis and design. McGrawHill. [51] Karnik, T., & Hazucha, P. (2004). Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Transaction on Dependable and Secure Computing, 128- 143. [52] Kauppila, J. S., Sternberg, A. L., Alles, M. L., Francis, A. M., Holmes, J., Amusan, O. A., & Massengill, L. W. (2009). A bias-dependent single-event compact model implemented into BSIM4 and a 90 nm CMOS process design kit. IEEE Transactions on Nuclear Science, 56, 3152-3157. [53] Kim, J. E., Lin, J., McMurchie, L., & Sechen, C. (2005). Mitigation of single and multiple- cycle-duration SETs using Double-Mode-Redundancy (DMR) in Time. IEEE Aerospace Conference, 1-10. 139 [54] Kodeti, N. M. (2009). White paper on silicon on insulator (SOI) implementation. www.infotech-enterprises.com. [55] Kratschmer, W., Lamb, L. D., Fostiropoulos, K., & Huffman, D. R. (1990). Solid C 60 : a new form of carbon. Nature, 347, 354-358. [56] Krithivasan, Marshall, P. W., Nayeem, M., Sutton, A. K., Kuo, W., Haugerud, B. M., Najafzadeh, L., Cressler, J. D., Carts, M. A., Marshall, C. J., Hansen, D. L., Jobe, K. M., Mckay, A. L., Niu, G., Reed, R., Randall, B. A., Burfield, C. A., Lindberg, M. D., Gilbert, B. K., & Daniel, E. S. (2006). Application of RHBD Techniques to SEU Hardening of Third – Generation SiGe HBT Logic Circuits. IEEE Transactions on Nuclear Science, 53, 3400-3407. [57] Kroto, H. W., Heath, J. R., O’Brien, S. C., Curl, R. F., & Smalley, R. E. (1985). C 60 : Buckminsterfullerene. Nature, 318, 162-163. [58] Lawrence, R. K., & Kelly, A. T. (2008). Single event effect induced multiple-cell upsets in a commercial 90 nm CMOS digital technology. IEEE Transactions on Nuclear Science, 55, 3367-3374. [59] Lee, K., Nam, I., Kwon, I., Gil, J., Han, K., Park, S., & Seo, B. (2005). The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application. IEEE Transactions on Electron Devices, 52, 1415-1422. [60] Li, L., Raghavendran, S., & Comer, D. T.(2005). CMOS Current Mode Logic gates for high- speed applications.12 th NASA Symposium on VLSI Design. [61] Liu, X. (2006). Synthesis, devices and applications of carbon nanotubes. PhD Dissertation, University of Southern California. [62] Lum, G. (2004). Hardness assurance for space systems. NSREC Short Course. [63] Maiz, J., Hareland, S., Zhang, K., & Armstrong, P. (2003). Characterization of multi-bit soft error events in advanced SRAMs. IEEE International Electron Devices Meeting (IEDM) Technical Digest, 21.4.1–21.4.4. [64] Martel, R., Drycke, V., Appenzeller, J., Wind, S., & Avouris, Ph. (2002). Carbon nanotube field-effect transistors and logic circuits. Design Automation Conference, 94-98. [65] Mavis, D. G., & Eaton, P. H. (2007). SEU and SET modeling and mitigation in deep submicron technologies. IEEE International Symposium on Reliability Physics, 293-305. [66] Mavis, D. G., & Eaton, P. H. (2002). Soft error rate mitigation techniques for modern microcircuits. IEEE International Symposyium on Reliability Physics, 216-225. [67] May, T. C., & Woods, M. H. (1979). Alpha-particle-induced soft errors in dynamic memories. IEEE Transactions on Electron. Devices, 26, 2-9. 140 [68] Meaney, P. J., Swaney, S. B., Sanda, P. N., & Spainhower, L. (2005). IBM z990 soft error detection and recovery. IEEE Transactions on Device and Materials Reliability, 5, 419–427. [69] Mitra, S., Seifert, N., Zhang, M., Shi, Q., & Kim, K.S. (2005). Robust system design with built-in soft-error resilience. Journal of Computer, 38, 43-52. [70] Mizuno, M., Yamashina, M., Furuta, K., Igura, H., Abiko, H., Okabe, K., Ono, A., & Yamada, H. (1996). A GHz MOS, Adaptive Pipeline Technique Using MOS Current-Mode Logic. IEEE Journal of Solid-State Circuits, 31, 784-791. [71] Mongkolkachit, P., & Bhuva, B. (2003). Design technique for mitigation of alpha-particle- induced single-event transients in combinational logic. IEEE Transactions on Device and Materials Reliability, 3, 89-92. [72] Musicer, J., & Rabaey, J. (2000). MOS Current Mode Logic for low power low noise CORDIC computation and mixed-signal environments. International Symposium on Low Power Electronics and Design, 102-107. [73] NASA/GSFC Radiation Effects & Analysis Home Page, www.radhome.gsfc.nasa.gov [74] Naseer, R. (2008). A framwork for soft error tolerant SRAM design. PhD Dissertation. [75] Naseer, R., Boulghassoul, Y., Draper, J., DasGupta, S., & Witulski, A. (2007). Critical charge characterization for soft error rate modeling in 90nm SRAM. International Symposium on Circuits and Systems (ISCAS), 28-30. [76] Naseer, R., & Draper, J. (2005). The DF-DICE storage element for immunity to soft errors. Midwest Symposium on Circuits and Systems, 303 – 306. [77] Neamen, D. A. (2003). Semiconductor physics and devices basic principles. McGrawHill. [78] Niu, G., Krithivasan, R., Cressler, J. D., Riggs, P. A., Randall, B. A., Marshall, P. W., Reed, R. A., & Gilbert, B. (2002). A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuits architectures. IEEE Transactions on Nuclear Science, 49, 3107-3114. [79] Normand, E. (1996). Single event upset at ground level. IEEE Transactions on Nuclear Science, 43, 2742-2750. [80] Olson, B. D., Ball, D. R., Warren, K. M., Massengill, L. W., Haddad, N. F., Doyle, S. E., & McMorrow, D. (2005). Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design. IEEE Transaction on Nuclear Science, 52, 2132-2136. [81] Pellish, J. A., Reed, R. A., Schrimpf, R. D., Alles, M. L., Varadharajaperumal, M., Niu, G., Sutton, A. K., Diestelhorst, R. M., Espinel, G., Krithivasan, R., Comeau, J. P., Cressler, J. D. 141 , Vizkelethy, G., Marshall, P. W., Weller, R. A., Mendenhall, M. H., & Montes, E. J. (2006). Substrate engineering concepts to mitigate charge collection in deep trench isolation technologies. IEEE Transactions on Nuclear Science, 53, 3298-3305. [82] Peterson, W. W., & Weldon, E. J. (1972). Error-correcting code. MIT Press, Cambridge, MA. [83] Pop, E., Mann, D., Wang, Q., Goodson, K., & Dai, H. (2005). Thermal conductance of an individual single-wall carbon nanotube above room temperature. Nano Letters, 96-100. [84] Quirk, M. & Serda, J. (2000). Semiconductor Manufacturing Technology. Prentice Hall. [85] Rabaey, J. M., Chandrakasan, A., & Nikolic. B. (2003). Digital Integrated Circuits. Prentice Hall. [86] Radaelli, D., Puchner, H., Wong, S., & Daniel, S. (2005). Investigation of multibit upsets in a 150 nm technology SRAM device. IEEE Transactions on Nuclear Science, 52, 2433–2437. [87] Parthasarathy, V., Zhu, R., Khemka, V., Roggenbauer, T., Bose, A., Hui, P., Rodriquez, P., Nivison, J., Collins, D., Wu, Z., Puchades, I., & Butner, M. (2002). A 0.25µm CMOS based 70V smart power technology with deep trench for high-voltage isolation. International Electron Devices Meeting, 459-462. [88] Razavi, B. (1996). Monolothic Phase-Locked Loops and clock recovery circuits. IEEE Press. [89] Reed, R. A., Marshall, P. W., Pickel, J. C., Carts, M. A., Fodness, B., Niu, G., Fritz, K., Vizkelethy, G., Dodd, P. E., Twin, T., Cressler, J. D., Krithivasan, R., Riggs, P., Prairie, J., Randall, B., Gilbert, B., & LaBel, K.A. (2003). Heavy-ion broad-beam and micoprobe studies of single-evnet upsets in a 0.2-µm SiGe heterojunction bipolar transistors and circuits. IEEE Transactions on Nuclear Science, 50, 2184-2190. [90] Ryu, K., Badmaev, A., Wang, C., Lin, A., Patil, N., Gomez, L., Kumar, A., Mitra, S., Philip Wong, H. S., & Zhou, C. (2009). CMOS-Analogous wafer-scale nanotube-on-isulator approach for submicrometer devices and integrated circuits using aligned nanotubes. Nano Letters, 9, 189-197. [91] Saito, S., Fujita, M., Dresselhaus, G., & Dresselhaus, M. S. (1992). Electronic structure of chiral graphene tubules. Applied Physics Letters, 60, 2204-2206. [92] Seckin, U., & Yang, C. K. (2008). A comprehensive delay model for CMOS CML circuits. IEEE Transactions on Circuits and Systems, 55, 2608-2618. [93] Sentaurus user guide, Version A-2008.09, Synopsys. [94] Seunghun, H., & Myung, S. (2007). Nanotube electronics: A flexible approach to mobility. Nature Nanotechnology, 207-208. 142 [95] Shi, Q., & Maki, G., (2000). New Design Techniques for SEU Immune Circuits. NASA Symposium on VLSI Design, 7.4.1-7.4.11. [96] Skotnicki, T., Hutchby, J. A., King, T., Wong, H. S. P., & Boeuf, F. (2005). The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and Devices Magazine, 21, 16-26. [97] Slayman, C. W., (2005). Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations. IEEE Transactins on Device and Material Reliability, 5, 397-404. [98] Snoeys, W. J., Gutierrez, T.A.P., & Anelli, G. (2002). A new NMOS layout structure for radiation tolerance. IEEE Transactions on Nuclear Science, 49, 1829 – 1833. [99] Spica, M., & Mak, T.M. (2004). Do we need anything more than single bit error correction (ECC)?. International Workshop on Memory Technology, Design and Testing, 111 – 116. [100] Sun microsystems- soft memory errors and their effect on sun fire systems, 2002. [101] Sutton, A. K., Bellini, M., Cressler, J.D., Pellish, J.A., Reed, R.A., Marshall, P.W., Niu, G., Vizkelethy, G., Turowski, M., & Raman, A. (2007). An evaluation of transistor-layout RHBD techniques for SEE mitigation in SiGe HBTs. IEEE Transactions on Nuclear Science, 54, 2044-2052. [102] Valazco, R., Calin, T., Nicolaidis, M., Moss, S. C., LaLumondiere, S. D., Tran, V. T., & Koga, R. (1996). SEU-hardenend storage cell validation using a pulsed laser. IEEE Transactions on Nuclear Science, 43, 2843-2848. [103] Voldman, S. H. (2006). The influence of a novel contaced polysilicon-filled deep trench (DT) biased structre and its voltage bias state on CMOS latchup. Symposium on Reliability Physics. [104] Woodruff, R. L., & Rudeck, P. J. (1993). Three-dimensional numerical simulation of single event upset of an SRAM cell. IEEE Transactions on Nuclear Science, 40, 1795-1803. [105] Writh, G., Kastensmidt, F., & Ribeiro, I. (2008). Single event transient in logic circuits-load and propagation induced pulse broadening. IEEE Transactions Nuclear Science, 55, no. 6, 2928-2935. [106] Zhao, Y., Liao, A., & Pop, E. (2009). Multiband mobility in semiconducting carbon nanotubes. IEEE Electron Device Letters, 30, 1078-1080. [107] Ziegler, J. L., & Lanford, W. A. (1979). Effects of cosmic rays on computer memories. Science, 206, 776-788. 143 [108] Ziegler, J. F. et al (1996). IBM experiments in soft fail in computer electronics (1978-1994). IBM Journal of Research and Development, 40, 3-18. [109] Ziegler, J. F. (1998). Terresterial cosmic ray intensities. IBM Journal of Research and Development, vol.42, no.1, pp.117-140, Jan. 1998

Abstract (if available)

Abstract As semiconductor industry continues to scale down to ever smaller feature sizes, radiation-induced soft errors are becoming a major concern for microelectronics reliability. A rising problem of a single particle strike causing upsets in more than one circuit node has become more frequent in deep sub-micron technologies. This is especially a troubling trend since most already existing single-event effect mitigation techniques for older technologies are based on the assumption of corruption of data in a single node. However, in deep sub-micron technologies, charge sharing and collecting among multiple nodes due to a single hit has invalidated the above assumption. Therefore, if sub-micron electronic circuits are targeted to be used in radiation sensitive environments, they have to be hard to charge sharing and collecting in addition to other single-event effects. This magnifies the necessity of charge sharing mitigation methods and prior to that a fast and accurate model to measure the sensitivity of adjacent nodes to charge sharing effects. After assessing the vulnerability of a circuit to charge sharing, appropriate mitigation techniques can be applied to reduce the induced error rate. We have developed a semi-empirical circuit model to predict the charge sharing effect between adjacent nodes. This is a fast and easy-to-use model with good accuracy that can be applied to circuit simulators at early stages of a design. The effectiveness of the proposed model is demonstrated by comparing the model with Technology Computer Aided Design (TCAD) simulation results for 65-nm CMOS technology. ❧ PFET devices are more prone to charge sharing than NFET devices due to PNP bipolar amplification

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Asset Metadata

Creator Haghi, Mahta (author)

Core Title Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 04/30/2012

Defense Date 11/08/2011

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag charge sharing,OAI-PMH Harvest,radiation hardening by design,single event transient,single event upset,sub-micron CMOS

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Draper, Jeffrey (committee chair), Nakano, Aiichiro (committee member), Steier, William Henry (committee member)

Creator Email mahta_h@yahoo.com,mhaghi@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c3-17193

Unique identifier UC11290268

Identifier usctheses-c3-17193 (legacy record id)

Legacy Identifier etd-HaghiMahta-679.pdf

Dmrecord 17193

Document Type Dissertation

Rights Haghi, Mahta

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA