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Integrated large-scale monolithic electro-optical systems in standard SOI CMOS process

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Integrated large-scale monolithic electro-optical systems in standard SOI CMOS process

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Content Integrated Large-Scale Monolithic Electro-Optical Systems in Standard SOI CMOS Process by Hooman Abediasl A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulllment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2017 Copyright 2017 Hooman Abediasl Dedication To my mother, Fariba, for her unconditional love, friendship, and support To may dad, Alireza, for his love and guidance ii Acknowledgements First, I would like to thank my advisor, Prof. Hossein Hashemi. His guidance and support has helped me at all the times during research. I would have been lost without him. I've been grateful to have him as my mentor. Besides my advisor, I would like to thank the rest of my thesis and qualifying committee: Dr. Dan Dapkus, Dr. Michelle Povinelli, Dr. Aluizio Prata, Dr. Stephen Cronin, Dr. Rehan Kapadia, and Dr. Aiichiro Nakano for their guidance and support. I thank my dear labmates in Prof. Hossein Hashemi's Group: Alireza Imani, Masashi Yamagata, Alireza Imani, Run Chen, Sushil Subramanian, Kunal Datta, Fatemeh Rezaiefar, and SungWon Chung for all the hard and fun time we have had toghter. I am thankful to Prof. Firooz A atuoni, Dr. Ankush Guel, and Dr. Behnam Analui for their generous assistance. Lastly, and most importantly, I thank my parents for everything. To them I dedicate this thesis. ii Table of Contents Dedication ii Acknowledgements ii List Of Tables vi List Of Figures viii Abstract xxi Chapter 1: Introduction and Background 1 1.1 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Why Silicon Photonics . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2: Silicon Photonics Process Technology 9 2.1 Silicon Photonics Processes . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 IBM/GF 7RF SOI CMOS for Photonics . . . . . . . . . . . . . . . 14 2.3 Photonic Device Designs in the IBM/GF 7RF SOI CMOS Process . 15 2.3.1 Passive photonics . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1.1 Waveguides . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1.2 Power Splitters and Combiners . . . . . . . . . . . 29 2.3.1.3 Grating Coupler . . . . . . . . . . . . . . . . . . . 39 2.3.2 Active Photonics . . . . . . . . . . . . . . . . . . . . . . . . 47 2.3.2.1 Variable Thermo-Optical Phase Shifter . . . . . . . 47 2.3.2.2 Variable Thermo-Optical Amplitude Controller . . 59 Chapter 3: Monolithic Optical Phased Array Transceiver 63 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 Principle of optical phased array . . . . . . . . . . . . . . . . . . . . 64 3.3 Background of optical phased arrays . . . . . . . . . . . . . . . . . 68 3.4 Challenges of integrated optical phased arrays . . . . . . . . . . . . 74 iii 3.4.1 Scalability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.4.2 Antenna pitch . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5 Monolithic optical phased-array transceiver in a standard SOI CMOS process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5.2 Optical phased array transceiver . . . . . . . . . . . . . . . . 80 3.5.3 Design of nano grating coupler as optical antenna . . . . . . 84 3.5.4 Design of power distribution network for 8 8 optical phased array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.5.5 Programmable electrical 7-bit Digital-to-Analog Converter and heater driver in the IBM/GF 7RF SOI Process . . . . . 92 3.5.6 Array elements and calibration . . . . . . . . . . . . . . . . 97 3.5.7 Antenna pitch . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.5.8 Scanning speed . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.5.9 Experimental results . . . . . . . . . . . . . . . . . . . . . . 106 3.5.9.1 Operation of optical phased array in the transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.5.9.2 Operation of optical phased array in the receive mode113 3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Chapter 4: 128-bit Spectral Processing of Sub-picosecond Optical Pulses in a Standard SOI CMOS Process 118 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.2 Integrated wavelength separation and combining elements . . . . . . 121 4.3 Monolithic Optical Short-Pulse Encoder/Decoder . . . . . . . . . . 131 4.4 System elements and calibration . . . . . . . . . . . . . . . . . . . . 134 4.5 Electrical routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.6.1 Operation of OSPED measured with fast electro-optical de- tection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.6.2 Operation of OSPED measured with optical short pulse auto- correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Chapter 5: Conclusions and Directions for Future Work 153 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 References 155 Appendix A Design of Schottky Photodiode in the IBM/GF 7RF SOI Process . . . . 167 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 iv A.2 Principle of doped silicon-metal schottky photodiode . . . . . . . . 168 v List Of Tables 2.1 Comparison of selected Silicon Photonics foundry processes. . . . . 13 2.2 Summary of measured straight and bend waveguide loss in the IBM/GF 7RF SOI process at 1550 nm. The waveguide width is 550 nm. . . . 28 2.3 Summary table of measured optimum coupling eciency of dier- ent grating coupler designs implemented in the IBM/GF 7RF SOI process at the 1550 nm wavelength. . . . . . . . . . . . . . . . . . . 49 2.4 Performance summary of the fabricated thermo-optical phase shifter at 1550 nm wavelength in the IBM/GF 7RF SOI process. . . . . . . 56 2.5 Performance summary of the fabricated thermo-optical attenuator at 1550 nm wavelength in the IBM/GF 7RF SOI process. . . . . . . 62 3.1 Target coupling ratio for 8 cells together with extracted optimized coupling lengths to work at 1550 nm form the rows to the corre- sponding cell waveguides. . . . . . . . . . . . . . . . . . . . . . . . . 91 3.2 Target coupling ratio for 8 cells together with extracted optimized coupling lengths to work at 1550 nm form the main bus to the row waveguides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.3 Comparison table between selected published integrated planar op- tical phased arrays and the presented work here. . . . . . . . . . . . 117 4.1 Performance summary table of monolithic arrayed waveguide gratings.131 4.2 Performance summary in comparison with other semi- or fully-monolithic spectral light processors. . . . . . . . . . . . . . . . . . . . . . . . . 152 vi A.1 Summary table of extracted Schottky diode parameters from IV mea- surements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 vii List Of Figures 1.1 (a) Real part of refractive index and (b) material optical absorption per unit length of silicon, germanium and SiO 2 versus wavelength [1, 2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Examples of published state of the art devices in silicon photonic processes: (a) 50 GHz electro-absorption Ge modulator [3], (b) 67 GHz Ge photodetector [4] and (c) IIIV laser bounded on silicon [5] 5 2.1 Two main approaches, a) hybrid, and b) monolithic, to integrate electro-optical integrated systems. . . . . . . . . . . . . . . . . . . . 11 2.2 Typical cross section of quarter-micron SOI photonics platforms: (a) passive IMEC, and (b) active IMEC and IME processes. . . . . . . 12 2.3 Cross section of IBM/GF 7RF SOI CMOS process with 4 metal layers. 14 2.4 Representative silicon waveguide geometry and simulated optical eld intensity within the silicon waveguide (conned mode) for the designed single mode waveguide in the IBM/GF 7RF SOI process. . 16 2.5 Geometry of 1D slab waveguide with silicon core and SiO 2 cladding. 17 2.6 Graphical solution of transcendental equations Eq. 2.2, and 2.3 to nd guided modes of 1D slab waveguide with 145 nm thick silicon surrounded by SiO 2 at 1550 nm wavelength for (a) TE and (b) TM modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7 The eect of waveguide width on the operation of waveguide for three widths, 400, 550 and 750 nm. For small widths, there are no conned modes. For large widths, waveguide is multi-mode. Only a narrow window in between supports a single conned mode. . . . . 21 viii 2.8 Simulated waveguide propagation loss versus waveguide width in the IBM/GF 7RF SOI process with 145nm silicon thickness. Assuming sidewall roughness variance is 7.5 nm, and background doping is 10 16 1=cm 3 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9 Simulated waveguide propagation loss versus silicon thickness for two dierent sidewall roughness variances (W WG = 550 nm, and background doping is assumed to be 10 15 1=cm 3 ). . . . . . . . . . . . 23 2.10 Simulated waveguide propagation loss as a function of silicon back- ground doping concentration for d Si = 145nm and W WG = 550nm. . 23 2.11 Loss characterization principle based on the end-cut method. . . . . 24 2.12 Loss characterization principle based on an interferometric method. 25 2.13 Measurement results of interferometric waveguide loss for structures with (a) 8 U-turns with radius R = 10 m, length dierence L = 2:3 mm, (b) 2 U-turns with radius R = 10 m, 14 U-turns with radius R = 5 m length dierence L = 288:04 m, (c) 16 U-turns with radius R = 10 m, length dierence L = 0:504 mm, (d) 4 U-turns with radius R = 10 m, 36 U-turns with radius R = 2 m length dierence L = 320:86 m . . . . . . . . . . . . . . . . . . . 26 2.14 Extracted straight waveguide loss from interferometric test struc- tures versus wavelength in the IBM/GF 7RF SOI process. Simulated waveguide loss for dierent sidewall roughness rms variances, c, are also shown to estimate the roughness. . . . . . . . . . . . . . . . . . 27 2.15 Extracted waveguide bend loss from interferometric test structures versus bend radius for two dierent wavelengths, 1550nm (top) and 1560 nm (bottom), in the IBM/GF 7RF SOI process. Simulated loss for dierent sidewall roughness rms variances are also shown to estimate the roughness. . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.16 Chip microphotograph of waveguide test structures realized in the IBM/GF 7RF SOI process. . . . . . . . . . . . . . . . . . . . . . . . 28 2.17 Principle operation of directional coupler as power splitter or combiner. 31 ix 2.18 (a) Geometry of a directional coupler in the IBM/GF 7RF SOI pro- cess. Simulation results of (b) coupling length, L , and (c) n odd and n even versus gap size, g. . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19 (a) Geometry of the implemented directional couplers in the IBM 7RF SOI process; (b) FDTD simulation result for coupling length equal to 18m to get 50:50 splitter; (c) Measurement result shows split ratio as a function of wavelength when the coupler length is 18m; (d) Measured split ratio a a function of coupling length at = 1550 nm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.20 Principle operation of multi-mode interferometer (MMI) as power splitter or combiner. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.21 FDTD simulation showing the eld intensity as light from a single mode waveguide couples to and propagates in a multi-mode region. The propagation speed dierence of various mode results in an in- terference pattern along the propagation (z) direction. . . . . . . . . 35 2.22 Design parameters of 1 2 MMI in IBM 7RF SOI process. . . . . . 35 2.23 Simulated performance of a two-way MMI-based power splitter as function of W . FOM is dened as LossWL. . . . . . . . . . . 36 2.24 (a) Geometry of the implemented compact two-way MMI in the IBM/GF 7RF SOI process; (b) FDTD simulations; (c) Measurement results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.25 Schematic of a Y-junction as an optical power splitter or combiner. 38 2.26 Measurement result together with FDTD simulation results of Y- junctions in the IBM/GF 7RF SOI process with dierent geometries. 38 2.27 (a) Coupling light from ber to silicon waveguide from the edge of a chip. (b) Optical eld intensity mode prole of ber (left) and silicon waveguide (right) withW = 8m at 1550 nm. (c) FDTD simulation result of coupling loss versus silicon waveguide width, W at 1550 nm. 40 2.28 Principle of grating coupler operation. . . . . . . . . . . . . . . . . 42 x 2.29 Simulated coupling eciency and optimum coupling angle in a grat- ing coupler as a function of grating period at = 1550 nm for N = 25, f = 0:5, and W G = 10m. . . . . . . . . . . . . . . . . . . . . . 43 2.30 Simulated coupling eciency and optimum coupling angle in a grat- ing coupler as a function of grating duty cycle at = 1550 nm for N = 25, = 720nm, and W G = 10m. . . . . . . . . . . . . . . . . . 44 2.31 Simulated normalized coupling eciency of grating coupler to ber as a function of wavelength. In this simulation, N = 25, f = 0:5, period = 720nm, W G = 10m, and = 18 . . . . . . . . . . . . . 44 2.32 Simulated normalized coupling eciency as a function of grating coupler sizeW G at = 1550nm when N = 25,f = 0:5, = 720nm, and = 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.33 Simulated impact ofN on coupling eciency of a grating coupler at = 1550nm for W G = 10m, f = 0:5, = 720nm, and = 18 . . 46 2.34 Layout of the implemented grating coupler in the IBM/GF 7RF SOI process that is used to couple the light between the chip and a ber. Combination of poly silicon (green) and active silicon (red) is used to create the periodic structure. . . . . . . . . . . . . . . . . . . . . 46 2.35 Experimental setup to measure coupling eciency of a grating coupler. 47 2.36 Measured optimum coupling eciency of fabricated grating couplers with W G = 10m, duty cycle f = 0:5, and N = 25 and dierent periods in the IBM /GF 7RF SOI process compared with simulations at 1550 nm wavelength. . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.37 Measured optimum coupling eciency of fabricated grating couplers with W G = 10m, = 720, and N = 25 and dierent duty cycles, f, in the IBM/GF 7RF SOI process compared with simulations at 1550 nm wavelength. . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.38 The principle of tunable optical phase shift is shown on the left side. Typical mechanisms to implement based on thermo-optical or carrier injection eects are shown on the right side. . . . . . . . . . . . . . 50 xi 2.39 Doped poly silicon heater generates heat as electrical current ows. The generated heat is partially spent in the resistor (H s ), transferred upward (H u ), downward (H d ), and to the left (H l ) and right (H r ) sides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.40 Example of simulated temperature prole across cross section of a silicon waveguide by burning 30 mW power inside adjacent doped poly silicon heater using the COMSOL software. . . . . . . . . . . . 53 2.41 Fabricated doped poly silicon heater together with adjacent waveg- uide as thero-optical phase shifter in the IBM/GF 7RF SOI process. An MZI is used to characterize the thermo-optical eciency. . . . . 55 2.42 Variable compact thermo-optical phase shifter that is implemented in the IBM/GF 7RF SOI process; (b) Corresponding measured am- plitude and phase responses as a function of burned power inside heater at 1550 nm wavelength. . . . . . . . . . . . . . . . . . . . . . 57 2.43 Test structures to characterize both phase and amplitude response of the thermo-optical phase shifter (top). Chip microphotograph of fabricated structures in the IBM/GF 7RF SOI process is shown (bottom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.44 Concept of variable amplitude controller using a thermo-optical phase shifter in an interferometer. . . . . . . . . . . . . . . . . . . . . . . 59 2.45 Variable thermo-optical amplitude controller that is implemented in the IBM/GF 7RF SOI process; (b) Corresponding measured ampli- tude and phase responses as a function of burned power inside heater at 1550 nm wavelength. . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.46 Test structures to characterize both phase and amplitude response of thermo-optical attenuator (top). Chip microphotograph of fabri- cated structures in the IBM/GF 7RF SOI process is shown (bottom). 61 3.1 Principle of phased array operation. By controlling the relative phase dierence between multiple coherent emitters, the far-eld direction can be changed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2 Simulated far eld pattern of an 8-element phased array with uniform antenna spacing (D) when (a) D ==2, (b) D =, (c) D = 5, (d) D = 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 xii 3.3 Simulated far eld pattern of an N-element phased array with uni- form antenna spacing (D = =2) when (a) N = 4, (b) N = 8, (c) N = 64, (d) N = 1024. . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4 Principle of beamforming by controlling both phase and amplitude of each emitter of an OPA. . . . . . . . . . . . . . . . . . . . . . . . 68 3.5 Conventional optical beam steering methods using either mechanical rotary mirrors or electronically controlled liquid crystals. . . . . . . 69 3.6 Digital light processor using 10 6 tiltable micro-mirrors [6]. . . . . . 69 3.7 2D array of 4 4 elements with with no active element and array spacing of 60m. The beam steering, 9:6 was achieved by tuning wavelength of the laser from 1530 - 1570 nm. . . . . . . . . . . . . . 72 3.8 1D array with 16 elements capable of 2D steering. Steering of 20 15 is demonstrated by using thermo-optical tuning in latitudinal direction and wavelength tuning (1480-1580 nm) in longitudinal di- rection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.9 1D array with 16 antennas and 2m spacing. 51 steering range has been reported using thermo-optical phase shifters. . . . . . . . . . . 73 3.10 2D array of 88 antennas with tunable thermo-optical phase shifter per element. 6 steering has been reported in both longitudinal and latitudinal directions. . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.11 1D array with 32 elements and 4 m pitch achieving 23 3:6 2D steering using tunable PIN diode phase shifters and tunable on-chip laser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.12 Dierent architectures to layout OPA elements: localized antennas only where active elements are placed further away and routed us- ing waveguides in a (a) 1D conguration or (b) 2D conguration. (c) Localized antennas and active elements within a cell. Power is delivered to each cell using a scalable passive distribution network. . 76 3.13 Schematic of a basic optical phased array transceiver. . . . . . . . . 79 xiii 3.14 (a) Schematic of the 8 8 monolithic OPA transceiver with indepen- dent amplitude and phase control at each element. In the transmit mode, the laser light is coupled in to the input Grating Coupler (GC) and delivered to each of the 64 antennas using silicon waveg- uides. In the receive mode, the impinged light on the optical phased array, after being collected and processed by each element, is com- bined into one eld and is sent out through the output GC; (b) Chip microphotograph of the fabricated optical phased array transceiver in the IBM/GF 7RF SOI process featuring over 300 distinct opti- cal components and over 74,000 distinct electrical components; (c) Close-up view of the Optical Phased Array core consisting of 64 opti- cal variable phase shifters, 64 optical variable attenuators, 64 optical nano-antennas, and 128 metal lines routing the control signals from the on-chip electronic circuitry to the optical core; (d) Close-up view of a unit optical element consisting of a variable phase shifter, a variable attenuator, and a nano-antenna. . . . . . . . . . . . . . . . 81 3.15 Schematic of a focusing grating coupler that consists of an input waveguide, a taper region and a grating region. Gratings are curved in such a way that the center of optical mode of input waveguide is at the focusing point of the curved grating. . . . . . . . . . . . . . . 84 3.16 Simulated eect of grating coupler width (W a ) and taper length on the upward radiation eciency at 1550 nm wavelength. . . . . . . . 86 3.17 (a) Schematic of designed focusing grating coupler in the IBM/GF 7RF SOI process. FDTD simulation result of (b) near-eld and (c) far-elds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.18 Dierent architectures to distribute optical power from input waveg- uide to N 2 = 2 m elements: (a) tree based approach by using 1 2 power splitters and (b) scalable approach using directional couplers with adjusted coupling ratio. . . . . . . . . . . . . . . . . . . . . . . 88 3.19 Schematic of a network to uniformly distribute optical power to all cells of an 8 8 optical phased array. . . . . . . . . . . . . . . . . . 89 3.20 Simulated coupling ratio of directional couplers with dierent cou- pling lengths as a function of wavelength form each row to corre- sponding cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 xiv 3.21 Simulated coupling ratio of directional couplers with dierent cou- pling lengths as a function of wavelength form the main bus to the rows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.22 Schematic of poly silicon heater driver circuitry consisting of a 7-bit programmable DAC and a high-power driver stage. . . . . . . . . . 93 3.23 Layout of the 7-bit DAC using segmented MOSFETs. Dummy MOS- FETs are placed to increase the uniformity of DAC transistors. . . . 94 3.24 Schematic of one bit digital program circuitry using shift registers. . 95 3.25 Schematic of the driver stage using double stacked high break-down transistors to deliver up to 100 mW to the heater. . . . . . . . . . . 96 3.26 Simulated delivered power to heater as a function of DAC output current (I DAC ) for two dierent V DDdriver values, 6.5 V and 10 V. . 97 3.27 Layout of complete control electronic to drive one heater. It consists of 7-bit programmable DAC with driver stage. The total foot print is 170 m 160 m. . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.28 Routing of the control lines from the electronic circuitry to the 8 8 optical phased array transceiver, using top-level metalization, is shown. The common electrical terminal of all the 128 thermo-optical heaters are connected together using bottommost metal lines. . . . 99 3.29 Layout of unit cell with related geometries. . . . . . . . . . . . . . . 102 3.30 Experimental setup to measure the speed of an implemented inte- grated thermo-optical attenuator. . . . . . . . . . . . . . . . . . . . 103 3.31 Measured normalized output power of attenuator vs wavelength while it is driven by zero volt to nd quadrature point. . . . . . . . . . . 104 3.32 Measured input and output time-domain waveforms of the imple- mented thermo-optical attenuator. . . . . . . . . . . . . . . . . . . . 105 3.33 Measurement setup to measure near-eld or far-eld of the optical phased array. The captured image from an infrared camera is fed back to a processing and programming unit (personal computer) to adjust the phase and amplitude settings. . . . . . . . . . . . . . . . 106 xv 3.34 A representative phase and amplitude prole of an uncalibrated op- tical phased array (left), and the corresponding uncalibrated far-eld radiation pattern (right). . . . . . . . . . . . . . . . . . . . . . . . . 107 3.35 Algorithm to measure the response of each variable optical attenua- tor in the optical phased array. . . . . . . . . . . . . . . . . . . . . 109 3.36 Algorithm to measure the relative phase response of variable ampli- tude and phase shifters in the optical phased array. . . . . . . . . . 110 3.37 Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the corresponding amplitude and phase prole settings; Far eld of focused beam gen- erated by uniform phase and amplitude proles shows 12 dB peak to rst side-lobe ratio. . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.38 Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the corresponding amplitude and phase prole settings; Gaussian amplitude prole and uniform phase prole create a wider far-eld main lobe with 11 dB side-lobe suppression compared with uniform amplitude prole. . . 111 3.39 Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the correspond- ing amplitude and phase prole settings; The main beam generated using Gaussian amplitude prole is steered 1:6 to the edge of each interference order in horizontal direction by progressing phase shift between columns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.40 Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the corresponding amplitude and phase prole settings; The main beam generated us- ing Gaussian amplitude prole is steered 1:6 to the edge of each interference order in vertical direction by progressing phase shift between rows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.41 Example of generated near- and far-eld radiation patterns using the OPA in the transmit mode with the corresponding amplitude and phase prole settings; Far eld image nearly resembling a straight line is created by setting proper amplitude and phase proles. . . . 113 xvi 3.42 (a) A ber with angle with respect to normal axis of OPA is placed far enough to create an impinging plane wave on the OPA. Each nano-photonic antenna collects a portion of the incident eld, adjusts its amplitude and phase, and couples it to the combining waveguide. The total collected eld is detected through another ber located at the top of the output grating coupler; (b) Received eld by each nano-photonic antenna is coupled to the combining waveguide through couplers judiciously designed to ensure near-equal coupled signal values across the array. Optical termination is used to dissi- pate the received power residue and eliminate the unwanted re ections.115 4.1 Schematic of a generic spectral processor for femtosecond optical pulses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.2 Generic geometry of ring resonator as wavelength lter. Drop port has band-pass response at resonance wavelength. . . . . . . . . . . . 123 4.3 Wavelength separation scheme with using 128 cascaded ring res- onators centered at 128 dierent wavelengths. . . . . . . . . . . . . 124 4.4 Simulated lter response of two cascaded ring resonators with 25 GHz channel spacing in three dierent processes: IBM/GF 7RF SOI, IMEC silicon photonics, and ideal (zero waveguide loss). . . . . . . 125 4.5 Operation principle of typical arrayed waveguide grating (AWG). . 126 4.6 Simulated diraction angle of waveguide mode into free propagation region in the IBM/7RF SOI process. . . . . . . . . . . . . . . . . . 129 4.7 (a) Geometry and (b) Simulated three adjacent channel responses of designed AWG in IBM/GF 7RF SOI process with 25 GHz channel spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.8 Schematic of the 128-bit monolithic optical short pulse processor with independent amplitude and phase control at each bit (wavelength- channel). Short pulse is diracted o-chip and multiple wavelengths centered at 128 dierent wavelengths (colors) are coupled in to grat- ing couplers. Each color is processed on chip using independent wavelength-dependent amplitude and phase control units, then cou- pled out of the chip using similar grating couplers. . . . . . . . . . . 132 xvii 4.9 Chip microphotograph of the fabricated 128-bit monolithic optical short pulse processor in the IBM/GF 7RF SOI CMOS process fea- turing over 500 distinct optical components and over 150,000 distinct electrical components. . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.10 (a) Grating coupler to couple light in or out of the chip with 4 m width and 30 m length for high isolation between adjacent chan- nels. (b) Typical measured response of grating coupler showing 1 dB bandwidth of 26 nm. . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.11 Simulated frequency selectivity of two adjacent grating couplers when they are coupled by diracted light with channel spacing of 20 GHz. 136 4.12 (a) Thermo-optical variable phase shifter realized as a meandered waveguide with poly-silicon heaters in between to increase the power eciency and decrease the voltage swing that is needed to cover 2 optical phase shift. (b) Typical measured phase and amplitude responses of a variable phase shifter as a function of heater power consumption at peak wavelength. . . . . . . . . . . . . . . . . . . . 136 4.13 (a) Optical variable attenuator is constructed as an interferometer with polysilicon heater in between. The relative phase change be- tween the two paths, due to thermo-optical eect that is more promi- nent in the longer branch, results in amplitude tunability of around 16 dB. The arm length is slightly dierent (L a has been adjusted) for each cluster to set the desired peak wavelength over the desired 30 nm wavelength range. (b) Typical passive response of attenu- ators of each cluster demonstrating peaks at dierent wavelengths. (c) Typical measured phase and amplitude responses of an optical variable attenuator as a function of heater power consumption at peak wavelength. (d) Simulated and measured peak wavelengths of variable attenuators of all clusters. . . . . . . . . . . . . . . . . . . 138 4.14 (a) Schematic of the measurement setup to characterize amplitude and phase responses of each channel; (b) Normalized measured spec- trum of all channels plotted together after amplitude calibration. . 139 4.15 Measured power spectrum of short pulse laser using an optical spec- trum analyzer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 xviii 4.16 (a) Measured spectrum of channels 63 and 64 picked up by a lensed ber at the top of grating couplers for two cases when phase shifter in channel 64 is tuned to give in or out of phase interference. The infor- mation at the mid-wavelength, here 1550.07 nm, is used to calibrate the phase shifter. (b) Example of normalized interference pattern at mid-wavelength of (a) as a function of active heater power of phase shifter in channel 64. . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.17 Schematic of the setup used to measure processed optical pulse width using both very fast electro-optical detection and optical short pulse intensity auto-correlator. . . . . . . . . . . . . . . . . . . . . . . . . 144 4.18 Photograph of the wirebonded chip that is mounted on a PCB with the required supply and programming signals as well as vias under- neath chip for better thermal conductivity. . . . . . . . . . . . . . . 144 4.19 Measured optical pulse width when one, two, three, 10 and 128 chan- nels are on and are in phase using a 50 GHz photodiode. . . . . . . 145 4.20 Detected optical pulse width using a 50 GHz detector versus the number of ON channels. After three channels, the pulse width is limited to the electrical bandwidth of the detection system. . . . . 145 4.21 Schematic of optical short pulse intensity auto-correlator [7]. . . . . 146 4.22 Experimental result of intensity auto-correlation of the output pro- cessed light for three code lengths, 64, 88 and 128, in two cases: one is successfully constructed short pulse, and second is encoded pulse with Walsh orthogonal code. The data is normalized to the peak of constructed signal and encoded signal for each code length is relatively normalized to corresponding constructed signal. . . . . 150 4.23 Extracted constructed pulse width and intensity ratio of pulse peak to peak of encoded signal versus number of used channels. . . . . . 150 4.24 Measured intensity auto-correlation of an encoded pulse with 128 channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.25 Intuitive emplanation of the eect of code length on intensity and intensity ayto-correlation for Gaussian pulse. . . . . . . . . . . . . . 151 A.1 Principle of Schottky doped silicon-metal photodiode. . . . . . . . . 168 xix A.2 Geometry of Schottky doped silicon-metal photodiode in IBM/GF 7RF SOI process (a) top and (b) side views. . . . . . . . . . . . . . 169 A.3 Measured IV of Schottky photodiode of fabricated device in the IBM/GF 7RF SOI process (a) linear (b) log scales. . . . . . . . . . 170 A.4 Measurement setups to characterize (a) responsivity and (b) electri- cal bandwidth of the Schottky photodiode. . . . . . . . . . . . . . . 171 A.5 Measurement results of (a) responsivity, (b) junction capacitance, and (c) electrical bandwidth using both direct and vector network analyzer of the Schottky photodiode versus reverse bias voltage com- pared with simulated values. . . . . . . . . . . . . . . . . . . . . . . 172 xx Abstract The thesis presents device level and system level integrated large-scale monolithic electro-optical solutions for wide range of applications, including: light detection and ranging (lidar), imaging, optical code division multiple access networks, opti- cal pulse shaping and biomedical sensing. Silicon photonics technology is used to enable monolithic integration, designing novel devices and systems particularly in commercially available SOI CMOS process. Two system level examples are pro- posed and demonstrated: rst, 8 8 optical phased array transceiver, the world's rst monolithically integrated 2-dimensional optical phased array in a commercial CMOS process, and second, 128-bit spectral light processor of sub-picosecond op- tical short pulses. xxi Chapter 1 Introduction and Background 1.1 Research Motivation Silicon has revolutionized electronics industry. Huge investment has been put into this material to turn it into cheap, reliable and high-performing choice for electronic applications [8, 9]. Today, very complex electronic systems have been realized thanks to decades of development [10]. These systems have changed human societies in a way that life can not be imagined without them. Photons, massless packet of energy, is unit of electromagnetic wave with a typ- ical frequency in the order of hundreds of THz. It oers much higher potential bandwidth to carry more information compared with lower-frequency electrons, better electromagnetic isolation, and smaller wavelength. Similar to the trend in electronics industry, integrating massive number of photonic components can po- tentially revolutionize and enable applications to the extent that have never been 1 conceived before [11, 12, 13]. So far, most of the eorts have been focused to im- plement standalone devices and optimize their performances by using combination of design, material, and process steps to guide, process, and detect light eciently [14, 15, 16, 17]. However, a technology platform that oers reliable, cheap, high- performing, very large scale electro-optical system does not exist. In the next section, it will be shown why s silicon technology can be the platform of choice to realize complex electro-optical systems. 1.2 Why Silicon Photonics Silicon has great potential to be considered as the core material for integrated photonics applications. Fundamentally, there is a wide range of wavelengths that the combination of refractive index and material loss of silicon enables realization of dierent types of integrated photonic devices. When an electromagnetic wave propagates in a medium with complex refractive index of n +ik, its phase and amplitude after length L chang as E(z;) =e 2kL e i2nL ; (1.1) 2 whereE(z;) is the electric eld and is the wavelength. Therefore, the power that is proportional to eld squared decays by factor of e 4kL . By denition, material absorption per unit length is dened as [18]: () = 4k : (1.2) therefore the propagation loss in dB/unit length can be found as Loss [dB=unit length] = 10log(e) = 4:34: (1.3) For example if = 100 1=cm, the propagation loss is 434 dB=cm. Figure 1.1 shows the real part of refractive index (n) and propagation loss per unit length () of silicon, germanium, and SiO 2 versus wavelength. These materials are compatible with standard CMOS processes. The large contrast between refractive indexes particularly silicon versusSiO 2 and extremely low material loss of silicon, specially in the 1300 - 1600 nm wavelength range, can be used to realize low-loss conned mode dielectric waveguides and passive photonics (Chapter 2). From the other side, big material loss of germanium in the same wavelength range makes it suitable to modulate or detect and convert photons to electrons [3, 16, 17]. 3 Figure 1.1: (a) Real part of refractive index and (b) material optical absorption per unit length of silicon, germanium and SiO 2 versus wavelength [1, 2]. Early demonstration of silicon photonic devices was around late 1980s early 1990s [19, 20, 21]. Over the past few decades, researchers have realized wide range of silicon photonic devices [22, 23, 24, 25]. Today, state of the art high-performing modulators and detectors with more than 50 GHz bandwidth and IIIV lasers integrated all in silicon photonic processes have been reported [3, 4, 5]. Figure 1.2 shows examples of some of these state-of-the-art devices. To realize complex electro-optical systems that consist of many components, the performance of each individual device doesn't necessarily have to be the opti- mum. In fact, even if components are the same by design, it is impossible to get identical experimental function given fabrication process tolerances, temperature variation, etc. However, it is possible to realize fully-functional systems by having enough tunability and controlability for all the components. This requires a reliable 4 Figure 1.2: Examples of published state of the art devices in silicon photonic pro- cesses: (a) 50 GHz electro-absorption Ge modulator [3], (b) 67 GHz Ge photode- tector [4] and (c) IIIV laser bounded on silicon [5] 5 fabrication process and material system. Silicon is the only material with success- ful track of record in electronics industry to play this role in integrated photonics industry as well. 1.3 Applications Large scale integrated electro-optical systems may oer cheap, reliable, high perfor- mance solution for wide range of applications including chip to chip interconnects, optical phased arrays for sensing, ranging, 3D imaging, holography, optical code division multiple access networks, or biomedical sensing. Recent advancement in fabrication technology have enabled realization of some of these systems [11, 26]. As an example, optical interconnects can benet from large scale integration and potentially be considered as competitor to replace conventional copper electrical counterparts by reducing the power consumption [27, 28]. Recent advancements to reduce power consumption of optical modulators and detectors [29, 30, 31, 32] have paved the way in this quest. Light detection and ranging (Lidar) systems where an optical beam is steered in space oer high-resolution 3D maps from surrounding environments [12, 13] and can be used in self-driving cars, and autonomous systems. Large scale integrated lidars can overcome challenges of conventional mechanical methods that have large size, high cost, and slow scanning speed. 6 Another type of applications that can benet from silicon photonics is biomed- ical sensing. Silicon photonics can oer very cost and size ecient solution to perform the entire sensing, analysis and processing on a single chip [33]. Additionally, large scale integrated electro-optical systems may nd unique ap- plications in future hand held devices. 1.4 Dissertation Outline The dissertation is organized as follows: In Chapter 2, dierent platforms for silicon photonics process technology are re- viewed. The application of IBM/GF 7RF SOI CMOS process for photonic system is discussed. Details of devices that have been designed and characterized in this process will be shown and discussed. Finally, I will talk about why this process is suitable for monolithic large scale electro-optical system integration. In Chapter 3, principle and applications of optical phased arrays will be introduced. Background will be reviewed and challenges of integrated implementation will be discussed. Then, I'll talk about my solution to address some of the key challenges and demonstrate the world's rst monolithic optical phased array transceiver in a standard SOI CMOS process. System level as well as device level design, analysis and simulations with measured performance are presented. Finally, I'll conclude the chapter with existing challenges and future direction. 7 In Chapter 4, principle and applications of optical short pulse processors as an- other example of large scale system will be shown. Integration challenges will be discussed. Then, I'll present my solution to implement large scale 128-bit spectral processing of sub-picosecond optical pulses in a standard SOI CMOS process. Sys- tem level as well as device level design, analysis and simulations with measured performance are presented. Finally, I'll conclude the chapter with suggested future work. In Chapter 5, the results of this dissertation are summarized and the future research directions are suggested. 8 Chapter 2 Silicon Photonics Process Technology 2.1 Silicon Photonics Processes Silicon photonics research has gained attraction recently because of its potential to demonstrate complex systems leveraging advancements in electronic silicon in- tegrated systems. Even though silicon photonic devices can be fabricated using commercial CMOS facilities, the majority of implementations have been done us- ing custom made process steps. The reason is that standard CMOS process steps are not necessarily optimized for photonics devices. For example, the standard etching steps used in standard CMOS process do not provide the smooth sidewalls that are needed to realize low-loss silicon optical waveguides [26]. New materials may be added to the silicon process to realize certain photonic devices and func- tions. Examples include growing IIIV materials on silicon to realize laser [34, 35], using organic materials to increase the nonlinear eects [36, 37], and adding silicon nitride for low loss waveguides [38, 39]. A few companies have tried to implement 9 photonic devices in a commercial CMOS foundary. Luxtera is one of the pioneers that fabricated complex electro-optical systems using this approach [40]. There are two dierent philosophies for realization of complex electro-optical integrated systems. In one approach, electronic and photonic functions are realized in two dierent chips each fabricated in a separate foundry. These chips are then interfaced electrically using solder bumps, wirebond, through wafer via, etc. (Fig. 2.1.a). This approach enables selecting the most appropriate process for realization of high-performance photonic and electronic functions. Alternatively, electronic and photonic functions may be realized in a monolithic chip (Fig. 2.1.b) Monolithic integration is more suitable for large-scale electro-optical system integration when a very large number of interconnects are needed and a hybrid approach does not oer reliable and low-cost solution. The main challenge in this approach is realization of high-performance photonic components in a process that is developed and optimized for high-performance electronic devices and functions. Furthermore, in the context of silicon photonics, the laser has to be implemented o the chip. It should be noted that the majority of commercial CMOS integrated circuits are realized in a bulk process. Silicon photonics requires isolating the silicon waveguide from the silicon substrate. Therefore, the majority of silicon photonics systems use silicon on insulator (SOI) wafers and corresponding processes. 10 Figure 2.1: Two main approaches, a) hybrid, and b) monolithic, to integrate electro- optical integrated systems. There have been demonstrations of CMOS photonic integrated circuits in the commercial IBM 45 nm and 32 nm CMOS SOI technologies [41, 42, 43, 44]. How- ever, in these processes, given a very thin Buried Oxide (BOX) underneath the active silicon layer ( 100 nm), the silicon handle under the waveguides and other photonic components is etched to reduce the optical loss due to the leakage of op- tical mode to the silicon substrate. A low-loss waveguide requires thick enough (micron level) cladding, e.g., silicon oxide, to avoid optical power leakage into the silicon substrate. A possible approach is utilization of an SOI wafer with thick BOX and a foundry CMOS or SiGe process to enable realization of electrical and photonic components. An example is IBM's silicon photonic platform developed in its commercial 90 nm CMOS foundry with additional process steps to enable integration of photodetectors [14]. Another example is realization of IHP's SiGe BiCMOS process on an SOI wafer [45]. Among available commercial SOI CMOS processes, IBM/GF 7RF SOI process oers thick oxide underneath active Si layer (BOX). This production process fea- tures CMOS transistors with 180 nm minimum channel length and is widely used to 11 Figure 2.2: Typical cross section of quarter-micron SOI photonics platforms: (a) passive IMEC, and (b) active IMEC and IME processes. realize RF switches for the front-end of cellular phones [46]. Passive photonic com- ponents have been reported in this process [47]. One drawback of using this process to realize optical components is the relatively high waveguide propagation loss of 1 dB/mm as compared with that of silicon photonic processes like IMEC 0.2 dB/mm. The increased loss is due to more sidewall surface roughness stemming from imperfect etching process in commercial electronics CMOS SOI processes. However, in a compact PIC, a few mm by a few mm, the advantage of having electronic may overcome the disadvantage of higher optical loss. Having photonic and electronic on the same die, potentially is enabling integration of electro-optical systems. 12 Table 2.1: Comparison of selected Silicon Photonics foundry processes. EPIXfab (LETI), IMEC, and IHP (microtechnology research and development centers in the EU) oer passive and active silicon processes in a multi-project wafer (MPW) form. Similarly, the institute of Micro-Electronics (IME) in Singapore oers silicon photonics MPW runs. The specication of some of the major silicon photonics foundries is shown in Table 2.1. 13 Figure 2.3: Cross section of IBM/GF 7RF SOI CMOS process with 4 metal layers. 2.2 IBM/GF 7RF SOI CMOS for Photonics Monolithic chips including electronic and photonic functions enable realization of complex electro-optical integrated systems. The IBM/GF 7RF SOI CMOS process oers the capability to monolithically integrate photonic and electronic components on the same die without requiring any post processing. This production process oers thick oxide underneath active Si layer that enables realization of low-loss photonic devices. A simplied cross section of the process is shown in Figure 2.3. Active silicon layer is 145 nm thick. A 165 nm thick poly silicon is being used as a gate of CMOS transistors. Available process steps like implantation and metalization can be used to realize active photonic devices such as tunable optical amplitude or phase adjusters. Multiple metal layers enable complex routing required in a large scale system. 14 We have designed and developed a photonic library of components in this process covering wide range of fundamental devices enabling realization of complex electro- optical integrated systems. The photonic devices can be categorized into two main classes: 1- Passive devices, including optical waveguide and waveguide components, ring resonators, and grating couplers, where the function is performed only in the optical domain without any tunability, and 2- Active devices, including, optical phase and amplitude modulators, and de- tectors, where the device function is tuned or enabled by electronics. In the next section, the photonic devices that have been designed and imple- mented in the IBM/GF 7RF SOI CMOS process are presented. 2.3 PhotonicDeviceDesignsintheIBM/GF7RF SOI CMOS Process 2.3.1 Passive photonics 2.3.1.1 Waveguides Waveguide is one of the most fundamental building blocks in any integrated pho- tonic system, and is used to route the optical signal on the chip. In radio frequency, microwave, and millimeter-wave integrated circuits (3GHz 300GHz), metallic transmission lines such as microstrips, coplanar waveguides, 15 and coplanar striplines may be used as the propagation medium for the electro- magnetic wave with a typical loss of 1 5dB=mm [48, 49, 50, 51]. The loss of metallic transmission lines is unacceptably high at near infrared optical frequencies (> 100THz) [52]; therefore, dielectric waveguides are often used. In SOI pro- cesses, the active silicon layer, that is isolated from the silicon substrate through the buried silicon oxide layer (BOX), can be used to create a low-loss dielectric waveguide. The optical wave is primarily conned in the silicon layer due to its higher refractive index (n Si 3:4) compared with that of the surrounding silicon dioxide layer (n SiO2 1:44). Thicker BOX layer is preferred to minimize the leak- age of guided optical mode to the silicon substrate. The intensity of optical signal outside of the silicon waveguide core drops exponentially (evanescence mode). The intensity drops by over 95% over around 300 nm distance from the edge of silicon waveguide in to the SiO 2 . Figure 2.4: Representative silicon waveguide geometry and simulated optical eld intensity within the silicon waveguide (conned mode) for the designed single mode waveguide in the IBM/GF 7RF SOI process. 16 Before considering the waveguide design in IBM/GF 7RF SOI process, an ex- ample of 1D slab waveguide is analytically solved to get an idea how dierent types of modes can be guided inside waveguide. The waveguide cross section consists of a core silicon layer with thickness of d surrounded by cladding material, SiO 2 as shown in Figure 2.5. First, transverse electric (TE) mode is considered. By deni- tion, for TE mode the E-eld components in z and x directions are zero. According to Maxwell's equation [15], nding E-eld component in y direction, i.e. E y , in all the regions is enough to nd all the H-eld components. The wave equation for E y is @ 2 E y @x 2 + (k 2 i 2 )E y = 0; (2.1) Figure 2.5: Geometry of 1D slab waveguide with silicon core and SiO 2 cladding. where k i = 2n i = and = 2n eff = are the wave numbers of each medium and guided mode respectively. For guided mode,k 2 < <k 1 in order to have sinusoidal 17 wave inside the silicon core and exponentially decaying wave in theSiO 2 claddings. The solution for E y is given by E y = 8 > > > > > > < > > > > > > : Ae kx ; 0<x Bcos(hx) +Csin(hx); d<x< 0 De k(x+d) ; x<d To nd unknown coecients, boundary conditions must be satised. Continu- ous E y at x = 0 results A =B, continuous H z = @Ey @x at x = 0 gives C =k=hA, continuous E y at x =d results D = Acos(hd) +kA=hsin(hd), and nally con- tinuous H z = @Ey @x at x =d gives tan(hd) = 2kh=(h 2 k 2 ). The last equation is a transcendental equation from which the propagation constant may be found. Considering wave number conservation, it can be proven that the nal equation to nd guided mode propagation wave numbers can be found from [15] tan(hd=2m=2) = p V 2 h 2 d 2 hd ; (2.2) for TE modes and similarly for TM mode from tan(hd=2m=2) = n 2 1 n 2 2 p V 2 h 2 d 2 hd ; (2.3) 18 where V = (2=)d p n 2 1 n 2 2 , and m = 0; 1; 2;::: is the mode number. Eq. 2.2, and 2.3 can be solved graphically for a given waveguide parameters. Assuming d = 145 nm, solving the equations shows there is only one TE and one TM mode supported with eective refractive indexes of guided mode to ben eff;TE = 2:44 and n eff;TM = 1:58 as shown in Figure 2.6 Figure 2.6: Graphical solution of transcendental equations Eq. 2.2, and 2.3 to nd guided modes of 1D slab waveguide with 145 nm thick silicon surrounded by SiO 2 at 1550 nm wavelength for (a) TE and (b) TM modes. In the IBM/GF 7RF SOI process, the thickness of silicon is 145 nm and dictated by the process; therefore, the waveguide width (W WG ) is the only design parameter. 19 Closed-form expressions for such a dielectric waveguide surrounded by inhomoge- nious material do not exist. To design the waveguide, W WG is swept to nd the range where waveguide only supports a single conned mode. For instance, Fig. 2.7 shows the eect of waveguide width on the operation of waveguide for three widths, namely, 400, 550, and 750 nm. TM mode where the E-eld is only in perpendicular direction with respect to the wafer (x axis) is un-conned for all the widths. In other words, even if a TM mode is excited, it will be very lossy. On the other hand, conned TE mode where E-eld is only in parallel direction with respect to the wafer (y axis) can exist for some widths. For small width (e.g., 400 nm), there is no conned mode. For large width, (e.g., 750 nm), waveguide can support multiple modes. Only a narrow window in between supports a single conned TE mode. In our process, this window is from W WG equal to 450 nm to 550 nm. In a dielectric waveguide, sidewall roughness is the major loss contributer. The larger the waveguide width, the smaller the overlap of the optical mode with sidewall will be. The simulated waveguide loss versus waveguide width, assuming an rms surface roughness of 7.5 nm, is shown in Figure 2.8. The mode with W WG = 550 nm has the lowest overlap with sidewalls. The loss of the waveguide is typically due to two major contributors, sidewall scattering because of roughness and plasmon dispersion free carrier loss due to background doping [19]. In the waveguide designed in the IBM/GF 7RF SOI process, the thickness of Si layer is relatively smaller compared to that of dedicated 20 Figure 2.7: The eect of waveguide width on the operation of waveguide for three widths, 400, 550 and 750 nm. For small widths, there are no conned modes. For large widths, waveguide is multi-mode. Only a narrow window in between supports a single conned mode. 21 silicon photonics processes. This will cause more mode leakage into the cladding (SiO 2 ). As a result, optical intensity overlap with sidewall roughness increases, hence makes it more sensitive to process variation. This is quantied in Figure 2.9. The IBM/GF 7RF SOI process is not optimized to minimize roughness because its primary intended application, i.e. electronics, does not require it. From the measured waveguide loss, the sidewall roughness variance is extracted to be around 7.5 nm. Figure 2.8: Simulated waveguide propagation loss versus waveguide width in the IBM/GF 7RF SOI process with 145nm silicon thickness. Assuming sidewall rough- ness variance is 7.5 nm, and background doping is 10 16 1=cm 3 ). Background doping of the silicon waveguide also contributes to the waveguide loss. In our process, this contribution is around 25% of the total loss ( 0:3dB=mm). The eect of silicon doping on waveguide loss is shown in Figure 2.10. The model to nd imaginary part of refractive index of silicon as a function of doping concen- tration is extracted from Soref's equations [19]. 22 Figure 2.9: Simulated waveguide propagation loss versus silicon thickness for two dierent sidewall roughness variances (W WG = 550 nm, and background doping is assumed to be 10 15 1=cm 3 ). Figure 2.10: Simulated waveguide propagation loss as a function of silicon back- ground doping concentration for d Si = 145nm and W WG = 550nm. 23 In order to characterize the waveguide loss, several methods can be used. In the end-cut method, waveguides with dierent lengths are fabricated. By measuring output power for a given input power at a desired wavelength, normalized output power versus length is measured. The slope of this graph is the waveguide loss per unit length. The accuracy of this method depends on the consistency of coupling the light in to and out of the waveguides (e.g., through grating couplers). The principle of this method is shown in Figure 2.11. If the waveguide loss is low, long waveguides are needed to enable loss measurements with sucient accuracy. The long waveguides are often laid out in a meandered way to save area. In these cases, the loss of bend sections within the meandered waveguide structure must be derived independently. Figure 2.11: Loss characterization principle based on the end-cut method. An interferometric structure, with uneven length waveguides in its arms, may also be used to characterize the waveguide loss. In this structure, the output optical power undergoes peaks and nulls as the input optical wavelength varies. This is due to constructive and destructive interference of the optical elds in the two branches 24 as the relative optical phase changes with wavelength. Assuming the power loss dierence between branches is , and the peak to null ratio is , it can be easily proved that = ( 1 + p 1 p ) 2 : (2.4) Figure 2.12: Loss characterization principle based on an interferometric method. In this method too, the loss of waveguide bends should be deembeded. Assuming the longer arm has N R number of U-turns with radius of R, and the total length dierence between arms to be L, the loss dierence between arms, , can be calculated as = WG L +N R R ; (2.5) 25 where WG is the loss of straight waveguide in dB per unit length and R is loss of one bend with radius of R. We fabricated dierent interferometric structures with dierent number of bends, bend radius and waveguide lengths in the IBM/GF 7RF SOI process. The corre- sponding measured results are shown in Figure 2.13. Figure 2.13: Measurement results of interferometric waveguide loss for structures with (a) 8 U-turns with radius R = 10 m, length dierence L = 2:3 mm, (b) 2 U-turns with radius R = 10 m, 14 U-turns with radius R = 5 m length dierence L = 288:04m, (c) 16 U-turns with radiusR = 10m, length dierence L = 0:504 mm, (d) 4 U-turns with radius R = 10 m, 36 U-turns with radius R = 2 m length dierence L = 320:86 m . From the peak to null information, the waveguide loss in dB per unit length and bend losses in dB per U-turn may be extracted using Eq. 2.5. The extracted waveguide loss is shown in Figure 2.14. In order to estimate the sidewall roughness of the waveguides, that is the main loss contributer, the waveguide loss for dierent 26 Figure 2.14: Extracted straight waveguide loss from interferometric test structures versus wavelength in the IBM/GF 7RF SOI process. Simulated waveguide loss for dierent sidewall roughness rms variances, c, are also shown to estimate the roughness. Figure 2.15: Extracted waveguide bend loss from interferometric test structures ver- sus bend radius for two dierent wavelengths, 1550nm (top) and 1560 nm (bottom), in the IBM/GF 7RF SOI process. Simulated loss for dierent sidewall roughness rms variances are also shown to estimate the roughness. 27 Table 2.2: Summary of measured straight and bend waveguide loss in the IBM/GF 7RF SOI process at 1550 nm. The waveguide width is 550 nm. roughness variances of 2.5, 5, 7.5 and 10 nm was simulated. The measured results match simulations with 7.5 nm surface roughness. Additionally, the extracted bend loss results for three dierent radius of 2, 5, and 10m are shown in Figure 2.15. Similar to straight loss results, the estimated sidewall roughness variance is well matched with measured result to be 7.5 nm. Figure 2.16: Chip microphotograph of waveguide test structures realized in the IBM/GF 7RF SOI process. Chip microphotograph of fabricated waveguide test structures is shown in Fig. 2.16. Light is coupled in/out of the chip using ber array through grating couplers with standard pitch size equal to 127 m. Table 2.2 summarizes the measured waveguide loss at the wavelength 1550 nm. 28 2.3.1.2 Power Splitters and Combiners Power splitters and combiners are essential components in many optical integrated systems. Three common ways to split the optical power use either directional couplers, or multimode interferometers (MMI), or Y-junction. In the rest of this section, the principle of each device is presented. Then the detailed designed and fabricated devices in IBM/GF 7RF SOI process are shown. Directional Coupler: In the discussions related to silicon waveguide, it was stated that a part of the optical mode leaks into theSiO 2 cladding. When another waveguide is placed very close to the initial waveguide, optical mode from the initial waveguide is evanescently coupled to the other waveguide. The amount of coupled power increases over the propagation direction along the waveguide; at a long enough distance, all the power is transferred from one waveguide to the other. The length that mode needs to travel to be completely transferred to another waveguide is called L . Figure 2.17 shows the principle of the operation of a directional coupler. On the cross section of two waveguides, two super modes exists. In one mode, referred to as even mode, the E-eld is identical in both waveguides. In the other mode, referred to as the odd mode, the E-eld is the two waveguides have the same magnitude and opposite phases. These modes propagates along the waveguides with slightly dierent speeds [15]. This dierence is a function of the gap size between waveguides. The smaller the gaps size is, the bigger the dierence between 29 propagation speeds will be [15]. At the beginning where all the light is inside the main waveguide, the two modes interfere constructively inside the main waveguide and destructively in the coupled waveguide. As the two modes propagate along the waveguides, because of the speed dierence, their relative phase will change. After L , the relative phase dierence will become. As a result, the modes now interfere constructively in the coupled waveguide and destructively in the main waveguide. Therefore, all the power is transferred from the main waveguide to the coupled waveguide. The coupling length, L , is hence given by L = 2(n odd n even ) ; (2.6) where n odd and n even are the refractive indexes corresponding to the odd and even propagating modes, respectively. The design procedure for a directional coupler is as follows. First, for a given waveguide cross section, the value ofL as a function of gap size (distance between waveguides) is derived from simulations. The result for the geometry of Fig. 2.18.a is shown in Fig. 2.18.b. The minimum allowable gap size in the IBM/GF 7RF SOI process is limited to 260 nm. As expected, smaller gap size results in a more compact coupler. Once L is known (for a xed gap size), any target split ratio, , can be designed by properly picking up the coupling length L c . The relation between , L , and L c is given by [15] 30 Figure 2.17: Principle operation of directional coupler as power splitter or combiner. Figure 2.18: (a) Geometry of a directional coupler in the IBM/GF 7RF SOI process. Simulation results of (b) coupling length,L , and (c)n odd andn even versus gap size, g. 31 =sin( 2 L c L ): (2.7) We have implemented directional couplers with dierent coupling lengths to realize dierent split ratios in the IBM/GF 7RF SOI process. The geometry of the device is shown in Figure 2.19.a. FDTD simulation results for coupling length equal to 18m to get 50:50 splitter shown in Fig. 2.19.b is in good agreement with the measurement results shown in Fig. 2.19.c,d. There is small wavelength dependency in the split ratio because the propagation speeds of the above mentioned odd and even modes are wavelength dependent. We measured 8% variation in the split ratio across the 40 nm optical bandwidth. Multi mode Interferometer: MMIs are interferometric devices that may be used to split or combine optical power. The principle of operation of MMI is shown in Fig. 2.20. In an MMI, the electromagnetic wave is coupled from a single-mode waveguide to a wider multi-mode waveguide region. The input optical mode excites multiple modes in the wide multi-mode region with dierent propagation velocities. As these modes propagate in the multi-mode region, the relative phases of modes changes creating a varying interference pattern. This would result in multiple peaks and nulls in the eld intensity at various locations. Figure 2.21 shows the simulated interference pattern along the propagation direction, z, in an example MMI. In one 32 Figure 2.19: (a) Geometry of the implemented directional couplers in the IBM 7RF SOI process; (b) FDTD simulation result for coupling length equal to 18m to get 50:50 splitter; (c) Measurement result shows split ratio as a function of wavelength when the coupler length is 18m; (d) Measured split ratio a a function of coupling length at = 1550 nm. 33 specic location, only two bright spots are seen, indicating equal eld intensities. That would be the optimum location for the output waveguides for a 2-way MMI- based power splitter. Figure 2.20: Principle operation of multi-mode interferometer (MMI) as power splitter or combiner. The performance of an MMI power splitter depends on geometrical parameters as shown in Fig. 2.22. Input and output waveguide widths, W i and W o , are xed, 550 nm, to be the same as single mode waveguides that have been used throughout the system and eliminate the need for additional tapers that contribute more loss. Therefore, the only parameters need to be dened are multimode region width and length, L and W , and the gap between output waveguides, W g . The objective is to come up with compact and low loss design. The design procedure is as follows: First W is xed, then the optimum length is simulated by nding the location where only two peaks are created as a result of interference of multiple modes inside 34 Figure 2.21: FDTD simulation showing the eld intensity as light from a single mode waveguide couples to and propagates in a multi-mode region. The propaga- tion speed dierence of various mode results in an interference pattern along the propagation (z) direction. Figure 2.22: Design parameters of 1 2 MMI in IBM 7RF SOI process. 35 the multi-mode region. At the same time, the optimum center to center distance between output waveguides is found based on vertical distance between two peaks as it is shown in Figure 2.21. Therefore, the insertion loss of a two-way MMI-based power splitter will only depend on W (Figure 2.23). To capture insertion loss and area of such a structure in one expression, we dene LossWL as a Figure of Merit (FOM); the lowest FOM is a suitable compromise between insertion loss and footprint. FOM is the lowest for W = 2m, L = 2:75m, and W g = 500nm (Figure 2.23). Figure 2.23: Simulated performance of a two-way MMI-based power splitter as function of W . FOM is dened as LossWL. We fabricated and characterized this device in the IBM/GF 7RF SOI process. The nal geometry together with the simulated and measured performances are summarized in Fig. 2.24. As measurement results show, the split ratio is almost equal for two outputs and at over a wide optical bandwidth, i.e. 40 nm. The measured insertion loss of this MMI is 0:3dB. 36 Figure 2.24: (a) Geometry of the implemented compact two-way MMI in the IBM/GF 7RF SOI process; (b) FDTD simulations; (c) Measurement results. Y-junction: Y-junction is a device that three waveguides are connected in a conguration that looks like a "Y" letter as shown in Figure 2.25. It may be used to split or combine the optical power. The light propagates from an input waveguide and by the time it reaches the Y-junction, because of symmetry, it has to split equally and continue to propagate in each of the output waveguides. In a simple implementation, the transition from straight waveguides may be realized as quarter circles with radius R (Fig. 2.25). There are two loss mechanism in the Y-junction, namely, the scattering loss in the junction, and the bend loss. The loss increases by reducing the device size. Similar to MMI design, the waveguide widths are xed, 550 nm, to be the same as single mode waveguides that have been used throughout the system and eliminate the need for additional tapers that contribute 37 more loss. We fabricated Y-junction with radius 10 m in the IBM/GF 7RF SOI process. The measured loss for this device together with FDTD simulation results as a function of wavelength for three dierent radius values, 2, 5 and 10 m, are shown in Fig. 2.26. Compared with the 2-way MMI that was presented earlier in this Chapter, Y-junctions have higher loss and much larger foot print. Figure 2.25: Schematic of a Y-junction as an optical power splitter or combiner. Figure 2.26: Measurement result together with FDTD simulation results of Y- junctions in the IBM/GF 7RF SOI process with dierent geometries. The main advantages of MMI compared with directional coupler for power split- ting/combining is compactness and wider optical bandwidth. Directional coupler 38 may be used when custom split ratios are needed. Both MMI and Y-junction have wide optical bandwidth; but the MMI consumes much lower footprint while oering smaller or better insertion loss. 2.3.1.3 Grating Coupler In many integrated photonic circuits, light must be coupled into and out of the chip. Specically, since a standard silicon process does not allow realization of laser, laser power must be coupled in to the silicon PIC. There are two primary coupling approaches to do this [15]. In a rst approach, referred to as an edge coupler, the coupling is done at the edge of the chip between an on-chip waveguide and an aligned ber. The light from a ber with a typical core diameter of 9m is coupled into a wide waveguide (Fig. 2.27.a). The mode size of ber on the vertical direction is much larger than the width of the silicon waveguide, i.e. 145 nm, in the IBM/GF 7RF SOI process. This results in signicant coupling loss even if a wide waveguide is used (Fig. 2.27.b). To improve the coupling eciency, a thicker silicon may be used in a costume process. Coupling loss less than 1.5 dB was reported using this approach [53]. Another drawback of edge coupler is low density when a number of I/O couplers are needed as each input/output waveguide must be routed to the edge of the chip. 39 Figure 2.27: (a) Coupling light from ber to silicon waveguide from the edge of a chip. (b) Optical eld intensity mode prole of ber (left) and silicon waveguide (right) with W = 8m at 1550 nm. (c) FDTD simulation result of coupling loss versus silicon waveguide width, W at 1550 nm. 40 In another approach, referred as a grating coupler, light is coupled almost verti- cally using a ber aligned at the top of a grating coupler [54]. Unlike an edge cou- pler, grating couplers can be placed anywhere across the chip and the input/output optical ports can be laid out as close to the desired points as needed. In grating coupler, the light propagates inside a waveguide and interfaces with a periodic structure where refractive index changes along the propagation length. Depending on the geometry and contrast ratio between the refractive indexes, light is diracted with an angle that is slightly o-normal to the surface of the chip. This is the angle where wave vectors of light inside grating is equal to wave vector component of diracted light along the propagation direction, i.e. momentums are conserved, and can be derived as [15] sin() =n eff ; (2.8) where n eff is the eective refractive index of optical mode inside waveguide, is the grating coupler period, and 0 is wavelength. The rest of the light is lost to substrate or back re ected. The principle of operation is shown in Figure 2.28. For a xed given process, the design parameters for a grating coupler are period of grating, , duty cycle of grating, f, number of periods, N, and the grating region width, W G . 41 In order to couple light from or to ber, the area of the grating coupler should match with the ber core. Single mode ber core diameter is 9m. IntuitivelyW G and N should be bigger than 9 m. Figure 2.28: Principle of grating coupler operation. In the IBM/GF 7RF SOI process, there is no available partial etch of silicon layer to create a periodic structure. However, a combination of poly silicon and active silicon layers can be used. We studied the eect of each parameter on the coupling eciency of ber to the grating coupler using 3D FDTD simulations. Figure 2.29 shows simulated eect of grating coupler period, , on the optimum coupling angle and also power coupling eciency to ber at 1550 nm wavelength. N is assumed to be 25, duty cycle f = 0:5, and W G = 10m. This shows at the wavelength of interest coupling 42 peaks at around 700 - 750 nm period that also corresponds to 15 to 20 optimum coupling angle. Figure 2.29: Simulated coupling eciency and optimum coupling angle in a grating coupler as a function of grating period at = 1550 nm for N = 25, f = 0:5, and W G = 10m. Figure 2.30 shows simulated eect of grating coupler duty cycle,f, on optimum coupling angle and power coupling eciency to ber at 1550 nm. N is assumed to be 25, period = 720, and W G = 10m. The coupling eciency peaks at around 50 % duty cycle and it drops by a few percent when the duty cycle changes by += 10%. The coupling eciency is a function of operation wavelength. The eect of wavelength is to change the normalized period of the structure. For a given set of parameters and ber angle, , coupling eciency changes as a function of wave- length. For applications like spectral optical short pulse processing that will be in 43 Figure 2.30: Simulated coupling eciency and optimum coupling angle in a grating coupler as a function of grating duty cycle at = 1550 nm for N = 25, = 720nm, and W G = 10m. Figure 2.31: Simulated normalized coupling eciency of grating coupler to ber as a function of wavelength. In this simulation, N = 25, f = 0:5, period = 720nm, W G = 10m, and = 18 . 44 Chapter 4, wide optical bandwidth helps to save active power consumption that is needed to compensate power degradation due to wavelength dependent response of optical components. Figure 2.32: Simulated normalized coupling eciency as a function of grating cou- pler size W G at = 1550nm when N = 25, f = 0:5, = 720nm, and = 18 . To achieve high coupling eciency, the area of grating coupler should be around or more than the ber mode size (9m diameter). However, increasing the area beyond the ber mode size does not improve the coupling eciency indenitely (Figure 2.32). In this simulation it can be seen that the coupling is almost un- changed for W G > 9m. Similar trend is observed for number of periods, N (Fig. 2.33). Based on optimization in the design space, the best achievable coupling eciency in the IBM/GF 7RF SOI process for this grating coupler geometry is around 33% that is achieved for W G = 10m, duty cycle f = 0:5, period = 720, and N = 25 45 Figure 2.33: Simulated impact of N on coupling eciency of a grating coupler at = 1550nm for W G = 10m, f = 0:5, = 720nm, and = 18 (Figure 2.34). The taper length has been selected long enough to add negligible loss. Figure 2.34: Layout of the implemented grating coupler in the IBM/GF 7RF SOI process that is used to couple the light between the chip and a ber. Combination of poly silicon (green) and active silicon (red) is used to create the periodic structure. To verify the design approach, we fabricated three grating coupler with dierent geometries while satisfying foundry design rules having W G = 10m, duty cycle f = 0:5, and N = 25 and dierent periods 650, 720, and 820 nm, respectively. Coupling eciency of the grating coupler is characterized in pair connected by short 46 waveguide, 250m, using a setup that is shown in Figure 2.35. Homemade ber probes with adjustable angle screw are manipulated by xyz stages. To achieve the optimum angles that maximize the coupling eciency Figure 2.36 shows measured coupling in comparison with simulation. The optimum grating coupler period is veried to be at 720 nm. The absolute numbers are o by 10 % that might be due to resolution of the xyz manipulator. Figure 2.35: Experimental setup to measure coupling eciency of a grating coupler. The eect of duty cycle on coupling eciency was measured similarly. Figure 2.37 shows that 50 % duty cycle is optimum. Summary table of measured optimum coupling eciency of dierent GC designs at 1550 nm wavelength is shown in Table 2.3. 2.3.2 Active Photonics 2.3.2.1 Variable Thermo-Optical Phase Shifter Variable phase shifters and variable amplitude controllers are two key building blocks in the realization of large scale systems like phased arrays and pulse shapers. 47 Figure 2.36: Measured optimum coupling eciency of fabricated grating couplers with W G = 10m, duty cycle f = 0:5, and N = 25 and dierent periods in the IBM /GF 7RF SOI process compared with simulations at 1550 nm wavelength. Figure 2.37: Measured optimum coupling eciency of fabricated grating couplers with W G = 10m, = 720, and N = 25 and dierent duty cycles, f, in the IBM/GF 7RF SOI process compared with simulations at 1550 nm wavelength. 48 Table 2.3: Summary table of measured optimum coupling eciency of dierent grating coupler designs implemented in the IBM/GF 7RF SOI process at the 1550 nm wavelength. The phase of an electromagnetic wave may be modied by changing the wave veloc- ity or the distance it travels. In principal, the tunability of phase is done by changing the eective refractive index of waveguide as it is shown in Figure 2.38. There are dierent mechanisms to do this, such as carrier injection or depletion in silicon using a diode structure, or using thermo-optical eect. Carrier injection/depletion based approach oers high speed operation while it is lossy and not compact [22, 55, 23]. On the other hand, thermo-optical phase shifter can be low-loss and compact [56]. In the IBM/GF 7RF SOI CMOS process, realization of carrier injection devices is nontrivial because of non-optimum available implantation levels, and unsuitable waveguide structures for modulator design while thermo-optical devices are easy to fabricate due to the ability to accurately control the local temperature. To utilize thermo-optical eect, heaters are needed. Heater can be designed to be a part of waveguide or placed as a separate element very close to waveguide. First type requires doping part of the waveguide to create a resistor. The amount of power that is needed for xed optical phase change is optimum in this case since the heat is generated inside the waveguide; however, the optical loss is big because 49 Figure 2.38: The principle of tunable optical phase shift is shown on the left side. Typical mechanisms to implement based on thermo-optical or carrier injection ef- fects are shown on the right side. of plasmon dispersion free carrier loss due to doping inside waveguide [11]. The available implantation levels in IBM 7RF SOI process are so high that the loss penalty is big. Instead, the latter approach to have a separate heater very close to waveguide can oer lower loss at the cost of worse thermo-optical eciency. In the IBM/GF 7RF SOI process, the closest possible layer to the silicon waveguide that can be used as a heater is poly silicon. The process oers doped poly silicon resistor. We used poly resistors placed very close to the waveguides while satisfying the foundry design rules to achieve the highest possible thermo-optical eciency. Design of poly silicon heaters: Doped poly silicon resistor can be used as a heater. The generated heat, as current passes through this resistor, causes self heating as well as heating of the adjacent environment (Fig. 2.39). The amount of transferred heat depends on the thermal conductivity of materials. Thermal 50 conductivity is the amount of heat that passes in unit time through a known area and thickness of a material when its other facet dier in temperature by one degree [57]. The unit is usually reported in [W:K 1 :m 1 ]. Figure 2.39: Doped poly silicon heater generates heat as electrical current ows. The generated heat is partially spent in the resistor (H s ), transferred upward (H u ), downward (H d ), and to the left (H l ) and right (H r ) sides. For the poly silicon heater case shown in Fig. 2.39, the generated heat power is transferred through three thermal conductive paths: oxide, poly and active silicon. Source heat is conducted through oxide conductivity, poly silicon conductivity, and waveguide conductivity (active silicon). The thermal conductivity of silicon is 148 [W:K 1 :m 1 ] while for oxide it is 1.1 [W:K 1 :m 1 ] [57]. It means silicon is 135 times more conductive than oxide. Therefore, most of the temperature change is happening inside poly silicon as well as waveguide that is desired. Oxide acts like thermal isolator to keep heat. 51 The temperature prole across all the materials as a function of geometry for a given burned power inside poly heater can be obtained by solving heat diusion equations. Once the temperature prole is found, thermo optical eect can be quantied. The refractive index of silicon changes with temperature following [56] n Si = 1:8 10 4 T: (2.9) The equation assumes change in the temperature is uniform across the cross section of the waveguide. In reality, the temperature has some gradient. We used commercially available tool CMOSOL to nd the temperature prole as a function of heater power in our geometries. Then, perturbation theory can be used to nd the eective change in the refractive index of the guided mode inside a waveguide [15] as n eff (P h ) = R volume jEj 2 n Si (x;y;z;P h )dxdydz R volume jEj 2 dxdydz ; (2.10) wherejEj 2 is the intensity of propagating mode inside waveguide that is found as it is explained in waveguide design section. The integral is calculated inside Matlab after extraction of temperature prole from COMSOL and optical mode intensity 52 prole from commercially available optical mode solver Photon Design. Example of simulated temperature prole across cross section of Si waveguide by burning 30 mW power inside adjacent doped poly Si heater using COMSOL software is shown in Fig. 2.40. Once eective refractive index as a function of heater power, P h , is calculated, the amount of change in the optical phase as a function of change in the heater power can be found as = 2n eff L=; (2.11) Figure 2.40: Example of simulated temperature prole across cross section of a silicon waveguide by burning 30 mW power inside adjacent doped poly silicon heater using the COMSOL software. where L is the length of the waveguide that is heated up and is the working wavelength. 53 The following rule of thumb may be used to nd the eective temperature change, T eff , needed to provide phase shift at = 1550nm over a length of L: T eff L = 4305:6[K:m]: (2.12) In short, the optical phase change is determined by the product of length and T . For instance, for T = 100 at least 43 m long waveguide is needed. To verify design methodology, we fabricated a test waveguide with poly silicon heater very close to the waveguide. The heater waveguide geometry together with test schematic and fabricated chip microphotograph are shown in Fig. 2.41. The edge to edge distance between the heater and the waveguide is set to be 500 nm to avoid doping leakage in to the waveguide that would increase passive optical loss without improving the thermo-optical eciency. We measured required heater power to give 2 optical phase shift to be 85 mW. The number is used to tune above mentioned simulation methodology for future designs. The rst generation designed heaters in this technology are not compact and power ecient. In large systems like optical phased arrays, it is required to have compact as well as ecient devices while satisfying the foundry rules in terms of geometry and current handling capability. Instead of single sided heater-waveguide conguration, meandered waveguide is used with poly silicon heaters in between 54 Figure 2.41: Fabricated doped poly silicon heater together with adjacent waveguide as thero-optical phase shifter in the IBM/GF 7RF SOI process. An MZI is used to characterize the thermo-optical eciency. 55 Table 2.4: Performance summary of the fabricated thermo-optical phase shifter at 1550 nm wavelength in the IBM/GF 7RF SOI process. as it is shown in Fig. 2.42.a. This conguration improves the thermo-optical e- ciency since each heater sees two waveguides on both sides. Heater width is picked up to be 2.34 m to conservatively satisfy 1.5 times required current that gives 2 optical phase shift. Therefore, the foot print of the phase shifter is dictated by design methodology that is experimentally veried before. Total 94.4 m-long meandered silicon waveguide in a compact footprint, 31.5m 12.4m (Fig. 2.42) achieves 2 optical phase by consuming 27.2 mW power in the heater with 1 k electrical resistance. To characterize both amplitude and phase responses of the device two types of characterization structures were fabricated (Fig. 2.43). Stan- dalone structure is used for amplitude calibration and MZI conguration is used for both amplitude together with phase calibration. Chip microphotograph of fab- ricated structures in the IBM/GF 7RF SOI process is also shown in Fig. 2.43. The measured performance of the device is shown in Fig. 2.42 using MZI congura- tion that was fabricated in the process for characterization. The performance of thermo-optical phase shifter at 1550 nm is presented in Table 2.4. 56 Figure 2.42: Variable compact thermo-optical phase shifter that is implemented in the IBM/GF 7RF SOI process; (b) Corresponding measured amplitude and phase responses as a function of burned power inside heater at 1550 nm wavelength. 57 Figure 2.43: Test structures to characterize both phase and amplitude response of the thermo-optical phase shifter (top). Chip microphotograph of fabricated struc- tures in the IBM/GF 7RF SOI process is shown (bottom). 58 2.3.2.2 Variable Thermo-Optical Amplitude Controller Thermo-optical phase tuning can be used to realize optical amplitude controller. By using variable thermo-optical phase shifter, similar to the one we introduced in the previous section in an interferometer, the optical amplitude can be tuned. The concept is shown in Fig. 2.44. Figure 2.44: Concept of variable amplitude controller using a thermo-optical phase shifter in an interferometer. Similar to the variable phase shifter, we used poly silicon resistor as heater and put it very close to one arm. In order to make the design compact, we made one of the interferometer arms longer than the other one to make sure the majority of generated heat is seen by the longer arm to increase the thermo-optical eciency. The previously designed compact 1 2 MMIs are used as splitter and combiner to build interferometer. Our designed variable compact amplitude controller is made of an Mach-Zehnder interferometer (MZI) using aforementioned compact 1 2 MMI power splitter/combiner in a total footprint of 29 m 7 m (Fig. 2.45.a). The longer arm is heated up by the poly resistor heater to create relative phase dierence between the elds of two arms that are combined constructively or destructively if phase dierence is 0 59 Figure 2.45: Variable thermo-optical amplitude controller that is implemented in the IBM/GF 7RF SOI process; (b) Corresponding measured amplitude and phase responses as a function of burned power inside heater at 1550 nm wavelength. 60 or . To characterize both amplitude and phase responses of the device two types of characterization structures were fabricated (Fig. 2.46). Standalone structure is used for amplitude calibration and MZI conguration is used for both amplitude together with phase calibration. Chip microphotograph of fabricated structures in the IBM/GF 7RF SOI process is shown in Fig. 2.46. The amplitude tunabil- ity of 16 dB is achieved with burning 14.9 mW DC power inside the heater with 1.18 k electrical resistance. (Fig. 2.45.b). The performance of the implemented thermo-optical phase shifter at 1550 nm is presented in Table 2.5. Figure 2.46: Test structures to characterize both phase and amplitude response of thermo-optical attenuator (top). Chip microphotograph of fabricated structures in the IBM/GF 7RF SOI process is shown (bottom). 61 Table 2.5: Performance summary of the fabricated thermo-optical attenuator at 1550 nm wavelength in the IBM/GF 7RF SOI process. 62 Chapter 3 Monolithic Optical Phased Array Transceiver 3.1 Introduction Optical phased arrays (OPA) have been used to create, shape and steer an optical beam. When light can be steered in a desired direction with ultra ne angular resolution, it can be used to nd the location of an object (ranging and sensing), communicate with a target receiver, or create 3D images. In fact lidar systems (light detection and ranging) have been used as one of the key sensors in today's self driving cars. Alternative approaches to steering the light beam have been bulky, expensive, or with very slow steering speed [58, 59]. In this chapter, I will rst review the principles of OPA. Relevant metrics, including beam width, steering angle range, power handling, steering speed, and beam shaping using OPA will be discussed. State of the art implementations from literature will be reviewed and challenges will be discussed. Then I will present my 63 solution with complete implementation that addresses some of the key challenges in OPA and enables scalable and large scale integration to improve the performance. 3.2 Principle of optical phased array Figure 3.1: Principle of phased array operation. By controlling the relative phase dierence between multiple coherent emitters, the far-eld direction can be changed. Figure 3.1 shows the principle of an optical phased array operation. In an OPA transmitter, light from a laser source is split and coupled into array of antennas. Ideally, the phase and amplitude of the optical signal that is fed into each of these antennas can be controlled independently. Therefore, the radiation pattern in the far-eld, that results from interference pattern of the electro-magnetic elds emit- ted by all the antennas, can be controlled and shaped. The relationship between 64 complex phase, amplitude and relative antenna positions to the far-eld pattern can be explained with a complex Fourier transform as [60, 61] E() = N X i=1 a i e 2i D sin()+i i (3.1) wherea i and i are the amplitude and phase of the optical signal at thei th antenna, D is antenna pitch, N is the number of elements, is the wavelength and is the far-eld coordinate longitudinal angle. There are two aspects of generated beam using OPA that are important and critical for system level performance: a) Beamwidth: The size of the generated beam is related to the size of the array. In order to achieve a narrow beam, the size of the array should be increased. Intuitively, this can be explained by drawing analogy between Fourier transform of a time-domain rectangle shaped pulse and far-eld of an OPA. Wider pulse duration in time domain, will result in narrower bandwidth in frequency domain. Therefore the beamwidth is inversely proportional to the size of OPA, i.e. (N 1)D. b) Steering angle range: The amount of angular range that the generated beam can be steered depends on array spacing, D. Ideally, D = =2. In this case, there is only one main beam in the far-eld; therefore, this beam can be steered across the entire 180 . For bigger spacing, there are identical images of the main beam, called grating lobes, in the far-eld. This will limit the unambiguous 65 steering range. Furthermore, presence of multiple beams creates unwanted prop- agation and interference paths in applications like free-space communication and ranging/sensing. The eect of antenna spacing on the far-eld pattern of an 8-element linear phased array are shown in Fig. 3.3. As expected, as the antenna pitch increases beyond =2, the beamwidth reduces while more unwanted image beams accrue. Fig. ?? shows the eect of number of antenna elements on the far eld pattern of a phased array with D = =2. The reduction of beamwidth with increasing the array size is evident. Figure 3.2: Simulated far eld pattern of an 8-element phased array with uniform antenna spacing (D) when (a) D ==2, (b) D =, (c) D = 5, (d) D = 20. 66 Figure 3.3: Simulated far eld pattern of an N-element phased array with uniform antenna spacing (D ==2) when (a)N = 4, (b)N = 8, (c)N = 64, (d)N = 1024. 67 It is important to note that, while only variable phase shifters can be used to form and steer the beam, variable amplitude controllers are required to create arbitrary beam patterns including multiple peaks and nulls at various directions or to suppress the sidelobes as in principle it is shown in Fig. 3.4 [52]. Figure 3.4: Principle of beamforming by controlling both phase and amplitude of each emitter of an OPA. 3.3 Background of optical phased arrays Shortly following the invention of laser in 1960, electronically-steerable laser beam was conceived to be useful in optical radars (lidars), free-space optical communi- cations with moving transmitter and/or receiver, projection television, etc. [52]. Conventionally, optical beam steering was done using either mechanical rotary mir- rors [62] or electronically controlled liquid crystals [63]. Digital light processors 68 (DLP) using tiltable miro-mirrors has been around as commercial product since 1980s (Fig. 3.6) [6].The drawback with these approaches is big size, high cost as well as slow steering speed. For instance, tuning time constant of typical liquid crystal is in the order of tens of ms [64]. More importantly, these approached are incapable of forming arbitrary beam patterns as phased arrays do. Figure 3.5: Conventional optical beam steering methods using either mechanical rotary mirrors or electronically controlled liquid crystals. Figure 3.6: Digital light processor using 10 6 tiltable micro-mirrors [6]. While optical beam steering has been around for several decades, monolithic optical phased arrays are more recent thanks to advancements in fabrication tech- nology [65, 66, 11, 67, 68, 26, 69, 70, 71]. 69 Silicon photonics has been considered to be a platform to realize OPA because of its potential to integrate dense number of components that are required for a phased array implementation. Acoleyen et al. at IMEC demonstrated a 2D array of 4 4 antennas spaced 60m apart (much more than=2 at 1550 nm) and without any phase or amplitude control capability [65]. The beam steering, 9:6 though was achieved by tuning wavelength of the laser from 1530 nm to 1570 nm since the angle of output light from grating coupler (antenna) is wavelength dependent in only longitudinal direction. Kwong et al. at UT used this approach with some improvements and presented a 1D array with 16 elements; but capable of 2D steering in a quarter micron silicon photonic platform [67]. The 16 elements are laid out with 4 m spacing. Steering of 20 15 was achieved. Thermo-optical variable phase shifters that are requiring 20 mW to provide 180 phase shift, were used for beam steering in the latitudinal direction. Wavelength tuning (1480-1580 nm) was used for beam steering in the longitudinal direction. Further improvement in steering angle was achieved by shrinking the antenna spacing in 1D conguration by Yaccobi et al. at MIT [58] where 16 antennas were placed with 2 m spacing in a quarter micron silicon photonics platform together with tunable thermo-optical phase shifters for each element. As a result, 51 steering range was achieved while consuming an average of 18 mW per element. 70 In the work of Sun et al. at MIT [11], an array of 64 64 elements consisting of a total 4096 antennas with 9m pitch was developed in a quarter micron silicon photonic platform. In this implementation, the phases of optical signals reaching the antennas are set by adjusting the waveguide lengths. Therefore, the far-eld can not be tuned. In the same work, active beam steering was achieved by incorporating thermo-optical phase shifters for each antenna in a 8 8 phased array. Due to the lack of transistors in this process, a simple electrical connection of phase shifters only facilitates controlling the entire phase shifters of a row or column at the same time; this limits the exibility in optical pattern generation. Beam steering of 6 was achieved. Each phase shifter requires 8 mW to give optical phase shift. Hulme et al. at UCSB made further improvements by taking a hybrid ap- proach where silicon photonics was used for passives, antenna and phase shifters and bonded III/V material was used for tunable laser and optical amplication to implement an integrated 321 OPA capable of 2D steering [72]. 32 elements with 4 m pitch were used for 23 3:6 2D steering. Similar to the above mentioned work at UT [67], the steering in latitudinal direction was achieved using phase shifter, here pin diode, that requires 160 mW to give optical phase shift and in longi- tudinal direction was achieved using wavelength tuning with an on-chip tunable laser. On-chip optical ampliers were used to compensate for the loss. On-chip photodiodes were incorporated to monitor the optical power for calibration. 71 Figure 3.7: 2D array of 44 elements with with no active element and array spacing of 60m. The beam steering, 9:6 was achieved by tuning wavelength of the laser from 1530 - 1570 nm. Figure 3.8: 1D array with 16 elements capable of 2D steering. Steering of 20 15 is demonstrated by using thermo-optical tuning in latitudinal direction and wavelength tuning (1480-1580 nm) in longitudinal direction. 72 Figure 3.9: 1D array with 16 antennas and 2 m spacing. 51 steering range has been reported using thermo-optical phase shifters. Figure 3.10: 2D array of 8 8 antennas with tunable thermo-optical phase shifter per element. 6 steering has been reported in both longitudinal and latitudinal directions. 73 Figure 3.11: 1D array with 32 elements and 4 m pitch achieving 23 3:6 2D steering using tunable PIN diode phase shifters and tunable on-chip laser. In all the implemented works, phased arrays are only capable to radiate an optical beam (transmit mode). Furthermore, the required control electronics was implemented using o-chip components. The antenna spacing has been over =2 and the range of required power for tuning the variable optical phase shifters is in the order of tens to hundreds of mW per element. Additionally in most applications like Lidar, it is desired to use a xed wavelength. In the next section, I will talk about some of the key challenges of integrated OPAs with possible solution for some of them. 3.4 Challengesofintegratedopticalphasedarrays 3.4.1 Scalability OPA performance improves by increasing the number of antenna elements. In particular, larger array size narrows the far-eld beamwidth and as such increases 74 the scanning resolution. Routing the optical signal as well as electronic control signals is a challenge in large-scale phased arrays. Integrated planar OPA by its nature has a passive network of waveguide struc- tures that splits and delivers the optical power into each antenna. In general, an independent amplitude and phase controller is needed for each antenna element. Typically, the size of active components are in the order of tens of m by tens of m if thermo-optical eect is used and is even bigger if carrier injection or depletion electro-optical eects are used. On the other hand, the size of antenna realized as a grating coupler can be a few m by a few m [11]. There are two scenarios to layout photonic components of a phased array. In the rst case, the antennas are placed close together, while active elements are placed further away and routed to each antenna using waveguides. Antennas can be lined up either in 1D or 2D conguration (Fig. 3.12.a and Fig. 3.12.b). In this case, antennas can be placed very close, typically down to a few m. For 1D conguration, this can give scalable solution as long as the size of the chip and required electronic can be scaled as well. The antenna pitch depends on antenna design and minimum distance that is required between antennas to avoid unwanted optical power coupling. However, this approach does not allow a scalable solution for 2D arrays. The reason is that for a given antenna pitch, there are limited number of waveguides that can be placed in between antennas. Adjacent waveguides require minimum gap in between to avoid optical coupling as discussed in Chapter 2. 75 Electrical routing is not an issue here since the active components can be placed far enough and multiple metal layers, available in silicon processes, may be used to connect the optical components to control electronic. Figure 3.12: Dierent architectures to layout OPA elements: localized antennas only where active elements are placed further away and routed using waveguides in a (a) 1D conguration or (b) 2D conguration. (c) Localized antennas and active elements within a cell. Power is delivered to each cell using a scalable passive distribution network. In a second scenario, the three main optical elements, i.e., antenna, phase shifter and amplitude controller, are localized in a unit cell. Optical power is delivered to the cells using a scalable passive network as it is shown in Fig. 3.12.c. The challenge here is to design very compact active elements to reduce antenna pitch as much as possible. At the same time, active performance of each cell should be isolated from other cells. This is particularly important when thermo-optical elements are used and thermal cross-talk can accrue among adjacent elements. Furthermore, electrical routing that is required to connect active components to the control electronic circuitry might not be scalable. For instance, the width 76 of metal interconnect is set by the required current handling that it must carry. Typically in CMOS processes, the top metal layers are thicker and can handle much more current. But, at the same time, these top metal layers require more line-to-line spacing. This limits the number of electrical interconnects that can be routed to the 2D array. The more number of metal layers available in the process, the more active components can be routed independently. One alternative might be to incorporate the control electronics local to each unit cell. However, the footprint of high-current driver electronics is not compact since it requires large transistors. This will increase the size of each unit cell and hence the antenna pitch, which in turn reduces the unambiguous steering angle. In summary, fully scalable solution for integrated planar OPA is still a challenge and requires process modication to enable 2D photonic routing as well as high current multiple metal layers. 3.4.2 Antenna pitch The size of photonic components compared with wavelength is large and makes it very challenging to shrink the antenna pitch to =2 even if only antennas are localized. On the antenna size, plasmonic structures can be used to further re- duce the size at the cost of higher loss [73]. These structures require using special types of metals, such as gold and silver that are not typically available in CMOS or silicon photonic processes [74]. Furthermore, coupling the optical signal from 77 silicon waveguidesinto plasmonic structures is challenging since the modes in the two structures are not matched. On the active devices though the challenge is much more. The thermo-optical electro-optical physics to tune optical phase or amplitude are typically weak eects. For instance, the change in refractive index of silicon is 1:8 10 4 per 1 C, or it is in the order of 10 3 for 1 V forward bias in carrier injection based devices. The situation is even worse for reversed biased based devices. Resonator based devices can oer more compact solutions; however, they typically require same order of power consumption to tune resonances across a wide range to compensate for process variation and temperature gradients. Using other physics that can be found in other materials can improve device size and power, but not necessarily the size. For instance, the Franz Keldysh eect [75] in Germanium material can change the amplitude of light with a small power consumption; but, still requires tens of m long device to give reasonable amplitude tunability [76]. 3.5 Monolithic optical phased-array transceiver in a standard SOI CMOS process 3.5.1 Introduction The generic block diagram of an optical phased array transceiver is shown in Figure 3.13. The choice between passive or active beam-forming components is primarily 78 dictated by the availability of optical gain and the loss of passive components in the technology platform of choice on the other hand, optical phased arrays that can be realized in standard CMOS processes, with inferior performance of optical components and availability of electronic components, may be more likely to be suitable for cost-sensitive commercial applications. Figure 3.13: Schematic of a basic optical phased array transceiver. Therefore, we demonstrate a monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic cir- cuitry that is tightly integrated with the nanophotonic components on the same substrate using a commercial foundry CMOS Silicon on Insulator SOI process [26]. The monolithic phased arrays chip includes 8 8 elements where each element consists of a thermo-optical tunable phase shifter, a thermo-optical tunable atten- uator, a radiating grating coupler acting as a nanophotonic antenna, and dedicated control electronics realized using CMOS transistors with 180 nm minimum chan- nel length. Optical switches enable receiving and transmitting functions as well 79 as built-in array calibration modes (not implemented in our prototype). The com- plex chip includes over 300 distinct optical components and over 74,000 distinct electrical components. 3.5.2 Optical phased array transceiver The OPA includes 64 radiating elements in a uniform two-dimensional conguration with independent amplitude and phase control of the optical eld at each element. The small wavelength of optical frequencies, 1550 nm in our demonstration, dictates small size for each unit element to reduce the unwanted grating lobes in the far- eld radiation pattern. The tunable optical phase shifters and attenuators are local to each unit element in a compact layout to ease the light distribution (Figure 3.14). Control electronics for all the tunable components are integrated on the same chip at a distant location from the optical array, and the control electrical signals are routed to the array elements using the available metal lines in the CMOS process. Independent control of phase shift and amplitude of optical eld at each element enables creation of arbitrary radiation patterns and removes the necessity for precision matching between elements in a large array. The realized optical phased array is a transceiver in that it can radiate the light with desired patterns in the transmitting mode and receive the light incident to the array at the desired directions. 80 Figure 3.14: (a) Schematic of the 8 8 monolithic OPA transceiver with indepen- dent amplitude and phase control at each element. In the transmit mode, the laser light is coupled in to the input Grating Coupler (GC) and delivered to each of the 64 antennas using silicon waveguides. In the receive mode, the impinged light on the optical phased array, after being collected and processed by each element, is combined into one eld and is sent out through the output GC; (b) Chip micropho- tograph of the fabricated optical phased array transceiver in the IBM/GF 7RF SOI process featuring over 300 distinct optical components and over 74,000 distinct electrical components; (c) Close-up view of the Optical Phased Array core consist- ing of 64 optical variable phase shifters, 64 optical variable attenuators, 64 optical nano-antennas, and 128 metal lines routing the control signals from the on-chip electronic circuitry to the optical core; (d) Close-up view of a unit optical element consisting of a variable phase shifter, a variable attenuator, and a nano-antenna. 81 The OPA transceiver is fabricated in the IBM/GF 7RF-SOI commercial CMOS process without any additional post processing. Photonics capabilities in this pro- cess has been studied with a list of photonic devices including detailed design and measured performance in Chapter 2. Additionally nano grating coupler to serve as optical antenna has been designed considering available process features. The details of this device is presented in the following sections. In the transmitting mode, laser signal is coupled into the chip through a larger grating coupler, routed to all 64 elements using silicon waveguides and directional couplers, and consequently reradiated following a desired pattern as a function of elements' phase shift and amplitude settings. Directional couplers are judiciously designed to deliver almost equal optical powers to all 64 elements. The detailed design of optical power distribution network is shown in the following sections. After fabrication, slight mismatches in the optical powers delivered to array elements are observed due to common fabrication tolerances. This small nonunifor- mity in optical power delivery to array elements is well within the range of optical amplitude control that is independent at each element. In the receiving mode, an- other large grating coupler is used to transfer the optical signal that impinges on the array, after being collected and processed by each element and then combined into one eld, o the chip. The measured coupling eciencies of these larger grating couplers are 30% (Chapter 2). Mach Zehnder Interferometers (MZI), realized with two 50-50 directional couplers as power splitter/combiner with one active heater on 82 top arm, are used as optical switches to route the light into the desired waveguides. The heater changes the phase shift of the optical eld due to the thermo-optical eect, and results in constructive (switch ON) or destructive (switch OFF) com- bining of the optical eld in two arms by providing 0 or phase shift dierence in the two arms. The heater is implemented using the poly-silicon layer that is typically used as the gate of MOSFETs in the commercial CMOS process. We used p-doped PC as heater and placed it very close to optical silicon waveguides with 0.5 m edge-to-edge margin to avoid unwanted doping leakage into the main waveguides that would have in turn increased the optical propagation loss. The measured electrical resistance of the heater is 814 . The heater requires 14.2mW electrical power to provide phase shift in the optical eld. The electrical current used to heat-up the PC heater is controlled by a programmable electrical 7-bit Digital-to-Analog Converter (DAC) that is implemented on the same chip using MOSFETS with 180 nm and 250 nm channel lengths with detailed design that is presented in the following sections. One such optical switch, with a measured isolation of 30dB, separates the array from input and output grating couplers in transmit and receive modes respectively (T/R Switch). Same optical switch is used to send light into the individual array elements in a calibration mode. 83 3.5.3 Design of nano grating coupler as optical antenna Antenna plays a key rule in the performance of OPA. The far eld radiation pattern of an OPA is the multiplication of the far eld of an individual antenna to the array factor [11]. While the far eld of an individual antenna is xed, but it shapes the envelop of far eld of the OPA and the array factor is related to the emitting phase and amplitude of all the elements in the array. Ideally, each antenna should be omni-directional so that interference pattern may be created in all the directions. The design objectives in antenna design are high radiation eciency, wide radiation beamwidth, and compact size. As presented in Chapter 2, grating couplers can be used to emit light in or out of the chip. The grating coupler design that was presented before for IO purposes, i.e. coupling from ber, is not desired here since it occupies a large footprint. Moreover because of its large footprint, the far eld radiation pattern is relatively narrow. Instead, we used a focusing grating coupler design to realize a very compact antenna. Figure 3.15: Schematic of a focusing grating coupler that consists of an input waveguide, a taper region and a grating region. Gratings are curved in such a way that the center of optical mode of input waveguide is at the focusing point of the curved grating. 84 The focusing grating coupler is implemented by curving the grating lines [77]. The light that propagates in an input waveguide enters a taper region that expands the optical mode before reaching the grating (Fig. 3.15). The grating lines are curved in such a way that the center of optical mode in the input waveguide is located at the focusing point of curvatures. To design the focusing grating coupler, we applied the formulas presented in [78] as N =zcos()n eff p y 2 +z 2 (3.2) whereN is the number of grating periods, is the optimum angle of grating coupler that light comes out (similar to what was discussed in Chapter 2 for IO GC), and n eff is the eective refractive index of optical mode inside waveguide, here it is 2.1. Similar to the previously-mentioned large grating coupler, the grating material is poly-silicon that is available in the process. To satisfy the process design rules, the grating curvatures were approximated with polygons. All the design optimization and simulations were done post layout. The optimum is related to grating period and grating linewidth and a design degree of freedom. We designed it to be 20 , slightly o-normal to ease the mea- surements. This value requires grating period to be 700 nm and grating linewidth to be 350 nm. The radiation eciency does not improve indenitely with the in- creasing number of periods. In fact, nearly all the power is radiated within the rst 85 5 periods. A narrower grating coupler width gives wider beamwidth in far-eld. This is because Fourier transform relationship between antenna aperture size and far-led radiation pattern. However, a narrow grating coupler has lower radiation eciency. For width less than 1 m, the eciency is degraded quite a lot as it is shown in Fig. 3.16. The eect of taper length is diminished above 380nm. The above considerations would result in the nal designed geometry that is shown in Fig. 3.17.a. FDTD simulation results of the designed grating coupler are shown in Fig. 3.17.b and .c. Figure 3.16: Simulated eect of grating coupler width (W a ) and taper length on the upward radiation eciency at 1550 nm wavelength. 86 Figure 3.17: (a) Schematic of designed focusing grating coupler in the IBM/GF 7RF SOI process. FDTD simulation result of (b) near-eld and (c) far-elds. 3.5.4 Designofpowerdistributionnetworkfor88optical phased array During transmit mode of the optical phased array, the optical power is distributed through a passive network consisting of waveguides and power splitters. Two types of architectures can be conceived here. A tree based approach where 1 2 power splitters are used to create 1N 2 = 2 m power splitter network or a directional coupler based approach with adjusted coupling ratios as shown in Fig. 3.18. Tree based approach requires waveguide routing in between antennas and is not scalable. Directional coupler based approach oers scalable solution [11] for a given cell size. It can also create any customized power distribution coecients by 87 Figure 3.18: Dierent architectures to distribute optical power from input waveg- uide to N 2 = 2 m elements: (a) tree based approach by using 1 2 power splitters and (b) scalable approach using directional couplers with adjusted coupling ratio. 88 adjusting the length of each directional coupler. For instance, this technique was used to passively create and distribute Gaussian power levels to a 8 8 optical phased array to reduce far-eld sidelobes [58]. Figure 3.19: Schematic of a network to uniformly distribute optical power to all cells of an 8 8 optical phased array. The objective is to deliver power with a predened pattern, usually uniform, to all the cells. Figure 3.19 shows schematic of such power distribution network. In order to facilitate array calibration, we designed the network to have power residues left at the end of main bus and row waveguides to feed to monitor photodiodes. For a 8 8 network, this means if we start with 81 unit power at the beginning, we end up with one unit delivered to the 64 cells, 9 units at the end of main bus, and one unit at the end of each row waveguide (Fig. 3.19). From the couplers between the main bus and row waveguides, we used low loss bend (5 m radius) whereas in the couplers between each row waveguide and unit 89 Figure 3.20: Simulated coupling ratio of directional couplers with dierent coupling lengths as a function of wavelength form each row to corresponding cells. cells we used sharper bend (2 m) to minimize the cell size. For the same target coupling ratio, low loss bends reduce the required coupling length a little bit because of the smooth change of bend curvature compared with sharp bend. To nd the coupling lengths L 1 to L 8 and D 1 to D 8 , FDTD simulations were conducted to get the coupling coecient versus wavelength for dierent coupling lengths, from 6 m to 22 m (Fig. 3.20 and 3.21). For a xed wavelength, in our demonstration 1550 nm, we created a look up table to nd the necessary coupling length for target couplings. The nal extracted target coupling lengths to work at 1550 nm are also shown in Tables 3.1 and 3.2. 90 Figure 3.21: Simulated coupling ratio of directional couplers with dierent coupling lengths as a function of wavelength form the main bus to the rows. Table 3.1: Target coupling ratio for 8 cells together with extracted optimized cou- pling lengths to work at 1550 nm form the rows to the corresponding cell waveg- uides. 91 Table 3.2: Target coupling ratio for 8 cells together with extracted optimized cou- pling lengths to work at 1550 nm form the main bus to the row waveguides. 3.5.5 Programmableelectrical7-bitDigital-to-AnalogConverter and heater driver in the IBM/GF 7RF SOI Process In order to drive the poly silicon heaters, current driver circuitry controlled by 7- bit programmable digital-to-analog converter (DAC) are realized in the same chip using MOSFETS with 180 nm and 250 nm channel lengths. The schematic of the driver circuitry is shown in Fig. 3.22. It consists of two main blocks, namely, a 7-bit programmable DAC and a high-power driver stage. Binary weighted current steering DAC scheme is used to generate controllable currents by copying and multiplication of reference current, I ref , that is generated to be independent of fabrication process, temperature, and supply voltage varia- tions. I ref is generated using bandgap reference circuitry [79]. It uses bandgap voltage of silicon as a very accurate reference voltage and converts it to 1 A cur- rent. It is important that DAC operation to be least sensitive to process tolerances. 92 Figure 3.22: Schematic of poly silicon heater driver circuitry consisting of a 7-bit programmable DAC and a high-power driver stage. 93 Figure 3.23: Layout of the 7-bit DAC using segmented MOSFETs. Dummy MOS- FETs are placed to increase the uniformity of DAC transistors. The design criteria was that the percentage change of the LSB current to be one tenth of DAC resolution, or = I I < 0:1 1 2 7 : (3.3) Given the process tolerance values of the IBM/GF 7RF SOI process, such a transistor must have a minimum area of 18 m 2 . Considering current handling and compactness of the layout, W is picked up to be 2 m and L to be 10 m. The uniformity of DAC operation is layout dependent. Segmented DAC layout is one eective way to minimized process non-uniformity across dierent transistors of DAC [80]. Layout of the entire DAC designed in the IBM/GF 7RF SOI process with foot print 60 m 170 m is shown in Fig. 3.23. 94 Figure 3.24: Schematic of one bit digital program circuitry using shift registers. Programmed bits, b 0 to b 6 , are set using digital shift registers available in the process development kit (PDK) library of the process. Figure 3.24 shows schematic of one bit digital program circuitry using shift registers. 00 Data in" is buered to the rst shift register ( ip- op) during each rising edge of clock signal and is serially moving to the next bit shift register. A copy of this signal is passed through to an other shift register to get loaded and programming the DAC bit on the rising edge of load signal. Driver circuitry consists of double stacked transistors to handle large voltage swings necessary to deliver up to 100 mW to each thermo-optical heater. The IBM/GF 7RF SOI process oers thick-gate oxide transistors with 5 V breakdown voltage; but, this voltage is not sucient to deliver the required power to resistive heaters. Two transistors are stacked and biased properly to enable almost twice breakdown voltage swing, i.e. 10 V, across the load. This means that for heater with 1 k resistance, up to 100 mW power can be delivered. Figure 3.25 shows 95 Figure 3.25: Schematic of the driver stage using double stacked high break-down transistors to deliver up to 100 mW to the heater. schematic of driver stage. The DAC current,I DAC is mirrored to set the gate voltage (V c ) of the bottom driver transistor (M 1 ) through diode connected transistor M c . If the control voltage,V c is small,M 1 turns o and forcesM 2 to be turned o as well. Therefore, the heater current, I h , is almost zero. When V c is high enough to turn onM 1 , the voltage drop across M 1 andM 2 drops to small saturation voltage, 0:2 V , forcing heater to draw maximum current. Gate voltage of M 2 , V b , in our design is set to xed 5 V to support this operation. The size of M 1 andM 2 are set to handle 10 mA of current while satisfying recommended PDK current handling requirement. Figure 3.26 shows simulation result of delivered power to heater as a function of DAC output current (I DAC ) for two dierent V DDdriver values, 6.5 V and 10 V. Heater resistance is assumed 1k . The range of delivered powered can be adjusted by changing V DDdriver . 96 Figure 3.26: Simulated delivered power to heater as a function of DAC output current (I DAC ) for two dierent V DDdriver values, 6.5 V and 10 V. Layout of complete control electronic to drive one heater is shown in Figure 3.27. It consists of 7-bit programmable DAC including shift registers and driver stage. The total foot print is 170 m 160 m. The presented circuitry is the base circuitry to control each heater that is used in the OPA. There are 129 heaters, 64 for phase shifters, 64 for attenuators and 1 for the TR switch that need to be controlled independently. The heater control circuitries are connected in parallel electrically throughout the chip occupying area of 3:8 mm 2 . 3.5.6 Array elements and calibration Each array element consists of a tunable thermo-optical attenuator followed by a tunable thermo-optical phase shifter that is coupled into a nanophotonic antenna. 97 Figure 3.27: Layout of complete control electronic to drive one heater. It consists of 7-bit programmable DAC with driver stage. The total foot print is 170 m 160 m. 98 The detailed design with measured performance of each individual device is shown in Chapter 2. The overall passive optical loss inside each array element that is 3 dB before radiation is mainly due to the sharp bends and waveguide sidewall roughness. Figure 3.28: Routing of the control lines from the electronic circuitry to the 8 8 optical phased array transceiver, using top-level metalization, is shown. The common electrical terminal of all the 128 thermo-optical heaters are connected together using bottommost metal lines. Built-in performance monitoring and calibration is essential in large-scale arrays. This is particularly true in optical arrays operating at short wavelengths where small fabrication mismatches lead to signicant changes in the radiation pattern. In this demonstration, the residues of optical power at the end of the main bus, 11% of the coupled input, and each row, 1.2% of the coupled input, are fed into on-chip schottky photodiode power monitors. The photodetectors are designed based on 99 p-doped silicon and Tungsten schottky interface with measured responsivity of 1 mA/W at -1 V reverse bias and minimum detectable power equal to 1.5 W . This low responsivity is sucient for monitoring the powers needed for array calibration. Since silicon is transparent at wavelength 1550 nm, schottky junction is used to lower down the band-gap energy (Schottky barrier) [81] to around 0.45 eV which is below the photon energy 0.8 eV. This increases the probability of photon absorption. Germanium, available in some commercial CMOS processes (not available in our process) as the additional doping for the source/drain regions of PFETs for strain engineering, can be used to enhance the responsivity [82, 24]. The detailed design and performance of the monitor photodiode is presented in Appendix A. The monolithic optical phased array transceiver has a total of 129 independent heaters, 64 for phase shifters and 64 for attenuators, and one for the front-end optical switch, that must be controlled independently. One terminal of all the heaters are connected electrically to a common terminal using the three bottommost available metal layers (bottommost copper and other two aluminum), and the other terminals are routed independently to the designated driver circuitry using the topmost available metal layer (aluminum). This topmost metal layer is 4 m thick and 2 m wide, and requires a minimum line-to-line spacing of 2.8 m due to the lithography limitations. Commercial CMOS processes require a near uniform distribution of metal layers for consistent Chemical Mechanical Polishing (CMP). All the routing is done judiciously to minimize the eect of metal lines on the optical 100 devices while satisfying the foundry metal density requirements. The control circuit is connected to the heaters via the aforementioned metal interconnects (Fig. 3.28). The 16 dB range for the tunable optical attenuators and the 2 range for the tunable optical phase shifters require a maximum voltage swing of 6 V that is well within the designed value. The chip is programmed serially through a computer using clock, reset, and load signals. 3.5.7 Antenna pitch The center-to-center spacing between antennas is determined based on the following considerations. 1- Thermal cross-talk between adjacent active elements: we conducted simulations to make sure how much heat is leaked from one heater to the adjacent one based on distance. In order to have less than 1 optical phase change when phase shifter heater is driven at the maximum power ( 27 mW ), at least 12 m edge-to-edge distance is needed for adjacent phase shifter heaters. A minimum edge-to-edge distance of 5 m is needed for adjacent attenuator heaters to result in less than 0:1dB amplitude change due to thermal cross-talk. 2- Metallization: As explained in the array metallization section, top metal layer requires minimum linewidth of 2m and line-to-line spacing of 2:8m. There are 128 metal lines that are needed to be routed from OPA core and it is only 32 101 spacing on the perimeter of OPA between edge cells. Therefore, the cell pitch should be big enough to make sure at least 4 lines can be routed in between antennas. 3- Metal excluded area: There must be metal excluded area at the top of antennas to avoid disturbing the radiated optical eld. We run FDTD simulations to nd the area of metal exclusion. As it is shown in Fig. 3.29, a conservative area of 12 m 6 m has been excluded from metal at the top of antenna. 4- Cell-to-cell waveguide clearance: There must be enough clearance be- tween two adjacent cells to avoid optical power leakage between waveguides. We considered slightly conservative number of 1:5m. Figure 3.29: Layout of unit cell with related geometries. 102 Considering all of these, we came up with center-to-center spacing of array elements to be 33 m in both dimensions. This value limits the unambiguous scanning range (limited by unwanted image lobe) to 1:6 . 3.5.8 Scanning speed In many applications the optical beam steering speed is an important specication. In an optical phased array, the beam steering speed depends on the tuning speed of each individual active element. Carrier depletion based modulators operate at tens of GHz speed albeit with very large footprint while compact thermo-optical devices have couple of KHz electrical bandwidth. To measure the speed of the active devices in our phased array, a thermo-optical attenuator with exact design and layout that is used for each array cell is fabricated individually with IO grating couplers to couple light in or out (Fig. 3.30). Figure 3.30: Experimental setup to measure the speed of an implemented integrated thermo-optical attenuator. 103 The laser wavelength is set at quadrature where the device response has the most linearity and sensitivity. To nd the quadrature point, rst the wavelength is swept while there is zero volt across electrical terminals of the device, and output power is recorded. The response is normalized to input power. Figure 3.31: Measured normalized output power of attenuator vs wavelength while it is driven by zero volt to nd quadrature point. Measured normalized response is shown is Figure 3.31. The closest quadrature wavelength to phased array working wavelength, 1550 nm, is obtained at 1554.2 nm. The laser wavelength is xed at quadrature. The device is driven with a pulse waveform having 1 s rise time, period of 500 s, and 200 mV voltage swing that is much smaller than the V of the device. V is extracted from the amount of power that is needed for full attenuation swing of the device. Based on measured result that is presented in Chapter 2, 14.9 mW across 1.18 k is needed for full attenuation swing that gives V = 4:19V . The modulated output optical power is detected using a fast photodiode with 10 GHz speed that is connected to transimpedance amplier with gain of 500 . 104 Figure 3.32 shows the normalized thermo-optical attenuator time response together with the input drive voltage waveform. The rise and fall times are extracted to be 39 and 40.5s, respectively. Assuming single pole response, the extracted thermo- optical bandwidth will be: BW = 1 2 = 3:93KHz: (3.4) Figure 3.32: Measured input and output time-domain waveforms of the imple- mented thermo-optical attenuator. 105 3.5.9 Experimental results 3.5.9.1 Operation of optical phased array in the transmit mode The performances of individual optical components, namely, the tunable optical phase shifter, the tunable optical attenuator, the grating couplers, and the nano- photonic antennas were individually characterized in stand-alone structures concur- rently fabricated in the same process. Array measurements, in the transmit mode, are conducted in near and far elds as the chip is placed on a temperature-controlled chuck using a measurement setup that is shown in Fig. 3.33. Figure 3.33: Measurement setup to measure near-eld or far-eld of the optical phased array. The captured image from an infrared camera is fed back to a process- ing and programming unit (personal computer) to adjust the phase and amplitude settings. 106 Figure 3.34: A representative phase and amplitude prole of an uncalibrated optical phased array (left), and the corresponding uncalibrated far-eld radiation pattern (right). Due to the inevitable fabrication process variations and mismatches as well as the nonuniform temperature prole across the optical phased array chip, the ampli- tude and phase values of dierent elements are unequal even for the same nominal settings. Figure 3.34 shows the measured far-eld image of the un-calibrated OPA in the transmit mode when all the elements have the same nominal amplitude and phase settings. The actual relative phase and amplitude values, derived after a calibration process to be discussed, are also shown in Fig. 3.34. The amplitude values for each setting can be directly measured in the near eld and calibrated as the eld emanating from each element does not interfere with those of others. Far eld measurements are used to extract the phase information. Initially, the amplitudes and phases of all the array elements, for all programmable amplitude and phase settings, are characterized and stored. The algorithms that are used to calibrate all the amplitude and phase settings are shown in Fig. 3.35 and Fig. 107 3.36, respectively. The stored values are later used to create the desired near and far-eld optical elds and radiation patterns. Amplitude measurements, for initial characterization, are conducted in near-eld. Phase measurements, for initial char- acterization, are conducted in far-eld and in pairs. The interference pattern of two radiating elements in far-eld, while no other element is radiating as all other attenuation levels are set to be at maximum, is indicative of the relative optical phases. It is important to note that the phase measurements are conducted for all the attenuation levels as the changes in the tunable optical attenuators aect the optical phase as well. After the initial measurements, a complete lookup table including the relative phases of all the elements for every possible amplitude setting is created that is used to create arbitrary near and far eld patterns. After array calibration some examples of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the correspond- ing amplitude and phase prole settings are experimentally obtained and compared with simulations. Figure 3.37 shows far eld of focused beam generated by uniform phase and amplitude proles with 12 dB peak to rst side-lobe ratio. Figure 3.38 presents how Gaussian amplitude prole and uniform phase prole can create a wider far-eld main lobe with 11 dB side-lobe suppression compared with uniform amplitude prole. In Fig. 3.39 and 3.40 the main beam generated with Gaussian amplitude prole is steered 1:6 to the edge of each interference order in horizontal 108 Figure 3.35: Algorithm to measure the response of each variable optical attenuator in the optical phased array. 109 Figure 3.36: Algorithm to measure the relative phase response of variable amplitude and phase shifters in the optical phased array. 110 and vertical directions by progressing phase shift between columns and rows, re- spectively. And nally, Fig. 3.41 shows far-eld image nearly resembling a straight line that is created by setting proper amplitude and phase proles. Figure 3.37: Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the corresponding amplitude and phase prole settings; Far eld of focused beam generated by uniform phase and amplitude proles shows 12 dB peak to rst side-lobe ratio. Figure 3.38: Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the corresponding amplitude and phase prole settings; Gaussian amplitude prole and uniform phase prole create a wider far-eld main lobe with 11 dB side-lobe suppression compared with uniform amplitude prole. 111 Figure 3.39: Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the corresponding amplitude and phase prole settings; The main beam generated using Gaussian amplitude prole is steered 1:6 to the edge of each interference order in horizontal direction by progressing phase shift between columns. Figure 3.40: Example of generated near- and far-eld radiation patterns using the optical phased array in the transmit mode with the corresponding amplitude and phase prole settings; The main beam generated using Gaussian amplitude prole is steered 1:6 to the edge of each interference order in vertical direction by progressing phase shift between rows. 112 Figure 3.41: Example of generated near- and far-eld radiation patterns using the OPA in the transmit mode with the corresponding amplitude and phase prole settings; Far eld image nearly resembling a straight line is created by setting proper amplitude and phase proles. 3.5.9.2 Operation of optical phased array in the receive mode A ber with angle 20 with respect to the normal axis of the optical phased array is placed far enough to create a plane wave impinging on the monolithic opti- cal phased array (Fig. 3.42). Each array element collects a portion of the impinged light through a nano-photonic antenna, modies the amplitude and phase through the tunable optical phase shifter and attenuator, and feeds the processed light to a combining waveguide. The total collected eld is detected through another ber located at the top of the output grating coupler. The received optical eld by each antenna is coupled to a row waveguide through a directional coupler. Optical termi- nation is used at the input waveguide of the coupler to dissipate the received power residue and eliminate the unwanted re ections. The coupling regions are designed judiciously to ensure near-equal power transfer from each element to the combining waveguide bus. To show the spatial selectivity of the optical phased array in receive 113 mode, a three-step experiment was performed. First, phases and amplitudes of all the cells were measured and calibrated similar to what the approach in the transmit mode. To calibrate the amplitudes, all the tunable optical attenuators were set to the maximum attenuation levels; then, by detecting the received power from only one cell, the amplitude response of that cell is calibrated. Phase calibration is done sequentially in pairs when the attenuation levels of all elements, except for two, are set at their maximum values. The power of the ber-coupled laser is around 15 mW at 1550 nm wavelength. The peak measured received power at the output ber after phase and amplitude calibration, when all the array elements are in phase, is around 65 W . Therefore, the total ber-to-ber loss is measured 23.6 dB. The loss breakdown is 5.6 dB coupling from input ber to the chip, 15 dB on-chip loss, and 3 dB from chip to output ber. In the second step, after amplitude and phase calibration, the attenuations and phases are set so that all elements (1) contribute the same amount of optical power to the combining waveguide, and (2) adjust the phase so that all the optical elds coupled to the combining waveguide are in phase. This ensures that maximum power is received at the specied incident angle. In the third step, in order to demonstrate optical phased array rejection of signals at unwanted incident angles, the phase shift settings of all the elements with odd column number are changed by 180 while all other settings remain intact. It is expected that, in this new setting, the eld collected by 32 elements (odd columns) will cancel the eld collected by the other 32 elements (even elements). The output 114 eld in this new setting (null of the spatial pattern) is measured to be around 2.3 W that is 14.5 dB below that of the original setting (peak of the spatial pattern). This measured peak to null ratio depends on the mismatches of array elements (especially in null extraction). Figure 3.42: (a) A ber with angle with respect to normal axis of OPA is placed far enough to create an impinging plane wave on the OPA. Each nano-photonic antenna collects a portion of the incident eld, adjusts its amplitude and phase, and couples it to the combining waveguide. The total collected eld is detected through another ber located at the top of the output grating coupler; (b) Received eld by each nano-photonic antenna is coupled to the combining waveguide through couplers judiciously designed to ensure near-equal coupled signal values across the array. Optical termination is used to dissipate the received power residue and eliminate the unwanted re ections. 115 3.6 Conclusion Large-scale optical phased arrays can be realized in commercial foundry processes. The choice of process technology depends on the target application. For instance, in ranging and positioning applications, such as Lidars envisioned in self-driving cars, the requirements for form-factor, scanning speed, and system cost are less stringent than the performance as determined by the transmitted optical power and receiver sensitivity. In these systems, a two-chip solution where an photonic chip includes low-loss high-performance optical components and an electronic chip includes beam-steering control and signal processing functions may be better. On the other hand, in certain consumer applications where form-factor and cost are major drivers, single-chip solution may be preferred. On the technical side, the ma- jor challenge are realization of optical phased arrays at other (especially shorter) wavelengths, reducing the spacing between array elements to near half-wavelength, reducing the power consumption, increasing the array size, reducing the optical loss, and incorporating on-chip array self calibration algorithms. Table 3.3 shows per- formance of the work presented here compared with selected published integrated planar optical phased arrays. 116 Table 3.3: Comparison table between selected published integrated planar optical phased arrays and the presented work here. 117 Chapter 4 128-bit Spectral Processing of Sub-picosecond Optical Pulses in a Standard SOI CMOS Process 4.1 Introduction Optical short pulse processing plays a key role in wide range of applications includ- ing optical code division multiple access networks [83, 84], optical secure commu- nication [85, 86, 87], optical pulse shapers [88, 89, 90, 91, 92, 93]. Figure 4.1 shows the schematic of a generic spectral processor for short opti- cal pulses occupying large optical bandwidth [94]. A rst block separates frequency contents of the optical pulse into multiple wavelengths. The amplitude and phase of each wavelength component is then adjusted independently. A nal block recom- bines these amplitude-and-phase adjusted wavelength components in to a single optical eld. The shape of output waveform depends on the amplitude and phase settings. The wavelength separating and combining blocks may be realized as a 118 prism, diraction grating, lter array, etc. Key metrics in such short pulse proces- sors are pulse width, or equivalently total optical bandwidth that is processed, and the number of wavelengths that can be independently processed. Figure 4.1: Schematic of a generic spectral processor for femtosecond optical pulses. For example, optical code-division multiple-access (O-CDMA) is a promising optical access technology due to several attractive features including exibility, recongurability, ease of network control, and potential for enhanced physical layer security [95]. The physical layer security relies on coexistence of multiple users and a large code space. Spectral phase encoded time-spreading O-CDMA is a coherent O-CDMA technique which applies spectral phase changes based on a unique code to each user's data modulated optical pulse, causing the encoded waveform to spread in the time domain [96, 95]. A receiver with full knowledge of the spectral code reconstructs the original short optical pulse and distinguishes the short pulse from other users' data pulses. In such a system, doubling the code length, improves the bit-error-rate (BER) by almost two orders of magnitude for a xed number of users [96]. The optical pulse width plays key role in determining the bit rate of the system. In the literature, an O-CDMA system with 320 Gbps throughput (32 users 10 Gbps) at BER< 10 11 using on-o keying modulation, 64 bit code length, 450 119 fs laser pulse, and enhanced non-linear detectors is experimentally demonstrated [97]. The throughput can be improved further by incorporating hybrid modulation schemes in O-CDMA networks [98]. There have been two primary approaches to implement ultra-short pulse optical spectral processors. In a rst approach, free-space diraction grating followed by spatial light modulators (SLM) are used either without control electronic (xed masks) [99, 97] or without amplitude control capability [95]. In a second approach, monolithic array waveguide gratings (AWG) or echelle gratings, serving as wave- length separator and combiner, along with on-chip phase and occasionally ampli- tude adjusters are used [100, 101, 102, 89]. The limitations of past realizations include high loss associated with AWG and echelle grating approaches for large number of channels and small channel spacing [100, 101, 102, 89, 103, 104, 105, 106], the inability to adjust both amplitude and phase of each wavelength, and a large system size (especially in SLM realizations) [99, 97, 95]. Our approach combines the best features of the free-space and monolithic ap- proaches while enabling scalability in the number of supported wavelengths and independent control of phase and amplitude for each wavelength. Specically, free- space diraction gratings are used as wavelength separation and combining blocks while a monolithic chip adjusts the phases and amplitudes of each wavelength in- dependently. The monolithic chip uses the IBM/GF 7RF SOI technology that is 120 widely used in the realization of radio frequency switches for the front-end of cel- lular networks [46]. No pre- or post-processing steps are needed. Ideally, the entire shortpulse spectral processor should be monolithically integrated in a chip. This would require monolithic wavelength separation and combining blocks that support a large number of wavelengths. Limited quality-factor of on-chip lters, and sen- sitivity of AWG to process mismatches are some of the challenges that need to be overcome for such monolithic realization. Table 1 summarizes the performance of selected published state of the art integrated wavelength separation devices. In the next section we talk about these challenges. 4.2 Integratedwavelengthseparationandcombining elements There are wide range of integrated solutions to separate wavelength components. Optical lters using resonance structures, e.g. ring resonators [107, 108, 109] and AWGs [110, 111, 112, 113] are commonly used as wavelength separation compo- nents. Figure 4.2 shows generic geometry of a ring resonator acting as a wavelength lter. Light from the input waveguide is coupled into a ring with coupling ratio of . The amount of round trip optical phase change will set the interference with input light to be constructive or destructive. It can be shown that the transfer function of drop port is given by [108] 121 T d = 0:5 2 e =2 1t 2 e ; (4.1) where t = p 1 2 , is the round trip loss, and is the round trip phase change inside the ring. The ring response is periodic. The period is called free spectral range (FSR) and can be found as FSR = 2 n g L ; (4.2) where L is the perimeter of the ring and n g is the group refractive index of the waveguide. The quality factor of ring resonator is also dened as resonance wave- length divided by the full width half magnitude of transfer response and it is a measure of the sharpness of the resonance. It can be shown that Q is given by [108] Q = n g L p t (1t) : (4.3) In order to increase the Q-factor, it is crucial to reduce the loss,. Furthermore, bigger ring geometry provides higher Q. Very high Q = 3 10 5 has been reported in the literature [114] beneting from a careful fabrication process and large ring 122 Figure 4.2: Generic geometry of ring resonator as wavelength lter. Drop port has band-pass response at resonance wavelength. geometry. In general, ring resonator based lter arrays channels that are suciently apart have been demonstrated for WDM applications [115, 116, 117]. Process variation and temperature gradient aect the resonance wavelength. Tunable rings have been demonstrated to overcome this problem at the cost of consuming some power [114]. For instance, heaters may be used close to the ring for a tunable response [118]. Supporting wide optical bandwidth with large number of channels that are relatively close would require ultra high Q ring resonators. As a case study, here the design challenges of sampling 25 nm optical bandwidth with 128 lters centered at dierent wavelengths using 128 cascaded ring resonators is presented. Light that travels on a silicon waveguide is coupled into a rst ring 123 centered at 1 followed by another ring centered at 2 and so on till 128 (Fig. 4.3). FSR of each ring should be greater than the required optical bandwidth, here 25 nm. Therefore, using Eqn. 4.2 we have Figure 4.3: Wavelength separation scheme with using 128 cascaded ring resonators centered at 128 dierent wavelengths. 25nm = 1550 2 [nm 2 ] 4:5L ; (4.4) where group refractive index of typical silicon waveguide is used at 1550 nm. This will result the radius of ring to be equal to 3:3m. Typically ring with this size has relatively high loss. In the IBM/GF 7RF SOI process U-turn loss for such a 124 bend radius is 0:7dB=cm (Chapter 2). Simulations were conducted for three process cases, namely, the IBM/GF 7RF SOI process, the IMEC silicon photonic process, and an ideal process with zero waveguide loss. In the IMEC silicon photonic process, the waveguide loss is 0.2 dB/mm and the loss for a 3m U-turn is 0.2 dB. As shown in Fig. 4.4, neither IBM/GF 7RF SOI nor the IMEC silicon photonic process allows realizing selective-enough lters to be used in the envisioned system where a high channel-channel isolation is required. For the ideal zero-loss platform, 15 dB channel isolation can be achieved. Figure 4.4: Simulated lter response of two cascaded ring resonators with 25 GHz channel spacing in three dierent processes: IBM/GF 7RF SOI, IMEC silicon pho- tonics, and ideal (zero waveguide loss). An alternative approach to separating wavelength components is by using an ar- rayed waveguide grating (AWG) [113, 119, 120]. The principle of AWG is based on 125 interference of set of delayed light signals in a free propagation region that provides wavelength-spatial lter. Figure 4.5 shows operation principle of typical AWG. Light from input waveguide is coupled to a free propagation region on the left side. The optical mode is diracted with angle and is coupled into M arrayed waveg- uides on the other side of the free propagation region. By design, there should be equal power coupled to each arrayed waveguide. Arrayed waveguide lengths are equally dierent by L. Therefore the optical phases of light are relatively changing as a function of L and wavelength. They are coupled to another free propagation region on the right side. The interference pattern of M light sources on the projection plane on the other side of the free propagation region is wave- length dependent. The geometry is designed so at each of the desired wavelengths, there is only one constructive interference at one particular point where the output waveguide is placed [121]. Figure 4.5: Operation principle of typical arrayed waveguide grating (AWG). 126 Here, we present design steps and simulation results of a typical AWG in the IBM/GF 7RF SOI process. The AWG response is periodic with wavelength. There- fore, the target optical bandwidth should be equal or smaller than the AWG period, FSR. Again, we also consider 25 nm optical bandwidth with 25 GHz channel spac- ing. FSR of AWG can be calculated as [121] FSR = c n g L : (4.5) where c is the speed of light, n g is the group refractive index, and L is the length dierence between adjacent arrayed waveguides. Assuming typical waveguide in IBM/GF 7RF process,n g = 4:5, based on Eqn. 4.5, L can be found to be 22m. In a typical design, the number of arrayed waveguides are set to be 3-4 times the number of output waveguides [121]. For 25 GHz channel spacing and 25 nm total optical bandwidth, the required number of output channels is 128. That would set M = 384. Therefore, the minimum length of longest arrayed waveguide will be L M =M L = 8:5 mm: (4.6) The large dierence in the lengths of arrayed waveguide causes a large ampli- tude imbalance for the signals at the beginning of second free propagation region. 127 This is unwanted as for the proper operation. Ideally only the phase of light inside arrayed waveguides should be changed. In the IBM/GF 7RF SOI process, with 1.27 dB/mm propagation loss in the silicon waveguides, there is 10.8 dB ampli- tude dierence between the longest and shortest waveguides. To compensate the amplitude imbalance, attenuators must be placed on each arrayed waveguide. In addition, phase shifters would need to be added to compensate the phase response of attenuators. These add the overall system loss considerably. To estimate device geometry, the size of free propagation regions should be cal- culated. Starting from input waveguide to be standard 550 nm wide single mode waveguide in the IBM/GF 7RF SOI process (similarly in other quarter micron plat- forms like IMEC), the diraction angle of the mode going into the free propagation region is simulated to be = 50 (Figure 4.6). Assuming similar waveguide width, e.g. 550 nm, for arrayed waveguides and minimum allowable gap size between waveguides to be 260 nm, the width of the rst free propagation region is found to be W f = 308 m. Having and W f , length of the free propagation region is calculated to be L f1 = 365 m. The length of arrayed waveguides, L 1 to L M , are derived based on the calculated L = 22 m. After propagating inside arrayed waveguides with assumption of balanced power and no phase mismatch, point source approximation can be used [121, 122] on the rst order to nd the geometry of second free propagation region. The interference 128 Figure 4.6: Simulated diraction angle of waveguide mode into free propagation region in the IBM/7RF SOI process. pattern on the other side of the free propagation region can be engineered to peak at certain spatial points at the desired wavelengths. We assume waveguide pitch and width of the output waveguides to be the same as array waveguides, 550 nm and 260 nm respectively. Figure 4.7 shows geometry and simulated amplitude response of three adjacent channels of the designed AWG in the IBM/GF 7RF SOI process with 25 GHz channel spacing assuming the amplitude imbalances are compensated. Assuming no phase error in the arrayed waveguides, 14.5 dB channel isolation is expected. Phase error control in AWG design is another challenge that degrades the chan- nel isolation. It was shown that for instance only 10 5 change in refractive index can result in signicant low channel selectivity and poor ltering performance of the device [121, 122]. For instance only 4 dB isolation for 512 channels with 25 GHz spacing has been achieved [122] even in a custom process. 129 Figure 4.7: (a) Geometry and (b) Simulated three adjacent channel responses of designed AWG in IBM/GF 7RF SOI process with 25 GHz channel spacing. 130 Table 4.1: Performance summary table of monolithic arrayed waveguide gratings. In summary, designing low-loss compact AWG for large number of close chan- nels is challenging. A active phase and amplitude tuning of arrayed waveguides are needed to compensate the phase and amplitude mismatches. Table 4.1 summarizes performance of previously reported AWGs along with the simulated performance of our designed AWG in the IBM/GF 7RF SOI process. It is seen that, similar to ring-resonator-based lter array, monolithic AWGs can not meet the desired re- quirements. Therefore, an o-chip approach for wavelength separation was adopted in our work. 4.3 MonolithicOpticalShort-PulseEncoder/Decoder The Optical Short-pulse En/De-coder (OSPED) includes 128 channels where each channel consists of a pair of grating couplers to couple light in and out of the chip and optical amplitude and phase adjusters in between (Figure 4.8). Optical short pulses that originate from a laser, are diracted using an o-chip grating, and subsequently coupled to the chip for spectral processing. The processed light 131 is coupled out and detected after all the channels are combined outside of the chip using a lens and diraction grating. Control electronics for all the tunable components are integrated on the same chip at a distant location from the optical core, and the control electrical signals are routed to the active elements using the available metal lines in the CMOS process. Independent control of phase shift and amplitude of optical eld at each element enables on-chip spectral processing and waveform engineering. Figure 4.8: Schematic of the 128-bit monolithic optical short pulse processor with independent amplitude and phase control at each bit (wavelength-channel). Short pulse is diracted o-chip and multiple wavelengths centered at 128 dierent wave- lengths (colors) are coupled in to grating couplers. Each color is processed on chip using independent wavelength-dependent amplitude and phase control units, then coupled out of the chip using similar grating couplers. Figure 4.9 shows the chip microphotograph of fabricated 128-bit monolithic optical short pulse processor in the IBM/GF 7RF SOI process. Performances of dierent types of photonics devices that are used in this system are presented in Chapter 2. We have optimized the devices for processing of very 132 Figure 4.9: Chip microphotograph of the fabricated 128-bit monolithic optical short pulse processor in the IBM/GF 7RF SOI CMOS process featuring over 500 distinct optical components and over 150,000 distinct electrical components. 133 large optical bandwidth. For instance, input and output grating couplers are dis- tanced far enough so that a reasonable channel isolation without causing too much optical power coupling loss is achieved. Each variable attenuator is designed in such a way that its passive response peaks at the nearest possible wavelength compared with the target channel center wavelength to save active power consumption. The electrical current used to tune active elements is controlled by a programmable electrical 7-bit Digital-to-Analog Converter (DAC) similar to the optical phased array driver electronics that is presented in Chapter 3. 4.4 System elements and calibration Each channel consists of a pair of grating couplers with tunable thermo-optical attenuator followed by a tunable thermo-optical phase shifter in between. Grating couplers are 4m wide and 30m long to ease coupling from diracted light. The period and ll factor are 700 nm and 50%, respectively (Fig. 4.10.a). The mea- sured normalized passive response of each grating coupler shows a 1 dB bandwidth of 26 nm (Fig. 4.10.b). The center-to-center distance between two adjacent grating couplers is 10 m to give better than 20 dB channel isolation. Figure 4.11 shows simulated normalized coupling from diracted light into two adjacent grating cou- plers. Assumption here is that the channel spacing between center wavelengths of each grating coupler is 20 GHz. The channel isolation that is dened as the value of 134 transfer function of an adjacent grating coupler at center wavelength of the target grating coupler is better than 26 dB. To ease the requirements for free space optics to couple diracted light in and out of the chip, 128 channels are laid out in 16 clusters of 8-channels in a staggered conguration occupying a total length of 1.575 mm. The edge to edge distance of adjacent clusters is 20 m. The dierence between design of each cluster is in the passive layout of tunable attenuator to shift the peak wavelength as close as possible to the target wavelength while satisfying lithography limitations of the process. The tunable phase shifter is slightly modied version of the one presented in Chapter 2 and it is realized as a 180 m-long meandered silicon waveguide with four polysilicon heaters connected in parallel electrically (Fig. 4.12). A 2 optical phase shift is achieved by consuming 31 mW power in the heater with 0.81 k electrical resistance. The tunable attenuator is also similar to the one was used in the optical phased array as discussed in Chapter 3. Figure 4.10: (a) Grating coupler to couple light in or out of the chip with 4 m width and 30 m length for high isolation between adjacent channels. (b) Typical measured response of grating coupler showing 1 dB bandwidth of 26 nm. 135 Figure 4.11: Simulated frequency selectivity of two adjacent grating couplers when they are coupled by diracted light with channel spacing of 20 GHz. Figure 4.12: (a) Thermo-optical variable phase shifter realized as a meandered waveguide with poly-silicon heaters in between to increase the power eciency and decrease the voltage swing that is needed to cover 2 optical phase shift. (b) Typical measured phase and amplitude responses of a variable phase shifter as a function of heater power consumption at peak wavelength. 136 The variable attenuator provides a measured 16 dB amplitude tunability while consuming 16 mW DC power at a peak designed wavelength (Fig. 4.13). The dif- ference here in the tunable attenuator of each cluster is that the length of longer arm in the MZI is slightly dierent (L a has been adjusted) to set the peak wavelength at a desired value, so that collectively all clusters cover 30 nm optical bandwidth while saving active power consumption. The measured passive responses of atten- uators of dierent clusters are shown in Fig. 4.13.b. The peak wavelength of each cluster from both measurement and simulations are presented in Fig. 4.13.d. Calibration of phase and amplitude active response of each channel is critical for system level demonstration. The experimental setup shown in Fig. 4.14.a is used for this calibration. Optical short pulses using a commercial mode locked laser with approximate pulse width of 320 fs and repetition rate of 100 MHz are shined to an o chip diraction grating using ber and collimating lens. The laser output power spectrum was measured using an optical spectrum analyzer (Fig. 4.15). The 3 dB optical BW equal to 34 nm. As a result, approximately 25 nm optical bandwidth is diracted and coupled to 128 channels on the chip. For each channel, the amplitude response is measured by using a lensed ber at the top of the corresponding output. The mode size of lensed ber at the focal point is 2 m that makes it suitable to pick up the power from each grating coupler. The response of peak wavelength (channel center wavelength) is used for ampli- tude characterization. Normalized spectrum of all individual channels are shown in 137 Figure 4.13: (a) Optical variable attenuator is constructed as an interferometer with polysilicon heater in between. The relative phase change between the two paths, due to thermo-optical eect that is more prominent in the longer branch, results in amplitude tunability of around 16 dB. The arm length is slightly dierent (L a has been adjusted) for each cluster to set the desired peak wavelength over the desired 30 nm wavelength range. (b) Typical passive response of attenuators of each cluster demonstrating peaks at dierent wavelengths. (c) Typical measured phase and amplitude responses of an optical variable attenuator as a function of heater power consumption at peak wavelength. (d) Simulated and measured peak wavelengths of variable attenuators of all clusters. 138 Figure 4.14: (a) Schematic of the measurement setup to characterize amplitude and phase responses of each channel; (b) Normalized measured spectrum of all channels plotted together after amplitude calibration. 139 Figure 4.15: Measured power spectrum of short pulse laser using an optical spec- trum analyzer. Fig. 4.14.b. For phase calibration, the interference signal at the mid-wavelength of two adjacent channels that has the strongest interference is used. A phase shifter in one channel is tuned and calibrated with respect to the adjacent channel phase. For each channel, the phase change from mid to center wavelength is almost negligible since they are only around 80 pm away. An example of measurement result of such a characterization is shown in Fig. 4.16. 4.5 Electrical routing The electro-optical chip has a total of 256 independent heaters, 128 for variable phase shifters and 128 for variable attenuators, that must be controlled indepen- dently. Metallization of the system was done similar to that os the optical phased 140 Figure 4.16: (a) Measured spectrum of channels 63 and 64 picked up by a lensed ber at the top of grating couplers for two cases when phase shifter in channel 64 is tuned to give in or out of phase interference. The information at the mid- wavelength, here 1550.07 nm, is used to calibrate the phase shifter. (b) Example of normalized interference pattern at mid-wavelength of (a) as a function of active heater power of phase shifter in channel 64. 141 array as discussed in Chapter 3. One terminal of all the heaters are connected elec- trically to a common terminal using the three bottommost available metal layers (bottommost copper and other two aluminum), and the other terminals are routed independently to the designated driver circuitry using the topmost available metal layer (aluminum). All the routing is done judiciously to minimize the eect of metal lines on the optical devices while satisfying the foundry metal density requirements. The digitally controlled integrated electronic consists of a programmable 7-bit DAC followed by the current drivers that drive the polysilicon heaters via the aforemen- tioned metal interconnects. The chip is programmed serially through a computer using clock, reset, and load signals. 4.6 Experimental results 4.6.1 OperationofOSPEDmeasuredwithfastelectro-optical detection The performances of individual optical components, namely, the tunable optical phase shifter, the tunable optical attenuator, and the grating couplers were indi- vidually characterized in stand-alone structures concurrently fabricated in the same process. The measured optical losses for components are around 5.5 dB for grating coupler, 0.3 dB per 12 MMI, 2 dB per phase shifter, 0.8 dB per attenuator, and 2 dB for silicon waveguide (1.27 dB/mm). The total optical insertion loss of the chip 142 is 15.8 dB. Phase and amplitude response of the channels were calibrated using the approach that is explained in the previous section. System level measurements are conducted using a setup that is shown in Fig. 4.17. The output light of channels after getting processed on the chip are combined using another o-chip diraction grating and coupled to an output ber. The total loss of free space setup together with on-chip loss is 20.3 dB. A low-dispersion optical amplier (EDFA) is used at the output to boost the power level while preserving the pulse shape. The amplied output is split to detect using either a 50 GHz photodiode and fast electrical oscillo- scope both with 50 GHz analog bandwidth (when number of on channels are small enough), or using optical short pulse auto-correlator. Figure 4.18 shows photograph of the chip mounted on a PCB with the required supply voltages and programming signals. Several thermal vias were placed under the die that is attached to the PCB using a thermally-conductive epoxy to improve the thermal conductivity. We measured electrically detected optical pulses when only 1, 2, 3, 4, 10 and 128 channels are on and they are all in phase. As shown in Fig. 4.19, and Fig. 4.20 after three channels, the detected pulse width is capped at around 23 ps in good agreement with simulations. 143 Figure 4.17: Schematic of the setup used to measure processed optical pulse width using both very fast electro-optical detection and optical short pulse intensity auto- correlator. Figure 4.18: Photograph of the wirebonded chip that is mounted on a PCB with the required supply and programming signals as well as vias underneath chip for better thermal conductivity. 144 Figure 4.19: Measured optical pulse width when one, two, three, 10 and 128 chan- nels are on and are in phase using a 50 GHz photodiode. Figure 4.20: Detected optical pulse width using a 50 GHz detector versus the number of ON channels. After three channels, the pulse width is limited to the electrical bandwidth of the detection system. 145 4.6.2 Operation of OSPED measured with optical short pulse auto-correlator Because of bandwidth limitation of electronic detection, the pulse width of output processed signal can not be measured for optical bandwidth higher than 0:4 nm. Instead, the well known auto-correlation techniques can be used to measure the pulse width of such ultra short optical signal [7]. Fig. 4.21 shows a typical auto- correlator setup. The principle of operation is based on recording the second order correlation function using an interferometer. An incoming pulse with electric eld E(t), is rst split into two branches. One branch is delayed relative to the other branch using a variable delay line. They are combined in a nonlinear crystal where proper phase matching conditions that will result in a second harmonic signal. The total intensity of the second harmonic signal is proportional to Figure 4.21: Schematic of optical short pulse intensity auto-correlator [7]. 146 I SH (t +) = (E(t) +E(t +)) 2 =E(t) 2 + [2E(t)E(t +)] +E(t +) 2 (4.7) The component [2E(t)E(t +)] represents the overlap of the two signals,i.e., this component of the signal will only be present when the two pulses are overlap in time. In the case that the two beams enter the nonlinear crystal as shown in Fig. 4.21, and when the phase matching conditions are satised, Eqn. 4.7 simplies to [7] I SH (t +) = 2E(t)E(t +): (4.8) The signal is detected using a photodiode. The detector squares the incident eld as well as integrates over the duration of the femtosecond pulse, t. Therefore, the amplitude of the detector signal, I pd , is proportional to I pd () = Z (2E(t)E(t +)) 2 dt: (4.9) which, by relating the square of the electric eld to the intensity can be expressed as 147 I pd ()/ Z I(t)I(t +))dt: (4.10) This represents the intensity autocorrelation of the initial pulse. Equation 4.10 is a correlation integral and indicates that the autocorrelation does not measure the pulse width directly. For Gaussian intensity of pulse width equal to t, assuming I(t) =e ( t p (2)t ) 2 , then the intensity autocorrelation can be found as I pd ()/ Z e ( t p (2)t ) 2 e ( t+ p (2)t ) 2 dt: (4.11) Simplifying the integrand, the equation will become I pd ()/ Z e ( t+=2 t ) 2 e ( 2t ) 2 dt; (4.12) This will lead to I pd ()/e ( p 2( p 2t) ) 2 : (4.13) 148 Therefore, the pulse width of intensity auto-correlation is p 2t [7]. We used a commercially available auto-correlator from ThorLabs (PulseScout2). The experiment was performed for three dierent code lengths (number of active channels) of 64, 88, and 128 for two cases. In the rst case, Gaussian amplitude prole and uniform phase prole are used across all the used channels. In the second case, the amplitude proles remain unchanged while the phases are scrambled using Walsh orthogonal code [123] where the phase of active channels with associated bit "1" are changed by compared with other active channels with associated bit "0". The encoded data was normalized to the peak of constructed signal for each code length. The recorded autocorrelation data for all the cases is shown in Fig. 4.22. As a result, intensity auto-correlation shows that both extracted short pulse width and intensity ratio of pulse peak to peak of encoded signal are correlated with code length as theoretically expected [96], i.e., pulse width scales down and intensity ratio of pulse peak-to-peak of encoded signal scales up linearly with code length (Fig. 4.23). This relationship is intuitively explained in Fig. 4.25. The initial laser pulse width is extracted to be 320 fs assuming Gaussian pulse. One example of measured intensity auto-correlation of encoded pulse with 128 active channels is also shown in Fig. 4.24. As expected, the pulse is spread in time domain from 0.38 ps to 50 ps with a ratio of 128. 149 Figure 4.22: Experimental result of intensity auto-correlation of the output pro- cessed light for three code lengths, 64, 88 and 128, in two cases: one is successfully constructed short pulse, and second is encoded pulse with Walsh orthogonal code. The data is normalized to the peak of constructed signal and encoded signal for each code length is relatively normalized to corresponding constructed signal. Figure 4.23: Extracted constructed pulse width and intensity ratio of pulse peak to peak of encoded signal versus number of used channels. 150 Figure 4.24: Measured intensity auto-correlation of an encoded pulse with 128 channels. Figure 4.25: Intuitive emplanation of the eect of code length on intensity and intensity ayto-correlation for Gaussian pulse. 151 4.7 Conclusion The presented work is the rst integration of a large scale optical short pulse pro- cessor, including the complete integrated control electronics, with independent am- plitude and phase control for every channel capable of arbitrary waveform gener- ation in a commercial CMOS SOI process. Table 4.2 shows the performance of this work in comparison with selected previously published fully- or semi- mono- lithic approaches. On the technical side, realization of integrated wavelength sep- aration/combining devices with low-loss, high channel number, and high channel isolation is still a challenge. Table 4.2: Performance summary in comparison with other semi- or fully-monolithic spectral light processors. 152 Chapter 5 Conclusions and Directions for Future Work 5.1 Summary This thesis presented the implementations of large scale complex electro-optical systems which utilize electrical engineering and photonics principles and the state- of-the-art integrated technologies. We have demonstrated the following state of the art examples: - The world's rst monolithic 2D optical phased array that is integrated with control electronic on the same die in a commercial CMOS SOI process. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any complex electronic- photonic integrated phased array system. - The world's rst monolithic 128-bit spectral processor of sub-picosecond optical pulses in standard commercial CMOS SOI process with application in OCDMA 153 networks, pulse shaping and secure communication. The complex chip includes over 500 distinct optical components and over 150,000 distinct electrical components. 5.2 Future Work There are several open questions and directions for future research that follow this thesis. The key open research topics in the area of integrated optical phased arrays are: 1. Large-scale 2D optical phased arrays with small (ideally =2) antenna spacing 2. Realization of monolithic optical phased arrays at various wavelengths such as ultra violet (UV), visible, mid wave infrared (MIR), and long wave infrared (LIR) 3. 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Note: Chapters 3 and 4 have been taken from my PhD papers which are [26, 52, 94]. 166 Appendix A Design of Schottky Photodiode in the IBM/GF 7RF SOI Process A.1 Introduction Light detection in silicon at IR wavelengths requires highly absorbing materials like Ge [82, 25, 124]. There are other methods available to make silicon an absorbing material that is based on highly implanting silicon crystalline with heavy ions [125, 126], or schottky eect based on photon absorption on low doped silicon metal junction that has barrier less than photon energy [81, 127]. Compared with Ge, the latter methods suers from weaker responsivity or operation bandwidth and may be used when Ge is not available in the process. 167 A.2 Principleofdopedsilicon-metalschottkyphotodiode In the IBM/GF 7RF SOI process, the only available option is to use the 00 via" metal directly connected to the available doped silicon. Light is coupled using a dielectric waveguide and to a Schottky junction. The principle of operation of Schottky doped silicon-metal photodiode is shown in Fig. A.1. The photon is incident to the Schottky junction. Because it has bandgap less than photon energy, i.e. 0.8 ev at 1550 nm, photon is absorbed and electron carrier is released as photocurrent. The Schottky bandgap depends on the doping level of silicon but it is around 0.4-0.7 eV for silicon doping concentration between 10 15 10 17 1=cm 3 [81]. Figure A.1: Principle of Schottky doped silicon-metal photodiode. Responsivity of Schottky photodiode, the amount of generated photocurrent per absorbed optical power, can be found as [81] =a q(1 q B h ) 2 h ; (A.1) 168 where a is the amount of absorbed power on Schottky junction, q is the charge of electron, h is the Planck's constant, B is the Schottky barrier, and is the frequency of light. In the IBM/GF 7RF SOI process, there is strict rule for the size of the metal via connecting to doped active silicon layer. It has to be 250 nm wide and placed exactly 250 nm away from an adjacent via. The via length must be maximum 2.5 m. This geometrical limitation will only leave one option for device geometry as it is shown in Fig. A.2. The light is coupled from dielectric waveguide and tapered up to improve coupling from the waveguide into Schottky junction. The process only oers two levels of p-doping, p and p+. p is used to create Schottky junction andp+ is used to create ohmic contact on the other side to collect the photocurrent. Figure A.2: Geometry of Schottky doped silicon-metal photodiode in IBM/GF 7RF SOI process (a) top and (b) side views. 169 We fabricated and characterized this device. First, the IV characteristic was measured to proof the existence of diode behavior (Fig. A.3) and then diode pa- rameters like series resistance, non-ideality factor, and dark current were extracted (Table A.1). Figure A.3: Measured IV of Schottky photodiode of fabricated device in the IBM/GF 7RF SOI process (a) linear (b) log scales. Responsivity and electrical bandwidth of the device has been measured using setups that are shown in Fig. A.4.a and b. Measured responsivity, junction ca- pacitance and electrical bandwidth versus reverse bise voltage are all shown in Fig. A.5a,b and c and compared with simulation. Considering measured dark (I d ) current and responsivity (), the minimum acceptable optical power (S min ) can be calculated as 170 Table A.1: Summary table of extracted Schottky diode parameters from IV mea- surements. Figure A.4: Measurement setups to characterize (a) responsivity and (b) electrical bandwidth of the Schottky photodiode. 171 Figure A.5: Measurement results of (a) responsivity, (b) junction capacitance, and (c) electrical bandwidth using both direct and vector network analyzer of the Schot- tky photodiode versus reverse bias voltage compared with simulated values. 172 S min = I d ; (A.2) Replacing I d = 16:5 nA, = 0:95 mA/W, S min = 1:7 m is calculated at -1 V reverse bias voltage. The performance of the presented photoiode given all the process limitation make it acceptable for monitoring optical power as long as the power is well above S min . 173

Abstract (if available)

Abstract The thesis presents device level and system level integrated large-scale monolithic electro-optical solutions for wide range of applications, including: light detection and ranging (lidar), imaging, optical code division multiple access networks, optical pulse shaping and biomedical sensing. Silicon photonics technology is used to enable monolithic integration, designing novel devices and systems particularly in commercially available SOI CMOS process. Two system level examples are proposed and demonstrated: first, 8 × 8 optical phased array transceiver, the world’s first monolithically integrated 2-dimensional optical phased array in a commercial CMOS process, and second, 128-bit spectral light processor of sub-picosecond optical short pulses.

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Creator Abediasl, Hooman (author)

Core Title Integrated large-scale monolithic electro-optical systems in standard SOI CMOS process

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Degree Conferral Date 2017-05

Publication Date 02/10/2017

Defense Date 01/25/2017

Publisher Los Angeles, California (original), University of Southern California (original), University of Southern California. Libraries (digital)

Tag CMOS photonics,integrated optical phased array,large-scale monolithic electro-optical systems,light processor,OAI-PMH Harvest,silicon photonics,spectral processing of sub-picosecond optical pulses,standard SOI CMOS process

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Advisor Hashemi, Hossein (committee chair), Dapkus, Dan (committee member), Kapadia, Rehan (committee member), Nakano, Aiichiro (committee member), Povinelli, Michelle (committee member), Prata, Aluizio (committee member)

Creator Email abediasl.hooman@usc.edu,abediasl@usc.edu

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