University of Southern California Dissertations and Theses

Carbon nanotube macroelectronics

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Carbon nanotube macroelectronics

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CARBON NANOTUBE MACROELECTRONICS

by
Jialu Zhang

A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)

May 2013

Copyright 2013 Jialu Zhang
ii

Dedication

Dedicated to my family.

iii

Acknowledgements

I never imaged I would gain such a valuable and wonderful experience when I joined
USC as a PhD student in 2008. During the past four and half years, I have met with
numerous people, who have helped, encouraged, and inspired me on my research as well
as my personal life. This dissertation would not be possible without their efforts.
First of all, I would like to express my deep appreciation to my advisor, Prof.
Chongwu Zhou, for all of his valuable guidance and support throughout my PhD study.
His mentorship was paramount in providing a well-rounded experience consistent my
long-term career goals. He encouraged me to not only grow as an experimentalist and a
researcher but also as an instructor and an independent thinker.
I also wish to thank my dissertation committee members Prof. Mark Thompson and
Prof. Steve Cronin for their helpful suggestions and comments as well as Prof. Alice
Parker and Prof. Michelle Povinelli for serving on my qualifying exam committee.
Additionally, I would like to thank all my former group members, fellow graduate
students and post-doc scholars. Dr. Koungmin Ryu, Dr. Fumiaki Ishikawa, Dr. Po-Chiang
Chen, Dr. Lewis Gomez, Dr. Akshay Kumar, Dr. Chuan Wang, Dr. Alexandar Badmaev,
Dr. Hsiao-Kang Chang, Dr. Anuj Madaria and Dr. Yi Zhang. Thanks all of you for your
patient training and valuable suggestions when I join the group as a junior student.
Haitian Chen, Yue Fu, Yuchi Che, Xue Lin, Jia Liu, Zhen Li, Jing Xu, Jing Qiu, Shelley
Wang, Maoqing Yao, Nappadol Aroonyadet, Mingyuan Ge, Jiepeng Rong, Luyao Zhang,
Xin Fang, Pyojae Kim, Younghyun Na, Rebecca Lee, Kuan-The Li, Ning Yang, Liang
iv

Chen, Hui Gui, Pattaramon Vuttipittayamongkol, Ahmad Abbas, Dr. Bilu Liu, Dr. Gang
Liu, Dr. Yung-Chen Lin, Yimo Han, Sen Cong, Yu Cao. Thank you for your help during
the past years. We have spent tough but spectacular time together, and I can never be too
gratefully for my luckiness of being able to spend such a fabulous time with all of you.
Moreover, I’d like to acknowledge all of the collaborators including Dr. Mike Fritze,
Dr. Michael Bajura, Dr. Jon Ahlbin, Dr. Ivan Sanchez from Information Sciences Institute
of USC, Prof. Kang L. Wang, Prof. Kosmas Galatsis from UCLA, Dr. Ming Zheng from
National Institute of Standards and Technology, Prof. Mark Hersam from Northwestern
University, for their priceless suggestions and discussions, which has helped diversifying
my scientific knowledge and broadening my vision.
Finally, and most importantly, I would like to thank my parents and my wife, Bei Pan.
Your support, encouragement, quiet patience and unwavering love were undeniably the
main reason for all of my achievements today.

v

Table of Contents

Dedication ........................................................................................................................... ii
Acknowledgements ............................................................................................................ iii
List of Figures .................................................................................................................. viii
Abstract .......................................................................................................................... xviii
Chapter 1: Introduction ....................................................................................................... 1
1.1 Introduction of carbon nanotubes ............................................................................ 1
1.2 Structure of carbon nanotubes .................................................................................. 2
1.3 Electronic properties of carbon nanotubes ............................................................... 3
1.4 Outline of the dissertation ........................................................................................ 8
Chapter 1. References .................................................................................................. 10
Chapter 2: Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film
Transistors for Display and Digital Circuit Applications ................................................. 11
2.1 Introduction ............................................................................................................ 11
2.2 Wafer-scale separated carbon nanotube thin-film deposition ................................ 13
2.3 Separated carbon nanotube thin-film transistors .................................................... 16
2.4 Comparison between TFTs using separated and CVD-grown nanotubes ............. 18
2.5 Effect of semiconducting nanotube purity on transistor performance ................... 24
2.6 Display electronics using separated nanotube thin-film transistors ....................... 34
2.7 Digital circuits using separated nanotube thin-film transistors .............................. 37
2.8 Summary ................................................................................................................ 43
Chapter 2. References .................................................................................................. 44
Chapter 3: Separated Carbon Nanotube Macroelectronics for Active Matrix
Organic Light-Emitting Diode Displays ........................................................................... 47
3.1 Introduction ............................................................................................................ 47
3.2 Structure of AMOLED circuit and layout .............................................................. 49
3.3 Carbon nanotube density and device geometry optimization ................................ 50
3.4 Electrical properties of transistors used in the AMOLED circuit. ......................... 54
3.5 Characteristics of the two-transistor AMOLED single-pixel circuit. .................... 56
3.6 AMOLED display characteristics .......................................................................... 58
3.7 Summary ................................................................................................................ 61
Chapter 3. References .................................................................................................. 62
vi

Chapter 4: Air-Stable n-Type Separated Carbon Nanotube Thin-Film Transistors
and Its Application in CMOS Logic Circuits ................................................................... 65
4.1 Introduction ............................................................................................................ 65
4.2 Symmetric n-type and p-type separated carbon nanotube thin-film
transistor fabrication ................................................................................. 67
4.3 Mechanism of the carrier type conversion ............................................................. 70
4.4 Factors affecting the n-type SN-TFT performance. ............................................... 76
4.5 Contact resistivity and channel sheet resistance analysis ...................................... 80
4.6 Channel length dependence of the n-type and p-type SN-TFT device
performance metrics.................................................................................. 81
4.7 CMOS logic circuits based on symmetric n-type and p-type separated
nanotube thin-film transistors ................................................................... 85
4.8 Summary ................................................................................................................ 90
Chapter 4. References .................................................................................................. 92
Chapter 5: Rigid / Flexible Transparent Electronics Based on Separated Carbon
Nanotube Thin-film Transistors and their Application in Display Electronics ................ 95
5.1 Introduction ............................................................................................................ 95
5.2 Structure of rigid/flexible transparent SN-TFTs .................................................... 97
5.3 Electrical performance of fully transparent transistors .......................................... 99
5.4 Transparent transistors with improved contacts ................................................... 101
5.5 Performance of fully transparent and flexible SN-TFTs...................................... 105
5.6 Display electronics based on fully transparent SN-TFTs .................................... 107
5.7 Summary .............................................................................................................. 109
Chapter 5. References ................................................................................................ 110
Chapter 6: Electrical performance analysis of gel-based separated nanotubes with
different diameter and their Thin-Film Transistor applications ...................................... 113
6.1 Introduction .......................................................................................................... 113
6.2 Gel-based column chromatographic nanotube separation ................................... 115
6.2 Electrical performance of gel-based SN-TFTs .................................................... 119
6.3 Diameter effect on SN-TFT device performance................................................. 122
Table 6.1 Key parameter comparison for separated nanotubes with different
diameter.………………………..……………………………………………………131
6.5 Comparison between gel-based and DGU based separated nanotube ................. 132
6.6 Summary .............................................................................................................. 134
Chapter 6. Reference .................................................................................................. 136

vii

Chapter 7: Conclusions and Future Directions ............................................................... 139
7.1 Conclusions .......................................................................................................... 139
7.2 Future directions on thin-film transistor based CMOS logic circuits .................. 139
7.3 Future directions on SN-TFT based display electronics ...................................... 143
Chapter 7. Reference .................................................................................................. 147
Bibliography ................................................................................................................... 149

viii

List of Figures

Figure 1.1 Structure of carbon nanotube. (a) a
1
and a
2
are the lattice vectors of
graphene. |a
1
|=|a
2
|= √3a, where a is the carbon–carbon bond length.
There are two atoms per unit cell shown by A and B. SWNTs are
equivalent to cutting a strip in the graphene sheet (blue) and rolling
them up such that each carbon atoms is bonded to its three nearest
neighbours. The creation of a (n, 0) zigzag nanotube is shown. (b)
Creation of a (n, n) armchair nanotube. (c)A (n,m) chiral nanotube. ............ 3
Figure 1.2 The energy dispersion relations for graphene with γ0 = 3.013 eV , s =
0.129 and ε2p = 0. The inset shows the energy dispersion along the
high symmetry lines between the Γ, M, and K points. .................................. 4
Figure 1.3 Illustration of allowed wavevector lines leading to semiconducting and
metallic CNTs and examples of bandstructures for semiconducting
and metallic zigzag CNTs. ............................................................................. 6
Figure 1.4 Density of states for (11,0) and (12,0) CNTs computed from tight
binding show Van Hove singularities. ........................................................... 7
Figure 1.5 Carbon nanotube applications in nanoelectronics(a) and
macroelectronics(b). ........................................................................................ 8
Figure 2.1 Wafer-scale deposition of separated carbon nanotubes and fabrication
of SN-TFTs. (a) Schematic diagram of APTES assisted nanotube
deposition on Si/SiO2 substrate. (b) Length distribution of the
separated nanotubes used in this study (95% semiconductive
nanotubes purchased from NanoIntegris, Inc.), the average nanotube
length is 1.716 μm. (c, d) FE-SEM images of separated nanotubes
deposited on Si/SiO2 substrates with (c) and without (d) APTES
functionalization, respectively. (e) Photograph of 4 in. Si/SiO
2
wafer
after APTES assisted nanotubes deposition. Inset: FE-SEM images
showing nanotubes deposited at different locations on the wafer, the
locations of the SEM images on the wafer correspond to the
approximate locations on the wafer where the images were taken. All
the scale bars are 5 μm. (f) Photograph of the same wafer after
electrode patterning. The wafer consists of SN-TFTs used in this
study and other types of electronic devices. Such SN-TFTs are made
with channel width (W) of 10, 20, 50, 100, and 200 μm, and channel
length (L) of 4, 10, 20, 50, and 100 μm. ........................................................ 14
ix

Figure 2.2 Electronic properties of back-gated SN-TFTs (a) Schematic diagram of
a back-gated transistor built on separated nanotube thin-film with
Ti/Pd (5 Å /70 nm) contacts and SiO
2
(50nm) gate dielectric. b)
FE-SEM image of a typical SN-TFT with 4 m channel length. (c, d)
Output (I
D
-V
D
) characteristics of a typical SN-TFT (L = 20 m, and W
= 100 μm) in triode region (c) and saturation region (d), respectively.
(e) Transfer (I
D
-V
G
) characteristics (red: linear scale, green: log scale)
and g
m
-V
G
characteristics (blue) of the same device with V
D
= 1V . (f)
Current density (I
on
/W) measured at V
D
= 1V and threshold voltage
(V
th
) of 10 representative SN-TFTs showing the uniformity of devices.
The red line represents the average value. .................................................... 17
Figure 2.3 Statistical study of 200 nanotube TFTs based on separated nanotubes
and mixed nanotubes. (a) Plot of current density (I
on
/W) versus
channel length for TFTs fabricated on separated nanotubes and mixed
nanotubes. (b) Plot of average on current (I
on
) versus channel width
for TFTs fabricated on separated nanotubes and mixed nanotubes,
with various channel lengths (4, 10, 20, 50, 100μm). (c) Plot of
average on/off ratio (I
on
/I
off
) versus channel length for TFTs fabricated
on separated nanotubes and mixed nanotubes. (d) Plot of average
transconductance per unit width (g
m
/W) and average devicemobility
(μ
device
) versus channel length for TFTs fabricated on separated
nanotubes and mixed nanotubes. ................................................................... 21
Figure 2.4 Simulation of nanotube thin-film percolation network. (a) Randomly
generated nanotube percolation networks of separated nanotubes (top)
and mixed nanotubes (bottom) for devices with L = 10 μm and W =
20μm. The red and blue lines represent metallic and semiconductive
nanotubes, respectively (b) comparison between the simulation data
derived from the percolation network and measurement data. ..................... 23
Figure 2.5 Comparison of nanotubes separated by density gradient
ultracentrifugation with different purities of semiconducting
nanotubes (a) Photograph of P3 (unsorted), 95% semiconducting and
98% semiconducting single-walled carbon nanotube solution. (b)
UV-Vis-NIR absorption spectra of the as-prepared P3 arc-discharge
nanotubes (blue trace), 95% semiconducting separated nanotubes (red
trace) and 98% semiconducting separated nanotubes (green trace). (c)
FE-SEM images of 95% semiconducting separated nanotubes
deposited on Si/SiO2 substrates with APTES functionalization. The
average density is 41 tubes/µ m2. (d) Length distribution of the 95%
semiconducting separated nanotubes, the average nanotube length is
0.97 µ m. (e) FE-SEM images of 98% semiconducting separated
nanotubes deposited on Si/SiO2 substrates with APTES
x

functionalization. The average density is 46 tubes/µ m2. (f) Length
distribution of the 98% semiconducting separated nanotubes, the
average nanotube length is 0.81 µ m. ............................................................. 25
Figure 2.6 Electrical properties of back-gated SN-TFTs using 95% and 98%
semiconducting nanotubes. (a) Optical microscope image of the
SN-TFT array fabricated on silicon substrate with 50 nm SiO
2
acting
as gate dielectric. (b) FE-SEM image showing the channel of a typical
back-gated SN-TFT with 10 μm channel length. (c, d) Transfer
characteristics (I
D
-V
G
) of the SN-TFTs using 95% (c) and 98% (d)
semiconducting nanotubes with various channel lengths (4, 10, 20, 50,
and 100 μm) and 100 μm channel width plotted in logarithm scale. (e)
Transfer characteristics (red: linear scale, green: log scale) and g
m
-V
G

characteristics (blue) of a typical SN-TFT (L = 50 μm, W = 100 μm)
using 95% semiconducting nanotubes. (f) Output characteristics
(I
D
-V
D
) of the same device in (e). (g) Transfer characteristics (red:
linear scale, green: log scale) and g
m
-V
G
characteristics (blue) of a
typical SN-TFT (L = 100 μm, W = 50 μm) using 98% semiconducting
nanotubes. (h) Output characteristics of the same device in (g). .................. 28
Figure 2.7 Statistical study of 175 SN-TFTs using separated nanotubes with 95%
and 98% semiconducting nanotubes, as well as comparison of key
device performance metrics. Plot of (a) current density (Ion/W), (b)
average on/off ratio (Ion/Ioff), (c) normalized transconductance
(gm/W) and (d) device mobility (μdevice) versus channel length for
TFTs fabricated on separated nanotubes with 95% (black trace) and
98% (red trace) semiconducting nanotubes. .................................................. 31
Figure 2.8 OLED control circuit by SN-TFT. (a) Transfer (I
D
-V
G
) characteristics
under different drain voltages for the device used to control the
OLED (L = 20 m, and W = 100 μm), Inset: optical microscope
image of the device. (b) Characteristics of the OLED control circuit
where the current flow through the OLED (I
OLED
) is measured by
sweeping the V
DD
and Input voltage V
G
. Various curves correspond to
various values of V
G
from -10 V to 10 V in 2 V steps. (c) Two
terminal measurement of the OLED showing the current through the
OLED (I
OLED
) (red line) and OLED light intensity (green line) versus
the voltage applied across the OLED (V
OLED
). (d) Plot of the current
through the OLED (I
OLED
) (red line) and OLED light intensity (green
line) versus V
G
with V
DD
= 5 V . Inset: The circuit diagram of an
OLED driven by a SN-TFT. (e) Photographs of the OLED driven by
SN-TFT under different inputs showing the turn on and turn off of the
OLED. ........................................................................................................... 35
xi

Figure 2.9 Integrated inverter circuits using separated carbon nanotubes. (a, d)
Schematic of two different diode-load inverters using SN-TFTs with
different device dimensions. (b, e) Optical microscope images of
these two corresponding inverters. (c,f) Inverter voltage transfer
characteristic (red trace) and voltage gain (blue trace) of these two
corresponding inverters. Both inverters work with a V
DD
of 3V and
exhibit symmetric input/output behaviour. (g) Inverter voltage
transfer characteristics measured at different supply voltages (V
DD
). (h)
Curve showing the dependence between the inverter voltage gain and
supply voltage. Inset: schematic of the circuit with parasitic resistance
at the output node. ......................................................................................... 39
Figure 2.10 Integrated 2-input NAND and NOR circuits using separated carbon
nanotubes. (a, d) Schematic of diode-load 2-input NAND and NOR
circuits using SN-TFTs. (b, e) Optical microscope images of the
corresponding NAND and NOR circuits. (c, f) Output characteristics
of the corresponding NAND and NOR circuits. The supply voltages
for both circuits are V
DD
= 2V . Input voltages of 3V and 0V are
treated as logic “1” and “0”, respectively. ..................................................... 42
Figure 3.1 Structure of AMOLED circuit and layout. (a) Schematic diagram for
the circuit of AMOLED. Each pixel contains one switching transistor,
one driving transistor, one charge storage capacitor, and an OLED. (b)
Top view for the layout of a single pixel AMOLED with an area of
500 × 500 μm2. (c) Cross-sectional view for the structure of the
AMOLED pixel consisting of a glass substrate, patterned Ti/Au gate
electrode, Al2O3 gate dielectric, separated CNT thin film for the
active channel, Ti/Pd source and drain contacts, integrated OLED
(ITO/NPD/Alq3/LiF/Al), and a SiO2 passivation layer. ............................... 50
Figure 3.2 Carbon nanotube TFT performance as a function of nanotube density.
(a-c) FE-SEM images of separated CNT thin-films with different
densities obtained by tuning the ratio of APTES and IPA used in the
surface functionalization process. (d) Relationship between nanotube
film density and APTES : IPA ratio. (e, f) Channel length dependence
of device on/off ratio (e) and normalized on-current (f) for transistors
fabricated on nanotube films using different APTES : IPA ratios. (blue
trace for APTES : IPA = 1 :100, red trace for APTES : IPA = 1 :10,
and green trace for APTES : IPA = 1 :1). ...................................................... 52
Figure 3.3 AFM image of SiO
2
surface coated with APTES solution with different
concentration. (a) Blank SiO
2
surface. (b-d) SiO
2
surface
functionalized with solution of APTES and IPA volume ratio of 1:1,
1:10 and 1:100, respectively. From the images, one can find that the
xii

SiO
2
surface in Figure 3.3b has many impurities, while the one in
Figure 3.3d shows that APTES did not cover the whole surface. ................. 53
Figure 3.4 Electrical properties of transistors used in the AMOLED circuit. (a)
Schematic diagram of the back-gated transistor built on separated
nanotube thin-film with Ti/Au (5 Å/40 nm) back gate, Ti/Pd (5 Å/50
nm) contact electrodes, and the Al
2
O
3
/SiO
2
bilayer gate dielectric (40
nm/5 nm). (b) FE-SEM image showing the channel of a back-gated
SN-TFT with 20 μm channel length. (c) Transfer (I
D
-V
G
)
characteristics (red, linear scale; green, log scale) and g
m
-V
G

characteristics (blue) of a typical SN-TFT (L = 20 m, W = 100 μm)
with V
D
= 1 V . (d) Output (I
D
-V
D
) characteristics of the same device
with V
G
varying from -5 V to 5 V in 1 V steps. ............................................. 55
Figure 3.5 (a,c) SEM images of the separated nanotube thin-films deposited on
Al
2
O
3
and Al
2
O
3
/SiO
2
surface, respectively (b,d) SEM images for the
same samples after one step of photolithography. Nanotubes on the
Al
2
O
3
sample would peel off while the ones on Al
2
O
3
/SiO
2
bilayer
dielectric still stick to the surface. ................................................................. 56
Figure 3.6 Characteristics of the two-transistor single-pixel circuit. (a) Optical
microscope image of the single pixel circuit with two SN-TFTs, one
capacitor, and the ITO electrode for OLED integration. (b, c) Transfer
(I
D
-V
DA TA
) characteristics of the single pixel circuit measured while
V
SCAN
= -5 V in linear scale (V
DD
= 1 V to 0.2 V with 0.2 V steps)
and logarithm scale (V
DD
= 1 V), respectively. Inset: schematic
diagram of the single pixel circuit (d) Output (I
D
-V
DD
) characteristics
measured at V
SCAN
= -5 V with different V
DATA
(-5 V to 5 V with 1V
steps). ............................................................................................................. 57
Figure 3.7 AMOLED display characteristics. (a) Characteristics of the OLED
controlled by single pixel circuit, where the current flow through the
OLED (I
OLED
) is measured by sweeping the V
DD
. The family of curves
correspond to values of V
DATA
from -5 to 5 V in 1 V steps. (b) Plot of
the current through the OLED (I
OLED
) (red line) and OLED light
intensity (green line) versus V
DATA
with V
DD
= 8 V . (c) Photographs
showing that under different V
DATA
, the two-transistor single-pixel
circuit can turn on and turn off the OLED. (d) Optical image of an
AMOLED substrate containing 7 AMOLED elements, each with 20 ×
25 pixels. (e) Photograph showing the pixels on an integrated
AMOLED are turned on when V
DATA
= -5 V , V
SCAN
= -5V , and V
DD
=
8 V are applied for the pixels. ....................................................................... 59
Figure 4.1 Symmetric p-type and n-type SN-TFTs. (a) Schematic diagram of a
n-type back-gated SN-TFT with Ti/Au (5 Å/50 nm) contacts and SiO
2

xiii

(50 nm) gate dielectric. (b) Optical micrograph of the SN-TFT array
with various channel lengths (5, 10, 20, 50, and 100 μm) and channel
widths (10, 20, 50, 100 and 200 μm). (c) FE-SEM image of a typical
SN-TFT with 5 m channel length. (d, e) Transfer (I
D
-V
G
) (d) and
output (I
D
-V
D
) (e) characteristics of a typical SN-TFT (L = 5 m, W =
200 μm) before (blue) and after (red) HfO
2
ALD. (f, g) I
D
-V
G

characteristics (red: linear scale, green: logarithm scale) and g
m
-V
G

characteristics (blue) of the same device with V
D
= 1 V before (f) and
after (g) HfO
2
ALD, respectively. .................................................................. 68
Figure 4.2 Long term air-stability of the n-type SN-TFTs. As fabricated (blue) and
9 months later (red) transfer characteristics for two typical n-type
SN-TFTs with (a) HfO
2
(L = 5 μm, W = 200 μm) and (b) Al
2
O
3
(L = 5
μm, W = 100 μm) passivation measured with V
D
= 1 V . ............................... 70
Figure 4.3 The mechanism of the n-type SN-TFT passivated by ALD high-κ oxide
layer. (a) I
D
-V
G
characteristics of the SN-TFTs (L = 5 m, W = 200
μm) with ALD of HfO
2
deposited at different temperatures (150 ° C
and 250 ° C) measured at V
D
= 1 V . Inset: schematic diagram to
explain the conversion mechanism. (b) Band structure of the
nanotube-metal contact with (solid line) and without (dash line) ALD
layer under different gate voltages (V
G
> 0 V , V
G
= 0 V , and V
G
< 0 V).
(c) I
D
-V
G
characteristics of a typical SN-TFT (L = 5 m, W = 200 μm)
in logarithm scale before (red) and after HfO
2
(blue) and Al
2
O
3
(green)
ALD measured V
D
= 1 V . (d) Temperature dependence of the I
D
-V
G

characteristics of the SN-TFTs (L = 5 m, W = 200 μm) with ALD of
Al
2
O
3
measured at V
D
= 1 V . ......................................................................... 74
Figure 4.4 (a) Transfer characteristics of devices (L = 5 μm and W = 200 μm)
before (green) and after Al
2
O
3
ALD at 150 ° C (red) and 250 ° C (blue)
plotted in logarithm scale. (b) Statistic data of the n-type device
threshold voltages with HfO
2
(blue) and Al
2
O
3
(red) passivation. ................ 75
Figure 4.5 In-depth study of the factors affecting the n-type SN-TFT performance.
(a) I
D
-V
G
characteristics of the SN-TFTs measured at V
D
= 1 V with
the same channel width (W = 50 μm) and various channel lengths (L
= 5, 10, 20, 50, and 100 μm) measured at V
D
= 1 V plotted in
logarithm scale after ALD of HfO
2
deposited at 250 ° C. (b) Plot of
I
on_N
/I
on_P
(the ratio between the N-branch on-current and the P-branch
on-current) versus the reciprocal of channel length (1/L) for the
n-type SN-TFTs with Al
2
O
3
and HfO
2
passivation. N-branch and
P-branch on-currents are measured with V
D
= 1 V , V
G
= 5 V or -5 V ,
respectively. (c) Statistical data of normalized N-branch and P-branch
on-current density (I
on
/W) versus 1/L for devices with HfO
2
and Al
2
O
3

xiv

passivation. .................................................................................................... 77
Figure 4.6 The effect of different source/drain metal contact materials. (a, b) I
D
-V
G

characteristics of typical SN-TFTs (L = 5 m, W = 200 μm) with
Ti/Au (a) and Ti/Pd (b) metal contacts before and after Al
2
O
3
ALD
measured at V
D
= 1 V . .................................................................................... 78
Figure 4.7 Measured device resistivity as a function of channel length before
(blue) and after (red) HfO
2
ALD. .................................................................. 80
Figure 4.8 (a) Average normalized on-current density (I
on
/W) versus the reciprocal
of channel length (1/L), (b) average on-current (I
on
) versus channel
width when channel length equals 10 μm, (c) average on/off ratio
(I
on
/I
off
) versus channel length for p-type SN-TFTs (red), n-type
SN-TFTs with HfO
2
ALD (blue) and Al
2
O
3
ALD (green). ........................... 82
Figure 4.9 Average device mobility versus channel length for the p-type SN-TFTs
(red), n-type SN-TFTs with HfO
2
(blue), and n-type SN-TFTs with
Al
2
O
3
(green). ................................................................................................ 84
Figure 4.10 CMOS inverter circuit using almost symmetric p-type and n-type
SN-TFTs. (a) Experiment (scatter line) and simulation (dash line) data
of the I
D
-V
G
characteristics of typical p-type (blue) and n-type (red)
SN-TFTs (L = 5 m, W = 200 μm) used in the inverter with V
D
= 1 V .
(b) Inverter voltage (experiment: red straight trace; simulation: green
dash trace) and current (blue trace) transfer characteristics. Inset:
schematic diagram of the CMOS inverter. The inverter works with a
V
DD
of 5 V and exhibits symmetric input/output behavior. The
inverter threshold voltage (V
TH
) is 2.6 V . (c) Plot of inverter gain
versus input voltage where the highest gain is 8.4. The input low
voltage (V
IL
) and the input high voltage (V
IH
) are measured to be 1.8
V and 3.1 V , respectively. .............................................................................. 86
Figure 4.11 CMOS integrated logic circuits. (a) Schematic diagram of the
integrated CMOS inverter based on n-type and p-type SN-TFTs. (b, c)
Output characteristics of the corresponding NAND and NOR circuits.
The supply voltages for both circuits are V
DD
= 5V . Input voltages of
5V and 0V are treated as logic “1” and “0”, respectively. ............................. 89
Figure 5.1 Fully transparent separated carbon nanotube devices. (a) Schematic
diagram of a transparent SN-TFT with ITO (100 nm) as back gate,
Al
2
O
3
/SiO
2
(40 nm/5 nm) as gate dielectric, and ITO (100 nm) as
source and drain contacts. (b) FE-SEM image of the separated carbon
nanotube thin-film inside the transistor channel region. (c) Optical
transmittance of the bare glass substrate (red curve) and glass with
xv

arrays of transparent SN-TFTs with ITO contacts (blue curve). Inset:
Optical image of the fully transparent SN-TFTs on 2 inch square
shape glass substrate with the substrate area marked with a red frame
for clarity. (d) Schematic diagram showing the fabrication steps for
transparent SN-TFTs on flexible substrates. (e) Optical image of
transparent SN-TFTs on PET substrate. ........................................................ 98
Figure 5.2 Electrical performance of the transparent devices with ITO electrodes.
(a) Transfer (I
D
-V
G
) characteristics (red, linear scale; green, log scale)
and g
m
-V
G
characteristics (blue) of a typical SN-TFT (L = 100 m, W
= 100 μm) with V
D
= 1 V . (b) I
D
-V
G
characteristics of a typical
SN-TFT (L = 100 m, W = 100 μm) under different V
D
from 0.2 to
1.0 V (the step of V
D
was 0.2 V). (c, d) Output (I
D
-V
D
) characteristics
of the same device in triode regime (c) and saturation regime (d),
respectively. ................................................................................................. 100
Figure 5.3 Optical transmittance of the 1 nm Au (red) and 1 nm Pd (blue)
thin-film. Inset: Photography of the thin metal films on glass slides. ......... 102
Figure 5.4 Transparent transistors with improved contacts. (a) Schematic diagram
of the improved transparent SN-TFT structure with Au/Pd + ITO as
the source and drain contacts. (b) Typical I
D
-V
D
plots for devices with
the same channel geometry (L = 20 m, W = 100 μm) but with
Au/ITO (red), Pd/ITO (black), and ITO (blue) contacts under V
G
= -5
V , respectively. (c) Optical transmittance of glass substrates with
arrays of transparent SN-TFTs with Au/ITO (green curve), Pd/ITO
(blue curve), and ITO (red curve) contacts. (d, e) Transfer (I
D
-V
G
)
characteristics (red, linear scale; green, log scale) and g
m
-V
G

characteristics (blue) of the typical SN-TFTs (L = 100 m, W = 100
μm) with Au/ITO (d) and Pd/ITO (e) contacts measured at V
D
= 1 V ,
respectively. ................................................................................................. 104
Figure 5.5 Fully transparent and flexible SN-TFTs. (a) Optical transmittance of a
PET substrate with transparent SN-TFTs with Au/ITO contacts. (b)
Transfer (I
D
-V
G
) characteristics of a representative device (L = 100
m, W = 100 μm) under different bending radius in linear and
logarithm scales. (c) Normalized transconductance (red) and on/off
ratio (blue) extracted from the data in Figure 5.6b versus bending
radius. Inset shows an optical micrograph of the experimental setup to
measure I
D
-V
G
under different bending radius. (d) Output (I
D
-V
D
)
characteristics of the same device under different gate voltages with
bending radius of 6.4 mm. Vg was swept from -5 V (black curve) to 2
V with 1 V steps. ......................................................................................... 106
xvi

Figure 5.6 OLED control circuit by transparent SN-TFT. (a)Transfer (I
D
-V
G
)
characteristics under different drain voltages (from 0.2 V to 1 V with
0.2 V steps) for the device used to control the OLED (L = 100 m, W
= 100 μm), Inset: I
D
-V
G
plot of the same device in logarithm scale
with V
D
= 1 V . (b) Output (I
D
-V
D
) characteristics of the same device
with different gate voltages. (c) I
OLED
-V
DD
Characteristics of the
OLED control circuit. Various curves correspond to various values of
V
G
from -5 to 5 V in 1 V steps. Inset: Schematic diagram of the
OLED control circuit. (d) Plot of the current through the OLED
(I
OLED
) versus V
G
with VDD= -8 V . The inset optical images show the
OLED intensity at certain gate voltages. ..................................................... 108
Figure 6.1 The Raman shift of arc-discharge, HiPCO and CoMoCAT SWNTs and
their respective G/D ratios. ...........................................................................116
Figure 6.2 Comparison of gel-based column chromatographic separated
nanotubes synthesized by different methods. (a-c) UV-Vis-NIR
absorption spectra of arc-discharge nanotubes (a), HiPCO nanotubes
(b), and CoMoCAT nanotubes (c) before (blue) and after (red)
separation. Inset: Nanotube solutions after separation. (d-f) Length
distribution of the separated semiconducting arc-discharge nanotubes
(d), HiPCO nanotubes (e), and CoMoCAT nanotubes (f), the average
nanotube length is 540 nm, 617 nm, and 576 nm, respectively. Inset:
FE-SEM images of separated semiconducting nanotubes network
deposited on Si/SiO
2
substrates with APTES functionalization, where
the scale bar is 1 µ m. (g) Schematic diagram of a back-gated SN-TFT.
(h) Optical microscope image of the SN-TFT array fabricated on
silicon substrate with 50 nm SiO
2
acting as gate dielectric. .........................118
Figure 6.3 Electrical properties of back-gated SN-TFTs using gel-based separated
semiconducting nanotubes synthesized with different methods. (a-c)
Normalized transfer characteristics (I
D
/W-V
G
) of the SN-TFTs using
semiconducting arc-discharge nanotubes (a), HiPCO nanotubes (b),
and CoMoCAT nanotubes (c) with various channel lengths (4, 10, 20,
50, and 100 μm) and 2000 μm channel width plotted in logarithm
scale. (d-f) Transfer characteristics (red: linear scale, green: log scale)
and g
m
-V
G
characteristics (blue) of a typical SN-TFT (L = 10 μm, W =
2000 μm) using semiconducting arc-discharge nanotubes (d), HiPCO
nanotubes (e), and CoMoCAT nanotubes (f). (g-i) Output
characteristics (I
D
-V
D
) of the same devices in (d-f). .................................... 120
Figure 6.4 Statistical study and key device performance metrics comparison of
SN-TFTs using separated nanotubes with different synthetic methods.
(a) Current density (I
on
/W) versus reversed channel length for TFTs
xvii

fabricated on separated semiconducting nanotubes synthesized by
arc-discharge (blue), HiPCO (red), and CoMoCAT (green) methods.
Plot of (b) device resistance and (c) average on/off ratio (I
on
/I
off
)
versus channel length for the same TFTs characterized in (a). (d)
Trade-off between Current density (I
on
/W) and on/off ratio (I
on
/I
off
). (e)
On/off ratio (I
on
/I
off
) versus drain voltage for devices using three
different kinds of semiconducting nanotubes with L = 50 μm and W =
1200 μm. (f) Relationship between device mobility and channel
length for three kinds of SN-TFTs............................................................... 123
Figure 6.5 Comparison of key device performance metrics of SN-TFTs using
semiconducting arc-discharge nanotubes separated by DGU and
gel-based column chromatographic methods. (a) UV-Vis-NIR
absorption spectra of semiconducting arc-discharge nanotubes
separated by DGU (blue) and gel-based column chromatographic (red)
methods. (b) Current density (I
on
/W) versus reversed channel length
for TFTs fabricated on semiconducting nanotubes separated by DGU
(blue) and gel-based (red) methods. Plot of (b) average on/off ratio
(I
on
/I
off
) and (c) device mobility (μ
device
) versus channel length for the
same devices measured in (b). ..................................................................... 133
Figure 7.1 IGZO n-type transistor performance. (a) Transfer characteristics in
linear (red) and logarithm (blue) scales. (b) Symmetric n-type (IGZO)
and p-type (separated nanotube) transistors ................................................ 141
Figure 7.2 Hybrid integrated CMOS logic circuits. (a) V oltage and current transfer
characteristics of the integrated CMOS inverter. (b) Output
characteristics of a five stage ring oscillator. (c, d) Schematic and
output characteristics of the integrated CMOS XOR gate. ......................... 142
Figure 7.3 (a) V oltage programming 2T1C circuit structure. (b, c) AMOLED (b)
and LCD (c) display structure ..................................................................... 144
Figure 7.4 Luminance uniformity improvement. (a) Luminance non-uniformity of
the 2T1C pixel caused by variations in the transistor output
characteristics. (b) Improved pixel luminance uniformity using
current programming circuit. ....................................................................... 145
Figure 7.5 Typical 4T1C current programming circuits and their corresponding
layout designs. ............................................................................................. 146

xviii

Abstract
In this dissertation, I discuss the application of carbon nanotubes in macroelectronis.
Due to the extraordinary electrical properties such as high intrinsic carrier mobility and
current-carrying capacity, single wall carbon nanotubes are very desirable for thin-film
transistor (TFT) applications such as flat panel display, transparent electronics, as well as
flexible and stretchable electronics. Compared with other popular channel material for
TFTs, namely amorphous silicon, polycrystalline silicon and organic materials, nanotube
thin-films have the advantages of low-temperature processing compatibility, transparency,
and flexibility, as well as high device performance.
In order to demonstrate scalable, practical carbon nanotube macroelectroncis, I have
developed a platform to fabricate high-density, uniform separated nanotube based
thin-film transistors. In addition, many other essential analysis as well as technology
components, such as nanotube film density control, purity and diameter dependent
semiconducting nanotube electrical performance study, air-stable n-type transistor
fabrication, and CMOS integration platform have also been demonstrated. On the basis of
the above achievement, I have further demonstrated various kinds of applications
including AMOLED display electronics, PMOS and CMOS logic circuits, flexible and
transparent electronics.
The dissertation is structured as follows. First, chapter 1 gives a brief introduction to
the electronic properties of carbon nanotubes, which serves as the background knowledge
for the following chapters. In chapter 2, I will present our approach of fabricating
wafer-scale uniform semiconducting carbon nanotube thin-film transistors and
xix

demonstrate their application in display electronics and logic circuits. Following that,
more detailed information about carbon nanotube thin-film transistor based active matrix
organic light-emitting diode (AMOLED) displays is discussed in chapter 3. And in
chapter 4, a technology to fabricate air-stable n-type semiconducting nanotube thin-film
transistor is developed and complementary metal–oxide–semiconductor (CMOS) logic
circuits are demonstrated. Chapter 5 discusses the application of carbon nanotubes in
transparent and flexible electronics. After that, in chapter 6, a simple and low cost
nanotube separation method is introduced and the electrical performance of separated
nanotubes with different diameter is studied. Finally, in chapter 7 a brief summary is
drawn and some future research directions are proposed with preliminary results.

1

Chapter 1: Introduction

1.1 Introduction of carbon nanotubes
Since first discovered by Sumio Ijima at NEC laboratory in Japan in 1991 [1], carbon
nanotubes have attracted tremendous research interest from fundamental science and
technological perspectives and are among the most explored one-dimensional
nanostructures. Due to their low dimensionality, carbon nanotubes (CNTs) possess unique
properties that make them promising candidates for future technology applications.
Depends on its geometry, nanotubes can be either metallic or semiconducting. For
semiconducting nanotubes, they have very long mean free path (in the order of a few
hundred nanometers) for the carriers and therefore offer scatter-free ballistic transport. [2]
At the meantime, the carrier mobility of semiconducting nanotubes is experimentally
measured to be > 10,000 cm
2
/Vs, [3,4] which is much higher than the state-of-the-art
silicon transistors. For metallic nanotubes, they have high current-carrying capability (>
10
10
A/cm
2
), which is better than the best metal interconnection material used in
semiconducting industry (Cu), and overcomes the problem of electromigration due to the
strong C-C bond. SWNTs also exhibit excellent thermal conductivity, [5] and
extraordinary mechanical properties, with Young’s modulus over 1 TPa [6] and tensile
strength over 200 GPa. Furthermore, due to the ultra-high surface-to-volume ratio of
carbon nanotubes, they can be also employed to work as high-performance chemical
sensors [7] and biosensors. [8]
2

1.2 Structure of carbon nanotubes [9]
Carbon nanotubes can be considered as graphene sheets with honeycomb structure
being rolled up into seamless, hollow cylinders, which is shown in Figure 1.1. Depending
on the number of graphene layers used, nanotubes can be categorized into single-walled
carbon nanotube (SWNT) and multi-walled carbon nanotube (MWNT). The basis vectors
a
1
= a( 3 , 0) and a
2
= a( 3 /2, 3/2) generate the graphene lattice, where a = 0.142 nm
is the carbon–carbon bond length. A and B are the two atoms in the unit cell of graphene.
In cutting the rectangular strip, one defines a circumferential vector, C = na
1
+ma
2
, from
which the CNT radius can be obtained: R = C/2π = ( 3 /2π)a mn m n + +
2
2
. When the
circumferential vector lies purely along one of the two basis vectors, the CNT is said to
be of the ‘zigzag’ type, as shown in Figure 1.1a. When the circumferential vector is along
the direction exactly between the two basis vectors (n = m), the CNT is said to be of
‘armchair’ type, as shown in Figure 1.1b. Figure 1.1c shows a nanotube with arbitrary
chirality (n,m), where the blue strip is generated by m ≠ n.
3

Figure 1.1 Structure of carbon nanotube. (a) a
1
and a
2
are the lattice vectors of graphene. |a
1
|=|a
2
|= √3a, where a is the
carbon–carbon bond length. There are two atoms per unit cell shown by A and B. SWNTs are equivalent to cutting a
strip in the graphene sheet (blue) and rolling them up such that each carbon atoms is bonded to its three nearest
neighbours. The creation of a (n, 0) zigzag nanotube is shown. (b) Creation of a (n, n) armchair nanotube. (c)A (n,m)
chiral nanotube. [9]
1.3 Electronic properties of carbon nanotubes [10]
Each carbon atom in the hexagonal lattice described in section 1.2 possesses six
electrons, and in the graphite structure carbon has two 1s electrons, three 2sp
2
electrons
and one 2p electron. The three 2sp
2
electrons form the three bonds in the plane of the
graphene sheet, leaving an unsaturated π orbital. This π orbital, perpendicular to the
graphene sheet and thus the nanotube surface, forms a delocalized π network across the
nanotube, responsible for its electronic properties.
2D energy dispersion relations of graphene can be found by solving the eigenvalue
problem for a (2× 2) Hamiltonian H and a (2× 2) overlap integral matrix S, associated with
4

the two inequivalent carbon atoms in 2D graphene [10], which is:
) ( 1
) (
) (
0 2
2
k s
k
k E
p
D g

  




, where
2
cos 4
2
cos
2
3
cos 4 1 ) (
2
a k a k
a k
k
y y
x
   
the electronic energy dispersion relations for graphene as a function of the
two-dimensional wave vectors k in the Brillouin zone is plotted in Figure 1.2. As shown
in this figure, these two bands have linear dispersion and meet at the Fermi level at the K
point in the Brillouin zone. The Fermi surface of an ideal graphene sheet consists of the
six corner K points[(±4π/3 3 a, 0); ( ±2π/3 3 a,±2π/3a)]. Graphene is thus described as
a semi-metal: it has a non-zero density of states at the Fermi level, but the Fermi surface
consists only of points.

Figure 1.2 The energy dispersion relations for graphene with γ0 = 3.013 eV, s = 0.129 and ε2p = 0. The inset shows the
energy dispersion along the high symmetry lines between the Γ, M, and K points. [10]
The band structure of the nanotube can be further derived based on the results from
graphene. When forming a tube, owing to the periodic boundary conditions imposed in
the circumferential direction, the electron wavevector along that direction is quantized.
5

As shonw in Figure 1.3, the wave vector (K
1
) along the circumferential direction of
nanotube becomes quantized due to the periodic boundary condition, and the wave vector
(K
2
) along the nanotube axis remains continuous for a nanotube of infinite length.
Therefore, based on the energy dispersion relations of graphene, the 1D energy dispersion
relations of a SWNT are given by:






   








 
 
N and
T
k
T
K
K
K
k k E k E
D g
,....., 2 , 1 , , ) ( ) (
1
2
2
2

 



Where T is the magnitude of the translational vector T, k is a 1D wave vector along
the nanotube axis, and N denotes the number of hexagons of the graphene honeycomb
lattice that lie within the nanotube unit cell. T and N can be calculated using the following
equations,
R
mn m n
N and
R
C
T
) (
,
2
3
2 2
 
 
The N pairs of energy dispersion curves correspond to the cross sections of the cuts
made on the lines of
1
2
2
K
K
K
k   on the graphene energy dispersion relationship shown
in Figure 1.2. From the equation, we can find that due to the quantization in the nanotube
circumferential direction, only a certain set of k states of the planar graphene sheet is
allowed, as indicated by the lines in Figure 1.3. Depending on the chirality (m, n) of the
nanotube, if the allowed states pass through a K point of the 2D Brillouin Zone, then the
nanotube has a zero energy gap and a nonzero density of states at the Fermi level,
resulting in a one-dimensional metal with 2 linear dispersing bands. On the other hand, if
the cutting lines do not pass through any of the K points, then the nanotube is
6

semiconducting with a finite energy gap between the valence and conduction bands.
Moreover, it is important to note that the states near the Fermi energy in both the metallic
and the semiconducting nanotubes are all from states near the K point, and hence their
transport and other properties are related to the properties of the states on these allowed
lines. For example, the conduction band and valence bands of a semiconducting nanotube
come from states along the lines closest to the K point.
The general rules for the metallicity of the single-walled carbon nanotubes are as
follows: (m, m) nanotubes (armchair nanotubes) are all metallic; (m, n) nanotubes with
m-n = 3j, where j is a nonzero integer, are very tiny-gap semiconductors; and all others
are large-gap semiconductors. Based on this rule of thumb, we can infer that one third of
the nanotubes are metallic and the other two thirds are Semiconducting. Moreover, the
bandgap for a semiconducting nanotube is dependent on its diameter. As the nanotube
radius R increases, the bandgaps of the large-gap and tiny-gap nanotubes decreases with
1/R and 1/R
2
dependence, respectively.

Figure 1.3 Illustration of allowed wavevector lines leading to semiconducting and metallic CNTs and examples of
bandstructures for semiconducting and metallic zigzag CNTs. [9]
7

Furthermore, based on the energy dispersion relations, the 1D density of states (DOS)
in units of states/C-atom/eV of the nanotube can be calculated. Figure 1.4 shows the
comparison of DOS for semiconducting (11, 0) and metallic (12, 0) nanotubes. We can
notice the difference between these two cases near the Fermi level E
F
located at E = 0,
where the DOS is zero for semiconducting nanotubes, and is non-zero for metallic ones.
In addition, the more interesting things are the kinks in DOS, which are the
characteristics of 1D systems and are called Van Hove singularities. These Van Hove
singularities are very important for determining many solid-state properties of carbon
nanotubes, such as the spectra observed by scanning tunneling spectroscopy, optical
absorption, and resonant Raman spectroscopy.

Figure 1.4 Density of states for (11,0) and (12,0) CNTs computed from tight binding show Van Hove singularities. [9]

8

1.4 Outline of the dissertation
Due to its excellent properties, carbon nanotube has attracted numerous research
effects in the past two decades, and many exciting results in nanoelectrincs field have
been demonstrated such as ballistic field-effect transistors [2,11], medium-scale
integrated circuits [12] and radio frequency transistors [13-15]. All of these achievements
in nanoelectronics make carbon nanotube look very promising as the candidate to replace
Si for future semiconducting industry.

Figure 1.5 Carbon nanotube applications in nanoelectronics(a) and macroelectronics(b).
Other than the application in nanoelectroncis, carbon nanotube also holds great
potential for macroelectronic applications, where, compared to nanoelectroncs, relatively
less effect has been made so far. Here, macroelectronics refers to the applications which
9

do not focus on the improvement of individual device performance or the scaling down of
transistor dimensions, but requires the ability to fabricate transistor with similar
performance uniformity over very large areas (tens of inches). Typical applications are
shown in Figure 1.5, which includes printed electronics, flexible electronics and display
electronics. In this dissertation, I will mainly focus on the application of carbon
nanotubes in macroelectronic field.
The dissertation is structured as follows. First, chapter 1 gives a brief introduction to
the electronic properties of carbon nanotubes, which serves as the background knowledge
for the following chapters. In chapter 2, I will present our approach of fabricating
wafer-scale uniform semiconducting carbon nanotube thin-film transistors and
demonstrate their application in display electronics and logic circuits. Following that,
more detailed information about carbon nanotube thin-film transistor based active matrix
organic light-emitting diode (AMOLED) displays is discussed in chapter 3. And in
chapter 4, a technology to fabricate air-stable n-type semiconducting nanotube thin-film
transistor is developed and complementary metal–oxide–semiconductor (CMOS) logic
circuits are demonstrated. Chapter 5 discusses the application of carbon nanotubes in
transparent and flexible electronics. After that, in chapter 6, a simple and low cost
nanotube separation method is introduced and the electrical performance of separated
nanotubes with different diameter is studied. Finally, in chapter 7 a brief summary is
drawn and some future research directions are proposed with preliminary results.

10

Chapter 1. References

1. Iijima, S. Helical Microtubules of Graphitic Carbon. Nature 1991, 354, 56-58.
2. Javey, A.; Guo, J.; Wang, Q.; Lundstrom, M.; Dai, H. J. Ballistic Carbon Nanotube
Field-Effect Transistors. Nature 2003, 424, 654-657.
3. Dü rkop, T.; Getty, S. A.; Cobas, E.; Fuhrer, M. S. Extraordinary Mobility in
Semiconducting Carbon Nanotubes. Nano Lett. 2003, 4, 35-39.
4. Zhou, X.; Park, J.-Y.; Huang, S.; Liu, J.; McEuen, P. L. Band Structure, Phonon
Scattering, and the Performance Limit of Single-Walled Carbon Nanotube
Transistors. Phys. Rev. Lett. 2005, 95, 146805.
5. Ruoff, R. S.; Lorents, D. C. Mechanical and Thermal-Properties of Carbon
Nanotubes. Carbon 1995, 33, 925-930.
6. Treacy, M. M. J.; Ebbesen, T. W.; Gibson, J. M. Exceptionally High Young's
Modulus Observed for Individual Carbon Nanotubes. Nature 1996, 381, 678-680.
7. Kong, J.; Franklin, N. R.; Zhou, C. W.; Chapline, M. G.; Peng, S.; Cho, K. J.; Dai, H.
J. Nanotube Molecular Wires as Chemical Sensors. Science 2000, 287, 622-625.
8. Chen, R. J.; Bangsaruntip, S.; Drouvalakis, K. A.; Kam, N. W. S.; Shim, M.; Li, Y.
M.; Kim, W.; Utz, P. J.; Dai, H. J. Noncovalent Functionalization of Carbon
Nanotubes for Highly Specific Electronic Biosensors. Proc. Natl. Acad. Sci. U.S.A.
2003, 100, 4984-4989.
9. Anantram, M. P.; Leonard, F. Physics of Carbon Nanotube Electronic Devices. Rep.
Prog. Phys. 2006, 69, 507-561.
10. Saito, R.; Dresselhaus, G.; Dresselhaus, M. S., Physical Properties of Carbon
Nanotubes. Imperial College Press: London, 1998.
11. Zhang, Z. Y.; Liang, X. L.; Wang, S.; Yao, K.; Hu, Y. F.; Zhu, Y. Z.; Chen, Q.; Zhou,
W. W.; Li, Y.; Yao, Y. G.; et al. Doping-Free Fabrication of Carbon Nanotube
Based Ballistic Cmos Devices and Circuits. Nano Lett. 2007, 7, 3603-3607.
12. Cao, Q.; Kim, H. S.; Pimparkar, N.; Kulkarni, J. P.; Wang, C.; Shim, M.; Roy, K.;
Alam, M. A.; Rogers, J. A. Medium-Scale Carbon Nanotube Thin-Film Integrated
Circuits on Flexible Plastic Substrates. Nature 2008, 454, 495-500.
13. Li, S. D.; Yu, Z.; Yen, S. F.; Tang, W. C.; Burke, P. J. Carbon Nanotube Transistor
Operation at 2.6 Ghz. Nano Lett. 2004, 4, 753-756.
14. Kocabas, C.; Dunham, S.; Cao, Q.; Cimino, K.; Ho, X. N.; Kim, H. S.; Dawson, D.;
Payne, J.; Stuenkel, M.; Zhang, H.; et al. High-Frequency Performance of
Submicrometer Transistors That Use Aligned Arrays of Single-Walled Carbon
Nanotubes. Nano Lett. 2009, 9, 1937-1943.
15. Che, Y.; Badmaev, A.; Jooyaie, A.; Wu, T.; Zhang, J.; Wang, C.; Galatsis, K.; Enaya,
H. A.; Zhou, C. Self-Aligned T-Gate High-Purity Semiconducting Carbon Nanotube
Rf Transistors Operated in Quasi-Ballistic Transport and Quantum Capacitance
Regime. ACS Nano 2012, 6, 6936-6943.
11

Chapter 2: Wafer-Scale Fabrication of Separated Carbon
Nanotube Thin-Film Transistors for Display and Digital
Circuit Applications

2.1 Introduction
As the most widely used channel material for thin film transistors (TFTs), amorphous
silicon, suffers from drawbacks that it requires high-temperature processing and the
mobility is relatively low. [1-6]

Organic TFTs as a replacement for amorphous silicon
based TFTs receives lots of attention, while on the other hand, they also suffer from poor
device mobility. [7,8] Single-walled carbon nanotubes (SWNTs) offers high intrinsic
carrier mobility and current-carrying capacity, and have already been used to demonstrate
ballistic and high mobility transistors, [9-11] and integrated logic circuits such as
inverters and ring-oscillators. [12-16]

Thin-films of SWNTs which possess extraordinary
conductivity, transparency and flexibility have been achieved using either solution based
filtration or chemical vapour deposition (CVD) growth, and TFTs based on SWNTs have
also been demonstrated and offers outstanding electrical properties as expected. [17-22]
However, all of the work mentioned above shares the same drawback which is the
co-existence of both metallic and semiconductive nanotubes with approximate 33%
nanotubes being metallic.
Recently, significant advance has been made on CVD grown nanotube networks for
flexible devices and circuits by using stripe-patterning to remove heterogeneous
percolative transport through metallic nanotube networks and increase the average device
12

on/off ratio to 10
4
. This technique nevertheless requires additional fabrication steps of
stripe patterning and large device dimensions. [23]
Alternatively, the problem of the co-existence of metallic and semiconductive
nanotubes can be solved using pre-separated semiconductive enriched nanotubes
produced by density gradient ultracentrifugation. [24,25] Based on the separated
nanotubes, TFTs have been demonstrated by the IBM research group. [26] 99%
semiconductive nanotubes were deposited using a sophisticated evaporation
self-assembly method and the devices exhibited on/off ratios of more than 10
3
with
channel length L = 4 m, sheet resistance of ~ 200 kΩ/sq, and mobility of ~ 10 cm
2
V
-1
s
-1
.
In spite of the significant progress, many interesting issues remain to be studied. For
example, can one use a simple and reliable method to assemble nanotubes besides the
evaporation self-assembly method? What are the key factors affecting the TFT
performance?
To answer the above mentioned questions, in this chapter, we report our recent
advance on wafer-scale processing of SN-TFTs and their potential application in display
electronics. Surprisingly, we have produced TFTs using enriched semiconductive
nanotubes with overall better performance than previous work [26] using 99% enriched
nanotubes. Our work includes the following essential components. (1) Uniform and high
density separated nanotube thin-films were deposited onto 3 inch Si/SiO
2
wafers using a
facile solution based assembly method. (2) Wafer-scale device fabrication was
performed on 3 inch Si/SiO
2
wafers to yield SN-TFTs with high yield (> 98%), small
sheet resistance (~ 25 kΩ/sq), high current density (~ 10 A/ m), high mobility (~ 26
13

cm
2
V
-1
s
-1
) and good on/off ratio (> 10
4
). (3) Comparison between TFTs using separated
and CVD-grown nanotubes. (4) Effect of semiconducting purity (3) OLED control circuit
has been demonstrated using the SN-TFT with output light intensity modulation over 10
4
.
(4) Basic logic gates including inverters, NAND and NOR gates. Our wafer-scale
processing of SN-TFTs shows significant advantage over conventional platforms with
respect to scalability, reproducibility and device performance, and suggests a practical
and realistic approach for nanotube based integrated circuit applications.
2.2 Wafer-scale separated carbon nanotube thin-film deposition
Figure 2.1 illustrates our wafer-scale processing of SN-TFTs including aminosilane
assisted nanotube deposition and device fabrication. In order to improve the density and
uniformity of the solution based nanotube assembly, aminosilane is introduced due to its
well-known affinity to the carbon nanotubes. [27,28] In this work, aminopropyltriethoxy
silane (APTES) is used to functionalize the Si/SiO
2
surface to form amine-terminated
monolayer and the schematic of the APTES assisted deposition is shown in Figure 2.1a.
The detailed procedure of wafer scale-separated nanotube assembly begins with using
corona discharge generator to generate UV ozone to clean the surface of the Si/SiO
2
wafer making it hydrophilic. Next, the cleaned wafer is immersed into diluted APTES
solution (3 drops of APTES in 20 mL of isopropanol alcohol (IPA)) for 10 minutes, then
rinsed with IPA and blew dry thoroughly. After APTES functionalization, the wafer is
immersed into the commercially available (NanoIntegris, Inc.) 0.01 mg/mL separated
nanotube solution with 95% semiconducting nanotubes for 20 minutes. The length
distribution of the semiconductive nanotubes is measured by field-emission scanning
14

Figure 2.1 Wafer-scale deposition of separated carbon nanotubes and fabrication of SN-TFTs. (a) Schematic diagram
of APTES assisted nanotube deposition on Si/SiO2 substrate. (b) Length distribution of the separated nanotubes used in
this study (95% semiconductive nanotubes purchased from NanoIntegris, Inc.), the average nanotube length is 1.716
μm. (c, d) FE-SEM images of separated nanotubes deposited on Si/SiO2 substrates with (c) and without (d) APTES
functionalization, respectively. (e) Photograph of 4 in. Si/SiO
2
wafer after APTES assisted nanotubes deposition. Inset:
FE-SEM images showing nanotubes deposited at different locations on the wafer, the locations of the SEM images on
the wafer correspond to the approximate locations on the wafer where the images were taken. All the scale bars are 5
μm. (f) Photograph of the same wafer after electrode patterning. The wafer consists of SN-TFTs used in this study and
other types of electronic devices. Such SN-TFTs are made with channel width (W) of 10, 20, 50, 100, and 200 μm, and
channel length (L) of 4, 10, 20, 50, and 100 μm.
c d
b
a
e f
0.5 1.0 1.5 2.0 2.5 3.0 3.5
0
1
2
3
4
5
6
7
8

Number of Tubes
Nanotube Length ( m)
Average CNT length = 1.716 m
15

electron microscope (FE-SEM) and the results are shown in Figure 2.1b. The average
length is measured to be 1.7 μm, which is longer than 1μm for 99% semiconducting
nanotubes as reported in the literature. [26] As a final step, IPA and deionized water
rinsing are used to remove the sodium dodecyl sulfate (SDS) residuals on the nanotubes,
and the wafer is blew dry with N
2
.
FE-SEM was used to inspect the surface after nanotube assembly. Figure 2.1c and
5.1d are the SEM images of the separated nanotubes deposited on Si/SiO
2
substrates with
and without APTES functionalization, respectively. From the image, one can find that the
sample with APTES functionalization gives much higher nanotube density than the
sample without APTES. Besides high density, APTES functionalization also helps to give
uniform deposition throughout the wafer. Figure 2.1e shows the photograph of a 3-inch
Si/SiO
2
wafer after APTES assisted nanotube deposition. There is no abnormal colour or
junk left on the wafer after the deposition and cleaning process. In order to determine the
deposition uniformity, SEM images were taken at nine different locations on the wafer. In
Figure 2.1e, the locations of the SEM images on the wafer correspond to the approximate
locations on the wafer where the images were taken and all the scale bars correspond to 5
μm. The SEM images indicate that high density, uniform deposition is achieved
throughout the 3 inch wafer.
Following the nanotube deposition is the device fabrication process. 50 nm SiO
2
is
used to act as the back-gate dielectric. The source and drain electrodes are patterned by
photolithography, and 5 Å Ti and 70 nm Pd are deposited followed by the lift-off process
to form the source and drain metal contacts. Finally, since the separated nanotube
16

thin-film cover the entire wafer, in order to achieve accurate channel length and width
and to remove the possible leakage in the devices, one more step of photolithography
plus O
2
plasma is used to remove the unwanted nanotubes outside the device channel
region. Figure 2.1f is a photograph of the wafer after electrode patterning. The wafer
consists of SN-TFTs used in this study and other types of electronic devices. Such
SN-TFTs are made with channel width (W) of 10, 20, 50, 100, and 200 μm, and channel
length (L) of 4, 10, 20, 50, and 100 μm.

2.3 Separated carbon nanotube thin-film transistors
We carried out systematic study of the electrical performance of the SN-TFTs as
basic components for macroelectronic integrated circuits and display electronics. Figure
2.2a shows the schematic diagram of a back-gated SN-TFT built on separated nanotube
thin-film with Ti/Pd (5 Å /70 nm) contacts and SiO
2
(50nm) gate dielectric. The SEM
image of the channel of a typical SN-TFT with 4 m channel length is shown in Figure
2.2b. Figure 2.2c and d are the output (I
D
-V
D
) characteristics of a typical SN-TFT (L = 20
m, and W = 100 μm) measured in triode region and saturation region, respectively. The
I
D
– V
D
curves appear to be very linear for V
D
between -1V and 1V , indicating that ohmic
contacts are formed between the electrodes and the nanotubes. Under more negative V
D
,
these devices typically exhibit saturation behaviour, as shown in Figure 2.2d. Figure 2.2e
shows the transfer (I
D
-V
G
) characteristics (red: linear scale, green: log scale) and g
m
-V
G

characteristics (blue) of the same representative device with V
D
= 1V . The on-current at
17

Figure 2.2 Electronic properties of back-gated SN-TFTs (a) Schematic diagram of a back-gated transistor built on
separated nanotube thin-film with Ti/Pd (5 Å /70 nm) contacts and SiO
2
(50nm) gate dielectric. b) FE-SEM image of a
typical SN-TFT with 4 m channel length. (c, d) Output (I
D
-V
D
) characteristics of a typical SN-TFT (L = 20 m, and W
= 100 μm) in triode region (c) and saturation region (d), respectively. (e) Transfer (I
D
-V
G
) characteristics (red: linear
scale, green: log scale) and g
m
-V
G
characteristics (blue) of the same device with V
D
= 1V. (f) Current density (I
on
/W)
measured at V
D
= 1V and threshold voltage (V
th
) of 10 representative SN-TFTs showing the uniformity of devices. The
red line represents the average value.

b
a
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
-10 -5 0 5 10
0
5
10
15
20

Gate Voltage (V)
Drain Current ( A)
0
1
2
3
4
Transconductance ( S)
Drain Current (A)

-10 -8 -6 -4 -2 0
-70
-60
-50
-40
-30
-20
-10
0

Drain Current ( A)
Drain Voltage (V)
Vg is from -10V to
0V in 1V steps
-1.0 -0.5 0.0 0.5 1.0
-20
-15
-10
-5
0
5
10
15
20

Drain Current ( A)
Drain Voltage (V)
Vg is from -10V to
10V in 2V steps
d
e
c
1 2 3 4 5 6 7 8 9 10
0
3
6
9
12
1 2 3 4 5 6 7 8 9 10
-6
-5
-4
-3
-2

I
on
/W ( A/ m)

Device number

V
th
(V)
f
18

V
D
= 1V is measured to be 18.5 μA, corresponding to a current density of 0.185 μA/μm.
The on/off ratio exceeds 10
4
and the transconductance is 3.3 μS. Furthermore, due to the
high density and uniform nature of the separated nanotube thin-film deposited on Si/SiO
2

substrates with APTES functionalization, the SN-TFTs are also expected to behave
uniformly. The uniformity of the devices is illustrated in Figure 2.2f which shows the
current density (I
on
/W) measured at V
D
= 1V and threshold voltage (V
th
) of 10
representative SN-TFTs with L = 4μm. The red lines represent the average values and one
can find that those device parameters have much smaller distribution compared with
single nanotube devices.
2.4 Comparison between TFTs using separated and CVD-grown
nanotubes
CVD grown nanotube thin-films with mixed nanotubes have also been used to
demonstrate TFTs and significant advance has been made toward flexible devices and
integrated circuits. [19,22,23] However, the major problem of using CVD grown
nanotube networks is the co-existence of metallic and semiconductive nanotubes, with
approximate 33% nanotubes being metallic. Stripe-patterning of CVD nanotube network
has been proposed to remove heterogeneous percolative transport through metallic
nanotube networks and increase the average device on/off ratio to 10
4
. Nevertheless, this
technique requires additional fabrication steps and large device dimensions.
To get a more comprehensive understanding, we compare the performance of
SN-TFTs based on separated nanotubes (5% metallic) with TFTs based on CVD grown
19

mixed nanotubes (33% metallic). Figure 2.3 summarizes the results after the
measurement of 200 nanotube TFTs with various channel lengths and channel widths.
Half of these devices are based on separated nanotubes and the other half based on mixed
nanotubes. The device yield is more than 98%, and the few un-conductive devices are
due to the peel-off of metal contact during fabrication process.
Figure 2.3a exhibits the average normalized on-current densities (I
on
/W) of the
transistors with various channel lengths measured at V
D
= 1 V and V
G
= -10 V , showing
that the on-current density is approximately reversely proportional to the channel length.
The highest on-current density is measured to be 10 μA/μm and is achieved in devices
with L = 4 μm. This value is comparable to the devices based on parallel aligned
nanotubes with a typical nanotube density of 5 tubes/μm. [29,30] Figure 2.3b shows that
the average on-current of the TFTs with various channel lengths is approximately
proportional to the channel width. The highest average on-current 1.59 mA is achieved in
devices with L = 4 μm and W = 200μm. Based on the information of Figure 2.3b, we can
further extract the best sheet resistance of the separated nanotube thin-film to be ~ 25
kΩ/sq, which is 8 times better than 200 kΩ/sq reported in the previous publication.
26

From Figure 2.3a and b, it is also clear that there is not too much difference between
solution assembly based separated nanotubes and CVD grown mixed nanotubes in terms
of current driving capability.
For TFTs fabricated with separated nanotubes and mixed nanotubes, the major
difference is expected to be the on/off ratio, and the difference is explained in Figure 2.3c.
First of all, as the channel length increases, the average on/off ratio of both SN-TFTs and
20

Mixed nanotubes TFTs increases. This can be explained by the decrease in the probability
of percolative transport through metallic nanotube networks as the device channel length
increases. On the other hand, SN-TFTs have much higher on/off ratio compared with
mixed nanotube TFTs due to the small percentage of metallic nanotubes. For the mixed
nanotube TFT, with 33% metallic nanotubes, the on/off ratio stays in the range of 2 to 10
as the channel length increases from 4 μm to 100 μm. In contrast, for SN-TFT, with only
5% metallic nanotubes, the on/off ratio improves significantly from 10 to above 10
4
as
the channel length increases from 4 μm to 100 μm. The turning point happens between 10
μm and 20 μm. When L > 20 μm, more than 90% of the devices exhibit on/off ratio
higher than 10
3
. This amount of on/off ratio is large enough for most kinds of integrated
circuit applications. Similar results have also been reported in previous work done by the
IBM research group. [26] For their work, the turning point happens between 2 μm and 4
μm. The reason that their turning point happens at smaller channel length is that they
used 99% semiconductive nanotubes. By using higher purity semiconductive enriched
nanotubes, on one hand, it can help to achieve sufficient on/off ratio with smaller channel
length, thus smaller device area; on the other hand, since higher purity requires more
ultracentrifugation which will give rise to shorter nanotube length, it can cause more
nanotube percolation and hurt the mobility of the devices as discussed below.
Besides the on current density and on/off ratio, there are two more important figures
of merit for SN-TFTs, which are device transconductance (g
m
) and mobility (μ
device
). The
normalized device transconductance (g
m
/W) and mobility of devices with various channel
21

Figure 2.3 Statistical study of 200 nanotube TFTs based on separated nanotubes and mixed nanotubes. (a) Plot of
current density (I
on
/W) versus channel length for TFTs fabricated on separated nanotubes and mixed nanotubes. (b) Plot
of average on current (I
on
) versus channel width for TFTs fabricated on separated nanotubes and mixed nanotubes, with
various channel lengths (4, 10, 20, 50, 100μm). (c) Plot of average on/off ratio (I
on
/I
off
) versus channel length for TFTs
fabricated on separated nanotubes and mixed nanotubes. (d) Plot of average transconductance per unit width (g
m
/W)
and average devicemobility (μ
device
) versus channel length for TFTs fabricated on separated nanotubes and mixed
nanotubes.
lengths are characterized and are plotted in Figure 2.3d. g
m
is extracted from the
maximum slope of the transfer characteristics measured at V
D
= 1 V , and is normalized to
device channel width. Based on the normalized transconductance, we can further extract
the mobility of the nanotube thin-film. Under V
D
= 1 V , devices operate in triode region,
so the device mobility can be calculated from the following equation:
0 20 40 60 80 100
0.01
0.1
1
10
Separated nanotubes
Mixed Nanotubes

I
on
/W ( A/ m)
Channel Length( m)
0 20 40 60 80 100
10
0
10
1
10
2
10
3
10
4
Separated Nanotubes
Mixed Nanotubes

On/Off Ratio
Chanel Length( m)
10
15
20
25
30
35
40
45
0 20 40 60 80 100
10
-3
10
-2
10
-1
10
0
Solid Line: Separated Nanotubes
Dash Line: Mixed Nanotubes
Mobility (cm
2
V
-1
s
-1
)
Channel Length ( m)
g
m
/W ( S/ m)

0 50 100 150 200
10
-6
10
-5
10
-4
10
-3
10
-2
L = 4 m
L = 10 m
L = 20 m
L = 50 m
L = 100 m

On Current (A)
Channel Width( m)
Solid Line: Separated Nanotubes
Dash Line: Mixed Nanotubes
b a
c d
22

dm
device
D ox g D ox
dI g LL
V C W dV V C W
     , where L is the device channel length, V
D
= 1 V , and
C
ox
is the gate capacitance per unity area and is calculated from parallel plate model since
the nanotubes form uniform thin-film. From the figure, one can find that as channel
length increases, g
m
/W decreases, this is because g
m
/W is also inversely proportional to
channel length.

For the device mobility, one interesting finding is that for the SN-TFTs, the device
mobility decreases as channel length increases, while for the mixed nanotube TFTs, the
device mobility increases as channel length increases. The highest mobility of SN-TFTs
is 26 cm
2
V
-1
s
-1
which is achieved by device with L = 4 μm, while the highest mobility of
mixed nanotube TFTs is 43 cm
2
V
-1
s
-1
which is achieved by device with L = 100 μm. The
reason for the difference is believed to be related to nanotube length. For the separated
nanotubes, the average length is small and is measured to be 1.7μm, so the device
mobility is limited by the percolative transport through nanotube network. As the device
channel length increases from a value comparable to the nanotube length to a much larger
value, there are significantly more tube-to-tube junctions introduced into the conduction
path, causing the device mobility to decrease. In contrast, for the mixed nanotubes, the
average length is much larger (>20 μm), so the device mobility is likely to be limited by
the metal/nanotube contacts, similar to the case for aligned nanotube transistors. [29-31]
As the channel length increases, the effect of metal/nanotube contacts becomes less
significant and the mobility increases. Our SN-TFTs exhibit mobility up to 26 cm
2
V
-1
s
-1
.

23

Our improvement in the device performance can be attributed to both higher nanotube
density and longer nanotube length as described before.
In order to further assess the effect of the carbon nanotube percolation network on
the performance of nanotube TFTs, a numerical simulation of nanotube TFTs with
various channel lengths was performed to extract their on/off ratios. [32,33] The
simulation consists of the following steps. First, we generate random nanotube networks
that are defined by the following parameters: density of nanotubes, nanotube length,
percentage of metallic nanotubes, channel length and width. The representative networks

Figure 2.4 Simulation of nanotube thin-film percolation network. (a) Randomly generated nanotube percolation
networks of separated nanotubes (top) and mixed nanotubes (bottom) for devices with L = 10 μm and W = 20μm. The
red and blue lines represent metallic and semiconductive nanotubes, respectively (b) comparison between the
simulation data derived from the percolation network and measurement data.
for semiconductive and metallic nanotubes are shown in Figure 2.4a. Then we calculate
the resistance of a nanotube network in the on- and off-states, where we assume that the
resistance per unit length of a semiconducting nanotube in the on-state to be equal to the
0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
0 20 40 60 80 100
10
0
10
1
10
2
10
3
10
4
10
5
Separated Nanotubes
CVD Mixed Nanotubes
Simulation Results
Measurement

On/Off Ratio
Chanel Length( m)
Measurement
0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
b a
24

resistance per unit length of a metallic nanotube, and 10
4
times larger in the off-state. We
also assume fixed contact resistances between metallic/metallic, metallic/semiconductive,
semiconductive/semiconductive nanotubes, and nanotubes/metal contacts. Based on the
resistance in the on- and off-states calculated from the randomly generated carbon
nanotube network, one can derive the on/off ratios of the devices. The simulation results
are compared with the measurement results and are plotted in Figure 2.4b. Based on the
figure, the simulation results fit the measurement results well, which indicate that the
nanotube percolation indeed plays a critical role in determining the on/off ratios of
nanotube TFTs.
2.5 Effect of semiconducting nanotube purity on transistor performance
Beside the comparison between separated and CVD-grown nanotubes, we have also
characterized the separated nanotubes with different purities of semiconducting
nanotubes and compared them with the unsorted nanotubes with approximately 33%
metallic nanotubes. Figure 2.5a is a photograph showing the unsorted arc-discharge P3
(Carbon solutions, Inc.) as well as 95% and 98% semiconducting single-walled carbon
nanotube solution used in this study. The separated 95% and 98% semiconducting
nanotubes (IsoNanotubes-S ™) were obtained from NanoIntegris, Inc. These samples
were enriched by density gradient ultracentrifugation, where the chemical discrimination
of surfactant molecules to adsorb on metallic or semiconducting nanotubes results in a
density difference between metallic and semiconducting nanotubes. By repeating the
same separation process, the purity of semiconducting nanotubes can be continuously
improved. Figure 2.5b shows the UV-Vis-NIR absorption spectra of the as-prepared P3
25

Figure 2.5 Comparison of carbon nanotubes separated by density gradient ultracentrifugation with different purities of
semiconducting nanotubes (a) Photograph of P3 (unsorted), 95% semiconducting and 98% semiconducting
single-walled carbon nanotube solution. (b) UV-Vis-NIR absorption spectra of the as-prepared P3 arc-discharge
nanotubes (blue trace), 95% semiconducting separated nanotubes (red trace) and 98% semiconducting separated
nanotubes (green trace). (c) FE-SEM images of 95% semiconducting separated nanotubes deposited on Si/SiO2
substrates with APTES functionalization. The average density is 41 tubes/µ m2. (d) Length distribution of the 95%
semiconducting separated nanotubes, the average nanotube length is 0.97 µ m. (e) FE-SEM images of 98%
semiconducting separated nanotubes deposited on Si/SiO2 substrates with APTES functionalization. The average
density is 46 tubes/µ m2. (f) Length distribution of the 98% semiconducting separated nanotubes, the average nanotube
length is 0.81 µ m.
a
0.0 0.5 1.0 1.5 2.0 2.5
0
1
2
3
4
5
6
7

Number of Tubes
Nanotube Length ( m)
0.0 0.5 1.0 1.5 2.0 2.5
0
1
2
3
4
5
6
7
8
9

Number of Tubes
Nanotube Length ( m)
500 600 700 800 900 1000 1100
0.4
0.6
0.8
1.0
1.2
1.4

P3 (Unsorted) SWNTs
95% Semiconducting SWNTs
98% Semiconducting SWNTs
S
22
S
33
Absorbance (norm.)
Wavelength (nm)
M
11
b
c
f e
d
95%
Semiconducting
98%
Semiconducting
95%
Semiconductin
g
98%
Semiconducti
ng
26

arc-discharge nanotubes (blue trace), 95% semiconducting separated nanotubes (red trace)
and 98% semiconducting separated nanotubes (green trace). Comparing those three traces,
one can clearly see the enrichment of semiconducting nanotubes in the separated
nanotube sample indicated by the decrease in M
11
peak and increase in S
22
, S
33
peaks.
Field-emission scanning electron microscope (FE-SEM) is used to inspect the
samples after nanotube assembly and the SEM images of the 95% and 98%
semiconducting nanotubes deposited on Si/SiO
2
substrates are shown in Figure 2.5c and e,
respectively. From the image, one can find that the samples with APTES
functionalization give high-density uniform nanotube deposition throughout the sample.
The average nanotube density for the 95% semiconducting nanotubes is measured to be
41 tubes/μm
2
and the average nanotube density for the 98% semiconducting nanotubes is
measured to be 46 tubes/μm
2
. The length distribution of the 95% and 98%
semiconducting nanotubes are also characterized based on the SEM images and the
corresponding histograms are plotted in Figure 2.5d and 1f, respectively. The length of
the 95% semiconducting nanotubes is measured to be 0.97 0.63 m   , and the length of
the 98% semiconducting nanotubes is measured to be 0.81 0.41 m   .
We use the back-gated SN-TFTs to directly compare the electrical performance of the
95% and 98% semiconducting nanotube thin-films. The nanotube deposition and device
fabrication for both nanotube samples are carried out at the same time so that any
variation in the sample preparation and device fabrication process can be minimized.
Such SN-TFTs are made with channel width (W) of 10, 20, 50, 100, and 200 μm, and
channel length (L) of 4, 10, 20, 50, and 100 μm. A microscope image of the fabricated
27

SN-TFT array is shown in Figure 2.6a and the SEM image of the channel of a typical
SN-TFT with 10 m channel length is shown in Figure 2.6b.
We have carried out systematic study of the electrical performance of the SN-TFTs
as basic components for macroelectronic integrated circuits. Figure 2.6c and 2d are the
transfer characteristics (I
D
-V
G
) of the SN-TFTs using 95% (Figure 2.6c) and 98% (Figure
2.6d) semiconducting nanotubes with various channel lengths (4, 10, 20, 50, and 100 μm)
and 100 μm channel width plotted in logarithm scale. All the curves are measured at V
D
=
1V . From the figures, we can have the following straightforward observations. (1)
Devices from both nanotube samples show p-type field-effect behavior and much higher
on/off ratio compared with the devices fabricated using unsorted nanotubes, which
typically exhibit on/off ratio of around 2~3. (2) As the device channel length increases,
the on/off ratio increases while the on-current decreases. Especially for the SN-TFTs with
95% semiconducting nanotubes, the on/off ratio improves significantly from around 10 to
over 10
4
as the channel length increases from 4 μm to 100 μm. (3) The devices using 98%
semiconducting nanotubes exhibit better on/off ratios but lower on-current than the
devices using 95% semiconducting nanotubes.
Figure 2.6e and g exhibit the transfer characteristics (red: linear scale, green: log
scale) and g
m
-V
G
characteristics (blue) of two typical SN-TFTs using 95% and 98%
semiconducting nanotubes measured at V
D
= 1V . For the 95% semiconducting nanotube
SN-TFT (Figure 2.6e), the channel length and width of the device are L = 50 μm and W =
100 μm, respectively. The on-current (I
on
) at V
D
= 1V , V
G
= -10V is measured to be 35.6
μA, corresponding to an on-current density (I
on
/W) of 0.356 μA/μm. Transconductance
28

Figure 2.6 Electrical properties of back-gated SN-TFTs using 95% and 98% semiconducting nanotubes. (a) Optical
microscope image of the SN-TFT array fabricated on silicon substrate with 50 nm SiO
2
acting as gate dielectric. (b)
FE-SEM image showing the channel of a typical back-gated SN-TFT with 10 μm channel length. (c, d) Transfer
characteristics (I
D
-V
G
) of the SN-TFTs using 95% (c) and 98% (d) semiconducting nanotubes with various channel
lengths (4, 10, 20, 50, and 100 μm) and 100 μm channel width plotted in logarithm scale. (e) Transfer characteristics
(red: linear scale, green: log scale) and g
m
-V
G
characteristics (blue) of a typical SN-TFT (L = 50 μm, W = 100 μm)
using 95% semiconducting nanotubes. (f) Output characteristics (I
D
-V
D
) of the same device in (e). (g) Transfer
characteristics (red: linear scale, green: log scale) and g
m
-V
G
characteristics (blue) of a typical SN-TFT (L = 100 μm, W
= 50 μm) using 98% semiconducting nanotubes. (h) Output characteristics of the same device in (g).
29

(g
m
) extracted from the maximum slope of the transfer characteristics is 4.6 μS and the
on/off ratio is 482. For the 98% semiconducting nanotube SN-TFT (Figure 2.6g), the
channel length is 100 μm and channel width is 50 μm. The on-current density is 0.058
μA/μm, transconductance is 0.53 μS and on/off ratio is 3x10
5
. The corresponding output
characteristics (I
D
-V
D
) of these two SN-TFTs are plotted in Figure 2.6f and h, respectively.
The output characteristics appear to be very linear under small V
D
biases, indicating that
ohmic contacts are formed between the metal electrodes and the nanotubes. Under more
negative V
D
biases, the devices exhibit saturation behaviour, indicating nice field-effect
operation.
Based on the transconductance, we can further extract the device mobility of the
SN-TFTs. Under V
D
= 1 V , devices operate in triode region, so the device mobility can be
calculated from the following equation,
dm
device
D ox g D ox
dI g LL
V C W dV V C W
     (1)
where L and W are the device channel length and width, V
D
= 1 V , and C
ox
is the gate
capacitance per unit area. The capacitance is calculated by considering the electrostatic
coupling between nanotubes using the following equation, [31,34]

1
11 00
0
0
sinh(2 / ) 1
ln
2
ox
ox Q
ox
t
CC
R

   


  
  




(2)
where 1/Λ
0
stands for the density of nanotubes and is measured to be around 10
tubes/μm, C
Q
= 4.0 x 10
-10
F/m is the quantum capacitance of nanotubes and the value is
taken from a previous report, [35] t
ox
= 50 nm is the thickness of the dielectric layer, R =
30

1.2 nm is the radius of nanotubes, and ε
0
ε
ox
= 3.9 x 8.85 x 10
-14
F/cm is the dielectric
constant at the interface where the nanotubes are placed. Based on Equation 2, one can
find that C
ox
= 3.46 x 10
-8
F/cm
2
. Using this C
ox
value, and based on the device geometry
and normalized transconductance g
m
/W, the device mobility is calculated to be 67
cm
2
V
-1
s
-1
for the 95% semiconducting nanotube SN-TFT, and 31 cm
2
V
-1
s
-1
for the 98%
semiconducting nanotube SN-TFT.
To get a more comprehensive understanding, we compare the key device
performance metrics such as on-current density, on/off ratio, transconductance and
mobility for SN-TFTs based on separated nanotubes with different purities of
semiconducting nanotubes. Figure 2.7 summarizes the results after the measurement of
175 SN-TFTs with various channel lengths, channel widths and different semiconducting
nanotube purities. Out of the devices measured, 100 of them are fabricated on 95%
semiconducting nanotubes, and 75 of them are fabricated on 98% semiconducting
nanotubes.
Figure 2.7a exhibits the normalized on-current densities (I
on
/W) of the transistors
with various channel lengths measured at V
D
= 1 V and V
G
= -10 V , showing that the
on-current density is approximately inversely proportional to the channel length for both
95% and 98% semiconducting nanotubes. The highest on-current density from SN-TFTs
using 95% semiconducting nanotubes is measured to be 5.2 μA/μm and the highest
on-current density from SN-TFTs using 98% semiconducting nanotubes is measured to
be 1.0 μA/μm. Both values are achieved in devices with L = 4 μm. Comparing the data
for transistors using 95% and 98% semiconducting nanotubes, one can easily find that the
31

Figure 2.7 Statistical study of 175 SN-TFTs using separated nanotubes with 95% and 98% semiconducting nanotubes,
as well as comparison of key device performance metrics. Plot of (a) current density (Ion/W), (b) average on/off ratio
(Ion/Ioff), (c) normalized transconductance (gm/W) and (d) device mobility (μdevice) versus channel length for TFTs
fabricated on separated nanotubes with 95% (black trace) and 98% (red trace) semiconducting nanotubes.
average on-current density of 95% semiconducting nanotubes is higher than the
on-current density of 98% semiconducting nanotubes by a factor of 3~7 at all device
channel lengths measured. The difference in the on-current density can be attributed to
the difference in nanotube lengths. For instance, the average length for the 95%
semiconducting nanotubes is approximately 0.97 μm, while the average length for the 98%
semiconducting nanotubes is about 0.81 μm. For transistors of similar channel length,
0 20 40 60 80 100
0.1
1
95% Semiconducting SWNTs
98% Semiconducting SWNTs

I
on
/W ( A/ m)
Channel Length ( m)
0 20 40 60 80 100
10
1
10
2
10
3
10
4
10
5
95% Semiconducting SWNTs
98% Semiconducting SWNTs

On/Off Ratio
Chanel Length ( m)
0 20 40 60 80 100
20
30
40
50
60
70
95% Semiconducting SWNTs
98% Semiconducting SWNTs

Mobility (cm
2
V
-1
s
-1
)
Channel Length ( m)
0 20 40 60 80 100
10
-2
10
-1
10
0
95% Semiconducting SWNTs
98% Semiconducting SWNTs

g
m
/W ( S/ m)
Channel Length ( m)
d
b a
c
32

using longer nanotubes would lead to less nanotube-nanotube junctions, and
consequently better performance. Besides, for devices using both 95% and 98%
semiconducting nanotubes, the measurement results exhibit very small error bar,
indicating the highly uniform nature of the SN-TFTs.
For SN-TFTs fabricated using separated nanotubes with different purities of
semiconducting nanotubes, besides the difference in on-current density discussed
previously, the other major difference is expected to be the on/off ratio and the difference
is explained in Figure 2.7b. First of all, as the channel length increases, the average on/off
ratio of SN-TFTs using both 95% and 98% semiconducting nanotubes increases. This can
be explained by the decrease in the probability of percolative transport through metallic
nanotube networks as the device channel length increases. On the other hand, SN-TFTs
with 98% semiconducting nanotubes have much higher on/off ratio compared with
SN-TFTs with 95% semiconducting nanotubes, especially at small channel lengths,
which can be naturally attributed to the small percentage of metallic nanotubes. For
SN-TFTs with 95% semiconducting nanotubes, the on/off ratio improves significantly
from around 10 to above 10
4
as the channel length increases from 4 μm to 100 μm. In
contrast, For the SN-TFTs 98% semiconducting nanotubes, the device on/off ratio stays
above 10
4
at all channel lengths.
Interestingly, the data shown in Figure 2.7a and b reveal a trade-off between
drive-current and on/off ratio. By using separated nanotubes with higher purity of
semiconducting nanotubes, on one hand, it can help to achieve sufficient on/off ratio with
smaller channel length, thus smaller device area; on the other hand, since higher purity
33

requires more ultracentrifugation which will give rise to shorter nanotube length, it can
cause more nanotube percolation and hurt the overall devices performance such as
on-current density discussed previously and mobility as will be discussed below.
Besides the on-current density and on/off ratio, there are two more important figures
of merit for SN-TFTs, which are device transconductance (g
m
) and mobility (μ
device
). The
normalized transconductance (g
m
/W) of devices with various channel lengths are
characterized and are plotted in Figure 2.7c. g
m
is extracted from the maximum slope of
the transfer characteristics measured at V
D
= 1 V , and is normalized to device channel
width. From the figure, one can find that as channel length increases, gm/W decreases,
this is because gm/W is also inversely proportional to channel length. Moreover, similar
to Ion/W, the SN-TFTs using 95% semiconducting nanotubes also exhibit better
performance in terms of gm/W compared with SN-TFTs using 98% semiconducting
nanotubes.
Using the data for the normalized transconductance plotted in Figure 2.7c and
Equation 1, we can calculate the devices mobility of the SN-TFTs and the data is plotted
in Figure 2.7d. Interestingly, the device mobility of the SN-TFTs with 95% and 98%
semiconducting nanotubes follows different trend. For the SN-TFTs with 95%
semiconducting nanotubes, the device mobility decreases as channel length increases,
while for the SN-TFTs with 98% semiconducting nanotubes, the device mobility
increases as channel length increases. The reason for the decreasing trend of the SN-TFTs
using 95% semiconducting nanotubes is attributed to the percolative transport through the
nanotube network. As the device channel length increases from a value comparable to the
34

nanotube length to a much larger value, there are significantly more tube-to-tube
junctions introduced into the conduction path, causing the device mobility to decrease.
32

On the other hand, it is not yet clear why the SN-TFTs using 98% semiconducting
nanotubes show increasing trend in the device mobility as the channel length increases
and this is currently under further investigation in our group. Another important point is
that devices using 95% semiconducting nanotubes exhibit higher mobilities than devices
using 98% semiconducting nanotubes. Besides the difference in the purity of
semiconducting nanotubes, other factors such as nanotube length, density of nanotube
network etc. also play a role in determining the ultimate electrical performance of the
SN-TFTs, resulting in the difference between the 95% and 98% semiconducting
nanotubes in terms of device mobility, as well as on-current density, transconductance
and on/off ratio discussed before. The reason is that the difference in nanotube length and
density can affect the nanotube percolation network, changing the amount of tube-to-tube
junctions, and the probability of metallic conduction path formation between the source
and drain electrodes.
2.6 Display electronics using separated nanotube thin-film transistors
Our ability to fabricate high performance, uniform, high on/off ratio SN-TFTs enable
us to further explore their applications in display electronics. For the proof of concept
purpose, an OLED was connected to and controlled by a typical SN-TFT device whose
transfer characteristics are shown in Figure 2.8a. More detailed and advanced
demonstration of SN-TFTs for display electronics will be illustrated in Chapter 3. The
device channel length is selected to be 20 μm so that the on/off reaches 10
4
and can meet
35

Figure 2.8 OLED control circuit by SN-TFT. (a) Transfer (I
D
-V
G
) characteristics under different drain voltages for the
device used to control the OLED (L = 20 m, and W = 100 μm), Inset: optical microscope image of the device. (b)
Characteristics of the OLED control circuit where the current flow through the OLED (I
OLED
) is measured by sweeping
the V
DD
and Input voltage V
G
. Various curves correspond to various values of V
G
from -10 V to 10 V in 2 V steps. (c)
Two terminal measurement of the OLED showing the current through the OLED (I
OLED
) (red line) and OLED light
intensity (green line) versus the voltage applied across the OLED (V
OLED
). (d) Plot of the current through the OLED
(I
OLED
) (red line) and OLED light intensity (green line) versus V
G
with V
DD
= 5 V . Inset: The circuit diagram of an
OLED driven by a SN-TFT. (e) Photographs of the OLED driven by SN-TFT under different inputs showing the turn
on and turn off of the OLED.
V
G
V
DD
= 5V
10
-12
10
-10
10
-8
10
-6
-10 -5 0 5 10
0
1
2
3
4
5
6
7
V
G
(V)
I
DD
(I
OLED
) ( A)

Light intensity (W/cm
2
)
V
G
V
DD
-10 -5 0 5 10
0
5
10
15
20
VD=1.0V
VD=0.8V
VD=0.6V
VD=0.4V
VD=0.2V

Drain Current ( A)
Gate Voltage (V)
10
-13
10
-11
10
-9
10
-7
10
-5
10
-3
0 2 4 6 8 10 12
0
2
4
6
8
10
12
V
OLED
(V)
I
OLED
(mA)

Light intensity (W/cm
2
)
a b
d c
e
-10 -8 -6 -4 -2 0
-80
-70
-60
-50
-40
-30
-20
-10
0
VG is from -10 V to
10 V in 2 V steps

I
DD
(I
OLED
) ( A)
V
DD
(V)
36

the requirement for controlling the OLED to switch on and off. The schematic of the
OLED control circuit is shown in the inset of Figure 2.8b, where one SN-TFT is
connected to an external OLED, and V
DD
(< 0 V) is applied to the cathode of the OLED.
The OLED control circuit is characterized by sweeping the V
DD
and Input voltage V
G
and
measure the current flow through the OLED (I
OLED
). It shows field effect transistor like
behavior, with various curves correspond to various values of input voltage. The figure
illustrates that by controlling V
DD
and V
G
that worked as the input for the circuit, we can
control the current flow through the OLED. To fully understand the behavior of the
OLED, it is further characterized and the current and output light intensity versus applied
voltage behaviours are plotted in Figure 2.8c. From the figure, we can see that the OLED
gives nice diode I-V characteristic and in terms of the light intensity, the turn on voltage
is about 3 V .

Based on the data in Figure 2.8b and c, we demonstrate the switching of the OLED
by applying V
DD
= 5 V to the source of the transistor and sweeping the input voltage V
G

from -10 V to 10 V . Figure 2.8d shows the current (red curve) flowing through the OLED,
which is successfully modulated by V
G
by a factor of 1140, and this modulation leads to
the control of the OLED light intensity as shown in the green curve. When V
G
= -10V , the
OLED is on, and based on the measured light intensity, the brightness is calculated to be
16.5 Cd/m
2
. When V
G
= 10V , the OLED is off and the brightness is calculated to be <
0.001 Cd/m
2
. The modulation in the OLED brightness is greater than 10
4
and the
significant change in the light intensity can be visually seen as shown in Figure 2.8e. The
37

optical photographs represent the OLED under various input voltages, with 1, 2, 3, 4, 5,
and 6 correspond to the inputs of -10, -8, -6, -4, -2, and 0 V , respectively.
2.7 Digital circuits using separated nanotube thin-film transistors
Our ability to fabricate high performance, uniform, high on/off ratio SN-TFTs also
enable us to further explore their applications in digital integrated circuits. We have
already discussed the trade-off between on-current and on/off ratio for different purities
of semiconducting nanotubes, and we choose to use the separated nanotubes with 98%
semiconducting nanotubes for the digital integrated circuit fabrication. The reason is that
for digital application, it is desirable to have large switching, preferably rail-to-rail, in
order to achieve large noise margin. More importantly, the off-state current has to be low
to reduce the static power consumption. Therefore, it is more important for the transistors
to have a large on/off ratio rather than high on-current. For SN-TFTs with 98%
semiconducting nanotubes, At all channel lengths measured, more than 95% of the
devices exhibit on/off ratio higher than 10
4
. This amount of on/off ratio is large enough
for most kinds of integrated circuit applications.
For the proof of concept purpose, we demonstrate the basic digital functional blocks
such as inverter, 2-input NAND and NOR using SN-TFTs. The fabrication process of
these integrated circuits is described as the following: Firstly, Ti/Au back-gate electrodes
are patterned by photolithography and lift-off process. 50 nm Al
2
O
3
high-κ dielectric and
5 nm SiO
2
are then deposited on top of the Ti/Au back-gate by atomic layer deposition
and e-beam evaporation, respectively. Vias are then patterned using photolithography and
buffered oxide etch (BOE) is used to remove the oxide layer in the vias to allow the
38

interconnection between the gate and drain of the transistor to form the diode-connected
load transistor. The separated nanotube thin-film is then deposited on the dielectric layer
using the method discussed above and the rest of the fabrication steps including the
source/drain electrodes patterning and unwanted nanotube etching is the same as the
back-gate transistor fabrication discussed previously. We start with the inverter design
and find that the highly uniform nature of the SN-TFTs allows us to optimize the circuit
performance using the conventional silicon transistor circuit design theory. As an
example, for the diode-load inverter investigated in Figure 2.9, the output impedance
looking into the source of the diode-connected SN-TFTs is 1/g
m_load
, and the voltage gain
of the inverter is given by
_
/
V m out m m load
A g R g g  . For transistors operating in the
saturation regime, the transconductance can be calculated by 2 ( / )
m p ox sd
g C W L I   ,
where μ
p
is the mobility of the devices, C
ox
is the gate capacitance per unit area, and I
sd
is
the source-drain current of the transistor. Considering that the current flowing through the
switching transistor (I
sd
) is equal to current flowing through the diode-connected
transistor (I
sd_load
), we can find the gain of the diode-load inverter to be equal to

L
L
W
W
I L W C
I L W C
g
g
A
l o a d
l o a d
l o a d sd load load ox p
sd ox p
load m
m
V
   
_
_
) / ( 2
) / ( 2


(3)
where W, L, W
load
, and L
load
, are the channel length, channel width for the switching
transistor and diode-load transistor, respectively.

39

Figure 2.9 Integrated inverter circuits using separated carbon nanotubes. (a, d) Schematic of two different diode-load
inverters using SN-TFTs with different device dimensions. (b, e) Optical microscope images of these two
corresponding inverters. (c,f) Inverter voltage transfer characteristic (red trace) and voltage gain (blue trace) of these
two corresponding inverters. Both inverters work with a V
DD
of 3V and exhibit symmetric input/output behaviour. (g)
Inverter voltage transfer characteristics measured at different supply voltages (V
DD
). (h) Curve showing the dependence
between the inverter voltage gain and supply voltage. Inset: schematic of the circuit with parasitic resistance at the
output node.

40

The schematics of two diode-load inverters with different geometries used in this
study are shown in Figure 2.9a, d. By design, inverter 1 has W = 100μm, L = 50μm, W
load

= 100μm, L
load
= 150μm; while inverter 2 has W = 100μm, L = 40μm, W
load
= 50μm, L
load

= 150μm. The corresponding optical microscope images of these two inverters are shown
in Figure 2.9b and e, respectively. In the circuit, one transistor is acting as the switching
transistor and is connected between the supply voltage V
DD
and the output, and the other
transistor is configured as a diode-load and is connected between the output and ground.
The inverters are characterized by sweeping input voltage V
IN
and measure the output
voltage V
OUT
. The corresponding inverter voltage transfer characteristics are plotted in
Figure 2.9 c and f, respectively. For the measurement, V
DD
is biased at 3V and V
IN
is
swept between 0V and 3V . Measurements reveal that for both inverters, as input voltages
increases from 0V to 3V , output voltages decrease from 3V to 0V , meaning that they are
functioning correctly as logic inverters. The maximum voltage gain measured is 1.45 for
inverter 1 and 2.78 for inverter 2. According to the conventional diode-load inverter
circuit design equation discussed before (Equation 3) and the device dimensions, we have
1
3 1.73
V
A  for inverter 1 and
2
7.5 2.74
V
A for inverter 2. This means that our
measurement results are consistent with the conventional circuit design theory, and by
simply changing the dimension of the switching and load transistors in the layout design,
we can achieve inverters with different voltage gains.
Another very important merit for the inverters using SN-TFTs is that they offer
symmetric input/output behavior, meaning that both input and output are operating under
the same voltage range (0~3V in this case). This character is important for single power
41

supply voltage operation, and is crucial for cascading logic blocks for larger scale
integration where the output of the preceding logic block needs to be able to drive the
ensuing logic block directly.
The relationship between the gain of the inverters and the power supply voltage is
also studied and the voltage transfer characteristics for an inverter measured under
different V
DD
are shown in Figure 2.9g. From the figure, we find that the inverter keeps
showing symmetric input/output behavior under all supply voltages. Besides, if we plot
the voltage gain versus V
DD
(Figure 2.9h), we see monotonic increase in maximum
voltage gain as the V
DD
increases. It is worth noting that for the diode-load inverters, the
voltage gain is ideally independent of V
DD
as shown in Equation 3. The reason we see the
increasing trend is due to the finite input impedance of the measurement instrument (HP
4156B in this case). Since the input impedance of the measurement instrument (R
P
) is
not infinitely large compared with the output impedance of the SN-TFT used in the
inverters, the instrument draws some amount of current (I
Rp
). As V
DD
increases, the
output DC level at the maximum voltage gain increases, causing I
Rp
to increase. From
Kirchhoff current law, we have I
sd
= I
sd_load
+ I
Rp
, so as V
DD
increases, I
sd_load
is getting
smaller and smaller compared with I
sd
. Furthermore, based on Equation 3, the inverter
voltage gain is proportional to
_
/
sd sd load
II , this explains why the voltage gain increases
as the power supply voltage increases.
42

Figure 2.10 Integrated 2-input NAND and NOR circuits using separated carbon nanotubes. (a, d) Schematic of
diode-load 2-input NAND and NOR circuits using SN-TFTs. (b, e) Optical microscope images of the corresponding
NAND and NOR circuits. (c, f) Output characteristics of the corresponding NAND and NOR circuits. The supply
voltages for both circuits are V
DD
= 2V. Input voltages of 3V and 0V are treated as logic “1” and “0”, respectively.
In addition to inverters, more sophisticated circuits such as 2-input NAND and NOR
have also been demonstrated. Figure 2.10 shows the schematics (Figure 2.10a, d), optical
microscope images (Figure 2.10b, e) and output characteristics (Figure 2.10c, f) of the
NAND and NOR, respectively. Both logic blocks employ a diode-connected SN-TFT in
the pull-down network similar to the inverters and they are both operated with a V
DD
of
2V . 3V and 0V applied on gate A and B are treated as logic “1” and “0”, respectively. For
the NAND, the output is “1” when either one of the two inputs is “0” (Figure 2.10c),
while for the NOR, the output is “0” when either one of the two inputs is “1” (Figure
2.10f). These output characteristics confirm that our circuits are realizing the logic
0.0
0.3
0.6
0.9
1.2
1.5
Gate B: "0" "1" "0" "1"
Gate A: "0" "0" "1" "1"

Output Voltage(V)
a
b
c
d
e
f
0.0
0.3
0.6
0.9
1.2
1.5
Gate B: "0" "1" "0" "1"

Output Voltage(V)
Gate A: "0" "0" "1" "1"
NAND
NOR
43

function correctly. Combining these basic logic blocks, more sophisticated logic circuits
which requires cascading multiple stages of logic gates can be readily constructed and the
work is currently ongoing in our group.
2.8 Summary
In summary, we have reported significant progress on wafer-scale processing of
SN-TFT for display and digital circuit applications, including progress on wafer-scale
assembly of high density, uniform separated nanotube networks; high-yield fabrication of
devices with good performance, and proof of concept demonstration of OLED switching
controlled by a SN-TFT and basic logic gates such as inverter, NAND and NOR gates.
The APTES assisted solution based assembly of separated nanotube thin-film has been
achieved on complete 3-inch Si/SiO
2
wafers, followed by the fabrication to yield
transistors with high yield (> 98%), small sheet resistance (~ 25 kΩ/sq), high current
density (~ 10 A/ m), high mobility (~ 26 cm
2
V
-1
s
-1
) and good on/off ratio (> 10
4
). In
addition, OLED control circuit has been demonstrated with the SN-TFT, and the
modulation in the output light intensity exceeds 10
4
. This demonstration can provide
guide to future research on SN-TFT based display electronics such as active matrix
organic light-emitting diode (AMOLED). Our work represents significant advance
toward the challenging task of large scale separated nanotube thin-film assembly and
solves the problem of co-existence of both metallic and semiconductive nanotubes in the
state-of-the-art nanotube transistor fabrication techniques.

44

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869-872.

47

Chapter 3: Separated Carbon Nanotube Macroelectronics for
Active Matrix Organic Light-Emitting Diode Displays

3.1 Introduction
Due to their high light efficiency, superior color purity, low power consumption,
large view angle, excellent flexibility, and low temperature processing, [1-5]

organic
light-emitting diodes (OLEDs) are one of the promising candidates for the next
generation display technologies.

However, the fabrication of thin-film transistors (TFTs)
in the active matrix (AM) backplane is still challenging. Unlike the requirement of
driving transistors for the traditional liquid crystal displays (LCDs), where amorphous
silicon (a-Si) (mobility ~1 cm
2
V
−1
s
−1
) [6,7] is applied as the transistor channel material,
higher current driving capability is needed. Although polycrystalline silicon (poly-Si),
[8,9] which has better mobility (~ 150 cm
2
V
−1
s
−1
), is used as a temporary solution for
AMOLED display transistors, its high cost, low transparency, and more importantly,
high-temperature processing, short life time, and poor uniformity limits the commercial
implementation of AMOLED displays. Other candidates such as organic semiconductor
materials are also attractive, but similar to a-Si, they also suffer from low carrier
mobilities. [10-12]
Compared with the above channel materials, one-dimensional nanoscale materials
such as semiconductor nanowires (NWs) [13-16] and single-walled carbon nanotubes
(SWNTs) [17-22] have the advantages in terms of mobility, transparency, flexibility, and
low temperature processing. AMOLED displays using NWs as the active channel
48

materials have already been demonstrated by our group and our collaborators before.
[23,24] However, the device uniformity, reliability, and processing scalability still need to
be further improved. Recently, we and several other groups have demonstrated
high-performance TFTs [25-28] using pre-separated semiconducting nanotubes produced
by density-gradient ultracentrifuge separation method developed by Hersam and his
coworkers [29,30]. In those previous reports, transistors exhibit highly uniform electrical
performance. Besides, due to the use of high purity semiconducting nanotubes, high
on/off ratio (>10
5
) as well as excellent on-current density (~ 1 µ A/µ m) has been achieved,
which makes such separated carbon nanotube TFTs (SN-TFTs) very attractive for
AMOLED display applications.
In this chapter, we report the first monolithically integrated AMOLED display with
SN-TFT based control circuit. We have investigated the relationship between the carbon
nanotube film density and the transistor electrical performance, and found the optimized
density for AMOLED applications. Devices with excellent performance are achieved. In
addition, the single pixel control circuits consisting of two SN-TFTs and one capacitor
are made and their OLED control capability is well examined. Finally, we have fabricated
and tested AMOLED display elements with 20 × 25 pixels driven by 1000 SN-TFTs.
Compared with conventional platforms, our SN-TFT platform shows significant
advantages such as low temperature processing compatibility, scalability, reproducibility
and device performance, and suggests a practical and realistic approach for carbon
nanotube based AMOLED display applications.

49

3.2 Structure of AMOLED circuit and layout
Figure 3.1a illustrates the schematic diagram of the AMOLED circuit with the red
box showing the circuit structure within one pixel. Each pixel contains one switching
transistor (T
s
), one driving transistor (T
d
), one charge storage capacitor (C
s
), and one
OLED. [5] The switching transistor, controlled by the signal from the scan line, is
employed to select one specific row of pixels in an AMOLED display element by passing
the signal from data line through the channel of the switching transistor to the gate of the
driving transistor. The driving transistor further controls the output light intensity of the
OLED pixel by modulating the current flowing through OLED. For the line-by-line
scanning technique presented in the display technology nowadays, the capacitor C
s
is
used to store and stabilize the voltage obtained from the data line during one scanning
period, which is crucial for dynamic displays. Based on the circuit diagram, the
corresponding layout of one pixel is shown in Figure 3.1b (top view) and c
(cross-sectional view). The single pixel layout has an total area of 500 × 500 μm
2
with
OLED area of 200 × 200 μm
2
, and is designed to be fabricated on glass substrate with
patterned Ti/Au (5 Å/40 nm) gate electrode, Al
2
O
3
(40 nm) gate dielectric, separated
nanotube thin-film for the active channel, Ti/Pd (5 Å/50 nm) source and drain contacts,
integrated green OLED, and a 200 nm SiO
2
passivation layer. The total fabrication
consists of 7 photo masks and 15 fabrication steps.
50

Figure 3.1 Structure of AMOLED circuit and layout. (a) Schematic diagram for the circuit of AMOLED. Each pixel
contains one switching transistor, one driving transistor, one charge storage capacitor, and an OLED. (b) Top view for
the layout of a single pixel AMOLED with an area of 500 × 500 μm2. (c) Cross-sectional view for the structure of the
AMOLED pixel consisting of a glass substrate, patterned Ti/Au gate electrode, Al2O3 gate dielectric, separated CNT
thin film for the active channel, Ti/Pd source and drain contacts, integrated OLED (ITO/NPD/Alq3/LiF/Al), and a SiO2
passivation layer.
3.3 Carbon nanotube density and device geometry optimization
In order to control the OLED intensity, the transistors in the control circuits need to
have high current on/off ratio and excellent current drive capability. Shorter channel
51

length and higher nanotube channel network density would lead to high on-current
density, which is needed for OLED display applications. However, it will also create
more metallic nanotube pass in the channel, which will negatively affect the transistor
current on/off ratio. Therefore, for the OLED control purpose, optimized device geometry
and channel nanotube network density is very important.
98% semiconducting carbon nanotube solution (from Nanointegris, Inc. Batch No.
S08-665) was used as suggested by previous work from our group, [26] to produce a
uniform, separated nanotube thin-film on aminopropyltriethoxy silane (APTES) Si/SiO
2

surface by solution-based deposition technique. [27,31] After treating the silicon safer
with a APTES solution and washing, the wafer is soaked in the pre-separated solution of
semiconducting nanotubes for 30 minutes to give a thin film of carbon nanotubes on the
silicon surface. The nanotube network density can be controlled by tuning the
concentration of APTES in isopropanol alcohol (IPA) solution used for SiO
2
surface
treatment, before nanotube deposition. Three different conditions are studied
(APTES:IPA = 1:1, 1:10, 1:100) and the field-emission scanning electron microscopy
(FE-SEM) images of the resulting nanotube thin-film are exhibited in Figure 3.2a-c.
From the images, one can find that the nanotube density varies significantly when
different volume ratios of APTES and IPA are used. From Figure 3.2d, one can see that
the sample with APTES:IPA ratio of 1:1 has low nanotube network density (4 tubes/μm
2
)
and the uniformity of the thin-film is poor. For the sample with APTES:IPA ratio of 1:10,
a highly uniform film is obtained with a density of 45 tubes/μm
2
. Nevertheless, if the
solution is further diluted to APTES:IPA = 1:100, the resulting film density decreases to
52

Figure 3.2 Carbon nanotube TFT performance as a function of nanotube density. (a-c) FE-SEM images of separated
CNT thin-films with different densities obtained by tuning the ratio of APTES and IPA used in the surface
functionalization process. (d) Relationship between nanotube film density and APTES : IPA ratio. (e, f) Channel length
dependence of device on/off ratio (e) and normalized on-current (f) for transistors fabricated on nanotube films using
different APTES : IPA ratios. (blue trace for APTES : IPA = 1 :100, red trace for APTES : IPA = 1 :10, and green trace
for APTES : IPA = 1 :1).
36 tubes/μm
2
. When APTES is not applied to the silicon wafer, nanotubes show very low
levels of coverage (< 0.5 tubes/ μm
2
) under the same conditions. [27] The relationship
between nanotube film density and APTES:IPA ratio can be explained as follows: the
APTES coats the SiO
2
surface, forming an amine-terminated monolayer, which capture
the nanotubes in solution, binding them to the substrate to form a uniform thin-film.
When the APTES concentration is very high, instead of a uniform monolayer, multiple
layers of APTES molecules are stacked onto the SiO
2
surface, leading to an uneven
amine surface and thus a low-density nanotube film. As the APTES concentration in IPA
is diluted, a uniform monolayer APTES molecule is formed, which results in a highly
uniform nanotube film with excellent density. However, when the APTES solution is
53

diluted even further, the APTES monolayer may have defects and vacancies, so the amine
surface and nanotube film density will decrease again. Atomic force microscope (AFM)
images of the SiO
2
surface functionalized with different concentration of APTES solution
can be found in Figure 3.3. Overall, by tuning the concentration of APTES in IPA
solution, separated nanotube thin-film with different densities can be achieved.

Figure 3.3 AFM image of SiO
2
surface coated with APTES solution with different concentration. (a) Blank SiO
2

surface. (b-d) SiO
2
surface functionalized with solution of APTES and IPA volume ratio of 1:1, 1:10 and 1:100,
respectively. From the images, one can find that the SiO
2
surface in Figure 3.3b has many impurities, while the one in
Figure 3.3d shows that APTES did not cover the whole surface.

Subsequently, electrical performance of the nanotube network with different density
is investigated. 100 transistors with different channel geometry were fabricated on each
sample with different nanotube density, and the channel length dependence of device
on/off ratio and normalized on-current are shown in Figure 3.2e and f. From these two
plots, one can find that due to the benefit of high purity semiconducting nanotube, all the
devices with channel lengths larger than 20 μm have on/off ratios higher than 10
4
, and
transistors made with nanotube film deposited using an APTES:IPA ratio of 1:10, which
gives the highest nanotube density, also offer the best current driving capability (0.5
μA/μm for 20 μm channel length devices). Based on the electrical performance,
54

APTES:IPA ratio of 1:10 and device geometry of L = 20 μm, W = 100 μm were chosen as
the optimized conditions for the transistors used in the AMOLED control circuits.
3.4 Electrical properties of transistors used in the AMOLED circuit.
Figure 3.4 shows the structure and electrical characteristics of the nanotube
transistors used in the AMOLED. For the sake of two transistors control circuit,
individual back-gated device structure was chosen as shown in Figure 3.4a. 5 Å Ti and 40
nm Au are patterned as the back gate, and 40 nm Al
2
O
3
is deposited by atomic layer
deposition (ALD) as the gate dielectric. Due to the poor adhesion between Al
2
O
3
and
APTES molecules, we have found that the deposited nanotube thin-film on Al
2
O
3
surface
peels off during the ensuing fabrication steps, which is shown in Figure 3.5. In order to
improve the adhesion, a thin layer of SiO
2
(5 nm) was deposited on top of the Al
2
O
3
layer
using electron beam evaporator to form a bilayer gate dielectric. With the help of the SiO
2

buffer layer, uniform nanotube thin film was achieved as shown in Figure 3.5d and Figure
3.4b. After the separated nanotube thin-film deposition, Ti/Pd (5 Å/50 nm) was applied
on top of the channel network to form ohmic source and drain contacts. Finally, the
nanotubes outside the channel region were etched away by photolithography and oxygen
plasma. Electrical properties of a typical transistor is plotted in Figure 3.4c, which
contains the transfer (I
D
-V
G
) characteristics (red curve for linear scale and green curve for
log scale) and g
m
-V
G
characteristics (blue) measured with V
D
= 1 V . The on-current at V
D

= 1 V and V
G
= -5 V is 82.9 µ A, corresponding to a current density of 0.829 µ A/µ m. The
55

Figure 3.4 Electrical properties of transistors used in the AMOLED circuit. (a) Schematic diagram of the back-gated
transistor built on separated nanotube thin-film with Ti/Au (5 Å/40 nm) back gate, Ti/Pd (5 Å/50 nm) contact electrodes,
and the Al
2
O
3
/SiO
2
bilayer gate dielectric (40 nm/5 nm). (b) FE-SEM image showing the channel of a back-gated
SN-TFT with 20 μm channel length. (c) Transfer (I
D
-V
G
) characteristics (red, linear scale; green, log scale) and g
m
-V
G

characteristics (blue) of a typical SN-TFT (L = 20 m, W = 100 μm) with V
D
= 1 V. (d) Output (I
D
-V
D
) characteristics of
the same device with V
G
varying from -5 V to 5 V in 1 V steps.
on/off ratio exceeds 10
4
and the peak transconductance is 25.5 µ S. Based on the
transconductance, the device mobility is extracted to be 31.65 cm
2
V
-1
s
-1
. We note that
parallel plate model is used to estimate the gate capacitance when calculating the device
mobility due to the complexity of the bilayer gate dielectric structure. If we take the
electrostatic coupling between nanotubes into consideration, the gate capacitance will be
smaller and therefore the real mobility can be larger than the value listed here. [32] In
addition, the output (I
D
-V
D
) characteristics of the same device are also measured with V
G

varying from -5 V to 5 V in 1 V steps as shown in Figure 3.4d, which indicates nice
field-effect operation and ohmic contacts.
56

Figure 3.5 (a,c) SEM images of the separated nanotube thin-films deposited on Al
2
O
3
and Al
2
O
3
/SiO
2
surface,
respectively (b,d) SEM images for the same samples after one step of photolithography. Nanotubes on the Al
2
O
3

sample would peel off while the ones on Al
2
O
3
/SiO
2
bilayer dielectric still stick to the surface.
3.5 Characteristics of the two-transistor AMOLED single-pixel circuit.
Following the single transistor analysis, the AMOLED pixel control circuits were
fabricated and studied. Figure 3.6a displays the optical microscope image of the
fabricated single pixel circuit before OLED integration, which contains two SN-TFTs,
one capacitor, and one Indium-tin oxide (ITO) electrode for further OLED integration. To
operate the driving transistor, -5 V is applied to the scan line to turn on the switching
transistor. Transfer (I
DD
-V
DA TA
) characteristics are plotted in Figure 3.6b and c in linear
scale and logarithm scale, respectively. The various curves in Figure 3.6b correspond to
various values of the supply voltage V
DD
(0.2 V to 1 V with 0.2 V steps), which was
57

connected to the source of the driving transistor as shown in the inset schematic diagram
in Figure 3.6c. From the transfer characteristics in logarithm scale, one can find that the
two-transistor-circuit exhibits excellent on/off ratio (higher than 10
6
), which is resulted
from the optimized channel geometry and film density as well as the high
semiconducting nanotube purity. This on/off ratio is crucial in order to guarantee that the
control circuits can fully turn off the OLED pixels.

Figure 3.6 Characteristics of the two-transistor single-pixel circuit. (a) Optical microscope image of the single pixel
circuit with two SN-TFTs, one capacitor, and the ITO electrode for OLED integration. (b, c) Transfer (I
D
-V
DA TA
)
characteristics of the single pixel circuit measured while V
SCAN
= -5 V in linear scale (V
DD
= 1 V to 0.2 V with 0.2 V
steps) and logarithm scale (V
DD
= 1 V), respectively. Inset: schematic diagram of the single pixel circuit (d) Output
(I
D
-V
DD
) characteristics measured at V
SCAN
= -5 V with different V
DA TA
(-5 V to 5 V with 1V steps).
Beside the on/off ratio, the current-drive of the circuit is also important for
AMOLED displays, which is examined by the output (I
DD
-V
DD
) characteristics shown in
58

Figure 3.6d. To keep V
GS
value of the driving transistor constant, source of the driving
transistor is grounded while the drain terminal (-V
DD
) is swept from 0 V to -7 V , and
different curves were obtained with V
DATA
changing from -5 V to 5 V with 1 V steps.
From this figure, one can clearly find that current flow through the driving transistor will
saturate under high V
DD
, and with the optimized semiconducting nanotube density, 50 μA
is achieved when V
DD
= 3 V , V
DATA
= -5 V , and V
SCAN
= -5 V , which offers high enough
current-density to drive OLED pixels with the designed area (200 × 200 μm
2
).
3.6 AMOLED display characteristics
To further understand the behavior of the circuit controlled AMOLED, an OLED was
connected to and controlled by a typical single pixel control circuit using wire bonding.
Standard NPD/Alq
3
OLED (2 × 2 mm
2
) with multi-layered configuration is employed in
this study given as ITO/4-4’-bis[N-(1-naphthyl)-N-phenyl-amino]bi-phenyl (NPD) [40
nm]/tris(8-hydroxyquinoline) aluminium (Alq
3
) [40 nm]/LiF [1 nm]/aluminum (Al) [100
nm] whose transfer characteristics are shown in Chapter 2 Figure 2.8. Organic and metal
films were deposited from resistively heated boats under UHV conditions, as reported
previously. [33] The schematic of the OLED control circuit is shown in the inset of
Figure 3.7a, where the drain of the driving transistor is connected to an external OLED
and a negative voltage (-V
DD
) was applied to the cathode of the OLED. The current flow
through the OLED (I
OLED
) was measured by sweeping the V
DD
while also changing input
voltage V
DATA
as plotted in Figure 3.7a. V
SCAN
is kept to be -5 V to keep the switching
transistor on and the family of curves corresponds to various values of V
DATA
from -5 to 5
V in 1 V steps. The figure illustrates that if V
DATA
is sufficiently negative enough, OLED
59

Figure 3.7 AMOLED display characteristics. (a) Characteristics of the OLED controlled by single pixel circuit, where
the current flow through the OLED (I
OLED
) is measured by sweeping the V
DD
. The family of curves correspond to
values of V
DA TA
from -5 to 5 V in 1 V steps. (b) Plot of the current through the OLED (I
OLED
) (red line) and OLED light
intensity (green line) versus V
DA TA
with V
DD
= 8 V. (c) Photographs showing that under different V
DA TA
, the
two-transistor single-pixel circuit can turn on and turn off the OLED. (d) Optical image of an AMOLED substrate
containing 7 AMOLED elements, each with 20 × 25 pixels. (e) Photograph showing the pixels on an integrated
AMOLED are turned on when V
DA TA
= -5 V, V
SCAN
= -5V, and V
DD
= 8 V are applied for the pixels.
will be turned on when the supply voltage is higher than the threshold voltage of the
OLED (about 3 V), and the current flow through OLED will increase as V
DATA
decreases.
Therefore, the light intensity of the OLED can be modulated by V
DATA
, which is directly
revealed in Figure 3.7b where current and output light intensity versus V
DATA

60

characteristics are plotted with a fixed V
DD
of 8 V as shown in the inset schematic. From
this figure, one can find that when sweeping V
DATA
from -5 V to 5 V , the current through
OLED changes from 71 µ A to 3.7 nA and the output light intensity also varies from 5.3 ×
10
-6
W/cm
2
to about 8 × 10
-12
W/cm
2
, which exceeds 5 orders of magnitude difference
and the significant change in the light intensity can be visually seen in Figure 3.7c. The
optical photographs represent the OLED under various V
DATA
voltages of -5, -3, -1, 1, 3,
and 5 V , respectively, and demonstrate that the external OLED can be fully turned on and
turned off by changing the voltage of V
DATA
.
Based on the discussion above, we went one step forward to fabricate a
monolithically integrated AMOLED display element. First, an array of AMOLED control
circuit (1 × 1.25 cm2) with 20 × 25 pixels driven by 1000 SN-TFTs was fabricated using
the same layout design as discussed previously. The pixel size was 200 × 200 μm2.
After preparing the control circuits, 200 nm SiO2 was deposited by electron beam
evaporator as a passivation layer, leaving only the pre-patterned ITO electrodes open for
OLED integration. Finally, green OLEDs with the same multilayer structure and
thickness (ITO/NPD/Alq3/LiF/Al) as used for the single pixel circuit study were
deposited by thermal evaporation onto ITO electrodes. Optical image of a completed
AMOLED substrate, which contains 7 AMOLED elements (20 × 25 pixels each) is
shown in Figure 3.7d. Figure 3.7e is a photograph showing all the pixels on one
integrated AMOLED element are turned on when VDATA = -5 V , VSCAN = -5V , and
VDD = 8 V are applied for all the pixels. In this figure, 348 out of 500 pixels are turned
on, corresponding to a yield of 70%, which is acceptable for the demonstration purpose in
61

the present laboratory-scale experiments. It is worth noting that many of the failed pixels
are due to the top SiO2 surface roughness, which leads to short circuits during OLED
evaporation, and can be improved by using a better passivation technique. To the best of
our knowledge, this is the first demonstration of AMOLED display driven solely by
SN-TFT circuits.
3.7 Summary
In summary, we have demonstrated the great potential of using SN-TFTs for high
performance display electronics. By tuning the concentration of APTES in IPA solution
during the surface functionalization step, an optimized separated nanotube thin-film
density of 45 tubes/µ m is achieved when 1:10 volume ratio between APTES and IPA is
used. Based on the optimized nanotube density and device geometry, individual
back-gated transistors with superior on/off ratio (>10
4
) and excellent current driving
capability ( ∼0.8 µ A/µ m) have been fabricated with 10 µ m channel length and 100 µ m
channel width. In addition, the electrical properties and OLED control capability of the
single pixel AMOLED control circuit are well examined and analyzed, and the
modulation in the output light intensity exceeds 10
5
. Moreover, a monolithically
integrated AMOLED display element with 500 pixels and 1000 transistors has been
further demonstrated. Our work represents significant advance in separated nanotube
based macroelectronics and might pave the way of using separated carbon nanotubes for
future display applications.
62

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65

Chapter 4: Air-Stable n-Type Separated Carbon Nanotube
Thin-Film Transistors and Its Application in CMOS Logic
Circuits

4.1 Introduction
Carbon nanotubes hold great potential as channel material for thin-film transistor
(TFT) applications [1-8]

due to their extraordinary electrical properties [9-13], such as
high intrinsic carrier mobility and current-carrying capability. Compared with other
popular TFT channel materials such as amorphous silicon, poly-silicon, [14,15] or
organic materials, [16,17] carbon nanotube based TFTs have the advantages of
room-temperature processing compatibility, transparency, flexibility, as well as high
device performance. Nevertheless, two major challenges are still faced by carbon
nanotube based TFTs, which are the co-existence of metallic and semiconducting
nanotubes and lacking of a reliable way to obtain n-type nanotube TFTs. Admixture of
metallic nanotubes will lead to low on/off current ratios and the absent of n-type TFTs
will limit the applications in large scale digital integrated circuits.
Recently, many groups including our own have demonstrated high-performance
TFTs using pre-separated semiconducting nanotubes. [18-20] However, how to obtain
air-stable n-type separated nanotube TFTs (SN-TFTs) reliably still remains to be a big
challenge. Although n-type transistors can be achieved by chemical doping [21,22] or
using metal contacts with low work functions such as Gd, Sc or Y , [23-25] the reliability
as well as long-term air-stability of those doping techniques has to be further improved.
66

Latest report shows that passivating the individual nanotube transistors using HfO
2
layer
deposited by atomic layer deposition (ALD) is an effective and air-stable method to
convert the devices into n-type. [26] Compared with other doping techniques, this method
is relatively easy, very reliable and robust, offers long-term air-stability, and is highly
compatible with the standard fabrication process adopted by semiconductor industries.
However, whether this technique can be extended to nanotube TFT devices and the
mechanism of such conversion still remains to be studied.
In this chapter, we report our recent progress in getting n-type SN-TFTs by
depositing a high-κ oxide layer onto the nanotube surface using ALD and its applications
in macroelectronic complementary metal-oxide-semiconductor (CMOS) circuits. Our
work includes the following essential components. (1) Air-stable n-type SN-TFTs are
obtained by passivating the back-gated transistors using a high-κ oxide layer. Such n-type
devices exhibit almost perfectly symmetric electrical performance compared with the
pristine p-type devices. (2) The mechanism for this carrier type conversion and the
factors affecting the conversion process including ALD temperature, metal contact
material, channel length, have been systematically studied by a series of designed
experiments. (3) A CMOS inverter with a maximum gain of 8.4, rail-to-rail output,
symmetric input/output behavior, and large noise margin is demonstrated, which satisfies
the crucial requirements for the cascading of multiple stages of logic blocks. Our CMOS
SN-TFT platform shows significant advantages over conventional platforms with respect
to stability, scalability, reproducibility and device performance, and suggests a practical
and realistic approach for nanotube based CMOS integrated circuit applications.
67

4.2 Symmetric n-type and p-type separated carbon nanotube thin-film
transistor fabrication
Figure 4.1a illustrates our n-type SN-TFT device structure. We use the solution-based
aminopropyltriethoxy silane (APTES) assisted separated nanotube deposition technique
reported in our previous publication [19,20]

to deposit high density, uniform
pre-separated nanotube thin-film onto the Si/SiO
2
substrates. The separated nanotubes
(IsoNanotubes-S ™) we used contain 98% semiconducting nanotubes and are obtained
from NanoIntegris, Inc. The heavily doped Si substrate and 50nm SiO
2
serve as the
back-gate and gate dielectric, respectively. Au is used as the source and drain contacts
due to its favourable work function (5.1 eV), which gives similar Schottky barrier for
electrons and holes, making it possible to fabricate p-type and n-type SN-TFTs with
symmetric device performance. On top of the transistor, HfO
2
passivation layer is further
deposited using ALD to convert the transistors into n-type. Figure 4.1b is a photograph
showing an array of such n-type devices after fabrication. The array consists of SN-TFTs
with channel widths (W) of 10, 20, 50, 100, and 200 μm, and channel lengths (L) of 5, 10,
20, 50, and 100 μm. Field-emission scanning electron microscope (FE-SEM) is used to
inspect the device after the source/drain patterning and the channel of a typical SN-TFT
with 5 m channel length is shown in Figure 4.1c. From the image, one can find that the
channel consists of uniform and dense nanotube thin-film due to the effort of our APTES
assisted deposition.
68

Figure 4.1 Symmetric p-type and n-type SN-TFTs. (a) Schematic diagram of a n-type back-gated SN-TFT with Ti/Au
(5 Å/50 nm) contacts and SiO
2
(50 nm) gate dielectric. (b) Optical micrograph of the SN-TFT array with various
channel lengths (5, 10, 20, 50, and 100 μm) and channel widths (10, 20, 50, 100 and 200 μm). (c) FE-SEM image of a
typical SN-TFT with 5 m channel length. (d, e) Transfer (I
D
-V
G
) (d) and output (I
D
-V
D
) (e) characteristics of a typical
SN-TFT (L = 5 m, W = 200 μm) before (blue) and after (red) HfO
2
ALD. (f, g) I
D
-V
G
characteristics (red: linear scale,
green: logarithm scale) and g
m
-V
G
characteristics (blue) of the same device with V
D
= 1 V before (f) and after (g) HfO
2
ALD, respectively.

e
g
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
-5.0 -2.5 0.0 2.5 5.0
0
3
6
9
12
15
18

Gate Voltage (V)
Drain Current ( A)
Before ALD
0
1
2
3
4
5
6
Transconductance ( S)
Drain Current (A)

10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
-5.0 -2.5 0.0 2.5 5.0
0
3
6
9
12
15
18

Gate Voltage (V)
Drain Current ( A)
After HfO
2
ALD
0
1
2
3
4
5
Transconductance ( S)
Drain Current (A)
-5.0 -2.5 0.0 2.5 5.0
0
3
6
9
12
15
18
0.2 V
0.4 V
0.6 V
0.8 V
V
D
= 1 V
0.2 V
0.4 V
0.6 V
0.8 V
N-CNTFET P-CNTFET

Drain Current ( A)
Gate Voltage (V)
V
D
= 1 V
V D = 1 V V D = 1 V
b c a
f
d
-1.0 -0.5 0.0 0.5 1.0
0
3
6
9
12
15
18
0
3
6
9
12
15
18
I
ds
( A)
P-CNTFET

-I
ds
( A)
Drain Voltage (V)
N-CNTFET
V
G
is from -5 V to 5 V
in 1 V step
69

The electrical performance of the SN-TFTs is characterized. Figure 4.1d and e shows
the family transfer (I
D
-V
G
) (Figure 4.1d) and output (I
D
-V
D
) (Figure 4.1e) characteristics
of the typical SN-TFTs before (blue) and after (red) HfO
2
deposition. These curves are
from the devices with the same geometry (channel length of 5 m and channel width of
200 m). More in-depth information of these two devices is shown in Figure 4.1f and g
which contain the I
D
-V
G
characteristics in both linear and logarithm scale and g
m
-V
G

characteristics measured at V
D
= 1 V before and after HfO
2
ALD, respectively. From
Figure 4.1d–g, one can find that the n-type SN-TFTs obtained using the ALD passivation
method exhibit perfectly symmetric behavior compared with their p-type counterparts in
terms of on-current (before ALD 18.1 A, after ALD 17.4 A), transconductance (before
ALD 5.06 S, after ALD 4.59 S), and on/off ratio (before ALD 1.616× 10
6
, after ALD
1.34× 10
6
). In addition, the device mobilities for these two devices are also very similar
and the typical mobilities for the devices with 5 m channel length are about 5 cm
2
V
-1
s
-1

before ALD and 3 cm
2
V
-1
s
-1
after HfO
2
ALD. Higher mobility can be obtained by
increasing the device channel length as longer channel length will reduce the effect of the
metal contact resistance on the device mobility. The mobility can reach up to 11 cm
2
V
-1
s
-1
and 6 cm
2
V
-1
s
-1
for p-type and n-type device with 100 m channel length.
It is worth noting that symmetric n-type and p-type transistors with good
performance have also been demonstrated before by using Sc as n-type contacts and Pd
as p-type contacts on an individual carbon nanotube.[27]

Compared with the previous
work, our method not only serves as an alternative approach that is compatible with the
standard semiconductor fabrication process, but also offers the benefit of long-term
70

stability in air. In order to verify this point, we have measured the electrical
characteristics of the n-type SN-TFT after being exposed in air for 9 months. The transfer
characteristics of two typical devices with Al
2
O
3
and HfO
2
passivation are plotted in
Figure 4.2. From the figure, one can find that the electrical characteristics of the
ALD-passivated n-type nanotube transistor remain almost unchanged.

Figure 4.2 Long term air-stability of the n-type SN-TFTs. As fabricated (blue) and 9 months later (red) transfer
characteristics for two typical n-type SN-TFTs with (a) HfO
2
(L = 5 μm, W = 200 μm) and (b) Al
2
O
3
(L = 5 μm, W =
100 μm) passivation measured with V
D
= 1 V.

4.3 Mechanism of the carrier type conversion
To get a better understanding of such carrier type conversion, we carried out
systematic experiments to study the temperature dependence of this method. HfO
2
is
deposited onto the SN-TFTs using ALD at different temperatures (150 ° C and 250 ° C).
The transfer characteristics of devices with 5 m channel length and 200 m channel
width plotted in Figure 4.3a clearly reveal the temperature dependence of this ALD
n-type method. At low temperature (150 ° C), the device exhibits ambipolar transistor
a b
-5.0 -2.5 0.0 2.5 5.0
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
Al
2
O
3
As fabricated
9 months later

Drain Current (A)
Gate Voltage (V)
-5.0 -2.5 0.0 2.5 5.0
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
As fabricated
9 months later

Drain Current (A)
Gate Voltage (V)
HfO
2
71

behavior but as the temperature increases (250 ° C), the P-branch on-current decreases
while the N-branch on-current increases, and the device is turned into n-type.
Based on the above experiments, two key factors are believed to be the reason for the
conversion from pristine p-type SN-TFTs to n-type by adding ALD high-κ oxide layer. (1)
The baking processing in the vacuum chamber during the ALD process, (2) The positive
fixed charge in the high-κ oxide layer introduced due to the deficiency of oxygen atoms.
It is known that the intrinsic carbon nanotubes have symmetric E-k relationships for
electrons and holes, which means that the intrinsic nanotube devices should exhibit
ambipolar transistor behavior. However, the adsorption of oxygen in the ambient and the
work function of the contact metal will affect the ultimate electrical property of the
devices. [24,28,29] For devices with Au contact, Schottky barriers are present for both
the electrons and holes, but due to the adsorbed oxygen molecules, some equivalent
negative charge will be stored near the source and drain contacts in the channel, which
will bend the energy band upwards and reduce the Schottky barrier width for holes. The
bended band structures under different gate voltages are shown in Figure 4.3b as the dash
line. When a negative gate voltage is applied to the device, the energy band will be
bended upwards even further. When the Schottky barrier is thin enough, holes can tunnel
through and the transistor is turned on. In contrast, when a positive voltage is applied to
the gate, the energy band will be flattened, increasing the barrier for holes, and putting
the transistor into OFF state. Therefore, due to the prescence of oxygen, the SN-TFTs
with Au contact in ambient typically show p-type transistor behavior.

72

During the ALD process, the devices are baked at 250 ° C in an evacuated chamber
with a pressure of 0.3 Torr for about 30 min. Oxygen atoms near the nanotube surface are
driven away and desorbed during the ALD process. In the meantime the high-κ oxide
layer is deposited on top to passivate the device, which will prevent the oxygen from
adsorbing onto the nanotube again and make the nanotube intrinsic. Moreover, positive
fixed charges will also be introduced into the high-κ dielectic layer, which is supported by
the capacitance-voltage (C-V) measurement by previous work, [26,30] and the deficiency
of oxygen atoms in the high-κ oxide layer is believed to be the reason for the positive
charges. The generated electric field due to the accumulated positive fixed charges near
the nanotube/ALD interface will bend the energy bend downwards and shift the transfer
characteristics toward more negative gate voltages. As a result, the electron conduction is
increased. Since the carrier type conversion is mainly resulted from the charges that are
close to the nanotube/ALD interface, the thickness of the ALD passivation layer should
not matter that much. The corresponding energy band diagrams are shown in Figure 4.3b
as the solid line. From the energy bend, one can find that the transistor will be turned on
when the gate voltage is positive and turned off when it is negative, i.e. the n-type
transistor behavior. When the temperature for ALD is high, the H
2
O introduced during
the ALD process vaporizes faster and is pumped away immediately, which means less
oxygen atoms are available during the formation of high-κ oxide layer. As a result, due to
the deficiency of the oxygen atoms in the oxide layer, more positive charge is
accumulated and the nanotube energy bend will be bent down even further. This explains
the temperature dependence as observed in Figure 4.3a.
73

In order to prove our hypothesis for the mechanism of the p-type to n-type
conversion by the ALD high-κ oxide layer, a series of experiments are designed and
carried out. We choose two p-type SN-TFTs with the same geometry and similar
electrical performance and let them go through the ALD process with different high-κ
materials (HfO
2
and Al
2
O
3
). HfO
2
ALD process is believed to introduce more positive
charge than the Al
2
O
3
ALD process. [26,30]

Based on our hypothesis, we should observe
larger shift in the transfer characteristics from the device with HfO
2
ALD than the device
with Al
2
O
3
ALD. The transfer characteristics of these two devices before and after ALD
measured at V
D
= 1V are shown in Figure 4.3c. The results are in accordance with the
expected transistor behavior, which is a good support for our hypothesis. Moreover, from
the figure, one can find that the shape of the P-branch transfer characteristics of the
device after ALD is very similar to the p-type transistor transfer characteristics before
ALD, which is also strong evidence that the n-type transistor behavior is resulted from
the shift of the intrinsic ambiploar behavior of SN-TFT due to the positive fixed charge.
Besides, we have also deposited Al
2
O
3
onto the SN-TFTs under different ALD
temperatures. Similar temperature dependence is also observed and the transfer
characteristics are exhibited in Figure 4.3d. The transistors covered with low temperature
ALD of Al
2
O
3
still show p-type behavior, which is because the positive charge in the low
temperature Al
2
O
3
layer is not sufficient to convert the device into n-type. As temperature
increases, more charges are trapped in Al
2
O
3
layer, which decreases the hole conduction
and increases the electron conduction. However, since Al
2
O
3
provides less positive fixed
charges compared with HfO
2
, the device is turned into ambipolar behavior with stronger
74

N-branch current instead of predominant n-type. The transfer characteristics for devices
with different ALD materials and various deposition temperatures are very reproducible
and controllable.

Figure 4.3 The mechanism of the n-type SN-TFT passivated by ALD high-κ oxide layer. (a) I
D
-V
G
characteristics of the
SN-TFTs (L = 5 m, W = 200 μm) with ALD of HfO
2
deposited at different temperatures (150 ° C and 250 ° C)
measured at V
D
= 1 V. Inset: schematic diagram to explain the conversion mechanism. (b) Band structure of the
nanotube-metal contact with (solid line) and without (dash line) ALD layer under different gate voltages (V
G
> 0 V, V
G

= 0 V, and V
G
< 0 V). (c) I
D
-V
G
characteristics of a typical SN-TFT (L = 5 m, W = 200 μm) in logarithm scale before
(red) and after HfO
2
(blue) and Al
2
O
3
(green) ALD measured V
D
= 1 V. (d) Temperature dependence of the I
D
-V
G

characteristics of the SN-TFTs (L = 5 m, W = 200 μm) with ALD of Al
2
O
3
measured at V
D
= 1 V.
As discussed above, the carrier type conversion after the ALD passivation is due to
the positive fixed charge in the ALD material, which will shift the device transfer
characteristics and thus affecting the threshold voltages. As both the ALD material and
-5.0 -2.5 0.0 2.5 5.0
0
2
4
6
8
10
12
14
16
@150
o
C
@250
o
C

Drain Current ( A)
Gate Voltage (V)
V D = 1 V
a
c d
b
-5.0 -2.5 0.0 2.5 5.0
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
Before ALD
After HfO
2
ALD
After Al
2
O
3
ALD

Drain Current (A)
Gate Voltage (V)
V D = 1 V
With Al 2O 3 ALD
-5.0 -2.5 0.0 2.5 5.0
0
2
4
6
8
10
@150
o
C
@250
o
C

Drain Current ( A)
Gate Voltage (V)
V D
= 1 V
75

deposition temperature determine the amount of charge, the threshold voltage of the
transistor can be adjusted by carefully controlling the ALD deposition condition. Figure
4.4a shows the transfer characteristics for devices with the same geometry (L = 5 μm and
W = 200 μm) before (green trace) and after Al
2
O
3
ALD at 150 ° C (red trace) and 250 ° C
(blue trace). From this plot, one can clearly see the temperature dependence of the carrier
type conversion. The pristine p-type device can be converted into ambipolar device with
either stronger P-branch (150 ° C) or stronger N-branch (250 ° C). Besides, as the ALD
temperature increases, a larger negative shift of the I
D
-V
G
curves is observed. Therefore,
the N-branch threshold voltage can by adjusted by tuning the ALD temperature.

Figure 4.4 (a) Transfer characteristics of devices (L = 5 μm and W = 200 μm) before (green) and after Al
2
O
3
ALD at
150 ° C (red) and 250 ° C (blue) plotted in logarithm scale. (b) Statistic data of the n-type device threshold voltages with
HfO
2
(blue) and Al
2
O
3
(red) passivation.
Different ALD material also affects the device threshold voltage as the amount of the
accumulated fixed charge varies in different materials. We have randomly selected 20
n-type devices with either Al
2
O
3
or HfO
2
passivation deposited at 250 °C, and their
threshold voltage distributions are plotted in Figure 4.4b. The figure shows that the
devices with HfO
2
passivation exhibit smaller threshold voltages (0.36 V on average)
a b
-5.0 -2.5 0.0 2.5 5.0
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
Befor ALD
ALD @150
o
C
ALD @250
o
C

Drain Current (A)
Gate Voltage (V)
V
D
= 1 V
1 2 3 4 5 6 7 8 9 10
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
HfO2
Al2O3

Threshold Voltage (V)
Device number
76

than those with Al
2
O
3
passivation (2.17 V on average), because HfO
2
provides more
positive fixed charges. Moreover, the threshold voltages of devices with the same
passivation material exhibit relatively small variation, suggesting that this approach is
reproducible and controllable.
4.4 Factors affecting the n-type SN-TFT performance.
During these experiments, we have also found that channel length affects the ratio
between the N-branch on-current (I
on_N
) and P-branch on-current (I
on_P
) of the SN-TFT
after the carrier conversion. As the channel length increases, the N-branch on-current
decreases more significantly than the P-branch on-current. Therefore, the I
on_N
/I
on_P
ratio
will decrease which means the transfer chracteristics of the SN-TFTs with ALD will
change from predominant n-type to almost ambipolar. This phenomenon is illustrated in
Figure 4.5a, where devices with the same channel width (W = 100 μm) and various
channel lengths (L = 5, 10, 20, 50, and 100 μm) are passivated with ALD of HfO
2
at
250 ° C. In order to get a better understanding of this channel length dependence, we
measured 200 devices (100 with ALD of HfO
2
, and the other 100 with ALD of Al
2
O
3
)
and the average ratios of I
on_N
/I
on_P
after ALD are summarized in Figure 4.5b. The figure
shows that both kinds of the devices have similar channel length dependence but devices
with HfO
2
passivation have much higher I
on_N
/I
on_P
ratio than the devices with Al
2
O
3
passivation.
This channel length dependence of I
on_N
/I
on_P
is attributed to the unique feature of
the nanotube network, which is percolation. Unlike the aligned or individual nanotube
devices, [31,32] nanotube percolation is happening inside the channel of SN-TFTs. This
77

Figure 4.5 In-depth study of the factors affecting the n-type SN-TFT performance. (a) I
D
-V
G
characteristics of the
SN-TFTs measured at V
D
= 1 V with the same channel width (W = 50 μm) and various channel lengths (L = 5, 10, 20,
50, and 100 μm) measured at V
D
= 1 V plotted in logarithm scale after ALD of HfO
2
deposited at 250 ° C. (b) Plot of
I
on_N
/I
on_P
(the ratio between the N-branch on-current and the P-branch on-current) versus the reciprocal of channel
length (1/L) for the n-type SN-TFTs with Al
2
O
3
and HfO
2
passivation. N-branch and P-branch on-currents are
measured with V
D
= 1 V, V
G
= 5 V or -5 V, respectively. (c) Statistical data of normalized N-branch and P-branch
on-current density (I
on
/W) versus 1/L for devices with HfO
2
and Al
2
O
3
passivation.
gives considerable channel resistance (R
ch
) for SN-TFTs with nanotube network as the
channel material. Because R
ch
= R
□
L/W, where R
□
is the sheet resistance of the separated
nanotube film with a typical value of 25 kΩ/□, [19]

the channel resistance is directly
proportional to the channel length (L). When a positive gate voltage is applied, the
current is determined by the electron conductance (G
e
), which equals to the inverse of the
sum of channel resistance and contact resistance for electrons (R
c_e
). Or we can write it as:
G
e
= 1/(R
ch
+R
c_e
). For the n-type device, R
c_e
is relatively small when the device is on, so
when the channel length is long enough, R
ch
will be much larger than R
c_e
. In another
word, G
e
≈ 1/R
ch

and I
on_N
= G
e
V
DS
≈ V
DS
/R
ch
= V
DS
W/R
□
L, meaning that I
on_N
is
proportional to 1/L. On the other hand, when the gate voltage is negative, the
conductance for holes (G
h
) can be written as G
e
= 1/(R
ch
+R
c_h
), where R
c_h
is the contact
resistance for holes. For n-type devices, the contact resistance for holes is very large even
with a negative V
G
because of the Schottky barrier, so G
e
≈ 1/R
c_h
and I
on_P
= G
h
V
DS
≈
V
DS
/R
c_h
. As R
c_h
comes from the Schottky barrier, which is independent of L, I
on_P
will
-5.0 -2.5 0.0 2.5 5.0
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
L=5 m
L=10 m
L=20 m
L=50 m
L=100 m

Drain Current (A)
Gate Voltage (V)
0.00 0.05 0.10 0.15 0.20
0.00
0.02
0.04
0.06
0.08
0.10
0.12
I
on
/W ( A/ m)
HfO2 ALD (N-branch on-current)
Al2O3 ALD (N-branch on-current)
HfO2 ALD (P-branch on-current)
Al2O3 ALD (P-branch on-current)

1/L ( m
-1
)
0 20 40 60 80 100
50
100
150
200
250
300
350
400
I
on_N
/I
on_P
HfO
2
ALD
Al
2
O
3
ALD
I
on_N
/I
on_P

Channel Length ( m)
0
4
8
12
16
20
24
28
32

b c a
V D =
1 V
78

stay the same even if L varies. The statistic data in Figure 4.5c proves our analysis. As L
increases from 5 μm to 100 μm, I
on_N
changes almost proportionally with 1/L while the
variation of I
on_p
is negligible, this leads to the drop of I
on_N
/I
on_P
ratio. Moreover, the
devices covered by HfO
2
have higher I
on_N
/I
on_P
ratio than the ones covered by Al
2
O
3
because of much lower I
on_P
at the gate voltage (V
G
= -5 V). In summary, shorter channel
length and HfO
2
ALD is preferred in order to get a perfect n-type behavior transistor
which is important for integrate circuit applications as it can affect the static power
consumption.

Figure 4.6 The effect of different source/drain metal contact materials. (a, b) I
D
-V
G
characteristics of typical SN-TFTs
(L = 5 m, W = 200 μm) with Ti/Au (a) and Ti/Pd (b) metal contacts before and after Al
2
O
3
ALD measured at V
D
= 1 V .
Other than the ALD temperature and channel length, the work function of the
source and drain contact metal is also a crucial factor for the n-type transistor
performance. For digital circuit applications, it is preferred to have symmetric p-type and
n-type transistor behavior in order to simplify the circuit design and also to save the
layout area. Besides, to guarantee the long-term air-stability and reliability of the n-type
device performance, the source and drain metal contacts must be stable and resistant to
a b
-5.0 -2.5 0.0 2.5 5.0
0
2
4
6
8
10
12
14
With Au S/D
Before ALD
After ALD

Drain Current ( A)
Gate Voltage (V)
V D = 1 V
-5.0 -2.5 0.0 2.5 5.0
0
10
20
30
40
50
Before ALD
After ALD

Drain Current ( A)
Gate Voltage (V)
With Pd S/D
V D = 1 V
79

oxidation. In this regard, some of the low work function metals such as Al and Ti etc. are
not suitable, as they will easily get oxidized under elevated temperatures during ALD
process. In comparison, Au is a good candidate as it is a stable metal and can provide
similar Schottky barriers for both electrons and holes in the nanotubes. To verify this
point, we made devices with Au and Pd as the metal contacts and converted them into
n-type devices by using ALD Al
2
O
3
passivation. Both kinds of devices have a channel
length of 5 μm and channel width of 200 μm and the transfer characteristics are plotted in
Figure 4.6. The curves reveal that for the device with Pd source and drain metal contacts
(Figure 4.6b), although the device has a higher p-type on-current before conversion (47
μA when V
G
= -5 V and V
D
= 1 V) which is what we expected as Pd forms Ohmic contact
for holes due to its large work function, the device after ALD has a much lower n-type
on-current (6.3 μA). Moreover, after conversion, the device still has significant amount of
p-type on-current and the ratio of I
on_N
/I
on_P
is only 2.74. In contrast, the device with Au
electrodes (Figure 4.6a) exhibits rather symmetric device performance in terms of
on-current before and after ALD (13.4 μA for the p-type device and 11.6 μA for the
n-type device). Besides, after the conversion into n-type, the P-branch on-current with Au
source/drain contacts is much lower compared with the device with Pd contacts and the
I
on_N
/I
on_P
ratio for this device is 43.5, 16 times larger than the Pd-contacted device. From
this comparison, one can find that Au electrodes can provide symmetric p-type and n-type
transistor performance and are thus better candidates than Pd for CMOS integrate circuit
applications.

80

4.5 Contact resistivity and channel sheet resistance analysis
We have extracted the contact resistivity and channel sheet resistance using the
transmission line measurement (TLM). The total device resistance (R
tot
) equals the sum
of the contact resistance (R
c
) and channel resistance (R
ch
). As R
ch
= R
□
L/W, where R
□
is
the sheet resistance of the separated nanotube thin-film, the total device resistance can be
written as R
tot
= R
c
+ R
□
L/W or R
tot
W

= R
c
W+ R
□
L. This equation means that at a fixed
channel width, R
tot
is proportional to the channel length with the slope corresponding to
R
□
and the intercept corresponding to the scaled contact resistivity (R
c
W). Therefore, by
plotting the normalized device resistivity data at gate biases of -5 V (p-type) and 5 V
(n-type) as a function of channel length (Figure 4.7), the scaled contact resistivity and
channel sheet resistance can be derived.

Figure 4.7 Measured device resistivity as a function of channel length before (blue) and after (red) HfO
2
ALD.
The calculated contact resistivities before and after HfO
2
ALD are 4.3 MΩ· μm and
6.7 MΩ· μm, respectively. This suggests that the n-type and p-type SN-TFTs have
comparable contact resistivity, which means that the Au contacts can provide similar
0 20 40 60 80 100
0
50
100
150
200
250
Before ALD
After HfO
2
ALD

Device Resistivity (M m)
Channel Length ( m)
81

Schottky barriers for both electrons and holes. On the other hand, the channel sheet
resistance increased from 785 kΩ/□ to 2.05 MΩ/□ after the ALD process, which might be
related to the ALD coating on the tube/tube junctions, leading to increased junction
resistance in the nanotube network. Although the sheet resistance increased after the
carrier type conversion, for short channel length devices, where the contact resistance
dominates, the total device resistances are comparable for both n-type and p-type devices.
Therefore, almost symmetric device behaviors can be achieved for transistors with 5 μm
channel length.
4.6 Channel length dependence of the n-type and p-type SN-TFT device
performance metrics
We have studied the channel length dependence of the n-type and p-type SN-TFT
device performance metrics (I
on
/W, on/off ratio) by measuring 300 devices with various
channel lengths and channel widths. Out of these devices, 100 of them are pristine p-type
SN-TFTs, 100 are converted to n-type SN-TFTs by HfO
2
ALD passivation and the rest
100 are n-type SN-TFTs with Al
2
O
3
ALD passivation. Key device performance metrics
including on-current density, on/off ratio are calculated and plotted in Figure 4.8.
Figure 4.8a exhibits the normalized on-current densities (I
on
/W) of the transistors
with various channel lengths and channel widths measured at V
D
= 1 V , V
G
= 5 V and -5
V for n-type and p-type SN-TFTs, respectively. The figure indicates that the on-current
density is approximately reversely proportional to the channel length for all three kinds of
SN-TFTs. The relationship between the average on-current and channel width is also
82

measured and is plotted in Figure 4.8b. The data is obtained from devices with 10 μm
channel length measured at the same bias voltages mentioned above. All three curves in
the figure show highly linear relationship, which illustrates the uniformity of the
separated nanotube film used in this study. Besides, comparing the data for the transistors
before and after ALD passivation, one can find that the n-type and p-type SN-TFTs
exhibit comparable performance in terms of on-current.

Figure 4.8 (a) Average normalized on-current density (I
on
/W) versus the reciprocal of channel length (1/L), (b) average
on-current (I
on
) versus channel width when channel length equals 10 μm, (c) average on/off ratio (I
on
/I
off
) versus
channel length for p-type SN-TFTs (red), n-type SN-TFTs with HfO
2
ALD (blue) and Al
2
O
3
ALD (green).
Moreover, other than the on-current discussed previously, the on/off ratio is studied
and explained in Figure 4.8c. All three kinds of devices exhibit on/off ratio higher than
10
4
for all the channel lengths studied. This high on/off ratio is crucial for digital
applications, as it helps to get large switching and rail-to-rail output which makes it easier
to achieve large noise margin. More importantly, the low off-state current can reduce the
static power consumption. Based on our previous report using 95% semiconducting
nanotubes, [19] the on/off ratio increases as the channel length increases due to the
reduction in the probability of percolative transport through metallic nanotube networks.
Here in this work, 98% semiconducting nanotube is used, the probability of percolative
a b c
0.00 0.05 0.10 0.15 0.20
0.00
0.05
0.10
0.15
I
on
/W ( A/ m)
Before

ALD (P-branch current)
HfO
2
ALD (N-branch current)
Al
2
O
3
ALD (N-branch current)

1/L ( m
-1
)
0 50 100 150 200
0
4
8
12
16
20
I
on
( A)
Before

ALD (P-branch current)
HfO
2
ALD (N-branch current)
Al
2
O
3
ALD (N-branch current)

Channel Width ( m)
0 20 40 60 80 100
10
2
10
3
10
4
10
5
10
6
10
7
On/Off Ratio
Before

ALD
HfO
2
ALD
Al
2
O
3
ALD

Channel Length ( m)
83

transport through metallic nanotube networks is nearly eliminated even for the shortest
channel length of 5 μm. In addition, the device on/off ratio almost stays the same before
and after ALD process, this ensures that the n-type devices obtained from this ALD
passivation technique can be used in nanotube CMOS logic circuits. One thing worth
mentioning is that the slight decrease in the on/off ratio for longer channel device is not
ascribable to the real device performance. It is because when the channel is very long, the
on-current decreases, while the off-current is already too small to be measured precisely
by our equipment (HP 4156B Semiconductor Parameter Analyzer with an accuracy of 1
pA). Therefore the calculated on/off ratios also decrease slightly.
The device mobility is also calculated by considering the electrostatic coupling
between the nanotubes in the channel network. First of all, the mobility can be extracted
based on the device transconductance using the following equation:
dm
device
D ox g D ox
dI g LL
V C W dV V C W
     (1)
where L and W are the device channel length and width, C
ox
is the gate capacitance
per unit area and g
m
is the device transconductance extracted from the maximum slope of
the transfer characteristics measured at V
D
= 1 V . Because of the one dimensional
property of nanotubes, electrostatic coupling between nanotubes needs to be considered
when calculating the gate capacitance. Following the previous work, the equation for the
gate capacitance can be written as: [33,34]
1
11 00
0
0
sinh(2 / ) 1
ln
2
ox
ox Q
ox
t
CC
R

   


  
  




(2)

84

Where 1/Λ
0
stands for the density of nanotubes and is measured to be around 10
tubes/μm, C
Q
= 4.0× 10
-10
F/m is the quantum capacitance of nanotubes, [35] t
ox
= 50 nm
is the thickness of the dielectric layer, R = 1.2 nm is the average diameter of our
nanotubes, and ε
0
ε
ox
= 3.9× 8.85× 10
-14
F/cm is the dielectric constant at the interface
where the nanotubes are placed. Based on Equation 2, one can find that C
ox
= 3.46× 10
-8

F/cm
2
. Therefore based on Equation 1 and the transconductance derived from the transfer
characteristics, we can calculate the devices mobility of the n-type and p-type SN-TFTs.

Figure 4.9 Average device mobility versus channel length for the p-type SN-TFTs (red), n-type SN-TFTs with HfO
2

(blue), and n-type SN-TFTs with Al
2
O
3
(green).
Based on the discussion above, the mobility for the n-type and p-type SN-TFTs with
various channel lengths can be derived and the results are plotted in Figure 4.9. From the
figure, one can find that the mobility for the pristine p-type SN-TFTs and n-type
SN-TFTs with HfO
2
ALD passivation increases as channel length increases. The reason is
that Schottky barriers are present between the Au/nanotube contacts, so the device
mobility is likely to be limited by the contacts, similar to the case for aligned nanotube
transistors. [31,34,36] As the channel length increases, the effect of metal/nanotube
0 20 40 60 80 100
2
4
6
8
10
12
14
Mobility (cm
2
V
-1
s
-1
)
Before

ALD
HfO
2
ALD
Al
2
O
3
ALD

Channel Length ( m)
85

contacts become less significant and the mobility increases. One interesting finding is
that for the n-type SN-TFTs with Al
2
O
3
ALD passivation, the mobility reduces as the
channel length increases. The reason for this is not yet clear and is worthy of further
investigation. The highest mobility obtained for the p-type SN-TFTs, n-type SN-TFTs
with HfO
2
, and n-type SN-TFTs with Al
2
O
3
are 11 cm
2
V
-1
s
-1
, 5.6 cm
2
V
-1
s
-1
and 5.9
cm
2
V
-1
s
-1
, respectively. All these values are much higher than the typical mobility for
amorphous silicon (0.4 cm
2
V
-1
s
-1
) [37]

and organic materials (0.02 cm
2
V
-1
s
-1
) [38].
4.7 CMOS logic circuits based on symmetric n-type and p-type
separated nanotube thin-film transistors
By utilizing the symmetric n-type and p-type SN-TFTs we have obtained, we further
connect them into a CMOS inverter whose schematic is shown in Figure 4.10b inset.
According to discussion above, devices with 5 μm channel length, 200 μm channel width,
and Au source/drain metal contacts are selected, and 15 nm ALD HfO
2
passivation
deposited at 250 ° C is used to achieve the n-type SN-TFTs. The corresponding transfer
characteristics of the p-type and n-type SN-TFTs used in the inverter are shown in Figure
4.10a. The as obtained CMOS inverter works with a V
DD
of 5 V and the corresponding
inverter voltage and current transfer characteristics are plotted in Figure 4.10b. The
inverter exhibits symmetric input/output behavior with rail-to-rail output and the inverter
threshold voltage is measured to be 2.6 V , which is very close to one half of the supply
voltage (V
DD
/2 = 2.5 V). Moreover, the current is zero when the output reaches its
boundary meaning that the static power consumption is almost zero as long as the
86

inverter stays in “0” or “1” state. In addition, by taking the derivative of the voltage
transfer characteristics, one can get the information about the gain of the inverter as
illustrated in Figure 4.10c. The highest gain of the inverter is calculated to be 8.4
achieved at an input voltage of 2.7 V .
To make the performance of the nanotube CMOS logic circuits more predictable and
practical, we utilize the compact device model based on the traditional field-effect
transistor operation theory to simulate the p-type and n-type SN-TFTs as well as CMOS
inverter. The model is based on the parameters such as the mobility, on/off ratio and
on-current extracted from the statistic data of 200 SN-TFTs, and the corresponding
simulation results of the SN-TFT transfer characteristics and the CMOS inverter voltage
transfer characteristics are plotted in Figure 4.10a and b as the dash line, respectively.
From the figure, one can find that the simulation results fit the experimental results very
well, which is very important as it gives a way to simulation and predict the large scale
logic circuit performance before real circuit fabrication.

Figure 4.10 CMOS inverter circuit using almost symmetric p-type and n-type SN-TFTs. (a) Experiment (scatter line)
and simulation (dash line) data of the I
D
-V
G
characteristics of typical p-type (blue) and n-type (red) SN-TFTs (L = 5 m,
W = 200 μm) used in the inverter with V
D
= 1 V. (b) Inverter voltage (experiment: red straight trace; simulation: green
dash trace) and current (blue trace) transfer characteristics. Inset: schematic diagram of the CMOS inverter. The
inverter works with a V
DD
of 5 V and exhibits symmetric input/output behavior. The inverter threshold voltage (V
TH
) is
2.6 V. (c) Plot of inverter gain versus input voltage where the highest gain is 8.4. The input low voltage (V
IL
) and the
input high voltage (V
IH
) are measured to be 1.8 V and 3.1 V, respectively.
a
0 1 2 3 4 5
0
1
2
3
4
5
Experiment
Simulation
I
DD
( A)

Output Voltage (V)
Input Voltage (V)
V
TH
0
1
2
3
4
5

-5.0 -2.5 0.0 2.5 5.0
0
2
4
6
8
10
12
14
N-type device (experiment)
N-type device (simulation)
P-type device (experiment)
P-type device (simulation)

Drain Current ( A)
Gate Voltage (V)
V D = 1 V
0 1 2 3 4 5
0
2
4
6
8
V
IH

Inverter Gain
Input Voltage (V)
V
IL
b
c
87

For digital circuits, other than the properties discussed above, there is one more
crucial parameter affecting the circuit performance which is the noise margin (NM).
33
It is
important because it quantifies how much external signal perturbation can a logic gate
withstand while operating. This tolerance ability to variations in the signal level is
especially valuable for the circuit nowadays as the supply voltage is getting smaller and
smaller while the parasitic effect is becoming more and more considerable. For a logic
gate like an inverter, the noise margin is the minimum of two values: the noise margin for
low signal levels (NM
L
) and the noise margin for high signal levels (NM
H
). Furthermore,
NM
L
is defined as the difference between maximum input voltage which can be
interpreted as logic “0” (V
IL
) and minimum output voltage when the output level is logic
“0” (V
OL
) or NM
L
= V
IL
-V
OL
. Similarly, NM
H
is the difference between maximum output
voltage when the output level is logic “1” (V
OH
) and minimum input voltage which can be
interpreted as logic “1” (V
IH
) or NM
H
= V
OH
-V
IH
. V
IH
and V
IL
are usually calculated as the
input voltages when the inverter gain equals to 1. Therefore, from the gain curve plotted
in Figure 4.10c, one can find that for our CMOS inverter, V
IL
= 1.8 V and V
IH
= 3.1 V . By
definition, V
OL
and V
OH
here are 0 V and 5 V , respectively, so NM
L
is calculated to be 1.8
V and NM
H
to be 1.9 V . Accordingly, the noise margin for the inverter is 1.8 V . As the
supply voltage is 5 V and the inverter V
TH
is 2.6 V , a noise margin of 1.8 V reveals that
the circuit has very strong noise tolerance ability and is easy to cascade with other logic
blocks. The reason we can get such a large noise margin is because of the contribution of
both the CMOS structure and symmetric n-type and p-type transistor behavior.

88

Besides the discrete inverter, we went one step further and demonstrated some basic
CMOS integrated logic gates, such as inverters, NAND and NOR gates. The results of
the integrated logic circuits are shown in Figure 4.11. Figure 4.11a illustrated the
schematic structure of the integrated inverter. As exhibited in this figure, both the p-type
and n-type transistors are fabricated based on separated nanotube thin-films but obtained
by different device structure. The p-type transistors are realized using the back-gated
device structure, where the nanotubes are exposed to ambient air and show p-type
behavior. At the meantime, the n-type transistors are made using the top-gated structure,
where the nanotubes are converted to n-type due to passivation effect of the ALD gate
dielectric layer. The fabrication steps of the CMOS integrated circuits are described as
followings: Firstly, Ti/Au (1 nm/50 nm) were patterned and deposited on Si/SiO
2

substrates as the gate electrodes for p-type devices and source/drain electrodes n-type
devices. Secondly, separated nanotube thin-films were deposited on the substrate and
patterned as the channel of n-type transistors. After that, 40 nm HfO
2
was deposited by
ALD served as the gate dielectric for both the n-type and p-type transistors. Also, 5 nm
SiO
2
was deposited on top of the ALD layer to improve the adhesion of nanotubes to the
substrate. Following that another layer of nanotubes were deposited and patterned as the
channel for the p-type transistors. Finally, gate electrodes for n-type devices as well as
source/drain electrodes for the p-type transistors were formed by Ti/Au (1 nm/50 nm).
Figure 2.11b exhibits the performance of the integrated CMOS inverter. From this
figure, one can find that similar to the discrete CMOS inverter discussed above,
symmetric input and output as well as rail-to-rail output is achieved. Also, current reaches
89

Figure 4.11 CMOS integrated logic circuits. (a) Schematic diagram of the integrated CMOS inverter based on n-type
and p-type SN-TFTs. (b, c) Output characteristics of the corresponding NAND and NOR circuits. The supply voltages
for both circuits are V
DD
= 5V. Input voltages of 5V and 0V are treated as logic “1” and “0”, respectively.

0 when the inverter is in the “0” or “1” state, which means that power consumption is
zero when the inverter is in the steady states. More importantly, compared with the
discrete inverter, a higher gain (11.6) was obtained for the integrated CMOS inverter,
which should attributed to smaller parasitic resistance and capacitance of the integrated
circuit and individual gate structure. In addition to inverters, more sophisticated circuits
such as 2-input NAND and NOR have also been demonstrated. Figure 2.11c and d shows
the schematics (inset) and output characteristics of the NAND and NOR, respectively. 5
V and 0 V applied on gate A and B are treated as logic “1” and “0”, respectively. For the
NAND gate, the output is “1” when either one of the two inputs is “0” (Figure 2.11c),
a
b
d
c
90

while for the NOR gate, the output is “0” when either one of the two inputs is “1” (Figure
2.11d). It is worth noting that, compared with the PMOS structure NAND and NOR gates
illustrated in Chapter 2, the CMOS structure NAND and NOR gated shown here exhibit
rail-to-rail output behavior, which is due to the stronger pull-down network in the CMOS
structure logic gates.
4.8 Summary
In conclusion, we report a reliable method to convert the SN-TFTs into air-stable
n-type transistors by passivating the devices with high-κ oxide layer deposited using ALD
and its application in CMOS logic circuits. n-type devices achieved using the proposed
ALD method exhibit symmetric electrical performance as compared with the pristine
p-type SN-TFTs in terms of on-current, on/off ratio and mobility. We have further
revealed that the desorption of oxygen and accumulation of positive fixed charge in the
high-κ oxide layer are the reasons for the carrier type conversion and this is verified by a
series of designed experiments. Besides, we have systematically studied the factors that
affect the n-type device performance including the ALD temperature, device channel
length and the material of the source/drain metal contacts. Moreover, CMOS discrete and
integrated inverter has been further demonstrated using p-type and n-type SN-TFTs with
symmetric transistor performance. The inverter exhibits rail-to-rail output, symmetric
input/output behavior and large noise margin, which allow the possibility of cascading
multiple stages of logic gates. In addition, more sophisticated CMOS circuits such as
2-input NAND and NOR gates have been demonstrated, rail-to-rail output behavior was
also observed. Our work represents significant advance in fabricating high performance
91

air-stable n-type thin-film transistors using semiconducting nanotubes and can provide
guidance to future research on SN-TFT based CMOS integrate circuits.

92

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95

Chapter 5: Rigid / Flexible Transparent Electronics Based on
Separated Carbon Nanotube Thin-film Transistors and their
Application in Display Electronics

5.1 Introduction
Since first proposed in 1997, [1] transparent electronics has attracted extensive
attention due to its great potential in wide variety of areas including solar cells, [2]

photo
detectors, [3]

charge-coupled devices (CCDs), [4] and so forth. Among all of those
applications, transparent display is one of the most attractive and promising ones. [5-7]
The major challenge for the realization of transparent displays is the development of high
performance transparent thin-film transistors with decent mobility, high current on/off
ratio, low operation voltage, and low-temperature-compatible fabrication process.
Amorphous silicon, [8,9] poly-silicon, [10,11] and organic materials [12,13] are possible
candidates for transparent transistor channel materials, but they either suffer from low
mobility and low transparency or require high-temperature process.
Compared with the above channel materials, single-walled carbon nanotubes
(SWNTs) [14-17] have advantages in terms of mobility, transparency, flexibility, and low
temperature processing. Transparent devices have already been reported previously by
using both aligned carbon nanotube arrays and random nanotube networks. [18-20]
However, those transistors share a common drawback, which is the co-existence of both
metallic and semiconducting nanotubes, and therefore require addition steps such as
electrical breakdown or stripe-patterning process to improve the device on/off ratio,
96

which would hurt the uniformity and mobility of the transistors. Recently, significant
progress has been made by us and several other groups in carbon nanotube thin-film
transistor (TFT) direction. High performance TFTs [21-25] have been demonstrated using
pre-separated semiconducting nanotubes produced by density-gradient ultracentrifuge
separation method [26,27]. In those previous reports, due to the use of high purity
semiconducting nanotubes, transistors exhibit highly uniform electrical performance,
high on/off ratio (>10
5
), as well as excellent mobility (up to 67 cm
2
V
-1
s
-1
), which make
separated nanotube thin-film transistors (SN-TFTs) very attractive for transparent
electronic applications.
In this chapter, we report our recent advance on fully transparent separated carbon
nanotube thin-film transistors on both rigid and flexible substrates, and their application
in display electronics. Transparent SN-TFTs with uniformly assembled separated
nanotube networks as channel material and indium tin oxide (ITO) as electrodes were
fabricated on glass substrate through low-temperature process. In addition, we have
investigated the contacts between ITO and naonotubes, and introduced a thin metal layer
(Au and Pd used) in between to improve the device performance. About three-time device
enhancement in terms of on-current and device mobility were achieved by adding the thin
metal layers. Furthermore, transparent SN-TFTs were also fabricated on flexible
substrates and excellent flexibility was observed. Finally, as a demonstration, OLED
control circuit has been fabricated using the transparent SN-TFT with output light
intensity modulation over 10
3
. Our transparent SN-TFT platform shows significant
advantages over conventional platforms with respect to low temperature processing
97

compatibility, scalability, reproducibility and device performance, and suggests a
practical and realistic approach for carbon-nanotube-based transparent devices, circuits,
and display applications.
5.2 Structure of rigid/flexible transparent SN-TFTs
Figure 5.1a illustrates our fully transparent SN-TFT device structure. 98%
semiconducting nanotubes obtained from NanoIntegris, Inc. (IsoNanotubes-S ™) were
uniformly deposited onto the glass substrate with pre-patterned ITO back gate (100 nm)
and Al
2
O
3
/SiO
2
(40 nm/ 5 nm) dielectric layer. We carried out separated nanotube
deposition by using aminopropyltriethoxy silane (APTES) to functionalize SiO
2
surface
and then immersing the substrate in nanotube solution as reported in Chapter 2 and our
previous publications[22,23]
.
Following that, source and drain electrodes made of 100 nm
ITO were sputter-coated and defined on top of the nanotube thin-film by
photolithography and lift-off techniques. Field-emission scanning electron microscopy
(FE-SEM) was used to inspect the surface after nanotube assembly.
Figure 5.1b is a representative SEM image of the deposited separated nanotube thin
film inside the transistor channel region on the glass substrate. From this image, one can
find that high-density, monolayer nanotube networks are uniformly deposited on top of
the Al
2
O
3
/SiO
2
dielectric layer. Nanotubes show very clean and smooth surface due to the
cleaning process using DI water and isopropanol alcohol rinsing after deposition. The
deposited nanotube density is around 30 tubes/μm
2
, which is a desired density for
transistor application considering the trade-off between the device on-current and current
on/off ratio studied in our previous work.

[24]
98

Figure 5.1 Fully transparent separated carbon nanotube devices. (a) Schematic diagram of a transparent SN-TFT with
ITO (100 nm) as back gate, Al
2
O
3
/SiO
2
(40 nm/5 nm) as gate dielectric, and ITO (100 nm) as source and drain contacts.
(b) FE-SEM image of the separated carbon nanotube thin-film inside the transistor channel region. (c) Optical
transmittance of the bare glass substrate (red curve) and glass with arrays of transparent SN-TFTs with ITO contacts
(blue curve). Inset: Optical image of the fully transparent SN-TFTs on 2 inch square shape glass substrate with the
substrate area marked with a red frame for clarity. (d) Schematic diagram showing the fabrication steps for transparent
SN-TFTs on flexible substrates. (e) Optical image of transparent SN-TFTs on PET substrate.
Due to the excellent transparency of the CNT film and ITO electrodes, SN-TFT
arrays on glass substrate have excellent transparency as exhibited in Figure 5.1c, where
99

the background can be easily seen through these devices fabricated on a 2 inch glass
substrate (marked in red dash lines) in the inset photograph. Optical transmittance
measurement in this plot shows that the sample with fabricated transparent SN-TFTS
with ITO electrodes had transmittance ~ 85% over the visible light regime (380 nm – 780
nm). In contrast, a similar glass substrate without any devices on top had a transmittance
~90%, so the transparent SN-TFTs only decreased the transmittance from 90% to 85%.
Benefited from the low temperature fabrication process, transparent SN-TFTs can
also be fabricated on flexible substrates. Flexible electronics is extremely attractive
owing to its wearable and portable properties as well as compatibility with roll-to-roll
fabrication.[7,12,13] Figure 5.1e illustrates the fabrication steps for transparent SN-TFTs
on flexible substrates. To minimize the fabrication difficulty, devices are first patterned
on thin polyimide (PI) films on silicon handling wafers.[28,29] After the fabrication,
transistors together with the polyimide films can be peeled off from the silicon wafer and
transferred to any target flexible substrates. As an example, Figure 5.1f shows an optical
image of transparent SN-TFTs on a polyethylene terephthalate (PET) substrate. Electrical
performance of the flexible transparent SN-TFTs will be discussed later in this article.
5.3 Electrical performance of fully transparent transistors
Electrical performance of fully transparent transistors on glass substrate is studied
and shown in Figure 5.2. Figure 5.2a exhibits the transfer characteristics of a typical
transparent SN-TFT with channel length of 100 m and channel width of 100 μm
including the drain current-gate voltage (I
D
-V
G
) characteristics in both linear and
logarithm scale and transconductance-gate voltage (g
m
-V
G
) characteristics measured at
100

drain voltage of 1 V. From this plot, one can find that on-current (I
on
) at V
D
= 1 V and V
G

=-5 is 0.55 A. Also, from the transfer curve in logarithm scale, one can derive the
current on/off ratio and subthreshold slope (S = dV
G
/[d(log
10
I
D
)]) to be 10
3
and 1.2
V/dec, respectively. In addition, the peak transconductance of this transistor is 0.16 S,
and device mobility is extracted to be 1 cm
2
V
-1
s
-1
. It is worth noting that the parallel plate
model is used to estimate the gate capacitance when calculating the device mobility,
which is essentially the effective device mobility for a TFT of channel length L and

Figure 5.2 Electrical performance of the transparent devices with ITO electrodes. (a) Transfer (I
D
-V
G
) characteristics
(red, linear scale; green, log scale) and g
m
-V
G
characteristics (blue) of a typical SN-TFT (L = 100 m, W = 100 μm)
with V
D
= 1 V. (b) I
D
-V
G
characteristics of a typical SN-TFT (L = 100 m, W = 100 μm) under different V
D
from 0.2 to
1.0 V (the step of V
D
was 0.2 V). (c, d) Output (I
D
-V
D
) characteristics of the same device in triode regime (c) and
saturation regime (d), respectively.
a
-5.0 -2.5 0.0 2.5 5.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VD = 1V
VD = 0.8V
VD = 0.6V
VD = 0.4V
VD = 0.2V

Drain Current ( A )
Gate Voltage (V)
-1.0 -0.5 0.0 0.5 1.0
-0.4
-0.2
0.0
0.2
0.4
0.6
V
G
from -5 V to 5 V
with 1 V steps

Drain Current ( A )
Drain Voltage (V)
b
-5 -4 -3 -2 -1 0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
V
G
from -5 V to 1 V
with 1 V steps

Drain Current ( A)
Drain Voltage (V)
10
-9
10
-8
10
-7
10
-6
-5.0 -2.5 0.0 2.5 5.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6

Gate Voltage (V)
Drain Current ( A )
0.00
0.05
0.10
0.15
0.20
Transconductance ( S)
Drain Current (A)

c
d
101

channel width W. The real gate capacitance would be smaller than the parallel plate
model predicts if we take the electrostatic coupling between nanotubes into consideration
and therefore the real nanotube network mobility can be larger than the value listed above.
[30,31]

While previously many groups, including us, reported mobility by calculating the
gate capacitance with electrostatic coupling between nanotubes into
consideration[22,32,33], we would like to point out that the effective device mobility is
as important, because it provides direct comparison with film-based TFTs and correlates
directly to transconductance and normalized on-current, both of which are important
parameters for TFT applications. In addition, family transfer and output characteristics of
this device can be found in Figure 5.2b, c and d.
5.4 Transparent transistors with improved contacts
Judging from the parameters derived above, the transparent devices with ITO
contacts exhibit rather moderate performance compared with previous reported SN-TFTs
with Ti/Pd source and drain contacts. This is resulted from the work function difference
between the ITO (3.9-4.4 eV) [34] electrodes and the nanotube thin-films (4.7-5.1 eV)
[35,36], which introduces large barriers at the source and drain contacts. As nanotube is
usually p-type doped in air, large work function metals, such as Au (5.1-5.47 eV) and Pd
(5.22-5.6 eV), are preferred to achieve ohmic contacts for holes. However, continuous Au
and Pd are not transparent over visible light regime, which means SN-TFTs will lose their
transparency if thick layer of metals are deposited directly as the electrodes. Therefore, in
order to improve the device performance while maintain a reasonable transmittance, we
added a thin layer (1 nm) of metal between nanotube and ITO to lower the contact barrier.
102

As only very small amount of metal was evaporated, instead of forming a continuous film,
metal “islands” were deposited on the substrate, which makes the metal layer
semi-transparent. Optical transmittance measurement of the thin metal films shown in
Figure 5.3 proves this point. In this plot, the transmittance of the glass substrate was
deducted as the background. Au thin film shows a transmittance of around 92% in the
visible light regime while the Pd thin film exhibits about 3% lower transmittance. The
transparency of the thin metal film can also be seen from the inset photograph, where the
Au film on glass shows a light pink color (corresponding to the transmittance drop at 540
nm) and Pd film shows a grey color compare to the bare glass slides.

Figure 5.3 Optical transmittance of the 1 nm Au (red) and 1 nm Pd (blue) thin-film. Inset: Photography of the thin
metal films on glass slides.
The electrical performance of the transparent SN-TFTs improves significantly after
thin-metal films are applied, which can be found in Figure 5.4. Figure 5.4a shows the
improved device structure, where 1nm Au or Pd was evaporated on top of the deposited
nanotube film before ITO sputtering. Typical I
D
-V
D
plots for devices with the same
channel geometry (L = 20 m, W = 100 μm) but with different source and drain contacts
103

under V
G
= -5 V shown in Figure 5.4b reveals that ohmic contacts were achieved for
devices with Au/ITO and Pd/ITO electrodes and on-current for these two kinds of devices
increased about 3 times compares with the one from devices with ITO-only source and
drain electrodes. While the electrical performance has been improved, the transparency of
the devices did not change too much. Figure 5.4c plots the transmittance of glass
substrates with arrays of transparent SN-TFTs with Pd/ITO, Au/ITO, and ITO contacts.
From this figure, one can found that the transmittance of the devices only decreases about
3% (with Au/ITO) and 5% (with Pd/ITO) compared with the ITO only electrodes, which
is acceptable considering the significant electrical performance improvement.
In addition to the on-current and optical transmittance, more detailed analysis of the
improved transparent SN-TFTs is shown in Figure 5.4 d and e, which includes the
transfer characteristics in both linear and logarithm scale and g
m
-V
G
characteristics of
typical device with channel dimension of L = 100 m, W = 100 μm. Based on this plot,
one can find that devices with Au/ITO and Pd/ITO exhibit similar behavior in terms of
on-current (1.8 A for device with Au/ITO contacts and 1.5 A for device with Pd/ITO
contacts; same sequence for parameters listed below), current on/off ratio (1.07× 10
3
and
1.6× 10
3
), subthreshold slope (0.8 V/dec and 0.85 V/dec), and peak transconductance (0.7
S and 0.6 S). Also, based on the peak transconductance, the derived device mobilities
for these two kinds of device are 4.47 cm
2
V
-1
s
-1
for transistor with Au/ITO contacts and
3.72 cm
2
V
-1
s
-1
for the one with Pd/ITO contacts. Compared with the devices that have the
same channel geometry but with ITO only source drain electrodes, all the parameters
listed above show 2-3 times improvement owing to the added large work function metal
104

Figure 5.4 Transparent transistors with improved contacts. (a) Schematic diagram of the improved transparent SN-TFT
structure with Au/Pd + ITO as the source and drain contacts. (b) Typical I
D
-V
D
plots for devices with the same channel
geometry (L = 20 m, W = 100 μm) but with Au/ITO (red), Pd/ITO (black), and ITO (blue) contacts under V
G
= -5 V,
respectively. (c) Optical transmittance of glass substrates with arrays of transparent SN-TFTs with Au/ITO (green
curve), Pd/ITO (blue curve), and ITO (red curve) contacts. (d, e) Transfer (I
D
-V
G
) characteristics (red, linear scale;
green, log scale) and g
m
-V
G
characteristics (blue) of the typical SN-TFTs (L = 100 m, W = 100 μm) with Au/ITO (d)
and Pd/ITO (e) contacts measured at V
D
= 1 V, respectively.

105

contact film. In addition, although Pd has slightly higher work function compared with
Au, devices with thin layers of Au and Pd provide similar electrical performance. This
may be due to the reason that the deposited Au/Pd were too thin to form a continuous
film, so the contact resistances between nanotube and source/drain electrodes are not only
affected by the work function of the thin metal layers, but also depend on some other
factors, such as the resistance of the thin metal layers or the contact resistances between
Au/Pd and ITO layers. While devices with Au film have higher transmittances, Au/ITO
contacts could be a better choice for transparent electronic applications.
5.5 Performance of fully transparent and flexible SN-TFTs
Besides the transistors on glass substrates, performance of transparent SN-TFTs on
flexible substrates is also investigated. Flexible transparent SN-TFTs with Au/ITO
contacts and 50 nm Al
2
O
3
and 5 nm SiO
2
gate dielectrics were fabricated on thin
polyimide (PI) films on silicon handling wafers and then transferred to polyethylene
terephthalate (PET) substrates for flexibility measurements. Figure 5.5a is the optical
transmittance of the transparent and flexible devices on PET. The optical transmittance is
~80% in the 500~1100 nm wavelength range, which is similar to the ones fabricated on
glass substrates. The sudden drop of transmittance below 500 nm is due to the existence
of the PI film, which shows a light yellow color. To evaluate the flexibility of our devices,
I
D
-V
G
measurements were performed under various bending radii (r) using the setup
illustrated in the inset of Figure 5.5c, and the plots are shown in Figure 5.5b. The I
D
-V
G

curves correspond to a device before bending (black), under weak (r = 12 mm, red),
moderate (r = 9.7 mm, green; r = 8.8 mm, blue), strong bending (r = 6.4 mm, cyan), and
106

after bending (magenta), respectively. From these curves, normalized transconductance
g
mn
(take the one before bending as g
m0
) and on/off ratio of this device at each bending
condition were extracted and plotted in Figure 5.5c. One can see that benefitting from the
excellent mechanical properties of SWNT [37], the device continued to perform as a
transistor for different bending radius and very small variation is observed from the
on-current, transconductance, and on/off ratio, which is also proved by the output (I
D
-V
D
)
characteristics of the same device before bending and with 6.4 mm radius bending as
exhibited in Figure 5.5d.

Figure 5.5 Fully transparent and flexible SN-TFTs. (a) Optical transmittance of a PET substrate with transparent
SN-TFTs with Au/ITO contacts. (b) Transfer (I
D
-V
G
) characteristics of a representative device (L = 100 m, W = 100
μm) under different bending radius in linear and logarithm scales. (c) Normalized transconductance (red) and on/off
ratio (blue) extracted from the data in Figure 5.6b versus bending radius. Inset shows an optical micrograph of the
experimental setup to measure I
D
-V
G
under different bending radius. (d) Output (I
D
-V
D
) characteristics of the same
device under different gate voltages with bending radius of 6.4 mm. Vg was swept from -5 V (black curve) to 2 V with
1 V steps.
107

5.6 Display electronics based on fully transparent SN-TFTs
Our ability to fabricate high performance transparent SN-TFTs on both rigid and
flexible substrates enable us to further explore their application in transparent display
electronics. For the proof of concept purpose, an organic light-emitting diode (OLED)
was connected to and controlled by a typical SN-TFT device on glass substrate whose
transfer and output characteristics are shown in Figure 5.6a and b, respectively. In order
to control OLED, device on-current as well as on/off ratio are crucial. Here the device
channel length and channel width are both selected to be 100 μm so that the transistor can
provide enough current while the on/off reaches 1.3× 10
3
and therefore can meet the
requirement for controlling the OLED to switch on and off. Standard NPD/Alq
3
OLED (2
× 2 mm
2
) with multi-layered configuration is employed in this study given as
ITO/4-4’-bis[N-(1-naphthyl)-N-phenyl-amino]bi-phenyl (NPD) [40
nm]/tris(8-hydroxyquinoline) aluminium (Alq
3
) [40 nm]/LiF [1 nm]/aluminum (Al) [100
nm] whose transfer characteristics are shown in the Chapter 2. The schematic of the
OLED control circuit is shown in the inset of Figure 5.6c, where the drain of the driving
transistor was connected to an external OLED and a negative voltage (-V
DD
) was applied
to the cathode of the OLED. Current flow through the OLED (I
OLED
) was measured by
sweeping the V
DD
while also changing input voltage V
G
as plotted in Figure 5.6c. The
figure illustrates that the tested OLED has a threshold voltage of about 3 V and it will be
turned on when the controlling transistor is in the “ON” state and the supply voltage is
higher than the OLED threshold voltage. Furthermore, the current flow through OLED
can be modified by varying the voltage applied to V
G
, as directly revealed in Figure 5.6d
108

where current versus V
G
characteristics are plotted with a fixed V
DD
of -8 V . From this
figure and the inset optical photographs taken at certain gate voltages, one can find that
the light intensity of the OLED is modulated by the gate voltage and it can be fully turned
on and turned off when V
G
are biased at -5 V and 5 V , respectively.

Figure 5.6 OLED control circuit by transparent SN-TFT. (a)Transfer (I
D
-V
G
) characteristics under different drain
voltages (from 0.2 V to 1 V with 0.2 V steps) for the device used to control the OLED (L = 100 m, W = 100 μm), Inset:
I
D
-V
G
plot of the same device in logarithm scale with V
D
= 1 V. (b) Output (I
D
-V
D
) characteristics of the same device
with different gate voltages. (c) I
OLED
-V
DD
Characteristics of the OLED control circuit. Various curves correspond to
various values of V
G
from -5 to 5 V in 1 V steps. Inset: Schematic diagram of the OLED control circuit. (d) Plot of the
current through the OLED (I
OLED
) versus V
G
with VDD= -8 V. The inset optical images show the OLED intensity at
certain gate voltages.

-5.0 -2.5 0.0 2.5 5.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4

Drain Current ( A)
Gate Voltage (V)
-5.0 -2.5 0.0 2.5 5.0
10
-10
10
-9
10
-8
10
-7
10
-6

Drain Current ( A )
Gate Voltage (V)
V
D
= 1 V
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
-2.0
-1.5
-1.0
-0.5
0.0
V
G
from -5 V to 1 V
with 1 V steps

Drain Current ( A)
Drain Voltage (V)
-8 -6 -4 -2 0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
G
from -5 V to 5 V
with 1 V steps

I
OLED
( A)
V
DD
(V)
I
OLED
V
DD
V
G
a
b
c
d
109

5.7 Summary
In summary, we have reported significant progress on fabrication of transparent
SN-TFTs for display electronics. These separated carbon nanotube based thin-film
transistors exhibit excellent transparency (~ 85%) and good electrical performance. In
addition, to further improve the device performance, a thin layer of large work function
metal is applied between carbon nanotube and ITO electrodes. While still maintaining the
attractive transparency (~82%) and current on/off ratio (>10
3
), devices with Au/ITO
electrodes show improved performance in terms of device mobility (4.47 cm
2
V
-1
s
-1
) and
subthreshold slope (0.8 V/dec). Furthermore, flexible and transparent SN-TFTs have been
fabricated and tested, very small variation of on-current, transconductance, and current
on/off ratio is observed down to 6.5 mm bending radius. Finally, OLED control circuit
has been demonstrated with transparent SN-TFTs, and large range output light intensity
modulation has been observed. Our results suggest that transparent SN-TFTs have great
potential to serve as building blocks for future transparent electronics. And this
demonstration can provide guidance to future research on SN-TFT based transparent
display electronics.

110

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113

Chapter 6: Electrical performance analysis of gel-based
separated nanotubes with different diameter and their
Thin-Film Transistor applications

6.1 Introduction
Since first discovered in 1991 [1], carbon nanotube has attracted a lot of attention
due to its extraordinary electrical properties such as high intrinsic carrier mobility and
current-carrying capacity [2-5]. Thin-films of single-walled carbon nanotubes which
exhibit extraordinary conductivity, transparency and flexibility hold great potential as
channel material for thin-film transistor (TFT) applications. Other popular TFT channel
materials, such as amorphous silicon [6]

and organic materials [7-9] suffer from their low
carrier mobility, while polycrystalline silicon [10,11] and metal oxide [12,13] have the
drawback of high cost and high temperature processing. Compared with all the materials
above, nanotube thin-films have the advantages of low cost, room-temperature processing
compatibility, superb transparency, excellent flexibility, as well as high device
performance. During the past four years, inspirited by density-gradient ultracentrifuge
(DGU) carbon nanotube separation method developed by Hersam and his coworkers
[14,15] , high-performance TFTs [16-18] using pre-separated semiconducting nanotubes
have been fabricated by us and several other groups. In those previous Chapters,
transistors exhibit high on/off ratio (>10
5
) as well as excellent current drive capability (~
1 µ A/µ m), and applications such as digital logic circuits [19,20], transparent electronics
114

[21] and active matrix organic light-emitting diode (AMOLED) displays [22] have been
demonstrated. However, the high cost and complexity of DGU nanotube separation
process limits the commercialization of separated nanotube thin-film transistors
(SN-TFTs). How to obtain high purity semiconducting nanotubes by a simple and low
cost method becomes very crucial for the implementation of SN-TFT electronics.
Recently, several groups [23,24] have reported a gel-based column chromatographic
nanotube separation method, which is very simple and inexpensive. By this method, high
purity semiconducting and even single chirality nanotubes [25,26] can be separated, and
devices fabricated using gel-based separation nanotubes show excellent electrical
performance. [27] Due to these merits, gel-based separation nanotube looks very
promising for TFT applications such as display electronics. In spite of the significant
progress reported so far, many interesting issues remain to be studied. For example,
among all the mainstream nanotubes, which kind of nanotubes is more suitable for TFT
applications? What are the key factors affecting the gel-based SN-TFT performance?
Is gel-based SN-TFTs good enough for AMOLED display applications? Does gel-based
separated nanotube have similar electrical property as DGU-based separated nanotubes?
To answer the above mentioned questions, in this Chapter, we report our recent
advance on gel-based column chromatographic nanotube separation of different kinds of
nanotubes and its application in macroelectronics. Our work includes the following
essential components. (1) We have carried out gel-based column chromatography for
arc-discharge nanotubes (Carbon Solutions, Inc), HiPCO nanotubes (Unidym, Inc), and
CoMoCAT nanotubes (Sigma Aldrich, Inc). High purity semiconducting nanotubes were
115

achieved. (2) SN-TFTs were fabricated using the three kinds of different gel-based
separated nanotubes and key device performance metrics such as on-current density,
on/off ratio, sheet resistance and device mobility are directly compared. Based on the
detailed analysis, we have revealed the diameter dependent performance behaviour of
SN-TFTs, and find that large diameter nanotubes are ideal for applications such as radio
frequency transistors, while small diameter nanotubes are preferred for applications like
digital circuits. (3) In addition, we have also compared the electrical property of
gel-based and DGU-based semiconducting nanotubes, and similar electrical performance
was observed for both kinds of semiconducting nanotubes. Our Gel-based SN-TFT
platform shows significant advantages over conventional platforms with respect to cost,
scalability, reproducibility, and device performance, and suggests a practical and realistic
approach for nanotube based AMOLED display applications.
6.2 Gel-based column chromatographic nanotube separation
To carry out nanotube separation, all three kinds of nanotubes were first dispersed in
aqueous solution. Arc-discharge nanotubes were dispersed in water with the assistant of
sodium cholate (SC) with a concentration of 1 mg/mL, while HiPCO and CoMoCAT
nanotubes were dispersed in aqueous solution assisted by 1% sodium dodecyl sulfate
(SDS, Sigma-Aldrich (99%)) at 0.3 mg/ml and 1 mg/mL, respectively. All three kinds of
nanotubes were sonicated using a tip-type ultrasonic homogenizer (Sonicator 3000,
Misonix) for 2 h at 9 W in a water/ice bath. After sonication, the solution was centrifuged
to remove any possible bundles or impurities (20,000× g for 3 h at 14 ° C). The resulting
supernatant was collected as Arc-discharge, HiPCO and CoMoCAT SWNT solutions.
116

After dispersion, all three kind of nanotubes went through gel-based separation
process, which is described as following: First, sephacryl medium (GE healthcare, Inc)
was filled into a typical column (30 cm in length and 2 cm in width). Second, the column
was equilibrated by flushing with 1% SDS solution. The nanotube solution was then
added to the column. After that 1% SDS solution was used to elute the column and
metallic nanotubes were sorted out during this elution step. Following that, for
arc-discharge and HiPCO nanotubes, 1% SC solution was added into the column to wash
out the remaining semiconducting nanotubes, while 1% SDS+0.04% SC solution was
used to get semiconducting CoMoCAT nanotubes.

400 800 1200 1600 2000

Intensity
Raman shift (cm
-1
)
Arc discharge
HiPCO
CoMCAT

Figure 6.1 The Raman shift of arc-discharge, HiPCO and CoMoCAT SWNTs and their respective G/D ratios.
After separation, we have characterized gel-based column chromatographic separated
nanotubes synthesized by different methods. Three kinds of carbon nanotubes, namely
arc-discharge nanotubes, HiPCO nanotubes, and CoMoCAT nanotubes are selected and
studied in this work. Ramen spectrum for all three kinds of nanotubes are shown in
Figure 6.1, which exhibited that high G/D ratio (35, 50, and 28 for arc-discharge, HiPCO
and CoMoCAT semiconducting nanotubes), or good quality, is observed for all the
117

nanotubes. Besides nanotube quality, diameter distribution is the main differences for
these three kinds of nanotubes. Arc-discharge nanotubes have diameters about 1.3 nm to
1.7 nm, which is longer compared with HiPCO nanotubes (0.8 nm to 1 nm) and
CoMoCAT nanotubes (~ 0.7 nm). Due to this diameter difference, different optical and
electrical properties were observed for these three kinds of separated nanotubes, which
will be discussed later in this article.
Figure 6.2 shows the comparison of gel-based column chromatographic separated
nanotubes synthesized by different methods. The UV-Vis-NIR absorption spectra before
(blue) and after (red) gel-based separation are plotted in Figure 6.2a-c (a: arc-discharge
nanotubes; b: HiPCO nanotubes; c: CoMoCAT nanotubes). Based on these curves, one
can derive the purity of the separated semiconducting nanotubes, which is 98%, 92% and
95%, respectively. Besides purity, diameter information can also be extracted, where
arc-discharge semiconducting nanotubes exhibit a diameter range of 1.3 nm to 1.7 nm,
while HiPCO and CoMoCAT ones show diameter range of 0.8 nm to 1 nm and ~ 0.7 nm,
respectively. Because of the different diameter distribution, these three kinds of separated
nanotubes exhibits different optical properties, which can be seen from the peak locations
in the UV-Vis-NIR absorption spectra, as well as the color of the separated
semiconducting nanotubes solutions shown in the inset of Figure 6.2a-c (light brown
color for arc-discharge semiconducting nanotubes; dark green color for HiPCO
semiconducting nanotubes; purple color for CoMoCAT semiconducting nanotubes).
Other than purity and diameter, nanotube length also plays a crucial role for nanotube
thin-film transistor performance. To characterize the length distribution of the three kinds
118

of gel-based separated semiconducting nanotubes, more than one hundred tubes from
each kind were imaged and measured by Field-emission scanning electron microscope

Figure 6.2 Comparison of gel-based column chromatographic separated nanotubes synthesized by different methods.
(a-c) UV-Vis-NIR absorption spectra of arc-discharge nanotubes (a), HiPCO nanotubes (b), and CoMoCAT nanotubes
(c) before (blue) and after (red) separation. Inset: Nanotube solutions after separation. (d-f) Length distribution of the
separated semiconducting arc-discharge nanotubes (d), HiPCO nanotubes (e), and CoMoCAT nanotubes (f), the
average nanotube length is 540 nm, 617 nm, and 576 nm, respectively. Inset: FE-SEM images of separated
semiconducting nanotubes network deposited on Si/SiO
2
substrates with APTES functionalization, where the scale bar
is 1 µ m. (g) Schematic diagram of a back-gated SN-TFT. (h) Optical microscope image of the SN-TFT array fabricated
on silicon substrate with 50 nm SiO
2
acting as gate dielectric.
(FE-SEM), and the histograms are shown in Figure 6.2 d-f. From these plots, one can
find that arc-discharge nanotubes, HiPCO nanotubes, and CoMoCAT nanotubes show
similar average nanotube lengths, which are 540 nm, 617 nm and 576 nm, respectively.
119

This similarity of nanotube length distribution is due to the fact that same nanotube
dispersion recipe was applied for all three kinds of nanotubes, as described above. As all
these three kinds of separated nanotubes are similar in terms of semiconducting purity
and nanotube length, they can be the ideal materials to study the diameter effort on the
electrical performance of SN-TFTs.
6.2 Electrical performance of gel-based SN-TFTs
To fabricate SN-TFT devices, high density, uniform separated nanotube thin-films
were deposited on Si/SiO
2
substrates using the solution-based aminosilane assisted
separated nanotube deposition technique reported in our previous publications. FE-SEM
is used to inspect the samples after nanotube assembly and the SEM images of the
arc-discharge, HiPCO, and CoMoCAT semiconducting nanotubes deposited on Si/SiO
2

substrates are shown in the inset of Figure 6.2d-f, respectively. These three kinds of
nanotubes have similar nanotube density, which is measured to be 32-41 tubes/μm
2
for
arc-discharge nanotubes, 27-38 tubes/μm
2
for HiPCO nanotubes, and 26-36 tubes/μm
2
for
CoMoCAT nanotubes. After nanotube assembly, the deposited separated nanotube
thin-films are used for back-gated SN-TFTs fabrication (see Methods). The schematic
diagram of the back-gated SN-TFTs and the optical microscope image of a fabricated
SN-TFT array are shown in Figure 6.2g and h, respectively.
Electrical performance of the arc-discharge, HiPCO and CoMoCAT SN-TFTs is
compared and exhibited in Figure 6.3. Such SN-TFTs are made with channel width (W)
of 200, 400, 800, 1200, 1600, and 2000 μm, and channel length (L) of 4, 10, 20, 50, and
100 μm. Based on these devices, we have carried out systematic analysis of the electrical
120

Figure 6.3 Electrical properties of back-gated SN-TFTs using gel-based separated semiconducting nanotubes
synthesized with different methods. (a-c) Normalized transfer characteristics (I
D
/W-V
G
) of the SN-TFTs using
semiconducting arc-discharge nanotubes (a), HiPCO nanotubes (b), and CoMoCAT nanotubes (c) with various channel
lengths (4, 10, 20, 50, and 100 μm) and 2000 μm channel width plotted in logarithm scale. (d-f) Transfer characteristics
(red: linear scale, green: log scale) and g
m
-V
G
characteristics (blue) of a typical SN-TFT (L = 10 μm, W = 2000 μm)
using semiconducting arc-discharge nanotubes (d), HiPCO nanotubes (e), and CoMoCAT nanotubes (f). (g-i) Output
characteristics (I
D
-V
D
) of the same devices in (d-f).
performance of the SN-TFTs. Figure 6.3a-c are the normalized transfer characteristics
(I
D
/W-V
G
) of the SN-TFTs using arc-discharge (Figure 6.3a), HiPCO (Figure 6.3b) and
CoMoCAT (Figure 6.3c) semiconducting nanotubes with various channel lengths (4, 10,
20, 50, and 100 μm) and fixed channel width (2000 μm) plotted in logarithm scale. All
the curves are measured at V
D
= 1V . From the figures, following behaviors can be
observed. (1) Devices from all nanotube samples show p-type field-effect behavior and
much higher on/off ratio compared with the devices fabricated using unsorted nanotubes
121

(typical on/off ratio of 2~3). (2) As the device channel length increases, the on/off ratio
increases while the on-current decreases. In addition, all three kinds of devices exhibits
on/off ratio higher than 10
6
when the channel length is longer than 50 μm. (3) The
devices using larger diameter (arc-discharge > HiPCO > CoMoCAT) semiconducting
nanotubes exhibit better on-current but lower on/off ratio than the devices using smaller
diameter semiconducting nanotubes.
Figure 6.3d-f exhibit the transfer characteristics (red: linear scale, green: log scale)
and g
m
-V
G
characteristics (blue) of typical SN-TFTs using three kinds semiconducting
nanotubes measured at V
D
= 1V . All the devices have a channel length of 10 μm and
width of 2000 μm. Based on these plots, one can find the key device performance metrics
of these three devices. For the arc-discharge SN-TFT, the on-current density (I
on
/W) at V
D

= 1V , V
G
= -10V is measured to be 0.34 μA/μm, and on/off raito is 2 × 10
4
. The
transconductance (g
m
) can also be extracted from the maximum slope of the transfer
characteristics, which is 113 μS. For the HiPCO SN-TFT, on-current density is 0.066
μA/μm, on/off ratio is 3.6× 10
6
, and transconductance is 33 μS. At the meantime, the
on-current density, on/off ratio and transconductance of the CoMoCAT SN-TFT are
calculated to be 0.0175 μA/μm, 1.6× 10
7
, and 10.6 μS, respectively. The corresponding
output characteristics (I
D
-V
D
) of these three SN-TFTs are also plotted in Figure 6.3g-i,
respectively. Under small V
D
biases, the devices exhibit linear behavior, indicating that
ohmic contacts are formed between the metal electrodes and the nanotubes. Saturation
behaviour was observed when more negative V
D
is applied, indicating nice field-effect
operation.
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6.3 Diameter effect on SN-TFT device performance
To get a more comprehensive understanding of the diameter dependent electrical
performance behavior, we have compared the key device performance metrics such as
on-current density, channel sheet resistance, on/off ratio and device mobility for SN-TFTs
based on gel-based separated nanotubes with different diameters. Figure 6.4 summarizes
the results after the measurement of 180 SN-TFTs with different semiconducting
nanotube diameters and various channel lengths, channel widths. Figure 6.4a shows the
normalized on-current densities (I
on
/W) of the transistors with various channel lengths
measured at V
D
= 1 V and V
G
= -10 V , showing that the on-current density is
approximately inversely proportional to the channel length for all three kinds of
semiconducting nanotubes. The highest on-current density is measured to be 1 μA/μm,
which comes from SN-TFTs using arc-discharge semiconducting nanotubes with a
channel length of 4 μm. Overall, with the same device dimension, SN-TFTs using
arc-discharge nanotubes provides about 5 times higher on-current density compared with
the ones using HiPCO nanotubes, and about 17 times higher on-current density compared
with the ones with CoMoCAT nanotubes. This conclusion is also in consistent with the
data shown in Figure 6.3.
To understand the reason of this on-current density difference, we have analysed the
contact resistivity and channel sheet resistance of these three different kinds of devices
using transfer length methods (TLM). For each transistor, we know that the total device
resistance (R
tot
) equals to the sum of the contact resistance (R
c
) and channel resistance
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Figure 6.4 Statistical study and key device performance metrics comparison of SN-TFTs using separated nanotubes
with different synthetic methods. (a) Current density (I
on
/W) versus reversed channel length for TFTs fabricated on
separated semiconducting nanotubes synthesized by arc-discharge (blue), HiPCO (red), and CoMoCAT (green)
methods. Plot of (b) device resistance and (c) average on/off ratio (I
on
/I
off
) versus channel length for the same TFTs
characterized in (a). (d) Trade-off between Current density (I
on
/W) and on/off ratio (I
on
/I
off
). (e) On/off ratio (I
on
/I
off
)
versus drain voltage for devices using three different kinds of semiconducting nanotubes with L = 50 μm and W = 1200
μm. (f) Relationship between device mobility and channel length for three kinds of SN-TFTs.
124

(R
ch
). As R
ch
= R
□
L/W, where R
□
is the sheet resistance of the separated nanotube film, the
total resistance can be described as: R
tot
= R
c
+ R
□
L/W or R
tot
W

= R
c
W+ R
□
L which means
that at fixed channel widths, the device resistance follows a linear relationship with the
channel length while the slope stands for the sheet resistance (R
□
) and the intercept stands
for the scaled contact resistivity (R
c
W). Therefore, using the normalized device resistivity
data obtained at gate bias of -10 V with different channel length, we can derive the scaled
contact resistivity and channel sheet resistance of the three different kinds of SN-TFTs
and the results are plotted in Figure 6.4b. The calculated channel sheet resistances for
arc-discharge SN-TFTs, HiPCO SN-TFTs and CoMoCAT SN-TFTs are 0.28 MΩ/□, 3.28
MΩ/□ and 6.46 MΩ/□, respectively. As the sheet resistances are dominated by the tube to
tube junction resistance [28], we can conclude that larger diameter nanotubes provides
smaller junction resistance compared with smaller diameter nanotubes, which may be
attributed to the fact that large diameter nanotubes have larger physical junction contact
areas, and therefore the junction resistances are reduced. Further experiments and
analysis maybe needed to validate this hypothesis. Meanwhile, the contact resistance of
these three kinds of nanotubes are also derived from the fitted linear curves. However,
due to the relatively small contact resistance between Pd electrodes and nanotube thin
film, and the lack of data points in the fitted curve (5 data points), we can only get rough
ranges of the contact resistances from the three kinds of SN-TFTs, which are 0-0.127
MΩ· μm for arc-discharge SN-TFTs, 0-2.96 MΩ· μm for HiPCO SN-TFTs, and 0-17.60
MΩ· μm for CoMoCAT SN-TFTs. From these values, one can find that larger diameter
nanotubes exhibit much smaller maximum contact resistance compared with smaller
125

diameter nanotubes, which can be explained by the bandgap difference of different
diameter nanotubes. As we know, the bandgap (E
g
) of nanotube is reversely proportional
to the diameter (d) of the nanotube, which can be written as E
g
= 2γ
o
a
c-c
/d, where γ
o
is the
C-C tight-binding overlap energy and a
c-c
is the nearest-neighbour C-C distance (0.142
nm). Based on literatures, γ
o
is around 2.7 eV [3,4], so we can derive that the bandgap
ranges for arc-discharge nanotube, HiPCO nanotube and CoMoCAT nanotube are
0.45-0.59 eV , 0.77-0.95 eV and 1.09 eV , respectively. Nanotubes with small bandgap,
whose diameter is large, are believed to have smaller Schottky barriers with metal
electrodes; therefore large diameter nanotubes can provide smaller contact resistance than
small diameter nanotubes. [29] Overall, we find that SN-TFTs using large diameter
nanotubes are superior to the ones using small diameter nanotubes in terms of channel
sheet resistance and contact resistance, which is also the reason that higher on-current
density is observed for devices fabricated with large diameter nanotubes.
Beside on-current density, the other important device parameter is current on/off ratio,
which is calculated and plotted in Figure 6.4c. From this plot, one can find that as the
channel length increases, the average on/off ratio of all three kinds of SN-TFTs increases,
which is due to the decrease in the probability of percolative transport through metallic
nanotube networks as the device channel length increases. It is worth noting that for
HiPCO and CoMoCAT SN-TFTs, we observe that the average on/off ratio decreases
slightly when the channel length is higher than 50 μm. This is because although the
on-current and off-current of the devices should decrease together when the channel
length increases, when the channel length is very long, the off-current of the devices will
126

stop decreasing once it reaches the noise level of the measurement equipment (Agilent
4156 B Semiconducting Parameter Analyzer with an accuracy of 1 pA). Therefore, we
see a slightly decrease of the on/off ratio for long channel devices.
In addition, from Figure 6.4c, we also observed that under the same channel length,
the on/off ratio of arc-discharge SN-TFTs is lower than the one of HiPCO and CoMoCAT
SN-TFTs, which means large diameter SN-TFTs have higher off-current compared with
small diameter SN-TFTs. There are two possible sources for the off-current, which are
the percolative transport through metallic nanotubes and the thermal excitation of carriers
through semiconducting nanotubes. [30] For short channel devices, the former source is
believed to be the main reason of the off-current as the channel length is comparable to
the length of nanotubes. On the other hand, when the channel length is much longer than
nanotubes length, based on the 2D stick model [31], the percolation threshold density (N)
can be expressed as the following equation:
2
)
236 . 4
(
1
l
N

 ,where l is the average
length of the nanotubes. If we take arc-discharge nanotubes as an example (l = 540 nm),
N can be calculated to be 20 tubes/ μm
2
. As only 2% of the separated arc-discharge
nanotubes are metallic, in order to form a metallic pathway for the long channel devices,
the totally nanotube density needs to reach 1000 tubes/ μm
2
, which is much higher than
the real nanotube density we measured above (32-41 tubes/μm
2
). Therefore, the
percolative transport through metallic nanotubes is negligible for long channel devices,
which suggests that the off-current mainly comes from the thermal excitation of carriers.
Benefited from their large bandgap, thermal excitation can be strongly suppressed for
small diameter SN-TFTs. However, for large diameter nanotubes, due to their narrow
127

bandgap, considerable amount of carriers can path through the channel to form a higher
off-current, which leads to lower on/off ratio compared with small diameter nanotube
devices.
The conclusion above is further supported by the results shown in Figure 6.4d, where
typical devices using three kinds of nanotubes with the same channel dimension (L = 50
μm, W = 1200 μm) are characterized. This plot shows us the on/off ratio of the
arc-discharge SN-TFTs decreases when source to drain voltage increases, while the ones
for HiPCO and CoMoCATs SN-TFTs remains the same under different drain biases. The
decrease of the on/off ratio for arc-discharge SN-TFTs is attributed to the fact that carriers
will gain more energy under a high source to drain bias, and therefore, more carriers will
be able to transport through the channel due to the thermal excitation, which will result in
a higher off-current and a lower on/off ratio. In contrary, the wide bandgap of HiPCO and
CoMoCAT semiconducting nanotubes can effectively suppress the thermal excitation
even under a high drain to source voltage, thus a constant on/off ratio is observed. This
phenomenon further proved that instead of percolative transport through metallic
nanotubes, thermal excitation is the main source of the off-current for long channel
SN-TFTs. This diameter dependent on/off ratio behaviour also suggests that small
diameter nanotubes are preferred for applications which need high biases, such as power
transistors.
Interestingly, the data shown in Figure 6.4a and c also reveal a trade-off between
drive-current and on/off ratio, both of which are key parameters for display applications.
On one hand, larger diameter nanotubes and shorter channel length can help to achieve
128

higher on-current density due to the small sheet resistance and contact resistance; on the
other hand, the narrow bandgap associated with large diameter nanotubes will give rise to
more thermal excitation, and shorter channel length can also increase the possibility of
percolative transport through metallic nanotubes, thus lead to higher off-current and
lower on/off ratio. The plot in Figure 6.4e clearly illustrated this trade-off. One of the
most promising applications of carbon nanotube thin-film transistors is AMOLED display
electronics, where current drive capability and on/off ratio are the most crucial merits.
Unlike liquid crystal display (LCD), where voltage controlled circuit is applied, current
controlled circuit is required for AMOLED displays, which means the current flow
through the driving transistors will directly go through the OLED pixels, and therefore,
decide the output light intensity of the OLED. Due to this reason, high current drive
capability is required for TFTs used in AMOLED displays to create enough light intensity
within a certain area. For 40 inch HDTV , in order to reach a brightness of 600 Cd/m
2
,
about 12 μA current need to be delivered to a pixel with an area of 153× 460 μm
2
, [32]
which means that, if two transistor control circuit is applied in each pixel, a minimum
current density of 0.00034 μA/μm
2
need to be satisfied for the driving transistors in the
circuitry. Besides driving current, on/off ratio is another crucial parameter for display
electronics. As progressive scanning is used in most of the display circuits nowadays,
each pixel will only be programmed for a very short time during one frame time. In order
to have a smooth picture, the switching transistors of each display pixel need to have high
enough on/off ratio to hold a constant light intensity. The larger the display, the higher
on/off ratio is needed, and based on literature [33], on/off ratio needs to reach 10
6
for 256
129

grayscale 1080P displays. From Figure 6.4e, we can find that for the three kinds of
SN-TFTs, if on/off ratio of 10
6
is required, the highest measured on-current density for
arc-discharge SN-TFTs is 0.17 μA/μm, which comes from a device with a channel length
of 20 μm, while the highest on-current density for HiPCO and CoMoCAT SN-TFTs is
0.11 μA/μm (L = 10 μm) and 0.014 μA/μm (L = 10 μm), respectively. In addition, if we
calculate the maximum on-current density per unit area, the value can be derived to be
0.0085 μA/μm
2
for arc-discharge SN-TFTs, 0.011 μA/μm
2
for HiPCO SN-TFTs, and
0.0014 μA/μm
2
for CoMoCAT SN-TFTs. One interesting finding is that although under
the same channel geometry, arc-discharge SN-TFTs exhibit about 5 times higher
on-current density than HiPCO SN-TFTs, these two kinds of SN-TFTs provide similar
maximum on-current density for devices with an on/off ratio higher than 10
6
, which is
due to the trade-off between on-current density and device on/off ratio. Overall, Based on
our analysis, all three kinds of SN-TFTs meet the basic requirements for transistors used
in AMOLED displays.
Besides the on-current density and on/off ratio, we have also characterized device
mobility (μ
device
) for all three kinds of SN-TFTs. Device mobility of the SN-TFTs is
extracted following the equation:
dm
device
D ox g D ox
dI g LL
V C W dV V C W
     ,
where L and W are the device channel length and width, V
D
= 1 V , and C
ox
is the gate
capacitance per unit area. Here, we use the parallel plate model to calculate the gate
capacitance as this method can directly reflect the relationship between on-current
130

density and device mobility. [21] The device mobility of three kinds of SN-TFTs is
plotted in Figure 6.4f. Among these three kinds of SN-TFTs, arc-discharge SN-TFTs
give the highest mobility, which is around 9 cm
2
/Vs. HiPCO and CoMoCAT SN-TFTs
show mobility around 3 cm
2
/Vs and 0.78 cm
2
/Vs, respectively. These data illustrates that
larger diameter nanotubes SN-TFTs provide higher mobility than small diameter
SN-TFTs, which is in consistent with the device sheet resistance and contact resistance
analysis we discussed above.
One important issue we want to point out is that although mobility is the key metric
for other thin-film transistor channel materials, it is not the best parameter to evaluate the
performance of carbon nanotube TFTs. The reason is that mobility can only directly
reflect the current drive capability, but cannot reveal the on/off ratio information of the
given transistors. It may not be a problem for other TFT channel materials, such as
amorphous silicon, polycrystalline silicon or metal oxide, because all those materials
have constant on/off ratio regardless of the channel geometry once their doping level or
element composition is fixed. However, due to the existence of metallic nanotube, carbon
nanotube TFTs exhibit a trade-off between on-current density and on/off ratio. Therefore,
it is not fair to evaluate the performance of nanotube TFTs by just compare the mobility,
which cannot reflect the on/off ratio difference between different transitors. One good
example is the comparison between arc-discharge and HiPCO SN-TFTs we discussed
above. Although arc-discharge SN-TFTs show about three times higher mobility than
HiPCO SN-TFTs, these two kinds of devices exhibit similar on-current density when the
device on/off ratio is required to be higher than 10
6
. For this reason, we think for carbon
131

nanotube TFTs, it is better to compare the maximum current drive capability under
certain on/off ratio requirement rather than compare the device mobility alone.
Arc-discharge
semiconducting
nanotube
HiPCO
semiconducting
nanotube
CoMoCAT
semiconducting
nanotube
Purity 98% 92% 95%
Diameter (nm) 1.3-1.7 0.8-1 ~0.7
Energy band(eV) 0.45-0.59 0.77-0.95 ~1.09
On-current density
when on/off ratio higher
than 10
6
( μA / μm)
0.17 0.11 0.014
Device Mobility
(cm
2
V
-1
S
-1
)
8.8± 0.27 3.0± 0.62 0.78± 0.067
Sheet resistance(M Ω / □ ) 0.28 3.28 6.46
Table 6.1 Key parameter comparison for separated nanotubes with different diameter

Based on the analysis above, we have found that different separated semiconducting
nanotubes exhibit different electrical properties. Table 6.1 summarizes all the differences
we have discussed so far for arc-discharge, HiPCO and CoMoCAT separated nanotubes,
including semiconducting nanotube purity, nanotube diameter, electrical bandgap, highest
on-current density for devices with on/off ratio higher than 10
6
, device mobility, and
channel sheet resistance. Overall, we find that large diameter nanotubes provide smaller
sheet resistance and contact resistance, which lead to higher transconductance and higher
device mobility. Hence, large diameter nanotubes have advantage in applications which
requires high carrier mobility, such as radio frequency circuits. In contrary, small
diameter nanotubes show higher on/off ratio and smaller off-current, which are preferred
132

for digital circuit applications, where on/off ratio and power consumption are big
concerns.
6.5 Comparison between gel-based and DGU based separated nanotube
In addition to the electrical performance comparison between different kinds of
gel-based separated semiconducting nanotubes, we are also very interested in the device
performance comparison between SN-TFTs using nanotubes separated by gel-based
column chromatography and the ones separated by other main stream nanotube
separation methods, especially density gradient ultra-centrifuge (DGU) method. To carry
out this comparison, we first compared the UV-Vis-NIR absorption spectra of
semiconducting arc-discharge nanotubes separated by DGU (blue) and gel-based column
chromatographic (red) methods, which are shown in Figure 6.5a. Here we choose 99%
separated semiconducting nanotubes purchased from Nanointegris Inc as standard DGU
separated nanotube sample. From this plot, one can find that very similar UV-Vis-NIR
absorption spectra was obtained for DGU-based and gel-based separated nanotubes,
which suggests that these two kinds of nanotubes shares similar purity as well as diameter
distribution. Starting with these two kinds of semiconducting nanotubes, we have
fabricated 120 SN-TFTs (each kind of nanotubes have 60 SN-TFTs) and compared their
performance. Figure 6.5b-d summarizes the statistic key parameters of the DGU-based
and gel-based arc-discharge SN-TFTs. The on-current density and on/off ratio
information can be found in Figure 6.5b and d, which reveal that DGU-based separated
SN-TFTs provides slightly higher on-current density than gel-based SN-TFTs, but lower
on/off ratio. This behaviour may due to the fact that DGU separated nanotubes have
133

Figure 6.5 Comparison of key device performance metrics of SN-TFTs using semiconducting arc-discharge nanotubes
separated by DGU and gel-based column chromatographic methods. (a) UV-Vis-NIR absorption spectra of
semiconducting arc-discharge nanotubes separated by DGU (blue) and gel-based column chromatographic (red)
methods. (b) Current density (I
on
/W) versus reversed channel length for TFTs fabricated on semiconducting nanotubes
separated by DGU (blue) and gel-based (red) methods. Plot of (b) average on/off ratio (I
on
/I
off
) and (c) device mobility
(μ
device
) versus channel length for the same devices measured in (b).
longer average length (~1 μm) than gel-based arc-discharge nanotubes (540 nm), which
leads to fewer nanotube to nanotube junctions and, therefore, lower sheet resistance but
higher possibility of metallic nanotube pass. Besides on-current and on/off, device
mobility is also studied in Figure 6.5d. Based on this figure, one can find that gel-based
arc-discharge SN-TFTs show slightly higher mobility than DGU-based SN-TFTs when
channel length is longer than 20 μm. Overall, although there are some small differences
134

between gel-based and DGU-based arc-discharge SN-TFTs, these two kinds of devices
provide similar electrical performance, which suggests that in terms of electrical property,
gel-based separated semiconducting nanotubes are comparable to DGU separated
semiconducting nanotubes.
6.6 Summary
In conclusion, we report our progress on gel-based column chromatographic
nanotube separation of different kinds of nanotubes and its application in
macroelectronics, including progress on the detailed analysis of key performance metrics
of devices using gel-based arc-discharge, HiPCO and CoMoCAT semiconducting
nanotubes, and direct comparison of the electrical property of gel-based and DGU-based
separated semiconducting nanotubes. We have revealed the diameter dependent
performance behaviour of SN-TFTs, and find that large diameter nanotubes are ideal for
applications requiring high mobility such as radio frequency transistors, while small
diameter nanotubes are preferred for applications like digital circuits, where on/off ratio
is more important. In addition, based on our analysis, gel-based SN-TFTs have satisfied
the requirement of large scale AMOLED high definition displays and can be a promising
candidate of the transistors used in next generation displays. Moreover, we have pointed
out that due to the trade-off between on-current density and on/off ratio for SN-TFTs,
instead of mobility, maximum on-current density for devices with on/off ratio above
certain threshold should be the main parameter to evaluate the electrical performance of
carbon nanotube thin-film transistors. Furthermore, we have carried out the comparison
between gel-based and DGU-based separated nanotubes, and found that both methods
135

can provide separated nanotubes with similar electrical performance. Our work represents
significant advance in the gel-based separated nanotube thin-film electronics, and may
provide guide to future research on SN-TFT based macroelectronics.

136

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139

Chapter 7: Conclusions and Future Directions

7.1 Conclusions
As a conclusion, this dissertation discussed the application of separated
semiconducting nanotube for scalable, practical, and high performance macroelectronics.
To overcome the main challenges of nanotube electronics, which are co-exist of metallic
and semiconducting nanotubes, and assembly of nanotubes, I have developed the
platform which is capable of providing thin-films of uniform, high-purity semiconducting
nanotubes at complete wafer-scale. In addition, many other essential analysis as well as
technology components, such as nanotube film density control, purity and diameter
dependent semiconducting nanotube electrical performance study, air-stable n-type
transistor fabrication, and CMOS integration platform have been demonstrated. On the
basis of the above achievement, I have further demonstrated various kinds of applications
including AMOLED display electronics, PMOS and CMOS logic circuits, flexible and
transparent electronics. Through experimental demonstration, this dissertation proves the
great potential and feasibility of carbon nanotube based macroelectronics.
7.2 Future directions on thin-film transistor based CMOS logic circuits
Due to the inherent advantage of flexibility and transparency, carbon nanotube
thin-film transistor based logic circuits have attracted a lot research effort. Circuits such
as 4-input decoders [1], 21-stages ring oscillators and master–slave delay flip-flops [2]
have been demonstrated on flexible substrate by other groups using nanotube thin-film
140

transistors. However, most of the previous reported circuits are based on PMOS only
circuit structures, which dramatically increase power consumption and limit the electrical
performance of the logic circuits. To solve these problems, CMOS structure logic circuit
is required and therefore, n-type transistors are needed. In chapter 4, I introduced a
technology to fabricate air-stable n-type nanotube transistors [3] and as a demonstration,
some basic CMOS integrated circuit, such as inverters, NAND and NOR gates have been
fabricated and characterized. Those circuits exhibit symmetric input and output behavior,
and rail-to-rail output have also been observed. In spite of the good performance, the
nanotube based CMOS integrated circuit platform involves relatively complicated
fabrication steps, multi-step nanotube deposition as well as different device structure for
p-type and n-type transistors are required. As a result, it is very hard to improve the yield
of the circuits, which is a major challenge when we want to fabricate more sophisticated
integrated circuits. Above all, how to fabricated n-type transistors with higher yield is the
key to solve this problem.
While the fabrication of nanotube based n-type transistor seem to be a bottleneck,
n-type transistor behavior can be easily achieved using other materials, such as metal
oxide thin-films. Therefore, in an alternative way, CMOS structure thin-film transistor
based circuits can be fabricated by hybridize p-type nanotube transistors with n-type
transistors made with metal oxide materials. To fulfill this task, one of the ideal metal
oxide materials is indium gallium zinc oxide (IGZO) [4,5], which exhibit similar mobility
as separated nanotube thin-film transistors (SN-TFTs) (~10-30 cm
2
/vs) and have good
transparency [6] and a certain flexibility [7].
141

0 3 6 9 12 15
0
5
10
15
20
25
30

Drain Current ( A )
Gate Voltage (V)
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4

Figure 7.1 IGZO n-type transistor performance. (a) Transfer characteristics in linear (red) and logarithm (blue) scales.
(b) Symmetric n-type (IGZO) and p-type (separated nanotube) transistors
Figure 7.1 exhibits the transfer characteristics of the typical IGZO n-type transistors.
These devices on fabricated on Si/SiO
2
substrate. Similar to nanotube devices, back gated
device structure are applied with highly doped Si serving as gate electrode and SiO
2
as
gate dielectric. IGZO thin-films are deposited by sputter and patterned by a standard
lift-off process. After that, Ti/Au electrodes are patterned as the source and drain of the
transistor. From the plot in Figure 7.1a, one can find that IGZO transistors exhibit n-type
behavior with on/off ratio higher than 10
5
. Meanwhile, very little hysteresis is observed
for IGZO transistors, which indicated that SiO
2
and IGZO thin-film are free of defects. In
addition, by choosing specific channel geometry for IGZO TFT and SN-TFTs, symmetric
transistor behavior can be achieved, which is shown in Figure 7.2b. These kinds of
transistors show very uniform behavior and high device yield, which can be a good
platform for TFT based CMOS integrated circuits.
On the basis of the symmetric n-type and p-type transistors, we can further obtain
integrated CMOS logic circuits. Figure 7.2 demonstrated some of the circuits we have
0 1 2 3 4 5
0
4
8
12
16
20
n-type IGZO TFTs
p-type SN-TFTs

Drain Current ( A )
Gate Voltage (V)
a b
142

fabricated so far. Figure 7.2a shows the voltage and current transfer characteristics of a
CMOS integrated inverter. Such inverter works with a V
DD
of 3 V , exhibits symmetric
input/output behavior as well as rail-to-rail output. The gain of this inverter is 14, which
is slightly higher than the inverter shown in chapter 4. Moreover, the current is zero when
the output reaches its boundary, which means that zero static power consumption is
achieved. Furthermore, benefitted from the symmetric n-type and p-type transistor
behavior, the threshold voltage of this invert is 1.5 V , which is exactly half of the
operation voltage. Based on the promising result of the CMOS inverter, a five stage ring
oscillator has been fabricated and the results are plotted in Figure 7.2b. This figure shows
that the ring oscillator works at 50 HZ and also exhibits rail-to-rail output.

Figure 7.2 Hybrid integrated CMOS logic circuits. (a) Voltage and current transfer characteristics of the integrated
CMOS inverter. (b) Output characteristics of a five stage ring oscillator. (c, d) Schematic and output characteristics of
the integrated CMOS XOR gate.
143

Beside inverter and ring oscillator, a more sophisticated integrated circuit, hybrid
CMOS XOR gate is designed and fabricated. This logic gate is also called as 2-bit half
adder which involves 12 transistors in total. The structure of the circuit is illustrated in
Figure 7.2c. The function of this gate is that when the two inputs are the same, the output
is “0”; otherwise the output is “1”. The output characteristics of this circuit are plotted in
Figure 7.2d, which confirms that our circuit is realizing the logic function correctly.
The above-discussed approach for integrated CMOS hybrid circuits is highly
scalable and reproducible. Some other circuits, such as NAND and NOR gates, decoders,
flip-flops, SRAM are under fabrication in our group. By combining all the circuits
together, we are planning to make a TFT based integrated central processing unit (CPU)
in the near future. Moreover, owing to flexibility of the materials and the low-temperature
compatibility of our platform, all the circuit can be made on flexible substrates, which
can lead to tremendous applications in future flexible electronics.
7.3 Future directions on SN-TFT based display electronics
Beside CMOS logic circuits, one of the most promising applications of SN-TFT is
display electronics. SN-TFT based active matrix organic light-emitting diode (AMOLED)
display elements have been demonstrated in chapter 3, which involves 500 OLED pixels
and 1000 SN-TFTs. This work proves that SN-TFT hold great potential for AMOLED
display electronics. However, several problems have also been revealed from this pioneer
work. One major problem is the pixel luminance uniformity, which can be clearly
observed in Figure 3.7e. The main cause of luminance non-uniformity is the variation of
pixel driving circuits. Two transistor one capacitor (2T1C) circuits are applied in this
144

work, which is also the standard circuit structure for liquid crystal display (LCD). The
schematic diagram of 2T1C circuit is shown in Figure 7.3a. 2T1C circuit is a voltage
programming circuit, which works well with LCDs because LCD is a voltage controlled
display. However, AMOLED is a current controlled display, meaning that the current
flow through the driving transistor will directly flow through the OLED pixel and
therefore determine the output light intensity. Therefore, any variation in the driving
transistors (T2) will be directly observed at the output light of the pixel. The difference
between LCD and AMOLED display is shown in Figure 7.3b and c. This transistor level
non-uniformity may be able to be improved by process refinements, but it is difficult to
reduce the variation across the array to a level necessary for good gray scale control.

Figure 7.3 (a) V oltage programming 2T1C circuit structure. (b, c) AMOLED (b) and LCD (c) display structure

Alternatively, the pixel luminance non-uniformity problem can be solved by applying
current programming pixel circuit. Previous reports [8-10] on polycrystalline silicon
based AMOLED displays prove that current programming pixel circuit can effectively
compensate the variation of the transistors and improve luminance uniformity. Figure 7.4
145

shows the improvement of luminance uniformity after using current programming circuit
achieved by Dawson and his co-workers[8].

Figure 7.4 Luminance uniformity improvement. (a) Luminance non-uniformity of the 2T1C pixel caused by variations
in the transistor output characteristics. (b) Improved pixel luminance uniformity using current programming circuit.
Compared with voltage programming circuits, which send specific voltage to the
gate of the driving transistor, current programming circuits can directly control the output
light intensity by sending a programmed current to the driving transistor and OLED pixel.
Therefore, current programming circuit can overcome any possible variations in the
driving transistors and improve the pixel luminance uniform.
Typical current programming circuits require more transistors than the 2T1C voltage
programming circuit. Usually, four transistors and one capacitor (4T1C) are needed.
Figure 7.5 shows three kinds of typical 4T1C circuits reported before [9,11,12] and their
corresponding layout designs. The basic idea of these kinds of 4T1C circuits can be
described as follows: When the pixel is selected, a programmed circuit, I
data
, will be
delivered to the OLED pixel directly or by a current mirror circuit. Meanwhile, the
capacitor will be charged up and provide a specific voltage to the load transistor. Once
the pixel is deselected, current flow through OLED will remain the same due to the
146

Figure 7.5 Typical 4T1C current programming circuits and their corresponding layout designs.
charges stored on the capacitor. Prototype SN-TFT based 4T1C display circuits are under
fabrication in our group and we are also working on integrate carbon nanotube based
AMOLED display circuits on flexible substrate. One can envision that the demonstration
of flexible AMOLED display would be a remarkable milestone in nanotube
macroelectronics.
147

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Abstract (if available)

Abstract In this dissertation, I discuss the application of carbon nanotubes in macroelectronics. Due to the extraordinary electrical properties such as high intrinsic carrier mobility and current-carrying capacity, single wall carbon nanotubes are very desirable for thin-film transistor (TFT) applications such as flat panel display, transparent electronics, as well as flexible and stretchable electronics. Compared with other popular channel material for TFTs, namely amorphous silicon, polycrystalline silicon and organic materials, nanotube thin-films have the advantages of low-temperature processing compatibility, transparency, and flexibility, as well as high device performance. ❧ In order to demonstrate scalable, practical carbon nanotube macroelectroncis, I have developed a platform to fabricate high-density, uniform separated nanotube based thin-film transistors. In addition, many other essential analysis as well as technology components, such as nanotube film density control, purity and diameter dependent semiconducting nanotube electrical performance study, air-stable n-type transistor fabrication, and CMOS integration platform have also been demonstrated. On the basis of the above achievement, I have further demonstrated various kinds of applications including AMOLED display electronics, PMOS and CMOS logic circuits, flexible and transparent electronics. ❧ The dissertation is structured as follows. First, chapter 1 gives a brief introduction to the electronic properties of carbon nanotubes, which serves as the background knowledge for the following chapters. In chapter 2, I will present our approach of fabricating wafer-scale uniform semiconducting carbon nanotube thin-film transistors and demonstrate their application in display electronics and logic circuits. Following that, more detailed information about carbon nanotube thin-film transistor based active matrix organic light-emitting diode (AMOLED) displays is discussed in chapter 3. And in chapter 4, a technology to fabricate air-stable n-type semiconducting nanotube thin-film transistor is developed and complementary metal–oxide–semiconductor (CMOS) logic circuits are demonstrated. Chapter 5 discusses the application of carbon nanotubes in transparent and flexible electronics. After that, in chapter 6, a simple and low cost nanotube separation method is introduced and the electrical performance of separated nanotubes with different diameter is studied. Finally, in chapter 7 a brief summary is drawn and some future research directions are proposed with preliminary results.

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Asset Metadata

Creator Zhang, Jialu (author)

Core Title Carbon nanotube macroelectronics

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 02/04/2013

Defense Date 01/22/2013

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag carbon nanotube,display electronics,flexible electronics,OAI-PMH Harvest,TFT,thin-film transistors,transparent electronics

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Zhou, Chongwu (committee chair), Cronin, Stephen B. (committee member), Thompson, Mark E. (committee member)

Creator Email jialuzh@gmail.com,jialuzha@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c3-218431

Unique identifier UC11292783

Identifier usctheses-c3-218431 (legacy record id)

Legacy Identifier etd-ZhangJialu-1425.pdf

Dmrecord 218431

Document Type Dissertation

Rights Zhang, Jialu

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA