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Mixed-signal integrated circuits for interference tolerance in wireless receivers and fast frequency hopping
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Mixed-signal integrated circuits for interference tolerance in wireless receivers and fast frequency hopping
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MIXED-SIGNAL INTEGRATED CIRCUITS FOR INTERFERENCE TOLERANCE IN WIRELESS RECEIVERS AND FAST FREQUENCY HOPPING by Sushil Subramanian A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulllment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) August 2017 Copyright 2017 Sushil Subramanian Dedication To Amma, Appa and Sudha ii Preface and Acknowledgements \To inquire and to create;|these are the grand centres around which all human pursuits revolve . . . " - Wilhelm von Humboldt 1 \You have a right to perform your prescribed duties, but you are not entitled to the fruits of your actions." - Srimad Bhagavad-Gita 2 This thesis summarizes work done over several years, and none of it would have been possible without the help, assistance, empathy and love of several individuals and organizations. My deepest gratitude goes to my academic advisor, mentor and Guru, Prof. Hossein Hashemi. Needless to say, Prof. Hashemi is and will remain my greatest professional in uence, and I will forever consider my work and research an exten- sion of his legacy. I have learnt a thousand lessons from his insight, wisdom and experience. He has always encouraged my ideas and thoughts, however crazy and amateur they may have been, and with his innite patience helped me nurture 1 from \Amelioration Of Morals," ch. VIII of The Limits of State Action, 1792. Translated from German by Joseph Coulthard, Jun. 2 ch. II, verse 47. Translated from Sanskrit by A.C. Bhaktivedanta Swami Prabhupada in his Bhagavad-Gita As It Is. iii them. As an uneducated researcher entering an unknown eld, a PhD student like myself could not ask for a better mentor than Prof. Hashemi. In many ways, both in and outside academia, I owe my current worldview to him. I am very grateful for the advice of my qualifying examination and defense committee members: Prof. Mike Shuo-Wei Chen, Prof. Peter Beerel, Prof. Urbashi Mitra, Prof. Paul Newton, Prof. Keith Chugg and Prof. Nestor Perez-Arancibia. I would especially like to thank Prof. Mike Shuo-Wei Chen for his mentoring throughout the course of my PhD. Being one of the foremost experts in mixed- signal design, his suggestions and comments have often been very critical to the success of my integrated circuit implementations. I would also like to thank Prof. Robert Scholtz; the work in this thesis is highly in uenced by many fundamental concepts I learnt from him during my edgling years. As is expected from any PhD student, I have spent an obscene amount of time in the oce and lab. And given that we are the sum total of the people around us, I am very grateful and honoured to have worked as a part of the best group of researchers one could associate with. First and foremost, I would like to thank my elder brother and best friend, Dr. Run Chen. It has been a privilege to have worked in the same oce as him for over six years, learning from his genius and watching him perform miracles in circuit design. He is a true virtuoso of electrical engineering and a wonderful teacher, and as a novice circuit designer I have learnt much of my trade from him. iv The company and counsel of my group seniors, I will forever cherish. Masashi Yamagata, Dr. Jonathan Roderick, Dr. Ankush Goel: apart from being a great friend over the past years, his academic work has been my golden standard and his research philosophy has in uenced me more than any other of my colleagues, Prof. Ta-Shun Chu, Dr. Zahra Safarian, Prof. Firooz A atouni: my senior ocemate and primary mentor, and Dr. Alireza Imani. While I did not overlap in time with Prof. Harish Krishnaswamy in the group, I sincerely acknowledge the in uence his academic work at USC has had on my research philosophy. I am very grateful for the friendship of my dear group mates Dr. Hooman Abediasl, my good friend of many memorable conversations Dr. Kunal Datta, my cherished oce companion Pingyue Song, Aria Samiei, Samer Idres, Fatemeh Rezaeifar, Chenliang Du, Shirin Vakilian, Timothy Mercer, Dr. Hongrui Wang, Dr. SungWon Chung, Dr. SangHyun Chang, Dr. Behnam Analui, Sam Mandegaran, Yibo Ronald Yin, Tie Yi, Matt Clark and Dr. Marcelo Segura. I would also like to thank my friends in Prof. Mike Shuo-Wei Chen's group: Jae-won Nam, Shiyu Su, Cheng-Ru Ho, Tzu-Fan Wu, Aoyang Zhang, Mohsen Hassanpourghadi, Praveen Kumar Sharma and Tui Tsai. The PhD in integrated circuit design entails the tapeout, a soul-searching process that tests one's mental and physical strength. Chenliang Du, Jae-won Nam and Aoyang Zhang were fellow travelers during my tapeouts, and our joint suering has only brought us closer. I am also especially v thankful to Yibo Ronald Yin and Run Chen for helping me navigate the basics of digital and analog design respectively. I am deeply indebted to Kim Reid, Diana Vuong, Elizabeth Castaneda, Lau- ren Villareal, Jaime Zelada, Diane Demetras, Sunny Bhalla and Ligia for their assistance. Their patience and timely help eased a lot of hurdles during the PhD process. The research detailed in this thesis was funded by the DARPA RF-FPGA program and the ONR Electronic Warfare Discovery and Invention Program. My education at USC was also signicantly sponsored by the USC Annenberg Graduate Fellowship Program. I am very grateful to the above institutions. An internship at Qualcomm Inc. in the summer of 2015 under Dr. Babak Vakili-Amini and Dr. Emanuele Lopelli helped me understand research in the context of the semiconduc- tor industry, and I thank them for their kind mentorship. Several friends and comrades have been great sources of happiness and reser- voirs of consolation in worrisome times. I thank my roommates, Lakshmi Kumar Dabbiru, Sunil Yeshwanth, Praveen Kumar Sharma, Tanner Sorensen, Alan Chen and in particular Naveen Kumar and Sandeep Acharya for their wonderful friend- ship over the years. My friends at USC, too numerous to mention yet I hope they understand I think of them as I write, have all given me amazing support and en- couragement during the PhD process. I am very grateful to Carol Dales and fellow musicians at Long Beach for their enduring friendship and providing me with an opportunity to publicly express the pianist in me. I thank my teammates at USC vi Marathon for the great times while helping me run several marathons, something I could have never imagined doing earlier. Friends and relatives from times past have always been willing to listen and converse whenever we met. I owe everything in my life to my parents, Subramanian M.V. (Appa) and Sundari Subramanian (Amma). Apart from being the foundation upon which I stand to view my universe, their encouragement and support has brought me thus far and will take me ahead in the future. All my actions, work and achievements are intended to honour them, for they are my religion and it is their pride I seek the most. Needless to say, this PhD is more a result of their hard work than mine. My dear sister and best friend in the whole wide world Sugandha Subramanian (Sudha), knows me better than anyone else. Her radiant positivity and her kind words in times of struggle are my primary medicine. To these three individuals, I dedicate my thesis. vii Table of Contents Dedication ii Preface and Acknowledgements iii List Of Tables xi List Of Figures xii List of Abbreviations xxiv Abstract xxvi 1: Introduction 1 1.1 Interference Tolerance in Wireless Receivers . . . . . . . . . . . . . 1 1.2 Fast Frequency Hopping . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 Summary of Results and Thesis Outline . . . . . . . . . . . . . . . 10 2: Joint Signal Conditioning and Quantization 13 2.1 Motivating the Filtering-ADC . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 Power Benets from Filtering . . . . . . . . . . . . . . . . . 13 2.1.2 Prior Filtering for Carrier Aggregation . . . . . . . . . . . . 17 2.2 Signal Structure and Conditioning . . . . . . . . . . . . . . . . . . . 19 2.2.1 Signal Conditioning by the Simple Dierence Filter . . . . . 20 2.2.2 Signal Conditioning given Signal Structure . . . . . . . . . . 21 2.2.3 Extension to Power Spectral Density . . . . . . . . . . . . . 26 2.2.4 Carrier Aggregation . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 Recongurable Signal Dependent ADC . . . . . . . . . . . . . . . . 30 2.3.1 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.2 DPCM, Recongurability, and Comparisons with Modu- lation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4 Behavioural Simulation and Implementation Challenges . . . . . . . 43 2.4.1 Error Analysis and Simulations . . . . . . . . . . . . . . . . 43 2.4.2 Implementation Challenges . . . . . . . . . . . . . . . . . . . 47 2.5 Feedforward Equalization Architecture . . . . . . . . . . . . . . . . 50 viii 2.5.1 Discrete-time Filtering and Equalization . . . . . . . . . . . 53 2.5.2 Practical Considerations . . . . . . . . . . . . . . . . . . . . 57 2.5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.6 A 200 MSPS Blocker Resilient ADC . . . . . . . . . . . . . . . . . . 61 2.6.1 Lossy Dierentiator and Variable Gain Amplier . . . . . . 63 2.6.2 Noise-Shaping ADC . . . . . . . . . . . . . . . . . . . . . . 67 2.7 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3: Semi-Digital IIR Filters for RF Channel Selection 81 3.1 Channel Selection at RF . . . . . . . . . . . . . . . . . . . . . . . . 81 3.1.1 Eliminating Analog Filters . . . . . . . . . . . . . . . . . . . 84 3.1.2 Semi-Digital IIR Filter Interpretation . . . . . . . . . . . . . 89 3.2 CT Receiver with Semi-Digital IIR STF . . . . . . . . . . . . . 96 3.2.1 Extension to Multiple Orders . . . . . . . . . . . . . . . . . 100 3.2.2 Direct Quantizing Receivers in Literature . . . . . . . . . . . 103 3.3 Quantizing Receiver Design . . . . . . . . . . . . . . . . . . . . . . 104 3.3.1 Compensation for Quantization Noise Amplication . . . . . 107 3.3.2 Receiver Budgeting . . . . . . . . . . . . . . . . . . . . . . . 111 3.4 Details of Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.4.1 Lossy Noise-Shaping ADC . . . . . . . . . . . . . . . . . . . 115 3.4.2 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.4.3 Feedback DAC . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.4.4 LNTA Design and Analysis . . . . . . . . . . . . . . . . . . 120 3.4.5 RF Passive Mixer and Clock Generation . . . . . . . . . . . 123 3.5 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.5.1 Small Signal Response . . . . . . . . . . . . . . . . . . . . . 126 3.5.2 Nonlinearity Tests . . . . . . . . . . . . . . . . . . . . . . . 130 3.5.3 Communication Tests . . . . . . . . . . . . . . . . . . . . . . 134 3.5.4 Power Consumption and Energy Eciency . . . . . . . . . . 136 3.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4: Rapid Hopping Digital Frequency Synthesis 140 4.1 Fast Frequency Hopping Clocks . . . . . . . . . . . . . . . . . . . . 140 4.2 Limitations of Conventional Architectures . . . . . . . . . . . . . . 142 4.2.1 Closed-Loop and Phase Synchronization Techniques . . . . . 143 4.2.2 Open-Loop and Phase Division Techniques . . . . . . . . . . 146 4.3 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.4 Theoretical Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.4.1 Sine-Weighted DDFS-DAC Operation . . . . . . . . . . . . . 155 4.4.2 DAC Construction . . . . . . . . . . . . . . . . . . . . . . . 162 4.5 Details of Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . 167 4.5.1 Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . 167 ix 4.5.2 13-Bit Sine-Weighted DAC . . . . . . . . . . . . . . . . . . . 169 4.5.3 Image Spur Rejection OTA-RC Filter . . . . . . . . . . . . . 171 4.6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . 174 4.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5: Conclusions 184 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . 186 References 188 Appendix A: OTA-RC Filter SNDR Limit 197 Appendix B: Discrete-Time Filtering and Quantization 199 B.1 Discrete-Time Filtered Signals . . . . . . . . . . . . . . . . . . . . . 199 B.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Appendix C: Signal Energy Distributions 204 C.1 Denitions and Periodization . . . . . . . . . . . . . . . . . . . . . 204 C.2 AM and FM Signals with IdenticaljX(f)j . . . . . . . . . . . . . . 207 C.3 Filter Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 C.4 Channelization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Appendix D: Output Noise of Lossy Dierentiator 211 x List Of Tables 2.1 Comparisons with Filtering-ADCs in Literature . . . . . . . . . . . 79 3.1 Design Parameters for Low-Power Receiver . . . . . . . . . . . . . . 114 3.2 Comparisons with Selected Direct CT Receivers . . . . . . . . . 137 3.3 Comparisons with Selected Low-Power Receivers . . . . . . . . . . . 138 4.1 Performance Comparison with DDFS-DAC Designs in Literature . . 182 xi List Of Figures 1.1 Representative input scenarios in a modern wireless receiver. . . . . 3 1.2 The software radio replaces the channel selection lter and the fre- quency shifting functionality from a typical transceiver shown in (a) to a direct front-end wideband, high dynamic range data convert- ers shown in (b), where frequency shifting and channel selection are performed digitally. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 The function of the SDR: (a) Today's multi-standard radio with tunable RF, IF and baseband blocks. (b) The SDR replaces the xed front end lter, LNA and the mixer with a programmable, recongurable analog processor that performs an equivalent function. 5 1.4 The programmable, recongurable ltering-ADC replaces the base- band lter, amplier and ADC for a power ecient solution. . . . . 6 1.5 A separate baseband path to lter and quantize in order to recover a desired channel. The question is whether more power ecient systems can be built. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.6 Replacing the baseband section of the receiver with the ltering- ADC gives the architecture shown in (a). (b) shows a conceptual where certains blocker in the front-end SDR can be combined with the ltering-ADC to provide for a synergic energy ecient receiver. 9 1.7 Applications considered in thesis: (a) ltering-ADC for carrier ag- gregation, (b) low power band and channel selecting receivers, and (c) fast frequency hopping synthesizers for electronic warfare. . . . 10 2.1 The simulation model for estimating the power budget for the base- band section of the communication system. . . . . . . . . . . . . . . 15 xii 2.2 Simulation results show that for a given dynamic range, the power consumption of the baseband reduces signicantly with higher order ltering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Conventional techniques may be used to quantize a multi-channel signal: (a) a high-dynamic range ADC (b) analog ltering in the front-end and then an ADC with a relaxed dynamic range . . . . . 18 2.4 A signal of limited slope being sampled using rate T s;1 and half the rateT s;2 . Due to the slope limitation (i.e., due to limited bandwidth of the signal), the resultant voltage dierences of samples re ect the sampling rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 Conceptual illustration of signal dependent quantization: Since dif- ferentiation causes signicant reduction in the full scale range of a bandlimited signal, the gainG can bring back the signal to full-scale. After this process, a quantizer is used to map the signal into quan- tization levels (in this case, 4 levels). Integration will then result in levels stacking on top of each other, thus increasing the overall resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 Filtering and gain boosting in the time domain and frequency domain. 22 2.7 Specic examples of maximum swing at the output of discrete-time lters: (a) Low-pass signal and dierentiator lter (b) Bandpass sig- nal and bandpass notch centred at f s =4. . . . . . . . . . . . . . . . 24 2.8 A lowpass signal of bandwidth B is sampled using a frequency f s = 2NB. The dierence of consecutive samples varies with the oversam- pling ratio N. (a) When N = 1, the maximum dierence spans the full scale range of a sinusoidal waveform of frequency B. (b) When N > 1, the maximum dierence occurs around the zero crossing of the same sinusoidal waveform. . . . . . . . . . . . . . . . . . . . . . 24 2.9 Oversampling, ltering and quantization using a general lter H(z) and its inverse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.10 Two dierent waveforms with dierent amplitudes, but the same power spectral density. (a) Amplitude of FM signal is 4.72 mV, (b) Amplitude of AM signal is 94 mV, (c) PSD of both waveforms measured using a spectrum analyzer, (d) FFT of both waveforms simulated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 xiii 2.11 A general signal dependent oversampled ADC with feedback. . . . . 32 2.12 DPCM and delta modulation are special cases of the general ADC architecture. In this case, H(z) is a simple dierentiator, and the loop lter is an integrator after the quantizer. The feedback lter 1=G, can be physically incorporated in the DAC. Both G and 1=G are variable, depending on N. . . . . . . . . . . . . . . . . . . . . . 34 2.13 An interesting recent implementation of delta modulation is the use of a Ring-VCO based quantizer. Using this quantizer in the delta modulation loop (Fig. 2.12), gives a digital PLL. Therefore, this dig- ital PLL can also be interpreted as a special case of delta modulation. 34 2.14 First order - ADC with signal and noise transfer functions. . . . 36 2.15 A comparison of the total noiseN e vs. oversampling ratioN for rst order delta modulation and modulation. It is shown that the noise rolls o as 1=N 3 for both architectures, with a nite 4.77 dB dierence asymptotically. . . . . . . . . . . . . . . . . . . . . . . . . 38 2.16 A comparison of the total noise N e vs. number of equi-power chan- nels R for rst order delta modulation and - modulation. Over- sampling ratio, N = 40. The modulator always considers noise in the entire bandwidth. However, depending on the maximum out- put of the dierentiator, delta modulation can adapt to changing channel allotments. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.17 The diagram shows two possible energy distributions. modula- tion produces the same noise shape for either energy distribution. However, the proposed ADC is sensitive to the maximum signal swing and therefore can potentially give a lower noise oor depend- ing on the signal energy distribution. Therefore, case (b) can have better performance than case (a). . . . . . . . . . . . . . . . . . . . 42 2.18 A second order delta modulator with forward equalization lterH(z) and feedback lter H fb (z). . . . . . . . . . . . . . . . . . . . . . . . 43 2.19 Error model for a second order DPCM ADC. . . . . . . . . . . . . . 44 xiv 2.20 Behavioural simulations for the ADC in Fig. 2.18 to characterize individual nonidealities: (a) Eect of ADC comparator oset in LSB on SNDR (100 iterations), (b) Eect of DAC mismatch in bits on SNDR (100 iterations), (c) Eect of gain error on SNDR. Spectra were estimated for a 100 s time window, after Blackman-Harris windowing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.21 Behavioural simulation of the scheme in Fig. 2.18 (100 iterations each): (a) A single-tone test (b) Three-channel scenario where the tone in either of the channels 1, 2 or 3 is 40 dB larger compared with the other two. SNDR per channel improves considerably for the low-energy signals of Case 1. . . . . . . . . . . . . . . . . . . . . 47 2.22 A switching scheme for the feedback DAC, to change between modes 1 and 2 having gains G 1 and G 2 respectively, where 2G 1 = G 2 . Changing to mode 1 decreases the number of bits by 1. The switching scheme ties together two unit elements (say, current sources) going from mode 2 to mode 1, maintaining the same full scale output, however with lower resolution. Accordingly, even index data signals are disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.23 Blocker tolerant ADCs reported in literature. . . . . . . . . . . . . . 52 2.24 Details of the proposed architecture. . . . . . . . . . . . . . . . . . 53 2.25 Signal model for the calculation of G. A i is the full scale range of the individual channel spanning (f i1 ;f i ). . . . . . . . . . . . . . . . 55 2.26 Two cases of NTF, H e (z), for signals with one high-energy channel. (a)H e (z) is at, (b)H e (z) notches at frequency of high-energy channel. 56 2.27 (a) Complex lter with variable for frequency-arbitrary notch. (b) Switched capacitor input impedance. . . . . . . . . . . . . . . . . . 58 2.28 Details of the proof-of-concept 200 MSPS ltering-ADC implemen- tation based on the proposed architecture. . . . . . . . . . . . . . . 61 2.29 Top-level block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 63 2.30 (a) Lossy dierentiator and variable gain amplication, (b) Opera- tional amplier, (c) AC response of op-amp, (d) Input refered noise of op-amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 xv 2.31 (a) Change in STF with . (b) Change in M e with . . . . . . 65 2.32 Input bootstrap network that shares large bootstrap capacitor for all paths to save area. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.33 (a) The noise shaping pipeline ADC uses two MDACs and a 4-bit Flash ADC, with residue feedback. (b) Since residue calculation for MDAC1 and MDAC2 takes place in alternate clock phases, the op- amp can be shared to save power. (c) Model for the ADC. . . . . . 67 2.34 (a) Op-amp schematic, (b) AC response, and (c) Input-refered noise. 68 2.35 Functional model of the system with nonidealities included. . . . . . 68 2.36 (a) Comparator schematic. The input transistors are scaled for the Flash ADC, but the schematic is identical; (b) Current-steering DAC unit cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.37 (a) Behavioural simulation results; (b) Transient noise schematic simulation results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.38 Chip photograph. The active area is 0.55 mm 2 . . . . . . . . . . . . 73 2.39 Small signal measurements for dierentiator transfer function show <1 dB deviation from an ideal 1:1z 1 . . . . . . . . . . . . . . . . 74 2.40 The ADC characterized for Nyquist performance: (a) Spectrum with 99 MHz input, (b) SNDR and SFDR versus input frequency. . . . . 75 2.41 (a) Output spectrum (averaged 10 times) in the mode for a 6 MHz bandwidth, with signal at 0.5 MHz. (b) SNR/SNDR versus input amplitude for a 6 MHz bandwidth. . . . . . . . . . . . . . . . 75 2.42 Measured SNDR in the channelized mode versus the frequency of the low-energy tone, X 2 . (a) The total SNDR, when both channels are desired; (b) SNDR of low-energy signal X 2 only, if X 1 is considered a high-energy blocker. . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.43 (a) Output spectrum with low-energy signal at 3.26 MHz (oset of 260 KHz). Results here show that the ADC is capable of full signal recovery after equalization; (b) Output spectrum with low-energy signal at highest frequency, the worst-case. . . . . . . . . . . . . . . 78 xvi 3.1 Impedance upconversion in the SDR: (a) conventional receiver with front-end lter. (b) Removing the front-end lter and using an LNTA instead of the LNA allows for current mode operation at the output of the LNTA. The baseband TIA impedance is then frequency up- converted to appear at the output of the LNTA, thereby ltering the swing due to out-of-band interferers at RF. . . . . . . . . . . . . . . 82 3.2 Replacing the SDR baseband with the conceptual ltering-ADC for channel selection, amplication of desired signal and quantization. . 83 3.3 (a) Replacing the receiver baseband with the ltering-ADC architec- ture discussed in Chapter 2 (Fig. 2.11), (b) translating the baseband impedance to RF using a passive mixer. . . . . . . . . . . . . . . . 85 3.4 Model of the receiver in Fig. 3.3b. . . . . . . . . . . . . . . . . . . . 85 3.5 Summary of proposed receiver architecture. Both band selection and channel selection analog lters are eliminated and accommodated for by the SDR and ltering-ADC techniques. . . . . . . . . . . . . . . 88 3.6 Digital IIR lters with only feedback coecients. The simulation results are shown for lters order N = 1; 2; 3. . . . . . . . . . . . . 91 3.7 Constructing the IIR lter with only feedback coecients: (a) Simple construction showing three coecients. (b) Construction with the representation of H(z), an FIR lter. . . . . . . . . . . . . . . . . . 92 3.8 Transforming the digital IIR lter to a mixed-signal IIR lter, with the introduction of a quantizer. . . . . . . . . . . . . . . . . . . . . 92 3.9 A current mode mixed-signal IIR lter. . . . . . . . . . . . . . . . . 94 3.10 A nal transformation of the current mode mixed-signal IIR lter introduces a passive mixer to make the control system identical to the one introduced in Fig. 3.5. . . . . . . . . . . . . . . . . . . . . . 94 3.11 The feedback lter and DAC can be implemented together as an FIR DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.12 The ADC is replaced with a ADC to give a CT . . . . . . . 96 xvii 3.13 Model for current mode, rst order CT ADC with NRZ feedback DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.14 Model for a generalized DT ADC with both feedforward and feedback lters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.15 Toplevel schematic of the receiver. . . . . . . . . . . . . . . . . . . . 105 3.16 STF and NTF of behavioral model of receiver simulated in Cadence. 106 3.17 Modifying the quantizer in the proposed architecture to include a delay-free loop with integrator, changes the quantization noise trans- fer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.18 Implementation of delay-free lossy noise shaping ADC. . . . . . . . 108 3.19 NTF of behavioral model of receiver simulated in Cadence, with and without additional noise shaping loop to compensate for unnecessary quantization noise amplication. . . . . . . . . . . . . . . . . . . . . 111 3.20 Complete receiver with noise-shaping ADC and other important blocks.112 3.21 Detailed schematic of the lossy noisy shaping ADC with the com- parator and loop lter op-amp schematics included. . . . . . . . . . 117 3.22 Detailed schematic of the integrator op-amp with the feedback ca- pacitorsC included. The dierential pair op-amp has a current con- sumption of 636 A. . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.23 Detailed schematic of the feedback FIR lter DAC in the I branch. 119 3.24 Inverters used for the LNTA in the receiver. . . . . . . . . . . . . . 120 3.25 Simplied front-end model for NF calculations. . . . . . . . . . . . . 121 3.26 Schematic simulations of gain and NTF (PSS+PAC), and noise gure (PSS+PNOISE) of the receiver, with real LNTA schematic. . . . . . 122 3.27 Schematic of synchronous divide-by-4 and buers with level shifters. 124 3.28 Chip photograph. The chip was implemented in a 65 nm CMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 xviii 3.29 S-parameter measurement results of the o-chip balun, performed in a back-to-back conguration. . . . . . . . . . . . . . . . . . . . . . . 126 3.30 Conversion gain of the receiver: (a) conversion gain across the center frequency range (f RF ) of interest, (b) conversion gain with respect to frequency oset at f RF = 2:07 GHz, in comparison with normalized ideal simulation results. . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.31 Wideband signal transfer function measurements shown the notches created at multiples of f s that create the band selection transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.32 Noise gure vs. RF center frequency. The results are lower than the 16 dB design requirement. . . . . . . . . . . . . . . . . . . . . . . . 129 3.33 In-channel IIP3, out-of-channel IIP3 and input referred 1 dB gain compression point measurement results. . . . . . . . . . . . . . . . . 130 3.34 Blocker power for CP1dB in the presence of blocker and blocker power for SNDR degradation by 3 dB, for varying blocker osets. Plots shown for f RF = 0.64 GHz and 2.51 GHz. . . . . . . . . . . . 131 3.35 SNDR measurements with input power show a dynamic range of 50 dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.36 Output spectrum at f RF = 2.51 GHz. (a) Output spectrum in the absence of blocker signal. (b) Output spectrum in the presence of a blocker with 10x power at 89.55 MHz. The input signal is at 1.56 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 3.37 8-PSK measurement results (a) EVM and SNR vs. RF input power. (b) EVM in the presence of a blocker at input power of -50 dBm, with center frequency of 2.51 GHz. (c) Example constellation diagram (0.64 GHz, -50 dBm). (d) Example constellation diagram (2.51 GHz, -50 dBm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.38 16-QAM measurement results: (a) Example constellation diagram (0.64 GHz, -45 dBm). (b) Example constellation diagram (2.51 GHz, -45 dBm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.39 Power consumption and energy eciency as a function of the center frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 xix 4.1 Four applications where fast frequency hopping clocks are essential: (a) Fast sweeping spectrum analyzers, (b) wideband OFDM UWB communications, (c) secure communications using data encoded as fast hopping frequency sequences, and (d) electronic warfare appli- cations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.2 Two techniques to create fast-hopping, high resolution wideband fre- quencies: (a) Using feedback with a clock reference and (b) feedfor- ward with a control voltage reference. . . . . . . . . . . . . . . . . . 143 4.3 Phase synchronization for fast frequency hopping: (a) use of Phase- Locked Loop; (b) use of multipliers with injection locking. . . . . . 144 4.4 Open-loop for fast frequency hopping: (a) direct control of an inte- grated oscillator using a precise controlling voltage; (b) using division mechanisms such as the direct-digital frequency synthesizer. . . . . 147 4.5 The trade-os between various architectures for fast frequency hop- ping. (a) The architectures can be classied as closed-loop, phase synchronizing or open-loop, phase division, each category with dis- tinct advantages and disadvantages. (b) A general plot shows the tradeos between architectures in important metrics. . . . . . . . . 149 4.6 (a) Replacing the xed crystal reference with a high resolution, fast hopping synthesizer would resolve the frequency resolution issue. (b) Simplied proposed frequency sythesizer architecture. . . . . . . . . 150 4.7 Details of the architecture with the relative contribution of each block to the power consumption, SFDR and hopping time. For further rejection of unwanted harmonics, two stages of locking are used. An image spur rejection lter after the DAC and harmonic rejection lter after the mixer are also required. . . . . . . . . . . . . . . . . 152 4.8 Model for injection locking, with injecting current of reference oscil- lator and feedback model for the output oscillator. . . . . . . . . . . 153 4.9 Results of simulation of injection locking process: (a) Output spec- trum to validate the locked spectrum. (b) A hop between two fre- quencies at the GHz range takes a few nanoseconds of time to settle. 154 4.10 Typical DDFS architecture consisting of accumulator, phase-to-sine conversion and DAC. An additional lter removes the image spurs. 156 xx 4.11 Signal path characteristics for the DDFS. The total allowable latency for the phase-to-sine conversion unit is only 15 ns, assuming that the total latency allowed is 25 ns, including the lter. This conversion time has to apply for an SFDR of 50 dB. The power consumption also has to be as low as possible. . . . . . . . . . . . . . . . . . . . 157 4.12 Using a sine-weighted DAC instead of a linear DAC can produce si- nusoidal outputs while replacing the state-machine based algorithm section of the digital circuits to a simple binary-to-thermometer con- verter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4.13 DDFS output waveforms are repetitive for four quadrants, and can be replicated by mirroring the output across =2 and , i.e. the x-axis and y-axis every 2 total phase. After wrapping the phase every =2, the DDFS output phase can be further divided into two parts, each generating the outputs only for =4 using the sine and cosine DACs. These waveforms can be swapped again, thus saving DAC area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.14 Simulations for the compressed DDFS-DAC shows that the SFDR does not improve after a certain value of M 13. . . . . . . . . . . 160 4.15 The current source weights for the coarse DAC are determined by splitting the DAC into a 1616 current grid and calculating the steps based on an index. The ne DAC is then used for extrapolating the coarse DAC current sources. . . . . . . . . . . . . . . . . . . . . . . 162 4.16 At time indexn = 1, current sources till (Row 2, Col. 15) are turned on. At n = 2, additional sources turn on till (Row 4, Col. 14) and increasing the amplitude. This process continues till = =4. The weights of current sources transfer the sin() slope to enable phase- to-sine conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.17 After waveform generation, additional amplitude raising DACs bring the signal to full scale. Swapping switches before the load generate the full quadrature output. . . . . . . . . . . . . . . . . . . . . . . . 165 4.18 Introducing the sine-weighted DDFS-DAC architecture has elimi- nated the latency that is produced by the phase-to-sine algorithm. . 166 4.19 Detailed schematic of the digital section. . . . . . . . . . . . . . . . 168 xxi 4.20 Layout of the digital section. . . . . . . . . . . . . . . . . . . . . . . 169 4.21 (a) Details of the unit current source used for the DAC. Tha layout is performed in a common centroid manner for the current sources which are connected remotely to switches located close to the DDFS output. (b) The dierential switch layout (M3 and M4) with dummy switches (M1 and M2) and inverter buers (B1 and B2). . . . . . . 171 4.22 At most frequencies, rows turns on more often than columns. To reduce systematic errors, column-sets are laid-out common centroid, and each set is also common centroid within (example shown for Column 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.23 Details of the 6th Order OTA-RC Chebychev lter schematic. . . . 173 4.24 Chip photograph and summary of measurement results. . . . . . . . 174 4.25 Image spur rejection lter results: (a) Small signal lter transfer function across various gain control settings. (b) IIP2 and IIP3 of lter across the frequency of operation. . . . . . . . . . . . . . . . . 175 4.26 DDFS-DAC with Filter measurement results: (a) SFDR of the sys- tem with clock at 800 MHz and varying input frequency. (b) SFDR of the system with varying clock frequency and f in at 1/16th of the clock frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 4.27 Simulations of the schematics with non-zero mismatch at the swap- ping switches shows that the quadrature waveform can be aected severely due to these large transistors. The result is a reduction in the SFDR performance. . . . . . . . . . . . . . . . . . . . . . . . . 177 4.28 Measured output spectrum at (a) 66 MHz, (b) 180 MHz output. . . 178 4.29 System hopping performance result: (a) A single frequency hop from 100 MHz to 50 MHz shows a hopping time of less than 15 ns. (b) Of this 15 ns, 10 ns comes from the latency, implying 5 ns should be the total analog delay. This result is shown in the plot of the instantaneous frequency versus time. . . . . . . . . . . . . . . . . . 179 4.30 Rapid frequency hopping from 100 MHz! 50 MHz! 100 MHz! 200 MHz, with 25 ns spent on each frequency. . . . . . . . . . . . . 180 xxii 4.31 Added phase noise measurements with the output at 100 MHz. . . . 180 A.1 Model for single stage OTA-RC lter. . . . . . . . . . . . . . . . . . 198 D.1 (a) Model of dierentiator in alternating clock phases for calculation of noise requirements. (b) Dierentiator output noise PSD; analysis versus schematic simulation for parameters chosen in implementation.213 xxiii List of Abbreviations ADC Analog to Digital Converter BER Bit Error Rate CMOS Complementary Metal-Oxide-Semiconductor CMRR Common Mode Rejection Ratio CORDIC COordinate Rotation DIgital Computer CT Continuous-Time DAC Digital to Analog Converter DDFS Direct Digital Frequency Synthesizer DDS Direct Digital Synthesis DFF Delay Flip-Flop DPCM Dierential Pulse Coded Modulation DT Discrete-Time ENOB Eective Number Of Bits FIR Finite Impulse-Response FOM Figure Of Merit GBW Gain-Bandwidth Product IIP2 Input second-order intercept point IIP3 Input third-order intercept point IIR Innite Impulse-Response xxiv IoT Internet of Things ISI Inter-Symbol Interference ISM Industrial Scientic and Medical LNA Low Noise Amplier LNTA Low Noise Transconductance Amplier LSB Least Signicant Bit MASH Multi-Stage Noise Shaping MDAC Multiplying Digital to Analog Converter NF Noise Figure NRZ Non-Return-to-Zero NTF Noise Transfer Function OFDM Orthogonal Frequency-Division Multiplexing PLL Phase-Locked Loop PSD Power Spectral Density ROM Read-Only Memory SAR Successive Approximation Register SDR Software-Dened Radio SFDR Spurious Free Dynamic Range SNDR Signal to Noise and Distortion Ratio SNR Signal to Noise Ratio SQNR Signal to Quantization Noise Ratio STF Signal Transfer Function TIA Trans-Impedance Amplier UWB Ultra-WideBand VCO Voltage-Controlled Oscillator VGA Variable Gain Amplier xxv Abstract Modern wireless communication systems require low power integrated circuit im- plementations of radio receivers that simultaneously oer programmability and re- congurability in order to cover various communication standards. The software- dened radio paradigm oers front-end exibility by eliminating the o-chip radio frequency front-end module and performing band selection, low noise amplication and frequency downconversion within the integrated circuit implementation. On the other hand, low power implementations that oer exibility for the baseband section of the receiver (that performs channel selection, amplication and quanti- zation by ADC) have not been the focus of the software-dened radio. The core program of this thesis consists of proposals of architectures that solve the power and dynamic range trade-os for the baseband section of a modern wireless receiver. The proposed architectures use mixed-signal techniques to relax or completely eliminate power and area hungry baseband lters, which are often not scalable with technology. On the other hand, the ltering functionality that provides interference tolerance at low noise levels is retained due to the mixed-signal feedback system used, with quantization using the ADC performed as expected. xxvi Thus, this thesis describes scalable and recongurable ltering-ADCs that integrate the entire baseband functionality into a single power ecient system. The ltering-ADC architectures are then extended to include the software- dened radio to create a synergic receiver that performs channel selection with low power and area at a desired radio frequency. The thesis elucidates the theory behind the systems used, while the integrated implementations prove that area and power reduction is indeed possible. Applications considered include adjacent chan- nel blocker tolerance such as in the case of Carrier Aggregation, and low power, low-rate communication systems, such as in the case of Internet of Things. The latter part of the thesis describes a mixed-signal architecture and its in- tegrated circuit implementation, for the generation of fast-hopping frequency se- quences with high frequency resolution over a wide range. The proposed architec- ture uses a fast-hopping DDFS-DAC that eliminates sampling at high rates while still having very low latency. The potential applications considered are secure com- munications and electronic warfare. xxvii Chapter 1 Introduction 1.1 Interference Tolerance in Wireless Receivers Conventional wireless transceivers are commonly designed for a specic standard. The transceiver architectures typically consist of (i) a radio-frequency front-end module, (2) analog amplication, frequency shifting and ltering, and (iii) digital baseband (Fig. 1.2a). The radio-frequency front-end module includes RF lters, duplexers (often realized in the acoustic domain) and/or switches. Modern wireless receivers, however, are required to exhibit unprecedented exi- bility by being able to cover several communication standards over wide frequency ranges. The typical wireless receiver faces multiple input scenarios, such as those shown in Fig. 1.1. These include covering wide frequency ranges (i.e. dierent frequency bands), large energy dierences between channels within a given band and instantaneous frequency switching among desired channels bands. 1 Eorts to realize such radios have led to the software radio transceiver concept [1,2], wherein the receiver typically consists of a wideband RF circulator, followed directly by a wideband, high dynamic range Analog to Digital Converter (ADC) (Fig. 1.2b). Amplication is not required and downconversion and band/channel selection is performed digitally. Similarly, upconversion is performed digitally in the transmit side. At this point, the radio architecture can cover a wide frequency and dynamic range due to the superior data converters at the front end. The canonical software radio proposed in [1] and shown in Fig. 1.2b is impractical as data converters at such high performance levels are not currently power ecient in implementation [3,4] 1 . A practical Software-Dened Radio (SDR) is an interim solution [5], that en- ables modication of radio parameters such as RF frequency, channel bandwidth, lter shape, amplication etc. through software programmability without requir- ing power-hungry wideband, high-resolution data converters. For the purposes of this thesis, consider only the receiver chain henceforth. Today's solution to realize multi-standard wireless receivers is an architecture where the specication of var- ious building blocker can be tuned (Fig. 1.3a) [6]. Given that compact, low-loss, tunable RF lters do not exist, the tunable front-end module often consists of an array of switchable RF lters and duplexers. Wideband local oscillators enable 1 In applications where exibility is more important than power consumption (e.g., base sta- tions) the canonical software radio may be an acceptable solution. 2 Fig. 1.1: Representative input scenarios in a modern wireless receiver. frequency downconversion of the desired frequency band. Channel selection is done using a combination of analog and digital programmable lters. Ongoing research is towards eliminating or relaxing the specications of the RF front-end module by the realization of a recongurable analog signal processor that performs ltering, amplication by an Low Noise Amplier (LNA) and frequency downconversion [5] (see Fig. 1.3b). Several features are common to SDR archi- tectures in literature [7{10] some of which are: (i) use of a wideband frequency synthesizer that covers the desired frequency range, (ii) current mode operation that enables band selection ltering at critical points in the receiver chain with 3 Fig. 1.2: The software radio replaces the channel selection lter and the frequency shifting functionality from a typical transceiver shown in (a) to a direct front- end wideband, high dynamic range data converters shown in (b), where frequency shifting and channel selection are performed digitally. lower nonlinearity, and (iii) relying on improvements in transistor transition fre- quency (f T ) with reducing transistor lengths over time [11] for low loss switches and wideband tranconductance cells. For the purposes of this thesis, any channel or band of signals that is undesired by a communication system by protocol is considered interference or an interferer or a blocker. Furthermore, dynamic range of any block or system is dened as the dierence in power between the smallest (usually noise limited) and largest signals 4 Fig. 1.3: The function of the SDR: (a) Today's multi-standard radio with tunable RF, IF and baseband blocks. (b) The SDR replaces the xed front end lter, LNA and the mixer with a programmable, recongurable analog processor that performs an equivalent function. (usually nonlinearity limited) that can be measured [12]. Authors of SDR architec- tures have extensively analyzed tradeo in dynamic range and power consumption for band selection purposes in the presence and absence of inband and out-of-band blockers. On the other hand, analysis of dynamic range tradeos and novel archi- tectures arising thereof, for the baseband channel selection section of the receiver consisting of the baseband lter, Variable Gain Amplier (VGA) and ADC, have been relatively recent topics of research. A core program of this thesis is the proposal of novel architectures that optimize power consumption and dynamic range for the baseband section of the receiver. The problem will be analyzed from the perspective of an ADC that features ltering and 5 Fig. 1.4: The programmable, recongurable ltering-ADC replaces the baseband lter, amplier and ADC for a power ecient solution. amplication, i.e., the intention is to create an energy ecient, programmable, re- congurable ltering-ADC that replaces the entire baseband section of the receiver, as shown in Fig. 1.4. The ltering-ADC approach shown in Fig. 1.4 is relevant for modern commu- nication scenarios. Consider a multi-channel input signal as shown in Fig. 1.5. Channels within the bandwidth have highly varying energy levels, dierent band- widths and modulations. Furthermore, any of the channels may be desired or undesired, with dierent blockers and desired signals tightly packed and adjacent to each other thereby drastically increasing dynamic range requirements. Such a multi-channel signal is often \aggregated" in carrier aggregation, a modern com- munications application where one or more contiguous or non-contiguous channels are assigned concurrently to a single user. The eective bandwidth and thereby, 6 capacity of an individual user can increase on an availability basis, and power al- location per channel is controlled by the Medium Access Control (MAC)/network layer based on measurements and deployment scenarios [13]. One solution for quantizing such a signal is to use a separate signal path that isolates a channel when desired (using a low-frequency programmable lter), and quantizes with an ADC that satises the requirement for that particular channel (Fig. 1.5). There are a few concerns that arise for this system: 1. For a single path, how would the designer tradeo the lter and ADC dynamic range requirements in order to minimize power consumption, i.e. how much ltering is required, if necessary at all? 2. How would one avoid a specialized ADC for each path and rather design a general purpose recongurable ADC i.e. one that can respond to changing bandwidths, modulations and spectral densities? 3. Ultimately, can the overall architecture shown in Fig. 1.5 be replaced by a single ADC that can perform recongurable quantization, while recovering all the desired channels with sucient resolution? It is shown in Chapter 2 that ltering prior to quantization in a multi-channel scenario (i.e. the question posed in item (1) above) is indeed benecial. Further- more, recongurable ltering ADCs for multi-channel signals covering items (2) and (3) above are proposed and implemented in subsequent chapters. Thus, the 7 Fig. 1.5: A separate baseband path to lter and quantize in order to recover a desired channel. The question is whether more power ecient systems can be built. thesis shows that indeed power ecient ltering ADC architectures can replace the conventional baseband (Fig. 1.4) in a multichannel, high dynamic range scenario. Having established the ltering-ADC concept, let us proceed and conceptually replace the baseband section in Fig. 1.3 with the proposed architecture. The resulting receiver is shown in Fig. 1.6a where the SDR and ltering-ADC concepts are both used. A power ecient implementation of such a receiver can be envisioned as a combination of the front-end and back-end as shown in Fig. 1.6b. Chapter 3 shows that certain circuit blocks can indeed be shared between the SDR and ltering-ADC thus giving a highly energy ecient RF-to-digital implementation. Thus, the goal of the thesis is to provide such synergic solutions to the receiver problem for modern communication applications. 8 Fig. 1.6: Replacing the baseband section of the receiver with the ltering-ADC gives the architecture shown in (a). (b) shows a conceptual where certains blocker in the front-end SDR can be combined with the ltering-ADC to provide for a synergic energy ecient receiver. 1.2 Fast Frequency Hopping A second application that is considered in this thesis is generation of fast frequency hopping sequences for secure communication and electronic warfare [14]. This project implements an energy ecient technique to generate hopping frequency sequences at nanosecond rates over a wide frequency range (1-6 GHz). Though typically such systems are built in a fully mixed-signal manner (using high speed DACs) without power consumption considerations, we analyze and implement a system that uses a mixed-signal/RF injection locking architecture that has poten- tial for large power savings. The clock could then serve as a local oscillator in 9 Fig. 1.7: Applications considered in thesis: (a) ltering-ADC for carrier aggrega- tion, (b) low power band and channel selecting receivers, and (c) fast frequency hopping synthesizers for electronic warfare. transceivers for secure communications over an unsecure channel, or alternately can be connected directly to a transmitter for jamming an enemy radio. 1.3 Summary of Results and Thesis Outline This thesis examines three applications, all shown in Fig. 1.7. The rst work (Fig. 1.7a) considers the codesign of the baseband lter and amplier with the quantizer. The result is an energy-ecient implementation of a ltering-ADC that is able to use digital equalization to relax ltering and ADC requirements. Chapter 2 of this thesis comprehensively discusses the theory of joint ltering and quantization, which generalizes to the concept of signal structure dependent quantization. Based on this 10 theory, we will discuss the integrated circuit implementation of a recongurable discrete-time ltering-ADC, for carrier aggregation applications that leverages the input signal structure. Chapter 3 discusses the second work (Fig. 1.7b), which extends the structure dependent ADC concept to the full SDR, where wide frequency coverage for various RF bands is possible. The key theory here shows that the ltering-ADC discussed in Chapter 2 is equivalent to a standard linear digital lter represented in a mixed- signal form. The integrated circuit implementation then merges the functionality of the ltering-ADC and the SDR front end as envisioned in Fig. 1.6. The result is a power ecient implementation of an RF-to-digital, low-power receiver. Chapter 4 discusses the architecture and design of a frequency synthesizer to generate rapid frequency sequences over a wide frequency range while consuming very low power (Fig. 1.7c). Results are shown for an energy ecient integrated circuit implementation of a sine-weighted DAC-DDFS with a digital core, that inherently has zero latency during the frequency hop process. Chapter 5 concludes the thesis. An important note here on the term \energy eciency": we realize that all the architectures considered in this thesis are analog- to-bits or bits-to-analog systems, i.e. quantization noise and thermal noise along with nonlinearity will determine the dynamic range. Thus, the use of the term \energy ecient" for ADCs implies superior performance in terms of energy con- sumption per eective number of thermometer bits, unless otherwise stated [3]. 11 On the other hand, the output current of a DAC is variable depending to the ap- plication, and energy eciency here implies lower power consumption of auxiliary circuits. 12 Chapter 2 Joint Signal Conditioning and Quantization 2.1 Motivating the Filtering-ADC This chapter describes in the detail the proposed energy ecient ltering-ADC architecture that is used as the baseband section of a communication system. Before describing the results it is important to address the questions posed in Chapter 1, i.e. is analog ltering prior to the ADC necessary at all, and if so, what are the corresponding challenges in a multi-channel scenario as shown in Fig. 1.5. 2.1.1 Power Benets from Filtering ADC energy eciencies have improved tremendously in recent times [4], and with improving dynamic range of ADCs, an important question is whether ltering is required prior to quantization at all, and if so, how would the power budget for these blocks be determined. If less ltering is done prior to quantization, additional 13 ltering may be performed digitally after quantization. One key assumption here is that digital ltering after quantization consumes an insignicant amount of power due to scalable and ecient implementations 1 [15]. We use simulations to analyze this problem, starting by constructing two chan- nels of 20 MHz bandwidth adjacent to each other, both consisting of 8-level mod- ulated signals, with one channel as undesired. The energy dierence between the two signals E is varied as is the order of lterN. Since the channels are adjacent to each other, Bessel lters are used to minimize the group delay variation within the lter passband. The simulation setup with the input is shown in Fig. 2.1. For each lter order N, E is varied and the system is simulated with random data to determine the swing at the lter output. Assuming full-scale range at the input of the lter, the VGA brings the signal back to full scale range for quantization. Using simulations, the gain of the VGA after ltering may also be determined from simulation. The dynamic range, or in this case the Signal to Noise and Distortion Ratio (SNDR) requirement for the ADC is simply calculated as sum of the energy dierence between the channels after ltering and the 3 bits required for 8 levels of signal modulation. For an ADC working at full scale V fs , the Signal to Noise Ratio (SNR) at the output of a charged input capacitor C, SNR = [(1=2)(V fs =2) 2 ]=[kT=C], where k is the Boltzmann constant andT is the temperature. For a desired SNR, the minimum 1 Integrated circuits discussed later will show that ADCs that feature digital ltering have lesser total power consumption. 14 Fig. 2.1: The simulation model for estimating the power budget for the baseband section of the communication system. power consumed isP min = (2B) 8kT SNR, whereB is the signal bandwidth [16]. Assuming this thermal limit, we may express the power consumption limit of ADCs, for a required SNDR as P ADC = 16kTB SNDR: (2.1) P ADC cannot be lowered indenitely for lower SNDR as per (2.1), and there is a minimum power consumption due to technology limitations [16] which has been included in the simulation model. A commonly used performance metric, the Figure Of Merit (FOM) for the analog lter+VGA is given as [12] FOM lter+VGA = NBG SNDR lter P lter+VGA ; (2.2) whereG is the gain of the VGA. While a variety of lter architectures are possible, the N-pole cascaded OTA-RC lter, commonly used for moderate bandwidth and high SNDR applications, has FOM lter = 2 =(18kT V DD ) (Appendix A), where is the technology channel length modulation parameter, = g m =I of the input 15 Fig. 2.2: Simulation results show that for a given dynamic range, the power con- sumption of the baseband reduces signicantly with higher order ltering. transistors, and is the ratio of feedback resistors to the output impedance of the OTA. For a 65 nm CMOS technology, 2, V DD = 1, and ecient lter design ensures 10, 10, giving FOM lter+VGA = 197 dB. Using the simulation results, and given the relations (2.1) and (2.2) a plot of total baseband power P ADC +P lter+VGA versus E for various N is shown in Fig. 2.2. As can be see, ltering prior to quantization is indeed benecial for blocker rejection and can signicantly reduce the total baseband power consumption. Note that Bessel lters that have poor frequency rollo were used in simulations to avoid large group delay variations; using other lter topologies such as Butterworth and Chebychev would further reduce system power consumption. 16 2.1.2 Prior Filtering for Carrier Aggregation Consider again the multi-channel scenario as shown in Fig. 1.5. In the previous subsection we have shown that ltering to remove an undesired channel is power ecient. Nevertheless, in carrier aggregation [13], this conventional approach may not suce because the high-energy channel may be desirable as well and should not be ltered, but will nevertheless overwhelm the quantizer. To better understand the challenges posed by multi-channel signal, consider again the simpler case of a two-channel input X with adjacent individual chan- nels X 1 and X 2 , with X 2 of higher energy (Fig. 2.3). Either X 1 or X 2 may be a blocker or a desired signal. Two conventional solutions to accommodate the large energy dierence between the channels, are possible. In a rst approach, an ADC may be used to directly quantize both channels. The individual channels may then be separated in the digital domain using digital lters. This technique requires a high-dynamic range ADC with well-known associated power costs [4]. In a second approach, an analog lter is used to reduce the level of X 2 . A sharp analog lter is required when X 1 and X 2 are very close in frequency. Most lter topologies with sharp amplitude roll-o have group delays that vary considerably within the passband, and especially close to the band edges. In fact, group delay variations outside of the passband, rarely considered in classic applications, is important in the aforementioned carrier aggregation application where the signal that is outside of the lter passband is also desired. Group delay and amplitude variations within 17 Fig. 2.3: Conventional techniques may be used to quantize a multi-channel signal: (a) a high-dynamic range ADC (b) analog ltering in the front-end and then an ADC with a relaxed dynamic range either X 1 or X 2 bands cause signal distortion unless compensated for digitally. Furthermore, although power savings are possible, lters are typically constructed using biquads [12] that require high gain Operational Ampliers (Op-Amps) and do not scale well with technology (higher transistor gain needs larger transistor lengths). While there are signicant eorts in recent literature to create all-digital, standard-cell based ADCs and lters [17, 18], scalability remains an issue. There- fore, ltering is benecial to reduce baseband power consumption while complete spectral recovery and scalability are not entirely addressed. Prior eorts have focused on creating multi-standard, general-purpose ADCs that tradeo bandwidth and dynamic range [19]. While such recongurable ADCs are valuable, the issue of variations in signal spectral density within the band of interest such as in the multi-channel scenario have not been considered in depth. 18 Furthermore, ltering-ADCs in literature (discussed in Section 5 of this chapter) have mostly focused on controlling the Signal Transfer Function (STF) in mod- ulators. In short, a fundamental approach for joint signal conditioning and quanti- zation to implement energy ecient ltering-ADCs is required. 2.2 Signal Structure and Conditioning The approach for the design of ltering-ADCs considered in this thesis exploits signal structure. Signal structure encompasses any property of the signal available apriori to the designer such as signal bandwidth, time-domain amplitude (largest absolute value), Power Spectral Density (PSD), center frequency (for RF signals), modulation, etc. In a cascaded lter-ADC system as shown in Fig. 2.2, the lter and ADC are linear signal-conditioning systems that modify the signal structure 2 . In carrier aggregation, while certain components of the signal structure such as bandwidths of individual channels are dened by standards, other properties of signal structure such as the relative energy dierences between channels may be available from coarse power measurements, and can be readily exploited. Our approach toward the ltering-ADC uses architectures that exploit signal structure to perform ltering prior to quantization, while successfully addressing the complete signal recovery, scalability and exibility. We will rst establish theory required to construct the ADC architectures. 2 Henceforth, quantization noise is considered as linear addition of signal-independent white noise. 19 2.2.1 Signal Conditioning by the Simple Dierence Filter For intuition purposes, consider signal conditioning by a simple dierence lter. For a lowpass bandlimited signal x(t) of bandwidth B, when sampled with frequency f s > 2B, the dierences in amplitudes of consecutive samples,x(nT s )x((n1)T s ), is a function of B and f s . Intuitively, as shown in Fig. 2.4, a signal of limited bandwidth has limitations in the rate of change of its amplitude. Consequently, shorter sampling time periods result in smaller dierences in amplitudes, due to a direct bandwidth dependent time-to-voltage transfer function. It will be shown that the maximum possible amplitude of the dierence signal x(t)x(tT s ), at any time t, will be V fs sin(B=f s ), where V fs is the full scale range of x(t). Using this property, a system of Fig. 2.5 can be constructed. The output of the signal dierentiator is passed through a gain, G = 1=[2 sin(B=f s )] that brings the signal back to the full scale range V fs . The signal then passes through a low-resolution quantizer. The quantized signal is then integrated digitally to obtain the nal output. Amplifying the dierence signal prior to quantization leads to increased ADC resolution; i.e. the increased resolution is a function of input signal. We do however pay a price: quantization noise undergoes an integration as well and an undesired noise shape is present. Fortunately, it will be shown that this issue can be resolved using appropriate feedback. Since dierences of signals over time samples are considered, we are ltering in the discrete-time. While the theory and ADC architectures discussed in subsequent 20 Fig. 2.4: A signal of limited slope being sampled using rate T s;1 and half the rate T s;2 . Due to the slope limitation (i.e., due to limited bandwidth of the signal), the resultant voltage dierences of samples re ect the sampling rate. Fig. 2.5: Conceptual illustration of signal dependent quantization: Since dieren- tiation causes signicant reduction in the full scale range of a bandlimited signal, the gainG can bring back the signal to full-scale. After this process, a quantizer is used to map the signal into quantization levels (in this case, 4 levels). Integration will then result in levels stacking on top of each other, thus increasing the overall resolution. sections are valid in the continuous-time as well, the development will be done assuming sampled signals. 2.2.2 Signal Conditioning given Signal Structure We will now generalize the intuition obtained from the simple dierence lter. Signal conditioning by the front-end lter reduces the full-scale range of the signal. Given the signal structure, the ADC designer can precisely calculate the reduces 21 Fig. 2.6: Filtering and gain boosting in the time domain and frequency domain. swing at the output of the lter, thus obtaining gain G, as dened in the previous subsection, and thereby enhancing the signal with respect to the quantization noise (see Fig. 2.5). In most systems, structure that is readily available is the signal bandwidth B, which can be used to enhance the quantization noise. Consider a band-limited signal x(t) of single-sided bandwidth B and such that jx(t)j V fs =2, sampled at a rate f s = 1=T s . The signal is supported in the frequency domain on [f 0 ;f 0 +B]. We assume the Nyquist-Shannon criterion, i.e., f 0 +B <f s =2. In Fig. 2.6, the sampled signalx(n) is shown as an input to a nite discrete-time lter,H(z) of impulse responseh(n). Note that ifH(z) = 1z 1 , the lter is a dierentiator as described in Section 2.2.1. The amplier following the lter boosts the level of ltered signaly f (n) to the full scale rangeV fs =2. Thus, we seek the maximum ofjy f (n)j =jx(n)h(n)j before determination of the amplier 22 gain G. We note that the Shannon-Nyquist guarantees a complete representation of the analog signal within f <f s =2. Therefore, maxjy f (n)j = maxjx(n)h(n)j = maxjx(t)h(t)j = max x(t)F 1 H 2jf f s ; whereF 1 denotes the inverse Fourier transform. In other words, ltered output of the analog signal gives the same maxima as the discrete-time ltered output. Using the above property, the maximization problem is formally stated as: max X(f) x(t)F 1 H 2jf f s ;X(f)2 [f 0 ;f 0 +B]; jx(t)j V fs 2 ; f 0 +B < f s 2 : (2.3) In Appendix B, it is shown that max X(f) x(t)F 1 H 2jf f s = V fs 2 max f2[f 0 ;f 0 +B] H 2jf f s : (2.4) Two particularly important cases of H(z) are now described. Case 1: H(z) = 1z 1 ;f 0 = 0 (Fig. 2.7a). This is the lowpass signal and dierentiator case, wherej1z 1 j = 2 sin(2f=f s ). This function is monotonically increasing with f and achieves a maximum at the edge of the band, thus giving maxjy f (n)j = V fs sin(B=f s ) = V fs sin (=2N), where N > 1 is the oversampling ratio. 23 Fig. 2.7: Specic examples of maximum swing at the output of discrete-time lters: (a) Low-pass signal and dierentiator lter (b) Bandpass signal and bandpass notch centred at f s =4. Fig. 2.8: A lowpass signal of bandwidthB is sampled using a frequencyf s = 2NB. The dierence of consecutive samples varies with the oversampling ratio N. (a) When N = 1, the maximum dierence spans the full scale range of a sinusoidal waveform of frequencyB. (b) WhenN > 1, the maximum dierence occurs around the zero crossing of the same sinusoidal waveform. As shown in Fig. 2.8a, at the Nyquist rate or at N = 1, the maximum sample dierence spans the entire full scale range of a sinusoidal signal of frequency B. However, when N > 1 (Fig. 2.8b), the sample dierence is maximized around the zero-crossing of the waveform. 24 Fig. 2.9: Oversampling, ltering and quantization using a general lter H(z) and its inverse. Case 2: H(z) = 1 +z 2 ;f 0 =f s B=2 (Fig. 2.7b). This is the bandpass signal case with a notch lter centred atf s =4. H(z) assumes a maximum at the edge of the band, f =f s B=2. If f s = 2NB, we again obtain, maxjy f (n)j =V fs sin(=2N). The above two cases can be generalized to a notch spanning anywhere from f = 0 to f =f s =2. In any such case, it can be shown (by a property of frequency translation) that a band pass signal will have maxjy f (n)j = V fs sin(=2N). From the preceding analysis, given that the ltered signal swing y f (n) is restricted to (V fs =2) max f2[f 0 ;f 0 +B] jH (2jf=f s )j , a gain stage with G = 1 max f2[f 0 ;f 0 +B] jH (2jf=f s )j ; (2.5) brings the signal to full scale range. Henceforth, we assume G > 1, which is usually the case when oversampled signal are considered (i.e.,N 1).The amplied signal is then input to a quantizer of M-bit resolution, with quantization step, 25 q = V fs =(2 M ). The frequency domain output of the quantizer Y q (z) is then given as: Y q (z) =GX(z)H(z) +E(z) = X(z)H(z) max f2[f 0 ;f 0 +B] jH (2jf=f s )j +E(z): (2.6) From (2.6), it is clear that the input signal is boosted by the gain G, but is still distorted due to the eect ofH(z). An inverse lter, post-quantization, can x this issue (Fig. 2.9). The inverse lter used is of the form z k =H(z), where k is an arbitrary delay parameter. The nal digital output is given as Y (z) =GX(z)z k + E(z) H(z) z k = X(z) max f2[f 0 ;f 0 +B] jH (2jf=f s )j z k + E(z) H(z) z k : (2.7) Note that while the signal is enhanced and thereby relaxes the ADC dynamic range requirement, quantization noise spectrum has a lter-dependent spectral shape. We will address this issue during the construction of the ADC architectures. At the point, we conclude that signal conditioning given signal structure (i.e. bandwidth B) can enable quantization resolution enhancement. 2.2.3 Extension to Power Spectral Density In wireless receivers, it is possible that additional information on the signal structure is available. To consider a very optimitic case, assume that the receiver is able to measure the frequency magnitude informationjX(f)j accurately. Spectrum analysis 26 Fig. 2.10: Two dierent waveforms with dierent amplitudes, but the same power spectral density. (a) Amplitude of FM signal is 4.72 mV, (b) Amplitude of AM signal is 94 mV, (c) PSD of both waveforms measured using a spectrum analyzer, (d) FFT of both waveforms simulated. and power measurements are commonly used to obtain an accurate estimate of the signal spectrum. A commercial spectrum analyzer is able to measure accurately, the magnitude of the Power Spectral Density (PSD) of an input signal [20], and recent advances in integrated circuits have enabled on-chip implementations of such measurements [21]. The maximum swing or full scale range of a set of signals x(t) that share the samejX(f)j, is upper-bounded using (Appendix C) maxjx(t)j = Z 1 1 jX(f)j df: (2.8) 27 By construction, (2.8) maximizes over all possible signalsx(t) that can havejX(f)j, as the absolute value operationjj results in the loss of phase information. To illustrate with an example, Fig. 2.10 shows a frequency modulated signal and an amplitude modulated signal, that have the same magnitude spectrumjX(f)j, but dier signicantly in the maximum swing (to see how this is possible, see Appendix C for an explanation). Likewise, the maximum swing of the output of the ltered version of x(t) is obtained as: maxjx(t)h(t)j = Z 1 1 jH(f)jjX(f)j df: (2.9) Notice that (2.9) reduces to (2.4), whenjX(f)j is not explicitly available as a func- tion of frequency, apriori from observations or measurements, but the maximum possible swing ofjx(t)j is known to be V fs =2. Maximizing the right hand side of (2.9) over all possible X(f) separates the two terms in the integral, resulting in (2.4). Expression (2.9) suggests that the value of gain G is aected by the maxi- mum swing at the output of a lter, and it is possible to set these parameters in the proposed ADC, based onjX(f)j. Practically however, the incorporation ofjX(f)j into the ADC requires either prior knowledge of the signal or tedious long-term measurements. Furthermore,jX(f)j is subject to variation depending upon choice of modulation and real-time knowledge is improbable. Having established this, it is still appreciable that the proposed ADCs are highly adaptable to the energy distribution in the signal spectrum. 28 2.2.4 Carrier Aggregation Carrier aggregation presents multiple closely-spaced channels whose bandwidths and relative energy levels may be readily known (Fig. 2.1). Consider an R- channel lowpass signal x(t) = P R r=1 x r (t), with the individual components x r (t) = F 1 fX r (f)g;8r andjx r (t)j V fs;r =2;8r, with X r (f) bandlimited to B r B. The full scale range is such that P R r=1 V fs;r =V fs . x(t) is sampled with frequency f s = 2N r B r ;N r > 1;8r. In summary, we are considering a lowpass x(t) to be a sum of R distinct signals that have a total full scale range V fs , each with a cer- tain bandwidth less than B. This is a suciently general model for channelization in the carrier aggregation scenario. To simplify further consider consecutive and equal bandwidth divisions, i.e., B r = rB=R; r2 [1;R]. We therefore note that N r =f s =2B r = (R=r)N where f s = 2NB. We consider the simplest possible lter: H(z) = 1 z 1 , givingjH(z)j = 2 sin(f=f s ). It can be shown that (Appendix C) maxjx(t)h(t)j = R X r=1 V fs;r sin r 2NR : (2.10) For large N, (2.10) is simplied as maxjx(t)h(t)j R X r=1 V fs;r r 2NR : (2.11) 29 The expression for maxjx(t)h(t)j directly aects the gain G (from (2.5) and (2.11)) and includes the contribution of individual V fs;r as a function of r. Using prior theory, these expressions are derivable for any lter H(z). Thus, any addi- tional information about the spectral density can be incorporated in the general theory to obtain better upper bounds of the maximum after conditioning by a l- ter. While the precise expression for G helps evaluate the resolution enhancement from (2.7), ADC architectures that prevent quantization noise shaping must be developed. 2.3 Recongurable Signal Dependent ADC Following Fig. 2.9 and (2.6), the quantization noise shape must be eliminated. Fur- thermore, while the lter enables a relaxed ADC design, the system sill remains a conventional progammable-analog system, with limited scalabity and recongura- bility. We will address all these concerns using appropriate feedback. 2.3.1 Feedback Consider a system as shown in Fig. 2.11 where the lterH(z) is eliminated, but the output of the quantizer is passed through a feedback lter H fb (z), and converted 30 to an analog waveform using a DAC. The choice of H fb (z) ensures (i) perfect re- construction of x[n] at the output and (ii) X(z)H(z) is seen as input to the gain block, i.e, the system, Y (z) =GX(z)z k ; X(z)Y (z)H fb (z) =X(z)H(z) is satised, thereby eliminating the front-end lter. With the feedback closing the loop, the added quantization noise E(z) can be input-referred to the gain G and added directly to the input X(z), thus eliminating noise-shaping while simultane- ously giving the desired output. We solve to obtain H fb (z) = 1H(z) Gz k : (2.12) H fb (z) is generally not causal; however, as will be seen, for specic values of H(z) and for specic values of k, H fb (z) is realizable. Note that the physical process of converting samples to waveforms is performed by the DAC, which can incorporate the feedback gain 1=G in (2.12). The complete expression for Y (z) is then Y (z) =GX(z)z k +E(z)z k = X(z) max f2[f 0 ;f 0 +B] jH (2jf=f s )j z k +E(z)z k ; (2.13) 31 Fig. 2.11: A general signal dependent oversampled ADC with feedback. thereby showing elimination of the noise shape present earlier in (2.7). The signal is still boosted with respect to the quantization noise, due to G, translating as an increase in eective resolution for the oversampled ADC, M e . In Appendix B, it is shown that M e =M + log 2 (G) =M log 2 max f2[f 0 ;f 0 +B] H 2jf f s : (2.14) Fig. 2.11 is the structure of the proposed signal dependent oversampled ADC ar- chitecture. A class of ADCs can be constructed, depending onH(z). Furthermore, H(z) can be considered a design parameter depending on the input signal structure, and is highly recongurable due to being digital. 32 2.3.2 DPCM, Recongurability, and Comparisons with Modulation The proposed ADC architecture [22] can vary the eective resolutionM e depending on G. In turn, G is determined by the lter in use (from (2.5)), which is digitally recongurable, depending on the signal structure information. Thus the ADC is signal dependent and is highly recongurable depending on the carrier aggregation scenario. In recongurable ADCs in literature, the innovation has been focused pri- marily on maintaining the FOM as much as possible across various signal band- widths [23{25]. In a quest to nd the right architecture for such recongurable data converters, it comes as little surprise that oversampled systems, particularly modulators have been ADCs of choice [23,26{28], due to a direct tradeo in band- width and resolution, and their robustness to circuit imperfections [29]. While modulators achieve bandwidth recongurability, and provides superior resolution if the oversampling ratio is high, the inband signal PSD is not a design criteria in determining the nal resolution. Furthermore, the signal bandwidth is often chosen to be B f s =2. On the other hand, several applications like carrier aggregation demand adaptability to spectral energy distributions. A special case of the proposed class of ADCs is whenH(z) = 1z 1 ,f 0 = 0, and k = 1 giving H fb = 1=G. This is the well-known delta modulation system, widely 33 Fig. 2.12: DPCM and delta modulation are special cases of the general ADC ar- chitecture. In this case, H(z) is a simple dierentiator, and the loop lter is an integrator after the quantizer. The feedback lter 1=G, can be physically incorpo- rated in the DAC. Both G and 1=G are variable, depending on N. Fig. 2.13: An interesting recent implementation of delta modulation is the use of a Ring-VCO based quantizer. Using this quantizer in the delta modulation loop (Fig. 2.12), gives a digital PLL. Therefore, this digital PLL can also be interpreted as a special case of delta modulation. studied in literature (Fig. 2.12). For delta modulation, G = 1=[2 sin(=2N)], obtained by direct subsitution in (2.5); f s = 2NB. First discussed by Cutler in [30], this scheme is also a special case of Dierential Pulse Coded Modulation (DPCM) for which CMOS prototypes have been described in literature [31]. DPCM is usually interpreted as predictive quantization where 34 the previous sample of a signal is most accurately predicted before quantization of the dierential is performed [32]. In delta modulation, the dierentiator transfer function modulus at the edge of the band is 2 sin(=2N), thus having lower signal swing at the output for large N. This observation was also made in [33], albeit with a much more cumbersome derivation. Some notable state-of-the-art oversampled ADCs are special cases of delta mod- ulation. For example, the ideal quantizer in Fig. 2.12, when replaced with a Ring- Voltage-Controlled Oscillator (Ring-VCO) based quantizer, has an inherent rst- order noise shaping (Fig. 2.13). Constructing a ADC around this Ring-VCO based quantizer, a integrated prototype is reported in [34]. The authors of [34], however, approach the problem as a Phase-Locked Loop (PLL) as the system can be simplied to obtain a structure that resembles a digital PLL (Fig. 2.13). We thus conclude that this digital PLL can also be interpreted as delta modulation. The eective resolution in delta modulation, M e , is given as (from (2.10)) M e =M 1 log 2 h sin 2N i : (2.15) For high values ofN,M e M log 2 [=N], i.e, an increase in oversampling ratio results in higher ADC resolution. This feature mimics rst order modulation, where resolution improves with higherf s =B ratio [29]. However, we wish to empha- size that this improvement in the proposed ADC is obtained with no noise shaping at all. 35 Fig. 2.14: First order - ADC with signal and noise transfer functions. Henceforth, the scheme in Fig. 2.12, will be referred to as rst order delta modulation. Just as modulation, delta modulation can be extended to higher orders. In an L th order delta modulation, we use L th order signal dierences, i.e. H(z) = (1z 1 ) L , with k = 1 giving a causal feedback lter H fb (z). Using the binomial expansion, H fb (z) = 1 (1z 1 ) L Gz 1 = 1 G L X l=1 L l (z) (l1) : From direct substitution into (2.5), G = 1= [2 sin(=2N)] L , thus giving an eective resolution from (2.10) M e =M + log 2 (G) =MLL log 2 h sin 2N i : (2.16) The practical design of H fb (z) and the inverse lter z 1 =(1z 1 ) L increases in complexity for larger L. 36 Since the only structural information available at this point isB, it is reasonable to compare the performance of the generalized rst order delta modulation with that of the rst order modulation. Comparing Fig. 2.12 and Fig. 2.14, rst order modulation and rst order delta modulation dier in two aspects: (i) the integrator and quantizer have switched positions in the feedforward path of the loop, and (ii) delta modulation has an additional gain G, as derived in Section 2.2.2, to bring the signal back to full scale range. A quantization stepq, gives a total noise power ofq 2 =12 [29] which, when spread over the single sideband bandwidthf s =2 gives a broadband noise PSD,q 2 =6f s 3 . For the oversampled case, when f s = 2NB, we are only concerned about noise within the signal bandwidth B. For rst order delta modulation, the total quantization noise of the output y(n) is, N e; = B |{z} Bandwidth q 2 6f s | {z } PSD h 4 sin 2 2N i | {z } Resolution Gain = q 2 12 4 N sin 2 2N : (2.17) 3 There is a subtle contradiction in calculating PSD for quantization noise, as we have considered x(t) to be nite energy signal with a well dened X(f). Given this, by denition x(t) has zero power. Therefore, a meaningful Signal to Quantization Noise Ratio (SQNR) is not denable. This contradiction is addressed and resolved in Appendix C. 37 Fig. 2.15: A comparison of the total noise N e vs. oversampling ratio N for rst order delta modulation and modulation. It is shown that the noise rolls o as 1=N 3 for both architectures, with a nite 4.77 dB dierence asymptotically. For modulation, quantization noise PSD is integrated tillf =B, with the noise shape: N e;- = Z B 0 q 2 6f s | {z } PSD 1 exp 2jf f s 2 | {z } Noise Shape df = q 2 12 2 N 2 sin N : (2.18) A normalized logarithmic plot of above expressions is shown in Fig. 2.15. Large N is of particular importance, as at this point asymptotic limits are applicable. In comparison, lim N!1 N e; N e;- = 2 =N 3 (2=N) (2=)(=N 3 =6N 3 ) = 2 =N 3 2 =3N 3 = 3 4:77 dB: 38 Therefore, for large N, modulation outperforms delta modulation by 4.77 dB, which is, by the uniform noise approximation, 4:77=6:02 0:79 bits of resolution, given the same low pass bandwidth. However, it is noteworthy that both schemes roll-o in total quantization noise as 1=N 3 , thereby showing that the performance is of the same order. Similar conclusions can be made for comparisons of higher order delta and modulation. Theory leading to the expression (2.17) assumes an arbitrary X(f); i.e. the maximization problem (2.3) maximizes over all possible X(f). The same is true for the derivation of (2.18), where the noise shape and bandwidthB are important parameters and notX(f) itself. We will now show that additional knowledge about X(f) in the case of carrier aggregation, can result in a superior ADC in our proposed schemes, which gives N e; <N e; . Returning to the case of carrier aggregation considered in Section 2.2.4, expres- sion (2.11) includes the contribution of individual V fs;r as a function of r, i.e., the energy per channel, Hence, we determine the best possible ADC resolution obtain- able, given the energy distribution. We will now examine two examples. Example 1 (Uniform Allocation): V fs;r = V fs =R;8r. i.e., energy is alloted equally to each channel. Expression (2.10) reduces to: maxjx(t)h(t)j = V fs R R X r=1 sin r 2NR V fs R R X r=1 r 2NR = 2N R + 1 2R : 39 The total quantization noise power is: N e; = B |{z} Bandwidth q 2 6f s | {z } PSD 2 4 4 " 1 R R X r=1 sin r 2NR # 2 3 5 | {z } Resolution Gain = q 2 12 2 4 4 N " 1 R R X r=1 sin r 2NR # 2 3 5 : (2.19) Comparing with rst order modulation, and using (2.19), with large N the asymptotic ratio of total quantization noise of the two schemes is given as: lim N!1 N e; N e;- = 2 N 3 R+1 2R 2 2 N 2 N 3 6N 3 = 3 R + 1 2R 2 : (2.20) For various values of the number of channels R, the ratio (2.20) can vary from 3 (for the single channel case, as is known from earlier), toR!1, when the ratio is equal to 0.75. In all cases, the roll-o is still 1=N 3 . However, depending on the signal energy distribution, the modulation total quantization noise is surpassed by that of delta modulation (Fig. 2.16). Example 2 (Non-uniform Allocation): Fig. 2.17 shows two cases where signal energy distributions dier vastly. In either case, modulation has the same noise shape and thus, identical integrated noise within the bandwidth. However, when energy distribution is non-uniform, the proposed ADC can potentially benet from further energy distribution-dependent noise reduction, due to a reduced signal maxima. 40 Fig. 2.16: A comparison of the total noise N e vs. number of equi-power channels R for rst order delta modulation and - modulation. Oversampling ratio, N = 40. The modulator always considers noise in the entire bandwidth. However, depending on the maximum output of the dierentiator, delta modulation can adapt to changing channel allotments. A numerical example will be appropriate to show the proposed ADC's adapt- ability to energy distributions. We have 12 channels, where the r th channel of highest frequency rB=12 has 6 dB lesser energy (i.e., half the amplitude) than the adjacent channel with highest frequency (r 1)B=12. The total V fs = 1. Using (2.11) it is easily veried, for large N, that 12 X r=1 V fs;r r 2N 12 = 0:166 2N : 41 Fig. 2.17: The diagram shows two possible energy distributions. modulation produces the same noise shape for either energy distribution. However, the proposed ADC is sensitive to the maximum signal swing and therefore can potentially give a lower noise oor depending on the signal energy distribution. Therefore, case (b) can have better performance than case (a). For a comparison with - modulation, we calculate the performance at large N: N e; N e;- (4=N) (0:166=2N) 2 2 =3N 3 =10:80 dB: It is thus seen that for the non-uniform case, large improvements over modu- lation are obtained with varying energy distributions. Other energy distributions and lter orders can potentially give further improvements. 42 Fig. 2.18: A second order delta modulator with forward equalization lter H(z) and feedback lter H fb (z). 2.4 Behavioural Simulation and Implementation Challenges In this subsection we present the behavioural simulation of proposed ADCs that can be used as starting points for corresponding integrated implementations. We will present detailed error analysis along with statistical simulations and also discuss implementation challenges, circuit-level recongurability and scalability. 2.4.1 Error Analysis and Simulations For error analysis, a DPCM ADC withL = 2, i.e., a second order delta modulation, is used for a lowpass signal, i.e.,f 0 = 0 (Fig. 2.18). This ADC has the simplest non- constant feedback lter H fb (z), which can be extended to other ADCs of interest. Here, H(z) = (1z 1 ) 2 (L = 2), giving H fb (z) = 2z 1 from (2.14) for k = 1. The error model used is shown in Fig. 2.19; it consists of gain errors, 1 in the forward path and 2 in the feedback path, the ADC comparator oset e 1 and the 43 Fig. 2.19: Error model for a second order DPCM ADC. DAC mismatche 2 . The digital ltersz 1 =(1z 1 ) 2 and 2z 1 are assumed ideal. In the frequency domain, Y (z) = (G 1 X(z) +E(z) +E 1 1 2 E 2 ) z 1 1 + (2z 1 +z 2 ) (1 1 2 ) : (2.21) The total signal boost G is degraded by the factor 1 . Also, just as E(z), E 1 is suppressed by the factor 1 G, with respect to the signal X(z). There is also an undesired total shaping that is eliminated if 1 2 = 1. However, given that gain errors are static, this shaping can be digitally equalized using an inverse lter, 1 + (2z 1 +z 2 ) (1 1 2 ). The eects of the nonidealities are characterized individually. The parameters for simulation are chosen as: B = 10 MHz, f s = 250 MHz, thus giving the over- sampling ratio N = 12:5. The quantizer is a Flash ADC with a M = 4 bits. The input signal to the ADC is a single sinusoidal tone of amplitude 0.5, with a zero mean, implying V fs = 1. Using the above parameters, ideally, M e = 7:99, 44 Fig. 2.20: Behavioural simulations for the ADC in Fig. 2.18 to characterize indi- vidual nonidealities: (a) Eect of ADC comparator oset in LSB on SNDR (100 iterations), (b) Eect of DAC mismatch in bits on SNDR (100 iterations), (c) Eect of gain error on SNDR. Spectra were estimated for a 100 s time window, after Blackman-Harris windowing. calculated using (2.10), giving an Signal to Noise and Distortion Ratio (SNDR) of 49:87 dB. Noise beyondB = 10 MHz is irrelevant; after subtraction, the total ideal SNDR is 60:84 dB. The resultant ADC is simulated behaviourally in MATLAB for 100 s and spectra were estimated after Blackman-Harris windowing 4 . Results in Fig. 2.20, show that for a3 requirement, to obtain a performance of about 57 dB, an ADC comparator oset of 0:2 LSB and DAC mismatch of 11 bits is required. The average performance is close to ideal. Gain errors have very minimal eect on the SNDR. Choosing above oset/mismatch values and 5% gain errors, the average spectrum for a single-tone test with all nonidealities included, is shown in Fig. 2.21a. As expected, the3 SNDR value lies at 57 dB, only a 4 dB degradation. 4 It is to be noted that simulations can be unstable for certain initial conditions as the value of G increases in the second order loop. To have a stable output unconditionally, the full scale-range at the input of the quantizer was deliberately reduced to 1=2 of the largest full scale range, in order to provide margin during the initial transient. 45 We now consider an aggressive channelization scenario (results shown in Fig. 2.21b), where one channel has 40 dB more energy than the energy of two other signals, and potentially behaves as a blocker. Comparisons with conventional modulation are also shown. Here, it is important to have high resolution, in order to quantize the weaker signals suciently. The channel bandwidths are 3 MHz, 3 MHz and 4 MHz; totaling 10 MHz. Three cases are considered, with either of the three channels having 40 dB larger energy compared with the other two channels that have equal energy. In Case 1, where the largest-energy channel is closer to DC, the proposed scheme oers a much higher SNDR for the low-energy channels compared with a standard scheme. In cases 2 and 3, the scheme provides a higher SNDR for the low-energy channels that are now close to DC. This is because in the proposed scheme, the input signal is high-pass ltered prior to quantization. In principle, this lter may be replaced with a band-pass or a low-pass lter to accommodate signal scenarios where the high-energy channel is located in the middle or the higher end of the desired frequency band, respectively. It is noteworthy, that the performance for the rst channelization case (i.e. total SNDR = 76:36 dB) is comparable to that of state-of-the-art oversampled ADCs [35], however at a clock speed of less than half, simply due to the signal adaptive nature of the proposed ADC. 46 Fig. 2.21: Behavioural simulation of the scheme in Fig. 2.18 (100 iterations each): (a) A single-tone test (b) Three-channel scenario where the tone in either of the channels 1, 2 or 3 is 40 dB larger compared with the other two. SNDR per channel improves considerably for the low-energy signals of Case 1. 2.4.2 Implementation Challenges We organize implementation challenges under three topics: (i) recongurability (ii) power consumption, scaling and maintaining FOM across recongurable modes (iii) comparisons with ADCs. Recongurability: Recongurability for the proposed ADC (Fig. 2.11) is fully achieved by varying the forward path gain, G and the feedback path gain 1=G (from H fb (z)). The quantity G varies with the given bandwidth and signal energy distribution, which can be implemented by a variable gain amplier. In the feedback path, the gain 1=G is embedded into the DAC. Consider two recongurable modes with gains G 1 , G 2 where (for simplicity), 2G 1 = G 2 . The corresponding eective resolution (from (2.10)) is M e;1 = M + log 2 (G 1 ) and 47 M e;2 = M + log 2 (G 2 ) = M + 1 + log 2 (G 1 ), with an additional bit required for the mode with G 2 . If the DAC consists of unitary elements, the number of el- ements decreases as G 2 =G 1 = 2, while, for the same full-scale output, the unit element size increases by the same factor. Thus, recongurability is achieved going from G 2 to G 1 , by tying two unit elements together, as shown in Fig. 2.22. We envision designing the unit element for the highest possible resolution, and creat- ing a digital switching scheme that performs tying or separating of unit elements between recongurable modes. Power Consumption, FOM and scaling: The second order DPCM ADC has two digital integrators. In general, both H(z) and H fb (z) are digital blocks that are well-suited for scaling with digital technology. On the contrary, a second order ADC has two analog integrators, that do not scale well in power consumption, with technology scaling. The power consumption of the proposed system is expected to be dominated by the forward path analog gain block, G. For a given capacitive load, the power consumption of this block, to the rst order, is assumed to be directly proportional to its Gain-Bandwidth Product (GBW) [12]; i.e. P G / GB. The ENOB/ 2 M e =G 2 M (from (2.10) and Appendix B) and the FOM is roughly estimated as: FOM = P G Nyquist Rate 2 ENOB / GB 2BG (2 M ) = 1 2 M+1 = Constant: 48 Fig. 2.22: A switching scheme for the feedback DAC, to change between modes 1 and 2 having gains G 1 and G 2 respectively, where 2G 1 = G 2 . Changing to mode 1 decreases the number of bits by 1. The switching scheme ties together two unit elements (say, current sources) going from mode 2 to mode 1, maintaining the same full scale output, however with lower resolution. Accordingly, even index data signals are disabled. Note that the above estimate is only true for cases with the same oversampling ratio, implying FOM tends to be constant over various channelization modes. FOM with changing bandwidths will also depend on the oversampling ratio. We will now illustrate with a numerical example. Let M = 4, f s = 250 MHz and B = 10 MHz. Consider two modes with gains G 1 = 15:91 (GBW = 159:1 MHz; single channel case) andG 2 = 63:64 (GBW = 636:4 MHz; multi-channel case) respectively. Subsequently, M e;1 = 7:99 and M e;2 = 9:99. Assuming G 1 consumes 2 mW, the FOM for the system in mode 1 is 111 fJ/conv-step. For mode 2, the power consumption increases to 8 mW for four times the GBW. With the corresponding increase in M e , the FOM again results as 111 fJ/conv.-step. Practically, an upper limit for the GBW of gainG is determined by the transition frequency (f T ) of the technology. In general, the system has an inherent tendency 49 to maintain a constant FOM over all channelization recongurable modes, as higher the value of GB=f s results in higher power consumption, while simultaneously, the resolution also increases. Furthermore, as mentioned, low-oversampling ratio designs give comparable results with state-of-the-art, due to channelization. The reduction in clock speed further reduces digital power consumption. Comparisons with ADCs: From the exposition presented, it is clear that the proposed ADC gives better resolution under varying signal energy distributions, while beneting from technology scaling. One disadvantage of the proposed ADC is that the unit element of the feedback DAC is determined byM e , which is generally a high resolution. This increases the DAC area and the complexity of layout. On the other hand, a ADC that uses the same quantizer of resolution M, requires a DAC of only resolution M. However, in both cases DAC mismatch errors are directly refered to the input, and mismatch requirements are the same. 2.5 Feedforward Equalization Architecture The ADC architecture of Fig. 2.11 is recongurable and scalable due to the use of mostly digital and mixed-signal blocks. Furthermore, the quantizer is still relaxed in dynamic range requirements, while the architecture is robust to mismatches. This attributes thus leads to the original intention of creating a mixed-signal processor that replaces conventional solution. 50 Regardless, the architecture has some disadvantages; the feedback DAC will invariably be a large implementation in terms of area, thus making it further sus- ceptible to noise and mismatch. Furthermore, it is important to note that the system is a feedback system with quantization, i.e. ensuring stability is very di- cult particularly for higher order (>3) inverse lters. It is thus useful to examine whether equalization can still assist an analog lter-ADC cascade, and thereby improve the energy eciency of the system. In Section 2.1 we determined that the conventional technique of using inde- pendently designed cascaded lters and ADC (regardless of which operation is performed rst), is not optimal for a structured input signal with large energy spectral-density dierences. In this subsection, we present an alternate architec- ture that provides a more power and area ecient solution to the above problem. Specically, we describe a feedforward discrete-time ltering and equalization ar- chitecture that relaxes both lter and quantizer requirements while fully recovering the signal after equalization. This will be achieved using a lter-ADC co-design, and will not require a large DAC. We present a proof-of-concept integrated circuit implementation of a 200 MSPS ltering-ADC that eciently quantizes adjacent channels of up to 40 dB energy dierence [36, 37]. Given complete signal recov- ery, the high-energy channel in the signal structure considered can be desirable or undesirable (i.e., a blocker). 51 Fig. 2.23: Blocker tolerant ADCs reported in literature. Blocker-tolerant ADCs reported in literature focus on independently control- ling the Signal Transfer Function (STF) and Noise Transfer Function (NTF) in Continuous-Time (CT) ADCs. The techniques reported can be broadly classi- ed as those that use (i) analog lters upfront within the CT loop [38{42], or (ii) digital inverse lters in the CT loop backend [22,43] (Fig. 2.23). While the techniques successfully lter out-of-band blockers, they do not address the multi- channel input scenario. Furthermore, since lters are introduced inside the feedback loop, stability conditions are very stringent. The literature also reports channelized-ADCs that aim to relax quantizer dynamic range by introducing multi- path interleaved lter banks that deliberately channelize an input signal [44, 45]. These \frequency-interleaved" ADCs however, do not perform digital equalization in real-time; therefore on-chip memory is required to store the ADCs output data for intensive post-processing. As will be shown, the proposed architecture requires 52 Fig. 2.24: Details of the proposed architecture. neither lters within a loop like in the case of blocker-tolerant CT ADCs, nor complicated oine equalization like in the case of frequency-interleaved ADCs. 2.5.1 Discrete-time Filtering and Equalization Consider the multi-channel input signal from Fig. 2.2. This signal is rst sampled at frequency f s for discrete-time signal processing (Fig. 2.24). H(z) then specif- ically lters high-energy channels (desired or undesired). Since no particular care is taken to have a uniform passband response, the lter may distort all channels signicantly in amplitude and phase. Filtering reduces the total amplitude, which is then brought back to full scale using gainG. ADC quantization noise modeled as E q (z)H e (z), whereE q (z) is the quantization noise of anM-bit quantizer andH e (z) is the NTF, represents digitizing of the ltered and amplied signal. To recover 53 the signal completely, a digital inverse lter 1=H(z) is used to equalize the ADC output. The output Y (z) is (Fig. 2.24) Y (z) =GX(z) +E q (z) H e (z) H(z) : (2.22) Equation (2.22) reveals two important features of the architecture; rst, the input X(z) is fully recovered and is amplied. Second, the quantization noise E q (z) is shaped by the lter STF H(z), besides the NTF, H e (z). Since GH(z)X(z) must not exceed full scale range at the input of the quantizer and is calculated precisely, blocker frequency and power detection is a prerequisite to determine H(z) and H e (z). Consider an N channel input signal, with each channel of full scale range A n . The channels span frequencies: [(f 0 ;f 1 ); (f 1 ;f 2 );:::; (f N1 ;f N )], where f 0 = 0 and f N =f s =2. Given H(z), in order to maintain the full scale amplitude V fs as shown in Fig. 2.25, a closed-form expression for G is derived as G = P N n=1 A n P N n=1 A n h max f2[f n1 ;fn] H 2jf fs i; (2.23) which is the inverse of the worst-case weighted full scale range loss due to ltering for each channel 5 . From (2.22), Signal to Noise Ratio (SNR) due to quantization 5 The derivation is similar to those obtained in Appendix B. 54 Fig. 2.25: Signal model for the calculation of G. A i is the full scale range of the individual channel spanning (f i1 ;f i ). noise and the eective bits M e at the output are related as, SNR = 2 M e = v u u t R fs=2 0 G 2 jX(f)j 2 df R fs=2 0 j(E q (f)H e (f))=H(f)j 2 df : (2.24) Note that from (2.23), G is xed. Furthermore, if E q (f) = E (for an M-bit quantizer), q ( R fs=2 0 jX(f)j 2 df)=(E 2 f s =2) = 2 M . Simplifying (2.24) we obtain, M e =M + log 2 (G) 1 2 log 2 " 2 f s Z fs=2 0 H e (f) H(f) 2 df # : (2.25) Ignoring the last term in (2.25) for now, we can see that after ltering and equal- ization, the eective resolution has increased by log 2 (G) bits, in a manner similar to the architecture constructed in Section 2.3. On the other hand, the STF H(z) 55 Fig. 2.26: Two cases of NTF, H e (z), for signals with one high-energy channel. (a) H e (z) is at, (b) H e (z) notches at frequency of high-energy channel. and NTF H e (z) should be co-designed to ensure that the additional error term (2=f s ) R fs=2 0 jH e (f)=H(f)j 2 df does not diminish the aforementioned resolution en- hancement. Preferably, 2 f s Z fs=2 0 H e (f) H(f) 2 df 1: (2.26) While it is dicult to analyze (2.26) generally, it is possible to satisfy for special cases of STF and NTF. Consider a signal that consists of one channel with sig- nicantly higher energy compared with the rest of the signal. A suitable lter in this scenario has a band-stop response at the center frequency of the high-energy channel. 56 Case 1: H e (z) = z 1 (no noise shaping). We resort to a qualitative analysis for this case. As can be seen in Fig. 2.26a, any notch ltering of a high-energy signal, when equalized will amplify the quantization noise. Therefore, (2.26) is not satised. Case 2: H e (z) = (1z 1 ) (rst order noise shaping; 2C;jj = 1). For a notch lter at f = f c , H(z) = (1z 1 ) with = exp 2jf c =f s , implying that M e =M + log 2 (G) (from (2.6)). The two cases of quantization noise shape that are discussed in the proposed scheme are illustrated in Fig. 2.26. Both lter H(z) and H 1 (z) are used in the architecture described in Fig. 2.24, and therefore need to be causal and stable, i.e. the lter H(z) is minimum phase. This implies that poles and zeroes of the lter must lie within the unit circle. Certain important lter transfer functions are excluded. For instance, Finite Impulse-Response (FIR) lters designed using the commonly used windowing method are generally not allowed. As an example, the third-order low-pass FIR lter with a normalized cuto frequency of 0.03, H(z) = 0:047 + 0:453z 1 + 0:453z 2 + 0:047z 3 has roots at z =1;8:54;0:12, whose inverse is unstable. 2.5.2 Practical Considerations The proposed architecture faces some practical challenges: (i) how to determine the frequency and power of the large-energy channel (or in-band blocker) in order 57 Fig. 2.27: (a) Complex lter with variable for frequency-arbitrary notch. (b) Switched capacitor input impedance. to calculate and G respectively, (ii) how to implement to obtain a frequency- arbitraryH(z) andH e (z), (iii) how to extend the architecture to implement several notches, i.e. when several high energy channels are present, and (iv) how to ensure matching between analog and digital inverse lters transfer functions. Detection of blocker frequency and power, and ensuring matching between the lters will be discussed in a subsequent subsection. Assuming an I/Q input, an ar- bitrary notch lterH(z) = (z 1 ) can be created by varying the lter coecient 58 , using the circuit shown in Fig. 2.27. Given the switched-capacitor impedance of Fig. 2.27b, the transfer function of the lter is V out V in = C s1 C f + C s2 C f C s3 C f z 1 j C s4 C f C s5 C f z 1 ; (2.27) where the capacitors C s are varied to vary and . A cascade of such lters, H(z) = Q K k=1 ( k k z 1 ) can be used to implement K notches for K high-energy channels. An arbitrary notch in quantization noise can be implemented using the discrete- time quadrature bandpass modulation technique [46]. With access to the quan- tization noise residue, a Multi-Stage Noise Shaping (MASH) architecture can be used to giveH e (z) = Q K k=1 ( k k z 1 ). The condition (2.26) can thus be satised in the presence of multiple arbitrary high-energy channels. 2.5.3 Discussion The proposed architecture provides several advantages for quantizing multi-channel signals: The signal is recovered entirely across the spectrum, thus being relevant to the carrier aggregation scenario, where all channels irrespective of their relative energy levels may be desired. 59 The front-end analog lter is imperfect; the lter's function is to reduce the full scale range and not to remove specic channels. This imperfect ltering largely relaxes the lter power and nonlinearity requirements. Equalization is simple and real-time, and consumes little power. This elim- inates the need for memory to store data on the chip, and post-processing. Furthermore, no feedback to generate the STF is used in this architecture. The dynamic range requirements of the quantizer is relaxed (M e M + log 2 (G)), as the lter reduces the full scale range of the signal before entering the ADC. However, there are some limitations: The accuracy of the notch lter (refer Fig. 2.27 and (2.27)) is determined by matching of capacitor values. While matching is technology dependent, matching of capacitor ratios is preferred and is used in the proof-of-concept implementation. While proper noise shaping ensured a at quantization noise PSD, the am- plication of thermal noise input referred to the quantizer is not preventable. As will be seen in a subsequent section, the thermal noise oor should be lower than the quantization noise PSD from the desired resolution M e . 60 Fig. 2.28: Details of the proof-of-concept 200 MSPS ltering-ADC implementation based on the proposed architecture. 2.6 A 200 MSPS Blocker Resilient ADC We implement a proof-of-concept, 200 MSPS ltering-ADC, for a 100 MHz multi- channel signal that may include a single high-energy channel between 0-3 MHz. This system is a special case of the generalized architecture, with a single notch at low frequencies, i.e. = 1, implying that only a single-channel implementation is required (instead of an I/Q implementation). The system is summarized in Fig. 2.28;X 1 is the high-energy channel, andX 2 is all other channels consolidated. Here, H(f) =z 1 ( 1) and H e (f) = 1z 1 , giving Y (z) =GX(z) +E q (z) 1z 1 z 1 : (2.28) The high-energy channel may be up to 40 dB stronger than the rest of the signal, mathematically representable as E = En(X 1 )=En(X 2 ) 40 dB, where En(X) = R jX(f)j 2 df is the signal energy in each channel. 61 The gain G, from (2.23), is G = A 1 +A 2 A 1 je 3j=100 j +A 2 je j j : (2.29) Under two-tone test conditions, from (2.25) and (2.28), substituting for En(X 1 ) = A 2 1 and En(X 2 ) =A 2 2 , we obtain M e =M + log 2 " p E + 1 p Eje 3j=100 j +je j j # 1 2 log 2 " 2 f s Z fs=2 0 1z 1 z 1 2 df # : (2.30) Note that the two tone condition represents the worst-case scenario; if signals were instead modulated, the amplitude at the output of the lter would be further limited and (2.30) will still hold true. The choice of > 1 depends on the required resolution. M e is maximized if is closer to 1; however, the equalizing inverse lter H 1 (z) may become unstable. Since (1z 1 )=(z 1 ) has a high pass transfer function, is chosen such that the highest frequency of the blocker lies at approximately the cuto frequency. For a 3 MHz cuto (bandwidth of X 1 ), = 1:1. Substituting in (2.30), we obtain in the worst case of E = 40 dB: M e =M + 3:34 bits. The top-level block diagram of the implementation is shown in Fig. 2.29. In addition to the desired functionality when the input is channelized, the lter can be bypassed (by SW1) for full Nyquist-Rate operation. This mode will serve to detect 62 Fig. 2.29: Top-level block diagram. high-energy channels with coarse quantization initially. The digital information obtained can then be used to detect the frequency of the blockers, which in turn can be used to program the notch location. In this mode, another reconguration switch (SW2) also turns o noise-shaping in the feedback path. All on-chip circuits are dierential and single-ended schematics are shown in subsequent sections for simplicity. 2.6.1 Lossy Dierentiator and Variable Gain Amplier The lter (lossy dierentiator,z 1 ) and variable gain amplication are realized as shown in Fig. 2.30a. H(z) =z 1 is constructed as the sum of two transfer functions ( 1) and (1z 1 ). C 1 =C 3 = 10, to give = 1:1. Since matching 63 Fig. 2.30: (a) Lossy dierentiator and variable gain amplication, (b) Operational amplier, (c) AC response of op-amp, (d) Input refered noise of op-amp. the lter transfer function with its digital inverse is important, this ratio is tightly controlled by capacitor layout. The value of gain, G, is adjusted by varying the ratio C 1 =C 2 as a function of relative channel amplitudes. If V in (full scale) = V DD = 1 V and V ADC (full scale) = 350 mV, after voltage scaling, G = (C 1 =C 2 )V in =V ADC , with G determined from (2.9). The complete transfer function as a function of circuit parameters is 64 Fig. 2.31: (a) Change in STF with . (b) Change in M e with . H(z) = (C 1 =C 2 )((C 3 =C 1 ) + 1z 1 ). In the worst-case blocker scenario, for E = 40 dB, C 1 =C 2 2:5. Mismatch between capacitors C 1 and C 3 , and errors due to the nite gain of the dierentiator op-amp can be modeled as a change in the value of the in the lter. The output is then modied as Y (z) =GX(z) + z 1 z 1 +E q (z) 1z 1 z 1 ; where is an error in . Assuming for simplicity that X(f) is uniformly dis- tributed, the change in M e is M e = 1 2 log 2 " 2 f s Z fs=2 0 1:1 + z 1 1:1z 1 2 df # : 65 Fig. 2.32: Input bootstrap network that shares large bootstrap capacitor for all paths to save area. The eect of 2 [1%; 1%] is plotted for the STF (Fig. 2.31a) and M e (Fig. 2.31b). As seen, the changes are very small. In the next subsection, it will be seen that the value of C 3 chosen is 90 fF (for E = 40 dB), which results in much less than 1% change in the value of for the technology used. All input switches to capacitors C 1 andC 3 are bootstrapped. In order to avoid incurring large chip area by having a bootstrapping capacitor for each path recon- gurable for variable gain G, a common clock doubling and bootstrapping circuit is connected to all input paths using reconguration switches (shown in Fig. 2.32). The design of the lter op-amp (shown in Fig. 2.30b) and values of capacitors C 1 andC 2 , are dependent on ADC system specications, and will be discussed below. 66 Fig. 2.33: (a) The noise shaping pipeline ADC uses two MDACs and a 4-bit Flash ADC, with residue feedback. (b) Since residue calculation for MDAC1 and MDAC2 takes place in alternate clock phases, the op-amp can be shared to save power. (c) Model for the ADC. 2.6.2 Noise-Shaping ADC The ADC is implemented using a 6-bit noise-shaping pipeline architecture (Fig. 2.33) [47]. The ADC is typically implemented with two Multiplying Digital to Analog Converter (MDAC) stages and one 4-bit Flash ADC as shown in Fig. 2.33a. 67 Fig. 2.34: (a) Op-amp schematic, (b) AC response, and (c) Input-refered noise. Fig. 2.35: Functional model of the system with nonidealities included. Let the input capacitance for each MDAC be C. Since the gain of the rst MDAC is 2, the residue of the 4-bit Flash ADC is calculated on C=2, in order to scale the swing during feedback. This charge is later transferred to the rst MDAC, thus providing the requisite delay for a (1z 1 ) NTF. Furthermore, as the two MDAC compute the residue in alternate phases, they are able to share a single op-amp (Fig. 2.33b). An equivalent model is shown in Fig. 2.33c. 68 A functional model for the full system is shown in Fig. 2.35, whered 1 ;d 2 ;d 3 ,d 4 are nonidealities (distortion and noise) introduced at the output of each stage, and q 1 ;q 2 ;q 3 are quantization noise introduced at MDAC1, MDAC2 and the 4-bit ash ADC respectively. The output is expressed as, Y (z) =GX(z) + q 3 (1z 1 ) + (4d 1 d 4 )z 1 + 2d 2 z 1=2 +d 3 4(z 1 ) ; (2.31) giving the conditionj((4d 1 d 4 )z 1 + 2d 2 z 1=2 +d 3 )=(1z 1 )j < q 3 . While this condition is impossible to satisfy closer to f = 0, in order to keep the system quantization noise limited, we must at least have (4d 1 d 4 )z 1 + 2d 2 z 1=2 +d 3 z 1 <q 3 ; (2.32) i.e., the ADC thermal noise should be lower than the desired resolutionM e . From (2.32) op-amp distortion should be specied for an additional 3.34 bits, giving a total of 9.34 bits sinceq 3 =4 is 6 bits. However, equalization provides 3x margin or 9.5 dB for nonlinearity at lower frequencies. Therefore, the lter op-amp is designed for 9 bits distortion (d 1 ) and the ADC op-amp is designed for 8 bits distortion (d 2 ), both with additional 1-bit margins. Noise at the output of the lter has to be specied for 9.34 bits. Certain com- ponents of the noise of the dierentiator are shaped by the lter transfer function (Appendix D). However, noise of the feedback DAC, d 4 is not shaped, and must 69 Fig. 2.36: (a) Comparator schematic. The input transistors are scaled for the Flash ADC, but the schematic is identical; (b) Current-steering DAC unit cell. take into account the requirement from (2.32). The noise at each pipeline ADC stage determines capacitance C. Assuming a high gain compensated 2-stage op- amp and a subsequent stage load of 3C, for both matching and noise performance, C = 120 fF [48]. From derivations in Appendix D, lter capacitances are deter- mined as C 1 = 10C 3 = 900 fF and C 2 = 333 fF, satisfying a 10 bit matching and noise requirement, in the worst case of E = 40 dB. The lter op-amp (Fig. 2.30b) is designed for at response across the 100 MHz bandwidth and requires 29 dB of gain (sucient for up to a 70 dB distortion performance - see Appendix A) and a GBW of 2 GHz. The AC signal and noise responses are shown in Fig. 2.30c and Fig. 2.30d. Due to relatively low gain and high bandwidth requirement, a dierential pair with active loads is used as a design choice. The ADC op-amp requires 54 dB of gain and a GBW of 800 MHz for 70 Fig. 2.37: (a) Behavioural simulation results; (b) Transient noise schematic simu- lation results. settling within an 8 bit resolution at the 2f s rate. The ADC op-amp is implemented as a two stage compensated op-amp for high gain (Fig. 2.34a), with the AC signal and noise responses shown in Fig. 2.34b and Fig. 2.34c. The comparators are designed with cascaded pre-ampliers and sense-amplier ip- ops [35]; Fig. 2.36a shows the comparator schematic for the MDACs, while the comparators for the 4-bit ash ADC use the same circuit but with scaled devices. The unit cell current sources used for the current steering DAC is shown in Fig. 2.36b. The DAC charges capacitor C=2 used for noise shaping, which is then fed back to the rst MDAC. Using a behavioural model for the op-amps and other circuit components the system is simulated with a single tone at 3 MHz (representing the high-energy channel) and a single tone of 40 dB lower energy at 100 MHz (representing all other channels) as input. The behavioral system simulation (Fig. 2.37a) shows an SNDR of 52 dB, with distortion dominated by the third harmonic. A transient 71 noise simulation result of the transistor-level schematic is shown in Fig. 2.37b. The total simulated SNDR is 49 dB, with additional harmonics and inter-modulation products due to distortions. Since the op-amp is shared between two MDAC stages, the layout of the ADC is particularly critical for correct operation. All capacitors C and C=2 are laid out together to enhance matching and improve the quantization noise shaping accuracy. The active input and outputs of the op-amp (node V B and V A in Fig. 2.33b) are laid out in proximity to the inputs and outputs of the MDAC and Flash ADC. In general, oor-planning of the ADCs with shared blocks and feedback can be important for proper functionality. 2.7 Measurement Results The 200 MSPS, ltering-ADC chip is fabricated in a 65 nm CMOS technology (Fig. 2.38), and packaged in a 44-pin 7 7 QFN package for measurement. An ADC driver with a 33 output impedance and 0 dB at passband response is used on the test PCB to convert the single-ended input signal to a dierential signal for the chip, while ensuring that the total amplitude entering the ADC is alwaysV DD = 1 V (p-p, single ended). After data acquisition using a logic analyzer, equalizationH 1 (z) = 1=(1:1z 1 ) in the high-energy channel mode is performed using MATLAB. Spectra are calculated after Blackman-Harris windowing. 72 Fig. 2.38: Chip photograph. The active area is 0.55 mm 2 . To characterize the lossy dierentiator lter and variable gain amplier transfer function, small-signal tests are performed with the ADC is set to the mode; i.e., SW2 in Fig. 2.29 is closed, while SW1 is open. Equalization is not performed in this mode. Measured lter transfer functions for dierent gain settings, normalized to the E = 40 dB setting, show <2 dB deviation from an ideal 1:1z 1 lter (Fig. 2.39), thus conrming that equalization can be performed with reasonable accuracy. The quantizer is then characterized for Nyquist rate performance, with the lter bypassed (SW1 switch closed) and reconguration switch SW2 left open (see Fig. 2.29). Results show a worst case SNDR of 33.1 dB at Nyquist Rate, with an ENOB of 5.2 bits (Fig. 2.40a). This performance remains approximately constant across the entire Nyquist range (Fig. 2.40b). Note that the SNDR is 73 Fig. 2.39: Small signal measurements for dierentiator transfer function show <1 dB deviation from an ideal 1:1z 1 . dominated heavily by the quantization noise, i.e. the SFDR is mostly a function of the quantization noise rather than memoryless nonlinearity of linear circuit blocks, and shows a large variation across the frequency range. Having characterized the lter and ADC separately, noise-shaping is then characterized with the lter still bypassed, however with the reconguration switch SW2 closed. The SNDR for a 0.5 MHz input frequency test is 48.4 dB (ENOB = 7.7) (Fig. 2.41a), for a signal bandwidth of 6 MHz, and a total dynamic range of about 65 dB is obtained (Fig. 2.41b). Up until the -20 dB point, the MDACs have constant output, as all the conversion is performed by the Flash ADC. However, the errors in the MDAC start appearing beyond this point, thus resulting in the decrease in the SNDR as shown in Fig. 2.41b. These errors are better prevented by using multibit MDACs (see Table I in [47]). 74 Fig. 2.40: The ADC characterized for Nyquist performance: (a) Spectrum with 99 MHz input, (b) SNDR and SFDR versus input frequency. Fig. 2.41: (a) Output spectrum (averaged 10 times) in the mode for a 6 MHz bandwidth, with signal at 0.5 MHz. (b) SNR/SNDR versus input amplitude for a 6 MHz bandwidth. To characterize the system under the structured signal mode, two tones with dierent frequencies and amplitudes are applied concurrently at the input. The high-energy signal X 1 spans 0-3 MHz and the low-energy signal X 2 lies within the 75 rest of the bandwidth (Fig. 2.28). Comprehensive measurements, carried out at E = 20 dB and E = 40 dB show that the lter assists to increase the total resolution, while the same 6-bit ADC is used (Fig. 2.42a). The total SNDR is calculated from the PSD as Total SNDR = Power of X 1 + Power of X 2 Noise Power (0-100 MHz) : Measurement results show increasing total SNDR with increasing energy dier- ences, in order to improve the resolution of the low-energy channels. Total SNDR decreases with decreasing E = 20 dB, till the point when Nyquist performance is achieved when signals have no energy dierences and the dierentiator is bypassed (SW1 closed). If X 1 is considered a blocker, we are interested in the SNDR of the desired channel X 2 only. This result, plotted in Fig. 2.41b, shows that the lter assists to provide additional total resolution, such that X 2 is recoverable in spite of being low energy. Two output spectra are shown in Fig. 2.42; one with the low-energy signal at the highest signal frequency (X 2 located at 100 MHz) and the other adjacent to high-energy signal at 3 MHz (X 2 located at 3.26 MHz). Func- tionally, this measurement shows that signal recovery is possible even with adjacent channels as the entire signal is recovered. Most of the distortion in the spectrum is caused by IM tones and harmonics. The measured SNDR at the highest input frequencies is 45.3 dB, close to as expected from schematic simulations (Fig. 2.38b). 76 Fig. 2.42: Measured SNDR in the channelized mode versus the frequency of the low-energy tone, X 2 . (a) The total SNDR, when both channels are desired; (b) SNDR of low-energy signal X 2 only, if X 1 is considered a high-energy blocker. The power breakdown of the chip is as follows: lter - 2.2 mW, ADC - 3.5 mW, DAC - 173 W, miscellaneous circuits - 500 W. The total power consumed is 6.4 mW. The power consumption of the lter remains lower than that of the ADC, a benet of imperfect ltering and lter-ADC co-design. On the other hand, the resolution improves regardless. A useful performance metric to bet- ter understand the power eciency of the ADC is the gure-of-merit: FOM ADC = Power ADC =(2 ENOB 2B) in units of fJ/lvl. For the Nyquist rate mode, the total power consumption is 3.5 mW, giving FOM ADC = 474 fJ/lvl. In the structured signal mode however, the total system power consumption is considered (6.4 mW). Using the SNDR at the highest input frequency, FOM Filter+ADC = 173 fJ/lvl at the 40 dB setting, an 2.7x improvement from Nyquist rate performance. This 77 Fig. 2.43: (a) Output spectrum with low-energy signal at 3.26 MHz (oset of 260 KHz). Results here show that the ADC is capable of full signal recovery after equalization; (b) Output spectrum with low-energy signal at highest frequency, the worst-case. improvement in FOM stands as a validation of the benets of discrete-time ltering and equalization. Table 2.1 summarizes the performance in comparison with recently published blocker-tolerant ADCs, assuming the high-energy channel is a blocker. The FOM based on measurements of the system is comparable with respect to other ltering oversampling ADCs. More importantly, in the proposed architecture, the high- energy signal (e.g., a blocker), and low-energy signal may be adjacent in frequency, due to discrete-time ltering and equalization. As a result, the relative blocker oset f o =BW is zero. 78 Table 2.1: Comparisons with Filtering-ADCs in Literature [38] [39] [40] [41] [42] [43] This Work Nyq. Blkr. BW (MHz) 1 10 9 2 20 10 100 6 100 f s (MHz) 64 250 288 256 500 480 200 Filter Order (N) 1 - 3 2 2 3 - - 1 Oset (f o ) (MHz) 4 15 3 3 29 30 - - 0 Rel. Oset (f o =BW) 4 1.5 0.33 1.5 1.45 3 - - 0 E Measured (dB) 30 24 - 63 - 48 - - 40 SNDR (dB) 59.0 65 58.1 74.4 64.0 70.3 33.1 48.4 45.3 ENOB (bits) 9.8 10.5 9.6 12.4 10.3 11.4 5.2 7.7 7.5 Power (mW) 2.0 18.0 5.4 5.0 17.1 14.3 3.5 4.2 6.4 FOM (fJ/lvl) 1373 620 457 291 339 267 474 1634 173 Active Area (mm 2 ) 0.14 1.35 0.13 0.33 0.43 0.17 0.55 V DD (V) 1.8 1.2 1.2 1.4 - 1.2 1.0 Technology (nm) 180 130 65 130 90 90 65 2.8 Conclusions In this chapter we introduce ltering-ADC architectures that aim to resolve the tradeos between the analog lter and the quantizer in the receiver baseband chain. We rst show that ltering prior to the quantizer is benecial for an energy ecient system, however, new architectures are still needed to make signal conditioning scalable and exible, particularly for demanding modern applications such as carrier aggregation. After providing a theoretical background, we develop two ADC architectures that both use signal structure and equalization to improve energy eciency with- out sacricing recongurability. The two architectures explore feedback and feedfor- ward mechanisms where the lter design is simpler or entirely eliminated, while the quantizer's dynamic range requirements are relaxed. Theory and measurements on a proof-of-concept blocker-resilient ADC based on the feedforward technique show 79 that the architectures developed are energy ecient in comparison to prior tech- niques. Furthermore, the exercise also enabled us to realize ltering-ADCs using the mixed-signal processor paradigm that was envisioned in Chapter I. Analog and mixed-signal baseband system power eciency can be vastly im- proved by co-designing lters and ADCs, when the input signal is multi-channel. The generalized theory and ADC architectures presented in this chapter can possi- bly lead to more interesting silicon implementations and applications, and further study of signal structure and energy ecient systems that exploit such properties. 80 Chapter 3 Semi-Digital IIR Filters for RF Channel Selection 3.1 Channel Selection at RF Combining the ltering-ADC architectures presented in Chapter 2 with the SDR paradigm can provide a complete low power solution for a receiver that performs band selection, frequency downconversion, channel selection and quantization in a syngeric manner, as alluded to in Chapter 1 (see also Fig. 1.6). Consider rst a conventional receiver performing band selection. A fundamental requirement in such a receiver, as elucidated in Chapter 1 is the removal of the xed- frequency front-end lter, thus making the receiver programmable and tunable (see Fig. 1.3). With the removal of the RF front-end band-select lter in the conventional receiver, the rst active stage, i.e. the LNA must be linear enough to hand the out-of-band interferers. The LNA linearity is oftentimes determined by its output voltage swing capability. To avoid large voltage swing at its output, the LNA may be replaced with a Low Noise Transconductance Amplier (LNTA), 81 Fig. 3.1: Impedance upconversion in the SDR: (a) conventional receiver with front- end lter. (b) Removing the front-end lter and using an LNTA instead of the LNA allows for current mode operation at the output of the LNTA. The baseband TIA impedance is then frequency upconverted to appear at the output of the LNTA, thereby ltering the swing due to out-of-band interferers at RF. which provides an output current (Fig. 3.1). With a passive mixer, this current is downconverted and is ltered by a Trans-Impedance Amplier (TIA). A single pole baseband bandwidth for the TIA with a 20 dB/decade rollo will determine band ltering. However, in this case current mode operation and the use of passive mixers allows the frequency upconversion of the baseband impedance Z BB to the center frequency as set by the local oscillator. Therefore, Z RF (f) =Z BB (ff RF ), and the swing due to out-of-band interferers is reduced at the output of the LNTA, as determined by the baseband [8]. 82 Fig. 3.2: Replacing the SDR baseband with the conceptual ltering-ADC for chan- nel selection, amplication of desired signal and quantization. Apart from blocker swing reduction at the output of the LNTA in spite of no output lter, one key advantage from the current mode SDR approach is that frequency upconversion of impedance to RF is can be performed at any frequency, i.e. the front-end ltering is now programmable. Furthermore, front-end lters in the conventional receiver are bulky o-chip components (due to higher order ltering and use of high quality factor components), while the SDR is now fully integrated on chip. The baseband impedance upconversion concept can be used in conjunction with the ltering-ADC from Chapter 2 to provide a complete programmable, power- ecient solution for the receiver, as shown in Fig. 3.2. Here the TIA is implemented as a simple op-amp with feedback RC network [8, 10], and the passive mixer is shown as a switch. A direct RF-to-baseband ADC as envisioned in Chapter 1 (Fig. 1.6) should provide channel ltering at the output of the LNTA. While the 83 combination of current-mode front-end and passive mixer provides band selection, channel selection at the front-end would require a higher order lter, that eliminates adjacent channels. In other words, the question now remains whether one may combine the benets of LNTA and passive mixer (oering ltering at the front- end) and ltering-ADC (oering ltering within the ADC) in one structure. 3.1.1 Eliminating Analog Filters Consider substituting the conceptual ltering-ADC block diagram as shown in Fig. 3.2 with the ltering-ADC architecture proposed in Chapter 2 from Fig. 2.11, with some minor rearrangements for the digital lter 1 . The resulting architecture is shown in Fig. 3.3a. Note that as explained in Chapter 2, in the ltering-ADC the feedback lter H(z) eectively eliminates the undesired signals (e.g., blockers) at the input to the gain stage G, thereby providing some level of channel ltering without having an analog lter. We modify this architecture to replace the voltage DAC with a current DAC, and rather feedback the current at the front of the TIA, as shown in Fig. 3.3b. With this modication, the aforementioned channel ltering is also frequency upconverted as set by the RF clock frequency to the output of the LNTA by the passive mixer, thus providing channel selection at the baseband. The advantages of recongurable digital feedback ltering using H(z) are now availed at the front-end. 1 In Fig. 2.11, the digital lterz 1 =H(z) is moved to the feedback to give an eective digital l- terz 1 H fb (z)=H(z). Henceforth, for the sake of this chapter we simply representz 1 H fb (z)=H(z) as H(z), with no relation to the lter H(z) from Section 2 of Chapter 2. 84 Fig. 3.3: (a) Replacing the receiver baseband with the ltering-ADC architecture discussed in Chapter 2 (Fig. 2.11), (b) translating the baseband impedance to RF using a passive mixer. Fig. 3.4: Model of the receiver in Fig. 3.3b. We model the receiver in Fig. 3.3b as shown in Fig. 3.4. Assume that added quantization noise due to the ADC, e(n) is small. From Fig. 3.3b, the baseband impedance Z BB (f), is given as Z BB (f) = R A(1 +sRC) 1 1 + g m2 RG 1+sRC H(z)z 1 ! ; (3.1) 85 where A is the op-amp open-loop gain, R and C are the feedback RC network parameters, G is the gain of the VGA, and g m2 is the transconductance of the feedback current DAC. Furthermore, s = 2jf and z = 2jf=f s where f s is the sampling clock frequency. A single z 1 delay is introduced due to sampling in the ADC. The baseband impedance is translated to RF through the passive mixer as Z RF (f) =Z BB (ff RF ) = R A(1 + 2j(ff RF )RC) | {z } Band Selection (SDR) 1 1 + g m2 RG 1+sRC H(z)z 1 ! ff RF | {z } Channel Selection (Filtering-ADC) ; (3.2) where f RF is the frequency of the local oscillator controlling the passive mixer. The rst term in (3.2) represents the typical band selection obtained from the frequency translation of an RC lter to RF in the SDR [8]. Assuming the second term represents a low-pass lter, it represents the channel selection obtained from the ltering-ADC [22] as explained in Chapter 2. Both terms are upconverted to appear as a bandpass response to the transconductance of the LNTA represented by g m1 , thereby eliminating the undesired bands and channels at the front-end. The output voltage response, including the quantization noise E(z) is given as: V out (z) = z 1 1 + g m2 RG 1+sRC t=ts H(z) g m1 RGV in (f +f RF ) (1 +sRC) t=ts +E(z)z 1 : (3.3) 86 The input is downconverted and quantized while being subject to both the band selection and channel selection transfer functions. Given the impedance has a similar transfer function after frequency translation, it is useful to note the voltage at the output of the LNTA (node V x ) as V x (f) = R A(1 + 2j(ff RF )RC) g m1 V in (f) (g m2 E(z)H(z)z 1 ) ff RF 1 + g m2 RG 1+sRC H(z)z 1 ff RF ; (3.4) which is equivalent toV x (f) =g m1 V in (f)Z RF (f) from (3.2) when quantization noise E(z) is small. As can be seen, both band selection and channel selection transfer functions are available at the output of the LNTA, thereby reducing the nonlinearity and providing said functionality at RF itself. In certain applications such as the low-power receivers for personal communica- tions [49], the receiver sensitivity requirements are quite relaxed, implying that gain can be provided almost entirely by the rst stage consisting of g m1 R. Therefore, for the sake of the application concerned, in subsequent analysis and gures, we will remove the VGA, i.e. G = 1. Also, a fundamental assumption is that band selection ltering is of higher bandwidth then that obtained from channel selection: 1=2RC Channel Bandwidth due to H(z). Consolidating these assumptions, one may rewrite (3.3) as V out (z) g m1 RV in (f +f RF ) (1 +sRC) t=ts z 1 (1 +g m2 RH(z)z 1 ) + E(z)z 1 1 +g m2 RH(z)z 1 : (3.5) 87 Fig. 3.5: Summary of proposed receiver architecture. Both band selection and channel selection analog lters are eliminated and accommodated for by the SDR and ltering-ADC techniques. The primary assumption in the receiver shown in Fig. 3.3b remains that the baseband signal is oversampled for the bandwidth of interest, due to use of the ltering-ADC from Chapter 2. From (3.5), it is notable that the quan- tization noise E(z) is also ltered with the channel selection transfer function 1=(1 +g m2 RH(z)z 1 ). Therefore, out-of-band quantization noise is also ltered given the system is oversampled, thus relaxing some ltering requirements for the decimation lter after quantization. To summarize the proposed receiver architecture, the nal transformation from the conventional receiver (without VGA) to the proposed architecture is shown in Fig. 3.5. As is seen, all analog lters are eliminated, while their functionality 88 is retained by using both the passive mixer impedance translation and ltering- ADC techniques. As was discussed earlier, channel selection implies that the low pass lter created by H(z) should necessarily be a high order lter with sharp rollos. While our proposed implementation includes the quantizer/ADC and is a mixed-signal approach, channel selection and interference removal using active analog feedback has been proposed using rst order feedback lters in [50] (narrow- band systems), [51] (wideband systems) and second order feedback lters in [52]. While the above analog systems do provide channel selection, higher order ltering invariably consumes a lot of power and area due to analog components, and are potentially unstable. In all the above receivers, the feedback lter (equivalent to H(z) in our proposed architecture) is a high-pass lter that detects the inteference and cancels it using feedback. Keeping in line with the same intuition, we would require to design a high passH(z) as well. However, a more complete theoretical in- terpretation in now provided for the design ofH(z) such that 1=(1+g m2 RH(z)z 1 ) is a desired low pass channel selecting lter. 3.1.2 Semi-Digital IIR Filter Interpretation Innite Impulse-Response (IIR) lters are often used to provide low cost digital ltering of signals after quantization. While a typical digital IIR lter contains both feedforward and feedback coecients, for the sake of this thesis we consider 89 only lters with feedback coecients with a lter transfer function of the form [53] V out (z) V in (z) = Kz 1 1 + P N n=1 n z n ; (3.6) whereK is a normalizing gain andN is the lter order. The selection of the coe- cients n will provide the appropriate low pass transfer function. The methodology for choosing the coecients starts from an analog low pass lter (in this thesis we choose Butterworth lters) whose cuto frequency f c and order N is provided. With an intended sampling frequency f s , the bilinear transform [53] gives the cor- responding digital lter of normalized cuto frequency f c =f s . With f c =f s = 0:1, the digital lter transfer functions F (z) are 2 , N = 1 :F (z) = 0:49z 1 1 0:51z 1 ; N = 2 :F (z) = 0:27z 1 1 1:14z 1 + 0:41z 2 ; N = 3 :F (z) = 0:14z 1 1 1:76z 1 + 1:18z 2 0:28z 3 : These transfer functions are plotted in Fig. 3.6. Note that asN increases, the lter roll-o improves afterf c =f s = 0:1. At the same time, the normalizing coecientK decreases exponentially (0:14 0:27=2 0:49=4). To see why this happens, it is important to note that at DC, z = 1 and 1 + P N n=1 n =K to give unity response 2 The bilinear transform also results in zeros at f s =2 to maximize rejection. These zeros are removed from the transfer functions to give lters with only feedback coecients. 90 Fig. 3.6: Digital IIR lters with only feedback coecients. The simulation results are shown for lters order N = 1; 2; 3. jF (z)j = 1. At the highest frequencyf s =2,z =1 andjF (z)j =K=(1+ P N n=1 j n j). Therefore, in order to improve rejection exponentially, the ratioK=(1 + P N n=1 j n j) has to reduce exponentially thus resulting in smaller values for K with increasing N. The small value of K < 1 behaves as a net attenuation, and is detrimental to the receiver as will be seen later. The IIR lter is simply constructed using digital delays and digital lter coef- cients as shown in Fig. 3.7a (the construction is shown only for three feedback coecients). This visual is modied to produce the compact representation shown 91 Fig. 3.7: Constructing the IIR lter with only feedback coecients: (a) Simple construction showing three coecients. (b) Construction with the representation of H(z), an FIR lter. Fig. 3.8: Transforming the digital IIR lter to a mixed-signal IIR lter, with the introduction of a quantizer. in Fig. 3.7b with the introduction of the feedback lter H(z); F (z) and H(z) are related as F (z) = Kz 1 1 + P N n=1 n z n = Kz 1 1 +H(z)z 1 ; (3.7) whereH(z) = P N n=1 n z (n1) , is a Finite Impulse-Response (FIR) lter with only feedforward coecients. While IIR lters are usually digital, one may visualize a \mixed-signal" version of the IIR lter. This is constructed by simply adding a quantizer within the loop 92 in Fig. 3.7b to result in the control system shown in Fig. 3.8. Since quantization noise is assumed random and added, the output response is V out (z) = (KV in (f) +E(z))z 1 1 +H(z)z 1 ; (3.8) whereE(z) is the quantization noise. The coecientK is now an analog amplier, and a DAC is required in the feedback path after the digital FIR lter H(z). A further transformation now converts the system to a current mode mixed-signal IIR lter, as shown in Fig. 3.9. The input amplier is a transconductanceg m1 , and the feedback DAC is a current DAC of transconductanceg m2 . The current is converted to voltage using a TIA with a bandwidth determined by the feedback RC network. The transfer function is now modied to V out (z)= z 1 1 + g m2 R 1+sRC t=ts H(z)z 1 ! g m1 RV in (f) (1 +sRC) t=ts +E(z) z 1 1 +g m2 RH(z)z 1 g m1 RV in (f) (1 +sRC) t=ts +E(z) : (3.9) The approximation is made with the argument that 1=2RC f c , i.e. the IIR lter cuts o at a frequency much lower than the rst pole of the TIA. Comparing (3.9) with (3.8), we deduce that g m1 R =K and g m2 R = 1 to obtain the same IIR lter. A nal transformation introduces a passive mixer after the transconductance stage as shown in Fig. 3.10, thus allowing for frequency translation of impedance 93 Fig. 3.9: A current mode mixed-signal IIR lter. Fig. 3.10: A nal transformation of the current mode mixed-signal IIR lter intro- duces a passive mixer to make the control system identical to the one introduced in Fig. 3.5. looking into the baseband. The system is now identical to the one introduced in the previous subsection (see Fig. 3.5). Iff c =f s is small and theH(z) is a high order lter (i.e., largeN), channel selection is available at the front-end transconductance output, as explained in the previous subsection. The FIR feedback lter H(z) may be implemented together with the DAC in a semi-digital manner as shown in the transformation in Fig. 3.11 (reminiscent of the digital IIR lter shown in Fig. 3.7a), with the coecients simply being added to the individual DAC transconductances. We term this resulting structure a semi- digital IIR lter. Semi-digital feedback DACs for CT oversampled ADCs were rst introduced to reduce the eect of clock jitter in the feedback DAC [54], and extensively used in integrated circuit implementations [41, 55]. The possibility of 94 Fig. 3.11: The feedback lter and DAC can be implemented together as an FIR DAC. the use of a semi-digital FIR DAC for feedback in oversampled ADCs in order to change the Signal Transfer Function (STF) was also alluded to in [43]. There is a key advantage of using the semi-digital structure: the DAC word-length is now equal to the word-length of the quantizer, and not instead determined by the word length at the output ofH(z) if an explicit digital lter were used. This allows for a modular design of the DAC with just the transconductance being changed to re ect the appropriate coecient n . 95 Fig. 3.12: The ADC is replaced with a ADC to give a CT 3.2 CT Receiver with Semi-Digital IIR STF For the receiver shown in Fig. 3.11, the cuto frequency f c =f s 1, i.e., the channel selection bandwidth is much smaller than the sampling frequency, and the system is a net oversampled system. Typically, oversampled systems can benet from additional quantization noise shaping for f f c , and the receiver does not provide for noise shaping as is clear from the system response (3.5). The receiver can be modied to provide rst-order noise shaping using the transformation shown in Fig. 3.12. The ADC (including the sampling delay) can be replaced by a rst-order ADC by providing an alternate feedback path of 96 Fig. 3.13: Model for current mode, rst order CT ADC with NRZ feedback DAC. transconductanceg m2 . Using the impulse invariance transform [56,57],C =g m2 =f s . To reduce the total number of DACs, a nal modication is made to change the coecient of the rst tap to ( 1 + 1), giving the nal control system as shown in Fig. 3.12, which is a CT receiver with a semi-digital IIR signal transfer func- tion. It is noteworthy that the band selection transfer function is still preserved due to the inbuilt anti-aliasing properties of the CT ADC [57]. The current mode rst-order CT is modeled as shown in Fig. 3.13. The sampler introduces a single delay ofz 1 , the quantization noise is added and random and the feedback DAC is assumed to have a Non-Return-to-Zero (NRZ) pulse shape. The transfer function is given as [57] V out (z)= (g m1 =Cf s )z 1 1 (1g m2 =Cf s )z 1 sin(f=f s ) (f=f s ) V in (f) t=ts + (1z 1 ) 1 (1g m2 =Cf s )z 1 E(z): (3.10) The sinc function from the integration of the NRZ pulse shape provides anti- 97 aliasing ltering for the signal with notches at f =f s ; 2f s ;:::. Ifg m2 =Cf s , (3.10) modies to V out (z) = g m1 g m2 z 1 sin(f=f s ) (f=f s ) V in (f) t=ts + (1z 1 )E(z); (3.11) i.e. the transfer function includes rst-order shaping for the quantization noise, and sinc ltering for the input signal. For the proposed system with the lter H(z) in the feedback as well as the CT ADC (Fig. 3.12), the transfer function modied from (3.10), after frequency translation is V out (z)= (g m1 =Cf s )z 1 1 + (g m2 =Cf s )H(z)z 1 sin(f=f s ) (f=f s ) V in (f +f RF ) t=ts + (1z 1 ) 1 + (g m2 =Cf s )H(z)z 1 E(z): (3.12) If g m2 =Cf s , (3.12) modies to V out (z)= (g m1 =g m2 )z 1 1 +H(z)z 1 | {z } Channel Selection 2 6 6 6 4 sin(f=f s ) (f=f s ) | {z } Band Selection V in (f +f RF ) 3 7 7 7 5 t=ts + (1z 1 ) 1 +H(z)z 1 E(z): (3.13) Consider the example IIR lters from the previous subsection (simulation results shown in Fig. 3.6). Here f c =f s = 0:1, while the rst notch of the band selecting lter appears atf s . Therefore, the two lters are still relatively independent of each 98 other. Channel selection at RF by upconverting the anti-aliasing transfer function of CT ADCs has been shown in works earlier [58, 59]. While the above works show that the passive mixer can upconvert the transfer function and impedance of the ADC, our approach produces independent band selection and channel selection lters as shown from the theory above. In other words, the integrator in the feedforward path provide band selection as is conceptually common with [58] and [59], while the semi-digital IIR lter independently performs channel selection. For the rst order ADC, the additional resolution due to quantization noise is a function of the oversampling ratio, OSR. For an M-bit quantizer in a modulator, the eective resolution M e (for large OSR) is given as M e =M + log 2 2 4 s 3 (OSR) 3 2 3 5 : (3.14) Consider the case with the quantization noise shaping as shown in (3.13); the denominator term 1 + H(z)z 1 at low frequencies (i.e., large OSR) is equal to 1 + P N n=1 n = K < 1 (see (3.6) and subsequent explanations). Therefore E(z) is amplied by 1=K. As a result, for the same full-scale range at the input of the quantizer V fs , (3.14) modies as M e =M + log 2 2 4 K s 3 (OSR) 3 2 3 5 : (3.15) 99 Fig. 3.14: Model for a generalized DT ADC with both feedforward and feedback lters. This unnecessary amplication of quantization noise is undesirable. Techniques to compensate for this eect will be discussed in a subsequent section. On the other hand, consider the signal transfer function within the channel from (3.13). The DC gain of the desired signal is g m1 =Kg m2 obtained using the same analysis for the quantization noise. Therefore, for a desired amplitude at the output of the integrator V fs (see Fig. 3.12c), the RF LNTA g m1 can instead be designed for an eective transconductance of Kg m1 . The remainder of the gain is obtained from the feedback of the IIR lter. 3.2.1 Extension to Multiple Orders The STF of a modulator can also be modied using the feedforward lters. While the feedforward lter considered in Fig. 3.12c is an integrator without an inherent STF, a generalized Discrete-Time (DT) with both feedforward and feedback lters is shown in Fig. 3.14. A DT structure is considered for simplic- ity; the CT equivalent may be obtained by simply using transformations such as the impulse invariance transform [56,57]. 100 The transfer function of the modulator shown in Fig. 3.14 is V out = V in (z)z 1 Q N n=1 H n (z) +E(z) 1 + P N n=1 H fb;n (z) Q N k=n H k (z) z 1 : Each feedforward lter H n (z) is a rst order lter with a single pole. The case described in Fig. 3.12c is when N = 1, giving V out = V in (z)H 1 (z)z 1 +E(z) 1 +H 1 (z)H fb;1 (z)z 1 ; withH(z) = 1=(1z 1 ) andH fb;1 (z) = ( 1 + 1) + 2 z 1 . As an example that has both feedforward and feedback ltering, consider a special case when N = 2, i.e. V out = V in (z)H 1 (z)H 2 (z)z 1 +E(z) 1 +H 1 (z)H 2 (z)H fb;1 (z)z 1 +H 2 (z)H fb;2 (z)z 1 : ChoosingH 1 (z) = 1=(1 1 z 1 ) andH 2 (z) = 1=(1 2 z 1 ), we simplify to obtain V out = V in (z)z 1 + (1 1 z 1 )(1 2 z 1 )E(z) (1 1 z 1 )(1 2 z 1 ) +H fb;1 (z)z 1 + (1 1 z 1 )H fb;2 (z)z 1 : If H fb;1 (z) and H fb;2 (z) are constants, the result is a second-order lter only due to the feedforward lters. If a 3rd order lter, z 1 =(1 + 1 z 1 + 2 z 2 + 3 z 3 ) is desired, we solve (assume for simplicity H fb;2 (z) = 1) (1 1 z 1 )(1 2 z 1 ) +H fb;1 (z)z 1 + (1 1 z 1 )z 1 = 1 + 1 z 1 + 2 z 2 + 3 z 3 ; 101 giving H fb;1 (z) = ( 1 + 1 + 2 1) + ( 2 + 2 1 2 )z 1 + 3 z 2 : Higher order lters may be accordingly designed. Note that the total ltering order has to be greater than or equal toN. The noise shaping is still aected only by the feedforward ltersH n (z). On the other hand, RF upconversion of the lter transfer function (with the addition of a mixer) takes place only due to the feedback lter coecients as explained previously, and the rst feedforward lter [60]. Higher order loops with feedback IIR lter coecients pose the same sta- bility issues as regular higher order ADCs. On the one hand, linear stability should be ensured by making sure all poles and zeroes of the transfer function at every node lie within the unit circle. However, this is true only if signal inde- pendent, linear addition of multi-bit quantization noise is considered. If the lter order increases, clipping at the output of any feedforward integrators will aect the stability [57]. Analysis in such cases involves hard nonlinearity with memory eects, and due to the diculties posed, extensive simulations are performed to ensure stability. Another brute force technique used is to ensure that full scale amplitudes at every node are much smaller than the supply voltage. Some progress in analyzing stability issues due to quantizer nonlinearity has been made in 1-bit modulator cases, in [61] and [62]. 102 3.2.2 Direct Quantizing Receivers in Literature Although CT ADCs have been described in theoretical detail with integrated implementations available for over 30 years [63, 64], the ltering-CT ADC is a relatively recent invention [38{43], with the rst concept and integrated circuit implementation shown in [38]. Please see Chapter 2, Section 5 for more details on the advantages and disadvantages of these architectures. The use of current-mode input with a passive mixer to convert the ltering- CT ADC into a direct conversion, ltering and quantizing receiver is a very recent development, with few integrated-circuit implementations as of the writing of this thesis [58{60]. It is notable, that all the implementations in literature use a current mode rst stage for the ltering-CT ADC, i.e. replacing the rst integrator with the LNTA, passive mixer, and TIA, so that ltering is seen at RF. The rest of the ltering takes place only at baseband (i.e. the impedance is not upconverted except for the rst integrator), and the system behaves as an SDR only for one order of ltering. The key distinguishing feature of the proposed system is its ability to provide RF ltering (i.e. ltering at the output of the LNTA), for all orders of ltering in the feedback. As shown in the previous subsection, with extension to multiple orders additional ltering may be used in the feedforward path, however, this would not be available at RF. Impedance upconversion would not be available for any lter in the feedforward path, except for the rst integrator. 103 3.3 Quantizing Receiver Design Having established the theory, details of the implementation from a receiver stand- point will now be discussed. The toplevel schematic of the current implementation is shown in Fig. 3.15. To show the proof of concept for channel selection, only two coecients are used in the feedback FIR lter, i.e. 1 and 2 . Explicit impedance matching was performed at the front of the LNTA using 50 resistors, thereby incurring a 3 dB Noise Figure (NF) automatically. While this is generally not pre- ferred, as will be seen for the purposes of the application under concern the noise gure will still fall under requirements. The implementation is fully dierential and has the in phase (I) and quadrature phase (Q) paths as shown. Frequency downcon- version is performed using 25% duty-cycle, 4-phase clocks that control RF switches, at the tunable frequency f RF [65]. Two-phase baseband clocks are required at the ADC at sampling frequency f s . The receiver provides 2nd order channel ltering at RF, however uses only a single op-amp, i.e. 40 dB/decade is obtained with the use of just a single op-amp. This feature is unlike implementations in [58] and [59], where the the rollo is (number of op-amps) 20 dB/decade. The mixed-signal approach in the proposed receiver scales better than op-amps that necessarily require large transistors for large gain. Thus, the proposed architecture has potential to save power in an integrated circuit implementation. 104 Fig. 3.15: Toplevel schematic of the receiver. The implementation uses the following parameters: f RF = 2 GHz, f s = 200 MSPS, 1 =1:14 and 2 = 0:41 (for f c = f s =10 = 20 MHz). From (3.13), assuming g m1 = g m2 = 1 mS for the sake of conceptual simulation, implies C = g m =f s = 5 pF. The output voltage is given by V out (z)= sin(f=(200 10 6 )) (f=(200 10 6 )) (CG)V in (f + (2 10 9 ))z 1 1 1:14z 1 + 0:41z 2 + (1z 1 )E(z) 1 1:14z 1 + 0:41z 2 ; (3.16) where CG is the conversion gain due to the mixer 3 . Using a behavioral model with ideal components and simulating in Cadence using a PSS+PAC setup, the system 3 Henceforth, the sampling detail of analog signals is not shown in equations for simplicity. 105 Fig. 3.16: STF and NTF of behavioral model of receiver simulated in Cadence. responses for both STF and NTF are shown in Fig. 3.16a. The plot is shown for frequency oset from f RF . As is expected from analysis earlier, the noise transfer function is ltered and amplied by 1=K = 3:70 and the signal transfer function is ltered and amplied by the value p 2=K = 1:67. The additional factor p 2= is due to the conversion gain of the 25% duty-cycle mixer. Note that the STF simulation also includes the inherent band selection sinc ltering; this does not aect the DC gain, and only marginally aects the amplitude response at Nyquist frequency f =f s =2. 106 3.3.1 Compensation for Quantization Noise Amplication Amplication of quantization is undesirable and it is preferred that given the full scale amplitude at the input to the quantizerV fs , the noise shape is reduced to just have the shape (1z 1 ) and not (1z 1 )=K. A technique to achieve this reduction value could be done using the transformation: E(z)!E(z)(1 (1K)z 1 ); (3.17) i.e. a further shaping of the quantization noise such that the DC value of noise is scaled by K. In the case of the current implementation, E(z) is transformed to E(z)(1 0:73z 1 ). The desired transfer function modies from (3.16) as V out (z)= sin(f=(200 10 6 )) (f=(200 10 6 )) (CG)V in (f + (2 10 9 ))z 1 1 1:14z 1 + 0:41z 2 + (1z 1 )(1 0:73z 1 )E(z) 1 1:14z 1 + 0:41z 2 : (3.18) The noise shape is equivalently second-order; thereby, a second-order loop is re- quired. Thus, the quantizer with single delay for sampling shown in Fig. 3.12c should be modied. On the other hand, the requirements for the IIR lter dictates that any modication to this quantizer should be done delay-free, i.e. without addi- tional delays introduced apart from that of sampling. The modication proposed is shown in Fig. 3.17 using the behavioral model for the quantizer. Solving the loop, the transformation (3.17) is realized. The internal loop in the modied quantizer in 107 Fig. 3.17: Modifying the quantizer in the proposed architecture to include a delay- free loop with integrator, changes the quantization noise transfer function. Fig. 3.18: Implementation of delay-free lossy noise shaping ADC. Fig. 3.17 is a lossy integrator with a feedforward gain 1K (a lossless integrator will have a feedforward gain of unity). To realize this transformation along with the sampling delay as a lossy noise- shaping ADC, we use the circuit shown in Fig. 3.18. In the diagram, the transfer function H I (z) of the low-Q integrator with op-amp gain A LF is given as [66] H I (z) C 2 C 3 1 1 A LF 1 + C 2 C 3 z 1=2 1 (1C 2 =A LF C 3 )z 1 ; 108 for large A LF . If C 3 =C 2 (1 + 1=A LF ), we have H I (z) 1 A LF + 1 A 2 LF z 1=2 1 (1 (A LF + 1)=A 2 LF )z 1 (1 1=A LF )z 1=2 1 (1 1=A LF )z 1 ; (3.19) for large A LF . Assuming C 1b C 3 , the output of the integrator is (V in (z) V out (z))H I (z)z 1=2 . Therefore, the voltage across C 1a at the end of the cycle 1 is V in (z) (V in (z)V out (z))H I (z)z 1=2 = V in (z) (1 1=A LF )V out (z)z 1 1 (1 1=A LF )z 1 ; which is compared with V ref , the quantizer reference voltage at the comparator in cycle 2 . Assuming for the sake of simplicity that V ref = 0 and quantization noise is added, we have V in (z) (1 1=A LF )V out (z)z 1 1 (1 1=A LF )z 1 +E(z) =V out (z); solving which we obtain V out (z) =V in (z) + (1 (1 1=A LF )z 1 )E(z): As can be seen, if A LF = 1=K, we obtain the transformation as desired in (3.17), without incurring any delay in the signal path. However, as for an ADC in a 109 loop, the sampling and update process creates an additional delay. Therefore the net transfer function is V out (z) =V in (z)z 1 + (1 (1 1=A LF )z 1 )E(z): For the current implementation the value of K = 0:27, implying that the op- amp gain A LF = 3:70, a very low value. Thus, the implementation of this lossy noise-shaping ADC can potentially be very low power. The control technique to reduce quantization noise using low power lossy integrators has been used earlier in the context of noise-shaping Successive Approximation Register (SAR) ADCs earlier [67,68]. A behavioral model of the lossy noise-shaping ADC with C 1 =C 2 = 6, C 2 =C 3 = 1:67 and A LF = 3:70 is constructed and placed in the receiver shown in Fig. 3.15 and the quantization noise response is simulated again using a PSS+PAC setup. The quantization noise response is plotted as shown in Fig. 3.19. As can be seen, the reduction in the quantization noise at DC is around 11.5 dB lower, conrming the eectiveness of the technique described. The complete receiver now including the lossy noise-shaping ADC, with all signal inputs and outputs and circuits blocks (minus bias and digital encoding/buering) is shown in Fig. 3.20. 110 Fig. 3.19: NTF of behavioral model of receiver simulated in Cadence, with and without additional noise shaping loop to compensate for unnecessary quantization noise amplication. 3.3.2 Receiver Budgeting Receiver budgeting for the component values begins with baseband ADC. The lossy noise-shaping ADC uses a 4-bit Flash ADC operating atf s = 200 MSPS. The 3-dB bandwidth isf c = 20 MHz. The desired bandwidth is chosen asf c =2 = 10 MHz for maximum atness in the passband, therefore giving oversampling ratio OSR = 10. The net ADC resolution M e , after compensation can be approximated as M e M + log 2 2 4 s 3 (OSR) 3 2 3 5 : (3.20) 111 Fig. 3.20: Complete receiver with noise-shaping ADC and other important blocks. Substituting M = 4 and OSR = 10, gives M e = 8:1 bits. This value is relatively low, thus making the system a good candidate for low power receiver design, and the baseband noise is assumed dominated by the quantization noise. Thus, as is common with a regular CT ADC and receivers in general, the noise and non- linearity is assumed dominated by the LNTA assuming sucient gain is available due to the front-end [16]. An important low power receiver application is those used for personal commu- nications and Internet of Things (IoT) [49]. The sensitivity specication of such receivers is around -70 dBm for 10 MHz bandwidth and the modulation used is 8-PSK. The circuit parameters are determined using the following analysis: 112 Assume the full scale input to the quantizer V fs = 400 mV = -4 dBm (50 reference impedance. Practically, the best case Eective Number Of Bits (ENOB) is assumed to be 7.5 bits implying that the quantization noise oor lies at -4 - (6.02)7.5 - 1.76 = -50.91 dBm. The minimum SNR for a Bit Error Rate (BER) of 10 6 in 8-PSK modulation is 13 dB, implying that the signal at the output of the ADC should lie at a power level of -50.91 + 13 = -37.91 dB. The conservative receiver sensitivity of -75 dBm, implies the maximum gain requirement of the receiver is -75 + 37.91 = 37.09 dB, which translates to true gain of 37.09 - 6.02 = 31.07 dB given 50 matching at the input of the LNTA. The gain of the receiver is (g m1 =Kg m2 ) (CG) = 31:07 dB (using (3.13) and (3.18)). With K = 0:27 and CG = p 2=, g m1 =g m2 = 42:9. If we choose g m2 = 0:5 mS, g m1 = 21:45 mS. From the impulse invariance transform, the integrator capacitor isC = 2:5 pF. The choice isg m2 is fromC, such that the load of the integrator, i.e. the net capacitance looking into the ADC is much smaller thanC. Lower value ofg m2 also implies a larger DAC, as will be seen in the next section. 113 Table 3.1: Design Parameters for Low-Power Receiver RF clock frequency (f RF ) 0.5-2.75 GHz Baseband sampling frequency (f s ) 200 MSPS Bandwidth (B) 10 MHz Desired receiver sensitivity <-70 dBm Data modulation 8-PSK Bit error rate (BER) 10 6 Desired noise gure (NF) <16 dB Oversampling ratio (OSR) 10 IIR lter order (N) 2 IIR lter cuto frequency (f c ) 20 MHz IIR lter rst tap coecient ( 1 ) -1.14 IIR lter second tap coecient ( 2 ) 0.41 IIR lter inherent gain (K = 1 + 1 + 2 ) 0.27 Mixer conversion gain (CG) p 2= = 0:45 Flash ADC bits (M) 4 Noise-shaping ADC op-amp gain (A LF ) > 1=K = 3:70 ADC full-scale range (V fs ) 400 mV Receiver gain (G R ) 31.1 dB Feedback DAC gain (g m2 ) 0.5 mS LNTA transconductance (g m1 ) 21.45 mS Integrator feedback capacitance (C) 2.5 pF The noise gure requirement is simply calculated from the sensitivity and SNR as: -(-174 + 75 + log(10 10 6 ) + 13) = 16 dB. This requirement being fairly large justies for direct matching at the input using 50 resistors and incurring 3 dB noise gure at the front-end. Based on above calculations, the design parameters for the receiver are summarized in Table 3.1. Having analyzed the system and specied the design parameters, we now proceed to circuit design. 114 3.4 Details of Schematics The receiver is designed and implemented in a 65 nm CMOS technology with a nominal supply ofV DD = 1 V. The key building blocks of the system are the front- end LNTA, RF mixers, 4-phase RF clock generator, integrator of the main loop, detailed implementation of the lossy noise-shaping ADC (from Fig. 3.18) and feed- back DAC for IIR ltering. The chip additionally has a 4-bit binary-to-thermometer converter for the output of the ADC, biasing circuits and programming shift reg- isters. Both clock signals are generated o-chip, buered and divided on-chip in order to generate accurate duty-cycles. 3.4.1 Lossy Noise-Shaping ADC It is preferable to design the noise-shaping ADC rst, as any input-referred noise and distortion is shaped due to the integrator. Therefore, the ADC sampling ca- pacitors need only be specied for M = 4 bits and the additional 11 dB 2 bits due to additional lossy noise-shaping. For a 6-bits specication, withV fs = 400 mV, the minimum required input capacitance for noise purposes is very small ( 0:07 fF). For the sake of matching the input capacitance is chosen as 150 fF. There are two capacitors of 150 fF each, representing capacitors C 1a and C 1b in Fig. 3.18. The loop in Fig. 3.18 is constructed for a 4-bit (i.e. 15-level) quantizer. The implementation of the circuit is shown Fig. 3.21. The resistor ladder is connected between the o-chip generated voltagesV + andV to create 15 references voltages. 115 These reference voltages V ref;i ; i = [1; 15] are used for the 15 comparators as a part of the 4-bit Flash ADC. The sampling capacitor C 1a = 150 fF is accordingly split into 15 unit capacitors of 10 fF each. The dierence voltage for the internal lossy noise-shaping loop is generated using a capacitive DAC. The capacitance C 1b is also split into 15 capacitors of 10 fF each, and the residue voltage is calculated directly from the data as shown. For each data output D i , the DAC output is D i V + +D i V . IfX out of 15 comparators have a positive output and 15X have a negative output, the residue voltage calculated at V X in Fig. 3.21 is given as V X =V cm V in + X 15 V + + (15X) 15 V ; where V cm is a common mode voltage (usually 0.5V DD = 500 mV). This residue is sampled on the negative plates of the individual capacitors that constitute C 1a in order to close the noise shaping loop. The comparator used is a strong-arm comparator with latch at the outputs (shown in Fig. 3.21). Preampliers are not used to save power. The input tran- sistors are designed to be large enough to satisfy oset requirements. Note that any oset is also shaped by the loop, and is therefore relaxed from an architecture standpoint. The resistor ladder input nodes V + and V are sucient bypassed to prevent noise from o-chip and ringing due to the wirebond inductances. The op- amp of the quantizer loop requires very low gain as mentioned earlier. Therefore, a 116 Fig. 3.21: Detailed schematic of the lossy noisy shaping ADC with the comparator and loop lter op-amp schematics included. simple dierential pair is used as shown, with as little as 40A of bias current. The gain of the op-amp is8 (larger to compensate for eects of its output impedance). 3.4.2 Integrator The integrator op-amp see a load of (C 1a +C) 1b = 300 fF. Note from earlier that (g m1 =Kg m2 )(CG) is the gain of the system, implying thatg m2 and henceC of the integrator can be indenitely reduced as long as the NF requirement is not aected. In the current implementation, for a 300 fF load for the integrator, the value of C should not be less than 2.5 pF, in order to avoid degradation in the noise shaping 117 Fig. 3.22: Detailed schematic of the integrator op-amp with the feedback capacitors C included. The dierential pair op-amp has a current consumption of 636 A. functionality. The op-amp gain and bandwidth is determined such that the settling time requirements are satised. Furthermore, nite gain eects should not disturb inband noise shaping. After extensive simulations a gain of about 27 dB and GBW of 140 MHz were deemed sucient. The op-amp is a dierential pair with the current consumption of 636 A (Fig. 3.22). The feedback capacitors are connected close to the op-amp in order to avoid additional parasitic capacitances. 3.4.3 Feedback DAC The feedback DACs represent a transconductance of ( 1 + 1)g m2 and 2 g m2 for the two taps respectively. Note that since we are using the semi-digital approach, both feedback DACs are 4 bit (15 levels) implementations. A resistive DAC with switching at the voltage reference side is preferred to eliminate upconversion of 118 Fig. 3.23: Detailed schematic of the feedback FIR lter DAC in the I branch. icker noise and to maximize the SNDR [55]. The voltage references for the DAC are common to those used for the resistor ladder of the quantizer, in order to maintain the same full-scale at all points in the loop. The value of the individual resistances are calculated as 15=(( 1 + 1)g m2 ) and 15=( 2 g m2 ) respectively, giving 214.4 k for the rst tap DAC unit resistance and 73.2 k for the second tap DAC unit resistance. The DAC implementation is shown in Fig. 3.23. For the second tap, the data is delayed using standard DFFs in the data path. A smaller value of g m2 , decreases the power consumption of the receiver, since gain of the receiver G R / 1=g m2 . However, the value of the feedback DAC resis- tances increases, thereby increasing the total chip area. Furthermore, as will be see in the next subsection, the receiver Noise Figure (NF) also increases. Therefore, we note that there are direct tradeos in power consumption, area and receiver performance, with the choice of the value of g m2 . 119 Fig. 3.24: Inverters used for the LNTA in the receiver. 3.4.4 LNTA Design and Analysis It is expected that the LNTA dominates the noise performance of the receiver. The LNTA architecture used in this system is similar to that in [51], consisting of inverters, however, with current sources to improve the CMRR and reduce the even order eects. The schematic of the LNTA is shown in Fig. 3.21. There are 6 inverter cells as shown, with the feedback self-biasing common-mode resistance R f = 50 k common to all 6 inverters. The 6 inverters are switchable in groups of 2 each for gain control. Current mirror biasing voltages leading to the current sources of the inverters are RC ltered to reduce the thermal noise at the output. 120 Fig. 3.25: Simplied front-end model for NF calculations. The noise gure of the receiver due to contributions only from the LNTA and the feedback DAC can be calculated by using a simplied model as shown in Fig. 3.25 (see [69] for an analysis for passive mixer based receivers in general). Consider the receiver as shown in Fig. 3.12c and ignore the quantization noise. At small frequency osets from RF, the feedback capacitance C is considered open circuit, while the eective impedance looking into the feedback DAC is given as 1=Kg m2 . If the conversion gain of the mixer is incorporated into the impedance, the eective impedance for feedback around the integrator op-amp is (CG)=Kg m2 . Assuming the feedback resistance of the LNTA R f = 50 k is very large, the LNTA can be modeled as a g m cell with output resistance R out in input capacitance C in . The passive mixer is removed, with the switch resistance R sw instead added in series to the input of the integrator op-amp as shown in Fig. 3.25 4 . There are four noise sources in the model: noise of the mixer switch resistance, the noise of the feedback resistance (i.e., noise of feedback DAC), the input noise of the integrator op-amp V n;A , and the noise of the LNTA. These components are 4 Contribution due to downconversion of noise from the other odd harmonics of the local oscil- lator are ignored for simplicity. 121 Fig. 3.26: Schematic simulations of gain and NTF (PSS+PAC), and noise gure (PSS+PNOISE) of the receiver, with real LNTA schematic. added to the 3 dB presented by the input matching 50 resistorsR s . Deriving the noise gure using the model in Fig. 3.25, we obtain NF = 2 + 4R sw R s g 2 m1 R 2 out + 4 (R out +R sw ) 2 =(CG=(Kg m2 )) R s g 2 m1 R 2 out + V 2 n;A kTR s g 2 m1 R 2 out + 4 g m1 R s : (3.21) Using the valuesR sw = 25 ,R s = 50 , assumingV n;A is small and the rest of the parameters from Table 3.1, the calculated noise gure is 7.7 dB in the passband, with steadily increasing values at higher frequency osets. The gain, noise gure and NTF of the receiver with the real LNTA schematic and a behavioral model for the rest of the circuit are shown in Fig. 3.26. As can be seen that as gain reduces, the noise gure increase steadily in the passband with the best value at 122 around 7.6 dB (close to expected from theory). The NTF on the other hand, is not a function of the LNTA gain, and remains quite constant over the gain range. Note that the gain is slightly lower, inspite of larger value of g m1 than those specied in Table 3.1 due to the loss from the pad and wirebond parasitics (also modeled in the simulation). Furthermore, 5 pF capacitances are used for AC coupling at the input. 3.4.5 RF Passive Mixer and Clock Generation The passive mixers used for frequency translation are NMOS transistors of size 30 m=0:06 m. These size are chosen to make sure that the resistance of the NMOS transistors remain less than 25 under all conditions. These mixers are turned on and o using 25% duty cycle clocks that work from 0.5-2.75 GHz. To generate these clock signals, a 4X frequency signal is input from o-chip, buered to rail and divided by 4 to produce the quadrature and dierential signals. These signals are then buered to the RF mixer NMOS transistors. The schematic for clock generation is shown in Fig. 3.27. To ensure that the resistance of the NMOS transistors is minimized under all RF input amplitude conditions, level shifters are used to change the swing range from 0-1 V to around 0.45-1.45 V. Since the output of the LNTA is typically low swing and has a common mode voltage of 0.5 V, it is expected that the switches do not turn on in all cases. Nevertheless, extensive simulations are performed across technology corners and 123 Fig. 3.27: Schematic of synchronous divide-by-4 and buers with level shifters. temperatures to ensure proper operation. The largest swing across the switches is around 1.2 V, which does not exceed the MOS gate-drain voltage requirements for the technology. The divide-by-4 circuit is a simple synchronous divider with quadrature outputs. The Delay Flip-Flop (DFF) uses a high-speed circuit, given the speed requirements of the output clock. Level shifters are implemented using AC coupling capacitors and biasing resistor dividers. It is expected that the clock generation will consume a signicant amount of power in the chip as large switches are used in the frequency translation mixers. On the other hand, on-chip clock generation can reduce input buer power con- sumption. In this implementation, we use a clock signal at 4f RF from o-chip. 124 Fig. 3.28: Chip photograph. The chip was implemented in a 65 nm CMOS tech- nology. 3.5 Measurement Results The receiver is fabricated in a 65 nm CMOS process and packaged in a 44-pin 7 7 QFN package (photograph shown in Fig. 3.28). The digital data is collected using a logic analyzer and spectra are calculated after Blackman-Harris windowing. Besides the input signal, RF clock signal, baseband clock signal and data outputs, supply regulators and shift register buers are also present on the board. An o-chip Balun is used to convert the RF signal input to dierential before entering the chip. This balun and its corresponding traces are rst measured in a back-to-back conguration. The resulting S-parameters are shown in Fig. 3.29. In all subsequent measurements the loss of the balun is de-embedded before reporting 125 Fig. 3.29: S-parameter measurement results of the o-chip balun, performed in a back-to-back conguration. receiver metrics such as gain, noise gure, etc. The loss is calculated using the S-parameters, divided by 2, and then used for de-embedding. 3.5.1 Small Signal Response Since the receiver is an RF-to-bits system, the small signal response is calculated after obtaining the spectra from the data recorded by the logic analyzer. The RF frequency f RF is tunable from 0.5-2.75 GHz, and a few representative frequencies in this range are chosen (note that clock at 4f RF is the actual input to the chip). Next, the signal frequency is selected with an oset from the RF clock frequency (f) which is varied from 0 to 100 MHz, the Nyquist Rate. The spectra of the downconverted and quantized signal gives the output signal strength with respect to the full scale range set V + and V , the o-chip ADC references: V fs =V + V . Under nominal conditions,V fs = 400 mV, implying signal amplitude at full-scale is around 200 mV. 126 Fig. 3.30: Conversion gain of the receiver: (a) conversion gain across the center frequency range (f RF ) of interest, (b) conversion gain with respect to frequency oset at f RF = 2:07 GHz, in comparison with normalized ideal simulation results. After de-embedding the loss due to the balun, the measured gain across the entire band of interest is shown in Fig. 3.30a. The conversion gain reduces from around 35 dB at 640 MHz to 32 dB at 2.51 GHz. This loss can be attributed to the input network of the chip, which consists of the pad capacitance and losses due to the wirebond inductance, and the lower gain of the LNTA at higher center frequencies (conrmed from simulations of the pad and wirebond network). The STF for channel selection with frequency osets from center frequency 2.07 GHz is shown in Fig. 3.30b. Filtering takes place with the expected 3 dB cuto at 20 MHz (i.e. f c =f s =10), and the frequency response closely matches as expected from ideal simulation (plotted from (3.18)), after normalization. To note the band selection transfer function, the oset is varied beyond the 100 MHz Nyquist Rate, upto 400 MHz. The amplitude of the image frequency (after quantization) is cal- culated to obtain the wideband transfer function. This result is plotted Fig. 3.31. 127 Fig. 3.31: Wideband signal transfer function measurements shown the notches cre- ated at multiples of f s that create the band selection transfer function. As can be see, notches are formed at 200 MHz and 400 MHz oset, conrming the sinc band selection transfer function from (3.18), in addition to channel selection at lower frequencies. The mismatch between I and Q branches are signicant after 30 dB of rejection and particularly close to f s =2 and its images (i.e. around 100 MHz and 300 MHz). This can be attributed to limitations resistor matching, which can be only up to 3% for closely spaced resistors in the given technology (as seen in Fig. 3.28, resistors of I and Q DACs are about 300 m apart), and more importantly the sensitivity to timing errors close to Nyquist sampling rate, where it is harder to satisfy impulse invariance. The quality factor (Q) for the eective band pass lter is given as Q = f RF 2f c = f RF 2f s ; (3.22) 128 Fig. 3.32: Noise gure vs. RF center frequency. The results are lower than the 16 dB design requirement. where is the ratio of the cuto frequency to the sampling frequency, according to the IIR lter in use. In this implementation = 0:1, f s = 200 MHz, and f RF = 0:52:75 GHz. Therefore,Q = 12.5-68.5, depending on the center frequency. The quality factor can be decreased further if clock rates are decreased, i.e., Q is simply a function of a ratio of the frequency of clocks 5 . The Noise Figure (NF) of the receiver is measured for various center frequencies (results shown in Fig. 3.32). The RF input signal is turned o to measure the noise oor after quantization. 5 Note however, that with changing f s , C or g m2 has to change to satisfy the condition f s = g m2 =C from the impulse invariance transform. 129 Fig. 3.33: In-channel IIP3, out-of-channel IIP3 and input referred 1 dB gain com- pression point measurement results. 3.5.2 Nonlinearity Tests The in-channel IIP3 of the receiver is measured by having two tones close to each other at osets within the baseband bandwidth. The osets chosen are 4.56 MHz and 5.56 MHz, with the IM3 tone measured at 3.56 MHz after downconversion and quantization. This measurement is carried out at representative center frequencies between 0.5-2.75 GHz. The out-of-channel IIP3 is an important scenario, where blockers outside the bandwidth of interest produce an IM3 tone within the band- width. To measure this eect, the oset frequencies chosen are 46.56 MHz and 89.56 MHz, with the IM3 tone measured at 3.56 MHz. The receiver input referred 1 dB gain compression point is also measured; Fig. 3.33 shows the results from these measurements. As is commonly expected, the out-of-channel IIP3 is around 130 Fig. 3.34: Blocker power for CP1dB in the presence of blocker and blocker power for SNDR degradation by 3 dB, for varying blocker osets. Plots shown for f RF = 0.64 GHz and 2.51 GHz. Fig. 3.35: SNDR measurements with input power show a dynamic range of 50 dBm. 10 dB more than the in-channel IIP3, due to blocker ltering. Note that the 1 dB gain compression is common to both channels, as only the main tone is measured. 131 Fig. 3.36: Output spectrum atf RF = 2.51 GHz. (a) Output spectrum in the absence of blocker signal. (b) Output spectrum in the presence of a blocker with 10x power at 89.55 MHz. The input signal is at 1.56 MHz. The nonlinearity of the desired signal in the presence of blocker is measured as the blocker power level for compression in gain by 1 dB of the desired signal, at various blocker osets. For this test the desired signal lies at 1.56 MHz oset. The blocker power level for decrease in SNDR by 3 dB for various blocker osets, is also measured, with the desired signal at -60 dBm power level and 1.56 MHz oset. In both measurements (shown in Fig. 3.34 for f RF = 0.64 GHz and 2.51 GHz), the blocker tolerance improves steadily with increasing blocker oset. The conversion gain is shown for correspondence in the plots. The large signal nonlinearity of the system is measured as a variation of in- channel SNDR versus input RF power. The results shown in Fig. 3.35 give a dynamic range of about 48 dB for the receiver in both I and Q channels. The measurements are conducted for the center frequency f RF of 2.51 GHz, with the desired signal at an oset of 1.56 MHz. Plots of the output spectrum for an input 132 Fig. 3.37: 8-PSK measurement results (a) EVM and SNR vs. RF input power. (b) EVM in the presence of a blocker at input power of -50 dBm, with center frequency of 2.51 GHz. (c) Example constellation diagram (0.64 GHz, -50 dBm). (d) Example constellation diagram (2.51 GHz, -50 dBm). signal oset of 1.56 MHz are shown in Fig. 3.36a (without blocker) and Fig. 3.36b (with blocker of 20 dB additional power at 89.55 MHz). As can be seen, the blocker is suciently ltered due to the STF of the IIR lter. 133 3.5.3 Communication Tests Communication tests were performed for the 8-PSK modulation case, using a 10 MSPS modulated source with a rectangular pulse shape, and carrier frequency varying from 0.5-2.75 GHz. The output of the ADC is decimated to the desired 10 MSPS symbol rate from 200 MSPS, and a 30-tap FIR lter based on the windowing method is used to lter out-of-band quantization noise. DC and frequency/phase oset are corrected for in MATLAB. As expected, the measured EVM steadily increases with input RF signal power (Fig. 3.37a) across the RF clock frequencies of interest (results are shown for 0.64 GHz and 2.51 GHz). SNR =20 log(EVM), is also plotted in Fig. 3.37a. The sensitivity is calculated as the input power that satises the BER requirement of 10 6 , corresponding to 13 dB of SNR for 8-PSK modulation. Given these condi- tions, the sensitivity is obtained as approximately -66 dBm for the receiver. The clock frequency is then xed at 2.51 GHz and the RF input power is xed at -50 dBm. A blocker is introduced at various frequencies osets with increasing power. As shown in Fig. 3.37b, as the blocker oset increases, increasing blocker power has lesser eect on the EVM due to blocker ltering at the front-end. Example 8-PSK constellations (without blocker) are shown in Fig. 3.37c (0.64 GHz) and Fig. 3.37d (2.51 GHz). Note that the measurements use only the raw I/Q data and do not perform I/Q gain and phase mismatch correction, which may improve the EVM as a result. As 134 Fig. 3.38: 16-QAM measurement results: (a) Example constellation diagram (0.64 GHz, -45 dBm). (b) Example constellation diagram (2.51 GHz, -45 dBm). shown in Fig. 3.37a, the EVM does not improve beyond a certain point with increas- ing power. This may be attributed to the use of a rectangular pulse shape, which leaks signicant power outside the 10 MHz bandwidth, thus causing Inter-Symbol Interference (ISI) which is proportional to signal power. If a better pulse shape (such as the raised cosine) were used, leakage power is reduced, however, correct sampling within the chip is critical. This can be remedied by adding programmable delays within the chip, which is not available in the current implementation. While the receiver is designed for an 8-PSK application (as stated in Section 3.3), other complex modulations such as 16-QAM can be used if input power is higher. Representative constellation measurement results (without blocker) for 16- QAM at an input RF power level of -45 dBm, for center frequencies of 0.64 GHz and 2.51 GHz are shown in Fig. 3.38. 135 Fig. 3.39: Power consumption and energy eciency as a function of the center frequency. 3.5.4 Power Consumption and Energy Eciency The total power consumption of the system (P DC ) is measured to be from 9.3 mW at 0.64 GHz to 16.2 mW at 2.51 GHz. This variation in the power consumption is primarily due by the 4-phase non-overlapping clock generators working at 4f RF . The baseband circuity consumes approximately the same power regardless of the center frequency at RF. The total system power consumption determines the energy eciency at the highest SNDR for a desired signal bandwidth of 10 MHz, given by Energy Eciency = P DC 2 SNDR 2BW 136 Table 3.2: Comparisons with Selected Direct CT Receivers [70] [71] [58] [59] This Work RF Clock (f RF ) (GHz) 0.4-1.7 0.4-4 0.7-2.7 0.6-3 0.5-2.75 Baseband Clock (f s ) (MHz) 1700 4000 1250 592 200 Signal BW (B) (MHz) 4 10 15 10 10 Gain (dB) 12 (max) 20 (max) 58 51 32-35 Channel Filter Order 0 0 4 4 2 Noise Figure (NF) (dB) 33.9 16 5.9-8.8 2.4-3.5 6.1-10.8 In-Channel IIP3 (dBm) 19 10 <-20 -23 -23 Out-of-Channel IIP3 a (dBm) - -13.5(40) -2(95) -2(30) -13(47) Blocker CP1dB b (dBm) - - -26(22.5) - -29(30) Peak SNDR (dB) 60 62 43 49 33 Power (P DC ) (mW) 42 40 90 45 16.7 Eciency (pJ/lvl) 2.6 0.8 10.6 4.0 5.5-9.8 Active Area (mm 2 ) 0.8 0.56 1 0.7 0.15 Technology (m) 90 65 40 65 65 Supply Voltage (V) 1.2 1.1 1.1 1.2 1 a Oset of closest blocker in brackets (MHz) b Oset of blocker in brackets (MHz) The energy eciency varies from 5.45 pJ/bit (at 0.64 GHz) to 9.75 pJ/bit (at 2.51 GHz), calculated per channel (either I or Q). The variations of these results versus the center frequency of the local oscillator in shown in Fig. 3.39. The receiver implemented in this project can be compared with two categories of receivers in literature; (i) ltering and quantizing, RF-to-bits CT receivers, and (ii) low-power receivers, particularly that are designed for low-rate communications such as for IoT. Table 3.2 shows comparison results of the receiver with state-of- the-art CT receivers. As is seen the receiver has very good energy eciency, while providing all the necessary nonlinearity requirements at very low total power consumption. More importantly, the active area of the system is far lower due to 137 Table 3.3: Comparisons with Selected Low-Power Receivers [72] [73] [74] [75] This Work Center Frequency (GHz) 2.4 2.4 2.4 2.4 0.5-2.75 Data Rate (MBPS) 2 1 1 2 30 Sensitivity (dBm) -92 -94.5 -87 -90 -66 Noise Figure (NF) (dB) 5 5.5 6.4 6 10.8 ACR (2 nd /3 rd ) (dB) 12/17 - 24/29 20/- 9/14 (at RF) Power (P DC ) (mW) 2.4 1.2 6 1.55 16.7 (I+Q) FOM (dB) a 181 174 169 178 159 Eciency (nJ/bit) 1.2 11.2 6 0.77 0.56 Technology (m) 90 55 65 40 65 Supply Voltage (V) 1 0.9-3.3 0.6-1.2 0.85 1 a Dened as FOM =Sensitvity 10 log 10 (P DC =Data Rate) the digital intensive ltering being performed. Comparison with low-power receivers (Table 3.3) show that energy eciency is high in comparison to works in literature in spite of increase in bandwidth and sensitivity therein. 3.6 Conclusions This chapter extends scalable and recongurable channel selection in the baseband of a communication system to include the full design and implementation of a receiver. In particular we show theoretically and experimentally that the ltering- ADC concept introduced in Chapter 2 can be extended to the receiver and combined with the current-mode SDR concept to perform both band selection and channel selection at the front-end. The receiver design was interpreted as a mixed-signal IIR lter with a semi- digital FIR lter feedback. With the introduction of a noise-shaping impedance, 138 the band selection was performed at RF due to the anti-aliasing properties of the rst-order CT ADC, while channel selection was performed at RF by the mixed- signal IIR lter. The integrated circuit implementation is a low power RF-to- bits reciever that performs band selection, frequency translation, channel selection, amplication and quantization with noise shaping in a small form factor. The motivation for this receiver was to realize a synergic communication system that benets from mixed-signal and digital blocks, thereby eliminating bulky analog components used in front-end and baseband lters. The digital-to-RF feedback technique used shows that receivers can greatly benet from such combined designs when approached from an architectural standpoint, rather than simply performing block level optimization separately for signal conditioning and quantization circuits. 139 Chapter 4 Rapid Hopping Digital Frequency Synthesis 4.1 Fast Frequency Hopping Clocks Clocks used for up/down conversion, an important component of the transceiver may have stringent requirements for special applications. We will examine one such requirement - fast frequency hopping - where the frequency synthesizers are designed to change frequencies rapidly over short time intervals. Fast frequency hopping in the local frequency synthesizers has several impor- tant applications: (i) Spectrum analyzers that need quick spectrum capture use fast-frequency hopping clock to sweep a wide frequency range over a short period of time. The result can then be used for vector signal analysis or for other impor- tant frequency domain functions such as blocker power detection, thus making the fast hopping synthesizer an important component of the SDR [21]. (ii) Fast fre- quency hopping over a wide frequency range can also provide for high bandwidth, multi-band communications, particularly for Ultra-WideBand (UWB)-Orthogonal 140 Fig. 4.1: Four applications where fast frequency hopping clocks are essential: (a) Fast sweeping spectrum analyzers, (b) wideband OFDM UWB communications, (c) secure communications using data encoded as fast hopping frequency sequences, and (d) electronic warfare applications. Frequency-Division Multiplexing (OFDM) applications [76]. (iii) A channel where two radios transmit and receive data over center frequencies that change rapidly, can be made secure if the sequences change at a fast rate, thereby preventing interception by a rogue transceiver [14]. (iv) The converse of the secure communi- cations applications may also use fast frequency hopping - a high, power jamming enemy transmitter in electronic warfare, can change single-tone frequencies rapidly enough to prevent the communication between two transceivers. These applications are summarized in Fig. 4.1. The application under consideration in this chapter is that of military commu- nications particularly, secure communications and electronic warfare. The require- ment here is to produce fast-hopping frequency sequences over 1-6 GHz (covering 141 the Industrial Scientic and Medical (ISM) band), with very high frequency reso- lution (<1 MHz) and a hopping rate of less than 50 ns, while maintaining signal spectral purity in terms of frequency stability, phase noise and SFDR 1 . Since we intend to use the fast hopping feature as an addition to the regular local clock fea- ture in the receiver, it is desirable that the power consumption of the system also be as low as possible. The combined use of wide frequency range, while increasing the frequency resolution and the hopping time simultaneously ensures robustness in terms of inability to track the jamming or secure communications frequency. However, the simultaneous design of these features poses certain challenges. 4.2 Limitations of Conventional Architectures At this point, we assume that any frequency is generated from an oscillator that can have possibly two control mechanisms: (i) direct control frequency control voltage (as in a VCO) and (ii) dividers at the output of the oscillator. Furthermore, it is also assumed that frequency variation using the control voltage is an inaccurate process and trades o directly with stability and phase noise, while frequency division is generally more stable, due to xed input oscillator frequency to the divider [77]. Using the above two mechanisms, common clock generation architectures under consideration are broadly classied as (i) those that use feedback Fig. 4.2a, and (ii) those that use feedforward techniques Fig. 4.2b. 1 Note that since the output is a single frequency tone used as a clock, harmonics of the main output frequency do not necessarily contribute to the SFDR. 142 Fig. 4.2: Two techniques to create fast-hopping, high resolution wideband frequen- cies: (a) Using feedback with a clock reference and (b) feedforward with a control voltage reference. The feedback technique as shown, consists of phase synchronization to a refer- ence clock which possesses superior purity and stability. On the other hand the feedforward technique rely on open loop control. Both techniques use the two \knobs" available - the control voltage prior to the oscillator and the divider after the oscillator. We will now examine these methods in detail. 4.2.1 Closed-Loop and Phase Synchronization Techniques Phase synchronization techniques can be further examined in the context of PLLs and injection locking techniques. Consider rst the use of an integer-N PLLs for fast frequency hopping Fig. 4.3a. With a required output resolution of 1 MHz and frequency range of 1-6 GHz, the divider N spans from 1000 to 6000, a very large number [78]. The use of the charge pump restricts the loop bandwidthf l of the PLL to usually (1=20)f ref [79], where f ref is the reference frequency. This implies that any change in the division ratioN would result in a stable locked output frequency after a hopping time t h =O(1=B) implying a hopping time in the order of a few 143 Fig. 4.3: Phase synchronization for fast frequency hopping: (a) use of Phase-Locked Loop; (b) use of multipliers with injection locking. microseconds. This result does not satisfy our specied requirement of 50 ns. The fundamental process determining frequency settling time is the step response of the loop transfer function. The phase transfer function of the integer-N PLL shown in Fig. 4.3a: out (s) in (s) = NK v H(s) (Ns +K v H(s)) ; (4.1) whereK v is the oscillator voltage-to-frequency gain, out (s) is the output phase of the oscillator and in (s) is the phase of the reference, usually consists of multiple poles whose step response has a large settling time often with overshoot. Furthermore, a large division of 6000 is impractical in terms of power consump- tion and noise performance of the divider (which is directly input-referred at the reference). A possible solution around this issue is to use a fractional-N PLL, that reduces the maximum divider ratio, while at the same time increases the f ref , thereby enabling a higher loop bandwidth. These changes are made at the cost of in- creased spur levels due to fractional-N divider quantization noise. Despite eorts to reduce spurs arising from the divider and the reference, the loop bandwidth usually 144 does not excess a few MHz frequencies in state-of-the-art fractional-N PLLs [80,81] as making f ref larger results in higher reference noise and also requires undesired ner fractional division in the feedback. Recent work has attempted to address the overshoot issue in the step response of (4.1), using instantaneous phase correction with a modied divider [82]. While the overshoot and settling time is reduced, the phase correction can still only take place at the rate of the reference frequency and loop bandwidth, in order to satisfy the Gardner limit [79]. Therefore, PLLs in their basic form satisfy the synchronization requirement, but are impractical for the fast hopping design requirements. An alternate technique that also uses synchronization is injection locking. While dynamically equivalent to the faster rst-order PLL, injection locking represents a system where the reference and the output oscillator are around the same frequency, within the locking range. However, to create the desired reference at the required frequency resolution of 1 MHz, a frequency multiplier is used to generate harmonics of a 1 MHz crystal reference, of which the output oscillator locks to one (Fig. 4.3b). Since the multiplier replaces the divider, the harmonics required to be generated are from the 1000th to 6000th, for an output frequency range of 1-6 GHz. This is a near impossible task at reasonable power consumption levels, as passive de- vices used for multiplication have low output power or require special materials, and active devices have low power eciency [83]. A reasonable power at the de- sired harmonic is necessary, as the locking bandwidth is directly proportional to the 145 injection strength [84]. As a result this technique has historically been applied to UWB-OFDM applications where fast hopping is desired, but the standard-specied channels are widely-spaced, thereby requiring only a few harmonics to be gener- ated [85,86]. Thus, for the purposes of the current application multiplication with injection locking does not serve the purpose as well. In conclusion, synchronization techniques are able to produce a spectrally stable clock frequency with low phase noise and SFDR, however the fast-hopping require- ment is severely restricted either due to the loop bandwidth or reference strength. 4.2.2 Open-Loop and Phase Division Techniques While a stable reference clock may be used for synchronizing a widely tunable out- put oscillator, it is also possible to vary stable oscillator directly without feedback control mechanisms to generate a desired output frequency. One mechanism is to control an oscillator in a rapid manner by directly using the control voltage [87] (Fig. 4.4a). However, this mechanism requires very precise control of the oscillator frequency using voltage supply and temperature measurements. Furthermore, due to the low quality factor of CMOS varactors, wide-tuning range and low phase noise are dicult to achieve simultaneously [88]. Therefore, fast hopping is possible but stability of the output frequency cannot be ensured. A technique commonly used in military applications to generate fast-hopping frequency sequences is Direct Digital Synthesis (DDS) [89]. In the most basic form, 146 Fig. 4.4: Open-loop for fast frequency hopping: (a) direct control of an integrated oscillator using a precise controlling voltage; (b) using division mechanisms such as the direct-digital frequency synthesizer. the Direct Digital Frequency Synthesizer (DDFS) consists of a stable reference clock which is used to accumulate a digital frequency word at the rate of the clock. The digital phase output is transformed to its sine-of-phase using a nonlinear trans- formation performed by a digital processor. Commonly used algorithms for this transformation include COordinate Rotation DIgital Computer (CORDIC) [90]. The output is then fed to a DAC that directly generates the sine waveform (Fig. 4.4b). The DDFS in essence behaves as a phase divider, and is capable of hopping between frequencies at a very fast rate, limited in latency only by the nonlin- ear phase-to-sine transformation algorithm. To improve the hopping rate, on-chip ROM units may be used to make the digital sine output read-out instantaneous. 147 The DDFS being a digital technique requires a sampling clock rate at atleast the Nyquist Rate of the highest desired output frequency 2 . Consider the fastest possible DDFS for the purposes of our application. This DDFS uses a ROM to reduce the frequency hopping time. For an output frequency of 6 GHz, the sampling rate required is 12 GSPS. Assuming an M-bit frequency word, the smallest possible output frequency of the DDFS is f out;min = f clk 2 M ; (4.2) implying that for a frequency resolution of 1 MHz, the frequency word is 13-bits long. For an SFDR of 40 dB ( 7 bits) at the output of an ideal DAC, the ROM requires to store 2 13 7 bits of data, which would have a large power consumption during the readout process at 12 GSPS. As a result, it is preferred to either reduce the DDFS sampling rate, compress the ROM [91], or use ROM-less architectures, such as those that use algorithms as already explained. Therefore, we see that there is a clear tradeo, particularly at high sampling rates, between power consumption and frequency hopping time, as ROM-less, algorithm-based phase-to-sine conver- sion has inherent latency. Furthermore, digital circuits consisting of thousands of gates, tend to consume a large amount of power: consider a 10000 gate circuit with 10 fF input gate capacitance. At a supply voltage of 1 V, and clock rate of 12 GSPS, 2 Oftentimes an oversampling rate is desired to ease the rejection of image frequencies at the output of the DAC. We will examine this requirement in greater detail later. 148 Fig. 4.5: The trade-os between various architectures for fast frequency hopping. (a) The architectures can be classied as closed-loop, phase synchronizing or open- loop, phase division, each category with distinct advantages and disadvantages. (b) A general plot shows the tradeos between architectures in important metrics. the total power consumption is 1.2 W, a particularly large value for hand-held radio devices. To summarize the techniques in literature, we plot the various architecture in a power vs. hopping time vs. frequency resolution plot as shown in Fig. 4.5b. Any proposed architecture should break tradeos aforementioned. The various architectures and their merits and demerits are summarized in Fig. 4.5a. 4.3 Proposed Architecture Consider again the architecture for injection locking shown in Fig. 4.3b. The disadvantage of this system is, as mentioned earlier, the inability to have a high resolution frequency output due to limitations of the frequency multiplier. However, 149 Fig. 4.6: (a) Replacing the xed crystal reference with a high resolution, fast hop- ping synthesizer would resolve the frequency resolution issue. (b) Simplied pro- posed frequency sythesizer architecture. shown in Fig. 4.6a, is a simple modication to the system, where the xed crystal reference can be replaced by a high-resolution, rapid frequency hopping reference. Consider the proposed frequency synthesizer as shown in Fig. 4.6b. The con- troller is input to a DDFS that produces a frequency output between 0-200 MHz. This frequency is upconverted to lie between 200-400 MHz. The multiplier then generates up to the 15th harmonic at it's output (which is relatively a small num- ber compared to 6000). Assuming the controller sets the coarse frequency of the output oscillator at 1 GHz, the 5th harmonic is chosen to obtain 1 GHz with the 200 MHz reference. If the oscillator coarse frequency is set at 6 GHz, the 15th harmonic is chosen with the 400 MHz reference. A resolution of 1 MHz at the output in the worst case, would translate to a requirement of 1/15 = 0.066 MHz 150 frequency resolution for the DDFS. Assuming Nyquist rate operation, and using (4.2) (f clk = 400 MHz) M = 13 bits. Recall that injection locking for frequency generation is a fast process with very low power consumption [86], as the output and reference frequencies both operate at GHz rates (i.e. a hopping time of a few nanoseconds). If the reference generation (i.e. 0-200 MHz DDFS and upconversion to 200-400 MHz), is phase continuous and real-time, the total frequency hop time updates at the sampling rate of 200 MSPS, corresponding to 5 ns. Thus the system is capable of hopping within a few nanoseconds while preserving the high frequency requirement. The proposed mixed-signal system also breaks the power, stability and hopping time tradeo. The DDFS operates at relatively low frequencies (ideal sampling rate 400 MSPS) where digital circuits do not consume much power, while the RF signal generation takes place in a low-power analog manner. It is useful to look at the architecture in some detail (Fig. 4.7). The architecture consists of a quadrature 0-200 MHz DDFS sampled at 800 MSPS with a sine-weighted DAC, which is the focus of the implementation in this project. The ltered, sine-weighted DAC output is then upconverted with harmonic rejection mixers to produce a clean reference with high resolution at 200-400 MHz. The reference is then shaped using a pulse generator to populate the harmonics. Depending on the desired output frequency, the harmonic of choice is selected to produce the 1-6 GHz output. 151 Fig. 4.7: Details of the architecture with the relative contribution of each block to the power consumption, SFDR and hopping time. For further rejection of unwanted harmonics, two stages of locking are used. An image spur rejection lter after the DAC and harmonic rejection lter after the mixer are also required. Since the RF section has been analyzed and implemented extensively in prior work [85,86] we summarize the results here. Injection locking is modeled as shown in Fig. 4.8, where the output oscillator is represented as a feedback system con- sisting of a bandpass impedance and a nonlinear feedback factor. The injection current source lies at a frequency within the locking range. Let representing 152 Fig. 4.8: Model for injection locking, with injecting current of reference oscillator and feedback model for the output oscillator. the instantaneous phase dierence between the injection oscillator and the output oscillator, whose dynamics are determined by the Adler equation [84]: sin( _ (t)) = ! ! 0 2Q sin((t)); (4.3) whereQ is the quality factor of the bandpass impedance, is the injection strength, ! 0 is the angular frequency of the standalone oscillator and ! is the angular frequency dierence between the injecting and output oscillators. For small , it follows from (4.3) that has the following solution: (t) 0 exp ! 0 2Q t ; (4.4) 153 Fig. 4.9: Results of simulation of injection locking process: (a) Output spectrum to validate the locked spectrum. (b) A hop between two frequencies at the GHz range takes a few nanoseconds of time to settle. i.e. the phase dierence diminishes exponentially at a rate proportional to the output frequency and inversely to the quality factor of the oscillator [92]. If the oscillator output lies at 1 GHz, the time taken to lock is within a few nanoseconds. To keep the quality factor low for faster locking purposes, ring oscillators are used as shown in Fig. 4.7. Using the parameters above, a MATLAB simulation for two oscillators tanks that reject unwanted injection harmonics is conducted, with the results shown in Fig. 4.9. As can be seen, the RF stage has a hopping time of a few nanoseconds, with moderate SFDR performance. The image and harmonic rejection lters have a conservative settling time of 15 ns, given their respective cuto frequencies at 200 MHz and 400 MHz respectively. Given the above parameters, the DDFS must change frequencies within a 10-15 ns hopping time, in order to satisfy the system requirement for 50 ns hopping time. The design of such a low latency DDFS poses a challenge by itself, and is the focus 154 of the integrated circuit implementation in this project. Note that from Fig. 4.7, we have a total power consumption of 450 mW for the system, with around 45 dB of required SFDR at the output. 4.4 Theoretical Overview Since the DDFS-DAC should have minimal hopping time it is critical that the algorithm that performs phase-to-sine conversion have very low latency. Since a ROM based implementation is to be avoided due to excessive power consumption, novel ideas should be considered. This is a particularly challenging problem since to benet from the proposed architecture, sampling rates are to be kept low (400 MSPS at the least), and multiple clock cycles due to state machine algorithms at such low rates would incur a large latency and thereby, a large frequency hopping time. 4.4.1 Sine-Weighted DDFS-DAC Operation A typical DDFS consists of three important blocks: the frequency accumulator that produces a phase output; the phase-to-sine conversion algorithm block, and binary-weighted DAC to produce an analog output (Fig. 4.10). Additionally, in the current implementation we also include an I/Q image spur rejection lter. Since the desired output is up at to 200 MHz, the sampling rate is raised to 800 MSPS, such that the closest image lies at 600 MHz. This would enable a relaxed image 155 Fig. 4.10: Typical DDFS architecture consisting of accumulator, phase-to-sine con- version and DAC. An additional lter removes the image spurs. spur rejection lter implementation at a cuto frequency of 200 MHz. The phase- to-sine algorithm is usually implemented as a rotation-based algorithm, such as the CORDIC [90, 93, 94]. The accuracy of the algorithm depends on the number of iterations taken to converge to the correct sine value, which is usually 15-16 iterations [93] for an SFDR of 50-60 dB, equivalent to 20 ns. Apart from the number of iterations required, several state machines are used for such a computation, thus increasing the 20 ns latency by a multiplier. Additional synchronization to solve setup and hold time errors will introduce further latency. The allowable latency for the phase-to-sine conversion unit can be visualized better using the signal path characteristics as shown in Fig. 4.11. The total allow- able latency for the phase-to-sine conversion unit is only 15 ns, assuming that the total latency allowed is 25 ns, including the lter. This conversion time has to apply for an SFDR of 50 dB and the power consumption has to be as low as possible as 156 Fig. 4.11: Signal path characteristics for the DDFS. The total allowable latency for the phase-to-sine conversion unit is only 15 ns, assuming that the total latency allowed is 25 ns, including the lter. This conversion time has to apply for an SFDR of 50 dB. The power consumption also has to be as low as possible. well. Therefore, state-machine algorithms that introduce latency (regardless of the clock speed or technology) are not useful in this application. Since the bottleneck lies in the digital section of the DDFS-DAC, it is noteworthy that the application requires only to output sinusoidal waveforms, i.e. the DAC does not have to be designed independent of the digital section. Examining this co-design path, we realize that the DAC can be weighted in a nonlinear manner to convert a linear phase ramp to a sinusoidal output waveform. In such a case, as shown in Fig. 4.12, the phase-to-sine algorithm section would simply be replaced by a binary-to-thermometer converter, which can ideally have zero latency! However, 157 Fig. 4.12: Using a sine-weighted DAC instead of a linear DAC can produce si- nusoidal outputs while replacing the state-machine based algorithm section of the digital circuits to a simple binary-to-thermometer converter. as we shall see the DAC resolution is now related to the frequency word resolution. Assume that the frequency word has a resolution of P bits. The output wave- forms required to be generated, given a frequency f are V out =A sin 2nf 2 P andA cos 2nf 2 P ; f2 1; 2 P ; (4.5) where A is the DAC full-scale output amplitude and n is the time index. The accumulator outputs a wrapped phase word, 2nf=2 P . Assume that the amplitude A has a resolution of M bits. Therefore, the desired output (only sine shown for brevity) is V out = 2 M 1 sin 2nf 2 P ; f2 1; 2 P : (4.6) The resolution P is determined by the application. In this case, for a 1 MHz frequency resolution and a sampling rate of 800 MSPS, the number of bits required is (log 2 (80015)) = 14 bits, keeping in mind the factor 15 for the sake of harmonic 158 Fig. 4.13: DDFS output waveforms are repetitive for four quadrants, and can be replicated by mirroring the output across=2 and, i.e. the x-axis and y-axis every 2 total phase. After wrapping the phase every =2, the DDFS output phase can be further divided into two parts, each generating the outputs only for =4 using the sine and cosine DACs. These waveforms can be swapped again, thus saving DAC area. generation. For a conservative implementation, we use a 15 bit frequency word in our implementation. It is noted that total DAC area can be reduced by realizing that the output sinusoidal waveform is repetitive for the four quadrants of the phase, i.e. a DAC has to generate outputs only from 0 to =2, after which these outputs can be mirrors and raised to produce the total output. This implies that the phase can be rewrapped from [0; 2] to [0;=2]. Further, since quadrature outputs are desired, the [0;=2] interval can be split into two DACs whose waveforms are swapped at the appropriate time, as shown in Fig. 4.13, in order to save DAC area further. 159 Fig. 4.14: Simulations for the compressed DDFS-DAC shows that the SFDR does not improve after a certain value of M 13. Therefore, the total interval of importance in the frequency word reduce from [1; 2 P ] to [1; 2 P =8], thus saving 3 bits of control for the DAC current sources. Equa- tion (4.6) is rewritten now as V out = 2 M 1 sin 4 nf 2 P ; f2 1; 2 P : (4.7) The number of phase entries still remains equivalent to 12 bits, which is 4096 DAC entries, a highly impractical number given the DAC requires an M bit resolution. Further compression of the nonlinear DDFS-DAC can result in a smaller DAC at the cost of output SFDR. If the rest P 3 bits undergo a 3-way segmentation as P = a +b +c, the desired frequency is then f = x 2 b+c +y 2 c +z, where 160 x2 (0; 2 a 1),y2 (0; 2 b 1), andz2 (0; 2 c 1). For each time indexn the output voltage is then given by V out =A sin n 4 x 2 b+c +y 2 c +z 2 a+b+c ; A = 2 M 1: (4.8) The above quantity still requires a 3-dimensional DAC of size 2 a 2 b 2 c equaling 4096 entries for perfect reconstruction. However, one can expand and project (4.8) to produce two 2-dimensional DACs of size 2 a 2 b and 2 a 2 c [95] as V out A sin n 4 x 2 b+c +y 2 c 2 a+b+c | {z } Coarse;2 a 2 b DAC + A cos n 4 x 2 b+c + y 2 c 2 a+b+c sin 2nz 2 a+b+c | {z } Fine;12 c DAC ; (4.9) where y represents an average value of y, and cos 2nz=2 a+b+c factor in the rst term is approximated to unity due to z representing the LSBs. A further compression in this implementation, projects the 2 a 2 c matrix to a single 1 2 c current source row, thus halving the total DAC area. At this point, the SFDR of the output is determined by the choice of M and the values of a, b and c. In the current implementation extensive simulations show that for a =b =c = 4 the SFDR is limited to 58 dB for M 13 over the entire Nyquist range. MATLAB simulation results for SFDR versus variable M is shown in Fig. 4.14, showing that performance does not improve beyond a certain DAC amplitude resolution. 161 Fig. 4.15: The current source weights for the coarse DAC are determined by splitting the DAC into a 16 16 current grid and calculating the steps based on an index. The ne DAC is then used for extrapolating the coarse DAC current sources. Therefore, M = 13 is chosen, with a = b = c = 4. Given these values, the digital core outputs 256 pins for each coarse DAC, 16 pins for each ne DAC and additional pins to raise the output of waveforms to full scale. Further, multiple pins turn on and o large switches to swap cosine and sine waveforms at the output of the DAC and for mirroring around phase =2. 4.4.2 DAC Construction Rewriting (4.9) with actual values of the bits, we obtain V out 2 12 1 sin 2nf MSB(512) 2 15 cos 2nf LSB(14) 2 15 | {z } 1 162 + 2 12 1 cos 2n f MSB(512) 2 15 | {z } Average Value sin 2nf LSB(14) 2 15 : The ne DAC is a 16 1 DAC which is used for extrapolating the 16 16 coarse DAC. Consider the construction of the coarse DAC. We are interested in the values (2 12 1) sin n 4 x 2 8 +y 2 4 2 12 ; for eachx andy, which will be used to determine the DAC weights. If hypothetically the current sources are placed in a row/column format each with 16 elements, an index pair (i;j) can be dened such that the cumulative DAC amplitudes are V out = 2 12 1 sin 2(256(i 1) + 16(j 1)) 2 15 ; (4.10) wherei2 [1; 16] is the row selector andj2 [1; 16] is the column selector. The DAC is setup in a manner such that all the current sources prior to the ith row are also turned on, given a (i;j) pair from the accumulator binary-to-thermometer output. Therefore, for every (i;j) the current source value is determined by subtracting the value of (4.10) for (i;j 1). If we are at a new row, i.e. at (i; 1), the value of (4.10) subtracted is for (i 1; 16). After the coarse DAC is turned on, the ne DAC is then used to extrapolate the output current. The construction of the DAC is summarized in Fig. 4.15, with the values of the actual weights of the current sources used in the implementation. 163 Fig. 4.16: At time index n = 1, current sources till (Row 2, Col. 15) are turned on. At n = 2, additional sources turn on till (Row 4, Col. 14) and increasing the amplitude. This process continues till = =4. The weights of current sources transfer the sin() slope to enable phase-to-sine conversion. To visualize the output current, consider the step-by-step nonlinear coarse DAC operation as shown in Fig. 4.16. As shown, at time index n = 1, current sources till (Row 2, Col. 15) are turned on. At n = 2, additional sources turn on till (Row 4, Col. 14), increasing the amplitude. This process continues till = =4. The weights of current sources transfer the sin() slope to enable phase-to-sine conversion. The output is then extrapolated by the ne DAC. In a similar manner, the range (=4;=2) is also generated, only by the cosine DAC, thereby completing the waveform. Note that the sinusoidal waveform is monotonically increasing in (0;=2). Therefore, as the indices (i;j) increase, additional current sources are turned on, i.e. no current source needs be turned o until the next quarter phase cycle. 164 Fig. 4.17: After waveform generation, additional amplitude raising DACs bring the signal to full scale. Swapping switches before the load generate the full quadrature output. After the waveforms are generator for the quadrant, additional DACs are re- quired to perform the raising function that serves to mirror the waveforms when the phase reaches. These amplitude raising DACs and their function is shown in Fig. 4.17. Additional switches that perform waveform swapping are present at the output before loading, to swap the currents at the appropriate instances in order to complete the quadrature output. Let us reexamine the signal path characteristics explained earlier using Fig. 4.11. With the DDFS-DAC architecture now using the sine-weighted DDFS-DAC architecture, the total latency is hypothetically zero, as all processes are instanta- neous. Assuming a 5 ns latency for the digital section determined entirely by gate 165 Fig. 4.18: Introducing the sine-weighted DDFS-DAC architecture has eliminated the latency that is produced by the phase-to-sine algorithm. delay requirements, the total hopping time can still be restricted to around 15 ns for the system. Since there no longer exist state machines in the digital implemen- tation, all delays and synchronization requirements are entirely determined by the technology and not restricted by the algorithms used. The tradeos here however are the SFDR at the output, and the dependence of the DAC resolution M with the frequency resolutionP . Also noteworthy is that this is a \rapid frequency hop- ping" system - the output is produced is instantaneously not only between hops, but also as frequency word instructions are available. This will be later validated experimentally. 166 4.5 Details of Circuit Design The technology used for the implementation is a 0.13m CMOS process. The core circuits in the system consist of the digital section, with the frequency word input, the binary-to-thermometer converter and output digital buers to drive the DAC. The DAC consists of the coarse, ne and amplitude raising DACs as described earlier. The output is then ltered by low pass lters with a cuto frequency of 200 MSPS. Each component is now described in detail. 4.5.1 Digital Section The top level schematic of the digital section is shown in Fig. 4.19. The digital section has the 15 bit frequency word as the input to the accumulator. For the 0.13 m technology, it is not possible to implement the accumulator with a single delay using a 15-bit adder 0.13 m without timing violations. Therefore, the system was split into three 5-bit pipelined adding stages, each using the carry look ahead adder architecture to generate the carry instantaneously. The total latency of the accumulator is thus 5 ns. The accumulator has a 15 bit output that is representative of the phase at the programmed frequency f. At the output of the accumulator, the 3 bits used for the amplitude raising DACs, the waveform mirroring operation, and the waveform swapping operation are separated. The result is a 12 bit word that is split into two data streams each for the sine and cosine operations. The 12 bit word is further split into its 167 Fig. 4.19: Detailed schematic of the digital section. (a;b;c) components, i.e. separated as 4+4+4 bit streams. Each 4 bit stream is then input to a binary to thermometer converter, giving the (i;j) index for the coarse DAC and the 16 bit thermometer word for the ne DAC. The (i;j) indices are further expanded to produce a two dimensional 256 bit of data corresponding to each element of the coarse DAC. The result of the digital section therefore has data for the swapping switches, the 2 256 bits for the coarse DACs, 2 16 bits for the ne DACs, and bits for the amplitude raising DACs. For synchronization purposes and to avoid timing violations, four stages of reg- isters have to be introduced at intermediate stages of the computations described. However, note that the system is still open loop, and there are no state machines. The total delay of the computation stage due to these slack and synchronizations registers (indicated with red and blue dotted lines in Fig. 4.19) is therefore 5 ns. 168 Fig. 4.20: Layout of the digital section. The digital section is designed in Verilog, veried using Cadence Incisiv. The netlist is generated using the Synopsys Design Compiler tool with the following con- servative parameters used in selecting standard cells: maximum delay and rise/fall time of 0.125 ns, load capacitance of 100 fF (to account for routing parasitics par- ticularly to the switches for the large amplitude swapping DACs) and maximum fanout of 16 for all paths. The layout of the digital section is generated using the Cadence Encounter tool (shown in Fig. 4.20). The area of the digital section is 1050 m 320 m. Given the number of output pins is large (approximately 1500), pins are placed at all edges of the digital section except for a small section in the center allotted for the 15 bit input frequency word f in , in order to save total area. 4.5.2 13-Bit Sine-Weighted DAC The 13-bit current-steering DAC outputs a total current of 12.5 mA to 23 on-chip loads to give a full scale peak-to-peak voltage of 287 mV. As shown in Fig. 4.21a, the 169 DAC is implemented as minimum size switches (with dummy switches to reduce switching transients at the input) that are compactly laid-out right next to the 1500 logic outputs of the DDFS, available at the edge of the layout shown in Fig. 4.20. Shown in Fig. 4.21b is a minimum design rule (occupying minimum possible area) highly compact, custom layout of a dierential switch with dummy switches and buers. Logic lines leading to the switch, therefore, also have minimum length. Long common mode current lines are then drawn to current sources of large length (to reduce mismatch) with two cascode transistors (to improve output impedance). The unit current is 1.525 A, and the output impedance of the current source is designed to be of the order M s, thus requiring at least two cascode transistors for the current source. One current mirror is used for each DAC, giving a total of 8 current mirror sources. The layout of the DAC current sources is performed in a pseudo-common cen- troid manner that is conducive to the algorithm. For the coarse DAC with 16 16 sources, rows and then columns are switched in sequence as mentioned in the pre- vious section (see also Fig. 4.16). At moderate output frequencies, simultaneous switching of entire rows occurs more often than columns, i.e. rows take precedence over the columns. Thus, to spread out switching events as much as possible and reduce systematic error, each column-set of 16 sources is laid-out in a common cen- troid manner [96], and within each set, 16 sources corresponding to the each row within the column are laid-out again in a common-centroid manner. The overall 170 Fig. 4.21: (a) Details of the unit current source used for the DAC. Tha layout is performed in a common centroid manner for the current sources which are connected remotely to switches located close to the DDFS output. (b) The dierential switch layout (M3 and M4) with dummy switches (M1 and M2) and inverter buers (B1 and B2). compact layout with switches close to DDFS outputs mitigates the need for high speed latches at the input. 4.5.3 Image Spur Rejection OTA-RC Filter An OTA-RC lter follows the DDFS-DAC output to remove the image spurs, and is optimized for performance at 200 MHz bandwidth while not disturbing the SFDR of the DDFS-DAC system. To achieve a minimum of 60 dB of rejection at the nearest sampling image spur of 600 MHz, a 3-stage Chebychev Filter is used. The OTA-RC structure, with folded cascode op-amps is chosen as it provides the best 171 Fig. 4.22: At most frequencies, rows turns on more often than columns. To reduce systematic errors, column-sets are laid-out common centroid, and each set is also common centroid within (example shown for Column 7). tradeos between dynamic range and power consumption. A summary of the lter schematics is shown in Fig. 4.23. The passives are chosen in a manner to not load the lter output and the lter gain is variable using the input resistors R x of the rst stage. The three stages are designed to work with progressively increasing quality factor in order to provide for better noise performance inband. The transistor level design of the lter posed several challenges: since the cuto bandwidth is 200 MHz, the GBW has to be high, while simultaneously keeping the gain high in order to obtain a large SFDR. While noise is not a critical performance criterion, some noise performance was sacriced and all transistors were designed at a small length of 120 nm. Furthermore, the high bandwidth implied a small feedback capacitance of 100 fF which was susceptible to parasitics. In spite of several iterations, the measurement results as will be seen later, were unable to 172 Fig. 4.23: Details of the 6th Order OTA-RC Chebychev lter schematic. achieve a perfect cuto at 200 MHz as the bandwidth and quality factor of the 2nd and 3rd stages were deliberately reduced to prevent unnecessary peaking caused by the parasitic capacitances. The inability to reduce the capacitor sizes implied that for the high bandwidth the feedback resistors have to be smaller, which would aect the intrinsic gain of the op-amps. Such tradeos were carefully considered before selecting the parameters shown in Fig. 4.23. Within the bandwidth of interest, the lter has a theoretical settling time of at most 10 ns for a frequency hop, and is designed for an SFDR of approximately 173 Fig. 4.24: Chip photograph and summary of measurement results. 55 dB, while consuming 23 mW of power in total. Two such lters are designed and implemented for the sine and cosine quadrature paths. Additional buers are placed at the output of the lters to accommodate a 50 output load. 4.6 Measurement Results The system is implemented in a 0.13 m CMOS technology [97] with the chip diagram shown in Fig. 4.24. A summary of the performance at the output is also shown in Fig. 4.24. The design uses two supply domains, 1.2 V for the digital circuits and 1.5 V for the DAC and image spur rejection lters. The 1.5 V is generated using on-chip regulators from an external 2.5 V supply. The input to the lters coming from the DAC loads, can be switched to those coming from a set of input buers to test the lters standalone. The lters also have attenuators at the output, in order to ensure that standalone nonlinearity measurements are not 174 Fig. 4.25: Image spur rejection lter results: (a) Small signal lter transfer function across various gain control settings. (b) IIP2 and IIP3 of lter across the frequency of operation. aected by the distortion introduced by the 50 output buers [98]. Note that of the 240 mW consumed by the 1.5 V reference around 160 mW is consumed by the regulators and buers alone. We begin by characterizing the image spur rejection lters. In this case, the output from the DACs are disabled, and the input buers are enabled in order to provide signals from o-chip. The small-signal measured transfer function is shown in Fig. 4.25 to simulations. As is seen from Fig. 4.25a the cuto frequency is around 180 MHz instead of the intended 200 MHz, due to the eect of the parasitics at higher frequencies - the STF is sensitive to small changes in the parasitics, which would explain the dierences between simulated and measured proles. However, the results were consistent across dierent gain values. The Input third-order inter- cept point (IIP3) plot shown in Fig. 4.25b is consistent across the frequency range 175 Fig. 4.26: DDFS-DAC with Filter measurement results: (a) SFDR of the system with clock at 800 MHz and varying input frequency. (b) SFDR of the system with varying clock frequency and f in at 1/16th of the clock frequency. while as expected the Input second-order intercept point (IIP2) being a function of the mismatch worsens over frequency as common mode capacitances decrease the Common Mode Rejection Ratio (CMRR). The input referred, measured RMS noise voltage, integrated over a 1 GHz band- width is approximately 690 V. Using the expression, SFDR dB = 2=3(IIP3 dBV P noise;dBV ) [12], the SFDR of the lter is calculated as 52 dB. A useful metric to compare lters is the FOM given by FOM = 10 log SFDR BW Power per Pole ; in the units of 1/Joule [12]. Given a total power consumption of 23 mW for 6 poles, an eective bandwidth of 180 MHz and SFDR of 52 dB, the FOM is 159 dB, which is close to state-of-the-art performance [12]. 176 Fig. 4.27: Simulations of the schematics with non-zero mismatch at the swapping switches shows that the quadrature waveform can be aected severely due to these large transistors. The result is a reduction in the SFDR performance. The system SFDR versus frequency is shown in Fig. 4.26a, at a clock frequency of 800 MHz. The SFDR results deviate more at higher frequencies from the sim- ulation results. While this was not expected during measurements, simulations were performed after tapeout to determine the cause of error. It was seen that one major drawback of the architecture is the use of swapping switches between the two quadrature outputs. Since a large current is being switched, the waveforms are especially susceptible to mismatches of the swapping transistors shown in Fig. 4.21a. Chip level simulations were performed with 5-10% mismatch of the transis- tors included. The simulation results for an output generated at 55 MHz are shown in Fig. 4.27. The result corresponds to what is seen in measurements. 177 Fig. 4.28: Measured output spectrum at (a) 66 MHz, (b) 180 MHz output. The system produces output up to a clock frequency of 950 MHz after which timing errors in the digital section prevent from producing a useful output. As shown in Fig. 4.26b, the SFDR steadily improving at lower clock rates, and drops rapidly at higher clock frequencies. The spectrum of the worst case SFDR at around 180 MHz, along with the spectrum at 66 MHz are shown in Fig. 4.28. The spurs are dominated by the second harmonic as well, showing that indeed the nonlinearity of the dierential DAC is not the only cause for the SFDR degradation. A control circuit placed in front of the digital section enables the testing of the hopping performance by changing input frequency words at programmable rates, starting from 25 ns for each frequency hop. The control circuit can produce up to 4 frequency hops successively, and stores frequency information for rapid execution purposes. 178 Fig. 4.29: System hopping performance result: (a) A single frequency hop from 100 MHz to 50 MHz shows a hopping time of less than 15 ns. (b) Of this 15 ns, 10 ns comes from the latency, implying 5 ns should be the total analog delay. This result is shown in the plot of the instantaneous frequency versus time. Measurement results of a single hop from 100 MHz to 50 MHz are shown in Fig. 4.29a conrming that frequency hopping does takes place within 15 ns. Of this 15 ns, from simulations, 10 ns comes from shift registers in the DDFS core to satisfy timing requirements and the rest from the analog delay of the circuits such as those from the lter phase transfer function. To validate this assertion, the instantaneous frequency is plotted versus time as shown in Fig. 4.29b. Since the DDFS-DAC is a phase continuous system, the instantaneous frequency is dened as f inst: = 1 2 d dt arcsin V out A ; 179 Fig. 4.30: Rapid frequency hopping from 100 MHz! 50 MHz! 100 MHz! 200 MHz, with 25 ns spent on each frequency. Fig. 4.31: Added phase noise measurements with the output at 100 MHz. whereA is the amplitude of the signal. As can be seen, the instantaneous frequency changes from 100 MHz to 50 MHz within about 5 ns, with an error of 0.72 ns within 5% o the desired frequencies. 180 To validate the latency of the digital section, instantaneous or rapid frequency hopping tests are performed by tuning the control circuit to change frequency words every 25 ns. The result in Fig. 4.30, shows distinctly observable frequency outputs going from 100 MHz! 50 MHz! 100 MHz! 200 MHz before repeating the frequency sequence, implying the system settles rapidly with around 15 ns latency. All measurements are performed from chip input to output, and thus also include any latency introduced by the PCB and measurement equipment. Note that the output at 200 MHz is relatively attenuated due the aforementioned cuto frequency of the Chebychev lters at 180 MHz. A phase noise measurement was also performed at the 100 MHz output; the re- sult is shown in Fig. 4.31. The added phase noise, after accounting for the division ratio of 8 (clock of 800 MHz) is 20 dB. The noise oor of the output was measured to be -128 dBc/Hz. Quadrature error between the sine and cosine output was mea- sured to be around 7.57% (corresponding to 6:81 ). The quadrature performance is measured as a percentage error of the zero-crossing time intervals between sine and cosine waveforms captured in the oscilloscope (after averaging). Note that these measurements may have better accuracy with no on-chip attenuation and better oscilloscope resolution. Table 4.1 shows the performance of the DDFS-DAC within the system, in com- parison to several published designs. It is important to note that the DDFS-DAC occupies about half the total die area and consumes about 200 mW of the total 181 Table 4.1: Performance Comparison with DDFS-DAC Designs in Literature [95] [99] [100] This Work a Process 0.13 m SiGe 0.09 m CMOS 0.35 m SiGe 0.13 m CMOS Quadrature No No No Yes Acc. Bits 11 24 9 15 DAC Bits 10 (Nonlinear) 11 (Hybrid) 8 (Linear) 13 (Nonlinear) Max. Clock 8.6 GHz 1.3 GHz 5 GHz 0.8 GHz Die Area 14 mm 2 2 mm 2 2.1 mm 2 3.8 mm 2 Avg. SFDR 33 dB 53 dB 47 dB 33 dB Hop Time - - - 10 ns Power 4800 mW 350 mW 460 mW 200 mW a DDFS-DAC performance only (Filters not included) power. Of the 15 ns measured hopping time, by design, the DDFS contributes 10 ns. Though the SFDR of the DDFS-DAC is comparable to recently published results, the hopping time is also addressed in this work, and is limited entirely due to data critical paths, as the architecture uses no state machines. 4.7 Conclusions In this chapter we discussed an application for electronic warfare and military com- munications, where a rapid frequency hopping system is essential. After examining the limitations of conventional frequency generation architectures, we established an architecture that considers a lower frequency DDFS as a reference input to a multiplier and an injection locking stage at higher frequencies to eectively achieve a low power, yet fast hopping implementation. 182 The latency of the DDFS forms the bottleneck and hence, became the focus of the integrated circuit implementation. A mixed-signal architecture that uses a codesigned and combined DDFS-DAC is proposed where the digital section la- tency is brought down to just synchronization delays. This is done by changing a linear DAC to a sine-weighted DAC implementation, thereby reducing the digital algorithm section to a binary to thermometer converter. An integrated circuit im- plementation that included the image spur rejection lter could produce quadrature DDFS-DAC output at less than 15 ns hopping time. While the implementation only considers the baseband section of the architec- ture discussed, the intended goal is to show that power consumption for a fast hopping frequency synthesizer can be signicantly reduced by combining baseband mixed-signal reference generation with RF injection locking at higher frequencies. The architecture and mixed-signal approach discussed herewith can possibly lead to further investigation, particularly in examining tradeos in synchronization speed and bandwidth. 183 Chapter 5 Conclusions 5.1 Summary This thesis examines the baseband section of a modern radio receiver, that performs channel selection and quantization. The primary motivation has been to create a radio receiver free of bulky analog lters both in the front-end as well as the base- band section, while providing identical functionality using mixed-signal approaches instead. In order to achieve this goal, multiple implementation steps were used. We rst considered a feedback system that completely eliminates the baseband lter while replacing with an inverse lter, post-quantization that performs an identical function at the front-end. The ltering-ADC adapts to the signal structure while being fully recongurable and scalable, due to the use digital lters. Theory and analysis shows that the oversampled ltering-ADC is equivalent in performance to 184 modulators, while additional information about the signal structure improves performance signicantly. The proposed ltering-ADC concept was then analyzed from the perspective of a discrete-time, equalization-based quantizing system that can tolerate a blocker channel adjacent to the desired channels, while relaxing the requirements for the baseband lter. A 200 MSPS ADC implementation shows that indeed energy e- ciency of the ltering-ADC improves when additional information about the struc- ture of the input signal is known apriori. Having established that digital lters in a feedback conguration with the quan- tizer, can indeed result in a power-ecient baseband, the ltering-ADC was com- bined with the software-dened radio to give a synergic receiver that has neither the front-end module nor that baseband analog lter, as was the goal of the thesis. Band selection in the front-end was performed using the current-mode impedance upconversion technique typical of SDRs, while channel selection was performed at RF using the proposed ltering-ADC feedback technique. We also show theory that interprets the ltering-ADC as a mixed-signal, semi-digital IIR lter thereby enabling very simple design of feedback coecients. The latter part of the thesis describes the design and implementation of a 800 MSPS DDFS that uses a sine-weighted DAC to signicantly reduce the latency of the system to less than 15 ns, in spite of the low sampling rates. This high- resolution frequency synthesizer is proposed to be used as a part of fast-hopping 185 clock that is power ecient due to the low-latency baseband reference, while using the fast-hopping injection locking for frequency generation at higher frequencies. 5.2 Recommendations for Future Work The ltering-ADC system introduced in this thesis is adaptible based on the input signal structure. In this thesis we have considered a class of possibly oversampled signals where Power Spectral Density (PSD) is the primary input structure un- der consideration. However, input structure may present itself in the time-domain as well. A common example is the case where ADCs are designed for biomedical signals. The relative inactivity of such signals can potentially improve energy e- ciency when the structure is presented apriori [101]. An unresolved aspect of the ltering-ADC from a theoretical standpoint, is how to optimize resolution and per- formance when signal structure is known simultaneously in the time and frequency domain. In general, I believe quantization with knowledge of signal structure is a fascinating topic that is worthy of several innovations in the future. From the perspective of a SDR, the proposed system presents similar issues as those of a feedback system with multiple ltering stages (such as high order CT ADCs): stability issues with multiple poles and latency. The choice of lter coecients, whether feedback or feedforward in such cases is critical. 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Dover, 9th edition, 1964. 196 Appendix A OTA-RC Filter SNDR Limit A simplied model for the OTA-RC lter in Fig. A.1 gives a transfer function V out (s)=V in (s) = [g f (g f +sCg m )]=[(g f +sC)(g d +g m +g f )+g f g d ], whereR = 1=g f is the value of the feedback resistors. It is assumed that for a functioning design, OTA gain is relatively high and the feedback impedances are large, giving the condition: g m g d g f . Under these conditions, and at low frequencies: V out (s)=V in (s)1. Also, V x (s)=V in (s) g d =g m . Let I 3 = g m3 v 3 x , the current due to third-order nonlinearity at the output, thus giving, V out (s)=I 3 (s) 2=g m . Consolidating the results, at low frequencies, v out =v in + 2g m3 g 3 d g 4 m v 3 in = 1 v in + 3 v 3 in : For a dierential pair input, with tail current I SS , we know that 2g m3 g 3 d =g 4 m = p 9=(8KI 5 SS )g 3 d , where K = n C ox W=2L, the standard transistor parameters [102]. Dening = 2g m =I SS and g d = I SS =, we simplify as v out =v in + (3=( 3 ))v 3 in . 197 Fig. A.1: Model for single stage OTA-RC lter. Of the three noise sources, the input resistor contribute the most noise under the condition g m g d g f . The noise at the output is P noise = 8kTB=g f . Using the relation [12] SNDR = A 2 IIP3 P noise = (4=3)j 1 = 3 j P noise ; the SNDR for a single stage of the OTA-RC lter is: SNDR = 2 P lter =(18kTB V DD ), where P lter = I SS V DD and = g d =g f . For an N-stage OTA-RC lter, the SFDR remains the same as IIP3 and noise scale, while the power increases N-fold. Assuming gain G scales 1 , SNDR lter+VGA = 2 P lter+VGA (18kTNGB V DD ) from where FOM lter+VGA as dened by (2.2) is obtained. 198 Appendix B Discrete-Time Filtering and Quantization This appendix establishes limits on the output swing of a ltered bandlimited signal. Eective resolution of the proposed ADCs are also derived. B.1 Discrete-Time Filtered Signals Consider a band-limited signal x(t) of single-sided bandwidth B and such that jx(t)j V fs =2, sampled at a rate f s = 1=T s . The signal is supported in the frequency domain on [f 0 ;f 0 +B]. We assume the Nyquist-Shannon criterion, i.e., f 0 +B <f s =2. LetH(z) be a nite, discrete-time lter continuous inz = 2jf=f s . In Theorem 1, we determine the maximum of the output signal of H(z) given x(t) as the input. 199 Lemma 1.1: Let ~ x(t) be a set of arbitrary signals with well dened single- sided Fourier transforms, ~ X(f). We assume that the conditions for uniqueness and existence of all ~ X(f), and those of nite-energy are satised [103]. max ~ x(t) (maxj~ x(t)j) = max ~ X(f) Z 1 0 j ~ X(f)jdf: (B.1) Proof: By denition j~ x(t)j = Z 1 0 ~ X(f)e 2jft df Z 1 0 ~ X(f)e 2jft df = Z 1 0 j ~ X(f)jdf ) maxj~ x(t)j = Z 1 0 j ~ X(f)jdf: By the existence and uniqueness assumption, we obtain the result. To show equality and complete the proof, we choose a signal ~ x 1 (t) = max ~ X(f) Z 1 0 j ~ X(f)jdf sin (2f 0 t +); for arbitrary f 0 and . The Fourier transform of ~ x 1 (t) gives the same maxima. Theorem 1: Given the signal x(t) and the lter H(z) as dened in Section II, max X(f) x(t)F 1 H 2jf f s = V fs 2 max f2[f 0 ;f 0 +B] H 2jf f s ; (B.2) whereF 1 is the inverse Fourier tranform. 200 Proof: The problem formulation considers the ltered output of the continuous- time signal. Rewriting, max X(f) x(t)F 1 H 2jf f s = max X(f) Z f 0 +B f 0 X(f)H 2jf f s e 2jft df max X(f) Z f 0 +B f 0 X(f)H 2jf f s e 2jft df max f2[f 0 ;f 0 +B] H 2jf f s max X(f) Z f 0 +B f 0 jX(f)j df: From assumptions on x(t), we have max x(t) (maxjx(t)j) =V fs =2. Using Lemma 1.1, we obtain the result. To show equality and complete the proof, we choose X(f) = V fs 2 (ff 0 ); wheref 0 = arg max f2[f 0 ;f 0 +B] H 2jf f s ; resubstitute in the original problem, and perform the inverse Fourier transform to obtain the same maxima. Corollary 1: Given the sampled signal x(n) of x(t), and the impulse response h(n) of the lter H(z), max X(f) jx(n)h(n)j = V fs 2 max f2[f 0 ;f 0 +B] H 2jf f s : (B.3) 201 Proof: Assuming the Nyquist-Shannon criterion is satised, X(f) is fully pre- served without aliasing in the spectrum of x(n). The rest of the proof is identical to Theorem 1. B.2 Quantization Theorem 2: Given a signal x(t), lters H(z) and H fb (z), and parameters k and G as dened in Section II.A (see also Fig. 9), the eective number of bits at the output of the digital reconstruction lter z k =H(z), M e , is given as: M e =M + log 2 (G) =M log 2 max f2[f 0 ;f 0 +B] H 2jf f s : (B.4) Proof: The digital reconstructed signalY (z) has an output full scale rangeGV fs . However, the quantizer step is V fs =2 M . Therefore, the total resolution of Y (z) is GV fs (V fs =2 M ) =G 2 M : Dene 2 M e =G(2 M ) and obtain the result. Corollary 2.1 (Delta Modulation): Choosing H(z) = 1z 1 , f 0 = 0 and k = 1 gives H fb (z) = 1=G. Assuming an oversampled signal with f s = 2NB;N > 1, the eective number of quantization bits is given as: M e =M 1 log 2 [sin(=2N)]. Proof: Obtained by direct substitution into (B.4). 202 Corollary 2.2 (\Bandpass" Delta Modulation): Choosing H(z) = 1 +z 2 , f 0 = f s =4B=2 and k = 2 gives H fb (z) =1=G. Assuming an oversampled signal with f s = 2NB;N > 1, the eective number of quantization bits is given as: M e =M 1 log 2 [sin(=2N)]. Proof: Obtained by direct substitution into (B.4). 203 Appendix C Signal Energy Distributions This appendix examines in detail the nature of energy spectral density in deter- mining the maximum swing of a signal and its ltered versions. C.1 Denitions and Periodization We are concerned with a signalx(t) for which a Fourier transformX(f) is denable, and that which has nite energy. Denition 1 (L p Spaces): A signal x(t) belongs to spaces L p (R);8t2R if jjx(t)jj p = Z 1 1 jx(t)j p dt 1=p <1; p = 1; 2; 3;:::; whereR is the set of all real numbers. 204 Denition 2 (Fourier Transform): A signalx(t)2L 1 and its Fourier transform X(f)2L 1 are related as: x(t) = Z 1 1 X(f)e 2jft dt; X(f) = Z 1 1 x(t)e 2jft df: We are only concerned with these type of signals henceforth. From the above, we see that x(t) and X(f) form a unique mapping withF 1 fFfx(t)gg =x(t), where F is Fourier transform operation. Denition 3 (Finite Energy): A signal x(t) 2 L 2 and its Fourier transform X(f)2L 2 , the signal energy is given as: Signal Energy = Z 1 1 jx(t)j 2 dt = Z 1 1 jX(f)j 2 df: The above relation is also known as Parseval's Theorem. We are only concerned with signals of nite energy. In combination with Denition 2, we are thus interested in x(t);X(f)2L 1 \L 2 . Denition 4 (Energy Distribution): For a deterministic signal x(t), the Fourier transform X(f) is also termed as the Energy Spectral Density (ESD). Henceforth, we will use the term \energy distribution" interchangeably withjX(f)j. 205 Theorem 3: The maximum of the signal swing maxjx(t)j of all signalsx(t) that share a common energy distribution is, maxjx(t)j = Z 1 1 jX(f)j df: Proof: The proof closely follows that of Lemma 1.1. It is useful to represent X(f) =jX(f)j expfj\X(f)g. With the absolute value operation, a loss of infor- mation occurs and \X(f) is eliminated, thus resulting in multiple x(t) with the same energy distribution. We note that to show equality we use a periodic signal in Lemma 1.1. A periodic signal by denition does not havex(t);X(f)2L 1 \L 2 . Herein, we use the Fourier series expansion as an alternate. For a periodic signalx(t) of periodT p , the Fourier series expansion is given as: x(t) = 1 X k=1 Re A k e j(2kt=Tp+ k ) ; whereA k and k represent the amplitude and phase at each point on the frequency axis, k=T p . In this case, it is sucient thatjjA k jj 1;2 are nite. In reality, signals input to an ADC are nite power signals, i.e., they have innite energy. However, the spectral characteristics of these signals are determined by the Discrete Fourier Transform (DFT) after quantization, which necessarily periodize 206 by windowing the signal to a nite time. This way a Fourier transform or Fourier series analysis is applicable. C.2 AM and FM Signals with IdenticaljX(f)j Consider an FM signal, x(t) =A cos(2f C t + 2(f) sin(2f I t)); where f C is the carrier frequency, f I is the information frequency and f is the frequency deviation. Using the Jacobi-Anger Expansion [104], x(t) =AJ 0 (2f) cos(2f C t) +A 1 X n=1 J n (2f) [cos (2(f C nf I )t)] +A 1 X n=1 J n (2f) [(1) n cos (2(f C +nf I )t)]; where J (z) represents the th Bessel Function. Note that the phase information is embedded in the \(1) n " multiplicand. Removing this multiplicand does not change the spectrum, but modies the expansion to y(t) = " J 0 (2f) + 1 X n=1 2J n (2f) cos(2nf I t) # A cos(2f C t): 207 The resultant signal is AM, and achieves the maximum possible swing given by Theorem 3, whereas the FM signal has only a swingA. It can be veried that both AM and FM signals have the same energy distributionjX(f)j. C.3 Filter Outputs If the signal energy distribution is known, Theorem 1 can be generalized to obtain better bounds. We assume that all signals abide by denitions earlier. Theorem 4: Given the signal x(t) and the lter H(z) as dened in Section II, max x(t)F 1 fH(f)g = Z f 0 +B f 0 jH(f)jjX(f)j df (C.1) Proof: The proof is again, closely related to Lemma 1.1: x(t)F 1 fH(f)g = Z f 0 +B f 0 H(f)X(f)e 2jft df Z f 0 +B f 0 H(f)X(f)e 2jft df Z f 0 +B f 0 jH(f)jjX(f)jdf ) maxjx(t)h(t)j = Z f 0 +B f 0 jH(f)jjX(f)jdf: To show equality and complete the proof, we choose a signal x 1 (t) = Z f 0 +B f 0 jH(f)jjX(f)jdf 208 sin (2f 0 t +) ; f 0 2 [f 0 ;f 0 +B]; for arbitrary . The Fourier transform of x 1 (t) gives the same maxima. C.4 Channelization It was established in Section III.A that the availability ofjX(f)j may be an over- optimistic case. However, a possible scenario is the channelization model, where some additional information about X(f) is available. Theorem 5: Given x(t) = P R r=1 x r (t), with x r (t) =F 1 fX r (f)g andjx r (t)j V fs;r =2;8r. Let allX r (f) be bandlimited toB r B and have a full scale range such that P R r=1 V fs;r =V fs . x(t) is sampled with frequency f s = 2N r B r ;N r > 1;8r. Furthermore, B r = rB=R; r2 [1;R] (consecutive and equal bandwidth divi- sions), thus giving N r =f s =2B r = (R=r)N where f s = 2NB. max x(t)F 1 ( 1 2jf f s 1 ) = R X r=1 V fs;r sin r 2NR : (C.2) Proof: Expanding, max X(f) R X r=1 x r (t)F 1 ( 1 2jf f s 1 ) R X r=1 max Xr (f) x r (t)F 1 ( 1 2jf f s 1 ) : 209 Using Theorem 1, with f 0 = 0;8r, R X r=1 max Xr (f) x r (t)F 1 ( 1 2jf f s 1 ) = R X r=1 V fs;r sin 2N r = R X r=1 V fs;r sin r 2NR : 210 Appendix D Output Noise of Lossy Dierentiator The lossy dierentiator is modeled for each phase of operation of the clock as shown in Fig. D.1a. The noise sources are due to the switch resistances R sw , the source resistanceR S , and the input-referred equivalent noise voltage of the op-amp, modeled as an equivalent noise resistorR A . In the charging phase 1 ,R sw ,R S and R A contribute to the output noise. Consider the noise contributed by R S during 1 . The impedance seen into the op-amp Z in is Z in = 1 s s(C 2 +C L )R out + 1 sR out (C 2 C in +C L (C in +C 2 )) + ((g m R out + 1)C 2 +C in ) : Note that Z in is large at lower frequencies; thereby we assume that R sw and R S are relatively small in comparison. Consider rst noise due to R S , V n;R S ; we are 211 interested in the noise voltage on the eective capacitance (C 1 +C 3 ) due to V n;R S . We note, S (C 1 +C 3 );R S (f)S R S (f) 1 1 +s(C 1 +C 3 )Z in 2 : (D.1) where S(f) is noise PSD. Assuming g m R out is large, the dominant pole in (D.1) is approximately g m C 2 =(C 2 C L + (C 2 +C L )(C in +C 1 +C 3 )). Therefore, jV n;R S j 2 kTR S g m C 2 C 2 C L + (C 2 +C L )(C in +C 1 +C 3 ) : This noise voltage is subject to the same transfer function as the input voltage. Therefore, S out;R S (f) = 4 f s 2 C 1 C 2 2 z 1 2 kTR S g m C 2 C 2 C L + (C 2 +C L )(C in +C 1 +C 3 ) ; where = 1(1=(g m R out C 2 =(C 1 +C 2 +C 3 +C in ))), the attenuation due to feedback. The transfer function of the switch noise sources as well as noise due toR A have the same dominant pole. Therefore, the total contribution during the charging phase 1 is given as S out; 1 (f) = 4 f s 2 C 1 C 2 2 g m (R S +R A )jz 1 j 2 +R sw (4j 1j 2 +j1z 1 j 2 kTC 2 C 2 C L + (C 2 +C L )(C in +C 1 +C 3 ) : 212 Fig. D.1: (a) Model of dierentiator in alternating clock phases for calculation of noise requirements. (b) Dierentiator output noise PSD; analysis versus schematic simulation for parameters chosen in implementation. Note that certain components of the noise are shaped by the lter transfer function. Consider the noise contributed by R sw across C 2 during 2 . Assuming g m R out is large, the eective capacitance seen by the noise source is stillC 2 . Therefore, the output noise is simply 4kT=C 2 f s . The contribution of the noise of the op-amp is dominated by the pole g m =C in . Summarizing, S out; 2 (f) = kT C 2 + kTR A g m C in 4 f s : (D.2) The total noise PSD at the output is S out; 1 (f) +S out; 2 (f). We are given the parameters, = 1:1, C 1 = 10C 3 , C 1 =C 2 = 2:5, C L = 3C (C is the ADC capaci- tance),R S 50 andR sw 100 . We assume that op-amp noise is dominated by the input transistors, implying R A 1=g m . Since C in aects the gain C 1 =C 2 apart from the noise, we obtain from calculations and iterative simulation, g m R out 30 213 dB andC 1 = 900 fF, to satisfy noise performance conditions as required by (2.30). For the chosen values, Cadence PSS+PNOISE schematic simulation results of the total output noise PSD compare reasonably well with analysis, given the several approximations (Fig. D.1b). SNR due to the dierentiator output noise only, cal- culated from integrating and equalizing the noise PSD, is 69.3 dB, which satises (2.30) with sucient margin. 214
Abstract (if available)
Abstract
Modern wireless communication systems require low power integrated circuit implementations of radio receivers that simultaneously offer programmability and reconfigurability in order to cover various communication standards. The software-defined radio paradigm offers front-end flexibility by eliminating the off-chip radio frequency front-end module and performing band selection, low noise amplification and frequency downconversion within the integrated circuit implementation. On the other hand, low power implementations that offer flexibility for the baseband section of the receiver (that performs channel selection, amplification and quantization by ADC) have not been the focus of the software-defined radio. ❧ The core program of this thesis consists of proposals of architectures that solve the power and dynamic range trade-offs for the baseband section of a modern wireless receiver. The proposed architectures use mixed-signal techniques to relax or completely eliminate power and area hungry baseband filters, which are often not scalable with technology. On the other hand, the filtering functionality that provides interference tolerance at low noise levels is retained due to the mixed-signal feedback system used, with quantization using the ADC performed as expected. Thus, this thesis describes scalable and reconfigurable filtering-ADCs that integrate the entire baseband functionality into a single power efficient system. ❧ The filtering-ADC architectures are then extended to include the software-defined radio to create a synergic receiver that performs channel selection with low power and area at a desired radio frequency. The thesis elucidates the theory behind the systems used, while the integrated implementations prove that area and power reduction is indeed possible. Applications considered include adjacent channel blocker tolerance such as in the case of Carrier Aggregation, and low power, low-rate communication systems, such as in the case of Internet of Things. ❧ The latter part of the thesis describes a mixed-signal architecture and its integrated circuit implementation, for the generation of fast-hopping frequency sequences with high frequency resolution over a wide range. The proposed architecture uses a fast-hopping DDFS-DAC that eliminates sampling at high rates while still having very low latency. The potential applications considered are secure communications and electronic warfare.
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Subramanian, Sushil
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Mixed-signal integrated circuits for interference tolerance in wireless receivers and fast frequency hopping
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Viterbi School of Engineering
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Electrical Engineering
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07/01/2018
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05/17/2017
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analog-to-digital conversion,blocker resilience,carrier aggregation,digital-to-analog conversion,direct digital frequency synthesizer,fast frequency hopping,frequency synthesizer,integrated circuits,interference tolerance,mixed-signal,OAI-PMH Harvest,signal structure,software-defined radio,wireless receiver
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Hashemi, Hossein (
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analog-to-digital conversion
blocker resilience
carrier aggregation
digital-to-analog conversion
direct digital frequency synthesizer
fast frequency hopping
frequency synthesizer
integrated circuits
interference tolerance
mixed-signal
signal structure
software-defined radio
wireless receiver