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High power, highly efficient millimeter-wave switching power amplifiers for watt-level high-speed silicon transmitters

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High power, highly efficient millimeter-wave switching power amplifiers for watt-level high-speed silicon transmitters

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Content HIGH POWER, HIGHLY EFFICIENT MILLIMETER-WAVE
SWITCHING POWER AMPLIFIERS FOR WATT-LEVEL
HIGH-SPEED SILICON TRANSMITTERS
by
Kunal Datta
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulllment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2016
Copyright 2016 Kunal Datta
Dedication
To my family
my Ma, my Bapi, my dearest Dada and my dearest Jaba
\The secret of success is constancy to purpose" - Benjamin Disraeli
ii
Acknowledgements
My PhD research would not have been possible without the support, motivation
and encouragement of many people.
First of all, I would like to thank my PhD. advisor, Prof. Hossein Hashemi. He
provided me an opportunity to visit his lab at University of Southern California
in the summer of 2009 when I was an undergraduate student in the Indian Insti-
tute of Technology, Kharagpur. My great experience in the lab (coupled with the
glorious California summer) motivated me to come back for my doctorate degree
next year ! I have learnt a lot from him, both regarding academics and beyond
academics. His passion about research has been instrumental in the way I grew up
to analyze problems critically and scientically. I would be always grateful for him
for transforming me from an undergraduate to a doctoral researcher !
My qualifying exam and defense committee, Prof. Mike S.W. Chen, Prof. Keith
Chugg, Prof. Aluizio Prata and Prof. Firdaus. E. Udwadia and Prof. Jayakanth
Ravichandran deserve sincere thanks for their time and eorts. I am grateful to
them for their feedbacks which has helped to enrich this thesis. I would also like
iii
to thank Prof. John Choma, who sadly passed away in 2014 for greatly motivating
me in one of the rst electrical engineering courses, I took at USC.
I am grateful for the guidance and support that I received from the senior
members of Prof. Hashemi's research group: Prof. Harish Krishnaswamy, Prof.
Ta-shun Chu, Prof. Firooz A
atouni, Dr. John Roderick, Dr. Ankush Goel, Dr.
Run Chen and Dr. Zahra Safarian. I am greatly indebted especially to John for
teaching me everything I know about my research and for being one of the kindest
and most helpful person I have ever met ! John, I am really grateful to you.
Special thanks to my group members and colleagues who had substantial in-

uence on my research at USC. My oce-mate Alireza Imani is one of the most
smartest and versatile people I have met. I must thank Hooman Abediasl for show-
ing me an impressive work ethic (coupled with intermittent tax-return advice). I
wish both of them all the success in their current and future endeavors. I must
mention Dr. Run Chen for being my academic elder brother and for being such a
good in
uence during my PhD. I greatly enjoyed having philosophical discussions
with Sushil Subramanian which provided many refreshing breaks from the some-
times tedious monotony of IC design. I would be grateful to Masashi for helping me
everytime I had any problems. Thanks also to Chenliang Du, Dr. Marcelo Segura,
Dr. Behnam Analui, Tie Yi, Dr. Hongrui Wang, Akshay Mahajan, Dr. Sungwon
Chung, Fatemeh Rezaeifar, Pingyue Song, Aria Samiei, Matt Clark, Timothy Mer-
cer, Sam Mandegaran for being the caring friends they have always been. Many
iv
Thanks to Kim Reid, Elizabeth Castaneda and Lauren Villarreal. Their dedication
signicantly assisted the progress of my projects.
Thanks to my internship managers Ying Shi (Skyworks) and Bryan Casper
(Intel Labs) for invaluable technical feedback and advice in developing my career.
I would like to thank all of my friends who enriched my life during the past years:
Sunav Chowdhury, Chitresh Bhusan, Praveen Kumar, Cheng-Ru Ho, Jaewon Nam,
Shiyu Su, Hao Feng and Aoyang Zhang.
My research projects are partially sponsored by DARPA under the ELASTx
program. Their nancial support is gratefully acknowledged.
I am deeply grateful to my parents, for their unconditional love and support.
My father and mother have been my rock in the often stormy sea of the doctoral
process.
Finally, and foremost, I would like to thank Rohit Datta, my elder brother, and
Jaba Mitra, my girlfriend for everything. Whenever I have faced insurmountable
odds, my Dada would be there to cheer me up with his extremely poor jokes about
running away to Japan and becoming a zen monk ! My dearest Jaba has been my
constant companion though happiness and sadness. I greatly appreciate her unend-
ing patience in tolerating my occasional bad moods while facing many challenges
in her own PhD. She is my best friend and soul mate. Without her full support
none of this would have been possible.
ii
Table of Contents
Dedication ii
Acknowledgements iii
List Of Tables vi
List Of Figures vii
Abstract xx
Chapter 1: Introduction 1
1.1 Mm-Wave Wireless Communication . . . . . . . . . . . . . . . . . . 1
1.2 Mm-Wave Wireless Link Budget . . . . . . . . . . . . . . . . . . . . 3
1.3 Mm-Wave Silicon Transmitter Challenges . . . . . . . . . . . . . . . 6
1.4 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2: Millimeter-Wave Silicon Power Ampliers 13
2.1 Power Amplier Metrics at Mm-Waves . . . . . . . . . . . . . . . . 15
2.1.1 Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2 DC Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.3 Input Power . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.4 Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.5 Collector (or Drain) Eciency . . . . . . . . . . . . . . . . . 17
2.1.6 Power Added Eciency . . . . . . . . . . . . . . . . . . . . 17
2.2 Millimeter-wave Silicon PA Design Challenges . . . . . . . . . . . . 18
2.2.1 Low Breakdown Voltage of Silicon Technology . . . . . . . . 18
2.2.2 On-Chip Passive Loss at Millimeter-Wave Frequencies . . . . 20
2.2.3 Lossy Impedance Transformation . . . . . . . . . . . . . . . 21
2.2.4 Large-Scale Lossy Power Combining . . . . . . . . . . . . . . 22
2.3 SiGe HBT Breakdown Mechanism . . . . . . . . . . . . . . . . . . . 22
2.3.1 Avalanche Breakdown in SiGe HBTs . . . . . . . . . . . . . 24
2.3.2 Breakdown Voltage Maximization in SiGe HBT Ampliers . 27
2.4 Linear Power Ampliers at Millimeter-Waves . . . . . . . . . . . . . 29
iii
2.4.1 Class-A Power Amplier . . . . . . . . . . . . . . . . . . . . 30
2.4.2 Linear Power Ampliers with Other Conduction Angles . . . 35
2.5 Switching Power Ampliers at Millimeter-Waves . . . . . . . . . . . 38
2.5.1 Mm-Wave Class-E Amplier Analysis . . . . . . . . . . . . . 41
2.5.2 Mm-Wave Class-E Performance Metrics . . . . . . . . . . . 46
2.5.3 Performance Limits of SiGe HBT Class-E PAs . . . . . . . . 53
2.5.4 Stability Considerations in Class-E HBT Ampliers . . . . . 59
2.5.5 Millimeter-Wave Class-E Implementations . . . . . . . . . . 60
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 3: Mm-Wave Stacked Switching Power Ampliers 69
3.1 Stacked Class-E Power Ampliers . . . . . . . . . . . . . . . . . . . 69
3.1.1 Operation of Stacked Transistors in Switching PAs . . . . . 70
3.1.2 Performance Limit of mm-Wave Stacked Class-E PAs . . . . 73
3.1.3 Q-band Stacked PA Implementations . . . . . . . . . . . . . 82
3.2 Transistor Stacking for W-band PAs . . . . . . . . . . . . . . . . . 91
3.2.1 Eect of Series Switches . . . . . . . . . . . . . . . . . . . . 93
3.2.2 Eect of Parasitic Layout Capacitors . . . . . . . . . . . . . 95
3.2.3 Eect of MIM Capacitor Q-factor . . . . . . . . . . . . . . . 97
3.2.4 Eect of Parasitic Collector Inductance . . . . . . . . . . . . 97
3.3 Multi-Port Stacked Transistor Topologies . . . . . . . . . . . . . . . 99
3.3.1 8 V Breakdown, 290 GHz f
max
Composite Transistor . . . . 99
3.3.2 11 V Breakdown, 260 GHz f
max
Composite Transistor . . . 103
3.3.3 W-Band Class-E PA Designs . . . . . . . . . . . . . . . . . . 104
3.3.4 W-band Stacked Switching PA Implementation . . . . . . . 107
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Chapter 4: Waveform Engineering in mm-Wave Switching Power Am-
pliers 116
4.1 Generalized Class-E Switching Power Ampliers . . . . . . . . . . . 120
4.1.1 Class-E Analysis with Non-Zero Boundary Conditions . . . . 121
4.1.2 Eciency Improvement in Generalized Class-E . . . . . . . . 129
4.2 Generalized Class-EF
x
y
Power Ampliers . . . . . . . . . . . . . . . 133
4.2.1 Mm-Wave Class-EF
y
x
PAs with K-Harmonics . . . . . . . . 135
4.2.2 Naming convention for Class-EF
y
x
PAs . . . . . . . . . . . . 138
4.2.3 Analysis of Class-EF
y
x
PAs . . . . . . . . . . . . . . . . . . . 140
4.2.4 Class-EF
y
x
PA Performance Metrics . . . . . . . . . . . . . . 147
4.2.5 Switching PA (EF
y
2
) with 2nd Harmonic Control . . . . . . 152
4.2.5.1 Class-E=F
2
PAs . . . . . . . . . . . . . . . . . . . 155
4.2.5.2 Class-EF
2
PAs . . . . . . . . . . . . . . . . . . . . 159
4.2.5.3 Class-EF
y
2
PAs with Arbitrary 2nd Harmonic Ter-
mination . . . . . . . . . . . . . . . . . . . . . . . 160
iv
4.2.5.4 Active Waveform Engineering by 2nd Harmonic In-
jection . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.3 Composite Waveforms in Stacked Switching Power Ampliers . . . 164
4.3.1 Stacked Class EF
y
x
Power Ampliers . . . . . . . . . . . . 165
4.3.1.1 30 GHz SiGe HBT Dierential Stacked Class-E=F
2;3
Power Amplier . . . . . . . . . . . . . . . . . . . 169
4.3.2 Stacked Class-K Composite Power Amplier . . . . . . . . . 173
4.3.3 Eciency Improvement in Stacked PAs . . . . . . . . . . . . 183
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Chapter 5: Watt-level Mm-Wave Digital Power Ampliers 187
5.1 Watt-level Power Amplication in Silicon . . . . . . . . . . . . . . . 188
5.1.1 Multi-Stage Class-E Amplier Chain . . . . . . . . . . . . . 189
5.1.2 Watt-Level mm-Wave Power Combining . . . . . . . . . . . 193
5.2 Data Transmission in Switching Ampliers . . . . . . . . . . . . . . 199
5.2.1 mm-Wave Class-E Power Modulator . . . . . . . . . . . . . 200
5.2.2 Q-band Class-E Modulator Implementations . . . . . . . . . 204
5.3 Mm-Wave Watt-Level Digital Power Amplier . . . . . . . . . . . . 208
5.3.1 Load-Pulling in Class-E . . . . . . . . . . . . . . . . . . . . 209
5.3.2 Variable Characteristic Impedance Transmission Line . . . . 211
5.3.3 Dynamic Load Modulation in mm-Wave Digital PA . . . . . 213
5.3.4 29 dBm mm-Wave Digital PA . . . . . . . . . . . . . . . . . 217
5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 6: Mm-Wave Digital Polar Transmitter Design 224
6.1 Digital Polar Transmitter for High-Speed Data Transmission . . . . 225
6.1.1 Mm-Wave Digital Polar Transmitter Architecture . . . . . . 225
6.1.2 Bandwidth Expansion in Digital Polar Transmitters . . . . . 227
6.1.3 Mm-Wave DPT Amplitude and Phase Resolution . . . . . . 230
6.2 Polar Transmitter System Level Performance . . . . . . . . . . . . . 233
6.2.1 60 GHz 8-Way Power Combiner . . . . . . . . . . . . . . . . 233
6.2.2 60 GHz Switching Ampliers . . . . . . . . . . . . . . . . . . 234
6.2.3 60 GHz Vector Modulator . . . . . . . . . . . . . . . . . . . 235
6.2.4 Digital Power Consumption . . . . . . . . . . . . . . . . . . 236
6.3 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . 239
Appendix A
SiGe BiCMOS Process Details . . . . . . . . . . . . . . . . . . . . . . . . 241
References 246
v
List Of Tables
2.1 Technology parameters of some modern SiGe BiCMOS process. . . 27
2.2 Output power vs peak PAE of some published mm-wave Silicon
power ampliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3 Measured Performance Summary of the Fabricated SiGe HBT Am-
pliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.1 Measured Performance Summary of the Fabricated stacked Q-band
SiGe HBT Ampliers. . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.2 Measured performance summary of the stacked W-band SiGe HBT
ampliers and comparison with some state-of-art published works. . 114
4.1 Performance Comparison with selected K-band Silicon Power Am-
pliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
4.2 Glossary of Generalized Switching Amplier Analysis . . . . . . . . 186
5.1 Performance comparison of our work with some reported state-of-art
mm-wave PAs and power DACs. . . . . . . . . . . . . . . . . . . . . 222
6.1 System Specication for 60 GHz Digital Polar Transmitter. . . . . . 239
vi
List Of Figures
1.1 Selected applications designated in the mm-wave frequency spectrum 2
1.2 Millimeter-wave wireless link at 60 GHz for large-scaled phased array
applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Cartesian (I/Q) transmitters : (a) homodyne, (b) heterodyne. . . . 8
1.4 Digital polar transmitter . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Performance of selected reported monolithic power ampliers imple-
mented in dierent semiconductor technologies versus frequency, (a)
P
out
, (b) PAE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Power amplier metrics. . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Breakdown voltage of some scaled silicon technologies. . . . . . . . 18
2.4 Simulated loss and quality factor of on-chip passives versus frequency
: (a) 50
micro-strip transmission line, (b) 70 fF MIM capacitor. . 19
2.5 (a) Impedance transformation for Watt-level output power in silicon
PAs, (b) Loss in output matching network. . . . . . . . . . . . . . . 20
2.6 (a) Power-combining for Watt-level output power in silicon PAs, (b)
Loss of corporate (binary tree) Wilkinson power combining at Q-
band versus number of power-combined unit ampliers. . . . . . . . 21
2.7 Avalanche breakdown in SiGe HBTs, (a) normal operation forV
CE
<
BV
CEO
, (b) impact ionization for V
CE
BV
CEO
, (c) electron-hole
pair generation under open base condition, (c) base current reversal
under shorted base condition. . . . . . . . . . . . . . . . . . . . . . 23
vii
2.8 (a) Breakdown voltage (V
Br
) versus collector current density (J
C
)
for the 130nm SiGe HBTs for dierent base resistance (r
B
) termina-
tions, (b) SiGe HBT eective breakdown voltage (V
Br
) under Class-A
amplier load-line : maximum collector voltage swing in SiGe HBT
Class-A ampliers can be higher thanBV
CEO
= 1.7 V depending on
DC bias point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.9 130 nm SiGe HBT Class-A amplier at 45 GHz : (a) schematic, (b)
design steps in a SiGe HBT process for mm-wave Class-A ampliers,
(c) collector voltage and current transient waveforms, (d) collector
voltage-current density contour showing the SiGe HBT stays within
the \Safe Area of Operation" while still swinging upto V
Br
= 4 V
(BV
CEO
= 1.7 V), (e) performance metrics. . . . . . . . . . . . . . . 34
2.10 Transient waveforms of linear power ampliers with arbitrary con-
duction angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.11 130 nm SiGe HBT Class-B amplier at 45 GHz : (a) schematic, (b)
design steps in a SiGe HBT process for mm-wave Class-B ampliers,
(c) collector voltage and current transient waveforms, (d) collector
voltage-current density contour showing the SiGe HBT stays within
the \Safe Area of Operation" while still swinging upto V
Br
= 5 V
(BV
CEO
= 1.7 V), (e) performance metrics. . . . . . . . . . . . . . . 38
2.12 Class-E amplier: (a) Generic schematic, (b) Simplied model dur-
ing ON cycle, (c) Simplied model during OFF cycle, (d) Ideal tran-
sient waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.13 (a) Collector voltage-current contour of Class-E switching power
amplier operating within SiGe HBT safe area of operation, (b)
Transient waveforms of a Class-E power amplier during its beyond
BV
CEO
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.14 Voltage scaling and transistor sizing in 130nm SiGe HBT Class-E
amplier design versus frequency. . . . . . . . . . . . . . . . . . . . 52
2.15 130 nm SiGe HBT Class-E amplier at 45 GHz : (a) schematic, (b)
design steps in a SiGe HBT process for mm-wave Class-E ampliers,
(c) collector voltage and current transient waveforms, (d) collector
voltage-current density contour showing the SiGe HBT stays within
the \Safe Area of Operation" while still swinging uptoV
Br
=BV
CBO
= 5.9 V, (e) performance metrics. . . . . . . . . . . . . . . . . . . . 52
viii
2.16 Maximum achievable output power, power gain, collector eciency,
and PAE versus frequency in a 130nm SiGe HBT Class-E amplier. 54
2.17 Maximum achievable output power, power gain, collector eciency,
and PAE versus maximum collector voltage (V
C;max
) for a 45 GHz,
130nm SiGe HBT, Class-E amplier. . . . . . . . . . . . . . . . . . 55
2.18 Maximum achievable output power, power gain, collector eciency,
and PAE versus the load resistance for a 45 GHz, 130nm SiGe HBT,
Class-E amplier (lossless passives). . . . . . . . . . . . . . . . . . . 56
2.19 Maximum achievable output power, power gain, collector eciency,
and PAE versus the load resistance for a 45 GHz, 130nm SiGe HBT,
Class-E amplier (Q
Passive
= 20). . . . . . . . . . . . . . . . . . . . 58
2.20 Lumped modeling of layout parasitics in a 2 16m SiGe HBT. . . 59
2.21 Class-E amplier instability mitigation, (a) Eect of half-harmonic
trap, (b) Eect of parallel resistance. . . . . . . . . . . . . . . . . . 60
2.22 One-stage Class-E amplier schematic and chip microphotograph. . 62
2.23 One-stage Class-E amplier performance: (a) Output power and
power gain versus input power at 41 GHz, (b) Collector eciency
versus output power at 41 GHz, (c) Measured performance across
the Q-band, (d) PAE versus output power at 41 GHz. . . . . . . . . 63
2.24 Two-stage Q-band Class-E amplier schematic and chip micropho-
tograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.25 Simulated transient waveforms of the 45 GHz SiGe HBT Class-E
amplier. Note that I
C
corresponds to the summation of transistor
and its collector capacitance currents. . . . . . . . . . . . . . . . . . 64
2.26 Design steps leading to a complete two-stage Q-band Class-E amplier. 64
2.27 Two-stage Class-E amplier performance: (a) Output power and
power gain versus input power at 45 GHz, (b) Collector eciency
versus output power at 45 GHz, (c) Measured performance across
the Q-band, (d) PAE versus output power at 45 GHz. . . . . . . . . 66
ix
2.28 Die photo of the two-way Wilkinson power-combined Q-band Class-
E amplier with S-parameters of back-to-back Q-band Wilkinson
power combiners. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.29 Two-way Wilkinson power combined Class-E amplier performance:
(a) Output power and power gain versus input power at 45 GHz, (b)
Collector eciency versus output power at 45 GHz, (c) Measured
performance across the Q-band, (d) PAE versus output power at 45
GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.1 Double-stacked Class-E SiGe HBT amplier, (a) Simplied schematic,
(b) Equivalent model when HBTs are ON, (c) Equivalent model when
HBTs are OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.2 (a) Equivalent circuit model for the OFF-mode operation, (b) Collec-
tor voltage waveforms of a double-stacked Class-E SiGe HBT amplier. 72
3.3 Maximum achievable output power, power gain, collector eciency,
and PAE versus frequency in a 130nm SiGe HBT double-stacked
Class-E amplier with ideal lossless passives. . . . . . . . . . . . . . 76
3.4 Maximum achievable output power, power gain, collector eciency,
and PAE versus the load resistance for a 45 GHz, 130nm SiGe HBT,
double-stacked, Class-E amplier (lossless passives). . . . . . . . . . 78
3.5 Theoretical maximum achievable PAE versus output power for a 45
GHz, 130nm SiGe HBT Class-E and double-stacked, Class-E am-
plier (with Q
Passive
= 20), with dotted line showing output power
level beyond which stacked architecture results in higher PAE. . . . 78
3.6 Triple-stacked Class-E SiGe HBT amplier, (a) Simplied schematic,
(b) Equivalent model with HBTs are ON, (c) Equivalent model with
HBTs are OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.7 (a) Equivalent circuit model for the OFF-mode operation, (b) Collec-
tor voltage waveforms of a triple-stacked Class-E SiGe HBT amplier. 81
3.8 Lumped modeling of layout parasitics in a 2 (16m-12m) stacked
SiGe HBT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.9 Double-stacked Q-band Class-E amplier: (a) schematic, (b) chip
microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
x
3.10 Simulated transient waveforms of the 45 GHz double-stacked SiGe
HBT Class-E amplier. Note that the currents correspond to the
summation of transistor and its collector capacitance currents. . . . 84
3.11 Design steps for the double-stacked Q-band Class-E amplier, (a)
HBTs are modeled with a switch, (b) collector-bulk capacitance of
HBTs are included,C
CB1
is absorbed inC
11
, (c) switches are replace
with SiGe HBTs, (d) SiGe HBT layout parasitics are included, (e)
the nite quality of passives (Q
ind
= 25,Q
cap
= 20) are included, (f)
including loss in the input matching network. . . . . . . . . . . . . 85
3.12 Large-signal performance of the implemented Q-band double-stacked
Class-E amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.13 Triple-stacked Q-band Class-E amplier schematic and chip micropho-
tograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.14 Simulated transient waveforms of the 45 GHz triple-stacked SiGe
HBT Class-E amplier. Note that the currents correspond to the
summation of transistor and its collector capacitance currents. . . . 86
3.15 Design steps of the triple-stacked Q-band Class-E amplier, (a) with
real HBTs and ideal passives , (b) SiGe HBT layout parasitics are
included, (c) the nite quality of passives (Q
ind
= 25, Q
cap
= 20)
are included, (d) including loss in the input matching network, (e)
performance including driver amplier. . . . . . . . . . . . . . . . . 87
3.16 Large-signal performance of the implemented Q-band triple-stacked
Class-E amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.17 Redesigned triple-stacked Class-E amplier: (a) Schematic, (b) Sim-
ulated performance at 45 GHz. . . . . . . . . . . . . . . . . . . . . 90
3.18 Phased-array W-band transceiver architecture. . . . . . . . . . . . . 92
3.19 Transistor stacking at W-band, (a) 2-stacked Class-E schematic, (b)
Class-E simulated voltage-current density contour at 90 GHz. . . . 92
3.20 (a) Simplied model of a double-stacked Class-E amplier, (b) The-
oretical eect ofr
ON
on collector eciency () in a 90nm SiGe HBT
technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
xi
3.21 (a) Simplied model of a double-stacked Class-E amplier with par-
asitic layout capacitor C
P
, (b) Theoretical eect of C
P
on collector
eciency (). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.22 (a) Simplied model of a double-stacked Class-E amplier with out-
put network capacitor C
OUT
, (b) Theoretical eect of C
OUT
quality
factor on collector eciency (). . . . . . . . . . . . . . . . . . . . . 96
3.23 (a) Simplied model of double-stacked Class-E amplier with para-
sitic collector inductanceL
P
, (b) Theoretical eect ofL
P
on stacked
PA output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.24 (a) Parasitics associated with discrete transistor stacking at mm-
wave frequencies, (b) Conceptual integrated multi-port high-breakdown,
high-f
max
transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.25 Composite 2-stacked multi-port SiGe HBT Layout, (a) collector con-
nections of series HBTs Q
1
-Q
2
, (b) Q
2
collector shielding and C
OUT
synthesis, (c) Q
1
collector shielding and C
B2
synthesis along with
equivalent 8 V transistor symbol. . . . . . . . . . . . . . . . . . . . 102
3.26 Composite 3-stacked multi-port SiGe HBT Layout, (a) collector con-
nections of series HBTsQ
1
-Q
3
, (b)Q
2
andQ
3
collector shielding and
C
OUT1
and C
OUT1
synthesis, (c) Q
1
and Q
2
collector shielding and
C
B2
and C
B3
synthesis along with equivalent 8 V transistor symbol. 105
3.27 Switching PA design examples at 90 GHz, (a) 2-stacked Class-E
PA along with transient collector voltage-current waveforms, (b) 3-
stacked Class-E PA along with transient collector voltage-current
waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.28 f
max
vs. current densityJ
C
for non-stacked native SiGe HBTs, com-
posite 2-stacked and 3-stacked HBTs . . . . . . . . . . . . . . . . . 107
3.29 Schematic and chip microphotograph of the 5-stage W-band non-
stacked Class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.30 Large-signal measurements of 5-stage W-band non-stacked Class-E
PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.31 Schematic and chip microphotograph of the 5-stage W-band 2-stacked
Class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
xii
3.32 Large-signal measurements of 5-stage W-band 2-stacked Class-E PA. 111
3.33 Schematic and chip microphotograph of the 6-stage W-band 3-stacked
Class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.34 Large-signal measurements of 6-stage W-band 3-stacked Class-E PA. 113
3.35 Output power vs peak PAE of the stacked mm-wave switching PAs
with some published mm-wave silicon power ampliers. . . . . . . . 115
4.1 Design space of switching ampliers under waveform engineering by
controlling the switching amplier collector impedanceZ
C
at higher
harmonics of the fundamental frequency of operation with active or
passive terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.2 Class-E amplier with non-zero switching boundary conditions, (a)
Simplied schematic, (b) equivalent model with HBTs are ON, (c)
equivalent model with HBTs are OFF, (d) transient waveforms with
non-zero `ZVS' and `ZdVS' boundary conditions. . . . . . . . . . . . 122
4.3 Class-E amplier design parameters with non-zero boundary switch-
ing conditions (A
1
;A
2
) at 30 GHz, (a) shuntC
OFF
value, (b) switch
r
ON
value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4 Class-E amplier performance metrics with non-zero boundary switch-
ing conditions (A
1
;A
2
), (a) P
out
, (b) G
P
, (c) , (d) PAE. . . . . . . 128
4.5 Class-E amplier loss constants with non-zero boundary switching
conditions (A
1
;A
2
) at 30 GHz, (a)
SwitchLoss
, (b)
CapacitiveLoss
. . . 131
4.6 Class-E amplier performance metrics with non-zero boundary switch-
ing conditions (A
1
;A
2
) at 1 GHz, (a) P
out
, (b) PAE. . . . . . . . . 133
4.7 Transient waveforms and performance table of a 30 GHz Class-E PA
designed with non-zero boundary conditions. . . . . . . . . . . . . . 134
4.8 (a) Circuit schematic of Class-EF
y
x
amplier with K harmonic load
control, (b) ON-state equivalent circuit, (b) OFF-state equivalent
circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.9 (a) Circuit schematic of Class-EF
y
2
amplier, (b) smith chart show-
ing variation of second harmonic load termination. . . . . . . . . . . 152
xiii
4.10 (a) Transient waveforms for 30 GHz Class-E=F
2
amplier, (b) perfor-
mance table, (c) open-circuit collector node impedance under second
harmonic load control. . . . . . . . . . . . . . . . . . . . . . . . . . 156
4.11 (a) Transient waveforms for 30 GHz Class-EF
2
amplier, (b) perfor-
mance table, (c) short-circuit collector node impedance under second
harmonic load control. . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.12 Simulated collector voltage and switch current waveforms under dif-
ferent second harmonic impedance Z
C
(2f
0
) in a 30 GHz Class-EF
y
2
amplier realized in a 130nm SiGe HBT process along with the cor-
responding P
out
and . Ideal passives are assumed in all cases . . . 162
4.13 Example of an active second harmonic injection in a Class-EF
y
2
switching amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.14 Two-Stacked Class-EF
y
x
switching amplier with a capacitive di-
vider K-harmonic control for the top transistor, (a) Circuit schematic,
(b) equivalent circuit during ON state, (c) equivalent circuit during
OFF state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.15 30 GHz dierential stacked Class-EF
2;3
amplier, (a) circuit schematic,
(b) simulated transient collector voltage and current waveforms, (c)
simulated performance assuming ideal passives. . . . . . . . . . . . 170
4.16 Design steps of the 30 GHz dierential stacked Class-EF
2;3
amplier
showing performance degradation due to (a) HBT layout parasitics,
(b) inductor loss (Q
ind
= 15), (c) loss of output impedance match-
ing networks (Q
ind
= 15, Q
cap
= 35), (d) loss of input impedance
matching network. . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.17 Schematic and die microphotograph of the two-stage two-stacked
dierential Class-E=F
2;3
amplier. . . . . . . . . . . . . . . . . . . . 172
4.18 Performance of the two-stage two-stacked dierential Class-E=F
2;3
amplier, (a) output power and power gain versus input power at
34 GHz, (b) saturated output power and corresponding PAE versus
frequency, (c) collector eciency versus output power, (d) power
added eciency versus output power. . . . . . . . . . . . . . . . . . 173
xiv
4.19 A 2-stacked Class-K switching ampliers with K-harmonic controls
for both HBTs, (a) Circuit schematic, (b) equivalent circuit during
the ON state, (c) equivalent circuit during the OFF state. . . . . . 174
4.20 30 GHz dierential 2-stacked Class-K amplier, (a) circuit schematic,
(b) simulated transient collector voltage and current waveforms, (c)
simulated performance assuming ideal passives. . . . . . . . . . . . 179
4.21 Performance degradation of various design stages of a 30 GHz, 2-
stacked dierential, Class-K amplier : Complete HBT model (lay-
out parasitics) and ideal passives, (b) nite quality factor for collector
inductanceL
1
(Q
ind
= 15), (c) Finite quality factor for the harmonic
load network components (Q
ind
= 15, Q
cap
= 35), (d) Adding input
driver stage and impedance matching network. . . . . . . . . . . . . 181
4.22 Schematic and die microphotograph of the two-stage two-stacked
dierential Class-K amplier. . . . . . . . . . . . . . . . . . . . . . 181
4.23 Performance of the two-stage two-stacked, dierential, Class-K am-
plier, (a) output power and power gain versus input power at 34
GHz, (b) saturated output power and corresponding PAE versus fre-
quency, (c) collector eciency versus output power, (d) power added
eciency versus output power. . . . . . . . . . . . . . . . . . . . . . 182
4.24 30 GHz 2-stacked Class-K amplier, (a) circuit schematic, (b) simu-
lated transient collector voltage and current waveforms, (c) simulated
performance assuming ideal passives. . . . . . . . . . . . . . . . . . 184
4.25 30 GHz 3-stacked Class-K amplier, (a) circuit schematic, (b) simu-
lated transient collector voltage and current waveforms, (c) simulated
performance assuming ideal passives. . . . . . . . . . . . . . . . . . 184
4.26 30 GHz 4-stacked Class-K amplier, (a) circuit schematic, (b) simu-
lated transient collector voltage and current waveforms, (c) simulated
performance assuming ideal passives. . . . . . . . . . . . . . . . . . 185
5.1 A N-stage mm-wave Class-E amplier chain with either a non-stacked
Class-E or a stacked Class-E as the output stage. . . . . . . . . . . 188
xv
5.2 Simulated performance comparison of 3-stage power amplier chains
where the last stage is either Class-E or double-stacked Class-E am-
plier, (a) Maximum achievable output power (P
out
) and power gain
(G
P
) at 45 GHz versus load resistance of the output stage (R
L;3
),
(b) Maximum achievable PAE vs P
out
. . . . . . . . . . . . . . . . . 193
5.3 (a) An M-stage power combining of M mm-wave Class-E PA chains
using 2-way 50
Wilkinson combiners (b) power combining of M
mm-wave Class-E PA Chains using an M-way 50
Wilkinson com-
biner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5.4 (a) A 70
micro-strip transmission implemented in the 0.13m SiGe
BiCMOS process, (b) simulated insertion loss of the 70
micro-strip
transmission line versus frequency. . . . . . . . . . . . . . . . . . . . 195
5.5 (a) Simulated insertion loss of quarter wavelength micro-strip trans-
mission line at 45 GHz versus transmission line characteristic impedance
(Z
C
) (b) simulated power combiner loss for dierent combining ratios
using M-stage or M-way or a hybrid combiner architecture, (c) over-
all P
out
and PAE for the power combined 1-Watt mm-wave Class-E
power amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.6 Simplied schematic of a mm-wave digital polar transmitter (DPT). 198
5.7 Representative simulated large signal transfer curves of mm-wave
stacked Class-E ampliers, (a) P
out
vs. P
in
, (b) I
DC
vs. P
in
. . . . . 200
5.8 1-bit mm-wave Class-E power modulator architecture : (a) simplied
schematic, (b) detailed schematic. . . . . . . . . . . . . . . . . . . . 201
5.9 1-bit Class-E modulator equivalent circuit, (a) ON-state, (b) OFF-
state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.10 Simulated large signal transient waveforms of the Class-E modulator,
(a) Input control-bit and output voltage vs. time, (b) I
DCSupply
vs.
time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.11 Schematic and chip microphotograph of 1-bit mm-wave Class-E power
modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.12 (a) Input switch network schematic, (b) isolation and insertion loss
trade-o vs. frequency and M
INSW1
switch size. . . . . . . . . . . 205
xvi
5.13 (a) Output switch network schematic, (b) isolation and insertion loss
trade-o vs. frequency and M
OUTSW1;2
switch size. . . . . . . . . . 206
5.14 1-bit Class-E modulator large signal measurements under ASK mod-
ulation at 46 GHz, (a) measured transient waveform, (b) recovered
eye-diagram at 500 Mb/s and 1.25 Gb/s, (c) average P
out
andPAE
versus modulation speed. . . . . . . . . . . . . . . . . . . . . . . . . 207
5.15 Power control by 8-way /4 load modulation, (a) peak power oper-
ation, (b) power back-o operation when m out of 8 unit PAs are
active, (c) variation of Z
PA
with power back-o. . . . . . . . . . . . 209
5.16 Simulated performance of mm-wave stacked Class-E amplier under
load pulling, (a) variation of P
out
with Z
OPT:
,(b) variation of PAE
with Z
OPT:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.17 A variable characteristic impedance (Z
C
) micro-strip transmission
line, (a) proposed architecture, (b) equivalent model in the \High
Z
C
" and \Low Z
C
" modes of operation. . . . . . . . . . . . . . . . 211
5.18 Variable impedance transmission line, (a) chip microphotograph, (b)
measuredZ
C
versus frequency, (b) measured attenuation constant
and propagation constant versus frequency. . . . . . . . . . . . . 212
5.19 (a) A two-way /4 combiner using variable Z
C
transmission lines,
(b) simulated power combining eciency under dierent operating
modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.20 Power control by dynamic load modulation, (a) peak power operation
when all unit ampliers are turned ON, (b) back-o power operation
when `m' out of 8 unit PAs are active, (c) variation of Z
PA
with
power back-o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
5.21 Schematic of the mm-Wave Watt-level 8-way combined digital power
amplier with dynamic load modulation network. . . . . . . . . . . 216
5.22 Operation of the dynamic load modulation network, (a) peak power
operation, power control by (b) 1 PA OFF, (c) 2 PAs OFF, (d) 3
PAs OFF, (e) 4 PAs OFF, (f) power back-o eciency comparison
between dierent schemes. . . . . . . . . . . . . . . . . . . . . . . . 218
xvii
5.23 Die microphotograph of the Watt-level 8-way combined digital power
amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.24 Small signal s-parameter measurements of the digital PA under Class-
A bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.25 Large signal measurements of the Watt-level digital PA at 46 GHz,
(a) P
out
, G
P
versus P
in
, (b) Eciency versus P
out
, (c) PAE versus.
P
out
, (d) performance across frequency. . . . . . . . . . . . . . . . . 220
5.26 Power control operation of the digital PA, (a) system eciency ver-
sus power back-o, (b) output voltage amplitude versus amplitude
control code, (c) DNL/INL versus amplitude control code. . . . . . 221
5.27 PAE at P
sat
for reported silicon mm-wave power ampliers. . . . . 223
6.1 A digital polar transmitter block diagram . . . . . . . . . . . . . . . 225
6.2 Bandwidth expansion of amplitude and phase signals in a polar
transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.3 Signal spectrums in a digital polar transmitter. . . . . . . . . . . . 228
6.4 Up-sampling of the base-band I/Q signal before amplitude and phase
splitting for, (a)N
1
= 1 (Nyquist), (b)N
1
= 2, (c)N
1
= 4, (c)N
1
= 8230
6.5 (a) EVM vs amplitude resolution N
A
and phase resolution N

in a
digital polar transmitter, (b) EVM requirement vs. BER for dierent
QAM constellations. . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.6 Reconstructed 256-QAM constellation from a digital polar transmit-
ter with 8-bit amplitude resolution and 6-bit phase resolution. . . . 232
6.7 Schematic for a high-speed Watt-level digital polar transmitter. . . 233
6.8 Schematic for (a) high-speed vector modulator, (b) variable charac-
teristic impedance and phase shift transmission line for load modu-
lation and phase compensation. . . . . . . . . . . . . . . . . . . . . 236
xviii
6.9 (a) Technology parameters for the 130nm CMOS FETs in the 130nm
SiGe BiCMOS process, (b) nal-stage of the digital driver chain used
to drive the amplitude control switches in the mm-wave DPT, (c)
total power consumption (P
Digital
) and number of stage requirement
(N) for the digital drivers. . . . . . . . . . . . . . . . . . . . . . . . 237
A.1 Metal stack of the 130nm SiGe BiCMOS process. . . . . . . . . . . 242
A.2 Metal stack of the 90nm SiGe BiCMOS process. . . . . . . . . . . . 242
A.3 (a) I
C
versus V
BE
, (b)I
C
versus V
CE
for a 616 m SiGe HBT in
the 130nm BiCMOS process. . . . . . . . . . . . . . . . . . . . . . . 243
A.4 (a) Cross-section of a 50
micro-strip transmission line in the 130nm
SiGe BiCMOS process, (b) measured characteristic impedance Z
C
,
(c) Measured attenuation constant and wave-factor . . . . . . . 244
A.5 (a) Isometric view of a 325 fF metal-insulator-metal (MIM) capacitor
in the 130nm SiGe BiCMOS process along with the equivalent circuit
schematic and values of circuit components for some capacitor values,
(b) measured and EM simulated (using IE3D simulator) s-parameter
(magnitude and phase) of the 325 fF MIM capacitor. . . . . . . . . 245
xix
Abstract
In recent years, millimeter wave wireless communication with carrier frequency
above 30 GHz has become an important area of research as the large available
bandwidth at the millimeter wave frequency spectrum enables supporting high
data-rates. Supporting reasonable wireless link distances requires the transmit-
ter front-end to generate large output power at millimeter wave frequencies. This
thesis presents innovative integrated circuit solutions, for implementation of Watt-
level, power-ecient millimeter-wave, silicon power ampliers and transmitters with
following contributions : (1) series stacking of transistors in switching power am-
plier architectures for generating high power with high eciency, (2) engineering
voltage-current waveforms for eciency enhancement in switching power ampliers
by harmonic manipulation at millimeter wave frequencies, and (3) recongurable
power combining networks with dynamic load modulation for improving eciency
at backed-o power levels in digital power ampliers.
The necessity for high-speed, energy ecient signal processing in high data-rate
wireless communications, makes the silicon technology very attractive for high-
speed millimeter wave wireless transceivers. However, the low breakdown voltage
xx
of modern scaled silicon CMOS and silicon germanium (SiGe) HBT processes and
lossy on-chip passive components present challenges for generation of Watt-level
power with high eciency at millimeter-wave frequencies. This thesis presents sev-
eral prototypes of Class-E switching power ampliers, where the transient voltage-
current waveform properties has been exploited in conjunction with SiGe hetero-
junction bipolar transistor breakdown physics, to generate high output power with
high eciency at millimeter waves. This thesis further presents stacked switching
power amplier architectures, where constructive addition of voltage swing across
multiple series stacked transistors enables generation of higher output power with
negligible power generation eciency degradation. Device and layout parasitics, of-
ten treated as unwanted secondary eects, are judiciously included in the mm-wave
designs. Several amplier prototypes at Q-band (around 45 GHz) and W-band
(around 85 GHz) validate the eectiveness of the proposed schemes at mm-wave
frequencies. Another contribution of this thesis is nding the performance limits of
switching ampliers as a function of transistor technology. While the experimental
demonstrations are limited to SiGe HBT processes, the proposed approaches are
general and applicable to other silicon and compound semiconductor technologies.
The role of harmonics in synthesizing the desired voltage and current waveforms
in switching power ampliers was investigated to probe the existence of the `best'
or `optimum' class of ampliers at millimeter wave frequencies. This waveform
xxi
engineering with harmonic manipulation result in better power generation and e-
ciency than conventional classes of ampliers. Waveform engineering by harmonic
manipulation is also extended to stacked switching power ampliers. Amplier
prototypes at 30 GHz demonstrate the value of such concepts at millimeter wave
frequencies.
Finally, a Watt-level millimeter-wave digital power amplier with multiple out-
put amplitude levels has been proposed utilizing the switching power amplier mod-
ules. An ON-OFF-Keying (OOK) mm-wave power modulator based on a Class-E
power ampliers is demonstrated. Several of these OOK mm-wave power modu-
lators can be power combined to realize a multi-level digital power amplier with
several levels of output amplitude and power control. Conventional passive power
combining schemes in such a architecture, however, result in load impedance vari-
ation and consequently eciency degradaton for dierent amplitude levels. To
mitigate the load pulling problem, a programmable power combining scheme com-
prising of transmission lines with variable characteristic impedance is proposed that
can dynamically correct any load variation in the transmitter. The implemented
prototype demonstrates Watt-level output power at millimeter wave frequencies
along with high eciency under power back-o operation. The thesis concludes
with a design example where the proposed mm-wave switching amplier is utilized
to highlight dierent system level concepts of a high-speed mm-wave Watt-level
digital polar transmitter.
xxii
Chapter 1
Introduction
1.1 Mm-Wave Wireless Communication
Over the last decade, the increasing demand for high denition audio and video
content over mobile devices has motivated research in wireless communication sys-
tems supporting higher data-rates. The present generation of commercial radio-
frequency transceivers used in cell phones, WiFi, etc. operate at carrier frequencies
around 900 MHz - 3 GHz with narrow channel bandwidths of 0.2 - 160 MHz, and
rely on complex modulation schemes like 1024 QAM to support data-rates upto 1
Gb/s. However, using such complex constellation schemes result in performance
trade-os and additional system complexity in the transceiver leading to higher cost
and lower battery life for devices supporting such data-rates. Moreover, existing
communication schemes are incapable of meeting even higher data-rates of 10-100
Gb/s envisioned for the next generation of 5G communication protocols.
1
Figure 1.1: Selected applications designated in the mm-wave frequency spectrum
In recent years, the millimeter-wave (mm-wave) frequency spectrum (30 GHz -
300 GHz) has become an important area of research to support wireless communica-
tion with high data-rates and high energy eciency [1] [2] [3]. The major advantage
of millimeter-wave wireless communication is the availability of large bandwidth (
5 GHz) around various millimeter wave communication bands such as 60 GHz, 77
GHz and 81 GHz as shown in Fig. 1.1. From the Shannon-Hartley theorem [4], the
channel capacity which is the maximum rate of eror-free information
ow through
a given communication channel can be expressed as,
ChannelCapacity =Bandwidthlog
2
(1 +SNR) (1.1)
where SNR stands for signal to noise ratio in that communication channel. The
over ten-fold increase in available channel bandwidths at millimeter-wave frequen-
cies compared to radio frequencies allows high-speed communication with much
lower SNR using simpler constellation schemes in more energy ecient transceiver
2
Figure 1.2: Millimeter-wave wireless link at 60 GHz for large-scaled phased array
applications.
architectures. On the other hand, if the same SNR can be maintained, then
millimeter-wave communication can support much higher data-rates. A recon-
gurable millimeter-wave radio can trade data-rates o with energy consumption
depending on the user needs. Millimeter-wave communication systems are also ap-
plicable in high resolution imaging [5], automotive radars [6], and military radars [7].
1.2 Mm-Wave Wireless Link Budget
Fig. 1.2 shows a mm-wave phased array transmitter (TX) - receiver (RX) archi-
tecture for supporting 50 Gb/s data-rate over a 1 Km wireless link using the 60
GHz 802.11 ad communication standard. The free-space radiation loss (FSRL) is
the main source of signal attenuation at 60 GHz, given by
FSRL = (
4d

)
2
: (1.2)
3
where d = 1 Km is the line-of-sight distance between the transmitter and receiver
and = 5 mm is the free-space wavelength at 60 GHz. The free space radiation
loss is in this case is 128 dB. The atmospheric absorption at the 60 GHz frequency
band leads to an additional signal attenuation of 12 dB/Km. To overcome this huge
atmospheric attenuation, most modern mm-wave communication systems require a
phased array transceiver front-end. An 128 element TX and RX transceiver system
is shown in Fig. 1.2 which helps to improves the directivity of the beam resulting
in equivalent isotropic radiated power (EIRP) gain given by,
EIRP Gain (dB) = 20log
10
(N); (1.3)
where N is the number of TX elements. For N = 128, this leads to 42 dB of EIRP
gain. For large scale phased array systems to be fully integrated, on-chip planar
antennas are used as radiating elements for both the transmitter and receiver front-
ends. The TX and RX antenna gain of such on-chip planar antennas are assumed to
be 3 dB, and hence the total TX path loss before the signal reaches the receiver
front-end is given by,
TX Loss =FSRL +AtmosphericLossEIRP Gain (G
TX
+G
RX
); (1.4)
where G
TX
, G
RX
are the TX and RX antenna gain respectively. For the 60 GHz
link under consideration, the TX path loss 92 dB.
4
On the receiver side, the sensitivity requirement of the receiver is set by min-
imum acceptable bit-error-rate (BER) for a given modulation scheme. In order
to realize a 50 Gb/s data rate using the 8 GHz of channel bandwidth available
centered around 60 GHz, requires using a modulation scheme that can transmit 8
bits/symbol. For a given BER, the choice of the modulation scheme, determines
the maximum error-vector magnitude (EVM) that the Rx can tolerate, which in
turn determines the required signal-to-noise (SNR) requirement at the receiver.
The EVM requirement for an acceptable BER = 10
6
in a wireless channel using
a 256-QAM constellation to support spectral density of 8 bits/symbol can be de-
termined to be 2% which translates to SNR requirement of 35 dB at the receiver
(Fig. 6.5(b)). This SNR = 35 dB at the receiver must be achieved in presence of
AWGN channel noise over a 8 GHz channel bandwidth, a receiver intrinsic noise
gure (NF
RX
) = 10 dB and the noise contribution from the high power transmitter
side denoted by NF
TX
= 10 dB. The phased array system improves the noise g-
ure contribution on both the receiver and transmitter side by 10log
10
(N) 21 dB
where N = 128 is the number of TX and RX elements. The overall RX sensitivity
can then be determined from,
SNR (dB) =Sensitivity
RX
(dBm) [10log
10
(kTBW )
+ (NF
RX
10log
10
(N)) + (NF
TX
10log
10
(N))]; (1.5)
5
where kT is denotes the AWGN channel noise per unit Hertz and BW = channel
bandwidth. The receiver sensitivity can be determined to be -62 dB, and hence
the unit output power requirement from each element of the 128-element phased
array transceiver is determined to be,
P
out;TX
=Sensitivity
RX
+TX Loss 30dBm: (1.6)
From the preceding link-budget analysis, a long distance energy ecient wireless
link at 60 GHz requires an ecient Watt-level transmitter for each phased array
element, supporting high-speed data transmission using a 256-QAM constellation.
1.3 Mm-Wave Silicon Transmitter Challenges
In recent years, implementation of mm-wave Watt-level transceivers in silicon tech-
nologies has gained traction to benet from integrated digital signal processing
and digital calibration on the same chip. However, realization of ecient, \Watt-
level" mm-wave power ampliers in scaled silicon technologies with low transistor
breakdown voltages present signicant challenges.
Most existing millimeter-wave transmitters are implemented using an I/Q trans-
mitter architecture shown in Fig. 1.3 to support both amplitude and phase modu-
lations [8{17]. In such a transmitter, the in-phase and quadrature-phase baseband
6
information, shown asA
I
(t) andA
Q
(t), are up-converted by quadrature mixers be-
fore being summed up to realize the amplitude and phase modulated signal. The
modulated signal is then transmitted after being amplied by a millimeter-wave
linear amplier. Ecient, high-power linear amplier design is a major challenge
at millimeter waves. The ratio of transistor knee voltage to breakdown voltage
is much higher in scaled silicon technologies resulting in linear amplier collector
eciency of approx 5-10 % at mm-waves (much lower than the 50% theoretical
Class-A eciency). Large-scale power-combining of small output power individual
power ampliers using lossy on-chip passives degrades the overall eciency even
further. Finally, the eciency in linear ampliers reduces signicantly with power
back-o. Thus I/Q transmitters with linear ampliers supporting complex constel-
lations with high peak to average power ratios (PAPR) suer from very low average
eciency under modulation. Digital polar transmitter architecture (Fig. (1.4))
is an alternative with recent mm-wave demonstrations [18{21]. In a digital polar
transmitter, the base-band I/Q data is converted into amplitude and phase bits us-
ing a digital cartesian-to-polar conversion process. The phase information is then
superimposed on a carrier using a phase modulator. This constant-envelope phase
modulated signal is then amplied by an array of ecient switching power ampli-
ers whose output signals are combined. The amplitude bits are used to control
the output amplitude of the switching ampliers to create the desired amplitude
7
Figure 1.3: Cartesian (I/Q) transmitters : (a) homodyne, (b) heterodyne.
Figure 1.4: Digital polar transmitter
8
modulation. In such digital transmitter architecture, the unit switching power am-
pliers may be designed to mimic a two-state binary block either amplifying the
constant-envelope phase modulated signal (ON state) or not passing the signal
through (OFF state). Such millimeter-wave switching ampliers can be designed
with much higher eciency than millimeter-wave linear ampliers resulting in a
higher transmitter eciency. However, the nonlinear cartesian-to-polar conversion
leads to bandwidth expansion of the baseband information, and necessitates wide
band design of switching power ampliers as well as phase and amplitude mod-
ulators. Eciency degradation with power back-o is still a challenge in digital
transmitters and can be mitigated by dynamic load modulation as discussed in
later chapters.
In summary, in both the I/Q and digital polar transmitter, the front-end Watt-
level power amplier is the most power consuming block. The objective of this
thesis (as highlighted in Fig. 1.4) is to propose transistor level, circuit level and ar-
chitectural level integrated solutions to achieve Watt-level millimeter-wave switch-
ing power ampliers with high eciency at peak output power and under power
back-o levels.
1.4 Dissertation Outline
This work mainly focuses on methods to achieve ecient power amplication with
high output power in millimeter-wave power ampliers. Firstly, the voltage-current
9
contours of switching power ampliers and the collector-current-dependent break-
down voltage range of silicon germanium (SiGe) heterojunction bipolar transistors
(HBT) have been exploited to design highly ecient, high-power switching am-
pliers at millimeter-wave frequencies. Secondly, series stacking of transistors is
proposed in a millimeter-wave switching amplier to improve output power gener-
ation. Thirdly, waveform shaping by higher harmonic termination is investigated
in switching power ampliers to improve millimeter-wave power amplier perfor-
mance. Finally, to prevent ecient degradation at backed-o power levels, an
integrated dynamic load modulation technique is proposed.
The dissertation is organized as follows. In Chapter 2, a millimeter-wave Class-
E power amplier is introduced in which the non-overlapping switching amplier
voltage and current waveforms are exploited to extend the collector voltage swing
beyond what can be achieved in linear ampliers. This results in increasing the
output power of Class-E switching ampliers while maintaining high eciency.
Performance limits of such Class-E ampliers versus frequency in dierent sili-
con technologies are also derived. Finally, proof-of-concept implementations of
millimeter-wave switching Class-E ampliers in a 130nm SiGe BiCMOS process
are presented.
Series stacking of transistors in a millimeter-wave switching amplier congu-
ration is proposed in Chapter 3. The proposed circuit architecture allows higher
overall higher voltage swing in the stacked collector node resulting in higher output
10
power for the same load impedance while allowing all transistors to operate within
safe voltage limits. The improvement in output power and power-added-eciency
in the stacked Class-E architecture is validated by 2-stacked and 3-stacked pro-
totypes implemented in the 130nm SiGe HBT process for Q-band (30- 50 GHz)
applications. Series stacking of transistors may lead to signicant layout parasitics
which can aect stacked Class-E performance at higher millimeter-wave frequencies.
A multi-port stacked transistor layout is presented in this chapter that eliminates
the layout parasitics by shielding the sensitive circuit nodes while realizing all the
network capacitors by layout interconnects. W-band switching amplier prototypes
using the composite multi-port stacked transistors have been implemented in a 90
nm SiGe BiCMOS process.
Engineering the voltage and current waveforms by controlling the harmonics
can be benecial in improving the switching amplier performance. In Chapter 4,
theoretical performance limits of generalized class of switching ampliers, where
harmonic terminations control the voltage and current waveforms, are presented.
This approach is extended to stacked switching ampliers where harmonic termi-
nations of various nodes shape the collector voltage and current of each stacked
transistor independently. A resulting new class of ampliers, referred as Class-K,
is introduced and analyzed. Proof of concept amplier prototypes at 30 GHz were
implemented in a 130 nm SiGe BiCMOS process to validate the eectiveness of the
proposed concepts.
11
In Chapter 5, a Watt-level digital power amplier has been demonstrated for
operation at millimeter-wave frequencies. First, the millimeter-wave Class-E power
amplier has been used to realize a high-speed 1-bit amplitude modulator. Several
of these `power modulators' are then power combined to realize a millimeter-wave
digital power amplier with 29 dBm peak output power and capable of achieving
several levels of output amplitude. The mitigate load modulation at backed-o
amplitude levels, a tunable transmission line power combiner with variable charac-
teristic impedance is proposed . A 130nm SiGe BiCMOS integrated prototype is
fabricated to demonstrate these concepts.
In Chapter 6, a high-speed Watt-level digital polar transmitter (DPT) design
example using mm-wave switching ampliers, such as those covered in this thesis,
is covered. The DPT specications including the amplitude and phase resolutions
as well as the total system eciency estimates are presented. The thesis concludes
by discussing possible future work in this research direction.
12
Chapter 2
Millimeter-Wave Silicon Power Ampliers
Power ampliers at millimeter-wave frequencies historically have been designed
in III-V compound semiconductors for military applications. In-fact, as shown
in Fig. 2.1(a), monolithic power ampliers in III-IV compound semiconductor
technologies like GaAs and GaN with breakdown voltage swings of 20 V - 40 V that
can generate several Watts of output power across the millimeter wave spectrum
have been successfully demonstrated
1
. In contrast, silicon power ampliers until
recently could achieve non-power-combined output powers of less than 50 mW at
similar frequencies of operation. The large breakdown voltage (V
Br
), low knee
voltage (V
K
), and high unity power gain frequency (f
max
) of the III-IV technologies
also results in higher power amplier eciency as shown in Fig. 2.1(b) compared to
the eciency of monolithic silicon power ampliers, where large-scale lossy power-
combining is needed to achieve similar output power levels [22].
1
Various power combining schemes have been used to create mm-wave power amplier modules
with signicantly higher output power (e.g., 10 W - 1 KW).
13
Figure 2.1: Performance of selected reported monolithic power ampliers imple-
mented in dierent semiconductor technologies versus frequency, (a)P
out
, (b)PAE.
In recent years, however, the mm-wave frequency spectrum has gained promi-
nence for commercial applications like high-speed point-to-point wireless commu-
nication in infrastructure and consumer electronics and high resolution automotive
radars. Implementing the entire millimeter-wave transceiver in a silicon platform
benets from the availability of on-chip digital signal processing, CMOS technology
scaling, and cost reduction for large volume applications. This chapter will show-
case how switching ampliers in a silicon-germanium (SiGe) hetero-junction bipolar
transistor (HBT) can achieve moderate output powers ( 100 - 200 mW) with high
eciency at mm-wave frequencies. These ampliers can then be used in small-scale
on-chip power combining schemes for ecient Watt-level power generation from a
monolithic silicon chip.
14
Figure 2.2: Power amplier metrics.
2.1 Power Amplier Metrics at Mm-Waves
The front-end Watt-level power amplier module is the most power consuming
block of a millimeter-wave transmitter. To quantify the performance of a power
amplier shown in Fig. 2.2 as a black-box with input,output and DC supply ports,
the following metrics are dened [23].
2.1.1 Output Power
The output power (P
out
) is the power at the fundamental frequency of operation
obtained in the output load resistance (R
Load
) and dened as,
P
out
=
1
2
V
out
I
out
=
1
2
V
2
out
R
Load
=
1
2
I
2
out
R
Load
; (2.1)
where V
out
and I
out
are peak voltage and current sinusoids at the fundamental
frequency.
15
2.1.2 DC Power
The DC power (P
DC
) is the power drawn from the power supply to facilitate power
amplication. For the PA module operating with a supply voltage source V
CC
drawing a dc current I
DC
, P
DC
is given by
P
out
=V
CC
I
DC
: (2.2)
2.1.3 Input Power
The input power (P
in
) is dened as the signal power that is delivered to the power
amplier input so that it is amplied. For an input voltage swing V
in
at the PA
input with input current of I
in
, the PA input power P
in
is given by
P
in
=
1
2
V
in
I
in
: (2.3)
2.1.4 Power Gain
The power gain (G
P
) is dened as the ratio of the output power P
out
generated by
the PA to the input power P
in
. As P
in
expressed as
G
P
=
P
out
P
in
: (2.4)
16
2.1.5 Collector (or Drain) Eciency
The collector (or drain) eciency of a power amplier represents its DC to AC
power conversion capability including power dissipation inside the active transis-
tors and passive networks. Ideally, 100% collector eciency is desirable as then
the entire DC power (P
DC
) is converted into power at the frequency of operation
(P
out
). In practical PA implementations, especially at millimeter-wave frequencies,
transistor non-idealities and loss of passive components can degrade the collector
eciency signicantly. The collector eciency is dened as,
=
P
out
P
DC
: (2.5)
2.1.6 Power Added Eciency
Power-added-eciency (PAE) measures the added power (P
out
- P
in
) generation
eciency at the cost of DC power (P
DC
) and is represented as
=
P
out
P
in
P
DC
= (1
1
G
P
): (2.6)
These above mentioned power amplier metrics will be used in this thesis to
evaluate the performance of the proposed millimeter-wave power ampliers.
17
Figure 2.3: Breakdown voltage of some scaled silicon technologies.
2.2 Millimeter-wave Silicon PA Design Challenges
Realization of mm-wave power ampliers in silicon poses challenges that primarily
stem from features of silicon material and devices.
2.2.1 Low Breakdown Voltage of Silicon Technology
There is a fundamental trade-o between the breakdown voltage and the maximum
frequency of operation of semiconductor devices [24]. As per the Johnson limit [24],
the scaling of transistor dimensions enable higher operational frequencies (f
T
,f
max
)
at the cost of lower breakdown voltage (V
Br
). Fig. 2.3 shows that the transistor
breakdown voltage is of the order of few volts for some modern silicon CMOS
and SiGe BiCMOS processes with f
T
,f
max
> 300 GHz. Millimeter-wave Watt-
level power amplier designs using such low breakdown voltage technologies thus
require either large impedance transformation of the standard 50
antenna load or
18
Figure 2.4: Simulated loss and quality factor of on-chip passives versus frequency :
(a) 50
micro-strip transmission line, (b) 70 fF MIM capacitor.
large scale power combining of small output power individual ampliers. Another
important technology parameter is the knee voltage V
K
which is dened as the
minimum collector-emitter (drain-source) voltage required for a transistor to act as
a good current source with high output impedance. However, while the breakdown
voltage scales down with technology scaling, the transistor knee voltage does not
scale down proportionately. This results in lower collector eciency for linear power
ampliers realized in scaled technologies. For millimeter-wave switching ampliers,
the non-zero ON resistance and non-innite OFF resistance of these scaled silicon
processes result in collector eciency degradation as well. The performance limits
of linear and switching PAs in scaled silicon technologies are described in detail in
the subsequent sections.
19
Figure 2.5: (a) Impedance transformation for Watt-level output power in silicon
PAs, (b) Loss in output matching network.
2.2.2 On-Chip Passive Loss at Millimeter-Wave Frequencies
In order to achieve a single chip integrated silicon power amplier with low break-
down voltage, the necessary input-output-interstage matching networks need to be
implemented using on-chip passives such as transmission lines, capacitors, and in-
ductors. Fig. 2.4(a) shows the quality factor and insertion loss of a typical on-chip
microstrip transmission line versus frequency. The increase of insertion loss ver-
sus frequency is due to the reduced skin depth of the metals. On-chip capacitors,
implemented as metal-insulator-metal (MIM) capacitors, suer from low quality
factor at higher frequencies primarily due to the increasing loss of metal plates and
associated interconnects. Fig. 2.4(b) shows the simulated quality factor of a 70 fF
MIM capacitor versus frequency.
20
Figure 2.6: (a) Power-combining for Watt-level output power in silicon PAs, (b)
Loss of corporate (binary tree) Wilkinson power combining at Q-band versus num-
ber of power-combined unit ampliers.
2.2.3 Lossy Impedance Transformation
To generate high output power using low breakdown voltage silicon transistors, the
standard 50
antenna load needs to be impedance transformed down to a much
lower load-line value as shown in Fig. 2.5(a). Assuming a simple Class-A linear
amplier with supply voltage V
CC
such that the maximum output voltage swing
V
out
= V
CC
, the required load-line for standard 1.8 V CMOS or SiGe processes is
shown in Fig. 2.5(b) for dierent output power levels. The loss of a 2-element
output matching network, using inductor quality factor = 25 and capacitor quality
factor = 15 at Q-band frequencies (from Fig. 2.4), is also shown in Fig. 2.5(b). For
instance, to output 1 Watt power, the impedance seen by the PA should be 2.5

resulting in over 3 dB insertion loss (losing half of output power) in the impedance
transformation network.
21
2.2.4 Large-Scale Lossy Power Combining
Watt-level output power at millimeter-wave frequencies can be achieved by power
combining of several unit power ampliers with low output power and 50
load-
line (Fig. 2.6(a)). At millimeter-wave frequencies, to prevent undesired modes of
oscillation in large-scale power combined systems [25], isolating power combiners
like 2:1 Wilkinson power combiners are often preferred. Using 2:1 Wilkinson power
combiners in a binary tree (corporate) Wilkinson power-combining scheme, how-
ever, can increase the overall power combining loss signicantly. As shown in Fig.
2.6(b), assuming 0.5 dB loss/combiner at mm-wave frequencies
2
, the overall power
combining loss to achieve Watt-level output power can be more than 2 dB resulting
in signicant eciency degradation of the Watt-level power-combined system at
millimeter-wave frequencies.
Realization of ecient Watt-level silicon power ampliers at mm-wave frequen-
cies thus greatly benets from (1) developing ecient unit power amplier modules
that can generate higher power levels, and (2) low loss power combining schemes.
2.3 SiGe HBT Breakdown Mechanism
In this thesis, Silicon Germanium (SiGe) heterostructure bipolar transistors (HBT)
are used to demonstrate mm-wave power ampliers. In this chapter, a 130 nm SiGe
2
Designvand measured performance of a Q-band 2:1 Wilkinson combiner will be presented
later
22
Figure 2.7: Avalanche breakdown in SiGe HBTs, (a) normal operation for V
CE
<
BV
CEO
, (b) impact ionization for V
CE
BV
CEO
, (c) electron-hole pair generation
under open base condition, (c) base current reversal under shorted base condition.
HBT BiCMOS process is used [26] that provides high-speed npn SiGe HBTs with
f
T
= 200 GHz, f
max
= 280 GHz and breakdown voltages of BV
CEO
= 1.7 V and
BV
CBO
= 5.9 V, as well as 130nm CMOS eld eect transistors (FET). The CMOS
transistors enable integrated digital logic synthesis for the digital signal processing
in a digital transmitter as discussed later in Chapter 5. The breakdown voltage of
SiGe HBTs vary between BV
CEO
= 1.7 V and BV
CBO
= 5.9 V depending on the
collector current densityJ
C
. This current-density dependency of breakdown voltage
can be especially useful for designing high-power millimeter-wave power ampliers.
First, a brief description of the HBT `Avalanche Breakdown' mechanism is provided
below.
23
2.3.1 Avalanche Breakdown in SiGe HBTs
In comparison to silicon bipolar transistors, a well engineered Ge prole in the npn
SiGe HBTs' base region, lowers the potential barrier for minority carrier injection
and results in increased collector current density (J
C
) and increased current gain
() for the SiGe device [27]. A graded Ge prole induces a drift eld in the neutral
base region of SiGe npn HBTs which accelerates the minority carriers and reduces
the base transit time. The increased collector current density also helps in reducing
the base-emitter and base-collector parasitic capacitor charging times, resulting in
an enhanced speed of SiGe HBTs. The larger f
T
(and f
max
) at a higher J
C
in
modern SiGe processes however comes at the cost of earlier onset of Kirk eect
which causes widening of the base region, lower current gain and degraded device
performance. A higher collector doping is thus used to mitigate the onset of Kirk
eect while operating at higher J
C
. This high collector doping which is necessary
to obtain fast SiGe HBTs, however also reduces the breakdown voltage of the tran-
sistors by reducing the maximum base-collector junction V
CB
at which avalanche
multiplication starts. During normal operation, when V
CB
(= V
CE
for grounded
emitter conguration) is suciently low (< BV
CEO
) as shown in Fig. 2.7(a), the
SiGe HBTs can support high collector current density J
C
. As the voltage across
the transistor increases however, the high collector doping increases the magnitude
of the drift eld within the base space charge region causing the conduction elec-
trons to attain critical velocity (Fig. 2.7(b)). These electrons then collides with the
24
lattice creating an electron hole pair (EHP) by energy transfer in a process called
`Impact Ionization'. The collector voltage at which this EHP generation starts is
known as the open-base breakdown voltage BV
CEO
. This is because when V
CB
(=
V
CE
) =BV
CEO
and the base terminal is made open circuit as shown in Fig. 2.7(c),
the EHP created by this \Impact Ionization" process are in turn accelerated by the
electric eld to cross the base junction and generate additional electron hole pairs
in the emitter terminal. The multiplicative eect of these EHP generation under
suciently high electric eld is called avalanche multiplication. Due to rapid EHP
generation, the collector current can increase very fast causing device breakdown
by heat and current handling limitation. SiGe HBT circuits that are driven by high
impedance drivers like current sources (Fig. 2.7(c)), thus need to operate withV
CE
< BV
CEO
.
`Impact Ionization' by itself, however, does not cause catastrophic transistor
breakdown. As shown in Fig. 2.7(b), during the onset of `Impact Ionization' (V
CE
= BV
CEO
), the holes generated by the avalanche multiplication process, can
ow
out of the base-terminal, instead of reaching the emitter and creating more EHPs.
This process is aided by a low base impedance termination r
B
, like when SiGe
HBTs are driven by voltage sources as shown in Fig. 2.7(d). As the holes exit
the base terminal, base current (I
B
) decreases until it becomes zero, and can even
turn negative (base current reversal) depending on the collector voltage. For very
low base resistance r
B
0, most of the holes generated by avalanche process in
25
the collector, exit the base terminal and do not cause additional EHP generation
in the emitter, thus pushing back the onset of catastrophic transistor breakdown.
This dependence of breakdown voltage on base termination can be very useful in
situations where the transistor needs to operate under large collector voltage.
In addition, the number of initial EHPs that were generated due to high col-
lector voltage is also proportional to the collector current density J
C
at which
the transistor must tolerate the high V
CE
. For V
CE
< BV
CEO
, the SiGe HBTs
can be biased at any J
C
as there is no `Impact Ionization'. But as V
CE
exceeds
BV
CEO
, lowering theJ
C
in the transistor along with lowr
B
can ensure the onset of
avalanche multiplication can be signicantly delayed. In the limit, withr
B
= 0 and
J
C
= 0 (i.e biased as a switch with zero conduction current), the V
CE
can reach
BV
CBO
value [28]. BV
CBO
is the collector-base voltage limit under open-emitter
conguration where the transistor breaks under eld eect and is typically three
times theBV
CEO
value. TheBV
CEO
andBV
CBO
of a few representative SiGe HBT
technologies are provided in Table 2.1.
Operation of SiGe HBTs beyond their nominalBV
CEO
collector voltage ratings
have been studied in a common-base cascode ampler congurations [29] and in
high-voltage drivers [30]. In this thesis, the beyondBV
CEO
operation of SiGe HBTs
has been studied in the context of high-power, high eciency millimeter-wave power
ampliers.
26
Table 2.1: Technology parameters of some modern SiGe BiCMOS process.
2.3.2 Breakdown Voltage Maximization in SiGe HBT Ampliers
The eective breakdown voltage of SiGe HBTs dened henceforth asV
Br
is a strong
function of collector current density (J
C
) and base impedance (r
B
) termination
[28, 31]. This is true for all the SiGe HBT processes, some of which have been
highlighted in Table 2.1. The technology parameters of Table 2.1 will be useful
in evaluating mm-wave linear and switching amplier performance metrics in the
subsequent sections. The input time constant
in
is dened as r
B
C
in
, where r
B
is the base resistance andC
in
is the total input (base) capacitance when emitter is
grounded. The output time constant
out
for an HBT that operates as a switch
3
is dened as r
ON
C
OFF
, where r
ON
is the switch ON resistance and C
OFF
is the
total collector-bulk capacitance.
For the 130 nm SiGe BiCMOS process that has been used for mm-wave am-
plier design in this chapter, the eective breakdown voltage of the SiGe HBTs
vary between BV
CEO
= 1.7 V and BV
CBO
= 5.9 V (Table 2.1). This huge vari-
ation in usable collector voltage range has important implication in the amplier
3
when operating as a switch, the HBT operates in deep saturation (switch ON) or cut-o
(switch OFF) regions
27
performance metrics like P
out
,G
P
, andPAE as will be discussed shortly. To en-
sure that the amplier design can maximize the breakdown voltage of SiGe HBTs,
the eective breakdown voltage of the SiGe HBTs under dierent collector current
densities can be obtained from the circuit simulation setup shown in Fig. 2.8(a).
In this setup, a parametric sweep of collector voltageV
CE
is conducted for dierent
values of the base voltage V
BE
for three dierent values of base resistance r
B
= 0

, 100
, and 1 K
, respectively. The collector voltage at which the transistor
breakdown occurs for dierent values of collector current density is noted and the
results are summarized in Fig. 2.8(a) as a family of curves for dierent r
B
values.
It can be observed from Fig. 2.8(a) that for the 130 nm SiGe BiCMOS process, for
J
C
> 30mA=m
2
, theV
CE
must remainBV
CEO
= 1.7 V, while for lowJ
C
with low
r
B
, the V
CE
can reach as high as BV
CBO
= 5.9 V. This unique property of bipolar
transistors is common to silicon technologies like SiGe as well as III-V technologies
like GaAs and can be leveraged especially for power amplier designs at mm-wave
frequencies. The three times improvement in breakdown voltage enables signicant
improvement in power generation capability from this SiGe process at mm-waves,
mitigating need for large scale power-combining or impedance transformation for
ecient high power generation.
28
Figure 2.8: (a) Breakdown voltage (V
Br
) versus collector current density (J
C
) for the
130nm SiGe HBTs for dierent base resistance (r
B
) terminations, (b) SiGe HBT
eective breakdown voltage (V
Br
) under Class-A amplier load-line : maximum
collector voltage swing in SiGe HBT Class-A ampliers can be higher thanBV
CEO
= 1.7 V depending on DC bias point.
2.4 Linear Power Ampliers at Millimeter-Waves
Linear power amplier designs have been extensively studied in the literature [32];
but, such designs typically assume a xed transistor breakdown voltage irrespective
of the instantaneous current density. However, in SiGe HBTs, since the eective
breakdown voltage can vary betweenBV
CEO
= 1.7 V andBV
CBO
= 5.9 V, the linear
amplier load-lines and supply voltages can be optimally chosen to benet from the
collector voltage swing maximization. These load-lines and supply voltages (and
therefor PA performance metrics) are also a strong function of the linear amplier
conduction angle . In this section, a design methodology to maximize the SiGe
HBT current-density-dependent breakdown voltage and obtain performance metrics
29
for dierent classes of linear ampliers
4
(A, B, AB, C) corresponding to conduction
angle varying between (0; 2) will discussed.
2.4.1 Class-A Power Amplier
The simplest class of linear ampliers is the Class-A power amplier (Fig. 2.9(a)).
Since the SiGe HBT in Class-A operation remain within the forward active region
throughout the entire amplication cycle, the Class-A ampliers have a conduction
angle = 2. For ideal Class-A operation, the transistor acts like a current source
with purely sinusoidal collector voltage and current waveforms as
8
>
>
>
<
>
>
>
:
I
C
=I
DC;Q
+I
DC;Q
sin(!t);
V
C
=V
CC
(V
CC
V
K
)sin(!t);
(2.7)
where V
CC
is the supply voltage, V
K
is the knee voltage, and I
DC;Q
is the DC
quiescent current
5
. The output waveforms are then give by,
8
>
>
>
<
>
>
>
:
I
out
=I
DC
sin(!t);
V
out
=(V
CC
V
K
)sin(!t):
(2.8)
4
Here, the terms linear amplier is used in contrast to switching amplier. Linearity is not
implied.
5
It is assumed that collector voltage and current waveforms swing as high as possible. This
leads to the highest collector eciency.
30
At mm-wave frequencies, the performance metrics of linear Class-A ampliers in
terms of technology parameters (Table 2.1) can be summarized [32] as,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
out;max
=
1
2
(V
CC
V
K
)
2
R
Load
=
1
8
(V
Br
V
K
)
2
R
Load
;
G
P;max
=
Pout
P
in
= (
!
!max
)
2
=U;

max
=
1
2
(1
V
K
V
CC
) =
1
2
(
V
Br
V
K
V
Br
+V
K
);
PAE
max
=
max
(1
1
G
P;max
):
(2.9)
where V
Br
is the transistor maximum breakdown voltage, R
Load
is the resistance
seen at the collector, ! is the frequency of operation, !
max
is the transistor unity-
gain frequency, and U is the Mason's invariant gain. The supply voltage V
CC
is
determined from breakdown voltage and knee voltage as,
V
CC
=
1
2
(V
Br
+V
K
): (2.10)
In order to achieve maximum eciency of Eqn. 2.9, the load resistanceR
Load
must
also satisfy,
R
Load
=
V
CC
V
K
I
DC;Q
=
1
2
V
Br
V
K
I
DC;Q
; (2.11)
where I
DC;Q
is the collector DC quiescent current. Parameters in G
P;max
expres-
sion is introduced to model the gain degradation that happens whenR
Load
is chosen
31
for eciency maximization rather than gain maximization [32]. For varying be-
tween 0.5 to 0.8, the power gain degrades by 1-3 dB from the theoretical value
predicted by the Mason's invariant gain U.
It is evident from Eqn. 2.9, that maximizing V
Br
improves both output power
P
out
and eciency. Choosing a low base impedance r
B
= 0, enables the eective
V
Br
to move along the J
C
versus V
Br
contour shown in Fig. 2.8(a). But V
Br
maximization under a Class-A linear load-line also depends on the quiescent current
density J
C;Q
as shown in Fig. 2.8(b). To maximize power gain G
P
and PAE, the
current density in the SiGe HBTs during the maximum current swing I
C;max
must
be J
C;fmax
= 14 mA=m
2
for the 130 nm SiGe process (Table 2.1). Since I
C;max
= 2 I
DC;Q
, this determines the dc quiescent current density for J
C;Q
= 0.5
J
C;fmax
= 7 mA=m
2
(Biasing Point A) and xes V
Br
= 4 V under a tangential
Class-A load-line as shown in Fig. 2.8(b). A higher J
C;Q
biasing point (Biasing
Point B) will result in lower eective breakdown voltage (V
Br
= 2.3 V), while a
higher eective breakdown voltage V
Br
= 4.6 V can be obtained at the Biasing
Point C in Fig. 2.8(b) at the cost of sub-optimal J
C;Q
and thus lower power gain.
For a specied P
out
, the V
Br
obtained from Fig. 2.8(b) for the optimum J
C;Q
(Biasing Point A) sets the Class-A load-line R
Load
. Values of R
Load
, V
Br
, and
the frequency of operation ! in turn determine power gain G
P
, eciency and
PAE from Eqn. 2.9 and technology parameters from Table 2.1. The DC quiescent
32
current I
DC;Q
can be determined from Eqn. 2.11. The total DC quiescent cur-
rent I
DC;Q
and the J
C;Q
current density (Bias Point A) then xes the SiGe HBT
size. For the chosen SiGe HBT transistor size, the total parasitic output capacitor
C
OFF
(obtained from Table 2.1) can be signicant at mm-wave frequencies. This
collector-bulk capacitance o capacitance C
OFF
is now resonated out by the col-
lector inductance given by L
1
=
1
!
2
C
OFF
. All the design parameters for a linear
Class-A power amplier as shown in Fig. 2.9(a) operating at a certain frequency !
to generate a specied P
out
are now xed.
45 GHz Class-A PA
To validate the above mentioned design procedure, the design of a linear Class-A
power amplier with P
out
= 16.5 dBm at 45 GHz is shown in Fig. 2.9(a). For
V
Br
= 4 V (determined from J
C;max
as discussed before), a R
Load
= 35
shall be
chosen forP
out
= 16.5 dBm. This requires a 40.12m16m HBT transistor. This
R
Load
value does not require signicant impedance transformation that degrades the
eciency due to nite loss of passive components. The design steps to maximize
V
Br
in a SiGe HBT Class-A power amplier and thus obtain a specied P
out
with
maximum PAE are summarized in Fig. 2.9(b). Transient collector voltage and
current waveforms in Fig. 2.9(c), collector voltage-current contour in Fig. 2.9(d),
and performance summary table (assuming ideal lossless passives) in Fig. 2.9(e)
validate the analytical results when compared with simulations. The signicance
33
Figure 2.9: 130 nm SiGe HBT Class-A amplier at 45 GHz : (a) schematic, (b)
design steps in a SiGe HBT process for mm-wave Class-A ampliers, (c) collector
voltage and current transient waveforms, (d) collector voltage-current density con-
tour showing the SiGe HBT stays within the \Safe Area of Operation" while still
swinging upto V
Br
= 4 V (BV
CEO
= 1.7 V), (e) performance metrics.
of the aforementioned approach is the ability to extract more power from Class-A
SiGe HBT ampliers when considering the safe operating region (and not merely
BV
CEO
) in the design.
34
Figure 2.10: Transient waveforms of linear power ampliers with arbitrary conduc-
tion angle .
2.4.2 Linear Power Ampliers with Other Conduction Angles
Compared to Class-A power ampliers with conduction angle = 2, other classes
of linear ampliers exist with arbitrary conduction angles summarized below,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
ClassA : = 2;
ClassAB : 2 (; 2);
ClassB : =;
ClassC : 2 (0;);
(2.12)
The performance of these classes of linear ampliers are strongly dependent on
their conduction angle . The transient waveforms of the linear PA with arbitrary
conduction angle is shown in Fig. 2.10, where the conduction angel is determined
35
from the base terminal biasing voltage V
B
, the base-emitter voltage swing V
BE
and the turn on voltage V
BE;on
6
as = 2cos
1
(
V
B
V
BE;on
V
BE
). For a generalized
conduction angle , the collector voltage remains sinusoidal, but the output AC
current I
out
( ) can be derived as [32]
8
>
>
>
<
>
>
>
:
V
out
=(V
CC
V
K
)sin(!t);
I
out
( ) =
I
out;ClassA

sin( )
1cos(

2
)
;
(2.13)
where V
CC
=
1
2
(V
Br
+V
K
) for maximum voltage swing. However, as the voltage
and current waveforms change with the conduction angle , the eective breakdown
voltage V
Br
can also change depending on the quiescent collector current density
J
C;Q
requirement. For < with the SiGe HBTs biased below the turn-on voltage
V
BE;on
0.75 V, theJ
C;Q
becomes quite small andV
Br
can reach almost 5 V (Fig.
2.8(b)). The performance metric (P
out
;G
P
;;PAE of the linear amplier can then
be expressed in terms of the Class-A metrics modied by conduction angle terms.
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
out;max
( ) =
1

sin( )
1cos(

2
)
P
out;ClassA
( );

max
( ) =
sin( )
2sin(

2
) cos(

2
)

max;ClassA
;
G
P;max
( ) =
1
4
( sin( ))(1cos(

2
))G
P;max;ClassA
;
PAE
max
( ) =
max
( ) (1
1
G
P;max
( )
);
(2.14)
6
For simplicity, it is assumed that the transistor does not conduct any current for V
BE
<
V
BE;on
36
where ( ) is used to model the V
Br
variation depending on the amplier class.
In all these cases, to obtain the maximum eciency, the output load resistance for
dierent conduction angles also need to change given by,
R
Load
( ) =
1cos(

2
)
sin( )
R
Load;ClassA
: (2.15)
For = 2, Eqn. 2.14 simplify into Class-A eciency and power gain values
with ( ) = 1. For Class-B operation with = , V
Br
5 V, and the max-
imum achievable collector eciency is given by
max;ClassB
=

4
(1
V
K
V
CC
) and
G
P;max;ClassB
=
1
4
G
P;max;ClassA
.
45 GHz Class-B PA
A linear Class-B power amplier is designed at 45 GHz to generateP
out
= 18.5 dBm
withR
Load
= 35
andV
CC
= 2.8 V (Fig. 2.11(a)). The transistor size is chosen to
be 6 0.12m 15m from the current density calculation. The theoretical and
simulated Class-B transient waveforms are shown in Fig. 2.11(c).
7
The collector
voltage-current density contour plot is shown in Fig. 2.11(d). The theoretical
and simulated PA performance tabulated in Fig. 2.11(e) correlate closely with the
theoretical limits at 45 GHz.
7
The collector current waveform includes the current through capacitor C
OFF
. As such, the
waveform is not half sinusoid as expected from a Class-B amplier.
37
Figure 2.11: 130 nm SiGe HBT Class-B amplier at 45 GHz : (a) schematic, (b)
design steps in a SiGe HBT process for mm-wave Class-B ampliers, (c) collector
voltage and current transient waveforms, (d) collector voltage-current density con-
tour showing the SiGe HBT stays within the \Safe Area of Operation" while still
swinging upto V
Br
= 5 V (BV
CEO
= 1.7 V), (e) performance metrics.
2.5 Switching Power Ampliers at Millimeter-Waves
Till recently, most of the reported mm-wave silicon ampliers belonged to linear
classes of ampliers like A, AB, B, and relied on on-chip power combining to achieve
moderate output power levels at the cost of low eciency [33,34]. In recent years,
however, switching power ampliers at mm-wave frequencies have been demon-
strated in both CMOS and SiGe HBT technologies [35{39].
In contrast to linear ampliers, switching ampliers require the active transis-
tors to act as switches, with sharp turn ON and OFF transitions. Ideal sharp
transitions are dicult to achieve in real transistors with nite base transit time
38
and non-zero switch ON resistance especially at millimeter-waves. However, previ-
ous studies [40] have shown that as long as the transistors are driven hard enough to
produce upto three-to-four harmonics, the current and voltage waveforms of some
switching amplier closely resemble those predicted by theory where all harmonics
are present. The main advantage of switching ampliers is the higher achievable
collector eciency due to non-overlapping collector voltage and current waveforms
which reduces the power dissipation in the transistors. However, the same non-
overlapping of voltage and current waveforms also enables the switching ampliers
in SiGe HBTs to achieve higher collector voltage swing by exploiting the SiGe HBT
breakdown curves of Fig. 2.8(a). In contrast to linear power ampliers, in SiGe
HBT switching power ampliers, the transistors are turned OFF with no collec-
tor current during half the amplication cycle, and thus the maximum transistor
breakdown voltage (V
Br
) in switching power ampliers can always be as high as
BV
CBO
[41]. This enables switching ampliers to achieve both high output power
while maintaining high eciency at mm-waves.
The nonlinear input-output transfer function of a switching power amplier
prevents it from being used in conventional linear transmitters. However, switching
ampliers can be successfully utilized in digital transmitter architecture like digital
polar transmitter, amplitude modulators, and power DACs [42{44]. Highly ecient,
medium power (100 - 200 mW), Class-E amplier unit cells, as demonstrated in this
thesis, can enable realization of ecient Watt-level power modulators and power
39
Figure 2.12: Class-E amplier: (a) Generic schematic, (b) Simplied model during
ON cycle, (c) Simplied model during OFF cycle, (d) Ideal transient waveforms.
DACs at mm-wave frequencies. Switching power ampliers, depending on their
fundamental load and harmonic terminations can encompass several classes like
Class-E, Class-F and their hybrids [45] which are discussed in detail in Chapter 4.
However, as an initial study for exploiting the beyond BV
CEO
operation of SiGe
HBTs in millimeter-wave switching power ampliers [41], a Class-E power amplier
architecture (Fig. 2.12)(a) is studied in this section. In comparison to other classes
of switching power ampliers, the Class-E PA provides several benets. Firstly the
collector-bulk capacitanceC
OFF
=C
1
of the large SiGe HBT power transistors can
be explicitly included in the mm-wave Class-E PA design. Thus, the transistor OFF
capacitance does not distort the non-overlapping collector voltage-current waveform
and a high Class-E eciency can be maintained even at mm-wave frequencies.
40
Figure 2.13: (a) Collector voltage-current contour of Class-E switching power am-
plier operating within SiGe HBT safe area of operation, (b) Transient waveforms
of a Class-E power amplier during its beyond BV
CEO
operation.
Secondly the Class-E collector-voltage current contour as shown in Fig. 2.13(a)
ensures that the transistors remain within safe breakdown voltage limits during
both DC and RF operations while still swinging as high as BV
CBO
= 5.9 V. (Fig.
2.13(b)).
2.5.1 Mm-Wave Class-E Amplier Analysis
The Class-E switching amplier architecture of Fig. 2.12 can be analyzed by solving
the equivalent circuits during the `ON' and `OFF' states (Fig. 2.12(b) and (c)),
respectively. Solving the Class-E equivalent circuits during the ON and OFF states
enables determining the circuit voltages and currents including the collector voltage
V
C
, output voltageV
out
, inductor currentI
L
, and the transistor switch currentI
SW
8
. This study will also allow determining the circuit design parameters like collector
8
Ideally, a Class-E transistor operates as an ON/OFF switch. Therefore, in this context, we
may refer to transistor and switch interchangebly
41
inductor L
1
and shunt capacitance C
1
(and thus the switch size C
OFF
=C
1
) for a
given load R
Load
and frequency of operation !.
Previous studies have shown that an equal ON-OFF duty cycle = 50% of the
time period leads to maximum power delivery [46]. A 50% duty cycle and an
output load current of I
Load
= I
R
sin( +) to ensure only fundamental power
delivery to the output load R
Load
has been assumed for the following analysis of
Class-E ampliers. In the following analysis =!t has been used to normalize the
Class-E time period irrespective of frequency of operation. The operation of the
Class-E amplier has been divided into two modes, namely, ON and OFF dened
as
8
>
>
>
<
>
>
>
:
TransistorON :2 (0;)
TransistorOFF :2 (; 2)
(2.16)
During the ON cycle, dierential equation for the Class-E equivalent schematic
shown in Fig. 2.12(b), can be summarized as
I
SW
() =
1
!L
1
Z

1
(V
CC
V
C
()) +I
R
sin( +);82 (0;):
Similarly, during the OFF cycle, dierential equation for the Class-E equivalent
schematic shown in Fig. 2.12(c), can be summarized as
V
C
() +!
2
L
1
C
1
d
2
V
C
()
d
2
=V
CC
+!L
1
I
R
cos( +);82 (; 2):
42
Dening two new variables as
8
>
>
>
<
>
>
>
:
q =
1
!
p
L
1
C
1
;
p =
!L
1
I
R
V
CC
:
(2.17)
the solution for the Class-E switch current I
SW
can be obtained to be,
I
SW
() =
8
>
>
>
<
>
>
>
:
I
R
[

p
+sin( +)sin] +I
SW
(0);82 (0;)
0;82 (; 2)
(2.18)
whereI
SW
(0) is the switch current boundary condition. An important assumption
for the Class-E analysis is zero-voltage switching `ZVS' and zero-voltage deriva-
tive switching `ZdVS' of the collector voltage and current waveforms [46]. This
essentially eliminates any conduction loss due to overlapping of voltage-current
waveforms during the OFF cycle (ZVS) and also eliminates any dissipative ca-
pacitive loss during the OFF-ON switching instant (ZdVS). Mathematically they
can be represented as V
C
(2) = 0 and V
0
C
(2) = 0. For periodic operation, the
43
= 0; 2 conditions can be merged to express the switch current boundary condi-
tion as I
SW
(0) = !C
1
V
0
C
(2) = 0 as well. Similarly, the solution for the Class-E
switch voltage V
C
, can be obtained as,
8
>
>
>
<
>
>
>
:
V
C
() = 0;82 (0;)
V
C
() +
1
q
2
d
2
V
C
()
d
2
=V
CC
[1 +pcos( +)];82 (; 2)
(2.19)
Solving the dierential equations of Eqn. 2.19 using homogenous and particular
solutions, and dening Q =
q
1q
2
the collector voltage V
C
can be further simplied
into,
8
>
>
>
<
>
>
>
:
V
C
() = 0;82 (0;)
V
C
() =V
CC
[K
1
cos(q) +K
2
sin(q) + 1qpQcos( +)];82 (; 2);
(2.20)
where the constants K
1
and K
2
are dened as,
8
>
>
>
<
>
>
>
:
K
1
=qQcos(2q)[pcos] +Qsin(2q)[psin]cos(2q)
K
2
=qQsin(2q)[pcos]Qcos(2q)[psin]sin(2q):
(2.21)
With zero switching conditions [46], the variables p and can be solved in Eqn.
2.18 and Eqn. 2.20 to uniquely determine the values ofL
1
,C
1
in terms of frequency
of operation ! and R
Load
. Two additional boundary conditions can be used :- the
current through the inductor is continuous during the switching moment = and
44
collector voltageV
C
needs to start from zero at the switching moment =. These
conditions can be mathematically expressed as,
8
>
>
>
<
>
>
>
:
I
SW
() =
1
q
2
!L
1
V
0
C
();
V
C
() = 0:
(2.22)
Solving Eqns. 2.18 and 2.20 using Eqn. 2.22 enables the variables p and to be
solved in a matrix form, given by,
2
6
6
4
qQ(1 +cos(q) Qsin(q)
qQsin(q) 2qQ[1 +cos(q)]
3
7
7
5
2
6
6
4
pcos
psin
3
7
7
5
=
2
6
6
4
1cos(q)
qsin(q)]
3
7
7
5
(2.23)
The solutions for the Class-E variables p and in Eqn. 2.23 can now be used to
uniquely determine the values of L
1
and C
1
(and thus C
1
=C
OFF
for switch size)
using,
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
P
out
=P
DC
; where
P
out
=
1
2
I
2
R
R
Load
;
P
DC
=
V
CC
2
R
2
0
I
L
()d:
(2.24)
From Eqn. 2.23, p and are found to be functions of the variable q. The values
of q are swept until the resulting value of p and lead to the maximum possible
C
1
= C
OFF
from Eqn. 2.25 (and hence largest switch size for maximum collector
eciency). For this value of q, and the resulting solved Class-E variablesp;, Eqn.
45
2.25 can also be used to obtain the other Class-E component value L
1
and output
power P
out
given by,
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
L
1
=
R
Load
!
p
Z
;
C
1
=
1
q
2
!R
Load
Z
p
;
P
out
=
V
2
CC
2R
Load
Z
2
;
(2.25)
where
Z =

2p
sin +
2

cos (2.26)
2.5.2 Mm-Wave Class-E Performance Metrics
Based on the previous solutions of Class-E circuit parameters, it is possible to
determine the Class-E performance metrics (P
out
, G
P
, , PAE). In a Class-E
design with ZVS, ZdVS boundary conditions, the only source of power loss is the
conduction loss in real transistors (P
SwitchLoss
) with non-zero r
ON
during the ON
cycle. Thus to minimize the switch r
ON
resistance, the largest possible transistor
size is chosen by ensuring the entire Class-E capacitance budget C
1
is made up of
the transistor o capacitanceC
OFF
. For a chosen technology, values ofC
1
=C
OFF
can be used to determine the switch on resistancer
ON
from the switch output time
constant
out
= r
ON
C
OFF
as shown in Table 2.1. The switch conduction loss
(P
SwitchLoss
), in presence of non-zero switchr
ON
, can be derived from perturbation
analysis as
P
SwitchLoss
=
1
2
Z

0
I
2
SW
()r
ON
d; (2.27)
46
whereI
SW
() is the switch current whenr
ON
= 0. For a given frequency of operation
!, output loadR
Load
, the Class-E component values L
1
,C
1
and output powerP
out
can be expressed in terms of normalized constants, K
L
, K
C
and K
P
respectively
given as,
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
K
L
=
!L
1
R
Load
;
K
C
=!C
1
R
Load
;
K
P
=
R
Load
V
2
CC
P
out
(2.28)
Using I
SW
expressions from Eqn. 2.18, the P
SwitchLoss
can now be expressed in
terms of P
out
as,
P
SwitchLoss
=
SwitchLoss
! [r
ON
C
OFF
]P
out
; (2.29)
where
SwitchLoss
=
Z
2
R

0
(

p
+sin(+)sin)
2
dsin+2cos)
2K
P
K
C
. For a Class-E amplier,
maximizing the switch size so that C
1
= C
OFF
ensures that K
L
;K
C
;K
P
are con-
stants, independent of given R
Load
, and frequency !. The maximum achievable
Class-E collector eciency can then be expressed in terms of operation frequency
! and technology time constant
out
=r
ON
C
OFF
(Table 2.1) as

max
=
P
out
P
out
+P
SwitchLoss
=
1
1 +
SwitchLoss
!
out
: (2.30)
For Class-E operation,
SwitchLoss
4.6 independent of R
Load
and !. It is im-
portant to note that Eqn. 2.30 puts an upper-bound on the maximum achievable
47
collector eciency in a Class-E architecture independent of R
Load
and in terms of
frequency ! and transistor technology
out
. As such, this equation is very use-
ful to estimate Class-E eciency not only in SiGe HBTs but in other silicon and
non-silicon technologies as well, across all frequencies of operation.
The other performance metrics in a Class-E amplier can also be expressed in
terms of silicon technology parameters. In a SiGe HBT Class-E design, the peak
collector voltage,V
C;max
, must remain below theBV
CBO
to prevent transistor break-
down. Given V
C;max
= BV
CBO
, R
Load
, and !, it can be shown that, the maximum
achievable output power P
out;max
occurs for q 1:41 and the corresponding p and
values. The maximum output power can then be written as
P
out;max
=
1
2
BV
2
CBO
R
Load

2
; (2.31)
where 0.453 is a Class-E constant, independent of frequency and technology.
It can also be shown that to maintainP
out
in presence of the conduction loss due to
the nite r
ON
of the small transistors at mm-wave frequencies, the supply voltage
V
CC
also needs to be scaled as given by,
V
CC
=V
CC
0
[1 +!
out

SwitchLoss
]; (2.32)
48
where V
CC
0
=

2p
sin+
2cos

BV
CBO

BV
CBO
3:56
. To determine the large-signal
power gain G
P
in switching Class-E ampliers, the input power P
in
of the Class-
E schematic in Fig. 2.12 can be determined in terms of transistor technology
parameters [47] as
P
in
=
1
2
[
!
in
1 + (!
in
)
2
]!C
in
V
2
in
; (2.33)
where
in
= r
in
C
in
is only a function of technology (Table 2.1). Input voltage
swing, V
in
, should be large enough so that the selected transistor size can produce
the required collector current. Unfortunately, too large a input voltage swing across
the transistor, in the case of SiGe HBT, has a detrimental eect: it causes the
base-collector diode to turn on heavily (during the ON cycle), dissipating a large
amount of power, and consequently degrading PAE. On the other hand, a small
input voltage swing is insucient to generate the peak current waveform; hence,
P
out
and consequently PAE drop [48]. The input power, shown in Eqn. 2.33, can
be simplied as a function of the voltage that appears across the intrinsic transistor
base-emitter junction, V
BE
, as
P
in
=
1
2
(!
in
)(!C
in
)V
2
BE
=
1
2
(!
in
)K
C
V
2
BE
R
Load
; (2.34)
where =
C
in
C
1
is the ratio of the HBT input and output capacitances (Table 2.1),
and V
BE
=
V
in
p
1+(!
in
)
2
determines the collector current waveform. Specically, the
49
peak value of V
BE
should provide the peak value of collector current I
SW;max
that
can be shown to be
I
SW;max
=
BV
CBO
R
Load
K(
max
;
I;max
)
K(
max
;
V;max
)
; (2.35)
where K(
max
;
I;max
) and K(
max
;
V;max
) are Class-E amplier constants, and

I;max
and
V;max
correspond to the phases where transistor current and voltage
reach their peak values, respectively. To ensure that the collector voltageV
C
reaches
BV
CBO
, the input base voltage swingV
BE
must be large enough to ensure the result-
ingI
C
=I
SW;max
. Using the exponential base-voltage collector current relationship
in an HBT,V
BE
=V
T
ln[
I
SW;max
I
DC;Q
] in Eqn. 2.34, the overall input power of the Class-E
amplier under the maximum output power condition is then given as
P
in
=
1
2
(!
in
)K
C
V
2
T
R
Load
[ln(BV
CBO
) +ln(!) +ln(K
ClassE
) +ln(
C
1
=m
2
I
DC;Q
=m
2
)]
2
:
(2.36)
The Class-E power gain G
P;max
=
Pout;max
P
in
can now be determined from Eqn. 2.31
and Eqn. 2.36. The maximum achievable PAE can now be obtained from Class-E

max
and G
P;max
values.
For a given frequency of operation ! and output load R
Load
, the Class-E per-
formance can be summarized in terms of transistor technology parameters. The
maximum achievableP
out
,,G
P
, and PAE will be achieved for the maximum pos-
sible collector peak voltage value, i.e., V
C;max
= BV
CBO
in the case of SiGe HBTs,
50
the maximum allowable HBT size (so that C
1
= C
OFF
), and optimum passive
values (L
1
, C
1
) (determined from Class-E p, solution) given as,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
out;max
=
1
2
BV
2
CBO
R
Load

2

BV
2
CBO
9:75R
Load
;

max
=
1
1+
SwitchLoss
!out

1
1+4:6!out
;
G
P;max
= [
1
!
][
BV
2
CBO

in

][

2
K
C
V
2
T
][ln(BV
CBO
) +ln(!) +ln(K
ClassE
) +ln(
C
1
=m
2
I
DC;Q
=m
2
)]
2
;
PAE
max
= (1
1
G
P;max
)
max
;
(2.37)
where 0:453,
SwitchLoss
4:6, K
C
0:6765, and K
ClassE
1:484 are Class-
E constants, I
DC;Q
=m
2
is the Class-E quiescent current density and remaining
terms are technology parameters shown in Table 2.1. To maintain the maximum
P
out
, G
P
, and PAE at mm-wave frequencies, the supply voltage V
CC
needs to be
scaled according to Eqn. 2.32. Hence, while low frequency Class-E design equations
predict the maximum collector voltageV
C;max
to be 3.56 times theV
CC
, in mm-wave
Class-E implementation this ratio is often closer to 2.5 and progressively gets lower
with higher frequency of operation. Using a higher value of V
CC
(Fig. 2.14) is not
necessarily disadvantageous for a SiGe HBT Class-E design, since the HBTs are
biased just below the cut-in threshold voltage with negligible quiescent DC collector
current. Thus, the SiGe HBTs in our proposed Class-E methodology are designed
to swing as high as theBV
CBO
to generate the desired mm-wave output power with
the maximum achievable PAE.
51
Figure 2.14: Voltage scaling and transistor sizing in 130nm SiGe HBT Class-E
amplier design versus frequency.
Figure 2.15: 130 nm SiGe HBT Class-E amplier at 45 GHz : (a) schematic, (b)
design steps in a SiGe HBT process for mm-wave Class-E ampliers, (c) collector
voltage and current transient waveforms, (d) collector voltage-current density con-
tour showing the SiGe HBT stays within the \Safe Area of Operation" while still
swinging upto V
Br
= BV
CBO
= 5.9 V, (e) performance metrics.
52
45 GHz Class-E PA
To verify that Class-E switching amplier waveforms can be designed at Q-band
frequencies in the 130 nm SiGe HBT process following the previously outlined
analysis (summarized in Fig. 2.15(b)), a 45 GHz Class-E power amplier withP
out
= 20 dBm is designed and simulated (Fig. 2.15(a)) with R
Load
= 35
. At Q-
band frequencies, the simulated collector voltage and collector current waveforms
as shown in Fig. 2.15(c) can only support the rst three harmonics; but, they
compare well with the theoretical Class-E waveforms [40]. The simulated Class-E
voltage-current contour at 45 GHz shown in Fig. 2.15(d) also compare favorably
with the theory. Estimate of Class-E performance based on technology parameters
(Table 2.1) and Eqn. 2.37 matches well with the simulated values (assuming lossless
passives) in the performance table of Fig. 2.15(e).
2.5.3 Performance Limits of SiGe HBT Class-E PAs
Several interesting trends can be inferred from the Class-E performance limits of
Eqn. 2.37. The output power, P
out
, of a Class-E amplier is independent of the
operational frequency as predicted by Eqn. 2.37 and veried with simulations. Fig.
2.16(a) shows the analytical and simulated output power versus operation frequency
for a Class-E 130nm SiGe HBT amplier designed to deliverP
out
= 20 dBm toR
Load
= 35
. Fig. 2.17(a) shows the quadratic increase of P
out
versus V
C;max
, the peak
collector voltage. The maximum output powerP
out
is obtained forV
C;max
equals to
53
Figure 2.16: Maximum achievable output power, power gain, collector eciency,
and PAE versus frequency in a 130nm SiGe HBT Class-E amplier.
BV
CBO
as predicted by Eqn. 2.37. The inverse relationship betweenP
out
andR
L
is
shown in Fig. 2.18. The maximum achievable collector eciency,
max
, of a Class-
E amplier is a decreasing function of frequency as predicted by Eqn. 2.37. Figure
2.16(b) shows the analytical and simulated
max
versus operational frequency for
a Class-E 130nm SiGe HBT amplier designed to deliver P
out
= 20 dBm to R
Load
= 35
. The analytical expression over-estimates the actual collector eciency for
a number of reasons. In our analysis, the values for r
ON
and C
1;max
= C
OFF
are
assumed to be constant, while in reality, both change across a wide range of values
throughout the large signal transients (Fig. 2.15(b)). There is a larger discrepancy
at lower frequencies since the eectiver
ON
of large HBTs do not scale down linearly
compared to the r
ON
of smaller HBTs used in the mm-wave designs. The eective
r
ON
of large HBTs are aected by the collector connection resistances in addition
to the intrinsic transistor ON resistance. Also for large devices at low frequencies,
54
Figure 2.17: Maximum achievable output power, power gain, collector eciency,
and PAE versus maximum collector voltage (V
C;max
) for a 45 GHz, 130nm SiGe
HBT, Class-E amplier.
the r
OFF
of the transistors may not be insignicant and dissipate some power
during the switch OFF state of the transistor. It is important to note that
max
only depends on
out
and not any other technology parameters. Figures 2.17(b)
and 2.18 show the independence of
max
versus peak collector voltage, V
C;max
and
R
Load
, respectively. In a SiGe HBT Class-E amplier, the maximum achievable
power gain, G
P;max
, is a nonlinear function of frequency as shown in Eqn. 2.37.
At high-enough frequencies, G
P;max
/ !
1
which indicates a much more graceful
degradation with frequency as compared to linear ampliers where G
P
/ !
2
.
Figure 2.16(a) shows the analytical and simulated maximum power gain versus
operation frequency for a Class-E 130nm SiGe HBT amplier designed to deliver
P
out
= 20 dBm to R
Load
= 35
, both indicating a -10 dB/dec decrease of G
P;max
versus frequency at high-enough frequencies. Figure 2.16(a) shows the quadratic
55
Figure 2.18: Maximum achievable output power, power gain, collector eciency,
and PAE versus the load resistance for a 45 GHz, 130nm SiGe HBT, Class-E
amplier (lossless passives).
increase ofG
P;max
versus the peak collector voltage V
C;max
, with the highest power
gain achievable only whenV
C;max
equalsBV
CBO
. It is important to note thatG
P;max
does not depend onR
L
or equivalentlyP
out
(Fig. 2.18). Maximum PAE drops with
frequency, increases withBV
CBO
, and is independent ofR
Load
(or equivalentlyP
out
)
as shown in Figs. 2.16(b), 2.17(b), and 2.18. The latter point is rather important
and peculiar - from the transistor perspective, at any frequency, the maximum
achievable PAE can be achieved independent of the output power level. However,
larger power levels require smaller load resistances seen by the device, and as such
necessitate a signicant impedance transformation for a typical 50
load. The
loss associated with such an impedance transformation network reduces the power
delivered to the ultimate 50
load and the overall PAE [49]. Input and output
56
impedance transformation networks, that are naturally lossy, do aect the amplier
performance as shown in the following modied expressions,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
Q
Passive
out;max
=P
out;max
[
1
1+2
Q
out
Q
Passive
];

Q
Passive
max
=
1
1+
SwitchLoss
!out+
1
Q
Passive

Passive

1
1+4:6!out+
2:39
Q
Passive
;
G
Q
Passive
P;max
=G
P;max
1
[1+2
Q
out
Q
Passive
][1+2
Q
in
Q
Passive
]
;
PAE
Q
Passive
max
= [1
1
G
Q
Passive
P;max
]
Q
Passive
max
;
(2.38)
whereQ
Passive
is the quality factor of passive components in the impedance transfor-
mation networks,
Passive
2.39 is another technology and frequency independent
Class-E constant under the output power maximization condition, and Q
out
and
Q
in
are input and output impedance transformation ratios determined from Q
out
=
q
R
LoadMatch
R
Load
1 and Q
in
=
q
R
SourceMatch
r
B
1. The eect of nite quality factor
passives with Q
Passive
= 20 under the 50
input and output matching conditions
at 45 GHz for dierent R
Load
values is shown in Fig. 2.19.
The analysis oered in this section enables predicting the performance of mm-
wave Class-E ampliers as a function of SiGe HBT technology parameters such as
those shown in Table 2.1. This is a major contribution as it allows the designers
to select the best technology (or specic
avor of a technology) for a given set of
specications, namely, P
out
and !. While this analysis accounts for the eect of
intrinsic transistor parasitics given by the technology parameters of Table 2.1 in
57
Figure 2.19: Maximum achievable output power, power gain, collector eciency,
and PAE versus the load resistance for a 45 GHz, 130nm SiGe HBT, Class-E
amplier (Q
Passive
= 20).
Class-E amplier performance, it must be mentioned that the parasitics associated
with the layout of HBTs especially at mm-waves have not been included in the
preceding analysis and simulations. The layout parasitic capacitances increases the
eective input and output time constant of the transistors leading to lower power
gain and collector eciency and thus lower PAE in practical implementations. At
mm-wave frequencies, this performance degradation can be quite signicant espe-
cially for stacked Class-E amplier architectures introduced in Chapter 3. Specic
eects of layout parasitics on the mm-wave Class-E performance has been discussed
in Chapter 3. For the transistor layouts used in the following mm-wave Class-E
implementations, the modeling of mm-wave SiGe HBTs (Fig. 2.20) and eect of
layout parasitics have been discussed in detail in Section 2.5.5 for specic imple-
mentations [41,50,51].
58
Figure 2.20: Lumped modeling of layout parasitics in a 2 16m SiGe HBT.
2.5.4 Stability Considerations in Class-E HBT Ampliers
Two main types of instability are observed in the SiGe HBT designs in a beyond
BV
CEO
Class-E operation. Firstly, large signal S-parameter simulations indicate
the generation of sub-harmonic tones in the designed circuit; this is most likely
caused parametrically due to hard switching of the device's large nonlinear base-
emitter capacitance. This instability can be mitigated by adding half-harmonic
traps, added to the base of Class-E ampliers (Fig. 2.21(a)). In addition, the base
current reversal due to the beyond BV
CEO
operation of SiGe HBTs results in a
negative real part of the input impedance, which makes the system susceptible to
small signal low frequency oscillations. A parallel base resistance can be added to
mitigate the eect of this base current reversal at large collector voltage swings (Fig.
2.21(b)). Addition of the above mentioned stabilizing networks in the implemented
designs has ensured that the designs remain unconditionally stable under both
small-signal and large signal operation.
59
Figure 2.21: Class-E amplier instability mitigation, (a) Eect of half-harmonic
trap, (b) Eect of parallel resistance.
2.5.5 Millimeter-Wave Class-E Implementations
To validate the aforementioned design methodologies, several Q-band Class-E SiGe
HBT ampliers have been fabricated in the 130 nm SiGe BiCMOS 8HP process
(Table 2.1) [26] with 7 metal layers and MIM capacitors. In all designs, the large
power transistors are realized as a parallel connection of smaller devices that are
available and modeled in the IBM 8HP Process Design Kit (PDK). Standard RC
extraction tools are used to model intra-device interconnects while passives such
as micro-strip lines and MIM capacitors are simulated in the HyperLynx 3D EM
electromagnetic simulator [52]. The output networks in all of these designs have
been implemented to serve as series resonant lter at the frequency of operation as
well impedance transformation network from the standard 50
interface. Both the
60
input and output networks have been designed using minimum number of on-chip
passives to reduce the eect of their loss on the overall performance. GSG pad
parasitics have also been included in these mm-wave designs. Mm-wave designs
generally need to undergo several iterations in order to mitigate the eect of layout
parasitics particulary the intra-device interconnect of the large SiGe HBTs (Fig.
2.20) on the overall performance. Eect of layout parasitics and the design steps
undertaken to address those issues for the Class-E designs have been highlighted
step-by-step in Fig. 2.26. Detailed design and layout principles concerning each
of the individual designs are available in [50,51]. During probe measurements, the
absence of spurious oscillations under large signal operation [25, 53], is ensured by
monitoring the output via a spectrum analyzer. The output power measurements
are validated both from the spectrum measurements as well as a thermocouple
power sensor. The measurement setup loss at both the input and output is de-
embedded by scalor \through" measurements.
One-Stage Q-band SiGe HBT Class-E Amplier
Fig. 2.22 shows the schematic and chip microphotograph of a one-stage Q-band
Class-E amplier. The active device core is realized as a parallel combination of
two high-f
T
npn HBTs available in the PDK, each with a 16 m emitter length,
each laid out in a CBEBC (collector-base-emitter-base-collector) conguration for
additional collector current handling reliability. Large signal measurements for the
61
Figure 2.22: One-stage Class-E amplier schematic and chip microphotograph.
Class-E operating points of V
CC
= 2.5 V and base DC voltage V
B
= 0.75 V are
shown in Fig. 2.23. Peak PAE of 36% at 18 dBm output power and a P
1dB
bandwidth of > 7 GHz around 41 GHz is measured.
Two-Stage Q-band SiGe HBT Class-E Amplier
Fig. 2.24 shows the schematic and chip microphotograph of a two-stage Q-band
Class-E amplier [50]. The simulated transient waveforms are shown in Fig. 2.25.
At mm-wave frequencies, various circuit non-idealities and implementation issues
such as layout parasitics can cause signicant performance deviation from the the
theoretical and initial simulation predictions (Fig. 2.26). The rst stage Class-E
driver is designed and biased identical to the single-stage Class-E that was discussed
previously (Fig. 2.22). Large signal measurements for the Class-E operating points
of V
CCCore
= 2.5 V and V
BCore
= 1.4 V are shown in Fig. 2.27. Peak PAE of
31.5% at 20.2 dBm output power and a P
1dB
bandwidth of at least 4 GHz (42 -
46 GHz) is measured.
62
Figure 2.23: One-stage Class-E amplier performance: (a) Output power and power
gain versus input power at 41 GHz, (b) Collector eciency versus output power
at 41 GHz, (c) Measured performance across the Q-band, (d) PAE versus output
power at 41 GHz.
Figure 2.24: Two-stage Q-band Class-E amplier schematic and chip microphoto-
graph.
63
Figure 2.25: Simulated transient waveforms of the 45 GHz SiGe HBT Class-E
amplier. Note thatI
C
corresponds to the summation of transistor and its collector
capacitance currents.
Figure 2.26: Design steps leading to a complete two-stage Q-band Class-E amplier.
64
Two-Way Wilkinson Power Combined SiGe Class-E Amplier
To demonstrate higher power generation using on-chip power-combining at milliemter-
wave frequencies, a two-way Wilkinson-power-combined Class-E amplier, using
the two-stage designs of the previous section, was fabricated [51] (Fig. 2.28). The
Wilkinson combiner uses microstrip transmission line as 8.5 m thick AM metal
layer for signal on a 50m thick M2-M1 ground plane 11.8m separation between
them. Two-back-to-back 50
Wilkinson combiners were fabricated and measured
using a calibrated vector network analyzer and the measured insertion loss was
divided equally assuming symmetrical loss in each of the combiners. The on-chip
two-way 50
Wilkinson power combiner in the design was measured to be 85%
ecient across the operating frequency range. Large signal measurements for the
Class-E operating points of V
CCCore
= 2.5 V are shown in Fig. 2.29. Peak PAE
of 23% at 22.4 dBm output power and a P
1dB
bandwidth of at least 4 GHz (42 -
46 GHz) is measured.
2.6 Conclusions
In this chapter, the design methodology and performance limits of switching Class-
E power ampliers are evaluated against linear amplier Classes at millimeter-wave
frequencies. From the preceding studies it can be observed, that switching ampli-
ers can achieve not only much higher collector eciencies at millimeter-waves com-
pared to linear ampliers, but can also generate higher power level for the same load
65
Figure 2.27: Two-stage Class-E amplier performance: (a) Output power and
power gain versus input power at 45 GHz, (b) Collector eciency versus output
power at 45 GHz, (c) Measured performance across the Q-band, (d) PAE versus
output power at 45 GHz.
Figure 2.28: Die photo of the two-way Wilkinson power-combined Q-band Class-E
amplier with S-parameters of back-to-back Q-band Wilkinson power combiners.
66
Figure 2.29: Two-way Wilkinson power combined Class-E amplier performance:
(a) Output power and power gain versus input power at 45 GHz, (b) Collector
eciency versus output power at 45 GHz, (c) Measured performance across the
Q-band, (d) PAE versus output power at 45 GHz
Table 2.2: Output power vs peak PAE of some published mm-wave Silicon power
ampliers.
67
Table 2.3: Measured Performance Summary of the Fabricated SiGe HBT Ampli-
ers.
resistance by exploiting the avalanche breakdown mechanics in SiGe HBT technolo-
gies. Performance limits of Class-E power ampliers in terms of silicon technology
parameters are also presented. Proof-of-concept prototypes demonstrating switch-
ing amplier operation at mm-wave frequencies are also implemented. Table. 5.1
shows the performance summary of the implemented designs; multiple chips are
measured to conrm the design robustness to process variations. Fig. 5.27 shows
the performance comparison with selected reported mm-wave silicon PAs. It can be
observed that while the SiGe HBT Class-E power ampliers can generate> 20 dBm
output power at millimeter-waves, they are still far-short of the Watt-level output
power required from millimeter-wave front-ends. To generate higher output power
from SiGe HBT PAs, without power combining, a transistor stacking technique is
proposed and discussed in the next chapter.
68
Chapter 3
Mm-Wave Stacked Switching Power Ampliers
In the previous chapter, the performance limits of SiGe HBT Class-E power am-
pliers were discussed for millimeter-wave operations. Since both load impedance
transformation and large scale power-combining are lossy at millimeter-waves, the
performance limit of Class-E ampliers is set, to a large degree, by the device
breakdown voltage, BV
CBO
of SiGe HBTs available in scaled SiGe processes. This
however limits ecient output power generation from non power combined switch-
ing PA designs to 20 dBm for BV
CBO
= 5.9 V [50].
3.1 Stacked Class-E Power Ampliers
Similar to passive power combining and impedance transformation, series stacking
of transistors enables a larger overall voltage swing across the load [54]. In recent
years, transistor stacking in CMOS mm-wave power ampliers have been reported
for both linear [55{57] and switching power ampliers [35, 58]. The principle of
69
transistor stacking can also be applied to realize SiGe HBT stacked Class-E power
ampliers [41]. Stacked SiGe HBT mm-wave Class-E power ampliers benet from
maintaining the \beyond BV
CEO
" switching Class-E operation across each of the
series stacked transistors while the overall allowable voltage swing additively scales
up. Thus, compared to a non-stacked SiGe HBT with maximum voltage swing of
BV
CBO
= 5.9 V, a stacked Class-E design with 2 series-stacked device can sustain
collector voltage swing > 10 V and generate P
out
> 23 dBm
1
. In this section,
the application of transistor stacking in the context of mm-wave Class-E power
amplier design is discussed.
3.1.1 Operation of Stacked Transistors in Switching PAs
The operation of transistor stacking in millimeter-wave stacked Class-E PAs can
be explained by considering the simplied case of a double-stacked Class-E power
amplier comprising of two series stacked SiGe HBTs operating as switches as
shown in Fig. 3.1(a). In a double-stacked Class-E amplier, the series HBTs,
Q
1
and Q
2
, are designed to turn ON and OFF simultaneously. This ensures that
the voltage swing across the transistors add up in phase leading to larger overall
output voltage swing and power delivered to a xed load. Ideally, the dynamic
voltage swing must be equally divided amongst all the series stacked HBTs to
1
Ideally, doubling the voltage swing should increase the output power by 6 dB. However in
mm-wave stacked designs, the collector voltage swing cannot be equally divided between the top
and bottom transistor resulting in non-optimal improvement in output power by stacking. This
point is elaborated upon later.
70
Figure 3.1: Double-stacked Class-E SiGe HBT amplier, (a) Simplied schematic,
(b) Equivalent model when HBTs are ON, (c) Equivalent model when HBTs are
OFF.
avoid stressing any single HBT. When the switching HBTs are ON (Fig. 3.1(b)),
the ratio of the device ON resistances, r
ON1
=r
ON2
, determines the voltage division
across the devices. In the OFF state (Fig. 3.1(c)), a capacitive ladder network
comprising of C
11
and C
12
is used for voltage division in the intermediate node.
In a mm-wave Class-E design, the bottom capacitor of the ladder network, C
11
, is
realized mostly by the intrinsic collector to bulk o-state capacitance ofQ
1
,C
OFF1
,
while the capacitor C
12
is realized by an additional explicit capacitor. The base
terminal of Q
2
is terminated with the capacitance C
B
whose value depends on the
base-emitter capacitance C
BE2
of the stacked transistor Q
2
[59]. The C
BE2
C
B
capacitive divider ensures (1) the base terminal of Q
2
swings up along with its
collector in the dynamic operation; thus, preventing Q
2
collector-base junction
breakdown, and (2) the base-emitter voltage of Q
2
, V
BE2
, swings up and down in
phase with the input signal applied to the base of the driving transistor, Q
1
; thus,
ensuring synchronous switching of the stacked devices.
71
Figure 3.2: (a) Equivalent circuit model for the OFF-mode operation, (b) Collector
voltage waveforms of a double-stacked Class-E SiGe HBT amplier.
It must be noted that the stacked Class-E switching amplier presented here
is dierent from the well known cascode Class-E power amplier [60]. In cascode
Class-E ampliers, the top transistor does not switch synchronously with the bot-
tom device and the base voltage of the top stacked device remains constant during
dynamic operation. As such the cascode device only introduces a constant oset
and shares most of the voltage swing during the OFF phase. To allow larger overall
voltage swing, the base voltage of the top device has to be increased which puts
limitation on the minimum collector voltage of the bottom device during the ON
cycle. In a SiGe HBT cascode implementation, the collector voltage of the bottom
device during the ON cycle can only reduce by one V
BE
0.9 V from the top
transistor quiescent base voltage thus resulting in higher dissipation loss compared
to stacked switching designs.
In this chapter, the analysis and performance limits of mm-wave stacked Class-
E operation is conducted on a double-stacked architecture with two series stacked
72
transistors. The same operating principle holds for higher stacked switching PAs as
well. However, transistor stacking while ostensibly allowing higher voltage swing in
scaled silicon technologies, also has its limitations which will be discussed as well.
3.1.2 Performance Limit of mm-Wave Stacked Class-E PAs
Previously, the output power from a non-stacked Class-E power amplier was for-
mulated based on the breakdown voltage BV
CBO
and the load impedance R
Load
.
For a properly designed stacked Class-E amplier with equal voltage division across
each series connected transistor, the maximum allowable voltage swing in theory
can scale linearly with the number of stacked transistors. Thus, a simplied anal-
ysis of a double-stacked Class-E amplier design predicts a 6 dB increase in P
out
,
corresponding to twice the voltage swing across the load, for the same maximum
collector eciency than that of a non-stacked Class-E amplier. However, mm-
wave stacked amplier designs fail to reach this output power due to less than
equal swing of the bottom device Q
1
compared to the top device Q
2
. The base
capacitance,C
B
, designed to ensure synchronous switching ofQ
2
, loads the middle
node V
mid
, resulting in lower voltage swing across the bottom device, and hence,
a lower overall voltage swing across the load (Fig. 3.2(b)). The OFF-mode volt-
age swing across each of the series stacked HBTs in the double-stacked Class-E
amplier can be analyzed using the capacitor divider model shown in Fig. 3.2(a).
In order to fully exploit the stacking of SiGe HBTs in mm-wave PAs, the voltage
73
swing acrossQ
2
is still maintained to be as high asBV
CBO
while the voltage swing
across Q
1
becomes a fraction of the overall voltage swing, V
C
, given by
V
mid
=
C
12
(C
2
+C
B
) +C
BE2
(C
12
+C
2
)
(C
11
+C
12
+C
BE2
)(C
2
+C
B
+C
BE2
)C
2
BE2
V
C
: (3.1)
The mid-node voltage swing,V
mid
, thus depends upon both the device sizing as well
as the base-capacitor, C
B
, unlike in a simplied switch model, where it is always
half the overall voltage swing. The total o-state capacitance in the collector node
(in Fig. 3.2) can be determined to be
C
OFF
=C
CB2
+
C
12
+C
B
jjC
BE2
C
11
+C
12
+C
B
jjC
BE2
: (3.2)
To ensure C
OFF
satises the Class-E capacitance budget for a given R
Load
at mm-
wave frequencies, certain assumptions are made to simplify the stacked Class-E
analysis. Assuming the extrinsic capacitorC
12
is chosen to be the same asC
OFF1
=
C
11
, neglecting C
2
, and choosing C
B
= C
BE2
to ensure the base voltage of Q
2
swings half that of V
mid
, the above equation can be simplied to V
mid
=
V
C
2
1
1+
C
B
4C
12
.
74
The output power and collector eciency (only considering the HBT conduction
loss) of the double-stacked mm-wave Class-E SiGe HBT amplier can then be
derived as
8
>
>
>
>
>
<
>
>
>
>
>
:
P
DoubleStackedClassE
out
= (
1
1
)
2
P
ClassE
out
= 4[
1
1+
C
B
4C
12
1+
C
B
4C
12
]
2
P
ClassE
out
;

DoubleStackedClassE
max
=
1
1+2
SwitchLoss
!out
;
(3.3)
where
=
V
mid
V
C
, and
out
and
SwitchLoss
= 4.6 are technology constants introduced
in Chapter 2 and tabulated in Table 2.1. Equation 3.3 shows that in a double-
stacked Class-E amplier (1) due to parasitics, the output power does not scale up
by 6 dB, and (2) collector eciency degrades at twice the rate as the non-stacked
design with frequency. The latter is caused by the inability to directly scale up the
HBT sizes in a stacked design (to maintain the same conduction loss) due to the
collector-to-bulk capacitance (C
CB2
) of the top HBT. As the supply voltageV
CC
is
scaled up in the stacked design, the Class-E peak current of I
DoubleStackedClassE
SW
Max
also increases, expressed in terms of the non-stacked Class-E switch current as,
I
DoubleStackedClassE
SW
Max
=
1
1
I
ClassE
SW
Max
. A larger input voltage swing, and hence
input power, is thus required to supply the stacked Class-E peak current. The
input power, power gain, and maximum achievable PAE of the double-stacked
75
Figure 3.3: Maximum achievable output power, power gain, collector eciency, and
PAE versus frequency in a 130nm SiGe HBT double-stacked Class-E amplier with
ideal lossless passives.
HBT amplier (in an analysis carried out similar to that in Chapter 2) is then be
given by
8
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
:
P
DoubleStackedCLassE
in
=
1
2
(!
in
)K
C
V
2
T
R
Load
[ln(BV
CBO
) +ln(!) +ln(
K
ClassE
C
1
=m
2
(1
)I
DC;Q
=m
2
)]
2
;
G
DoubleStackedClassE
P;max
= [
1
!
][
BV
2
CBO
(1
)
2
1

in

][

2
K
C
V
2
T
][ln(BV
CBO
) +ln(!) +ln(
K
ClassE
C
1
=m
2
(1
)I
DC;Q
=m
2
)]
2
;
PAE
DoubleStackedClassE
max
= (1
1
G
DoubleStackedClassE
P;max
)
DoubleStackedClassE
max
:
(3.4)
In Eqn. 3.4, the constants 0:453,V
T
= 0.025 V,K
C
0:6765, andK
ClassE

1:484 are constants that were introduced in Chapter 2 and remaining terms are
technology parameters (BV
CBO
, ,
in
,
o
ut, C
1
=m
2
,I
DC;Q
=m
2
) shown in Table
2.1.
Fig. 3.3 shows the analytical and simulated values for P
out;max
, G
P;max
,
max
,
and PAE
max
versus frequency in a double-stacked Class-E amplier realized in
76
a 130 nm SiGe HBT process. In a mm-wave double-stacked Class-E amplier,
the improvement in output power comes at the cost of lower collector eciency.
Assuming ideal passives, the maximum output power P
out;max
in a double-stacked
Class-E at 45 GHz increases inversely with the load resistance R
load
for the same
maximum
max
and PAE
max
as shown in Fig. 3.4. In a practical implementation
however, with passive quality factor 20 at mm-waves, any R
load
< 25 result in
signicant additional loss in the output matching and input matching networks.
Moreover, the larger HBTs that need to be chosen for supporting higher Class-E
peak currents for R
load
< 25, can suer from bad reverse isolation due to large
C

capacitors [41]. The theoretical formulation of the eect of nite quality factor
passive components on the overall double-stacked Class-E amplier performance at
mm-wave frequencies can be modeled similarly as shown for non-stacked Class-E
ampliers in Chapter 2 and is not repeated here.
Eect of nite quality passive components (Q
ind
= 25, Q
cap
= 15 at 45 GHz)
on the maximum achievablePAE
max
for dierent power levels in a double-stacked
Class-E PA is shown in Fig. 3.5. It can be observed that the maximum PAE is
obtained forP
out
22 dBm corresponding toR
Load
= 50
with performance drop-
ping on either side due to passive matching loss. Another interesting observation
from Fig. 3.5 is that, on including passive loss, the PAE of double-stacked Class-E
ampliers will be better compared with what can be achieved from conventional
non-stacked Class-E ampliers for the same total P
out
beyond > 21 dBm. This is
77
Figure 3.4: Maximum achievable output power, power gain, collector eciency, and
PAE versus the load resistance for a 45 GHz, 130nm SiGe HBT, double-stacked,
Class-E amplier (lossless passives).
Figure 3.5: Theoretical maximum achievable PAE versus output power for a
45 GHz, 130nm SiGe HBT Class-E and double-stacked, Class-E amplier (with
Q
Passive
= 20), with dotted line showing output power level beyond which stacked
architecture results in higher PAE.
also validated in practical implementations, as shown later, by comparing the per-
formance of a stacked design versus using on-chip power combining of non-stacked
ampliers for the same P
out
[36] [51].
Stacked Class-E amplier analysis can also be extended for the triple-stacked
Class-E design (Fig. 3.6). For the capacitive divider network shown in Fig. 3.7, the
78
Figure 3.6: Triple-stacked Class-E SiGe HBT amplier, (a) Simplied schematic,
(b) Equivalent model with HBTs are ON, (c) Equivalent model with HBTs are
OFF.
various mid-node voltages can be expressed in terms of the overall collector voltage
swing V
C
given by,
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
V
mid1
=
1
V
mid2
;
1
=
C
12
(C
2
+C
B1
)+C
BE2
(C
12
+C
2
)
(C
11
+C
12
+C
BE2
)(C
2
+C
B1
+C
BE2
)C
2
BE2
;
V
B2
=
2
V
mid2
;
2
=
C
12
(C
2
+C
BE2
)+C
2
(C
11
+C
BE2
)
(C
11
+C
12
+C
BE2
)(C
2
+C
B1
+C
BE2
)C
2
BE2
;
V
mid2
=
3
V
C
;
3
=
C
13
(C
3
+C
B2
)+C
BE3
(C
13
+C
3
)
(C
3
+C
B2
+C
BE3
)(C
13
+C
OFF2
+C
12
(1
1
)+C
2
(1
2
)+C
BE3
)C
2
BE3
:
(3.5)
As more transistors are stacked in series, various design constraints especially at
mm-wave frequencies must be accounted for. Firstly, as more transistors are stacked
to increase the output power, each of the series stacked transistor size must also be
increased, to ensure the ON resistance of the overall stacked network does not lead
to higher conduction loss. However, the parasitic collector-bulk capacitances of the
top devices, Q
2
and Q
3
, does not come in series with the extrinsic capacitors C
12
and C
13
and leads to exceeding the overall Class-E capacitance budget (C
1
) at a
79
given frequency of operation [41]. It can be shown, that in presence of the parasitic
bulk capacitances (C
CB2
, C
CB3
), the collector-base capacitance (C
2
, C
3
) and the
extrinsic base capacitors (C
B1
, C
B2
), the equivalent parallel capacitance from the
collector to bulk (C
OFF TripleStacked
) in a triple stacked device is given by
C
OFF;TripleStacked
= (1
3
)C
13
+ (1
2

3
)C
3
+C
OFF3
; (3.6)
where
2
and
3
are dened before. To ensure non-overlapping voltage and cur-
rent waveforms in a triple-stacked Class-E design, the following assumptions are
made regarding the stacked HBT transistor sizes and extrinsic capacitors. The
extrinsic capacitors C
12
, C
13
are chosen to be the same as C
OFF1
= C
11
= C
OFF2
and the stacked HBTs (Q
2
and Q
3
) are chosen to be the same size as Q
1
i.e.,
C
CB2
= C
CB3
= C
11
. To simplify the performance expressions for the triple-
stacked architecture, C
2
, C
3
may be neglected and C
B1
= C
B2
= C
BE1
= C
BE2
= C
B
is chosen to ensure the base voltages of Q
2
and Q
3
swing half that of V
mid1
and V
mid2
respectively, thus ensuring proper switching of the stacked HBTs. With
these assumptions, the above equations can be simplied to V
mid1
=
V
mid2
2
1
1+
C
B
4C
12
and V
mid2
=
V
C
2
1+
C
B
4C
12
1:25+2:5
C
B
4C
12
+(
C
B
4C
12
)
2
. The output power and collector eciency (only
80
Figure 3.7: (a) Equivalent circuit model for the OFF-mode operation, (b) Collector
voltage waveforms of a triple-stacked Class-E SiGe HBT amplier.
considering the HBT conduction loss) of the triple-stacked mm-wave Class-E SiGe
HBT amplier can then be derived as
8
>
>
>
<
>
>
>
:
P
TripleStackedClassE
out
= (
1
1
3
)
2
P
ClassE
out
;

TripleStackedClassE
max
=
1
1+3
SwitchLoss
!out
;
(3.7)
The input power, power gain and the maximum achievable PAE of the triple-
stacked Class-E design can be obtained by replacing
with
3
in Eqn. 3.4. In
principle, as shown above, the aforementioned stacking of Class-E ampliers at
mm-wave frequencies can be extended to more than two series-stacked devices.
However, the potential increase in output power in a higher stacked designs comes
at the cost of lower collector eciency. Even the scaling in output power is aected
by the mm-wave design constraints. At mm-waves, as shown in Eqn. (3.5), the
loading of intermediate nodes by the base capacitors, C
B1
and C
B2
, allows the
lower transistors to only swing a fraction of the maximum BV
CBO
voltage. The
81
Figure 3.8: Lumped modeling of layout parasitics in a 2 (16m-12m) stacked
SiGe HBT.
incremental gain in the overall voltage swing and hence output power, becomes
smaller and smaller as we stack more and more transistors. As shown in Eqn.
(3.7), to ensure the increased overall voltage swing in the triple-stacked design,
requires a higher overall current swing resulting in the need for a stronger driver
amplier than that needed to drive a double-stacked design. Mere stacking of more
transistors, without proper capacitive divider networks, HBT sizing and driving
amplier design does not necessarily result in higher output power [61].
3.1.3 Q-band Stacked PA Implementations
To demonstrate transistor stacking in mm-wave SiGe HBT switching PAs, proof-of-
concept double-stacked and triple-stacked Class-E power ampliers were fabricated
in the 130nm SiGe BiCMOS process for Q-band (30-50 GHz) operation. Since
82
Figure 3.9: Double-stacked Q-band Class-E amplier: (a) schematic, (b) chip mi-
crophotograph.
stacked transistor layouts can be more susceptible to layout parasitics at millimeter-
wave frequencies, extensive electro-magnetic simulation have been undertaken for
accurate modeling (Fig. 3.8). Individual design steps highlighting the performance
variation from an ideal switch-based model to the actual implemented design have
been shown in Fig. 3.11. Detailed design and layout principles concerning each of
the individual designs are available in [36,41,61].
83
Figure 3.10: Simulated transient waveforms of the 45 GHz double-stacked SiGe
HBT Class-E amplier. Note that the currents correspond to the summation of
transistor and its collector capacitance currents.
Q-band Double-Stacked SiGe Class-E Amplier
To validate the mm-wave Stacked Class-E concept where each of the series stacked
SiGe HBTs are operating in beyond BV
CEO
mode, a two-stage double-stacked Q-
band Class-E power amplier is fabricated [36] (Fig. 3.9). The simulated transient
waveforms are shown in Fig. 3.10. Design steps of the stacked Class-E PA, shown
in Fig. 3.11, highlight the performance degradation due to addition of various
circuit non-idealities. Large signal measurements for the Class-E operating points
of V
CCCore
= 4.5 V, V
BaseLower
= 0.75 V, and V
BaseUpper
= 2.7 V are shown in
Fig. 3.12. Measured peak PAE of 34.9% at 23.4 dBm output power and a P
1dB
bandwidth of at least 5 GHz within the 39 - 47 GHz clearly shows the advantage of a
proper stacked design in comparison with conventional Wilkinson power combining
approach [51].
84
Figure 3.11: Design steps for the double-stacked Q-band Class-E amplier, (a)
HBTs are modeled with a switch, (b) collector-bulk capacitance of HBTs are in-
cluded,C
CB1
is absorbed inC
11
, (c) switches are replace with SiGe HBTs, (d) SiGe
HBT layout parasitics are included, (e) the nite quality of passives (Q
ind
= 25,
Q
cap
= 20) are included, (f) including loss in the input matching network.
Figure 3.12: Large-signal performance of the implemented Q-band double-stacked
Class-E amplier.
85
Figure 3.13: Triple-stacked Q-band Class-E amplier schematic and chip micropho-
tograph.
Figure 3.14: Simulated transient waveforms of the 45 GHz triple-stacked SiGe HBT
Class-E amplier. Note that the currents correspond to the summation of transistor
and its collector capacitance currents.
86
Figure 3.15: Design steps of the triple-stacked Q-band Class-E amplier, (a) with
real HBTs and ideal passives , (b) SiGe HBT layout parasitics are included, (c) the
nite quality of passives (Q
ind
= 25, Q
cap
= 20) are included, (d) including loss in
the input matching network, (e) performance including driver amplier.
Q-band Triple-Stacked SiGe Class-E Amplier
To extend the stacking of Class-E PA to more than two series stacked HBTs, a
triple-stacked Class-E amplier design was attempted [61] (Fig. 3.13). The simu-
lated transient waveforms are shown in Fig. 3.14. Device parasitics as well as mm-
wave design limitations cause unequal voltage division across the series stacked SiGe
HBTs, resulting in an lower overall voltage swing, output power, and eciency in
this design compared to the double-stacked Class-E implemented previously. The
87
design steps for the triple-stacked design are shown in Fig. 3.15. Large signal mea-
surements for the Class-E operating points of V
CCCore
= 6.5 V with V
BaseLower
= 0.75 V, and V
BaseUpper
= 5 V are shown in Fig. 3.16.
In this triple-stacked implementation, Eqn. (3.7) predicts only 2 dB improve-
ment in saturated output power (as opposed to an ideal scaling of 9.5 dB) compared
to a non-stacked Class-E design which was validated in both simulation and mea-
surement. This was primarily due to a sub-optimal triple-stacked design as the
theoretical expressions showing the eect of base capacitors on the overall output
performance had not been derived at the time of implementation. Also, the HBT
transistors were not properly sized to reduce the eect of collect-to-bulk capacitor
of the top devicesQ
2
andQ
3
. In addition, the same driver designed for the double-
stacked Class-E was used to drive the triple-stacked design, resulting in sub-optimal
performance.
To achieve improved performance in terms of output power and eciency in a
triple-stacked mm-wave SiGe HBT Class-E architecture, a re-optimized design was
undertaken and improved output power while maintaining high PAE was observed
in the simulation (Fig. 3.17). Several design techniques were used in the redesign.
Firstly, the stacked HBTs are properly sized with larger bottom device Q
1
for
lower ON resistance and smaller top devices Q
2
and Q
3
for mitigating the eect
of collector bulk capacitors C
CB2
and C
CB2
. Secondly, the extrinsic capacitors
C
12
andC
13
in the capacitor divider network are now realized entirely by the HBT
88
Figure 3.16: Large-signal performance of the implemented Q-band triple-stacked
Class-E amplier.
layout metal-oxide-metal parasitic capacitances. This helps in reducing the eect of
interconnect inductances in connecting the extrinsic MIM capacitors. Also, such a
layout allows shielding the intermediate collectors ofQ
2
andQ
3
from the substrate,
further reducing voltage-current overlap. Finally, to drive the triple-stacked Class-
E into proper saturation, a stronger driver amplier was implemented. The re-
optimized triple stacked Class-E shows a simulated output power of 24.8 dBm at
24% PAE at 45 GHz, further improving the power that can be generated from a
single unit amplier at mm-waves.
The performance summary of the implemented SiGe HBT stacked Class-E am-
pliers have been shown in Table. 3.1 across dierent measured chips. The mea-
surements demonstrate ecient generation of> 23 dBm output power at mm-waves
89
Figure 3.17: Redesigned triple-stacked Class-E amplier: (a) Schematic, (b) Simu-
lated performance at 45 GHz.
Table 3.1: Measured Performance Summary of the Fabricated stacked Q-band SiGe
HBT Ampliers.
90
with high eciency is achievable from stacked switching power amplier architec-
tures.
In the next section, the application of stacked switching PAs for the higher
W-band (75-110 GHz) frequencies, the associated challenges, and solutions are
discussed.
3.2 Transistor Stacking for W-band PAs
In recent years, the W-band frequency spectrum (75-110 GHz) has been extensively
used to support multi-Gb/s data rates for wireless cellular back-haul (71 - 76 GHz,
81 - 86 GHz), millimeter-wave imaging (90 GHz), and automotive radars (77 GHz).
To maintain high SNR (signal-to-noise ratio) for high data-rates over mm-wave
wireless channels of link-length 1 Km, with high atmospheric attenuation, it
can be shown that each transmitter in a 128-element large-scale phased-array must
radiate > 22 dBm output power levels (Fig. 3.18). Silicon W-band transmitters
implemented in scaled CMOS SOI or bulk SiGe BiCMOS processes are limited to
< 50 mW output power generation [62] [63]. On-chip [64{69] or spatial [62] power
combining has been used to increase the total output power, but at the cost of
larger area or lower eciency. Similar to Q-band implementations of Section 3.1,
series connection of transistors in a stacked approach, along with proper passive
components, can enable higher voltage swing and higher output power at W-band
frequencies [70]. However, layout approaches for lower Q-band implementations,
91
Figure 3.18: Phased-array W-band transceiver architecture.
Figure 3.19: Transistor stacking at W-band, (a) 2-stacked Class-E schematic, (b)
Class-E simulated voltage-current density contour at 90 GHz.
in which the transistors and the necessary passive components are treated sepa-
rately will signicantly aect performance for the higher W-band designs where
the interconnects are as signicant as transistors or passive components [71]. The
eect of various transistor and layout non-idealities on W-band stacked switching
PA performance is discussed in this section.
92
3.2.1 Eect of Series Switches
A 90nm SiGe BiCMOS process (Table. 2.1) with f
T
, f
max
= 300/350 GHz and
BVCEO/BVCBO = 1.5/5.3 V is chosen for the W-band stacked switching PA
implementations. Stacked switching power ampliers using SiGe HBTs however
addresses two key limitations for W-band PA design in this 90nm SiGe process.
Firstly, when used in a Class-E switching amplier conguration, the non-overlapping
collector voltage-current contour of the SiGe HBTs allow the transistors to operate
at a much higher BVCBO = 5.3 V while simultaneously achieving high collector
eciency [41]. Using the technology HBT transistors as a gain-compressed switch,
however results in only 2-3 dB large signal power gain in the W-band frequency
range, signicantly increasing the input power requirement and degrading PAE. Se-
ries stacking of SiGe HBTs mitigates this problem by increasing the voltage swing
and power generation capability while simultaneously increasing the power gain at
W-band frequencies.
In the stacked transistor conguration (Fig. 3.19(a)) the native transistors are
connected in series with appropriately chosen capacitors values C
OUT
and C
B2
.
During large signal switching mode operation, the intrinsic HBT parasitics in con-
junction with the added capacitors ensure that each transistor operate within the
5.3 V BVCBO breakdown limit while resulting in an increase of the overall break-
down voltage of the stacked transistor conguration (Fig. 3.19(b)) . The increased
93
Figure 3.20: (a) Simplied model of a double-stacked Class-E amplier, (b) Theo-
retical eect of r
ON
on collector eciency () in a 90nm SiGe HBT technology.
output power in stacked Class-E designs comes at the cost of reduced collector ef-
ciency. In a stacked Class-E design, when multiple switches are placed in series,
the switch ON resistances add up leading to higher conduction loss.
In a generalized `N' series stacked power amplier conguration, assuming equally
sized series transistors, the Eqn. 3.3 for collector eciency () can be generalized
for N-stacked Class-E conguration as

NStackedClassE
max

1
1 + 4:6N!
out
; (3.8)
where ! is the operational frequency in radians,
out
= R
ON
C
OFF
is the HBT
output time constant ( = 0.1 ps for the 90nm SiGe process) of Table. 2.1. At
the higher W-band frequencies this leads to low eciency from stacked switching
PAs. For a 2-stacked design, assuming ideal passives for all the input and output
94
Figure 3.21: (a) Simplied model of a double-stacked Class-E amplier with para-
sitic layout capacitor C
P
, (b) Theoretical eect of C
P
on collector eciency ().
matching networks, Fig. 3.20(b) shows the theoretical collector eciency degrades
to 65% at 90 GHz from the ideal theoretical 100% value.
3.2.2 Eect of Parasitic Layout Capacitors
Metal interconnection of large power transistors in a stacked conguration can
result in signicant layout parasitic capacitors at mm-waves. As shown in the Fig.
3.21(a), when the two discrete HBTs Q
1
and Q
2
are connected in series the layout
capacitors C
P1
and C
P2
result at each HBT collector terminal. These parasitic
capacitors subtract from the overall Class-E shunt capacitance budget C
OFF
and
limits the size of SiGe HBTs that can be chosen leading to higher conduction loss
and lower collector eciency.
95
Figure 3.22: (a) Simplied model of a double-stacked Class-E amplier with output
network capacitor C
OUT
, (b) Theoretical eect of C
OUT
quality factor on collector
eciency ().
The eect of layout parasitic capacitors from each collector node on the overall
collector eciency can be predicted by augmenting Eqn. 3.8 as,

NStackedClassE
max

1
1 + 4:6!
out
N (1 +
C
P
C
OFF
)
; (3.9)
where for simplicity,C
OFF;K :K2(1;N)
=C
OFF
andC
P;K :K2(1;N)
=C
P
are assumed.
As the transistor output capacitance, C
OFF
, that needs to be chosen for W-band
switching PA implementations becomes smaller at the higher mm-wave frequencies
[41], the layout parasitic capacitors C
P
becomes a more signicant proportion of
the smaller device o-capacitanceC
OFF
and leads to signicant additional eciency
degradation in the stacked PA conguration as shown in Fig. 3.21(b).
96
3.2.3 Eect of MIM Capacitor Q-factor
In a stacked switching amplier architecture, an output capacitor divider network
is used to ensure the overall collector voltage swing can be equally divided between
the top and bottom transistors. At lower mm-wave frequencies C
OUT
(Fig. 3.22)
can be implemented using discrete metal-insulator-metal (MIM) capacitors for area
reduction. At W-band frequencies however, the low Q-factor of the MIM capacitors
Q
Cap
5-7 reduces the eciency as quantied by

NStackedClassE
max

1
1 + 4:6!
out
N (1 +
C
P
C
OFF
) +
1:87
Q
Cap
: (3.10)
Fig. 3.22(b), shows the eciency degradation in a 2-stacked Class-E amplier when
C
OUT
is realized using MIM capacitors in the 90nm SiGe process.
3.2.4 Eect of Parasitic Collector Inductance
Parasitic lead inductance L
P
at each transistor collector node as shown in Fig.
3.23(a), arising primarily from the via inductance for connecting the dierent layers
of the metal stack also lead to performance degradation. At mm-wave frequencies,
this layout parasitic inductanceL
P
can become a signicant portion of the collector
inductance L
1
. The parasitic inductance L
P
reduces the output power generation
in stacked switching PAs, since the voltage swing across the L
P
subtracts from the
97
Figure 3.23: (a) Simplied model of double-stacked Class-E amplier with parasitic
collector inductance L
P
, (b) Theoretical eect of L
P
on stacked PA output power.
overall collector voltage swing. The output power, P
out
, reduces both with number
of stacked transistors (N) as well as the
L
P
L
1
ratio given by
P
NStackedClassE
out;L
Par:
=
P
out
(1 +N
L
P
L
1
)
2
: (3.11)
The values of both L
1
and shunt Class-E capacitance C
OFF
scale down with fre-
quency. But as less number of parallel HBTs are now used to realize smaller values
ofC
OFF
, the parasitic lead inductanceL
P
scales up with frequency. Thus
L
P
L
1
/!
2
where ! is frequency of operation in radians. This increasing
L
P
L
1
ratio with fre-
quency degrades output power by more than 1 dB at 90 GHz in the 90nm SiGe
process (Fig. 3.23(b)).
98
The signicant performance degradation at W-band frequencies from layout
parasitics in stacked PA congurations, necessitates the synthesis of multi-port
composite transistor topologies that can eliminate or incorporate the layout par-
asitics into the mm-wave PA design network and result in improved overall PA
performance.
3.3 Multi-Port Stacked Transistor Topologies
Low frequency transistor stacking techniques like discrete layout of stacked HBTs
and MIM capacitor implementations of capacitive dividers can degrade switching
PA performance signicantly at W-band frequencies as summarized in Fig. 3.24(a).
To mitigate the deleterious eect of layout parasitics and lossy on-chip passives, a
composite multi-port transistor topology for realizing high breakdown, high f
max
stacked HBTs is proposed in this section. The objective of this layout technique
conceptualized in Fig. 3.24(b) is to shield the sensitive intermediate collector nodes
from the harmful layout parasitic capacitance and inductance while realizing the
desired network capacitors C
OUT
and C
B2
from the layout interconnects.
3.3.1 8 V Breakdown, 290 GHz f
max
Composite Transistor
To enable stacked switching power amplier designs at W-band (75-110 GHz) a
composite multi-port 2-stacked transistor layout is built up as shown in Fig. 3.25.
In Fig. 3.25(a) two native SiGe HBTsQ
1
andQ
2
available in the technology library
99
Figure 3.24: (a) Parasitics associated with discrete transistor stacking at mm-
wave frequencies, (b) Conceptual integrated multi-port high-breakdown, high-f
max
transistors.
are placed in series and their collector connections are made in `M2-4B' and `OL'
metal layers respectively. But, this layout connection leads to generation of the
parasitic layout capacitors C
C1
and C
C2
from the transistor nodes as shown in
the Fig. 3.25(a) schematic which will degrade the collector eciency. To shield
the collector of the top transistor Q
2
from ground, the collector connection of Q
1
can be extended as shown in Fig. 3.25(b). This step eliminates C
C2
and is also
used to synthesize the capacitor C
OUT
entirely from the overlap of the Q
1
and Q
2
collector interconnects. This output capacitor C
OUT
enables equitable distribution
of collector voltage across series transistorsQ
1
-Q
2
and its realization from the `OL'
and `M2-4B' metal overlap achieves a metal-oxide-metal (MOM) capacitor having
comparatively high Q-factor of 25 at W-band frequencies. Extending Q
1
collector
connection, shields the collector of Q
2
; but, an additional parasitic capacitor to
100
ground C
C1
0 from the Q
1
collector terminal is created as shown in Fig. 3.25(b).
This parasitic capacitor also degrades the Q
1
collector eciency. In the nal step
shown in Fig. 3.25(c), the base terminal connection ofQ
2
using the metal layer `M1-
2B' can now be used to shield theQ
1
collector terminal. The `M1-2B' base terminal
connection is also used to realize theQ
2
base terminal capacitorC
B2
which ensures
that Q
2
switches synchronously with Q
1
. Since the relative separation between
`M1-2B' and the `M1-M4' ground layer is small, this arrangement is ideal to realize
high-Q relatively largeC
B2
values in small form factor. Two parasitic base-emitter
capacitors C
BE1
and C
BE2
are generated in this composite 2-stacked HBT layout
strategy. However since these parasitic base-emitter capacitors come in parallel
to large intrinsic HBT base-emitter capacitors, they do not degrade W-band PA
performance.
The complete 2-stacked multi-port transistor topology is shown in Fig. 3.25(c).
The main innovation in this layout conguration over the traditional lower fre-
quency transistor stacking lies in the layout of two SiGe HBT native transistors
in collector-base-emitter-base-collector (CBEBC) conguration with appropriate
metal layers chosen for the collector, emitter and base terminals which synthesizes
all the desired capacitors (C
OUT
,C
B2
) from the layout parasitics while at the same
time shielding the sensitive intermediate nodes (collectors of Q
1
and Q
2
) from any
parasitic addition. The close spacing of the Q
1
and Q
2
collector connection also
101
Figure 3.25: Composite 2-stacked multi-port SiGe HBT Layout, (a) collector con-
nections of series HBTs Q
1
-Q
2
, (b) Q
2
collector shielding and C
OUT
synthesis, (c)
Q
1
collector shielding and C
B2
synthesis along with equivalent 8 V transistor sym-
bol.
102
ensures that collector lead inductance is minimized. This composite transistor lay-
out can be simplied into a 3-terminal equivalent transistor (with an additional DC
bias node) with 8 V equivalent breakdown voltage.
A Class-E power amplier architecture (described in detail in Section 3.3.1)
using several such `2-stacked composite multi-port HBTs' in parallel can be designed
and the simulated voltage-current contour of such composite transistors shown in
Fig. 3.25(c) shows that the collector voltage in such composite transistors can swing
as high as 8V even at W-band frequencies. The layout parasitic modeled peak small-
signalf
max
= 290 GHz of this composite transistor (Fig. 3.28) is determined to be
marginally lower than the 320 GHz f
max
of a parasitic modeled native SiGe HBT.
3.3.2 11 V Breakdown, 260 GHzf
max
Composite Transistor
The same approach can be extended to include more series stacked HBTs resulting
in a composite transistor with even higher breakdown voltage. Fig. 3.26 shows a
3-stacked composite transistor with 11 V breakdown voltage. Similar to the `two-
stacked composite multi-port HBT' layout, the development of the `three-stacked
composite multi-port HBTs' can be shown in several steps of Fig. 3.26(a)-(c). In
the `2-stacked composite multi-port HBT' layout of Fig. 3.26, the desired network
capacitors C
OUT1
, C
OUT2
, C
B2
and C
B3
are realized by the overlap of Q
1
, Q
2
, Q
3
base, collector and emitter metal interconnects. Like before, the sensitive collector
nodes of Q
1
, Q
2
and Q
3
are protected from any additional parasitic capacitor to
103
the grounded emitter, improving collector eciency. The only resulting parasitic
capacitances from this layout viz. C
BE1
, C
BE2
and C
BE3
are all parallel to much
larger intrinsic base-emitter device capacitors and negligibly aect the W-band
performance. As shown in Fig. 3.26(c), this composite transistor can again be
represented by an equivalent 3 terminal transistor (with 2 additional DC bias node)
but with a larger breakdown voltage of 11 V.
Multiple instances of `three-stacked composite multi-port HBTs' in parallel can
be used in the design of a W-band switcching power ampliers and the simulated
collector voltage-current contour of `three-stacked composite multi-port HBT' con-
guration in Fig. 3.26(c) show each SiGe HBT operating within safe limits while
swinging 11 V in a bulk silicon process. The layout parasitic modeled `3-stacked
composite multi-port HBT' conguration also shows a high peak small-signal f
max
of 260 GHz with the marginal degradation arising from the resistivity of the metal
interconnects (Fig. 3.28(a)).
3.3.3 W-Band Class-E PA Designs
From the HBT safe-area-operation shown in Fig. 3.25 and Fig. 3.26, the breakdown
voltages for the `two-stacked' and `three-stacked' topologies under Class-E operation
are 8 V and 11 V, respectively. The schematic of the Class-E design using the `two-
stacked' multi-port topology under a 25
load-line and the transient collector
voltage and current waveforms are shown in Fig. 3.27(a). Simulations predict P
out
104
Figure 3.26: Composite 3-stacked multi-port SiGe HBT Layout, (a) collector con-
nections of series HBTs Q
1
-Q
3
, (b) Q
2
and Q
3
collector shielding and C
OUT1
and
C
OUT1
synthesis, (c)Q
1
andQ
2
collector shielding andC
B2
andC
B3
synthesis along
with equivalent 8 V transistor symbol.
105
Figure 3.27: Switching PA design examples at 90 GHz, (a) 2-stacked Class-E PA
along with transient collector voltage-current waveforms, (b) 3-stacked Class-E PA
along with transient collector voltage-current waveforms
= 23.5 dBm, G
P
= 9 dB, = 55%, and PAE = 49%. The schematic of the
Class-E design using the `three-stacked' multi-port topology under a 25
load-
line and the transient collector voltage and current waveforms are shown in Fig.
3.27(b). Simulations predict P
out
= 25 dBm, G
P
= 11 dB, = 35%, and PAE
= 31%. These design examples using the multi-port stacked transistor topologies
have been implemented multi-stage stacked switching power ampliers in the 90nm
SiGe process.
106
Figure 3.28: f
max
vs. current density J
C
for non-stacked native SiGe HBTs, com-
posite 2-stacked and 3-stacked HBTs
3.3.4 W-band Stacked Switching PA Implementation
The proposed `2-stacked' and `3-stacked composite multi-port HBTs' enable high
power generation at W-band while maintaining high collector eciency by elimi-
nating the harmful layout parasitics. In addition, since these transistor topologies
enable higher collector swings of 8 V and 11 V respectively while still maintaining
a base voltage swing of 1.2 V, the proposed transistor congurations also boost
the achievable large-signal power gain at W-band improving the PAE as well. To
validate these claims, 2-stacked and 3-stacked switching PAs using the proposed
composite layout strategies have been implemented in a 90nm SiGe BiCMOS pro-
cess for W-band operation. To benchmark the performance of these stacked PAs,
a non-stacked conventional Class-E PA using native SiGe HBTs have also been
implemented in the same technology node.
107
Figure 3.29: Schematic and chip microphotograph of the 5-stage W-band non-
stacked Class-E PA.
19.5 dBm, 5-stage W-band non-stacked Class-E PA
To benchmark the 90nm SiGe process for switching PA operation at W-band fre-
quencies, a 5-stage non-stacked Class-E power amplier was designed and fabricated
using the native SiGe HBTs as shown in Fig. 3.29. The last two power stages are
designed as Class-E switching PAs and operate under large supply voltage of 2.2
V. The 1st three stages are designed as high gain Class-AB ampliers and operate
108
Figure 3.30: Large-signal measurements of 5-stage W-band non-stacked Class-E
PA.
under lower 1.8 V supply. The large signal measurements of this switching PA are
shown in Fig. 3.30. This power amplier achieved a peak output power of 19.5
dBm at 16% peak PAE at 88 GHz. The measured performance of this switching PA
will be used to benchmark the proposed stacked Class-E PA designs also fabricated
in the same process.
22 dBm, 5-stage W-band 2-stacked Class-E PA
To demonstrate the performance benets of using the proposed composite transistor
topologies, a 5-stage W-band power amplier chain was implemented with the 8 V
`2-stacked composite multi-port HBTs' congurations in the nal stage (Fig. 3.31).
The last two power stages are biased for Class-E switching operation with the initial
109
Figure 3.31: Schematic and chip microphotograph of the 5-stage W-band 2-stacked
Class-E PA.
stages operating as Class-AB/B stages for additional power gain. All the inter-
stage network capacitors and inductors have been implemented as custom-designed
metal-oxide-metal capacitors and micro-strip transmission lines respectively. Fig.
3.32 shows the measured large signal performance of the implemented W-band
power amplier chain at 85 GHz. A maximum output power of 22 dBm (160 mW)
is reported with 17 dB of large signal power gain with peak collector eciencies
110
Figure 3.32: Large-signal measurements of 5-stage W-band 2-stacked Class-E PA.
of 19.5% and peak PAE of 19% respectively. The implemented PA chain also
demonstrates wide-band performance with P
1dB
bandwidth of 12 GHz with PAE
> 16% across theP
1dB
band. The output power remains> 14 dBm across 75 GHz
- 105 GHz with upper frequency measurements limited by test-setup limitations.
23.3 dBm 6-stage W-band 3-stacked Class-E PA
The operation of the `3-stacked composite multi-port HBTs' conguration is demon-
strated by implementing a 6-stage W-band power amplier chain as shown in Fig.
3.33 with individual stage performances. The last three stages are biased in Class-E
switching amplier mode for high eciency and the initial stages as Class-AB/B
mode for high gain. The improvement of power gain by stacking transistors using
111
Figure 3.33: Schematic and chip microphotograph of the 6-stage W-band 3-stacked
Class-E PA.
the proposed technique can be seen in larger power gain of 4.5 dB and 5.3 dB in
`2-stacked composite multi-port HBTs' and `3-stacked composite multi-port HBTs'
congurations respectively, compared to the 2 dB power gain using the process SiGe
HBTs in a Class-E operation at W-band. The measured large signal performance
in Fig. 3.34 shows an even larger output power of 23.3 dBm (220 mW) with 18.7
dB power gain at 83 GHz. The peak eciency and PAE are reported as 17.5% and
17% respectively with a P
1dB
bandwidth of 7GHz with PAE > 15% across the
P
1dB
band. In both the implementations, the measurement results and simulation
112
Figure 3.34: Large-signal measurements of 6-stage W-band 3-stacked Class-E PA.
follow closely, validating the accuracy of the composite device parasitics and passive
modeling.
The performance of all the fabricated designs are tabulated in Table. 3.2. Tran-
sistor stacking improves the output power generation but unequal voltage division
amongst the stacked transistors prevents ideal scaling of the output power of the
2-stacked and 3-stacked compared to the non-stacked prototype. Compared to the
reference Class-E design, the Class-E designs with the proposed composite transis-
tors have better performance in terms of output power, power gain and power-added
eciency validating the merit of the proposed transistor topologies. Compared to
reported state-of-art silicon PAs at W-band, the proposed designs demonstrate the
widest frequency of operation, highest power generated at a single transistor node
113
Table 3.2: Measured performance summary of the stacked W-band SiGe HBT
ampliers and comparison with some state-of-art published works.
with highest reported PAE for such power levels leading to a better gure-of- merit
(FOM) compared to previously reported works. Such high power, high PAE stacked
switching power ampliers not only demonstrate of the scalability of silicon tran-
sistor stacking techniques to the higher mm-wave frequencies but also enable high
data-rate silicon transmitters with high system eciency, in the W-band mm-wave
spectrum.
114
Figure 3.35: Output power vs peak PAE of the stacked mm-wave switching PAs
with some published mm-wave silicon power ampliers.
3.4 Conclusion
In this chapter series stacking of transistors in mm-wave switching Class-E power
ampliers for Q-band and W-band operation have been discussed. Stacked switch-
ing ampliers can support large voltage swing and high output power generation
while still maintaining high Class-E eciency at mm-waves. Series stacked PA
designs are however susceptible to layout parasitics at mm-wave frequencies which
can be mitigated by the proposed multi-port composite transistor layouts. The
implemented stacked PA designs demonstrate> 22 dBm output power and will be
used as the unit power amplier modules for realizing ecient Watt-level mm-wave
transmitters to be discussed in the later sections.
115
Chapter 4
Waveform Engineering in mm-Wave Switching
Power Ampliers
Switching power ampliers can generate output power with high eciency by main-
taining non-overlapping collector voltage-current waveforms and thus minimizing
conduction loss inside the transistor. One particular example of switching ampli-
ers, the Class-E amplier has been extensively covered in the previous chapters
for ecient power generation using a SiGe HBT process in both stacked and non-
stacked congurations. However, other classes of switching ampliers [45, 72, 73]
also exist that can maintain non-overlapping of voltage and current waveforms and
potentially generate power with high eciency at mm-wave frequencies. In partic-
ular, the Class-E/F family of switching ampliers [45] is an interesting extension of
switching Class-E amplier concept with additional control over higher harmonics
for waveform shaping. While such Class-E/F family of switching ampliers has
116
Figure 4.1: Design space of switching ampliers under waveform engineering by
controlling the switching amplier collector impedance Z
C
at higher harmonics of
the fundamental frequency of operation with active or passive terminations.
been usually used for operation at lower RF frequencies, understanding its perfor-
mance merits and demerits for mm-wave operation has also become an important
area of research in recent years [74{76]. In switching ampliers, the operation of
the transistor as a non-linear switch enables generation of multiple harmonics of the
fundamental frequency. The relative amplitude and phase of these harmonic signals
compared to the fundamental frequency signal plays the critical role in achieving the
non-overlapping voltage and current waveforms required for high eciency switch-
ing power amplier operation. Conditions for non-overlapping of voltage and cur-
rent waveforms in switching ampliers are represented by two boundary conditions :
(1) \Zero Voltage Switching (ZVS)" condition which ensures that the voltage across
the switching transistor goes to zero before it starts conducting current during its
117
ON cycle thus eliminating any power dissipation in the switch through conduction
loss, and (2) \Zero Voltage Derivative Switching (ZdVS)" condition which ensures
that the 1
st
derivative of the switch voltage is also zero at the switching moment
to prevent any capacitive loss due to charge dissipation from the Class-E parallel
capacitor [46]. These ZVS and ZdVS boundary conditions are used not only for
Class-E ampliers, but also for the more generalized Class-E/F family of switch-
ing ampliers as well [45], especially at mm-wave frequencies where the transistor
parasitic capacitors need to be incorporated into the switching amplier analysis.
Interestingly, the conditions for non-overlapping of voltage and current wave-
forms does not uniquely dene the amplitude and phase requirements of the har-
monics and as such innite classes of switching ampliers are possible each satisfying
the ZVS and ZdVS boundary conditions. Even more interestingly, while traditional
switching ampliers operating at low RF frequencies have always relied on satis-
fying the ZVS and ZdVS conditions, non-ZVS and non-ZdVS switching amplier
designs are also possible. While not satisfying the power dissipation conditions may
seem counter-intuitive at rst, it will be shown in Section 4.1, that at mm-wave
frequencies, sometimes satisfying only one of ZVS or ZdVS and not both simulta-
neously can lead to better Class-E designs. Such non-zero switching conditions also
can be extended to the Class-E/F amplier classes, generalizing the already large
class of Class-E/F ampliers and widening the design space for switching amplier
design. This generalized family of Class-E/F ampliers with arbitrary boundary
118
switching conditions have been studied in Section 4.2. The space for switching am-
plier design is summarized in Fig. 4.1. As shown in Fig. 4.1, in contrast to certain
nite classes of switching ampliers like Class-E [77] and Class-F [78], the general-
ized switching ampliers constitute a continuum of classes with the traditional well
known ampliers forming sub-classes of them. The availability of higher harmonics
and non-zero boundary conditions enable shaping the collector voltage and current
waveforms according to desired PA performance and can be termed as \Waveform
Engineering" in mm-wave switching ampliers. In most cases such harmonic ampli-
tude and phase control is enabled by reactive termination and constitute \Passive
Waveform Engineering". However as shown in Fig. 4.1, active harmonic injection as
rst proposed by the Class-EM ampliers [79] [80] can also shape transistor voltage
and current waveforms for eciency improvement by \Active Waveform Engineer-
ing". The theory of active waveform engineering in switching PAs is brie
y covered
in Section 4.1, although it will be shown that for current silicon processes it may
not yet be a practical solution for mm-wave frequencies.
Finally, the concept of generalized switching ampliers can also be extended to
stacked transistor architectures. Similar to stacked Class-E ampliers, generalized
stacked Class-E/F ampliers can sustain similar non-overlapping Class-E/F wave-
forms on both the stacked transistors by capacitive coupling for eciency and power
improvement. In addition, a new class of stacked switching PAs is also proposed
which can sustain dissimilar waveforms on each of the series stacked transistors.
119
The proposed stacked switching PAs have been called the stacked Class-K ampli-
ers (the nomenclature following, the well known Class-J linear amplier) and add
to the previously discussed switching amplier design space of Fig. 4.1. Fabricated
silicon prototypes highlighting the important features of some of these generalized
mm-wave switching amplier classes are also discussed in this chapter.
4.1 Generalized Class-E Switching Power Ampliers
Traditional Class-E power amplier design [77] relies on the previously discussed
\ZVS" and \ZdVS" switching boundary conditions to achieve 100% theoretical
Class-E collector eciency by ensuring non-overlapping transistor voltage and cur-
rent waveforms. This 100% theoretical Class-E eciency assumes transistors mimic
ideal switches with zero switch ON resistances. In reality, transistors have a nite
r
ON
switch ON resistance as well as a C
OFF
collector switch OFF capacitance. At
mm-wave frequencies, the transistor C
OFF
shunt capacitance can signicantly dis-
tort the non-overlapping collector voltage-current waveforms, unless it is explicitly
included in the Class-E analysis (as carried out in Chapter 2) and incorporated in
the Class-E shunt capacitanceC
1
as shown in Fig. 4.2(a). Maximizing the Class-E
eciency at mm-waves thus requires realizing the entire shunt capacitanceC
1
with
the transistorC
OFF
so that the largest possible transistor with the smallest possible
r
ON
can be chosen to minimize the conduction loss. With increasing frequency, the
C
1
values become smaller and thus smaller transistor size needs to be chosen to
120
ensure the parasitic C
OFF
does not distort the Class-E waveforms. Given transis-
tor's nite
out
= r
ON
C
OFF
time constant in a given technology, the maximum
achievable Class-E amplier eciency thus decreases with frequency as given in
Chapter 2 and repeated here for convenience as,

max
=
1
1 +
SwitchLoss
!
out

1
1 + 4:6!
out
: (4.1)
In this approach, the Class-E ampliers are designed to satisfy the \ZVS" and
\ZdVS" switching boundary conditions, thus eliminating any conduction loss or
capacitive discharge loss from the transistor voltage-current overlap. However, this
approach does not minimize the conduction loss arising during the switch ON cycle
due to the transistor non-zero r
ON
. At mm-wave frequencies, this r
ON
loss can
be as signicant source of eciency degradation as the transistor conduction loss
and the capacitive discharge loss. Hence, a more generalized approach to maximize
collector eciency by minimizing all sources of loss is necessary in mm-wave Class-E
designs.
4.1.1 Class-E Analysis with Non-Zero Boundary Conditions
One way to maximize the collector eciency, exceeding that predicted by Eqn. 4.1
is to assume non-zero \ZVS" and \ZdVS" switching boundary conditions. Non-zero
switching boundary conditions lead to more generalized Class-E waveforms shown
in Fig. 4.2(d). Intuitively, the potential for eciency improvement in generalized
121
Figure 4.2: Class-E amplier with non-zero switching boundary conditions, (a)
Simplied schematic, (b) equivalent model with HBTs are ON, (c) equivalent model
with HBTs are OFF, (d) transient waveforms with non-zero `ZVS' and `ZdVS'
boundary conditions.
Class-E designs arises because, the \ZVS" and \ZdVS" boundary conditions in
traditional Class-E switching amplier analysis acted as the limiting factor on the
Class-E shunt capacitor C
1
value which limits the switch size C
OFF
and increase
conduction loss due to switchr
ON
. Allowing non-zero \ZVS" and \ZdVS" boundary
conditions however, allows the shunt capacitor value C
1
to be much larger for the
same frequency of operation, enabling larger transistors to be used as a switch,
lowering the r
ON
conduction loss. However, if the boundary switching conditions
(V
C
(2) =A
1
V
CC
6= 0;V
0
C
(2) =A
2
V
CC
6= 0) become too large, the conduction
loss and capacitive discharge loss may exceed the improvement achieved through
reducing the switch r
ON
conduction loss.
122
The formulation for the generalized Class-E switching amplier with non-zero
switching boundary conditions, follows similarly to the traditional Class-E analysis
detailed in Chapter 2. Figures 4.2(b),(c) show the equivalent schematics of the
Class-E ampliers during the ON and OFF cycles. Previous studies have shown
that an equal ON-OFF duty cycle = 50% of the time period leads to maximum
power delivery [46]. A 50% duty cycle and an output load current of I
Load
=
I
R
sin( +) to ensure only fundamental power delivery to the output load R
Load
has been assumed for the subsequent analysis of generalized Class-E ampliers. In
the following analysis, =!t has been used to normalize the Class-E time period
irrespective of frequency of operation. The operation of the generalized Class-E
design has been divided into two modes : ON and OFF dened as,
8
>
>
>
<
>
>
>
:
SwitchON :2 (0;)
SwitchOFF :2 (; 2)
(4.2)
During the ON cycle, dierential equations for the Class-E equivalent schematic
shown in Fig. 4.2(b), can be summarized as
I
SW
() =
1
!L
1
Z

1
(V
CC
V
C
()) +I
R
sin( +);82 (0;):
123
Similarly, during the OFF cycle, dierential equations for the Class-E equivalent
schematic shown in Fig. 4.2(c), can be summarized as
V
C
() +!
2
L
1
C
1
d
2
V
C
()
d
2
=V
CC
+!L
1
I
R
cos( +);82 (; 2)
Dening some variables q =
1
!
p
L
1
C
1
and p =
!L
1
I
R
V
CC
, the solution for the Class-E
switch current I
SW
can be obtained as,
I
SW
() =
8
>
>
>
<
>
>
>
:
I
R
[

p
+sin( +)sin] +I
SW
(0);82 (0;)
0;82 (; 2)
(4.3)
whereI
SW
(0) is the switch current boundary condition and non-zero for the gener-
alized Class-E analysis. Similarly, the solution for the Class-E switch voltage V
C
,
can be obtained as
8
>
>
>
<
>
>
>
:
V
C
() = 0;82 (0;)
V
C
() +
1
q
2
d
2
V
C
()
d
2
=V
CC
[1 +pcos( +)];82 (; 2)
(4.4)
with boundary conditionsV
C
(2) =A
1
V
CC
andV
0
C
(2) =A
2
V
CC
denoting the
non-zero \ZVS" and \ZdVS" boundary conditions. For periodic operation, the =
0; 2 conditions can be merged to express the switch current boundary condition
as I
SW
(0) = !C
1
V
0
C
(2). Both Eqns. 4.3 and 4.4 are identical to the Class-
E dierential equations of Chapter 2 except the boundary conditions which are
124
Figure 4.3: Class-E amplier design parameters with non-zero boundary switching
conditions (A
1
;A
2
) at 30 GHz, (a) shunt C
OFF
value, (b) switch r
ON
value.
allowed to be non-zero for the generalized Class-E analysis. Solving the dierential
equations of Eqn. 4.4 using homogenous and particular solutions, and dening
Q =
q
1q
2
the collector voltage V
C
can be further simplied as,
8
>
>
>
<
>
>
>
:
V
C
() = 0;82 (0;);
V
C
() =V
CC
[K
1
cos(q) +K
2
sin(q) + 1qpQcos( +);82 (; 2);
(4.5)
where the constants K
1
and K
2
are dened as
8
>
>
>
<
>
>
>
:
K
1
=qQcos(2q)[pcos] +Qsin(2q)[psin]cos(2q) +A
1
cos(2q)
1
q
A
2
sin(2q);
K
2
=qQsin(2q)[pcos]Qcos(2q)[psin]sin(2q) +A
1
sin(2q) +
1
q
A
2
cos(2q):
(4.6)
Traditional Class-E analysis with zero switching conditions [46] solve the variablesp
and to uniquely determine the values ofL
1
,C
1
in terms of frequency of operation
125
! and R
Load
. For the generalized Class-E analysis, the values of p and are
similarly solved using two additional boundary conditions. The current through
the inductor is continuous during the switching moment = and collector voltage
V
C
needs to start from zero at the switching moment =. These conditions can
be mathematically expressed as,
8
>
>
>
<
>
>
>
:
I
SW
() =
1
q
2
!L
1
V
0
C
();
V
C
() = 0:
(4.7)
Solving Eqns. 4.3 and 4.5 using Eqn. 4.7 enables the variablesp and to be solved
in a matrix form, given by,
2
6
6
4
qQ(1 +cos(q) Qsin(q)
qQsin(q) 2qQ[1 +cos(q)]
3
7
7
5
2
6
6
4
pcos
psin
3
7
7
5
=
2
6
6
4
A
1
cos(q)
1
q
A
2
sin(q)
A
1
sin(q)
1
q
A
2
[1cos(q)] [q +sin(q)]
3
7
7
5
:
(4.8)
In contrast, to traditional zero switching Class-E analysis, the solutions for the
Class-E variablesp and in Eqn. 4.8 are now also functions of the non-zero switch-
ing conditions A
1
and A
2
. This additional choice of boundary conditions allows a
generalized Class-E design where the high conduction loss of the small switch size
at mm-wave frequencies can be reduced by trading o with some capacitive loss
126
from non-zeroA
1
andA
2
. To uniquely determine the values ofL
1
andC
1
(and thus
C
1
=C
OFF
for switch size), a loss conservation equation is used,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
out
+P
CapacitiveLoss
=P
DC
; where
P
out
=
1
2
I
2
R
R
Load
;
P
CapacitiveLoss
=
1
2
R
2

I
C
()V
C
()d =
!C
1
4
V
2
CC
A
2
1
;
P
DC
=
V
CC
2
R
2
0
I
L
()d:
(4.9)
Eqn. 4.9 is used in conjunction with the Class-E variables (p;) =f(q;A
1
;A
2
) to
obtain the Class-E component values L
1
, C
1
and output power P
out
given by,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
L
1
=
R
Load
!
p
Z
;
C
1
=
1
q
2
!R
Load
Z
p
;
P
out
=
V
2
CC
2R
Load
Z
2
;
Z =

2p
sin +
2

cos +
1
q
2
p
A
1
(1 0:5A
1
) +
1
q
2
p
A
2
:
(4.10)
The Class-E circuit variablesp,,L
1
,C
1
of Eqns. 4.8 and 4.10 depend on the values
of q and boundary conditions A
1
;A
2
. To achieve a Class-E design with highest
eciency requires achieving the largest value of C
1
(and thus smallest transistor
r
ON
). This can be achieved by sweeping the values of q and solving Eqns. 4.8 and
4.10 to obtain the circuit variables with largest switch size for each value of (A
1
;A
2
)
pair.
127
Figure 4.4: Class-E amplier performance metrics with non-zero boundary switch-
ing conditions (A
1
;A
2
), (a) P
out
, (b) G
P
, (c) , (d) PAE.
A theoretical analysis of Eqn. 4.10 for dierent non-zero A
1
;A
2
boundary con-
dition is shown in Fig.4.3 for a Class-E design at 30 GHz using the 130 nm SiGe
BiCMOS process parameters (Table 2.1). Fig. 4.3(a) shows that compared to the
traditional Class-E analysis (A
1
;A
2
= 0), non-zero A
1
;A
2
= (0.5, -1.5) does allow
larger C
1
shunt capacitance in the Class-E design enabling using larger switch size
C
OFF
. For a transistor with xed
out
= r
ON
C
OFF
as in the 130 nm SiGe HBT
technology, this translates into lower switch r
ON
as shown in Fig. 4.3(b). Also for
the same supply voltage V
CC
chosen from technology breakdown voltage V
Br
, the
non-zero (A
1
;A
2
) also improves the fundamental content in the collector voltageV
C
resulting in higher P
out
delivery on the same output load as shown in Fig. 4.4(a).
128
4.1.2 Eciency Improvement in Generalized Class-E
The preceding theoretical analysis of generalized Class-E ampliers demonstrated
that it is possible to choose larger switch sizes for non-zero switching boundary
conditions compared to traditional Class-E analysis. Non-zero A
1
;A
2
boundary
conditions lead to capacitive discharge at the switching boundary and additional
loss P
CapacitiveLoss
arising from the resultant voltage-current overlap as quantied
in Eqn. 4.9. However, the larger switch size with lower ON resistance r
ON
that
such non-zero boundary condition allows, reduces the switch conduction loss at
mm-wave frequencies and improves the overall collector eciency. To verify if the
overall collector eciency indeed improves under non-zero boundary condition, a
perturbation analysis to calculate the switch conduction loss (in presence of nite
switch r
ON
) and non-zero boundary conditions is carried out next.
For a given frequency of operation!, output loadR
Load
, and non-zero boundary
conditions (A
1
;A
2
), the Class-E component values L
1
, C
1
and output power P
out
can be expressed in terms of normalized constants, K
L
, K
C
and K
P
respectively
given as,
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
K
L
=
!L
1
R
Load
;
K
C
=!C
1
R
Load
;
K
P
=
R
Load
V
2
CC
P
out
(4.11)
129
Using Eqn. 4.11, theP
CapacitiveLoss
from Eqn. 4.9 can be expressed in terms ofP
out
as,
P
CapacitiveLoss
=
K
C
4K
P
A
2
1
P
out
=
CapacitiveLoss
A
2
1
P
out
(4.12)
where,
CapacitiveLoss
=
K
C
4K
P
. On the other hand, the switch conduction loss,
P
SwitchLoss
due to switch r
ON
can be evaluated as,
P
SwitchLoss
=
1
2
Z

0
I
2
SW
()r
ON
d (4.13)
UsingI
SW
expressions from Eqn. 4.3, theP
SwitchLoss
can also be expressed in terms
of P
out
as,
8
>
>
>
<
>
>
>
:
P
SwitchLoss
=
SwitchLoss
! [r
ON
C
OFF
]P
out
;
where
SwitchLoss
=
K
2
C
A
2
2
+ZK
C
A
2
(

2
2p
sin+2cos)+Z
2
R

0
(

p
+sin(+)sin)
2
d
2K
P
K
C
;
(4.14)
The Class-E collector eciency can then be expressed in terms of operation fre-
quency!, technology time constant
out
=r
ON
C
OFF
, and nally constants
CapacitiveLoss
and
SwitchLoss
whose values only depend on non-zero boundary conditions (A
1
;A
2
).
8
>
>
>
<
>
>
>
:

GeneralizedClassE
max
=
Pout
Pout+P
SwitchLoss
+P
CapacitiveLoss
;
)
GeneralizedClassE
max
=
1
1+
SwitchLoss
!out+
CapacitiveLoss
A
2
1
:
(4.15)
130
Figure 4.5: Class-E amplier loss constants with non-zero boundary switching con-
ditions (A
1
;A
2
) at 30 GHz, (a)
SwitchLoss
, (b)
CapacitiveLoss
.
For traditional Class-E design with \ZVS" and \ZdVS" switching conditions,
SwitchLoss
= 4.6 and
CapacitiveLoss
= 0, and Eqn. 4.15 simplies to Eqn. 4.1. For other non-
zero boundary conditions the values of
SwitchLoss
and
CapacitiveLoss
can be quite
dierent (Fig. 4.5). Thus, for the generalized Class-E design, the maximum achiev-
able collector eciency
GeneralizedClassE
max
given by Eqn. 4.15 at a given frequency!
can be higher or lower than that obtained from Eqn. 4.1 depending on the boundary
conditions (A
1
;A
2
). A theoretical analysis of maximum collector eciency under
dierent values of (A
1
;A
2
) for a mm-wave Class-E design at 30 GHz is shown in
Fig. 4.4(c) and shows that the collector eciency improves to 82% for (A
1
;A
2
)
= (0.5, -1.5), compared to 72% obtained from conventional zero-switching Class-
E analysis (A
1
;A
2
) = (0, 0)). For mm-wave Class-E design, apart from P
out
and
, other PA performance metrics like power gain G
P
and power-added-eciency
PAE are also important. The formulations for the G
P
and PAE in a generalized
131
Class-E analysis are similar to those carried out for the traditional Class-E design
in Chapter 2. Plots of G
P
and PAE as functions of boundary conditions (A
1
;A
2
)
for a 130nm SiGe HBT generalized Class-E amplier at 30 GHz are shown in Fig.
4.4(b) and 4.4(d), respecteively. A peak PAE of 77% is predicted from the gener-
alized Class-E analysis at A
1
;A
2
= (0.5, -1.5) compared to the 68% obtained from
traditional zero-switching Class-E design.
The benet of the generalized Class-E design methodology is more evident at
mm-wave frequencies since the eect of limited switch size and thus higher con-
duction loss becomes dominant only at the mm-wave frequencies. At lower RF
frequencies, while the generalized Class-E analysis is still valid, the capacitive dis-
charge loss due to non-zero boundary conditions will always be higher than any
benet of lower conduction loss. For instance, for a 1 GHz Class-E design under
various boundary conditions, the maximum PAE point always correspond to the
\ZVS" and \ZdVS" switching conditions as shown in Fig. 4.6.
To validate the proposed generalized Class-E design methodology, a Class-E
amplier with ideal passives was design in the 130 nm SiGe BiCMOS process with
boundary conditions corresponding to the maximum PAE point of Fig. 4.4(d). The
simulated collector voltage-current waveforms and the performance summary, show
good correlation between simulated performance from real transistors with those
predicted from theoretical analysis (Fig. 4.7).
132
Figure 4.6: Class-E amplier performance metrics with non-zero boundary switch-
ing conditions (A
1
;A
2
) at 1 GHz, (a) P
out
, (b) PAE.
The generalized Class-E analysis starts as a good starting point for the study of
generalized family of switching ampliers. In the next sections, generalized Class-
E/F power ampliers will be discussed where in addition to non-zero switching
conditions, arbitrary terminations of other harmonics (not just the fundamental as
in the case of Class-E PAs) open up other design spaces for switching PA designs.
4.2 Generalized Class-EF
x
y
Power Ampliers
Utilizing harmonics of the fundamental frequency of operation for shaping non-
overlapping voltage and current waveforms has been well known in the context of
Class-F power ampliers [78]. In Class-F ampliers, the higher harmonics of the
fundamental frequency are used to ensure eciency improvement by minimizing
conduction loss within the active device. However, Class-F amplier operation re-
lies on transistors acting as current sources, and not as switches (e.g. as in Class-E
133
Figure 4.7: Transient waveforms and performance table of a 30 GHz Class-E PA
designed with non-zero boundary conditions.
ampliers). In addition, conventional Class-F analysis relying on the theory of
\maximally
at waveforms" do not account for the switch parasitic o capacitance
C
OFF
which can signicantly distort the non-overlapping requirement of the transis-
tor waveforms. To benet from the eciency improvement of additional harmonic
control of Class-F ampliers, while still incorporating the Class-E shunt capaci-
tance explicitly into the amplier load-line, a hybrid family of Class-E/F ampliers
was proposed in [45]. This new family of amplier had several advantages over
traditional Class-E design including better eciency and higher output power ca-
pability for the same transistor technology parameters. Similar studies on using
higher harmonics in a Class-E switching amplier architecture has been carried
out in [73] [72]. However, certain assumptions made in the analysis and design of
such Class-E/F ampliers limits their applications to lower RF frequencies. For
instance, assuming a large inductive choke at the collector for DC current path
134
limits the switching power amplier analysis to only one non-optimal subset of -
nite collector inductance designs as has been extensively discussed in [46]. From
the Class-E analysis of Chapter 2, eciency of mm-wave Class-E designs can be
signicantly improved with nite supply inductor. Secondly, the Class-E/F ampli-
ers described previously only assumes an open circuit or short circuit termination
for the higher harmonics. Generally, the dierent harmonics in a Class-E/F ampli-
er may require dierent harmonic terminations for optimum eciency and output
power improvement. In the following section, a generalized analysis of the Class-
E/F family of switching ampliers is carried out for arbitrary number of harmonics
with independent arbitrary harmonic terminations. Similar to the Class-E switch-
ing PA analysis carried out in Chapter 2, a mm-wave design methodology for this
generalized switching amplier classes will be discussed along with formulations for
the switching PA performance metrics (P
out
, G
P
, , PAE) in terms of transistor
technology parameters of Table 2.1.
4.2.1 Mm-Wave Class-EF
y
x
PAs with K-Harmonics
The architecture of a generalized Class-E/F family of switching ampliers is shown
in Fig. 4.8. The proposed switching amplier schematic is very similar to that of
the Class-E amplier except for the additional load terminations that are presented
to the higher harmonics. A detailed time-domain analysis of this proposed amplier
architecture will be discussed in this section. The main motivation for analyzing the
135
Figure 4.8: (a) Circuit schematic of Class-EF
y
x
amplier with K harmonic load
control, (b) ON-state equivalent circuit, (b) OFF-state equivalent circuit.
136
generalized Class-E/F family of ampliers is eciency enhancement and increased
power delivery at mm-wave frequencies for the same transistor technology compared
to conventional Class-E ampliers. The parasitic o capacitanceC
OFF
of the large
power transistors is a limiting factor in determining the switch size (and hence how
small the switch ON resistancer
ON
can be) in mm-wave switching amplier design.
However, as will discussed in this section, on presenting the higher harmonics of
the fundamental frequency with the optimum load terminations, it is possible to
increase the maximum allowable shunt capacitanceC
OFF
at a given frequency and
thus achieve higher eciency. Intuitively, this is because, in absence of additional
harmonic control, simply choosing a large switch size causes voltage current overlap
leading to capacitive discharge loss and eciency degradation. However, once the
higher harmonics are properly terminated, even in presence of a larger C
OFF
, the
phase and amplitude of the collector voltage and current waveforms can be con-
trolled in such a manner so as to prevent any additional capacitive discharge loss.
Another improvement that can be achieved in these generalized switching ampliers
with harmonic control, is improved power delivery. In conventional Class-E switch-
ing ampliers using 130nm SiGe HBTs, the non-overlapping voltage and current
waveforms, allow the collector voltage to swing as high asBV
CBO
= 5:9 V. However,
the fundamental harmonic content in this collector voltage is much smaller, with
much of the voltage headroom of 5.9 V occupied by the Class-E higher harmonic
137
content that is necessary for Class-E operation. On the other hand, for the general-
ized Class-E/F ampliers proposed here, with the right harmonic terminations, the
amplitude and phase of the voltage and current harmonics may be synthesized to
realize
atter waveforms with increased harmonic content and thus deliver higher
output power under similar breakdown voltage constraints.
4.2.2 Naming convention for Class-EF
y
x
PAs
This brief section is dedicated to explaining the naming convention for the proposed
generalized class of switching ampliers incorporating features of the both Class-E
and Class-F ampliers. Historically, the family of switching ampliers proposed
by [45] was called Class-E/F because the most ecient member of the proposed
amplier family incorporated Class-F
1
characteristics in a Class-E type switching
PA. The number of harmonics being used to achieve such F
1
operation was de-
noted by naming it Class-E=F
x
where x = 1,2, ....k for k harmonics being used. The
harmonic termination that was proposed was limited to open or short circuit. On
the other hand, the amplier family proposed here allows for arbitrary harmonic
termination. This continuity of amplier class will be denoted as Class-EF
y
1
x
1
;
y
2
x
2
;
:::
:::
;
where x
i
2 2; 3;::::: correspond to the harmonics that are being controlled. The
corresponding value of collector impedance dened as Z
C
(f
0
; 2f
0
;:::::) in Fig. 4.8
is denoted by y
i
. For example, if the second harmonic impedance (Z
C
(2f
0
)) at the
collector node in a switching Class-E PA is designed to present an open circuit,
138
so that the collector current does not have any second harmonic waveform, similar
to F
1
ampliers, then it is called Class-EF
1
2
ampliers. If the second harmonic
impedance (Z
C
(2f
0
)) at the collector node is designed to present a short circuit
so that the collector voltage is devoid of any 2nd harmonic content like a Class-F
amplier, then the amplier class will be denoted as Class-EF
2
or Class-EF
+1
2
am-
plier. A generalized load termination of the 2nd harmonic in a Class-E switching
PA will be denoted as Class-EF
y
2
where y can take values from `-1' to '1' as de-
scribed previously, with y = `0' corresponding to the second harmonic impedance
at the collector node seeing a capacitive load which results in the conventional
Class-E PA. In order to present the 2nd harmonic impedance at the collector node
(Z
C
(2f
0
)) with the appropriate impedance in presence of the parasitic output o-
state capacitance C
OFF
, the load termination for the 2nd harmonic shown as Z
L2
in Fig. 4.9 needs to be properly chosen as will be described in subsequent sections.
As yet another example, when 2nd and 3rd harmonic waveforms are controlled
so that the transistor sees open circuit at the 2nd harmonic and short circuit at
the 3rd harmonic, the collector current follows a Class-F
1
waveform while still
having a Class-E switch, and the amplier is called Class-E=F
2;3
or Class-EF
1
2
;
1
3
amplier. On the other hand, short circuit at the 2nd harmonic and open circuit
at the 3rd harmonic ensures the collector voltage follows a Class-F waveform while
still having a Class-E switch, and the amplier is called Class-EF
2;3
amplier.
139
4.2.3 Analysis of Class-EF
y
x
PAs
The analysis of the generalized Class-EF
y
x
ampliers follows solving the same `ON'
and `OFF' state equivalent circuit dierential equations with appropriate boundary
conditions similar to the generalized Class-E analysis of Section 4.1. In fact, it will
be evident later that the analysis of Section 4.1 is a special case of the switching
amplier analysis described next. In the generalized Class-EF
y
x
PA with `K' har-
monics shown in Fig. 4.8(a), along with the fundamental load current delivering
power to the output load R
Load
, there are `K-1' more harmonic currents. These
harmonic current contributions are dened as I
Rk
sin(k +
k
);8k2 (1;K). The
amplitude and phase of these `K' harmonic currents can be properly chosen for im-
proved power and eciency performance. The number of `K' harmonics can vary
from K = 1 for the Class-E analysis to K =1 for Class-E=F analysis.
The simplied circuit for the generic Class-EF
y
x
switching PA with `K' harmon-
ics is shown in Fig. 4.8(a). The `ON' state and `OFF' state equivalent circuits
are shown in Fig. 4.8(b) and Fig. 4.8(c), respectively, where the `ON' and `OFF'
state correspond to the active switching device operating in ON and OFF mode
according to the conditions of Eqn. 4.2.
During the ON cycle, dierential equations for the generalized Class-EF
y
x
equiv-
alent schematic shown in Fig. 4.8(a) can be summarized as
I
SW
() =
1
!L
1
Z

1
(V
CC
V
C
())d +
k=K
X
k=1
I
Rk
sin(k +
k
);82 (0;)
140
Similarly, during the OFF cycle, dierential equations for the Class-E equivalent
schematic shown in Fig. 4.8(b), can be summarized as,
V
C
() +!
2
L
1
C
OFF
d
2
V
C
()
d
2
=V
CC
+!L
1
k=K
X
k=1
kI
Rk
cos(k +
k
);82 (; 2)
Dening some new variables q =
1
!
p
L
1
C
OFF
and p
k
=
!L
1
I
Rk
V
CC
, the solution for the
Class-E switch current I
SW
when r
ON
= 0 can be obtained to be,
I
SW
() =
8
>
>
>
<
>
>
>
:
V
CC
!L
1
[ +
P
k=K
k=1
p
k
(sin(k +
k
)sin
k
)] +I
SW
(0);82 (0;)
0;82 (; 2)
(4.16)
whereI
SW
(0) is the switch current boundary condition and non-zero for the gener-
alized Class-E analysis. Similarly, the solution for the Class-E switch voltage V
C
,
can be obtained as,
8
>
>
>
<
>
>
>
:
V
C
() = 0;82 (; 2)
V
C
() +
1
q
2
d
2
V
C
()
d
2
=V
CC
[1 +
P
k=K
k=1
kp
k
cos(k +
k
)];82 (; 2)
(4.17)
Similar to the analysis in Section 4.1, the boundary conditions V
C
(2) = A
1

V
CC
and V
0
C
(2) = A
2
V
CC
denote the non-zero \ZVS" and \ZdVS" boundary
conditions. For periodic operation, the = 0; 2 conditions can be merged to
express the switch current boundary condition asI
SW
(0) =!C
OFF
V
0
C
(2). Solving
141
the dierential equations of Eqn. 4.17 using homogenous and particular solutions,
and dening Q
k
=
q
k
2
q
2
the collector voltage V
C
can be further simplied into,
8
>
>
>
<
>
>
>
:
V
C
() = 0;82 (; 2)
V
C
() =V
CC
[K
1
cos(q) +K
2
sin(q) + 1q
P
k=K
k=1
kp
k
Q
k
cos(k +
k
)];82 (; 2);
(4.18)
where the constants K
1
and K
2
are dened as,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
K
1
=qcos(2q)
P
k=K
k=1
kQ
k
[p
k
cos
k
] +sin(2q)
P
k=K
k=1
k
2
Q
k
[p
k
sin
k
]
cos(2q) +A
1
cos(2q)
1
q
A
2
sin(2q)
K
2
=qsin(2q)
P
k=K
k=1
kQ
k
[p
k
cos
k
]cos(2q)
P
k=K
k=1
k
2
Q
k
[p
k
sin
k
]
sin(2q) +A
1
sin(2q) +
1
q
A
2
cos(2q):
(4.19)
For the generalized Class-EF
y
x
analysis, there are `2K' variables (p
k
and
k
8k2
(1;K)) that need to be solved to uniquely determine the amplitude and phase of
the `K' harmonic currents that are design variables in this design. Out of the
`2K' equations needed to solve these `2K' variables, two equations arise from the
following boundary conditions (1) the current through the inductor is continuous
during the switching moment =, and (2) the collector voltageV
C
needs to start
142
from zero at the switching moment =. These conditions can be mathematically
expressed as,
8
>
>
>
<
>
>
>
:
I
SW
() =
1
q
2
!L
1
V
0
C
();
V
C
() = 0:
(4.20)
To simplify using Eqn. 4.20 in Eqn. 4.16 and Eqn. 4.18, the k harmonics can be
divided into groups of odd harmonic and even harmonic given by
8
>
>
>
<
>
>
>
:
k = 2m 1;8k =oddandm 2 (1;1)
k = 2n;8k =evenandn 2 (1;1):
(4.21)
Solving Eqns. 4.16 and 4.18 using Eqn. 4.20 results in two equations that can
be used to solve the variables (p
k
;
k
)8 k = (odd, even) given by,
[qsinq
m=1
X
m=1
(2m1)Q
2m1
](p
2m1
cos
2m1
)+[qsinq
n=1
X
n=1
(2n)Q
2n
](p
2n
cos
2n
)
+
m=1
X
m=1
[2q(2m1)
2
Q
2m1
(1+cosq)](p
2m1
sin
2m1
)+[
n=1
X
n=1
(2n)
2
Q
2n
(1cosq)](p
2n
sin
2n
)
(q +sinq) +A
1
cosq
1
q
A
2
sinq = 0;
(4.22)
143
[q(1+cosq)
m=1
X
m=1
(2m1)Q
2m1
](p
2m1
cos
2m1
)+[q(1cosq)
n=1
X
n=1
(2n)Q
2n
](p
2n
cos
2n
)
+sinq[
m=1
X
m=1
(2m1)
2
Q
2m1
](p
2m1
sin
2m1
)+sinq[
n=1
X
n=1
(2n)
2
Q
2n
](p
2n
sin
2n
)
+ (1cosq)A
1
sinq
1
q
A
2
(1cosq) = 0 (4.23)
The remaining `2K-2' equations are determined by the load termination conditions
for the K harmonics i.e. the real and imaginary part of Z
Lk
8 k2 (2;K)) for
the K-1 higher harmonics of the fundamental frequency of operation. As a example
consider the impedance termination for theN
th
harmonic to beZ
LN
=R
LN
+jX
LN
where N2 (2;K). The N
th
harmonic content of the collector voltage V
C
can then
be decomposed into the two orthogonal components given by,
8
>
>
>
<
>
>
>
:
V
RN
=I
RN
R
LN
=
1

R
2
0
V
C
()sin(N +
N
)d();
V
XN
=I
XN
X
LN
=
1

R
2
0
V
C
()cos(N +
N
)d();
(4.24)
Eqn. 4.24 can be simplied into,
8
>
>
>
<
>
>
>
:
1
V
CC
R
2
0
V
C
()sin(N)d() =p
N
cos
N
R
LN
!L
1
+p
N
sin
N
X
LN
!L
1
;
1
V
CC
R
2
0
V
C
()cos(N)d() =p
N
sin
N
R
LN
!L
1
p
N
cos
N
X
LN
!L
1
;
(4.25)
144
For `K-1' distinct values of N, the LHS of Eqn. 4.25 can be solved using Eqn. 4.18 to
obtain the remaining `2K-2' equations in terms of the harmonic terminations R
LN
andX
LN
. Along with Eqn. 4.22 and Eqn. 4.23, Eqn. 4.25 forms the total set of 'K'
equations that are needed to solve the normalized amplitude and phase coecients
p
k
and
k
for the K-harmonic Class-EF
y
x
amplier. To make the solution tractable,
the variables for the amplitude and phase coecients p
k
;
k
for k = odd, even can
be further redened as,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
fork =odd :
8
>
>
>
>
<
>
>
>
>
:
p
k
cos
k
=p
2m1
cos
2m1
=x
1;2m1
;
p
k
sin
k
=p
2m1
sin
2m1
=x
2;2m1
;
fork =even :
8
>
>
>
>
<
>
>
>
>
:
p
k
cos
k
=p
2n
cos
2n
=x
1;2n
;
p
k
sin
k
=p
2n
sin
2n
=x
2;2n
;
(4.26)
The `2K' variables can then be solved together in a matrix form given by,
2
6
6
6
6
4
S
1;1
:: S
1;2m1
S
1;2n
:: S
1;K
T
1;1
:: T
1;2m1
T
1;2n
:: T
1;K
S
2;1
:: S
2;2m1
S
2;2n
:: S
2;K
T
2;1
:: T
2;2m1
T
2;2n
:: T
2;K
S
3;1
:: S
3;2m1
S
3;2n
:: S
3;K
T
3;1
:: T
3;2m1
T
3;2n
:: T
3;K
.
.
. ::
.
.
.
.
.
. ::
.
.
.
.
.
. ::
.
.
.
.
.
. ::
.
.
.
.
.
. ::
.
.
.
.
.
. ::
.
.
.
.
.
. ::
.
.
.
.
.
. ::
.
.
.
S
2K;1
:: S
2K;2m1
S
2K;2n
:: S
2K;K
T
2K;1
:: T
2K;2m1
T
2K;2n
:: T
2K;K
3
7
7
7
7
5
2
6
6
6
6
6
6
6
6
6
6
6
6
6
6
4
x
1;1
x
1;2
.
.
.
x
1;2m1
x
1;2n
.
.
.
x
1;K
x
2;1
x
2;2
.
.
.
x
2;2m1
x
2;2n
.
.
.
x
2;K
3
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
=
2
6
6
6
6
6
6
6
4
H
1;1
H
1;2
.
.
.
H
2m1;1
H
2m1;2
H
2n;1
H
2n;2
.
.
.
H
K;2K
3
7
7
7
7
7
7
7
5
(4.27)
145
where the rst two row coecients from the waveform boundary conditions (Eqn.4.22,Eqn.4.23)
are given by,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
S
1;2m1
= (2m 1)qQ
2m1
sinq
S
1;2n
= (2n)qQ
2n
sinq
T
1;2m1
= 2q (2m 1)
2
Q
2m1
(1 +cosq)
T
1;2n
= (2n)
2
Q
2n
(1cosq)
H
1;1
=(q +sinq) +A
1
cosq
1
q
A
2
sinq
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
S
2;2m1
= (2m 1)qQ
2m1
(1 +cosq)
S
2;2n
=(2n)qQ
2n
(1cosq)
T
2;2m1
= (2m 1)
2
Q
2n
sinq
T
2;2n
= (2n)
2
Q
2n
sinq
H
1;2
=(1cosq)A
1
sinq
1
q
A
2
(1cosq)
(4.28)
where Q
2m1
=
q
2
(2m1)
2
q
2
and Q
2n
=
q
2
(2n)
2
q
2
. The remaining (2K 2) 2K
coecients in the LHS and 2K 2 coecients in the RHS of Eqn. 4.27 are ob-
tained by solving Eqn. 4.25 and rearranging the coecients of the state variables
x
1;2m1
;x
2;2m1
and x
1;2n
;x
2;2n
for the odd and even harmonic conditions respec-
tively. It is evident from Eqn. 4.25 and Eqn. 4.27, that the amplitude and phase
of the k
th
harmonic content of the collector voltage and current waveforms can be
controlled by the k
th
harmonic terminations Z
Lk
= R
Lk
+jX
Lk
8 k2 (2;K)).
In order to demonstrate how Eqn. 4.27 can be used to design switching PAs with
harmonic control at mm-wave frequencies, a special case considering only 2nd har-
monic control under dierent load termination conditions is described in Section
4.2.5.
146
4.2.4 Class-EF
y
x
PA Performance Metrics
To demonstrate the eect of additional harmonic control available in a generalized
Class-EF
y
x
amplier on the switching PA performance metrics, P
out
;G
P
;, and
PAE under arbitrary load terminations are discussed in this section.
Solving Eqn. 4.27 for the state variables x
1;k
;x
2;k
for given harmonic loads
Z
Lk
= R
Lk
+jX
Lk
enables us to determine the amplitude and phase coecients
p
k
;
k
of the harmonic currentsI
Rk
8k2 (1;K). These harmonic currents in turn,
determine the total collector voltage V
C
and the switch current I
SW
as well the
collector inductor L
1
and switch size C
OFF
.
The output power P
out
delivered to the fundamental load R
L1
in a given tech-
nology with xed BV
CBO
can vary depending the solutions of p
k
;
k
. Since the
maximum voltage that a SiGe HBT can support is always limited to its BV
CBO
irrespective of its harmonic content, Eqn. 4.18 can be used to determine the supply
voltage V
CC
of the switching PA,
V
C
(
V;max
) =V
CC
[K
1
cos(q
V;max
) +K
2
sin(q
V;max
) + 1q
P
k=K
k=1
kp
k
Q
k
cos(k
V;max
+
k
)] =BV
CBO
;
(4.29)
where
V;max
is the time instance of maximum collector voltage swing. ThusV
CC
=
BV
CBO
where is function ofp
k
;
k
determined by the harmonic terminations.
Similar to the generalized Class-E analysis of Section 4.1, for a given frequency of
operation !, output load R
Load
, and non-zero boundary conditions (A
1
;A
2
), the
147
Class-EF
y
x
component values L
1
, C
1
and output power P
out
can be expressed in
terms of normalized constants, K
L
, K
C
and K
P
respectively given as
8
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
:
K
L
=
!L
1
R
Load
;
K
C
=!C
1
R
Load
;
K
P
=
R
Load
V
2
CC
P
out
=
R
Load

2
BV
2
CBO
P
out
:
(4.30)
From conservation of power, we have
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
out
+
P
k=1
k=2
P
Lk
+P
CapacitiveLoss
=P
DC
;
P
out
=
1
2
I
2
R1
R
Load
;
P
Lk
=
1
2
I
2
Rk
R
Lk
;
P
CapacitiveLoss
=
1
2
R
2

I
C
()V
C
()d =
!C
OFF
4
A
2
1
;
P
DC
=
V
CC
2
R
2
0
I
L
()d;
(4.31)
whereP
Lk
is the power dissipated in the resistive part ofk
th
harmonic termination,
andP
CapacitiveLoss
is the capacitive dissipation due to non-zero boundary conditions
(A
1
;A
2
). Solving Eqn. 4.31 using Eqn. 4.16 and Eqn. 4.18 enables us to dene a
new variable `Z' given by
Z =
I
R1
R
Load
V
CC
=

2p
1

P
k=1
k=1
p
k
p
1
sin
k
+
2

P
k=odd
cos
k
k
+
1
q
2
p
A
1
(1 0:5A
1
) +
1
q
2
p
A
2
1 +
P
k=1
k=2
(
p
k
p
1
)
2
R
Lk
:
(4.32)
148
The values of L
1
, C
OFF
and P
out
for a given frequency ! and fundamental load
R
Load
can then be derived to be,
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
L
1
=
R
Load
!
K
L
=
R
Load
!
p
1
Z
;
C
OFF
=
1
!R
Load
K
C
=
1
!R
Load
Z
q
2
p
1
;
P
out
=

2
BV
2
CBO
R
Load
K
P
=

2
BV
2
CBO
R
Load
Z
2
2
=
2
BV
2
CBO
R
Load
:
(4.33)
It is evident from Eqn. 4.33 that solutions p
k
;
k
, boundary conditions (A
1
;A
2
),
and load terminationsZ
Lk
that increase values of `Z' are benecial to increase both
output power P
out
and switch size C
OFF
. It is also seen in Eqn. 4.32 that any
harmonic resistive termination will dissipate additional power and thus lowers the
power delivered to the fundamental load. Thus, in any practical implementations
of the generalized Class-EF
y
x
ampliers only reactive harmonic terminations are
considered. However, if R
Lk
can be made negative implying harmonic injection
(and power delivery from other harmonic active sources), then values of `Z' can
actually be increased leading to eciency and power improvement; this is brie
y
covered in Section. 4.2.5.4.
To quantify the eciency improvement in switching PAs with harmonic control,
the capacitive loss,P
CapacitiveLoss
, and switch conduction loss,P
SwitchLoss
, now need
149
to be considered. From Eqn. 4.31, the capacitive loss in terms of non-zero boundary
conditions can be calculated as,
P
CapacitiveLoss
=
K
C
4K
P
A
2
1
P
out
=
CapacitiveLoss
A
2
1
P
out
(4.34)
where,
CapacitiveLoss
=
K
C
4K
P
. On the other hand, assuming small switch ON resis-
tance, the switch conduction loss, P
SwitchLoss
, can be evaluated as
P
SwitchLoss
=
1
2
Z

0
I
2
SW
()r
ON
d: (4.35)
UsingI
SW
expressions from Eqn. 4.3, theP
SwitchLoss
can also be expressed in terms
of P
out
as,
P
SwitchLoss
=
SwitchLoss
! [r
ON
C
OFF
]P
out
; (4.36)
where

SwitchLoss
=
K
2
C
A
2
2
+ZK
C
A
2
(

2
2p
1

P
k=1
k=1
p
k
p
1
sin
k
+2
P
k=odd
cos
k
)+Z
2
R

0
[

p
1
+
P
k=1
k=1
(sin(k+
k
)sin
k
)]
2
d
2K
P
K
C
:
(4.37)
150
The Class-EF
y
x
collector eciency can then be expressed in terms of operation
frequency !, technology time constant
out
=r
ON
C
OFF
, and nally loss constants

CapacitiveLoss
and
SwitchLoss
as
8
>
>
>
<
>
>
>
:

ClassEF
y
x
max
=
Pout
Pout+P
SwitchLoss
+P
CapacitiveLoss
;
)
ClassEF
y
x
max
=
1
1+
SwitchLoss
!out+
CapacitiveLoss
A
2
1
:
(4.38)
The eciency and output power formulation of the generalized Class-EF
y
x
am-
pliers are identical to those of Class-E amplier (Eqn. 4.15,4.11). Like the
Class-E switching PAs, the output power and eciency in the generalized Class-
EF
y
x
ampliers are only dependent on technology parameters like BV
CBO
and

out
= r
ON
C
OFF
. In contrast to Class-E ampliers however, the additional
harmonic control in the Class-EF
y
x
allows the power constant and the eciency
constant
SwitchLoss
to be dierent depending on how many harmonics are being
controlled and what harmonic termination have been used. By choosing the op-
timum number of harmonic control with the optimum harmonic termination, it is
thus possible to exceed the Class-E amplier performance at a given frequency using
the same transistor technology. In the next section, a demonstration of switching
PA with only 2nd harmonic control is discussed the illustrate the theory highlighted
in this section.
151
Figure 4.9: (a) Circuit schematic of Class-EF
y
2
amplier, (b) smith chart showing
variation of second harmonic load termination.
4.2.5 Switching PA (EF
y
2
) with 2nd Harmonic Control
In order to demonstrate how Eqn. 4.27 can be used to design switching PAs at
mm-wave frequencies, various Class-EF
y
2
ampliers with only 2nd harmonic control
and dierent 2nd harmonic load terminationsZ
L2
are considered (Fig. 4.9(a)). For
K=2, a total of 4 variables p
1
;p
2
and
1
, and
2
need to be solved to uniquely
determine the contribution of the fundamental and 2nd harmonic frequencies in
the collector voltage and current waveforms. The collector voltage and current
waveforms of the generalized Class-EF
y
x
amplier in Eqn. 4.18 and 4.16 can then
be simplied to,
8
>
>
>
>
<
>
>
>
>
:
I
SW
() =
V
C
C
!L
1
[ +p
1
(sin( +
1
)sin
1
) +p
2
(sin(2 +
2
)sin
2
)] +!C
OFF
A
2
V
CC
;82 (0;)
V
C
() =V
CC
[K
1
cos(q) +K
2
sin(q) + 1qp
1
Q
1
cos( +
1
) 2qp
2
Q
2
cos(2 +
2
);82 (; 2);
(4.39)
152
where K
1
;K
2
can be obtained for K=2 in Eqn. 4.19 and Q
1
=
q
1q
2
;Q
2
=
q
4q
2
.
Using the current continuity conditions at =, and renaming the variables as,
8
>
>
>
<
>
>
>
:
p
1
cos
1
=x
1;1
;
p
1
sin
1
=x
2;1
;
8
>
>
>
<
>
>
>
:
p
2
cos
2
=x
1;2
;
p
2
sin
2
=x
2;2
;
(4.40)
the equations for solving the 4 variables can be expressed as,
2
6
6
6
6
6
6
6
6
6
6
4
S
1;1
S
1;2
T
1;1
T
1;2
S
2;1
S
2;2
T
2;1
T
2;2
S
3;1
S
3;2
T
3;1
T
3;2
S
4;1
S
4;2
T
4;1
T
4;2
3
7
7
7
7
7
7
7
7
7
7
5
2
6
6
6
6
6
6
6
6
6
6
4
x
1;1
x
1;2
x
2;1
x
2;2
3
7
7
7
7
7
7
7
7
7
7
5
=
2
6
6
6
6
6
6
6
6
6
6
4
H
1;1
H
1;2
H
2;1
H
2;2
3
7
7
7
7
7
7
7
7
7
7
5
; (4.41)
where the rst two row coecients from the waveform boundary conditions are
given by,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
S
1;1
=qQ
1
sinq
S
1;2
= 2qQ
2
sin
T
1;1
= 2qQ
1
(1 +cosq)
T
1;2
= 4Q
2
(1cosq)
H
1;1
=(q +sinq) +A
1
cosq
1
q
A
2
sinq
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
S
2;1
=qQ
1
(1 +cosq)
S
2;2
=2qQ
2
(1cosq)
T
2;1
=Q
1
sinq
T
2;2n
= 4Q
2
sinq
H
1;2
=(1cosq)A
1
sinq
1
q
A
2
(1cosq)
(4.42)
153
The values of the last two rows will depend on the second harmonic load termi-
nations (Fig. 4.9(b)) to realize dierent type of waveforms. Solving the values
of x
1;1
;x
1;2
;x
2;1
;x
2;2
enables solution of the harmonic amplitude and phase contri-
butions p
1
;p
2
,
1
;
2
. As mentioned before, the harmonic load terminations are
considered to be lossless, i.e, R
L2
= 0. Therefore, parameter `Z' dened in Eqn.
4.32 can be simplied for this Class-EF
y
2
amplier class as,
Z =
1
2p
1
[ 2(p
1
sin
1
+p
2
sin
2
) +
4

p
1
cos
1
]: (4.43)
The values of L
1
and C
OFF
(i.e., switch size) and the PA performance metrics
(P
out
;;G
P
;PAE) can then calculated for each case of 2nd harmonic termination
for a given ! and fundamental load R
L1
as,
8
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
:
L
1
=
R
L1
!
p
1
Z
;
C
OFF
=
1
!R
L1
Z
q
2
p
1
;
P
out
=
2
BV
2
CBO
R
L1
;

ClassEF
y
2
max
=
1
1+
SwitchLoss
!out+
CapacitiveLoss
A
2
1
;
(4.44)
154
where
CapacitiveLoss
and
SwitchLoss
are constants that are also determined based
on the solutions of the Class-EF
y
2
variables p
1
;p
2
,
1
and
2
as
8
>
>
>
<
>
>
>
:

SwitchLoss
=
K
2
C
A
2
2
+ZK
C
A2(

2
2p
1
sin1
p
2
p
1
sin2+2cos1)+Z
2
R

0
(

p
+sin(+1)sin1+sin(2+2)sin2)
2
d
2K
P
K
C
;

CapacitiveLoss
=
K
C
4K
P
:
(4.45)
In the remaining sections, some special cases of Class-EF
y
2
ampliers will be con-
sidered to demonstrate how the voltage and current waveforms change based on
the 2nd harmonic load termination as well as how the PA performance metrics
improve/degrade based on dierent 2nd harmonic termination values. Proof-of-
concept design simulations demonstrating mm-wave 30 GHz operation are also
provided to support the aforementioned methodology.
4.2.5.1 Class-E=F
2
PAs
One of the most well know class within the Class-EF
y
2
family of ampliers is the
Class-E=F
2
amplier where the voltage and current waveforms have the property
of both Class-E and Class-F
1
2
ampliers [45].The main characteristic of Class-
F
1
ampliers is the open-circuit collector impedance for the 2nd harmonic, i.e,
Z
C2
=1, resulting in zero 2nd harmonic contribution in the switch current I
SW
.
It is important to keep in mind that, open circuit 2nd harmonic collector impedance
Z
C2
=1, does not mean the 2nd harmonic load termination Z
L2
in Fig. 4.9(a)
is also open-circuit. Since the transistor used as the switching device has a nite
155
Figure 4.10: (a) Transient waveforms for 30 GHz Class-E=F
2
amplier, (b) per-
formance table, (c) open-circuit collector node impedance under second harmonic
load control.
C
OFF
, the 2nd harmonic load termination Z
L2
needs to be inductive to tune out
thisC
OFF
at the 2nd harmonic. The lack of 2nd harmonic component in the switch
current I
SW
may be expressed as
8
>
>
>
<
>
>
>
:
1

R
2
0
I
SW
()sin(2)d() = 0;
1

R
2
0
I
SW
()cos(2)d() = 0:
(4.46)
Assuming the boundary conditions, A
1
= 0;A
2
= 0 for this particular design
156
example, the coecients in Eqn. 4.41 are found as,
2
6
6
4
S
3;1
S
3;2
T
3;1
T
3;2
S
4;1
S
4;2
T
4;1
T
4;2
3
7
7
5
=
2
6
6
4

2
3
0 0

2
0

2
4
3
0
3
7
7
5
(4.47)
2
6
6
4
H
2;1
H
1;2
3
7
7
5
=
2
6
6
4
0

2
3
7
7
5
From the solutions to this equation and Eqns. 4.47, 4.40, the variables p
1
;p
2
;
1
;
and
2
are found to be 0.935, 0.935, 0.23, and 0.44 respectively. From Eqn. 4.43
the parameter Z will be 1.65. For a 30 GHz design with R
Load
= 50
, the values
of circuit components and parameters can be obtained from Eqn. 4.44 as L
1
=
150 pH, C
OFF
= 142 fF. For the solved values of p
1
;p
2
;
1
; and
2
, the maximum
value of the collector voltage V
C
() from Eqn. 4.29 can be equated withBV
CBO
to
determine the supply voltageV
CC
of the design. This in turn enables determination
of =
V
CC
BV
CBO
(Eqn. 4.30) and thus P
out
= 70 mW from Eqn. 4.44 leading to
= 0.32. For eciency calculation, the loss constant
SwitchLoss
= 2.3 leading to
= 90%. The theoretical Class-E=F
2
waveforms along with the 130nm SiGe HBT
simulated design are shown in Fig. 4.10(a). The PA performance metrics are
summarized in Fig. 4.10(b). The second harmonic impedance at the collector node
Z
C
(2f
0
) is shown in Fig. 4.10(c) and demonstrates open-circuit termination.
157
Figure 4.11: (a) Transient waveforms for 30 GHz Class-EF
2
amplier, (b) perfor-
mance table, (c) short-circuit collector node impedance under second harmonic load
control.
Compared to the Class-E=F
2
ampliers, a conventional Class-E design results
in
SwitchLoss
= 4.6 and a resultant = 72% at 30 GHz with a switch size C
OFF
= 75 fF for 50
R
Load
. Thus the additional 2nd harmonic control in Class-E=F
2
helps to improve the switching PA eciency by ensuring a larger transistor can be
used as the active switch.
158
4.2.5.2 Class-EF
2
PAs
Another special case of switching PAs with harmonic control is the Class-EF
2
amplier where the voltage and collector waveforms have both Class-E and Class-
F characteristics. Thus, the 2nd harmonic content of the collector voltage in the
Class-EF
2
amplier needs to be zero, similar to that of Class-F
2
amplier. This
means zero 2nd harmonic load impedance, i.e., Z
L2
= 0. This condition can be
used for obtaining two additional constraints given by
8
>
>
>
>
<
>
>
>
>
:
1

R
2
0
V
C
()sin(2)d() = 0;
1

R
2
0
V
C
()cos(2)d() = 0:
(4.48)
Assuming boundary conditions A
1
= 0;A
2
= 0 for this particular design example,
the remaining coecients for Eqn. 4.41 are then obtained as,
2
6
6
4
S
3;1
S
3;2
T
3;1
T
3;2
S
4;1
S
4;2
T
4;1
T
4;2
3
7
7
5
=
h
2Q
1
[
2
3
qQ
2
(1cosq)] 4Q
2
2
(1cosq)
2
q
Q
1
Q
2
sinq Q
2
(q+
8
q
Q
2
sinq)
qQ
1
Q
2
sinq Q
1
[
2
3
qQ
2
(1cosq)]qQ
2
(+2Q
2
sinq) 4Q
2
2
(1cosq)
i
(4.49)
2
6
6
4
H
2;1
H
1;2
3
7
7
5
=
2
6
6
4
2
q
Q
2
(1cosq)
Q
2
sinq
3
7
7
5
159
From the solutions to this equation and Eqns. 4.42, 4.40, the variables p
1
;p
2
;
1
;
and
2
are found to be 1.86, 1.86, 0.55, and 1.32 respectively. From Eqn. 4.43 the
parameter Z will be 1.225. For a 30 GHz design with R
Load
= 50
, the values
of circuit components and parameters can be obtained from Eqn. 4.44 are given
as L
1
= 400 pH, C
OFF
= 15 fF. For the solved values of p
1
;p
2
;
1
; and
2
, the
maximum value of the collector voltage V
C
() from Eqn. 4.29 can be equated with
BV
CBO
to determine the supply voltage V
CC
of the design. This in turn enables
determination of =
V
CC
BV
CBO
(Eqn. 4.30) and thus P
out
= 40 mW from Eqn. 4.44
leading to = 0.24. For eciency calculation, the loss constant
SwitchLoss
= 24
leading to = 50%. The theoretical Class-EF
2
waveforms along with the 130nm
SiGe HBT simulated design are shown in Fig. 4.11(a). The PA performance metrics
are summarized in Fig. 4.11(b). It is evident that this particular design achieves
worse performance compared to the conventional Class-E design (Fig. 4.7). The
second harmonic impedance at the collector node Z
C
(2f
0
) is shown in Fig. 4.11(c)
and demonstrates short-circuit termination.
4.2.5.3 Class-EF
y
2
PAs with Arbitrary 2nd Harmonic Termination
For the generalized case of arbitrary 2nd harmonic non-resistive load termination
i.e., Z
L2
= jX
L2
, dierent classes of amplier design are possible including the
Class-E, Class-EF
2
and Class-E=F
2
. Depending on the 2nd harmonic load termi-
nation, the collector voltage and current waveforms can be quite dierent as shown
160
for some examples in Fig. 4.12. For dierent load terminations Z
L2
, the total
2nd harmonic collector impedance Z
C2
(including switch capacitance C
OFF
) can
behave as open circuit (Class-E=F
2
), capacitive (Class-E), and short circuit Class-
EF
2
. The classication of dierent amplier classes based on Z
C2
is shown in Fig.
4.9(b). Intuitively, as the 2nd harmonic impedance moves from capacitive (Class-
E) to open-circuit (Class-E=F
2
), the switch size can be increased for the same
fundamental loadR
Load
at the same frequency! leading to eciency improvement
as shown in Fig. 4.12. Again, as the 2nd harmonic collector impedance Z
C2
moves
from open circuit to short circuit (Class-EF 2), the allowable switch size becomes
smaller and smaller,leading to eciency degradation (Fig. 4.12). Other interme-
diate classes of PAs are also shown in Fig. 4.12 for various capacitive-inductive
second harmonic collector impedances along with their associated performances at
30 GHz
4.2.5.4 Active Waveform Engineering by 2nd Harmonic Injection
Harmonic injection in Class-E power ampliers have been discussed in the litera-
ture [79, 80], for waveform shaping and eciency improvement. However, instead
of treating such harmonic-injected Class-E power ampliers as a separate class of
switching PAs called Class-E
M
[79,80], it can be shown that that such active har-
monic injection may be treated as a sub class of the generalized harmonic controlled
Class-EF
y
x
amplier that was discussed in Section. 4.2.
161
Figure 4.12: Simulated collector voltage and switch current waveforms under dier-
ent second harmonic impedanceZ
C
(2f
0
) in a 30 GHz Class-EF
y
2
amplier realized
in a 130nm SiGe HBT process along with the corresponding P
out
and . Ideal
passives are assumed in all cases
162
Figure 4.13: Example of an active second harmonic injection in a Class-EF
y
2
switch-
ing amplier.
In Section. 4.2.5, the resistive part of 2nd harmonic load termination R
L2
was
set to zero to prevent power dissipation in the harmonic load network. In fact, from
Eqn. 4.32,
Z =
1
2p
1
2(p
1
sin
1
+p
2
sin
2
) +
4

p
1
cos
1
1 + (
p
2
p
1
)
2
R
L2
: (4.50)
We can see that for R
L2
0, setting R
L2
= 0 maximizes `Z' leading to higher
C
OFF
, , and P
out
. However, in presence of 2nd harmonic injection from an ex-
ternal active power source, R
L2
< 0 and values of `Z' can be increased to obtain
better PA performance. The schematic of one such 2nd harmonic-injected switch-
ing power ampliers is shown in Fig. 4.13. In general, the power consumption
163
needed to generate the 2nd harmonic injection also needs to be considered in cal-
culating the overall eciency of the harmonic injected switching PAs. For a given
technology, since switching amplier eciency degrades with frequency, the e-
ciency of an active `auxiliary' harmonic injectors is often worse than that of the
main power generation stage. As such, the overall eciency of a harmonic-injected
PA is not better than that of passive waveform shaped switching PA. However, in
technologies where dierent
avors of transistors are available, using high break-
down voltage, low-speed transistors for the main power generation stage and low
breakdown voltage, high-speed transistors for the harmonic injector design, may
enable performance improvement in active harmonic injected switching PAs.
4.3 Composite Waveforms in Stacked Switching
Power Ampliers
Series stacking of transistors in a Class-E switching amplier architecture was dis-
cussed in Chapter 3 for improving the collector voltage swing and output power
of Class-E SiGe PAs. Series stacking of transistors can also be implemented in
the generalized Class-EF
y
x
switching PAs with additional harmonic control. Such
designs may oer higher output power and eciency compared to stacked Class-E
ampliers.
164
Stacked power ampliers can achieve higher collector voltage swing by dividing
the overall collector voltage amongst the series stacked transistors. In most mm-
wave implementations of stacked PAs, such voltage division is achieved through a
capacitive divider network. This capacitive voltage divider results in similar voltage
waveforms with similar harmonic contents across each of the series stacked switching
transistors in the `OFF' state. Analysis of such capacitively coupled stacked Class-
EF
y
x
ampliers will be covered in Sec. 4.3.1. A new architecture of stacked switching
PAs called Class-K PAs is proposed in Sec. 4.3.2 where instead of a capacitive
divider, independent harmonic load networks are connected to the collector of each
series stacked transistor. In stacked Class-K PAs, a harmonic impedance network is
connected to allow each transistor of the stacked conguration to achieve dierent
voltage and collector waveforms with dierent harmonic contents. The merits and
demerits of such composite waveforms stacked Class-K PAs are discussed in Sec.
4.3.2.
4.3.1 Stacked Class EF
y
x
Power Ampliers
In stacked Class-EF
y
x
ampliers, two or more switching transistors are placed in
series and a proper capacitive division ensures that the overall collector voltage is
divided across all the series stacked transistors. The schematic of a generic stacked
Class-EF
y
x
amplier with two series stacked HBTs is shown in Fig. 4.14(a). In this
architecture, the collector voltage and current of the top transistorQ
1
is shaped by
165
Figure 4.14: Two-Stacked Class-EF
y
x
switching amplier with a capacitive divider
K-harmonic control for the top transistor, (a) Circuit schematic, (b) equivalent
circuit during ON state, (c) equivalent circuit during OFF state.
impedances Z
Lk
presented at each of the K harmonics as discussed in Section 4.2.
The collector voltage of this top transistor is then replicated across the collector
of the lower HBT by means of the capacitive divider. The equivalent circuits of
the 2-stacked Class-EF
y
x
PAs during the switch `ON' and `OFF' state are shown
in Fig. 4.14(b) and 4.14(c), respectively. The operation of the stacked Class-EF
y
x
relies on the synchronous switching action of all the series stacked HBTs. During
the ON state, the Class-EF
y
x
switch current I
SW
including all the harmonic com-
ponents, as dictated by the harmonic impedance networks,
ows through each of
the series transistors. During the OFF state, a capacitive divider network compris-
ing of capacitor C
OUT
and the intrinsic parasitic capacitance C
OFF1
of the bottom
transistor ensures that collector voltage waveform of the top transistor is replicated
166
at the bottom transistor collector node (Fig. 4.14(c)). Therefore, all the series
stacked HBTs operate in the same Class-EF
y
x
mode of operation with a resultant
higher overall collector voltage swing and higher output power.
The analysis of the stacked Class-EF
y
x
can be carried out based on the analysis
of non-stacked Class-EF
y
x
PAs in Section 4.2 and the stacked Class-E PA analysis
of Chapter 3. The analysis is shown for a special case of the 2-stacked PA but it
can be generalized to an N-stacked transistor as well.
During the ON-state (Fig. 4.14(b)), the switch currents in the series-stacked
switches Q
1
and Q
2
denoted as I
SW1
and I
SW2
, respectively, can be derived from
82 (0;)
8
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
:
I
SW2
() =
1
!L
1
R

1
(V
CC
V
C
()) +
P
k=K
k=1
I
Rk
sin(k +
k
);
I
SW1
() =I
SW2
() +I
B2
();
I
B
2
() =!C
B2
d
d
V
B2
() =
C
B2
C
2
C
B2
+C
2
d
d
V
mid
()
Assuming r
ON1
= r
ON2
= 0, V
mid
() = 0; 8 2 (0;). Therefore, using the
previously dened variables p
k
, the switch currents can be expressed as
I
SW
() =I
SW2
() =I
SW1
() =
8
>
>
>
>
<
>
>
>
>
:
V
C
C
!L
1
[ +
P
k=K
k=1
p
k
(sin( +
k
)sin
k
)] +I
SW
(0);82 (0;)
0;82 (; 2)
(4.51)
167
where I
SW
(0) is the switch current boundary condition and non-zero for the generalized
stacked PA analysis. Similarly, during the OFF cycle, dierential equations for the stacked
switching PA equivalent schematic shown in Fig. 4.14(c) can be summarized as
82 (; 2)
8
>
>
>
>
<
>
>
>
>
:
V
C
() +!
2
L
1
C
eq
d
2
[V
C
()V
mid
()]
d
2
=V
CC
+!L
1
P
k=K
k=1
kI
Rk
cos(k +
k
);
V
mid
() =
C
OUT
C
OFF1
+C
OUT
+
C
B2
C
2
C
B2
+C
2
V
C
():
The solution for the stacked PA switch voltages, V
C
and V
mid
, can be obtained as
8
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
:
V
C
() = 0;82 (; 2)
V
C
() +
1
q
2
d
2
V
C
()
d
2
=V
CC
[1 +
P
k=K
k=1
kp
k
cos(k +
k
)];82 (; 2)
V
mid
() =
C
OUT
C
OFF1
+C
OUT
+
C
B2
C
2
C
B2
+C
2
V
C
() =
V
C
();82 (0; 2)
(4.52)
whereq =
1
p
L
1
Ceq
,C
eq
=C
OFF2
jjC
OUT
C
OFF1
+C
2
jjC
B
2
C
OUT
+C
OFF1
+C
2
jjC
B
2
and
=
C
OUT
C
OFF1
+C
OUT
+
C
B2
C
2
C
B2
+C
2
.
Equations 4.51, 4.52 can be solved for obtaining the time domain expressions of the
collector voltage and currents in the stacked PA architecture, by following the same
matrix form solution of the harmonic current amplitude, p
k
and phase,
k
, as outlined in
Section. 4.2.
Once the collector voltages V
C
and V
mid
and switch currents I
SW1
and I
SW2
are
determined based on the harmonic load terminations, Z
Lk
, the performance metrics of
the stacked Class-EF
y
x
ampliers can be determined. To maximize the output power
168
generation capability in stacked switching PAs, the collector-emitter voltage of the top
transistor V
CE2
is maximized to reach BV
CBO
,
8
>
>
>
>
<
>
>
>
>
:
V
CE2
() =V
C
()V
mid
() = (1
)V
C
();
V
C
(
V;max
) =
1
1
V
CE2
(
V;max
) =
1
1
BV
CBO
;
(4.53)
where
=
V
C
V
mid
. The output power and eciency in a 2-stacked Class-EF
y
x
switching PA
are then given by
8
>
>
>
>
<
>
>
>
>
:
P
out
=

2
(1
)
2
BV
2
CBO
R
Load
;

StackedClassEF
y
2
max
=
1
1+2
SwitchLoss
!out+
CapacitiveLoss
A
2
1
:
(4.54)
Similar to the non-stacked Class-EF
y
x
ampliers of Section 4.2, the values of and

SwitchLoss
;
CapacitiveLoss
also vary depending on the type of harmonic loading Z
Lk
. In
order to demonstrate transistor stacking using Class-EF
y
x
architecture, a special case of
stacked Class-E=F
2;3
power amplier operating at 30 GHz is described next.
4.3.1.1 30 GHz SiGe HBT Dierential Stacked Class-E=F
2;3
Power Amplier
To demonstrate operation of stacked switching PAs with harmonic load control at mm-
wave frequencies, a 30 GHz, 2-stacked, Class-E=F
2;3
dierential amplier is designed
(Fig. 4.17(a)). The dierential architecture eliminates the need for any lossy DC blocking
capacitors in the harmonic load network. Parallel tanks resonant at the fundamental 30
GHz frequency are added to the harmonic load networks to prevent any fundamental load
current from entering in the harmonic load networks.
169
Figure 4.15: 30 GHz dierential stacked Class-EF
2;3
amplier, (a) circuit schematic,
(b) simulated transient collector voltage and current waveforms, (c) simulated per-
formance assuming ideal passives.
For the rst and third odd-harmonics, the dierential half circuits simplies to the
generic stacked Class-EF
y
x
circuits of Fig. 4.14. The harmonic load at the third harmonic,
dictated primarily by the series inductor Z
L3
is chosen to present a short circuit at the
collector node, i.e., Z
C
(90 GHz) = 0. The inductor Z
L2
is connected from the harmonic
load mid-point to the ground and appropriately chosen so that the collector sees an
open circuit at the second harmonic, i.e.,Z
C
(60 GHz) =1. Under these harmonic load
terminations, the collector voltage and current waveforms are shown in Fig. 4.17(b).
170
Assuming ideal passives, the 2-stacked dierential Class-E=F
2;3
PA generatesP
out
= 26.5
dBm, with G
P
= 11 dB, = 65%, and PAE = 62 %.
Practical implementation of such harmonic controlled PA, however, must also account
for additional conduction loss arising from the nite quality factor of the passives in the
harmonic load network. In order to account for performance degradation due to nite
on-chip passive loss, Fig. 4.16 shows the dierent design steps, starting from the Class-
E=F
2;3
design with ideal passives and parasitic modeled HBT layout in Fig. 4.16(a). It
can be observed that the collector eciency degrades due to the nite Q-factor of the
collector inductanceL
1
(Fig. 4.16(b)) as well as from the conduction loss in the harmonic
load network (Fig. 4.16(c)). On including the loss of the on-chip passives, the collector
eciency for the stacked switching PAs can be expressed as,

StackedClassK
max
=
1
1 + 2 2:3!
out
(1 +
C
OFF2
C
OUT
) +
8
Q
L1
+
4
Q
HarmonicNetwork
; (4.55)
whereQ
L1
15 is the quality factor for theL
1
collector inductance andQ
HarmonicNetwork
15 is the equivalent quality factor for the harmonic load network. The schematic and
die microphotograph of a complete two-stage stacked Class-E=F
2;3
amplier fabricated
in a 130 nm SiGe BiCMOS process are shown in Fig. 4.17. The performance of the
implemented design shown in Fig. 4.18 demonstrate a center frequency shift to 34 GHz,
peak output power of 25.1 dBm with corresponding 11 dB large signal power gain, 26%
collector eciency, and 25% power added eciency.
171
Figure 4.16: Design steps of the 30 GHz dierential stacked Class-EF
2;3
amplier
showing performance degradation due to (a) HBT layout parasitics, (b) inductor
loss (Q
ind
= 15), (c) loss of output impedance matching networks (Q
ind
= 15,Q
cap
= 35), (d) loss of input impedance matching network.
Figure 4.17: Schematic and die microphotograph of the two-stage two-stacked dif-
ferential Class-E=F
2;3
amplier.
172
Figure 4.18: Performance of the two-stage two-stacked dierential Class-E=F
2;3
amplier, (a) output power and power gain versus input power at 34 GHz, (b)
saturated output power and corresponding PAE versus frequency, (c) collector ef-
ciency versus output power, (d) power added eciency versus output power.
4.3.2 Stacked Class-K Composite Power Amplier
Another conguration in which harmonic load impedances can be used to shape collector
voltage and current waveforms in a stacked switching PA architecture is shown in Fig.
4.19(a). In this conguration, two distinct harmonic load networks, (Z
Lk
andZ
midk
) are
connected to the collector of each stacked HBT, Q
1
and Q
2
, respectively. An important
distinction between the architecture of Fig. 4.19(a) and the stacked amplier Class-EF
y
x
of Sec. 4.3.1 is the absence of capacitive divider network in the collector nodeV
C
. Hence,
in this case, collector voltage and current waveforms in each of the stacked transistors
can be set to be dierent based on the harmonic load networks Z
Lk
and Z
midk
. Such
independent control of collector voltages of the series stacked transistors results in several
advantages. Firstly, the absence of capacitive divider implies that during the OFF cycle,
173
Figure 4.19: A 2-stacked Class-K switching ampliers with K-harmonic controls
for both HBTs, (a) Circuit schematic, (b) equivalent circuit during the ON state,
(c) equivalent circuit during the OFF state.
the series stacked transistors are separated into independent equivalent circuits as shown
in Fig. 4.19(c). Thus, the voltage waveform on each of the series stacked HBT can be
chosen to reach the maximumBV
CBO
value independently of capacitive division ration
which limits the voltage swing on the lower transistors for the capacitively coupled Class-
EF
y
x
PAs. As result, each series stacked HBT can support dierent collector waveforms
independent of each other and also generate higher output power. Secondly, since the
harmonic impedance networks are connected to the collector of each series stacked HBTs,
a proper harmonic impedance termination can allow choosing larger transistor sizes re-
sulting in lower overall conduction loss and higher eciency in the composite stacked
Class-K PAs.
The analysis of the Class-K composite waveform PAs can be carried out based on
the equivalent circuit schematics during the switch ON and OFF states as shown in Fig.
174
4.19(b) and Fig. 4.19(c), respectively. During the ON cycle shown in Fig. 4.19(b), the
switch currents I
SW1
and I
SW2
are given by
82 (0;)
8
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
:
I
SW2
() =
1
!L
1
R

1
(V
CC
V
C
()) +
P
k=K
k=1
I
Rk
sin(k +
k
);
I
SW1
() =I
SW2
() +I
B2
() +
P
k=K
k=1
I
midk
sin(k +
midk
);
I
B
2
() =!C
B2
d
d
V
B2
() =
C
B2
C
2
C
B2
+C
2
d
d
V
mid
():
Since V
mid
() = 0;82 (0;), then using the dened variables
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
p
k
=
!L
1
I
Rk
V
CC
;
p
midk
=
!L
1
I
midk
V
CC
;
q
top
=
1
p
L
1
C
OFF2
;
q
bottom
=
1
p
L
1
C
mid
where C
mid
=C
OFF1
+C
B2
jjC
2
, the switch currents can be expressed as
I
SW2
() =
8
>
>
>
>
<
>
>
>
>
:
V
CC
!L
1
[ +
P
k=K
k=1
p
k
(sin(k +
k
)sin
k
)] +I
SW2
(0);82 (0;)
0;82 (; 2)
(4.56)
and
I
SW1
() =
8
>
>
>
>
<
>
>
>
>
:
I
SW2
() +
P
k=K
k=1
p
midk
sin(k +
midk
);82 (0;)
0:82 (; 2)
(4.57)
175
Similarly, during the OFF cycle shown in Fig. 4.19(c), the collector voltagesV
C
andV
mid
can be determined from
82 (; 2)
8
>
>
>
>
<
>
>
>
>
:
V
C
() +!
2
L
1
C
OFF2
d
2
V
C
()
d
2
=V
CC
+!L
1
P
k=K
k=1
kI
Rk
cos(k +
k
);
d
d
V
mid
() =
1
!C
mid
P
k=K
k=1
I
midk
sin(k +
midk
):
The solution for the stacked PA switch voltages V
C
and V
mid
, can be obtained from,
8
>
>
>
>
<
>
>
>
>
:
V
C
() = 0;82 (0;)
V
C
() +
1
q
2
d
2
V
C
()
d
2
=V
CC
[1 +
P
k=K
k=1
kp
k
cos(k +
k
)];82 (; 2)
(4.58)
and
8
>
>
>
>
<
>
>
>
>
:
V
mid
() = 0;82 (0;)
V
mid
() =q
2
bottom
P
k=K
k=1
1
k
[cos(k +
midk
) +cos
midk
]:82 (; 2)
(4.59)
The collector-emitter voltages of the HBTs are then found from,
8
>
>
>
>
<
>
>
>
>
:
V
CE2
() =V
C
()V
mid
();
V
CE1
() =V
mid
():
(4.60)
Compared to the non-stacked Class-EF
y
x
case, the stacked composite waveform Class-K
PA with K harmonic control for both the bottom and top transistors depends on `4K
0
variables requiring total of `4K
0
equations (2K for each of the 2-stacked HBTs). The
collector voltages and switch currents of the individual stacked transistorsQ
1
andQ
2
can
176
be solved using the non-zero ZVS and ZdVS boundary conditionsA
1
andA
2
for both top
and bottom transistors individually along with the (K-1) harmonic loading conditions
Z
Lk
and Z
midk
8 k 2 (2;K) to uniquely determine the contribution of the harmonic
amplitudes p
k
and p
midk
and harmonic phases
k
and
midk
.
The performance metric for the stacked Class-K composite power amplier can be
determined in terms of transistor technology parameters. In the previously discussed
stacked Class-EF
y
x
PA of Section 4.3.1, the collector voltage of the bottom transistor is
a fraction of the overall collector voltage according the capacitive division ration V
mid
=

V
C
. In the proposed Class-K PA, the collector voltage of the bottom transistor is
determined by the non-ZVS boundary conditions for the bottom transistorA
b
1
andA
b
2
as,
V
CE1
() =V
mid
() =V
CC
[0:5A
b
1
(1 +cos)A
b
2
sin]; (4.61)
The bottom transistor collector voltage thus can always be set to reachBV
CBO
, resulting
in improved output power compared to non-stacked switching PAs for the same transistor
breakdown voltages. In addition, the switch current in each of the series stacked HBTs
can be individually designed so that a larger switch capacitance (and thus larger transistor
size) can be used and hence conduction loss may be lowered. Thus, unlike the eciency
equation for the stacked switching PAs in Eqn. 4.44, where the eciency degrades linearly
177
with the number of stacked transistors, for the proposed Class-K PA, the output power
and eciency are given by
8
>
>
>
>
<
>
>
>
>
:
P
out
= 4
BV
2
CBO
R
Load

2
;

StackedClassK
max
=
1
1+
Switch1
!out+
Switch2
!out+
Capacitive1
(A
t
1
)
2
+
Capacitive1
(A
b
1
)
2
:
(4.62)
In this equation,
Switch1
and
Switch2
are the eciency constants of the bottom and top
transistors, Q
1
, and Q
2
, respectively. A
t
1
and A
t
2
are the ZVS and ZdVS boundary con-
ditions for the top transistor. By choosing the right harmonic loading terminations, Z
Lk
andZ
midk
, it can be ensured that
Switch1
+
Switch2
< 2
Switch2
(1 +
C
OFF2
C
OUT
) resulting
in eciency improvement in the Class-K PA over the stacked Class-EF
y
x
ampliers.
30 GHz SiGe HBT Stacked Class-K Power Amplier
To demonstrate the operation of stacked switching PAs with harmonic load control at
mm-wave frequencies, a 30 GHz, 2-stacked, Class-K dierential amplier is designed
(Fig. 4.22(a)). The dierential architecture eliminates the need for lossy DC blocking
capacitors in the harmonic load networks of Q
1
and Q
2
. Parallel tanks resonant at the
fundamental 30 GHz frequency are added to the harmonic load networks ofQ
2
to prevent
fundamental load current from circulating in the harmonic load networks. The harmonic
load network of the top transistor presents an open-circuit at the 3rd harmonic resulting a
much
atter Class-EF type waveform for theQ
2
collector-emitter voltageV
CE2
as shown
in Fig. 4.22(b). The harmonic load network of the bottom transistor Q
1
presents an in-
ductive load at the fundamental component, resulting in a half sinusoidal collector-emitter
178
Figure 4.20: 30 GHz dierential 2-stacked Class-K amplier, (a) circuit schematic,
(b) simulated transient collector voltage and current waveforms, (c) simulated per-
formance assuming ideal passives.
voltage V
CE1
as shown in Fig. 4.22(b). The proposed Class-K architecture has several
advantages over the stacked Class-EF
y
x
ampliers. Firstly, in the 2-stacked Class-E=F
2;3
amplier of Fig. 4.17, the parasitic collector-bulk capacitor C
OFF2
of the top transistor
Q
2
, limits the size of Q
2
transistor that can be chosen while still satisfying the overall
collector capacitance budget C
eq
(Eqn. 4.52). Choosing a smaller size Q
2
(compared to
the bottom transistor Q
1
) leads to higher conduction loss in the top device. In contrast,
in the Class-K architecture, the absence of the coupling capacitor C
OUT
and presence
of the mid-node load network, Z
midk
, decouple the operation of the series stacked HBTs
179
Q
1
and Q
2
from each other in the OFF state as shown in Fig. 4.19(c). This decoupled
operation ensures that the sizes ofQ
1
andQ
2
can be chosen such that both collector-bulk
capacitorsC
OFF1
andC
OFF2
equal to the collector capacitance budgetC
OFF
of the non-
stacked operation (Eqn. 4.33). Both the stacked transistors can thus be chosen to be of
equal size (Fig. 4.22(a)) resulting in lower conduction loss and eciency improvement.
Secondly, in capacitively coupled stacked Class-EF
y
x
ampliers, the unequal voltage divi-
sion between the top and bottom transistors due to presence of the parasitic capacitors
C
B2
andC
OFF2
, limits
=
V
mid
V
C
< 0.5 and reduces power generation capability from the
stacked architecture (Eqn. 4.54). In the stacked Class-K architecture, the presence of
the mid-node load network ensures that the mid-node voltage V
mid
always reaches the
maximum allowable BV
CBO
voltage. Thus, the collector-emitter voltages of the stacked
HBTs can beV
CE1
=V
CE2
BV
CBO
, resulting in improved power generation capability
in the stacked Class-K architecture for the same silicon technology process. Compared
to the stacked Class-E=F
2;3
amplier of Sec. 4.3.1.1, the 2-stacked dierential Class-K
PA generatesP
out
= 27 dBm,G
P
= 12 dB, = 70% andPAE = 67 % (Fig. 4.22(c)).
Practical implementation of such harmonic controlled PA, must also account for ad-
ditional conduction loss arising from the nite quality passives in the harmonic load
networks connected to the collectors of Q
1
and Q
2
. Fig. 4.21 shows performance degra-
dation at various stages of the Class-K design. It can be observed that the collector
eciency degrades due to the nite Q-factor of the collector inductanceL
1
(Fig. 4.21(b))
as well as that of the harmonic load networks (Fig. 4.21(c)). On including the loss of the
180
Figure 4.21: Performance degradation of various design stages of a 30 GHz, 2-
stacked dierential, Class-K amplier : Complete HBT model (layout parasitics)
and ideal passives, (b) nite quality factor for collector inductance L
1
(Q
ind
= 15),
(c) Finite quality factor for the harmonic load network components (Q
ind
= 15,
Q
cap
= 35), (d) Adding input driver stage and impedance matching network.
Figure 4.22: Schematic and die microphotograph of the two-stage two-stacked dif-
ferential Class-K amplier.
181
Figure 4.23: Performance of the two-stage two-stacked, dierential, Class-K ampli-
er, (a) output power and power gain versus input power at 34 GHz, (b) saturated
output power and corresponding PAE versus frequency, (c) collector eciency ver-
sus output power, (d) power added eciency versus output power.
on-chip passives, the collector eciency for the stacked switching PAs can be expressed
as,

StackedClassK
max
=
1
1 + 6:7!
out
+ 2:3!
out
+
5:8
Q
L1
+
4
Q
mid
+
4:65
Q
HarmonicNetwork
;
(4.63)
whereQ
L1
15 andQ
mid
15 are the quality factors of theL
1
andL
mid
inductances, and
Q
HarmonicNetwork
15 is the equivalent quality factor of the harmonic load network. The
schematic and die microphotograph of the two-stage stacked Class-K amplier fabricated
in a 130 nm SiGe BiCMOS process are shown in Fig. 4.22. The large signal performance
of the implemented design, shown in Fig. 4.23 demonstrate a measured output power
182
Table 4.1: Performance Comparison with selected K-band Silicon Power Ampliers
of 25.4 dBm, large signal power gain of 13 dB and eciency of 28%, and power added
eciency of 26% respectively.
The performance of the implemented two-stage 2-stacked Class-E=F
2;3
amplier and
the two-stage 2-stacked Class-K amplier are summarized in Table 4.1. Compared to
previously published work at similar frequency range [22,41,44,81,82], the implemented
ampliers demonstrate higher output power with a somewhat similar power eciency.
4.3.3 Eciency Improvement in Stacked PAs
The proposed Class-K amplier architecture with independent harmonic load networks at
the collector of each series-stacked transistor can be generalized for more than two stacked
HBTs. As discussed in Sec. 4.3.2, independent harmonic load networks attached to the
collector of the series connected transistors can be used to improve the eciency and
183
Figure 4.24: 30 GHz 2-stacked Class-K amplier, (a) circuit schematic, (b) simu-
lated transient collector voltage and current waveforms, (c) simulated performance
assuming ideal passives.
Figure 4.25: 30 GHz 3-stacked Class-K amplier, (a) circuit schematic, (b) simu-
lated transient collector voltage and current waveforms, (c) simulated performance
assuming ideal passives.
184
Figure 4.26: 30 GHz 4-stacked Class-K amplier, (a) circuit schematic, (b) simu-
lated transient collector voltage and current waveforms, (c) simulated performance
assuming ideal passives.
output power of the 2-stacked ampliers as shown in Fig. 4.24 for a single-ended design.
Similar strategy for eciency and power improvement can be employed for more number
of series stacked transistors as well. In fact, the improvement oered by having additional
harmonic networks can become larger with increased number of stacked devices. Two
design examples, a 3-stacked and a 4-stacked 30 GHz, Class-K ampliers are shown in
Fig. 4.25(a) and Fig. 4.26(a), respectively. The transient waveforms of Fig. 4.25(b) and
Fig. 4.26(b) show that the collector voltage in each stacked HBT for both designs can
reach close to BV
CBO
, resulting in improved output power generation compared to the
2-stacked design.
185
Table 4.2: Glossary of Generalized Switching Amplier Analysis
4.4 Conclusion
In this chapter, a generalized analysis of various switching amplier classes is oered
for both stacked and non-stacked transistor architecture. The design space of mm-wave
Class-E ampliers is explored by considering non-zero ZVS and ZdVS boundary condi-
tions that oer eciency and power enhancements. Eect of controlling the load termi-
nation of `K
0
harmonics in a switching amplier for waveform engineering is also studied
in the context of Class-E/F family of ampliers. This concept is extended to stacked
designs as well. Finally, a new class of stacked Class-K ampliers is proposed capable
of supporting independent voltage and current waveforms in the stacked transistors re-
sulting in eciency and power improvement. Proof-of-concept prototypes implemented
in a 130nm SiGe BiCMOS process validate the eectiveness of the proposed schemes and
design steps.
186
Chapter 5
Watt-level Mm-Wave Digital Power Ampliers
In the previous chapters, various switching amplier architectures were discussed to gen-
erate 20-23 dBm output power with high eciency at millimeter-wave frequencies
using silicon technologies. These power-ecient ampliers can now be used in a power-
combined system to generate Watt-level output power and support mm-wave wireless
links over reasonable distances. It is desirable that such Watt-level transmitters be capa-
ble of supporting high data-rates (e.g., exceeding 10 Gbps) using complex modulations
over wide bandwidths. Commercial wireless devices can transmit over 1 Gbps using
around 100 MHz at radio frequencies below 6 GHz. Recent eorts at \Watt-level" power
generation in both silicon CMOS and HBT technologies [22, 44, 69, 83] have relied on
large-scale combining of< 20 dBm unit cells with< 10% overall Power-Added-Eciency
(PAE). Integrated mm-wave power DACs capable of supporting modulation and power
control [43, 44] have been reported with even lower output power ( 24 dBm) and av-
erage PAE (< 7%). Demonstrating \Watt-level" (P
out
30 dBm) power ampliers and
high-speed digital transmitters with high eciency (> 20%) is still a research challenge.
187
Figure 5.1: A N-stage mm-wave Class-E amplier chain with either a non-stacked
Class-E or a stacked Class-E as the output stage.
5.1 Watt-level Power Amplication in Silicon
This chapter discusses various power combining techniques using the switching ampliers
discussed in previous chapters, to achieve ecient Watt-level mm-wave digital power
ampliers and transmitters. Since switching ampliers utilizes the SiGe HBT transistors
as gain compressed switches, the large signal power gain from each switching amplier
stages can be pretty low ( 4-6 dB including matching network losses) at mm-wave
frequencies. For the power-combined Watt-level amplier/transmitter to have enough
overall power gain, multiple amplier stages need to be used in each of the power-combined
switching PA chains. The eciency of each of these driver ampliers can aect the
overall system performance and needs to be analyzed. On-chip power-combining schemes
at mm-wave frequencies also can be lossy; as such, the power combining architecture
needs to be studied for optimum performance. The performance limits of single-stage
Class-E and stacked Class-E ampliers has been discussed in previous chapters. Utilizing
these performance limits, and the achievable performance of on-chip power combiners, the
eciency limits for Watt-level power ampliers at mm-wave frequencies will be discussed.
188
5.1.1 Multi-Stage Class-E Amplier Chain
Switching ampliers like Class-E, enable high power, highly ecient power ampliers at
mm-wave frequencies by ensuring non-overlapping collector voltage and current wave-
forms [41]. Mm-wave Class-E design equations have been extensively analysed in [41]
(and Chapter 2) to provide power amplier performance metrics like output power P
out
,
power gainG
P
, collector eciency and power-added eciency PAE versus frequency of
operation! and load terminationR
Load
. For the 0.13m SiGe BiCMOS process used for
demonstrating a \Watt-level" power amplier in this chapter, the technology parameters
from Table 2.1 can be used in Eqn. 2.36 to simplify the performance metrics for a single
stage Class-E power amplier as
8
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>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
ClassE
out;max
=
3:7
R
Load
;

ClassE
max
=
1
1+4:6!out
;
G
ClassE
P;max
=
65:510
12
![ln(!)20:5]
2
;
PAE
ClassE
max
= (1
1
G
ClassE
P;max
)
ClassE
max
:
(5.1)
At 45 GHz, using ideal passive components for input and output matching network,
this translates into G
P
= 8.0 dB, = 70% and maximum achievable PAE = 62% for
dierent output power levels.
Stacking of transistors in a Class-E conguration is another technique to increase
both output power and power gain at mm-wave frequencies in a low breakdown voltage
silicon process [41] (and Chapter 3). The performance metrics for the double-stacked
189
single stage Class-E design as shown in Eqn. 3.2 and 3.3 can be simplied by using the
technology parameters of Table 2.1 for the 0.13 m SiGe BiCMOS process as
8
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>
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>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
StackedClassE
out;max
=
1
(1
)
2
P
ClassE
out;max
;

StackedClassE
max
=
1
1+24:6!out
;
G
StackedClassE
P;max
=
65:510
12
!(1
)
2
[ln(!)20:5ln(1
)]
2
;
PAE
StackedClassE
max
= (1
1
G
StackedClassE
P;max
)
StackedClassE
max
:
(5.2)
At 45 GHz,
=
V
mid
Vc
0.33 leading to 3.5 dB output power improvement over a non-
stacked Class-E design with G
P
= 11.3 dB, = 55% and maximum achievable PAE =
51%. AssumingR
Load
= 50
, the calculated maximum output power of the Class-E and
the double-stacked Class-E ampliers are around 18.7 dBm and 22.2 dBm respectively.
For \Watt-level" power generation with moderate passive power combining on a single
chip, several of these 20 dBm - 23 dBm unit Class-E ampliers must be power combined.
To enable sucient gain for the entire power combined system, the single-stage Class-
E and stacked Class-E power ampliers need to be cascaded with driver ampliers. In
Chapter 3, we had concluded that for P
out
< 20 dBm, non-stacked Class-E ampliers
have better performance than stacked Class-E ampliers and thus the low power driver
ampliers have all been chosen to be non-stacked Class-E design. For a multi-stage Class-
E amplier chain, the losses in the input matching, output matching and inter-stage
matching network with nite quality factor passive component become signicant. Fig.
5.1 shows the schematic of a N-stage mm-wave Class-E amplier chain with theK
th
stage
amplier metrics denoted as load resistance R
L;K
, input resistance R
B;K
, output power
190
P
out;K
and input powerP
in;K
. The losses in the matching networks are denoted asOM for
the nal stage output matching network, IM for the rst stage input matching network
and MM
K
for the K
th
inter-stage matching network. The performance metrics of the
N-stage (all non-stacked) Class-E amplier chain shown in Fig. 5.1 can be summarized
as follows :
8
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>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
NStage
out;max
=OMP
ClassE
out;max
;
G
NStage
P;max
= [G
ClassE
P;max
]
N
OMIMMM
N1
MM
N2
:::::MM
2
;

NStage
max
=

ClassE
max
OM
1+
1
[G
ClassE
P;max
]MM
N1
+
1
[G
ClassE
P;max
]
2
MM
N1
MM
N2
+:::
1
[G
ClassE
P;max
]
N
MM
N1
MM
N2
:::MM
2
;
PAE
NStage
max
= (1
1
G
NStage
P;max
)
NStage
max
:
(5.3)
When the nal output-stage amplier is a stacked Class-E PA driven by non-stacked
Class-E drivers (Fig. 5.1), the performance metric for that amplier chain conguration
can be similarly derived and summarized as :
8
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>
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>
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>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
P
NStage
out;max
=OMP
StackedClassE
out;max
;
G
NStage
P;max
= [G
StackedClassE
P
] [G
ClassE
P
]
N1
OMIMMM
N1
MM
N2
:::::MM
2
;

NStage
max
=

StackedClassE
max
OM
1 +

StackedClassE
max

ClassE
max
[G
StackedClassE
P;max
]MM
N1
+:::

StackedClassE
max

ClassE
max
[G
StackedClassE
P;max
][G
ClassE
P;max
]
N1
MM
N1
MM
N2
:::MM
2
;
PAE
NStage
max
= (1
1
G
NStage
P;max
)
NStage
max
:
(5.4)
191
In both the cases, the expressions for the two-element matching network losses in the
input-stage, output-stage and inter-stage matching networks are given by [84],
8
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>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
:
OM =
1
1+
2
Q
Passive
r
R
Load
R
L;N
1
;
MM
K :K21:N1
=
1
1+
2
Q
Passive
r
R
L;K
R
B;K+1
1
;
IM =
1
1+
2
Q
Passive
r
R
Source
R
B;1
1
:
(5.5)
The aforementioned expressions, assuming a realizable passive quality factor Q
Passive

15 at 45 GHz, are used to plot the performance metrics of a 3-stage power amplier
chain both with a non-stacked Class-E and a stacked Class-E output stage at 45 GHz for
dierent values of nal-stage load resistance R
L;3
(Fig. 5.2(a)). In this comparison, the
losses of all the matching networks (input, inter-stage and output for non-50
R
L;3
) have
been considered. It can be observed that even though the individual collector eciency
(55%) of the stacked Class-E amplier is lower than that of a non-stacked Class-E design
(70%) at 45 GHz, the 3.5 dB power improvement in a stacked design, enables the stacked
Class-E amplier chain conguration to achieve better PAE for the same output power
levels > 20 dBm compared to a non-stacked Class-E amplier chain. In the subsequent
section for Watt-level power generation at mm-wave frequencies, the maximum achievable
system performance by passive power combining of the stacked Class-E amplier chains
will be discussed.
192
Figure 5.2: Simulated performance comparison of 3-stage power amplier chains
where the last stage is either Class-E or double-stacked Class-E amplier, (a) Max-
imum achievable output power (P
out
) and power gain (G
P
) at 45 GHz versus load
resistance of the output stage (R
L;3
), (b) Maximum achievable PAE vs P
out
.
5.1.2 Watt-Level mm-Wave Power Combining
Transmission line based power combining schemes may be utilized at mm-wave frequencies
to achieve Watt-level power using the power amplier chains discussed in the previous
section. At the same time, to achieve output waveforms of dierent amplitude levels (for
multi-level bit transmission), a power control scheme in the transmitter is necessary by
dynamically turning ON/OFF the dierent amplier chains that are contributing to the
overall power-combined output. In such digital power ampliers with independent control
of individual amplier chains, isolation between the dierent amplier arms is critical to
maintain eciency at power back-o. Hence, the power combining structure is limited
to isolating quarter wavelength (/4) power combiners. Such quarter wavelength (/4)
transmission line segments are especially useful in preventing load-pulling in digital power
ampliers as will be discussed in Section 5.3. In this section, for power combining at the
193
Figure 5.3: (a) An M-stage power combining of M mm-wave Class-E PA chains
using 2-way 50
Wilkinson combiners (b) power combining of M mm-wave Class-
E PA Chains using an M-way 50
Wilkinson combiner.
194
Figure 5.4: (a) A 70
micro-strip transmission implemented in the 0.13 m SiGe
BiCMOS process, (b) simulated insertion loss of the 70
micro-strip transmission
line versus frequency.
output and power splitting at the input, the power combining eciency of a corporate M-
Stage Wilkinson power-combiner architecture (Fig. 5.3(a)) [84] is compared to a M-Way
Wilkinson power-combiner (Fig. 5.3(b)) [84] to determine the optimum conguration of
combiners and amplier chains for Watt-level power generation with highest PAE at mm-
wave frequencies. For ease of comparison, each power combiner structure is assumed to be
designed for 50
input and output impedance and as such can be directly used by the 50

input-output Class-E amplier chains discussed previously. For the 50
input-output
binary Wilkinson combiner architecture in Fig. 5.3(a), 2
M1
2-way 50
Wilkinson power
combiners, each with 70
/4 micro-strip transmission lines are used. The simulated
insertion loss for a 70
on-chip micro-strip transmission line versus frequency is shown
in Fig. 5.4. To realize an M-stage corporate Wilkinson combiner structure, a cascade of
2-way 50
Wilkinson combiners each realized with this 70
/4 will be used.
For the M-way Wilkinson power-combiner,M quarter wavelength (/4) transmission
line segments each with transmission line characteristic impedance Z
C
= 50
p
M must be
195
used. Fig. 5.5(a) shows the simulated insertion loss of the /4 micro-strip transmission
line for dierent values of characteristic impedance Z
C
at 45 GHz. It can be observed
that for the signal and ground plane metal options chosen in Fig. 5.4(a), the insertion
loss of the quarter wavelength transmission line increases with higher impedance due
to the increase of ohmic resistance of thinner metal traces that are needed to realize
higher Z
C
. Fig. 5.5(b) shows the insertion loss comparison of the corporate M-Stage
Wilkinson combiner with the M-Way Wilkinson combiner at 45 GHz. It can be observed
that while for moderate combining < 4:1 combining, the M-way combiner seems to have
better power combining eciency, for higher combining ratios, the high insertion loss of
highZ
C
transmission lines make M-stage corporate combiners a more amenable solution.
Interestingly as shown in Fig. 5.5(b), for higher combining ratios, a hybrid solution of 2-
way and 4-way solution for 8:1 combining lead to highest combining eciencies. Likewise,
a cascaded connection of 4-way combiners results in a lower insertion loss, compared with
the aformentioned approaches, for 16-way power combining. The overall system output
powerP
out
and PAE of a 1-Watt power combined system is shown in Fig. 5.5(c). It can be
observed that while individual PA chains with smaller output power have higher eciency
(Fig. 5.2), on including the combiner loss for large-scale combining, the overall PAE for 1-
way (single amplier chain without power combining) to 8-way combined system remains
approximately constant over dierent combining ratios. Beyond 16:1 combined systems,
the overall PAE drops as the power combiner loss becomes dominant.
Even though, from the preceding analysis, a single-chain amplier (without power
combining) results in same performance as a 8-way power combined system for 1-Watt
power generation at 45 GHz, there are several reasons for preferring the latter. Firstly, a
196
Figure 5.5: (a) Simulated insertion loss of quarter wavelength micro-strip trans-
mission line at 45 GHz versus transmission line characteristic impedance (Z
C
) (b)
simulated power combiner loss for dierent combining ratios using M-stage or M-
way or a hybrid combiner architecture, (c) overall P
out
and PAE for the power
combined 1-Watt mm-wave Class-E power amplier.
single Watt-level Class-E PA chain requires very large SiGe HBT transistors for the nal
output stage. The large collector-base capacitances (C

) of these large HBTs reduces
the reverse isolation signicantly and lead to stability concerns. For practical implemen-
tations, small and large signal stability of such large transistors is usually mitigated by
resistive ballasting at the base. Since the base resistanceR
B
of these large transistors are
very small, any base ballasting further reduces the power gain of the stage and lead to fur-
ther degradation of the PAE (not captured in the simplied analysis leading to Fig. 5.5).
Secondly, since for the Class-E amplier chains, the R
B
of the nal output stage need to
matched toR
L
of the previous stage using inter-stage matching, the very smallR
B
of the
> 27 dBm unit output stages, makes the inter-stage networks extremely narrow-band and
prevents high-speed data transmission with large instantaneous bandwidths. An overall
narrow-band response of the PA chains is not suitable for the high data-rate transmitter
197
Figure 5.6: Simplied schematic of a mm-wave digital polar transmitter (DPT).
applications. Finally and most importantly, in most applications, the mm-wave trans-
mitter must support amplitude and phase modulation. Switching Class-E ampliers can
only generate two amplitude levels depending whether they are turned `ON' or `OFF'.
The output power of switching ampliers may be modulated by modulating the supply
voltage. However, this comes at eciency degradation and challenges associated with
wide-band supply modulators. On the other hand, digital power amplier architecture
consisting of several power-combined amplier chains that may be turned `ON' or `OFF'
independently, can also support digital amplitude modulation with high power eciency.
To support many amplitude levels needed to create complex constellations (e.g., 1024
QAM) larger number of independently controlled amplier chains is preferred. However,
keeping in mind the trade-o of system PAE with higher combining ratios, an optimum
8:1 power combined Watt-level mm-wave power amplier has been chosen for implemen-
tation in the next sections. Complementary techniques such as pulse-width or delta-sigma
modulation may be used to enhance the amplitude modulation capacity.
198
5.2 Data Transmission in Switching Ampliers
High-speed data transmission at mm-wave frequencies may be achieved by using quadra-
ture amplitude modulation (QAM) schemes in linear power ampliers [85{87]. However,
the low eciency of mm-wave linear power ampliers at both peak and backed-o power
levels under QAM modulation signicantly degrades the overall transmitter eciency.
Millimeter-wave digital polar transmitters (DPT) may enable high transmitter eciency
while supporting several Gb/s of data-rate at mm-wave frequencies [21]. A simplied
mm-wave digital polar transmitter architecture is shown in Fig. 5.6. In a DPT, the
baseband QAM information is separated into amplitude and phase information using a
cartesian-to-polar converter. The separated phase information is then phase modulated
into the mm-wave carrier frequency. The resulting constant envelope phase modulated
signal can then be amplied by the highly ecient mm-wave switching power ampliers.
To support amplitude modulation, the amplitude information is utilized to control how
many of the phase modulated switching power ampliers need to be activated so that the
envelope of the overall power combined phase modulated waveform tracks the baseband
QAM input. The important blocks of a mm-wave digital polar transmitter scheme are
the mm-wave switching \Power Modulators" that are capable of turning ON-OFF fast to
support rapid amplitude modulations, the ecient output power combiner, and the high-
speed phase modulator. The mm-wave switching \Power Modulators" [88] are discussed
in the next section.
199
Figure 5.7: Representative simulated large signal transfer curves of mm-wave
stacked Class-E ampliers, (a) P
out
vs. P
in
, (b) I
DC
vs. P
in
.
5.2.1 mm-Wave Class-E Power Modulator
The operation of the proposed switching power modulator relies on the switching nature
of the Class-E amplier P
out
-P
in
transfer curve. As shown in Fig. 5.7(a), if the input
power to a stacked Class-E amplier can be attenuated by 10 dB, the output power
drops by 40 dB, eectively shutting down that particular Class-E amplier. A Class-
E amplier chain comprising of cascade of several such Class-E ampliers has an even
sharper P
out
-P
in
transfer curve, similar to a digital inverter. More importantly as shown
in Fig. 5.7(b), the DC current consumption under large signal operation in a Class-E
amplier tracks the output power. Hence, when a mm-wave Class-E power amplier is
shut down by reducing the input power, the DC current drawn from the supply becomes
negligible. The I
DC;Quiescent
0 feature is extremely important in maintaining high
average eciency in a DPT as little DC power is dissipated in amplier chains that are
200
Figure 5.8: 1-bit mm-wave Class-E power modulator architecture : (a) simplied
schematic, (b) detailed schematic.
not generating power. In contrast, linear mm-wave ampliers with signicant quiescent
current need to have supply switching schemes for application in a DPT architecture.
Supply switching schemes lead to eciency degradation due to presence of switch ON-
resistance in the collector current path, and digital power dissipation, when the large
supply switches need to be modulated at a higher speed [89]. In comparison, the small
switches used at the input of the Class-E ampliers only marginally degrade the power
gain of the system and dissipate less digital power under high speed switching. Fig.
5.8(a) shows a simplied schematic of the input-modulated Class-E power modulator,
while a detailed schematic including several features for enhanced operation at mm-wave
frequencies is highlighted in Fig. 5.8(b). The ON and OFF state equivalent circuits for
the mm-wave Class-E power modulator is shown in Fig. 5.9. During the ON-state of Fig.
5.9(a), the series input switch (M
INSW1
) turns ON, allowing the input signal to reach
the input of the stacked Class-E PA with minimal insertion loss. The input signal is then
amplied eciently by the mm-wave PA. The stacked output switches (M
OUTSW1;2
)
201
which are turned OFF for this mode, are designed with thick oxide FETs to sustain the
high voltage swing at the PA output. The OFF-state capacitance of the output switches
are included in the Class-E PA design. In the OFF state of Fig. 5.9(b), the input
series switch (M
INSW1
) is turned OFF isolating the PA input from the mm-wave input
signal. A low impedance shunt complementary switch (M
INSW2
) is turned ON to sink
the incident power providing better isolation and also to ensure decent input matching
under OFF condition. Since the input signal reaching the PA input is attenuated, it is
insucient to switch the Class-E ampliers ON resulting in negligible power generation
and voltage swing at the output. The isolation of the series input switch (M
INSW1
) is
enhanced by resonating out the o capacitance, C
OFF
, with a parallel inductorL
Parallel
.
The output switches (M
OUTSW1;2
) are turned ON, shorting a large capacitor, C
OUT2
,
to ground, further increasing the extinction ratio (
P
out;ON
P
out;OFF
). In the OFF mode, since the
Class-E amplier does not turn ON, no DC current is drawn from the supply ensuring
that the average PAE is not aected by the ideal state DC consumption. Choosing the
right MOSFET sizes for the input and output switches is an important design criteria in
the speed versus insertion loss trade-o [88] and discussed in the implementation section.
The simulated transient waveforms under 1-bit ASK modulation at 1 Gb/s is shown in
Fig. 5.10. The large transient spikes and the resultant ringing in the DC current are
primarily due to the wire-bond inductances of the supply pads. At suciently high data-
rates, the transient ringing may prevent the DC current from following the bit-pattern
resulting in higher average power consumption and lower average eciency. Sucient
on-chip DC bypass capacitors are needed to mitigate this issue. The 1-bit Class-E power
modulator implementation details and measurement results are discussed next.
202
Figure 5.9: 1-bit Class-E modulator equivalent circuit, (a) ON-state, (b) OFF-state.
Figure 5.10: Simulated large signal transient waveforms of the Class-E modulator,
(a) Input control-bit and output voltage vs. time, (b) I
DCSupply
vs. time.
203
Figure 5.11: Schematic and chip microphotograph of 1-bit mm-wave Class-E power
modulator.
5.2.2 Q-band Class-E Modulator Implementations
To demonstrate, high speed data transmission using an input modulated Class-E power
modulator, a high speed 1-bit 3-stage Class-E power modulator is implemented in the
0.13 m SiGe BiCMOS process using the SiGe HBTs for the power amplier core and
the 130nm CMOS FETs for digital control of the input and output switch networks.
The schematic and die microphotograph for the Class-E power modulator with all the
component values are shown in Fig. 5.11. The FET switches at the input and output of
Class-E modulator as well as the on-chip digital CMOS drivers for driving these switches
204
Figure 5.12: (a) Input switch network schematic, (b) isolation and insertion loss
trade-o vs. frequency and M
INSW1
switch size.
have been carefully designed to ensure an optimum trade-o between insertion loss, speed
of data transmission and digital power consumption. The design of the series input switch
network (Fig. 5.12(a)) is important in realizing high modulation speed, low insertion loss
in the ON state and high signal isolation in the OFF state. In particular, the isolation
of the series input switch (M
INSW1
) is enhanced by resonating out the o capacitance
by using a shunt inductance L
Parallel
= 60 pH. The enhancement of isolation in the
frequency band of interest is shown in Fig. 5.12(b). The size of the series input switch
M
INSW1
also need to be carefully chosen to ensure good trade-o between insertion
loss and isolation. A 250 m nger width is chosen based on the 1.2 dB of insertion loss
when the series switch is ON and at least 20 dB of signal isolation when the series switch
is OFF as shown in Fig. 5.12(b). A shunt complementary switch M
INSW2
ensures the
input matching is always maintained under modulation.
To enhance the extinction ratio of the ON-to-OFF amplitudes, a stacked switch
scheme implemented using thick-oxide MOSFETs is used to further attenuate the output
205
Figure 5.13: (a) Output switch network schematic, (b) isolation and insertion loss
trade-o vs. frequency and M
OUTSW1;2
switch size.
amplitude during the OFF state as shown in Fig. 5.13(a). Choosing the right MOSFET
sizes for the output switches is also an important design criteria in the isolation versus
insertion loss trade-o as shown in Fig. 5.13(b). Output stacked switches, each of to-
tal size 100 m nger width is chosen to ensure 6-7 dB additional extinction ratio at
the cost of 0.7 dB insertion loss. A high ON/OFF extinction ratio is needed to ensure
proper identication of `1' and `0' bit in a 1-bit modulation. In presence of any inter-
symbol-interference and other non-idealities, a higher ON/OFF extinction ratio results
in better eye-diagram (and BER) in a 1-bit ASK modulation. The quality and bit error
rate of an 1-bit ASK modulation is determined by a quantity known as \Quality Factor"
dened as Q =
j
1

0
j

1

0
, where
1
and
0
are the average values of the `1' and `0' bit
levels and
1
and
0
are the standard deviations of the `1' and `0' bit levels due to bit
transmission non-idealities [90]. The BER for 1-bit ASK modulation is given by BER =
0.5erfc(
Q
p
2
) [90]. A higher ON/OFF extinction ratio ensures a much larger
1

0
and
thus higher Q-factor and better BER for the same
1

0
transmission non-idealities.
206
Figure 5.14: 1-bit Class-E modulator large signal measurements under ASK mod-
ulation at 46 GHz, (a) measured transient waveform, (b) recovered eye-diagram at
500 Mb/s and 1.25 Gb/s, (c) average P
out
and PAE versus modulation speed.
For achieving BER of 10
12
or better, Q-factor 7, requiring the extinction ratio to
approach 40 dB [90].
Under static continuous wave operation, the measured peak output power is 21.8
dBm with 18.5% peak PAE at 46 GHz [88]. A representative 1-bit ASK modulated
dynamic operation is shown in Fig. 5.14(a) where the transient waveform at 46 GHz
carrier frequency captured using a sampling oscilloscope demonstrates a rise and fall
times of 450 ps and 250 ps, respectively. The measured ON/OFF extinction ratio from
Fig. 5.14(b) is estimated to be 30 dB. The reconstructed eye-diagram obtained by down-
converting the modulated waveform is shown in Fig. 5.14(b) under 500 Mb/s and 1.25
Gb/s 1-bit ASK modulation. The power modulator was tested under dierent data rates
and the captured measured bit-streams was post-processed using MATLAB commscope-
eyediagram toolbox [91] to estimate the BER to be 1:6 10
10
at 500 Mb/s, 0:9 10
6
207
at 1 Gb/s, 1:53 10
6
at 1.25 Gb/s. The average power measurements under dierent
modulation speeds is shown in Fig. 5.14(c) and shows 3 dB lower measured power
corresponding to 50% duty cycle and PAE varying between 12% and 10% for dierent
modulation speeds. The measured average eciency is lower than the peak eciency
under continuous wave measurement due to the additional power consumption of the
digital drivers while the measured average PAE is also degraded due to the 3 dB lower
power gain under 50% duty cycle ASK modulation.
5.3 Mm-Wave Watt-Level Digital Power Amplier
Load impedance variation also known as \load-pulling" is a common unwanted phe-
nomenon in power amplier designs and can lead to lower output power, higher power
dissipation, increased adjacent channel power leakage due to reduced linearity, and insta-
bility and transistor breakdown. Load-pulling in traditional I-Q transmitters using linear
ampliers typically arises from the antenna impedance mismatch and as such, much eort
is put into designing ampliers that are more robust to load impedance variation at the
cost of reduced eciency. In the proposed mm-wave DPT using switching power modula-
tors, as various amplitude levels are generated at the output, the code dependent voltage
and current variation in the combining nodes creates variation in the load impedance pre-
sented to the unit power modulators. This power dependent load modulation, a unique
feature of the proposed DPT, aects the design of output power combiner as discussed
next.
208
Figure 5.15: Power control by 8-way /4 load modulation, (a) peak power opera-
tion, (b) power back-o operation when m out of 8 unit PAs are active, (c) variation
of Z
PA
with power back-o.
5.3.1 Load-Pulling in Class-E
To realize a mm-wave Watt-level digital power amplier with several output amplitude
levels, several of the 1-bit Class-E power modulators can be power combined using the
M-way combiner schemes discussed previously. However, since each of the Class-E power
modulators in this power-combined system needs to be independently turned ON-OFF
to realize the discrete output amplitudes, the common mode resistors in the M-stage cor-
porate Wilkinson combiner or the M-way/4 Wilkinson combiner need to be removed as
otherwise they will dissipate a signicant portion of the generated power during the un-
balanced combining modes of amplitude modulation. One such power combining scheme
was demonstrated in [44] where 8 Class-E power ampliers were power combined using a
/4 combining scheme as shown in Fig. 5.15. In this approach, power back-o is achieved
by switching OFF some of the unit PA chains and then shorting those /4 transmission
line branches, so that active unit PAs are isolated from the inactive ones (Fig. 5.15(b)).
One major disadvantage of this scheme, however, is that, as the dierent Class-E PA
chains/modulators are switched ON-OFF to realize dierent output amplitude levels, the
209
Figure 5.16: Simulated performance of mm-wave stacked Class-E amplier under
load pulling, (a) variation of P
out
with Z
OPT:
,(b) variation of PAE with Z
OPT:
.
impedance seen by the remaining active Class-E modulators will change as a function of
the number of active PAs / output amplitude levels in a phenomenon know an \Load
Pulling". Fig. 5.15(c) shows the normalized impedance seen by each power modulator
as the number of active (ON) unit varies. In a 8-way combined system realized using
/4 transmission line combiners, Z
PA
can scale from Z
OPT
to 8Z
OPT
. Fig. 5.16 shows
the eect of changing impedance on a stacked Class-E output power and PAE. It can be
observed that unless the Z
PA
under all switching congurations can be limited to 0.6
Z
OPT
to 1.5 Z
OPT
, there will be signicant degradation in PAE at backed-o power
levels and can even lead to catastrophic transistor breakdown because of non-optimal
load conditions.
210
Figure 5.17: A variable characteristic impedance (Z
C
) micro-strip transmission line,
(a) proposed architecture, (b) equivalent model in the \High Z
C
" and \Low Z
C
"
modes of operation.
5.3.2 Variable Characteristic Impedance Transmission Line
One way to mitigate the aforementioned \load pulling" problem in digital power ampliers
is to design a \recongurable" power combining network capable of automatically re-
optimizing the impedance presented to the unit Class-E modulators (Z
PA
) back toZ
OPT
as function of output amplitude level. For the /4 transmission line based scheme, this
is possible by engineering a variable characteristic impedance (Z
C
) transmission lines.
Tunable transmission lines having variable phase shifts while maintaining a constant
Z
C
have been demonstrated before [92] [93]. However, the tunable transmission line
structure shown in Fig. 5.17(a) addresses the converse problem of digitally controlling
the characteristic impedance of the transmission lines while keeping a constant phase shift.
Since in an integrated planar micro-strip transmission line, the characteristic impedance is
primarily controlled by the relative spacing of the signal and ground planes, a transmission
line with several switch-connected metal layers that are either connected to ground or
211
Figure 5.18: Variable impedance transmission line, (a) chip microphotograph, (b)
measured Z
C
versus frequency, (b) measured attenuation constant and propaga-
tion constant versus frequency.

oating can have variable characteristic impedance. Since the electrical length (phase
shift) of the transmission line is only controlled by the dielectric constant of the silicon
substrate, the isolating action of the /4 transmission line combiners remain intact in
this tunable transmission line structure.
In this particular implementation of a dual-state transmission line Fig. 5.17(a), the
thick top metal AM is used as the signal line and the stacked metals M1-MQ as the xed
ground plane. The metal layer LY is used as the
oating plane digitally controlled by
thick-oxide MOSFET switches to ensure voltage handling capability when used for power
combining the unit Class-E modulator outputs. When the MOSFET switches are turned
OFF, the LY layer is
oating, giving a characteristic impedance of 50
. However,
when all the MOSFET switches are turned on simultaneously electrically shorting the LY
layer to ground, the ground plane virtually moves, reducing the separation between the
signal and ground plane and lowering theZ
C
to 35
as shown in Fig. 5.18(b). Having
a tunable transmission line comes at the cost of higher insertion loss in the lowZ
C
mode,
212
Figure 5.19: (a) A two-way /4 combiner using variableZ
C
transmission lines, (b)
simulated power combining eciency under dierent operating modes.
as the ON resistance of the MOSFET switches in the return path contribute to a larger
attenuation constant as shown in Fig. 5.18(c). These dual-state transmission lines have
been used to realize a two-way /4 transmission line combiner at 45 GHz (Fig. 5.19)
which are used in the 8-way dynamic load modulation discussed in Section 5.3.3. In-spite
of a more lossy combing network when using these tunable transmission line, it will be
shown later, that the overall system performance especially in power back-o improves
signicantly in this approach.
5.3.3 Dynamic Load Modulation in mm-Wave Digital PA
The tunable transmission line based two-way /4 combiner is used in conjunction with a
4:1 /4 combiner to realize a 8-way dynamic load modulation network as shown in Fig.
5.20. By correctly synchronizing the operating mode of the tunable transmission line
combiner (lowZ
C
or highZ
C
mode), with the number of active unit Class-E modulators,
213
Figure 5.20: Power control by dynamic load modulation, (a) peak power operation
when all unit ampliers are turned ON, (b) back-o power operation when `m' out
of 8 unit PAs are active, (c) variation of Z
PA
with power back-o.
the impedance seen by the active unit PAs (Z
PA
) always remain close toZ
OPT
irrespective
of the switching states (Fig. 5.20(c)). The schematic for a practical implementation of the
mm-wave Watt-level 8-way combined digital PA with dynamic load modulation is shown
in Fig. 5.21. The implemented system comprises of 8-way combined 3-stage Class-E PA
chains designed forZ
OPT
= 35
with input and output switch control. The input switch
is used to control power generation from the Class-E modulators while the output switch
network shorts the output of the inactive PA chains to low impedance and enables the/4
tunable transmission lines connected to the inactive modulator to provide isolation (open
circuit) to the active modulator chains. The output dynamic load modulation network
comprises of the dual-state transmission line base two-way /4 combiner and a 4:1 slow
wave combiner for presenting the 35
optimum impedance to each of the 8 unit PA chains
under dierent switching congurations. The 4:1 slow wave combiner is realized with/4
slow wave transmission lines with slotted ground planes for low insertion loss shown in
Fig. 5.21 inset. Since the Class-E modulator inputs are always constant impedance due
214
to the complementary input switch network of each Class-E modulator, a low loss zero-
phase transmission line based input splitter have been used [22]. Finally, an additional
Class-E driver is used at the input of 8-way power splitter (Fig. 5.21) for additional power
gain of the system and to provide enough power to saturate the Watt-level digital power
amplier. Each unit PA chain is designed to have a peak eciency of 28% forZ
OPT
= 35

including all the layout non-idealities. The operation of the dynamic load modulation
network as the dierent unit PAs are switched OFF is shown in Fig. 5.22. It can be
observed that by correctly choosing the operating mode of the dual-state transmission
line combiners as well as the pattern of unit PA switching, the system becomes balanced
again when 4 unit PAs are switched OFF thereby achieving peak eciency at back-o
and then the previous cycle of switching OFF the remaining PAs can be repeated. To
compare the ecacy of the dynamic load modulation technique for amplitude control and
enhanced back-o eciency in a mm-wave digital power amplier, the proposed system
is compared with the well known Doherty amplier load modulation curve assuming ideal
lossless transmission line implementation (Fig. 5.22(f)). The resultant eciency curve
versus power back-o in this proposed dynamic load modulation network is similar to that
achieved by a Doherty amplier architecture but with much
atter eciency response for
the 0 to -6 dB power control range and much smoother eciency degradation at further
back-o levels. In addition, since Doherty ampliers typically use less ecient Class-AB
ampliers as the main amplier and the less ecient Class-C ampliers as the peaking
amplier, the overall system eciency of this ecient Class-E amplier based dynamic
load modulation network can be signicantly better. In addition, at deeper back-o, the
proposed load modulation system gives better eciency than a Doherty amplier. This
215
Figure 5.21: Schematic of the mm-Wave Watt-level 8-way combined digital power
amplier with dynamic load modulation network.
is because while at deep back-o, the Doherty amplier eciency prole is primarily the
Class-AB slope, the dynamic load modulation network in conjunction with the R
Ballast
in Fig. 5.21 can still provide close to optimum impedance for the active unit Class-E PA
chains for high eciency. It can also be observed that the eciency at back-o for the
proposed system is better than using a /4 load modulation with xed Z
C
transmission
lines.
Compared to the theoretical maximum achievable PAE of 34% for a 8-way combined
system in Fig. 5.5(c), the achieved PAE for the 8-way digital power amplier is lower
at 18.5%. Firstly, compared to the theoretical maximum PAE of a stacked Class-E
PA at 52% based on the technology parameters, a real HBT implementation achieves
45% PAE primarily due to the unavailability of the higher harmonics of 45 GHz in the
216
right amplitude and phase [40]. Secondly, to realize the Class-E modulator action with
a lossy output switch network, the overall 3-stage PA modulator eciency again drops
to 28% compared to the theoretical 45% for only a 3-stage amplier. Finally, compared
to the theoretical 8-way combining loss of -1.2 dB by using a hybrid 2-way and 4-way
combining (Fig. 5.5(b)), the dynamic load modulation network with tunable transmission
lines has a higher insertion of 2 dB which further reduces the overall system peak PAE
to 18.5% [94]. However in return, the chosen architecture can achieve high eciency at
backed-o power levels with several levels of output amplitude control.
5.3.4 29 dBm mm-Wave Digital PA
To demonstrate Watt-level power generation at mm-wave frequencies and enhanced ef-
ciency under power back-o, a 8-way combined digital power amplier with integrated
dynamic load modulation network was fabricated in the 0.13 m SiGe BiCMOS pro-
cess [94]. The die microphotograph of the fabricated chip is shown in Fig. 5.23. Exten-
sive testability has been incorporated in these multi-stage power combined systems by
including GSG pads at the critical nodes albeit at the cost of a larger die area. The large
power transistors used for large power generation have been realized by parallel connec-
tion of smaller HBT devices from the process design kit (PDK). The capacitively coupled
intra-device parasitics are modeled from standard RC extraction tools while the large vias
for the top metal layers have been modeled as parasitic inductances using HyperLynx 3D
EM electromagnetic simulator [52]. The passive components including MIM capacitors,
transmission line slab-based inductors and most importantly the tunable transmission line
based 2-way combiner and slow-wave transmission line based 4:1 combiner have also been
217
Figure 5.22: Operation of the dynamic load modulation network, (a) peak power
operation, power control by (b) 1 PA OFF, (c) 2 PAs OFF, (d) 3 PAs OFF, (e) 4
PAs OFF, (f) power back-o eciency comparison between dierent schemes.
Figure 5.23: Die microphotograph of the Watt-level 8-way combined digital power
amplier.
218
Figure 5.24: Small signal s-parameter measurements of the digital PA under Class-
A bias.
simulated and modeled using HyperLynx 3D EM electromagnetic simulator. Detailed
design and layout principles are available in [94]. To validate the mm-wave modeling of
the passives and actives for this multi-stage power combined system, a small signal S-
Parameter measurement (Fig. 5.24) was conducted under Class-A biasing, showing good
correlation of input matching and gain transfer function between measurement and simu-
lation. The absence of spurious oscillations under large signal operation [25] [53], during
probe measurements, is ensured by monitoring the output via a spectrum analyzer. The
output power measurements are validated both from the spectrum measurements as well
as a thermocouple power sensor. The measurement setup losses at both the input and
output are de-embedded by scalor \through" measurements. Watt-level power generation
in a silicon process at mm-waves was demonstrated by turning ON all the unit Class-E
PA chains by making the amplitude control bits B3-B0 high, and providing a continuous
219
Figure 5.25: Large signal measurements of the Watt-level digital PA at 46 GHz,
(a) P
out
, G
P
versus P
in
, (b) Eciency versus P
out
, (c) PAE versus. P
out
, (d)
performance across frequency.
wave input at mm-wave frequencies. Fig. 5.25 shows the measured large signal perfor-
mance of the prototype with 28.9 dBm peak output power at 46 GHz with 18.4 % peak
PAE and 13 dB of large-signal power gain. The power control operation of the digital
PA was tested by cycling through dierent combination of the amplitude control bits
B3-B0 with a 46 GHz input signal. Fig. 5.26(a) shows the measured eciency versus
back-o power levels as the output power level scales down for the dierent control bits.
A -6 dB back-o eciency of 11% is reported which is 60% of the peak eciency. It
can be observed that the measured eciency at -6dB back-o is worse compared to the
expected 100% peak eciency when all the 4 unit PAs are turned OFF as shown in Fig.
5.22(f). This is primarily because of the higher insertion loss of the tunable transmission
220
Figure 5.26: Power control operation of the digital PA, (a) system eciency versus
power back-o, (b) output voltage amplitude versus amplitude control code, (c)
DNL/INL versus amplitude control code.
line when they operate in the low Z
C
mode at -6 dB back-o point. In addition, there is
some additional power loss and eciency degradation due to non-ideal/4 termination of
the inactive PA chains. The linearity of the system while not a primary design objective
is tested by converting the measured output power on a 50
load into output voltage
amplitude and plotted in Fig. 5.26(b). The nonlinearity at the middle of control code
sequence re
ected by the highest DNL in Fig. 5.26(c) is again due to the balanced state
that the dynamic load modulation network achieves at the code midpoint.
5.4 Conclusion
Ecient Watt-level power generation at mm-wave frequencies requires both ecient unit
power ampliers as well as an ecient power combining scheme. In this chapter, the per-
formance limits for Watt-level power ampliers at mm-wave frequencies in a SiGe HBT
221
Table 5.1: Performance comparison of our work with some reported state-of-art
mm-wave PAs and power DACs.
process is discussed using Class-E power ampliers and various power-combining archi-
tectures. Based on this study, the best conguration of power combining architectures for
achieving Watt-level power with the highest system PAE is provided. To support high
speed data transmission using switching power ampliers, a high-speed ASK modulated
bit-transmission architecture is introduced in the form a 1-bit Class-E power modulator
which are then used in a 8-way combined digital power amplier for Watt-level peak out-
put power with high eciency. To address the problem of load pulling in mm-wave digital
power ampliers, a tunable transmission line based dynamic load modulation network is
proposed which enables high eciency under backed-o power levels in the digital power
amplier. Prototypes demonstrating the highlighted concepts were fabricated in the 0.13
m SiGe BiCMOS process and are summarized in Table 5.1 along with performance
comparison with reported state-of-art mm-wave power ampliers and power DACs. The
222
Figure 5.27: PAE at P
sat
for reported silicon mm-wave power ampliers.
benet of using switching ampliers at mm-waves in a power combined scheme is clear
from the performance comparison graph of Fig. 5.27 which shows the implemented sys-
tem achieves the highest output power with highest reported PAE compared to other
state-of-art mm-wave silicon power ampliers. The proposed architecture and circuit
techniques enable realizing ecient Watt-level power ampliers in silicon technologies for
use in high-speed, high power silicon transmitters at mm-wave frequencies.
223
Chapter 6
Mm-Wave Digital Polar Transmitter Design
This thesis has primarily focussed on the analysis, design and implementation of mm-wave
switching ampliers in a SiGe HBT BiCMOS process. As discussed in Chapter 1, the main
motivation for the development of these silicon power ampliers for mm-wave frequency
operation is to enable full silicon integration of Watt-level transmitters supporting long
distance, high-speed wireless links. In this chapter, the system level design example of
one such mm-wave digital polar transmitter architecture using switching power ampliers
is discussed.
As covered in Chapter 1, to support high data rates (> 10 Gbps) over long distance
mm-wave wireless links (> 1 Km), phased array transceivers having Watt-level transmit
power per antenna are needed. Digital polar transmitter (DPT) architecture can use such
switching ampliers [18{21]. Digital polar transmitters suer from bandwidth expansion
due the inherently non-linear I/Q to amplitude and phase conversion process [18]. Digital
base-band requirements to address the aforementioned bandwidth expansion in DPTs is
also discussed in the following system level analysis.
224
Figure 6.1: A digital polar transmitter block diagram
6.1 Digital Polar Transmitter for High-Speed Data
Transmission
In recent years, the digital polar transmitter architecture (DPT) has become popular for
energy ecient data transmission [18]. The DPT architecture relies on energy ecient
baseband signal processing as well ecient as switching ampliers for achieving high
average eciency during information transmission.
6.1.1 Mm-Wave Digital Polar Transmitter Architecture
The generic architecture of a digital polar transmitter is shown in Fig. 6.1. In contrast
to conventional I/Q transmitters, where the main amplication block at the front-end is
a linear power amplier, a digital polar transmitter uses an array of switching ampliers
for the signal amplication and an output combiner. The baseband portion of a DPT
225
consists of a cartesian-to-polar converter (CORDIC)
1
. This module takes converts the in-
phase, A
I
(t), and quadrature-phase, A
Q
(t), input data to amplitude (A
N
(t)) and phase
bits (
N
(t)) for the modulated signal given by,
8
>
>
>
>
<
>
>
>
>
:
A
N
(t) =
q
A
2
I
(t) +A
2
Q
(t);

N
(t) =tan
1
(
A
Q
(t)
A
I
(t)
):
(6.1)
The phase information
N
(t) is then superimposed on a carrier though a phase modulator.
The resulting phase modulated signalA
0
cos(!
0
t+
N
(t)) has a constant envelope, and as
such may be amplied by the switching ampliers without causing signal distortion. Each
switching amplier operates in a binary mode where the input signal is either amplied or
not passed through. The amplitude informationA
N
(t) is used in an amplitude controller
that enables/disables an appropriate number of switching ampliers. This scheme enables
each of the unit switching ampliers to always operate with maximum eciency during
the signal amplication (Peak P
out
andPAE) while not consuming any DC power when
disabled (no signal pass through). Therefore, the overall eciency of the DPT can be
much higher than a I/Q transmitter even in deep power back-o mode.
The main benet of DPT architecture is eciency improvement thanks to the abil-
ity to use ecient switching ampliers. However, the architecture of DPT has its own
unique drawbacks. Firstly, the inherently non-linear cartesian-to-polar conversion leads
to bandwidth expansion in the amplitude,A
N
(t), and phase,
N
(t), waveforms compared
to that in the in-phase A
I
(t), and quadrature phase, A
Q
(t), signals. Secondly, as was
1
Most modern communications used Quadrature Amplitude Modulation (QAM) that is easily
represented in baseband as A
I
(t) + jA
Q
(t).
226
Figure 6.2: Bandwidth expansion of amplitude and phase signals in a polar trans-
mitter.
discussed in Chapter 5, independent control of switching ampliers in a power-combined
system leads to load-pulling which can aect system eciency at back-o. To mitigate
load-pulling, dynamic load modulation networks similar to the one proposed in [94] may
be implemented. Finally, since the amplitude and phase signals pass through dierent
blocks, proper time synchronization between them is critical for proper DPT operation.
At high modulation speeds, such amplitude and phase synchronization is not trivial.
6.1.2 Bandwidth Expansion in Digital Polar Transmitters
The main drawback in using digital polar transmitter for high-speed data transmission is
the bandwidth expansion in the amplitude and phase of the modulated signals. The DPT
architecture of Fig. 6.1 is expanded in Fig. 6.3(a) to showcase the baseband processing
blocks as well. Assuming the sampled baseband signals A
I
(n) and A
Q
(n) have a symbol
227
Figure 6.3: Signal spectrums in a digital polar transmitter.
228
rate ofR
sym
= 2 GHz, the spectrum of the baseband I/Q signal under root-raised cosine
ltering is bandlimited as shown in Fig. 6.3(b). In typical I/Q transmitter, discrete time
signalsA
I
(n) andA
Q
(n) are frequency up-converted using quadrature mixers and nally
amplied by a linear amplier. In this process,, the bandlimited baseband signal is simply
frequency shifted and amplied (Fig. 6.3(f)). In the digital polar transmitter, however,
the baseband I/Q signals A
I
(n) and A
Q
(n) undergo a non-linear transformation of Eqn.
6.1 to obtain the discrete time amplitude,A
N
(n), and phase,
N
(n), signals. BothA
N
(n)
and
N
(n) undergo bandwidth expansion; the bandwidth of
N
(n) will be much larger
due to the stronger nonlinear tan
1
function. This necessitates a very high-speed phase
modulator. An alternate approach is to convert the I/Q signals to A
N
(n) and e
j
N
(n)
,
8
>
>
>
>
<
>
>
>
>
:
A(n) =
q
A
2
I
(n) +A
2
Q
(n);
e
j
N
(n)
=
A
I
(n)+jA
Q
(n)
q
A
2
I
(n)+A
2
Q
(n)
:
(6.2)
The new signal, e
j
N
(n)
, has a lower bandwidth when compared to
N
(n). For R
sym
=
2 GHz, the baseband I/Q and the polar components are shown in Fig. 6.2. In absence
of any up-sampling N
1
, this bandwidth expansion would cause spectral aliasing with the
adjacent images. This spectral aliasing causes distortion in the nally recombined polar
signal. To reduce aliasing, A
I
(n) and A
Q
(n) are rst up-sampled and ltered (for N
1
=
2 in Fig. 6.3(c)) such that after the non-linear transformation of Eqn. 6.2, little aliasing
occurs in A
N
(n) ande
j
N
(n)
spectrums. The eect of up-sampling factor N
1
is shown in
Fig. 6.4. In absence of sucient up-sampling, the spectral regrowth of the recombined
polar signal would be unable to meet the transmit spectral mask requirements. Very
229
Figure 6.4: Up-sampling of the base-band I/Q signal before amplitude and phase
splitting for, (a) N
1
= 1 (Nyquist), (b) N
1
= 2, (c) N
1
= 4, (c) N
1
= 8
high up-sampling however is impractical and energy inecient especially for high-speed
modulations.
6.1.3 Mm-Wave DPT Amplitude and Phase Resolution
Another consideration is the nite resolution of amplitude A(n) and exponent e
j
N
(n)
digital signals that can be achieved in a practical implementation of the digital polar
transmitter. When the amplitude and exponent signal passes through a mm-wave
digital polar transmitter with amplitude resolution `N
A
' and exponent resolution `N

',
the quantization noise due to this nite resolution is added to the to the spectrum as
shown in Fig. 6.3(e). This quantization noise degrades the signal to noise ratio or the
230
Figure 6.5: (a) EVM vs amplitude resolution N
A
and phase resolution N

in a
digital polar transmitter, (b) EVM requirement vs. BER for dierent QAM con-
stellations.
Error Vector Magnitude (EVM) of the transmitted waveform. Thus to satisfy a specic
BER for a chosen constellation, the minimum EVM requirement must be ensured by
choosing appropriate N
A
andN

bits in the DPT. Similar to an over-sampled ADC, the
eective number of amplitude and phase bits can also be increased by up-sampling the
amplitude and phase signals (N
2
) followed by digital ltering. For N
2
= 2, the image
frequencies of amplitude and exponent signals are pushed two times further apart and
the quantization noise is spread over twice the bandwidth improving the eective number
of bits by 3 dB or 0.5 bits. Instead of simple over-sampling, a higher order - loop may
be introduced to increase the eective number of bits further. Increasing the eective
number of bits by over-sampling however places further constraints on the speed and
power consumption of the phase modulator and amplitude decoder.
To support 50 Gb/s data-rate over an 8 GHz channel bandwidth (aggregating 4 sub-
carriers of 2 GHz each) would require 8 bits/symbol (assuming some of the channel
231
Figure 6.6: Reconstructed 256-QAM constellation from a digital polar transmitter
with 8-bit amplitude resolution and 6-bit phase resolution.
bandwidth is used for root raised cosine ltering). Thus a 256-QAM constellation is con-
sidered with BER = 10
6
requiring -35 dB EVM from the polar transmitter as shown
in Fig. 6.5(b). The simulated plot of EVM of the reconstructed 256-QAM constellation
for N
1
= 2 and N
2
= 1 using the DPT block diagram of Fig. 6.1 for dierent amplitude
bitsN
A
and phase bitsN

is shown in Fig. 6.5(a). To achieve EVM< -35 dB requiresN
A
= 8 bits and N

= 6 bits respectively. The simulated 256-QAM constellation obtained
after amplitude and phase separation in the baseband, frequency up-conversion in the
6-bit phase modulator, amplication and recombining in the 8-bit amplitude modulator,
and nally down-conversion of the transmitted signal in an ideal receiver is shown in Fig.
6.6. The amplitude and phase bit resolutions obtained from the system level analysis are
then used to estimate the performance of the digital polar transmitter and its constituent
building blocks.
232
Figure 6.7: Schematic for a high-speed Watt-level digital polar transmitter.
6.2 Polar Transmitter System Level Performance
The block schematic of a mm-wave digital polar transmitter with 8 amplitude bits and
6 phase bits is shown in Fig. 6.7. Previous results related to the performance of mm-
wave switching ampliers and power-combining schemes are used to derive performance
estimates for the entire transmitter assuming realization in the 130 nm SiGe BiCMOS
process.
6.2.1 60 GHz 8-Way Power Combiner
A digital polar transmitter with 8-bits amplitude resolution using binary weighted switch-
ing ampliers require an 8-way combining network similar to one discussed in Chapter 5.
The 8-way binary-weighted power-combining required for the proposed transmitter can
be realized using 4-way and 2-way power combining schemes as was used in Chapter 5
for Watt-level power generation. However, both the 4-way and 2-way combiners need to
be unequal current combiners [84], such that in presence of unequal current contribution
233
from the unit ampliers attached to each combining branch, a constant impedance looking
into each branch can be maintained. Mm-wave unequal combiners have been implemented
before [95], typically at the cost of slightly higher insertion loss compared to the equal
division power combiners, due to the higher characteristic impedance transmission lines
that such combiners require. In order to maintain high system eciency under power
back-o, a dynamic load modulation network [94] can also be used in this transmitter
(Chapter 5). This dynamic load modulation can be achieved by using variable character-
istic impedance transmission lines in an equal-division 8-way power combiner. From the
insertion loss versus transmission line characteristic impedance curves of Chapter 5 (Fig.
5.6), an insertion loss of -2 dB for peak output power operation is estimated for the
8-way combiner. The requirement for the input power splitter (from the phase modulator
to the switching amplier array) is much less stringent due to lower power levels. An
insertion loss of -1.5 dB is estimated for 8-way splitter at mm-wave frequencies [44] [22].
6.2.2 60 GHz Switching Ampliers
Accounting for the insertion loss in the output combiner, the switching amplier array
in the digital polar transmitter with N
A
= 8 bit amplitude resolution must generate
output power ranging from 8 dbm for the LSB to 29 dBm for the MSB. As discussed in
Chapter 5, for generating output power < 21 dBm, a non-stacked Class-E architecture
results in better eciency compared to a stacked architecture. Thus, the rst 5 LSBs
for the DPT switching amplier aray are chosen to be non-stacked switching amplier
designs. For the last three MSBs with output powers of 23 dBm, 26 dBm, and 29 dBm,
respectively, stacked switching ampliers are preferred. From the non-stacked Class-E
234
eciency equations in Chapter 2, the eciency of the 60 GHz non-stacked Class-E nal
stage for the rst 5 LSBs is 65% including the loss in the nite-Q inductor L
1
. For a
3-stage implementation, the total eciency for each of the amplier chains of the 5 LSBs
can be estimated using the multi-stage amplier eciency equations of Chapter 5 to be
40%.
For the last 3 MSBs with P
out
> 23 dBm, stacked Class-E implementations (two-
stacked, three-stacked, and four-stacked) is preferred. At 60 GHz, the eciency of the
two-stacked, three-stacked and four-stacked Class-E ampliers can be estimated to be
40%, 35%, and 30% respectively. A three-stage implementation for the 3 MSB amplier
chains, including impedance transformation loss or power combining loss (Chapter 5) for
the last 2 MSBs result in amplier chain eciencies of 35%, 32% and 27% respectively for
23 dBm, 26 dBm and 29 dBmP
out
levels. The eciency of the individual amplier chains
can be used to calculate the total eciency of the system including the output combiner
loss. The total DC power dissipated in the switching ampliers chains for realizing 8-bit
amplitude resolution can be estimated to be 5.2 Watts for 30 dBm total output power
and overall peak eciency of 19%.
6.2.3 60 GHz Vector Modulator
For realizing 6-bit N

phase resolution, a high-speed I/Q 6-bit mm-wave vector modula-
tor, as shown in Fig. 6.8(a) may be realized. Mm-wave multi-Gs/s vector modulators with
high phase resolution have been implemented before in silicon technologies [96] [97] [98]
and consume between 50 mW to 100 mW of DC power. Depending on the amplitude
bit level that needs to be transmitted, the AM-PM response of each amplier chain may
235
Figure 6.8: Schematic for (a) high-speed vector modulator, (b) variable character-
istic impedance and phase shift transmission line for load modulation and phase
compensation.
vary. To account for the phase distortion that happens as function of amplitude levels,
passive transmission line base phase modulators [92] may need to be implemented at the
input or output of the switching amplier chains (Fig. 6.8(b)).
6.2.4 Digital Power Consumption
In Chapter 5, a mm-wave 1-bit ASK power modulator using switching ampliers and FET
switches at the input and outputs was demonstrated [88]. A similar architecture is shown
in Fig. 6.7 where the binary-weighted switching ampliers
2
are turned ON/OFF by
using the input control switches according to the amplitude control codes. Assuming the
switching ampliers have enough power gain, the insertion loss introduced by the series
switches do not signicantly aect the overall system performance. The FET switches
2
Each switching amplier may consist of multiple stages.
236
Figure 6.9: (a) Technology parameters for the 130nm CMOS FETs in the 130nm
SiGe BiCMOS process, (b) nal-stage of the digital driver chain used to drive the
amplitude control switches in the mm-wave DPT, (c) total power consumption
(P
Digital
) and number of stage requirement (N) for the digital drivers.
and the inverter chains that drive them, must operate at high speed (multi-Gbps) to
support the desired high data-rates in the polar transmitter. The maximum operational
speed of inverter based CMOS digital circuits and the required power dissipation can be
estimated based on the CMOS transistor parameters (Fig. 6.9(a)) in the 130 nm SiGe
process as [99],
8
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
:
T
Period
=M (T
Rise
+T
Fall
);
f
max;Inverter
=
1
22:2M(
NMOS
+
PMOS
)
15GHz;
f
max;Chain
=
f
max;Inverter
1+
7GHz;
LE =

f
max;Inverter
f
0
1
0:3 @3GHz;
P
Digital
= [1 +
1
f
max;Inverter
f
0
1
][
1LE
N
1LE
]V
2
DD
C
L
f
0
:
(6.3)
237
In the Eqn. 6.3, margin of safety parameterM is chosen to be greater than 2 to ensure the
sum of rise time,T
Rise
, and fall time,T
Fall
, of the inverter do not exceed the time period
T
Period
.
NMOS
and
PMOS
are the NFET and PFET time constants that determine the
maximum speed of each inverter stage (f
max;Inverter
). To ensure that each inverter stage
can be driven by a smaller preceding stage inverter, the loading eort LE must be < 1 .
The eective maximum frequency of operationf
max;Chain
for the 130nm CMOS inverter
chains available in the process can be estimated to be about 7 GHz. The total digital
power consumption P
Digital
is then determined based on frequency of operation f
0
, the
number of inverter stages N, as well the load C
L
of the input series switches to each of
the mm-wave ampliers.
To achieve 50 Gb/s using a 256-QAM constellation would require 8 parallel inverter
chain driving the control switches of the 8-bit binary weighted digital amplier operating
a 6 Gs/s (f
0
= 3 GHz). The total inverter power consumption is estimated to 10 mW per
chain (Fig. 6.9(c)) corresponding to about 100 mW total power consumption for driving
the digital circuits.
The total power consumption of the Watt-level digital polar transmitter is estimated
to be 6W leading to total peak system eciency of 16%. The complete system level
specication and estimated performance is shown in Table 6.1. This calculation shows
that high-speed, energy-ecient, mm-wave digital polar transmitters, leveraging the pro-
posed switching ampliers of this thesis, can be realized in today's silicon technologies.
238
Table 6.1: System Specication for 60 GHz Digital Polar Transmitter.
6.3 Conclusion and Future Work
In this thesis, innovative silicon-based switching amplier architectures and corresponding
design methodology and performance limitation at mm-wave frequencies have been pre-
sented. Eciency enhancement methods include exploiting the collector current-density-
dependent-breakdown voltage of SiGe HBTs as well as waveform engineering by harmonic
load termination. Series stacking of HBTs in mm-wave switching ampliers have been in-
troduced to generate higher power levels for the same load impedances without requiring
lossy impedance matching networks. Finally, eciency enhancement at power back-o
by using a dynamic load modulation network has been proposed resulting in a Watt-level
digital power amplier at mm-waves.
The main benet of these highly ecient switching ampliers would be in high-speed
mm-wave digital polar transmitters, where the power amplier DC power consumption
dominates the overall system performance. System architecture and analysis of such
digital polar transmitter has been discussed.
239
Future work may include fully integrated implementation of such silicon digital polar
transmitters with Watt-level output power for supporting long distant wireless links for
the upcoming 5G applications. Addressing other critical issues in mm-wave high-speed
digital polar transmitters such as amplitude and phase delay synchronization and cali-
bration for AM-AM and AM-PM non-idealities, are also areas that should be studied.
Finally, large-scale mm-wave phased array transceivers, where several Watt-level trans-
mitters work in tandem, oer further challenges for future work.
240
Appendix A
SiGe BiCMOS Process Details
Two SiGe BiCMOS process from the IBM/Global Foundry has been used for the im-
plementation of mm-wave power ampliers presented in this thesis. A brief summary of
features available in both the SiGe BiCMOS technologies is presented here.
130nm 8HP SiGe BiCMOS Process
The 130nm SiGe BiCMOS process [100] [26] is a scaled BiCMOS process having both
130nm npn SiGe HBTs withf
T
= 200 GHz,f
max
= 270 GHz respectively with breakdown
voltages of BV
CEO
= 1.8 V and BV
CBO
= 5.9 V. 130nm CMOS transistors are also
available in this process. The metal stack in this process comprises of 7 metal layers and
MIM capacitors as shown in Fig. A.1 .
90nm 9HP SiGe BiCMOS Process
The 90nm SiGe BiCMOS process [101] is a scaled BiCMOS process having both 90nm npn
SiGe HBTs with f
T
= 270 GHz, f
max
= 320 GHz respectively with breakdown voltages
241
Figure A.1: Metal stack of the 130nm SiGe BiCMOS process.
Figure A.2: Metal stack of the 90nm SiGe BiCMOS process.
242
Figure A.3: (a) I
C
versus V
BE
, (b)I
C
versus V
CE
for a 616 m SiGe HBT in the
130nm BiCMOS process.
of BV
CEO
= 1.5 V and BV
CBO
= 5.0 V. 130nm CMOS transistors are also available in
this process. The metal stack in this process comprises of 10 metal layers and MIM and
dual-MIM capacitors as shown in Fig. A.2.
Active and Passive Characterization
The active transistors and passive components available in the 130nm SiGe BiCMOS
process has been characterised. A 616 m SiGe HBT transistor was fabricated for DC
measurement as shown in Fig. A.3. BothI
C
versusV
BE
andI
C
versusV
CE
measurement
was carried and match accurately with the simulated results.
All the inductors in the mm-wave designs implemented in this thesis have been realized
as micro-strip transmission lines. The validate the modeling accuracy of the micro-strip
transmission lines, a 50
transmission line was fabricated and measured as shown in Fig.
A.4.
243
Figure A.4: (a) Cross-section of a 50
micro-strip transmission line in the 130nm
SiGe BiCMOS process, (b) measured characteristic impedance Z
C
, (c) Measured
attenuation constant and wave-factor .
Realizing high-density, low-loss on-chip capacitor is another challenge for mm-wave
integrated designs. In the 130nm SiGe process, metal-insulator-metal (MIM) capacitor
available in the technology library has been used. At mm-wave frequencies, the MIM
capacitor can be modeled as an equivalent circuit with series inductor and resistors as
shown in Fig. A.5(a). The cross-section of a 325 fF MIM capacitor and typical model
component values of some MIM capacitors is also shown in Fig. A.5(a). The modeling
accuracy has been veried by fabricating and measuring a 325 fF MIM capacitor in the
130nm SiGe process as shown in Fig. A.5(b).
244
Figure A.5: (a) Isometric view of a 325 fF metal-insulator-metal (MIM) capacitor
in the 130nm SiGe BiCMOS process along with the equivalent circuit schematic
and values of circuit components for some capacitor values, (b) measured and EM
simulated (using IE3D simulator) s-parameter (magnitude and phase) of the 325
fF MIM capacitor.
245
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Abstract (if available)

Abstract In recent years, millimeter wave wireless communication with carrier frequency above 30 GHz has become an important area of research as the large available bandwidth at the millimeter wave frequency spectrum enables supporting high data-rates. Supporting reasonable wireless link distances requires the transmitter front-end to generate large output power at millimeter wave frequencies. This thesis presents innovative integrated circuit solutions, for implementation of Watt-level, power-efficient millimeter-wave, silicon power amplifiers and transmitters with following contributions: (1) series stacking of transistors in switching power amplifier architectures for generating high power with high efficiency, (2) engineering voltage-current waveforms for efficiency enhancement in switching power amplifiers by harmonic manipulation at millimeter wave frequencies, and (3) reconfigurable power combining networks with dynamic load modulation for improving efficiency at backed-off power levels in digital power amplifiers. ❧ The necessity for high-speed, energy efficient signal processing in high data-rate wireless communications, makes the silicon technology very attractive for high-speed millimeter wave wireless transceivers. However, the low breakdown voltage of modern scaled silicon CMOS and silicon germanium (SiGe) HBT processes and lossy on-chip passive components present challenges for generation of Watt-level power with high efficiency at millimeter-wave frequencies. This thesis presents several prototypes of Class-E switching power amplifiers, where the transient voltage-current waveform properties has been exploited in conjunction with SiGe heterojunction bipolar transistor breakdown physics, to generate high output power with high efficiency at millimeter waves. This thesis further presents stacked switching power amplifier architectures, where constructive addition of voltage swing across multiple series stacked transistors enables generation of higher output power with negligible power generation efficiency degradation. Device and layout parasitics, often treated as unwanted secondary effects, are judiciously included in the mm-wave designs. Several amplifier prototypes at Q-band (around 45 GHz) and W-band (around 85 GHz) validate the effectiveness of the proposed schemes at mm-wave frequencies. Another contribution of this thesis is finding the performance limits of switching amplifiers as a function of transistor technology. While the experimental demonstrations are limited to SiGe HBT processes, the proposed approaches are general and applicable to other silicon and compound semiconductor technologies. ❧ The role of harmonics in synthesizing the desired voltage and current waveforms in switching power amplifiers was investigated to probe the existence of the 'best' or 'optimum' class of amplifiers at millimeter wave frequencies. This waveform engineering with harmonic manipulation result in better power generation and efficiency than conventional classes of amplifiers. Waveform engineering by harmonic manipulation is also extended to stacked switching power amplifiers. Amplifier prototypes at 30 GHz demonstrate the value of such concepts at millimeter wave frequencies. ❧ Finally, a Watt-level millimeter-wave digital power amplifier with multiple output amplitude levels has been proposed utilizing the switching power amplifier modules. An ON-OFF-Keying (OOK) mm-wave power modulator based on a Class-E power amplifiers is demonstrated. Several of these OOK mm-wave power modulators can be power combined to realize a multi-level digital power amplifier with several levels of output amplitude and power control. Conventional passive power combining schemes in such a architecture, however, result in load impedance variation and consequently efficiency degradaton for different amplitude levels. To mitigate the load pulling problem, a programmable power combining scheme comprising of transmission lines with variable characteristic impedance is proposed that can dynamically correct any load variation in the transmitter. The implemented prototype demonstrates Watt-level output power at millimeter wave frequencies along with high efficiency under power back-off operation. The thesis concludes with a design example where the proposed mm-wave switching amplifier is utilized to highlight different system level concepts of a high-speed mm-wave Watt-level digital polar transmitter.

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Asset Metadata

Creator Datta, Kunal (author)

Core Title High power, highly efficient millimeter-wave switching power amplifiers for watt-level high-speed silicon transmitters

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 10/13/2016

Defense Date 10/03/2016

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag Class-E,CMOS,HBT,integrated circuits,mm-wave,OAI-PMH Harvest,power amplifier,silicon germanium,transmitter

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Hashemi, Hossein (committee chair), Chen, Mike S. W. (committee member), Chugg, Keith (committee member), Prata, Aluizio (committee member), Ravichandran, Jayakanth (committee member)

Creator Email kdatta@usc.edu,kunal.cal@gmail.com

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c40-314764

Unique identifier UC11213622

Identifier etd-DattaKunal-4882.pdf (filename),usctheses-c40-314764 (legacy record id)

Legacy Identifier etd-DattaKunal-4882.pdf

Dmrecord 314764

Document Type Dissertation

Format application/pdf (imt)

Rights Datta, Kunal

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA