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Wideband low phase-noise RF and mm-wave frequency generation

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Wideband low phase-noise RF and mm-wave frequency generation

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Content Wideband Low Phase-Noise RF and mm-Wave Frequency Generation by Alireza Imani A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2016 Copyright 2016 Alireza Imani Acknowledgements The support of many has been critical in the completion of this work. First, I would like to thank my advisor and mentor, Prof. Hossein Hashemi for putting the trust in hiring me, mentoring me through highs and lows, and advising me in doing work that I am proud of. Perhaps most importantly, I want to thank him for teaching me (and the group in general), that through systematic research, almost any technical problem can be tackled. I would like to thank the other members of my defense committee, Prof. Mahta Moghaddam, Prof. Aluizio Prata, Prof. Mike Chen, and Prof. Jayakanth Ravichandran, for their help and support. I also thank current and past members of Prof. Hashemi’s research group, Prof. Tashun Chu, Dr. Ankush Goel, Dr. John Roderick, Prof. Firooz Aflatouni, Dr. Zahra Safarian, Dr. Behnam Analui, Tim Mercer, Chenliang Du, Dr. Run Chen, Dr. Kunal Datta, Masashi Yamagata, Sushil Subramanian, Pingyue Song, Hooman Abediasl, and others, for their support, friendship, and countless hours of technical and non-technical discussions. ii My parents have been a great source of support and inspiration through these years. I thank them here, as I thank them every day. Last and foremost, this work would have not been done without the help and support of the most important person of my life, my wife, Sanaz Barghi. iii Table of Contents Acknowledgements ii List of Tables vi List of Figures vii Abstract xv Chapter 1: Frequency generation for mm-wave wireless transceivers 1 1.1 Phase noise and jitter definitions . . . . . . . . . . . . . . . . . . . . . 4 1.2 Effect of phase noise in communications throughput . . . . . . . . . . . 8 1.2.1 M-QAM signals . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.2 OFDM signals . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.3 Reciprocal mixing . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.4 Data conversion . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 Transceiver system design of a 100 Gbps SDR . . . . . . . . . . . . . 15 Chapter 2: High-frequency reference design 22 2.1 Phase noise in oscillators with nonlinear resonators . . . . . . . . . . . 24 2.1.1 FBAR nonlinear model . . . . . . . . . . . . . . . . . . . . . . 25 2.1.2 General formulation and analysis . . . . . . . . . . . . . . . . 29 2.1.2.1 Problem formulation . . . . . . . . . . . . . . . . . . 29 2.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1.2.3 Simulations . . . . . . . . . . . . . . . . . . . . . . 39 2.1.3 An FBAR Colpitts oscillator . . . . . . . . . . . . . . . . . . . 40 2.1.3.1 Basics . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.1.4 Oscillator design and measurements . . . . . . . . . . . . . . . 47 2.2 Phase noise reduction techniques . . . . . . . . . . . . . . . . . . . . . 52 2.2.1 Phase noise reduction basics and definitions . . . . . . . . . . . 53 2.2.2 Design and implementation of a resonator-based phase-frequency discriminator and phase noise reduction scheme . . . . . . . . . 57 2.2.2.1 Resonator-based phase-frequency discriminator . . . 58 iv 2.2.2.2 Phase noise reduction scheme . . . . . . . . . . . . . 64 2.2.2.3 Limitations of feedback scheme and proposed solution 71 Chapter 3: Distributed injection locked frequency dividers 75 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.2 Conventional injection-locked frequency divider . . . . . . . . . . . . . 76 3.3 Distributed injection-locked frequency divider . . . . . . . . . . . . . . 84 3.4 Implementation of a mm-wave distributed injection locked frequency di- vider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chapter 4: Phase noise scaling in mm-wave oscillators 104 4.1 Oscillator phase noise scaling . . . . . . . . . . . . . . . . . . . . . . . 106 4.1.1 Ideal phase noise scaling . . . . . . . . . . . . . . . . . . . . . 107 4.1.2 Phase noise of frequency-scaled mm-wave oscillators . . . . . . 111 4.2 Implementation of mm-wave oscillators . . . . . . . . . . . . . . . . . 122 4.2.1 mm-wave cross-coupled pair oscillators . . . . . . . . . . . . . 122 4.2.2 mm-wave Colpitts oscillators . . . . . . . . . . . . . . . . . . . 124 4.3 Coupled mm-wave oscillator arrays . . . . . . . . . . . . . . . . . . . 130 4.4 Frequency tuning in mm-wave frequencies . . . . . . . . . . . . . . . . 136 Chapter 5: Conclusions 140 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.2 Recommendations for future work . . . . . . . . . . . . . . . . . . . . 141 References 143 Appendix A 152 A.1 Solutions to amplitude and phase stochastic differential equations of an oscillator with a nonlinear resonator . . . . . . . . . . . . . . . . . . . 152 A.2 Analysis of a band pass filter with an amplitude and phase modulated sinusoid input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Appendix B 157 v List of Tables 2.1 Comparison with FBAR and other low phase noise oscillators . . . . . 52 3.1 Comparison with mm-wave frequency dividers . . . . . . . . . . . . . 102 4.1 Performance summary and comparison with selsected silicon mm-wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 vi List of Figures 1.1 mm-wave spectrum and designation of bands. . . . . . . . . . . . . . . 3 1.2 Example phase noise profile of a practical self-sustained oscillator as a function of offset frequency. . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 (a) 64-QAM signal constellation, (b) SNR versus SER for M-QAM sig- nals in AWGN communication channel. . . . . . . . . . . . . . . . . . 10 1.4 (a) Simulink model to simulate the effect of phase noise on M-QAM signal, (b) 64-QAM constellation with SNR=25 dB and no phase noise (SER=210 4 ), (c) 64-QAM constellation with SNR=1 dB and 3 o rms phase noise (SER=2 10 3 ), (d) 64-QAM constellation with SNR=25 dB and 3 o rms phase noise (SER=2 10 2 ). . . . . . . . . . . . . . . . 11 1.5 Simulated SER versus SNR for 64-QAM and 1024-QAM signals for dif- ferent phase noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.6 (a) An OFDM transmitter architecture, (b) An OFDM receiver architec- ture, (c) Frequency spectrum of an OFDM signal highlighting orthogo- nal subcarriers (d) Frequency spectrum of an OFDM signal in presence of phase noise highlighting Inter Carrier Interference. . . . . . . . . . . 12 1.7 Effect of LO phase noise in reciprocal mixing. . . . . . . . . . . . . . 13 1.8 Sampling error due to ADC clock phase noise (or timing jitter). . . . . 15 1.9 (a) Conventional PLL-based frequency synthesizer for mm-wave SDR, (b) proposed two-stage PLL-based frequency synthesizer. . . . . . . . 19 1.10 Receiver architecture for 100 Gbps mm-wave Software Defined Radio (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 vii 2.1 Resonator limited phase noise of two oscillators where f 1 Q 1 = f 2 Q 2 holds for resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 Resonator based oscillator . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 Simple cross-section of an FBAR and its associated linear BVD equiva- lent lumped circuit model . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 Small-signal S-parameter measurements of the FBAR and comparison with the BVD model . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5 Measured and fitted values for output fundamental and IM3 tones for 100kHz tone separation . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.6 Nonlinearity measurement setup . . . . . . . . . . . . . . . . . . . . . 28 2.7 FBAR nonlinear model including memory effects . . . . . . . . . . . . 28 2.8 Measured and modeled IM3 values as a function of two-tone frequency separation when the power absorbed by the FBAR is 6dBm . . . . . . . 29 2.9 A general model of a self sustained Oscillator with nonlinear resonator with memory effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.10 Graphical representation of phase noise generation in an oscillator with nonlinear resonator with memory effect . . . . . . . . . . . . . . . . . 36 2.11 Contribution of different noise generation mechanisms in the amplitude, frequency and phase noise power spectral densities . . . . . . . . . . . 36 2.12 Steady-state oscillation frequency change as a function of power incident on the resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.13 Analysis and simulation of phase noise in the self-sustained oscillator shown in Fig. 2.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.14 Analysis and simulation of phase noise as a function of power incident on the resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.15 An FBAR oscillator (a) circuit schematic, (b) equivalent model. . . . . 42 viii 2.16 Phase noise at 1kHz offset as a function of power incident on the res- onator in the Colpitts oscillator . . . . . . . . . . . . . . . . . . . . . . 49 2.17 Schematic of the designed CMOS Colpitts oscillators . . . . . . . . . . 49 2.19 Measurement and simulation of phase noise in the main oscillator . . . 50 2.20 simulated and measured phase noise of the scaled osillator when the the power consumption in the core is 15mW . . . . . . . . . . . . . . . . . 50 2.21 simulated and measured phase noise of the scaled osillator when the power consumption in the core is 20mW together with the theoretical ultimate phase noise of the resonator . . . . . . . . . . . . . . . . . . . 51 2.22 Block diagram of a feedback phase noise reduction scheme . . . . . . . 55 2.23 Transfer function of a phase discriminator, frequency discriminator, and phase-frequency discriminator versus offset frequency ( ) from the input frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.24 (a) Resonator-based phase discriminator (b) resonator based oscillator, (c) phase noise floor of the discriminator. . . . . . . . . . . . . . . . . 58 2.25 (a) Block diagram of the implemented phase-frequency discriminator, (b) Schematic of the notch filter, (c) Schematic of the LNA, (d) Schematic of the mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.26 Comparison of the phase noise floor of the discriminator and an opti- mally designed self-sustained oscillator with the same resonator and power. 61 2.27 Photograph of the resonator-based phase-frequency discriminator CMOS chip wirebonded to the FBAR. . . . . . . . . . . . . . . . . . . . . . . 62 2.28 Notch-filter and LNA combined S-parameters. . . . . . . . . . . . . . . 62 2.29 Phase to voltage transfer function of the phase-frequency discriminator. 64 2.30 Discriminator output noise measurement setup. . . . . . . . . . . . . . 65 2.31 PSD of the Phase-frequency discriminator output noise. . . . . . . . . . 66 ix 2.32 Phase noise reduction scheme. * The portion shown in the dashed box was implemented in the chip but did not work because of a schematic error, and its detail design will not be discussed here. . . . . . . . . . . 66 2.33 Block diagram describing the locking behavior of the feedback phase noise reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.34 (a) Output of the amplitude loop filter (notch depth control), (b) Output of the quadrature mixer (VCO frequency control), (c) LNA output voltage. 70 2.35 Photograph of the phase noise reduction CMOS chip wirebonded to the FBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.36 Output spectrum of the phase noise reduction scheme (a) before locking and (b) after locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.37 Phase noise floor of the phase-frequency discriminator and the output of the phase noise reduction scheme. . . . . . . . . . . . . . . . . . . . . 72 2.38 Proposed feedforward phase noise reduction to overcome feedback band- width limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.39 Phase noise simulation of the feedback and feedback/feedforward schemes. 74 3.1 (a) Conventional injection locked frequency divider and (b) its first order model where the injection device is assumed to be always ON. . . . . . 77 3.2 Different regimes in conventional injection locked frequency divider (a) injection device always ON, self-oscillation occurs (I DC = 820A, V GATE = 1:7V ,W=L = 6m=130nm,V CC = 1:1V ,R ON = 120 , 1 = 14:6mA=V , 3 = 1A=V 3 , K0 = 0:037A=v 2 )(b) injection de- vice always ON, no self-oscillation (I DC = 410A, V GATE = 1:7V , W=L = 6m=130nm,V CC = 1:1V ,R ON = 120 , 1 = 7:3mA=V , 3 = 0:5A=V 3 ,K0 = 0:037A=v 2 ) (c) injection device biased at verge of being ON, self-oscillation happens (I DC = 300A,V GATE = 1:4V , W=L = 6m=130nm,V CC = 1:1V ,R ON = 1000 , 1 = 5:5mA=V ). 81 3.3 Schematic of the proposed distributed injection locked frequency divider. 85 3.4 (a) N-elementLC-ladder , (b) one-sided infinitely longLC-ladder. . . . 86 3.5 Equivalent circuit around the first parallel mode resonance. . . . . . . . 87 x 3.6 Simulated impedances of a 10-element LC-ladder and its equivalent LC tank of Fig. 3.5 (L 1 = 1 nH,C 1 = 625 fF,R 1 = 18 ,C eq = 5:5C 1 ). . . 89 3.7 (a) Short-circuit current from p-th injection in N-element LC-ladder, (b) Equivalent circuit based on double-sided1-elementLC-ladder. . . . . 90 3.8 Analytical and simulated equivalent injection currents of a 10-element distributed and a conventional injection-locked frequency dividers (L 1 = 1 nH,C 1 = 625 fF,R 1 = 18 ,C eq = 5:5C 1 ). . . . . . . . . . . . . . . 93 3.9 (a) Conventional injection locked frequency divider with LC load, (b) Injection-locked frequency divider with a distributed load, (c) Distributed injection-locked frequency divider, (d) Simulated sensitivity curves for the injection-locked frequency dividers of (a), (b), and (c) where theLC- ladders consist of 10 sections, (e) Simulated differential peak to peak swing across the cross-coupled pair in the 10-element distributed injection- locked frequency of (c) whenV inj = 450mV . . . . . . . . . . . . . . . 94 3.10 Micrograph of the mm-wave distributed injection-locked frequency divider. 97 3.11 Schematics of the fabricated mm-wave distributed injection locked fre- quency divider with optimum bias conditions. . . . . . . . . . . . . . . 98 3.12 Measured reflection coefficient of the implemented distributed injection- locked frequency divider. . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.13 Simulation of impedance change due to switched capacitor close to the first parallel mode resonance frequency. . . . . . . . . . . . . . . . . . 100 3.15 Measured phase noise of input (48 GHz), and output signals of the im- plemented distributed injection-locked frequency divider. . . . . . . . . 100 3.16 Simulated and measured sensitivity curves for high and low bands for nominal bias conditions. . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.17 Measured sensitivity curves for high DC current (phase condition limited).102 3.18 Measured sensitivity curves for low DC current (gain condition limited). 103 xi 4.1 (a) Schematic of a cross-coupled pair LC oscillator. (b) Schematic of a power scaled cross-coupled pair oscillator. (c) Cross-coupled oscillator phase noise as a function of power consumption; the unscaled design pa- rameters areL P = 140pH,Q = 10,I BIAS = 4mA,L E = 2m,C P is the parasitic capacitor of the cross-coupled pair, and the oscillation fre- quency is 73 GHz which is very close to the topologyf max = 79GHz. (d) Inductor value versus the achieved phase noise. . . . . . . . . . . . 108 4.2 Power scaling in a single oscillator compared to an array of coupled os- cillators. Both schemes will consumeN times the original power, lead- ing to 10log(N) improvement in phase noise. . . . . . . . . . . . . . . 110 4.3 (a) Schematic of a Colpitts oscillator. (b) Schematic of a frequency- scaled Colpitts oscillator. (c) Phase noise of a frequency-scaled Colpitts oscillator versus frequency. In simulations, Q = 10, L E = 5m, and P DC = 1mW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.4 (a) Schematic of a mm-wave Colpitts oscillator. (b) Simplified equiv- alent model of a mm-wave Colpitts oscillator using a simplified high- frequency large signal transistor model. . . . . . . . . . . . . . . . . . 112 4.5 (a) Equivalent model of the Colpitts oscillator in regime 1. Simulated and analytical (b) oscillation frequency as a function of inductor size, (c) oscillation amplitude as a function of inductor size, and (d) phase noise as a function of oscillation frequency. In transistor-level simulations, L E = 8m,I BIAS = 7mA, andV CC = 1:5V leading toC = 103fF , C = 9fF ,g m = 200mA=V ,R B = 19 , andQ = 20. . . . . . . . . . 113 4.6 (a) Equivalent model of the scaled Colpitts oscillator in regime 2. (b) Optimum device, capacitor and inductor scaling factors as a function of oscillation frequency. (c) Simulated normalized amplitude of oscillation as a function of oscillation frequency, and (d) Analytical and simulated phase noise of the oscillator across the entire frequency scaling range (regimes 1 and 2) and comparison with ideal phase noise scaling. . . . . 120 4.7 (a) Simulated amplitude of oscillation of the cross-coupled pair oscil- lator shown in Fig. 1.a in regime 1 (inductive only scaling), and (b) simulated phase noise of the cross-coupled pair oscillator across the en- tire frequency range (regimes 1 and 2). In these plots,I BIAS = 2:5mA, V CC = 1:5V ,L E = 2:5m, andQ = 10. . . . . . . . . . . . . . . . . 122 xii 4.8 Schematics, chip photos, and measured phase noise of scaled cross-coupled pair oscillators at (a),(b),(c) 67 GHz, (d),(e),(f) 39 GHz, and (g),(h),(i) 26 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.9 Theoretical and experimental phase noiseof scaled oscillators at 1 MHz mm-wave cross-coupled pair oscillators at 1 MHz offset versus oscilla- tion frequency. Measured data points are indicated by solid circles. . . . 125 4.10 Schematics and chip diagram of the 106 GHz Colpitts oscillator. . . . . 127 4.11 Proposed Colpitts oscillator core (a) Differential mode excitation, (b) common-mode excitation, and (c) small-signal simulation of the impedance real part with differential and common-mode excitations. . . . . . . . . 128 4.12 Measurement results of the 106 GHz Colpitts oscillator: (a) output spec- trum, (b) output power and oscillation frequency versus bias current, (c) phase noise profile at 106 GHz, (d) phase noise and output power versus oscillation frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.13 (a) Spectrum measurement setup in W-band. (b) phase noise measure- ment setup in W-band with cross-spectrum measurement capability. . . 130 4.14 Schematic and chip photo of the frequency-scaled 148 GHz Colpitts os- cillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.15 Measurement results of the 148 GHz oscillator: (a) output spectrum, (b) output power and oscillation frequency versus bias current, (c) phase noise profile at 148 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.16 Comparison of measured differential Colpitts oscillators with simulated optimum scaled phase noise of this topology. . . . . . . . . . . . . . . 133 4.17 (a) Proposed coupling scheme. (b) Differential mode coupling (cannot be sustained). (c) Common-mode coupling. . . . . . . . . . . . . . . . 134 4.18 Schematic of the 8-element common-mode coupled oscillator. . . . . . 137 4.19 Measurement results of the 8-element common-mode coupled oscilla- tor: (a) output spectrum directly read from spectrum analyzer, (b) de- embedded output power and oscillation frequency versus bias current, (c) phase noise with 1 and 10 cross-correlations at 105.6 GHz. . . . . . 139 xiii 4.20 Chip microphotograph of the 8-element common-mode coupled oscillator. 139 A.1 Bandpass filter used to model memory effect with an amplitude and phase modulated input . . . . . . . . . . . . . . . . . . . . . . . . . . 155 B.1 Cross-section of the metal stack used in the integrated implementations 158 B.2 SiGe HBT bipolar transistor (a) layout with two collector connections, (b) simplified small signal model, (c) maximum oscillation frequency versus current density. The emitter length of the example device is 3 m. 159 B.3 130 nm NMOS transistor (a) layout with two fingers, (b) simplified small signal model, (c) maximum oscillation frequency versus current density. For the example device, W/L=2 m/130 nm. . . . . . . . . . . . . . . 159 B.4 Microstrip transmission line (a) geometry, (b) equivalent model, (c) imag- inary part of input admittance, (d) real part of input admittance, (e) qual- ity factor when used as an inductor. . . . . . . . . . . . . . . . . . . . . 160 B.5 Differential MIM capacitor (a) four-finger geometry, (b) equivalent model, (c) imaginary part of input admittance, (d) real part of input admittance, (e) quality factor versus frequency. . . . . . . . . . . . . . . . . . . . . 161 xiv Abstract The exponential demand for higher data rates has resulted in aggressive use of com- munication resources in wireless radios. On one end, in Radio Frequency (RF) radios, this has led to using complex modulations (e.g., 1024-QAM in the upcoming 802.11AX WiFi aiming at 10 Gbps throughput) for spectral efficient communications. On another end, migration to mm-wave frequencies (e.g., fifth generation (5G) cellular in 28 GHz, 38 GHz, and beyond) is aiming to leverage the 100 GHz available bandwidth from 30- 300 GHz. Both these trends result in challenges in design of wireless transceivers in RF and mm-waves. Specifically, frequency synthesizers used in transceivers for frequency translation and data conversion need to meet challenging specifications in terms of phase noise and tuning range. This thesis is dedicated to the study of architectures and circuit techniques to tackle these challenges in frequency generation systems for future radios. A two-stage Phase Locked Loop (PLL) architecture is proposed that enables mm- wave wireless radios with 100 Gbps throughput. The architecture employs very low phase noise RF oscillators, low phase noise mm-wave coupled oscillators, and wide lock- ing range frequency dividers. These low phase noise and/or wide frequency range blocks xv are proposed, designed, and implemented based on theoretical treatment of their perfor- mance limits. Theory of phase noise in RF self-sustained oscillators with nonlinear resonators is developed and used to design and implement RF oscillators with less than 10 fs integrated jitter. Phase noise reduction schemes are studied theoretically and through integrated implementations as an alternative to self-sustained oscillators. Theory of phase noise scaling of mm-wave oscillators is developed and experimen- tally verified by implementing mm-wave oscillators in the range of 20-150 GHz. Based on a proposed coupling scheme, a 106 GHz 8-element coupled oscillator is designed and implemented with record phase noise among Silicon mm-wave oscillators. Concept of distributed injection-locked frequency division is introduced as a method to expand the operation frequency of injection-locked frequency dividers beyond conven- tional limits. An integrated implementation of this concept reaches close to one octave locking range in mm-wave frequencies. xvi Chapter 1 Frequency generation for mm-wave wireless transceivers We live in a world where demand for higher data rates is exponentially increasing with time. Mobile data traffic has grown 4,000-fold over the past 10 years and almost 400- million-fold over the past 15 years, consumed by more than 0.5 Billion mobile devices [1]. Global mobile traffic is predicted to reach 30.6 exa Bytes per month in 2020 [1], an 8-fold increase in less than 5 years. In the consumer world, this increase is driven, now and in the future, by proliferation of smart mobile devices (on-average, each smart device consumes 14 times more data than a non-smart phone), increased demand for connectivity (i.e. WiFi) for bandwidth intensive applications such as real time HD video and multimedia (3=4 th of mobile data traffic will be video by 2020), live gaming, and emerging technologies like Augmented Reality, etc [1]. This trend will be accelerated by Machine-to-Machine (M2M) connectivity (i.e. Internet of Everything (IoE), including 600 Million wearable devices by 2020). In fact, the fifth generation (5G) networks are predicted to be driven largely by IoE applications [1]. 1 Next generation communication and connectivity networks aim at addressing this data demand in the future. To improve data throughput in these networks, two general approaches are considered: 1- More efficient use of the traditional wireless frequency spectrum (< 6 GHz). This is enabled by smart and cognitive radios (i.e., spectrally aware and smart allocation of bandwidth resources), use of more complex modulations to cram more data into the same bandwidth, carrier aggregation, multiple input multiple output (MIMO) techniques, etc. 2- Migrating to mm-wave frequencies. The 30-300 GHz frequency range contains large contiguous spectrum bands that can potentially be leveraged for high data rate wireless networks. It has been recently shown that through multi-antenna transceivers (beamforming and MIMO techniques) and network optimization, these frequencies can be adopted for cellular communication (5G) and Wireless connectivity (WiFi 802.11ad and WiGig) [2]. Current standards in mm-wave use relatively simple modulations (BPSK, QPSK, 16 QAM, and 64 QAM in 802.11ad [3]) to reach data rates of up to 7 Gbps (28 Gbps if 4 4 spatial time multiplexing is used). To further increase these data rates, more complex modulations (such as 256-QAM and 1024-QAM) may be used in the future. Even now, for microwave and mm-wave backhaul applications, 4096-QAM is used to increase the throughput [4]. Furthermore, the high non-recurring engineering cost as- sociated with mm-wave wireless transceivers in state-of-the-art technologies and large number of designated mm-wave frequency bands as shown in Fig. 1.1, each with a wide 2 Figure 1.1: mm-wave spectrum and designation of bands. contiguous bandwidth, for the same or similar applications, motivate wideband software programmable mm-wave transceivers and related building blocks. This vision introduces several interesting challenges in the transceiver implementation. In particular, the required frequency synthesizer and data conversion clock will have a set of very challenging specifications. The frequency synthesizer needs to have low phase noise to enable complex modulations, and needs to be wideband to enable the im- plementation of a mm-wave Software Defined Radio (SDR). The data conversion clock needs to have very low jitter because of the high required Signal to Noise Ratio (SNR) and wide signal bandwidth. In the remainder of this chapter, we will first quantify the effect of Local Oscillator (LO) phase noise on the performance of wireless transceivers. Then, we will cover system design of a mm-wave wireless transceiver (with focus on fre- quency synthesizer and data conversion clock) to enable 100 Gbps data rate in mm-wave frequencies. 3 1.1 Phase noise and jitter definitions The majority of the work in this thesis deals with phase noise and techniques to reduce it in RF and mm-wave systems. Engineered systems often require a time reference to perform tasks, operations, data collection, and signal processing. The performance of different systems like radars, wireline and wireless transceivers, etc., is tightly coupled to the quality of the time reference in the system. A major block in frequency generation systems is called self-sustained oscillator. A self-sustained oscillator is an autonomous nonlinear dynamical system that has an output signal which is periodic in time ,i.e., x(t +T 0 ) = x(t). In absence of noise, the Fourier transform of this signal contains impulses at integer multiples off 0 = 1 T 0 . In presence of noise, the spectrum of a self- sustained oscillator spreads around its center frequency (and harmonics), and the period of the signal varies over time. The output of a self-sustained oscillator with a sinusoidal waveform, in presence of noise, can be written as x(t) = (a s +a(t))cos(2f 0 t +(t)); (1.1) wherea s is the steady state amplitude of oscillation,a(t) is the time-varying amplitude noise, and (t) is the phase noise (also called PM noise). Statistics and properties of (t) are in general of more interest compared to a(t), since (t) is a measure of time uncertainty and also becausea(t) can be suppressed by using a hard amplitude limiter (we will discuss AM-FM conversion in detail in a later chapter). The Power Spectral 4 Density of(t) is not flat in general and therefore, phase noise is typically measured and reported at different offset frequencies from the carrier frequency, f 0 . Throughout this thesis, the offset frequency is denoted by f in Hz or in rad/sec. By definition, phase noise at f offset frequency is the power of the signal (neglecting its amplitude noise) at f offset frequency over a 1 Hz bandwidth divided by the total power of the signal with units of dBc/Hz. Due to the double sideband nature of phase modulation, this can be written as L(f) = 10log( 1 2 S (f)); (1.2) where L(f) is the phase noise at f offset frequency in dBc/Hz and S (f) is the power spectral density of the PM noise (t). It should be noted that in most phase noise measurement techniques, the PSD ofsin((t)) is measured. In general,(t) and sin((t)) have different PSDs [5]. They are, however, pretty close at offset frequencies of interest [5] and are interchagably used in simulations and measurements. In presence of white noise, the phase noise of self sustained oscillators can be mod- eled as a Wiener process (Appendix A). This means that, in general,(t) has a variance that increases linearly with time and formally, a PSD cannot be assigned to it. However, bothsin((t)) andcos(!t +(t)) will be stationary with Lorentzian PSD [5]. This type of phase noise is typically referred to as white FM noise, random-walk PM noise, or 20 dB/dec region 1 . In practice, there will also be a phase noise floor which is usually set 1 for non-white sources of noise in practical oscillators, the PSD of(t),sin((t)), andcos(! 0 t+(t) will all be different in presence of these non-white noise sources 5 Figure 1.2: Example phase noise profile of a practical self-sustained oscillator as a func- tion of offset frequency. by the output buffer that follows the oscillator; this is referred to as white PM noise. At lower frequency offsets, modulation of the oscillator phase by flicker noise sources will result in a phase noise region which is called flicker FM noise. These different domains in an oscillator phase noise PSD are summarized in Fig. 1.2. As a specific example, the phase noise of common quartz crystal oscillators (often referred to as frequency ref- erences in the context of phase-locked loops), is dominated by the white PM noise in the offset frequency range of interest. For this reason, the phase noise PSD of crystal oscillator is assumed to be flat in the literature and throughout this thesis. Another useful measure of phase noise is rms phase noise (with units of dBc or degrees). This measure is formally defined as rms = s Z 1 f=0 S (f)df; (1.3) 6 This formal definition will lead to infinite rms phase noise. A more practical defini- tion of rms phase noise is rms = s Z f H f=f L S (f)df = s 2 Z f H f=f L 10 L(f 10 df; (1.4) where f L and f H are lower and upper bounds of integration set by the application. In communication systems,f L is usually set by the packet rate. Jitter is a measure of uncertainty in time for oscillators and is tightly related to the phase noise process as jitter(t) = (t) 2f 0 : (1.5) It is clear that rms jitter may be defined asjitter rms = rms 2f 0 . Depending on applica- tion, different statistics of this process might be of interest. For example, period jitter is defined as the uncertainty in one period of the signal PJ(t) = (t)(tT 0 ) 2f 0 ; (1.6) and its rms value can be calculted as (PJ) rms = 1 2f 0 Z 1 =0 1e j T 0 2 S ( )d : (1.7) 7 1.2 Effect of phase noise in communications throughput 1.2.1 M-QAM signals For a given communications bandwidth, data rate may be increased by using more com- plex modulations while demanding more SNR. Increasing number of bits per symbol will increase bandwidth efficiency (bits/Hz), but makes the system more susceptible to non-idealities such as noise, nonlinearity, I/Q imbalance, and phase noise [6][7]. Figure 1.3.a shows ideal signal constellation of a 64-symbol Quadrature Amplitude Modulation (QAM) scheme. For an M-QAM signal,log 2 (M) bits are sent per symbol; and therefore, the achievable data rate can be written as Bit Rate = 2log 2 (M)BW bps, where BW is the bandwidth of the communication channel in Hz. Figure 1.3.b shows Symbol Error Rate (SER) versus SNR for an Additive White Gaussian Noise (AWGN) communica- tion channel [8]. As expected, for a given acceptable SER, more complex modulation requires higher SNR ( 6 dB per quadrupling M). As an example, a 1024-QAM signal can lead to a 10-fold increase in spectral efficiency compared with BPSK while requiring 36 dB SNR for< 10 3 symbol error rate. In presence of phase noise, the signal constellation rotates causing SER to increase [6][7]. The modulated signal in baseband can be written as x(t) =x BB (t)e j(t) +n(t); (1.8) 8 wherex BB (t) is the modulated signal,e j(t) is the representation of phase noise, andn(t) is an additive noise. Notice that the effect of phase noise is multiplicative. This results in a nonlinear interaction of noise and phase noise, and prevents us from using super- position. Figure 1.4.a shows the MATLAB Simulink model used to simulate the effect of phase noise on the SER of an M-QAM signal. In an unlocked oscillator, phase noise can be modeled as a Wiener process with a variance that increases linearly with time (as discussed in detail in the next Chapter). However, the phase noise of oscillators that are locked to a reference source (such as quartz crystal oscillators as discussed before) may be approximated a Gaussian process with variance 2 rms . For a locked oscillator, the rms phase noise may be expressed as rms = s 2 Z 1 f=0 10 L(f) 10 f; (1.9) where L(f) is the phase noise measured at offset frequency f in units of dBc/Hz. Figure 1.4.b shows the 64-QAM signal constellation with SNR=25 dB and no phase noise leading to SER=2 10 4 . Figure 1.4.c and 1.4.d show the signal constellation for 3 o rms phase noise with and without the additive noise. It can be seen that the combined effect of additive noise and phase noise leads to much higher SER. Figure 1.5 shows SER simulations for 64 and 1024-QAM signals for different values of rms phase noise. For rms = 0:5 o and target SER< 10 3 , a 1024-QAM will require SNR 39 dB which is 3 dB higher compared with the case with no phase noise. This translates to either a lower communication range or requiring twice transmit power for the same range. For 9 Figure 1.3: (a) 64-QAM signal constellation, (b) SNR versus SER for M-QAM signals in AWGN communication channel. rms = 0:3 o , the effect of phase noise on required SNR will be less than 1 dB, which may be considered a good target for a 1024-QAM signal constellation. 1.2.2 OFDM signals Orthogonal Frequency Division Multiplexing (OFDM) is a scheme that is being used very frequently in high throughput communication systems. In this scheme, the avail- able bandwidth is divided into multiple narrow sub-channels with orthogonal sub-carriers [9]. Each sub-carrier is modulated and coded with independent data streams (e.g., modu- lated M-QAM signals). The high spectral efficiency and resiliency to frequency selective fading [9] are some of the reasons for widespread use of OFMDM in advanced commu- nication signaling. Figure 1.6 shows a typical OFDM transmitter and receiver along with frequency spectrum of an OFDM signal with orthogonal sub-channels. Phase noise affects an OFDM signal integrity in two ways: 10 Figure 1.4: (a) Simulink model to simulate the effect of phase noise on M-QAM signal, (b) 64-QAM constellation with SNR=25 dB and no phase noise (SER=2 10 4 ), (c) 64-QAM constellation with SNR=1 dB and 3 o rms phase noise (SER=2 10 3 ), (d) 64-QAM constellation with SNR=25 dB and 3 o rms phase noise (SER=2 10 2 ). Figure 1.5: Simulated SER versus SNR for 64-QAM and 1024-QAM signals for different phase noise. 11 Figure 1.6: (a) An OFDM transmitter architecture, (b) An OFDM receiver architecture, (c) Frequency spectrum of an OFDM signal highlighting orthogonal subcarriers (d) Fre- quency spectrum of an OFDM signal in presence of phase noise highlighting Inter Carrier Interference. 1- Similar to a one-carrier M-QAM architecture described in previous Section, the signal quality of each sub-channel depends on phase noise. 2- The presence of phase noise will cause Inter-Carrier Interference (ICI), that will affect the overall SNR [7][10][11][12]. Figure 1.6.d shows how phase noise causes unwanted leakage among adjacent sub- channels in the adjacent sub-channels. Each subcarrier will result in a portion of phase noise to appear in the subcarrier band of interest. Assuming equal amplitude for all subcarriers. The worst ICI corresponds to the middle subcarrier and can be written as ICI = Z BW 2 f= BW 2N S (f)d(f); (1.10) 12 Figure 1.7: Effect of LO phase noise in reciprocal mixing. where BW is the total communication bandwidth, N is the number of subcarriers, f is offset frequency from LO carrier, andS (f) is the Power Spectral Density of the noise in phase of the LO signal. 1.2.3 Reciprocal mixing A well-known effect of phase noise on the performance of communication systems is re- ciprocal mixing [13]. As illustrated in Fig. 1.7, phase noise frequency down-converts the adjacent blockers to the same frequency of the down-converted desired channel, degrad- ing the overall SNR. This is a major concern in RF transceivers where in-band blockers can be much stronger than the desired signal. In mm-wave receivers, this effect is less of a concern, since there is generally less interference and interference mitigation through RF beam-forming is a possibility. 13 1.2.4 Data conversion Data conversion is an important function in modern transceivers. In wireless receivers, the received analog signal after amplification, frequency down-conversion, and filtering is converted to a digital signal using an Analog to Digital Converter (ADC) for further digital processing. An ADC can be modeled as a sampler (as shown in Fig. 1.8), followed by a quantizer. A uniform sampling ADC uses a sampling clock to digitize the signal at periodic time instances. Phase noise in the sampling clock causes uncertainty in sampling times (also referred to as timing jitter), which will introduce error in the samples as shown in Fig.1.8. An ideal B-bit quantizer with 2 B levels introduces an error in its output with a frequency spectrum that may be approximated with a white noise [14]. The SNR of an ideal quantizer due to this quantization noise can be written as [15] 2 SNR(dB) = 6:02B + 1:76: (1.11) The effect of sampling clock phase noise (or equivalently timing jitter) on the SNR of an otherwise ideal sampler can be written as [15] SNR =20log(2 f sig ); (1.12) where is the rms jitter and f sig is the maximum frequency of the input signal. In a communications scenario, can be related to phase noise as 2 This is the motivation behind defining Effective Number of Bits (ENOB) for a non-ideal quantizer as ENOB = SNDR(dB)1:76 6:02 : 14 Figure 1.8: Sampling error due to ADC clock phase noise (or timing jitter). = 1 2f clk s 2 Z f clk =2 f=1=T frame 10 L(f) 10 d(f); (1.13) wheref clk is the frequency of the clock, andT frame is the time duration of a communica- tion frame. The assumption is that the communication receiver performss ideal synchro- nization at the beginning of each data frame. 1.3 Transceiver system design of a 100 Gbps SDR To get to the vision of a mm-wave SDR with 100 Gbps data rate, several challenges need to be overcome in different layers of the communication system. Here, we will study a communication scheme for this data rate and find its ramifications on the frequency generation sub-system within the transceiver architecture. We make the following system level assumptions: 1- The available bandwidth is 5 GHz with a center frequency of 60 GHz. We do not consider the required bandwidth for coding in what proceeds. 15 2- The signal modulation is 1024-QAM with 2048-subcarrier OFDM. This will result in an achievable data rate of 50 Gbps. The sub-carrier spacing is 2.4 MHz. Subcarrier spacing is determined by system level considerations such as the effect of multi-path fading and Doppler [16] and its detailed derivations are beyond the scope of this thesis. 3- To get to 100 Gbps, a 2 2 MIMO scheme is considered. Two sets of indepen- dent beams are received by an antenna array (spatial multiplexing), and demodulated by two separate receivers, resulting in 100 Gbps aggregate data rate. The number of an- tennas used will affect the range and required transmitted power 3 and will not affect the specifications of the receiver frequency synthesizer. From Section 1.1.1., for a 1024-QAM modulation, rms phase error of 0:28 o will result in a required SNR 37:5 dB for SER=10 3 . Consider the phase locked loop shown in Fig. 1.9.a. A phase locked loop is a feedback system that enables a voltage controlled oscillator to lock in frequency and/or phase to a reference (typically a quartz- crystal oscillator). Detailed analysis of phase locked loops will be covered in the next chapter. Here, it suffices to note that the transfer function from the reference phase noise to the output phase noise will be low pass with a gain of N, where N is the frequency division ratio between the VCO and the reference. The transfer function from VCO phase noise to the output phase noise is high-pass with the same 3-dB bandwidth as that of the reference transfer function. The crystal reference oscillator can be assumed to have a flat phase noise floor. A typical number for the phase noise floor of a 40 MHz 3 An N-element phased array can result in a 10log(N) improvement of SNR given the same total trans- mitter power. 16 reference clock is -150 dBc/Hz (-86 dBc/Hz when referred to the 60 GHz PLL output). If we assume that the VCO phase noise is a Wiener process (i.e., -20 dB/dec phase noise profile), from (1.9), in order to reach 0:3 o rms phase noise, the required phase noise of the 60 GHz VCO needs to be less than -130 dBc/Hz at 1 MHz for loop bandwidth of 5.4 kHz 4 . From the theory of phase noise scaling, and also by looking at state of the art (both discussed in detail in the last chapter of this thesis), it is extremely challenging, if not impossible, to implement a mm-wave VCO with this specification. To overcome this limitation, we propose a two-stage PLL structure as shown in Fig.1.9.b. The first stage PLL locks a high frequency Film Bulk Acoustic Resonator (FBAR) based oscillator to a crystal quartz oscillator. Typical resonance frequency of a commercial FBAR is at the GHz range. As will be discussed in detail in the next chapter, this will result in lower phase noise at higher offset frequencies when compared to the MHz-range crystal oscillator phase noise referred to the same frequency. The output of the first PLL acts as a high frequency reference to the mm-wave PLL. The overall two- stage PLL rms phase noise can be much smaller than that of the single-stage approach. Figure 1.9.c compares the overall phase noise of the single-stage and two-stage PLL approaches. PN 1 is the output referred phase noise of the crystal oscillator, and is the same for single-stage and two-stage PLL architectures (-86 dBc/Hz). PN 3 is the phase noise floor of the FBAR oscillator referred to 60 GHz output. We have implemented FBAR oscillators with phase noise floor of -160 dBc/Hz as discussed in the next chapter 4 the loop bandwidth is chosen at the intersection of frequency reference output referred phase noise and mm-wave oscillator phase noise to minimize rms phase noise of the PLL output 17 (PN 3 =160+20log( 60GHz 1:5GHz) ) =128dBc=Hz). If we consider the phase noise profile of our implemented FBAR oscillator, the loop bandwidth of the 1 st PLL should be set to 5 kHz for lowest achievable rms phase noise 5 . If the mm-wave VCO phase noise is designed to have a phase noise of -108 dBc/Hz at 1 MHz offset (which is practical as proved experimentally in the last chapter of this thesis), then the rms phase noise of the two-stage PLL architecture is 0:28 o which will require an SNR=37.5 dB forSER< 10 3 in a 1024-QAM architecture. If we assume the same mm-wave VCO phase noise of -108 dBc/Hz for the single-stage design, the rms phase noise will be 1:68 o . With this rms phase noise, a 1024-QAM signal cannot reachSER> 0:01 even if SNR is infinity. This rms phase noise would result inSER< 10 3 for a 64-QAM modulated signal with an SNR=30 dB. This means that the achievable data rate is now reduced to 30 Gbps (60 Gbps for 2 2 spatial multiplexing). The next step is to calculate the effect of ICI. From (1.3), the ICI can be derived by integrating phase noise profile of the two-stage PLL as ICI = Z 2:5GHz f=1:25MHz S (f)d(f)58dB: (1.14) Given the required SNR of 37.5 dB, the effect of ICI is negligible due to the phase noise of the two-stage PLL. Figure 1.10 shows a possible receiver architecture utilizing the proposed frequency synthesizer scheme to reach 100 Gbps over 5 GHz bandwidth. 5 This is due to the fact that the implemented FBAR oscillator has a phase noise of -120 dBc/Hz at 5 kHz offset. When referred to the output of the second PLL, this phase noise equals -86 dBc/Hz which is equal to the quartz oscillator phase noise referred to the same output. 18 Figure 1.9: (a) Conventional PLL-based frequency synthesizer for mm-wave SDR, (b) proposed two-stage PLL-based frequency synthesizer. 19 The architecture requires a 10 GS/sec Nyquist ADC. The overall SNR of the system after data conversion needs to be higher than 37.5 dB. If the contribution of the ADC quantization noise is chosen to be less than 1 dB in the overall SNR, then the SNR of the ADC needs to be larger than 44 dB, which means that the ADC needs to have 7 bits ENOB. Considering all the nonidealities, the ADC needs to be designed with 8 bits. If the ADC SNR due to the clock jitter is chosen to be 47 dB, the required clock jitter can be found from (1.5) to be 142 fs. As shown in Figure 1.10, the reference clock is generated by frequency multiplying the output of the first stage PLL. For a frame rate of 1 ms, and using (1.6), the overall jitter will be less than 10 fs. This is found by integrating the phase noise of the locked FBAR oscillator from 1 kHz to half the FBAR oscillator frequency (eqn. 1.13). The proposed two-stage PLL frequency generation scheme enables an SDR with 100 Gbps communication over a 5 GHz bandwidth. The first stage PLL is acting as a high frequency reference for the second stage PLL. Low phase noise high frequency genera- tion will be discussed in detail in Chapter 2. The second stage mm-wave PLL requires wideband voltage controlled oscillators and frequency dividers. In Chapter 3, distributed injection-locked frequency division concept is introduced as an effective method to in- crease the operation frequency range of frequency dividers. The bottleneck in the overall rms phase noise of the two-stage PLL architecture is the mm-wave VCO. Theory of phase noise scaling in mm-wave frequencies together with implementation of very low phase noise mm-wave oscillators will be discussed in Chapter 4. 20 Figure 1.10: Receiver architecture for 100 Gbps mm-wave Software Defined Radio (SDR). 21 Chapter 2 High-frequency reference design In Chapter 1, we proposed a two-stage PLL architecture for low phase noise mm-wave frequency synthesis over a wide frequency range. The first PLL provides a low phase noise radio-frequency reference for the second mm-wave PLL. The key building block in the first PLL is a low-phase noise radio-frequency V oltage Controlled Oscillator (VCO). In this chapter, theory and techniques in implementing low phase noise radio-frequency oscillators and frequency-stabilized sources will be discussed. The proposed the first stage PLL locks a radio-frequency piezo-electric thin Film Bulk Acoustic Resonator (FBAR) oscillator to a low-frequency piezo-electric quartz crystal oscillator (Fig. 1.9). We will discuss the details of FBAR oscillators in detail in this chapter. Consider two high quality factor piezo-electric resonators, and assume f 1 Q 1 =f 2 Q 2 ; (2.1) f 2 =Mf 1 ; (2.2) 22 Figure 2.1: Resonator limited phase noise of two oscillators wheref 1 Q 1 = f 2 Q 2 holds for resonators. wheref 1 ,Q 1 ,f 2 , andQ 2 represent the resonance frequency and quality factor of the first and second resonators, respectively, andM > 1. This relationship approximately holds for crystal and FBAR resonators [49] 1 . Using Leeson model for phase noise[17], the resonator limited phase noise of the oscillators using these resonators when referred to the higher frequency f 2 are shown in Fig. 2.1. In Fig. 2.1, the assumption is that the power consumption in the core oscillator and output buffer is the same for the two oscil- lators and the added phase noise of the output buffers are equal. This resonator-limited phase noise relationship is the reason why the first stage PLL in Fig. 1.9 can achieve very low phase noise over a wide range of offset frequencies. By properly designing the PLL loop, the output phase noise will follow the phase noise of the crystal oscillator at low offset frequencies and that of the FBAR oscillator in higher offset frequencies, resulting in an overall low phase noise. 1 The product f.Q is often used as a figure-of-merit for resonators 23 2.1 Phase noise in oscillators with nonlinear resonators Many self-sustained oscillators can be modeled with a resonator coupled to a nonlinear element [17] (Fig. 2.2). In these resonator based oscillators, it is well known that the phase noise improves as the incident power on the passive linear resonator increases [17][18]. Motivated by the application benefits of miniature engineered systems, and enabled by advancements in fabrication, high quality nano-resonators have become mainstream [19][20][21][22]. Miniature resonators have nonlinear dependency on the incident power at modest power levels [23][24][25][26]. This resonator nonlinearity affects the nonlin- ear dynamics and stochastics of self-sustained oscillators. Several papers have reported oscillators using nano-resonators with measured phase-noise plots that diverge from sim- ple models that assume a linear resonator [27][28][29]. Theoretical papers analyzing this effect also exist [30][31][32][33]. Moreover, experimentalists continue to pursue theo- retical predictions that resonator nonlinearity, if exploited properly, can enhance oscilla- tor phase-noise [35]. Yurke, et al. have provided a comprehensive theoretical analysis of nonlinear oscillator noise with a nonlinear resonator, and showed phase-noise sup- pression due to resonator nonlinearity under suitable conditions [33]. In their approach, amplitude and phase fluctuations are assumed to be small leading into linearization of the steady-state solution, and hence, finding linear stochastic differential equations for the amplitude and phase fluctuations that can be solved. Lin He, et al. use a state-space approach to form stochastic differential equation for phase and amplitude fluctuations in 24 Nonlinear active Core Passive Resonator Figure 2.2: Resonator based oscillator a nonlinear Micro Electro Mechanical System (MEMS) oscillator, that is solved numer- ically by a computer [30]. Pardo, et al. suggest an empirical model for the phase-noise of nonlinear MEMS oscillators [35]. This modification to Leeson’s empirical phase- noise expression was experimentally validated in [34]. Ward, et al. model the parametric amplitude to phase fluctuation conversion due to resonator nonlinearity to provide an in- tuitive expression for oscillator phase-noise [32]. Despite these publications, a generic approach to analysis of nonlinear oscillators that lead to optimum designs does not exist. 2.1.1 FBAR nonlinear model Thin Film, Bulk Wave Acoustic Resonators, or FBARs, work based on piezo-electric principle. In the FBAR used in this Chapter’s work, a thin piezo-electric AlN is used as the piezo-electric material and is sandwiched between two electrodes [47]. The size of the mechanical resonator structure is typically around 100m 100m [48]. Figure 2.3 shows the well-known modified Butterworth-Van Dyke (BVD) linear equiv- alent lumped circuit model for an FBAR around its fundamental resonance mode. L m , 25 C m , andR m represent electrical circuit equivalent components for the mechanical res- onator, and are referred to as motional inductance, capacitance, and resistance, respec- tively.C 0 represents the electrical capacitance between the FBAR terminals, andR s rep- resents the ohmic loss of the electrode contacts. There is a series resonance frequency, ! r = 1 p LmCm , determined primarily by the thickness of the AlN film, and a parallel resonance frequency,! p = 1 q Lm( CmC 0 Cm +C 0 ) . The equivalent circuit parameters may be de- rived by fitting the one-port small-signal S-parameter FBAR measurements to those of the model simulations. One-port small-signal S-parameter measurements of our sample FBAR represented on a Smith Chart as well as on real and imaginary impedance axes versus frequency are shown in Fig. 2.4. This FBAR has a series resonance frequency of 1.485 GHz with an unloaded quality factor of 1570 at series resonance. Measurements of five FBAR samples show consistent results. There are a few ways to measure and characterize the nonlinearity of a passive resonator under large incident power levels. A common technique has been to measure and show the impedance versus frequency for different incident power levels [24]. A more accurate method is the two-tone test where the values of Inter Modulation (IM) products that are caused due to nonlinearity are mea- sured [37]. Nonlinear terms can be incorporated in one or some of the lumped equivalent circuit parameters to capture the measured resonator nonlinearity. For instance, a third- order polynomial relating the magnetic flux to the current of the inductor, L m , in the FBAR model is sufficient to fit the experimental data. Figure 2.5 shows the measured and fitted values for output fundamental and IM3 tones when the input two tones are 26 Figure 2.3: Simple cross-section of an FBAR and its associated linear BVD equivalent lumped circuit model Figure 2.4: Small-signal S-parameter measurements of the FBAR and comparison with the BVD model separated by 100 kHz. The measurement setup is shown in Fig. 2.6. A 1 pF capacitor is put in series with the FBAR to improve the impedance matching and power delivery to the FBAR. -5 0 5 10 -100 -80 -60 -40 -20 0 Input Power (dBm) Main and IM3 output power (dBm) Main tone (Simulation) IM3 (Simulation) Main tone (Measurement) IM3 (Measurement) Figure 2.5: Measured and fitted values for output fundamental and IM3 tones for 100kHz tone separation 27 Cs=1pF Spectrum Analyzer Hybrid Δ Σ 50 Signal Generator 1 Signal Generator 2 Circulator PA OIP 3=44dBm Figure 2.6: Nonlinearity measurement setup C 0 =1.1 pF R s =1 Ω R m =1.68 Ω C m=25 fF ) (I Φ I R 0=8 Ω 37500 ) ) ( 15 . 05 . 0 .( 450 ) ( )) ( ( 2 3 2 0 0 2 0 = ∗ + + = Φ + + = NL NL NL Q I h I I I nH I Q s s Q s t h L ω ω ω Figure 2.7: FBAR nonlinear model including memory effects During two-tone measurements, we observed that the relative value of IM products and fundamental tones changes as a function of two-tone frequency separation (also ob- served in [37]). Notice that this effect is observed when the tone separation is low and within the resonator peak, and cannot be modeled with a memory-less nonlinearity. This indicates that the resonator nonlinearity includes memory effects. We propose a new analytical model for the resonator nonlinearity including this memory effect (Fig. 2.7) [68]. In this model, the nonlinearity of the FBAR is modeled by adding two nonlinear terms to the magnetic flux () versus current (I) equation ofL m . The first nonlinear term models the nonlinearity at higher tone separations and the second term will increase the IM products at lower tone separations through the convolution with the impulse response of a band pass filter with impulse response h(t). Figure 2.8 shows the measured and modeled IM3 values as a function of two-tone frequency separation when the FBAR absorbed power is 6 dBm. 28 10 3 10 4 10 5 10 6 -8 -6 -4 -2 0 Offset frequency (Hz) Peak IMD3 level (dBm) Measurement Simulation Figure 2.8: Measured and modeled IM3 values as a function of two-tone frequency sep- aration when the power absorbed by the FBAR is 6dBm 2.1.2 General formulation and analysis 2.1.2.1 Problem formulation A generic self-sustained nonlinear oscillator can be modeled with a nonlinear active core that is coupled to a resonator (Fig. 2.2). The nonlinear active core provides energy to build and sustain the oscillations, and the resonator sets the oscillation frequency. The nonlinearity of the resonator typically manifests itself in the energy storage element of the resonator, e.g., the nonlinear relationship between the restoring force in a mechanical resonator and displacement [27]. The resonator close to its resonance can be modeled with a second-order system, where typically, the energy oscillates back-and-forth be- tween two different energy storage mechanisms. An electrical equivalent model for a second-order resonator can be made using an inductor and a capacitor. A resistor is always needed in the model to capture the resonator loss (and noise). The resonator nonlinearity can be incorporated in the model for either or both of these energy storing elements. The resonator nonlinearity can include memory effects too. In this section, a simplified nonlinear parallel RLC resonator model is motivated by measurements of 29 FBARs showing nonlinear and memory effects (Fig. 2.9). While this model does not capture both series and parallel modes, the analysis using the simplified parallel tank will lead to results related to amplitude and phase noise that are qualitatively the same as the ones with the complete FBAR model; we will show a complete analysis using the FBAR model in next section. This simplified model is used in this section to give insight about the effect of nonlinearity and memory of the resonator on phase noise. The nonlinearity with memory effects is captured in the inductor magnetic flux () - current (I) relationship as (I) =L 0 (I + L 1 I 3 + L 2 (Ih) 2 :I); (2.3) whereL 0 is the inductance at small power levels and the second term, including L 1 , models the nonlinearity. The third term, including L 2 , captures the memory effect through convolution () of the current,I, with a band-pass filter impulse response,h, the Laplace transform of which is given by H(s) = !s Q NL :s s 2 + !s Q NL :s +! 2 s ; (2.4) where! s is the steady state oscillation frequency andQ NL is a fitting parameter. 30 C + - V R I a =f(V) In(t) φ(I) I Nonlinear Resonator Model Active Core Noise Source D (f) S n I = 3 3 1 V α V α I a − = 0 0 0 2 2 3 1 0 1 ) ) ( ( ) ( Lω R , Q C L ω I h I L I L I L I = = ∗ Δ + Δ + = φ Figure 2.9: A general model of a self sustained Oscillator with nonlinear resonator with memory effect The complete model for the self sustained nonlinear oscillator with the aforemen- tioned nonlinear resonator is shown in Fig. 2.9 where the nonlinear active core is mod- eled as a voltage dependent nonlinear current source f(V ). Without the loss of gen- erality in the approach, a third-order polynomial is used to model f(V ), i.e., f(V ) = 1 V 3 V 3 . Current source,I n (t), models all the noise that originates from the non- linear active core and the passive resonator. The noise of the active circuitry may include thermal, shot and flicker noise sources and is often cyclostationary in steady-state opera- tion of a self-sustained oscillator [41]. The passive resonator noise is typically dominated by a thermal source and also has a flicker component [42]. 2.1.2.2 Analysis Consider the oscillator model shown in Fig. 2.9. Taking the voltage across the capacitor, V , and current in the inductor,I, as independent state variables, the dynamical equations of this second-order nonlinear oscillator can be written as 31 d(I) dt =V; (2.5) C dV dt =f(V ) V R I +I n (t): (2.6) We use quasi-harmonic approximations and averaging technique [36] to find the stochas- tic differential equations for steady-state amplitude and phase. The quasi-harmonic ap- proximations assume that steady-state solutions are V (t) =a(t)cos(! 0 t +(t)); (2.7) I(t) = a(t) L 0 ! 0 sin(! 0 t +(t)); (2.8) I(t)h(t) = a LP (t) L 0 ! 0 sin(! 0 t + LP (t)); (2.9) where the rates of changes ina(t) and(t) are much slower compared with the steady- state oscillation frequency,! s . In (2.7)-(2.9),! 0 is the natural frequency of the nonlinear resonator with small drive,i.e.,! 0 = 1 L 0 C , and a LP (t) =h LP (t)a(t); (2.10) LP (t) =h LP (t)(t); (2.11) h LP (t) = ! s 2Q NL e !st 2Q NL u(t); (2.12) 32 where u(t) is the step function. In (2.10) and (2.11), a LP (t) and LP (t) are low-pass filtered versions ofa(t) and(t), respectively. Detailed derivation leading to these equa- tions is presented in Appendix A.2. By inserting the quasi-harmonic approximate solutions (2.7)-(2.9) in the dynamical system (2.5)-(2.6) and applying averaging, the amplitude and phase stochastic differen- tial equations can be derived as _ a(t) = a(t) 2 ( 1 1=R C 3 3 4 a(t) 2 ) + I n (t) C cos(! 0 t +(t)); (2.13) _ (t) = I n (t) a(t)C sin(! 0 t +(t)) | {z } standard diffusion process 3 8 L 1 L 2 0 ! 0 a(t) 2 3 8 L 2 L 2 0 ! 0 a LP (t) 2 | {z } AM-FM conversion : (2.14) The second and third terms in the phase stochastic differential equation (2.14) are due to resonator nonlinearity and result in the conversion of amplitude noise to frequency noise. It can be shown that when 1 > 1=R the amplitude differential equation (2.13) has a stable fixed point at a =a s = 2 s 1 1=R 3 3 : (2.15) 33 Therefore, 1 , commonly known as the small-signal transconductance of the active core, can be written as 1 = (1 +K)=R; (2.16) whereK > 0 and has a typical range of 1-3 for reliable start up under modeling uncer- tainties and variations in process, temperature, and supply voltage. The amplitude differential equation can be linearized around this stable fixed point, resulting in a linear stochastic differential equation expressed in the standard Ito form [38] as a(t)=a s +a n (t); (2.17) da n (t)= K! 0 Q a n (t)dt + p D C cos(! 0 t +(t))dB t ; (2.18) where Q = R p C=L 0 is the quality factor of the resonator with small drive, a n (t) denotes the time domain representation of the amplitude noise, anddB t denotes the time increment of a standard Wiener process. For simplicity, circuit noise,I n (t), is assumed to be Gaussian and White with a Power Spectral Density (PSD) given by S In =D; (2.19) 34 where D is the diffusion constant. The stochastic differential equation (2.18) can be solved using standard Ito integral properties (Appendix A). The PSD of amplitude noise, a n (t), as a function of frequency will then be S an ( ) = D 2C 2 1 2 + ( K! 0 Q ) 2 ; (2.20) which is a Lorentzian. Now, let us consider the phase differential equation (2.14). By finding the fixed point of the phase differential equation, the stable steady-state solution for the oscillation frequency can be derived as ! s ,! 0 + _ j steady-state =! 0 (1 K(L 1 + L 2 ) 2 3 R(L 0 ! 0 ) 2 ): (2.21) It can be seen that the steady state oscillation frequency,! s , is shifted from the natural frequency of the resonator,! 0 , due to resonator nonlinearity and amplitude to frequency conversion. This shift in frequency has been shown before [32]. Assuming small am- plitude noise, a n (t), the linearized version of the phase stochastic differential equation (2.14) is simplified to n (t) , (! 0 ! s )t +(t) (2.22) _ n (t) = I n (t) a s C sin(! s t + n (t)) 3 4L 2 0 ! 0 a s (L 1 a n (t) + L 2 a nLP (t)); (2.23) 35 Figure 2.10: Graphical representation of phase noise generation in an oscillator with nonlinear resonator with memory effect Ω Q 0 ω NL s Q ω 1 δ 2 δ ) ( S φ Ω • 1 to due FM - AM ΔL 2 to due FM - AM ΔL noise Basic Ω ) ( S Ω n a 2 0 2 ) ( 2 ω CK DQ Ω Q 0 ω NL s Q ω ) ( S φ Ω -20 dB/dec -40 dB/dec Lorentzian Linear resonator Nonlinear resonator Q 0 ω Figure 2.11: Contribution of different noise generation mechanisms in the amplitude, frequency and phase noise power spectral densities wherea nLP (t) is the low-pass filtered version ofa n (t) similar to (2.20) with a PSD given by S a nLP ( ) = D 2C 2 ( !s 2Q NL ) 2 ( 2 + ( K! 0 Q ) 2 )( 2 + ( !s 2Q NL ) 2 ) : (2.24) In (2.23), the first term corresponds to the standard diffusion process in nonlinear os- cillators with linear resonators. The other terms in (2.23) are due to the resonator nonlin- earity and memory effect and show amplitude to frequency noise conversion. Equation 36 (2.23) can be intuitively understood by the graphical representation of Fig. 2.10. The noise contributions from the two branches to phase noise are independent as the noise in the top branch depends on the instantaneous value of the White noise, while the other de- pends on its history (due to the low-pass function). Figure 2.11 shows the contributions of the different noise generation mechanisms on the frequency noise, i.e., derivative of phase noise together with the PSD of amplitude and phase noise based on the derivations in Appendix A and (2.22)-(2.24). Notice that the phase noise will have a -40 dB/dec slope when the dominant frequency noise component has -20 dB/dec slope. Based on the methodology presented in Appendix A, the PSD of phase noise can be expressed as S ( ) =S 0 (1 + 2 : 1 + ( z ) 2 (1 + ( Q K! 0 ) 2 )(1 + ( p ) 2 ) ); (2.25) where S 0 = D 2a 2 s C 2 : 2 ; (2.26) = 3Q 3 (L 1 + L 2 )P res KR ; (2.27) P res = a 2 s 2R ; (2.28) p = ! s Q NL ; (2.29) z = (1 + L 2 L 1 )p; (2.30) 37 and S 0 is the PSD of phase noise of the oscillator with a linear resonator. The sin- gle sideband phase noise of the oscillator in dBc/Hz can now be written as L( ) = 10log( 1 2 S ( )). To find the ultimate phase noise achievable using a nonlinear resonator, we consider the noise to be only due to the resonator loss,i.e., D = 4K B T R ; (2.31) whereK B is the Boltzmann constant andT is the absolute temperature. Equation (2.26) can then be written as S 0 = K B T P res Q 2 ( ! 0 ) 2 : (2.32) Equation (2.26) shows that by increasing the power incident on the resonator,P res , the phase noise (and consequently frequency noise) reduces. However, increasing the res- onator power leads to an increase in the phase noise due to amplitude to frequency noise conversion as observable in (2.23) and (2.25). The smallest close-in phase noise is there- fore achieved when d _ (0) dP res = 0; (2.33) 38 where _ (0) is the frequency noise at zero offset frequency ( = 0). The optimum incident power on the nonlinear resonator to achieve the lowest phase noise is then P resopt = KR 3Q 3 (L 1 + L 2 ) : (2.34) At this power level, the phase noise of the oscillator at low offset frequencies, i.e., << ! 0 =Q and << ! s =Q NL , is twice the phase noise achieved if the resonator was linear (long term stability). It is worthwhile that the oscillator phase noise at high offset frequencies (short term stability) remains intact whether a linear or a nonlinear resonator is used (Fig. 2.11). 2.1.2.3 Simulations To verify the analysis, the model shown in Fig. 2.9 was simulated using the time-domain stochastic simulation tool in Cadence Spectre-RF [39]. The simulation parameters are set to Q = 100, Q NL = 2500, R = 1 k , C =10 pF, L 0 =1 nH, L 1 = 0:1, and L 2 = 0:3. Figure 2.12 shows the steady-state oscillation frequency as a function of power incident on the resonator. Figure 2.13 shows the analysis and simulation of the single sideband phase noise as a function of offset frequency for linear and nonlinear resonator when 1 =2mA=V and 3 =1.3mA=V 3 (corresponding toP res =500W from (2.15) and (2.28)). Figure 2.14 shows the phase noise of the oscillator at 1 kHz offset as a function of the power loss in the resonator. From (2.38), the optimum power 39 Figure 2.12: Steady-state oscillation frequency change as a function of power incident on the resonator 10 4 10 6 10 8 10 3 10 5 10 7 10 7 -180 -160 -140 -120 -100 -80 Offset frequency (Hz) Phase noise (dBc/Hz) Nonlinear resonator (Theory) Linear resonator (Theory) Linear resonator (Simulation) Nonlinear resonator (Simulation) Figure 2.13: Analysis and simulation of phase noise in the self-sustained oscillator shown in Fig. 2.9 loss in the resonator for optimum phase noise isP resopt =830W which is in agreement with simulations. 2.1.3 An FBAR Colpitts oscillator 2.1.3.1 Basics The methodology outlined in Section 2.1.2 can be applied to analyze and design oscilla- tors with nonlinear resonators. As an example, let us consider the well known Colpitts oscillator [40] with a nonlinear FBAR resonator (Fig. 2.15.a). A Bipolar Junction Tran- sistor (BJT), with exponential collector current to base-emitter voltage characteristic is chosen to allow derivation of closed-form solutions for amplitude and phase noise. The 40 10 -1 10 0 10 1 -105 -100 -95 -90 -85 -80 -75 Power incident on the resonator (mW) Phase noise at 1kHz offset (dBc/Hz) Linear resonator (Theory) Nonlinear resonator (Theory) Nonlinear resonator (Simulation) opt res P − Figure 2.14: Analysis and simulation of phase noise as a function of power incident on the resonator nonlinear resonator model discussed in Section 2.1.1 can be simplified down to a loss el- ement (R e ), a nonlinear magnetic energy storage element ( e (I)) and a linear capacitive energy storage element (C e ) around the oscillation frequency. The simplified schematic of the oscillator is shown in Fig. 2.15.b where I C =f(V 1 ) =I BIAS (e ( V 1 V T 1); (2.35) I n (t) = q 2qI BIAS e V 1 V T :W (t); (2.36) andI BIAS is the bias current of the transistor,V T is equal to K B T q ,I n (t) is the collector shot noise,q is the charge of electron, andW (t) is the standard White Gaussian process. As stated before, the active device noise, I n (t), is cyclostationary due to the periodic dependency ofV 1 with respect to time in steady-state. The oscillation frequency and the values for the resonator equivalent model can be written as ! 0 = 2f 0 = 2f r (1 + C m 2(C o +C T ) ); (2.37) 41 Figure 2.15: An FBAR oscillator (a) circuit schematic, (b) equivalent model. R e =R s +R m (1 + C o C T ) 2 R m (1 + C o C T ) 2 ; (2.38) L e =L m (1 + C o C T ) 2 ; (2.39) C e = ( 1 L e ! 2 0 1 C T ) 0:5 ; (2.40) wheref r is the series resonance frequency of the FBAR ,C T is the series combination ofC 1 andC 2 and! 0 is the oscillation frequency assuming the resonator is linear. The dynamical equations for this Colpitts oscillator are _ V 1 = I C ; (2.41) _ V 2 = f(V 1 ) +I +I n (t) C 2 ; (2.42) _ V 3 = I C e ; (2.43) _ e (I) =(R e I +V 1 +V 2 +V 3 ): (2.44) 42 We apply the following quasi-harmonic approximations for the state space variables V 1 (t) = a(t)cos(! 0 t +(t)) +b 1 (t); (2.45) V 2 (t) =a(t)cos(! 0 t +(t)) +b 2 (t); (2.46) V 3 (t) =a(t)cos(! 0 t +(t))b 1 (t)b 2 (t); (2.47) I(t) = (1 + +) L e ! 0 a(t)sin(! 0 t +(t)); (2.48) where = C 2 C 1 and = C 2 Ce . By substituting these approximations into the dynami- cal equations and applying the averaging technique, the amplitude and phase stochastic differential equations are derived as _ a(t) = R e a(t) 2L e + I BIAS C 2 (1 + +) I 1 ( a=V T ) I 0 ( a=V T ) + I n (t) C 2 (1 + +) cos(! 0 t +(t));(2.49) _ (t) = I n (t) C 2 a(t)(1 + +) sin(! 0 t +(t)) 3 8 L 1 L 2 m ! 0 a(t) 2 3 8 L 2 L 2 e ! 0 a LP (t) 2 : (2.50) where I 1 (:) and I 0 (:) are modified Bessel functions. Assuming a V T >> 1, the stable fixed point of the amplitude differential equation can be derived as a s 2L e I BIAS R e C 2 (1 + +) : (2.53) The oscillation steady-state amplitude increases with the DC bias current, I BIAS . It should be noted that the steady-state voltage swing will be bounded by the DC voltage 43 source,V CC . Using the properties of modified Bessel functions, the amplitude stochastic differential equation can be linearized around its stable fixed point as a(t)=a s +a n (t); (2.54) _ a n (t)= ! 0 Q res a n (t) + I n (t) C 2 (1 + +) cos(! 0 t +(t)); (2.55) where Q res = Le! 0 Re is the quality factor of the FBAR resonator at the oscillation fre- quency under small drive. This stochastic equation can be solved using the procedure explained in Section 2.1.2 and Appendix A. The PSD of the amplitude noise will be S an ( ) = 2K B TR e L e C 2 (1 + +) 1 2 + ( ! 0 Q ) 2 : (2.56) Likewise, the PSD of the phase noise with linear resonator can be written as S ( ) = 2K B TR e L e C 2 a 2 s (1 + +) 2 : (2.57) Substituting a s from (2.53), and keeping the equivalent capacitor C T constant, the op- timum phase noise under small drive level is achieved for = 1. The optimum value ofa s depends on the maximum possible voltage swing as limited by DC power supply and should remain the same asI BIAS is scaled. As seen in (2.53) and (2.57), increasing the capacitor valuesC 1 andC 2 while the amplitude of oscillation is kept unchanged will 44 result in improvement of phase noise (scaling). The amplitude of oscillation,a s , can be kept unchanged by scaling up the current according to C 1 =C 2 = 2C T ; (2.58) a s (C T +C 0 ) 2 = Q res 2! 0 I BIAS C m : (2.59) Under these conditions, the incident power on the resonator may be written as P res =a s I BIAS : (2.60) As seen in this equation, if the conditions of scaling are met, increasing the bias current will result in increasing the incident power on the resonator while oscillation amplitude is kept constant. Notice that the impedance of the resonator changes according to (2.38)- (2.40) as the oscillator is scaled. The overall oscillator phase noise with the nonlinear resonator can be written as S ( ) =S 0 (1 + 2 : 1 + ( z ) 2 (1 + ( Q ! 0 ) 2 )(1 + ( p ) 2 ) ); (2.61) 45 where S 0 = K B T 2P res Q 2 res ( ! s ) 2 ; (2.62) = 3Q(L 1 + L 2 )P res R m ; (2.63) p = ! s Q NL ; (2.64) z = (1 + L 2 L 1 )p: (2.65) Comparing (2.61) and (2.25), we see that the phase noise of this Colpitts nonlinear os- cillator is similar to that of the basic model of a nonlinear oscillator with the following modification S 0 = 3K B T 2P res Q 2 res ( ! s ) 2 : (2.66) As long as the conditions for optimal scaling (2.58)-(2.59) are met, increasing the power incident on the resonator will improve the phase noise until the amplitude to frequency noise conversion dominates. The optimal power level at which the lowest phase noise at low offset frequencies is achieved can be found to be P resopt = R m 3Q res (L 1 + L 2 ) : (2.67) Although the equations presented here are derived for a BJT with exponential I-V characteristic, the results are applicable to design CMOS Colpitts oscillators as well. This 46 is because BJT and CMOS Colpitts oscillators will have the same oscillation amplitude for the same passive components and bias current [50]. This is shown in simulations where the BJT is replaced with a square-law MOSFET that has the same small-signal transconductance as the BJT. From simulations, it is observed that the incident power on the resonator, for each current level (by following scaling equations (2.58) and (2.59)), is very close to the BJT counterpart. In Fig. 9, the simulation and analysis of phase noise at 1 kHz offset are plotted versus the power incident on the resonator for bipolar and MOS devices. At each power level, the transistor bias current and capacitors are scaled according to (2.59) to keepa s = 0:4V . The resonator parameters are the same as the model provided in Section 2.1.1. The excess noise factor of the NMOS ( ) is set to 1. As seen in Fig. 2.16, for both MOS and BJT oscillators, there exist an optimal power level beyond which increasing power results in worse phase noise. 2.1.4 Oscillator design and measurements In order to verify the theoretical findings and to achieve the lowest possible phase noise in a resonator-based oscillator, with a fixed topology and FBAR, two Colpitts oscillators that are properly scaled to provide different powers to the resonator were designed (Fig. 2.17). The active core consists of a PMOS Field Effect Transistor (FET)M 1 instead of an NMOS FET because of its lower flicker noise. Current sourceM 2 is biased using a current mirrorM 3 and an RC low-pass filter (R 3 ;R 4 ;C 3 ;C 4 ) is used to reduce the effect of bias noise on the oscillator performance. As discussed in previous section, while 47 drain current,I, to Gate-Source voltage,V GS , of a MOSFET is not exponential as in the BJT , which makes the derivations of closed-form solutions tedious and uninsightful, the results of the previous section are still applicable in the CMOS Colpitts oscillator as the steady-state current/voltage waveforms remain very similar [50]. By concurrent scaling of capacitorsC 1 andC 2 , the active core, and the current source, the power incident on the FBAR is scaled in the scaled oscillator. The size of main device M 1 is chosen to satisfy the start up condition and provide the optimum swing across the resonator based on the methodology explained in Section 2.1.3. The channel lengths of M 1 and M 3 are increased to reduce the flicker noise and decrease their output impedance. An on- chip supply regulator minimizes the effect of supply noise on the oscillator performance, and is used under nominal bias conditions where the lowest phase noise is expected. Moreover, the bias voltage of the reference current sourceM 3 can be adjusted off-chip to vary the current of the FBAR oscillator, and hence, the power incident on the FBAR. This is used in measurements to collect more experimental data points for theory verification. Both oscillators were fabricated in a 130 nm CMOS technology, and are followed with on-chip buffers to facilitate measurement in a 50 environment. The power consumption 48 10 -1 10 0 10 1 -130 -125 -120 -115 -110 -105 Power incident on the resonator (mW) Phase noise at 1kHz (dBc/Hz) Nonlinear resonator (simulation-BJT) Nonlinear resonator (theory-BJT) Linear resonator (theory-BJT) Nonlinear resonator (simulation-MOS) Figure 2.16: Phase noise at 1kHz offset as a function of power incident on the resonator in the Colpitts oscillator 6/0.6 100pF 100pF 125/0.6 2.5MΩ 2.5MΩ I BIAS C 2=1.7pF C 1=1.1pF 480/0.2 10.5kΩ 21kΩ Biasing To Off-chip FBAR To Buffer M 1 M 2 V DD 6/0.6 100pF 100pF 2.5MΩ 2.5MΩ K.I BIAS K 1.C2 K 1 .C 1 10.5kΩ 21kΩ Biasing To Off-chip FBAR To Buffer K.M 1 K.M 2 V DD Main Oscillator Scaled Oscillator K=4 K 1 =3.5 R 3 R 4 C 4 C 3 M 3 Figure 2.17: Schematic of the designed CMOS Colpitts oscillators 49 10 2 10 3 10 4 10 5 10 6 10 7 -160 -140 -120 -100 -80 -60 -40 Offset frequency(Hz) Phase noise (dBc/Hz) IBIAS=3mA, Pout=-7dBm Icore=2mA, Pout=-8.5dBm Icore=1m, Pout=-11dBm Simulation, Pout=-7dBm I BIAS =3 mA, P out =-7 dBm I BIAS=2 mA, P out=-8.5 dBm I BIAS=1 mA, P out=-11 dBm Simulation, P out=-7dBm Figure 2.19: Measurement and simulation of phase noise in the main oscillator 10 2 10 3 10 4 10 5 10 6 10 7 -160 -140 -120 -100 -80 -60 -40 Offset frequency (Hz) Phase noise (dBc/Hz) Measurement Simulation (Nonlinear resonator) Simulation (Linear resonator) Figure 2.20: simulated and measured phase noise of the scaled osillator when the the power consumption in the core is 15mW of the buffer is 20 mW to facilitate measuring a low phase-noise floor. The diced chip is mounted on a standard FR4 Printed Circuit Board (PCB) adjacent to the FBAR (Fig. ??). The chip to FBAR connection is through wire-bonds. All reported measurements are performed using RF probes. Phase noise measurements are done using an Agilent E5052B signal source analyzer. Figure 2.19 shows the measured phase noise of the main oscillator versus offset fre- quency at different power levels together with the simulation result at highest power level. Figure 2.20 shows the simulated and measured phase noise of the scaled osillator when the output power is -7 dBm and the power consumption in the core is 15 mW. Com- parison with simulation with linear and nonlinear resonator model shows the validity of 50 10 3 10 4 10 5 10 6 10 7 10 8 -180 -160 -140 -120 -100 -80 -60 Offset frequency (Hz) Phase noise (dBc/Hz) Measurement Simulation with NL model Theory: Ultimate phase noise Figure 2.21: simulated and measured phase noise of the scaled osillator when the power consumption in the core is 20mW together with the theoretical ultimate phase noise of the resonator the proposed FBAR model in predicting the phase noise of the oscillator. Figure 2.21 shows the simulated and measured phase noise of the scaled osillator when the output power is -6 dBm and the power consumption in the core is 20 mW. The theoretical ulti- mate phase noise achievable using the FBAR resonator from (2.61)-(2.67) is also shown. As can be seen in this figure, the measured phase noise is getting close to this ultimate limit in the middle offset frequencies. The divergence at lower offsets is likely due to the active core flicker noise and at higher offsets due to the output buffer phase noise floor. This plot corresponds to the lowest measured phase noise. The absolute phase jit- ter of this oscillator (integrated from 12 kHz to 20 MHz offset frequency) is 9.8 fs. Most electrical oscillators with linear resonators show a phase-noise versus frequency offset slope of -30 dBc/Hz and -20 dBc/Hz at low and high offset frequencies, corresponding to 1/f flicker noise and white thermal noise contributions to the phase-noise, respectively, before reaching a constant floor (limited by the output power) [17]. Nonlinearity in the resonator changes this typical behavior as seen in the measured graphs at higher power levels. An increase in the slope of phase-noise versus offset at mid offset frequencies is 51 Table 2.1: Comparison with FBAR and other low phase noise oscillators clearly visible. At low offset frequencies, the phase-noise slope is -40 dBc/Hz in both oscillators. The measured performance summary compared with state of the art FBAR oscillators as well as other types of low phase noise oscillators is included in Table 2.1. 2.2 Phase noise reduction techniques In the previous Section, limits of phase noise in a resonator-based oscillator was linked to the nonlinearity of the resonator. Phase noise of a practical oscillator deviates from the ultimate phase noise limit set by the resonator, and is often a strong function of os- cillator topology and other components of the oscillator. Therefore, natural questions to ask are: given a set of active devices (e.g., transistors, active optical media, etc.) and passive devices (e.g., delay-lines, resonators, inductors, etc.) (1) what are the different schemes that can be used to generate stable frequencies and (2) what are the fundamental limitations of these schemes. Over the years, motivated by the limitations of the avail- able components, multiple frequency generation and stabilization schemes have been 52 developed, each providing their own fundamental limitations, practical issues, and ad- vantages. ”Phase noise reduction schemes” are an important class of stable frequency generation. The general idea in these schemes is to measure the frequency/phase fluctua- tions of an oscillator and use the measurement to correct for those fluctuations. Examples of such schemes are Pound [63] and Pound-Drever-Hall [64] microwave and laser stabi- lization, microwave frequency stabilization using interferometric signal processing [65], and feedforward laser phase noise reduction [66][74][75]. This Section focuses on de- sign and implementation of an integrated feedback/feedforward phase noise reduction scheme using an FBAR resonator as the main frequency determining element. 2.2.1 Phase noise reduction basics and definitions Basic representation of a feedback phase noise reduction scheme is shown in Fig. 2.22. The phase noise information of a controlled oscillator is measured by a phase discrimi- nator, and is fed back to the oscillator control node to suppress the phase noise. The main block in this feedback phase noise reduction systems is the phase discrim- inator. More generally, a phase-frequency discriminator may be used in a phase noise reduction scheme. The input of a phase-frequency discriminator is an amplitude and 53 phase modulated sinusoidal waveform and the output is only a linear function of the phase information (Fig. 2.23) as given by v in (t) = (a 0 +a(t))cos(! 0 t +(t)); (2.68) v out (t) =g(t)(t) +v n;out (t); (2.69) where! 0 is the input center frequency,a(t) and(t) represent the amplitude and phase perturbations of the input signal, g(t) is the phase-to-voltage impulse response, and v n;out (t) represents the output-referred noise caused by the phase-frequency discrimi- nator. The phase-frequency discriminator is a Linear Time Invariant (LTI) system from the perspective of input phase to output voltage, and its output is not a function of input amplitude perturbations. The phase-frequency discriminator phase-to-voltage transfer function, when output-referred noise is zero, is defined as G( ) =F(g(t)) = V out ( ) ( ) ; (2.70) where represents the Fourier frequency typically referred to as offset frequency from the oscillation or center frequency! 0 ,V out ( ) and ( ) represent the Fourier transforms of the discriminator output and input phase, respectively. As shown in Fig. 2.23, depend- ing on the transfer function, the discriminator may be a phase discriminator, a frequency 54 Figure 2.22: Block diagram of a feedback phase noise reduction scheme discriminator or a combination of the two, phase-frequency discriminator. The sensitiv- ity or minimum detectable input phase information depends on the output-referred noise v n;out and the discriminator transfer function. We define the phase noise floor process of the frequency discriminator as S ;floor ( ) = S vn;out ( ) jG( )j 2 ; (2.71) whereS vn;out ( ) is the Power Spectral Density (PSD) of the output noise units ofV 2 =Hz. The Single-Side-Band (SSB) phase noise floor with units of dBc/Hz will then be PN floor = 10log( 1 2 S ;floor ( )); (2.72) 55 Figure 2.23: Transfer function of a phase discriminator, frequency discriminator, and phase-frequency discriminator versus offset frequency ( ) from the input frequency. Figure 2.24.a shows the schematic of an example resonator-based phase-frequency dis- criminator. The basic operation of this block is similar to that of the delay line discrimi- nator [68] with the group delay of the resonator replacing the true-time delay. Using the results of Appendix A.2, the phase-to-voltage transfer function can be derived as G( ) = V out ( ) ( ) =K j j + 1 ; (2.73) where is the group delay of the loaded resonator at! 0 , andK is the combined conver- sion gain of the amplifier and mixer with the resonator loss. At low offset frequencies ( << 1=), this discriminator acts as a frequency discriminator and at higher offsets ( >> 1=), it acts as a phase discriminator. Applying the averaging technique, the phase noise floor of this discriminator can be derived as shown in Fig. 2.24.c. In Fig. 2.24.c, F is the noise factor of the active circuitry,Q U is the unloaded quality factor of the resonator, andP res is the power incident on the resonator. The resonator-based phase- frequency discriminator of Fig. 2.24.a may be used in a phase noise reduction scheme 56 (such as Fig. 2.22). The ultimate achievable phase noise is naturally limited by the phase noise floor of the phase-frequency discriminator. Alternatively, the resonator and active device (amplifier) may be used to create a self-sustained oscillator (Fig. 2.24.b). It can be shown that the phase noise floor of this discriminator and the optimum phase noise of the self-sustained oscillator using the same resonator (Fig. 2.24.b), are equal for same amount of active devices noise (flicker noise is ignored). In particular, assuming noise- less actives (F = 1), the phase noise limit due to the resonator is exactly the same for the two schemes. There are, however, practical and secondary considerations that may favor one scheme versus another for a given application. For instance, the large signal swing across the nonlinear active device in a self-sustained oscillator results in the unwanted frequency translation of flicker noise, as well as noise around the oscillator harmonics, to around the main oscillation frequency [5][41]. Phase noise reduction schemes can be specifically designed to limit the signal swing across the active devices, and hence, elim- inate the unwanted flicker noise up-conversion and other noise frequency translations [65]. This will be elaborated further as a design example in the next section. 2.2.2 Design and implementation of a resonator-based phase-frequency discriminator and phase noise reduction scheme Based on the general representation of low-phase noise frequency generation schemes, a feedback/feed-forward phase noise reduction scheme is proposed [69][70] that relies on 57 Figure 2.24: (a) Resonator-based phase discriminator (b) resonator based oscillator, (c) phase noise floor of the discriminator. a resonator-based phase-frequency discriminator. The design, simulations, and measure- ments are discussed in this section. 2.2.2.1 Resonator-based phase-frequency discriminator The proposed resonator-based phase-frequency discriminator consists of a notch filter, a Low Noise Amplifier (LNA), a mixer, and a phase shifter (Fig. 2.25.a). The frequency of the applied signal to the discriminator and the notch filter are assumed to be matched. The phase shifter ensures that the inputs to the mixer are in quadrature. Similar to the 58 resonator-based bandpass discriminator, the phase-frequency transfer function of this notch-based discriminator may be derived as (Appendix A.2) G( ) = V out ( ) ( ) =a o A LNA A Mixer j j + 1 ; (2.74) where! 0 is the frequency of the notch filter and the input,A LNA is the LNA gain, and A Mixer is the mixer conversion gain, and = 2Q L ! 0 is the maximum group delay of the notch filter. It is apparent that higher quality factor leads to higher transfer gain and sensitivity. Figure 2.25.b shows the schematic of the notch filter. The resonator used in implementing the notch filter is an AlN FBAR, and has a series resonance frequency of 1.488 GHz with a corresponding quality factor of 1500. Signals located at the FBAR resonance frequency appear in both output terminals of the notch filter, and get rejected in a subsequent dif- ferential LNA. A voltage-controlled resistor is placed in the bottom branch of the notch filter, so that the signal attenuations in both paths can be perfectly matched. The dc volt- age applied to the voltage controlled resistor balances the loss between the two branches of the notch, thereby controlling the depth of the notch. Some of the voltage swing at the source ofM s , is coupled to its gate through the capacitive divider formed byC c , to improve linearity of the voltage controlled resistor (passive bootstrapping). Capacitor C s shifts the resonance frequency of the top branch and increases its resistance at reso- nance. This is necessary because at the FBAR series resonance, the resistive value of the 59 resonator is really low and very sensitive to parasitics. InductorL s ensures that the max- imum group delay is achieved at the notch frequency. The reason for using a notch filter is to suppress the large signal carrier at the input of the LNA to prevent the up-conversion of the flicker noise in the LNA and proceeding blocks. As such, a common-mode trap, comprising ofC R andL R , is used to suppress the common-mode input swing at the LNA input by creating a short at common mode, without affecting the differential mode op- eration. The LNA is an inductively degenerated cascode amplifier with tuned load (Fig 2.25.c). Passive mixer is used for superior flicker noise performance (Fig 2.25.d). The phase shifter is a simple RC filter. The phase noise floor of the resonator-based discrim- inator and the phase noise of a self-sustained oscillator using the same resonator follow the same equations. However, as opposed to the amplifier used in the self-sustained os- cillator, the signal input to the amplifier in the proposed scheme is small-signal and the effective noise factor is lower at low offsets compared with the amplifier used in the self-sustained oscillator. Figure 2.26 shows the simulated phase noise floor of this dis- criminator compared with an optimally designed oscillator using the same technology. For the same incident power on the resonator, this scheme has lower phase noise floor at lower offsets when compared with the self-sustained oscillator, due to elimination of flicker noise up-conversion. Figure 2.27 shows the photograph of the phase-frequency discriminator chip wirebonded to the FBAR. The chip has an area of 1.8 mm1.2 mm, is fabricated in an IBM 0.13 m RF CMOS technology, and consumes 26 mW. Figure 2.28 shows the simulated and 60 L=435 pH C R C R =12.8 pF L S=320 pH C C =1.7 pF R P =35 Ω C C R B=10 kΩ M S 280/0.4 Input R s = 7Ω VDD FBAR Linearized Voltage Controlled Resistor Common-Mode Trap + Output (To LNA) - L G=2.3nH L S =1.2nH L G C L =1.3pF C L M 3 M 4 I=9mA IN+ IN- 200/0.3 NF=30,M=2 48/0.12 NF=30, M=2 1000/0.5 NF=40 300/0.5 NF=30 L L =9.5nH LNA_I 48/0.12 NF=30 160/0.3 NF=20 VDD VDD 4.3k 12k G M Cell Notch Filter FBAR LNA Phase Shifter Mixer Input Output Cs=1 pF R s= 600 Ω Depth Control )) ( cos( ) ( 0 t t a t V o in φ ω + = 0 ω VDD (a) (b) (c) Output + + - - R F =1.5kΩ R F LO+ LO- LO+ LO- Cs=10pF Cs 80/0.12 NF=20 VDD Output Input (from LNA) (d) Figure 2.25: (a) Block diagram of the implemented phase-frequency discriminator, (b) Schematic of the notch filter, (c) Schematic of the LNA, (d) Schematic of the mixer. Figure 2.26: Comparison of the phase noise floor of the discriminator and an optimally designed self-sustained oscillator with the same resonator and power. 61 Figure 2.27: Photograph of the resonator-based phase-frequency discriminator CMOS chip wirebonded to the FBAR. Figure 2.28: Notch-filter and LNA combined S-parameters. 62 measured S-parameters of the notch filter and LNA when the outputs of the LNA are combined using a 50 off-chip hybrid. Maximum measured group delay of 130 ns, corresponding toQ L = 610, enables sensitive discrimination of phase noise. Figure 2.29 shows the measured and simulated phase to voltage transfer function of the discrimina- tor under the quadrature condition when the input frequency is matched with the notch filter frequency (while the quadrature point is ensured by manually adjusting the phase shift) and also when the frequency of the input signal and the notch filter are off by 1 MHz. For the measurements, an E8257C Agilent signal generator with 8 dBm of power is FM modulated and used as an input and the discriminated tone is measured at the out- put of the discriminator. Notice that, as expected from (2.74), the phase discriminator is acting as a frequency discriminator at frequencies below 1= = 1:2 MHz and a phase discriminator above that frequency. Output noise of the phase-frequency discriminator is measured using the technique shown in Fig. 2.30. The measured output of each path consists of the discriminated phase noise of the input signal generator, C n (t), added to the inherent noise of the discriminator and following components. Given independent paths, the latter noise contributions,a n (t) andb n (t), are uncorrelated; but, have the same PSD. The PSD of the difference of the two outputs will be twice the PSD of each discrim- inator noise, and the signal generator discriminated phase-noise will be canceled. In Fig. 2.30, S XY (f) represents the PSD of the difference signalx(t)y(t). In presence of mismatch between the two arms, the phase noise of the signal generator will contribute 63 Figure 2.29: Phase to voltage transfer function of the phase-frequency discriminator. toS XY (f). This effect is minimized by calibrating the transfer gain of the two discrimi- nators in the digital domain. Also, the cross-spectrum technique [72] is applied to reduce the noise of the discriminators to find the correlated noise. Figure 2.31 shows the mea- sured output noise PSD of the two discriminators, the normalized PSD of the subtracted outputs, and the cross-correlated PSD of the output noise of the two discriminators with 1000 times averaging. At low offset frequencies, the PSD of the subtracted outputs is lower than the PSD of each output, indicating the dominance of correlated noise at these frequencies. The phase noise floor of this discriminator can be derived from the output noise and transfer gain measurements as discussed next. 2.2.2.2 Phase noise reduction scheme The aforementioned low-noise phase-frequency discriminator can be used to reduce the phase noise of an oscillator in feedback and/or feed-forward configurations. It has been shown that the lowest achievable phase noise in an oscillator is determined by the phase 64 Figure 2.30: Discriminator output noise measurement setup. 65 Figure 2.31: PSD of the Phase-frequency discriminator output noise. Figure 2.32: Phase noise reduction scheme. * The portion shown in the dashed box was implemented in the chip but did not work because of a schematic error, and its detail design will not be discussed here. 66 noise floor of its discriminating component which is typically a high-Q resonator. How- ever, given the large signal operation of the oscillator, low-frequency noise is often up- converted to around the oscillation frequency, prohibiting reaching the resonator-limited phase noise floor. The proposed discriminator is specifically designed to eliminate the noise frequency up-conversion and enable reaching close to the FBAR-limited phase noise floor. The schematic of the proposed feedback-feed-forward phase noise reduction scheme that utilizes the phase-frequency discriminator of Fig. 2.25.a is shown in Fig 2.32. The use of a notch based discriminator in a feedback phase loop is the same as the frequency stabilization technique described in [65]. In this scheme, the discriminator measures the phase noise of a VCO and feeds it back to its control voltage through a phase loop filter. This feedback loop serves two purposes. Firstly, the VCO frequency will be locked to the notch frequency set by the FBAR, and hence, the phase noise will be reduced inside the loop bandwidth down to the discriminator phase noise floor. The locking mechanism makes the oscillator long-term stability (including temperature sen- sitivity and drift) to follow that of the FBAR resonator. The locking mechanism of this type II loop (with two integrators as in type II PLL) can be explained using the large signal representation of this loop (Fig. 2.33). The use of double integration in the loop filter ensures that the two inputs to the mixer are in quadrature. This condition happens at three frequencies as shown in the notch phase response. The only stable quadrature point is at the notch frequency. Therefore, if the initial frequency of the VCO is within the two unstable quadrature frequencies, the loop will ensure that the VCO frequency is 67 locked at the notch filter center frequency. Another loop consisting of mixer (I), phase shifter (I), and an amplitude loop filter is used to ensure balanced operation of notch filter of Fig. 2.25.b. Under locked condition, the two inputs to mixer (I) are in phase. The mixer (I) output signal is proportional to LNA output swing and is fed-back to the voltage-controlled resistor in the notch filter to control the depth of the notch. The op- eration of this loop is essential to the performance of the discriminator, since the depth of the notch indicates the swing at the LNA input. One challenge in the design of this system is the simultaneous operation of the two loops. During the frequency locking transient, the two loops interact. To ensure stability and locking in the desired mode, the phase loop is designed to be faster than the amplitude loop. Figure 2.34 shows the transient signals involved in the two loops before locking. Initially, the two arms of the notch filter are mismatched causing an imperfect notch response and the VCO frequency is away from the notch filter center frequency, and hence a large swing at the LNA output is observed. The faster phase loop changes the frequency of the VCO to move towards the center frequency of the notch filter and the amplitude loop aligns the loss in the two arms of the notch filter, hence enhances the notch filter response. These two effects re- sult in reducing the voltage swing at the LNA output. Under locked condition, the LNA output voltage swing is minimized and primarily includes the phase noise information (carrier is suppressed). The phase noise reduction due to the operation of the phase feedback is limited to the bandwidth of the loop posed by stability constraints set by the parasitic poles in the loop, 68 Figure 2.33: Block diagram describing the locking behavior of the feedback phase noise reduction. including the tuned LNA, the notch filter, and the loop filter. A feed-forward path may be added to extend the range of phase noise reduction beyond the feedback loop bandwidth. The entire system, including the VCO, is implemented in a 2 mm3 mm CMOS chip and consumes 350 mW (Fig. 2.35). 200 mW of the power is used in the buffers to ensure that the phase noise floor caused by buffers do not hinder the phase noise floor of the discriminator. The VCO consumes 10 mW and the rest of the power is used in the active RC filter in the feedback path. The PVT variations will affect the gain and transfer function of different blocks which changes the loop dynamics, locking range, and consequently the phase noise. Enough controllability is set in amplitude and phase filters to accommodate for these variations. Figure 2.36 shows the chip output spectrum before and after locking. The chip shows a 12 MHz locking range and 25 MHz tracking range. Figure 2.37 shows the simulated and measured phase noise of the stand-alone VCO and the feedback reduction with feed-forward simulations. Phase noise measurements are 69 Figure 2.34: (a) Output of the amplitude loop filter (notch depth control), (b) Output of the quadrature mixer (VCO frequency control), (c) LNA output voltage. 70 Figure 2.35: Photograph of the phase noise reduction CMOS chip wirebonded to the FBAR done using an Agilent E5052B signal source analyzer. The phase noise floor of the phase-frequency discriminator is derived based on (2.71) and (2.72) and the output noise and transfer gain measurements of the discriminator shown in Fig. 2.29 and Fig. 2.31, respectively. 2.2.2.3 Limitations of feedback scheme and proposed solution As shown in Fig. 2.37, the output phase noise of the system reaches the phase noise floor of the frequency/phase discriminator in a limited bandwidth. This limited phase noise reduction bandwidth is posed by the stability requirements of the phase feedback loop. To reduce the phase noise down to the phase noise floor over a wider range of frequency, we propose the use of feedforward phase noise reduction [66][73], as shown in Fig. 2.38. The reconstruction needs to be done beyond the frequency where the feed- back loop reduces the phase noise down to the discriminator phase noise floor. Ideally, 71 Figure 2.36: Output spectrum of the phase noise reduction scheme (a) before locking and (b) after locking. Figure 2.37: Phase noise floor of the phase-frequency discriminator and the output of the phase noise reduction scheme. 72 Figure 2.38: Proposed feedforward phase noise reduction to overcome feedback band- width limitation. the feedforward filter transfer function should be the inverse of the phase-frequency dis- criminator transfer function (eqn. 2.74), which is an integrator with a zero located at 1=. Aside from the difficulties in implementing an ideal integrator, the use of an ideal integrator would cause in unbounded output due to the brownian motion nature of phase noise. However, the reconstruction filter only needs to reconstruct phase noise beyond the offset frequency where the feedback loop reduces phase noise down to the discriminator floor. Therefore, a lossy integrator with a pole at 50 kHz and a zero at 1= = 2MHz is implemented. The output of this filter will then modulate the phase of the output through the phase modulator to reduce phase noise over an extended offset frequency range. Fig- ure 2.39 shows the Cadence simulation of the phase noise with the feedforward scheme. The feedforward filter is designed as an active-RC filter. Due to a mistake in the biasing connections to the feedforward filter, it failed to operate in the implemented chip. 73 Figure 2.39: Phase noise simulation of the feedback and feedback/feedforward schemes. 74 Chapter 3 Distributed injection locked frequency dividers 3.1 Introduction In Chapter 1, the motivation behind a mm-wave software defined radio was discussed and a two-stage PLL architecture was proposed to reach 100 Gbps throughput (Fig. 1.10). For wideband frequency synthesis, the first frequency divider following the wideband VCO in the mm-wave PLL (stage-2 in the two-stage PLL architecture shown in Fig. 1.10) must also be wideband and operate at mm-wave frequencies. As non-autonomous nonlinear dynamical systems, frequency dividers operate over a finite frequency range commonly referred to as locking range. Among different topologies, injection locked frequency dividers are capable of operating at high frequencies; but, a conventional design will result in a limited frequency locking range. Different techniques have been explored to improve the locking range of the in- jection locked frequencys [77][79][80]. These techniques generally aim at improving the 75 injection efficiency over wider range of frequencies using passive structures. For exam- ple, a passiveLC circuit may be added between the injection device and the active core to track the impedance of the tank and improve the injection strength over a wider range of frequencies [77]. Here, we propose a very effective method in achieving wideband injec- tion locked frequencys. In the proposed solution, named as distributed injection-locked frequency division, the injection device is broken down to several smaller devices. These multiple injection devices sit at different nodes of anLC-ladder network. As analytically and experimentally verified in this paper, this enables wideband frequency locking. If designed properly, the injection-locked frequency divider can operate over multiples of its first resonance frequency. Prior to this work, this property has not been shown in any other injection-locked frequency divider. Section 3.2 is dedicated to analysis, simulation, and comparison of conventional injection- locked frequency divider and distributed injection-locked frequency divider. Section 3.3 details the prototype implementation, measurements, and comparison to simulations and state-of the art. Section 3.4 concludes this Chapter. 3.2 Conventional injection-locked frequency divider In a conventional injection-locked frequency divider, as shown in Fig. 3.1.a, a signal is injected at a frequency close to twice the frequency of theLC resonant tank. Throughout the paper, Bipolar symbol is used for the core transistors, and FET symbol is used for the injection device. This ensures consistency with the experimental prototypes; however, 76 Figure 3.1: (a) Conventional injection locked frequency divider and (b) its first order model where the injection device is assumed to be always ON. the underlying analysis and results are independent of transistor types. A simplified model of the conventional injection locked frequency divider is shown in Fig. 3.1.b. The cross coupled pair is modeled as a current source with a 3 rd order polynomial dependency to the voltage across it where 1 > 0 and 3 > 0 are determined by the tail DC current and core devices. The injection device (FET) is modeled with an effective ON resistance, R on;eff , and a mixing injection current,I inj (t). This model is valid if the injection device is always ON during the operation of the injection-locked frequency divider. Differential equations for amplitude and phase of the output voltageV O (t) can be formed using the averaging technique, similar to the methodology described in Chapter 2 for oscillators, and assuming 77 8 > > > > > > > > > > > > > > > > < > > > > > > > > > > > > > > > > : V O (t) =V CC +a(t)cos(! 0 t +(t) | {z } o ); ! 0 = 1 p L P C P ; V inj (t) =V G +V inj cos(! inj t |{z} inj ); ! inj = 2! 0 + 2!; (3.1) and can be written as 8 > > > < > > > : da(t) dt = ( 1 1 Req 2C )a(t) 3 3 8C a(t) 3 +a(t) K 0 V inj 2 cos(2(t) 2!t); d(t) dt = K 0 V inj C sin(2(t) 2!t); (3.2) whereK 0 =frac n C ox 2W=L for a transistor operating in the square-law region. Un- der locked condition, the oscillation frequency will be equal to half the injection fre- quency (! inj =2 = ! 0 + !). Therefore,(t) = !t +, where is the phase differ- ence between input and locked output waveforms. Applying this condition to the phase differential equation results in ! = K 0 V inj C sin(2): (3.3) The locking range is given by ! < K 0 V inj C , and ==4 at the edges of locking range. This requirement is typically referred to as the “phase condition” and is analogous to the Adler expression for injection-locked oscillators [84]. According to this condition, 78 increasing the size of the injection device (K 0 ) and the amplitude of the injection signal (V inj ) should increase the locking range. Under the locked condition, the amplitude differential equation simplifies to da(t) dt = 1 2C 1 1 R eq + K 0 V inj 2 cos(2) a(t) 3 3 8C a(t) 3 : (3.4) For the amplitude differential equation to have a non-zero stable point, we need to have 1 1 Req + K 0 V inj 2 cos(2)> 0. Within the locking range,jj< 4 and 0<cos(2)< 1. If 1 1 Req is larger than zero, i.e., the frequency divider starts self-oscillations without injection, this condition is always satisfied and the locking range will be determined by the phase condition of (3.3). Without self-oscillation, if 1 1 Req + K 0 V inj 2 > 0, then the amplitude equation will have a non-zero stable point, and the locking range will be determined by 1 1 R eq +K 0 V inj cos(2) = 0; (3.5) where according to (3.3),cos(2) = q 1 ( C! K 0 V inj ) 2 . This condition is referred to as the “gain condition”. In conclusion, if the injection device is ON during the entire operation cycle, the fre- quency divider operates at two separate regimes: 79 1- If self-oscillation occurs, the locking range is determined by the phase condition given by Eqn. (3.3). In this regime, the frequency divider output will show frequency pulling behavior outside of the locking range. 2- If self-oscillation does not occur, enough injection strength can result in frequency division as predicted by the gain condition in Eqn. (3.5). In this regime, the frequency divider output will be zero outside the locking range. Figures 3.2.a and 3.2.b show the sensitivity curves obtained from simulation and analysis of the model shown in Fig. 3.1.b and the schematic shown in Fig. 3.1.a in these two regions. It is verified that based on this model, the injection locked frequency divider will only operate in these two regimes. If the injection device is not ON at all times, its current needs to be modified, and the injection-locked frequency divider can have other operation regimes. In general, the cur- rent of the MOS injection device shown in Fig. 3.1.b is a complicated nonlinear function of the injection signal and the core signal as the switch goes through different operat- ing regions (off, triode, saturation, velocity saturation, etc.). In this appendix, we will simplify this function to the point where it leads to accurate predictions of the injection- locked divider while the analysis remains simple enough to draw intuitive conclusions 80 Figure 3.2: Different regimes in conventional injection locked frequency divider (a) in- jection device always ON, self-oscillation occurs (I DC = 820A, V GATE = 1:7V , W=L = 6m=130nm,V CC = 1:1V ,R ON = 120 , 1 = 14:6mA=V , 3 = 1A=V 3 , K0 = 0:037A=v 2 )(b) injection device always ON, no self-oscillation (I DC = 410A, V GATE = 1:7V ,W=L = 6m=130nm,V CC = 1:1V ,R ON = 120 , 1 = 7:3mA=V , 3 = 0:5A=V 3 , K0 = 0:037A=v 2 ) (c) injection device biased at verge of being ON, self-oscillation happens (I DC = 300A, V GATE = 1:4V , W=L = 6m=130nm, V CC = 1:1V ,R ON = 1000 , 1 = 5:5mA=V ). 81 about the dynamics of the divider. Similar to (3.1), for the switch shown in Fig. 3.1.b, we define 8 > > > > > > > > < > > > > > > > > : V od0 =V G V CC V th0 ; inj =! inj t; o =! 0 t +(t); (3.6) whereV od0 is the switch DC overdrive voltage, and inj and o represent the time vary- ing phase arguments of the injection and output voltage waveforms. The injection device current corresponding to cut-off, triode, and moderate saturation is given by I SW = 8 > > > > > > > > < > > > > > > > > : 0; V inj cos inj +V o jcos o j +V od0 < 0 K 0 (V inj cos inj +V o jcos o j +V od0 )2V o cos o ; V inj cos inj V o jcos o j +V od0 > 0 K 0 (V inj cos inj +V o jcos o j +V od0 ) 2 sgn(cos o ); otherwise; (3.7) where sgn(.) is the sign function with value of +1(-1) when the argument is more (less) than zero. We have ignored velocity saturation. For the two cases of triode and moder- ate saturation, considering only the terms that have frequency components close to the resonator frequency (! o ), the injection device current may be simplified as I SW 2K 0 V inj V o cos inj cos o + 2K 0 V od0 V o cos o : (3.8) 82 Therefore, the injection device current throughout the entire cycle may be written as I SW = 8 > > > < > > > : 0; V inj cos inj +V o jcos o j +V od0 < 0; 2K 0 V inj V o cos inj cos o + 2K 0 V od0 V o cos o ; otherwise: (3.9) As an example, consider the scenario where the injection device is biased at the verge of being ON (V G V CC = V th ) anda(t) << V INJ . The injection device current can then be approximately written as I SW = 8 > > > < > > > : 0; cos inj < 0 2K 0 V inj V o cos inj cos o otherwise: = 2K 0 V inj V o cos inj cos o 1=2 +S 1=2 ( inj ) ; (3.10) whereS 1=2 (:) is a half-amplitude square-wave signal. The averaged differential equation for amplitude can now be formed as da(t) dt = 1 2C 1 1 R eq + K 0 V inj (2cos(2)) 4 a(t) 3 3 8C a(t) 3 : (3.11) In this case, the “gain condition” can be written as 1 1 R P + K 0 V inj (2cos(2)) 4 > 0. In this scenario, even if self-oscillations exist 1 1 R P > 0 and phase condition is satisfied, the divider can lose lock at the edges if gain condition is not satisfied. Figure 3.2.c shows the schematic and model simulations in this scenario. As predicted by (3.11), it 83 is observed that for increased injection strength, the gain condition becomes dominant and the frequency divider output dies down at the edges of the locking range instead of showing frequency pulling behavior. 3.3 Distributed injection-locked frequency divider The locking range of a conventional injection-locked frequency divider depends on the injection power (V inj ), size of the injection device (K 0 ), quality factor of the tank (R eq and C), and the active core ( 1 ). On one hand, larger injection device size and input power are desirable to increase the strength of the injected signal (enhanced phase con- dition). On the other hand, larger size of the injection device increases its conductance which can stop the output from oscillation (reduced gain condition). Larger injection device size also increases the parasitic capacitance at the tank nodes resulting in lower maximum frequency and/or higher power consumption (smaller inductor, higher power). Lower quality factor tank generally increases the locking range; but, necessitates in- creased power consumption to satisfy the gain condition. Figure 3.3 shows a schematic of the proposed distributed injection locked frequency di- vider. In this scheme, the injection device is broken down to multiple smaller injection devices. As it will be discussed in this section, this can yield significant increase in 84 Figure 3.3: Schematic of the proposed distributed injection locked frequency divider. the locking range. To start the analysis, consider the N-element and infinitely long LC- ladders shown in Fig. 3.4. Parallel capacitors represent parasitics of the distributed in- jection devices. The ladder exhibits several series and parallel mode resonances. Steady- state equations for the infinitely long ladder can be written as 8 > > > < > > > : I k+1 I k =C 1 j!V k ; V m =L 1 j! P m k=1 I k : (3.12) From these equations, the difference equation for ladder currents may be found as I k+1 I k = k X m=1 I m ; (3.13) where =L 1 C 1 ! 2 . The difference equation for inductor current may be written as 85 Figure 3.4: (a) N-elementLC-ladder , (b) one-sided infinitely longLC-ladder. I k (2)I k1 +I k2 = 0: (3.14) The poles of the one-sided z-transform of the difference equation are given by z 1 = 2 p 2 4 2 : (3.15) For small, the poles can be approximated asz 1 1 2 j p . Equation (3.16) can then be derived by taking the inverse z-transform and applying the boundary conditions, leading to 8 > > > < > > > : I n I 1 (1=2) n1 cos( p (n 1))I 1 cos( p (n 1)); V n jZ 0 I 1 sin( p n); (3.16) where = L 1 C 1 ! 2 andZ 0 = p L 1 =C 1 . The approximations hold as long asn << 1, which will prove to be valid for our region of interest as it will come clear shortly. 86 Figure 3.5: Equivalent circuit around the first parallel mode resonance. Looking now into the N-element array, the parallel mode resonances happen when the current out of the ladder is zero independent of the network that it gets connected to. At this mode, the first N-elements of the infinite network and the N-element network will be equivalent since the dynamical equations are the same and the current out of theN th node is 0. Therefore, the first parallel mode resonance frequency (! 1p ) of the N-element array can be found as cos( p N) = 0! p N ==2!! 1p = 2N p L 1 C 1 : (3.17) With the same token, all parallel modes are solutions of cos( p N) = 0. In the se- ries mode, the N th node voltage will be zero and based on (3.16), they happen when sin( p N) = 0. In summary, the parallel and series resonances of the N-element LC- ladder can be given by 8 > > > < > > > : ! ip = i 2N p L 1 C 1 ; ! is = i N p L 1 C 1 : (3.18) The N-element LC-ladder may be represented with an equivalent parallel (series) LC tank around its parallel (series) resonant frequencies[85]. To find the equivalent parallel tank of the network around its first parallel mode resonance (as shown in Fig. 3.5), the 87 maximum capacitive energy stored in the two networks for the same voltage swing at the output node are equated as 1=2C eq V 2 o = 1=2C 1 N X i=1 V 2 n 1=2C 1 V 2 o N X i=1 sin 2 ( 2N i))C eq =C 1 N X i=1 sin 2 ( 2N i); (3.19) where the voltages across C 1 capacitors were replaced according to (3.16). As an ex- ample, for a 10-stage LC-ladder network, the first parallel mode equivalent capacitance is C eq = 5:5C 1 . The equivalent inductance can readily be calculated from (3.17) and (3.18). In the distributed injection-locked frequency divider of Fig. 3.3, the loss is dom- inated by the ON resistance of the distributed injection devices, and may be represented with resistorsR 1 in parallel with capacitorsC 1 in the equivalent ladder networks of Fig. 3.4. An equivalent parallel resistanceR eq can be derived following a similar approach in derivingC eq (Fig. 3.5). It can be shown thatQ = R 1 C 1 ! 1p = R eq C eq ! 1p . Figure 3.6 shows the schematic simulations of a 10-element ladder and its equivalent RLC tank at the first parallel resonance mode. Now that we have found the open circuit impedance of the LC-ladder, we will proceed to the equivalent short circuit current (Norton equivalent) due to the distributed injection signals. Figure 3.7.a shows the N-element ladder. To analyze this circuit, consider the double-sided infinitely longLC-ladder shown in Fig. 3.7.b. The currents and voltages at node n of the infinite ladder due to the injection signalI inj;p can be calculated using the double-sided z-transform and may be written as 88 Figure 3.6: Simulated impedances of a 10-elementLC-ladder and its equivalentLC tank of Fig. 3.5 (L 1 = 1 nH,C 1 = 625 fF,R 1 = 18 ,C eq = 5:5C 1 ). 8 > > > < > > > : I n I inj;p 2 cos( p (np)); V n jZ 0 I inj;p 2 sin( p (np)): (3.20) To make the infinite-element ladder equivalent to the N-element ladder, we add two ad- ditional injection signalsI aux;1 andI aux;N as shown in Fig. 3.7, and use superposition to force nodes 1 and N in the infinitely long ladder to have zero voltages (virtual ground). Based on (3.20), the values of the additional signals need to be 8 > > > < > > > : I aux;1 =I inj;p sin( p (Np)) sin( p N) ; I aux;N =I inj;p sin( p p) sin( p N) : (3.21) Using superposition, the short circuit current due to the injection signal in the N-element LC-ladder can now be calculated as 89 Figure 3.7: (a) Short-circuit current from p-th injection in N-element LC-ladder, (b) Equivalent circuit based on double-sided1-elementLC-ladder. I SC;p = I inj;p 2 cos p (Np) + I inj;p 2 sin( p p)cos( p )cos( p N)sin p (Np) sin( p N) : (3.22) At first parallel mode resonance frequency, i.e., p N ==2, equation (3.22) simplifies to I SC;p j @! 1p =I inj;p sin( p p): (3.23) Going back to the injection-locked frequency divider schematics of Fig 3.1.a and Fig. 3.3, and according to the Appendix B, the injection current by each injection device is a mixing product of the injected signal and the voltage swing at injection node. Therefore, 90 since the voltages at nodes 1 to N scale assin( p n) (eqn. (3.16)), the injection signal at node p can be written as I inj;p =K dist V o V inj sin( p p): (3.24) Here,K dist is the mixing coefficient of the injection devices in the distributed injection- locked frequency divider. To have a fair comparison between the conventional injection- locked frequency divider of Fig. 3.1.a and the proposed distributed injection-locked frequency divider of Fig. 3.3, we make the following assumptions: (a) Both schemes have the same impedance at the first parallel resonance frequency. This ensures that with the same current consumption, the two schemes will have the same self- oscillation frequency and voltage swing. (b) The injection devices scale with the size of the capacitors at each node. This is partic- ularly true in mm-wave implementations where the parasitic capacitors of the injection devices are dominant and no explicit capacitors are used. From these assumptions, we note that the injection devices used in the distributed imple- mentation should be scaled according to (3.19). This means that K dist = K conv P N i=1 sin 2 ( 2N i) ; (3.25) whereK conv is the mixing coefficient of the injection device used in the corresponding conventional injection-locked frequency divider. 91 The total short-circuit injection current due to all N injection devices can be written as I SC;dist = N X p=1 I SC;p ; (3.26) that at! 1p , from (3.23) and (3.24), simplifies to I SC;dist j @! 1p = N X p=1 K dist V o V inj sin( p p) 2 =K conv V o V inj : (3.27) This is a very interesting result; it states that in the proposed distributed injection-locked frequency divider, when the injection frequency is exactly double the first parallel reso- nance mode of theLC-network, the overall injection current due to the scaled distributed injection devices will be equal to that of the single injection device in a conventional injection-locked frequency divider. However, unlike the conventional divider, the injec- tion current in this distributed divider is frequency dependent. Figure 3.8 shows the to- tal short-circuit equivalent injection current of a 10-element distributed injection-locked frequency divider as a function of frequency, below its first series mode resonance. The effective injection in the distributed scheme is weaker than that of the conventional fre- quency divider at frequencies below the first parallel resonance frequency and higher above that. Notice that the above analysis will result in infinitely large injection at the series modes. Even after considering the finite quality factor of the network, the effective injection strength peaks at series modes and reduces to the same value in the parallel 92 Figure 3.8: Analytical and simulated equivalent injection currents of a 10-element dis- tributed and a conventional injection-locked frequency dividers (L 1 = 1 nH,C 1 = 625 fF,R 1 = 18 ,C eq = 5:5C 1 ). modes. It is also noteworthy that the increase in injection strength kicks in before reach- ing the 3dB bandwidth of the series mode. Because of this property of injection strength in the distributed injection-locked fre- quency divider, both gain and phase conditions can be satisfied for all parallel and se- ries mode resonance frequencies. If designed properly, the frequency divider can operate over multiples of the first resonance frequency. To our best knowledge, this is a property that has not been shown in any other injection-locked frequency divider. To illustrate this, consider three schematics shown in Fig. 3.9. Figures 3.9.a and 3.9.c correspond to a conventional and a distributed injection-locked frequency dividers. Figure 3.9.b shows an alternate injection-locked frequency divider that has anLC-ladder distributed load, but only one injection device across the active core (similar to the conventional scheme). The LC-ladders in both Fig. 3.9.b and 3.9.c have all the parallel and series mode resonances. However, the equivalent injection current in the divider of Fig. 3.9.b is frequency inde- pendent and equal to that of the conventional design. Figure 3.9.d shows the simulated 93 Figure 3.9: (a) Conventional injection locked frequency divider with LC load, (b) Injection-locked frequency divider with a distributed load, (c) Distributed injection- locked frequency divider, (d) Simulated sensitivity curves for the injection-locked fre- quency dividers of (a), (b), and (c) where theLC-ladders consist of 10 sections, (e) Sim- ulated differential peak to peak swing across the cross-coupled pair in the 10-element distributed injection-locked frequency of (c) whenV inj = 450mV . 94 sensitivity curves of these three schematics. The distributed load/single point injection frequency divider of Fig. 3.9.b can operate only around the parallel resonance frequen- cies and fails to divide at series resonance frequencies. In fact, in absence of injection, start-up condition is not satisfied at series mode resonances. This can be verified by comparing the negative conductance of the cross-coupled pair (30mA=V ) to the conductance of the injection device plus the distributed load ( 50mA=V ). As shown in Fig. 3.8, for 10-element distributed injection, the strength of injection is approximately 37 dB (effective gain of 70) higher in the first series resonance frequency compared with that of the first parallel resonance frequency. In Section 3.2, we showed that for a nor- mally ON injection device, injection helps the startup condition (eqn. (3.4)). Injection signal can satisfy the startup condition in spite of the low resistance of the load because of the large effective gain provided by the distributed network. Therefore, oscillation at half the injection frequency can be sustained at the series resonance frequency. The am- plitude is limited by the fact that as the swing increases, the effectiveR ON of the injection devices drop. As shown in Fig. 3.9.d, the distributed injection locked frequency divider can divide continuously across multiple parallel and series resonance frequencies. This is due to the natural injection equalization in this scheme: as the impedance of the load drops, the injection strength increases. Notice that as one moves from parallel resonance frequencies towards series resonance frequencies, the injection strength increases, which helps satisfy the phase condition over a wider range (eqn. (3.3)). Figure 3.9.e shows the output swing of the 10-element distributed injection locked frequency divider versus 95 the injection frequency. Even though the self-oscillation condition is not satisfied at the series resonance modes, output amplitude at the first series resonance frequency is larger than half that of the first parallel mode resonance frequency. It should be noted that from the presented first-order analysis, one might expect that the locking range of the distributed injection-locked frequency will be smaller below the first parallel resonance frequency because of weaker injection (Fig. 3.8), but simulations show very similar behavior at the lower frequency end. This may be due to the very small difference in the effective injection strength between the two cases (below the first parallel resonance). 3.4 Implementation of a mm-wave distributed injection locked frequency divider As shown in previous section, distributed injection locking technique can be used to im- prove the locking range beyond the conventional limits of injection-locked frequency dividers. A mm-wave implementation of the proposed scheme is discussed in this Sec- tion [86]. Figure 3.10 shows the micrograph of the chip. The chip has an area of 1 mm 0:9mm and is fabricated in the IBM 0.13m SiGe BiCMOS technology (8HP). The divider’s active area is 630m 90m as marked in Fig. 3.10. Figure 3.11 shows the complete schematics of the fabricated chip. The implementation is a 5-stage design where microstrip transmission lines are used to implement the inductors. Five microstrip 96 Figure 3.10: Micrograph of the mm-wave distributed injection-locked frequency divider. transmission lines are used for the input feed and coupled differential transmission lines are used for the core distributed resonator. The parasitics of the input Electro-Static Discharge (ESD) diode and the injection NMOS devices are incorporated into the input artificial transmission line network, preventing them from limiting the input matching bandwidth. Figure 3.12 shows the reflection coefficient measurement of the input net- work. An additional switched MIM capacitor is added across the cross-coupled pair to extend the division frequency to lower frequencies by reducing the self-oscillation frequency of the divider. Figure 3.13 shows the simulated impedance of the ladder network for both states of the switched capacitor. The buffer is an open-collector differential pair with resistive degeneration to reduce the capacitive loading of the buffer on the divider core. Figure ?? shows representative spectrum measurements of the output signal read directly from the Spectrum Analyzer when the MIM capacitor is not switched in. For nominal bias conditions (V G = 1:6V , V CC = 1:2V , I core = 4mA, I buf = 1:5mA), the self- oscillation frequency for the high and low bands are 25.9 and 21.3 GHz, respectively. 97 Figure 3.11: Schematics of the fabricated mm-wave distributed injection locked fre- quency divider with optimum bias conditions. Figure 3.12: Measured reflection coefficient of the implemented distributed injection- locked frequency divider. 98 In this implementation, the maximum oscillation frequency of the cross-coupled pair, consisting of two 4m emitter length transistors is 65 GHz. Because of this limitation, gain condition cannot be satisfied at higher-order resonance modes. However, the signif- icantly improved injection strength beyond the self-oscillation frequency of the divider results in a wide locking range. An alternative design could use a load with a smaller first parallel mode resonance frequency to cover a wider range (e.g., 10-60 GHz). The output power for nominal bias conditions is measured at -21 dBm single-ended (simulated -19 dBm), and is -25 dBm for the low-band. Figure 3.15 shows the measured phase noise of the input and divided output for a 48 GHz input signal with -10 dBm power. The phase noise at lower offsets follow the input phase noise with 6 dB difference (the stan- dard deviation from the ideal divided phase noise from 1 kHz to 1 MHz is 0.73 dB). The phase noise floor beyond 1 MHz varies as the bias current of the buffer (and hence output power) is changed, indicating that it is the combined phase noise floor of the buffer and the measurement instrument. 99 Figure 3.13: Simulation of impedance change due to switched capacitor close to the first parallel mode resonance frequency. Figure 3.15: Measured phase noise of input (48 GHz), and output signals of the imple- mented distributed injection-locked frequency divider. 100 Figure 3.16 shows the simulated and measured sensitivity curves for nominal design bias conditions (V G = 1:6 V , V CC = 1:2 V , I core = 4 mA, I buf = 1:5 mA). The spectrum beyond the sensitivity curve region shows characteristics of a pulled oscillator spectrum, indicating that locking is lost by not satisfying the phase condition. As expected from the previous analysis, the achieved locking range is varied as the bias conditions (e.g., gate-source voltage of injection devices, active core and buffer bias current) are changed. When changing the bias conditions, two separate regimes of operation are observed. Figure 3.17 shows sensitivity curves for I core = 5 mA and I buf = 0:9 mA. Since the effective transconductance of the cross-coupled pair guarantees start-up condition, the injection-locked frequency only shows frequency pulling outside the locking range. Be- low 2.8 mA, at the edge of the locking range, the output signal disappears, indicating that the gain condition is not satisfied due to injection devices loss. An example sensitivity curve is shown in Fig. 3.18 for I core = 2:5 mA and I buf = 0:6 mA. For V G = 1:54 V ,V CC = 1:1 V ,I core = 3:5 mA, andI buf = 0:9 mA, maximum locking range of 41- 59.5 GHz for the high band, and 35-44 GHz for the low band for 0 dBm input power are achieved. Table 3.1 shows the performance in comparison with selected published mm-wave frequency dividers. It should be noted that the injection devices in this design are 0.13 m CMOS transistors, and migrating to a lower CMOS node is expected to improve the locking range even further due to increase in injection strength (K 0 ) for the same parasitic capacitance. 101 Figure 3.16: Simulated and measured sensitivity curves for high and low bands for nom- inal bias conditions. Figure 3.17: Measured sensitivity curves for high DC current (phase condition limited). Table 3.1: Comparison with mm-wave frequency dividers 102 Figure 3.18: Measured sensitivity curves for low DC current (gain condition limited). 3.5 Conclusions In this Chapter, the concept of distributed injection-locked frequency division is intro- duced to increase the locking range beyond conventional limits of injection-locked fre- quency dividers that enable implementation of wideband mm-wave PLL for mm-wave software defined radios. It is analytically shown that continuous frequency division can be achieved over a frequency range that spans over multiples of the self-oscillation fre- quency of the core divider. As a proof-of-concept, a prototype was realized in a foundry 130 nm BiCMOS SiGe HBT technology, achieving a measured locking range of 35-44 GHz and 41-59.5 GHz while consuming 3.8 mW from a 1.15 V supply. 103 Chapter 4 Phase noise scaling in mm-wave oscillators In Chapter 1, a two-stage PLL architecture was introduced to enable high-throughput mm-wave SDRs. An important block in this scheme that determines the overall power consumption, tuning range, and phase noise is the mm-wave V oltage Controlled Oscil- lator (VCO) in the second-stage PLL (Fig. 1.10). A significant body of work has been published in the recent years in the area of mm-wave frequency generation using com- mercial silicon processes. Frequency synthesizers with output frequencies as high as 500 GHz have been reported [87][88]. Much work in this area has been focused on increas- ing the oscillation frequency while delivering moderate to high output powers [89][90]. mm-wave oscillators can be categorized into fundamental and superharmonic oscilla- tors (e.g. push-push [91], triple-push [92], self-mixing [93], etc.). Based on the results of [94], oscillator topologies can be investigated in terms of their maximum oscillation frequency and their DC-RF efficiency in mm-wave frequencies, which can help in the choice of frequency synthesizer and oscillator topology. For example, to design a fre- quency synthesizer with 300 GHz output frequency in a technology that has a transistor 104 maximum oscillation of 300 GHz, the third harmonic of an oscillator topology with an inherent high maximum oscillation frequency would result in reasonable output power and DC-RF efficiency. However, the choice of the oscillator topology and whether to use superharmonic oscillators can be harder to make especially when lowest phase noise for a given power consumption is the objective. Theoretical and experimental study of phase noise of mm-wave oscillators as the oscillation frequency approaches their maximum oscillation frequency can be very helpful in making such choices. Given a certain power budget, circuit techniques can improve the achievable phase noise [96][97][98]. However, each oscillator topology has a lower bound of achievable phase noise set by the quality factor of the passives and properties of the active device; this bound rapidly increases as the oscillation frequency gets close to the maximum oscilla- tion frequency of the chosen oscillator topology. Once an optimum design is achieved for a given topology and power consumption, the design may be scaled to reduce phase noise (1 dB phase noise reduction for 1 dB more power consumption). In mm-wave implementations however, passive component values of a scaled oscillator can quickly become impractical because of either the self-resonance frequency of large capacitors or inductor values that become close to interconnect parasitics. Phase noise may be im- proved by coupling oscillators without requiring to scale the passive values [99][100]. In this chapter, phase noise scaling in mm-wave frequencies will be analytically and exper- imentally treated for cross-coupled pair and Colpitts oscillators. In Section 4.1, analysis 105 and simulation results of phase noise scaling will be presented. In Section 4.2, measure- ment results of three scaled cross-coupled pair oscillators at 26, 38, and 67 GHz, and two differential Colpitts oscillators at 106 and 148 GHz will be discussed confirming the derived phase noise scaling in mm-wave frequencies. In Section 4.3, design and im- plementation of an 8-element common-mode-coupled 106 GHz oscillator is presented. Section 4.4 concludes this chapter. 4.1 Oscillator phase noise scaling In designing a mm-wave frequency synthesizer, the designer faces several system and circuit level choices that directly affect the overall performance of the frequency synthe- sizer. Some of the important design choices and related questions are as follows (1) For a given output frequency and power, is it more energy efficient to design a funda- mental oscillator or a superharmonic oscillator (e.g., push-push, edge-combining, etc.)? (2) What oscillator topology leads to the lowest phase noise for a given oscillation fre- quency and power consumption? (3) For a given phase noise requirement, is one oscillator sufficient, or an array of coupled oscillators need to be used? To answer these questions, the first step is to quantify how phase noise scales with power consumption and oscillation frequency, especially as the frequency approaches the max- imum oscillation frequency that a given topology and technology support. Analytical 106 treatment of phase noise scaling in mm-wave frequencies will be discussed in this sec- tion and will be verified by simulations. 4.1.1 Ideal phase noise scaling Under relatively general conditions, the following two statements are true for oscillator phase noise scaling (1) Power scaling: At a certain frequencyf 0 , the phase noise of an optimally designed oscillator can be reduced by 10log(N) dB by scaling transistors, current consumption, and passive elements admittances byN. (2) Frequency scaling: To scale an oscillator from frequencyf 0 , to frequencyMf 0 , for the same power consumption and scaled passives, the phase noise will scale linearly with frequency (i.e., increases by 20logM). The first scaling rule is true if the quality factor of passive components remain constant under scaling. Figure 4.1.a and 4.1.b illustrate the scaling rule (1) for a conventional cross-coupled pair LC oscillator as an example. Different arguments can be made on why this rule holds for oscillator phase noise. For example, from [101], the phase noise of the oscillator can be written as PN = 10log 2 rms I 2 n q 2 max 4! 2 ; (4.1) 107 Figure 4.1: (a) Schematic of a cross-coupled pair LC oscillator. (b) Schematic of a power scaled cross-coupled pair oscillator. (c) Cross-coupled oscillator phase noise as a function of power consumption; the unscaled design parameters are L P = 140pH, Q = 10,I BIAS = 4mA,L E = 2m,C P is the parasitic capacitor of the cross-coupled pair, and the oscillation frequency is 73 GHz which is very close to the topologyf max = 79GHz. (d) Inductor value versus the achieved phase noise. 108 where rms is the rms value of the impulse sensitivity function, I 2 n is the white noise power spectral density, q max is the total charge on the capacitor, and ! is the offset frequency. Under the scaling rule, the voltage waveforms remain unchanged and the currents will be N times larger and therefore ( rms ) scaled = rms (4.2) ( I 2 n ) scaled =N I 2 n (4.3) (q 2 max ) scaled =N 2 q 2 max ; (4.4) which leads to PN scaled = PN 10log(N). Figure 4.1.c shows the simulated phase noise of a 73 GHz cross-coupled pair oscillator as a function of DC power consumption (P DC = V CC NI BIAS ). The technology used in all simulations is the Global Foundries 130 nm SiGe HBT BiCMOS technology (8HP) to reflect the integrated implementations discussed in the next section. While this scaling condition is frequency independent, the size of the passive components can become impractical for largeN. As shown in Fig. 4.1.d, to get to phase noise of -85 dBc/Hz at 1 MHz offset frequency away from a 73 GHz carrier, the inductor value should be chosen as 1 pH which is not practical. This practical limitation poses a challenge in achieving low phase noise at mm-wave frequencies. To overcome this limitation, one solution is coupling multiple oscillators. As conceptually 109 Figure 4.2: Power scaling in a single oscillator compared to an array of coupled oscil- lators. Both schemes will consume N times the original power, leading to 10log(N) improvement in phase noise. shown in Fig. 4.2, couplingN oscillators will ideally result in phase noise improvement of 10log(N) which is the same as scaling the core oscillator by a factor onN. The frequency scaling rule is true if the quality factor of passive components remain con- stant under scaling and transistor parasitics are neglected, (i.e., the transistor is modeled as a memory-less nonlinearity). Figure 4.3.a and 4.3.b illustrate the frequency scaling rule for a Colpitts oscillator as an example. Similar to the arguments for power scaling, here ( rms ) scaled = rms , ( I 2 n ) scaled = I 2 n and (q 2 max ) scaled = 1 M 2 q 2 max , which results in (f 0 ) scaled =Mf 0 andPN scaled =PN + 20log(M). Figure 4.3.c shows the phase noise scaling for a Colpitts oscillator as a function of oscillation frequency. Unlike the power scaling rule, frequency scaling is strongly dependent on transistor parasitics. The phase noise of an optimally designed oscillator sharply deviates from this linear with frequency behavior as the oscillation frequency approaches the maximum oscillation frequency of 110 Figure 4.3: (a) Schematic of a Colpitts oscillator. (b) Schematic of a frequency-scaled Colpitts oscillator. (c) Phase noise of a frequency-scaled Colpitts oscillator versus fre- quency. In simulations,Q = 10,L E = 5m, andP DC = 1mW . the chosen topology. Therefore, frequency scaling of mm-wave oscillators need to be investigated in more detail. 4.1.2 Phase noise of frequency-scaled mm-wave oscillators Consider the Colpitts oscillator schematic shown in Fig. 4.4.a and its simplified equiv- alent model in Fig. 4.4.b where major transistor parasitics are included and f(V ) = I s e V=MV T , whereM 1:4. The maximum oscillation frequency of the device, as de- fined by the Mason invariance function [94], can be written as 111 Figure 4.4: (a) Schematic of a mm-wave Colpitts oscillator. (b) Simplified equivalent model of a mm-wave Colpitts oscillator using a simplified high-frequency large signal transistor model. f max = 1 4 r g m (C +C )C R B ; (4.5) whereg m is the small-signal transconductance of the device. In our 130 nm SiGe HBT technology, from simulations, for a transistor with emitter length L E = 8m, f max is maximized for I BIAS = 7mA. For this DC current, R B = 19 , C = 101fF , C = 9fF ,g m = 200mA=V resulting inf max = 260GHz. Maximum oscillation frequency of the Colpitts oscillator shown in Fig. 4.4 can be found by finding theC 2 capacitance value which maximizes the frequency at which the real part of the impedance looking into the base of the transistor becomes zero. This procedure will lead to f max;colp = f max q 1 +g m R b C C ; (4.6) 112 Figure 4.5: (a) Equivalent model of the Colpitts oscillator in regime 1. Simulated and an- alytical (b) oscillation frequency as a function of inductor size, (c) oscillation amplitude as a function of inductor size, and (d) phase noise as a function of oscillation frequency. In transistor-level simulations,L E = 8m,I BIAS = 7mA, andV CC = 1:5V leading to C = 103fF ,C = 9fF ,g m = 200mA=V ,R B = 19 , andQ = 20. which happens when C 2 = C (1 + 2g m R b C C ) = 15fF and f max;colp = 224GHz. Circuit level simulation showsf max;colp = 222GHz. Figure 4.5.a shows the equivalent circuit for the simplified schematic of Fig. 4.4.b where L,R B , andC are lumped into an equivalent series RL circuit at the frequency of interest, i.e., oscillation frequency given by f 0 = 1 2 p L(C kC 2 +C ) : (4.7) 113 The actual maximum frequency that this circuit can oscillate will be slightly lower than f max;colp due to the limited quality factor of the inductor. Given a transistor geometry and bias current, f max;colp will be fixed, and can be achieved with a specific inductor valueL. The value of inductor can be increased to reduce the frequency of oscillation to another value. Alternatively, more capacitance may be added (e.g., in parallel withC or C 2 ) to reduce the oscillation frequency for the same bias current. Assuming a constant quality factor, the oscillation amplitude changes as a function of inductor value before getting limited by the DC voltage supply. For reasons that will become clear shortly, in the first regime of frequency scaling (referred to as regime 1 in this paper), it is optimum to only scale the inductor, keeping everything else constant, until the desired oscillation amplitude is reached (verge of voltage limited region as defined in [95]). Figure 4.5.b shows the oscillation frequency as a function of inductor value. Amplitude of oscillation and phase noise of the simplified circuit shown in Fig. 4.5.a can be derived analytically using quasi-periodic assumptions and averaging technique as shown in Section 2.1.3 of this thesis. The peak-to-peak voltage swing across capacitorC 2 is given by a pp = 4I BIAS L K(R B +R L )C 2 (1 +) I 1 ( app 2MV T ) I 0 ( app 2MV T ) ; (4.8) where K = CkC 2 +C CkC 2 2(1 +g m R B C C ), = C 2 C , and I 1 (:) and I 0 (:) are modified Bessel functions. In this regime, increasing the inductor value will sharply increase the oscillation amplitude. Figure. 4.5.c shows the circuit level simulation and analytical result of the peak-to-peak voltage swing across C 2 (a pp ) when Q L = 20. The sharp 114 increase in the oscillation amplitude as a function of inductor value is the reason why in this regime, it is optimum to only scale the inductor value. Phase noise of the Colpitts oscillator due to the collector shot noise can be derived as shown in Section 2.1.3 in Chapter 2 of this thesis. Phase noise of the oscillator shown in Fig. 4.5 can be derived by solving the oscillator nonlinear dynamical equations us- ing quasi-harmonic approximations for state variables (voltages across capacitors and currents of inductors) and averaging. The dynamical equations of this oscillator can be written as V = I L C ; (4.9) V 2 = f(V ) +I L I BIAS +I n (t) C 2 ; (4.10) I L = K 2 (R B +R L )I L +V 2 +V KL ; (4.11) whereI n (t) is the transistor collector shot noise. The approximate quasi-harmonic solu- tions for the state space variables may be expressed as V (t) =a pp (t)=2cos(! 0 t +(t)) +V ;dc +b (t); (4.12) V 2 (t) =a pp (t)=2cos(! 0 t +(t)) +V 2;dc b (t); (4.13) I(t) = (1 +) 2KL! 0 a pp (t)sin(! 0 t +(t)); (4.14) 115 where = C 2 C , V ;dc and V 2;dc are the DC voltages across C and C 2 in absence of oscillations. By substituting these approximate solutions into the dynamical equations and applying the averaging technique, the amplitude and phase differential equations can be derived as a pp (t) = (R B +R L )a pp (t) 2KL + 2I BIAS C 2 (1 +) I 1 (a pp =2MV T ) I 0 a pp =2MV T ; (4.15) (t) = 2I n (t) C 2 a pp (1 +) sin(! 0 t +(t)): (4.16) The steady state peak-to-peak oscillation amplitude can be found by the fixed point of amplitude differential equation leading to Eqn. (4.8). Phase noise can be found by solving the stochastic phase differential equation (4.16) using I n (t) = q 2qI BIAS e b +acos(! 0 t) =MV T ) W (t); (4.17) whereq is the charge of electron,a is the voltage swing acrossC ,b is the DC voltage change across the base-emitter under steady-state oscillations (b = 0 in absence of oscillation), and W(t) is the standard white Gaussian noise. Due to the periodic nature of the base-emitter swing, this noise is cyclostationary. Note thatb changes asa changes to keep the total DC current flowing through the transistor equal toI BIAS . Phase noise of the oscillator can be written as 116 The steady state value ofb (t) (b in (4.17)) can be found by equating the DC current of the transistor under large signal operation toI BIAS . The solution to the phase stochastic differential equation will lead to L(f) = 10log 2 rms qI BIAS C 2 2 (1 +) 2 a 2 pp ; (4.18) 2 rms = average e acos(T )=MV T (sin(T )) 2 average e acos(T )=MV T ; 11 (4.19) where theaverage(g(T )) operator finds the average of the functiong(T ) over 2. The denominator in Eqn. (4.19) is to accommodate for the DC voltage change b as the voltage swing changes. For regime 1, 2 rms varies from 0.5 to 0.2 as the voltage swing increases. To design the optimum oscillator at frequencies below regime 1, (referred to as regime 2), where the oscillation amplitude does not increase withL anymore, capacitorC 2 , device size emitter lengthL E , and base inductorL should be scaled following f 0;S = f 0 m ; (4.20) C 2;S =M C C 2 ; (4.21) L E;S =M T L E ; (4.22) L S =M L L; (4.23) 117 wheref 0;S is the scaled frequency of oscillation, f 0 is the lowest oscillation frequency in regime 1,C 2 andL are the values of emitter capacitor and inductor atf 0 , andL E is the emitter length chosen for regime 1 (L E = 8m for I BIAS = 7mA), and scaling factors M C , M T , and M L are constants that will be found later. To keep the quality factor of the inductor constant across frequency,R L;S = R L M L m . For the scaled device with emitter lengthL E;S ,C ;S =M T C ,R B;S = R B M T , andC ;S =g m f +M T C J , where g m f is the intrinsic base-emitter capacitor andC J is the base emitter junction capacitor. For the 8m device, g m f = 78fF and C J = 25fF . Similar to Fig. 4.5.a, in Fig. 4.6.a, the inducotorL S , resistorR B;S , and capacitorC ;S are lumped into inductorK S L and resistor (R B;S +R L;S )K 2 S whereK S = C ;S kC 2;S +C ;S C ;S kC 2;S . For an optimally designed oscillator at a scaled down frequency, the following conditions must satisfy M L C ;S kC 2;S +C ;S =m 2 C kC 2 +C (frequency condition); (4.24) a pp;S =a pp (amplitude condition); (4.25) minimize(PN m ); (4.26) wherea pp;S anda pp are the oscillation peak-to-peak swing across emitter capacitors at f 0;S and f 0 , and PN m is the phase noise at the scaled frequency f 0 m . In this regime, I 1 ( a pp;S 2MV T ) I 0 ( a pp;S 2MV T ) 1, and therefore, the amplitude of oscillation can be written as a pp;S 4I BIAS L S K S (R B;S +R L;S )C 2;S (1 + S ) ; (4.27) 118 where S = C 2;S C ;S . Since the amplitude of oscillation is kept constant, from Eqn. (4.18), the phase noise of the scaled oscillator can be written as PN m =PN 0 20log M C (1 + S ) ; (4.28) wherePN 0 is the phase noise at frequencyf 0 following Eqn. (4.19). Applying condi- tions (4.24) and (4.25) into the phase noise equation (4.28), the optimum scaling factors to minimize phase noise can be derived as M T = R B +R L R B;S +R L;S ( C+C 2 2C ) 2 m 2 1 + ( C+C 2 2C ) 2 1 + (m 1) C J C ; (4.29) M C = R B +R L R B;S +R L;S C +C 2 C 2 p M T M T C C 2 ; (4.30) M L = m 2 C kC 2 +C C ;S kC 2;S +C ;S : (4.31) Figure 4.6.b shows the logarithmic plot of the scaling factors as a function of oscillation frequency. Two distinct scaling regions can be observed in this plot. Above 100 GHz, the inductor value is relatively constant and frequency scaling is achieved by scaling the capacitor and device sizes. This is because in this frequency range, the effective qual- ity factor of the equivalent inductor is dominated by the scaled device base resistance R B;S = R B M T ; hence, according to (4.27), amplitude of oscillation can be kept constant for maximum capacitor scaling (a pp;S / L (M T C)(R=M T ) ). Maximum capacitor and device scal- ing while amplitude of oscillation is constant will in turn result in minimum phase noise. Below 100 GHz, the inductor base resistance starts to affect the amplitude of oscillation 119 Figure 4.6: (a) Equivalent model of the scaled Colpitts oscillator in regime 2. (b) Opti- mum device, capacitor and inductor scaling factors as a function of oscillation frequency. (c) Simulated normalized amplitude of oscillation as a function of oscillation frequency, and (d) Analytical and simulated phase noise of the oscillator across the entire frequency scaling range (regimes 1 and 2) and comparison with ideal phase noise scaling. 120 and inductive scaling is required to reach minimum phase noise. Figure 4.6.c shows the transistor-level simulated amplitude of oscillation normalized to amplitude of oscillation at f 0 (a pp ). Notice that the scaling criteria keeps the amplitude of oscillation close to constant over the entire frequency scaling range. Figure 4.6.d shows the scaled oscillator phase noise over regimes 1 and 2. Transistor-level simulation of phase noise follows the derived phase noise scaling (Eqn. (4.18) and (4.28)) over the entire frequency scaling range. At lower frequencies, the phase noise scaling reaches the ideal 20log(m) phase noise scaling as discussed in Section 4.1.1. An extremely sharp phase noise degradation close to the oscillator maximum oscillation frequency (regime 1). It is possible to find similar scaling criteria for other oscillator topologies. The two regimes of phase noise scaling can be observed for cross-coupled pair oscillators. Figure 4.7.a shows the simulated amplitude of oscillation for the oscillator shown in Fig. 4.1.a when inductive only scaling is applied (regime 1). For this topology, maximum oscilla- tion frequency is 78 GHz. Once the amplitude of oscillation is reached voltage limited region, both inductive and capacitive scaling is required to minimize phase noise. Figure 4.7.b shows the optimum phase noise as the oscillation frequency is scaled. 121 Figure 4.7: (a) Simulated amplitude of oscillation of the cross-coupled pair oscillator shown in Fig. 1.a in regime 1 (inductive only scaling), and (b) simulated phase noise of the cross-coupled pair oscillator across the entire frequency range (regimes 1 and 2). In these plots,I BIAS = 2:5mA,V CC = 1:5V ,L E = 2:5m, andQ = 10. 4.2 Implementation of mm-wave oscillators In this section, we demonstrate implementation and measurement results of various cross-coupled pair and Colpitts oscillators that are designed at different mm-wave fre- quencies following the aforementioned methodology. A 130 nm SiGe HBT BiCMOS process is used in all realizations. 4.2.1 mm-wave cross-coupled pair oscillators The schematic and chip photos of the mm-wave cross-coupled pair oscillators are shown in Fig. 4.8. Given that the maximum oscillation frequency that this topology can support in this technology is 78 GHz for cross-coupled pair topology, oscillators at 67 GHz, 39 GHz, and 26 GHz are implemented. The DC current in all oscillators is 2.5 mA. The resonant tanks are scaled appropriately to result in the lowest phase noise at each oscillator. In all three designs, the inductors are implemented as microstrip transmission 122 Figure 4.8: Schematics, chip photos, and measured phase noise of scaled cross-coupled pair oscillators at (a),(b),(c) 67 GHz, (d),(e),(f) 39 GHz, and (g),(h),(i) 26 GHz. lines with the signal routed on the 4m thick top metal layer and theM 5 ground at 9 m distance. The quality factors of these microstrip-based inductors at 67 GHz, 39 GHz, and 26 GHz are 17, 13, and 9.5, respectively. Figures 4.8.a and b show the schematic and chip photo of the 67 GHz cross-coupled pair oscillator. This oscillator is designed in the first regime of scaling (i.e., inductive only scaling), and therefore no explicit capacitor is used across the cross-coupled pair. An output buffer with small device size (L E = 1m) is used to enable measurements in a 123 50 environment without significant capacitive loading on the core oscillator. For the 67 GHz oscillator, a balun turns the differential output of the buffer into single-ended. In Fig. 4.8.c, the measured phase noise of this 67 GHz oscillator is -87 dBc/Hz at 1 MHz offset. In the two other oscillators at 39 and 26 GHz, explicit MIM capacitors are placed across the cross-coupled pair as part of their resonance tanks. The simulated quality factors of the 40 fF and 160 fF MIM capacitors at the 39 GHz and 26 GHz oscillation frequencies are 23 and 37, respectively. The design and phase noise measurement results of these two oscillators are shown in Fig. 4.8.d-i. Figure 4.9 shows the measured phase noise results at 1 MHz offset along with theoreti- cal cross-coupled oscillator phase noise scaling versus oscillation frequency. Notice the large deviation in phase noise of the scaled oscillators from that of the low frequency region (20 dB/dec) as the oscillation frequency approaches the maximum oscillation fre- quency of the cross-coupled pair oscillator topology. 4.2.2 mm-wave Colpitts oscillators The maximum oscillation frequency that Colpitts topology can sustain in this technology is around 220 GHz (ignoring layout parasitics). As such, to show the effect of transistor f max on phase noise in this topology, and validate the aforementioned design approach, two Colpitts oscillators at 106 and 148 GHz are implemented. Design details of the 106 GHz oscillator are discussed first. The 148 GHz oscillator is designed as the frequency- scaled version of the 106 GHz oscillator as shown later. Schematic and chip photo of the 124 Figure 4.9: Theoretical and experimental phase noiseof scaled oscillators at 1 MHz mm- wave cross-coupled pair oscillators at 1 MHz offset versus oscillation frequency. Mea- sured data points are indicated by solid circles. 106 GHz oscillator is shown in Fig. 4.10. The chip consumes 11 mW from a 1.6 V supply for the lowest phase noise setting. The output is drawn from the collectors of the core BJT transistors and connected to the 50 load through a balun. In the Colpitts topology, the core transistors need to see a low impedance in the collectors to result in a large maximum oscillation frequency. Therefore, an impedance transformation network consisting of C C and L C is inserted between the balun and the collectors of BJT transistors. The capacitive divider network of the core comprises of BJT device capacitorsC and metal- oxide-metal (MOM) capacitorsC E with floating bottom-plate (to reduce the common- mode effective capacitor). C E capacitors are implemented using third and fourth metal layers with 0:35m spacing in between; these capacitors and interconnect parasitics up to fifth metal layer are derived by RC-extraction. All inductors and transmission lines are implemented as microstrip transmission lines with the signal routed on the 4 125 m thick top metal layer and the M 5 ground at 9 m distance. The BJT transistors are biased using a current mirror connected to the common node of the base inductors and resistors R E . Use of resistors instead of current sources reduces the contribution of biasing circuitry in phase noise. ResistorR CM is used to de-Q the base inductors in common-mode. Quarter-wavelength (=4) transmission lines andC B are used between R E and core transistors emitters. Each C B is implemented as 4 MIM capacitors with floating bottom-plate. This enables implementation of a very large capacitor value of 260 fF with a self-resonance frequency of 170 GHz. In differential mode,C B capacitors provide a low-impedance path to virtual ground at mm-wave frequencies. Therefore, in this mode, R E is effectively shorted to ground and the impedance looking into the =4 line from the emitter side is high (Z big ). ThereforeR E does not load the oscillator core. In addition, =4 line acts as an additional high quality factor resonator in the oscillator, filtering the injected noise from active core transistors and reduce their effect on phase noise. Based on simulations, the use of the =4 resonator reduces the phase noise contribution of active core devices by 7 dB. In common-mode,C B capacitors are open-circuit. In this mode, the impedance looking into the=4 line from the emitter side is low preventing common-mode oscillations. Figure 4.11 shows the simulated small- signal impedance real part of the proposed Colpitts oscillator core under differential and common-mode excitations. For the common-mode excitation, the core is passive across frequency and unable to sustain oscillations. In differential mode, the core has negative input resistance in the 97-112 GHz frequency range; hence differential mode oscillation 126 Figure 4.10: Schematics and chip diagram of the 106 GHz Colpitts oscillator. in this frequency range is supported. The frequency range of 97-112 GHz is determined by the=4 line bandwidth. Measurement results of the implemented differential Colpitts oscillator are summarized in 4.12. Figure 4.13 shows the W-band oscillator measurement setup. For spectrum mea- surements, the harmonic mixer conversion-loss calibration data is loaded to the spectrum analyzer. Phase noise measurements are done using cross spectrum measurement tech- nique with a W-band power splitter preceded by two harmonic mixers and a signal source analyzer. The cross-spectrum measurement technique is used to reduce the measurement phase noise floor by 5logN where N is the number of averages in the cross-spectrum measurements). Figure 4.12.a shows the full W-band and zoomed-in measurement of 127 Figure 4.11: Proposed Colpitts oscillator core (a) Differential mode excitation, (b) common-mode excitation, and (c) small-signal simulation of the impedance real part with differential and common-mode excitations. the spectrum directly read from the spectrum analyzer. Figure 4.12.b shows the de- embedded output power and oscillation frequency as a function of bias current. The os- cillator has a measured maximum de-embedded output power of -6 dBm. Output power is within 3 dB of the peak output power across 105-108 GHz (frequency tuning mecha- nism is through changing the bias current and consequently changingC . The oscillator has a measured phase noise of -102 dBc/Hz at 1 MHz offset (Fig. 4.12.c) for a 106 GHz oscillation frequency. Figure 4.14 shows the schematic and chip photo of the scaled 148 GHz oscillator. The designs is similar to the design of the 106 GHz oscillator, but adapted to 148 GHz. Fig- ure 4.15 summarizes the measured results of the 148 GHz Colpitts oscillator. Figure 4.16 shows the measured results of the Colpitts oscillators together with the simulated phase 128 Figure 4.12: Measurement results of the 106 GHz Colpitts oscillator: (a) output spec- trum, (b) output power and oscillation frequency versus bias current, (c) phase noise profile at 106 GHz, (d) phase noise and output power versus oscillation frequency. 129 Figure 4.13: (a) Spectrum measurement setup in W-band. (b) phase noise measurement setup in W-band with cross-spectrum measurement capability. noise of the frequency-scaled Colpitts oscillator versus frequency. Similar to the cross- coupled pair oscillators, and as expected from analysis, phase noise degrades sharply as the oscillation frequency approaches the maximum oscillation frequency that the topol- ogy supports. 4.3 Coupled mm-wave oscillator arrays As discussed in Section 4.1.1, an optimally designed oscillator at a certain frequency and power consumption can be scaled asI BIAS;scaled = NI BIAS , (Devicesize) scaled = N(Devicesize),L scaled =L=N, andC scaled =NC, to reduce phase noise by 10log(N) 130 Figure 4.14: Schematic and chip photo of the frequency-scaled 148 GHz Colpitts oscil- lator. dB. In mm-wave implementations however, passive component values of a scaled oscil- lator can quickly become impractical because of either the self-resonance frequency of large capacitors or inductor values that become close to interconnect parasitics. Phase noise may be alternatively improved by N dB by coupling N of original oscillators. An ideal coupling scheme will not load the stand-alone oscillators while achieving the 10log(N) dB phase noise improvement. We propose a “common-mode coupling” scheme that enables reaching close to the theoretical limit phase noise improvement (10log(N) dB for N elements) in practice, demonstrating very low phase noise in mm-wave fre- quencies. To show the effectiveness of coupling in reducing phase noise of mm-wave oscillators, an 8-element common-mode-coupled Colpitts oscillator array is designed and implemented. 131 Figure 4.15: Measurement results of the 148 GHz oscillator: (a) output spectrum, (b) output power and oscillation frequency versus bias current, (c) phase noise profile at 148 GHz. 132 Figure 4.16: Comparison of measured differential Colpitts oscillators with simulated optimum scaled phase noise of this topology. Figure 4.17.a shows the concept of common-mode coupling employing the aforemen- tioned 106 GHz differential Colpitts oscillator. Adjacent Colpitts oscillators are coupled through large coupling capacitors tapped from the center of the base inductors. In gen- eral, in-phase coupled oscillators may operate in differential or common modes. For this scheme, in the differential mode, as shown in Fig. 4.17.b, the large coupling ca- pacitors essentially short the center tap of the base inductors to virtual ground, reducing the effective inductance seen by the core to L B =2. Therefore, to support differential- mode-coupled oscillations (not to be confused with the differential operation of a single Colpitts oscillator), the Colpitts oscillators would need to oscillate at p 2f 0 . As seen in Fig. 4.11, at this frequency, oscillations cannot be supported due to positive real part of the core impedance; hence, differential-mode-coupled oscillation is suppressed in the coupled oscillators. In the common-mode, the coupling network is open circuit and does not load the oscillators; therefore, each core will oscillate as it would standalone without 133 Figure 4.17: (a) Proposed coupling scheme. (b) Differential mode coupling (cannot be sustained). (c) Common-mode coupling. being affected by the coupling network. This property of the proposed coupling scheme leads to a couple of important advantages. First, since the coupling network does not load the core oscillators, the required phase noise and the size of passives are completely de-coupled and in principle, one can achieve very low phase noise numbers. Second, the scheme is insensitive to series interconnect parasitic inductors as long as the differential- mode-coupled oscillations cannot sustain (i.e., L par << L B =2). This means that the coupling scheme is robust to coupling mismatches, enabling the scheme to achieve close to theoretical limit improvement in phase noise due to coupling. The common-mode coupling concept is used to design and implement an 8-element cou- pled oscillator as shown in Fig. 4.18. The implemented chip (Fig. 4.20) occupies an area of 1.7 mm 1.4 mm and consumes 90 mW from a 1.6 V supply for the lowest phase noise setting. In a loop structure, each oscillator is coupled to its two neighbors using large floating-bottom-plate 260 fF capacitors. For the oscillators at the far left 134 and far right, longer interconnect lines are needed to couple the oscillators. 660 m lines are routed to connect these oscillators to the corresponding coupling capacitors. However, the coupling remains intact as the differential mode is suppressed and the se- ries inductances do not affect core oscillators in common-mode. The outputs of the 8 coupled oscillators are combined using a Wilkinson power combining tree with approxi- mately 1.3 dB insertion loss per stage. The combined output directly drives the output 50 . Figure 4.19 shows the measurement results. The coupled oscillator has a measured de-embedded maximum output power of -0.4 dBm. The coupled oscillator frequency ranges from 105-105.6 GHz before output power drops more than 3 dB. At 105.4 GHz, the oscillator shows a measured phase noise of -111 dBc/Hz at 1 MHz offset. In the phase noise measurement with no cross-correlation, the oscillator shows 20 dB/dec be- havior below 1 MHz and it somewhat deviates from this behavior at higher offsets before hitting the phase noise floor. Cross-correlation measurements with 10 times averaging shows the continuation of the 20 dB/dec behavior at higher offsets and proves the de- viation in the measurements without cross-correlation to be due to inherent noise of the measurement setup. It should be noted that unlike the results reported here, the phase noise profile of mm-wave silicon oscillators is rarely successfully measured over multi- ple decades of offset frequency. In addition to the capable signal source analyzer used here (Keysight E5052B+E5053A) with cross-spectrum capability, this is due to the large output power (enabling low phase noise floor) and low phase noise values (enabling mea- surements down to low offset frequencies). Table 4.1 shows the performance summary 135 of implemented Colpitts oscillators in comparison with selected published silicon mm- wave oscillators. An important achievement of this work is to show close to theoretical limit improvement in phase noise (9 dB) when relatively large number of oscillators (8 oscillators) are coupled. This is due to the robustness of the proposed coupling scheme to mismatch and preventing the coupling network from loading core oscillators. This has led to equal FOM of -192.6 dB for the one and 8-element coupled oscillators. 4.4 Frequency tuning in mm-wave frequencies The oscillators discussed in this chapter are either fixed-frequency or have limited tuning range. In the system proposed in Chapter 1, wide tuning range mm-wave voltage con- trolled oscillators are required. Varactors, switched capacitors, and switched inductors, are the typical choices in tuning the oscillation frequency. At mm-wave frequencies, the quality factor of the varactors reduce, resulting in phase noise degradation. Furthere- more, the R ON C OFF product of switches causes a tradeoff between tuning range and phase noise. As such, designing wide tuning range mm-wave VCOs with low phase noise is particularly challenging. One way to mitigate the challenges in frequency tuning at very high frequencies is to use superharmonic oscillators. This comes at the cost of frequency multiplier power consumption and area overhead. Another method is to distribute the varactors in the oscillator tank similar to that described in Chapter 3. Smaller varactors generally have 136 Figure 4.18: Schematic of the 8-element common-mode coupled oscillator. 137 Table 4.1: Performance summary and comparison with selsected silicon mm-wave oscil- lators higher quality factors, and as discussed in Chapter 3, it is possible to realize a resonator using smaller capacitors in a distibuted load. xConclusions Oscillator phase noise is significantly affected as the oscillation frequency approaches the maximum frequency that a given topology can support. A systematic ap- proach to designing mm-wave Colpitts and cross-coupled pair oscillators, while achiev- ing the lowest phase noise, is presented. Analytical results and design procedures are verified experimentally through several oscillator prototypes realized in a 130 nm SiGe HBT process. Coupling oscillators is an effective method to reduce phase noise. Concept of ”common- mode coupling” is introduced as an effective coupling scheme that leads to near ideal phase noise improvement due to coupling. A 106 GHz 8-element common-mode coupled Colpitts oscillator is presented with a measured phase noise of -111 dBc/Hz at 1 MHz offset while consuming 90 mW reaching an FOM of -192.6 dB. 138 Figure 4.19: Measurement results of the 8-element common-mode coupled oscillator: (a) output spectrum directly read from spectrum analyzer, (b) de-embedded output power and oscillation frequency versus bias current, (c) phase noise with 1 and 10 cross- correlations at 105.6 GHz. Figure 4.20: Chip microphotograph of the 8-element common-mode coupled oscillator. 139 Chapter 5 Conclusions 5.1 Summary This thesis provides a theoretical and experimental study of frequency generation in RF and mm-wave frequencies. Systems and circuits are proposed and implemented to ad- dress major challenges in designing low phase noise, widebad frequency synthesizers. The major contributions of this work may be summarized as follows: 1- A two-stage PLL architecture is proposed that enables 100 Gbps wireless communi- cations at mm-wave frequencies. 2- Theory of phase noise of self-sustained oscillators with nonlinear resonators is devel- oped. The theoretical results are used to implement FBAR/CMOS oscillators with less than 10 fs integrated jitter. 3- Phase noise reduction schemes are studied and compared with self-sustained oscil- lators. A feedback feedforward phase noise reduction scheme is proposed and imple- mented using a notch-based phase-frequency discriminator. 140 4- Concept of distributed injection-locked frequency dividers is proposed. It is analyti- cally shown that this scheme can break the locking range limit of conventional injection- locked frequency dividers. An integrated implementation of this scheme is shown to have a close to 1-octave locking range in mm-wave frequencies, enabling wideband frequency synthesis for mm-wave software defined radios. 5- Theory of phase noise scaling of mm-wave oscillators is introduced. Integrated im- plementation of mm-wave oscillators from 20 GHz to 150 GHz is used to verify the theory. 6- An efficient coupling scheme in mm-wave frequencies is introduced to reduce phase noise of mm-wave oscillators. An integrated implementation is presented achieving record -111 dBc/Hz phase noise at 1 MHz offset from a 106 GHz carrier. 5.2 Recommendations for future work The proposed schemes and the theoretical platforms open up a couple of interesting areas for future work: 1- Integrated implementation of the two-stage PLL architecture for low-phase noise wideband mm-wave frequency synthesis. 2- Employing the concept of distributed injection locking to implement multi-octave locking range frequency dividers. 3- Adapting the distributed injection-locking concept to implement wide tuning range mm-wave VCOs. 141 4- Using the knowledge on phase noise reduction schemes to develop digital processing techniques for reducing the effect of jitter in data conversion systems. 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It can be shown [5] that(t), when considering the standard diffusion term, is a Wiener process with parameter c = p D=2 a s C ; (A.2) where D is the variance of the white noise. Parameter c is also called the Lorentzian corner of the phase noise or the linewidth of the oscillator. In Chapter 2, the amplitude noise stochastic differential equation was derived as (Eqn. 2.17) da n (t) =a n (t)dt + p D C cos(! 0 t +(t))dB t ; (A.3) = K! 0 Q : (A.4) The solution to this linear stochastic differential equation may be written as [38] a n (t) =e (tt 0 ) (a n (t 0 ) + Z t t 0 p D C cos(! 0 s +(s)):e (st 0 ) dB s ): (A.5) To solve this equation, we will use the properties of Ito stochastic integrals. Consider the bounded, adapted stochastic processX(t). The following equations can be proved [38] E( Z T 0 (X(t)dB t )) = 0; (A.6) 153 E(( Z T 0 (X(t)dB t )) 2 ) =E( Z T 0 (X(t) 2 dt)); (A.7) E( Z T 0 (X(t)dB t ): Z T 2 T (X(t)dB t )) = 0; (A.8) wheredB t is the increment of a standard Wiener process (Brownian motion) andT 2 > T > 0. To find the power spectral density of the amplitude noise when the oscillator has reached its steady state, the amplitude noise autocorrelation function is found as time goes to infinity as > 0 lim t!+1 E(a n (t)a n (t +)) = D C 2 lim t!+1 e 2(tt 0 ) e [E(( Z t t 0 g(s)dB s ) 2 ) +E( Z t t 0 g(s)dB s Z t+ t g(s)dB s )] (A.9) g(t) = p D C :cos(! 0 t + t )e ((tt 0 )) (A.10) From (A.8), the second expectation in the right hand side of (A.10) is zero and from (A.7), the first expectation can be written as E(( Z t t 0 g(s)dB s ) 2 ) =E(( Z t t 0 g(s) 2 :ds)) =f(t;t 0 ); (A.11) f(t;t 0 ) = D 2C 2 (e 2(tt 0 ) 1) +e 2(st 0 ) E( Z t t 0 cos(2! 0 s+2(s))ds): (A.12) 154 φ(t)) t (ω a(t) x(t) s + = sin (t)) φ t (ω (t) a y(t) LP s LP + = sin 2 2 s NL s NL s ω Q ω s s Q ω s H(s) + + = Figure A.1: Bandpass filter used to model memory effect with an amplitude and phase modulated input Assuming the phase changes slowly (phase changes much less than 2 over one period) the second term on the right side of (A.12) may be neglected. The amplitude noise autocorrelation function and power spectral density can then be written as R an () = lim t!+1 E(a nt a n(t+) ) = D 4:C 2 : K! 0 Q e K! 0 Q jj ; (A.13) S an (!) = D 2C 2 1 ! 2 + ( K! 0 Q ) 2 : (A.14) A.2 Analysis of a band pass filter with an amplitude and phase modulated sinusoid input In this appendix, the output of filter with the impulse responseh(t) to a amplitude and phase modulated sinusoid is calculated (Fig. A.1). The differential equation of this system can be written as ! s Q NL dx dt = d 2 y dt 2 + ! s Q NL dy dt +! 2 s y: (A.15) 155 The equivalent dynamical equations of this system can be written as dy dt =y 1 ; (A.16) dy 1 dt = ! s Q NL dx dt ! s Q NL :y 1 ! 2 s y: (A.17) assuming the input signal is an amplitude and phase modulated waveform, the input and output waveforms may be written as x(t) =a(t):sin(! s t +(t)); (A.18) y(t) =a LP (t):sin(! s t + LP (t)); (A.19) y 1 (t) =a LP (t):cos(! s t + LP (t)): (A.20) By plugging these approximations into the dynamical equations (78)-(79) and applying averaging, the amplitude and phase differential equations can be derived as _ a LP (t)= ! s 2Q NL a LP (t) + ! 0 2Q NL a(t)cos((t) LP (t)) (A.21) _ LP (t) = a a LP ! s 2Q NL sin((t) LP (t)): (A.22) Assumingj(t) LP (t)j<< 1, both amplitude and phase differential equations will reduce to the differential equation of a first order low pass filter with a pole at !s 2Q NL . Since the frequencies over which the oscillator phase noise is significant is typically much smaller than !s Q NL , this assumption is valid. 156 Appendix B The integrated circuits presented in this thesis are fabricated in two technologies: 1- IBM (Global Foundries) 130 nm CMOS technology (8RF). 2- IBM (Global Foundries) 130 nm SiGe HBT BiCMOS technology (8HP). The CMOS transistors and the metal-stack used in these two technologies are very sim- ilar. Figure B.1 shows the cross-section of the metal stack option that is used in the fab- rications. The top three metal layers (MQ, LY , and AM) are used to implement low-loss passives and interconnects. The process offers Metal-Insulator-Metal (MIM) capacitors with high dielectric constant between layers QY and LY as shown in Fig. B.1. The 8HP technology offers high performance hetero-junction bipolar transistors (HBT). Figure B.2 depicts an example layout of an HBT transistor with emitter length of 3 m together with its simplified small-signal model and simulated maximum oscillation frequency. The HBT transistors show maximum oscillation frequency of around 260 GHz (248 GHz when layout parasitics are included). Both 8HP and 8RF technologies offer CMOS transistors with minimum gate length of 130 nm. Figure B.3 depicts an example layout of an NMOS minimum-length transistor 157 Figure B.1: Cross-section of the metal stack used in the integrated implementations with channel width of 2 m (two 1 m fingers) together with its simplified small-signal model and simulated maximum oscillation frequency. The NMOS transistors show max- imum oscillation frequency of around 178 GHz (175 GHz when layout parasitics are included). Thick metal layers are available in these technologies to enable on-chip implementation of low-loss passives. As an example, consider the microstrip transmission with the ge- ometry shown in Fig. B.4.a. Figure B.4.b shows the equivalent cascaded network used to model the transmission line. Figures B.4.c and B.4.c show the imaginary and real parts of the input admittance of this transmission line when the output port is shorted to ground. When used as an inductor, this transmission line shows a maximum quality factor of 20. 158 Figure B.2: SiGe HBT bipolar transistor (a) layout with two collector connections, (b) simplified small signal model, (c) maximum oscillation frequency versus current density. The emitter length of the example device is 3 m. Figure B.3: 130 nm NMOS transistor (a) layout with two fingers, (b) simplified small signal model, (c) maximum oscillation frequency versus current density. For the example device, W/L=2 m/130 nm. 159 Figure B.4: Microstrip transmission line (a) geometry, (b) equivalent model, (c) imagi- nary part of input admittance, (d) real part of input admittance, (e) quality factor when used as an inductor. MIM capacitors offered in these technologies are frequently used in RF and mm-wave designs due to their high density. The quality factor and self-resonance-frequency (SRF) of these capacitors are strong functions of their layout. As an example, Fig. B.4.a shows the geometry of a differential MIM capacitor structure. On each side, four MIM capaci- tors, each with a nominal value of 66 fF, are connected, with their bottom-plates floating. Figure B.4.b shows the model of the differential capacitor. The capacitor shows an SRF of 171 GHz (B.4.c), and a maximum quality factor of 9 at 100 GHz. 160 Figure B.5: Differential MIM capacitor (a) four-finger geometry, (b) equivalent model, (c) imaginary part of input admittance, (d) real part of input admittance, (e) quality factor versus frequency. 161

Abstract (if available)

Abstract The exponential demand for higher data rates has resulted in aggressive use of communication resources in wireless radios. On one end, in Radio Frequency (RF) radios, this has led to using complex modulations (e.g., 1024-QAM in the upcoming 802.11AX WiFi aiming at 10 Gbps throughput) for spectral efficient communications. On another end, migration to mm-wave frequencies (e.g., fifth generation (5G) cellular in 28 GHz, 38 GHz, and beyond) is aiming to leverage the 100 GHz available bandwidth from 30-300 GHz. Both these trends result in challenges in design of wireless transceivers in RF and mm-waves. Specifically, frequency synthesizers used in transceivers for frequency translation and data conversion need to meet challenging specifications in terms of phase noise and tuning range. This thesis is dedicated to the study of architectures and circuit techniques to tackle these challenges in frequency generation systems for future radios. ❧ A two-stage Phase Locked Loop (PLL) architecture is proposed that enables mmwave wireless radios with 100 Gbps throughput. The architecture employs very low phase noise RF oscillators, low phase noise mm-wave coupled oscillators, and wide locking range frequency dividers. These low phase noise and/or wide frequency range blocks are proposed, designed, and implemented based on theoretical treatment of their performance limits. ❧ Theory of phase noise in RF self-sustained oscillators with nonlinear resonators is developed and used to design and implement RF oscillators with less than 10 fs integrated jitter. Phase noise reduction schemes are studied theoretically and through integrated implementations as an alternative to self-sustained oscillators. ❧ Theory of phase noise scaling of mm-wave oscillators is developed and experimentally verified by implementing mm-wave oscillators in the range of 20-150 GHz. Based on a proposed coupling scheme, a 106 GHz 8-element coupled oscillator is designed and implemented with record phase noise among Silicon mm-wave oscillators. ❧ Concept of distributed injection-locked frequency division is introduced as a method to expand the operation frequency of injection-locked frequency dividers beyond conventional limits. An integrated implementation of this concept reaches close to one octave locking range in mm-wave frequencies.

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University of Southern California Dissertations and Theses

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Asset Metadata

Creator Imani, Alireza (author)

Core Title Wideband low phase-noise RF and mm-wave frequency generation

School Viterbi School of Engineering

Degree Doctor of Philosophy

Degree Program Electrical Engineering

Publication Date 11/18/2016

Defense Date 10/19/2016

Publisher University of Southern California (original), University of Southern California. Libraries (digital)

Tag frequency generation,frequency synthesizer,integrated circuits,mm-wave,OAI-PMH Harvest,phase locked loops,phase noise,RF

Format application/pdf (imt)

Language English

Contributor Electronically uploaded by the author (provenance)

Advisor Hashemi, Hossein (committee chair), Chen, Mike Shuo-Wei (committee member), Moghaddam, Mahta (committee member), Prata, Aluizio (committee member), Ravichandran, Jayakanth (committee member)

Creator Email alireza1.imani@gmail.com,imani@usc.edu

Permanent Link (DOI) https://doi.org/10.25549/usctheses-c40-322843

Unique identifier UC11213645

Identifier etd-ImaniAlire-4938.pdf (filename),usctheses-c40-322843 (legacy record id)

Legacy Identifier etd-ImaniAlire-4938.pdf

Dmrecord 322843

Document Type Dissertation

Format application/pdf (imt)

Rights Imani, Alireza

Type texts

Source University of Southern California (contributing entity), University of Southern California Dissertations and Theses (collection)

Access Conditions The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the a...

Repository Name University of Southern California Digital Library

Repository Location USC Digital Library, University of Southern California, University Park Campus MC 2810, 3434 South Grand Avenue, 2nd Floor, Los Angeles, California 90089-2810, USA