Design of low-power and resource-efficient on-chip networks 

Performance improvement and power reduction techniques of on-chip networks 

Efficient techniques for sharing on-chip resources in CMPs 

Dynamically reconfigurable off- and on-chip networks 

Dynamic packet fragmentation for increased virtual channel utilization and fault tolerance in on-chip routers 

Hardware techniques for efficient communication in transactional systems 

Communication mechanisms for processing-in-memory systems 

Power efficient design of SRAM arrays and optimal design of signal and power distribution networks in VLSI circuits 

Lifetime reliability studies for microprocessor chip architecture 

Reconfiguration in sensor networks 

An FPGA-friendly, mixed-computation inference accelerator for deep neural networks 

Statistical modeling of sequence and gene expression data to infer gene regulatory networks 

Media access control for optical CDMA networks through interference avoidance 

Congestion control in multi-hop wireless networks 

Towards highly-available cloud and content-provider networks 

Robust routing and energy management in wireless sensor networks 

Optical signal processing for high-speed, reconfigurable fiber optic networks 

fame-012-sermon.pdf 

Techniques for increasing number of users in dynamically reconfigurable optical code division multiple access systems and networks 

Understanding and exploiting the acoustic propagation delay in underwater sensor networks 

Traffic pattern in negatively curved network 

Theoretical and computational foundations for cyber‐physical systems design 

Discrete-synapse recurrent neural network for nonlinear system modeling and seismic signal classification 

Optimizing power delivery networks in VLSI platforms 

Rate adaptation in networks of wireless sensors