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Combining compile -time and run -time parallelization
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Cost -sensitive cache replacement algorithms
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Compiler directed data management for configurable architectures with heterogeneous memory structures
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Parallel simulation of chip-multiprocessor
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Analysis of high-density oligonucleotide gene expression data for dissecting aging pathways
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Variation-aware circuit and chip level power optimization in digital VLSI systems
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Microsoft Word - $ASQ117808_supp_undefined_9EB8ACB8-12E4-11E1-A7BA-440BEF8616FA.docx
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Power efficient multimedia applications on embedded systems
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Thermal management in microprocessor chips and dynamic backlight control in liquid crystal diaplays
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Microsoft Word - LOVAAS-- Dissertation Manuscript--27 Sept 2016.docx
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Energy-efficient shutdown of circuit components and computing systems
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Energy efficient design and provisioning of hardware resources in modern computing systems
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Microsoft Word - $ASQ101738_supp_undefined_9EEDD572-A94A-11E0-81A6-334B9E1A67F9.docx
Deciphering natural language
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Globalization of a teacher education program at a comprehensive state university campus: a case study
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Multi-softcore architectures and algorithms for a class of sparse computations
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A study of academic success with students of color: what really matters? Lessons from high-performing, high-poverty urban schools
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Dynamically reconfigurable off- and on-chip networks
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Low power and reliability assessment techniques for advanced processor design