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Extending the design space for networks on chip
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A low-cost framework for processor functional verification
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Estimation of parameters and missing values under a regression model with non-randomly incomplete and non-normally distributed data
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A knowledge based system for designing testable VLSI circuits
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A planning model of the design process
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Transient fault recovery techniques for the VLSI processor arrays
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Incremental process planning as a support tool for economic product design
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Regression modeling of residential magnetic field exposure from wiring configurations
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Microsoft Word - $ASQ117920_supp_undefined_36A1D492-099D-11E1-858F-A02A9E1A67F9.docx
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An alternative capstone project: gap analysis of districtwide reform implementation of Focus on Results
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Spatial mapping of real-time quantitative shear stress with vascular oxidative stress
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Integrating land survey data into measurement-based GIS: an assessment of challenges and practical solutions for surveyors in Texas
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